ath9k: remove spurious check for channel on keycache reset
[linux-2.6.git] / drivers / net / wireless / ath / ath9k / hw.c
1 /*
2  * Copyright (c) 2008-2009 Atheros Communications Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16
17 #include <linux/io.h>
18 #include <asm/unaligned.h>
19
20 #include "ath9k.h"
21 #include "initvals.h"
22
23 static int btcoex_enable;
24 module_param(btcoex_enable, bool, 0);
25 MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
26
27 #define ATH9K_CLOCK_RATE_CCK            22
28 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
29 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
30
31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
32 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
33                               enum ath9k_ht_macmode macmode);
34 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
35                               struct ar5416_eeprom_def *pEepData,
36                               u32 reg, u32 value);
37 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
38 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
39
40 /********************/
41 /* Helper Functions */
42 /********************/
43
44 static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
45 {
46         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
47
48         if (!ah->curchan) /* should really check for CCK instead */
49                 return clks / ATH9K_CLOCK_RATE_CCK;
50         if (conf->channel->band == IEEE80211_BAND_2GHZ)
51                 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
52
53         return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
54 }
55
56 static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
57 {
58         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
59
60         if (conf_is_ht40(conf))
61                 return ath9k_hw_mac_usec(ah, clks) / 2;
62         else
63                 return ath9k_hw_mac_usec(ah, clks);
64 }
65
66 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
67 {
68         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
69
70         if (!ah->curchan) /* should really check for CCK instead */
71                 return usecs *ATH9K_CLOCK_RATE_CCK;
72         if (conf->channel->band == IEEE80211_BAND_2GHZ)
73                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
74         return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
75 }
76
77 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
78 {
79         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
80
81         if (conf_is_ht40(conf))
82                 return ath9k_hw_mac_clks(ah, usecs) * 2;
83         else
84                 return ath9k_hw_mac_clks(ah, usecs);
85 }
86
87 /*
88  * Read and write, they both share the same lock. We do this to serialize
89  * reads and writes on Atheros 802.11n PCI devices only. This is required
90  * as the FIFO on these devices can only accept sanely 2 requests. After
91  * that the device goes bananas. Serializing the reads/writes prevents this
92  * from happening.
93  */
94
95 void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val)
96 {
97         if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
98                 unsigned long flags;
99                 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
100                 iowrite32(val, ah->ah_sc->mem + reg_offset);
101                 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
102         } else
103                 iowrite32(val, ah->ah_sc->mem + reg_offset);
104 }
105
106 unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset)
107 {
108         u32 val;
109         if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
110                 unsigned long flags;
111                 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
112                 val = ioread32(ah->ah_sc->mem + reg_offset);
113                 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
114         } else
115                 val = ioread32(ah->ah_sc->mem + reg_offset);
116         return val;
117 }
118
119 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
120 {
121         int i;
122
123         BUG_ON(timeout < AH_TIME_QUANTUM);
124
125         for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
126                 if ((REG_READ(ah, reg) & mask) == val)
127                         return true;
128
129                 udelay(AH_TIME_QUANTUM);
130         }
131
132         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
133                 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
134                 timeout, reg, REG_READ(ah, reg), mask, val);
135
136         return false;
137 }
138
139 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
140 {
141         u32 retval;
142         int i;
143
144         for (i = 0, retval = 0; i < n; i++) {
145                 retval = (retval << 1) | (val & 1);
146                 val >>= 1;
147         }
148         return retval;
149 }
150
151 bool ath9k_get_channel_edges(struct ath_hw *ah,
152                              u16 flags, u16 *low,
153                              u16 *high)
154 {
155         struct ath9k_hw_capabilities *pCap = &ah->caps;
156
157         if (flags & CHANNEL_5GHZ) {
158                 *low = pCap->low_5ghz_chan;
159                 *high = pCap->high_5ghz_chan;
160                 return true;
161         }
162         if ((flags & CHANNEL_2GHZ)) {
163                 *low = pCap->low_2ghz_chan;
164                 *high = pCap->high_2ghz_chan;
165                 return true;
166         }
167         return false;
168 }
169
170 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
171                            const struct ath_rate_table *rates,
172                            u32 frameLen, u16 rateix,
173                            bool shortPreamble)
174 {
175         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
176         u32 kbps;
177
178         kbps = rates->info[rateix].ratekbps;
179
180         if (kbps == 0)
181                 return 0;
182
183         switch (rates->info[rateix].phy) {
184         case WLAN_RC_PHY_CCK:
185                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
186                 if (shortPreamble && rates->info[rateix].short_preamble)
187                         phyTime >>= 1;
188                 numBits = frameLen << 3;
189                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
190                 break;
191         case WLAN_RC_PHY_OFDM:
192                 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
193                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
194                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
195                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
196                         txTime = OFDM_SIFS_TIME_QUARTER
197                                 + OFDM_PREAMBLE_TIME_QUARTER
198                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
199                 } else if (ah->curchan &&
200                            IS_CHAN_HALF_RATE(ah->curchan)) {
201                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
202                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
203                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
204                         txTime = OFDM_SIFS_TIME_HALF +
205                                 OFDM_PREAMBLE_TIME_HALF
206                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
207                 } else {
208                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
209                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
210                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
211                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
212                                 + (numSymbols * OFDM_SYMBOL_TIME);
213                 }
214                 break;
215         default:
216                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
217                         "Unknown phy %u (rate ix %u)\n",
218                         rates->info[rateix].phy, rateix);
219                 txTime = 0;
220                 break;
221         }
222
223         return txTime;
224 }
225
226 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
227                                   struct ath9k_channel *chan,
228                                   struct chan_centers *centers)
229 {
230         int8_t extoff;
231
232         if (!IS_CHAN_HT40(chan)) {
233                 centers->ctl_center = centers->ext_center =
234                         centers->synth_center = chan->channel;
235                 return;
236         }
237
238         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
239             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
240                 centers->synth_center =
241                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
242                 extoff = 1;
243         } else {
244                 centers->synth_center =
245                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
246                 extoff = -1;
247         }
248
249         centers->ctl_center =
250                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
251         centers->ext_center =
252                 centers->synth_center + (extoff *
253                          ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
254                           HT40_CHANNEL_CENTER_SHIFT : 15));
255 }
256
257 /******************/
258 /* Chip Revisions */
259 /******************/
260
261 static void ath9k_hw_read_revisions(struct ath_hw *ah)
262 {
263         u32 val;
264
265         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
266
267         if (val == 0xFF) {
268                 val = REG_READ(ah, AR_SREV);
269                 ah->hw_version.macVersion =
270                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
271                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
272                 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
273         } else {
274                 if (!AR_SREV_9100(ah))
275                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
276
277                 ah->hw_version.macRev = val & AR_SREV_REVISION;
278
279                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
280                         ah->is_pciexpress = true;
281         }
282 }
283
284 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
285 {
286         u32 val;
287         int i;
288
289         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
290
291         for (i = 0; i < 8; i++)
292                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
293         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
294         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
295
296         return ath9k_hw_reverse_bits(val, 8);
297 }
298
299 /************************************/
300 /* HW Attach, Detach, Init Routines */
301 /************************************/
302
303 static void ath9k_hw_disablepcie(struct ath_hw *ah)
304 {
305         if (AR_SREV_9100(ah))
306                 return;
307
308         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
309         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
310         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
311         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
312         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
313         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
314         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
315         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
316         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
317
318         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
319 }
320
321 static bool ath9k_hw_chip_test(struct ath_hw *ah)
322 {
323         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
324         u32 regHold[2];
325         u32 patternData[4] = { 0x55555555,
326                                0xaaaaaaaa,
327                                0x66666666,
328                                0x99999999 };
329         int i, j;
330
331         for (i = 0; i < 2; i++) {
332                 u32 addr = regAddr[i];
333                 u32 wrData, rdData;
334
335                 regHold[i] = REG_READ(ah, addr);
336                 for (j = 0; j < 0x100; j++) {
337                         wrData = (j << 16) | j;
338                         REG_WRITE(ah, addr, wrData);
339                         rdData = REG_READ(ah, addr);
340                         if (rdData != wrData) {
341                                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
342                                         "address test failed "
343                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
344                                         addr, wrData, rdData);
345                                 return false;
346                         }
347                 }
348                 for (j = 0; j < 4; j++) {
349                         wrData = patternData[j];
350                         REG_WRITE(ah, addr, wrData);
351                         rdData = REG_READ(ah, addr);
352                         if (wrData != rdData) {
353                                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
354                                         "address test failed "
355                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
356                                         addr, wrData, rdData);
357                                 return false;
358                         }
359                 }
360                 REG_WRITE(ah, regAddr[i], regHold[i]);
361         }
362         udelay(100);
363
364         return true;
365 }
366
367 static const char *ath9k_hw_devname(u16 devid)
368 {
369         switch (devid) {
370         case AR5416_DEVID_PCI:
371                 return "Atheros 5416";
372         case AR5416_DEVID_PCIE:
373                 return "Atheros 5418";
374         case AR9160_DEVID_PCI:
375                 return "Atheros 9160";
376         case AR5416_AR9100_DEVID:
377                 return "Atheros 9100";
378         case AR9280_DEVID_PCI:
379         case AR9280_DEVID_PCIE:
380                 return "Atheros 9280";
381         case AR9285_DEVID_PCIE:
382                 return "Atheros 9285";
383         case AR5416_DEVID_AR9287_PCI:
384         case AR5416_DEVID_AR9287_PCIE:
385                 return "Atheros 9287";
386         }
387
388         return NULL;
389 }
390
391 static void ath9k_hw_init_config(struct ath_hw *ah)
392 {
393         int i;
394
395         ah->config.dma_beacon_response_time = 2;
396         ah->config.sw_beacon_response_time = 10;
397         ah->config.additional_swba_backoff = 0;
398         ah->config.ack_6mb = 0x0;
399         ah->config.cwm_ignore_extcca = 0;
400         ah->config.pcie_powersave_enable = 0;
401         ah->config.pcie_clock_req = 0;
402         ah->config.pcie_waen = 0;
403         ah->config.analog_shiftreg = 1;
404         ah->config.ht_enable = 1;
405         ah->config.ofdm_trig_low = 200;
406         ah->config.ofdm_trig_high = 500;
407         ah->config.cck_trig_high = 200;
408         ah->config.cck_trig_low = 100;
409         ah->config.enable_ani = 1;
410         ah->config.diversity_control = 0;
411         ah->config.antenna_switch_swap = 0;
412
413         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
414                 ah->config.spurchans[i][0] = AR_NO_SPUR;
415                 ah->config.spurchans[i][1] = AR_NO_SPUR;
416         }
417
418         ah->config.intr_mitigation = true;
419
420         /*
421          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
422          * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
423          * This means we use it for all AR5416 devices, and the few
424          * minor PCI AR9280 devices out there.
425          *
426          * Serialization is required because these devices do not handle
427          * well the case of two concurrent reads/writes due to the latency
428          * involved. During one read/write another read/write can be issued
429          * on another CPU while the previous read/write may still be working
430          * on our hardware, if we hit this case the hardware poops in a loop.
431          * We prevent this by serializing reads and writes.
432          *
433          * This issue is not present on PCI-Express devices or pre-AR5416
434          * devices (legacy, 802.11abg).
435          */
436         if (num_possible_cpus() > 1)
437                 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
438 }
439
440 static void ath9k_hw_init_defaults(struct ath_hw *ah)
441 {
442         ah->hw_version.magic = AR5416_MAGIC;
443         ah->regulatory.country_code = CTRY_DEFAULT;
444         ah->hw_version.subvendorid = 0;
445
446         ah->ah_flags = 0;
447         if (ah->hw_version.devid == AR5416_AR9100_DEVID)
448                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
449         if (!AR_SREV_9100(ah))
450                 ah->ah_flags = AH_USE_EEPROM;
451
452         ah->regulatory.power_limit = MAX_RATE_POWER;
453         ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX;
454         ah->atim_window = 0;
455         ah->diversity_control = ah->config.diversity_control;
456         ah->antenna_switch_swap =
457                 ah->config.antenna_switch_swap;
458         ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
459         ah->beacon_interval = 100;
460         ah->enable_32kHz_clock = DONT_USE_32KHZ;
461         ah->slottime = (u32) -1;
462         ah->acktimeout = (u32) -1;
463         ah->ctstimeout = (u32) -1;
464         ah->globaltxtimeout = (u32) -1;
465
466         ah->gbeacon_rate = 0;
467
468         ah->power_mode = ATH9K_PM_UNDEFINED;
469 }
470
471 static int ath9k_hw_rfattach(struct ath_hw *ah)
472 {
473         bool rfStatus = false;
474         int ecode = 0;
475
476         rfStatus = ath9k_hw_init_rf(ah, &ecode);
477         if (!rfStatus) {
478                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
479                         "RF setup failed, status: %u\n", ecode);
480                 return ecode;
481         }
482
483         return 0;
484 }
485
486 static int ath9k_hw_rf_claim(struct ath_hw *ah)
487 {
488         u32 val;
489
490         REG_WRITE(ah, AR_PHY(0), 0x00000007);
491
492         val = ath9k_hw_get_radiorev(ah);
493         switch (val & AR_RADIO_SREV_MAJOR) {
494         case 0:
495                 val = AR_RAD5133_SREV_MAJOR;
496                 break;
497         case AR_RAD5133_SREV_MAJOR:
498         case AR_RAD5122_SREV_MAJOR:
499         case AR_RAD2133_SREV_MAJOR:
500         case AR_RAD2122_SREV_MAJOR:
501                 break;
502         default:
503                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
504                         "Radio Chip Rev 0x%02X not supported\n",
505                         val & AR_RADIO_SREV_MAJOR);
506                 return -EOPNOTSUPP;
507         }
508
509         ah->hw_version.analog5GhzRev = val;
510
511         return 0;
512 }
513
514 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
515 {
516         u32 sum;
517         int i;
518         u16 eeval;
519
520         sum = 0;
521         for (i = 0; i < 3; i++) {
522                 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
523                 sum += eeval;
524                 ah->macaddr[2 * i] = eeval >> 8;
525                 ah->macaddr[2 * i + 1] = eeval & 0xff;
526         }
527         if (sum == 0 || sum == 0xffff * 3)
528                 return -EADDRNOTAVAIL;
529
530         return 0;
531 }
532
533 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
534 {
535         u32 rxgain_type;
536
537         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
538                 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
539
540                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
541                         INIT_INI_ARRAY(&ah->iniModesRxGain,
542                         ar9280Modes_backoff_13db_rxgain_9280_2,
543                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
544                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
545                         INIT_INI_ARRAY(&ah->iniModesRxGain,
546                         ar9280Modes_backoff_23db_rxgain_9280_2,
547                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
548                 else
549                         INIT_INI_ARRAY(&ah->iniModesRxGain,
550                         ar9280Modes_original_rxgain_9280_2,
551                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
552         } else {
553                 INIT_INI_ARRAY(&ah->iniModesRxGain,
554                         ar9280Modes_original_rxgain_9280_2,
555                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
556         }
557 }
558
559 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
560 {
561         u32 txgain_type;
562
563         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
564                 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
565
566                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
567                         INIT_INI_ARRAY(&ah->iniModesTxGain,
568                         ar9280Modes_high_power_tx_gain_9280_2,
569                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
570                 else
571                         INIT_INI_ARRAY(&ah->iniModesTxGain,
572                         ar9280Modes_original_tx_gain_9280_2,
573                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
574         } else {
575                 INIT_INI_ARRAY(&ah->iniModesTxGain,
576                 ar9280Modes_original_tx_gain_9280_2,
577                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
578         }
579 }
580
581 static int ath9k_hw_post_init(struct ath_hw *ah)
582 {
583         int ecode;
584
585         if (!ath9k_hw_chip_test(ah))
586                 return -ENODEV;
587
588         ecode = ath9k_hw_rf_claim(ah);
589         if (ecode != 0)
590                 return ecode;
591
592         ecode = ath9k_hw_eeprom_init(ah);
593         if (ecode != 0)
594                 return ecode;
595
596         DPRINTF(ah->ah_sc, ATH_DBG_CONFIG, "Eeprom VER: %d, REV: %d\n",
597                 ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah));
598
599         ecode = ath9k_hw_rfattach(ah);
600         if (ecode != 0)
601                 return ecode;
602
603         if (!AR_SREV_9100(ah)) {
604                 ath9k_hw_ani_setup(ah);
605                 ath9k_hw_ani_init(ah);
606         }
607
608         return 0;
609 }
610
611 static bool ath9k_hw_devid_supported(u16 devid)
612 {
613         switch (devid) {
614         case AR5416_DEVID_PCI:
615         case AR5416_DEVID_PCIE:
616         case AR5416_AR9100_DEVID:
617         case AR9160_DEVID_PCI:
618         case AR9280_DEVID_PCI:
619         case AR9280_DEVID_PCIE:
620         case AR9285_DEVID_PCIE:
621         case AR5416_DEVID_AR9287_PCI:
622         case AR5416_DEVID_AR9287_PCIE:
623                 return true;
624         default:
625                 break;
626         }
627         return false;
628 }
629
630 static bool ath9k_hw_macversion_supported(u32 macversion)
631 {
632         switch (macversion) {
633         case AR_SREV_VERSION_5416_PCI:
634         case AR_SREV_VERSION_5416_PCIE:
635         case AR_SREV_VERSION_9160:
636         case AR_SREV_VERSION_9100:
637         case AR_SREV_VERSION_9280:
638         case AR_SREV_VERSION_9285:
639         case AR_SREV_VERSION_9287:
640                 return true;
641         default:
642                 break;
643         }
644         return false;
645 }
646
647 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
648 {
649         if (AR_SREV_9160_10_OR_LATER(ah)) {
650                 if (AR_SREV_9280_10_OR_LATER(ah)) {
651                         ah->iq_caldata.calData = &iq_cal_single_sample;
652                         ah->adcgain_caldata.calData =
653                                 &adc_gain_cal_single_sample;
654                         ah->adcdc_caldata.calData =
655                                 &adc_dc_cal_single_sample;
656                         ah->adcdc_calinitdata.calData =
657                                 &adc_init_dc_cal;
658                 } else {
659                         ah->iq_caldata.calData = &iq_cal_multi_sample;
660                         ah->adcgain_caldata.calData =
661                                 &adc_gain_cal_multi_sample;
662                         ah->adcdc_caldata.calData =
663                                 &adc_dc_cal_multi_sample;
664                         ah->adcdc_calinitdata.calData =
665                                 &adc_init_dc_cal;
666                 }
667                 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
668         }
669 }
670
671 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
672 {
673         if (AR_SREV_9287_11_OR_LATER(ah)) {
674                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
675                                 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
676                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
677                                 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
678                 if (ah->config.pcie_clock_req)
679                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
680                         ar9287PciePhy_clkreq_off_L1_9287_1_1,
681                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
682                 else
683                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
684                         ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
685                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
686                                         2);
687         } else if (AR_SREV_9287_10_OR_LATER(ah)) {
688                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
689                                 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
690                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
691                                 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
692
693                 if (ah->config.pcie_clock_req)
694                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
695                         ar9287PciePhy_clkreq_off_L1_9287_1_0,
696                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
697                 else
698                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
699                         ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
700                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
701                                   2);
702         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
703
704
705                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
706                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
707                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
708                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
709
710                 if (ah->config.pcie_clock_req) {
711                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
712                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
713                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
714                 } else {
715                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
716                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
717                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
718                                   2);
719                 }
720         } else if (AR_SREV_9285_10_OR_LATER(ah)) {
721                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
722                                ARRAY_SIZE(ar9285Modes_9285), 6);
723                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
724                                ARRAY_SIZE(ar9285Common_9285), 2);
725
726                 if (ah->config.pcie_clock_req) {
727                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
728                         ar9285PciePhy_clkreq_off_L1_9285,
729                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
730                 } else {
731                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
732                         ar9285PciePhy_clkreq_always_on_L1_9285,
733                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
734                 }
735         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
736                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
737                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
738                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
739                                ARRAY_SIZE(ar9280Common_9280_2), 2);
740
741                 if (ah->config.pcie_clock_req) {
742                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
743                                ar9280PciePhy_clkreq_off_L1_9280,
744                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
745                 } else {
746                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
747                                ar9280PciePhy_clkreq_always_on_L1_9280,
748                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
749                 }
750                 INIT_INI_ARRAY(&ah->iniModesAdditional,
751                                ar9280Modes_fast_clock_9280_2,
752                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
753         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
754                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
755                                ARRAY_SIZE(ar9280Modes_9280), 6);
756                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
757                                ARRAY_SIZE(ar9280Common_9280), 2);
758         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
759                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
760                                ARRAY_SIZE(ar5416Modes_9160), 6);
761                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
762                                ARRAY_SIZE(ar5416Common_9160), 2);
763                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
764                                ARRAY_SIZE(ar5416Bank0_9160), 2);
765                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
766                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
767                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
768                                ARRAY_SIZE(ar5416Bank1_9160), 2);
769                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
770                                ARRAY_SIZE(ar5416Bank2_9160), 2);
771                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
772                                ARRAY_SIZE(ar5416Bank3_9160), 3);
773                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
774                                ARRAY_SIZE(ar5416Bank6_9160), 3);
775                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
776                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
777                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
778                                ARRAY_SIZE(ar5416Bank7_9160), 2);
779                 if (AR_SREV_9160_11(ah)) {
780                         INIT_INI_ARRAY(&ah->iniAddac,
781                                        ar5416Addac_91601_1,
782                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
783                 } else {
784                         INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
785                                        ARRAY_SIZE(ar5416Addac_9160), 2);
786                 }
787         } else if (AR_SREV_9100_OR_LATER(ah)) {
788                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
789                                ARRAY_SIZE(ar5416Modes_9100), 6);
790                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
791                                ARRAY_SIZE(ar5416Common_9100), 2);
792                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
793                                ARRAY_SIZE(ar5416Bank0_9100), 2);
794                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
795                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
796                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
797                                ARRAY_SIZE(ar5416Bank1_9100), 2);
798                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
799                                ARRAY_SIZE(ar5416Bank2_9100), 2);
800                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
801                                ARRAY_SIZE(ar5416Bank3_9100), 3);
802                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
803                                ARRAY_SIZE(ar5416Bank6_9100), 3);
804                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
805                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
806                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
807                                ARRAY_SIZE(ar5416Bank7_9100), 2);
808                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
809                                ARRAY_SIZE(ar5416Addac_9100), 2);
810         } else {
811                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
812                                ARRAY_SIZE(ar5416Modes), 6);
813                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
814                                ARRAY_SIZE(ar5416Common), 2);
815                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
816                                ARRAY_SIZE(ar5416Bank0), 2);
817                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
818                                ARRAY_SIZE(ar5416BB_RfGain), 3);
819                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
820                                ARRAY_SIZE(ar5416Bank1), 2);
821                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
822                                ARRAY_SIZE(ar5416Bank2), 2);
823                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
824                                ARRAY_SIZE(ar5416Bank3), 3);
825                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
826                                ARRAY_SIZE(ar5416Bank6), 3);
827                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
828                                ARRAY_SIZE(ar5416Bank6TPC), 3);
829                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
830                                ARRAY_SIZE(ar5416Bank7), 2);
831                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
832                                ARRAY_SIZE(ar5416Addac), 2);
833         }
834 }
835
836 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
837 {
838         if (AR_SREV_9287_11(ah))
839                 INIT_INI_ARRAY(&ah->iniModesRxGain,
840                 ar9287Modes_rx_gain_9287_1_1,
841                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
842         else if (AR_SREV_9287_10(ah))
843                 INIT_INI_ARRAY(&ah->iniModesRxGain,
844                 ar9287Modes_rx_gain_9287_1_0,
845                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
846         else if (AR_SREV_9280_20(ah))
847                 ath9k_hw_init_rxgain_ini(ah);
848
849         if (AR_SREV_9287_11(ah)) {
850                 INIT_INI_ARRAY(&ah->iniModesTxGain,
851                 ar9287Modes_tx_gain_9287_1_1,
852                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
853         } else if (AR_SREV_9287_10(ah)) {
854                 INIT_INI_ARRAY(&ah->iniModesTxGain,
855                 ar9287Modes_tx_gain_9287_1_0,
856                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
857         } else if (AR_SREV_9280_20(ah)) {
858                 ath9k_hw_init_txgain_ini(ah);
859         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
860                 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
861
862                 /* txgain table */
863                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
864                         INIT_INI_ARRAY(&ah->iniModesTxGain,
865                         ar9285Modes_high_power_tx_gain_9285_1_2,
866                         ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
867                 } else {
868                         INIT_INI_ARRAY(&ah->iniModesTxGain,
869                         ar9285Modes_original_tx_gain_9285_1_2,
870                         ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
871                 }
872
873         }
874 }
875
876 static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw *ah)
877 {
878         u32 i, j;
879
880         if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
881             test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
882
883                 /* EEPROM Fixup */
884                 for (i = 0; i < ah->iniModes.ia_rows; i++) {
885                         u32 reg = INI_RA(&ah->iniModes, i, 0);
886
887                         for (j = 1; j < ah->iniModes.ia_columns; j++) {
888                                 u32 val = INI_RA(&ah->iniModes, i, j);
889
890                                 INI_RA(&ah->iniModes, i, j) =
891                                         ath9k_hw_ini_fixup(ah,
892                                                            &ah->eeprom.def,
893                                                            reg, val);
894                         }
895                 }
896         }
897 }
898
899 int ath9k_hw_init(struct ath_hw *ah)
900 {
901         int r = 0;
902
903         if (!ath9k_hw_devid_supported(ah->hw_version.devid))
904                 return -EOPNOTSUPP;
905
906         ath9k_hw_init_defaults(ah);
907         ath9k_hw_init_config(ah);
908
909         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
910                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Couldn't reset chip\n");
911                 return -EIO;
912         }
913
914         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
915                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
916                 return -EIO;
917         }
918
919         if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
920                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
921                     (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
922                         ah->config.serialize_regmode =
923                                 SER_REG_MODE_ON;
924                 } else {
925                         ah->config.serialize_regmode =
926                                 SER_REG_MODE_OFF;
927                 }
928         }
929
930         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
931                 ah->config.serialize_regmode);
932
933         if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
934                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
935                         "Mac Chip Rev 0x%02x.%x is not supported by "
936                         "this driver\n", ah->hw_version.macVersion,
937                         ah->hw_version.macRev);
938                 return -EOPNOTSUPP;
939         }
940
941         if (AR_SREV_9100(ah)) {
942                 ah->iq_caldata.calData = &iq_cal_multi_sample;
943                 ah->supp_cals = IQ_MISMATCH_CAL;
944                 ah->is_pciexpress = false;
945         }
946         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
947
948         ath9k_hw_init_cal_settings(ah);
949
950         ah->ani_function = ATH9K_ANI_ALL;
951         if (AR_SREV_9280_10_OR_LATER(ah))
952                 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
953
954         ath9k_hw_init_mode_regs(ah);
955
956         if (ah->is_pciexpress)
957                 ath9k_hw_configpcipowersave(ah, 0);
958         else
959                 ath9k_hw_disablepcie(ah);
960
961         r = ath9k_hw_post_init(ah);
962         if (r)
963                 return r;
964
965         ath9k_hw_init_mode_gain_regs(ah);
966         ath9k_hw_fill_cap_info(ah);
967         ath9k_hw_init_11a_eeprom_fix(ah);
968
969         r = ath9k_hw_init_macaddr(ah);
970         if (r) {
971                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
972                         "Failed to initialize MAC address\n");
973                 return r;
974         }
975
976         if (AR_SREV_9285(ah))
977                 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
978         else
979                 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
980
981         ath9k_init_nfcal_hist_buffer(ah);
982
983         return 0;
984 }
985
986 static void ath9k_hw_init_bb(struct ath_hw *ah,
987                              struct ath9k_channel *chan)
988 {
989         u32 synthDelay;
990
991         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
992         if (IS_CHAN_B(chan))
993                 synthDelay = (4 * synthDelay) / 22;
994         else
995                 synthDelay /= 10;
996
997         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
998
999         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1000 }
1001
1002 static void ath9k_hw_init_qos(struct ath_hw *ah)
1003 {
1004         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
1005         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
1006
1007         REG_WRITE(ah, AR_QOS_NO_ACK,
1008                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
1009                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
1010                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
1011
1012         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
1013         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
1014         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
1015         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
1016         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
1017 }
1018
1019 static void ath9k_hw_init_pll(struct ath_hw *ah,
1020                               struct ath9k_channel *chan)
1021 {
1022         u32 pll;
1023
1024         if (AR_SREV_9100(ah)) {
1025                 if (chan && IS_CHAN_5GHZ(chan))
1026                         pll = 0x1450;
1027                 else
1028                         pll = 0x1458;
1029         } else {
1030                 if (AR_SREV_9280_10_OR_LATER(ah)) {
1031                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1032
1033                         if (chan && IS_CHAN_HALF_RATE(chan))
1034                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1035                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1036                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1037
1038                         if (chan && IS_CHAN_5GHZ(chan)) {
1039                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1040
1041
1042                                 if (AR_SREV_9280_20(ah)) {
1043                                         if (((chan->channel % 20) == 0)
1044                                             || ((chan->channel % 10) == 0))
1045                                                 pll = 0x2850;
1046                                         else
1047                                                 pll = 0x142c;
1048                                 }
1049                         } else {
1050                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1051                         }
1052
1053                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1054
1055                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1056
1057                         if (chan && IS_CHAN_HALF_RATE(chan))
1058                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1059                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1060                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1061
1062                         if (chan && IS_CHAN_5GHZ(chan))
1063                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1064                         else
1065                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1066                 } else {
1067                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1068
1069                         if (chan && IS_CHAN_HALF_RATE(chan))
1070                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1071                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1072                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1073
1074                         if (chan && IS_CHAN_5GHZ(chan))
1075                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
1076                         else
1077                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
1078                 }
1079         }
1080         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1081
1082         udelay(RTC_PLL_SETTLE_DELAY);
1083
1084         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1085 }
1086
1087 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1088 {
1089         int rx_chainmask, tx_chainmask;
1090
1091         rx_chainmask = ah->rxchainmask;
1092         tx_chainmask = ah->txchainmask;
1093
1094         switch (rx_chainmask) {
1095         case 0x5:
1096                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1097                             AR_PHY_SWAP_ALT_CHAIN);
1098         case 0x3:
1099                 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
1100                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1101                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1102                         break;
1103                 }
1104         case 0x1:
1105         case 0x2:
1106         case 0x7:
1107                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1108                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1109                 break;
1110         default:
1111                 break;
1112         }
1113
1114         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1115         if (tx_chainmask == 0x5) {
1116                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1117                             AR_PHY_SWAP_ALT_CHAIN);
1118         }
1119         if (AR_SREV_9100(ah))
1120                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1121                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1122 }
1123
1124 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1125                                           enum nl80211_iftype opmode)
1126 {
1127         ah->mask_reg = AR_IMR_TXERR |
1128                 AR_IMR_TXURN |
1129                 AR_IMR_RXERR |
1130                 AR_IMR_RXORN |
1131                 AR_IMR_BCNMISC;
1132
1133         if (ah->config.intr_mitigation)
1134                 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1135         else
1136                 ah->mask_reg |= AR_IMR_RXOK;
1137
1138         ah->mask_reg |= AR_IMR_TXOK;
1139
1140         if (opmode == NL80211_IFTYPE_AP)
1141                 ah->mask_reg |= AR_IMR_MIB;
1142
1143         REG_WRITE(ah, AR_IMR, ah->mask_reg);
1144         REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1145
1146         if (!AR_SREV_9100(ah)) {
1147                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1148                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1149                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1150         }
1151 }
1152
1153 static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1154 {
1155         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1156                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1157                 ah->acktimeout = (u32) -1;
1158                 return false;
1159         } else {
1160                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1161                               AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1162                 ah->acktimeout = us;
1163                 return true;
1164         }
1165 }
1166
1167 static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1168 {
1169         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1170                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1171                 ah->ctstimeout = (u32) -1;
1172                 return false;
1173         } else {
1174                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1175                               AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1176                 ah->ctstimeout = us;
1177                 return true;
1178         }
1179 }
1180
1181 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1182 {
1183         if (tu > 0xFFFF) {
1184                 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1185                         "bad global tx timeout %u\n", tu);
1186                 ah->globaltxtimeout = (u32) -1;
1187                 return false;
1188         } else {
1189                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1190                 ah->globaltxtimeout = tu;
1191                 return true;
1192         }
1193 }
1194
1195 static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1196 {
1197         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1198                 ah->misc_mode);
1199
1200         if (ah->misc_mode != 0)
1201                 REG_WRITE(ah, AR_PCU_MISC,
1202                           REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1203         if (ah->slottime != (u32) -1)
1204                 ath9k_hw_setslottime(ah, ah->slottime);
1205         if (ah->acktimeout != (u32) -1)
1206                 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1207         if (ah->ctstimeout != (u32) -1)
1208                 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1209         if (ah->globaltxtimeout != (u32) -1)
1210                 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1211 }
1212
1213 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1214 {
1215         return vendorid == ATHEROS_VENDOR_ID ?
1216                 ath9k_hw_devname(devid) : NULL;
1217 }
1218
1219 void ath9k_hw_detach(struct ath_hw *ah)
1220 {
1221         if (!AR_SREV_9100(ah))
1222                 ath9k_hw_ani_disable(ah);
1223
1224         ath9k_hw_rf_free(ah);
1225         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1226         kfree(ah);
1227         ah = NULL;
1228 }
1229
1230 /*******/
1231 /* INI */
1232 /*******/
1233
1234 static void ath9k_hw_override_ini(struct ath_hw *ah,
1235                                   struct ath9k_channel *chan)
1236 {
1237         /*
1238          * Set the RX_ABORT and RX_DIS and clear if off only after
1239          * RXE is set for MAC. This prevents frames with corrupted
1240          * descriptor status.
1241          */
1242         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1243
1244
1245         if (!AR_SREV_5416_20_OR_LATER(ah) ||
1246             AR_SREV_9280_10_OR_LATER(ah))
1247                 return;
1248
1249         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1250 }
1251
1252 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1253                               struct ar5416_eeprom_def *pEepData,
1254                               u32 reg, u32 value)
1255 {
1256         struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1257
1258         switch (ah->hw_version.devid) {
1259         case AR9280_DEVID_PCI:
1260                 if (reg == 0x7894) {
1261                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1262                                 "ini VAL: %x  EEPROM: %x\n", value,
1263                                 (pBase->version & 0xff));
1264
1265                         if ((pBase->version & 0xff) > 0x0a) {
1266                                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1267                                         "PWDCLKIND: %d\n",
1268                                         pBase->pwdclkind);
1269                                 value &= ~AR_AN_TOP2_PWDCLKIND;
1270                                 value |= AR_AN_TOP2_PWDCLKIND &
1271                                         (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1272                         } else {
1273                                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1274                                         "PWDCLKIND Earlier Rev\n");
1275                         }
1276
1277                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1278                                 "final ini VAL: %x\n", value);
1279                 }
1280                 break;
1281         }
1282
1283         return value;
1284 }
1285
1286 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1287                               struct ar5416_eeprom_def *pEepData,
1288                               u32 reg, u32 value)
1289 {
1290         if (ah->eep_map == EEP_MAP_4KBITS)
1291                 return value;
1292         else
1293                 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1294 }
1295
1296 static void ath9k_olc_init(struct ath_hw *ah)
1297 {
1298         u32 i;
1299
1300         for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1301                 ah->originalGain[i] =
1302                         MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1303                                         AR_PHY_TX_GAIN);
1304         ah->PDADCdelta = 0;
1305 }
1306
1307 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1308                               struct ath9k_channel *chan)
1309 {
1310         u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1311
1312         if (IS_CHAN_B(chan))
1313                 ctl |= CTL_11B;
1314         else if (IS_CHAN_G(chan))
1315                 ctl |= CTL_11G;
1316         else
1317                 ctl |= CTL_11A;
1318
1319         return ctl;
1320 }
1321
1322 static int ath9k_hw_process_ini(struct ath_hw *ah,
1323                                 struct ath9k_channel *chan,
1324                                 enum ath9k_ht_macmode macmode)
1325 {
1326         int i, regWrites = 0;
1327         struct ieee80211_channel *channel = chan->chan;
1328         u32 modesIndex, freqIndex;
1329
1330         switch (chan->chanmode) {
1331         case CHANNEL_A:
1332         case CHANNEL_A_HT20:
1333                 modesIndex = 1;
1334                 freqIndex = 1;
1335                 break;
1336         case CHANNEL_A_HT40PLUS:
1337         case CHANNEL_A_HT40MINUS:
1338                 modesIndex = 2;
1339                 freqIndex = 1;
1340                 break;
1341         case CHANNEL_G:
1342         case CHANNEL_G_HT20:
1343         case CHANNEL_B:
1344                 modesIndex = 4;
1345                 freqIndex = 2;
1346                 break;
1347         case CHANNEL_G_HT40PLUS:
1348         case CHANNEL_G_HT40MINUS:
1349                 modesIndex = 3;
1350                 freqIndex = 2;
1351                 break;
1352
1353         default:
1354                 return -EINVAL;
1355         }
1356
1357         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1358         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1359         ah->eep_ops->set_addac(ah, chan);
1360
1361         if (AR_SREV_5416_22_OR_LATER(ah)) {
1362                 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1363         } else {
1364                 struct ar5416IniArray temp;
1365                 u32 addacSize =
1366                         sizeof(u32) * ah->iniAddac.ia_rows *
1367                         ah->iniAddac.ia_columns;
1368
1369                 memcpy(ah->addac5416_21,
1370                        ah->iniAddac.ia_array, addacSize);
1371
1372                 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1373
1374                 temp.ia_array = ah->addac5416_21;
1375                 temp.ia_columns = ah->iniAddac.ia_columns;
1376                 temp.ia_rows = ah->iniAddac.ia_rows;
1377                 REG_WRITE_ARRAY(&temp, 1, regWrites);
1378         }
1379
1380         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1381
1382         for (i = 0; i < ah->iniModes.ia_rows; i++) {
1383                 u32 reg = INI_RA(&ah->iniModes, i, 0);
1384                 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1385
1386                 REG_WRITE(ah, reg, val);
1387
1388                 if (reg >= 0x7800 && reg < 0x78a0
1389                     && ah->config.analog_shiftreg) {
1390                         udelay(100);
1391                 }
1392
1393                 DO_DELAY(regWrites);
1394         }
1395
1396         if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1397                 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1398
1399         if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1400             AR_SREV_9287_10_OR_LATER(ah))
1401                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1402
1403         for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1404                 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1405                 u32 val = INI_RA(&ah->iniCommon, i, 1);
1406
1407                 REG_WRITE(ah, reg, val);
1408
1409                 if (reg >= 0x7800 && reg < 0x78a0
1410                     && ah->config.analog_shiftreg) {
1411                         udelay(100);
1412                 }
1413
1414                 DO_DELAY(regWrites);
1415         }
1416
1417         ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1418
1419         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1420                 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1421                                 regWrites);
1422         }
1423
1424         ath9k_hw_override_ini(ah, chan);
1425         ath9k_hw_set_regs(ah, chan, macmode);
1426         ath9k_hw_init_chain_masks(ah);
1427
1428         if (OLC_FOR_AR9280_20_LATER)
1429                 ath9k_olc_init(ah);
1430
1431         ah->eep_ops->set_txpower(ah, chan,
1432                                  ath9k_regd_get_ctl(&ah->regulatory, chan),
1433                                  channel->max_antenna_gain * 2,
1434                                  channel->max_power * 2,
1435                                  min((u32) MAX_RATE_POWER,
1436                                  (u32) ah->regulatory.power_limit));
1437
1438         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1439                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1440                         "ar5416SetRfRegs failed\n");
1441                 return -EIO;
1442         }
1443
1444         return 0;
1445 }
1446
1447 /****************************************/
1448 /* Reset and Channel Switching Routines */
1449 /****************************************/
1450
1451 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1452 {
1453         u32 rfMode = 0;
1454
1455         if (chan == NULL)
1456                 return;
1457
1458         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1459                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1460
1461         if (!AR_SREV_9280_10_OR_LATER(ah))
1462                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1463                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1464
1465         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1466                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1467
1468         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1469 }
1470
1471 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1472 {
1473         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1474 }
1475
1476 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1477 {
1478         u32 regval;
1479
1480         regval = REG_READ(ah, AR_AHB_MODE);
1481         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1482
1483         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1484         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1485
1486         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1487
1488         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1489         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1490
1491         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1492
1493         if (AR_SREV_9285(ah)) {
1494                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1495                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1496         } else {
1497                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1498                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1499         }
1500 }
1501
1502 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1503 {
1504         u32 val;
1505
1506         val = REG_READ(ah, AR_STA_ID1);
1507         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1508         switch (opmode) {
1509         case NL80211_IFTYPE_AP:
1510                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1511                           | AR_STA_ID1_KSRCH_MODE);
1512                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1513                 break;
1514         case NL80211_IFTYPE_ADHOC:
1515         case NL80211_IFTYPE_MESH_POINT:
1516                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1517                           | AR_STA_ID1_KSRCH_MODE);
1518                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1519                 break;
1520         case NL80211_IFTYPE_STATION:
1521         case NL80211_IFTYPE_MONITOR:
1522                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1523                 break;
1524         }
1525 }
1526
1527 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1528                                                  u32 coef_scaled,
1529                                                  u32 *coef_mantissa,
1530                                                  u32 *coef_exponent)
1531 {
1532         u32 coef_exp, coef_man;
1533
1534         for (coef_exp = 31; coef_exp > 0; coef_exp--)
1535                 if ((coef_scaled >> coef_exp) & 0x1)
1536                         break;
1537
1538         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1539
1540         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1541
1542         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1543         *coef_exponent = coef_exp - 16;
1544 }
1545
1546 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1547                                      struct ath9k_channel *chan)
1548 {
1549         u32 coef_scaled, ds_coef_exp, ds_coef_man;
1550         u32 clockMhzScaled = 0x64000000;
1551         struct chan_centers centers;
1552
1553         if (IS_CHAN_HALF_RATE(chan))
1554                 clockMhzScaled = clockMhzScaled >> 1;
1555         else if (IS_CHAN_QUARTER_RATE(chan))
1556                 clockMhzScaled = clockMhzScaled >> 2;
1557
1558         ath9k_hw_get_channel_centers(ah, chan, &centers);
1559         coef_scaled = clockMhzScaled / centers.synth_center;
1560
1561         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1562                                       &ds_coef_exp);
1563
1564         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1565                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1566         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1567                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1568
1569         coef_scaled = (9 * coef_scaled) / 10;
1570
1571         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1572                                       &ds_coef_exp);
1573
1574         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1575                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1576         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1577                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1578 }
1579
1580 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1581 {
1582         u32 rst_flags;
1583         u32 tmpReg;
1584
1585         if (AR_SREV_9100(ah)) {
1586                 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1587                 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1588                 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1589                 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1590                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1591         }
1592
1593         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1594                   AR_RTC_FORCE_WAKE_ON_INT);
1595
1596         if (AR_SREV_9100(ah)) {
1597                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1598                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1599         } else {
1600                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1601                 if (tmpReg &
1602                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1603                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1604                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1605                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1606                 } else {
1607                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1608                 }
1609
1610                 rst_flags = AR_RTC_RC_MAC_WARM;
1611                 if (type == ATH9K_RESET_COLD)
1612                         rst_flags |= AR_RTC_RC_MAC_COLD;
1613         }
1614
1615         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1616         udelay(50);
1617
1618         REG_WRITE(ah, AR_RTC_RC, 0);
1619         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1620                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1621                         "RTC stuck in MAC reset\n");
1622                 return false;
1623         }
1624
1625         if (!AR_SREV_9100(ah))
1626                 REG_WRITE(ah, AR_RC, 0);
1627
1628         ath9k_hw_init_pll(ah, NULL);
1629
1630         if (AR_SREV_9100(ah))
1631                 udelay(50);
1632
1633         return true;
1634 }
1635
1636 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1637 {
1638         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1639                   AR_RTC_FORCE_WAKE_ON_INT);
1640
1641         REG_WRITE(ah, AR_RTC_RESET, 0);
1642         udelay(2);
1643         REG_WRITE(ah, AR_RTC_RESET, 1);
1644
1645         if (!ath9k_hw_wait(ah,
1646                            AR_RTC_STATUS,
1647                            AR_RTC_STATUS_M,
1648                            AR_RTC_STATUS_ON,
1649                            AH_WAIT_TIMEOUT)) {
1650                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1651                 return false;
1652         }
1653
1654         ath9k_hw_read_revisions(ah);
1655
1656         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1657 }
1658
1659 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1660 {
1661         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1662                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1663
1664         switch (type) {
1665         case ATH9K_RESET_POWER_ON:
1666                 return ath9k_hw_set_reset_power_on(ah);
1667         case ATH9K_RESET_WARM:
1668         case ATH9K_RESET_COLD:
1669                 return ath9k_hw_set_reset(ah, type);
1670         default:
1671                 return false;
1672         }
1673 }
1674
1675 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
1676                               enum ath9k_ht_macmode macmode)
1677 {
1678         u32 phymode;
1679         u32 enableDacFifo = 0;
1680
1681         if (AR_SREV_9285_10_OR_LATER(ah))
1682                 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1683                                          AR_PHY_FC_ENABLE_DAC_FIFO);
1684
1685         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1686                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1687
1688         if (IS_CHAN_HT40(chan)) {
1689                 phymode |= AR_PHY_FC_DYN2040_EN;
1690
1691                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1692                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1693                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1694
1695                 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1696                         phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1697         }
1698         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1699
1700         ath9k_hw_set11nmac2040(ah, macmode);
1701
1702         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1703         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1704 }
1705
1706 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1707                                 struct ath9k_channel *chan)
1708 {
1709         if (OLC_FOR_AR9280_20_LATER) {
1710                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1711                         return false;
1712         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1713                 return false;
1714
1715         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1716                 return false;
1717
1718         ah->chip_fullsleep = false;
1719         ath9k_hw_init_pll(ah, chan);
1720         ath9k_hw_set_rfmode(ah, chan);
1721
1722         return true;
1723 }
1724
1725 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1726                                     struct ath9k_channel *chan,
1727                                     enum ath9k_ht_macmode macmode)
1728 {
1729         struct ieee80211_channel *channel = chan->chan;
1730         u32 synthDelay, qnum;
1731
1732         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1733                 if (ath9k_hw_numtxpending(ah, qnum)) {
1734                         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1735                                 "Transmit frames pending on queue %d\n", qnum);
1736                         return false;
1737                 }
1738         }
1739
1740         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1741         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1742                            AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1743                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1744                         "Could not kill baseband RX\n");
1745                 return false;
1746         }
1747
1748         ath9k_hw_set_regs(ah, chan, macmode);
1749
1750         if (AR_SREV_9280_10_OR_LATER(ah)) {
1751                 ath9k_hw_ar9280_set_channel(ah, chan);
1752         } else {
1753                 if (!(ath9k_hw_set_channel(ah, chan))) {
1754                         DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1755                                 "Failed to set channel\n");
1756                         return false;
1757                 }
1758         }
1759
1760         ah->eep_ops->set_txpower(ah, chan,
1761                              ath9k_regd_get_ctl(&ah->regulatory, chan),
1762                              channel->max_antenna_gain * 2,
1763                              channel->max_power * 2,
1764                              min((u32) MAX_RATE_POWER,
1765                              (u32) ah->regulatory.power_limit));
1766
1767         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1768         if (IS_CHAN_B(chan))
1769                 synthDelay = (4 * synthDelay) / 22;
1770         else
1771                 synthDelay /= 10;
1772
1773         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1774
1775         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1776
1777         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1778                 ath9k_hw_set_delta_slope(ah, chan);
1779
1780         if (AR_SREV_9280_10_OR_LATER(ah))
1781                 ath9k_hw_9280_spur_mitigate(ah, chan);
1782         else
1783                 ath9k_hw_spur_mitigate(ah, chan);
1784
1785         if (!chan->oneTimeCalsDone)
1786                 chan->oneTimeCalsDone = true;
1787
1788         return true;
1789 }
1790
1791 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1792 {
1793         int bb_spur = AR_NO_SPUR;
1794         int freq;
1795         int bin, cur_bin;
1796         int bb_spur_off, spur_subchannel_sd;
1797         int spur_freq_sd;
1798         int spur_delta_phase;
1799         int denominator;
1800         int upper, lower, cur_vit_mask;
1801         int tmp, newVal;
1802         int i;
1803         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1804                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1805         };
1806         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1807                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1808         };
1809         int inc[4] = { 0, 100, 0, 0 };
1810         struct chan_centers centers;
1811
1812         int8_t mask_m[123];
1813         int8_t mask_p[123];
1814         int8_t mask_amt;
1815         int tmp_mask;
1816         int cur_bb_spur;
1817         bool is2GHz = IS_CHAN_2GHZ(chan);
1818
1819         memset(&mask_m, 0, sizeof(int8_t) * 123);
1820         memset(&mask_p, 0, sizeof(int8_t) * 123);
1821
1822         ath9k_hw_get_channel_centers(ah, chan, &centers);
1823         freq = centers.synth_center;
1824
1825         ah->config.spurmode = SPUR_ENABLE_EEPROM;
1826         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1827                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1828
1829                 if (is2GHz)
1830                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1831                 else
1832                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1833
1834                 if (AR_NO_SPUR == cur_bb_spur)
1835                         break;
1836                 cur_bb_spur = cur_bb_spur - freq;
1837
1838                 if (IS_CHAN_HT40(chan)) {
1839                         if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1840                             (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1841                                 bb_spur = cur_bb_spur;
1842                                 break;
1843                         }
1844                 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1845                            (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1846                         bb_spur = cur_bb_spur;
1847                         break;
1848                 }
1849         }
1850
1851         if (AR_NO_SPUR == bb_spur) {
1852                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1853                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1854                 return;
1855         } else {
1856                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1857                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1858         }
1859
1860         bin = bb_spur * 320;
1861
1862         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1863
1864         newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1865                         AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1866                         AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1867                         AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1868         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1869
1870         newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1871                   AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1872                   AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1873                   AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1874                   SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1875         REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1876
1877         if (IS_CHAN_HT40(chan)) {
1878                 if (bb_spur < 0) {
1879                         spur_subchannel_sd = 1;
1880                         bb_spur_off = bb_spur + 10;
1881                 } else {
1882                         spur_subchannel_sd = 0;
1883                         bb_spur_off = bb_spur - 10;
1884                 }
1885         } else {
1886                 spur_subchannel_sd = 0;
1887                 bb_spur_off = bb_spur;
1888         }
1889
1890         if (IS_CHAN_HT40(chan))
1891                 spur_delta_phase =
1892                         ((bb_spur * 262144) /
1893                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1894         else
1895                 spur_delta_phase =
1896                         ((bb_spur * 524288) /
1897                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1898
1899         denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1900         spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1901
1902         newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1903                   SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1904                   SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1905         REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1906
1907         newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1908         REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1909
1910         cur_bin = -6000;
1911         upper = bin + 100;
1912         lower = bin - 100;
1913
1914         for (i = 0; i < 4; i++) {
1915                 int pilot_mask = 0;
1916                 int chan_mask = 0;
1917                 int bp = 0;
1918                 for (bp = 0; bp < 30; bp++) {
1919                         if ((cur_bin > lower) && (cur_bin < upper)) {
1920                                 pilot_mask = pilot_mask | 0x1 << bp;
1921                                 chan_mask = chan_mask | 0x1 << bp;
1922                         }
1923                         cur_bin += 100;
1924                 }
1925                 cur_bin += inc[i];
1926                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1927                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1928         }
1929
1930         cur_vit_mask = 6100;
1931         upper = bin + 120;
1932         lower = bin - 120;
1933
1934         for (i = 0; i < 123; i++) {
1935                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1936
1937                         /* workaround for gcc bug #37014 */
1938                         volatile int tmp_v = abs(cur_vit_mask - bin);
1939
1940                         if (tmp_v < 75)
1941                                 mask_amt = 1;
1942                         else
1943                                 mask_amt = 0;
1944                         if (cur_vit_mask < 0)
1945                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1946                         else
1947                                 mask_p[cur_vit_mask / 100] = mask_amt;
1948                 }
1949                 cur_vit_mask -= 100;
1950         }
1951
1952         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1953                 | (mask_m[48] << 26) | (mask_m[49] << 24)
1954                 | (mask_m[50] << 22) | (mask_m[51] << 20)
1955                 | (mask_m[52] << 18) | (mask_m[53] << 16)
1956                 | (mask_m[54] << 14) | (mask_m[55] << 12)
1957                 | (mask_m[56] << 10) | (mask_m[57] << 8)
1958                 | (mask_m[58] << 6) | (mask_m[59] << 4)
1959                 | (mask_m[60] << 2) | (mask_m[61] << 0);
1960         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1961         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1962
1963         tmp_mask = (mask_m[31] << 28)
1964                 | (mask_m[32] << 26) | (mask_m[33] << 24)
1965                 | (mask_m[34] << 22) | (mask_m[35] << 20)
1966                 | (mask_m[36] << 18) | (mask_m[37] << 16)
1967                 | (mask_m[48] << 14) | (mask_m[39] << 12)
1968                 | (mask_m[40] << 10) | (mask_m[41] << 8)
1969                 | (mask_m[42] << 6) | (mask_m[43] << 4)
1970                 | (mask_m[44] << 2) | (mask_m[45] << 0);
1971         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1972         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1973
1974         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1975                 | (mask_m[18] << 26) | (mask_m[18] << 24)
1976                 | (mask_m[20] << 22) | (mask_m[20] << 20)
1977                 | (mask_m[22] << 18) | (mask_m[22] << 16)
1978                 | (mask_m[24] << 14) | (mask_m[24] << 12)
1979                 | (mask_m[25] << 10) | (mask_m[26] << 8)
1980                 | (mask_m[27] << 6) | (mask_m[28] << 4)
1981                 | (mask_m[29] << 2) | (mask_m[30] << 0);
1982         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1983         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1984
1985         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1986                 | (mask_m[2] << 26) | (mask_m[3] << 24)
1987                 | (mask_m[4] << 22) | (mask_m[5] << 20)
1988                 | (mask_m[6] << 18) | (mask_m[7] << 16)
1989                 | (mask_m[8] << 14) | (mask_m[9] << 12)
1990                 | (mask_m[10] << 10) | (mask_m[11] << 8)
1991                 | (mask_m[12] << 6) | (mask_m[13] << 4)
1992                 | (mask_m[14] << 2) | (mask_m[15] << 0);
1993         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1994         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1995
1996         tmp_mask = (mask_p[15] << 28)
1997                 | (mask_p[14] << 26) | (mask_p[13] << 24)
1998                 | (mask_p[12] << 22) | (mask_p[11] << 20)
1999                 | (mask_p[10] << 18) | (mask_p[9] << 16)
2000                 | (mask_p[8] << 14) | (mask_p[7] << 12)
2001                 | (mask_p[6] << 10) | (mask_p[5] << 8)
2002                 | (mask_p[4] << 6) | (mask_p[3] << 4)
2003                 | (mask_p[2] << 2) | (mask_p[1] << 0);
2004         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2005         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2006
2007         tmp_mask = (mask_p[30] << 28)
2008                 | (mask_p[29] << 26) | (mask_p[28] << 24)
2009                 | (mask_p[27] << 22) | (mask_p[26] << 20)
2010                 | (mask_p[25] << 18) | (mask_p[24] << 16)
2011                 | (mask_p[23] << 14) | (mask_p[22] << 12)
2012                 | (mask_p[21] << 10) | (mask_p[20] << 8)
2013                 | (mask_p[19] << 6) | (mask_p[18] << 4)
2014                 | (mask_p[17] << 2) | (mask_p[16] << 0);
2015         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2016         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2017
2018         tmp_mask = (mask_p[45] << 28)
2019                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2020                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2021                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2022                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2023                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2024                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2025                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2026         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2027         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2028
2029         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2030                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2031                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2032                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2033                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2034                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2035                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2036                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2037         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2038         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2039 }
2040
2041 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
2042 {
2043         int bb_spur = AR_NO_SPUR;
2044         int bin, cur_bin;
2045         int spur_freq_sd;
2046         int spur_delta_phase;
2047         int denominator;
2048         int upper, lower, cur_vit_mask;
2049         int tmp, new;
2050         int i;
2051         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
2052                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2053         };
2054         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2055                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2056         };
2057         int inc[4] = { 0, 100, 0, 0 };
2058
2059         int8_t mask_m[123];
2060         int8_t mask_p[123];
2061         int8_t mask_amt;
2062         int tmp_mask;
2063         int cur_bb_spur;
2064         bool is2GHz = IS_CHAN_2GHZ(chan);
2065
2066         memset(&mask_m, 0, sizeof(int8_t) * 123);
2067         memset(&mask_p, 0, sizeof(int8_t) * 123);
2068
2069         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2070                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
2071                 if (AR_NO_SPUR == cur_bb_spur)
2072                         break;
2073                 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2074                 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2075                         bb_spur = cur_bb_spur;
2076                         break;
2077                 }
2078         }
2079
2080         if (AR_NO_SPUR == bb_spur)
2081                 return;
2082
2083         bin = bb_spur * 32;
2084
2085         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2086         new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2087                      AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2088                      AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2089                      AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2090
2091         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2092
2093         new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2094                AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2095                AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2096                AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2097                SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2098         REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2099
2100         spur_delta_phase = ((bb_spur * 524288) / 100) &
2101                 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2102
2103         denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2104         spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2105
2106         new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2107                SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2108                SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2109         REG_WRITE(ah, AR_PHY_TIMING11, new);
2110
2111         cur_bin = -6000;
2112         upper = bin + 100;
2113         lower = bin - 100;
2114
2115         for (i = 0; i < 4; i++) {
2116                 int pilot_mask = 0;
2117                 int chan_mask = 0;
2118                 int bp = 0;
2119                 for (bp = 0; bp < 30; bp++) {
2120                         if ((cur_bin > lower) && (cur_bin < upper)) {
2121                                 pilot_mask = pilot_mask | 0x1 << bp;
2122                                 chan_mask = chan_mask | 0x1 << bp;
2123                         }
2124                         cur_bin += 100;
2125                 }
2126                 cur_bin += inc[i];
2127                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2128                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2129         }
2130
2131         cur_vit_mask = 6100;
2132         upper = bin + 120;
2133         lower = bin - 120;
2134
2135         for (i = 0; i < 123; i++) {
2136                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2137
2138                         /* workaround for gcc bug #37014 */
2139                         volatile int tmp_v = abs(cur_vit_mask - bin);
2140
2141                         if (tmp_v < 75)
2142                                 mask_amt = 1;
2143                         else
2144                                 mask_amt = 0;
2145                         if (cur_vit_mask < 0)
2146                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2147                         else
2148                                 mask_p[cur_vit_mask / 100] = mask_amt;
2149                 }
2150                 cur_vit_mask -= 100;
2151         }
2152
2153         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2154                 | (mask_m[48] << 26) | (mask_m[49] << 24)
2155                 | (mask_m[50] << 22) | (mask_m[51] << 20)
2156                 | (mask_m[52] << 18) | (mask_m[53] << 16)
2157                 | (mask_m[54] << 14) | (mask_m[55] << 12)
2158                 | (mask_m[56] << 10) | (mask_m[57] << 8)
2159                 | (mask_m[58] << 6) | (mask_m[59] << 4)
2160                 | (mask_m[60] << 2) | (mask_m[61] << 0);
2161         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2162         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2163
2164         tmp_mask = (mask_m[31] << 28)
2165                 | (mask_m[32] << 26) | (mask_m[33] << 24)
2166                 | (mask_m[34] << 22) | (mask_m[35] << 20)
2167                 | (mask_m[36] << 18) | (mask_m[37] << 16)
2168                 | (mask_m[48] << 14) | (mask_m[39] << 12)
2169                 | (mask_m[40] << 10) | (mask_m[41] << 8)
2170                 | (mask_m[42] << 6) | (mask_m[43] << 4)
2171                 | (mask_m[44] << 2) | (mask_m[45] << 0);
2172         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2173         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2174
2175         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2176                 | (mask_m[18] << 26) | (mask_m[18] << 24)
2177                 | (mask_m[20] << 22) | (mask_m[20] << 20)
2178                 | (mask_m[22] << 18) | (mask_m[22] << 16)
2179                 | (mask_m[24] << 14) | (mask_m[24] << 12)
2180                 | (mask_m[25] << 10) | (mask_m[26] << 8)
2181                 | (mask_m[27] << 6) | (mask_m[28] << 4)
2182                 | (mask_m[29] << 2) | (mask_m[30] << 0);
2183         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2184         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2185
2186         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2187                 | (mask_m[2] << 26) | (mask_m[3] << 24)
2188                 | (mask_m[4] << 22) | (mask_m[5] << 20)
2189                 | (mask_m[6] << 18) | (mask_m[7] << 16)
2190                 | (mask_m[8] << 14) | (mask_m[9] << 12)
2191                 | (mask_m[10] << 10) | (mask_m[11] << 8)
2192                 | (mask_m[12] << 6) | (mask_m[13] << 4)
2193                 | (mask_m[14] << 2) | (mask_m[15] << 0);
2194         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2195         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2196
2197         tmp_mask = (mask_p[15] << 28)
2198                 | (mask_p[14] << 26) | (mask_p[13] << 24)
2199                 | (mask_p[12] << 22) | (mask_p[11] << 20)
2200                 | (mask_p[10] << 18) | (mask_p[9] << 16)
2201                 | (mask_p[8] << 14) | (mask_p[7] << 12)
2202                 | (mask_p[6] << 10) | (mask_p[5] << 8)
2203                 | (mask_p[4] << 6) | (mask_p[3] << 4)
2204                 | (mask_p[2] << 2) | (mask_p[1] << 0);
2205         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2206         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2207
2208         tmp_mask = (mask_p[30] << 28)
2209                 | (mask_p[29] << 26) | (mask_p[28] << 24)
2210                 | (mask_p[27] << 22) | (mask_p[26] << 20)
2211                 | (mask_p[25] << 18) | (mask_p[24] << 16)
2212                 | (mask_p[23] << 14) | (mask_p[22] << 12)
2213                 | (mask_p[21] << 10) | (mask_p[20] << 8)
2214                 | (mask_p[19] << 6) | (mask_p[18] << 4)
2215                 | (mask_p[17] << 2) | (mask_p[16] << 0);
2216         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2217         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2218
2219         tmp_mask = (mask_p[45] << 28)
2220                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2221                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2222                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2223                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2224                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2225                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2226                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2227         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2228         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2229
2230         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2231                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2232                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2233                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2234                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2235                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2236                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2237                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2238         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2239         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2240 }
2241
2242 static void ath9k_enable_rfkill(struct ath_hw *ah)
2243 {
2244         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2245                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
2246
2247         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
2248                     AR_GPIO_INPUT_MUX2_RFSILENT);
2249
2250         ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
2251         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
2252 }
2253
2254 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2255                     bool bChannelChange)
2256 {
2257         u32 saveLedState;
2258         struct ath_softc *sc = ah->ah_sc;
2259         struct ath9k_channel *curchan = ah->curchan;
2260         u32 saveDefAntenna;
2261         u32 macStaId1;
2262         int i, rx_chainmask, r;
2263
2264         ah->extprotspacing = sc->ht_extprotspacing;
2265         ah->txchainmask = sc->tx_chainmask;
2266         ah->rxchainmask = sc->rx_chainmask;
2267
2268         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2269                 return -EIO;
2270
2271         if (curchan)
2272                 ath9k_hw_getnf(ah, curchan);
2273
2274         if (bChannelChange &&
2275             (ah->chip_fullsleep != true) &&
2276             (ah->curchan != NULL) &&
2277             (chan->channel != ah->curchan->channel) &&
2278             ((chan->channelFlags & CHANNEL_ALL) ==
2279              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
2280             (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2281                                    !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) {
2282
2283                 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2284                         ath9k_hw_loadnf(ah, ah->curchan);
2285                         ath9k_hw_start_nfcal(ah);
2286                         return 0;
2287                 }
2288         }
2289
2290         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2291         if (saveDefAntenna == 0)
2292                 saveDefAntenna = 1;
2293
2294         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2295
2296         saveLedState = REG_READ(ah, AR_CFG_LED) &
2297                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2298                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2299
2300         ath9k_hw_mark_phy_inactive(ah);
2301
2302         if (!ath9k_hw_chip_reset(ah, chan)) {
2303                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Chip reset failed\n");
2304                 return -EINVAL;
2305         }
2306
2307         if (AR_SREV_9280_10_OR_LATER(ah))
2308                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2309
2310         if (AR_SREV_9287_10_OR_LATER(ah)) {
2311                 /* Enable ASYNC FIFO */
2312                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2313                                 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
2314                 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
2315                 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2316                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2317                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2318                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2319         }
2320         r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2321         if (r)
2322                 return r;
2323
2324         /* Setup MFP options for CCMP */
2325         if (AR_SREV_9280_20_OR_LATER(ah)) {
2326                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2327                  * frames when constructing CCMP AAD. */
2328                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2329                               0xc7ff);
2330                 ah->sw_mgmt_crypto = false;
2331         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2332                 /* Disable hardware crypto for management frames */
2333                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2334                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2335                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2336                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2337                 ah->sw_mgmt_crypto = true;
2338         } else
2339                 ah->sw_mgmt_crypto = true;
2340
2341         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2342                 ath9k_hw_set_delta_slope(ah, chan);
2343
2344         if (AR_SREV_9280_10_OR_LATER(ah))
2345                 ath9k_hw_9280_spur_mitigate(ah, chan);
2346         else
2347                 ath9k_hw_spur_mitigate(ah, chan);
2348
2349         ah->eep_ops->set_board_values(ah, chan);
2350
2351         ath9k_hw_decrease_chain_power(ah, chan);
2352
2353         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
2354         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
2355                   | macStaId1
2356                   | AR_STA_ID1_RTS_USE_DEF
2357                   | (ah->config.
2358                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2359                   | ah->sta_id1_defaults);
2360         ath9k_hw_set_operating_mode(ah, ah->opmode);
2361
2362         REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
2363         REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
2364
2365         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2366
2367         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
2368         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2369                   ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2370
2371         REG_WRITE(ah, AR_ISR, ~0);
2372
2373         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2374
2375         if (AR_SREV_9280_10_OR_LATER(ah))
2376                 ath9k_hw_ar9280_set_channel(ah, chan);
2377         else
2378                 if (!(ath9k_hw_set_channel(ah, chan)))
2379                         return -EIO;
2380
2381         for (i = 0; i < AR_NUM_DCU; i++)
2382                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2383
2384         ah->intr_txqs = 0;
2385         for (i = 0; i < ah->caps.total_queues; i++)
2386                 ath9k_hw_resettxqueue(ah, i);
2387
2388         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2389         ath9k_hw_init_qos(ah);
2390
2391         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2392                 ath9k_enable_rfkill(ah);
2393
2394         ath9k_hw_init_user_settings(ah);
2395
2396         if (AR_SREV_9287_10_OR_LATER(ah)) {
2397                 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2398                           AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2399                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2400                           AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2401                 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2402                           AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2403
2404                 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2405                 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2406
2407                 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2408                             AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2409                 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2410                               AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2411         }
2412         if (AR_SREV_9287_10_OR_LATER(ah)) {
2413                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2414                                 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2415         }
2416
2417         REG_WRITE(ah, AR_STA_ID1,
2418                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2419
2420         ath9k_hw_set_dma(ah);
2421
2422         REG_WRITE(ah, AR_OBS, 8);
2423
2424         if (ah->config.intr_mitigation) {
2425                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2426                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2427         }
2428
2429         ath9k_hw_init_bb(ah, chan);
2430
2431         if (!ath9k_hw_init_cal(ah, chan))
2432                 return -EIO;
2433
2434         rx_chainmask = ah->rxchainmask;
2435         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2436                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2437                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2438         }
2439
2440         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2441
2442         if (AR_SREV_9100(ah)) {
2443                 u32 mask;
2444                 mask = REG_READ(ah, AR_CFG);
2445                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2446                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2447                                 "CFG Byte Swap Set 0x%x\n", mask);
2448                 } else {
2449                         mask =
2450                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2451                         REG_WRITE(ah, AR_CFG, mask);
2452                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2453                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2454                 }
2455         } else {
2456 #ifdef __BIG_ENDIAN
2457                 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2458 #endif
2459         }
2460
2461         return 0;
2462 }
2463
2464 /************************/
2465 /* Key Cache Management */
2466 /************************/
2467
2468 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2469 {
2470         u32 keyType;
2471
2472         if (entry >= ah->caps.keycache_size) {
2473                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2474                         "keychache entry %u out of range\n", entry);
2475                 return false;
2476         }
2477
2478         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2479
2480         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2481         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2482         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2483         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2484         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2485         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2486         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2487         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2488
2489         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2490                 u16 micentry = entry + 64;
2491
2492                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2493                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2494                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2495                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2496
2497         }
2498
2499         return true;
2500 }
2501
2502 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2503 {
2504         u32 macHi, macLo;
2505
2506         if (entry >= ah->caps.keycache_size) {
2507                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2508                         "keychache entry %u out of range\n", entry);
2509                 return false;
2510         }
2511
2512         if (mac != NULL) {
2513                 macHi = (mac[5] << 8) | mac[4];
2514                 macLo = (mac[3] << 24) |
2515                         (mac[2] << 16) |
2516                         (mac[1] << 8) |
2517                         mac[0];
2518                 macLo >>= 1;
2519                 macLo |= (macHi & 1) << 31;
2520                 macHi >>= 1;
2521         } else {
2522                 macLo = macHi = 0;
2523         }
2524         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2525         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2526
2527         return true;
2528 }
2529
2530 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2531                                  const struct ath9k_keyval *k,
2532                                  const u8 *mac)
2533 {
2534         const struct ath9k_hw_capabilities *pCap = &ah->caps;
2535         u32 key0, key1, key2, key3, key4;
2536         u32 keyType;
2537
2538         if (entry >= pCap->keycache_size) {
2539                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2540                         "keycache entry %u out of range\n", entry);
2541                 return false;
2542         }
2543
2544         switch (k->kv_type) {
2545         case ATH9K_CIPHER_AES_OCB:
2546                 keyType = AR_KEYTABLE_TYPE_AES;
2547                 break;
2548         case ATH9K_CIPHER_AES_CCM:
2549                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2550                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2551                                 "AES-CCM not supported by mac rev 0x%x\n",
2552                                 ah->hw_version.macRev);
2553                         return false;
2554                 }
2555                 keyType = AR_KEYTABLE_TYPE_CCM;
2556                 break;
2557         case ATH9K_CIPHER_TKIP:
2558                 keyType = AR_KEYTABLE_TYPE_TKIP;
2559                 if (ATH9K_IS_MIC_ENABLED(ah)
2560                     && entry + 64 >= pCap->keycache_size) {
2561                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2562                                 "entry %u inappropriate for TKIP\n", entry);
2563                         return false;
2564                 }
2565                 break;
2566         case ATH9K_CIPHER_WEP:
2567                 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2568                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2569                                 "WEP key length %u too small\n", k->kv_len);
2570                         return false;
2571                 }
2572                 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
2573                         keyType = AR_KEYTABLE_TYPE_40;
2574                 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2575                         keyType = AR_KEYTABLE_TYPE_104;
2576                 else
2577                         keyType = AR_KEYTABLE_TYPE_128;
2578                 break;
2579         case ATH9K_CIPHER_CLR:
2580                 keyType = AR_KEYTABLE_TYPE_CLR;
2581                 break;
2582         default:
2583                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2584                         "cipher %u not supported\n", k->kv_type);
2585                 return false;
2586         }
2587
2588         key0 = get_unaligned_le32(k->kv_val + 0);
2589         key1 = get_unaligned_le16(k->kv_val + 4);
2590         key2 = get_unaligned_le32(k->kv_val + 6);
2591         key3 = get_unaligned_le16(k->kv_val + 10);
2592         key4 = get_unaligned_le32(k->kv_val + 12);
2593         if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2594                 key4 &= 0xff;
2595
2596         /*
2597          * Note: Key cache registers access special memory area that requires
2598          * two 32-bit writes to actually update the values in the internal
2599          * memory. Consequently, the exact order and pairs used here must be
2600          * maintained.
2601          */
2602
2603         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2604                 u16 micentry = entry + 64;
2605
2606                 /*
2607                  * Write inverted key[47:0] first to avoid Michael MIC errors
2608                  * on frames that could be sent or received at the same time.
2609                  * The correct key will be written in the end once everything
2610                  * else is ready.
2611                  */
2612                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2613                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2614
2615                 /* Write key[95:48] */
2616                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2617                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2618
2619                 /* Write key[127:96] and key type */
2620                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2621                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2622
2623                 /* Write MAC address for the entry */
2624                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2625
2626                 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2627                         /*
2628                          * TKIP uses two key cache entries:
2629                          * Michael MIC TX/RX keys in the same key cache entry
2630                          * (idx = main index + 64):
2631                          * key0 [31:0] = RX key [31:0]
2632                          * key1 [15:0] = TX key [31:16]
2633                          * key1 [31:16] = reserved
2634                          * key2 [31:0] = RX key [63:32]
2635                          * key3 [15:0] = TX key [15:0]
2636                          * key3 [31:16] = reserved
2637                          * key4 [31:0] = TX key [63:32]
2638                          */
2639                         u32 mic0, mic1, mic2, mic3, mic4;
2640
2641                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2642                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2643                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2644                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2645                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
2646
2647                         /* Write RX[31:0] and TX[31:16] */
2648                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2649                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2650
2651                         /* Write RX[63:32] and TX[15:0] */
2652                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2653                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2654
2655                         /* Write TX[63:32] and keyType(reserved) */
2656                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2657                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2658                                   AR_KEYTABLE_TYPE_CLR);
2659
2660                 } else {
2661                         /*
2662                          * TKIP uses four key cache entries (two for group
2663                          * keys):
2664                          * Michael MIC TX/RX keys are in different key cache
2665                          * entries (idx = main index + 64 for TX and
2666                          * main index + 32 + 96 for RX):
2667                          * key0 [31:0] = TX/RX MIC key [31:0]
2668                          * key1 [31:0] = reserved
2669                          * key2 [31:0] = TX/RX MIC key [63:32]
2670                          * key3 [31:0] = reserved
2671                          * key4 [31:0] = reserved
2672                          *
2673                          * Upper layer code will call this function separately
2674                          * for TX and RX keys when these registers offsets are
2675                          * used.
2676                          */
2677                         u32 mic0, mic2;
2678
2679                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2680                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2681
2682                         /* Write MIC key[31:0] */
2683                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2684                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2685
2686                         /* Write MIC key[63:32] */
2687                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2688                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2689
2690                         /* Write TX[63:32] and keyType(reserved) */
2691                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2692                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2693                                   AR_KEYTABLE_TYPE_CLR);
2694                 }
2695
2696                 /* MAC address registers are reserved for the MIC entry */
2697                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2698                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2699
2700                 /*
2701                  * Write the correct (un-inverted) key[47:0] last to enable
2702                  * TKIP now that all other registers are set with correct
2703                  * values.
2704                  */
2705                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2706                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2707         } else {
2708                 /* Write key[47:0] */
2709                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2710                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2711
2712                 /* Write key[95:48] */
2713                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2714                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2715
2716                 /* Write key[127:96] and key type */
2717                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2718                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2719
2720                 /* Write MAC address for the entry */
2721                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2722         }
2723
2724         return true;
2725 }
2726
2727 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2728 {
2729         if (entry < ah->caps.keycache_size) {
2730                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2731                 if (val & AR_KEYTABLE_VALID)
2732                         return true;
2733         }
2734         return false;
2735 }
2736
2737 /******************************/
2738 /* Power Management (Chipset) */
2739 /******************************/
2740
2741 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2742 {
2743         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2744         if (setChip) {
2745                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2746                             AR_RTC_FORCE_WAKE_EN);
2747                 if (!AR_SREV_9100(ah))
2748                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2749
2750                 REG_CLR_BIT(ah, (AR_RTC_RESET),
2751                             AR_RTC_RESET_EN);
2752         }
2753 }
2754
2755 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2756 {
2757         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2758         if (setChip) {
2759                 struct ath9k_hw_capabilities *pCap = &ah->caps;
2760
2761                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2762                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2763                                   AR_RTC_FORCE_WAKE_ON_INT);
2764                 } else {
2765                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2766                                     AR_RTC_FORCE_WAKE_EN);
2767                 }
2768         }
2769 }
2770
2771 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2772 {
2773         u32 val;
2774         int i;
2775
2776         if (setChip) {
2777                 if ((REG_READ(ah, AR_RTC_STATUS) &
2778                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2779                         if (ath9k_hw_set_reset_reg(ah,
2780                                            ATH9K_RESET_POWER_ON) != true) {
2781                                 return false;
2782                         }
2783                 }
2784                 if (AR_SREV_9100(ah))
2785                         REG_SET_BIT(ah, AR_RTC_RESET,
2786                                     AR_RTC_RESET_EN);
2787
2788                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2789                             AR_RTC_FORCE_WAKE_EN);
2790                 udelay(50);
2791
2792                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2793                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2794                         if (val == AR_RTC_STATUS_ON)
2795                                 break;
2796                         udelay(50);
2797                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2798                                     AR_RTC_FORCE_WAKE_EN);
2799                 }
2800                 if (i == 0) {
2801                         DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2802                                 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2803                         return false;
2804                 }
2805         }
2806
2807         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2808
2809         return true;
2810 }
2811
2812 static bool ath9k_hw_setpower_nolock(struct ath_hw *ah,
2813                                      enum ath9k_power_mode mode)
2814 {
2815         int status = true, setChip = true;
2816         static const char *modes[] = {
2817                 "AWAKE",
2818                 "FULL-SLEEP",
2819                 "NETWORK SLEEP",
2820                 "UNDEFINED"
2821         };
2822
2823         if (ah->power_mode == mode)
2824                 return status;
2825
2826         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s -> %s\n",
2827                 modes[ah->power_mode], modes[mode]);
2828
2829         switch (mode) {
2830         case ATH9K_PM_AWAKE:
2831                 status = ath9k_hw_set_power_awake(ah, setChip);
2832                 break;
2833         case ATH9K_PM_FULL_SLEEP:
2834                 ath9k_set_power_sleep(ah, setChip);
2835                 ah->chip_fullsleep = true;
2836                 break;
2837         case ATH9K_PM_NETWORK_SLEEP:
2838                 ath9k_set_power_network_sleep(ah, setChip);
2839                 break;
2840         default:
2841                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2842                         "Unknown power mode %u\n", mode);
2843                 return false;
2844         }
2845         ah->power_mode = mode;
2846
2847         return status;
2848 }
2849
2850 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2851 {
2852         unsigned long flags;
2853         bool ret;
2854
2855         spin_lock_irqsave(&ah->ah_sc->sc_pm_lock, flags);
2856         ret = ath9k_hw_setpower_nolock(ah, mode);
2857         spin_unlock_irqrestore(&ah->ah_sc->sc_pm_lock, flags);
2858
2859         return ret;
2860 }
2861
2862 void ath9k_ps_wakeup(struct ath_softc *sc)
2863 {
2864         unsigned long flags;
2865
2866         spin_lock_irqsave(&sc->sc_pm_lock, flags);
2867         if (++sc->ps_usecount != 1)
2868                 goto unlock;
2869
2870         ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_AWAKE);
2871
2872  unlock:
2873         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2874 }
2875
2876 void ath9k_ps_restore(struct ath_softc *sc)
2877 {
2878         unsigned long flags;
2879
2880         spin_lock_irqsave(&sc->sc_pm_lock, flags);
2881         if (--sc->ps_usecount != 0)
2882                 goto unlock;
2883
2884         if (sc->ps_enabled &&
2885             !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
2886                               SC_OP_WAIT_FOR_CAB |
2887                               SC_OP_WAIT_FOR_PSPOLL_DATA |
2888                               SC_OP_WAIT_FOR_TX_ACK)))
2889                 ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2890
2891  unlock:
2892         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2893 }
2894
2895 /*
2896  * Helper for ASPM support.
2897  *
2898  * Disable PLL when in L0s as well as receiver clock when in L1.
2899  * This power saving option must be enabled through the SerDes.
2900  *
2901  * Programming the SerDes must go through the same 288 bit serial shift
2902  * register as the other analog registers.  Hence the 9 writes.
2903  */
2904 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
2905 {
2906         u8 i;
2907
2908         if (ah->is_pciexpress != true)
2909                 return;
2910
2911         /* Do not touch SerDes registers */
2912         if (ah->config.pcie_powersave_enable == 2)
2913                 return;
2914
2915         /* Nothing to do on restore for 11N */
2916         if (restore)
2917                 return;
2918
2919         if (AR_SREV_9280_20_OR_LATER(ah)) {
2920                 /*
2921                  * AR9280 2.0 or later chips use SerDes values from the
2922                  * initvals.h initialized depending on chipset during
2923                  * ath9k_hw_init()
2924                  */
2925                 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2926                         REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2927                                   INI_RA(&ah->iniPcieSerdes, i, 1));
2928                 }
2929         } else if (AR_SREV_9280(ah) &&
2930                    (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2931                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2932                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2933
2934                 /* RX shut off when elecidle is asserted */
2935                 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2936                 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2937                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2938
2939                 /* Shut off CLKREQ active in L1 */
2940                 if (ah->config.pcie_clock_req)
2941                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2942                 else
2943                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2944
2945                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2946                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2947                 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2948
2949                 /* Load the new settings */
2950                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2951
2952         } else {
2953                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2954                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2955
2956                 /* RX shut off when elecidle is asserted */
2957                 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2958                 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2959                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2960
2961                 /*
2962                  * Ignore ah->ah_config.pcie_clock_req setting for
2963                  * pre-AR9280 11n
2964                  */
2965                 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2966
2967                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2968                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2969                 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2970
2971                 /* Load the new settings */
2972                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2973         }
2974
2975         udelay(1000);
2976
2977         /* set bit 19 to allow forcing of pcie core into L1 state */
2978         REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2979
2980         /* Several PCIe massages to ensure proper behaviour */
2981         if (ah->config.pcie_waen) {
2982                 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
2983         } else {
2984                 if (AR_SREV_9285(ah))
2985                         REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2986                 /*
2987                  * On AR9280 chips bit 22 of 0x4004 needs to be set to
2988                  * otherwise card may disappear.
2989                  */
2990                 else if (AR_SREV_9280(ah))
2991                         REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
2992                 else
2993                         REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
2994         }
2995 }
2996
2997 /**********************/
2998 /* Interrupt Handling */
2999 /**********************/
3000
3001 bool ath9k_hw_intrpend(struct ath_hw *ah)
3002 {
3003         u32 host_isr;
3004
3005         if (AR_SREV_9100(ah))
3006                 return true;
3007
3008         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
3009         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
3010                 return true;
3011
3012         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
3013         if ((host_isr & AR_INTR_SYNC_DEFAULT)
3014             && (host_isr != AR_INTR_SPURIOUS))
3015                 return true;
3016
3017         return false;
3018 }
3019
3020 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
3021 {
3022         u32 isr = 0;
3023         u32 mask2 = 0;
3024         struct ath9k_hw_capabilities *pCap = &ah->caps;
3025         u32 sync_cause = 0;
3026         bool fatal_int = false;
3027
3028         if (!AR_SREV_9100(ah)) {
3029                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
3030                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
3031                             == AR_RTC_STATUS_ON) {
3032                                 isr = REG_READ(ah, AR_ISR);
3033                         }
3034                 }
3035
3036                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
3037                         AR_INTR_SYNC_DEFAULT;
3038
3039                 *masked = 0;
3040
3041                 if (!isr && !sync_cause)
3042                         return false;
3043         } else {
3044                 *masked = 0;
3045                 isr = REG_READ(ah, AR_ISR);
3046         }
3047
3048         if (isr) {
3049                 if (isr & AR_ISR_BCNMISC) {
3050                         u32 isr2;
3051                         isr2 = REG_READ(ah, AR_ISR_S2);
3052                         if (isr2 & AR_ISR_S2_TIM)
3053                                 mask2 |= ATH9K_INT_TIM;
3054                         if (isr2 & AR_ISR_S2_DTIM)
3055                                 mask2 |= ATH9K_INT_DTIM;
3056                         if (isr2 & AR_ISR_S2_DTIMSYNC)
3057                                 mask2 |= ATH9K_INT_DTIMSYNC;
3058                         if (isr2 & (AR_ISR_S2_CABEND))
3059                                 mask2 |= ATH9K_INT_CABEND;
3060                         if (isr2 & AR_ISR_S2_GTT)
3061                                 mask2 |= ATH9K_INT_GTT;
3062                         if (isr2 & AR_ISR_S2_CST)
3063                                 mask2 |= ATH9K_INT_CST;
3064                         if (isr2 & AR_ISR_S2_TSFOOR)
3065                                 mask2 |= ATH9K_INT_TSFOOR;
3066                 }
3067
3068                 isr = REG_READ(ah, AR_ISR_RAC);
3069                 if (isr == 0xffffffff) {
3070                         *masked = 0;
3071                         return false;
3072                 }
3073
3074                 *masked = isr & ATH9K_INT_COMMON;
3075
3076                 if (ah->config.intr_mitigation) {
3077                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
3078                                 *masked |= ATH9K_INT_RX;
3079                 }
3080
3081                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
3082                         *masked |= ATH9K_INT_RX;
3083                 if (isr &
3084                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
3085                      AR_ISR_TXEOL)) {
3086                         u32 s0_s, s1_s;
3087
3088                         *masked |= ATH9K_INT_TX;
3089
3090                         s0_s = REG_READ(ah, AR_ISR_S0_S);
3091                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
3092                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
3093
3094                         s1_s = REG_READ(ah, AR_ISR_S1_S);
3095                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
3096                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
3097                 }
3098
3099                 if (isr & AR_ISR_RXORN) {
3100                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3101                                 "receive FIFO overrun interrupt\n");
3102                 }
3103
3104                 if (!AR_SREV_9100(ah)) {
3105                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3106                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
3107                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
3108                                         *masked |= ATH9K_INT_TIM_TIMER;
3109                         }
3110                 }
3111
3112                 *masked |= mask2;
3113         }
3114
3115         if (AR_SREV_9100(ah))
3116                 return true;
3117
3118         if (sync_cause) {
3119                 fatal_int =
3120                         (sync_cause &
3121                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
3122                         ? true : false;
3123
3124                 if (fatal_int) {
3125                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
3126                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
3127                                         "received PCI FATAL interrupt\n");
3128                         }
3129                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
3130                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
3131                                         "received PCI PERR interrupt\n");
3132                         }
3133                         *masked |= ATH9K_INT_FATAL;
3134                 }
3135                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
3136                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3137                                 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
3138                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
3139                         REG_WRITE(ah, AR_RC, 0);
3140                         *masked |= ATH9K_INT_FATAL;
3141                 }
3142                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
3143                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3144                                 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
3145                 }
3146
3147                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
3148                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
3149         }
3150
3151         return true;
3152 }
3153
3154 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3155 {
3156         u32 omask = ah->mask_reg;
3157         u32 mask, mask2;
3158         struct ath9k_hw_capabilities *pCap = &ah->caps;
3159
3160         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
3161
3162         if (omask & ATH9K_INT_GLOBAL) {
3163                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
3164                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3165                 (void) REG_READ(ah, AR_IER);
3166                 if (!AR_SREV_9100(ah)) {
3167                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3168                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3169
3170                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3171                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3172                 }
3173         }
3174
3175         mask = ints & ATH9K_INT_COMMON;
3176         mask2 = 0;
3177
3178         if (ints & ATH9K_INT_TX) {
3179                 if (ah->txok_interrupt_mask)
3180                         mask |= AR_IMR_TXOK;
3181                 if (ah->txdesc_interrupt_mask)
3182                         mask |= AR_IMR_TXDESC;
3183                 if (ah->txerr_interrupt_mask)
3184                         mask |= AR_IMR_TXERR;
3185                 if (ah->txeol_interrupt_mask)
3186                         mask |= AR_IMR_TXEOL;
3187         }
3188         if (ints & ATH9K_INT_RX) {
3189                 mask |= AR_IMR_RXERR;
3190                 if (ah->config.intr_mitigation)
3191                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3192                 else
3193                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3194                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3195                         mask |= AR_IMR_GENTMR;
3196         }
3197
3198         if (ints & (ATH9K_INT_BMISC)) {
3199                 mask |= AR_IMR_BCNMISC;
3200                 if (ints & ATH9K_INT_TIM)
3201                         mask2 |= AR_IMR_S2_TIM;
3202                 if (ints & ATH9K_INT_DTIM)
3203                         mask2 |= AR_IMR_S2_DTIM;
3204                 if (ints & ATH9K_INT_DTIMSYNC)
3205                         mask2 |= AR_IMR_S2_DTIMSYNC;
3206                 if (ints & ATH9K_INT_CABEND)
3207                         mask2 |= AR_IMR_S2_CABEND;
3208                 if (ints & ATH9K_INT_TSFOOR)
3209                         mask2 |= AR_IMR_S2_TSFOOR;
3210         }
3211
3212         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3213                 mask |= AR_IMR_BCNMISC;
3214                 if (ints & ATH9K_INT_GTT)
3215                         mask2 |= AR_IMR_S2_GTT;
3216                 if (ints & ATH9K_INT_CST)
3217                         mask2 |= AR_IMR_S2_CST;
3218         }
3219
3220         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3221         REG_WRITE(ah, AR_IMR, mask);
3222         mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3223                                            AR_IMR_S2_DTIM |
3224                                            AR_IMR_S2_DTIMSYNC |
3225                                            AR_IMR_S2_CABEND |
3226                                            AR_IMR_S2_CABTO |
3227                                            AR_IMR_S2_TSFOOR |
3228                                            AR_IMR_S2_GTT | AR_IMR_S2_CST);
3229         REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3230         ah->mask_reg = ints;
3231
3232         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3233                 if (ints & ATH9K_INT_TIM_TIMER)
3234                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3235                 else
3236                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3237         }
3238
3239         if (ints & ATH9K_INT_GLOBAL) {
3240                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
3241                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3242                 if (!AR_SREV_9100(ah)) {
3243                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3244                                   AR_INTR_MAC_IRQ);
3245                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3246
3247
3248                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3249                                   AR_INTR_SYNC_DEFAULT);
3250                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
3251                                   AR_INTR_SYNC_DEFAULT);
3252                 }
3253                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3254                          REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3255         }
3256
3257         return omask;
3258 }
3259
3260 /*******************/
3261 /* Beacon Handling */
3262 /*******************/
3263
3264 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3265 {
3266         int flags = 0;
3267
3268         ah->beacon_interval = beacon_period;
3269
3270         switch (ah->opmode) {
3271         case NL80211_IFTYPE_STATION:
3272         case NL80211_IFTYPE_MONITOR:
3273                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3274                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3275                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3276                 flags |= AR_TBTT_TIMER_EN;
3277                 break;
3278         case NL80211_IFTYPE_ADHOC:
3279         case NL80211_IFTYPE_MESH_POINT:
3280                 REG_SET_BIT(ah, AR_TXCFG,
3281                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3282                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3283                           TU_TO_USEC(next_beacon +
3284                                      (ah->atim_window ? ah->
3285                                       atim_window : 1)));
3286                 flags |= AR_NDP_TIMER_EN;
3287         case NL80211_IFTYPE_AP:
3288                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3289                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3290                           TU_TO_USEC(next_beacon -
3291                                      ah->config.
3292                                      dma_beacon_response_time));
3293                 REG_WRITE(ah, AR_NEXT_SWBA,
3294                           TU_TO_USEC(next_beacon -
3295                                      ah->config.
3296                                      sw_beacon_response_time));
3297                 flags |=
3298                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3299                 break;
3300         default:
3301                 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3302                         "%s: unsupported opmode: %d\n",
3303                         __func__, ah->opmode);
3304                 return;
3305                 break;
3306         }
3307
3308         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3309         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3310         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3311         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3312
3313         beacon_period &= ~ATH9K_BEACON_ENA;
3314         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3315                 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3316                 ath9k_hw_reset_tsf(ah);
3317         }
3318
3319         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3320 }
3321
3322 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3323                                     const struct ath9k_beacon_state *bs)
3324 {
3325         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3326         struct ath9k_hw_capabilities *pCap = &ah->caps;
3327
3328         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3329
3330         REG_WRITE(ah, AR_BEACON_PERIOD,
3331                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3332         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3333                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3334
3335         REG_RMW_FIELD(ah, AR_RSSI_THR,
3336                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3337
3338         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3339
3340         if (bs->bs_sleepduration > beaconintval)
3341                 beaconintval = bs->bs_sleepduration;
3342
3343         dtimperiod = bs->bs_dtimperiod;
3344         if (bs->bs_sleepduration > dtimperiod)
3345                 dtimperiod = bs->bs_sleepduration;
3346
3347         if (beaconintval == dtimperiod)
3348                 nextTbtt = bs->bs_nextdtim;
3349         else
3350                 nextTbtt = bs->bs_nexttbtt;
3351
3352         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3353         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3354         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3355         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3356
3357         REG_WRITE(ah, AR_NEXT_DTIM,
3358                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3359         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3360
3361         REG_WRITE(ah, AR_SLEEP1,
3362                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3363                   | AR_SLEEP1_ASSUME_DTIM);
3364
3365         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3366                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3367         else
3368                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3369
3370         REG_WRITE(ah, AR_SLEEP2,
3371                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3372
3373         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3374         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3375
3376         REG_SET_BIT(ah, AR_TIMER_MODE,
3377                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3378                     AR_DTIM_TIMER_EN);
3379
3380         /* TSF Out of Range Threshold */
3381         REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3382 }
3383
3384 /*******************/
3385 /* HW Capabilities */
3386 /*******************/
3387
3388 void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3389 {
3390         struct ath9k_hw_capabilities *pCap = &ah->caps;
3391         u16 capField = 0, eeval;
3392
3393         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3394         ah->regulatory.current_rd = eeval;
3395
3396         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3397         if (AR_SREV_9285_10_OR_LATER(ah))
3398                 eeval |= AR9285_RDEXT_DEFAULT;
3399         ah->regulatory.current_rd_ext = eeval;
3400
3401         capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3402
3403         if (ah->opmode != NL80211_IFTYPE_AP &&
3404             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3405                 if (ah->regulatory.current_rd == 0x64 ||
3406                     ah->regulatory.current_rd == 0x65)
3407                         ah->regulatory.current_rd += 5;
3408                 else if (ah->regulatory.current_rd == 0x41)
3409                         ah->regulatory.current_rd = 0x43;
3410                 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3411                         "regdomain mapped to 0x%x\n", ah->regulatory.current_rd);
3412         }
3413
3414         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3415         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3416
3417         if (eeval & AR5416_OPFLAGS_11A) {
3418                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3419                 if (ah->config.ht_enable) {
3420                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3421                                 set_bit(ATH9K_MODE_11NA_HT20,
3422                                         pCap->wireless_modes);
3423                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3424                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3425                                         pCap->wireless_modes);
3426                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3427                                         pCap->wireless_modes);
3428                         }
3429                 }
3430         }
3431
3432         if (eeval & AR5416_OPFLAGS_11G) {
3433                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3434                 if (ah->config.ht_enable) {
3435                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3436                                 set_bit(ATH9K_MODE_11NG_HT20,
3437                                         pCap->wireless_modes);
3438                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3439                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3440                                         pCap->wireless_modes);
3441                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3442                                         pCap->wireless_modes);
3443                         }
3444                 }
3445         }
3446
3447         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3448         if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3449             !(eeval & AR5416_OPFLAGS_11A))
3450                 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3451         else
3452                 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3453
3454         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3455                 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3456
3457         pCap->low_2ghz_chan = 2312;
3458         pCap->high_2ghz_chan = 2732;
3459
3460         pCap->low_5ghz_chan = 4920;
3461         pCap->high_5ghz_chan = 6100;
3462
3463         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3464         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3465         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3466
3467         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3468         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3469         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3470
3471         if (ah->config.ht_enable)
3472                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3473         else
3474                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3475
3476         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3477         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3478         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3479         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3480
3481         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3482                 pCap->total_queues =
3483                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3484         else
3485                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3486
3487         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3488                 pCap->keycache_size =
3489                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3490         else
3491                 pCap->keycache_size = AR_KEYTABLE_SIZE;
3492
3493         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3494         pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3495
3496         if (AR_SREV_9285_10_OR_LATER(ah))
3497                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3498         else if (AR_SREV_9280_10_OR_LATER(ah))
3499                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3500         else
3501                 pCap->num_gpio_pins = AR_NUM_GPIO;
3502
3503         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3504                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3505                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3506         } else {
3507                 pCap->rts_aggr_limit = (8 * 1024);
3508         }
3509
3510         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3511
3512 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3513         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3514         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3515                 ah->rfkill_gpio =
3516                         MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3517                 ah->rfkill_polarity =
3518                         MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3519
3520                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3521         }
3522 #endif
3523
3524         if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) ||
3525             (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ||
3526             (ah->hw_version.macVersion == AR_SREV_VERSION_9160) ||
3527             (ah->hw_version.macVersion == AR_SREV_VERSION_9100) ||
3528             (ah->hw_version.macVersion == AR_SREV_VERSION_9280) ||
3529             (ah->hw_version.macVersion == AR_SREV_VERSION_9285))
3530                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3531         else
3532                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3533
3534         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3535                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3536         else
3537                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3538
3539         if (ah->regulatory.current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3540                 pCap->reg_cap =
3541                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3542                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3543                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3544                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3545         } else {
3546                 pCap->reg_cap =
3547                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3548                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3549         }
3550
3551         pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3552
3553         pCap->num_antcfg_5ghz =
3554                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3555         pCap->num_antcfg_2ghz =
3556                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3557
3558         if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
3559                 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
3560                 ah->btactive_gpio = 6;
3561                 ah->wlanactive_gpio = 5;
3562         }
3563 }
3564
3565 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3566                             u32 capability, u32 *result)
3567 {
3568         switch (type) {
3569         case ATH9K_CAP_CIPHER:
3570                 switch (capability) {
3571                 case ATH9K_CIPHER_AES_CCM:
3572                 case ATH9K_CIPHER_AES_OCB:
3573                 case ATH9K_CIPHER_TKIP:
3574                 case ATH9K_CIPHER_WEP:
3575                 case ATH9K_CIPHER_MIC:
3576                 case ATH9K_CIPHER_CLR:
3577                         return true;
3578                 default:
3579                         return false;
3580                 }
3581         case ATH9K_CAP_TKIP_MIC:
3582                 switch (capability) {
3583                 case 0:
3584                         return true;
3585                 case 1:
3586                         return (ah->sta_id1_defaults &
3587                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3588                         false;
3589                 }
3590         case ATH9K_CAP_TKIP_SPLIT:
3591                 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3592                         false : true;
3593         case ATH9K_CAP_DIVERSITY:
3594                 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3595                         AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3596                         true : false;
3597         case ATH9K_CAP_MCAST_KEYSRCH:
3598                 switch (capability) {
3599                 case 0:
3600                         return true;
3601                 case 1:
3602                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3603                                 return false;
3604                         } else {
3605                                 return (ah->sta_id1_defaults &
3606                                         AR_STA_ID1_MCAST_KSRCH) ? true :
3607                                         false;
3608                         }
3609                 }
3610                 return false;
3611         case ATH9K_CAP_TXPOW:
3612                 switch (capability) {
3613                 case 0:
3614                         return 0;
3615                 case 1:
3616                         *result = ah->regulatory.power_limit;
3617                         return 0;
3618                 case 2:
3619                         *result = ah->regulatory.max_power_level;
3620                         return 0;
3621                 case 3:
3622                         *result = ah->regulatory.tp_scale;
3623                         return 0;
3624                 }
3625                 return false;
3626         case ATH9K_CAP_DS:
3627                 return (AR_SREV_9280_20_OR_LATER(ah) &&
3628                         (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3629                         ? false : true;
3630         default:
3631                 return false;
3632         }
3633 }
3634
3635 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3636                             u32 capability, u32 setting, int *status)
3637 {
3638         u32 v;
3639
3640         switch (type) {
3641         case ATH9K_CAP_TKIP_MIC:
3642                 if (setting)
3643                         ah->sta_id1_defaults |=
3644                                 AR_STA_ID1_CRPT_MIC_ENABLE;
3645                 else
3646                         ah->sta_id1_defaults &=
3647                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3648                 return true;
3649         case ATH9K_CAP_DIVERSITY:
3650                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3651                 if (setting)
3652                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3653                 else
3654                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3655                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3656                 return true;
3657         case ATH9K_CAP_MCAST_KEYSRCH:
3658                 if (setting)
3659                         ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3660                 else
3661                         ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3662                 return true;
3663         default:
3664                 return false;
3665         }
3666 }
3667
3668 /****************************/
3669 /* GPIO / RFKILL / Antennae */
3670 /****************************/
3671
3672 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3673                                          u32 gpio, u32 type)
3674 {
3675         int addr;
3676         u32 gpio_shift, tmp;
3677
3678         if (gpio > 11)
3679                 addr = AR_GPIO_OUTPUT_MUX3;
3680         else if (gpio > 5)
3681                 addr = AR_GPIO_OUTPUT_MUX2;
3682         else
3683                 addr = AR_GPIO_OUTPUT_MUX1;
3684
3685         gpio_shift = (gpio % 6) * 5;
3686
3687         if (AR_SREV_9280_20_OR_LATER(ah)
3688             || (addr != AR_GPIO_OUTPUT_MUX1)) {
3689                 REG_RMW(ah, addr, (type << gpio_shift),
3690                         (0x1f << gpio_shift));
3691         } else {
3692                 tmp = REG_READ(ah, addr);
3693                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3694                 tmp &= ~(0x1f << gpio_shift);
3695                 tmp |= (type << gpio_shift);
3696                 REG_WRITE(ah, addr, tmp);
3697         }
3698 }
3699
3700 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3701 {
3702         u32 gpio_shift;
3703
3704         ASSERT(gpio < ah->caps.num_gpio_pins);
3705
3706         gpio_shift = gpio << 1;
3707
3708         REG_RMW(ah,
3709                 AR_GPIO_OE_OUT,
3710                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3711                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3712 }
3713
3714 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3715 {
3716 #define MS_REG_READ(x, y) \
3717         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3718
3719         if (gpio >= ah->caps.num_gpio_pins)
3720                 return 0xffffffff;
3721
3722         if (AR_SREV_9287_10_OR_LATER(ah))
3723                 return MS_REG_READ(AR9287, gpio) != 0;
3724         else if (AR_SREV_9285_10_OR_LATER(ah))
3725                 return MS_REG_READ(AR9285, gpio) != 0;
3726         else if (AR_SREV_9280_10_OR_LATER(ah))
3727                 return MS_REG_READ(AR928X, gpio) != 0;
3728         else
3729                 return MS_REG_READ(AR, gpio) != 0;
3730 }
3731
3732 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3733                          u32 ah_signal_type)
3734 {
3735         u32 gpio_shift;
3736
3737         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3738
3739         gpio_shift = 2 * gpio;
3740
3741         REG_RMW(ah,
3742                 AR_GPIO_OE_OUT,
3743                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3744                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3745 }
3746
3747 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3748 {
3749         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3750                 AR_GPIO_BIT(gpio));
3751 }
3752
3753 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3754 {
3755         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3756 }
3757
3758 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3759 {
3760         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3761 }
3762
3763 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3764                                enum ath9k_ant_setting settings,
3765                                struct ath9k_channel *chan,
3766                                u8 *tx_chainmask,
3767                                u8 *rx_chainmask,
3768                                u8 *antenna_cfgd)
3769 {
3770         static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3771
3772         if (AR_SREV_9280(ah)) {
3773                 if (!tx_chainmask_cfg) {
3774
3775                         tx_chainmask_cfg = *tx_chainmask;
3776                         rx_chainmask_cfg = *rx_chainmask;
3777                 }
3778
3779                 switch (settings) {
3780                 case ATH9K_ANT_FIXED_A:
3781                         *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3782                         *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3783                         *antenna_cfgd = true;
3784                         break;
3785                 case ATH9K_ANT_FIXED_B:
3786                         if (ah->caps.tx_chainmask >
3787                             ATH9K_ANTENNA1_CHAINMASK) {
3788                                 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3789                         }
3790                         *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3791                         *antenna_cfgd = true;
3792                         break;
3793                 case ATH9K_ANT_VARIABLE:
3794                         *tx_chainmask = tx_chainmask_cfg;
3795                         *rx_chainmask = rx_chainmask_cfg;
3796                         *antenna_cfgd = true;
3797                         break;
3798                 default:
3799                         break;
3800                 }
3801         } else {
3802                 ah->diversity_control = settings;
3803         }
3804
3805         return true;
3806 }
3807
3808 /*********************/
3809 /* General Operation */
3810 /*********************/
3811
3812 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3813 {
3814         u32 bits = REG_READ(ah, AR_RX_FILTER);
3815         u32 phybits = REG_READ(ah, AR_PHY_ERR);
3816
3817         if (phybits & AR_PHY_ERR_RADAR)
3818                 bits |= ATH9K_RX_FILTER_PHYRADAR;
3819         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3820                 bits |= ATH9K_RX_FILTER_PHYERR;
3821
3822         return bits;
3823 }
3824
3825 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3826 {
3827         u32 phybits;
3828
3829         REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3830         phybits = 0;
3831         if (bits & ATH9K_RX_FILTER_PHYRADAR)
3832                 phybits |= AR_PHY_ERR_RADAR;
3833         if (bits & ATH9K_RX_FILTER_PHYERR)
3834                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3835         REG_WRITE(ah, AR_PHY_ERR, phybits);
3836
3837         if (phybits)
3838                 REG_WRITE(ah, AR_RXCFG,
3839                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3840         else
3841                 REG_WRITE(ah, AR_RXCFG,
3842                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3843 }
3844
3845 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3846 {
3847         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3848 }
3849
3850 bool ath9k_hw_disable(struct ath_hw *ah)
3851 {
3852         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3853                 return false;
3854
3855         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3856 }
3857
3858 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3859 {
3860         struct ath9k_channel *chan = ah->curchan;
3861         struct ieee80211_channel *channel = chan->chan;
3862
3863         ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER);
3864
3865         ah->eep_ops->set_txpower(ah, chan,
3866                                  ath9k_regd_get_ctl(&ah->regulatory, chan),
3867                                  channel->max_antenna_gain * 2,
3868                                  channel->max_power * 2,
3869                                  min((u32) MAX_RATE_POWER,
3870                                  (u32) ah->regulatory.power_limit));
3871 }
3872
3873 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3874 {
3875         memcpy(ah->macaddr, mac, ETH_ALEN);
3876 }
3877
3878 void ath9k_hw_setopmode(struct ath_hw *ah)
3879 {
3880         ath9k_hw_set_operating_mode(ah, ah->opmode);
3881 }
3882
3883 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3884 {
3885         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3886         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3887 }
3888
3889 void ath9k_hw_setbssidmask(struct ath_softc *sc)
3890 {
3891         REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
3892         REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
3893 }
3894
3895 void ath9k_hw_write_associd(struct ath_softc *sc)
3896 {
3897         REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
3898         REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
3899                   ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3900 }
3901
3902 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3903 {
3904         u64 tsf;
3905
3906         tsf = REG_READ(ah, AR_TSF_U32);
3907         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3908
3909         return tsf;
3910 }
3911
3912 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3913 {
3914         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3915         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3916 }
3917
3918 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3919 {
3920         ath9k_ps_wakeup(ah->ah_sc);
3921         if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3922                            AH_TSF_WRITE_TIMEOUT))
3923                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3924                         "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3925
3926         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3927         ath9k_ps_restore(ah->ah_sc);
3928 }
3929
3930 bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3931 {
3932         if (setting)
3933                 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3934         else
3935                 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3936
3937         return true;
3938 }
3939
3940 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
3941 {
3942         if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3943                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3944                 ah->slottime = (u32) -1;
3945                 return false;
3946         } else {
3947                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3948                 ah->slottime = us;
3949                 return true;
3950         }
3951 }
3952
3953 void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
3954 {
3955         u32 macmode;
3956
3957         if (mode == ATH9K_HT_MACMODE_2040 &&
3958             !ah->config.cwm_ignore_extcca)
3959                 macmode = AR_2040_JOINED_RX_CLEAR;
3960         else
3961                 macmode = 0;
3962
3963         REG_WRITE(ah, AR_2040_MODE, macmode);
3964 }
3965
3966 /***************************/
3967 /*  Bluetooth Coexistence  */
3968 /***************************/
3969
3970 void ath9k_hw_btcoex_enable(struct ath_hw *ah)
3971 {
3972         /* connect bt_active to baseband */
3973         REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3974                         (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
3975                          AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
3976
3977         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3978                         AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
3979
3980         /* Set input mux for bt_active to gpio pin */
3981         REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
3982                         AR_GPIO_INPUT_MUX1_BT_ACTIVE,
3983                         ah->btactive_gpio);
3984
3985         /* Configure the desired gpio port for input */
3986         ath9k_hw_cfg_gpio_input(ah, ah->btactive_gpio);
3987
3988         /* Configure the desired GPIO port for TX_FRAME output */
3989         ath9k_hw_cfg_output(ah, ah->wlanactive_gpio,
3990                             AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
3991 }