0b1b88ffa49751eacd49b25894b13eb7363148ab
[linux-2.6.git] / drivers / net / wireless / ath / ath9k / hw.c
1 /*
2  * Copyright (c) 2008-2009 Atheros Communications Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16
17 #include <linux/io.h>
18 #include <asm/unaligned.h>
19
20 #include "hw.h"
21 #include "rc.h"
22 #include "initvals.h"
23
24 #define ATH9K_CLOCK_RATE_CCK            22
25 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
26 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
27
28 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
29 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
30 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
31                               struct ar5416_eeprom_def *pEepData,
32                               u32 reg, u32 value);
33
34 MODULE_AUTHOR("Atheros Communications");
35 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
36 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
37 MODULE_LICENSE("Dual BSD/GPL");
38
39 static int __init ath9k_init(void)
40 {
41         return 0;
42 }
43 module_init(ath9k_init);
44
45 static void __exit ath9k_exit(void)
46 {
47         return;
48 }
49 module_exit(ath9k_exit);
50
51 /********************/
52 /* Helper Functions */
53 /********************/
54
55 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
56 {
57         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
58
59         if (!ah->curchan) /* should really check for CCK instead */
60                 return usecs *ATH9K_CLOCK_RATE_CCK;
61         if (conf->channel->band == IEEE80211_BAND_2GHZ)
62                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
63         return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
64 }
65
66 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
67 {
68         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
69
70         if (conf_is_ht40(conf))
71                 return ath9k_hw_mac_clks(ah, usecs) * 2;
72         else
73                 return ath9k_hw_mac_clks(ah, usecs);
74 }
75
76 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
77 {
78         int i;
79
80         BUG_ON(timeout < AH_TIME_QUANTUM);
81
82         for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
83                 if ((REG_READ(ah, reg) & mask) == val)
84                         return true;
85
86                 udelay(AH_TIME_QUANTUM);
87         }
88
89         ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
90                   "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
91                   timeout, reg, REG_READ(ah, reg), mask, val);
92
93         return false;
94 }
95 EXPORT_SYMBOL(ath9k_hw_wait);
96
97 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
98 {
99         u32 retval;
100         int i;
101
102         for (i = 0, retval = 0; i < n; i++) {
103                 retval = (retval << 1) | (val & 1);
104                 val >>= 1;
105         }
106         return retval;
107 }
108
109 bool ath9k_get_channel_edges(struct ath_hw *ah,
110                              u16 flags, u16 *low,
111                              u16 *high)
112 {
113         struct ath9k_hw_capabilities *pCap = &ah->caps;
114
115         if (flags & CHANNEL_5GHZ) {
116                 *low = pCap->low_5ghz_chan;
117                 *high = pCap->high_5ghz_chan;
118                 return true;
119         }
120         if ((flags & CHANNEL_2GHZ)) {
121                 *low = pCap->low_2ghz_chan;
122                 *high = pCap->high_2ghz_chan;
123                 return true;
124         }
125         return false;
126 }
127
128 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
129                            u8 phy, int kbps,
130                            u32 frameLen, u16 rateix,
131                            bool shortPreamble)
132 {
133         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
134
135         if (kbps == 0)
136                 return 0;
137
138         switch (phy) {
139         case WLAN_RC_PHY_CCK:
140                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
141                 if (shortPreamble)
142                         phyTime >>= 1;
143                 numBits = frameLen << 3;
144                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
145                 break;
146         case WLAN_RC_PHY_OFDM:
147                 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
148                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
149                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
150                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
151                         txTime = OFDM_SIFS_TIME_QUARTER
152                                 + OFDM_PREAMBLE_TIME_QUARTER
153                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
154                 } else if (ah->curchan &&
155                            IS_CHAN_HALF_RATE(ah->curchan)) {
156                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
157                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
158                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
159                         txTime = OFDM_SIFS_TIME_HALF +
160                                 OFDM_PREAMBLE_TIME_HALF
161                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
162                 } else {
163                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
164                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
165                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
166                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
167                                 + (numSymbols * OFDM_SYMBOL_TIME);
168                 }
169                 break;
170         default:
171                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
172                           "Unknown phy %u (rate ix %u)\n", phy, rateix);
173                 txTime = 0;
174                 break;
175         }
176
177         return txTime;
178 }
179 EXPORT_SYMBOL(ath9k_hw_computetxtime);
180
181 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
182                                   struct ath9k_channel *chan,
183                                   struct chan_centers *centers)
184 {
185         int8_t extoff;
186
187         if (!IS_CHAN_HT40(chan)) {
188                 centers->ctl_center = centers->ext_center =
189                         centers->synth_center = chan->channel;
190                 return;
191         }
192
193         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
194             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
195                 centers->synth_center =
196                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
197                 extoff = 1;
198         } else {
199                 centers->synth_center =
200                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
201                 extoff = -1;
202         }
203
204         centers->ctl_center =
205                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
206         /* 25 MHz spacing is supported by hw but not on upper layers */
207         centers->ext_center =
208                 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
209 }
210
211 /******************/
212 /* Chip Revisions */
213 /******************/
214
215 static void ath9k_hw_read_revisions(struct ath_hw *ah)
216 {
217         u32 val;
218
219         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
220
221         if (val == 0xFF) {
222                 val = REG_READ(ah, AR_SREV);
223                 ah->hw_version.macVersion =
224                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
225                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
226                 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
227         } else {
228                 if (!AR_SREV_9100(ah))
229                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
230
231                 ah->hw_version.macRev = val & AR_SREV_REVISION;
232
233                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
234                         ah->is_pciexpress = true;
235         }
236 }
237
238 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
239 {
240         u32 val;
241         int i;
242
243         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
244
245         for (i = 0; i < 8; i++)
246                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
247         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
248         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
249
250         return ath9k_hw_reverse_bits(val, 8);
251 }
252
253 /************************************/
254 /* HW Attach, Detach, Init Routines */
255 /************************************/
256
257 static void ath9k_hw_disablepcie(struct ath_hw *ah)
258 {
259         if (AR_SREV_9100(ah))
260                 return;
261
262         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
263         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
264         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
265         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
266         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
267         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
268         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
269         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
270         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
271
272         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
273 }
274
275 static bool ath9k_hw_chip_test(struct ath_hw *ah)
276 {
277         struct ath_common *common = ath9k_hw_common(ah);
278         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
279         u32 regHold[2];
280         u32 patternData[4] = { 0x55555555,
281                                0xaaaaaaaa,
282                                0x66666666,
283                                0x99999999 };
284         int i, j;
285
286         for (i = 0; i < 2; i++) {
287                 u32 addr = regAddr[i];
288                 u32 wrData, rdData;
289
290                 regHold[i] = REG_READ(ah, addr);
291                 for (j = 0; j < 0x100; j++) {
292                         wrData = (j << 16) | j;
293                         REG_WRITE(ah, addr, wrData);
294                         rdData = REG_READ(ah, addr);
295                         if (rdData != wrData) {
296                                 ath_print(common, ATH_DBG_FATAL,
297                                           "address test failed "
298                                           "addr: 0x%08x - wr:0x%08x != "
299                                           "rd:0x%08x\n",
300                                           addr, wrData, rdData);
301                                 return false;
302                         }
303                 }
304                 for (j = 0; j < 4; j++) {
305                         wrData = patternData[j];
306                         REG_WRITE(ah, addr, wrData);
307                         rdData = REG_READ(ah, addr);
308                         if (wrData != rdData) {
309                                 ath_print(common, ATH_DBG_FATAL,
310                                           "address test failed "
311                                           "addr: 0x%08x - wr:0x%08x != "
312                                           "rd:0x%08x\n",
313                                           addr, wrData, rdData);
314                                 return false;
315                         }
316                 }
317                 REG_WRITE(ah, regAddr[i], regHold[i]);
318         }
319         udelay(100);
320
321         return true;
322 }
323
324 static void ath9k_hw_init_config(struct ath_hw *ah)
325 {
326         int i;
327
328         ah->config.dma_beacon_response_time = 2;
329         ah->config.sw_beacon_response_time = 10;
330         ah->config.additional_swba_backoff = 0;
331         ah->config.ack_6mb = 0x0;
332         ah->config.cwm_ignore_extcca = 0;
333         ah->config.pcie_powersave_enable = 0;
334         ah->config.pcie_clock_req = 0;
335         ah->config.pcie_waen = 0;
336         ah->config.analog_shiftreg = 1;
337         ah->config.ofdm_trig_low = 200;
338         ah->config.ofdm_trig_high = 500;
339         ah->config.cck_trig_high = 200;
340         ah->config.cck_trig_low = 100;
341         ah->config.enable_ani = 1;
342
343         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
344                 ah->config.spurchans[i][0] = AR_NO_SPUR;
345                 ah->config.spurchans[i][1] = AR_NO_SPUR;
346         }
347
348         if (ah->hw_version.devid != AR2427_DEVID_PCIE)
349                 ah->config.ht_enable = 1;
350         else
351                 ah->config.ht_enable = 0;
352
353         ah->config.rx_intr_mitigation = true;
354
355         /*
356          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
357          * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
358          * This means we use it for all AR5416 devices, and the few
359          * minor PCI AR9280 devices out there.
360          *
361          * Serialization is required because these devices do not handle
362          * well the case of two concurrent reads/writes due to the latency
363          * involved. During one read/write another read/write can be issued
364          * on another CPU while the previous read/write may still be working
365          * on our hardware, if we hit this case the hardware poops in a loop.
366          * We prevent this by serializing reads and writes.
367          *
368          * This issue is not present on PCI-Express devices or pre-AR5416
369          * devices (legacy, 802.11abg).
370          */
371         if (num_possible_cpus() > 1)
372                 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
373 }
374 EXPORT_SYMBOL(ath9k_hw_init);
375
376 static void ath9k_hw_init_defaults(struct ath_hw *ah)
377 {
378         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
379
380         regulatory->country_code = CTRY_DEFAULT;
381         regulatory->power_limit = MAX_RATE_POWER;
382         regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
383
384         ah->hw_version.magic = AR5416_MAGIC;
385         ah->hw_version.subvendorid = 0;
386
387         ah->ah_flags = 0;
388         if (ah->hw_version.devid == AR5416_AR9100_DEVID)
389                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
390         if (!AR_SREV_9100(ah))
391                 ah->ah_flags = AH_USE_EEPROM;
392
393         ah->atim_window = 0;
394         ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
395         ah->beacon_interval = 100;
396         ah->enable_32kHz_clock = DONT_USE_32KHZ;
397         ah->slottime = (u32) -1;
398         ah->globaltxtimeout = (u32) -1;
399         ah->power_mode = ATH9K_PM_UNDEFINED;
400 }
401
402 static int ath9k_hw_rf_claim(struct ath_hw *ah)
403 {
404         u32 val;
405
406         REG_WRITE(ah, AR_PHY(0), 0x00000007);
407
408         val = ath9k_hw_get_radiorev(ah);
409         switch (val & AR_RADIO_SREV_MAJOR) {
410         case 0:
411                 val = AR_RAD5133_SREV_MAJOR;
412                 break;
413         case AR_RAD5133_SREV_MAJOR:
414         case AR_RAD5122_SREV_MAJOR:
415         case AR_RAD2133_SREV_MAJOR:
416         case AR_RAD2122_SREV_MAJOR:
417                 break;
418         default:
419                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
420                           "Radio Chip Rev 0x%02X not supported\n",
421                           val & AR_RADIO_SREV_MAJOR);
422                 return -EOPNOTSUPP;
423         }
424
425         ah->hw_version.analog5GhzRev = val;
426
427         return 0;
428 }
429
430 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
431 {
432         struct ath_common *common = ath9k_hw_common(ah);
433         u32 sum;
434         int i;
435         u16 eeval;
436
437         sum = 0;
438         for (i = 0; i < 3; i++) {
439                 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
440                 sum += eeval;
441                 common->macaddr[2 * i] = eeval >> 8;
442                 common->macaddr[2 * i + 1] = eeval & 0xff;
443         }
444         if (sum == 0 || sum == 0xffff * 3)
445                 return -EADDRNOTAVAIL;
446
447         return 0;
448 }
449
450 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
451 {
452         u32 rxgain_type;
453
454         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
455                 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
456
457                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
458                         INIT_INI_ARRAY(&ah->iniModesRxGain,
459                         ar9280Modes_backoff_13db_rxgain_9280_2,
460                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
461                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
462                         INIT_INI_ARRAY(&ah->iniModesRxGain,
463                         ar9280Modes_backoff_23db_rxgain_9280_2,
464                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
465                 else
466                         INIT_INI_ARRAY(&ah->iniModesRxGain,
467                         ar9280Modes_original_rxgain_9280_2,
468                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
469         } else {
470                 INIT_INI_ARRAY(&ah->iniModesRxGain,
471                         ar9280Modes_original_rxgain_9280_2,
472                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
473         }
474 }
475
476 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
477 {
478         u32 txgain_type;
479
480         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
481                 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
482
483                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
484                         INIT_INI_ARRAY(&ah->iniModesTxGain,
485                         ar9280Modes_high_power_tx_gain_9280_2,
486                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
487                 else
488                         INIT_INI_ARRAY(&ah->iniModesTxGain,
489                         ar9280Modes_original_tx_gain_9280_2,
490                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
491         } else {
492                 INIT_INI_ARRAY(&ah->iniModesTxGain,
493                 ar9280Modes_original_tx_gain_9280_2,
494                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
495         }
496 }
497
498 static int ath9k_hw_post_init(struct ath_hw *ah)
499 {
500         int ecode;
501
502         if (!ath9k_hw_chip_test(ah))
503                 return -ENODEV;
504
505         ecode = ath9k_hw_rf_claim(ah);
506         if (ecode != 0)
507                 return ecode;
508
509         ecode = ath9k_hw_eeprom_init(ah);
510         if (ecode != 0)
511                 return ecode;
512
513         ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
514                   "Eeprom VER: %d, REV: %d\n",
515                   ah->eep_ops->get_eeprom_ver(ah),
516                   ah->eep_ops->get_eeprom_rev(ah));
517
518         if (!AR_SREV_9280_10_OR_LATER(ah)) {
519                 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
520                 if (ecode) {
521                         ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
522                                   "Failed allocating banks for "
523                                   "external radio\n");
524                         return ecode;
525                 }
526         }
527
528         if (!AR_SREV_9100(ah)) {
529                 ath9k_hw_ani_setup(ah);
530                 ath9k_hw_ani_init(ah);
531         }
532
533         return 0;
534 }
535
536 static bool ath9k_hw_devid_supported(u16 devid)
537 {
538         switch (devid) {
539         case AR5416_DEVID_PCI:
540         case AR5416_DEVID_PCIE:
541         case AR5416_AR9100_DEVID:
542         case AR9160_DEVID_PCI:
543         case AR9280_DEVID_PCI:
544         case AR9280_DEVID_PCIE:
545         case AR9285_DEVID_PCIE:
546         case AR5416_DEVID_AR9287_PCI:
547         case AR5416_DEVID_AR9287_PCIE:
548         case AR9271_USB:
549         case AR2427_DEVID_PCIE:
550                 return true;
551         default:
552                 break;
553         }
554         return false;
555 }
556
557 static bool ath9k_hw_macversion_supported(u32 macversion)
558 {
559         switch (macversion) {
560         case AR_SREV_VERSION_5416_PCI:
561         case AR_SREV_VERSION_5416_PCIE:
562         case AR_SREV_VERSION_9160:
563         case AR_SREV_VERSION_9100:
564         case AR_SREV_VERSION_9280:
565         case AR_SREV_VERSION_9285:
566         case AR_SREV_VERSION_9287:
567         case AR_SREV_VERSION_9271:
568                 return true;
569         default:
570                 break;
571         }
572         return false;
573 }
574
575 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
576 {
577         if (AR_SREV_9160_10_OR_LATER(ah)) {
578                 if (AR_SREV_9280_10_OR_LATER(ah)) {
579                         ah->iq_caldata.calData = &iq_cal_single_sample;
580                         ah->adcgain_caldata.calData =
581                                 &adc_gain_cal_single_sample;
582                         ah->adcdc_caldata.calData =
583                                 &adc_dc_cal_single_sample;
584                         ah->adcdc_calinitdata.calData =
585                                 &adc_init_dc_cal;
586                 } else {
587                         ah->iq_caldata.calData = &iq_cal_multi_sample;
588                         ah->adcgain_caldata.calData =
589                                 &adc_gain_cal_multi_sample;
590                         ah->adcdc_caldata.calData =
591                                 &adc_dc_cal_multi_sample;
592                         ah->adcdc_calinitdata.calData =
593                                 &adc_init_dc_cal;
594                 }
595                 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
596         }
597 }
598
599 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
600 {
601         if (AR_SREV_9271(ah)) {
602                 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
603                                ARRAY_SIZE(ar9271Modes_9271), 6);
604                 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
605                                ARRAY_SIZE(ar9271Common_9271), 2);
606                 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
607                                ar9271Modes_9271_1_0_only,
608                                ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
609                 return;
610         }
611
612         if (AR_SREV_9287_11_OR_LATER(ah)) {
613                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
614                                 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
615                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
616                                 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
617                 if (ah->config.pcie_clock_req)
618                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
619                         ar9287PciePhy_clkreq_off_L1_9287_1_1,
620                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
621                 else
622                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
623                         ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
624                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
625                                         2);
626         } else if (AR_SREV_9287_10_OR_LATER(ah)) {
627                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
628                                 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
629                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
630                                 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
631
632                 if (ah->config.pcie_clock_req)
633                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
634                         ar9287PciePhy_clkreq_off_L1_9287_1_0,
635                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
636                 else
637                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
638                         ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
639                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
640                                   2);
641         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
642
643
644                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
645                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
646                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
647                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
648
649                 if (ah->config.pcie_clock_req) {
650                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
651                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
652                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
653                 } else {
654                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
655                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
656                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
657                                   2);
658                 }
659         } else if (AR_SREV_9285_10_OR_LATER(ah)) {
660                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
661                                ARRAY_SIZE(ar9285Modes_9285), 6);
662                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
663                                ARRAY_SIZE(ar9285Common_9285), 2);
664
665                 if (ah->config.pcie_clock_req) {
666                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
667                         ar9285PciePhy_clkreq_off_L1_9285,
668                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
669                 } else {
670                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
671                         ar9285PciePhy_clkreq_always_on_L1_9285,
672                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
673                 }
674         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
675                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
676                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
677                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
678                                ARRAY_SIZE(ar9280Common_9280_2), 2);
679
680                 if (ah->config.pcie_clock_req) {
681                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
682                                ar9280PciePhy_clkreq_off_L1_9280,
683                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
684                 } else {
685                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
686                                ar9280PciePhy_clkreq_always_on_L1_9280,
687                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
688                 }
689                 INIT_INI_ARRAY(&ah->iniModesAdditional,
690                                ar9280Modes_fast_clock_9280_2,
691                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
692         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
693                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
694                                ARRAY_SIZE(ar9280Modes_9280), 6);
695                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
696                                ARRAY_SIZE(ar9280Common_9280), 2);
697         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
698                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
699                                ARRAY_SIZE(ar5416Modes_9160), 6);
700                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
701                                ARRAY_SIZE(ar5416Common_9160), 2);
702                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
703                                ARRAY_SIZE(ar5416Bank0_9160), 2);
704                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
705                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
706                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
707                                ARRAY_SIZE(ar5416Bank1_9160), 2);
708                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
709                                ARRAY_SIZE(ar5416Bank2_9160), 2);
710                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
711                                ARRAY_SIZE(ar5416Bank3_9160), 3);
712                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
713                                ARRAY_SIZE(ar5416Bank6_9160), 3);
714                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
715                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
716                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
717                                ARRAY_SIZE(ar5416Bank7_9160), 2);
718                 if (AR_SREV_9160_11(ah)) {
719                         INIT_INI_ARRAY(&ah->iniAddac,
720                                        ar5416Addac_91601_1,
721                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
722                 } else {
723                         INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
724                                        ARRAY_SIZE(ar5416Addac_9160), 2);
725                 }
726         } else if (AR_SREV_9100_OR_LATER(ah)) {
727                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
728                                ARRAY_SIZE(ar5416Modes_9100), 6);
729                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
730                                ARRAY_SIZE(ar5416Common_9100), 2);
731                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
732                                ARRAY_SIZE(ar5416Bank0_9100), 2);
733                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
734                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
735                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
736                                ARRAY_SIZE(ar5416Bank1_9100), 2);
737                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
738                                ARRAY_SIZE(ar5416Bank2_9100), 2);
739                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
740                                ARRAY_SIZE(ar5416Bank3_9100), 3);
741                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
742                                ARRAY_SIZE(ar5416Bank6_9100), 3);
743                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
744                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
745                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
746                                ARRAY_SIZE(ar5416Bank7_9100), 2);
747                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
748                                ARRAY_SIZE(ar5416Addac_9100), 2);
749         } else {
750                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
751                                ARRAY_SIZE(ar5416Modes), 6);
752                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
753                                ARRAY_SIZE(ar5416Common), 2);
754                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
755                                ARRAY_SIZE(ar5416Bank0), 2);
756                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
757                                ARRAY_SIZE(ar5416BB_RfGain), 3);
758                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
759                                ARRAY_SIZE(ar5416Bank1), 2);
760                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
761                                ARRAY_SIZE(ar5416Bank2), 2);
762                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
763                                ARRAY_SIZE(ar5416Bank3), 3);
764                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
765                                ARRAY_SIZE(ar5416Bank6), 3);
766                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
767                                ARRAY_SIZE(ar5416Bank6TPC), 3);
768                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
769                                ARRAY_SIZE(ar5416Bank7), 2);
770                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
771                                ARRAY_SIZE(ar5416Addac), 2);
772         }
773 }
774
775 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
776 {
777         if (AR_SREV_9287_11_OR_LATER(ah))
778                 INIT_INI_ARRAY(&ah->iniModesRxGain,
779                 ar9287Modes_rx_gain_9287_1_1,
780                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
781         else if (AR_SREV_9287_10(ah))
782                 INIT_INI_ARRAY(&ah->iniModesRxGain,
783                 ar9287Modes_rx_gain_9287_1_0,
784                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
785         else if (AR_SREV_9280_20(ah))
786                 ath9k_hw_init_rxgain_ini(ah);
787
788         if (AR_SREV_9287_11_OR_LATER(ah)) {
789                 INIT_INI_ARRAY(&ah->iniModesTxGain,
790                 ar9287Modes_tx_gain_9287_1_1,
791                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
792         } else if (AR_SREV_9287_10(ah)) {
793                 INIT_INI_ARRAY(&ah->iniModesTxGain,
794                 ar9287Modes_tx_gain_9287_1_0,
795                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
796         } else if (AR_SREV_9280_20(ah)) {
797                 ath9k_hw_init_txgain_ini(ah);
798         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
799                 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
800
801                 /* txgain table */
802                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
803                         INIT_INI_ARRAY(&ah->iniModesTxGain,
804                         ar9285Modes_high_power_tx_gain_9285_1_2,
805                         ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
806                 } else {
807                         INIT_INI_ARRAY(&ah->iniModesTxGain,
808                         ar9285Modes_original_tx_gain_9285_1_2,
809                         ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
810                 }
811
812         }
813 }
814
815 static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw *ah)
816 {
817         u32 i, j;
818
819         if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
820             test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
821
822                 /* EEPROM Fixup */
823                 for (i = 0; i < ah->iniModes.ia_rows; i++) {
824                         u32 reg = INI_RA(&ah->iniModes, i, 0);
825
826                         for (j = 1; j < ah->iniModes.ia_columns; j++) {
827                                 u32 val = INI_RA(&ah->iniModes, i, j);
828
829                                 INI_RA(&ah->iniModes, i, j) =
830                                         ath9k_hw_ini_fixup(ah,
831                                                            &ah->eeprom.def,
832                                                            reg, val);
833                         }
834                 }
835         }
836 }
837
838 int ath9k_hw_init(struct ath_hw *ah)
839 {
840         struct ath_common *common = ath9k_hw_common(ah);
841         int r = 0;
842
843         if (!ath9k_hw_devid_supported(ah->hw_version.devid)) {
844                 ath_print(common, ATH_DBG_FATAL,
845                           "Unsupported device ID: 0x%0x\n",
846                           ah->hw_version.devid);
847                 return -EOPNOTSUPP;
848         }
849
850         ath9k_hw_init_defaults(ah);
851         ath9k_hw_init_config(ah);
852
853         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
854                 ath_print(common, ATH_DBG_FATAL,
855                           "Couldn't reset chip\n");
856                 return -EIO;
857         }
858
859         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
860                 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
861                 return -EIO;
862         }
863
864         if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
865                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
866                     (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
867                         ah->config.serialize_regmode =
868                                 SER_REG_MODE_ON;
869                 } else {
870                         ah->config.serialize_regmode =
871                                 SER_REG_MODE_OFF;
872                 }
873         }
874
875         ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
876                 ah->config.serialize_regmode);
877
878         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
879                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
880         else
881                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
882
883         if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
884                 ath_print(common, ATH_DBG_FATAL,
885                           "Mac Chip Rev 0x%02x.%x is not supported by "
886                           "this driver\n", ah->hw_version.macVersion,
887                           ah->hw_version.macRev);
888                 return -EOPNOTSUPP;
889         }
890
891         if (AR_SREV_9100(ah)) {
892                 ah->iq_caldata.calData = &iq_cal_multi_sample;
893                 ah->supp_cals = IQ_MISMATCH_CAL;
894                 ah->is_pciexpress = false;
895         }
896
897         if (AR_SREV_9271(ah))
898                 ah->is_pciexpress = false;
899
900         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
901
902         ath9k_hw_init_cal_settings(ah);
903
904         ah->ani_function = ATH9K_ANI_ALL;
905         if (AR_SREV_9280_10_OR_LATER(ah)) {
906                 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
907                 ah->ath9k_hw_rf_set_freq = &ath9k_hw_ar9280_set_channel;
908                 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_9280_spur_mitigate;
909         } else {
910                 ah->ath9k_hw_rf_set_freq = &ath9k_hw_set_channel;
911                 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_spur_mitigate;
912         }
913
914         ath9k_hw_init_mode_regs(ah);
915
916         if (ah->is_pciexpress)
917                 ath9k_hw_configpcipowersave(ah, 0, 0);
918         else
919                 ath9k_hw_disablepcie(ah);
920
921         /* Support for Japan ch.14 (2484) spread */
922         if (AR_SREV_9287_11_OR_LATER(ah)) {
923                 INIT_INI_ARRAY(&ah->iniCckfirNormal,
924                        ar9287Common_normal_cck_fir_coeff_92871_1,
925                        ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
926                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
927                        ar9287Common_japan_2484_cck_fir_coeff_92871_1,
928                        ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
929         }
930
931         r = ath9k_hw_post_init(ah);
932         if (r)
933                 return r;
934
935         ath9k_hw_init_mode_gain_regs(ah);
936         r = ath9k_hw_fill_cap_info(ah);
937         if (r)
938                 return r;
939
940         ath9k_hw_init_11a_eeprom_fix(ah);
941
942         r = ath9k_hw_init_macaddr(ah);
943         if (r) {
944                 ath_print(common, ATH_DBG_FATAL,
945                           "Failed to initialize MAC address\n");
946                 return r;
947         }
948
949         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
950                 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
951         else
952                 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
953
954         ath9k_init_nfcal_hist_buffer(ah);
955
956         common->state = ATH_HW_INITIALIZED;
957
958         return 0;
959 }
960
961 static void ath9k_hw_init_bb(struct ath_hw *ah,
962                              struct ath9k_channel *chan)
963 {
964         u32 synthDelay;
965
966         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
967         if (IS_CHAN_B(chan))
968                 synthDelay = (4 * synthDelay) / 22;
969         else
970                 synthDelay /= 10;
971
972         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
973
974         udelay(synthDelay + BASE_ACTIVATE_DELAY);
975 }
976
977 static void ath9k_hw_init_qos(struct ath_hw *ah)
978 {
979         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
980         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
981
982         REG_WRITE(ah, AR_QOS_NO_ACK,
983                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
984                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
985                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
986
987         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
988         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
989         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
990         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
991         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
992 }
993
994 static void ath9k_hw_change_target_baud(struct ath_hw *ah, u32 freq, u32 baud)
995 {
996         u32 lcr;
997         u32 baud_divider = freq * 1000 * 1000 / 16 / baud;
998
999         lcr = REG_READ(ah , 0x5100c);
1000         lcr |= 0x80;
1001
1002         REG_WRITE(ah, 0x5100c, lcr);
1003         REG_WRITE(ah, 0x51004, (baud_divider >> 8));
1004         REG_WRITE(ah, 0x51000, (baud_divider & 0xff));
1005
1006         lcr &= ~0x80;
1007         REG_WRITE(ah, 0x5100c, lcr);
1008 }
1009
1010 static void ath9k_hw_init_pll(struct ath_hw *ah,
1011                               struct ath9k_channel *chan)
1012 {
1013         u32 pll;
1014
1015         if (AR_SREV_9100(ah)) {
1016                 if (chan && IS_CHAN_5GHZ(chan))
1017                         pll = 0x1450;
1018                 else
1019                         pll = 0x1458;
1020         } else {
1021                 if (AR_SREV_9280_10_OR_LATER(ah)) {
1022                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1023
1024                         if (chan && IS_CHAN_HALF_RATE(chan))
1025                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1026                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1027                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1028
1029                         if (chan && IS_CHAN_5GHZ(chan)) {
1030                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1031
1032
1033                                 if (AR_SREV_9280_20(ah)) {
1034                                         if (((chan->channel % 20) == 0)
1035                                             || ((chan->channel % 10) == 0))
1036                                                 pll = 0x2850;
1037                                         else
1038                                                 pll = 0x142c;
1039                                 }
1040                         } else {
1041                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1042                         }
1043
1044                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1045
1046                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1047
1048                         if (chan && IS_CHAN_HALF_RATE(chan))
1049                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1050                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1051                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1052
1053                         if (chan && IS_CHAN_5GHZ(chan))
1054                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1055                         else
1056                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1057                 } else {
1058                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1059
1060                         if (chan && IS_CHAN_HALF_RATE(chan))
1061                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1062                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1063                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1064
1065                         if (chan && IS_CHAN_5GHZ(chan))
1066                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
1067                         else
1068                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
1069                 }
1070         }
1071         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1072
1073         /* Switch the core clock for ar9271 to 117Mhz */
1074         if (AR_SREV_9271(ah)) {
1075                 if ((pll == 0x142c) || (pll == 0x2850) ) {
1076                         udelay(500);
1077                         /* set CLKOBS to output AHB clock */
1078                         REG_WRITE(ah, 0x7020, 0xe);
1079                         /*
1080                          * 0x304: 117Mhz, ahb_ratio: 1x1
1081                          * 0x306: 40Mhz, ahb_ratio: 1x1
1082                          */
1083                         REG_WRITE(ah, 0x50040, 0x304);
1084                         /*
1085                          * makes adjustments for the baud dividor to keep the
1086                          * targetted baud rate based on the used core clock.
1087                          */
1088                         ath9k_hw_change_target_baud(ah, AR9271_CORE_CLOCK,
1089                                                     AR9271_TARGET_BAUD_RATE);
1090                 }
1091         }
1092
1093         udelay(RTC_PLL_SETTLE_DELAY);
1094
1095         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1096 }
1097
1098 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1099 {
1100         int rx_chainmask, tx_chainmask;
1101
1102         rx_chainmask = ah->rxchainmask;
1103         tx_chainmask = ah->txchainmask;
1104
1105         switch (rx_chainmask) {
1106         case 0x5:
1107                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1108                             AR_PHY_SWAP_ALT_CHAIN);
1109         case 0x3:
1110                 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
1111                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1112                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1113                         break;
1114                 }
1115         case 0x1:
1116         case 0x2:
1117         case 0x7:
1118                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1119                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1120                 break;
1121         default:
1122                 break;
1123         }
1124
1125         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1126         if (tx_chainmask == 0x5) {
1127                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1128                             AR_PHY_SWAP_ALT_CHAIN);
1129         }
1130         if (AR_SREV_9100(ah))
1131                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1132                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1133 }
1134
1135 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1136                                           enum nl80211_iftype opmode)
1137 {
1138         ah->mask_reg = AR_IMR_TXERR |
1139                 AR_IMR_TXURN |
1140                 AR_IMR_RXERR |
1141                 AR_IMR_RXORN |
1142                 AR_IMR_BCNMISC;
1143
1144         if (ah->config.rx_intr_mitigation)
1145                 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1146         else
1147                 ah->mask_reg |= AR_IMR_RXOK;
1148
1149         ah->mask_reg |= AR_IMR_TXOK;
1150
1151         if (opmode == NL80211_IFTYPE_AP)
1152                 ah->mask_reg |= AR_IMR_MIB;
1153
1154         REG_WRITE(ah, AR_IMR, ah->mask_reg);
1155         REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1156
1157         if (!AR_SREV_9100(ah)) {
1158                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1159                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1160                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1161         }
1162 }
1163
1164 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
1165 {
1166         u32 val = ath9k_hw_mac_to_clks(ah, us);
1167         val = min(val, (u32) 0xFFFF);
1168         REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
1169 }
1170
1171 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1172 {
1173         u32 val = ath9k_hw_mac_to_clks(ah, us);
1174         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
1175         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1176 }
1177
1178 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1179 {
1180         u32 val = ath9k_hw_mac_to_clks(ah, us);
1181         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1182         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
1183 }
1184
1185 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1186 {
1187         if (tu > 0xFFFF) {
1188                 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
1189                           "bad global tx timeout %u\n", tu);
1190                 ah->globaltxtimeout = (u32) -1;
1191                 return false;
1192         } else {
1193                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1194                 ah->globaltxtimeout = tu;
1195                 return true;
1196         }
1197 }
1198
1199 void ath9k_hw_init_global_settings(struct ath_hw *ah)
1200 {
1201         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
1202         int acktimeout;
1203         int slottime;
1204         int sifstime;
1205
1206         ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1207                   ah->misc_mode);
1208
1209         if (ah->misc_mode != 0)
1210                 REG_WRITE(ah, AR_PCU_MISC,
1211                           REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1212
1213         if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
1214                 sifstime = 16;
1215         else
1216                 sifstime = 10;
1217
1218         /* As defined by IEEE 802.11-2007 17.3.8.6 */
1219         slottime = ah->slottime + 3 * ah->coverage_class;
1220         acktimeout = slottime + sifstime;
1221         ath9k_hw_setslottime(ah, slottime);
1222         ath9k_hw_set_ack_timeout(ah, acktimeout);
1223         ath9k_hw_set_cts_timeout(ah, acktimeout);
1224         if (ah->globaltxtimeout != (u32) -1)
1225                 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1226 }
1227 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1228
1229 void ath9k_hw_deinit(struct ath_hw *ah)
1230 {
1231         struct ath_common *common = ath9k_hw_common(ah);
1232
1233         if (common->state <= ATH_HW_INITIALIZED)
1234                 goto free_hw;
1235
1236         if (!AR_SREV_9100(ah))
1237                 ath9k_hw_ani_disable(ah);
1238
1239         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1240
1241 free_hw:
1242         if (!AR_SREV_9280_10_OR_LATER(ah))
1243                 ath9k_hw_rf_free_ext_banks(ah);
1244         kfree(ah);
1245         ah = NULL;
1246 }
1247 EXPORT_SYMBOL(ath9k_hw_deinit);
1248
1249 /*******/
1250 /* INI */
1251 /*******/
1252
1253 static void ath9k_hw_override_ini(struct ath_hw *ah,
1254                                   struct ath9k_channel *chan)
1255 {
1256         u32 val;
1257
1258         if (AR_SREV_9271(ah)) {
1259                 /*
1260                  * Enable spectral scan to solution for issues with stuck
1261                  * beacons on AR9271 1.0. The beacon stuck issue is not seeon on
1262                  * AR9271 1.1
1263                  */
1264                 if (AR_SREV_9271_10(ah)) {
1265                         val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) |
1266                               AR_PHY_SPECTRAL_SCAN_ENABLE;
1267                         REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
1268                 }
1269                 else if (AR_SREV_9271_11(ah))
1270                         /*
1271                          * change AR_PHY_RF_CTL3 setting to fix MAC issue
1272                          * present on AR9271 1.1
1273                          */
1274                         REG_WRITE(ah, AR_PHY_RF_CTL3, 0x3a020001);
1275                 return;
1276         }
1277
1278         /*
1279          * Set the RX_ABORT and RX_DIS and clear if off only after
1280          * RXE is set for MAC. This prevents frames with corrupted
1281          * descriptor status.
1282          */
1283         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1284
1285         if (AR_SREV_9280_10_OR_LATER(ah)) {
1286                 val = REG_READ(ah, AR_PCU_MISC_MODE2) &
1287                                (~AR_PCU_MISC_MODE2_HWWAR1);
1288
1289                 if (AR_SREV_9287_10_OR_LATER(ah))
1290                         val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1291
1292                 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1293         }
1294
1295         if (!AR_SREV_5416_20_OR_LATER(ah) ||
1296             AR_SREV_9280_10_OR_LATER(ah))
1297                 return;
1298         /*
1299          * Disable BB clock gating
1300          * Necessary to avoid issues on AR5416 2.0
1301          */
1302         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1303 }
1304
1305 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1306                               struct ar5416_eeprom_def *pEepData,
1307                               u32 reg, u32 value)
1308 {
1309         struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1310         struct ath_common *common = ath9k_hw_common(ah);
1311
1312         switch (ah->hw_version.devid) {
1313         case AR9280_DEVID_PCI:
1314                 if (reg == 0x7894) {
1315                         ath_print(common, ATH_DBG_EEPROM,
1316                                 "ini VAL: %x  EEPROM: %x\n", value,
1317                                 (pBase->version & 0xff));
1318
1319                         if ((pBase->version & 0xff) > 0x0a) {
1320                                 ath_print(common, ATH_DBG_EEPROM,
1321                                           "PWDCLKIND: %d\n",
1322                                           pBase->pwdclkind);
1323                                 value &= ~AR_AN_TOP2_PWDCLKIND;
1324                                 value |= AR_AN_TOP2_PWDCLKIND &
1325                                         (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1326                         } else {
1327                                 ath_print(common, ATH_DBG_EEPROM,
1328                                           "PWDCLKIND Earlier Rev\n");
1329                         }
1330
1331                         ath_print(common, ATH_DBG_EEPROM,
1332                                   "final ini VAL: %x\n", value);
1333                 }
1334                 break;
1335         }
1336
1337         return value;
1338 }
1339
1340 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1341                               struct ar5416_eeprom_def *pEepData,
1342                               u32 reg, u32 value)
1343 {
1344         if (ah->eep_map == EEP_MAP_4KBITS)
1345                 return value;
1346         else
1347                 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1348 }
1349
1350 static void ath9k_olc_init(struct ath_hw *ah)
1351 {
1352         u32 i;
1353
1354         if (OLC_FOR_AR9287_10_LATER) {
1355                 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
1356                                 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
1357                 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
1358                                 AR9287_AN_TXPC0_TXPCMODE,
1359                                 AR9287_AN_TXPC0_TXPCMODE_S,
1360                                 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
1361                 udelay(100);
1362         } else {
1363                 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1364                         ah->originalGain[i] =
1365                                 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1366                                                 AR_PHY_TX_GAIN);
1367                 ah->PDADCdelta = 0;
1368         }
1369 }
1370
1371 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1372                               struct ath9k_channel *chan)
1373 {
1374         u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1375
1376         if (IS_CHAN_B(chan))
1377                 ctl |= CTL_11B;
1378         else if (IS_CHAN_G(chan))
1379                 ctl |= CTL_11G;
1380         else
1381                 ctl |= CTL_11A;
1382
1383         return ctl;
1384 }
1385
1386 static int ath9k_hw_process_ini(struct ath_hw *ah,
1387                                 struct ath9k_channel *chan)
1388 {
1389         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1390         int i, regWrites = 0;
1391         struct ieee80211_channel *channel = chan->chan;
1392         u32 modesIndex, freqIndex;
1393
1394         switch (chan->chanmode) {
1395         case CHANNEL_A:
1396         case CHANNEL_A_HT20:
1397                 modesIndex = 1;
1398                 freqIndex = 1;
1399                 break;
1400         case CHANNEL_A_HT40PLUS:
1401         case CHANNEL_A_HT40MINUS:
1402                 modesIndex = 2;
1403                 freqIndex = 1;
1404                 break;
1405         case CHANNEL_G:
1406         case CHANNEL_G_HT20:
1407         case CHANNEL_B:
1408                 modesIndex = 4;
1409                 freqIndex = 2;
1410                 break;
1411         case CHANNEL_G_HT40PLUS:
1412         case CHANNEL_G_HT40MINUS:
1413                 modesIndex = 3;
1414                 freqIndex = 2;
1415                 break;
1416
1417         default:
1418                 return -EINVAL;
1419         }
1420
1421         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1422         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1423         ah->eep_ops->set_addac(ah, chan);
1424
1425         if (AR_SREV_5416_22_OR_LATER(ah)) {
1426                 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1427         } else {
1428                 struct ar5416IniArray temp;
1429                 u32 addacSize =
1430                         sizeof(u32) * ah->iniAddac.ia_rows *
1431                         ah->iniAddac.ia_columns;
1432
1433                 memcpy(ah->addac5416_21,
1434                        ah->iniAddac.ia_array, addacSize);
1435
1436                 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1437
1438                 temp.ia_array = ah->addac5416_21;
1439                 temp.ia_columns = ah->iniAddac.ia_columns;
1440                 temp.ia_rows = ah->iniAddac.ia_rows;
1441                 REG_WRITE_ARRAY(&temp, 1, regWrites);
1442         }
1443
1444         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1445
1446         for (i = 0; i < ah->iniModes.ia_rows; i++) {
1447                 u32 reg = INI_RA(&ah->iniModes, i, 0);
1448                 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1449
1450                 REG_WRITE(ah, reg, val);
1451
1452                 if (reg >= 0x7800 && reg < 0x78a0
1453                     && ah->config.analog_shiftreg) {
1454                         udelay(100);
1455                 }
1456
1457                 DO_DELAY(regWrites);
1458         }
1459
1460         if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1461                 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1462
1463         if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1464             AR_SREV_9287_10_OR_LATER(ah))
1465                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1466
1467         for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1468                 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1469                 u32 val = INI_RA(&ah->iniCommon, i, 1);
1470
1471                 REG_WRITE(ah, reg, val);
1472
1473                 if (reg >= 0x7800 && reg < 0x78a0
1474                     && ah->config.analog_shiftreg) {
1475                         udelay(100);
1476                 }
1477
1478                 DO_DELAY(regWrites);
1479         }
1480
1481         ath9k_hw_write_regs(ah, freqIndex, regWrites);
1482
1483         if (AR_SREV_9271_10(ah))
1484                 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
1485                                 modesIndex, regWrites);
1486
1487         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1488                 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1489                                 regWrites);
1490         }
1491
1492         ath9k_hw_override_ini(ah, chan);
1493         ath9k_hw_set_regs(ah, chan);
1494         ath9k_hw_init_chain_masks(ah);
1495
1496         if (OLC_FOR_AR9280_20_LATER)
1497                 ath9k_olc_init(ah);
1498
1499         ah->eep_ops->set_txpower(ah, chan,
1500                                  ath9k_regd_get_ctl(regulatory, chan),
1501                                  channel->max_antenna_gain * 2,
1502                                  channel->max_power * 2,
1503                                  min((u32) MAX_RATE_POWER,
1504                                  (u32) regulatory->power_limit));
1505
1506         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1507                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1508                           "ar5416SetRfRegs failed\n");
1509                 return -EIO;
1510         }
1511
1512         return 0;
1513 }
1514
1515 /****************************************/
1516 /* Reset and Channel Switching Routines */
1517 /****************************************/
1518
1519 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1520 {
1521         u32 rfMode = 0;
1522
1523         if (chan == NULL)
1524                 return;
1525
1526         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1527                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1528
1529         if (!AR_SREV_9280_10_OR_LATER(ah))
1530                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1531                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1532
1533         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1534                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1535
1536         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1537 }
1538
1539 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1540 {
1541         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1542 }
1543
1544 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1545 {
1546         u32 regval;
1547
1548         /*
1549          * set AHB_MODE not to do cacheline prefetches
1550         */
1551         regval = REG_READ(ah, AR_AHB_MODE);
1552         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1553
1554         /*
1555          * let mac dma reads be in 128 byte chunks
1556          */
1557         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1558         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1559
1560         /*
1561          * Restore TX Trigger Level to its pre-reset value.
1562          * The initial value depends on whether aggregation is enabled, and is
1563          * adjusted whenever underruns are detected.
1564          */
1565         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1566
1567         /*
1568          * let mac dma writes be in 128 byte chunks
1569          */
1570         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1571         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1572
1573         /*
1574          * Setup receive FIFO threshold to hold off TX activities
1575          */
1576         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1577
1578         /*
1579          * reduce the number of usable entries in PCU TXBUF to avoid
1580          * wrap around issues.
1581          */
1582         if (AR_SREV_9285(ah)) {
1583                 /* For AR9285 the number of Fifos are reduced to half.
1584                  * So set the usable tx buf size also to half to
1585                  * avoid data/delimiter underruns
1586                  */
1587                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1588                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1589         } else if (!AR_SREV_9271(ah)) {
1590                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1591                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1592         }
1593 }
1594
1595 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1596 {
1597         u32 val;
1598
1599         val = REG_READ(ah, AR_STA_ID1);
1600         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1601         switch (opmode) {
1602         case NL80211_IFTYPE_AP:
1603                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1604                           | AR_STA_ID1_KSRCH_MODE);
1605                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1606                 break;
1607         case NL80211_IFTYPE_ADHOC:
1608         case NL80211_IFTYPE_MESH_POINT:
1609                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1610                           | AR_STA_ID1_KSRCH_MODE);
1611                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1612                 break;
1613         case NL80211_IFTYPE_STATION:
1614         case NL80211_IFTYPE_MONITOR:
1615                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1616                 break;
1617         }
1618 }
1619
1620 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1621                                                  u32 coef_scaled,
1622                                                  u32 *coef_mantissa,
1623                                                  u32 *coef_exponent)
1624 {
1625         u32 coef_exp, coef_man;
1626
1627         for (coef_exp = 31; coef_exp > 0; coef_exp--)
1628                 if ((coef_scaled >> coef_exp) & 0x1)
1629                         break;
1630
1631         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1632
1633         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1634
1635         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1636         *coef_exponent = coef_exp - 16;
1637 }
1638
1639 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1640                                      struct ath9k_channel *chan)
1641 {
1642         u32 coef_scaled, ds_coef_exp, ds_coef_man;
1643         u32 clockMhzScaled = 0x64000000;
1644         struct chan_centers centers;
1645
1646         if (IS_CHAN_HALF_RATE(chan))
1647                 clockMhzScaled = clockMhzScaled >> 1;
1648         else if (IS_CHAN_QUARTER_RATE(chan))
1649                 clockMhzScaled = clockMhzScaled >> 2;
1650
1651         ath9k_hw_get_channel_centers(ah, chan, &centers);
1652         coef_scaled = clockMhzScaled / centers.synth_center;
1653
1654         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1655                                       &ds_coef_exp);
1656
1657         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1658                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1659         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1660                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1661
1662         coef_scaled = (9 * coef_scaled) / 10;
1663
1664         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1665                                       &ds_coef_exp);
1666
1667         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1668                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1669         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1670                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1671 }
1672
1673 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1674 {
1675         u32 rst_flags;
1676         u32 tmpReg;
1677
1678         if (AR_SREV_9100(ah)) {
1679                 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1680                 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1681                 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1682                 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1683                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1684         }
1685
1686         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1687                   AR_RTC_FORCE_WAKE_ON_INT);
1688
1689         if (AR_SREV_9100(ah)) {
1690                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1691                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1692         } else {
1693                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1694                 if (tmpReg &
1695                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1696                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1697                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1698                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1699                 } else {
1700                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1701                 }
1702
1703                 rst_flags = AR_RTC_RC_MAC_WARM;
1704                 if (type == ATH9K_RESET_COLD)
1705                         rst_flags |= AR_RTC_RC_MAC_COLD;
1706         }
1707
1708         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1709         udelay(50);
1710
1711         REG_WRITE(ah, AR_RTC_RC, 0);
1712         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1713                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1714                           "RTC stuck in MAC reset\n");
1715                 return false;
1716         }
1717
1718         if (!AR_SREV_9100(ah))
1719                 REG_WRITE(ah, AR_RC, 0);
1720
1721         if (AR_SREV_9100(ah))
1722                 udelay(50);
1723
1724         return true;
1725 }
1726
1727 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1728 {
1729         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1730                   AR_RTC_FORCE_WAKE_ON_INT);
1731
1732         if (!AR_SREV_9100(ah))
1733                 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1734
1735         REG_WRITE(ah, AR_RTC_RESET, 0);
1736         udelay(2);
1737
1738         if (!AR_SREV_9100(ah))
1739                 REG_WRITE(ah, AR_RC, 0);
1740
1741         REG_WRITE(ah, AR_RTC_RESET, 1);
1742
1743         if (!ath9k_hw_wait(ah,
1744                            AR_RTC_STATUS,
1745                            AR_RTC_STATUS_M,
1746                            AR_RTC_STATUS_ON,
1747                            AH_WAIT_TIMEOUT)) {
1748                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1749                           "RTC not waking up\n");
1750                 return false;
1751         }
1752
1753         ath9k_hw_read_revisions(ah);
1754
1755         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1756 }
1757
1758 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1759 {
1760         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1761                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1762
1763         switch (type) {
1764         case ATH9K_RESET_POWER_ON:
1765                 return ath9k_hw_set_reset_power_on(ah);
1766         case ATH9K_RESET_WARM:
1767         case ATH9K_RESET_COLD:
1768                 return ath9k_hw_set_reset(ah, type);
1769         default:
1770                 return false;
1771         }
1772 }
1773
1774 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
1775 {
1776         u32 phymode;
1777         u32 enableDacFifo = 0;
1778
1779         if (AR_SREV_9285_10_OR_LATER(ah))
1780                 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1781                                          AR_PHY_FC_ENABLE_DAC_FIFO);
1782
1783         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1784                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1785
1786         if (IS_CHAN_HT40(chan)) {
1787                 phymode |= AR_PHY_FC_DYN2040_EN;
1788
1789                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1790                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1791                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1792
1793         }
1794         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1795
1796         ath9k_hw_set11nmac2040(ah);
1797
1798         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1799         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1800 }
1801
1802 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1803                                 struct ath9k_channel *chan)
1804 {
1805         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1806                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1807                         return false;
1808         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1809                 return false;
1810
1811         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1812                 return false;
1813
1814         ah->chip_fullsleep = false;
1815         ath9k_hw_init_pll(ah, chan);
1816         ath9k_hw_set_rfmode(ah, chan);
1817
1818         return true;
1819 }
1820
1821 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1822                                     struct ath9k_channel *chan)
1823 {
1824         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1825         struct ath_common *common = ath9k_hw_common(ah);
1826         struct ieee80211_channel *channel = chan->chan;
1827         u32 synthDelay, qnum;
1828         int r;
1829
1830         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1831                 if (ath9k_hw_numtxpending(ah, qnum)) {
1832                         ath_print(common, ATH_DBG_QUEUE,
1833                                   "Transmit frames pending on "
1834                                   "queue %d\n", qnum);
1835                         return false;
1836                 }
1837         }
1838
1839         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1840         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1841                            AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1842                 ath_print(common, ATH_DBG_FATAL,
1843                           "Could not kill baseband RX\n");
1844                 return false;
1845         }
1846
1847         ath9k_hw_set_regs(ah, chan);
1848
1849         r = ah->ath9k_hw_rf_set_freq(ah, chan);
1850         if (r) {
1851                 ath_print(common, ATH_DBG_FATAL,
1852                           "Failed to set channel\n");
1853                 return false;
1854         }
1855
1856         ah->eep_ops->set_txpower(ah, chan,
1857                              ath9k_regd_get_ctl(regulatory, chan),
1858                              channel->max_antenna_gain * 2,
1859                              channel->max_power * 2,
1860                              min((u32) MAX_RATE_POWER,
1861                              (u32) regulatory->power_limit));
1862
1863         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1864         if (IS_CHAN_B(chan))
1865                 synthDelay = (4 * synthDelay) / 22;
1866         else
1867                 synthDelay /= 10;
1868
1869         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1870
1871         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1872
1873         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1874                 ath9k_hw_set_delta_slope(ah, chan);
1875
1876         ah->ath9k_hw_spur_mitigate_freq(ah, chan);
1877
1878         if (!chan->oneTimeCalsDone)
1879                 chan->oneTimeCalsDone = true;
1880
1881         return true;
1882 }
1883
1884 static void ath9k_enable_rfkill(struct ath_hw *ah)
1885 {
1886         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
1887                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
1888
1889         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
1890                     AR_GPIO_INPUT_MUX2_RFSILENT);
1891
1892         ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1893         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
1894 }
1895
1896 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1897                     bool bChannelChange)
1898 {
1899         struct ath_common *common = ath9k_hw_common(ah);
1900         u32 saveLedState;
1901         struct ath9k_channel *curchan = ah->curchan;
1902         u32 saveDefAntenna;
1903         u32 macStaId1;
1904         u64 tsf = 0;
1905         int i, rx_chainmask, r;
1906
1907         ah->txchainmask = common->tx_chainmask;
1908         ah->rxchainmask = common->rx_chainmask;
1909
1910         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1911                 return -EIO;
1912
1913         if (curchan && !ah->chip_fullsleep)
1914                 ath9k_hw_getnf(ah, curchan);
1915
1916         if (bChannelChange &&
1917             (ah->chip_fullsleep != true) &&
1918             (ah->curchan != NULL) &&
1919             (chan->channel != ah->curchan->channel) &&
1920             ((chan->channelFlags & CHANNEL_ALL) ==
1921              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1922              !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
1923              IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
1924
1925                 if (ath9k_hw_channel_change(ah, chan)) {
1926                         ath9k_hw_loadnf(ah, ah->curchan);
1927                         ath9k_hw_start_nfcal(ah);
1928                         return 0;
1929                 }
1930         }
1931
1932         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1933         if (saveDefAntenna == 0)
1934                 saveDefAntenna = 1;
1935
1936         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1937
1938         /* For chips on which RTC reset is done, save TSF before it gets cleared */
1939         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1940                 tsf = ath9k_hw_gettsf64(ah);
1941
1942         saveLedState = REG_READ(ah, AR_CFG_LED) &
1943                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1944                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1945
1946         ath9k_hw_mark_phy_inactive(ah);
1947
1948         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1949                 REG_WRITE(ah,
1950                           AR9271_RESET_POWER_DOWN_CONTROL,
1951                           AR9271_RADIO_RF_RST);
1952                 udelay(50);
1953         }
1954
1955         if (!ath9k_hw_chip_reset(ah, chan)) {
1956                 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1957                 return -EINVAL;
1958         }
1959
1960         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1961                 ah->htc_reset_init = false;
1962                 REG_WRITE(ah,
1963                           AR9271_RESET_POWER_DOWN_CONTROL,
1964                           AR9271_GATE_MAC_CTL);
1965                 udelay(50);
1966         }
1967
1968         /* Restore TSF */
1969         if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1970                 ath9k_hw_settsf64(ah, tsf);
1971
1972         if (AR_SREV_9280_10_OR_LATER(ah))
1973                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1974
1975         if (AR_SREV_9287_12_OR_LATER(ah)) {
1976                 /* Enable ASYNC FIFO */
1977                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1978                                 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
1979                 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
1980                 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1981                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1982                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1983                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1984         }
1985         r = ath9k_hw_process_ini(ah, chan);
1986         if (r)
1987                 return r;
1988
1989         /* Setup MFP options for CCMP */
1990         if (AR_SREV_9280_20_OR_LATER(ah)) {
1991                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1992                  * frames when constructing CCMP AAD. */
1993                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1994                               0xc7ff);
1995                 ah->sw_mgmt_crypto = false;
1996         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1997                 /* Disable hardware crypto for management frames */
1998                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1999                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2000                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2001                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2002                 ah->sw_mgmt_crypto = true;
2003         } else
2004                 ah->sw_mgmt_crypto = true;
2005
2006         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2007                 ath9k_hw_set_delta_slope(ah, chan);
2008
2009         ah->ath9k_hw_spur_mitigate_freq(ah, chan);
2010         ah->eep_ops->set_board_values(ah, chan);
2011
2012         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
2013         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
2014                   | macStaId1
2015                   | AR_STA_ID1_RTS_USE_DEF
2016                   | (ah->config.
2017                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2018                   | ah->sta_id1_defaults);
2019         ath9k_hw_set_operating_mode(ah, ah->opmode);
2020
2021         ath_hw_setbssidmask(common);
2022
2023         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2024
2025         ath9k_hw_write_associd(ah);
2026
2027         REG_WRITE(ah, AR_ISR, ~0);
2028
2029         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2030
2031         r = ah->ath9k_hw_rf_set_freq(ah, chan);
2032         if (r)
2033                 return r;
2034
2035         for (i = 0; i < AR_NUM_DCU; i++)
2036                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2037
2038         ah->intr_txqs = 0;
2039         for (i = 0; i < ah->caps.total_queues; i++)
2040                 ath9k_hw_resettxqueue(ah, i);
2041
2042         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2043         ath9k_hw_init_qos(ah);
2044
2045         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2046                 ath9k_enable_rfkill(ah);
2047
2048         ath9k_hw_init_global_settings(ah);
2049
2050         if (AR_SREV_9287_12_OR_LATER(ah)) {
2051                 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2052                           AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2053                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2054                           AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2055                 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2056                           AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2057
2058                 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2059                 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2060
2061                 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2062                             AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2063                 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2064                               AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2065         }
2066         if (AR_SREV_9287_12_OR_LATER(ah)) {
2067                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2068                                 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2069         }
2070
2071         REG_WRITE(ah, AR_STA_ID1,
2072                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2073
2074         ath9k_hw_set_dma(ah);
2075
2076         REG_WRITE(ah, AR_OBS, 8);
2077
2078         if (ah->config.rx_intr_mitigation) {
2079                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2080                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2081         }
2082
2083         ath9k_hw_init_bb(ah, chan);
2084
2085         if (!ath9k_hw_init_cal(ah, chan))
2086                 return -EIO;
2087
2088         rx_chainmask = ah->rxchainmask;
2089         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2090                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2091                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2092         }
2093
2094         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2095
2096         /*
2097          * For big endian systems turn on swapping for descriptors
2098          */
2099         if (AR_SREV_9100(ah)) {
2100                 u32 mask;
2101                 mask = REG_READ(ah, AR_CFG);
2102                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2103                         ath_print(common, ATH_DBG_RESET,
2104                                 "CFG Byte Swap Set 0x%x\n", mask);
2105                 } else {
2106                         mask =
2107                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2108                         REG_WRITE(ah, AR_CFG, mask);
2109                         ath_print(common, ATH_DBG_RESET,
2110                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2111                 }
2112         } else {
2113                 /* Configure AR9271 target WLAN */
2114                 if (AR_SREV_9271(ah))
2115                         REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
2116 #ifdef __BIG_ENDIAN
2117                 else
2118                         REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2119 #endif
2120         }
2121
2122         if (ah->btcoex_hw.enabled)
2123                 ath9k_hw_btcoex_enable(ah);
2124
2125         return 0;
2126 }
2127 EXPORT_SYMBOL(ath9k_hw_reset);
2128
2129 /************************/
2130 /* Key Cache Management */
2131 /************************/
2132
2133 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2134 {
2135         u32 keyType;
2136
2137         if (entry >= ah->caps.keycache_size) {
2138                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2139                           "keychache entry %u out of range\n", entry);
2140                 return false;
2141         }
2142
2143         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2144
2145         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2146         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2147         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2148         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2149         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2150         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2151         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2152         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2153
2154         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2155                 u16 micentry = entry + 64;
2156
2157                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2158                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2159                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2160                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2161
2162         }
2163
2164         return true;
2165 }
2166 EXPORT_SYMBOL(ath9k_hw_keyreset);
2167
2168 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2169 {
2170         u32 macHi, macLo;
2171
2172         if (entry >= ah->caps.keycache_size) {
2173                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2174                           "keychache entry %u out of range\n", entry);
2175                 return false;
2176         }
2177
2178         if (mac != NULL) {
2179                 macHi = (mac[5] << 8) | mac[4];
2180                 macLo = (mac[3] << 24) |
2181                         (mac[2] << 16) |
2182                         (mac[1] << 8) |
2183                         mac[0];
2184                 macLo >>= 1;
2185                 macLo |= (macHi & 1) << 31;
2186                 macHi >>= 1;
2187         } else {
2188                 macLo = macHi = 0;
2189         }
2190         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2191         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2192
2193         return true;
2194 }
2195 EXPORT_SYMBOL(ath9k_hw_keysetmac);
2196
2197 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2198                                  const struct ath9k_keyval *k,
2199                                  const u8 *mac)
2200 {
2201         const struct ath9k_hw_capabilities *pCap = &ah->caps;
2202         struct ath_common *common = ath9k_hw_common(ah);
2203         u32 key0, key1, key2, key3, key4;
2204         u32 keyType;
2205
2206         if (entry >= pCap->keycache_size) {
2207                 ath_print(common, ATH_DBG_FATAL,
2208                           "keycache entry %u out of range\n", entry);
2209                 return false;
2210         }
2211
2212         switch (k->kv_type) {
2213         case ATH9K_CIPHER_AES_OCB:
2214                 keyType = AR_KEYTABLE_TYPE_AES;
2215                 break;
2216         case ATH9K_CIPHER_AES_CCM:
2217                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2218                         ath_print(common, ATH_DBG_ANY,
2219                                   "AES-CCM not supported by mac rev 0x%x\n",
2220                                   ah->hw_version.macRev);
2221                         return false;
2222                 }
2223                 keyType = AR_KEYTABLE_TYPE_CCM;
2224                 break;
2225         case ATH9K_CIPHER_TKIP:
2226                 keyType = AR_KEYTABLE_TYPE_TKIP;
2227                 if (ATH9K_IS_MIC_ENABLED(ah)
2228                     && entry + 64 >= pCap->keycache_size) {
2229                         ath_print(common, ATH_DBG_ANY,
2230                                   "entry %u inappropriate for TKIP\n", entry);
2231                         return false;
2232                 }
2233                 break;
2234         case ATH9K_CIPHER_WEP:
2235                 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2236                         ath_print(common, ATH_DBG_ANY,
2237                                   "WEP key length %u too small\n", k->kv_len);
2238                         return false;
2239                 }
2240                 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
2241                         keyType = AR_KEYTABLE_TYPE_40;
2242                 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2243                         keyType = AR_KEYTABLE_TYPE_104;
2244                 else
2245                         keyType = AR_KEYTABLE_TYPE_128;
2246                 break;
2247         case ATH9K_CIPHER_CLR:
2248                 keyType = AR_KEYTABLE_TYPE_CLR;
2249                 break;
2250         default:
2251                 ath_print(common, ATH_DBG_FATAL,
2252                           "cipher %u not supported\n", k->kv_type);
2253                 return false;
2254         }
2255
2256         key0 = get_unaligned_le32(k->kv_val + 0);
2257         key1 = get_unaligned_le16(k->kv_val + 4);
2258         key2 = get_unaligned_le32(k->kv_val + 6);
2259         key3 = get_unaligned_le16(k->kv_val + 10);
2260         key4 = get_unaligned_le32(k->kv_val + 12);
2261         if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2262                 key4 &= 0xff;
2263
2264         /*
2265          * Note: Key cache registers access special memory area that requires
2266          * two 32-bit writes to actually update the values in the internal
2267          * memory. Consequently, the exact order and pairs used here must be
2268          * maintained.
2269          */
2270
2271         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2272                 u16 micentry = entry + 64;
2273
2274                 /*
2275                  * Write inverted key[47:0] first to avoid Michael MIC errors
2276                  * on frames that could be sent or received at the same time.
2277                  * The correct key will be written in the end once everything
2278                  * else is ready.
2279                  */
2280                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2281                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2282
2283                 /* Write key[95:48] */
2284                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2285                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2286
2287                 /* Write key[127:96] and key type */
2288                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2289                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2290
2291                 /* Write MAC address for the entry */
2292                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2293
2294                 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2295                         /*
2296                          * TKIP uses two key cache entries:
2297                          * Michael MIC TX/RX keys in the same key cache entry
2298                          * (idx = main index + 64):
2299                          * key0 [31:0] = RX key [31:0]
2300                          * key1 [15:0] = TX key [31:16]
2301                          * key1 [31:16] = reserved
2302                          * key2 [31:0] = RX key [63:32]
2303                          * key3 [15:0] = TX key [15:0]
2304                          * key3 [31:16] = reserved
2305                          * key4 [31:0] = TX key [63:32]
2306                          */
2307                         u32 mic0, mic1, mic2, mic3, mic4;
2308
2309                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2310                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2311                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2312                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2313                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
2314
2315                         /* Write RX[31:0] and TX[31:16] */
2316                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2317                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2318
2319                         /* Write RX[63:32] and TX[15:0] */
2320                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2321                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2322
2323                         /* Write TX[63:32] and keyType(reserved) */
2324                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2325                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2326                                   AR_KEYTABLE_TYPE_CLR);
2327
2328                 } else {
2329                         /*
2330                          * TKIP uses four key cache entries (two for group
2331                          * keys):
2332                          * Michael MIC TX/RX keys are in different key cache
2333                          * entries (idx = main index + 64 for TX and
2334                          * main index + 32 + 96 for RX):
2335                          * key0 [31:0] = TX/RX MIC key [31:0]
2336                          * key1 [31:0] = reserved
2337                          * key2 [31:0] = TX/RX MIC key [63:32]
2338                          * key3 [31:0] = reserved
2339                          * key4 [31:0] = reserved
2340                          *
2341                          * Upper layer code will call this function separately
2342                          * for TX and RX keys when these registers offsets are
2343                          * used.
2344                          */
2345                         u32 mic0, mic2;
2346
2347                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2348                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2349
2350                         /* Write MIC key[31:0] */
2351                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2352                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2353
2354                         /* Write MIC key[63:32] */
2355                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2356                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2357
2358                         /* Write TX[63:32] and keyType(reserved) */
2359                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2360                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2361                                   AR_KEYTABLE_TYPE_CLR);
2362                 }
2363
2364                 /* MAC address registers are reserved for the MIC entry */
2365                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2366                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2367
2368                 /*
2369                  * Write the correct (un-inverted) key[47:0] last to enable
2370                  * TKIP now that all other registers are set with correct
2371                  * values.
2372                  */
2373                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2374                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2375         } else {
2376                 /* Write key[47:0] */
2377                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2378                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2379
2380                 /* Write key[95:48] */
2381                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2382                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2383
2384                 /* Write key[127:96] and key type */
2385                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2386                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2387
2388                 /* Write MAC address for the entry */
2389                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2390         }
2391
2392         return true;
2393 }
2394 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
2395
2396 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2397 {
2398         if (entry < ah->caps.keycache_size) {
2399                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2400                 if (val & AR_KEYTABLE_VALID)
2401                         return true;
2402         }
2403         return false;
2404 }
2405 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
2406
2407 /******************************/
2408 /* Power Management (Chipset) */
2409 /******************************/
2410
2411 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2412 {
2413         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2414         if (setChip) {
2415                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2416                             AR_RTC_FORCE_WAKE_EN);
2417                 if (!AR_SREV_9100(ah))
2418                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2419
2420                 if(!AR_SREV_5416(ah))
2421                         REG_CLR_BIT(ah, (AR_RTC_RESET),
2422                                     AR_RTC_RESET_EN);
2423         }
2424 }
2425
2426 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2427 {
2428         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2429         if (setChip) {
2430                 struct ath9k_hw_capabilities *pCap = &ah->caps;
2431
2432                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2433                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2434                                   AR_RTC_FORCE_WAKE_ON_INT);
2435                 } else {
2436                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2437                                     AR_RTC_FORCE_WAKE_EN);
2438                 }
2439         }
2440 }
2441
2442 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2443 {
2444         u32 val;
2445         int i;
2446
2447         if (setChip) {
2448                 if ((REG_READ(ah, AR_RTC_STATUS) &
2449                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2450                         if (ath9k_hw_set_reset_reg(ah,
2451                                            ATH9K_RESET_POWER_ON) != true) {
2452                                 return false;
2453                         }
2454                         ath9k_hw_init_pll(ah, NULL);
2455                 }
2456                 if (AR_SREV_9100(ah))
2457                         REG_SET_BIT(ah, AR_RTC_RESET,
2458                                     AR_RTC_RESET_EN);
2459
2460                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2461                             AR_RTC_FORCE_WAKE_EN);
2462                 udelay(50);
2463
2464                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2465                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2466                         if (val == AR_RTC_STATUS_ON)
2467                                 break;
2468                         udelay(50);
2469                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2470                                     AR_RTC_FORCE_WAKE_EN);
2471                 }
2472                 if (i == 0) {
2473                         ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2474                                   "Failed to wakeup in %uus\n",
2475                                   POWER_UP_TIME / 20);
2476                         return false;
2477                 }
2478         }
2479
2480         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2481
2482         return true;
2483 }
2484
2485 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2486 {
2487         struct ath_common *common = ath9k_hw_common(ah);
2488         int status = true, setChip = true;
2489         static const char *modes[] = {
2490                 "AWAKE",
2491                 "FULL-SLEEP",
2492                 "NETWORK SLEEP",
2493                 "UNDEFINED"
2494         };
2495
2496         if (ah->power_mode == mode)
2497                 return status;
2498
2499         ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
2500                   modes[ah->power_mode], modes[mode]);
2501
2502         switch (mode) {
2503         case ATH9K_PM_AWAKE:
2504                 status = ath9k_hw_set_power_awake(ah, setChip);
2505                 break;
2506         case ATH9K_PM_FULL_SLEEP:
2507                 ath9k_set_power_sleep(ah, setChip);
2508                 ah->chip_fullsleep = true;
2509                 break;
2510         case ATH9K_PM_NETWORK_SLEEP:
2511                 ath9k_set_power_network_sleep(ah, setChip);
2512                 break;
2513         default:
2514                 ath_print(common, ATH_DBG_FATAL,
2515                           "Unknown power mode %u\n", mode);
2516                 return false;
2517         }
2518         ah->power_mode = mode;
2519
2520         return status;
2521 }
2522 EXPORT_SYMBOL(ath9k_hw_setpower);
2523
2524 /*
2525  * Helper for ASPM support.
2526  *
2527  * Disable PLL when in L0s as well as receiver clock when in L1.
2528  * This power saving option must be enabled through the SerDes.
2529  *
2530  * Programming the SerDes must go through the same 288 bit serial shift
2531  * register as the other analog registers.  Hence the 9 writes.
2532  */
2533 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
2534 {
2535         u8 i;
2536         u32 val;
2537
2538         if (ah->is_pciexpress != true)
2539                 return;
2540
2541         /* Do not touch SerDes registers */
2542         if (ah->config.pcie_powersave_enable == 2)
2543                 return;
2544
2545         /* Nothing to do on restore for 11N */
2546         if (!restore) {
2547                 if (AR_SREV_9280_20_OR_LATER(ah)) {
2548                         /*
2549                          * AR9280 2.0 or later chips use SerDes values from the
2550                          * initvals.h initialized depending on chipset during
2551                          * ath9k_hw_init()
2552                          */
2553                         for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2554                                 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2555                                           INI_RA(&ah->iniPcieSerdes, i, 1));
2556                         }
2557                 } else if (AR_SREV_9280(ah) &&
2558                            (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2559                         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2560                         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2561
2562                         /* RX shut off when elecidle is asserted */
2563                         REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2564                         REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2565                         REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2566
2567                         /* Shut off CLKREQ active in L1 */
2568                         if (ah->config.pcie_clock_req)
2569                                 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2570                         else
2571                                 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2572
2573                         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2574                         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2575                         REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2576
2577                         /* Load the new settings */
2578                         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2579
2580                 } else {
2581                         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2582                         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2583
2584                         /* RX shut off when elecidle is asserted */
2585                         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2586                         REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2587                         REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2588
2589                         /*
2590                          * Ignore ah->ah_config.pcie_clock_req setting for
2591                          * pre-AR9280 11n
2592                          */
2593                         REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2594
2595                         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2596                         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2597                         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2598
2599                         /* Load the new settings */
2600                         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2601                 }
2602
2603                 udelay(1000);
2604
2605                 /* set bit 19 to allow forcing of pcie core into L1 state */
2606                 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2607
2608                 /* Several PCIe massages to ensure proper behaviour */
2609                 if (ah->config.pcie_waen) {
2610                         val = ah->config.pcie_waen;
2611                         if (!power_off)
2612                                 val &= (~AR_WA_D3_L1_DISABLE);
2613                 } else {
2614                         if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2615                             AR_SREV_9287(ah)) {
2616                                 val = AR9285_WA_DEFAULT;
2617                                 if (!power_off)
2618                                         val &= (~AR_WA_D3_L1_DISABLE);
2619                         } else if (AR_SREV_9280(ah)) {
2620                                 /*
2621                                  * On AR9280 chips bit 22 of 0x4004 needs to be
2622                                  * set otherwise card may disappear.
2623                                  */
2624                                 val = AR9280_WA_DEFAULT;
2625                                 if (!power_off)
2626                                         val &= (~AR_WA_D3_L1_DISABLE);
2627                         } else
2628                                 val = AR_WA_DEFAULT;
2629                 }
2630
2631                 REG_WRITE(ah, AR_WA, val);
2632         }
2633
2634         if (power_off) {
2635                 /*
2636                  * Set PCIe workaround bits
2637                  * bit 14 in WA register (disable L1) should only
2638                  * be set when device enters D3 and be cleared
2639                  * when device comes back to D0.
2640                  */
2641                 if (ah->config.pcie_waen) {
2642                         if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
2643                                 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2644                 } else {
2645                         if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2646                               AR_SREV_9287(ah)) &&
2647                              (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
2648                             (AR_SREV_9280(ah) &&
2649                              (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
2650                                 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2651                         }
2652                 }
2653         }
2654 }
2655 EXPORT_SYMBOL(ath9k_hw_configpcipowersave);
2656
2657 /**********************/
2658 /* Interrupt Handling */
2659 /**********************/
2660
2661 bool ath9k_hw_intrpend(struct ath_hw *ah)
2662 {
2663         u32 host_isr;
2664
2665         if (AR_SREV_9100(ah))
2666                 return true;
2667
2668         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2669         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2670                 return true;
2671
2672         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2673         if ((host_isr & AR_INTR_SYNC_DEFAULT)
2674             && (host_isr != AR_INTR_SPURIOUS))
2675                 return true;
2676
2677         return false;
2678 }
2679 EXPORT_SYMBOL(ath9k_hw_intrpend);
2680
2681 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2682 {
2683         u32 isr = 0;
2684         u32 mask2 = 0;
2685         struct ath9k_hw_capabilities *pCap = &ah->caps;
2686         u32 sync_cause = 0;
2687         bool fatal_int = false;
2688         struct ath_common *common = ath9k_hw_common(ah);
2689
2690         if (!AR_SREV_9100(ah)) {
2691                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2692                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2693                             == AR_RTC_STATUS_ON) {
2694                                 isr = REG_READ(ah, AR_ISR);
2695                         }
2696                 }
2697
2698                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2699                         AR_INTR_SYNC_DEFAULT;
2700
2701                 *masked = 0;
2702
2703                 if (!isr && !sync_cause)
2704                         return false;
2705         } else {
2706                 *masked = 0;
2707                 isr = REG_READ(ah, AR_ISR);
2708         }
2709
2710         if (isr) {
2711                 if (isr & AR_ISR_BCNMISC) {
2712                         u32 isr2;
2713                         isr2 = REG_READ(ah, AR_ISR_S2);
2714                         if (isr2 & AR_ISR_S2_TIM)
2715                                 mask2 |= ATH9K_INT_TIM;
2716                         if (isr2 & AR_ISR_S2_DTIM)
2717                                 mask2 |= ATH9K_INT_DTIM;
2718                         if (isr2 & AR_ISR_S2_DTIMSYNC)
2719                                 mask2 |= ATH9K_INT_DTIMSYNC;
2720                         if (isr2 & (AR_ISR_S2_CABEND))
2721                                 mask2 |= ATH9K_INT_CABEND;
2722                         if (isr2 & AR_ISR_S2_GTT)
2723                                 mask2 |= ATH9K_INT_GTT;
2724                         if (isr2 & AR_ISR_S2_CST)
2725                                 mask2 |= ATH9K_INT_CST;
2726                         if (isr2 & AR_ISR_S2_TSFOOR)
2727                                 mask2 |= ATH9K_INT_TSFOOR;
2728                 }
2729
2730                 isr = REG_READ(ah, AR_ISR_RAC);
2731                 if (isr == 0xffffffff) {
2732                         *masked = 0;
2733                         return false;
2734                 }
2735
2736                 *masked = isr & ATH9K_INT_COMMON;
2737
2738                 if (ah->config.rx_intr_mitigation) {
2739                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2740                                 *masked |= ATH9K_INT_RX;
2741                 }
2742
2743                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2744                         *masked |= ATH9K_INT_RX;
2745                 if (isr &
2746                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2747                      AR_ISR_TXEOL)) {
2748                         u32 s0_s, s1_s;
2749
2750                         *masked |= ATH9K_INT_TX;
2751
2752                         s0_s = REG_READ(ah, AR_ISR_S0_S);
2753                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2754                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2755
2756                         s1_s = REG_READ(ah, AR_ISR_S1_S);
2757                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2758                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2759                 }
2760
2761                 if (isr & AR_ISR_RXORN) {
2762                         ath_print(common, ATH_DBG_INTERRUPT,
2763                                   "receive FIFO overrun interrupt\n");
2764                 }
2765
2766                 if (!AR_SREV_9100(ah)) {
2767                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2768                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2769                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
2770                                         *masked |= ATH9K_INT_TIM_TIMER;
2771                         }
2772                 }
2773
2774                 *masked |= mask2;
2775         }
2776
2777         if (AR_SREV_9100(ah))
2778                 return true;
2779
2780         if (isr & AR_ISR_GENTMR) {
2781                 u32 s5_s;
2782
2783                 s5_s = REG_READ(ah, AR_ISR_S5_S);
2784                 if (isr & AR_ISR_GENTMR) {
2785                         ah->intr_gen_timer_trigger =
2786                                 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
2787
2788                         ah->intr_gen_timer_thresh =
2789                                 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
2790
2791                         if (ah->intr_gen_timer_trigger)
2792                                 *masked |= ATH9K_INT_GENTIMER;
2793
2794                 }
2795         }
2796
2797         if (sync_cause) {
2798                 fatal_int =
2799                         (sync_cause &
2800                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2801                         ? true : false;
2802
2803                 if (fatal_int) {
2804                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2805                                 ath_print(common, ATH_DBG_ANY,
2806                                           "received PCI FATAL interrupt\n");
2807                         }
2808                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2809                                 ath_print(common, ATH_DBG_ANY,
2810                                           "received PCI PERR interrupt\n");
2811                         }
2812                         *masked |= ATH9K_INT_FATAL;
2813                 }
2814                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2815                         ath_print(common, ATH_DBG_INTERRUPT,
2816                                   "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2817                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2818                         REG_WRITE(ah, AR_RC, 0);
2819                         *masked |= ATH9K_INT_FATAL;
2820                 }
2821                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2822                         ath_print(common, ATH_DBG_INTERRUPT,
2823                                   "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2824                 }
2825
2826                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2827                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2828         }
2829
2830         return true;
2831 }
2832 EXPORT_SYMBOL(ath9k_hw_getisr);
2833
2834 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
2835 {
2836         u32 omask = ah->mask_reg;
2837         u32 mask, mask2;
2838         struct ath9k_hw_capabilities *pCap = &ah->caps;
2839         struct ath_common *common = ath9k_hw_common(ah);
2840
2841         ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2842
2843         if (omask & ATH9K_INT_GLOBAL) {
2844                 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
2845                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2846                 (void) REG_READ(ah, AR_IER);
2847                 if (!AR_SREV_9100(ah)) {
2848                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2849                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2850
2851                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2852                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2853                 }
2854         }
2855
2856         mask = ints & ATH9K_INT_COMMON;
2857         mask2 = 0;
2858
2859         if (ints & ATH9K_INT_TX) {
2860                 if (ah->txok_interrupt_mask)
2861                         mask |= AR_IMR_TXOK;
2862                 if (ah->txdesc_interrupt_mask)
2863                         mask |= AR_IMR_TXDESC;
2864                 if (ah->txerr_interrupt_mask)
2865                         mask |= AR_IMR_TXERR;
2866                 if (ah->txeol_interrupt_mask)
2867                         mask |= AR_IMR_TXEOL;
2868         }
2869         if (ints & ATH9K_INT_RX) {
2870                 mask |= AR_IMR_RXERR;
2871                 if (ah->config.rx_intr_mitigation)
2872                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2873                 else
2874                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
2875                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
2876                         mask |= AR_IMR_GENTMR;
2877         }
2878
2879         if (ints & (ATH9K_INT_BMISC)) {
2880                 mask |= AR_IMR_BCNMISC;
2881                 if (ints & ATH9K_INT_TIM)
2882                         mask2 |= AR_IMR_S2_TIM;
2883                 if (ints & ATH9K_INT_DTIM)
2884                         mask2 |= AR_IMR_S2_DTIM;
2885                 if (ints & ATH9K_INT_DTIMSYNC)
2886                         mask2 |= AR_IMR_S2_DTIMSYNC;
2887                 if (ints & ATH9K_INT_CABEND)
2888                         mask2 |= AR_IMR_S2_CABEND;
2889                 if (ints & ATH9K_INT_TSFOOR)
2890                         mask2 |= AR_IMR_S2_TSFOOR;
2891         }
2892
2893         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2894                 mask |= AR_IMR_BCNMISC;
2895                 if (ints & ATH9K_INT_GTT)
2896                         mask2 |= AR_IMR_S2_GTT;
2897                 if (ints & ATH9K_INT_CST)
2898                         mask2 |= AR_IMR_S2_CST;
2899         }
2900
2901         ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
2902         REG_WRITE(ah, AR_IMR, mask);
2903         mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
2904                                            AR_IMR_S2_DTIM |
2905                                            AR_IMR_S2_DTIMSYNC |
2906                                            AR_IMR_S2_CABEND |
2907                                            AR_IMR_S2_CABTO |
2908                                            AR_IMR_S2_TSFOOR |
2909                                            AR_IMR_S2_GTT | AR_IMR_S2_CST);
2910         REG_WRITE(ah, AR_IMR_S2, mask | mask2);
2911         ah->mask_reg = ints;
2912
2913         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2914                 if (ints & ATH9K_INT_TIM_TIMER)
2915                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2916                 else
2917                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2918         }
2919
2920         if (ints & ATH9K_INT_GLOBAL) {
2921                 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
2922                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
2923                 if (!AR_SREV_9100(ah)) {
2924                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
2925                                   AR_INTR_MAC_IRQ);
2926                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
2927
2928
2929                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
2930                                   AR_INTR_SYNC_DEFAULT);
2931                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
2932                                   AR_INTR_SYNC_DEFAULT);
2933                 }
2934                 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
2935                           REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
2936         }
2937
2938         return omask;
2939 }
2940 EXPORT_SYMBOL(ath9k_hw_set_interrupts);
2941
2942 /*******************/
2943 /* Beacon Handling */
2944 /*******************/
2945
2946 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2947 {
2948         int flags = 0;
2949
2950         ah->beacon_interval = beacon_period;
2951
2952         switch (ah->opmode) {
2953         case NL80211_IFTYPE_STATION:
2954         case NL80211_IFTYPE_MONITOR:
2955                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2956                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
2957                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
2958                 flags |= AR_TBTT_TIMER_EN;
2959                 break;
2960         case NL80211_IFTYPE_ADHOC:
2961         case NL80211_IFTYPE_MESH_POINT:
2962                 REG_SET_BIT(ah, AR_TXCFG,
2963                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2964                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
2965                           TU_TO_USEC(next_beacon +
2966                                      (ah->atim_window ? ah->
2967                                       atim_window : 1)));
2968                 flags |= AR_NDP_TIMER_EN;
2969         case NL80211_IFTYPE_AP:
2970                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2971                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
2972                           TU_TO_USEC(next_beacon -
2973                                      ah->config.
2974                                      dma_beacon_response_time));
2975                 REG_WRITE(ah, AR_NEXT_SWBA,
2976                           TU_TO_USEC(next_beacon -
2977                                      ah->config.
2978                                      sw_beacon_response_time));
2979                 flags |=
2980                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2981                 break;
2982         default:
2983                 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
2984                           "%s: unsupported opmode: %d\n",
2985                           __func__, ah->opmode);
2986                 return;
2987                 break;
2988         }
2989
2990         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
2991         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
2992         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
2993         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
2994
2995         beacon_period &= ~ATH9K_BEACON_ENA;
2996         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
2997                 ath9k_hw_reset_tsf(ah);
2998         }
2999
3000         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3001 }
3002 EXPORT_SYMBOL(ath9k_hw_beaconinit);
3003
3004 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3005                                     const struct ath9k_beacon_state *bs)
3006 {
3007         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3008         struct ath9k_hw_capabilities *pCap = &ah->caps;
3009         struct ath_common *common = ath9k_hw_common(ah);
3010
3011         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3012
3013         REG_WRITE(ah, AR_BEACON_PERIOD,
3014                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3015         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3016                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3017
3018         REG_RMW_FIELD(ah, AR_RSSI_THR,
3019                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3020
3021         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3022
3023         if (bs->bs_sleepduration > beaconintval)
3024                 beaconintval = bs->bs_sleepduration;
3025
3026         dtimperiod = bs->bs_dtimperiod;
3027         if (bs->bs_sleepduration > dtimperiod)
3028                 dtimperiod = bs->bs_sleepduration;
3029
3030         if (beaconintval == dtimperiod)
3031                 nextTbtt = bs->bs_nextdtim;
3032         else
3033                 nextTbtt = bs->bs_nexttbtt;
3034
3035         ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3036         ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3037         ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3038         ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3039
3040         REG_WRITE(ah, AR_NEXT_DTIM,
3041                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3042         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3043
3044         REG_WRITE(ah, AR_SLEEP1,
3045                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3046                   | AR_SLEEP1_ASSUME_DTIM);
3047
3048         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3049                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3050         else
3051                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3052
3053         REG_WRITE(ah, AR_SLEEP2,
3054                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3055
3056         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3057         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3058
3059         REG_SET_BIT(ah, AR_TIMER_MODE,
3060                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3061                     AR_DTIM_TIMER_EN);
3062
3063         /* TSF Out of Range Threshold */
3064         REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3065 }
3066 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
3067
3068 /*******************/
3069 /* HW Capabilities */
3070 /*******************/
3071
3072 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
3073 {
3074         struct ath9k_hw_capabilities *pCap = &ah->caps;
3075         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3076         struct ath_common *common = ath9k_hw_common(ah);
3077         struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
3078
3079         u16 capField = 0, eeval;
3080
3081         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3082         regulatory->current_rd = eeval;
3083
3084         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3085         if (AR_SREV_9285_10_OR_LATER(ah))
3086                 eeval |= AR9285_RDEXT_DEFAULT;
3087         regulatory->current_rd_ext = eeval;
3088
3089         capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3090
3091         if (ah->opmode != NL80211_IFTYPE_AP &&
3092             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3093                 if (regulatory->current_rd == 0x64 ||
3094                     regulatory->current_rd == 0x65)
3095                         regulatory->current_rd += 5;
3096                 else if (regulatory->current_rd == 0x41)
3097                         regulatory->current_rd = 0x43;
3098                 ath_print(common, ATH_DBG_REGULATORY,
3099                           "regdomain mapped to 0x%x\n", regulatory->current_rd);
3100         }
3101
3102         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3103         if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
3104                 ath_print(common, ATH_DBG_FATAL,
3105                           "no band has been marked as supported in EEPROM.\n");
3106                 return -EINVAL;
3107         }
3108
3109         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3110
3111         if (eeval & AR5416_OPFLAGS_11A) {
3112                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3113                 if (ah->config.ht_enable) {
3114                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3115                                 set_bit(ATH9K_MODE_11NA_HT20,
3116                                         pCap->wireless_modes);
3117                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3118                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3119                                         pCap->wireless_modes);
3120                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3121                                         pCap->wireless_modes);
3122                         }
3123                 }
3124         }
3125
3126         if (eeval & AR5416_OPFLAGS_11G) {
3127                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3128                 if (ah->config.ht_enable) {
3129                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3130                                 set_bit(ATH9K_MODE_11NG_HT20,
3131                                         pCap->wireless_modes);
3132                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3133                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3134                                         pCap->wireless_modes);
3135                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3136                                         pCap->wireless_modes);
3137                         }
3138                 }
3139         }
3140
3141         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3142         /*
3143          * For AR9271 we will temporarilly uses the rx chainmax as read from
3144          * the EEPROM.
3145          */
3146         if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3147             !(eeval & AR5416_OPFLAGS_11A) &&
3148             !(AR_SREV_9271(ah)))
3149                 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
3150                 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3151         else
3152                 /* Use rx_chainmask from EEPROM. */
3153                 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3154
3155         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3156                 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3157
3158         pCap->low_2ghz_chan = 2312;
3159         pCap->high_2ghz_chan = 2732;
3160
3161         pCap->low_5ghz_chan = 4920;
3162         pCap->high_5ghz_chan = 6100;
3163
3164         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3165         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3166         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3167
3168         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3169         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3170         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3171
3172         if (ah->config.ht_enable)
3173                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3174         else
3175                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3176
3177         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3178         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3179         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3180         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3181
3182         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3183                 pCap->total_queues =
3184                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3185         else
3186                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3187
3188         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3189                 pCap->keycache_size =
3190                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3191         else
3192                 pCap->keycache_size = AR_KEYTABLE_SIZE;
3193
3194         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3195
3196         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
3197                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
3198         else
3199                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3200
3201         if (AR_SREV_9285_10_OR_LATER(ah))
3202                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3203         else if (AR_SREV_9280_10_OR_LATER(ah))
3204                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3205         else
3206                 pCap->num_gpio_pins = AR_NUM_GPIO;
3207
3208         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3209                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3210                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3211         } else {
3212                 pCap->rts_aggr_limit = (8 * 1024);
3213         }
3214
3215         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3216
3217 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3218         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3219         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3220                 ah->rfkill_gpio =
3221                         MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3222                 ah->rfkill_polarity =
3223                         MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3224
3225                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3226         }
3227 #endif
3228
3229         pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3230
3231         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3232                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3233         else
3234                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3235
3236         if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3237                 pCap->reg_cap =
3238                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3239                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3240                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3241                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3242         } else {
3243                 pCap->reg_cap =
3244                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3245                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3246         }
3247
3248         /* Advertise midband for AR5416 with FCC midband set in eeprom */
3249         if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
3250             AR_SREV_5416(ah))
3251                 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3252
3253         pCap->num_antcfg_5ghz =
3254                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3255         pCap->num_antcfg_2ghz =
3256                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3257
3258         if (AR_SREV_9280_10_OR_LATER(ah) &&
3259             ath9k_hw_btcoex_supported(ah)) {
3260                 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
3261                 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
3262
3263                 if (AR_SREV_9285(ah)) {
3264                         btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
3265                         btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
3266                 } else {
3267                         btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
3268                 }
3269         } else {
3270                 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
3271         }
3272
3273         return 0;
3274 }
3275
3276 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3277                             u32 capability, u32 *result)
3278 {
3279         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3280         switch (type) {
3281         case ATH9K_CAP_CIPHER:
3282                 switch (capability) {
3283                 case ATH9K_CIPHER_AES_CCM:
3284                 case ATH9K_CIPHER_AES_OCB:
3285                 case ATH9K_CIPHER_TKIP:
3286                 case ATH9K_CIPHER_WEP:
3287                 case ATH9K_CIPHER_MIC:
3288                 case ATH9K_CIPHER_CLR:
3289                         return true;
3290                 default:
3291                         return false;
3292                 }
3293         case ATH9K_CAP_TKIP_MIC:
3294                 switch (capability) {
3295                 case 0:
3296                         return true;
3297                 case 1:
3298                         return (ah->sta_id1_defaults &
3299                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3300                         false;
3301                 }
3302         case ATH9K_CAP_TKIP_SPLIT:
3303                 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3304                         false : true;
3305         case ATH9K_CAP_DIVERSITY:
3306                 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3307                         AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3308                         true : false;
3309         case ATH9K_CAP_MCAST_KEYSRCH:
3310                 switch (capability) {
3311                 case 0:
3312                         return true;
3313                 case 1:
3314                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3315                                 return false;
3316                         } else {
3317                                 return (ah->sta_id1_defaults &
3318                                         AR_STA_ID1_MCAST_KSRCH) ? true :
3319                                         false;
3320                         }
3321                 }
3322                 return false;
3323         case ATH9K_CAP_TXPOW:
3324                 switch (capability) {
3325                 case 0:
3326                         return 0;
3327                 case 1:
3328                         *result = regulatory->power_limit;
3329                         return 0;
3330                 case 2:
3331                         *result = regulatory->max_power_level;
3332                         return 0;
3333                 case 3:
3334                         *result = regulatory->tp_scale;
3335                         return 0;
3336                 }
3337                 return false;
3338         case ATH9K_CAP_DS:
3339                 return (AR_SREV_9280_20_OR_LATER(ah) &&
3340                         (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3341                         ? false : true;
3342         default:
3343                 return false;
3344         }
3345 }
3346 EXPORT_SYMBOL(ath9k_hw_getcapability);
3347
3348 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3349                             u32 capability, u32 setting, int *status)
3350 {
3351         u32 v;
3352
3353         switch (type) {
3354         case ATH9K_CAP_TKIP_MIC:
3355                 if (setting)
3356                         ah->sta_id1_defaults |=
3357                                 AR_STA_ID1_CRPT_MIC_ENABLE;
3358                 else
3359                         ah->sta_id1_defaults &=
3360                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3361                 return true;
3362         case ATH9K_CAP_DIVERSITY:
3363                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3364                 if (setting)
3365                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3366                 else
3367                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3368                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3369                 return true;
3370         case ATH9K_CAP_MCAST_KEYSRCH:
3371                 if (setting)
3372                         ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3373                 else
3374                         ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3375                 return true;
3376         default:
3377                 return false;
3378         }
3379 }
3380 EXPORT_SYMBOL(ath9k_hw_setcapability);
3381
3382 /****************************/
3383 /* GPIO / RFKILL / Antennae */
3384 /****************************/
3385
3386 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3387                                          u32 gpio, u32 type)
3388 {
3389         int addr;
3390         u32 gpio_shift, tmp;
3391
3392         if (gpio > 11)
3393                 addr = AR_GPIO_OUTPUT_MUX3;
3394         else if (gpio > 5)
3395                 addr = AR_GPIO_OUTPUT_MUX2;
3396         else
3397                 addr = AR_GPIO_OUTPUT_MUX1;
3398
3399         gpio_shift = (gpio % 6) * 5;
3400
3401         if (AR_SREV_9280_20_OR_LATER(ah)
3402             || (addr != AR_GPIO_OUTPUT_MUX1)) {
3403                 REG_RMW(ah, addr, (type << gpio_shift),
3404                         (0x1f << gpio_shift));
3405         } else {
3406                 tmp = REG_READ(ah, addr);
3407                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3408                 tmp &= ~(0x1f << gpio_shift);
3409                 tmp |= (type << gpio_shift);
3410                 REG_WRITE(ah, addr, tmp);
3411         }
3412 }
3413
3414 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3415 {
3416         u32 gpio_shift;
3417
3418         BUG_ON(gpio >= ah->caps.num_gpio_pins);
3419
3420         gpio_shift = gpio << 1;
3421
3422         REG_RMW(ah,
3423                 AR_GPIO_OE_OUT,
3424                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3425                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3426 }
3427 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
3428
3429 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3430 {
3431 #define MS_REG_READ(x, y) \
3432         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3433
3434         if (gpio >= ah->caps.num_gpio_pins)
3435                 return 0xffffffff;
3436
3437         if (AR_SREV_9287_10_OR_LATER(ah))
3438                 return MS_REG_READ(AR9287, gpio) != 0;
3439         else if (AR_SREV_9285_10_OR_LATER(ah))
3440                 return MS_REG_READ(AR9285, gpio) != 0;
3441         else if (AR_SREV_9280_10_OR_LATER(ah))
3442                 return MS_REG_READ(AR928X, gpio) != 0;
3443         else
3444                 return MS_REG_READ(AR, gpio) != 0;
3445 }
3446 EXPORT_SYMBOL(ath9k_hw_gpio_get);
3447
3448 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3449                          u32 ah_signal_type)
3450 {
3451         u32 gpio_shift;
3452
3453         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3454
3455         gpio_shift = 2 * gpio;
3456
3457         REG_RMW(ah,
3458                 AR_GPIO_OE_OUT,
3459                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3460                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3461 }
3462 EXPORT_SYMBOL(ath9k_hw_cfg_output);
3463
3464 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3465 {
3466         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3467                 AR_GPIO_BIT(gpio));
3468 }
3469 EXPORT_SYMBOL(ath9k_hw_set_gpio);
3470
3471 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3472 {
3473         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3474 }
3475 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
3476
3477 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3478 {
3479         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3480 }
3481 EXPORT_SYMBOL(ath9k_hw_setantenna);
3482
3483 /*********************/
3484 /* General Operation */
3485 /*********************/
3486
3487 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3488 {
3489         u32 bits = REG_READ(ah, AR_RX_FILTER);
3490         u32 phybits = REG_READ(ah, AR_PHY_ERR);
3491
3492         if (phybits & AR_PHY_ERR_RADAR)
3493                 bits |= ATH9K_RX_FILTER_PHYRADAR;
3494         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3495                 bits |= ATH9K_RX_FILTER_PHYERR;
3496
3497         return bits;
3498 }
3499 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
3500
3501 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3502 {
3503         u32 phybits;
3504
3505         REG_WRITE(ah, AR_RX_FILTER, bits);
3506
3507         phybits = 0;
3508         if (bits & ATH9K_RX_FILTER_PHYRADAR)
3509                 phybits |= AR_PHY_ERR_RADAR;
3510         if (bits & ATH9K_RX_FILTER_PHYERR)
3511                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3512         REG_WRITE(ah, AR_PHY_ERR, phybits);
3513
3514         if (phybits)
3515                 REG_WRITE(ah, AR_RXCFG,
3516                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3517         else
3518                 REG_WRITE(ah, AR_RXCFG,
3519                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3520 }
3521 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
3522
3523 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3524 {
3525         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
3526                 return false;
3527
3528         ath9k_hw_init_pll(ah, NULL);
3529         return true;
3530 }
3531 EXPORT_SYMBOL(ath9k_hw_phy_disable);
3532
3533 bool ath9k_hw_disable(struct ath_hw *ah)
3534 {
3535         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3536                 return false;
3537
3538         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
3539                 return false;
3540
3541         ath9k_hw_init_pll(ah, NULL);
3542         return true;
3543 }
3544 EXPORT_SYMBOL(ath9k_hw_disable);
3545
3546 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3547 {
3548         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3549         struct ath9k_channel *chan = ah->curchan;
3550         struct ieee80211_channel *channel = chan->chan;
3551
3552         regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
3553
3554         ah->eep_ops->set_txpower(ah, chan,
3555                                  ath9k_regd_get_ctl(regulatory, chan),
3556                                  channel->max_antenna_gain * 2,
3557                                  channel->max_power * 2,
3558                                  min((u32) MAX_RATE_POWER,
3559                                  (u32) regulatory->power_limit));
3560 }
3561 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
3562
3563 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3564 {
3565         memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
3566 }
3567 EXPORT_SYMBOL(ath9k_hw_setmac);
3568
3569 void ath9k_hw_setopmode(struct ath_hw *ah)
3570 {
3571         ath9k_hw_set_operating_mode(ah, ah->opmode);
3572 }
3573 EXPORT_SYMBOL(ath9k_hw_setopmode);
3574
3575 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3576 {
3577         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3578         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3579 }
3580 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
3581
3582 void ath9k_hw_write_associd(struct ath_hw *ah)
3583 {
3584         struct ath_common *common = ath9k_hw_common(ah);
3585
3586         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
3587         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
3588                   ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3589 }
3590 EXPORT_SYMBOL(ath9k_hw_write_associd);
3591
3592 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3593 {
3594         u64 tsf;
3595
3596         tsf = REG_READ(ah, AR_TSF_U32);
3597         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3598
3599         return tsf;
3600 }
3601 EXPORT_SYMBOL(ath9k_hw_gettsf64);
3602
3603 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3604 {
3605         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3606         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3607 }
3608 EXPORT_SYMBOL(ath9k_hw_settsf64);
3609
3610 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3611 {
3612         if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3613                            AH_TSF_WRITE_TIMEOUT))
3614                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
3615                           "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3616
3617         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3618 }
3619 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
3620
3621 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3622 {
3623         if (setting)
3624                 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3625         else
3626                 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3627 }
3628 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
3629
3630 /*
3631  *  Extend 15-bit time stamp from rx descriptor to
3632  *  a full 64-bit TSF using the current h/w TSF.
3633 */
3634 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
3635 {
3636         u64 tsf;
3637
3638         tsf = ath9k_hw_gettsf64(ah);
3639         if ((tsf & 0x7fff) < rstamp)
3640                 tsf -= 0x8000;
3641         return (tsf & ~0x7fff) | rstamp;
3642 }
3643 EXPORT_SYMBOL(ath9k_hw_extend_tsf);
3644
3645 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
3646 {
3647         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
3648         u32 macmode;
3649
3650         if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
3651                 macmode = AR_2040_JOINED_RX_CLEAR;
3652         else
3653                 macmode = 0;
3654
3655         REG_WRITE(ah, AR_2040_MODE, macmode);
3656 }
3657
3658 /* HW Generic timers configuration */
3659
3660 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
3661 {
3662         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3663         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3664         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3665         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3666         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3667         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3668         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3669         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3670         {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
3671         {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
3672                                 AR_NDP2_TIMER_MODE, 0x0002},
3673         {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
3674                                 AR_NDP2_TIMER_MODE, 0x0004},
3675         {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
3676                                 AR_NDP2_TIMER_MODE, 0x0008},
3677         {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
3678                                 AR_NDP2_TIMER_MODE, 0x0010},
3679         {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
3680                                 AR_NDP2_TIMER_MODE, 0x0020},
3681         {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
3682                                 AR_NDP2_TIMER_MODE, 0x0040},
3683         {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
3684                                 AR_NDP2_TIMER_MODE, 0x0080}
3685 };
3686
3687 /* HW generic timer primitives */
3688
3689 /* compute and clear index of rightmost 1 */
3690 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
3691 {
3692         u32 b;
3693
3694         b = *mask;
3695         b &= (0-b);
3696         *mask &= ~b;
3697         b *= debruijn32;
3698         b >>= 27;
3699
3700         return timer_table->gen_timer_index[b];
3701 }
3702
3703 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
3704 {
3705         return REG_READ(ah, AR_TSF_L32);
3706 }
3707 EXPORT_SYMBOL(ath9k_hw_gettsf32);
3708
3709 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3710                                           void (*trigger)(void *),
3711                                           void (*overflow)(void *),
3712                                           void *arg,
3713                                           u8 timer_index)
3714 {
3715         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3716         struct ath_gen_timer *timer;
3717
3718         timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
3719
3720         if (timer == NULL) {
3721                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
3722                           "Failed to allocate memory"
3723                           "for hw timer[%d]\n", timer_index);
3724                 return NULL;
3725         }
3726
3727         /* allocate a hardware generic timer slot */
3728         timer_table->timers[timer_index] = timer;
3729         timer->index = timer_index;
3730         timer->trigger = trigger;
3731         timer->overflow = overflow;
3732         timer->arg = arg;
3733
3734         return timer;
3735 }
3736 EXPORT_SYMBOL(ath_gen_timer_alloc);
3737
3738 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3739                               struct ath_gen_timer *timer,
3740                               u32 timer_next,
3741                               u32 timer_period)
3742 {
3743         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3744         u32 tsf;
3745
3746         BUG_ON(!timer_period);
3747
3748         set_bit(timer->index, &timer_table->timer_mask.timer_bits);
3749
3750         tsf = ath9k_hw_gettsf32(ah);
3751
3752         ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
3753                   "curent tsf %x period %x"
3754                   "timer_next %x\n", tsf, timer_period, timer_next);
3755
3756         /*
3757          * Pull timer_next forward if the current TSF already passed it
3758          * because of software latency
3759          */
3760         if (timer_next < tsf)
3761                 timer_next = tsf + timer_period;
3762
3763         /*
3764          * Program generic timer registers
3765          */
3766         REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3767                  timer_next);
3768         REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3769                   timer_period);
3770         REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3771                     gen_tmr_configuration[timer->index].mode_mask);
3772
3773         /* Enable both trigger and thresh interrupt masks */
3774         REG_SET_BIT(ah, AR_IMR_S5,
3775                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3776                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3777 }
3778 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
3779
3780 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3781 {
3782         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3783
3784         if ((timer->index < AR_FIRST_NDP_TIMER) ||
3785                 (timer->index >= ATH_MAX_GEN_TIMER)) {
3786                 return;
3787         }
3788
3789         /* Clear generic timer enable bits. */
3790         REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3791                         gen_tmr_configuration[timer->index].mode_mask);
3792
3793         /* Disable both trigger and thresh interrupt masks */
3794         REG_CLR_BIT(ah, AR_IMR_S5,
3795                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3796                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3797
3798         clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
3799 }
3800 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
3801
3802 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3803 {
3804         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3805
3806         /* free the hardware generic timer slot */
3807         timer_table->timers[timer->index] = NULL;
3808         kfree(timer);
3809 }
3810 EXPORT_SYMBOL(ath_gen_timer_free);
3811
3812 /*
3813  * Generic Timer Interrupts handling
3814  */
3815 void ath_gen_timer_isr(struct ath_hw *ah)
3816 {
3817         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3818         struct ath_gen_timer *timer;
3819         struct ath_common *common = ath9k_hw_common(ah);
3820         u32 trigger_mask, thresh_mask, index;
3821
3822         /* get hardware generic timer interrupt status */
3823         trigger_mask = ah->intr_gen_timer_trigger;
3824         thresh_mask = ah->intr_gen_timer_thresh;
3825         trigger_mask &= timer_table->timer_mask.val;
3826         thresh_mask &= timer_table->timer_mask.val;
3827
3828         trigger_mask &= ~thresh_mask;
3829
3830         while (thresh_mask) {
3831                 index = rightmost_index(timer_table, &thresh_mask);
3832                 timer = timer_table->timers[index];
3833                 BUG_ON(!timer);
3834                 ath_print(common, ATH_DBG_HWTIMER,
3835                           "TSF overflow for Gen timer %d\n", index);
3836                 timer->overflow(timer->arg);
3837         }
3838
3839         while (trigger_mask) {
3840                 index = rightmost_index(timer_table, &trigger_mask);
3841                 timer = timer_table->timers[index];
3842                 BUG_ON(!timer);
3843                 ath_print(common, ATH_DBG_HWTIMER,
3844                           "Gen timer[%d] trigger\n", index);
3845                 timer->trigger(timer->arg);
3846         }
3847 }
3848 EXPORT_SYMBOL(ath_gen_timer_isr);
3849
3850 static struct {
3851         u32 version;
3852         const char * name;
3853 } ath_mac_bb_names[] = {
3854         /* Devices with external radios */
3855         { AR_SREV_VERSION_5416_PCI,     "5416" },
3856         { AR_SREV_VERSION_5416_PCIE,    "5418" },
3857         { AR_SREV_VERSION_9100,         "9100" },
3858         { AR_SREV_VERSION_9160,         "9160" },
3859         /* Single-chip solutions */
3860         { AR_SREV_VERSION_9280,         "9280" },
3861         { AR_SREV_VERSION_9285,         "9285" },
3862         { AR_SREV_VERSION_9287,         "9287" },
3863         { AR_SREV_VERSION_9271,         "9271" },
3864 };
3865
3866 /* For devices with external radios */
3867 static struct {
3868         u16 version;
3869         const char * name;
3870 } ath_rf_names[] = {
3871         { 0,                            "5133" },
3872         { AR_RAD5133_SREV_MAJOR,        "5133" },
3873         { AR_RAD5122_SREV_MAJOR,        "5122" },
3874         { AR_RAD2133_SREV_MAJOR,        "2133" },
3875         { AR_RAD2122_SREV_MAJOR,        "2122" }
3876 };
3877
3878 /*
3879  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3880  */
3881 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3882 {
3883         int i;
3884
3885         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3886                 if (ath_mac_bb_names[i].version == mac_bb_version) {
3887                         return ath_mac_bb_names[i].name;
3888                 }
3889         }
3890
3891         return "????";
3892 }
3893
3894 /*
3895  * Return the RF name. "????" is returned if the RF is unknown.
3896  * Used for devices with external radios.
3897  */
3898 static const char *ath9k_hw_rf_name(u16 rf_version)
3899 {
3900         int i;
3901
3902         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3903                 if (ath_rf_names[i].version == rf_version) {
3904                         return ath_rf_names[i].name;
3905                 }
3906         }
3907
3908         return "????";
3909 }
3910
3911 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3912 {
3913         int used;
3914
3915         /* chipsets >= AR9280 are single-chip */
3916         if (AR_SREV_9280_10_OR_LATER(ah)) {
3917                 used = snprintf(hw_name, len,
3918                                "Atheros AR%s Rev:%x",
3919                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3920                                ah->hw_version.macRev);
3921         }
3922         else {
3923                 used = snprintf(hw_name, len,
3924                                "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3925                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3926                                ah->hw_version.macRev,
3927                                ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3928                                                 AR_RADIO_SREV_MAJOR)),
3929                                ah->hw_version.phyRev);
3930         }
3931
3932         hw_name[used] = '\0';
3933 }
3934 EXPORT_SYMBOL(ath9k_hw_name);