Merge branch 'for-linus' of git://git.kernel.dk/linux-block
[linux-2.6.git] / drivers / net / wireless / ath / ath9k / eeprom_9287.c
1 /*
2  * Copyright (c) 2008-2011 Atheros Communications Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16
17 #include "hw.h"
18 #include "ar9002_phy.h"
19
20 #define SIZE_EEPROM_AR9287 (sizeof(struct ar9287_eeprom) / sizeof(u16))
21
22 static int ath9k_hw_ar9287_get_eeprom_ver(struct ath_hw *ah)
23 {
24         return (ah->eeprom.map9287.baseEepHeader.version >> 12) & 0xF;
25 }
26
27 static int ath9k_hw_ar9287_get_eeprom_rev(struct ath_hw *ah)
28 {
29         return (ah->eeprom.map9287.baseEepHeader.version) & 0xFFF;
30 }
31
32 static bool __ath9k_hw_ar9287_fill_eeprom(struct ath_hw *ah)
33 {
34         struct ar9287_eeprom *eep = &ah->eeprom.map9287;
35         struct ath_common *common = ath9k_hw_common(ah);
36         u16 *eep_data;
37         int addr, eep_start_loc = AR9287_EEP_START_LOC;
38         eep_data = (u16 *)eep;
39
40         for (addr = 0; addr < SIZE_EEPROM_AR9287; addr++) {
41                 if (!ath9k_hw_nvram_read(common, addr + eep_start_loc,
42                                          eep_data)) {
43                         ath_dbg(common, ATH_DBG_EEPROM,
44                                 "Unable to read eeprom region\n");
45                         return false;
46                 }
47                 eep_data++;
48         }
49
50         return true;
51 }
52
53 static bool __ath9k_hw_usb_ar9287_fill_eeprom(struct ath_hw *ah)
54 {
55         u16 *eep_data = (u16 *)&ah->eeprom.map9287;
56
57         ath9k_hw_usb_gen_fill_eeprom(ah, eep_data,
58                                      AR9287_HTC_EEP_START_LOC,
59                                      SIZE_EEPROM_AR9287);
60         return true;
61 }
62
63 static bool ath9k_hw_ar9287_fill_eeprom(struct ath_hw *ah)
64 {
65         struct ath_common *common = ath9k_hw_common(ah);
66
67         if (!ath9k_hw_use_flash(ah)) {
68                 ath_dbg(common, ATH_DBG_EEPROM,
69                         "Reading from EEPROM, not flash\n");
70         }
71
72         if (common->bus_ops->ath_bus_type == ATH_USB)
73                 return __ath9k_hw_usb_ar9287_fill_eeprom(ah);
74         else
75                 return __ath9k_hw_ar9287_fill_eeprom(ah);
76 }
77
78 static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah)
79 {
80         u32 sum = 0, el, integer;
81         u16 temp, word, magic, magic2, *eepdata;
82         int i, addr;
83         bool need_swap = false;
84         struct ar9287_eeprom *eep = &ah->eeprom.map9287;
85         struct ath_common *common = ath9k_hw_common(ah);
86
87         if (!ath9k_hw_use_flash(ah)) {
88                 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET,
89                                          &magic)) {
90                         ath_err(common, "Reading Magic # failed\n");
91                         return false;
92                 }
93
94                 ath_dbg(common, ATH_DBG_EEPROM,
95                         "Read Magic = 0x%04X\n", magic);
96
97                 if (magic != AR5416_EEPROM_MAGIC) {
98                         magic2 = swab16(magic);
99
100                         if (magic2 == AR5416_EEPROM_MAGIC) {
101                                 need_swap = true;
102                                 eepdata = (u16 *)(&ah->eeprom);
103
104                                 for (addr = 0; addr < SIZE_EEPROM_AR9287; addr++) {
105                                         temp = swab16(*eepdata);
106                                         *eepdata = temp;
107                                         eepdata++;
108                                 }
109                         } else {
110                                 ath_err(common,
111                                         "Invalid EEPROM Magic. Endianness mismatch.\n");
112                                 return -EINVAL;
113                         }
114                 }
115         }
116
117         ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
118                 need_swap ? "True" : "False");
119
120         if (need_swap)
121                 el = swab16(ah->eeprom.map9287.baseEepHeader.length);
122         else
123                 el = ah->eeprom.map9287.baseEepHeader.length;
124
125         if (el > sizeof(struct ar9287_eeprom))
126                 el = sizeof(struct ar9287_eeprom) / sizeof(u16);
127         else
128                 el = el / sizeof(u16);
129
130         eepdata = (u16 *)(&ah->eeprom);
131
132         for (i = 0; i < el; i++)
133                 sum ^= *eepdata++;
134
135         if (need_swap) {
136                 word = swab16(eep->baseEepHeader.length);
137                 eep->baseEepHeader.length = word;
138
139                 word = swab16(eep->baseEepHeader.checksum);
140                 eep->baseEepHeader.checksum = word;
141
142                 word = swab16(eep->baseEepHeader.version);
143                 eep->baseEepHeader.version = word;
144
145                 word = swab16(eep->baseEepHeader.regDmn[0]);
146                 eep->baseEepHeader.regDmn[0] = word;
147
148                 word = swab16(eep->baseEepHeader.regDmn[1]);
149                 eep->baseEepHeader.regDmn[1] = word;
150
151                 word = swab16(eep->baseEepHeader.rfSilent);
152                 eep->baseEepHeader.rfSilent = word;
153
154                 word = swab16(eep->baseEepHeader.blueToothOptions);
155                 eep->baseEepHeader.blueToothOptions = word;
156
157                 word = swab16(eep->baseEepHeader.deviceCap);
158                 eep->baseEepHeader.deviceCap = word;
159
160                 integer = swab32(eep->modalHeader.antCtrlCommon);
161                 eep->modalHeader.antCtrlCommon = integer;
162
163                 for (i = 0; i < AR9287_MAX_CHAINS; i++) {
164                         integer = swab32(eep->modalHeader.antCtrlChain[i]);
165                         eep->modalHeader.antCtrlChain[i] = integer;
166                 }
167
168                 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
169                         word = swab16(eep->modalHeader.spurChans[i].spurChan);
170                         eep->modalHeader.spurChans[i].spurChan = word;
171                 }
172         }
173
174         if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR9287_EEP_VER
175             || ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
176                 ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
177                         sum, ah->eep_ops->get_eeprom_ver(ah));
178                 return -EINVAL;
179         }
180
181         return 0;
182 }
183
184 static u32 ath9k_hw_ar9287_get_eeprom(struct ath_hw *ah,
185                                       enum eeprom_param param)
186 {
187         struct ar9287_eeprom *eep = &ah->eeprom.map9287;
188         struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
189         struct base_eep_ar9287_header *pBase = &eep->baseEepHeader;
190         u16 ver_minor;
191
192         ver_minor = pBase->version & AR9287_EEP_VER_MINOR_MASK;
193
194         switch (param) {
195         case EEP_NFTHRESH_2:
196                 return pModal->noiseFloorThreshCh[0];
197         case EEP_MAC_LSW:
198                 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
199         case EEP_MAC_MID:
200                 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
201         case EEP_MAC_MSW:
202                 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
203         case EEP_REG_0:
204                 return pBase->regDmn[0];
205         case EEP_REG_1:
206                 return pBase->regDmn[1];
207         case EEP_OP_CAP:
208                 return pBase->deviceCap;
209         case EEP_OP_MODE:
210                 return pBase->opCapFlags;
211         case EEP_RF_SILENT:
212                 return pBase->rfSilent;
213         case EEP_MINOR_REV:
214                 return ver_minor;
215         case EEP_TX_MASK:
216                 return pBase->txMask;
217         case EEP_RX_MASK:
218                 return pBase->rxMask;
219         case EEP_DEV_TYPE:
220                 return pBase->deviceType;
221         case EEP_OL_PWRCTRL:
222                 return pBase->openLoopPwrCntl;
223         case EEP_TEMPSENSE_SLOPE:
224                 if (ver_minor >= AR9287_EEP_MINOR_VER_2)
225                         return pBase->tempSensSlope;
226                 else
227                         return 0;
228         case EEP_TEMPSENSE_SLOPE_PAL_ON:
229                 if (ver_minor >= AR9287_EEP_MINOR_VER_3)
230                         return pBase->tempSensSlopePalOn;
231                 else
232                         return 0;
233         default:
234                 return 0;
235         }
236 }
237
238 static void ar9287_eeprom_get_tx_gain_index(struct ath_hw *ah,
239                             struct ath9k_channel *chan,
240                             struct cal_data_op_loop_ar9287 *pRawDatasetOpLoop,
241                             u8 *pCalChans,  u16 availPiers, int8_t *pPwr)
242 {
243         u16 idxL = 0, idxR = 0, numPiers;
244         bool match;
245         struct chan_centers centers;
246
247         ath9k_hw_get_channel_centers(ah, chan, &centers);
248
249         for (numPiers = 0; numPiers < availPiers; numPiers++) {
250                 if (pCalChans[numPiers] == AR5416_BCHAN_UNUSED)
251                         break;
252         }
253
254         match = ath9k_hw_get_lower_upper_index(
255                 (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
256                 pCalChans, numPiers, &idxL, &idxR);
257
258         if (match) {
259                 *pPwr = (int8_t) pRawDatasetOpLoop[idxL].pwrPdg[0][0];
260         } else {
261                 *pPwr = ((int8_t) pRawDatasetOpLoop[idxL].pwrPdg[0][0] +
262                          (int8_t) pRawDatasetOpLoop[idxR].pwrPdg[0][0])/2;
263         }
264
265 }
266
267 static void ar9287_eeprom_olpc_set_pdadcs(struct ath_hw *ah,
268                                           int32_t txPower, u16 chain)
269 {
270         u32 tmpVal;
271         u32 a;
272
273         /* Enable OLPC for chain 0 */
274
275         tmpVal = REG_READ(ah, 0xa270);
276         tmpVal = tmpVal & 0xFCFFFFFF;
277         tmpVal = tmpVal | (0x3 << 24);
278         REG_WRITE(ah, 0xa270, tmpVal);
279
280         /* Enable OLPC for chain 1 */
281
282         tmpVal = REG_READ(ah, 0xb270);
283         tmpVal = tmpVal & 0xFCFFFFFF;
284         tmpVal = tmpVal | (0x3 << 24);
285         REG_WRITE(ah, 0xb270, tmpVal);
286
287         /* Write the OLPC ref power for chain 0 */
288
289         if (chain == 0) {
290                 tmpVal = REG_READ(ah, 0xa398);
291                 tmpVal = tmpVal & 0xff00ffff;
292                 a = (txPower)&0xff;
293                 tmpVal = tmpVal | (a << 16);
294                 REG_WRITE(ah, 0xa398, tmpVal);
295         }
296
297         /* Write the OLPC ref power for chain 1 */
298
299         if (chain == 1) {
300                 tmpVal = REG_READ(ah, 0xb398);
301                 tmpVal = tmpVal & 0xff00ffff;
302                 a = (txPower)&0xff;
303                 tmpVal = tmpVal | (a << 16);
304                 REG_WRITE(ah, 0xb398, tmpVal);
305         }
306 }
307
308 static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah,
309                                                 struct ath9k_channel *chan,
310                                                 int16_t *pTxPowerIndexOffset)
311 {
312         struct cal_data_per_freq_ar9287 *pRawDataset;
313         struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop;
314         u8 *pCalBChans = NULL;
315         u16 pdGainOverlap_t2;
316         u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
317         u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
318         u16 numPiers = 0, i, j;
319         u16 numXpdGain, xpdMask;
320         u16 xpdGainValues[AR5416_NUM_PD_GAINS] = {0, 0, 0, 0};
321         u32 reg32, regOffset, regChainOffset, regval;
322         int16_t diff = 0;
323         struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
324
325         xpdMask = pEepData->modalHeader.xpdGain;
326
327         if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >=
328             AR9287_EEP_MINOR_VER_2)
329                 pdGainOverlap_t2 = pEepData->modalHeader.pdGainOverlap;
330         else
331                 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
332                                             AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
333
334         if (IS_CHAN_2GHZ(chan)) {
335                 pCalBChans = pEepData->calFreqPier2G;
336                 numPiers = AR9287_NUM_2G_CAL_PIERS;
337                 if (ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
338                         pRawDatasetOpenLoop =
339                         (struct cal_data_op_loop_ar9287 *)pEepData->calPierData2G[0];
340                         ah->initPDADC = pRawDatasetOpenLoop->vpdPdg[0][0];
341                 }
342         }
343
344         numXpdGain = 0;
345
346         /* Calculate the value of xpdgains from the xpdGain Mask */
347         for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
348                 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
349                         if (numXpdGain >= AR5416_NUM_PD_GAINS)
350                                 break;
351                         xpdGainValues[numXpdGain] =
352                                 (u16)(AR5416_PD_GAINS_IN_MASK-i);
353                         numXpdGain++;
354                 }
355         }
356
357         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
358                       (numXpdGain - 1) & 0x3);
359         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
360                       xpdGainValues[0]);
361         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
362                       xpdGainValues[1]);
363         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
364                       xpdGainValues[2]);
365
366         for (i = 0; i < AR9287_MAX_CHAINS; i++) {
367                 regChainOffset = i * 0x1000;
368
369                 if (pEepData->baseEepHeader.txMask & (1 << i)) {
370                         pRawDatasetOpenLoop =
371                         (struct cal_data_op_loop_ar9287 *)pEepData->calPierData2G[i];
372
373                         if (ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
374                                 int8_t txPower;
375                                 ar9287_eeprom_get_tx_gain_index(ah, chan,
376                                                         pRawDatasetOpenLoop,
377                                                         pCalBChans, numPiers,
378                                                         &txPower);
379                                 ar9287_eeprom_olpc_set_pdadcs(ah, txPower, i);
380                         } else {
381                                 pRawDataset =
382                                         (struct cal_data_per_freq_ar9287 *)
383                                         pEepData->calPierData2G[i];
384
385                                 ath9k_hw_get_gain_boundaries_pdadcs(ah, chan,
386                                                            pRawDataset,
387                                                            pCalBChans, numPiers,
388                                                            pdGainOverlap_t2,
389                                                            gainBoundaries,
390                                                            pdadcValues,
391                                                            numXpdGain);
392                         }
393
394                         ENABLE_REGWRITE_BUFFER(ah);
395
396                         if (i == 0) {
397                                 if (!ath9k_hw_ar9287_get_eeprom(ah,
398                                                         EEP_OL_PWRCTRL)) {
399
400                                         regval = SM(pdGainOverlap_t2,
401                                                     AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
402                                                 | SM(gainBoundaries[0],
403                                                      AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
404                                                 | SM(gainBoundaries[1],
405                                                      AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
406                                                 | SM(gainBoundaries[2],
407                                                      AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
408                                                 | SM(gainBoundaries[3],
409                                                      AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4);
410
411                                         REG_WRITE(ah,
412                                                   AR_PHY_TPCRG5 + regChainOffset,
413                                                   regval);
414                                 }
415                         }
416
417                         if ((int32_t)AR9287_PWR_TABLE_OFFSET_DB !=
418                             pEepData->baseEepHeader.pwrTableOffset) {
419                                 diff = (u16)(pEepData->baseEepHeader.pwrTableOffset -
420                                              (int32_t)AR9287_PWR_TABLE_OFFSET_DB);
421                                 diff *= 2;
422
423                                 for (j = 0; j < ((u16)AR5416_NUM_PDADC_VALUES-diff); j++)
424                                         pdadcValues[j] = pdadcValues[j+diff];
425
426                                 for (j = (u16)(AR5416_NUM_PDADC_VALUES-diff);
427                                      j < AR5416_NUM_PDADC_VALUES; j++)
428                                         pdadcValues[j] =
429                                           pdadcValues[AR5416_NUM_PDADC_VALUES-diff];
430                         }
431
432                         if (!ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
433                                 regOffset = AR_PHY_BASE +
434                                         (672 << 2) + regChainOffset;
435
436                                 for (j = 0; j < 32; j++) {
437                                         reg32 = ((pdadcValues[4*j + 0] & 0xFF) << 0)
438                                                 | ((pdadcValues[4*j + 1] & 0xFF) << 8)
439                                                 | ((pdadcValues[4*j + 2] & 0xFF) << 16)
440                                                 | ((pdadcValues[4*j + 3] & 0xFF) << 24);
441
442                                         REG_WRITE(ah, regOffset, reg32);
443                                         regOffset += 4;
444                                 }
445                         }
446                         REGWRITE_BUFFER_FLUSH(ah);
447                 }
448         }
449
450         *pTxPowerIndexOffset = 0;
451 }
452
453 static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah,
454                                                      struct ath9k_channel *chan,
455                                                      int16_t *ratesArray,
456                                                      u16 cfgCtl,
457                                                      u16 AntennaReduction,
458                                                      u16 twiceMaxRegulatoryPower,
459                                                      u16 powerLimit)
460 {
461 #define CMP_CTL \
462         (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \
463          pEepData->ctlIndex[i])
464
465 #define CMP_NO_CTL \
466         (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \
467          ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))
468
469 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN     6
470 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN   10
471
472         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
473         u16 twiceMaxEdgePower = MAX_RATE_POWER;
474         static const u16 tpScaleReductionTable[5] =
475                 { 0, 3, 6, 9, MAX_RATE_POWER };
476         int i;
477         int16_t twiceLargestAntenna;
478         struct cal_ctl_data_ar9287 *rep;
479         struct cal_target_power_leg targetPowerOfdm = {0, {0, 0, 0, 0} },
480                                     targetPowerCck = {0, {0, 0, 0, 0} };
481         struct cal_target_power_leg targetPowerOfdmExt = {0, {0, 0, 0, 0} },
482                                     targetPowerCckExt = {0, {0, 0, 0, 0} };
483         struct cal_target_power_ht targetPowerHt20,
484                                     targetPowerHt40 = {0, {0, 0, 0, 0} };
485         u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
486         static const u16 ctlModesFor11g[] = {
487                 CTL_11B, CTL_11G, CTL_2GHT20,
488                 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
489         };
490         u16 numCtlModes = 0;
491         const u16 *pCtlMode = NULL;
492         u16 ctlMode, freq;
493         struct chan_centers centers;
494         int tx_chainmask;
495         u16 twiceMinEdgePower;
496         struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
497         tx_chainmask = ah->txchainmask;
498
499         ath9k_hw_get_channel_centers(ah, chan, &centers);
500
501         /* Compute TxPower reduction due to Antenna Gain */
502         twiceLargestAntenna = max(pEepData->modalHeader.antennaGainCh[0],
503                                   pEepData->modalHeader.antennaGainCh[1]);
504         twiceLargestAntenna = (int16_t)min((AntennaReduction) -
505                                            twiceLargestAntenna, 0);
506
507         /*
508          * scaledPower is the minimum of the user input power level
509          * and the regulatory allowed power level.
510          */
511         maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
512
513         if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX)
514                 maxRegAllowedPower -=
515                         (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
516
517         scaledPower = min(powerLimit, maxRegAllowedPower);
518
519         /*
520          * Reduce scaled Power by number of chains active
521          * to get the per chain tx power level.
522          */
523         switch (ar5416_get_ntxchains(tx_chainmask)) {
524         case 1:
525                 break;
526         case 2:
527                 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
528                 break;
529         case 3:
530                 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
531                 break;
532         }
533         scaledPower = max((u16)0, scaledPower);
534
535         /*
536          * Get TX power from EEPROM.
537          */
538         if (IS_CHAN_2GHZ(chan)) {
539                 /* CTL_11B, CTL_11G, CTL_2GHT20 */
540                 numCtlModes =
541                         ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
542
543                 pCtlMode = ctlModesFor11g;
544
545                 ath9k_hw_get_legacy_target_powers(ah, chan,
546                                                   pEepData->calTargetPowerCck,
547                                                   AR9287_NUM_2G_CCK_TARGET_POWERS,
548                                                   &targetPowerCck, 4, false);
549                 ath9k_hw_get_legacy_target_powers(ah, chan,
550                                                   pEepData->calTargetPower2G,
551                                                   AR9287_NUM_2G_20_TARGET_POWERS,
552                                                   &targetPowerOfdm, 4, false);
553                 ath9k_hw_get_target_powers(ah, chan,
554                                            pEepData->calTargetPower2GHT20,
555                                            AR9287_NUM_2G_20_TARGET_POWERS,
556                                            &targetPowerHt20, 8, false);
557
558                 if (IS_CHAN_HT40(chan)) {
559                         /* All 2G CTLs */
560                         numCtlModes = ARRAY_SIZE(ctlModesFor11g);
561                         ath9k_hw_get_target_powers(ah, chan,
562                                                    pEepData->calTargetPower2GHT40,
563                                                    AR9287_NUM_2G_40_TARGET_POWERS,
564                                                    &targetPowerHt40, 8, true);
565                         ath9k_hw_get_legacy_target_powers(ah, chan,
566                                                   pEepData->calTargetPowerCck,
567                                                   AR9287_NUM_2G_CCK_TARGET_POWERS,
568                                                   &targetPowerCckExt, 4, true);
569                         ath9k_hw_get_legacy_target_powers(ah, chan,
570                                                   pEepData->calTargetPower2G,
571                                                   AR9287_NUM_2G_20_TARGET_POWERS,
572                                                   &targetPowerOfdmExt, 4, true);
573                 }
574         }
575
576         for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
577                 bool isHt40CtlMode =
578                         (pCtlMode[ctlMode] == CTL_2GHT40) ? true : false;
579
580                 if (isHt40CtlMode)
581                         freq = centers.synth_center;
582                 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
583                         freq = centers.ext_center;
584                 else
585                         freq = centers.ctl_center;
586
587                 /* Walk through the CTL indices stored in EEPROM */
588                 for (i = 0; (i < AR9287_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
589                         struct cal_ctl_edges *pRdEdgesPower;
590
591                         /*
592                          * Compare test group from regulatory channel list
593                          * with test mode from pCtlMode list
594                          */
595                         if (CMP_CTL || CMP_NO_CTL) {
596                                 rep = &(pEepData->ctlData[i]);
597                                 pRdEdgesPower =
598                                 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1];
599
600                                 twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq,
601                                                                 pRdEdgesPower,
602                                                                 IS_CHAN_2GHZ(chan),
603                                                                 AR5416_NUM_BAND_EDGES);
604
605                                 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
606                                         twiceMaxEdgePower = min(twiceMaxEdgePower,
607                                                                 twiceMinEdgePower);
608                                 } else {
609                                         twiceMaxEdgePower = twiceMinEdgePower;
610                                         break;
611                                 }
612                         }
613                 }
614
615                 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
616
617                 /* Apply ctl mode to correct target power set */
618                 switch (pCtlMode[ctlMode]) {
619                 case CTL_11B:
620                         for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
621                                 targetPowerCck.tPow2x[i] =
622                                         (u8)min((u16)targetPowerCck.tPow2x[i],
623                                                 minCtlPower);
624                         }
625                         break;
626                 case CTL_11A:
627                 case CTL_11G:
628                         for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
629                                 targetPowerOfdm.tPow2x[i] =
630                                         (u8)min((u16)targetPowerOfdm.tPow2x[i],
631                                                 minCtlPower);
632                         }
633                         break;
634                 case CTL_5GHT20:
635                 case CTL_2GHT20:
636                         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
637                                 targetPowerHt20.tPow2x[i] =
638                                         (u8)min((u16)targetPowerHt20.tPow2x[i],
639                                                 minCtlPower);
640                         }
641                         break;
642                 case CTL_11B_EXT:
643                         targetPowerCckExt.tPow2x[0] =
644                                 (u8)min((u16)targetPowerCckExt.tPow2x[0],
645                                         minCtlPower);
646                         break;
647                 case CTL_11A_EXT:
648                 case CTL_11G_EXT:
649                         targetPowerOfdmExt.tPow2x[0] =
650                                 (u8)min((u16)targetPowerOfdmExt.tPow2x[0],
651                                         minCtlPower);
652                         break;
653                 case CTL_5GHT40:
654                 case CTL_2GHT40:
655                         for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
656                                 targetPowerHt40.tPow2x[i] =
657                                         (u8)min((u16)targetPowerHt40.tPow2x[i],
658                                                 minCtlPower);
659                         }
660                         break;
661                 default:
662                         break;
663                 }
664         }
665
666         /* Now set the rates array */
667
668         ratesArray[rate6mb] =
669         ratesArray[rate9mb] =
670         ratesArray[rate12mb] =
671         ratesArray[rate18mb] =
672         ratesArray[rate24mb] = targetPowerOfdm.tPow2x[0];
673
674         ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
675         ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
676         ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
677         ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
678
679         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
680                 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
681
682         if (IS_CHAN_2GHZ(chan)) {
683                 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
684                 ratesArray[rate2s] =
685                 ratesArray[rate2l] = targetPowerCck.tPow2x[1];
686                 ratesArray[rate5_5s] =
687                 ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
688                 ratesArray[rate11s] =
689                 ratesArray[rate11l] = targetPowerCck.tPow2x[3];
690         }
691         if (IS_CHAN_HT40(chan)) {
692                 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++)
693                         ratesArray[rateHt40_0 + i] = targetPowerHt40.tPow2x[i];
694
695                 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
696                 ratesArray[rateDupCck]  = targetPowerHt40.tPow2x[0];
697                 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
698
699                 if (IS_CHAN_2GHZ(chan))
700                         ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
701         }
702
703 #undef CMP_CTL
704 #undef CMP_NO_CTL
705 #undef REDUCE_SCALED_POWER_BY_TWO_CHAIN
706 #undef REDUCE_SCALED_POWER_BY_THREE_CHAIN
707 }
708
709 static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah,
710                                         struct ath9k_channel *chan, u16 cfgCtl,
711                                         u8 twiceAntennaReduction,
712                                         u8 twiceMaxRegulatoryPower,
713                                         u8 powerLimit, bool test)
714 {
715         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
716         struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
717         struct modal_eep_ar9287_header *pModal = &pEepData->modalHeader;
718         int16_t ratesArray[Ar5416RateSize];
719         int16_t txPowerIndexOffset = 0;
720         u8 ht40PowerIncForPdadc = 2;
721         int i;
722
723         memset(ratesArray, 0, sizeof(ratesArray));
724
725         if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >=
726             AR9287_EEP_MINOR_VER_2)
727                 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
728
729         ath9k_hw_set_ar9287_power_per_rate_table(ah, chan,
730                                                  &ratesArray[0], cfgCtl,
731                                                  twiceAntennaReduction,
732                                                  twiceMaxRegulatoryPower,
733                                                  powerLimit);
734
735         ath9k_hw_set_ar9287_power_cal_table(ah, chan, &txPowerIndexOffset);
736
737         regulatory->max_power_level = 0;
738         for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
739                 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
740                 if (ratesArray[i] > MAX_RATE_POWER)
741                         ratesArray[i] = MAX_RATE_POWER;
742
743                 if (ratesArray[i] > regulatory->max_power_level)
744                         regulatory->max_power_level = ratesArray[i];
745         }
746
747         if (test)
748                 return;
749
750         if (IS_CHAN_2GHZ(chan))
751                 i = rate1l;
752         else
753                 i = rate6mb;
754
755         regulatory->max_power_level = ratesArray[i];
756
757         if (AR_SREV_9280_20_OR_LATER(ah)) {
758                 for (i = 0; i < Ar5416RateSize; i++)
759                         ratesArray[i] -= AR9287_PWR_TABLE_OFFSET_DB * 2;
760         }
761
762         ENABLE_REGWRITE_BUFFER(ah);
763
764         /* OFDM power per rate */
765         REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
766                   ATH9K_POW_SM(ratesArray[rate18mb], 24)
767                   | ATH9K_POW_SM(ratesArray[rate12mb], 16)
768                   | ATH9K_POW_SM(ratesArray[rate9mb], 8)
769                   | ATH9K_POW_SM(ratesArray[rate6mb], 0));
770
771         REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
772                   ATH9K_POW_SM(ratesArray[rate54mb], 24)
773                   | ATH9K_POW_SM(ratesArray[rate48mb], 16)
774                   | ATH9K_POW_SM(ratesArray[rate36mb], 8)
775                   | ATH9K_POW_SM(ratesArray[rate24mb], 0));
776
777         /* CCK power per rate */
778         if (IS_CHAN_2GHZ(chan)) {
779                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
780                           ATH9K_POW_SM(ratesArray[rate2s], 24)
781                           | ATH9K_POW_SM(ratesArray[rate2l], 16)
782                           | ATH9K_POW_SM(ratesArray[rateXr], 8)
783                           | ATH9K_POW_SM(ratesArray[rate1l], 0));
784                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
785                           ATH9K_POW_SM(ratesArray[rate11s], 24)
786                           | ATH9K_POW_SM(ratesArray[rate11l], 16)
787                           | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
788                           | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
789         }
790
791         /* HT20 power per rate */
792         REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
793                   ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
794                   | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
795                   | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
796                   | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
797
798         REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
799                   ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
800                   | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
801                   | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
802                   | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
803
804         /* HT40 power per rate */
805         if (IS_CHAN_HT40(chan)) {
806                 if (ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
807                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
808                                   ATH9K_POW_SM(ratesArray[rateHt40_3], 24)
809                                   | ATH9K_POW_SM(ratesArray[rateHt40_2], 16)
810                                   | ATH9K_POW_SM(ratesArray[rateHt40_1], 8)
811                                   | ATH9K_POW_SM(ratesArray[rateHt40_0], 0));
812
813                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
814                                   ATH9K_POW_SM(ratesArray[rateHt40_7], 24)
815                                   | ATH9K_POW_SM(ratesArray[rateHt40_6], 16)
816                                   | ATH9K_POW_SM(ratesArray[rateHt40_5], 8)
817                                   | ATH9K_POW_SM(ratesArray[rateHt40_4], 0));
818                 } else {
819                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
820                                   ATH9K_POW_SM(ratesArray[rateHt40_3] +
821                                                ht40PowerIncForPdadc, 24)
822                                   | ATH9K_POW_SM(ratesArray[rateHt40_2] +
823                                                  ht40PowerIncForPdadc, 16)
824                                   | ATH9K_POW_SM(ratesArray[rateHt40_1] +
825                                                  ht40PowerIncForPdadc, 8)
826                                   | ATH9K_POW_SM(ratesArray[rateHt40_0] +
827                                                  ht40PowerIncForPdadc, 0));
828
829                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
830                                   ATH9K_POW_SM(ratesArray[rateHt40_7] +
831                                                ht40PowerIncForPdadc, 24)
832                                   | ATH9K_POW_SM(ratesArray[rateHt40_6] +
833                                                  ht40PowerIncForPdadc, 16)
834                                   | ATH9K_POW_SM(ratesArray[rateHt40_5] +
835                                                  ht40PowerIncForPdadc, 8)
836                                   | ATH9K_POW_SM(ratesArray[rateHt40_4] +
837                                                  ht40PowerIncForPdadc, 0));
838                 }
839
840                 /* Dup/Ext power per rate */
841                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
842                           ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
843                           | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
844                           | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
845                           | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
846         }
847         REGWRITE_BUFFER_FLUSH(ah);
848 }
849
850 static void ath9k_hw_ar9287_set_addac(struct ath_hw *ah,
851                                       struct ath9k_channel *chan)
852 {
853 }
854
855 static void ath9k_hw_ar9287_set_board_values(struct ath_hw *ah,
856                                              struct ath9k_channel *chan)
857 {
858         struct ar9287_eeprom *eep = &ah->eeprom.map9287;
859         struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
860         u32 regChainOffset, regval;
861         u8 txRxAttenLocal;
862         int i;
863
864         pModal = &eep->modalHeader;
865
866         REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
867
868         for (i = 0; i < AR9287_MAX_CHAINS; i++) {
869                 regChainOffset = i * 0x1000;
870
871                 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
872                           pModal->antCtrlChain[i]);
873
874                 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
875                           (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset)
876                            & ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
877                                AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
878                           SM(pModal->iqCalICh[i],
879                              AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
880                           SM(pModal->iqCalQCh[i],
881                              AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
882
883                 txRxAttenLocal = pModal->txRxAttenCh[i];
884
885                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
886                               AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
887                               pModal->bswMargin[i]);
888                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
889                               AR_PHY_GAIN_2GHZ_XATTEN1_DB,
890                               pModal->bswAtten[i]);
891                 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
892                               AR9280_PHY_RXGAIN_TXRX_ATTEN,
893                               txRxAttenLocal);
894                 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
895                               AR9280_PHY_RXGAIN_TXRX_MARGIN,
896                               pModal->rxTxMarginCh[i]);
897         }
898
899
900         if (IS_CHAN_HT40(chan))
901                 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
902                               AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40);
903         else
904                 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
905                               AR_PHY_SETTLING_SWITCH, pModal->switchSettling);
906
907         REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
908                       AR_PHY_DESIRED_SZ_ADC, pModal->adcDesiredSize);
909
910         REG_WRITE(ah, AR_PHY_RF_CTL4,
911                   SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
912                   | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
913                   | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON)
914                   | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
915
916         REG_RMW_FIELD(ah, AR_PHY_RF_CTL3,
917                       AR_PHY_TX_END_TO_A2_RX_ON, pModal->txEndToRxOn);
918
919         REG_RMW_FIELD(ah, AR_PHY_CCA,
920                       AR9280_PHY_CCA_THRESH62, pModal->thresh62);
921         REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
922                       AR_PHY_EXT_CCA0_THRESH62, pModal->thresh62);
923
924         regval = REG_READ(ah, AR9287_AN_RF2G3_CH0);
925         regval &= ~(AR9287_AN_RF2G3_DB1 |
926                     AR9287_AN_RF2G3_DB2 |
927                     AR9287_AN_RF2G3_OB_CCK |
928                     AR9287_AN_RF2G3_OB_PSK |
929                     AR9287_AN_RF2G3_OB_QAM |
930                     AR9287_AN_RF2G3_OB_PAL_OFF);
931         regval |= (SM(pModal->db1, AR9287_AN_RF2G3_DB1) |
932                    SM(pModal->db2, AR9287_AN_RF2G3_DB2) |
933                    SM(pModal->ob_cck, AR9287_AN_RF2G3_OB_CCK) |
934                    SM(pModal->ob_psk, AR9287_AN_RF2G3_OB_PSK) |
935                    SM(pModal->ob_qam, AR9287_AN_RF2G3_OB_QAM) |
936                    SM(pModal->ob_pal_off, AR9287_AN_RF2G3_OB_PAL_OFF));
937
938         ath9k_hw_analog_shift_regwrite(ah, AR9287_AN_RF2G3_CH0, regval);
939
940         regval = REG_READ(ah, AR9287_AN_RF2G3_CH1);
941         regval &= ~(AR9287_AN_RF2G3_DB1 |
942                     AR9287_AN_RF2G3_DB2 |
943                     AR9287_AN_RF2G3_OB_CCK |
944                     AR9287_AN_RF2G3_OB_PSK |
945                     AR9287_AN_RF2G3_OB_QAM |
946                     AR9287_AN_RF2G3_OB_PAL_OFF);
947         regval |= (SM(pModal->db1, AR9287_AN_RF2G3_DB1) |
948                    SM(pModal->db2, AR9287_AN_RF2G3_DB2) |
949                    SM(pModal->ob_cck, AR9287_AN_RF2G3_OB_CCK) |
950                    SM(pModal->ob_psk, AR9287_AN_RF2G3_OB_PSK) |
951                    SM(pModal->ob_qam, AR9287_AN_RF2G3_OB_QAM) |
952                    SM(pModal->ob_pal_off, AR9287_AN_RF2G3_OB_PAL_OFF));
953
954         ath9k_hw_analog_shift_regwrite(ah, AR9287_AN_RF2G3_CH1, regval);
955
956         REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
957                       AR_PHY_TX_END_DATA_START, pModal->txFrameToDataStart);
958         REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
959                       AR_PHY_TX_END_PA_ON, pModal->txFrameToPaOn);
960
961         ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TOP2,
962                                   AR9287_AN_TOP2_XPABIAS_LVL,
963                                   AR9287_AN_TOP2_XPABIAS_LVL_S,
964                                   pModal->xpaBiasLvl);
965 }
966
967 static u16 ath9k_hw_ar9287_get_spur_channel(struct ath_hw *ah,
968                                             u16 i, bool is2GHz)
969 {
970 #define EEP_MAP9287_SPURCHAN \
971         (ah->eeprom.map9287.modalHeader.spurChans[i].spurChan)
972
973         struct ath_common *common = ath9k_hw_common(ah);
974         u16 spur_val = AR_NO_SPUR;
975
976         ath_dbg(common, ATH_DBG_ANI,
977                 "Getting spur idx:%d is2Ghz:%d val:%x\n",
978                 i, is2GHz, ah->config.spurchans[i][is2GHz]);
979
980         switch (ah->config.spurmode) {
981         case SPUR_DISABLE:
982                 break;
983         case SPUR_ENABLE_IOCTL:
984                 spur_val = ah->config.spurchans[i][is2GHz];
985                 ath_dbg(common, ATH_DBG_ANI,
986                         "Getting spur val from new loc. %d\n", spur_val);
987                 break;
988         case SPUR_ENABLE_EEPROM:
989                 spur_val = EEP_MAP9287_SPURCHAN;
990                 break;
991         }
992
993         return spur_val;
994
995 #undef EEP_MAP9287_SPURCHAN
996 }
997
998 const struct eeprom_ops eep_ar9287_ops = {
999         .check_eeprom           = ath9k_hw_ar9287_check_eeprom,
1000         .get_eeprom             = ath9k_hw_ar9287_get_eeprom,
1001         .fill_eeprom            = ath9k_hw_ar9287_fill_eeprom,
1002         .get_eeprom_ver         = ath9k_hw_ar9287_get_eeprom_ver,
1003         .get_eeprom_rev         = ath9k_hw_ar9287_get_eeprom_rev,
1004         .set_board_values       = ath9k_hw_ar9287_set_board_values,
1005         .set_addac              = ath9k_hw_ar9287_set_addac,
1006         .set_txpower            = ath9k_hw_ar9287_set_txpower,
1007         .get_spur_channel       = ath9k_hw_ar9287_get_spur_channel
1008 };