ath9k_hw: sanitize noise floor values properly on all chips
[linux-2.6.git] / drivers / net / wireless / ath / ath9k / ar9003_phy.c
1 /*
2  * Copyright (c) 2010 Atheros Communications Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16
17 #include "hw.h"
18 #include "ar9003_phy.h"
19
20 static const int firstep_table[] =
21 /* level:  0   1   2   3   4   5   6   7   8  */
22         { -4, -2,  0,  2,  4,  6,  8, 10, 12 }; /* lvl 0-8, default 2 */
23
24 static const int cycpwrThr1_table[] =
25 /* level:  0   1   2   3   4   5   6   7   8  */
26         { -6, -4, -2,  0,  2,  4,  6,  8 };     /* lvl 0-7, default 3 */
27
28 /*
29  * register values to turn OFDM weak signal detection OFF
30  */
31 static const int m1ThreshLow_off = 127;
32 static const int m2ThreshLow_off = 127;
33 static const int m1Thresh_off = 127;
34 static const int m2Thresh_off = 127;
35 static const int m2CountThr_off =  31;
36 static const int m2CountThrLow_off =  63;
37 static const int m1ThreshLowExt_off = 127;
38 static const int m2ThreshLowExt_off = 127;
39 static const int m1ThreshExt_off = 127;
40 static const int m2ThreshExt_off = 127;
41
42 /**
43  * ar9003_hw_set_channel - set channel on single-chip device
44  * @ah: atheros hardware structure
45  * @chan:
46  *
47  * This is the function to change channel on single-chip devices, that is
48  * all devices after ar9280.
49  *
50  * This function takes the channel value in MHz and sets
51  * hardware channel value. Assumes writes have been enabled to analog bus.
52  *
53  * Actual Expression,
54  *
55  * For 2GHz channel,
56  * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
57  * (freq_ref = 40MHz)
58  *
59  * For 5GHz channel,
60  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
61  * (freq_ref = 40MHz/(24>>amodeRefSel))
62  *
63  * For 5GHz channels which are 5MHz spaced,
64  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
65  * (freq_ref = 40MHz)
66  */
67 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
68 {
69         u16 bMode, fracMode = 0, aModeRefSel = 0;
70         u32 freq, channelSel = 0, reg32 = 0;
71         struct chan_centers centers;
72         int loadSynthChannel;
73
74         ath9k_hw_get_channel_centers(ah, chan, &centers);
75         freq = centers.synth_center;
76
77         if (freq < 4800) {     /* 2 GHz, fractional mode */
78                 channelSel = CHANSEL_2G(freq);
79                 /* Set to 2G mode */
80                 bMode = 1;
81         } else {
82                 channelSel = CHANSEL_5G(freq);
83                 /* Doubler is ON, so, divide channelSel by 2. */
84                 channelSel >>= 1;
85                 /* Set to 5G mode */
86                 bMode = 0;
87         }
88
89         /* Enable fractional mode for all channels */
90         fracMode = 1;
91         aModeRefSel = 0;
92         loadSynthChannel = 0;
93
94         reg32 = (bMode << 29);
95         REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
96
97         /* Enable Long shift Select for Synthesizer */
98         REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
99                       AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
100
101         /* Program Synth. setting */
102         reg32 = (channelSel << 2) | (fracMode << 30) |
103                 (aModeRefSel << 28) | (loadSynthChannel << 31);
104         REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
105
106         /* Toggle Load Synth channel bit */
107         loadSynthChannel = 1;
108         reg32 = (channelSel << 2) | (fracMode << 30) |
109                 (aModeRefSel << 28) | (loadSynthChannel << 31);
110         REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
111
112         ah->curchan = chan;
113         ah->curchan_rad_index = -1;
114
115         return 0;
116 }
117
118 /**
119  * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
120  * @ah: atheros hardware structure
121  * @chan:
122  *
123  * For single-chip solutions. Converts to baseband spur frequency given the
124  * input channel frequency and compute register settings below.
125  *
126  * Spur mitigation for MRC CCK
127  */
128 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
129                                             struct ath9k_channel *chan)
130 {
131         u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
132         int cur_bb_spur, negative = 0, cck_spur_freq;
133         int i;
134
135         /*
136          * Need to verify range +/- 10 MHz in control channel, otherwise spur
137          * is out-of-band and can be ignored.
138          */
139
140         for (i = 0; i < 4; i++) {
141                 negative = 0;
142                 cur_bb_spur = spur_freq[i] - chan->channel;
143
144                 if (cur_bb_spur < 0) {
145                         negative = 1;
146                         cur_bb_spur = -cur_bb_spur;
147                 }
148                 if (cur_bb_spur < 10) {
149                         cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
150
151                         if (negative == 1)
152                                 cck_spur_freq = -cck_spur_freq;
153
154                         cck_spur_freq = cck_spur_freq & 0xfffff;
155
156                         REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
157                                       AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
158                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
159                                       AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
160                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
161                                       AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
162                                       0x2);
163                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
164                                       AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
165                                       0x1);
166                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
167                                       AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
168                                       cck_spur_freq);
169
170                         return;
171                 }
172         }
173
174         REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
175                       AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
176         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
177                       AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
178         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
179                       AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
180 }
181
182 /* Clean all spur register fields */
183 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
184 {
185         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
186                       AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
187         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
188                       AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
189         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
190                       AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
191         REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
192                       AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
193         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
194                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
195         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
196                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
197         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
198                       AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
199         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
200                       AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
201         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
202                       AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
203
204         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
205                       AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
206         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
207                       AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
208         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
209                       AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
210         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
211                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
212         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
213                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
214         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
215                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
216         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
217                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
218         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
219                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
220         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
221                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
222         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
223                       AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
224 }
225
226 static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
227                                 int freq_offset,
228                                 int spur_freq_sd,
229                                 int spur_delta_phase,
230                                 int spur_subchannel_sd)
231 {
232         int mask_index = 0;
233
234         /* OFDM Spur mitigation */
235         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
236                  AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
237         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
238                       AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
239         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
240                       AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
241         REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
242                       AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
243         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
244                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
245         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
246                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
247         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
248                       AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
249         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
250                       AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
251         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
252                       AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
253
254         if (REG_READ_FIELD(ah, AR_PHY_MODE,
255                            AR_PHY_MODE_DYNAMIC) == 0x1)
256                 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
257                               AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
258
259         mask_index = (freq_offset << 4) / 5;
260         if (mask_index < 0)
261                 mask_index = mask_index - 1;
262
263         mask_index = mask_index & 0x7f;
264
265         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
266                       AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
267         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
268                       AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
269         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
270                       AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
271         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
272                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
273         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
274                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
275         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
276                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
277         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
278                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
279         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
280                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
281         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
282                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
283         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
284                       AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
285 }
286
287 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
288                                      struct ath9k_channel *chan,
289                                      int freq_offset)
290 {
291         int spur_freq_sd = 0;
292         int spur_subchannel_sd = 0;
293         int spur_delta_phase = 0;
294
295         if (IS_CHAN_HT40(chan)) {
296                 if (freq_offset < 0) {
297                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
298                                            AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
299                                 spur_subchannel_sd = 1;
300                         else
301                                 spur_subchannel_sd = 0;
302
303                         spur_freq_sd = ((freq_offset + 10) << 9) / 11;
304
305                 } else {
306                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
307                             AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
308                                 spur_subchannel_sd = 0;
309                         else
310                                 spur_subchannel_sd = 1;
311
312                         spur_freq_sd = ((freq_offset - 10) << 9) / 11;
313
314                 }
315
316                 spur_delta_phase = (freq_offset << 17) / 5;
317
318         } else {
319                 spur_subchannel_sd = 0;
320                 spur_freq_sd = (freq_offset << 9) /11;
321                 spur_delta_phase = (freq_offset << 18) / 5;
322         }
323
324         spur_freq_sd = spur_freq_sd & 0x3ff;
325         spur_delta_phase = spur_delta_phase & 0xfffff;
326
327         ar9003_hw_spur_ofdm(ah,
328                             freq_offset,
329                             spur_freq_sd,
330                             spur_delta_phase,
331                             spur_subchannel_sd);
332 }
333
334 /* Spur mitigation for OFDM */
335 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
336                                          struct ath9k_channel *chan)
337 {
338         int synth_freq;
339         int range = 10;
340         int freq_offset = 0;
341         int mode;
342         u8* spurChansPtr;
343         unsigned int i;
344         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
345
346         if (IS_CHAN_5GHZ(chan)) {
347                 spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
348                 mode = 0;
349         }
350         else {
351                 spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
352                 mode = 1;
353         }
354
355         if (spurChansPtr[0] == 0)
356                 return; /* No spur in the mode */
357
358         if (IS_CHAN_HT40(chan)) {
359                 range = 19;
360                 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
361                                    AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
362                         synth_freq = chan->channel - 10;
363                 else
364                         synth_freq = chan->channel + 10;
365         } else {
366                 range = 10;
367                 synth_freq = chan->channel;
368         }
369
370         ar9003_hw_spur_ofdm_clear(ah);
371
372         for (i = 0; spurChansPtr[i] && i < 5; i++) {
373                 freq_offset = FBIN2FREQ(spurChansPtr[i], mode) - synth_freq;
374                 if (abs(freq_offset) < range) {
375                         ar9003_hw_spur_ofdm_work(ah, chan, freq_offset);
376                         break;
377                 }
378         }
379 }
380
381 static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
382                                     struct ath9k_channel *chan)
383 {
384         ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
385         ar9003_hw_spur_mitigate_ofdm(ah, chan);
386 }
387
388 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
389                                          struct ath9k_channel *chan)
390 {
391         u32 pll;
392
393         pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
394
395         if (chan && IS_CHAN_HALF_RATE(chan))
396                 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
397         else if (chan && IS_CHAN_QUARTER_RATE(chan))
398                 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
399
400         pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
401
402         return pll;
403 }
404
405 static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
406                                        struct ath9k_channel *chan)
407 {
408         u32 phymode;
409         u32 enableDacFifo = 0;
410
411         enableDacFifo =
412                 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
413
414         /* Enable 11n HT, 20 MHz */
415         phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 | AR_PHY_GC_WALSH |
416                   AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
417
418         /* Configure baseband for dynamic 20/40 operation */
419         if (IS_CHAN_HT40(chan)) {
420                 phymode |= AR_PHY_GC_DYN2040_EN;
421                 /* Configure control (primary) channel at +-10MHz */
422                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
423                     (chan->chanmode == CHANNEL_G_HT40PLUS))
424                         phymode |= AR_PHY_GC_DYN2040_PRI_CH;
425
426         }
427
428         /* make sure we preserve INI settings */
429         phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
430         /* turn off Green Field detection for STA for now */
431         phymode &= ~AR_PHY_GC_GF_DETECT_EN;
432
433         REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
434
435         /* Configure MAC for 20/40 operation */
436         ath9k_hw_set11nmac2040(ah);
437
438         /* global transmit timeout (25 TUs default)*/
439         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
440         /* carrier sense timeout */
441         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
442 }
443
444 static void ar9003_hw_init_bb(struct ath_hw *ah,
445                               struct ath9k_channel *chan)
446 {
447         u32 synthDelay;
448
449         /*
450          * Wait for the frequency synth to settle (synth goes on
451          * via AR_PHY_ACTIVE_EN).  Read the phy active delay register.
452          * Value is in 100ns increments.
453          */
454         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
455         if (IS_CHAN_B(chan))
456                 synthDelay = (4 * synthDelay) / 22;
457         else
458                 synthDelay /= 10;
459
460         /* Activate the PHY (includes baseband activate + synthesizer on) */
461         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
462
463         /*
464          * There is an issue if the AP starts the calibration before
465          * the base band timeout completes.  This could result in the
466          * rx_clear false triggering.  As a workaround we add delay an
467          * extra BASE_ACTIVATE_DELAY usecs to ensure this condition
468          * does not happen.
469          */
470         udelay(synthDelay + BASE_ACTIVATE_DELAY);
471 }
472
473 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
474 {
475         switch (rx) {
476         case 0x5:
477                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
478                             AR_PHY_SWAP_ALT_CHAIN);
479         case 0x3:
480         case 0x1:
481         case 0x2:
482         case 0x7:
483                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
484                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
485                 break;
486         default:
487                 break;
488         }
489
490         REG_WRITE(ah, AR_SELFGEN_MASK, tx);
491         if (tx == 0x5) {
492                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
493                             AR_PHY_SWAP_ALT_CHAIN);
494         }
495 }
496
497 /*
498  * Override INI values with chip specific configuration.
499  */
500 static void ar9003_hw_override_ini(struct ath_hw *ah)
501 {
502         u32 val;
503
504         /*
505          * Set the RX_ABORT and RX_DIS and clear it only after
506          * RXE is set for MAC. This prevents frames with
507          * corrupted descriptor status.
508          */
509         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
510
511         /*
512          * For AR9280 and above, there is a new feature that allows
513          * Multicast search based on both MAC Address and Key ID. By default,
514          * this feature is enabled. But since the driver is not using this
515          * feature, we switch it off; otherwise multicast search based on
516          * MAC addr only will fail.
517          */
518         val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
519         REG_WRITE(ah, AR_PCU_MISC_MODE2,
520                   val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE);
521 }
522
523 static void ar9003_hw_prog_ini(struct ath_hw *ah,
524                                struct ar5416IniArray *iniArr,
525                                int column)
526 {
527         unsigned int i, regWrites = 0;
528
529         /* New INI format: Array may be undefined (pre, core, post arrays) */
530         if (!iniArr->ia_array)
531                 return;
532
533         /*
534          * New INI format: Pre, core, and post arrays for a given subsystem
535          * may be modal (> 2 columns) or non-modal (2 columns). Determine if
536          * the array is non-modal and force the column to 1.
537          */
538         if (column >= iniArr->ia_columns)
539                 column = 1;
540
541         for (i = 0; i < iniArr->ia_rows; i++) {
542                 u32 reg = INI_RA(iniArr, i, 0);
543                 u32 val = INI_RA(iniArr, i, column);
544
545                 REG_WRITE(ah, reg, val);
546                 DO_DELAY(regWrites);
547         }
548 }
549
550 static int ar9003_hw_process_ini(struct ath_hw *ah,
551                                  struct ath9k_channel *chan)
552 {
553         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
554         unsigned int regWrites = 0, i;
555         struct ieee80211_channel *channel = chan->chan;
556         u32 modesIndex, freqIndex;
557
558         switch (chan->chanmode) {
559         case CHANNEL_A:
560         case CHANNEL_A_HT20:
561                 modesIndex = 1;
562                 freqIndex = 1;
563                 break;
564         case CHANNEL_A_HT40PLUS:
565         case CHANNEL_A_HT40MINUS:
566                 modesIndex = 2;
567                 freqIndex = 1;
568                 break;
569         case CHANNEL_G:
570         case CHANNEL_G_HT20:
571         case CHANNEL_B:
572                 modesIndex = 4;
573                 freqIndex = 2;
574                 break;
575         case CHANNEL_G_HT40PLUS:
576         case CHANNEL_G_HT40MINUS:
577                 modesIndex = 3;
578                 freqIndex = 2;
579                 break;
580
581         default:
582                 return -EINVAL;
583         }
584
585         for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
586                 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
587                 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
588                 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
589                 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
590         }
591
592         REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
593         REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
594
595         /*
596          * For 5GHz channels requiring Fast Clock, apply
597          * different modal values.
598          */
599         if (IS_CHAN_A_FAST_CLOCK(ah, chan))
600                 REG_WRITE_ARRAY(&ah->iniModesAdditional,
601                                 modesIndex, regWrites);
602
603         ar9003_hw_override_ini(ah);
604         ar9003_hw_set_channel_regs(ah, chan);
605         ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
606
607         /* Set TX power */
608         ah->eep_ops->set_txpower(ah, chan,
609                                  ath9k_regd_get_ctl(regulatory, chan),
610                                  channel->max_antenna_gain * 2,
611                                  channel->max_power * 2,
612                                  min((u32) MAX_RATE_POWER,
613                                  (u32) regulatory->power_limit));
614
615         return 0;
616 }
617
618 static void ar9003_hw_set_rfmode(struct ath_hw *ah,
619                                  struct ath9k_channel *chan)
620 {
621         u32 rfMode = 0;
622
623         if (chan == NULL)
624                 return;
625
626         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
627                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
628
629         if (IS_CHAN_A_FAST_CLOCK(ah, chan))
630                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
631
632         REG_WRITE(ah, AR_PHY_MODE, rfMode);
633 }
634
635 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
636 {
637         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
638 }
639
640 static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
641                                       struct ath9k_channel *chan)
642 {
643         u32 coef_scaled, ds_coef_exp, ds_coef_man;
644         u32 clockMhzScaled = 0x64000000;
645         struct chan_centers centers;
646
647         /*
648          * half and quarter rate can divide the scaled clock by 2 or 4
649          * scale for selected channel bandwidth
650          */
651         if (IS_CHAN_HALF_RATE(chan))
652                 clockMhzScaled = clockMhzScaled >> 1;
653         else if (IS_CHAN_QUARTER_RATE(chan))
654                 clockMhzScaled = clockMhzScaled >> 2;
655
656         /*
657          * ALGO -> coef = 1e8/fcarrier*fclock/40;
658          * scaled coef to provide precision for this floating calculation
659          */
660         ath9k_hw_get_channel_centers(ah, chan, &centers);
661         coef_scaled = clockMhzScaled / centers.synth_center;
662
663         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
664                                       &ds_coef_exp);
665
666         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
667                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
668         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
669                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
670
671         /*
672          * For Short GI,
673          * scaled coeff is 9/10 that of normal coeff
674          */
675         coef_scaled = (9 * coef_scaled) / 10;
676
677         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
678                                       &ds_coef_exp);
679
680         /* for short gi */
681         REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
682                       AR_PHY_SGI_DSC_MAN, ds_coef_man);
683         REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
684                       AR_PHY_SGI_DSC_EXP, ds_coef_exp);
685 }
686
687 static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
688 {
689         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
690         return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
691                              AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
692 }
693
694 /*
695  * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
696  * Read the phy active delay register. Value is in 100ns increments.
697  */
698 static void ar9003_hw_rfbus_done(struct ath_hw *ah)
699 {
700         u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
701         if (IS_CHAN_B(ah->curchan))
702                 synthDelay = (4 * synthDelay) / 22;
703         else
704                 synthDelay /= 10;
705
706         udelay(synthDelay + BASE_ACTIVATE_DELAY);
707
708         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
709 }
710
711 /*
712  * Set the interrupt and GPIO values so the ISR can disable RF
713  * on a switch signal.  Assumes GPIO port and interrupt polarity
714  * are set prior to call.
715  */
716 static void ar9003_hw_enable_rfkill(struct ath_hw *ah)
717 {
718         /* Connect rfsilent_bb_l to baseband */
719         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
720                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
721         /* Set input mux for rfsilent_bb_l to GPIO #0 */
722         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
723                     AR_GPIO_INPUT_MUX2_RFSILENT);
724
725         /*
726          * Configure the desired GPIO port for input and
727          * enable baseband rf silence.
728          */
729         ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
730         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
731 }
732
733 static void ar9003_hw_set_diversity(struct ath_hw *ah, bool value)
734 {
735         u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
736         if (value)
737                 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
738         else
739                 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
740         REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
741 }
742
743 static bool ar9003_hw_ani_control(struct ath_hw *ah,
744                                   enum ath9k_ani_cmd cmd, int param)
745 {
746         struct ar5416AniState *aniState = ah->curani;
747         struct ath_common *common = ath9k_hw_common(ah);
748         struct ath9k_channel *chan = ah->curchan;
749         s32 value, value2;
750
751         switch (cmd & ah->ani_function) {
752         case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
753                 /*
754                  * on == 1 means ofdm weak signal detection is ON
755                  * on == 1 is the default, for less noise immunity
756                  *
757                  * on == 0 means ofdm weak signal detection is OFF
758                  * on == 0 means more noise imm
759                  */
760                 u32 on = param ? 1 : 0;
761                 /*
762                  * make register setting for default
763                  * (weak sig detect ON) come from INI file
764                  */
765                 int m1ThreshLow = on ?
766                         aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
767                 int m2ThreshLow = on ?
768                         aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
769                 int m1Thresh = on ?
770                         aniState->iniDef.m1Thresh : m1Thresh_off;
771                 int m2Thresh = on ?
772                         aniState->iniDef.m2Thresh : m2Thresh_off;
773                 int m2CountThr = on ?
774                         aniState->iniDef.m2CountThr : m2CountThr_off;
775                 int m2CountThrLow = on ?
776                         aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
777                 int m1ThreshLowExt = on ?
778                         aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
779                 int m2ThreshLowExt = on ?
780                         aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
781                 int m1ThreshExt = on ?
782                         aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
783                 int m2ThreshExt = on ?
784                         aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
785
786                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
787                               AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
788                               m1ThreshLow);
789                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
790                               AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
791                               m2ThreshLow);
792                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
793                               AR_PHY_SFCORR_M1_THRESH, m1Thresh);
794                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
795                               AR_PHY_SFCORR_M2_THRESH, m2Thresh);
796                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
797                               AR_PHY_SFCORR_M2COUNT_THR, m2CountThr);
798                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
799                               AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
800                               m2CountThrLow);
801
802                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
803                               AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt);
804                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
805                               AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt);
806                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
807                               AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt);
808                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
809                               AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt);
810
811                 if (on)
812                         REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
813                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
814                 else
815                         REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
816                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
817
818                 if (!on != aniState->ofdmWeakSigDetectOff) {
819                         ath_print(common, ATH_DBG_ANI,
820                                   "** ch %d: ofdm weak signal: %s=>%s\n",
821                                   chan->channel,
822                                   !aniState->ofdmWeakSigDetectOff ?
823                                         "on" : "off",
824                                   on ? "on" : "off");
825                         if (on)
826                                 ah->stats.ast_ani_ofdmon++;
827                         else
828                                 ah->stats.ast_ani_ofdmoff++;
829                         aniState->ofdmWeakSigDetectOff = !on;
830                 }
831                 break;
832         }
833         case ATH9K_ANI_FIRSTEP_LEVEL:{
834                 u32 level = param;
835
836                 if (level >= ARRAY_SIZE(firstep_table)) {
837                         ath_print(common, ATH_DBG_ANI,
838                                   "ATH9K_ANI_FIRSTEP_LEVEL: level "
839                                   "out of range (%u > %u)\n",
840                                   level,
841                                   (unsigned) ARRAY_SIZE(firstep_table));
842                         return false;
843                 }
844
845                 /*
846                  * make register setting relative to default
847                  * from INI file & cap value
848                  */
849                 value = firstep_table[level] -
850                         firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
851                         aniState->iniDef.firstep;
852                 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
853                         value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
854                 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
855                         value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
856                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
857                               AR_PHY_FIND_SIG_FIRSTEP,
858                               value);
859                 /*
860                  * we need to set first step low register too
861                  * make register setting relative to default
862                  * from INI file & cap value
863                  */
864                 value2 = firstep_table[level] -
865                          firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
866                          aniState->iniDef.firstepLow;
867                 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
868                         value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
869                 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
870                         value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
871
872                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
873                               AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
874
875                 if (level != aniState->firstepLevel) {
876                         ath_print(common, ATH_DBG_ANI,
877                                   "** ch %d: level %d=>%d[def:%d] "
878                                   "firstep[level]=%d ini=%d\n",
879                                   chan->channel,
880                                   aniState->firstepLevel,
881                                   level,
882                                   ATH9K_ANI_FIRSTEP_LVL_NEW,
883                                   value,
884                                   aniState->iniDef.firstep);
885                         ath_print(common, ATH_DBG_ANI,
886                                   "** ch %d: level %d=>%d[def:%d] "
887                                   "firstep_low[level]=%d ini=%d\n",
888                                   chan->channel,
889                                   aniState->firstepLevel,
890                                   level,
891                                   ATH9K_ANI_FIRSTEP_LVL_NEW,
892                                   value2,
893                                   aniState->iniDef.firstepLow);
894                         if (level > aniState->firstepLevel)
895                                 ah->stats.ast_ani_stepup++;
896                         else if (level < aniState->firstepLevel)
897                                 ah->stats.ast_ani_stepdown++;
898                         aniState->firstepLevel = level;
899                 }
900                 break;
901         }
902         case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
903                 u32 level = param;
904
905                 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
906                         ath_print(common, ATH_DBG_ANI,
907                                   "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level "
908                                   "out of range (%u > %u)\n",
909                                   level,
910                                   (unsigned) ARRAY_SIZE(cycpwrThr1_table));
911                         return false;
912                 }
913                 /*
914                  * make register setting relative to default
915                  * from INI file & cap value
916                  */
917                 value = cycpwrThr1_table[level] -
918                         cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
919                         aniState->iniDef.cycpwrThr1;
920                 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
921                         value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
922                 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
923                         value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
924                 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
925                               AR_PHY_TIMING5_CYCPWR_THR1,
926                               value);
927
928                 /*
929                  * set AR_PHY_EXT_CCA for extension channel
930                  * make register setting relative to default
931                  * from INI file & cap value
932                  */
933                 value2 = cycpwrThr1_table[level] -
934                          cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
935                          aniState->iniDef.cycpwrThr1Ext;
936                 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
937                         value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
938                 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
939                         value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
940                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
941                               AR_PHY_EXT_CYCPWR_THR1, value2);
942
943                 if (level != aniState->spurImmunityLevel) {
944                         ath_print(common, ATH_DBG_ANI,
945                                   "** ch %d: level %d=>%d[def:%d] "
946                                   "cycpwrThr1[level]=%d ini=%d\n",
947                                   chan->channel,
948                                   aniState->spurImmunityLevel,
949                                   level,
950                                   ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
951                                   value,
952                                   aniState->iniDef.cycpwrThr1);
953                         ath_print(common, ATH_DBG_ANI,
954                                   "** ch %d: level %d=>%d[def:%d] "
955                                   "cycpwrThr1Ext[level]=%d ini=%d\n",
956                                   chan->channel,
957                                   aniState->spurImmunityLevel,
958                                   level,
959                                   ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
960                                   value2,
961                                   aniState->iniDef.cycpwrThr1Ext);
962                         if (level > aniState->spurImmunityLevel)
963                                 ah->stats.ast_ani_spurup++;
964                         else if (level < aniState->spurImmunityLevel)
965                                 ah->stats.ast_ani_spurdown++;
966                         aniState->spurImmunityLevel = level;
967                 }
968                 break;
969         }
970         case ATH9K_ANI_MRC_CCK:{
971                 /*
972                  * is_on == 1 means MRC CCK ON (default, less noise imm)
973                  * is_on == 0 means MRC CCK is OFF (more noise imm)
974                  */
975                 bool is_on = param ? 1 : 0;
976                 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
977                               AR_PHY_MRC_CCK_ENABLE, is_on);
978                 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
979                               AR_PHY_MRC_CCK_MUX_REG, is_on);
980                 if (!is_on != aniState->mrcCCKOff) {
981                         ath_print(common, ATH_DBG_ANI,
982                                   "** ch %d: MRC CCK: %s=>%s\n",
983                                   chan->channel,
984                                   !aniState->mrcCCKOff ? "on" : "off",
985                                   is_on ? "on" : "off");
986                 if (is_on)
987                         ah->stats.ast_ani_ccklow++;
988                 else
989                         ah->stats.ast_ani_cckhigh++;
990                 aniState->mrcCCKOff = !is_on;
991                 }
992         break;
993         }
994         case ATH9K_ANI_PRESENT:
995                 break;
996         default:
997                 ath_print(common, ATH_DBG_ANI,
998                           "invalid cmd %u\n", cmd);
999                 return false;
1000         }
1001
1002         ath_print(common, ATH_DBG_ANI,
1003                   "ANI parameters: SI=%d, ofdmWS=%s FS=%d "
1004                   "MRCcck=%s listenTime=%d CC=%d listen=%d "
1005                   "ofdmErrs=%d cckErrs=%d\n",
1006                   aniState->spurImmunityLevel,
1007                   !aniState->ofdmWeakSigDetectOff ? "on" : "off",
1008                   aniState->firstepLevel,
1009                   !aniState->mrcCCKOff ? "on" : "off",
1010                   aniState->listenTime,
1011                   aniState->cycleCount,
1012                   aniState->listenTime,
1013                   aniState->ofdmPhyErrCount,
1014                   aniState->cckPhyErrCount);
1015         return true;
1016 }
1017
1018 static void ar9003_hw_do_getnf(struct ath_hw *ah,
1019                               int16_t nfarray[NUM_NF_READINGS])
1020 {
1021         struct ath_common *common = ath9k_hw_common(ah);
1022         int16_t nf;
1023
1024         nf = MS(REG_READ(ah, AR_PHY_CCA_0), AR_PHY_MINCCA_PWR);
1025         if (nf & 0x100)
1026                 nf = 0 - ((nf ^ 0x1ff) + 1);
1027         ath_print(common, ATH_DBG_CALIBRATE,
1028                   "NF calibrated [ctl] [chain 0] is %d\n", nf);
1029         nfarray[0] = nf;
1030
1031         nf = MS(REG_READ(ah, AR_PHY_CCA_1), AR_PHY_CH1_MINCCA_PWR);
1032         if (nf & 0x100)
1033                 nf = 0 - ((nf ^ 0x1ff) + 1);
1034         ath_print(common, ATH_DBG_CALIBRATE,
1035                   "NF calibrated [ctl] [chain 1] is %d\n", nf);
1036         nfarray[1] = nf;
1037
1038         nf = MS(REG_READ(ah, AR_PHY_CCA_2), AR_PHY_CH2_MINCCA_PWR);
1039         if (nf & 0x100)
1040                 nf = 0 - ((nf ^ 0x1ff) + 1);
1041         ath_print(common, ATH_DBG_CALIBRATE,
1042                   "NF calibrated [ctl] [chain 2] is %d\n", nf);
1043         nfarray[2] = nf;
1044
1045         nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
1046         if (nf & 0x100)
1047                 nf = 0 - ((nf ^ 0x1ff) + 1);
1048         ath_print(common, ATH_DBG_CALIBRATE,
1049                   "NF calibrated [ext] [chain 0] is %d\n", nf);
1050         nfarray[3] = nf;
1051
1052         nf = MS(REG_READ(ah, AR_PHY_EXT_CCA_1), AR_PHY_CH1_EXT_MINCCA_PWR);
1053         if (nf & 0x100)
1054                 nf = 0 - ((nf ^ 0x1ff) + 1);
1055         ath_print(common, ATH_DBG_CALIBRATE,
1056                   "NF calibrated [ext] [chain 1] is %d\n", nf);
1057         nfarray[4] = nf;
1058
1059         nf = MS(REG_READ(ah, AR_PHY_EXT_CCA_2), AR_PHY_CH2_EXT_MINCCA_PWR);
1060         if (nf & 0x100)
1061                 nf = 0 - ((nf ^ 0x1ff) + 1);
1062         ath_print(common, ATH_DBG_CALIBRATE,
1063                   "NF calibrated [ext] [chain 2] is %d\n", nf);
1064         nfarray[5] = nf;
1065 }
1066
1067 static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
1068 {
1069         ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1070         ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
1071         ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
1072         ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1073         ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1074         ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
1075 }
1076
1077 /*
1078  * Find out which of the RX chains are enabled
1079  */
1080 static u32 ar9003_hw_get_rx_chainmask(struct ath_hw *ah)
1081 {
1082         u32 chain = REG_READ(ah, AR_PHY_RX_CHAINMASK);
1083         /*
1084          * The bits [2:0] indicate the rx chain mask and are to be
1085          * interpreted as follows:
1086          * 00x => Only chain 0 is enabled
1087          * 01x => Chain 1 and 0 enabled
1088          * 1xx => Chain 2,1 and 0 enabled
1089          */
1090         return chain & 0x7;
1091 }
1092
1093 static void ar9003_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
1094 {
1095         struct ath9k_nfcal_hist *h;
1096         unsigned i, j;
1097         int32_t val;
1098         const u32 ar9300_cca_regs[6] = {
1099                 AR_PHY_CCA_0,
1100                 AR_PHY_CCA_1,
1101                 AR_PHY_CCA_2,
1102                 AR_PHY_EXT_CCA,
1103                 AR_PHY_EXT_CCA_1,
1104                 AR_PHY_EXT_CCA_2,
1105         };
1106         u8 chainmask, rx_chain_status;
1107         struct ath_common *common = ath9k_hw_common(ah);
1108
1109         rx_chain_status = ar9003_hw_get_rx_chainmask(ah);
1110
1111         chainmask = 0x3F;
1112         h = ah->nfCalHist;
1113
1114         for (i = 0; i < NUM_NF_READINGS; i++) {
1115                 if (chainmask & (1 << i)) {
1116                         val = REG_READ(ah, ar9300_cca_regs[i]);
1117                         val &= 0xFFFFFE00;
1118                         val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
1119                         REG_WRITE(ah, ar9300_cca_regs[i], val);
1120                 }
1121         }
1122
1123         /*
1124          * Load software filtered NF value into baseband internal minCCApwr
1125          * variable.
1126          */
1127         REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1128                     AR_PHY_AGC_CONTROL_ENABLE_NF);
1129         REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1130                     AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
1131         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
1132
1133         /*
1134          * Wait for load to complete, should be fast, a few 10s of us.
1135          * The max delay was changed from an original 250us to 10000us
1136          * since 250us often results in NF load timeout and causes deaf
1137          * condition during stress testing 12/12/2009
1138          */
1139         for (j = 0; j < 1000; j++) {
1140                 if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
1141                      AR_PHY_AGC_CONTROL_NF) == 0)
1142                         break;
1143                 udelay(10);
1144         }
1145
1146         /*
1147          * We timed out waiting for the noisefloor to load, probably due to an
1148          * in-progress rx. Simply return here and allow the load plenty of time
1149          * to complete before the next calibration interval.  We need to avoid
1150          * trying to load -50 (which happens below) while the previous load is
1151          * still in progress as this can cause rx deafness. Instead by returning
1152          * here, the baseband nf cal will just be capped by our present
1153          * noisefloor until the next calibration timer.
1154          */
1155         if (j == 1000) {
1156                 ath_print(common, ATH_DBG_ANY, "Timeout while waiting for nf "
1157                           "to load: AR_PHY_AGC_CONTROL=0x%x\n",
1158                           REG_READ(ah, AR_PHY_AGC_CONTROL));
1159                 return;
1160         }
1161
1162         /*
1163          * Restore maxCCAPower register parameter again so that we're not capped
1164          * by the median we just loaded.  This will be initial (and max) value
1165          * of next noise floor calibration the baseband does.
1166          */
1167         for (i = 0; i < NUM_NF_READINGS; i++) {
1168                 if (chainmask & (1 << i)) {
1169                         val = REG_READ(ah, ar9300_cca_regs[i]);
1170                         val &= 0xFFFFFE00;
1171                         val |= (((u32) (-50) << 1) & 0x1ff);
1172                         REG_WRITE(ah, ar9300_cca_regs[i], val);
1173                 }
1174         }
1175 }
1176
1177 /*
1178  * Initialize the ANI register values with default (ini) values.
1179  * This routine is called during a (full) hardware reset after
1180  * all the registers are initialised from the INI.
1181  */
1182 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1183 {
1184         struct ar5416AniState *aniState;
1185         struct ath_common *common = ath9k_hw_common(ah);
1186         struct ath9k_channel *chan = ah->curchan;
1187         struct ath9k_ani_default *iniDef;
1188         int index;
1189         u32 val;
1190
1191         index = ath9k_hw_get_ani_channel_idx(ah, chan);
1192         aniState = &ah->ani[index];
1193         ah->curani = aniState;
1194         iniDef = &aniState->iniDef;
1195
1196         ath_print(common, ATH_DBG_ANI,
1197                   "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
1198                   ah->hw_version.macVersion,
1199                   ah->hw_version.macRev,
1200                   ah->opmode,
1201                   chan->channel,
1202                   chan->channelFlags);
1203
1204         val = REG_READ(ah, AR_PHY_SFCORR);
1205         iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1206         iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1207         iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1208
1209         val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1210         iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1211         iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1212         iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1213
1214         val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1215         iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1216         iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1217         iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1218         iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1219         iniDef->firstep = REG_READ_FIELD(ah,
1220                                          AR_PHY_FIND_SIG,
1221                                          AR_PHY_FIND_SIG_FIRSTEP);
1222         iniDef->firstepLow = REG_READ_FIELD(ah,
1223                                             AR_PHY_FIND_SIG_LOW,
1224                                             AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1225         iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1226                                             AR_PHY_TIMING5,
1227                                             AR_PHY_TIMING5_CYCPWR_THR1);
1228         iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1229                                                AR_PHY_EXT_CCA,
1230                                                AR_PHY_EXT_CYCPWR_THR1);
1231
1232         /* these levels just got reset to defaults by the INI */
1233         aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
1234         aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
1235         aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG;
1236         aniState->mrcCCKOff = !ATH9K_ANI_ENABLE_MRC_CCK;
1237
1238         aniState->cycleCount = 0;
1239 }
1240
1241 void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1242 {
1243         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1244
1245         priv_ops->rf_set_freq = ar9003_hw_set_channel;
1246         priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
1247         priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
1248         priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
1249         priv_ops->init_bb = ar9003_hw_init_bb;
1250         priv_ops->process_ini = ar9003_hw_process_ini;
1251         priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1252         priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
1253         priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1254         priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1255         priv_ops->rfbus_done = ar9003_hw_rfbus_done;
1256         priv_ops->enable_rfkill = ar9003_hw_enable_rfkill;
1257         priv_ops->set_diversity = ar9003_hw_set_diversity;
1258         priv_ops->ani_control = ar9003_hw_ani_control;
1259         priv_ops->do_getnf = ar9003_hw_do_getnf;
1260         priv_ops->loadnf = ar9003_hw_loadnf;
1261         priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
1262
1263         ar9003_hw_set_nf_limits(ah);
1264 }
1265
1266 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
1267 {
1268         struct ath_common *common = ath9k_hw_common(ah);
1269         u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms;
1270         u32 val, idle_count;
1271
1272         if (!idle_tmo_ms) {
1273                 /* disable IRQ, disable chip-reset for BB panic */
1274                 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1275                           REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &
1276                           ~(AR_PHY_WATCHDOG_RST_ENABLE |
1277                             AR_PHY_WATCHDOG_IRQ_ENABLE));
1278
1279                 /* disable watchdog in non-IDLE mode, disable in IDLE mode */
1280                 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1281                           REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &
1282                           ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1283                             AR_PHY_WATCHDOG_IDLE_ENABLE));
1284
1285                 ath_print(common, ATH_DBG_RESET, "Disabled BB Watchdog\n");
1286                 return;
1287         }
1288
1289         /* enable IRQ, disable chip-reset for BB watchdog */
1290         val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;
1291         REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1292                   (val | AR_PHY_WATCHDOG_IRQ_ENABLE) &
1293                   ~AR_PHY_WATCHDOG_RST_ENABLE);
1294
1295         /* bound limit to 10 secs */
1296         if (idle_tmo_ms > 10000)
1297                 idle_tmo_ms = 10000;
1298
1299         /*
1300          * The time unit for watchdog event is 2^15 44/88MHz cycles.
1301          *
1302          * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick
1303          * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick
1304          *
1305          * Given we use fast clock now in 5 GHz, these time units should
1306          * be common for both 2 GHz and 5 GHz.
1307          */
1308         idle_count = (100 * idle_tmo_ms) / 74;
1309         if (ah->curchan && IS_CHAN_HT40(ah->curchan))
1310                 idle_count = (100 * idle_tmo_ms) / 37;
1311
1312         /*
1313          * enable watchdog in non-IDLE mode, disable in IDLE mode,
1314          * set idle time-out.
1315          */
1316         REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1317                   AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1318                   AR_PHY_WATCHDOG_IDLE_MASK |
1319                   (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
1320
1321         ath_print(common, ATH_DBG_RESET,
1322                   "Enabled BB Watchdog timeout (%u ms)\n",
1323                   idle_tmo_ms);
1324 }
1325
1326 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
1327 {
1328         /*
1329          * we want to avoid printing in ISR context so we save the
1330          * watchdog status to be printed later in bottom half context.
1331          */
1332         ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);
1333
1334         /*
1335          * the watchdog timer should reset on status read but to be sure
1336          * sure we write 0 to the watchdog status bit.
1337          */
1338         REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
1339                   ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR);
1340 }
1341
1342 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
1343 {
1344         struct ath_common *common = ath9k_hw_common(ah);
1345         u32 rxc_pcnt = 0, rxf_pcnt = 0, txf_pcnt = 0, status;
1346
1347         if (likely(!(common->debug_mask & ATH_DBG_RESET)))
1348                 return;
1349
1350         status = ah->bb_watchdog_last_status;
1351         ath_print(common, ATH_DBG_RESET,
1352                   "\n==== BB update: BB status=0x%08x ====\n", status);
1353         ath_print(common, ATH_DBG_RESET,
1354                   "** BB state: wd=%u det=%u rdar=%u rOFDM=%d "
1355                   "rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1356                   MS(status, AR_PHY_WATCHDOG_INFO),
1357                   MS(status, AR_PHY_WATCHDOG_DET_HANG),
1358                   MS(status, AR_PHY_WATCHDOG_RADAR_SM),
1359                   MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
1360                   MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
1361                   MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
1362                   MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
1363                   MS(status, AR_PHY_WATCHDOG_AGC_SM),
1364                   MS(status,AR_PHY_WATCHDOG_SRCH_SM));
1365
1366         ath_print(common, ATH_DBG_RESET,
1367                   "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
1368                   REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
1369                   REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
1370         ath_print(common, ATH_DBG_RESET,
1371                   "** BB mode: BB_gen_controls=0x%08x **\n",
1372                   REG_READ(ah, AR_PHY_GEN_CTRL));
1373
1374         if (ath9k_hw_GetMibCycleCountsPct(ah, &rxc_pcnt, &rxf_pcnt, &txf_pcnt))
1375                 ath_print(common, ATH_DBG_RESET,
1376                           "** BB busy times: rx_clear=%d%%, "
1377                           "rx_frame=%d%%, tx_frame=%d%% **\n",
1378                           rxc_pcnt, rxf_pcnt, txf_pcnt);
1379
1380         ath_print(common, ATH_DBG_RESET,
1381                   "==== BB update: done ====\n\n");
1382 }
1383 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);