ath9k_hw: move the cycle counter tracking to ath
[linux-2.6.git] / drivers / net / wireless / ath / ath9k / ar9003_phy.c
1 /*
2  * Copyright (c) 2010 Atheros Communications Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16
17 #include "hw.h"
18 #include "ar9003_phy.h"
19
20 static const int firstep_table[] =
21 /* level:  0   1   2   3   4   5   6   7   8  */
22         { -4, -2,  0,  2,  4,  6,  8, 10, 12 }; /* lvl 0-8, default 2 */
23
24 static const int cycpwrThr1_table[] =
25 /* level:  0   1   2   3   4   5   6   7   8  */
26         { -6, -4, -2,  0,  2,  4,  6,  8 };     /* lvl 0-7, default 3 */
27
28 /*
29  * register values to turn OFDM weak signal detection OFF
30  */
31 static const int m1ThreshLow_off = 127;
32 static const int m2ThreshLow_off = 127;
33 static const int m1Thresh_off = 127;
34 static const int m2Thresh_off = 127;
35 static const int m2CountThr_off =  31;
36 static const int m2CountThrLow_off =  63;
37 static const int m1ThreshLowExt_off = 127;
38 static const int m2ThreshLowExt_off = 127;
39 static const int m1ThreshExt_off = 127;
40 static const int m2ThreshExt_off = 127;
41
42 /**
43  * ar9003_hw_set_channel - set channel on single-chip device
44  * @ah: atheros hardware structure
45  * @chan:
46  *
47  * This is the function to change channel on single-chip devices, that is
48  * all devices after ar9280.
49  *
50  * This function takes the channel value in MHz and sets
51  * hardware channel value. Assumes writes have been enabled to analog bus.
52  *
53  * Actual Expression,
54  *
55  * For 2GHz channel,
56  * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
57  * (freq_ref = 40MHz)
58  *
59  * For 5GHz channel,
60  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
61  * (freq_ref = 40MHz/(24>>amodeRefSel))
62  *
63  * For 5GHz channels which are 5MHz spaced,
64  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
65  * (freq_ref = 40MHz)
66  */
67 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
68 {
69         u16 bMode, fracMode = 0, aModeRefSel = 0;
70         u32 freq, channelSel = 0, reg32 = 0;
71         struct chan_centers centers;
72         int loadSynthChannel;
73
74         ath9k_hw_get_channel_centers(ah, chan, &centers);
75         freq = centers.synth_center;
76
77         if (freq < 4800) {     /* 2 GHz, fractional mode */
78                 channelSel = CHANSEL_2G(freq);
79                 /* Set to 2G mode */
80                 bMode = 1;
81         } else {
82                 channelSel = CHANSEL_5G(freq);
83                 /* Doubler is ON, so, divide channelSel by 2. */
84                 channelSel >>= 1;
85                 /* Set to 5G mode */
86                 bMode = 0;
87         }
88
89         /* Enable fractional mode for all channels */
90         fracMode = 1;
91         aModeRefSel = 0;
92         loadSynthChannel = 0;
93
94         reg32 = (bMode << 29);
95         REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
96
97         /* Enable Long shift Select for Synthesizer */
98         REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
99                       AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
100
101         /* Program Synth. setting */
102         reg32 = (channelSel << 2) | (fracMode << 30) |
103                 (aModeRefSel << 28) | (loadSynthChannel << 31);
104         REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
105
106         /* Toggle Load Synth channel bit */
107         loadSynthChannel = 1;
108         reg32 = (channelSel << 2) | (fracMode << 30) |
109                 (aModeRefSel << 28) | (loadSynthChannel << 31);
110         REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
111
112         ah->curchan = chan;
113         ah->curchan_rad_index = -1;
114
115         return 0;
116 }
117
118 /**
119  * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
120  * @ah: atheros hardware structure
121  * @chan:
122  *
123  * For single-chip solutions. Converts to baseband spur frequency given the
124  * input channel frequency and compute register settings below.
125  *
126  * Spur mitigation for MRC CCK
127  */
128 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
129                                             struct ath9k_channel *chan)
130 {
131         u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
132         int cur_bb_spur, negative = 0, cck_spur_freq;
133         int i;
134
135         /*
136          * Need to verify range +/- 10 MHz in control channel, otherwise spur
137          * is out-of-band and can be ignored.
138          */
139
140         for (i = 0; i < 4; i++) {
141                 negative = 0;
142                 cur_bb_spur = spur_freq[i] - chan->channel;
143
144                 if (cur_bb_spur < 0) {
145                         negative = 1;
146                         cur_bb_spur = -cur_bb_spur;
147                 }
148                 if (cur_bb_spur < 10) {
149                         cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
150
151                         if (negative == 1)
152                                 cck_spur_freq = -cck_spur_freq;
153
154                         cck_spur_freq = cck_spur_freq & 0xfffff;
155
156                         REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
157                                       AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
158                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
159                                       AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
160                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
161                                       AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
162                                       0x2);
163                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
164                                       AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
165                                       0x1);
166                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
167                                       AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
168                                       cck_spur_freq);
169
170                         return;
171                 }
172         }
173
174         REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
175                       AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
176         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
177                       AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
178         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
179                       AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
180 }
181
182 /* Clean all spur register fields */
183 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
184 {
185         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
186                       AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
187         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
188                       AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
189         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
190                       AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
191         REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
192                       AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
193         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
194                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
195         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
196                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
197         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
198                       AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
199         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
200                       AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
201         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
202                       AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
203
204         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
205                       AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
206         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
207                       AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
208         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
209                       AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
210         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
211                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
212         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
213                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
214         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
215                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
216         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
217                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
218         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
219                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
220         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
221                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
222         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
223                       AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
224 }
225
226 static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
227                                 int freq_offset,
228                                 int spur_freq_sd,
229                                 int spur_delta_phase,
230                                 int spur_subchannel_sd)
231 {
232         int mask_index = 0;
233
234         /* OFDM Spur mitigation */
235         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
236                  AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
237         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
238                       AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
239         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
240                       AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
241         REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
242                       AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
243         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
244                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
245         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
246                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
247         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
248                       AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
249         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
250                       AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
251         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
252                       AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
253
254         if (REG_READ_FIELD(ah, AR_PHY_MODE,
255                            AR_PHY_MODE_DYNAMIC) == 0x1)
256                 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
257                               AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
258
259         mask_index = (freq_offset << 4) / 5;
260         if (mask_index < 0)
261                 mask_index = mask_index - 1;
262
263         mask_index = mask_index & 0x7f;
264
265         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
266                       AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
267         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
268                       AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
269         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
270                       AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
271         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
272                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
273         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
274                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
275         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
276                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
277         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
278                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
279         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
280                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
281         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
282                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
283         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
284                       AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
285 }
286
287 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
288                                      struct ath9k_channel *chan,
289                                      int freq_offset)
290 {
291         int spur_freq_sd = 0;
292         int spur_subchannel_sd = 0;
293         int spur_delta_phase = 0;
294
295         if (IS_CHAN_HT40(chan)) {
296                 if (freq_offset < 0) {
297                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
298                                            AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
299                                 spur_subchannel_sd = 1;
300                         else
301                                 spur_subchannel_sd = 0;
302
303                         spur_freq_sd = ((freq_offset + 10) << 9) / 11;
304
305                 } else {
306                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
307                             AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
308                                 spur_subchannel_sd = 0;
309                         else
310                                 spur_subchannel_sd = 1;
311
312                         spur_freq_sd = ((freq_offset - 10) << 9) / 11;
313
314                 }
315
316                 spur_delta_phase = (freq_offset << 17) / 5;
317
318         } else {
319                 spur_subchannel_sd = 0;
320                 spur_freq_sd = (freq_offset << 9) /11;
321                 spur_delta_phase = (freq_offset << 18) / 5;
322         }
323
324         spur_freq_sd = spur_freq_sd & 0x3ff;
325         spur_delta_phase = spur_delta_phase & 0xfffff;
326
327         ar9003_hw_spur_ofdm(ah,
328                             freq_offset,
329                             spur_freq_sd,
330                             spur_delta_phase,
331                             spur_subchannel_sd);
332 }
333
334 /* Spur mitigation for OFDM */
335 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
336                                          struct ath9k_channel *chan)
337 {
338         int synth_freq;
339         int range = 10;
340         int freq_offset = 0;
341         int mode;
342         u8* spurChansPtr;
343         unsigned int i;
344         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
345
346         if (IS_CHAN_5GHZ(chan)) {
347                 spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
348                 mode = 0;
349         }
350         else {
351                 spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
352                 mode = 1;
353         }
354
355         if (spurChansPtr[0] == 0)
356                 return; /* No spur in the mode */
357
358         if (IS_CHAN_HT40(chan)) {
359                 range = 19;
360                 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
361                                    AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
362                         synth_freq = chan->channel - 10;
363                 else
364                         synth_freq = chan->channel + 10;
365         } else {
366                 range = 10;
367                 synth_freq = chan->channel;
368         }
369
370         ar9003_hw_spur_ofdm_clear(ah);
371
372         for (i = 0; spurChansPtr[i] && i < 5; i++) {
373                 freq_offset = FBIN2FREQ(spurChansPtr[i], mode) - synth_freq;
374                 if (abs(freq_offset) < range) {
375                         ar9003_hw_spur_ofdm_work(ah, chan, freq_offset);
376                         break;
377                 }
378         }
379 }
380
381 static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
382                                     struct ath9k_channel *chan)
383 {
384         ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
385         ar9003_hw_spur_mitigate_ofdm(ah, chan);
386 }
387
388 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
389                                          struct ath9k_channel *chan)
390 {
391         u32 pll;
392
393         pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
394
395         if (chan && IS_CHAN_HALF_RATE(chan))
396                 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
397         else if (chan && IS_CHAN_QUARTER_RATE(chan))
398                 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
399
400         pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
401
402         return pll;
403 }
404
405 static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
406                                        struct ath9k_channel *chan)
407 {
408         u32 phymode;
409         u32 enableDacFifo = 0;
410
411         enableDacFifo =
412                 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
413
414         /* Enable 11n HT, 20 MHz */
415         phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 | AR_PHY_GC_WALSH |
416                   AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
417
418         /* Configure baseband for dynamic 20/40 operation */
419         if (IS_CHAN_HT40(chan)) {
420                 phymode |= AR_PHY_GC_DYN2040_EN;
421                 /* Configure control (primary) channel at +-10MHz */
422                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
423                     (chan->chanmode == CHANNEL_G_HT40PLUS))
424                         phymode |= AR_PHY_GC_DYN2040_PRI_CH;
425
426         }
427
428         /* make sure we preserve INI settings */
429         phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
430         /* turn off Green Field detection for STA for now */
431         phymode &= ~AR_PHY_GC_GF_DETECT_EN;
432
433         REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
434
435         /* Configure MAC for 20/40 operation */
436         ath9k_hw_set11nmac2040(ah);
437
438         /* global transmit timeout (25 TUs default)*/
439         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
440         /* carrier sense timeout */
441         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
442 }
443
444 static void ar9003_hw_init_bb(struct ath_hw *ah,
445                               struct ath9k_channel *chan)
446 {
447         u32 synthDelay;
448
449         /*
450          * Wait for the frequency synth to settle (synth goes on
451          * via AR_PHY_ACTIVE_EN).  Read the phy active delay register.
452          * Value is in 100ns increments.
453          */
454         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
455         if (IS_CHAN_B(chan))
456                 synthDelay = (4 * synthDelay) / 22;
457         else
458                 synthDelay /= 10;
459
460         /* Activate the PHY (includes baseband activate + synthesizer on) */
461         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
462
463         /*
464          * There is an issue if the AP starts the calibration before
465          * the base band timeout completes.  This could result in the
466          * rx_clear false triggering.  As a workaround we add delay an
467          * extra BASE_ACTIVATE_DELAY usecs to ensure this condition
468          * does not happen.
469          */
470         udelay(synthDelay + BASE_ACTIVATE_DELAY);
471 }
472
473 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
474 {
475         switch (rx) {
476         case 0x5:
477                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
478                             AR_PHY_SWAP_ALT_CHAIN);
479         case 0x3:
480         case 0x1:
481         case 0x2:
482         case 0x7:
483                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
484                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
485                 break;
486         default:
487                 break;
488         }
489
490         REG_WRITE(ah, AR_SELFGEN_MASK, tx);
491         if (tx == 0x5) {
492                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
493                             AR_PHY_SWAP_ALT_CHAIN);
494         }
495 }
496
497 /*
498  * Override INI values with chip specific configuration.
499  */
500 static void ar9003_hw_override_ini(struct ath_hw *ah)
501 {
502         u32 val;
503
504         /*
505          * Set the RX_ABORT and RX_DIS and clear it only after
506          * RXE is set for MAC. This prevents frames with
507          * corrupted descriptor status.
508          */
509         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
510
511         /*
512          * For AR9280 and above, there is a new feature that allows
513          * Multicast search based on both MAC Address and Key ID. By default,
514          * this feature is enabled. But since the driver is not using this
515          * feature, we switch it off; otherwise multicast search based on
516          * MAC addr only will fail.
517          */
518         val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
519         REG_WRITE(ah, AR_PCU_MISC_MODE2,
520                   val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE);
521 }
522
523 static void ar9003_hw_prog_ini(struct ath_hw *ah,
524                                struct ar5416IniArray *iniArr,
525                                int column)
526 {
527         unsigned int i, regWrites = 0;
528
529         /* New INI format: Array may be undefined (pre, core, post arrays) */
530         if (!iniArr->ia_array)
531                 return;
532
533         /*
534          * New INI format: Pre, core, and post arrays for a given subsystem
535          * may be modal (> 2 columns) or non-modal (2 columns). Determine if
536          * the array is non-modal and force the column to 1.
537          */
538         if (column >= iniArr->ia_columns)
539                 column = 1;
540
541         for (i = 0; i < iniArr->ia_rows; i++) {
542                 u32 reg = INI_RA(iniArr, i, 0);
543                 u32 val = INI_RA(iniArr, i, column);
544
545                 if (reg >= 0x16000 && reg < 0x17000)
546                         ath9k_hw_analog_shift_regwrite(ah, reg, val);
547                 else
548                         REG_WRITE(ah, reg, val);
549
550                 DO_DELAY(regWrites);
551         }
552 }
553
554 static int ar9003_hw_process_ini(struct ath_hw *ah,
555                                  struct ath9k_channel *chan)
556 {
557         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
558         unsigned int regWrites = 0, i;
559         struct ieee80211_channel *channel = chan->chan;
560         u32 modesIndex, freqIndex;
561
562         switch (chan->chanmode) {
563         case CHANNEL_A:
564         case CHANNEL_A_HT20:
565                 modesIndex = 1;
566                 freqIndex = 1;
567                 break;
568         case CHANNEL_A_HT40PLUS:
569         case CHANNEL_A_HT40MINUS:
570                 modesIndex = 2;
571                 freqIndex = 1;
572                 break;
573         case CHANNEL_G:
574         case CHANNEL_G_HT20:
575         case CHANNEL_B:
576                 modesIndex = 4;
577                 freqIndex = 2;
578                 break;
579         case CHANNEL_G_HT40PLUS:
580         case CHANNEL_G_HT40MINUS:
581                 modesIndex = 3;
582                 freqIndex = 2;
583                 break;
584
585         default:
586                 return -EINVAL;
587         }
588
589         for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
590                 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
591                 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
592                 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
593                 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
594         }
595
596         REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
597         REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
598
599         /*
600          * For 5GHz channels requiring Fast Clock, apply
601          * different modal values.
602          */
603         if (IS_CHAN_A_FAST_CLOCK(ah, chan))
604                 REG_WRITE_ARRAY(&ah->iniModesAdditional,
605                                 modesIndex, regWrites);
606
607         ar9003_hw_override_ini(ah);
608         ar9003_hw_set_channel_regs(ah, chan);
609         ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
610
611         /* Set TX power */
612         ah->eep_ops->set_txpower(ah, chan,
613                                  ath9k_regd_get_ctl(regulatory, chan),
614                                  channel->max_antenna_gain * 2,
615                                  channel->max_power * 2,
616                                  min((u32) MAX_RATE_POWER,
617                                  (u32) regulatory->power_limit));
618
619         return 0;
620 }
621
622 static void ar9003_hw_set_rfmode(struct ath_hw *ah,
623                                  struct ath9k_channel *chan)
624 {
625         u32 rfMode = 0;
626
627         if (chan == NULL)
628                 return;
629
630         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
631                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
632
633         if (IS_CHAN_A_FAST_CLOCK(ah, chan))
634                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
635
636         REG_WRITE(ah, AR_PHY_MODE, rfMode);
637 }
638
639 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
640 {
641         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
642 }
643
644 static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
645                                       struct ath9k_channel *chan)
646 {
647         u32 coef_scaled, ds_coef_exp, ds_coef_man;
648         u32 clockMhzScaled = 0x64000000;
649         struct chan_centers centers;
650
651         /*
652          * half and quarter rate can divide the scaled clock by 2 or 4
653          * scale for selected channel bandwidth
654          */
655         if (IS_CHAN_HALF_RATE(chan))
656                 clockMhzScaled = clockMhzScaled >> 1;
657         else if (IS_CHAN_QUARTER_RATE(chan))
658                 clockMhzScaled = clockMhzScaled >> 2;
659
660         /*
661          * ALGO -> coef = 1e8/fcarrier*fclock/40;
662          * scaled coef to provide precision for this floating calculation
663          */
664         ath9k_hw_get_channel_centers(ah, chan, &centers);
665         coef_scaled = clockMhzScaled / centers.synth_center;
666
667         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
668                                       &ds_coef_exp);
669
670         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
671                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
672         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
673                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
674
675         /*
676          * For Short GI,
677          * scaled coeff is 9/10 that of normal coeff
678          */
679         coef_scaled = (9 * coef_scaled) / 10;
680
681         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
682                                       &ds_coef_exp);
683
684         /* for short gi */
685         REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
686                       AR_PHY_SGI_DSC_MAN, ds_coef_man);
687         REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
688                       AR_PHY_SGI_DSC_EXP, ds_coef_exp);
689 }
690
691 static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
692 {
693         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
694         return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
695                              AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
696 }
697
698 /*
699  * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
700  * Read the phy active delay register. Value is in 100ns increments.
701  */
702 static void ar9003_hw_rfbus_done(struct ath_hw *ah)
703 {
704         u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
705         if (IS_CHAN_B(ah->curchan))
706                 synthDelay = (4 * synthDelay) / 22;
707         else
708                 synthDelay /= 10;
709
710         udelay(synthDelay + BASE_ACTIVATE_DELAY);
711
712         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
713 }
714
715 /*
716  * Set the interrupt and GPIO values so the ISR can disable RF
717  * on a switch signal.  Assumes GPIO port and interrupt polarity
718  * are set prior to call.
719  */
720 static void ar9003_hw_enable_rfkill(struct ath_hw *ah)
721 {
722         /* Connect rfsilent_bb_l to baseband */
723         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
724                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
725         /* Set input mux for rfsilent_bb_l to GPIO #0 */
726         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
727                     AR_GPIO_INPUT_MUX2_RFSILENT);
728
729         /*
730          * Configure the desired GPIO port for input and
731          * enable baseband rf silence.
732          */
733         ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
734         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
735 }
736
737 static void ar9003_hw_set_diversity(struct ath_hw *ah, bool value)
738 {
739         u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
740         if (value)
741                 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
742         else
743                 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
744         REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
745 }
746
747 static bool ar9003_hw_ani_control(struct ath_hw *ah,
748                                   enum ath9k_ani_cmd cmd, int param)
749 {
750         struct ath_common *common = ath9k_hw_common(ah);
751         struct ath9k_channel *chan = ah->curchan;
752         struct ar5416AniState *aniState = &chan->ani;
753         s32 value, value2;
754
755         switch (cmd & ah->ani_function) {
756         case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
757                 /*
758                  * on == 1 means ofdm weak signal detection is ON
759                  * on == 1 is the default, for less noise immunity
760                  *
761                  * on == 0 means ofdm weak signal detection is OFF
762                  * on == 0 means more noise imm
763                  */
764                 u32 on = param ? 1 : 0;
765                 /*
766                  * make register setting for default
767                  * (weak sig detect ON) come from INI file
768                  */
769                 int m1ThreshLow = on ?
770                         aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
771                 int m2ThreshLow = on ?
772                         aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
773                 int m1Thresh = on ?
774                         aniState->iniDef.m1Thresh : m1Thresh_off;
775                 int m2Thresh = on ?
776                         aniState->iniDef.m2Thresh : m2Thresh_off;
777                 int m2CountThr = on ?
778                         aniState->iniDef.m2CountThr : m2CountThr_off;
779                 int m2CountThrLow = on ?
780                         aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
781                 int m1ThreshLowExt = on ?
782                         aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
783                 int m2ThreshLowExt = on ?
784                         aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
785                 int m1ThreshExt = on ?
786                         aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
787                 int m2ThreshExt = on ?
788                         aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
789
790                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
791                               AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
792                               m1ThreshLow);
793                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
794                               AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
795                               m2ThreshLow);
796                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
797                               AR_PHY_SFCORR_M1_THRESH, m1Thresh);
798                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
799                               AR_PHY_SFCORR_M2_THRESH, m2Thresh);
800                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
801                               AR_PHY_SFCORR_M2COUNT_THR, m2CountThr);
802                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
803                               AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
804                               m2CountThrLow);
805
806                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
807                               AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt);
808                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
809                               AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt);
810                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
811                               AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt);
812                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
813                               AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt);
814
815                 if (on)
816                         REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
817                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
818                 else
819                         REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
820                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
821
822                 if (!on != aniState->ofdmWeakSigDetectOff) {
823                         ath_print(common, ATH_DBG_ANI,
824                                   "** ch %d: ofdm weak signal: %s=>%s\n",
825                                   chan->channel,
826                                   !aniState->ofdmWeakSigDetectOff ?
827                                         "on" : "off",
828                                   on ? "on" : "off");
829                         if (on)
830                                 ah->stats.ast_ani_ofdmon++;
831                         else
832                                 ah->stats.ast_ani_ofdmoff++;
833                         aniState->ofdmWeakSigDetectOff = !on;
834                 }
835                 break;
836         }
837         case ATH9K_ANI_FIRSTEP_LEVEL:{
838                 u32 level = param;
839
840                 if (level >= ARRAY_SIZE(firstep_table)) {
841                         ath_print(common, ATH_DBG_ANI,
842                                   "ATH9K_ANI_FIRSTEP_LEVEL: level "
843                                   "out of range (%u > %u)\n",
844                                   level,
845                                   (unsigned) ARRAY_SIZE(firstep_table));
846                         return false;
847                 }
848
849                 /*
850                  * make register setting relative to default
851                  * from INI file & cap value
852                  */
853                 value = firstep_table[level] -
854                         firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
855                         aniState->iniDef.firstep;
856                 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
857                         value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
858                 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
859                         value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
860                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
861                               AR_PHY_FIND_SIG_FIRSTEP,
862                               value);
863                 /*
864                  * we need to set first step low register too
865                  * make register setting relative to default
866                  * from INI file & cap value
867                  */
868                 value2 = firstep_table[level] -
869                          firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
870                          aniState->iniDef.firstepLow;
871                 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
872                         value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
873                 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
874                         value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
875
876                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
877                               AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
878
879                 if (level != aniState->firstepLevel) {
880                         ath_print(common, ATH_DBG_ANI,
881                                   "** ch %d: level %d=>%d[def:%d] "
882                                   "firstep[level]=%d ini=%d\n",
883                                   chan->channel,
884                                   aniState->firstepLevel,
885                                   level,
886                                   ATH9K_ANI_FIRSTEP_LVL_NEW,
887                                   value,
888                                   aniState->iniDef.firstep);
889                         ath_print(common, ATH_DBG_ANI,
890                                   "** ch %d: level %d=>%d[def:%d] "
891                                   "firstep_low[level]=%d ini=%d\n",
892                                   chan->channel,
893                                   aniState->firstepLevel,
894                                   level,
895                                   ATH9K_ANI_FIRSTEP_LVL_NEW,
896                                   value2,
897                                   aniState->iniDef.firstepLow);
898                         if (level > aniState->firstepLevel)
899                                 ah->stats.ast_ani_stepup++;
900                         else if (level < aniState->firstepLevel)
901                                 ah->stats.ast_ani_stepdown++;
902                         aniState->firstepLevel = level;
903                 }
904                 break;
905         }
906         case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
907                 u32 level = param;
908
909                 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
910                         ath_print(common, ATH_DBG_ANI,
911                                   "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level "
912                                   "out of range (%u > %u)\n",
913                                   level,
914                                   (unsigned) ARRAY_SIZE(cycpwrThr1_table));
915                         return false;
916                 }
917                 /*
918                  * make register setting relative to default
919                  * from INI file & cap value
920                  */
921                 value = cycpwrThr1_table[level] -
922                         cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
923                         aniState->iniDef.cycpwrThr1;
924                 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
925                         value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
926                 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
927                         value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
928                 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
929                               AR_PHY_TIMING5_CYCPWR_THR1,
930                               value);
931
932                 /*
933                  * set AR_PHY_EXT_CCA for extension channel
934                  * make register setting relative to default
935                  * from INI file & cap value
936                  */
937                 value2 = cycpwrThr1_table[level] -
938                          cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
939                          aniState->iniDef.cycpwrThr1Ext;
940                 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
941                         value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
942                 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
943                         value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
944                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
945                               AR_PHY_EXT_CYCPWR_THR1, value2);
946
947                 if (level != aniState->spurImmunityLevel) {
948                         ath_print(common, ATH_DBG_ANI,
949                                   "** ch %d: level %d=>%d[def:%d] "
950                                   "cycpwrThr1[level]=%d ini=%d\n",
951                                   chan->channel,
952                                   aniState->spurImmunityLevel,
953                                   level,
954                                   ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
955                                   value,
956                                   aniState->iniDef.cycpwrThr1);
957                         ath_print(common, ATH_DBG_ANI,
958                                   "** ch %d: level %d=>%d[def:%d] "
959                                   "cycpwrThr1Ext[level]=%d ini=%d\n",
960                                   chan->channel,
961                                   aniState->spurImmunityLevel,
962                                   level,
963                                   ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
964                                   value2,
965                                   aniState->iniDef.cycpwrThr1Ext);
966                         if (level > aniState->spurImmunityLevel)
967                                 ah->stats.ast_ani_spurup++;
968                         else if (level < aniState->spurImmunityLevel)
969                                 ah->stats.ast_ani_spurdown++;
970                         aniState->spurImmunityLevel = level;
971                 }
972                 break;
973         }
974         case ATH9K_ANI_MRC_CCK:{
975                 /*
976                  * is_on == 1 means MRC CCK ON (default, less noise imm)
977                  * is_on == 0 means MRC CCK is OFF (more noise imm)
978                  */
979                 bool is_on = param ? 1 : 0;
980                 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
981                               AR_PHY_MRC_CCK_ENABLE, is_on);
982                 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
983                               AR_PHY_MRC_CCK_MUX_REG, is_on);
984                 if (!is_on != aniState->mrcCCKOff) {
985                         ath_print(common, ATH_DBG_ANI,
986                                   "** ch %d: MRC CCK: %s=>%s\n",
987                                   chan->channel,
988                                   !aniState->mrcCCKOff ? "on" : "off",
989                                   is_on ? "on" : "off");
990                 if (is_on)
991                         ah->stats.ast_ani_ccklow++;
992                 else
993                         ah->stats.ast_ani_cckhigh++;
994                 aniState->mrcCCKOff = !is_on;
995                 }
996         break;
997         }
998         case ATH9K_ANI_PRESENT:
999                 break;
1000         default:
1001                 ath_print(common, ATH_DBG_ANI,
1002                           "invalid cmd %u\n", cmd);
1003                 return false;
1004         }
1005
1006         ath_print(common, ATH_DBG_ANI,
1007                   "ANI parameters: SI=%d, ofdmWS=%s FS=%d "
1008                   "MRCcck=%s listenTime=%d "
1009                   "ofdmErrs=%d cckErrs=%d\n",
1010                   aniState->spurImmunityLevel,
1011                   !aniState->ofdmWeakSigDetectOff ? "on" : "off",
1012                   aniState->firstepLevel,
1013                   !aniState->mrcCCKOff ? "on" : "off",
1014                   aniState->listenTime,
1015                   aniState->ofdmPhyErrCount,
1016                   aniState->cckPhyErrCount);
1017         return true;
1018 }
1019
1020 static void ar9003_hw_do_getnf(struct ath_hw *ah,
1021                               int16_t nfarray[NUM_NF_READINGS])
1022 {
1023         int16_t nf;
1024
1025         nf = MS(REG_READ(ah, AR_PHY_CCA_0), AR_PHY_MINCCA_PWR);
1026         nfarray[0] = sign_extend(nf, 9);
1027
1028         nf = MS(REG_READ(ah, AR_PHY_CCA_1), AR_PHY_CH1_MINCCA_PWR);
1029         nfarray[1] = sign_extend(nf, 9);
1030
1031         nf = MS(REG_READ(ah, AR_PHY_CCA_2), AR_PHY_CH2_MINCCA_PWR);
1032         nfarray[2] = sign_extend(nf, 9);
1033
1034         if (!IS_CHAN_HT40(ah->curchan))
1035                 return;
1036
1037         nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
1038         nfarray[3] = sign_extend(nf, 9);
1039
1040         nf = MS(REG_READ(ah, AR_PHY_EXT_CCA_1), AR_PHY_CH1_EXT_MINCCA_PWR);
1041         nfarray[4] = sign_extend(nf, 9);
1042
1043         nf = MS(REG_READ(ah, AR_PHY_EXT_CCA_2), AR_PHY_CH2_EXT_MINCCA_PWR);
1044         nfarray[5] = sign_extend(nf, 9);
1045 }
1046
1047 static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
1048 {
1049         ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1050         ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
1051         ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
1052         ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1053         ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1054         ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
1055 }
1056
1057 /*
1058  * Initialize the ANI register values with default (ini) values.
1059  * This routine is called during a (full) hardware reset after
1060  * all the registers are initialised from the INI.
1061  */
1062 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1063 {
1064         struct ar5416AniState *aniState;
1065         struct ath_common *common = ath9k_hw_common(ah);
1066         struct ath9k_channel *chan = ah->curchan;
1067         struct ath9k_ani_default *iniDef;
1068         u32 val;
1069
1070         aniState = &ah->curchan->ani;
1071         iniDef = &aniState->iniDef;
1072
1073         ath_print(common, ATH_DBG_ANI,
1074                   "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
1075                   ah->hw_version.macVersion,
1076                   ah->hw_version.macRev,
1077                   ah->opmode,
1078                   chan->channel,
1079                   chan->channelFlags);
1080
1081         val = REG_READ(ah, AR_PHY_SFCORR);
1082         iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1083         iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1084         iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1085
1086         val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1087         iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1088         iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1089         iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1090
1091         val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1092         iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1093         iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1094         iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1095         iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1096         iniDef->firstep = REG_READ_FIELD(ah,
1097                                          AR_PHY_FIND_SIG,
1098                                          AR_PHY_FIND_SIG_FIRSTEP);
1099         iniDef->firstepLow = REG_READ_FIELD(ah,
1100                                             AR_PHY_FIND_SIG_LOW,
1101                                             AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1102         iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1103                                             AR_PHY_TIMING5,
1104                                             AR_PHY_TIMING5_CYCPWR_THR1);
1105         iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1106                                                AR_PHY_EXT_CCA,
1107                                                AR_PHY_EXT_CYCPWR_THR1);
1108
1109         /* these levels just got reset to defaults by the INI */
1110         aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
1111         aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
1112         aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG;
1113         aniState->mrcCCKOff = !ATH9K_ANI_ENABLE_MRC_CCK;
1114 }
1115
1116 void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1117 {
1118         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1119         const u32 ar9300_cca_regs[6] = {
1120                 AR_PHY_CCA_0,
1121                 AR_PHY_CCA_1,
1122                 AR_PHY_CCA_2,
1123                 AR_PHY_EXT_CCA,
1124                 AR_PHY_EXT_CCA_1,
1125                 AR_PHY_EXT_CCA_2,
1126         };
1127
1128         priv_ops->rf_set_freq = ar9003_hw_set_channel;
1129         priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
1130         priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
1131         priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
1132         priv_ops->init_bb = ar9003_hw_init_bb;
1133         priv_ops->process_ini = ar9003_hw_process_ini;
1134         priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1135         priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
1136         priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1137         priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1138         priv_ops->rfbus_done = ar9003_hw_rfbus_done;
1139         priv_ops->enable_rfkill = ar9003_hw_enable_rfkill;
1140         priv_ops->set_diversity = ar9003_hw_set_diversity;
1141         priv_ops->ani_control = ar9003_hw_ani_control;
1142         priv_ops->do_getnf = ar9003_hw_do_getnf;
1143         priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
1144
1145         ar9003_hw_set_nf_limits(ah);
1146         memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
1147 }
1148
1149 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
1150 {
1151         struct ath_common *common = ath9k_hw_common(ah);
1152         u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms;
1153         u32 val, idle_count;
1154
1155         if (!idle_tmo_ms) {
1156                 /* disable IRQ, disable chip-reset for BB panic */
1157                 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1158                           REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &
1159                           ~(AR_PHY_WATCHDOG_RST_ENABLE |
1160                             AR_PHY_WATCHDOG_IRQ_ENABLE));
1161
1162                 /* disable watchdog in non-IDLE mode, disable in IDLE mode */
1163                 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1164                           REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &
1165                           ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1166                             AR_PHY_WATCHDOG_IDLE_ENABLE));
1167
1168                 ath_print(common, ATH_DBG_RESET, "Disabled BB Watchdog\n");
1169                 return;
1170         }
1171
1172         /* enable IRQ, disable chip-reset for BB watchdog */
1173         val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;
1174         REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1175                   (val | AR_PHY_WATCHDOG_IRQ_ENABLE) &
1176                   ~AR_PHY_WATCHDOG_RST_ENABLE);
1177
1178         /* bound limit to 10 secs */
1179         if (idle_tmo_ms > 10000)
1180                 idle_tmo_ms = 10000;
1181
1182         /*
1183          * The time unit for watchdog event is 2^15 44/88MHz cycles.
1184          *
1185          * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick
1186          * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick
1187          *
1188          * Given we use fast clock now in 5 GHz, these time units should
1189          * be common for both 2 GHz and 5 GHz.
1190          */
1191         idle_count = (100 * idle_tmo_ms) / 74;
1192         if (ah->curchan && IS_CHAN_HT40(ah->curchan))
1193                 idle_count = (100 * idle_tmo_ms) / 37;
1194
1195         /*
1196          * enable watchdog in non-IDLE mode, disable in IDLE mode,
1197          * set idle time-out.
1198          */
1199         REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1200                   AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1201                   AR_PHY_WATCHDOG_IDLE_MASK |
1202                   (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
1203
1204         ath_print(common, ATH_DBG_RESET,
1205                   "Enabled BB Watchdog timeout (%u ms)\n",
1206                   idle_tmo_ms);
1207 }
1208
1209 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
1210 {
1211         /*
1212          * we want to avoid printing in ISR context so we save the
1213          * watchdog status to be printed later in bottom half context.
1214          */
1215         ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);
1216
1217         /*
1218          * the watchdog timer should reset on status read but to be sure
1219          * sure we write 0 to the watchdog status bit.
1220          */
1221         REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
1222                   ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR);
1223 }
1224
1225 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
1226 {
1227         struct ath_common *common = ath9k_hw_common(ah);
1228         u32 status;
1229
1230         if (likely(!(common->debug_mask & ATH_DBG_RESET)))
1231                 return;
1232
1233         status = ah->bb_watchdog_last_status;
1234         ath_print(common, ATH_DBG_RESET,
1235                   "\n==== BB update: BB status=0x%08x ====\n", status);
1236         ath_print(common, ATH_DBG_RESET,
1237                   "** BB state: wd=%u det=%u rdar=%u rOFDM=%d "
1238                   "rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1239                   MS(status, AR_PHY_WATCHDOG_INFO),
1240                   MS(status, AR_PHY_WATCHDOG_DET_HANG),
1241                   MS(status, AR_PHY_WATCHDOG_RADAR_SM),
1242                   MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
1243                   MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
1244                   MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
1245                   MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
1246                   MS(status, AR_PHY_WATCHDOG_AGC_SM),
1247                   MS(status,AR_PHY_WATCHDOG_SRCH_SM));
1248
1249         ath_print(common, ATH_DBG_RESET,
1250                   "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
1251                   REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
1252                   REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
1253         ath_print(common, ATH_DBG_RESET,
1254                   "** BB mode: BB_gen_controls=0x%08x **\n",
1255                   REG_READ(ah, AR_PHY_GEN_CTRL));
1256
1257 #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
1258         if (common->cc_survey.cycles)
1259                 ath_print(common, ATH_DBG_RESET,
1260                           "** BB busy times: rx_clear=%d%%, "
1261                           "rx_frame=%d%%, tx_frame=%d%% **\n",
1262                           PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
1263
1264         ath_print(common, ATH_DBG_RESET,
1265                   "==== BB update: done ====\n\n");
1266 }
1267 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);