1bc33f51e4663c877fca5208d4c9fcee83df8481
[linux-2.6.git] / drivers / net / wireless / ath / ath9k / ar9003_phy.c
1 /*
2  * Copyright (c) 2010 Atheros Communications Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16
17 #include "hw.h"
18 #include "ar9003_phy.h"
19
20 static const int firstep_table[] =
21 /* level:  0   1   2   3   4   5   6   7   8  */
22         { -4, -2,  0,  2,  4,  6,  8, 10, 12 }; /* lvl 0-8, default 2 */
23
24 static const int cycpwrThr1_table[] =
25 /* level:  0   1   2   3   4   5   6   7   8  */
26         { -6, -4, -2,  0,  2,  4,  6,  8 };     /* lvl 0-7, default 3 */
27
28 /*
29  * register values to turn OFDM weak signal detection OFF
30  */
31 static const int m1ThreshLow_off = 127;
32 static const int m2ThreshLow_off = 127;
33 static const int m1Thresh_off = 127;
34 static const int m2Thresh_off = 127;
35 static const int m2CountThr_off =  31;
36 static const int m2CountThrLow_off =  63;
37 static const int m1ThreshLowExt_off = 127;
38 static const int m2ThreshLowExt_off = 127;
39 static const int m1ThreshExt_off = 127;
40 static const int m2ThreshExt_off = 127;
41
42 /**
43  * ar9003_hw_set_channel - set channel on single-chip device
44  * @ah: atheros hardware structure
45  * @chan:
46  *
47  * This is the function to change channel on single-chip devices, that is
48  * all devices after ar9280.
49  *
50  * This function takes the channel value in MHz and sets
51  * hardware channel value. Assumes writes have been enabled to analog bus.
52  *
53  * Actual Expression,
54  *
55  * For 2GHz channel,
56  * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
57  * (freq_ref = 40MHz)
58  *
59  * For 5GHz channel,
60  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
61  * (freq_ref = 40MHz/(24>>amodeRefSel))
62  *
63  * For 5GHz channels which are 5MHz spaced,
64  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
65  * (freq_ref = 40MHz)
66  */
67 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
68 {
69         u16 bMode, fracMode = 0, aModeRefSel = 0;
70         u32 freq, channelSel = 0, reg32 = 0;
71         struct chan_centers centers;
72         int loadSynthChannel;
73
74         ath9k_hw_get_channel_centers(ah, chan, &centers);
75         freq = centers.synth_center;
76
77         if (freq < 4800) {     /* 2 GHz, fractional mode */
78                 if (AR_SREV_9485(ah)) {
79                         u32 chan_frac;
80
81                         /*
82                          * freq_ref = 40 / (refdiva >> amoderefsel); where refdiva=1 and amoderefsel=0
83                          * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
84                          * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
85                          */
86                         channelSel = (freq * 4) / 120;
87                         chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
88                         channelSel = (channelSel << 17) | chan_frac;
89                 } else
90                         channelSel = CHANSEL_2G(freq);
91                 /* Set to 2G mode */
92                 bMode = 1;
93         } else {
94                 channelSel = CHANSEL_5G(freq);
95                 /* Doubler is ON, so, divide channelSel by 2. */
96                 channelSel >>= 1;
97                 /* Set to 5G mode */
98                 bMode = 0;
99         }
100
101         /* Enable fractional mode for all channels */
102         fracMode = 1;
103         aModeRefSel = 0;
104         loadSynthChannel = 0;
105
106         reg32 = (bMode << 29);
107         REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
108
109         /* Enable Long shift Select for Synthesizer */
110         REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
111                       AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
112
113         /* Program Synth. setting */
114         reg32 = (channelSel << 2) | (fracMode << 30) |
115                 (aModeRefSel << 28) | (loadSynthChannel << 31);
116         REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
117
118         /* Toggle Load Synth channel bit */
119         loadSynthChannel = 1;
120         reg32 = (channelSel << 2) | (fracMode << 30) |
121                 (aModeRefSel << 28) | (loadSynthChannel << 31);
122         REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
123
124         ah->curchan = chan;
125         ah->curchan_rad_index = -1;
126
127         return 0;
128 }
129
130 /**
131  * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
132  * @ah: atheros hardware structure
133  * @chan:
134  *
135  * For single-chip solutions. Converts to baseband spur frequency given the
136  * input channel frequency and compute register settings below.
137  *
138  * Spur mitigation for MRC CCK
139  */
140 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
141                                             struct ath9k_channel *chan)
142 {
143         static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
144         int cur_bb_spur, negative = 0, cck_spur_freq;
145         int i;
146         int range, max_spur_cnts, synth_freq;
147         u8 *spur_fbin_ptr = NULL;
148
149         /*
150          * Need to verify range +/- 10 MHz in control channel, otherwise spur
151          * is out-of-band and can be ignored.
152          */
153
154         if (AR_SREV_9485(ah)) {
155                 spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah,
156                                                          IS_CHAN_2GHZ(chan));
157                 if (spur_fbin_ptr[0] == 0) /* No spur */
158                         return;
159                 max_spur_cnts = 5;
160                 if (IS_CHAN_HT40(chan)) {
161                         range = 19;
162                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
163                                            AR_PHY_GC_DYN2040_PRI_CH) == 0)
164                                 synth_freq = chan->channel + 10;
165                         else
166                                 synth_freq = chan->channel - 10;
167                 } else {
168                         range = 10;
169                         synth_freq = chan->channel;
170                 }
171         } else {
172                 range = 10;
173                 max_spur_cnts = 4;
174                 synth_freq = chan->channel;
175         }
176
177         for (i = 0; i < max_spur_cnts; i++) {
178                 negative = 0;
179                 if (AR_SREV_9485(ah))
180                         cur_bb_spur = FBIN2FREQ(spur_fbin_ptr[i],
181                                         IS_CHAN_2GHZ(chan)) - synth_freq;
182                 else
183                         cur_bb_spur = spur_freq[i] - synth_freq;
184
185                 if (cur_bb_spur < 0) {
186                         negative = 1;
187                         cur_bb_spur = -cur_bb_spur;
188                 }
189                 if (cur_bb_spur < range) {
190                         cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
191
192                         if (negative == 1)
193                                 cck_spur_freq = -cck_spur_freq;
194
195                         cck_spur_freq = cck_spur_freq & 0xfffff;
196
197                         REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
198                                       AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
199                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
200                                       AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
201                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
202                                       AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
203                                       0x2);
204                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
205                                       AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
206                                       0x1);
207                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
208                                       AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
209                                       cck_spur_freq);
210
211                         return;
212                 }
213         }
214
215         REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
216                       AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
217         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
218                       AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
219         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
220                       AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
221 }
222
223 /* Clean all spur register fields */
224 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
225 {
226         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
227                       AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
228         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
229                       AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
230         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
231                       AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
232         REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
233                       AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
234         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
235                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
236         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
237                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
238         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
239                       AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
240         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
241                       AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
242         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
243                       AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
244
245         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
246                       AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
247         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
248                       AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
249         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
250                       AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
251         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
252                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
253         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
254                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
255         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
256                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
257         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
258                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
259         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
260                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
261         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
262                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
263         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
264                       AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
265 }
266
267 static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
268                                 int freq_offset,
269                                 int spur_freq_sd,
270                                 int spur_delta_phase,
271                                 int spur_subchannel_sd)
272 {
273         int mask_index = 0;
274
275         /* OFDM Spur mitigation */
276         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
277                  AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
278         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
279                       AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
280         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
281                       AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
282         REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
283                       AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
284         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
285                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
286         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
287                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
288         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
289                       AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
290         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
291                       AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
292         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
293                       AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
294
295         if (REG_READ_FIELD(ah, AR_PHY_MODE,
296                            AR_PHY_MODE_DYNAMIC) == 0x1)
297                 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
298                               AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
299
300         mask_index = (freq_offset << 4) / 5;
301         if (mask_index < 0)
302                 mask_index = mask_index - 1;
303
304         mask_index = mask_index & 0x7f;
305
306         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
307                       AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
308         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
309                       AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
310         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
311                       AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
312         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
313                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
314         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
315                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
316         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
317                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
318         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
319                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
320         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
321                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
322         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
323                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
324         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
325                       AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
326 }
327
328 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
329                                      struct ath9k_channel *chan,
330                                      int freq_offset)
331 {
332         int spur_freq_sd = 0;
333         int spur_subchannel_sd = 0;
334         int spur_delta_phase = 0;
335
336         if (IS_CHAN_HT40(chan)) {
337                 if (freq_offset < 0) {
338                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
339                                            AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
340                                 spur_subchannel_sd = 1;
341                         else
342                                 spur_subchannel_sd = 0;
343
344                         spur_freq_sd = ((freq_offset + 10) << 9) / 11;
345
346                 } else {
347                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
348                             AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
349                                 spur_subchannel_sd = 0;
350                         else
351                                 spur_subchannel_sd = 1;
352
353                         spur_freq_sd = ((freq_offset - 10) << 9) / 11;
354
355                 }
356
357                 spur_delta_phase = (freq_offset << 17) / 5;
358
359         } else {
360                 spur_subchannel_sd = 0;
361                 spur_freq_sd = (freq_offset << 9) /11;
362                 spur_delta_phase = (freq_offset << 18) / 5;
363         }
364
365         spur_freq_sd = spur_freq_sd & 0x3ff;
366         spur_delta_phase = spur_delta_phase & 0xfffff;
367
368         ar9003_hw_spur_ofdm(ah,
369                             freq_offset,
370                             spur_freq_sd,
371                             spur_delta_phase,
372                             spur_subchannel_sd);
373 }
374
375 /* Spur mitigation for OFDM */
376 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
377                                          struct ath9k_channel *chan)
378 {
379         int synth_freq;
380         int range = 10;
381         int freq_offset = 0;
382         int mode;
383         u8* spurChansPtr;
384         unsigned int i;
385         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
386
387         if (IS_CHAN_5GHZ(chan)) {
388                 spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
389                 mode = 0;
390         }
391         else {
392                 spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
393                 mode = 1;
394         }
395
396         if (spurChansPtr[0] == 0)
397                 return; /* No spur in the mode */
398
399         if (IS_CHAN_HT40(chan)) {
400                 range = 19;
401                 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
402                                    AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
403                         synth_freq = chan->channel - 10;
404                 else
405                         synth_freq = chan->channel + 10;
406         } else {
407                 range = 10;
408                 synth_freq = chan->channel;
409         }
410
411         ar9003_hw_spur_ofdm_clear(ah);
412
413         for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
414                 freq_offset = FBIN2FREQ(spurChansPtr[i], mode) - synth_freq;
415                 if (abs(freq_offset) < range) {
416                         ar9003_hw_spur_ofdm_work(ah, chan, freq_offset);
417                         break;
418                 }
419         }
420 }
421
422 static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
423                                     struct ath9k_channel *chan)
424 {
425         ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
426         ar9003_hw_spur_mitigate_ofdm(ah, chan);
427 }
428
429 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
430                                          struct ath9k_channel *chan)
431 {
432         u32 pll;
433
434         pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
435
436         if (chan && IS_CHAN_HALF_RATE(chan))
437                 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
438         else if (chan && IS_CHAN_QUARTER_RATE(chan))
439                 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
440
441         pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
442
443         return pll;
444 }
445
446 static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
447                                        struct ath9k_channel *chan)
448 {
449         u32 phymode;
450         u32 enableDacFifo = 0;
451
452         enableDacFifo =
453                 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
454
455         /* Enable 11n HT, 20 MHz */
456         phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 | AR_PHY_GC_WALSH |
457                   AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
458
459         /* Configure baseband for dynamic 20/40 operation */
460         if (IS_CHAN_HT40(chan)) {
461                 phymode |= AR_PHY_GC_DYN2040_EN;
462                 /* Configure control (primary) channel at +-10MHz */
463                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
464                     (chan->chanmode == CHANNEL_G_HT40PLUS))
465                         phymode |= AR_PHY_GC_DYN2040_PRI_CH;
466
467         }
468
469         /* make sure we preserve INI settings */
470         phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
471         /* turn off Green Field detection for STA for now */
472         phymode &= ~AR_PHY_GC_GF_DETECT_EN;
473
474         REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
475
476         /* Configure MAC for 20/40 operation */
477         ath9k_hw_set11nmac2040(ah);
478
479         /* global transmit timeout (25 TUs default)*/
480         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
481         /* carrier sense timeout */
482         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
483 }
484
485 static void ar9003_hw_init_bb(struct ath_hw *ah,
486                               struct ath9k_channel *chan)
487 {
488         u32 synthDelay;
489
490         /*
491          * Wait for the frequency synth to settle (synth goes on
492          * via AR_PHY_ACTIVE_EN).  Read the phy active delay register.
493          * Value is in 100ns increments.
494          */
495         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
496         if (IS_CHAN_B(chan))
497                 synthDelay = (4 * synthDelay) / 22;
498         else
499                 synthDelay /= 10;
500
501         /* Activate the PHY (includes baseband activate + synthesizer on) */
502         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
503
504         /*
505          * There is an issue if the AP starts the calibration before
506          * the base band timeout completes.  This could result in the
507          * rx_clear false triggering.  As a workaround we add delay an
508          * extra BASE_ACTIVATE_DELAY usecs to ensure this condition
509          * does not happen.
510          */
511         udelay(synthDelay + BASE_ACTIVATE_DELAY);
512 }
513
514 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
515 {
516         switch (rx) {
517         case 0x5:
518                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
519                             AR_PHY_SWAP_ALT_CHAIN);
520         case 0x3:
521         case 0x1:
522         case 0x2:
523         case 0x7:
524                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
525                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
526                 break;
527         default:
528                 break;
529         }
530
531         if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
532                 REG_WRITE(ah, AR_SELFGEN_MASK, 0x3);
533         else
534                 REG_WRITE(ah, AR_SELFGEN_MASK, tx);
535
536         if (tx == 0x5) {
537                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
538                             AR_PHY_SWAP_ALT_CHAIN);
539         }
540 }
541
542 /*
543  * Override INI values with chip specific configuration.
544  */
545 static void ar9003_hw_override_ini(struct ath_hw *ah)
546 {
547         u32 val;
548
549         /*
550          * Set the RX_ABORT and RX_DIS and clear it only after
551          * RXE is set for MAC. This prevents frames with
552          * corrupted descriptor status.
553          */
554         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
555
556         /*
557          * For AR9280 and above, there is a new feature that allows
558          * Multicast search based on both MAC Address and Key ID. By default,
559          * this feature is enabled. But since the driver is not using this
560          * feature, we switch it off; otherwise multicast search based on
561          * MAC addr only will fail.
562          */
563         val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
564         REG_WRITE(ah, AR_PCU_MISC_MODE2,
565                   val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE);
566 }
567
568 static void ar9003_hw_prog_ini(struct ath_hw *ah,
569                                struct ar5416IniArray *iniArr,
570                                int column)
571 {
572         unsigned int i, regWrites = 0;
573
574         /* New INI format: Array may be undefined (pre, core, post arrays) */
575         if (!iniArr->ia_array)
576                 return;
577
578         /*
579          * New INI format: Pre, core, and post arrays for a given subsystem
580          * may be modal (> 2 columns) or non-modal (2 columns). Determine if
581          * the array is non-modal and force the column to 1.
582          */
583         if (column >= iniArr->ia_columns)
584                 column = 1;
585
586         for (i = 0; i < iniArr->ia_rows; i++) {
587                 u32 reg = INI_RA(iniArr, i, 0);
588                 u32 val = INI_RA(iniArr, i, column);
589
590                 REG_WRITE(ah, reg, val);
591
592                 DO_DELAY(regWrites);
593         }
594 }
595
596 static int ar9003_hw_process_ini(struct ath_hw *ah,
597                                  struct ath9k_channel *chan)
598 {
599         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
600         unsigned int regWrites = 0, i;
601         struct ieee80211_channel *channel = chan->chan;
602         u32 modesIndex, freqIndex;
603
604         switch (chan->chanmode) {
605         case CHANNEL_A:
606         case CHANNEL_A_HT20:
607                 modesIndex = 1;
608                 freqIndex = 1;
609                 break;
610         case CHANNEL_A_HT40PLUS:
611         case CHANNEL_A_HT40MINUS:
612                 modesIndex = 2;
613                 freqIndex = 1;
614                 break;
615         case CHANNEL_G:
616         case CHANNEL_G_HT20:
617         case CHANNEL_B:
618                 modesIndex = 4;
619                 freqIndex = 2;
620                 break;
621         case CHANNEL_G_HT40PLUS:
622         case CHANNEL_G_HT40MINUS:
623                 modesIndex = 3;
624                 freqIndex = 2;
625                 break;
626
627         default:
628                 return -EINVAL;
629         }
630
631         for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
632                 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
633                 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
634                 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
635                 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
636         }
637
638         REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
639         REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
640
641         /*
642          * For 5GHz channels requiring Fast Clock, apply
643          * different modal values.
644          */
645         if (IS_CHAN_A_FAST_CLOCK(ah, chan))
646                 REG_WRITE_ARRAY(&ah->iniModesAdditional,
647                                 modesIndex, regWrites);
648
649         ar9003_hw_override_ini(ah);
650         ar9003_hw_set_channel_regs(ah, chan);
651         ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
652
653         /* Set TX power */
654         ah->eep_ops->set_txpower(ah, chan,
655                                  ath9k_regd_get_ctl(regulatory, chan),
656                                  channel->max_antenna_gain * 2,
657                                  channel->max_power * 2,
658                                  min((u32) MAX_RATE_POWER,
659                                  (u32) regulatory->power_limit), false);
660
661         return 0;
662 }
663
664 static void ar9003_hw_set_rfmode(struct ath_hw *ah,
665                                  struct ath9k_channel *chan)
666 {
667         u32 rfMode = 0;
668
669         if (chan == NULL)
670                 return;
671
672         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
673                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
674
675         if (IS_CHAN_A_FAST_CLOCK(ah, chan))
676                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
677
678         REG_WRITE(ah, AR_PHY_MODE, rfMode);
679 }
680
681 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
682 {
683         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
684 }
685
686 static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
687                                       struct ath9k_channel *chan)
688 {
689         u32 coef_scaled, ds_coef_exp, ds_coef_man;
690         u32 clockMhzScaled = 0x64000000;
691         struct chan_centers centers;
692
693         /*
694          * half and quarter rate can divide the scaled clock by 2 or 4
695          * scale for selected channel bandwidth
696          */
697         if (IS_CHAN_HALF_RATE(chan))
698                 clockMhzScaled = clockMhzScaled >> 1;
699         else if (IS_CHAN_QUARTER_RATE(chan))
700                 clockMhzScaled = clockMhzScaled >> 2;
701
702         /*
703          * ALGO -> coef = 1e8/fcarrier*fclock/40;
704          * scaled coef to provide precision for this floating calculation
705          */
706         ath9k_hw_get_channel_centers(ah, chan, &centers);
707         coef_scaled = clockMhzScaled / centers.synth_center;
708
709         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
710                                       &ds_coef_exp);
711
712         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
713                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
714         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
715                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
716
717         /*
718          * For Short GI,
719          * scaled coeff is 9/10 that of normal coeff
720          */
721         coef_scaled = (9 * coef_scaled) / 10;
722
723         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
724                                       &ds_coef_exp);
725
726         /* for short gi */
727         REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
728                       AR_PHY_SGI_DSC_MAN, ds_coef_man);
729         REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
730                       AR_PHY_SGI_DSC_EXP, ds_coef_exp);
731 }
732
733 static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
734 {
735         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
736         return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
737                              AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
738 }
739
740 /*
741  * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
742  * Read the phy active delay register. Value is in 100ns increments.
743  */
744 static void ar9003_hw_rfbus_done(struct ath_hw *ah)
745 {
746         u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
747         if (IS_CHAN_B(ah->curchan))
748                 synthDelay = (4 * synthDelay) / 22;
749         else
750                 synthDelay /= 10;
751
752         udelay(synthDelay + BASE_ACTIVATE_DELAY);
753
754         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
755 }
756
757 static void ar9003_hw_set_diversity(struct ath_hw *ah, bool value)
758 {
759         u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
760         if (value)
761                 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
762         else
763                 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
764         REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
765 }
766
767 static bool ar9003_hw_ani_control(struct ath_hw *ah,
768                                   enum ath9k_ani_cmd cmd, int param)
769 {
770         struct ath_common *common = ath9k_hw_common(ah);
771         struct ath9k_channel *chan = ah->curchan;
772         struct ar5416AniState *aniState = &chan->ani;
773         s32 value, value2;
774
775         switch (cmd & ah->ani_function) {
776         case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
777                 /*
778                  * on == 1 means ofdm weak signal detection is ON
779                  * on == 1 is the default, for less noise immunity
780                  *
781                  * on == 0 means ofdm weak signal detection is OFF
782                  * on == 0 means more noise imm
783                  */
784                 u32 on = param ? 1 : 0;
785                 /*
786                  * make register setting for default
787                  * (weak sig detect ON) come from INI file
788                  */
789                 int m1ThreshLow = on ?
790                         aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
791                 int m2ThreshLow = on ?
792                         aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
793                 int m1Thresh = on ?
794                         aniState->iniDef.m1Thresh : m1Thresh_off;
795                 int m2Thresh = on ?
796                         aniState->iniDef.m2Thresh : m2Thresh_off;
797                 int m2CountThr = on ?
798                         aniState->iniDef.m2CountThr : m2CountThr_off;
799                 int m2CountThrLow = on ?
800                         aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
801                 int m1ThreshLowExt = on ?
802                         aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
803                 int m2ThreshLowExt = on ?
804                         aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
805                 int m1ThreshExt = on ?
806                         aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
807                 int m2ThreshExt = on ?
808                         aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
809
810                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
811                               AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
812                               m1ThreshLow);
813                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
814                               AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
815                               m2ThreshLow);
816                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
817                               AR_PHY_SFCORR_M1_THRESH, m1Thresh);
818                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
819                               AR_PHY_SFCORR_M2_THRESH, m2Thresh);
820                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
821                               AR_PHY_SFCORR_M2COUNT_THR, m2CountThr);
822                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
823                               AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
824                               m2CountThrLow);
825
826                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
827                               AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt);
828                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
829                               AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt);
830                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
831                               AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt);
832                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
833                               AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt);
834
835                 if (on)
836                         REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
837                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
838                 else
839                         REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
840                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
841
842                 if (!on != aniState->ofdmWeakSigDetectOff) {
843                         ath_dbg(common, ATH_DBG_ANI,
844                                 "** ch %d: ofdm weak signal: %s=>%s\n",
845                                 chan->channel,
846                                 !aniState->ofdmWeakSigDetectOff ?
847                                 "on" : "off",
848                                 on ? "on" : "off");
849                         if (on)
850                                 ah->stats.ast_ani_ofdmon++;
851                         else
852                                 ah->stats.ast_ani_ofdmoff++;
853                         aniState->ofdmWeakSigDetectOff = !on;
854                 }
855                 break;
856         }
857         case ATH9K_ANI_FIRSTEP_LEVEL:{
858                 u32 level = param;
859
860                 if (level >= ARRAY_SIZE(firstep_table)) {
861                         ath_dbg(common, ATH_DBG_ANI,
862                                 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
863                                 level, ARRAY_SIZE(firstep_table));
864                         return false;
865                 }
866
867                 /*
868                  * make register setting relative to default
869                  * from INI file & cap value
870                  */
871                 value = firstep_table[level] -
872                         firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
873                         aniState->iniDef.firstep;
874                 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
875                         value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
876                 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
877                         value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
878                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
879                               AR_PHY_FIND_SIG_FIRSTEP,
880                               value);
881                 /*
882                  * we need to set first step low register too
883                  * make register setting relative to default
884                  * from INI file & cap value
885                  */
886                 value2 = firstep_table[level] -
887                          firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
888                          aniState->iniDef.firstepLow;
889                 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
890                         value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
891                 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
892                         value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
893
894                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
895                               AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
896
897                 if (level != aniState->firstepLevel) {
898                         ath_dbg(common, ATH_DBG_ANI,
899                                 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
900                                 chan->channel,
901                                 aniState->firstepLevel,
902                                 level,
903                                 ATH9K_ANI_FIRSTEP_LVL_NEW,
904                                 value,
905                                 aniState->iniDef.firstep);
906                         ath_dbg(common, ATH_DBG_ANI,
907                                 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
908                                 chan->channel,
909                                 aniState->firstepLevel,
910                                 level,
911                                 ATH9K_ANI_FIRSTEP_LVL_NEW,
912                                 value2,
913                                 aniState->iniDef.firstepLow);
914                         if (level > aniState->firstepLevel)
915                                 ah->stats.ast_ani_stepup++;
916                         else if (level < aniState->firstepLevel)
917                                 ah->stats.ast_ani_stepdown++;
918                         aniState->firstepLevel = level;
919                 }
920                 break;
921         }
922         case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
923                 u32 level = param;
924
925                 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
926                         ath_dbg(common, ATH_DBG_ANI,
927                                 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
928                                 level, ARRAY_SIZE(cycpwrThr1_table));
929                         return false;
930                 }
931                 /*
932                  * make register setting relative to default
933                  * from INI file & cap value
934                  */
935                 value = cycpwrThr1_table[level] -
936                         cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
937                         aniState->iniDef.cycpwrThr1;
938                 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
939                         value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
940                 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
941                         value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
942                 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
943                               AR_PHY_TIMING5_CYCPWR_THR1,
944                               value);
945
946                 /*
947                  * set AR_PHY_EXT_CCA for extension channel
948                  * make register setting relative to default
949                  * from INI file & cap value
950                  */
951                 value2 = cycpwrThr1_table[level] -
952                          cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
953                          aniState->iniDef.cycpwrThr1Ext;
954                 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
955                         value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
956                 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
957                         value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
958                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
959                               AR_PHY_EXT_CYCPWR_THR1, value2);
960
961                 if (level != aniState->spurImmunityLevel) {
962                         ath_dbg(common, ATH_DBG_ANI,
963                                 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
964                                 chan->channel,
965                                 aniState->spurImmunityLevel,
966                                 level,
967                                 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
968                                 value,
969                                 aniState->iniDef.cycpwrThr1);
970                         ath_dbg(common, ATH_DBG_ANI,
971                                 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
972                                 chan->channel,
973                                 aniState->spurImmunityLevel,
974                                 level,
975                                 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
976                                 value2,
977                                 aniState->iniDef.cycpwrThr1Ext);
978                         if (level > aniState->spurImmunityLevel)
979                                 ah->stats.ast_ani_spurup++;
980                         else if (level < aniState->spurImmunityLevel)
981                                 ah->stats.ast_ani_spurdown++;
982                         aniState->spurImmunityLevel = level;
983                 }
984                 break;
985         }
986         case ATH9K_ANI_MRC_CCK:{
987                 /*
988                  * is_on == 1 means MRC CCK ON (default, less noise imm)
989                  * is_on == 0 means MRC CCK is OFF (more noise imm)
990                  */
991                 bool is_on = param ? 1 : 0;
992                 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
993                               AR_PHY_MRC_CCK_ENABLE, is_on);
994                 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
995                               AR_PHY_MRC_CCK_MUX_REG, is_on);
996                 if (!is_on != aniState->mrcCCKOff) {
997                         ath_dbg(common, ATH_DBG_ANI,
998                                 "** ch %d: MRC CCK: %s=>%s\n",
999                                 chan->channel,
1000                                 !aniState->mrcCCKOff ? "on" : "off",
1001                                 is_on ? "on" : "off");
1002                 if (is_on)
1003                         ah->stats.ast_ani_ccklow++;
1004                 else
1005                         ah->stats.ast_ani_cckhigh++;
1006                 aniState->mrcCCKOff = !is_on;
1007                 }
1008         break;
1009         }
1010         case ATH9K_ANI_PRESENT:
1011                 break;
1012         default:
1013                 ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd);
1014                 return false;
1015         }
1016
1017         ath_dbg(common, ATH_DBG_ANI,
1018                 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1019                 aniState->spurImmunityLevel,
1020                 !aniState->ofdmWeakSigDetectOff ? "on" : "off",
1021                 aniState->firstepLevel,
1022                 !aniState->mrcCCKOff ? "on" : "off",
1023                 aniState->listenTime,
1024                 aniState->ofdmPhyErrCount,
1025                 aniState->cckPhyErrCount);
1026         return true;
1027 }
1028
1029 static void ar9003_hw_do_getnf(struct ath_hw *ah,
1030                               int16_t nfarray[NUM_NF_READINGS])
1031 {
1032 #define AR_PHY_CH_MINCCA_PWR    0x1FF00000
1033 #define AR_PHY_CH_MINCCA_PWR_S  20
1034 #define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
1035 #define AR_PHY_CH_EXT_MINCCA_PWR_S 16
1036
1037         int16_t nf;
1038         int i;
1039
1040         for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1041                 if (ah->rxchainmask & BIT(i)) {
1042                         nf = MS(REG_READ(ah, ah->nf_regs[i]),
1043                                          AR_PHY_CH_MINCCA_PWR);
1044                         nfarray[i] = sign_extend32(nf, 8);
1045
1046                         if (IS_CHAN_HT40(ah->curchan)) {
1047                                 u8 ext_idx = AR9300_MAX_CHAINS + i;
1048
1049                                 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
1050                                                  AR_PHY_CH_EXT_MINCCA_PWR);
1051                                 nfarray[ext_idx] = sign_extend32(nf, 8);
1052                         }
1053                 }
1054         }
1055 }
1056
1057 static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
1058 {
1059         ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1060         ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
1061         ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
1062         ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1063         ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1064         ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
1065 }
1066
1067 /*
1068  * Initialize the ANI register values with default (ini) values.
1069  * This routine is called during a (full) hardware reset after
1070  * all the registers are initialised from the INI.
1071  */
1072 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1073 {
1074         struct ar5416AniState *aniState;
1075         struct ath_common *common = ath9k_hw_common(ah);
1076         struct ath9k_channel *chan = ah->curchan;
1077         struct ath9k_ani_default *iniDef;
1078         u32 val;
1079
1080         aniState = &ah->curchan->ani;
1081         iniDef = &aniState->iniDef;
1082
1083         ath_dbg(common, ATH_DBG_ANI,
1084                 "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
1085                 ah->hw_version.macVersion,
1086                 ah->hw_version.macRev,
1087                 ah->opmode,
1088                 chan->channel,
1089                 chan->channelFlags);
1090
1091         val = REG_READ(ah, AR_PHY_SFCORR);
1092         iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1093         iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1094         iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1095
1096         val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1097         iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1098         iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1099         iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1100
1101         val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1102         iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1103         iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1104         iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1105         iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1106         iniDef->firstep = REG_READ_FIELD(ah,
1107                                          AR_PHY_FIND_SIG,
1108                                          AR_PHY_FIND_SIG_FIRSTEP);
1109         iniDef->firstepLow = REG_READ_FIELD(ah,
1110                                             AR_PHY_FIND_SIG_LOW,
1111                                             AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1112         iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1113                                             AR_PHY_TIMING5,
1114                                             AR_PHY_TIMING5_CYCPWR_THR1);
1115         iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1116                                                AR_PHY_EXT_CCA,
1117                                                AR_PHY_EXT_CYCPWR_THR1);
1118
1119         /* these levels just got reset to defaults by the INI */
1120         aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
1121         aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
1122         aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG;
1123         aniState->mrcCCKOff = !ATH9K_ANI_ENABLE_MRC_CCK;
1124 }
1125
1126 static void ar9003_hw_set_radar_params(struct ath_hw *ah,
1127                                        struct ath_hw_radar_conf *conf)
1128 {
1129         u32 radar_0 = 0, radar_1 = 0;
1130
1131         if (!conf) {
1132                 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1133                 return;
1134         }
1135
1136         radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1137         radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1138         radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1139         radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1140         radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1141         radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1142
1143         radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1144         radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1145         radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1146         radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1147         radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1148
1149         REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1150         REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1151         if (conf->ext_channel)
1152                 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1153         else
1154                 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1155 }
1156
1157 static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1158 {
1159         struct ath_hw_radar_conf *conf = &ah->radar_conf;
1160
1161         conf->fir_power = -28;
1162         conf->radar_rssi = 0;
1163         conf->pulse_height = 10;
1164         conf->pulse_rssi = 24;
1165         conf->pulse_inband = 8;
1166         conf->pulse_maxlen = 255;
1167         conf->pulse_inband_step = 12;
1168         conf->radar_inband = 8;
1169 }
1170
1171 void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1172 {
1173         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1174         static const u32 ar9300_cca_regs[6] = {
1175                 AR_PHY_CCA_0,
1176                 AR_PHY_CCA_1,
1177                 AR_PHY_CCA_2,
1178                 AR_PHY_EXT_CCA,
1179                 AR_PHY_EXT_CCA_1,
1180                 AR_PHY_EXT_CCA_2,
1181         };
1182
1183         priv_ops->rf_set_freq = ar9003_hw_set_channel;
1184         priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
1185         priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
1186         priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
1187         priv_ops->init_bb = ar9003_hw_init_bb;
1188         priv_ops->process_ini = ar9003_hw_process_ini;
1189         priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1190         priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
1191         priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1192         priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1193         priv_ops->rfbus_done = ar9003_hw_rfbus_done;
1194         priv_ops->set_diversity = ar9003_hw_set_diversity;
1195         priv_ops->ani_control = ar9003_hw_ani_control;
1196         priv_ops->do_getnf = ar9003_hw_do_getnf;
1197         priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
1198         priv_ops->set_radar_params = ar9003_hw_set_radar_params;
1199
1200         ar9003_hw_set_nf_limits(ah);
1201         ar9003_hw_set_radar_conf(ah);
1202         memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
1203 }
1204
1205 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
1206 {
1207         struct ath_common *common = ath9k_hw_common(ah);
1208         u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms;
1209         u32 val, idle_count;
1210
1211         if (!idle_tmo_ms) {
1212                 /* disable IRQ, disable chip-reset for BB panic */
1213                 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1214                           REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &
1215                           ~(AR_PHY_WATCHDOG_RST_ENABLE |
1216                             AR_PHY_WATCHDOG_IRQ_ENABLE));
1217
1218                 /* disable watchdog in non-IDLE mode, disable in IDLE mode */
1219                 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1220                           REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &
1221                           ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1222                             AR_PHY_WATCHDOG_IDLE_ENABLE));
1223
1224                 ath_dbg(common, ATH_DBG_RESET, "Disabled BB Watchdog\n");
1225                 return;
1226         }
1227
1228         /* enable IRQ, disable chip-reset for BB watchdog */
1229         val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;
1230         REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1231                   (val | AR_PHY_WATCHDOG_IRQ_ENABLE) &
1232                   ~AR_PHY_WATCHDOG_RST_ENABLE);
1233
1234         /* bound limit to 10 secs */
1235         if (idle_tmo_ms > 10000)
1236                 idle_tmo_ms = 10000;
1237
1238         /*
1239          * The time unit for watchdog event is 2^15 44/88MHz cycles.
1240          *
1241          * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick
1242          * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick
1243          *
1244          * Given we use fast clock now in 5 GHz, these time units should
1245          * be common for both 2 GHz and 5 GHz.
1246          */
1247         idle_count = (100 * idle_tmo_ms) / 74;
1248         if (ah->curchan && IS_CHAN_HT40(ah->curchan))
1249                 idle_count = (100 * idle_tmo_ms) / 37;
1250
1251         /*
1252          * enable watchdog in non-IDLE mode, disable in IDLE mode,
1253          * set idle time-out.
1254          */
1255         REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1256                   AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1257                   AR_PHY_WATCHDOG_IDLE_MASK |
1258                   (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
1259
1260         ath_dbg(common, ATH_DBG_RESET,
1261                 "Enabled BB Watchdog timeout (%u ms)\n",
1262                 idle_tmo_ms);
1263 }
1264
1265 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
1266 {
1267         /*
1268          * we want to avoid printing in ISR context so we save the
1269          * watchdog status to be printed later in bottom half context.
1270          */
1271         ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);
1272
1273         /*
1274          * the watchdog timer should reset on status read but to be sure
1275          * sure we write 0 to the watchdog status bit.
1276          */
1277         REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
1278                   ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR);
1279 }
1280
1281 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
1282 {
1283         struct ath_common *common = ath9k_hw_common(ah);
1284         u32 status;
1285
1286         if (likely(!(common->debug_mask & ATH_DBG_RESET)))
1287                 return;
1288
1289         status = ah->bb_watchdog_last_status;
1290         ath_dbg(common, ATH_DBG_RESET,
1291                 "\n==== BB update: BB status=0x%08x ====\n", status);
1292         ath_dbg(common, ATH_DBG_RESET,
1293                 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1294                 MS(status, AR_PHY_WATCHDOG_INFO),
1295                 MS(status, AR_PHY_WATCHDOG_DET_HANG),
1296                 MS(status, AR_PHY_WATCHDOG_RADAR_SM),
1297                 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
1298                 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
1299                 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
1300                 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
1301                 MS(status, AR_PHY_WATCHDOG_AGC_SM),
1302                 MS(status, AR_PHY_WATCHDOG_SRCH_SM));
1303
1304         ath_dbg(common, ATH_DBG_RESET,
1305                 "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
1306                 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
1307                 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
1308         ath_dbg(common, ATH_DBG_RESET,
1309                 "** BB mode: BB_gen_controls=0x%08x **\n",
1310                 REG_READ(ah, AR_PHY_GEN_CTRL));
1311
1312 #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
1313         if (common->cc_survey.cycles)
1314                 ath_dbg(common, ATH_DBG_RESET,
1315                         "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n",
1316                         PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
1317
1318         ath_dbg(common, ATH_DBG_RESET,
1319                 "==== BB update: done ====\n\n");
1320 }
1321 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);