mac80211: fix TKIP replay vulnerability
[linux-2.6.git] / drivers / net / wireless / ath / ath5k / initvals.c
1 /*
2  * Initial register settings functions
3  *
4  * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
5  * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
6  * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
7  *
8  * Permission to use, copy, modify, and distribute this software for any
9  * purpose with or without fee is hereby granted, provided that the above
10  * copyright notice and this permission notice appear in all copies.
11  *
12  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19  *
20  */
21
22 #include "ath5k.h"
23 #include "reg.h"
24 #include "debug.h"
25 #include "base.h"
26
27 /*
28  * Mode-independent initial register writes
29  */
30
31 struct ath5k_ini {
32         u16     ini_register;
33         u32     ini_value;
34
35         enum {
36                 AR5K_INI_WRITE = 0,     /* Default */
37                 AR5K_INI_READ = 1,      /* Cleared on read */
38         } ini_mode;
39 };
40
41 /*
42  * Mode specific initial register values
43  */
44
45 struct ath5k_ini_mode {
46         u16     mode_register;
47         u32     mode_value[3];
48 };
49
50 /* Initial register settings for AR5210 */
51 static const struct ath5k_ini ar5210_ini[] = {
52         /* PCU and MAC registers */
53         { AR5K_NOQCU_TXDP0,     0 },
54         { AR5K_NOQCU_TXDP1,     0 },
55         { AR5K_RXDP,            0 },
56         { AR5K_CR,              0 },
57         { AR5K_ISR,             0, AR5K_INI_READ },
58         { AR5K_IMR,             0 },
59         { AR5K_IER,             AR5K_IER_DISABLE },
60         { AR5K_BSR,             0, AR5K_INI_READ },
61         { AR5K_TXCFG,           AR5K_DMASIZE_128B },
62         { AR5K_RXCFG,           AR5K_DMASIZE_128B },
63         { AR5K_CFG,             AR5K_INIT_CFG },
64         { AR5K_TOPS,            8 },
65         { AR5K_RXNOFRM,         8 },
66         { AR5K_RPGTO,           0 },
67         { AR5K_TXNOFRM,         0 },
68         { AR5K_SFR,             0 },
69         { AR5K_MIBC,            0 },
70         { AR5K_MISC,            0 },
71         { AR5K_RX_FILTER_5210,  0 },
72         { AR5K_MCAST_FILTER0_5210, 0 },
73         { AR5K_MCAST_FILTER1_5210, 0 },
74         { AR5K_TX_MASK0,        0 },
75         { AR5K_TX_MASK1,        0 },
76         { AR5K_CLR_TMASK,       0 },
77         { AR5K_TRIG_LVL,        AR5K_TUNE_MIN_TX_FIFO_THRES },
78         { AR5K_DIAG_SW_5210,    0 },
79         { AR5K_RSSI_THR,        AR5K_TUNE_RSSI_THRES },
80         { AR5K_TSF_L32_5210,    0 },
81         { AR5K_TIMER0_5210,     0 },
82         { AR5K_TIMER1_5210,     0xffffffff },
83         { AR5K_TIMER2_5210,     0xffffffff },
84         { AR5K_TIMER3_5210,     1 },
85         { AR5K_CFP_DUR_5210,    0 },
86         { AR5K_CFP_PERIOD_5210, 0 },
87         /* PHY registers */
88         { AR5K_PHY(0),  0x00000047 },
89         { AR5K_PHY_AGC, 0x00000000 },
90         { AR5K_PHY(3),  0x09848ea6 },
91         { AR5K_PHY(4),  0x3d32e000 },
92         { AR5K_PHY(5),  0x0000076b },
93         { AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE },
94         { AR5K_PHY(8),  0x02020200 },
95         { AR5K_PHY(9),  0x00000e0e },
96         { AR5K_PHY(10), 0x0a020201 },
97         { AR5K_PHY(11), 0x00036ffc },
98         { AR5K_PHY(12), 0x00000000 },
99         { AR5K_PHY(13), 0x00000e0e },
100         { AR5K_PHY(14), 0x00000007 },
101         { AR5K_PHY(15), 0x00020100 },
102         { AR5K_PHY(16), 0x89630000 },
103         { AR5K_PHY(17), 0x1372169c },
104         { AR5K_PHY(18), 0x0018b633 },
105         { AR5K_PHY(19), 0x1284613c },
106         { AR5K_PHY(20), 0x0de8b8e0 },
107         { AR5K_PHY(21), 0x00074859 },
108         { AR5K_PHY(22), 0x7e80beba },
109         { AR5K_PHY(23), 0x313a665e },
110         { AR5K_PHY_AGCCTL, 0x00001d08 },
111         { AR5K_PHY(25), 0x0001ce00 },
112         { AR5K_PHY(26), 0x409a4190 },
113         { AR5K_PHY(28), 0x0000000f },
114         { AR5K_PHY(29), 0x00000080 },
115         { AR5K_PHY(30), 0x00000004 },
116         { AR5K_PHY(31), 0x00000018 },   /* 0x987c */
117         { AR5K_PHY(64), 0x00000000 },   /* 0x9900 */
118         { AR5K_PHY(65), 0x00000000 },
119         { AR5K_PHY(66), 0x00000000 },
120         { AR5K_PHY(67), 0x00800000 },
121         { AR5K_PHY(68), 0x00000003 },
122         /* BB gain table (64bytes) */
123         { AR5K_BB_GAIN(0), 0x00000000 },
124         { AR5K_BB_GAIN(1), 0x00000020 },
125         { AR5K_BB_GAIN(2), 0x00000010 },
126         { AR5K_BB_GAIN(3), 0x00000030 },
127         { AR5K_BB_GAIN(4), 0x00000008 },
128         { AR5K_BB_GAIN(5), 0x00000028 },
129         { AR5K_BB_GAIN(6), 0x00000028 },
130         { AR5K_BB_GAIN(7), 0x00000004 },
131         { AR5K_BB_GAIN(8), 0x00000024 },
132         { AR5K_BB_GAIN(9), 0x00000014 },
133         { AR5K_BB_GAIN(10), 0x00000034 },
134         { AR5K_BB_GAIN(11), 0x0000000c },
135         { AR5K_BB_GAIN(12), 0x0000002c },
136         { AR5K_BB_GAIN(13), 0x00000002 },
137         { AR5K_BB_GAIN(14), 0x00000022 },
138         { AR5K_BB_GAIN(15), 0x00000012 },
139         { AR5K_BB_GAIN(16), 0x00000032 },
140         { AR5K_BB_GAIN(17), 0x0000000a },
141         { AR5K_BB_GAIN(18), 0x0000002a },
142         { AR5K_BB_GAIN(19), 0x00000001 },
143         { AR5K_BB_GAIN(20), 0x00000021 },
144         { AR5K_BB_GAIN(21), 0x00000011 },
145         { AR5K_BB_GAIN(22), 0x00000031 },
146         { AR5K_BB_GAIN(23), 0x00000009 },
147         { AR5K_BB_GAIN(24), 0x00000029 },
148         { AR5K_BB_GAIN(25), 0x00000005 },
149         { AR5K_BB_GAIN(26), 0x00000025 },
150         { AR5K_BB_GAIN(27), 0x00000015 },
151         { AR5K_BB_GAIN(28), 0x00000035 },
152         { AR5K_BB_GAIN(29), 0x0000000d },
153         { AR5K_BB_GAIN(30), 0x0000002d },
154         { AR5K_BB_GAIN(31), 0x00000003 },
155         { AR5K_BB_GAIN(32), 0x00000023 },
156         { AR5K_BB_GAIN(33), 0x00000013 },
157         { AR5K_BB_GAIN(34), 0x00000033 },
158         { AR5K_BB_GAIN(35), 0x0000000b },
159         { AR5K_BB_GAIN(36), 0x0000002b },
160         { AR5K_BB_GAIN(37), 0x00000007 },
161         { AR5K_BB_GAIN(38), 0x00000027 },
162         { AR5K_BB_GAIN(39), 0x00000017 },
163         { AR5K_BB_GAIN(40), 0x00000037 },
164         { AR5K_BB_GAIN(41), 0x0000000f },
165         { AR5K_BB_GAIN(42), 0x0000002f },
166         { AR5K_BB_GAIN(43), 0x0000002f },
167         { AR5K_BB_GAIN(44), 0x0000002f },
168         { AR5K_BB_GAIN(45), 0x0000002f },
169         { AR5K_BB_GAIN(46), 0x0000002f },
170         { AR5K_BB_GAIN(47), 0x0000002f },
171         { AR5K_BB_GAIN(48), 0x0000002f },
172         { AR5K_BB_GAIN(49), 0x0000002f },
173         { AR5K_BB_GAIN(50), 0x0000002f },
174         { AR5K_BB_GAIN(51), 0x0000002f },
175         { AR5K_BB_GAIN(52), 0x0000002f },
176         { AR5K_BB_GAIN(53), 0x0000002f },
177         { AR5K_BB_GAIN(54), 0x0000002f },
178         { AR5K_BB_GAIN(55), 0x0000002f },
179         { AR5K_BB_GAIN(56), 0x0000002f },
180         { AR5K_BB_GAIN(57), 0x0000002f },
181         { AR5K_BB_GAIN(58), 0x0000002f },
182         { AR5K_BB_GAIN(59), 0x0000002f },
183         { AR5K_BB_GAIN(60), 0x0000002f },
184         { AR5K_BB_GAIN(61), 0x0000002f },
185         { AR5K_BB_GAIN(62), 0x0000002f },
186         { AR5K_BB_GAIN(63), 0x0000002f },
187         /* 5110 RF gain table (64btes) */
188         { AR5K_RF_GAIN(0), 0x0000001d },
189         { AR5K_RF_GAIN(1), 0x0000005d },
190         { AR5K_RF_GAIN(2), 0x0000009d },
191         { AR5K_RF_GAIN(3), 0x000000dd },
192         { AR5K_RF_GAIN(4), 0x0000011d },
193         { AR5K_RF_GAIN(5), 0x00000021 },
194         { AR5K_RF_GAIN(6), 0x00000061 },
195         { AR5K_RF_GAIN(7), 0x000000a1 },
196         { AR5K_RF_GAIN(8), 0x000000e1 },
197         { AR5K_RF_GAIN(9), 0x00000031 },
198         { AR5K_RF_GAIN(10), 0x00000071 },
199         { AR5K_RF_GAIN(11), 0x000000b1 },
200         { AR5K_RF_GAIN(12), 0x0000001c },
201         { AR5K_RF_GAIN(13), 0x0000005c },
202         { AR5K_RF_GAIN(14), 0x00000029 },
203         { AR5K_RF_GAIN(15), 0x00000069 },
204         { AR5K_RF_GAIN(16), 0x000000a9 },
205         { AR5K_RF_GAIN(17), 0x00000020 },
206         { AR5K_RF_GAIN(18), 0x00000019 },
207         { AR5K_RF_GAIN(19), 0x00000059 },
208         { AR5K_RF_GAIN(20), 0x00000099 },
209         { AR5K_RF_GAIN(21), 0x00000030 },
210         { AR5K_RF_GAIN(22), 0x00000005 },
211         { AR5K_RF_GAIN(23), 0x00000025 },
212         { AR5K_RF_GAIN(24), 0x00000065 },
213         { AR5K_RF_GAIN(25), 0x000000a5 },
214         { AR5K_RF_GAIN(26), 0x00000028 },
215         { AR5K_RF_GAIN(27), 0x00000068 },
216         { AR5K_RF_GAIN(28), 0x0000001f },
217         { AR5K_RF_GAIN(29), 0x0000001e },
218         { AR5K_RF_GAIN(30), 0x00000018 },
219         { AR5K_RF_GAIN(31), 0x00000058 },
220         { AR5K_RF_GAIN(32), 0x00000098 },
221         { AR5K_RF_GAIN(33), 0x00000003 },
222         { AR5K_RF_GAIN(34), 0x00000004 },
223         { AR5K_RF_GAIN(35), 0x00000044 },
224         { AR5K_RF_GAIN(36), 0x00000084 },
225         { AR5K_RF_GAIN(37), 0x00000013 },
226         { AR5K_RF_GAIN(38), 0x00000012 },
227         { AR5K_RF_GAIN(39), 0x00000052 },
228         { AR5K_RF_GAIN(40), 0x00000092 },
229         { AR5K_RF_GAIN(41), 0x000000d2 },
230         { AR5K_RF_GAIN(42), 0x0000002b },
231         { AR5K_RF_GAIN(43), 0x0000002a },
232         { AR5K_RF_GAIN(44), 0x0000006a },
233         { AR5K_RF_GAIN(45), 0x000000aa },
234         { AR5K_RF_GAIN(46), 0x0000001b },
235         { AR5K_RF_GAIN(47), 0x0000001a },
236         { AR5K_RF_GAIN(48), 0x0000005a },
237         { AR5K_RF_GAIN(49), 0x0000009a },
238         { AR5K_RF_GAIN(50), 0x000000da },
239         { AR5K_RF_GAIN(51), 0x00000006 },
240         { AR5K_RF_GAIN(52), 0x00000006 },
241         { AR5K_RF_GAIN(53), 0x00000006 },
242         { AR5K_RF_GAIN(54), 0x00000006 },
243         { AR5K_RF_GAIN(55), 0x00000006 },
244         { AR5K_RF_GAIN(56), 0x00000006 },
245         { AR5K_RF_GAIN(57), 0x00000006 },
246         { AR5K_RF_GAIN(58), 0x00000006 },
247         { AR5K_RF_GAIN(59), 0x00000006 },
248         { AR5K_RF_GAIN(60), 0x00000006 },
249         { AR5K_RF_GAIN(61), 0x00000006 },
250         { AR5K_RF_GAIN(62), 0x00000006 },
251         { AR5K_RF_GAIN(63), 0x00000006 },
252         /* PHY activation */
253         { AR5K_PHY(53), 0x00000020 },
254         { AR5K_PHY(51), 0x00000004 },
255         { AR5K_PHY(50), 0x00060106 },
256         { AR5K_PHY(39), 0x0000006d },
257         { AR5K_PHY(48), 0x00000000 },
258         { AR5K_PHY(52), 0x00000014 },
259         { AR5K_PHY_ACT, AR5K_PHY_ACT_ENABLE },
260 };
261
262 /* Initial register settings for AR5211 */
263 static const struct ath5k_ini ar5211_ini[] = {
264         { AR5K_RXDP,            0x00000000 },
265         { AR5K_RTSD0,           0x84849c9c },
266         { AR5K_RTSD1,           0x7c7c7c7c },
267         { AR5K_RXCFG,           0x00000005 },
268         { AR5K_MIBC,            0x00000000 },
269         { AR5K_TOPS,            0x00000008 },
270         { AR5K_RXNOFRM,         0x00000008 },
271         { AR5K_TXNOFRM,         0x00000010 },
272         { AR5K_RPGTO,           0x00000000 },
273         { AR5K_RFCNT,           0x0000001f },
274         { AR5K_QUEUE_TXDP(0),   0x00000000 },
275         { AR5K_QUEUE_TXDP(1),   0x00000000 },
276         { AR5K_QUEUE_TXDP(2),   0x00000000 },
277         { AR5K_QUEUE_TXDP(3),   0x00000000 },
278         { AR5K_QUEUE_TXDP(4),   0x00000000 },
279         { AR5K_QUEUE_TXDP(5),   0x00000000 },
280         { AR5K_QUEUE_TXDP(6),   0x00000000 },
281         { AR5K_QUEUE_TXDP(7),   0x00000000 },
282         { AR5K_QUEUE_TXDP(8),   0x00000000 },
283         { AR5K_QUEUE_TXDP(9),   0x00000000 },
284         { AR5K_DCU_FP,          0x00000000 },
285         { AR5K_STA_ID1,         0x00000000 },
286         { AR5K_BSS_ID0,         0x00000000 },
287         { AR5K_BSS_ID1,         0x00000000 },
288         { AR5K_RSSI_THR,        0x00000000 },
289         { AR5K_CFP_PERIOD_5211, 0x00000000 },
290         { AR5K_TIMER0_5211,     0x00000030 },
291         { AR5K_TIMER1_5211,     0x0007ffff },
292         { AR5K_TIMER2_5211,     0x01ffffff },
293         { AR5K_TIMER3_5211,     0x00000031 },
294         { AR5K_CFP_DUR_5211,    0x00000000 },
295         { AR5K_RX_FILTER_5211,  0x00000000 },
296         { AR5K_MCAST_FILTER0_5211, 0x00000000 },
297         { AR5K_MCAST_FILTER1_5211, 0x00000002 },
298         { AR5K_DIAG_SW_5211,    0x00000000 },
299         { AR5K_ADDAC_TEST,      0x00000000 },
300         { AR5K_DEFAULT_ANTENNA, 0x00000000 },
301         /* PHY registers */
302         { AR5K_PHY_AGC, 0x00000000 },
303         { AR5K_PHY(3),  0x2d849093 },
304         { AR5K_PHY(4),  0x7d32e000 },
305         { AR5K_PHY(5),  0x00000f6b },
306         { AR5K_PHY_ACT, 0x00000000 },
307         { AR5K_PHY(11), 0x00026ffe },
308         { AR5K_PHY(12), 0x00000000 },
309         { AR5K_PHY(15), 0x00020100 },
310         { AR5K_PHY(16), 0x206a017a },
311         { AR5K_PHY(19), 0x1284613c },
312         { AR5K_PHY(21), 0x00000859 },
313         { AR5K_PHY(26), 0x409a4190 },   /* 0x9868 */
314         { AR5K_PHY(27), 0x050cb081 },
315         { AR5K_PHY(28), 0x0000000f },
316         { AR5K_PHY(29), 0x00000080 },
317         { AR5K_PHY(30), 0x0000000c },
318         { AR5K_PHY(64), 0x00000000 },
319         { AR5K_PHY(65), 0x00000000 },
320         { AR5K_PHY(66), 0x00000000 },
321         { AR5K_PHY(67), 0x00800000 },
322         { AR5K_PHY(68), 0x00000001 },
323         { AR5K_PHY(71), 0x0000092a },
324         { AR5K_PHY_IQ,  0x00000000 },
325         { AR5K_PHY(73), 0x00058a05 },
326         { AR5K_PHY(74), 0x00000001 },
327         { AR5K_PHY(75), 0x00000000 },
328         { AR5K_PHY_PAPD_PROBE, 0x00000000 },
329         { AR5K_PHY(77), 0x00000000 },   /* 0x9934 */
330         { AR5K_PHY(78), 0x00000000 },   /* 0x9938 */
331         { AR5K_PHY(79), 0x0000003f },   /* 0x993c */
332         { AR5K_PHY(80), 0x00000004 },
333         { AR5K_PHY(82), 0x00000000 },
334         { AR5K_PHY(83), 0x00000000 },
335         { AR5K_PHY(84), 0x00000000 },
336         { AR5K_PHY_RADAR, 0x5d50f14c },
337         { AR5K_PHY(86), 0x00000018 },
338         { AR5K_PHY(87), 0x004b6a8e },
339         /* Initial Power table (32bytes)
340          * common on all cards/modes.
341          * Note: Table is rewritten during
342          * txpower setup later using calibration
343          * data etc. so next write is non-common */
344         { AR5K_PHY_PCDAC_TXPOWER(1), 0x06ff05ff },
345         { AR5K_PHY_PCDAC_TXPOWER(2), 0x07ff07ff },
346         { AR5K_PHY_PCDAC_TXPOWER(3), 0x08ff08ff },
347         { AR5K_PHY_PCDAC_TXPOWER(4), 0x09ff09ff },
348         { AR5K_PHY_PCDAC_TXPOWER(5), 0x0aff0aff },
349         { AR5K_PHY_PCDAC_TXPOWER(6), 0x0bff0bff },
350         { AR5K_PHY_PCDAC_TXPOWER(7), 0x0cff0cff },
351         { AR5K_PHY_PCDAC_TXPOWER(8), 0x0dff0dff },
352         { AR5K_PHY_PCDAC_TXPOWER(9), 0x0fff0eff },
353         { AR5K_PHY_PCDAC_TXPOWER(10), 0x12ff12ff },
354         { AR5K_PHY_PCDAC_TXPOWER(11), 0x14ff13ff },
355         { AR5K_PHY_PCDAC_TXPOWER(12), 0x16ff15ff },
356         { AR5K_PHY_PCDAC_TXPOWER(13), 0x19ff17ff },
357         { AR5K_PHY_PCDAC_TXPOWER(14), 0x1bff1aff },
358         { AR5K_PHY_PCDAC_TXPOWER(15), 0x1eff1dff },
359         { AR5K_PHY_PCDAC_TXPOWER(16), 0x23ff20ff },
360         { AR5K_PHY_PCDAC_TXPOWER(17), 0x27ff25ff },
361         { AR5K_PHY_PCDAC_TXPOWER(18), 0x2cff29ff },
362         { AR5K_PHY_PCDAC_TXPOWER(19), 0x31ff2fff },
363         { AR5K_PHY_PCDAC_TXPOWER(20), 0x37ff34ff },
364         { AR5K_PHY_PCDAC_TXPOWER(21), 0x3aff3aff },
365         { AR5K_PHY_PCDAC_TXPOWER(22), 0x3aff3aff },
366         { AR5K_PHY_PCDAC_TXPOWER(23), 0x3aff3aff },
367         { AR5K_PHY_PCDAC_TXPOWER(24), 0x3aff3aff },
368         { AR5K_PHY_PCDAC_TXPOWER(25), 0x3aff3aff },
369         { AR5K_PHY_PCDAC_TXPOWER(26), 0x3aff3aff },
370         { AR5K_PHY_PCDAC_TXPOWER(27), 0x3aff3aff },
371         { AR5K_PHY_PCDAC_TXPOWER(28), 0x3aff3aff },
372         { AR5K_PHY_PCDAC_TXPOWER(29), 0x3aff3aff },
373         { AR5K_PHY_PCDAC_TXPOWER(30), 0x3aff3aff },
374         { AR5K_PHY_PCDAC_TXPOWER(31), 0x3aff3aff },
375         { AR5K_PHY_CCKTXCTL, 0x00000000 },
376         { AR5K_PHY(642), 0x503e4646 },
377         { AR5K_PHY_GAIN_2GHZ, 0x6480416c },
378         { AR5K_PHY(644), 0x0199a003 },
379         { AR5K_PHY(645), 0x044cd610 },
380         { AR5K_PHY(646), 0x13800040 },
381         { AR5K_PHY(647), 0x1be00060 },
382         { AR5K_PHY(648), 0x0c53800a },
383         { AR5K_PHY(649), 0x0014df3b },
384         { AR5K_PHY(650), 0x000001b5 },
385         { AR5K_PHY(651), 0x00000020 },
386 };
387
388 /* Initial mode-specific settings for AR5211
389  * 5211 supports OFDM-only g (draft g) but we
390  * need to test it !
391  */
392 static const struct ath5k_ini_mode ar5211_ini_mode[] = {
393         { AR5K_TXCFG,
394         /*      A/XR          B           G       */
395            { 0x00000015, 0x0000001d, 0x00000015 } },
396         { AR5K_QUEUE_DFS_LOCAL_IFS(0),
397            { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
398         { AR5K_QUEUE_DFS_LOCAL_IFS(1),
399            { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
400         { AR5K_QUEUE_DFS_LOCAL_IFS(2),
401            { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
402         { AR5K_QUEUE_DFS_LOCAL_IFS(3),
403            { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
404         { AR5K_QUEUE_DFS_LOCAL_IFS(4),
405            { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
406         { AR5K_QUEUE_DFS_LOCAL_IFS(5),
407            { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
408         { AR5K_QUEUE_DFS_LOCAL_IFS(6),
409            { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
410         { AR5K_QUEUE_DFS_LOCAL_IFS(7),
411            { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
412         { AR5K_QUEUE_DFS_LOCAL_IFS(8),
413            { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
414         { AR5K_QUEUE_DFS_LOCAL_IFS(9),
415            { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
416         { AR5K_DCU_GBL_IFS_SLOT,
417            { 0x00000168, 0x000001b8, 0x00000168 } },
418         { AR5K_DCU_GBL_IFS_SIFS,
419            { 0x00000230, 0x000000b0, 0x00000230 } },
420         { AR5K_DCU_GBL_IFS_EIFS,
421            { 0x00000d98, 0x00001f48, 0x00000d98 } },
422         { AR5K_DCU_GBL_IFS_MISC,
423            { 0x0000a0e0, 0x00005880, 0x0000a0e0 } },
424         { AR5K_TIME_OUT,
425            { 0x04000400, 0x20003000, 0x04000400 } },
426         { AR5K_USEC_5211,
427            { 0x0e8d8fa7, 0x01608f95, 0x0e8d8fa7 } },
428         { AR5K_PHY(8),
429            { 0x02020200, 0x02010200, 0x02020200 } },
430         { AR5K_PHY_RF_CTL2,
431            { 0x00000e0e, 0x00000707, 0x00000e0e } },
432         { AR5K_PHY_RF_CTL3,
433            { 0x0a020001, 0x05010000, 0x0a020001 } },
434         { AR5K_PHY_RF_CTL4,
435            { 0x00000e0e, 0x00000e0e, 0x00000e0e } },
436         { AR5K_PHY_PA_CTL,
437            { 0x00000007, 0x0000000b, 0x0000000b } },
438         { AR5K_PHY_SETTLING,
439            { 0x1372169c, 0x137216a8, 0x1372169c } },
440         { AR5K_PHY_GAIN,
441            { 0x0018ba67, 0x0018ba69, 0x0018ba69 } },
442         { AR5K_PHY_DESIRED_SIZE,
443            { 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0 } },
444         { AR5K_PHY_SIG,
445            { 0x7e800d2e, 0x7ec00d2e, 0x7e800d2e } },
446         { AR5K_PHY_AGCCOARSE,
447            { 0x31375d5e, 0x313a5d5e, 0x31375d5e } },
448         { AR5K_PHY_AGCCTL,
449            { 0x0000bd10, 0x0000bd38, 0x0000bd10 } },
450         { AR5K_PHY_NF,
451            { 0x0001ce00, 0x0001ce00, 0x0001ce00 } },
452         { AR5K_PHY_RX_DELAY,
453            { 0x00002710, 0x0000157c, 0x00002710 } },
454         { AR5K_PHY(70),
455            { 0x00000190, 0x00000084, 0x00000190 } },
456         { AR5K_PHY_FRAME_CTL_5211,
457            { 0x6fe01020, 0x6fe00920, 0x6fe01020 } },
458         { AR5K_PHY_PCDAC_TXPOWER_BASE,
459            { 0x05ff14ff, 0x05ff14ff, 0x05ff19ff } },
460         { AR5K_RF_BUFFER_CONTROL_4,
461            { 0x00000010, 0x00000010, 0x00000010 } },
462 };
463
464 /* Initial register settings for AR5212 */
465 static const struct ath5k_ini ar5212_ini_common_start[] = {
466         { AR5K_RXDP,            0x00000000 },
467         { AR5K_RXCFG,           0x00000005 },
468         { AR5K_MIBC,            0x00000000 },
469         { AR5K_TOPS,            0x00000008 },
470         { AR5K_RXNOFRM,         0x00000008 },
471         { AR5K_TXNOFRM,         0x00000010 },
472         { AR5K_RPGTO,           0x00000000 },
473         { AR5K_RFCNT,           0x0000001f },
474         { AR5K_QUEUE_TXDP(0),   0x00000000 },
475         { AR5K_QUEUE_TXDP(1),   0x00000000 },
476         { AR5K_QUEUE_TXDP(2),   0x00000000 },
477         { AR5K_QUEUE_TXDP(3),   0x00000000 },
478         { AR5K_QUEUE_TXDP(4),   0x00000000 },
479         { AR5K_QUEUE_TXDP(5),   0x00000000 },
480         { AR5K_QUEUE_TXDP(6),   0x00000000 },
481         { AR5K_QUEUE_TXDP(7),   0x00000000 },
482         { AR5K_QUEUE_TXDP(8),   0x00000000 },
483         { AR5K_QUEUE_TXDP(9),   0x00000000 },
484         { AR5K_DCU_FP,          0x00000000 },
485         { AR5K_DCU_TXP,         0x00000000 },
486         /* Tx filter table 0 (32 entries) */
487         { AR5K_DCU_TX_FILTER_0(0),  0x00000000 }, /* DCU 0 */
488         { AR5K_DCU_TX_FILTER_0(1),  0x00000000 },
489         { AR5K_DCU_TX_FILTER_0(2),  0x00000000 },
490         { AR5K_DCU_TX_FILTER_0(3),  0x00000000 },
491         { AR5K_DCU_TX_FILTER_0(4),  0x00000000 }, /* DCU 1 */
492         { AR5K_DCU_TX_FILTER_0(5),  0x00000000 },
493         { AR5K_DCU_TX_FILTER_0(6),  0x00000000 },
494         { AR5K_DCU_TX_FILTER_0(7),  0x00000000 },
495         { AR5K_DCU_TX_FILTER_0(8),  0x00000000 }, /* DCU 2 */
496         { AR5K_DCU_TX_FILTER_0(9),  0x00000000 },
497         { AR5K_DCU_TX_FILTER_0(10), 0x00000000 },
498         { AR5K_DCU_TX_FILTER_0(11), 0x00000000 },
499         { AR5K_DCU_TX_FILTER_0(12), 0x00000000 }, /* DCU 3 */
500         { AR5K_DCU_TX_FILTER_0(13), 0x00000000 },
501         { AR5K_DCU_TX_FILTER_0(14), 0x00000000 },
502         { AR5K_DCU_TX_FILTER_0(15), 0x00000000 },
503         { AR5K_DCU_TX_FILTER_0(16), 0x00000000 }, /* DCU 4 */
504         { AR5K_DCU_TX_FILTER_0(17), 0x00000000 },
505         { AR5K_DCU_TX_FILTER_0(18), 0x00000000 },
506         { AR5K_DCU_TX_FILTER_0(19), 0x00000000 },
507         { AR5K_DCU_TX_FILTER_0(20), 0x00000000 }, /* DCU 5 */
508         { AR5K_DCU_TX_FILTER_0(21), 0x00000000 },
509         { AR5K_DCU_TX_FILTER_0(22), 0x00000000 },
510         { AR5K_DCU_TX_FILTER_0(23), 0x00000000 },
511         { AR5K_DCU_TX_FILTER_0(24), 0x00000000 }, /* DCU 6 */
512         { AR5K_DCU_TX_FILTER_0(25), 0x00000000 },
513         { AR5K_DCU_TX_FILTER_0(26), 0x00000000 },
514         { AR5K_DCU_TX_FILTER_0(27), 0x00000000 },
515         { AR5K_DCU_TX_FILTER_0(28), 0x00000000 }, /* DCU 7 */
516         { AR5K_DCU_TX_FILTER_0(29), 0x00000000 },
517         { AR5K_DCU_TX_FILTER_0(30), 0x00000000 },
518         { AR5K_DCU_TX_FILTER_0(31), 0x00000000 },
519         /* Tx filter table 1 (16 entries) */
520         { AR5K_DCU_TX_FILTER_1(0),  0x00000000 },
521         { AR5K_DCU_TX_FILTER_1(1),  0x00000000 },
522         { AR5K_DCU_TX_FILTER_1(2),  0x00000000 },
523         { AR5K_DCU_TX_FILTER_1(3),  0x00000000 },
524         { AR5K_DCU_TX_FILTER_1(4),  0x00000000 },
525         { AR5K_DCU_TX_FILTER_1(5),  0x00000000 },
526         { AR5K_DCU_TX_FILTER_1(6),  0x00000000 },
527         { AR5K_DCU_TX_FILTER_1(7),  0x00000000 },
528         { AR5K_DCU_TX_FILTER_1(8),  0x00000000 },
529         { AR5K_DCU_TX_FILTER_1(9),  0x00000000 },
530         { AR5K_DCU_TX_FILTER_1(10), 0x00000000 },
531         { AR5K_DCU_TX_FILTER_1(11), 0x00000000 },
532         { AR5K_DCU_TX_FILTER_1(12), 0x00000000 },
533         { AR5K_DCU_TX_FILTER_1(13), 0x00000000 },
534         { AR5K_DCU_TX_FILTER_1(14), 0x00000000 },
535         { AR5K_DCU_TX_FILTER_1(15), 0x00000000 },
536         { AR5K_DCU_TX_FILTER_CLR, 0x00000000 },
537         { AR5K_DCU_TX_FILTER_SET, 0x00000000 },
538         { AR5K_STA_ID1,         0x00000000 },
539         { AR5K_BSS_ID0,         0x00000000 },
540         { AR5K_BSS_ID1,         0x00000000 },
541         { AR5K_BEACON_5211,     0x00000000 },
542         { AR5K_CFP_PERIOD_5211, 0x00000000 },
543         { AR5K_TIMER0_5211,     0x00000030 },
544         { AR5K_TIMER1_5211,     0x0007ffff },
545         { AR5K_TIMER2_5211,     0x01ffffff },
546         { AR5K_TIMER3_5211,     0x00000031 },
547         { AR5K_CFP_DUR_5211,    0x00000000 },
548         { AR5K_RX_FILTER_5211,  0x00000000 },
549         { AR5K_DIAG_SW_5211,    0x00000000 },
550         { AR5K_ADDAC_TEST,      0x00000000 },
551         { AR5K_DEFAULT_ANTENNA, 0x00000000 },
552         { AR5K_FRAME_CTL_QOSM,  0x000fc78f },
553         { AR5K_XRMODE,          0x2a82301a },
554         { AR5K_XRDELAY,         0x05dc01e0 },
555         { AR5K_XRTIMEOUT,       0x1f402710 },
556         { AR5K_XRCHIRP,         0x01f40000 },
557         { AR5K_XRSTOMP,         0x00001e1c },
558         { AR5K_SLEEP0,          0x0002aaaa },
559         { AR5K_SLEEP1,          0x02005555 },
560         { AR5K_SLEEP2,          0x00000000 },
561         { AR_BSSMSKL,           0xffffffff },
562         { AR_BSSMSKU,           0x0000ffff },
563         { AR5K_TXPC,            0x00000000 },
564         { AR5K_PROFCNT_TX,      0x00000000 },
565         { AR5K_PROFCNT_RX,      0x00000000 },
566         { AR5K_PROFCNT_RXCLR,   0x00000000 },
567         { AR5K_PROFCNT_CYCLE,   0x00000000 },
568         { AR5K_QUIET_CTL1,      0x00000088 },
569         /* Initial rate duration table (32 entries )*/
570         { AR5K_RATE_DUR(0),     0x00000000 },
571         { AR5K_RATE_DUR(1),     0x0000008c },
572         { AR5K_RATE_DUR(2),     0x000000e4 },
573         { AR5K_RATE_DUR(3),     0x000002d5 },
574         { AR5K_RATE_DUR(4),     0x00000000 },
575         { AR5K_RATE_DUR(5),     0x00000000 },
576         { AR5K_RATE_DUR(6),     0x000000a0 },
577         { AR5K_RATE_DUR(7),     0x000001c9 },
578         { AR5K_RATE_DUR(8),     0x0000002c },
579         { AR5K_RATE_DUR(9),     0x0000002c },
580         { AR5K_RATE_DUR(10),    0x00000030 },
581         { AR5K_RATE_DUR(11),    0x0000003c },
582         { AR5K_RATE_DUR(12),    0x0000002c },
583         { AR5K_RATE_DUR(13),    0x0000002c },
584         { AR5K_RATE_DUR(14),    0x00000030 },
585         { AR5K_RATE_DUR(15),    0x0000003c },
586         { AR5K_RATE_DUR(16),    0x00000000 },
587         { AR5K_RATE_DUR(17),    0x00000000 },
588         { AR5K_RATE_DUR(18),    0x00000000 },
589         { AR5K_RATE_DUR(19),    0x00000000 },
590         { AR5K_RATE_DUR(20),    0x00000000 },
591         { AR5K_RATE_DUR(21),    0x00000000 },
592         { AR5K_RATE_DUR(22),    0x00000000 },
593         { AR5K_RATE_DUR(23),    0x00000000 },
594         { AR5K_RATE_DUR(24),    0x000000d5 },
595         { AR5K_RATE_DUR(25),    0x000000df },
596         { AR5K_RATE_DUR(26),    0x00000102 },
597         { AR5K_RATE_DUR(27),    0x0000013a },
598         { AR5K_RATE_DUR(28),    0x00000075 },
599         { AR5K_RATE_DUR(29),    0x0000007f },
600         { AR5K_RATE_DUR(30),    0x000000a2 },
601         { AR5K_RATE_DUR(31),    0x00000000 },
602         { AR5K_QUIET_CTL2,      0x00010002 },
603         { AR5K_TSF_PARM,        0x00000001 },
604         { AR5K_QOS_NOACK,       0x000000c0 },
605         { AR5K_PHY_ERR_FIL,     0x00000000 },
606         { AR5K_XRLAT_TX,        0x00000168 },
607         { AR5K_ACKSIFS,         0x00000000 },
608         /* Rate -> db table
609          * notice ...03<-02<-01<-00 ! */
610         { AR5K_RATE2DB(0),      0x03020100 },
611         { AR5K_RATE2DB(1),      0x07060504 },
612         { AR5K_RATE2DB(2),      0x0b0a0908 },
613         { AR5K_RATE2DB(3),      0x0f0e0d0c },
614         { AR5K_RATE2DB(4),      0x13121110 },
615         { AR5K_RATE2DB(5),      0x17161514 },
616         { AR5K_RATE2DB(6),      0x1b1a1918 },
617         { AR5K_RATE2DB(7),      0x1f1e1d1c },
618         /* Db -> Rate table */
619         { AR5K_DB2RATE(0),      0x03020100 },
620         { AR5K_DB2RATE(1),      0x07060504 },
621         { AR5K_DB2RATE(2),      0x0b0a0908 },
622         { AR5K_DB2RATE(3),      0x0f0e0d0c },
623         { AR5K_DB2RATE(4),      0x13121110 },
624         { AR5K_DB2RATE(5),      0x17161514 },
625         { AR5K_DB2RATE(6),      0x1b1a1918 },
626         { AR5K_DB2RATE(7),      0x1f1e1d1c },
627         /* PHY registers (Common settings
628          * for all chips/modes) */
629         { AR5K_PHY(3),          0xad848e19 },
630         { AR5K_PHY(4),          0x7d28e000 },
631         { AR5K_PHY_TIMING_3,    0x9c0a9f6b },
632         { AR5K_PHY_ACT,         0x00000000 },
633         { AR5K_PHY(16),         0x206a017a },
634         { AR5K_PHY(21),         0x00000859 },
635         { AR5K_PHY_BIN_MASK_1,  0x00000000 },
636         { AR5K_PHY_BIN_MASK_2,  0x00000000 },
637         { AR5K_PHY_BIN_MASK_3,  0x00000000 },
638         { AR5K_PHY_BIN_MASK_CTL, 0x00800000 },
639         { AR5K_PHY_ANT_CTL,     0x00000001 },
640         /*{ AR5K_PHY(71), 0x0000092a },*/ /* Old value */
641         { AR5K_PHY_MAX_RX_LEN,  0x00000c80 },
642         { AR5K_PHY_IQ,          0x05100000 },
643         { AR5K_PHY_WARM_RESET,  0x00000001 },
644         { AR5K_PHY_CTL,         0x00000004 },
645         { AR5K_PHY_TXPOWER_RATE1, 0x1e1f2022 },
646         { AR5K_PHY_TXPOWER_RATE2, 0x0a0b0c0d },
647         { AR5K_PHY_TXPOWER_RATE_MAX, 0x0000003f },
648         { AR5K_PHY(82),         0x9280b212 },
649         { AR5K_PHY_RADAR,       0x5d50e188 },
650         /*{ AR5K_PHY(86), 0x000000ff },*/
651         { AR5K_PHY(87),         0x004b6a8e },
652         { AR5K_PHY_NFTHRES,     0x000003ce },
653         { AR5K_PHY_RESTART,     0x192fb515 },
654         { AR5K_PHY(94),         0x00000001 },
655         { AR5K_PHY_RFBUS_REQ,   0x00000000 },
656         /*{ AR5K_PHY(644), 0x0080a333 },*/ /* Old value */
657         /*{ AR5K_PHY(645), 0x00206c10 },*/ /* Old value */
658         { AR5K_PHY(644),        0x00806333 },
659         { AR5K_PHY(645),        0x00106c10 },
660         { AR5K_PHY(646),        0x009c4060 },
661         /* { AR5K_PHY(647), 0x1483800a }, */
662         /* { AR5K_PHY(648), 0x01831061 }, */ /* Old value */
663         { AR5K_PHY(648),        0x018830c6 },
664         { AR5K_PHY(649),        0x00000400 },
665         /*{ AR5K_PHY(650), 0x000001b5 },*/
666         { AR5K_PHY(651),        0x00000000 },
667         { AR5K_PHY_TXPOWER_RATE3, 0x20202020 },
668         { AR5K_PHY_TXPOWER_RATE4, 0x20202020 },
669         /*{ AR5K_PHY(655), 0x13c889af },*/
670         { AR5K_PHY(656),        0x38490a20 },
671         { AR5K_PHY(657),        0x00007bb6 },
672         { AR5K_PHY(658),        0x0fff3ffc },
673 };
674
675 /* Initial mode-specific settings for AR5212 (Written before ar5212_ini) */
676 static const struct ath5k_ini_mode ar5212_ini_mode_start[] = {
677         { AR5K_QUEUE_DFS_LOCAL_IFS(0),
678         /*      A/XR          B           G       */
679            { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
680         { AR5K_QUEUE_DFS_LOCAL_IFS(1),
681            { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
682         { AR5K_QUEUE_DFS_LOCAL_IFS(2),
683            { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
684         { AR5K_QUEUE_DFS_LOCAL_IFS(3),
685            { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
686         { AR5K_QUEUE_DFS_LOCAL_IFS(4),
687            { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
688         { AR5K_QUEUE_DFS_LOCAL_IFS(5),
689            { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
690         { AR5K_QUEUE_DFS_LOCAL_IFS(6),
691            { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
692         { AR5K_QUEUE_DFS_LOCAL_IFS(7),
693            { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
694         { AR5K_QUEUE_DFS_LOCAL_IFS(8),
695            { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
696         { AR5K_QUEUE_DFS_LOCAL_IFS(9),
697            { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
698         { AR5K_DCU_GBL_IFS_SIFS,
699            { 0x00000230, 0x000000b0, 0x00000160 } },
700         { AR5K_DCU_GBL_IFS_SLOT,
701            { 0x00000168, 0x000001b8, 0x0000018c } },
702         { AR5K_DCU_GBL_IFS_EIFS,
703            { 0x00000e60, 0x00001f1c, 0x00003e38 } },
704         { AR5K_DCU_GBL_IFS_MISC,
705            { 0x0000a0e0, 0x00005880, 0x0000b0e0 } },
706         { AR5K_TIME_OUT,
707            { 0x03e803e8, 0x04200420, 0x08400840 } },
708         { AR5K_PHY(8),
709            { 0x02020200, 0x02010200, 0x02020200 } },
710         { AR5K_PHY_RF_CTL2,
711            { 0x00000e0e, 0x00000707, 0x00000e0e } },
712         { AR5K_PHY_SETTLING,
713            { 0x1372161c, 0x13721722, 0x137216a2 } },
714         { AR5K_PHY_AGCCTL,
715            { 0x00009d10, 0x00009d18, 0x00009d18 } },
716         { AR5K_PHY_NF,
717            { 0x0001ce00, 0x0001ce00, 0x0001ce00 } },
718         { AR5K_PHY_WEAK_OFDM_HIGH_THR,
719            { 0x409a4190, 0x409a4190, 0x409a4190 } },
720         { AR5K_PHY(70),
721            { 0x000001b8, 0x00000084, 0x00000108 } },
722         { AR5K_PHY_OFDM_SELFCORR,
723            { 0x10058a05, 0x10058a05, 0x10058a05 } },
724         { 0xa230,
725            { 0x00000000, 0x00000000, 0x00000108 } },
726 };
727
728 /* Initial mode-specific settings for AR5212 + RF5111 (Written after ar5212_ini) */
729 static const struct ath5k_ini_mode rf5111_ini_mode_end[] = {
730         { AR5K_TXCFG,
731         /*      A/XR          B           G       */
732            { 0x00008015, 0x00008015, 0x00008015 } },
733         { AR5K_USEC_5211,
734            { 0x128d8fa7, 0x04e00f95, 0x12e00fab } },
735         { AR5K_PHY_RF_CTL3,
736            { 0x0a020001, 0x05010100, 0x0a020001 } },
737         { AR5K_PHY_RF_CTL4,
738            { 0x00000e0e, 0x00000e0e, 0x00000e0e } },
739         { AR5K_PHY_PA_CTL,
740            { 0x00000007, 0x0000000b, 0x0000000b } },
741         { AR5K_PHY_GAIN,
742            { 0x0018da5a, 0x0018ca69, 0x0018ca69 } },
743         { AR5K_PHY_DESIRED_SIZE,
744            { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } },
745         { AR5K_PHY_SIG,
746            { 0x7e800d2e, 0x7ee84d2e, 0x7ee84d2e } },
747         { AR5K_PHY_AGCCOARSE,
748            { 0x3137665e, 0x3137665e, 0x3137665e } },
749         { AR5K_PHY_WEAK_OFDM_LOW_THR,
750            { 0x050cb081, 0x050cb081, 0x050cb080 } },
751         { AR5K_PHY_RX_DELAY,
752            { 0x00002710, 0x0000157c, 0x00002af8 } },
753         { AR5K_PHY_FRAME_CTL_5211,
754            { 0xf7b81020, 0xf7b80d20, 0xf7b81020 } },
755         { AR5K_PHY_GAIN_2GHZ,
756            { 0x642c416a, 0x6440416a, 0x6440416a } },
757         { AR5K_PHY_CCK_RX_CTL_4,
758            { 0x1883800a, 0x1873800a, 0x1883800a } },
759 };
760
761 static const struct ath5k_ini rf5111_ini_common_end[] = {
762         { AR5K_DCU_FP,          0x00000000 },
763         { AR5K_PHY_AGC,         0x00000000 },
764         { AR5K_PHY_ADC_CTL,     0x00022ffe },
765         { 0x983c,               0x00020100 },
766         { AR5K_PHY_GAIN_OFFSET, 0x1284613c },
767         { AR5K_PHY_PAPD_PROBE,  0x00004883 },
768         { 0x9940,               0x00000004 },
769         { 0x9958,               0x000000ff },
770         { 0x9974,               0x00000000 },
771         { AR5K_PHY_SPENDING,    0x00000018 },
772         { AR5K_PHY_CCKTXCTL,    0x00000000 },
773         { AR5K_PHY_CCK_CROSSCORR, 0xd03e6788 },
774         { AR5K_PHY_DAG_CCK_CTL, 0x000001b5 },
775         { 0xa23c,               0x13c889af },
776 };
777
778 /* Initial mode-specific settings for AR5212 + RF5112 (Written after ar5212_ini) */
779 static const struct ath5k_ini_mode rf5112_ini_mode_end[] = {
780         { AR5K_TXCFG,
781         /*      A/XR          B           G       */
782            { 0x00008015, 0x00008015, 0x00008015 } },
783         { AR5K_USEC_5211,
784            { 0x128d93a7, 0x04e01395, 0x12e013ab } },
785         { AR5K_PHY_RF_CTL3,
786            { 0x0a020001, 0x05020100, 0x0a020001 } },
787         { AR5K_PHY_RF_CTL4,
788            { 0x00000e0e, 0x00000e0e, 0x00000e0e } },
789         { AR5K_PHY_PA_CTL,
790            { 0x00000007, 0x0000000b, 0x0000000b } },
791         { AR5K_PHY_GAIN,
792            { 0x0018da6d, 0x0018ca75, 0x0018ca75 } },
793         { AR5K_PHY_DESIRED_SIZE,
794            { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } },
795         { AR5K_PHY_SIG,
796            { 0x7e800d2e, 0x7ee80d2e, 0x7ee80d2e } },
797         { AR5K_PHY_AGCCOARSE,
798            { 0x3137665e, 0x3137665e, 0x3137665e } },
799         { AR5K_PHY_WEAK_OFDM_LOW_THR,
800            { 0x050cb081, 0x050cb081, 0x050cb081 } },
801         { AR5K_PHY_RX_DELAY,
802            { 0x000007d0, 0x0000044c, 0x00000898 } },
803         { AR5K_PHY_FRAME_CTL_5211,
804            { 0xf7b81020, 0xf7b80d10, 0xf7b81010 } },
805         { AR5K_PHY_CCKTXCTL,
806            { 0x00000000, 0x00000008, 0x00000008 } },
807         { AR5K_PHY_CCK_CROSSCORR,
808            { 0xd6be6788, 0xd03e6788, 0xd03e6788 } },
809         { AR5K_PHY_GAIN_2GHZ,
810            { 0x642c0140, 0x6442c160, 0x6442c160 } },
811         { AR5K_PHY_CCK_RX_CTL_4,
812            { 0x1883800a, 0x1873800a, 0x1883800a } },
813 };
814
815 static const struct ath5k_ini rf5112_ini_common_end[] = {
816         { AR5K_DCU_FP,          0x00000000 },
817         { AR5K_PHY_AGC,         0x00000000 },
818         { AR5K_PHY_ADC_CTL,     0x00022ffe },
819         { 0x983c,               0x00020100 },
820         { AR5K_PHY_GAIN_OFFSET, 0x1284613c },
821         { AR5K_PHY_PAPD_PROBE,  0x00004882 },
822         { 0x9940,               0x00000004 },
823         { 0x9958,               0x000000ff },
824         { 0x9974,               0x00000000 },
825         { AR5K_PHY_DAG_CCK_CTL, 0x000001b5 },
826         { 0xa23c,               0x13c889af },
827 };
828
829 /* Initial mode-specific settings for RF5413/5414 (Written after ar5212_ini) */
830 static const struct ath5k_ini_mode rf5413_ini_mode_end[] = {
831         { AR5K_TXCFG,
832         /*      A/XR          B           G       */
833            { 0x00000015, 0x00000015, 0x00000015 } },
834         { AR5K_USEC_5211,
835            { 0x128d93a7, 0x04e01395, 0x12e013ab } },
836         { AR5K_PHY_RF_CTL3,
837            { 0x0a020001, 0x05020100, 0x0a020001 } },
838         { AR5K_PHY_RF_CTL4,
839            { 0x00000e0e, 0x00000e0e, 0x00000e0e } },
840         { AR5K_PHY_PA_CTL,
841            { 0x00000007, 0x0000000b, 0x0000000b } },
842         { AR5K_PHY_GAIN,
843            { 0x0018fa61, 0x001a1a63, 0x001a1a63 } },
844         { AR5K_PHY_DESIRED_SIZE,
845            { 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da } },
846         { AR5K_PHY_SIG,
847            { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } },
848         { AR5K_PHY_AGCCOARSE,
849            { 0x3139605e, 0x3139605e, 0x3139605e } },
850         { AR5K_PHY_WEAK_OFDM_LOW_THR,
851            { 0x050cb081, 0x050cb081, 0x050cb081 } },
852         { AR5K_PHY_RX_DELAY,
853            { 0x000007d0, 0x0000044c, 0x00000898 } },
854         { AR5K_PHY_FRAME_CTL_5211,
855            { 0xf7b81000, 0xf7b80d00, 0xf7b81000 } },
856         { AR5K_PHY_CCKTXCTL,
857            { 0x00000000, 0x00000000, 0x00000000 } },
858         { AR5K_PHY_CCK_CROSSCORR,
859            { 0xd6be6788, 0xd03e6788, 0xd03e6788 } },
860         { AR5K_PHY_GAIN_2GHZ,
861            { 0x002ec1e0, 0x002ac120, 0x002ac120 } },
862         { AR5K_PHY_CCK_RX_CTL_4,
863            { 0x1883800a, 0x1863800a, 0x1883800a } },
864         { 0xa300,
865            { 0x18010000, 0x18010000, 0x18010000 } },
866         { 0xa304,
867            { 0x30032602, 0x30032602, 0x30032602 } },
868         { 0xa308,
869            { 0x48073e06, 0x48073e06, 0x48073e06 } },
870         { 0xa30c,
871            { 0x560b4c0a, 0x560b4c0a, 0x560b4c0a } },
872         { 0xa310,
873            { 0x641a600f, 0x641a600f, 0x641a600f } },
874         { 0xa314,
875            { 0x784f6e1b, 0x784f6e1b, 0x784f6e1b } },
876         { 0xa318,
877            { 0x868f7c5a, 0x868f7c5a, 0x868f7c5a } },
878         { 0xa31c,
879            { 0x90cf865b, 0x8ecf865b, 0x8ecf865b } },
880         { 0xa320,
881            { 0x9d4f970f, 0x9b4f970f, 0x9b4f970f } },
882         { 0xa324,
883            { 0xa7cfa38f, 0xa3cf9f8f, 0xa3cf9f8f } },
884         { 0xa328,
885            { 0xb55faf1f, 0xb35faf1f, 0xb35faf1f } },
886         { 0xa32c,
887            { 0xbddfb99f, 0xbbdfb99f, 0xbbdfb99f } },
888         { 0xa330,
889            { 0xcb7fc53f, 0xcb7fc73f, 0xcb7fc73f } },
890         { 0xa334,
891            { 0xd5ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf } },
892 };
893
894 static const struct ath5k_ini rf5413_ini_common_end[] = {
895         { AR5K_DCU_FP,          0x000003e0 },
896         { AR5K_5414_CBCFG,      0x00000010 },
897         { AR5K_SEQ_MASK,        0x0000000f },
898         { 0x809c,               0x00000000 },
899         { 0x80a0,               0x00000000 },
900         { AR5K_MIC_QOS_CTL,     0x00000000 },
901         { AR5K_MIC_QOS_SEL,     0x00000000 },
902         { AR5K_MISC_MODE,       0x00000000 },
903         { AR5K_OFDM_FIL_CNT,    0x00000000 },
904         { AR5K_CCK_FIL_CNT,     0x00000000 },
905         { AR5K_PHYERR_CNT1,     0x00000000 },
906         { AR5K_PHYERR_CNT1_MASK, 0x00000000 },
907         { AR5K_PHYERR_CNT2,     0x00000000 },
908         { AR5K_PHYERR_CNT2_MASK, 0x00000000 },
909         { AR5K_TSF_THRES,       0x00000000 },
910         { 0x8140,               0x800003f9 },
911         { 0x8144,               0x00000000 },
912         { AR5K_PHY_AGC,         0x00000000 },
913         { AR5K_PHY_ADC_CTL,     0x0000a000 },
914         { 0x983c,               0x00200400 },
915         { AR5K_PHY_GAIN_OFFSET, 0x1284233c },
916         { AR5K_PHY_SCR,         0x0000001f },
917         { AR5K_PHY_SLMT,        0x00000080 },
918         { AR5K_PHY_SCAL,        0x0000000e },
919         { 0x9958,               0x00081fff },
920         { AR5K_PHY_TIMING_7,    0x00000000 },
921         { AR5K_PHY_TIMING_8,    0x02800000 },
922         { AR5K_PHY_TIMING_11,   0x00000000 },
923         { AR5K_PHY_HEAVY_CLIP_ENABLE, 0x00000000 },
924         { 0x99e4,               0xaaaaaaaa },
925         { 0x99e8,               0x3c466478 },
926         { 0x99ec,               0x000000aa },
927         { AR5K_PHY_SCLOCK,      0x0000000c },
928         { AR5K_PHY_SDELAY,      0x000000ff },
929         { AR5K_PHY_SPENDING,    0x00000014 },
930         { AR5K_PHY_DAG_CCK_CTL, 0x000009b5 },
931         { 0xa23c,               0x93c889af },
932         { AR5K_PHY_FAST_ADC,    0x00000001 },
933         { 0xa250,               0x0000a000 },
934         { AR5K_PHY_BLUETOOTH,   0x00000000 },
935         { AR5K_PHY_TPC_RG1,     0x0cc75380 },
936         { 0xa25c,               0x0f0f0f01 },
937         { 0xa260,               0x5f690f01 },
938         { 0xa264,               0x00418a11 },
939         { 0xa268,               0x00000000 },
940         { AR5K_PHY_TPC_RG5,     0x0c30c16a },
941         { 0xa270, 0x00820820 },
942         { 0xa274, 0x081b7caa },
943         { 0xa278, 0x1ce739ce },
944         { 0xa27c, 0x051701ce },
945         { 0xa338, 0x00000000 },
946         { 0xa33c, 0x00000000 },
947         { 0xa340, 0x00000000 },
948         { 0xa344, 0x00000000 },
949         { 0xa348, 0x3fffffff },
950         { 0xa34c, 0x3fffffff },
951         { 0xa350, 0x3fffffff },
952         { 0xa354, 0x0003ffff },
953         { 0xa358, 0x79a8aa1f },
954         { 0xa35c, 0x066c420f },
955         { 0xa360, 0x0f282207 },
956         { 0xa364, 0x17601685 },
957         { 0xa368, 0x1f801104 },
958         { 0xa36c, 0x37a00c03 },
959         { 0xa370, 0x3fc40883 },
960         { 0xa374, 0x57c00803 },
961         { 0xa378, 0x5fd80682 },
962         { 0xa37c, 0x7fe00482 },
963         { 0xa380, 0x7f3c7bba },
964         { 0xa384, 0xf3307ff0 },
965 };
966
967 /* Initial mode-specific settings for RF2413/2414 (Written after ar5212_ini) */
968 /* XXX: a mode ? */
969 static const struct ath5k_ini_mode rf2413_ini_mode_end[] = {
970         { AR5K_TXCFG,
971         /*      A/XR          B           G       */
972            { 0x00000015, 0x00000015, 0x00000015 } },
973         { AR5K_USEC_5211,
974            { 0x128d93a7, 0x04e01395, 0x12e013ab } },
975         { AR5K_PHY_RF_CTL3,
976            { 0x0a020001, 0x05020000, 0x0a020001 } },
977         { AR5K_PHY_RF_CTL4,
978            { 0x00000e00, 0x00000e00, 0x00000e00 } },
979         { AR5K_PHY_PA_CTL,
980            { 0x00000002, 0x0000000a, 0x0000000a } },
981         { AR5K_PHY_GAIN,
982            { 0x0018da6d, 0x001a6a64, 0x001a6a64 } },
983         { AR5K_PHY_DESIRED_SIZE,
984            { 0x0de8b4e0, 0x0de8b0da, 0x0c98b0da } },
985         { AR5K_PHY_SIG,
986            { 0x7e800d2e, 0x7ee80d2e, 0x7ec80d2e } },
987         { AR5K_PHY_AGCCOARSE,
988            { 0x3137665e, 0x3137665e, 0x3139605e } },
989         { AR5K_PHY_WEAK_OFDM_LOW_THR,
990            { 0x050cb081, 0x050cb081, 0x050cb081 } },
991         { AR5K_PHY_RX_DELAY,
992            { 0x000007d0, 0x0000044c, 0x00000898 } },
993         { AR5K_PHY_FRAME_CTL_5211,
994            { 0xf7b81000, 0xf7b80d00, 0xf7b81000 } },
995         { AR5K_PHY_CCKTXCTL,
996            { 0x00000000, 0x00000000, 0x00000000 } },
997         { AR5K_PHY_CCK_CROSSCORR,
998            { 0xd6be6788, 0xd03e6788, 0xd03e6788 } },
999         { AR5K_PHY_GAIN_2GHZ,
1000            { 0x002c0140, 0x0042c140, 0x0042c140 } },
1001         { AR5K_PHY_CCK_RX_CTL_4,
1002            { 0x1883800a, 0x1863800a, 0x1883800a } },
1003 };
1004
1005 static const struct ath5k_ini rf2413_ini_common_end[] = {
1006         { AR5K_DCU_FP,          0x000003e0 },
1007         { AR5K_SEQ_MASK,        0x0000000f },
1008         { AR5K_MIC_QOS_CTL,     0x00000000 },
1009         { AR5K_MIC_QOS_SEL,     0x00000000 },
1010         { AR5K_MISC_MODE,       0x00000000 },
1011         { AR5K_OFDM_FIL_CNT,    0x00000000 },
1012         { AR5K_CCK_FIL_CNT,     0x00000000 },
1013         { AR5K_PHYERR_CNT1,     0x00000000 },
1014         { AR5K_PHYERR_CNT1_MASK, 0x00000000 },
1015         { AR5K_PHYERR_CNT2,     0x00000000 },
1016         { AR5K_PHYERR_CNT2_MASK, 0x00000000 },
1017         { AR5K_TSF_THRES,       0x00000000 },
1018         { 0x8140,               0x800000a8 },
1019         { 0x8144,               0x00000000 },
1020         { AR5K_PHY_AGC,         0x00000000 },
1021         { AR5K_PHY_ADC_CTL,     0x0000a000 },
1022         { 0x983c,               0x00200400 },
1023         { AR5K_PHY_GAIN_OFFSET, 0x1284233c },
1024         { AR5K_PHY_SCR,         0x0000001f },
1025         { AR5K_PHY_SLMT,        0x00000080 },
1026         { AR5K_PHY_SCAL,        0x0000000e },
1027         { 0x9958,               0x000000ff },
1028         { AR5K_PHY_TIMING_7,    0x00000000 },
1029         { AR5K_PHY_TIMING_8,    0x02800000 },
1030         { AR5K_PHY_TIMING_11,   0x00000000 },
1031         { AR5K_PHY_HEAVY_CLIP_ENABLE, 0x00000000 },
1032         { 0x99e4,               0xaaaaaaaa },
1033         { 0x99e8,               0x3c466478 },
1034         { 0x99ec,               0x000000aa },
1035         { AR5K_PHY_SCLOCK,      0x0000000c },
1036         { AR5K_PHY_SDELAY,      0x000000ff },
1037         { AR5K_PHY_SPENDING,    0x00000014 },
1038         { AR5K_PHY_DAG_CCK_CTL, 0x000009b5 },
1039         { 0xa23c,               0x93c889af },
1040         { AR5K_PHY_FAST_ADC,    0x00000001 },
1041         { 0xa250,               0x0000a000 },
1042         { AR5K_PHY_BLUETOOTH,   0x00000000 },
1043         { AR5K_PHY_TPC_RG1,     0x0cc75380 },
1044         { 0xa25c,               0x0f0f0f01 },
1045         { 0xa260,               0x5f690f01 },
1046         { 0xa264,               0x00418a11 },
1047         { 0xa268,               0x00000000 },
1048         { AR5K_PHY_TPC_RG5,     0x0c30c16a },
1049         { 0xa270, 0x00820820 },
1050         { 0xa274, 0x001b7caa },
1051         { 0xa278, 0x1ce739ce },
1052         { 0xa27c, 0x051701ce },
1053         { 0xa300, 0x18010000 },
1054         { 0xa304, 0x30032602 },
1055         { 0xa308, 0x48073e06 },
1056         { 0xa30c, 0x560b4c0a },
1057         { 0xa310, 0x641a600f },
1058         { 0xa314, 0x784f6e1b },
1059         { 0xa318, 0x868f7c5a },
1060         { 0xa31c, 0x8ecf865b },
1061         { 0xa320, 0x9d4f970f },
1062         { 0xa324, 0xa5cfa18f },
1063         { 0xa328, 0xb55faf1f },
1064         { 0xa32c, 0xbddfb99f },
1065         { 0xa330, 0xcd7fc73f },
1066         { 0xa334, 0xd5ffd1bf },
1067         { 0xa338, 0x00000000 },
1068         { 0xa33c, 0x00000000 },
1069         { 0xa340, 0x00000000 },
1070         { 0xa344, 0x00000000 },
1071         { 0xa348, 0x3fffffff },
1072         { 0xa34c, 0x3fffffff },
1073         { 0xa350, 0x3fffffff },
1074         { 0xa354, 0x0003ffff },
1075         { 0xa358, 0x79a8aa1f },
1076         { 0xa35c, 0x066c420f },
1077         { 0xa360, 0x0f282207 },
1078         { 0xa364, 0x17601685 },
1079         { 0xa368, 0x1f801104 },
1080         { 0xa36c, 0x37a00c03 },
1081         { 0xa370, 0x3fc40883 },
1082         { 0xa374, 0x57c00803 },
1083         { 0xa378, 0x5fd80682 },
1084         { 0xa37c, 0x7fe00482 },
1085         { 0xa380, 0x7f3c7bba },
1086         { 0xa384, 0xf3307ff0 },
1087 };
1088
1089 /* Initial mode-specific settings for RF2425 (Written after ar5212_ini) */
1090 /* XXX: a mode ? */
1091 static const struct ath5k_ini_mode rf2425_ini_mode_end[] = {
1092         { AR5K_TXCFG,
1093         /*      A/XR          B           G       */
1094            { 0x00000015, 0x00000015, 0x00000015 } },
1095         { AR5K_USEC_5211,
1096            { 0x128d93a7, 0x04e01395, 0x12e013ab } },
1097         { AR5K_PHY_RF_CTL3,
1098            { 0x0a020001, 0x05020100, 0x0a020001 } },
1099         { AR5K_PHY_RF_CTL4,
1100            { 0x00000e0e, 0x00000e0e, 0x00000e0e } },
1101         { AR5K_PHY_PA_CTL,
1102            { 0x00000003, 0x0000000b, 0x0000000b } },
1103         { AR5K_PHY_SETTLING,
1104            { 0x1372161c, 0x13721722, 0x13721422 } },
1105         { AR5K_PHY_GAIN,
1106            { 0x0018fa61, 0x00199a65, 0x00199a65 } },
1107         { AR5K_PHY_DESIRED_SIZE,
1108            { 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da } },
1109         { AR5K_PHY_SIG,
1110            { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } },
1111         { AR5K_PHY_AGCCOARSE,
1112            { 0x3139605e, 0x3139605e, 0x3139605e } },
1113         { AR5K_PHY_WEAK_OFDM_LOW_THR,
1114            { 0x050cb081, 0x050cb081, 0x050cb081 } },
1115         { AR5K_PHY_RX_DELAY,
1116            { 0x000007d0, 0x0000044c, 0x00000898 } },
1117         { AR5K_PHY_FRAME_CTL_5211,
1118            { 0xf7b81000, 0xf7b80d00, 0xf7b81000 } },
1119         { AR5K_PHY_CCKTXCTL,
1120            { 0x00000000, 0x00000000, 0x00000000 } },
1121         { AR5K_PHY_CCK_CROSSCORR,
1122            { 0xd6be6788, 0xd03e6788, 0xd03e6788 } },
1123         { AR5K_PHY_GAIN_2GHZ,
1124            { 0x00000140, 0x0052c140, 0x0052c140 } },
1125         { AR5K_PHY_CCK_RX_CTL_4,
1126            { 0x1883800a, 0x1863800a, 0x1883800a } },
1127         { 0xa324,
1128            { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
1129         { 0xa328,
1130            { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
1131         { 0xa32c,
1132            { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
1133         { 0xa330,
1134            { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
1135         { 0xa334,
1136            { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
1137 };
1138
1139 static const struct ath5k_ini rf2425_ini_common_end[] = {
1140         { AR5K_DCU_FP,          0x000003e0 },
1141         { AR5K_SEQ_MASK,        0x0000000f },
1142         { 0x809c,               0x00000000 },
1143         { 0x80a0,               0x00000000 },
1144         { AR5K_MIC_QOS_CTL,     0x00000000 },
1145         { AR5K_MIC_QOS_SEL,     0x00000000 },
1146         { AR5K_MISC_MODE,       0x00000000 },
1147         { AR5K_OFDM_FIL_CNT,    0x00000000 },
1148         { AR5K_CCK_FIL_CNT,     0x00000000 },
1149         { AR5K_PHYERR_CNT1,     0x00000000 },
1150         { AR5K_PHYERR_CNT1_MASK, 0x00000000 },
1151         { AR5K_PHYERR_CNT2,     0x00000000 },
1152         { AR5K_PHYERR_CNT2_MASK, 0x00000000 },
1153         { AR5K_TSF_THRES,       0x00000000 },
1154         { 0x8140,               0x800003f9 },
1155         { 0x8144,               0x00000000 },
1156         { AR5K_PHY_AGC,         0x00000000 },
1157         { AR5K_PHY_ADC_CTL,     0x0000a000 },
1158         { 0x983c,               0x00200400 },
1159         { AR5K_PHY_GAIN_OFFSET, 0x1284233c },
1160         { AR5K_PHY_SCR,         0x0000001f },
1161         { AR5K_PHY_SLMT,        0x00000080 },
1162         { AR5K_PHY_SCAL,        0x0000000e },
1163         { 0x9958,               0x00081fff },
1164         { AR5K_PHY_TIMING_7,    0x00000000 },
1165         { AR5K_PHY_TIMING_8,    0x02800000 },
1166         { AR5K_PHY_TIMING_11,   0x00000000 },
1167         { 0x99dc,               0xfebadbe8 },
1168         { AR5K_PHY_HEAVY_CLIP_ENABLE, 0x00000000 },
1169         { 0x99e4,               0xaaaaaaaa },
1170         { 0x99e8,               0x3c466478 },
1171         { 0x99ec,               0x000000aa },
1172         { AR5K_PHY_SCLOCK,      0x0000000c },
1173         { AR5K_PHY_SDELAY,      0x000000ff },
1174         { AR5K_PHY_SPENDING,    0x00000014 },
1175         { AR5K_PHY_DAG_CCK_CTL, 0x000009b5 },
1176         { AR5K_PHY_TXPOWER_RATE3, 0x20202020 },
1177         { AR5K_PHY_TXPOWER_RATE4, 0x20202020 },
1178         { 0xa23c,               0x93c889af },
1179         { AR5K_PHY_FAST_ADC,    0x00000001 },
1180         { 0xa250,               0x0000a000 },
1181         { AR5K_PHY_BLUETOOTH,   0x00000000 },
1182         { AR5K_PHY_TPC_RG1,     0x0cc75380 },
1183         { 0xa25c,               0x0f0f0f01 },
1184         { 0xa260,               0x5f690f01 },
1185         { 0xa264,               0x00418a11 },
1186         { 0xa268,               0x00000000 },
1187         { AR5K_PHY_TPC_RG5,     0x0c30c166 },
1188         { 0xa270, 0x00820820 },
1189         { 0xa274, 0x081a3caa },
1190         { 0xa278, 0x1ce739ce },
1191         { 0xa27c, 0x051701ce },
1192         { 0xa300, 0x16010000 },
1193         { 0xa304, 0x2c032402 },
1194         { 0xa308, 0x48433e42 },
1195         { 0xa30c, 0x5a0f500b },
1196         { 0xa310, 0x6c4b624a },
1197         { 0xa314, 0x7e8b748a },
1198         { 0xa318, 0x96cf8ccb },
1199         { 0xa31c, 0xa34f9d0f },
1200         { 0xa320, 0xa7cfa58f },
1201         { 0xa348, 0x3fffffff },
1202         { 0xa34c, 0x3fffffff },
1203         { 0xa350, 0x3fffffff },
1204         { 0xa354, 0x0003ffff },
1205         { 0xa358, 0x79a8aa1f },
1206         { 0xa35c, 0x066c420f },
1207         { 0xa360, 0x0f282207 },
1208         { 0xa364, 0x17601685 },
1209         { 0xa368, 0x1f801104 },
1210         { 0xa36c, 0x37a00c03 },
1211         { 0xa370, 0x3fc40883 },
1212         { 0xa374, 0x57c00803 },
1213         { 0xa378, 0x5fd80682 },
1214         { 0xa37c, 0x7fe00482 },
1215         { 0xa380, 0x7f3c7bba },
1216         { 0xa384, 0xf3307ff0 },
1217 };
1218
1219 /*
1220  * Initial BaseBand Gain settings for RF5111/5112 (AR5210 comes with
1221  * RF5110 only so initial BB Gain settings are included in AR5K_AR5210_INI)
1222  */
1223
1224 /* RF5111 Initial BaseBand Gain settings */
1225 static const struct ath5k_ini rf5111_ini_bbgain[] = {
1226         { AR5K_BB_GAIN(0), 0x00000000 },
1227         { AR5K_BB_GAIN(1), 0x00000020 },
1228         { AR5K_BB_GAIN(2), 0x00000010 },
1229         { AR5K_BB_GAIN(3), 0x00000030 },
1230         { AR5K_BB_GAIN(4), 0x00000008 },
1231         { AR5K_BB_GAIN(5), 0x00000028 },
1232         { AR5K_BB_GAIN(6), 0x00000004 },
1233         { AR5K_BB_GAIN(7), 0x00000024 },
1234         { AR5K_BB_GAIN(8), 0x00000014 },
1235         { AR5K_BB_GAIN(9), 0x00000034 },
1236         { AR5K_BB_GAIN(10), 0x0000000c },
1237         { AR5K_BB_GAIN(11), 0x0000002c },
1238         { AR5K_BB_GAIN(12), 0x00000002 },
1239         { AR5K_BB_GAIN(13), 0x00000022 },
1240         { AR5K_BB_GAIN(14), 0x00000012 },
1241         { AR5K_BB_GAIN(15), 0x00000032 },
1242         { AR5K_BB_GAIN(16), 0x0000000a },
1243         { AR5K_BB_GAIN(17), 0x0000002a },
1244         { AR5K_BB_GAIN(18), 0x00000006 },
1245         { AR5K_BB_GAIN(19), 0x00000026 },
1246         { AR5K_BB_GAIN(20), 0x00000016 },
1247         { AR5K_BB_GAIN(21), 0x00000036 },
1248         { AR5K_BB_GAIN(22), 0x0000000e },
1249         { AR5K_BB_GAIN(23), 0x0000002e },
1250         { AR5K_BB_GAIN(24), 0x00000001 },
1251         { AR5K_BB_GAIN(25), 0x00000021 },
1252         { AR5K_BB_GAIN(26), 0x00000011 },
1253         { AR5K_BB_GAIN(27), 0x00000031 },
1254         { AR5K_BB_GAIN(28), 0x00000009 },
1255         { AR5K_BB_GAIN(29), 0x00000029 },
1256         { AR5K_BB_GAIN(30), 0x00000005 },
1257         { AR5K_BB_GAIN(31), 0x00000025 },
1258         { AR5K_BB_GAIN(32), 0x00000015 },
1259         { AR5K_BB_GAIN(33), 0x00000035 },
1260         { AR5K_BB_GAIN(34), 0x0000000d },
1261         { AR5K_BB_GAIN(35), 0x0000002d },
1262         { AR5K_BB_GAIN(36), 0x00000003 },
1263         { AR5K_BB_GAIN(37), 0x00000023 },
1264         { AR5K_BB_GAIN(38), 0x00000013 },
1265         { AR5K_BB_GAIN(39), 0x00000033 },
1266         { AR5K_BB_GAIN(40), 0x0000000b },
1267         { AR5K_BB_GAIN(41), 0x0000002b },
1268         { AR5K_BB_GAIN(42), 0x0000002b },
1269         { AR5K_BB_GAIN(43), 0x0000002b },
1270         { AR5K_BB_GAIN(44), 0x0000002b },
1271         { AR5K_BB_GAIN(45), 0x0000002b },
1272         { AR5K_BB_GAIN(46), 0x0000002b },
1273         { AR5K_BB_GAIN(47), 0x0000002b },
1274         { AR5K_BB_GAIN(48), 0x0000002b },
1275         { AR5K_BB_GAIN(49), 0x0000002b },
1276         { AR5K_BB_GAIN(50), 0x0000002b },
1277         { AR5K_BB_GAIN(51), 0x0000002b },
1278         { AR5K_BB_GAIN(52), 0x0000002b },
1279         { AR5K_BB_GAIN(53), 0x0000002b },
1280         { AR5K_BB_GAIN(54), 0x0000002b },
1281         { AR5K_BB_GAIN(55), 0x0000002b },
1282         { AR5K_BB_GAIN(56), 0x0000002b },
1283         { AR5K_BB_GAIN(57), 0x0000002b },
1284         { AR5K_BB_GAIN(58), 0x0000002b },
1285         { AR5K_BB_GAIN(59), 0x0000002b },
1286         { AR5K_BB_GAIN(60), 0x0000002b },
1287         { AR5K_BB_GAIN(61), 0x0000002b },
1288         { AR5K_BB_GAIN(62), 0x00000002 },
1289         { AR5K_BB_GAIN(63), 0x00000016 },
1290 };
1291
1292 /* RF5112 Initial BaseBand Gain settings (Same for RF5413/5414+) */
1293 static const struct ath5k_ini rf5112_ini_bbgain[] = {
1294         { AR5K_BB_GAIN(0), 0x00000000 },
1295         { AR5K_BB_GAIN(1), 0x00000001 },
1296         { AR5K_BB_GAIN(2), 0x00000002 },
1297         { AR5K_BB_GAIN(3), 0x00000003 },
1298         { AR5K_BB_GAIN(4), 0x00000004 },
1299         { AR5K_BB_GAIN(5), 0x00000005 },
1300         { AR5K_BB_GAIN(6), 0x00000008 },
1301         { AR5K_BB_GAIN(7), 0x00000009 },
1302         { AR5K_BB_GAIN(8), 0x0000000a },
1303         { AR5K_BB_GAIN(9), 0x0000000b },
1304         { AR5K_BB_GAIN(10), 0x0000000c },
1305         { AR5K_BB_GAIN(11), 0x0000000d },
1306         { AR5K_BB_GAIN(12), 0x00000010 },
1307         { AR5K_BB_GAIN(13), 0x00000011 },
1308         { AR5K_BB_GAIN(14), 0x00000012 },
1309         { AR5K_BB_GAIN(15), 0x00000013 },
1310         { AR5K_BB_GAIN(16), 0x00000014 },
1311         { AR5K_BB_GAIN(17), 0x00000015 },
1312         { AR5K_BB_GAIN(18), 0x00000018 },
1313         { AR5K_BB_GAIN(19), 0x00000019 },
1314         { AR5K_BB_GAIN(20), 0x0000001a },
1315         { AR5K_BB_GAIN(21), 0x0000001b },
1316         { AR5K_BB_GAIN(22), 0x0000001c },
1317         { AR5K_BB_GAIN(23), 0x0000001d },
1318         { AR5K_BB_GAIN(24), 0x00000020 },
1319         { AR5K_BB_GAIN(25), 0x00000021 },
1320         { AR5K_BB_GAIN(26), 0x00000022 },
1321         { AR5K_BB_GAIN(27), 0x00000023 },
1322         { AR5K_BB_GAIN(28), 0x00000024 },
1323         { AR5K_BB_GAIN(29), 0x00000025 },
1324         { AR5K_BB_GAIN(30), 0x00000028 },
1325         { AR5K_BB_GAIN(31), 0x00000029 },
1326         { AR5K_BB_GAIN(32), 0x0000002a },
1327         { AR5K_BB_GAIN(33), 0x0000002b },
1328         { AR5K_BB_GAIN(34), 0x0000002c },
1329         { AR5K_BB_GAIN(35), 0x0000002d },
1330         { AR5K_BB_GAIN(36), 0x00000030 },
1331         { AR5K_BB_GAIN(37), 0x00000031 },
1332         { AR5K_BB_GAIN(38), 0x00000032 },
1333         { AR5K_BB_GAIN(39), 0x00000033 },
1334         { AR5K_BB_GAIN(40), 0x00000034 },
1335         { AR5K_BB_GAIN(41), 0x00000035 },
1336         { AR5K_BB_GAIN(42), 0x00000035 },
1337         { AR5K_BB_GAIN(43), 0x00000035 },
1338         { AR5K_BB_GAIN(44), 0x00000035 },
1339         { AR5K_BB_GAIN(45), 0x00000035 },
1340         { AR5K_BB_GAIN(46), 0x00000035 },
1341         { AR5K_BB_GAIN(47), 0x00000035 },
1342         { AR5K_BB_GAIN(48), 0x00000035 },
1343         { AR5K_BB_GAIN(49), 0x00000035 },
1344         { AR5K_BB_GAIN(50), 0x00000035 },
1345         { AR5K_BB_GAIN(51), 0x00000035 },
1346         { AR5K_BB_GAIN(52), 0x00000035 },
1347         { AR5K_BB_GAIN(53), 0x00000035 },
1348         { AR5K_BB_GAIN(54), 0x00000035 },
1349         { AR5K_BB_GAIN(55), 0x00000035 },
1350         { AR5K_BB_GAIN(56), 0x00000035 },
1351         { AR5K_BB_GAIN(57), 0x00000035 },
1352         { AR5K_BB_GAIN(58), 0x00000035 },
1353         { AR5K_BB_GAIN(59), 0x00000035 },
1354         { AR5K_BB_GAIN(60), 0x00000035 },
1355         { AR5K_BB_GAIN(61), 0x00000035 },
1356         { AR5K_BB_GAIN(62), 0x00000010 },
1357         { AR5K_BB_GAIN(63), 0x0000001a },
1358 };
1359
1360
1361 /*
1362  * Write initial register dump
1363  */
1364 static void ath5k_hw_ini_registers(struct ath5k_hw *ah, unsigned int size,
1365                 const struct ath5k_ini *ini_regs, bool skip_pcu)
1366 {
1367         unsigned int i;
1368
1369         /* Write initial registers */
1370         for (i = 0; i < size; i++) {
1371                 /* Skip PCU registers if
1372                  * requested */
1373                 if (skip_pcu &&
1374                                 ini_regs[i].ini_register >= AR5K_PCU_MIN &&
1375                                 ini_regs[i].ini_register <= AR5K_PCU_MAX)
1376                         continue;
1377
1378                 switch (ini_regs[i].ini_mode) {
1379                 case AR5K_INI_READ:
1380                         /* Cleared on read */
1381                         ath5k_hw_reg_read(ah, ini_regs[i].ini_register);
1382                         break;
1383                 case AR5K_INI_WRITE:
1384                 default:
1385                         AR5K_REG_WAIT(i);
1386                         ath5k_hw_reg_write(ah, ini_regs[i].ini_value,
1387                                         ini_regs[i].ini_register);
1388                 }
1389         }
1390 }
1391
1392 static void ath5k_hw_ini_mode_registers(struct ath5k_hw *ah,
1393                 unsigned int size, const struct ath5k_ini_mode *ini_mode,
1394                 u8 mode)
1395 {
1396         unsigned int i;
1397
1398         for (i = 0; i < size; i++) {
1399                 AR5K_REG_WAIT(i);
1400                 ath5k_hw_reg_write(ah, ini_mode[i].mode_value[mode],
1401                         (u32)ini_mode[i].mode_register);
1402         }
1403
1404 }
1405
1406 int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool skip_pcu)
1407 {
1408         /*
1409          * Write initial register settings
1410          */
1411
1412         /* For AR5212 and combatible */
1413         if (ah->ah_version == AR5K_AR5212) {
1414
1415                 /* First set of mode-specific settings */
1416                 ath5k_hw_ini_mode_registers(ah,
1417                         ARRAY_SIZE(ar5212_ini_mode_start),
1418                         ar5212_ini_mode_start, mode);
1419
1420                 /*
1421                  * Write initial settings common for all modes
1422                  */
1423                 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5212_ini_common_start),
1424                                 ar5212_ini_common_start, skip_pcu);
1425
1426                 /* Second set of mode-specific settings */
1427                 switch (ah->ah_radio) {
1428                 case AR5K_RF5111:
1429
1430                         ath5k_hw_ini_mode_registers(ah,
1431                                         ARRAY_SIZE(rf5111_ini_mode_end),
1432                                         rf5111_ini_mode_end, mode);
1433
1434                         ath5k_hw_ini_registers(ah,
1435                                         ARRAY_SIZE(rf5111_ini_common_end),
1436                                         rf5111_ini_common_end, skip_pcu);
1437
1438                         /* Baseband gain table */
1439                         ath5k_hw_ini_registers(ah,
1440                                         ARRAY_SIZE(rf5111_ini_bbgain),
1441                                         rf5111_ini_bbgain, skip_pcu);
1442
1443                         break;
1444                 case AR5K_RF5112:
1445
1446                         ath5k_hw_ini_mode_registers(ah,
1447                                         ARRAY_SIZE(rf5112_ini_mode_end),
1448                                         rf5112_ini_mode_end, mode);
1449
1450                         ath5k_hw_ini_registers(ah,
1451                                         ARRAY_SIZE(rf5112_ini_common_end),
1452                                         rf5112_ini_common_end, skip_pcu);
1453
1454                         ath5k_hw_ini_registers(ah,
1455                                         ARRAY_SIZE(rf5112_ini_bbgain),
1456                                         rf5112_ini_bbgain, skip_pcu);
1457
1458                         break;
1459                 case AR5K_RF5413:
1460
1461                         ath5k_hw_ini_mode_registers(ah,
1462                                         ARRAY_SIZE(rf5413_ini_mode_end),
1463                                         rf5413_ini_mode_end, mode);
1464
1465                         ath5k_hw_ini_registers(ah,
1466                                         ARRAY_SIZE(rf5413_ini_common_end),
1467                                         rf5413_ini_common_end, skip_pcu);
1468
1469                         ath5k_hw_ini_registers(ah,
1470                                         ARRAY_SIZE(rf5112_ini_bbgain),
1471                                         rf5112_ini_bbgain, skip_pcu);
1472
1473                         break;
1474                 case AR5K_RF2316:
1475                 case AR5K_RF2413:
1476
1477                         ath5k_hw_ini_mode_registers(ah,
1478                                         ARRAY_SIZE(rf2413_ini_mode_end),
1479                                         rf2413_ini_mode_end, mode);
1480
1481                         ath5k_hw_ini_registers(ah,
1482                                         ARRAY_SIZE(rf2413_ini_common_end),
1483                                         rf2413_ini_common_end, skip_pcu);
1484
1485                         /* Override settings from rf2413_ini_common_end */
1486                         if (ah->ah_radio == AR5K_RF2316) {
1487                                 ath5k_hw_reg_write(ah, 0x00004000,
1488                                                         AR5K_PHY_AGC);
1489                                 ath5k_hw_reg_write(ah, 0x081b7caa,
1490                                                         0xa274);
1491                         }
1492
1493                         ath5k_hw_ini_registers(ah,
1494                                         ARRAY_SIZE(rf5112_ini_bbgain),
1495                                         rf5112_ini_bbgain, skip_pcu);
1496                         break;
1497                 case AR5K_RF2317:
1498
1499                         ath5k_hw_ini_mode_registers(ah,
1500                                         ARRAY_SIZE(rf2413_ini_mode_end),
1501                                         rf2413_ini_mode_end, mode);
1502
1503                         ath5k_hw_ini_registers(ah,
1504                                         ARRAY_SIZE(rf2425_ini_common_end),
1505                                         rf2425_ini_common_end, skip_pcu);
1506
1507                         /* Override settings from rf2413_ini_mode_end */
1508                         ath5k_hw_reg_write(ah, 0x00180a65, AR5K_PHY_GAIN);
1509
1510                         /* Override settings from rf2413_ini_common_end */
1511                         ath5k_hw_reg_write(ah, 0x00004000, AR5K_PHY_AGC);
1512                         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TPC_RG5,
1513                                 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP, 0xa);
1514                         ath5k_hw_reg_write(ah, 0x800000a8, 0x8140);
1515                         ath5k_hw_reg_write(ah, 0x000000ff, 0x9958);
1516
1517                         ath5k_hw_ini_registers(ah,
1518                                         ARRAY_SIZE(rf5112_ini_bbgain),
1519                                         rf5112_ini_bbgain, skip_pcu);
1520                         break;
1521                 case AR5K_RF2425:
1522
1523                         ath5k_hw_ini_mode_registers(ah,
1524                                         ARRAY_SIZE(rf2425_ini_mode_end),
1525                                         rf2425_ini_mode_end, mode);
1526
1527                         ath5k_hw_ini_registers(ah,
1528                                         ARRAY_SIZE(rf2425_ini_common_end),
1529                                         rf2425_ini_common_end, skip_pcu);
1530
1531                         ath5k_hw_ini_registers(ah,
1532                                         ARRAY_SIZE(rf5112_ini_bbgain),
1533                                         rf5112_ini_bbgain, skip_pcu);
1534                         break;
1535                 default:
1536                         return -EINVAL;
1537
1538                 }
1539
1540         /* For AR5211 */
1541         } else if (ah->ah_version == AR5K_AR5211) {
1542
1543                 /* AR5K_MODE_11B */
1544                 if (mode > 2) {
1545                         ATH5K_ERR(ah->ah_sc,
1546                                 "unsupported channel mode: %d\n", mode);
1547                         return -EINVAL;
1548                 }
1549
1550                 /* Mode-specific settings */
1551                 ath5k_hw_ini_mode_registers(ah, ARRAY_SIZE(ar5211_ini_mode),
1552                                 ar5211_ini_mode, mode);
1553
1554                 /*
1555                  * Write initial settings common for all modes
1556                  */
1557                 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5211_ini),
1558                                 ar5211_ini, skip_pcu);
1559
1560                 /* AR5211 only comes with 5111 */
1561
1562                 /* Baseband gain table */
1563                 ath5k_hw_ini_registers(ah, ARRAY_SIZE(rf5111_ini_bbgain),
1564                                 rf5111_ini_bbgain, skip_pcu);
1565         /* For AR5210 (for mode settings check out ath5k_hw_reset_tx_queue) */
1566         } else if (ah->ah_version == AR5K_AR5210) {
1567                 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5210_ini),
1568                                 ar5210_ini, skip_pcu);
1569         }
1570
1571         return 0;
1572 }