adm8211: fix cfg80211 band API conversion
[linux-2.6.git] / drivers / net / wireless / adm8211.c
1
2 /*
3  * Linux device driver for ADMtek ADM8211 (IEEE 802.11b MAC/BBP)
4  *
5  * Copyright (c) 2003, Jouni Malinen <j@w1.fi>
6  * Copyright (c) 2004-2007, Michael Wu <flamingice@sourmilk.net>
7  * Some parts copyright (c) 2003 by David Young <dyoung@pobox.com>
8  * and used with permission.
9  *
10  * Much thanks to Infineon-ADMtek for their support of this driver.
11  *
12  * This program is free software; you can redistribute it and/or modify
13  * it under the terms of the GNU General Public License version 2 as
14  * published by the Free Software Foundation. See README and COPYING for
15  * more details.
16  */
17
18 #include <linux/init.h>
19 #include <linux/if.h>
20 #include <linux/skbuff.h>
21 #include <linux/etherdevice.h>
22 #include <linux/pci.h>
23 #include <linux/delay.h>
24 #include <linux/crc32.h>
25 #include <linux/eeprom_93cx6.h>
26 #include <net/mac80211.h>
27
28 #include "adm8211.h"
29
30 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
31 MODULE_AUTHOR("Jouni Malinen <j@w1.fi>");
32 MODULE_DESCRIPTION("Driver for IEEE 802.11b wireless cards based on ADMtek ADM8211");
33 MODULE_SUPPORTED_DEVICE("ADM8211");
34 MODULE_LICENSE("GPL");
35
36 static unsigned int tx_ring_size __read_mostly = 16;
37 static unsigned int rx_ring_size __read_mostly = 16;
38
39 module_param(tx_ring_size, uint, 0);
40 module_param(rx_ring_size, uint, 0);
41
42 static struct pci_device_id adm8211_pci_id_table[] __devinitdata = {
43         /* ADMtek ADM8211 */
44         { PCI_DEVICE(0x10B7, 0x6000) }, /* 3Com 3CRSHPW796 */
45         { PCI_DEVICE(0x1200, 0x8201) }, /* ? */
46         { PCI_DEVICE(0x1317, 0x8201) }, /* ADM8211A */
47         { PCI_DEVICE(0x1317, 0x8211) }, /* ADM8211B/C */
48         { 0 }
49 };
50
51 static struct ieee80211_rate adm8211_rates[] = {
52         { .bitrate = 10, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
53         { .bitrate = 20, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
54         { .bitrate = 55, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
55         { .bitrate = 110, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
56         { .bitrate = 220, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, /* XX ?? */
57 };
58
59 static const struct ieee80211_channel adm8211_channels[] = {
60         { .center_freq = 2412},
61         { .center_freq = 2417},
62         { .center_freq = 2422},
63         { .center_freq = 2427},
64         { .center_freq = 2432},
65         { .center_freq = 2437},
66         { .center_freq = 2442},
67         { .center_freq = 2447},
68         { .center_freq = 2452},
69         { .center_freq = 2457},
70         { .center_freq = 2462},
71         { .center_freq = 2467},
72         { .center_freq = 2472},
73         { .center_freq = 2484},
74 };
75
76
77 static void adm8211_eeprom_register_read(struct eeprom_93cx6 *eeprom)
78 {
79         struct adm8211_priv *priv = eeprom->data;
80         u32 reg = ADM8211_CSR_READ(SPR);
81
82         eeprom->reg_data_in = reg & ADM8211_SPR_SDI;
83         eeprom->reg_data_out = reg & ADM8211_SPR_SDO;
84         eeprom->reg_data_clock = reg & ADM8211_SPR_SCLK;
85         eeprom->reg_chip_select = reg & ADM8211_SPR_SCS;
86 }
87
88 static void adm8211_eeprom_register_write(struct eeprom_93cx6 *eeprom)
89 {
90         struct adm8211_priv *priv = eeprom->data;
91         u32 reg = 0x4000 | ADM8211_SPR_SRS;
92
93         if (eeprom->reg_data_in)
94                 reg |= ADM8211_SPR_SDI;
95         if (eeprom->reg_data_out)
96                 reg |= ADM8211_SPR_SDO;
97         if (eeprom->reg_data_clock)
98                 reg |= ADM8211_SPR_SCLK;
99         if (eeprom->reg_chip_select)
100                 reg |= ADM8211_SPR_SCS;
101
102         ADM8211_CSR_WRITE(SPR, reg);
103         ADM8211_CSR_READ(SPR);          /* eeprom_delay */
104 }
105
106 static int adm8211_read_eeprom(struct ieee80211_hw *dev)
107 {
108         struct adm8211_priv *priv = dev->priv;
109         unsigned int words, i;
110         struct ieee80211_chan_range chan_range;
111         u16 cr49;
112         struct eeprom_93cx6 eeprom = {
113                 .data           = priv,
114                 .register_read  = adm8211_eeprom_register_read,
115                 .register_write = adm8211_eeprom_register_write
116         };
117
118         if (ADM8211_CSR_READ(CSR_TEST0) & ADM8211_CSR_TEST0_EPTYP) {
119                 /* 256 * 16-bit = 512 bytes */
120                 eeprom.width = PCI_EEPROM_WIDTH_93C66;
121                 words = 256;
122         } else {
123                 /* 64 * 16-bit = 128 bytes */
124                 eeprom.width = PCI_EEPROM_WIDTH_93C46;
125                 words = 64;
126         }
127
128         priv->eeprom_len = words * 2;
129         priv->eeprom = kmalloc(priv->eeprom_len, GFP_KERNEL);
130         if (!priv->eeprom)
131                 return -ENOMEM;
132
133         eeprom_93cx6_multiread(&eeprom, 0, (__le16 *)priv->eeprom, words);
134
135         cr49 = le16_to_cpu(priv->eeprom->cr49);
136         priv->rf_type = (cr49 >> 3) & 0x7;
137         switch (priv->rf_type) {
138         case ADM8211_TYPE_INTERSIL:
139         case ADM8211_TYPE_RFMD:
140         case ADM8211_TYPE_MARVEL:
141         case ADM8211_TYPE_AIROHA:
142         case ADM8211_TYPE_ADMTEK:
143                 break;
144
145         default:
146                 if (priv->pdev->revision < ADM8211_REV_CA)
147                         priv->rf_type = ADM8211_TYPE_RFMD;
148                 else
149                         priv->rf_type = ADM8211_TYPE_AIROHA;
150
151                 printk(KERN_WARNING "%s (adm8211): Unknown RFtype %d\n",
152                        pci_name(priv->pdev), (cr49 >> 3) & 0x7);
153         }
154
155         priv->bbp_type = cr49 & 0x7;
156         switch (priv->bbp_type) {
157         case ADM8211_TYPE_INTERSIL:
158         case ADM8211_TYPE_RFMD:
159         case ADM8211_TYPE_MARVEL:
160         case ADM8211_TYPE_AIROHA:
161         case ADM8211_TYPE_ADMTEK:
162                 break;
163         default:
164                 if (priv->pdev->revision < ADM8211_REV_CA)
165                         priv->bbp_type = ADM8211_TYPE_RFMD;
166                 else
167                         priv->bbp_type = ADM8211_TYPE_ADMTEK;
168
169                 printk(KERN_WARNING "%s (adm8211): Unknown BBPtype: %d\n",
170                        pci_name(priv->pdev), cr49 >> 3);
171         }
172
173         if (priv->eeprom->country_code >= ARRAY_SIZE(cranges)) {
174                 printk(KERN_WARNING "%s (adm8211): Invalid country code (%d)\n",
175                        pci_name(priv->pdev), priv->eeprom->country_code);
176
177                 chan_range = cranges[2];
178         } else
179                 chan_range = cranges[priv->eeprom->country_code];
180
181         printk(KERN_DEBUG "%s (adm8211): Channel range: %d - %d\n",
182                pci_name(priv->pdev), (int)chan_range.min, (int)chan_range.max);
183
184         BUILD_BUG_ON(sizeof(priv->channels) != sizeof(adm8211_channels));
185
186         memcpy(priv->channels, adm8211_channels, sizeof(priv->channels));
187         priv->band.channels = priv->channels;
188         priv->band.n_channels = ARRAY_SIZE(adm8211_channels);
189         priv->band.bitrates = adm8211_rates;
190         priv->band.n_bitrates = ARRAY_SIZE(adm8211_rates);
191
192         for (i = 1; i <= ARRAY_SIZE(adm8211_channels); i++)
193                 if (i < chan_range.min || i > chan_range.max)
194                         priv->channels[i - 1].flags |= IEEE80211_CHAN_DISABLED;
195
196         switch (priv->eeprom->specific_bbptype) {
197         case ADM8211_BBP_RFMD3000:
198         case ADM8211_BBP_RFMD3002:
199         case ADM8211_BBP_ADM8011:
200                 priv->specific_bbptype = priv->eeprom->specific_bbptype;
201                 break;
202
203         default:
204                 if (priv->pdev->revision < ADM8211_REV_CA)
205                         priv->specific_bbptype = ADM8211_BBP_RFMD3000;
206                 else
207                         priv->specific_bbptype = ADM8211_BBP_ADM8011;
208
209                 printk(KERN_WARNING "%s (adm8211): Unknown specific BBP: %d\n",
210                        pci_name(priv->pdev), priv->eeprom->specific_bbptype);
211         }
212
213         switch (priv->eeprom->specific_rftype) {
214         case ADM8211_RFMD2948:
215         case ADM8211_RFMD2958:
216         case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
217         case ADM8211_MAX2820:
218         case ADM8211_AL2210L:
219                 priv->transceiver_type = priv->eeprom->specific_rftype;
220                 break;
221
222         default:
223                 if (priv->pdev->revision == ADM8211_REV_BA)
224                         priv->transceiver_type = ADM8211_RFMD2958_RF3000_CONTROL_POWER;
225                 else if (priv->pdev->revision == ADM8211_REV_CA)
226                         priv->transceiver_type = ADM8211_AL2210L;
227                 else if (priv->pdev->revision == ADM8211_REV_AB)
228                         priv->transceiver_type = ADM8211_RFMD2948;
229
230                 printk(KERN_WARNING "%s (adm8211): Unknown transceiver: %d\n",
231                        pci_name(priv->pdev), priv->eeprom->specific_rftype);
232
233                 break;
234         }
235
236         printk(KERN_DEBUG "%s (adm8211): RFtype=%d BBPtype=%d Specific BBP=%d "
237                "Transceiver=%d\n", pci_name(priv->pdev), priv->rf_type,
238                priv->bbp_type, priv->specific_bbptype, priv->transceiver_type);
239
240         return 0;
241 }
242
243 static inline void adm8211_write_sram(struct ieee80211_hw *dev,
244                                       u32 addr, u32 data)
245 {
246         struct adm8211_priv *priv = dev->priv;
247
248         ADM8211_CSR_WRITE(WEPCTL, addr | ADM8211_WEPCTL_TABLE_WR |
249                           (priv->pdev->revision < ADM8211_REV_BA ?
250                            0 : ADM8211_WEPCTL_SEL_WEPTABLE ));
251         ADM8211_CSR_READ(WEPCTL);
252         msleep(1);
253
254         ADM8211_CSR_WRITE(WESK, data);
255         ADM8211_CSR_READ(WESK);
256         msleep(1);
257 }
258
259 static void adm8211_write_sram_bytes(struct ieee80211_hw *dev,
260                                      unsigned int addr, u8 *buf,
261                                      unsigned int len)
262 {
263         struct adm8211_priv *priv = dev->priv;
264         u32 reg = ADM8211_CSR_READ(WEPCTL);
265         unsigned int i;
266
267         if (priv->pdev->revision < ADM8211_REV_BA) {
268                 for (i = 0; i < len; i += 2) {
269                         u16 val = buf[i] | (buf[i + 1] << 8);
270                         adm8211_write_sram(dev, addr + i / 2, val);
271                 }
272         } else {
273                 for (i = 0; i < len; i += 4) {
274                         u32 val = (buf[i + 0] << 0 ) | (buf[i + 1] << 8 ) |
275                                   (buf[i + 2] << 16) | (buf[i + 3] << 24);
276                         adm8211_write_sram(dev, addr + i / 4, val);
277                 }
278         }
279
280         ADM8211_CSR_WRITE(WEPCTL, reg);
281 }
282
283 static void adm8211_clear_sram(struct ieee80211_hw *dev)
284 {
285         struct adm8211_priv *priv = dev->priv;
286         u32 reg = ADM8211_CSR_READ(WEPCTL);
287         unsigned int addr;
288
289         for (addr = 0; addr < ADM8211_SRAM_SIZE; addr++)
290                 adm8211_write_sram(dev, addr, 0);
291
292         ADM8211_CSR_WRITE(WEPCTL, reg);
293 }
294
295 static int adm8211_get_stats(struct ieee80211_hw *dev,
296                              struct ieee80211_low_level_stats *stats)
297 {
298         struct adm8211_priv *priv = dev->priv;
299
300         memcpy(stats, &priv->stats, sizeof(*stats));
301
302         return 0;
303 }
304
305 static int adm8211_get_tx_stats(struct ieee80211_hw *dev,
306                                 struct ieee80211_tx_queue_stats *stats)
307 {
308         struct adm8211_priv *priv = dev->priv;
309         struct ieee80211_tx_queue_stats_data *data = &stats->data[0];
310
311         data->len = priv->cur_tx - priv->dirty_tx;
312         data->limit = priv->tx_ring_size - 2;
313         data->count = priv->dirty_tx;
314
315         return 0;
316 }
317
318 static void adm8211_interrupt_tci(struct ieee80211_hw *dev)
319 {
320         struct adm8211_priv *priv = dev->priv;
321         unsigned int dirty_tx;
322
323         spin_lock(&priv->lock);
324
325         for (dirty_tx = priv->dirty_tx; priv->cur_tx - dirty_tx; dirty_tx++) {
326                 unsigned int entry = dirty_tx % priv->tx_ring_size;
327                 u32 status = le32_to_cpu(priv->tx_ring[entry].status);
328                 struct ieee80211_tx_status tx_status;
329                 struct adm8211_tx_ring_info *info;
330                 struct sk_buff *skb;
331
332                 if (status & TDES0_CONTROL_OWN ||
333                     !(status & TDES0_CONTROL_DONE))
334                         break;
335
336                 info = &priv->tx_buffers[entry];
337                 skb = info->skb;
338
339                 /* TODO: check TDES0_STATUS_TUF and TDES0_STATUS_TRO */
340
341                 pci_unmap_single(priv->pdev, info->mapping,
342                                  info->skb->len, PCI_DMA_TODEVICE);
343
344                 memset(&tx_status, 0, sizeof(tx_status));
345                 skb_pull(skb, sizeof(struct adm8211_tx_hdr));
346                 memcpy(skb_push(skb, info->hdrlen), skb->cb, info->hdrlen);
347                 memcpy(&tx_status.control, &info->tx_control,
348                        sizeof(tx_status.control));
349                 if (!(tx_status.control.flags & IEEE80211_TXCTL_NO_ACK)) {
350                         if (status & TDES0_STATUS_ES)
351                                 tx_status.excessive_retries = 1;
352                         else
353                                 tx_status.flags |= IEEE80211_TX_STATUS_ACK;
354                 }
355                 ieee80211_tx_status_irqsafe(dev, skb, &tx_status);
356
357                 info->skb = NULL;
358         }
359
360         if (priv->cur_tx - dirty_tx < priv->tx_ring_size - 2)
361                 ieee80211_wake_queue(dev, 0);
362
363         priv->dirty_tx = dirty_tx;
364         spin_unlock(&priv->lock);
365 }
366
367
368 static void adm8211_interrupt_rci(struct ieee80211_hw *dev)
369 {
370         struct adm8211_priv *priv = dev->priv;
371         unsigned int entry = priv->cur_rx % priv->rx_ring_size;
372         u32 status;
373         unsigned int pktlen;
374         struct sk_buff *skb, *newskb;
375         unsigned int limit = priv->rx_ring_size;
376         u8 rssi, rate;
377
378         while (!(priv->rx_ring[entry].status & cpu_to_le32(RDES0_STATUS_OWN))) {
379                 if (!limit--)
380                         break;
381
382                 status = le32_to_cpu(priv->rx_ring[entry].status);
383                 rate = (status & RDES0_STATUS_RXDR) >> 12;
384                 rssi = le32_to_cpu(priv->rx_ring[entry].length) &
385                         RDES1_STATUS_RSSI;
386
387                 pktlen = status & RDES0_STATUS_FL;
388                 if (pktlen > RX_PKT_SIZE) {
389                         if (net_ratelimit())
390                                 printk(KERN_DEBUG "%s: frame too long (%d)\n",
391                                        wiphy_name(dev->wiphy), pktlen);
392                         pktlen = RX_PKT_SIZE;
393                 }
394
395                 if (!priv->soft_rx_crc && status & RDES0_STATUS_ES) {
396                         skb = NULL; /* old buffer will be reused */
397                         /* TODO: update RX error stats */
398                         /* TODO: check RDES0_STATUS_CRC*E */
399                 } else if (pktlen < RX_COPY_BREAK) {
400                         skb = dev_alloc_skb(pktlen);
401                         if (skb) {
402                                 pci_dma_sync_single_for_cpu(
403                                         priv->pdev,
404                                         priv->rx_buffers[entry].mapping,
405                                         pktlen, PCI_DMA_FROMDEVICE);
406                                 memcpy(skb_put(skb, pktlen),
407                                        skb_tail_pointer(priv->rx_buffers[entry].skb),
408                                        pktlen);
409                                 pci_dma_sync_single_for_device(
410                                         priv->pdev,
411                                         priv->rx_buffers[entry].mapping,
412                                         RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
413                         }
414                 } else {
415                         newskb = dev_alloc_skb(RX_PKT_SIZE);
416                         if (newskb) {
417                                 skb = priv->rx_buffers[entry].skb;
418                                 skb_put(skb, pktlen);
419                                 pci_unmap_single(
420                                         priv->pdev,
421                                         priv->rx_buffers[entry].mapping,
422                                         RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
423                                 priv->rx_buffers[entry].skb = newskb;
424                                 priv->rx_buffers[entry].mapping =
425                                         pci_map_single(priv->pdev,
426                                                        skb_tail_pointer(newskb),
427                                                        RX_PKT_SIZE,
428                                                        PCI_DMA_FROMDEVICE);
429                         } else {
430                                 skb = NULL;
431                                 /* TODO: update rx dropped stats */
432                         }
433
434                         priv->rx_ring[entry].buffer1 =
435                                 cpu_to_le32(priv->rx_buffers[entry].mapping);
436                 }
437
438                 priv->rx_ring[entry].status = cpu_to_le32(RDES0_STATUS_OWN |
439                                                           RDES0_STATUS_SQL);
440                 priv->rx_ring[entry].length =
441                         cpu_to_le32(RX_PKT_SIZE |
442                                     (entry == priv->rx_ring_size - 1 ?
443                                      RDES1_CONTROL_RER : 0));
444
445                 if (skb) {
446                         struct ieee80211_rx_status rx_status = {0};
447
448                         if (priv->pdev->revision < ADM8211_REV_CA)
449                                 rx_status.ssi = rssi;
450                         else
451                                 rx_status.ssi = 100 - rssi;
452
453                         rx_status.rate_idx = rate;
454
455                         rx_status.freq = adm8211_channels[priv->channel - 1].center_freq;
456                         rx_status.band = IEEE80211_BAND_2GHZ;
457
458                         ieee80211_rx_irqsafe(dev, skb, &rx_status);
459                 }
460
461                 entry = (++priv->cur_rx) % priv->rx_ring_size;
462         }
463
464         /* TODO: check LPC and update stats? */
465 }
466
467
468 static irqreturn_t adm8211_interrupt(int irq, void *dev_id)
469 {
470 #define ADM8211_INT(x)                                                     \
471 do {                                                                       \
472         if (unlikely(stsr & ADM8211_STSR_ ## x))                           \
473                 printk(KERN_DEBUG "%s: " #x "\n", wiphy_name(dev->wiphy)); \
474 } while (0)
475
476         struct ieee80211_hw *dev = dev_id;
477         struct adm8211_priv *priv = dev->priv;
478         u32 stsr = ADM8211_CSR_READ(STSR);
479         ADM8211_CSR_WRITE(STSR, stsr);
480         if (stsr == 0xffffffff)
481                 return IRQ_HANDLED;
482
483         if (!(stsr & (ADM8211_STSR_NISS | ADM8211_STSR_AISS)))
484                 return IRQ_HANDLED;
485
486         if (stsr & ADM8211_STSR_RCI)
487                 adm8211_interrupt_rci(dev);
488         if (stsr & ADM8211_STSR_TCI)
489                 adm8211_interrupt_tci(dev);
490
491         /*ADM8211_INT(LinkOn);*/
492         /*ADM8211_INT(LinkOff);*/
493
494         ADM8211_INT(PCF);
495         ADM8211_INT(BCNTC);
496         ADM8211_INT(GPINT);
497         ADM8211_INT(ATIMTC);
498         ADM8211_INT(TSFTF);
499         ADM8211_INT(TSCZ);
500         ADM8211_INT(SQL);
501         ADM8211_INT(WEPTD);
502         ADM8211_INT(ATIME);
503         /*ADM8211_INT(TBTT);*/
504         ADM8211_INT(TEIS);
505         ADM8211_INT(FBE);
506         ADM8211_INT(REIS);
507         ADM8211_INT(GPTT);
508         ADM8211_INT(RPS);
509         ADM8211_INT(RDU);
510         ADM8211_INT(TUF);
511         /*ADM8211_INT(TRT);*/
512         /*ADM8211_INT(TLT);*/
513         /*ADM8211_INT(TDU);*/
514         ADM8211_INT(TPS);
515
516         return IRQ_HANDLED;
517
518 #undef ADM8211_INT
519 }
520
521 #define WRITE_SYN(name,v_mask,v_shift,a_mask,a_shift,bits,prewrite,postwrite)\
522 static void adm8211_rf_write_syn_ ## name (struct ieee80211_hw *dev,         \
523                                            u16 addr, u32 value) {            \
524         struct adm8211_priv *priv = dev->priv;                               \
525         unsigned int i;                                                      \
526         u32 reg, bitbuf;                                                     \
527                                                                              \
528         value &= v_mask;                                                     \
529         addr &= a_mask;                                                      \
530         bitbuf = (value << v_shift) | (addr << a_shift);                     \
531                                                                              \
532         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_1);                 \
533         ADM8211_CSR_READ(SYNRF);                                             \
534         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_0);                 \
535         ADM8211_CSR_READ(SYNRF);                                             \
536                                                                              \
537         if (prewrite) {                                                      \
538                 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_WRITE_SYNDATA_0);     \
539                 ADM8211_CSR_READ(SYNRF);                                     \
540         }                                                                    \
541                                                                              \
542         for (i = 0; i <= bits; i++) {                                        \
543                 if (bitbuf & (1 << (bits - i)))                              \
544                         reg = ADM8211_SYNRF_WRITE_SYNDATA_1;                 \
545                 else                                                         \
546                         reg = ADM8211_SYNRF_WRITE_SYNDATA_0;                 \
547                                                                              \
548                 ADM8211_CSR_WRITE(SYNRF, reg);                               \
549                 ADM8211_CSR_READ(SYNRF);                                     \
550                                                                              \
551                 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_1); \
552                 ADM8211_CSR_READ(SYNRF);                                     \
553                 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_0); \
554                 ADM8211_CSR_READ(SYNRF);                                     \
555         }                                                                    \
556                                                                              \
557         if (postwrite == 1) {                                                \
558                 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_0);   \
559                 ADM8211_CSR_READ(SYNRF);                                     \
560         }                                                                    \
561         if (postwrite == 2) {                                                \
562                 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_1);   \
563                 ADM8211_CSR_READ(SYNRF);                                     \
564         }                                                                    \
565                                                                              \
566         ADM8211_CSR_WRITE(SYNRF, 0);                                         \
567         ADM8211_CSR_READ(SYNRF);                                             \
568 }
569
570 WRITE_SYN(max2820,  0x00FFF, 0, 0x0F, 12, 15, 1, 1)
571 WRITE_SYN(al2210l,  0xFFFFF, 4, 0x0F,  0, 23, 1, 1)
572 WRITE_SYN(rfmd2958, 0x3FFFF, 0, 0x1F, 18, 23, 0, 1)
573 WRITE_SYN(rfmd2948, 0x0FFFF, 4, 0x0F,  0, 21, 0, 2)
574
575 #undef WRITE_SYN
576
577 static int adm8211_write_bbp(struct ieee80211_hw *dev, u8 addr, u8 data)
578 {
579         struct adm8211_priv *priv = dev->priv;
580         unsigned int timeout;
581         u32 reg;
582
583         timeout = 10;
584         while (timeout > 0) {
585                 reg = ADM8211_CSR_READ(BBPCTL);
586                 if (!(reg & (ADM8211_BBPCTL_WR | ADM8211_BBPCTL_RD)))
587                         break;
588                 timeout--;
589                 msleep(2);
590         }
591
592         if (timeout == 0) {
593                 printk(KERN_DEBUG "%s: adm8211_write_bbp(%d,%d) failed"
594                        " prewrite (reg=0x%08x)\n",
595                        wiphy_name(dev->wiphy), addr, data, reg);
596                 return -ETIMEDOUT;
597         }
598
599         switch (priv->bbp_type) {
600         case ADM8211_TYPE_INTERSIL:
601                 reg = ADM8211_BBPCTL_MMISEL;    /* three wire interface */
602                 break;
603         case ADM8211_TYPE_RFMD:
604                 reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP |
605                       (0x01 << 18);
606                 break;
607         case ADM8211_TYPE_ADMTEK:
608                 reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP |
609                       (0x05 << 18);
610                 break;
611         }
612         reg |= ADM8211_BBPCTL_WR | (addr << 8) | data;
613
614         ADM8211_CSR_WRITE(BBPCTL, reg);
615
616         timeout = 10;
617         while (timeout > 0) {
618                 reg = ADM8211_CSR_READ(BBPCTL);
619                 if (!(reg & ADM8211_BBPCTL_WR))
620                         break;
621                 timeout--;
622                 msleep(2);
623         }
624
625         if (timeout == 0) {
626                 ADM8211_CSR_WRITE(BBPCTL, ADM8211_CSR_READ(BBPCTL) &
627                                   ~ADM8211_BBPCTL_WR);
628                 printk(KERN_DEBUG "%s: adm8211_write_bbp(%d,%d) failed"
629                        " postwrite (reg=0x%08x)\n",
630                        wiphy_name(dev->wiphy), addr, data, reg);
631                 return -ETIMEDOUT;
632         }
633
634         return 0;
635 }
636
637 static int adm8211_rf_set_channel(struct ieee80211_hw *dev, unsigned int chan)
638 {
639         static const u32 adm8211_rfmd2958_reg5[] =
640                 {0x22BD, 0x22D2, 0x22E8, 0x22FE, 0x2314, 0x232A, 0x2340,
641                  0x2355, 0x236B, 0x2381, 0x2397, 0x23AD, 0x23C2, 0x23F7};
642         static const u32 adm8211_rfmd2958_reg6[] =
643                 {0x05D17, 0x3A2E8, 0x2E8BA, 0x22E8B, 0x1745D, 0x0BA2E, 0x00000,
644                  0x345D1, 0x28BA2, 0x1D174, 0x11745, 0x05D17, 0x3A2E8, 0x11745};
645
646         struct adm8211_priv *priv = dev->priv;
647         u8 ant_power = priv->ant_power > 0x3F ?
648                 priv->eeprom->antenna_power[chan - 1] : priv->ant_power;
649         u8 tx_power = priv->tx_power > 0x3F ?
650                 priv->eeprom->tx_power[chan - 1] : priv->tx_power;
651         u8 lpf_cutoff = priv->lpf_cutoff == 0xFF ?
652                 priv->eeprom->lpf_cutoff[chan - 1] : priv->lpf_cutoff;
653         u8 lnags_thresh = priv->lnags_threshold == 0xFF ?
654                 priv->eeprom->lnags_threshold[chan - 1] : priv->lnags_threshold;
655         u32 reg;
656
657         ADM8211_IDLE();
658
659         /* Program synthesizer to new channel */
660         switch (priv->transceiver_type) {
661         case ADM8211_RFMD2958:
662         case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
663                 adm8211_rf_write_syn_rfmd2958(dev, 0x00, 0x04007);
664                 adm8211_rf_write_syn_rfmd2958(dev, 0x02, 0x00033);
665
666                 adm8211_rf_write_syn_rfmd2958(dev, 0x05,
667                         adm8211_rfmd2958_reg5[chan - 1]);
668                 adm8211_rf_write_syn_rfmd2958(dev, 0x06,
669                         adm8211_rfmd2958_reg6[chan - 1]);
670                 break;
671
672         case ADM8211_RFMD2948:
673                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_MAIN_CONF,
674                                               SI4126_MAIN_XINDIV2);
675                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_POWERDOWN,
676                                               SI4126_POWERDOWN_PDIB |
677                                               SI4126_POWERDOWN_PDRB);
678                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_PHASE_DET_GAIN, 0);
679                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_N_DIV,
680                                               (chan == 14 ?
681                                                2110 : (2033 + (chan * 5))));
682                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_N_DIV, 1496);
683                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_R_DIV, 44);
684                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_R_DIV, 44);
685                 break;
686
687         case ADM8211_MAX2820:
688                 adm8211_rf_write_syn_max2820(dev, 0x3,
689                         (chan == 14 ? 0x054 : (0x7 + (chan * 5))));
690                 break;
691
692         case ADM8211_AL2210L:
693                 adm8211_rf_write_syn_al2210l(dev, 0x0,
694                         (chan == 14 ? 0x229B4 : (0x22967 + (chan * 5))));
695                 break;
696
697         default:
698                 printk(KERN_DEBUG "%s: unsupported transceiver type %d\n",
699                        wiphy_name(dev->wiphy), priv->transceiver_type);
700                 break;
701         }
702
703         /* write BBP regs */
704         if (priv->bbp_type == ADM8211_TYPE_RFMD) {
705
706         /* SMC 2635W specific? adm8211b doesn't use the 2948 though.. */
707         /* TODO: remove if SMC 2635W doesn't need this */
708         if (priv->transceiver_type == ADM8211_RFMD2948) {
709                 reg = ADM8211_CSR_READ(GPIO);
710                 reg &= 0xfffc0000;
711                 reg |= ADM8211_CSR_GPIO_EN0;
712                 if (chan != 14)
713                         reg |= ADM8211_CSR_GPIO_O0;
714                 ADM8211_CSR_WRITE(GPIO, reg);
715         }
716
717         if (priv->transceiver_type == ADM8211_RFMD2958) {
718                 /* set PCNT2 */
719                 adm8211_rf_write_syn_rfmd2958(dev, 0x0B, 0x07100);
720                 /* set PCNT1 P_DESIRED/MID_BIAS */
721                 reg = le16_to_cpu(priv->eeprom->cr49);
722                 reg >>= 13;
723                 reg <<= 15;
724                 reg |= ant_power << 9;
725                 adm8211_rf_write_syn_rfmd2958(dev, 0x0A, reg);
726                 /* set TXRX TX_GAIN */
727                 adm8211_rf_write_syn_rfmd2958(dev, 0x09, 0x00050 |
728                         (priv->pdev->revision < ADM8211_REV_CA ? tx_power : 0));
729         } else {
730                 reg = ADM8211_CSR_READ(PLCPHD);
731                 reg &= 0xff00ffff;
732                 reg |= tx_power << 18;
733                 ADM8211_CSR_WRITE(PLCPHD, reg);
734         }
735
736         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF |
737                           ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST);
738         ADM8211_CSR_READ(SYNRF);
739         msleep(30);
740
741         /* RF3000 BBP */
742         if (priv->transceiver_type != ADM8211_RFMD2958)
743                 adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT,
744                                   tx_power<<2);
745         adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, lpf_cutoff);
746         adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, lnags_thresh);
747         adm8211_write_bbp(dev, 0x1c, priv->pdev->revision == ADM8211_REV_BA ?
748                                      priv->eeprom->cr28 : 0);
749         adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29);
750
751         ADM8211_CSR_WRITE(SYNRF, 0);
752
753         /* Nothing to do for ADMtek BBP */
754         } else if (priv->bbp_type != ADM8211_TYPE_ADMTEK)
755                 printk(KERN_DEBUG "%s: unsupported BBP type %d\n",
756                        wiphy_name(dev->wiphy), priv->bbp_type);
757
758         ADM8211_RESTORE();
759
760         /* update current channel for adhoc (and maybe AP mode) */
761         reg = ADM8211_CSR_READ(CAP0);
762         reg &= ~0xF;
763         reg |= chan;
764         ADM8211_CSR_WRITE(CAP0, reg);
765
766         return 0;
767 }
768
769 static void adm8211_update_mode(struct ieee80211_hw *dev)
770 {
771         struct adm8211_priv *priv = dev->priv;
772
773         ADM8211_IDLE();
774
775         priv->soft_rx_crc = 0;
776         switch (priv->mode) {
777         case IEEE80211_IF_TYPE_STA:
778                 priv->nar &= ~(ADM8211_NAR_PR | ADM8211_NAR_EA);
779                 priv->nar |= ADM8211_NAR_ST | ADM8211_NAR_SR;
780                 break;
781         case IEEE80211_IF_TYPE_IBSS:
782                 priv->nar &= ~ADM8211_NAR_PR;
783                 priv->nar |= ADM8211_NAR_EA | ADM8211_NAR_ST | ADM8211_NAR_SR;
784
785                 /* don't trust the error bits on rev 0x20 and up in adhoc */
786                 if (priv->pdev->revision >= ADM8211_REV_BA)
787                         priv->soft_rx_crc = 1;
788                 break;
789         case IEEE80211_IF_TYPE_MNTR:
790                 priv->nar &= ~(ADM8211_NAR_EA | ADM8211_NAR_ST);
791                 priv->nar |= ADM8211_NAR_PR | ADM8211_NAR_SR;
792                 break;
793         }
794
795         ADM8211_RESTORE();
796 }
797
798 static void adm8211_hw_init_syn(struct ieee80211_hw *dev)
799 {
800         struct adm8211_priv *priv = dev->priv;
801
802         switch (priv->transceiver_type) {
803         case ADM8211_RFMD2958:
804         case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
805                 /* comments taken from ADMtek vendor driver */
806
807                 /* Reset RF2958 after power on */
808                 adm8211_rf_write_syn_rfmd2958(dev, 0x1F, 0x00000);
809                 /* Initialize RF VCO Core Bias to maximum */
810                 adm8211_rf_write_syn_rfmd2958(dev, 0x0C, 0x3001F);
811                 /* Initialize IF PLL */
812                 adm8211_rf_write_syn_rfmd2958(dev, 0x01, 0x29C03);
813                 /* Initialize IF PLL Coarse Tuning */
814                 adm8211_rf_write_syn_rfmd2958(dev, 0x03, 0x1FF6F);
815                 /* Initialize RF PLL */
816                 adm8211_rf_write_syn_rfmd2958(dev, 0x04, 0x29403);
817                 /* Initialize RF PLL Coarse Tuning */
818                 adm8211_rf_write_syn_rfmd2958(dev, 0x07, 0x1456F);
819                 /* Initialize TX gain and filter BW (R9) */
820                 adm8211_rf_write_syn_rfmd2958(dev, 0x09,
821                         (priv->transceiver_type == ADM8211_RFMD2958 ?
822                          0x10050 : 0x00050));
823                 /* Initialize CAL register */
824                 adm8211_rf_write_syn_rfmd2958(dev, 0x08, 0x3FFF8);
825                 break;
826
827         case ADM8211_MAX2820:
828                 adm8211_rf_write_syn_max2820(dev, 0x1, 0x01E);
829                 adm8211_rf_write_syn_max2820(dev, 0x2, 0x001);
830                 adm8211_rf_write_syn_max2820(dev, 0x3, 0x054);
831                 adm8211_rf_write_syn_max2820(dev, 0x4, 0x310);
832                 adm8211_rf_write_syn_max2820(dev, 0x5, 0x000);
833                 break;
834
835         case ADM8211_AL2210L:
836                 adm8211_rf_write_syn_al2210l(dev, 0x0, 0x0196C);
837                 adm8211_rf_write_syn_al2210l(dev, 0x1, 0x007CB);
838                 adm8211_rf_write_syn_al2210l(dev, 0x2, 0x3582F);
839                 adm8211_rf_write_syn_al2210l(dev, 0x3, 0x010A9);
840                 adm8211_rf_write_syn_al2210l(dev, 0x4, 0x77280);
841                 adm8211_rf_write_syn_al2210l(dev, 0x5, 0x45641);
842                 adm8211_rf_write_syn_al2210l(dev, 0x6, 0xEA130);
843                 adm8211_rf_write_syn_al2210l(dev, 0x7, 0x80000);
844                 adm8211_rf_write_syn_al2210l(dev, 0x8, 0x7850F);
845                 adm8211_rf_write_syn_al2210l(dev, 0x9, 0xF900C);
846                 adm8211_rf_write_syn_al2210l(dev, 0xA, 0x00000);
847                 adm8211_rf_write_syn_al2210l(dev, 0xB, 0x00000);
848                 break;
849
850         case ADM8211_RFMD2948:
851         default:
852                 break;
853         }
854 }
855
856 static int adm8211_hw_init_bbp(struct ieee80211_hw *dev)
857 {
858         struct adm8211_priv *priv = dev->priv;
859         u32 reg;
860
861         /* write addresses */
862         if (priv->bbp_type == ADM8211_TYPE_INTERSIL) {
863                 ADM8211_CSR_WRITE(MMIWA,  0x100E0C0A);
864                 ADM8211_CSR_WRITE(MMIRD0, 0x00007C7E);
865                 ADM8211_CSR_WRITE(MMIRD1, 0x00100000);
866         } else if (priv->bbp_type == ADM8211_TYPE_RFMD ||
867                    priv->bbp_type == ADM8211_TYPE_ADMTEK) {
868                 /* check specific BBP type */
869                 switch (priv->specific_bbptype) {
870                 case ADM8211_BBP_RFMD3000:
871                 case ADM8211_BBP_RFMD3002:
872                         ADM8211_CSR_WRITE(MMIWA,  0x00009101);
873                         ADM8211_CSR_WRITE(MMIRD0, 0x00000301);
874                         break;
875
876                 case ADM8211_BBP_ADM8011:
877                         ADM8211_CSR_WRITE(MMIWA,  0x00008903);
878                         ADM8211_CSR_WRITE(MMIRD0, 0x00001716);
879
880                         reg = ADM8211_CSR_READ(BBPCTL);
881                         reg &= ~ADM8211_BBPCTL_TYPE;
882                         reg |= 0x5 << 18;
883                         ADM8211_CSR_WRITE(BBPCTL, reg);
884                         break;
885                 }
886
887                 switch (priv->pdev->revision) {
888                 case ADM8211_REV_CA:
889                         if (priv->transceiver_type == ADM8211_RFMD2958 ||
890                             priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER ||
891                             priv->transceiver_type == ADM8211_RFMD2948)
892                                 ADM8211_CSR_WRITE(SYNCTL, 0x1 << 22);
893                         else if (priv->transceiver_type == ADM8211_MAX2820 ||
894                                  priv->transceiver_type == ADM8211_AL2210L)
895                                 ADM8211_CSR_WRITE(SYNCTL, 0x3 << 22);
896                         break;
897
898                 case ADM8211_REV_BA:
899                         reg  = ADM8211_CSR_READ(MMIRD1);
900                         reg &= 0x0000FFFF;
901                         reg |= 0x7e100000;
902                         ADM8211_CSR_WRITE(MMIRD1, reg);
903                         break;
904
905                 case ADM8211_REV_AB:
906                 case ADM8211_REV_AF:
907                 default:
908                         ADM8211_CSR_WRITE(MMIRD1, 0x7e100000);
909                         break;
910                 }
911
912                 /* For RFMD */
913                 ADM8211_CSR_WRITE(MACTEST, 0x800);
914         }
915
916         adm8211_hw_init_syn(dev);
917
918         /* Set RF Power control IF pin to PE1+PHYRST# */
919         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF |
920                           ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST);
921         ADM8211_CSR_READ(SYNRF);
922         msleep(20);
923
924         /* write BBP regs */
925         if (priv->bbp_type == ADM8211_TYPE_RFMD) {
926                 /* RF3000 BBP */
927                 /* another set:
928                  * 11: c8
929                  * 14: 14
930                  * 15: 50 (chan 1..13; chan 14: d0)
931                  * 1c: 00
932                  * 1d: 84
933                  */
934                 adm8211_write_bbp(dev, RF3000_CCA_CTRL, 0x80);
935                 /* antenna selection: diversity */
936                 adm8211_write_bbp(dev, RF3000_DIVERSITY__RSSI, 0x80);
937                 adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT, 0x74);
938                 adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, 0x38);
939                 adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, 0x40);
940
941                 if (priv->eeprom->major_version < 2) {
942                         adm8211_write_bbp(dev, 0x1c, 0x00);
943                         adm8211_write_bbp(dev, 0x1d, 0x80);
944                 } else {
945                         if (priv->pdev->revision == ADM8211_REV_BA)
946                                 adm8211_write_bbp(dev, 0x1c, priv->eeprom->cr28);
947                         else
948                                 adm8211_write_bbp(dev, 0x1c, 0x00);
949
950                         adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29);
951                 }
952         } else if (priv->bbp_type == ADM8211_TYPE_ADMTEK) {
953                 /* reset baseband */
954                 adm8211_write_bbp(dev, 0x00, 0xFF);
955                 /* antenna selection: diversity */
956                 adm8211_write_bbp(dev, 0x07, 0x0A);
957
958                 /* TODO: find documentation for this */
959                 switch (priv->transceiver_type) {
960                 case ADM8211_RFMD2958:
961                 case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
962                         adm8211_write_bbp(dev, 0x00, 0x00);
963                         adm8211_write_bbp(dev, 0x01, 0x00);
964                         adm8211_write_bbp(dev, 0x02, 0x00);
965                         adm8211_write_bbp(dev, 0x03, 0x00);
966                         adm8211_write_bbp(dev, 0x06, 0x0f);
967                         adm8211_write_bbp(dev, 0x09, 0x00);
968                         adm8211_write_bbp(dev, 0x0a, 0x00);
969                         adm8211_write_bbp(dev, 0x0b, 0x00);
970                         adm8211_write_bbp(dev, 0x0c, 0x00);
971                         adm8211_write_bbp(dev, 0x0f, 0xAA);
972                         adm8211_write_bbp(dev, 0x10, 0x8c);
973                         adm8211_write_bbp(dev, 0x11, 0x43);
974                         adm8211_write_bbp(dev, 0x18, 0x40);
975                         adm8211_write_bbp(dev, 0x20, 0x23);
976                         adm8211_write_bbp(dev, 0x21, 0x02);
977                         adm8211_write_bbp(dev, 0x22, 0x28);
978                         adm8211_write_bbp(dev, 0x23, 0x30);
979                         adm8211_write_bbp(dev, 0x24, 0x2d);
980                         adm8211_write_bbp(dev, 0x28, 0x35);
981                         adm8211_write_bbp(dev, 0x2a, 0x8c);
982                         adm8211_write_bbp(dev, 0x2b, 0x81);
983                         adm8211_write_bbp(dev, 0x2c, 0x44);
984                         adm8211_write_bbp(dev, 0x2d, 0x0A);
985                         adm8211_write_bbp(dev, 0x29, 0x40);
986                         adm8211_write_bbp(dev, 0x60, 0x08);
987                         adm8211_write_bbp(dev, 0x64, 0x01);
988                         break;
989
990                 case ADM8211_MAX2820:
991                         adm8211_write_bbp(dev, 0x00, 0x00);
992                         adm8211_write_bbp(dev, 0x01, 0x00);
993                         adm8211_write_bbp(dev, 0x02, 0x00);
994                         adm8211_write_bbp(dev, 0x03, 0x00);
995                         adm8211_write_bbp(dev, 0x06, 0x0f);
996                         adm8211_write_bbp(dev, 0x09, 0x05);
997                         adm8211_write_bbp(dev, 0x0a, 0x02);
998                         adm8211_write_bbp(dev, 0x0b, 0x00);
999                         adm8211_write_bbp(dev, 0x0c, 0x0f);
1000                         adm8211_write_bbp(dev, 0x0f, 0x55);
1001                         adm8211_write_bbp(dev, 0x10, 0x8d);
1002                         adm8211_write_bbp(dev, 0x11, 0x43);
1003                         adm8211_write_bbp(dev, 0x18, 0x4a);
1004                         adm8211_write_bbp(dev, 0x20, 0x20);
1005                         adm8211_write_bbp(dev, 0x21, 0x02);
1006                         adm8211_write_bbp(dev, 0x22, 0x23);
1007                         adm8211_write_bbp(dev, 0x23, 0x30);
1008                         adm8211_write_bbp(dev, 0x24, 0x2d);
1009                         adm8211_write_bbp(dev, 0x2a, 0x8c);
1010                         adm8211_write_bbp(dev, 0x2b, 0x81);
1011                         adm8211_write_bbp(dev, 0x2c, 0x44);
1012                         adm8211_write_bbp(dev, 0x29, 0x4a);
1013                         adm8211_write_bbp(dev, 0x60, 0x2b);
1014                         adm8211_write_bbp(dev, 0x64, 0x01);
1015                         break;
1016
1017                 case ADM8211_AL2210L:
1018                         adm8211_write_bbp(dev, 0x00, 0x00);
1019                         adm8211_write_bbp(dev, 0x01, 0x00);
1020                         adm8211_write_bbp(dev, 0x02, 0x00);
1021                         adm8211_write_bbp(dev, 0x03, 0x00);
1022                         adm8211_write_bbp(dev, 0x06, 0x0f);
1023                         adm8211_write_bbp(dev, 0x07, 0x05);
1024                         adm8211_write_bbp(dev, 0x08, 0x03);
1025                         adm8211_write_bbp(dev, 0x09, 0x00);
1026                         adm8211_write_bbp(dev, 0x0a, 0x00);
1027                         adm8211_write_bbp(dev, 0x0b, 0x00);
1028                         adm8211_write_bbp(dev, 0x0c, 0x10);
1029                         adm8211_write_bbp(dev, 0x0f, 0x55);
1030                         adm8211_write_bbp(dev, 0x10, 0x8d);
1031                         adm8211_write_bbp(dev, 0x11, 0x43);
1032                         adm8211_write_bbp(dev, 0x18, 0x4a);
1033                         adm8211_write_bbp(dev, 0x20, 0x20);
1034                         adm8211_write_bbp(dev, 0x21, 0x02);
1035                         adm8211_write_bbp(dev, 0x22, 0x23);
1036                         adm8211_write_bbp(dev, 0x23, 0x30);
1037                         adm8211_write_bbp(dev, 0x24, 0x2d);
1038                         adm8211_write_bbp(dev, 0x2a, 0xaa);
1039                         adm8211_write_bbp(dev, 0x2b, 0x81);
1040                         adm8211_write_bbp(dev, 0x2c, 0x44);
1041                         adm8211_write_bbp(dev, 0x29, 0xfa);
1042                         adm8211_write_bbp(dev, 0x60, 0x2d);
1043                         adm8211_write_bbp(dev, 0x64, 0x01);
1044                         break;
1045
1046                 case ADM8211_RFMD2948:
1047                         break;
1048
1049                 default:
1050                         printk(KERN_DEBUG "%s: unsupported transceiver %d\n",
1051                                wiphy_name(dev->wiphy), priv->transceiver_type);
1052                         break;
1053                 }
1054         } else
1055                 printk(KERN_DEBUG "%s: unsupported BBP %d\n",
1056                        wiphy_name(dev->wiphy), priv->bbp_type);
1057
1058         ADM8211_CSR_WRITE(SYNRF, 0);
1059
1060         /* Set RF CAL control source to MAC control */
1061         reg = ADM8211_CSR_READ(SYNCTL);
1062         reg |= ADM8211_SYNCTL_SELCAL;
1063         ADM8211_CSR_WRITE(SYNCTL, reg);
1064
1065         return 0;
1066 }
1067
1068 /* configures hw beacons/probe responses */
1069 static int adm8211_set_rate(struct ieee80211_hw *dev)
1070 {
1071         struct adm8211_priv *priv = dev->priv;
1072         u32 reg;
1073         int i = 0;
1074         u8 rate_buf[12] = {0};
1075
1076         /* write supported rates */
1077         if (priv->pdev->revision != ADM8211_REV_BA) {
1078                 rate_buf[0] = ARRAY_SIZE(adm8211_rates);
1079                 for (i = 0; i < ARRAY_SIZE(adm8211_rates); i++)
1080                         rate_buf[i + 1] = (adm8211_rates[i].bitrate / 5) | 0x80;
1081         } else {
1082                 /* workaround for rev BA specific bug */
1083                 rate_buf[0] = 0x04;
1084                 rate_buf[1] = 0x82;
1085                 rate_buf[2] = 0x04;
1086                 rate_buf[3] = 0x0b;
1087                 rate_buf[4] = 0x16;
1088         }
1089
1090         adm8211_write_sram_bytes(dev, ADM8211_SRAM_SUPP_RATE, rate_buf,
1091                                  ARRAY_SIZE(adm8211_rates) + 1);
1092
1093         reg = ADM8211_CSR_READ(PLCPHD) & 0x00FFFFFF; /* keep bits 0-23 */
1094         reg |= 1 << 15; /* short preamble */
1095         reg |= 110 << 24;
1096         ADM8211_CSR_WRITE(PLCPHD, reg);
1097
1098         /* MTMLT   = 512 TU (max TX MSDU lifetime)
1099          * BCNTSIG = plcp_signal (beacon, probe resp, and atim TX rate)
1100          * SRTYLIM = 224 (short retry limit, TX header value is default) */
1101         ADM8211_CSR_WRITE(TXLMT, (512 << 16) | (110 << 8) | (224 << 0));
1102
1103         return 0;
1104 }
1105
1106 static void adm8211_hw_init(struct ieee80211_hw *dev)
1107 {
1108         struct adm8211_priv *priv = dev->priv;
1109         u32 reg;
1110         u8 cline;
1111
1112         reg = ADM8211_CSR_READ(PAR);
1113         reg |= ADM8211_PAR_MRLE | ADM8211_PAR_MRME;
1114         reg &= ~(ADM8211_PAR_BAR | ADM8211_PAR_CAL);
1115
1116         if (!pci_set_mwi(priv->pdev)) {
1117                 reg |= 0x1 << 24;
1118                 pci_read_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, &cline);
1119
1120                 switch (cline) {
1121                 case  0x8: reg |= (0x1 << 14);
1122                            break;
1123                 case 0x16: reg |= (0x2 << 14);
1124                            break;
1125                 case 0x32: reg |= (0x3 << 14);
1126                            break;
1127                   default: reg |= (0x0 << 14);
1128                            break;
1129                 }
1130         }
1131
1132         ADM8211_CSR_WRITE(PAR, reg);
1133
1134         reg = ADM8211_CSR_READ(CSR_TEST1);
1135         reg &= ~(0xF << 28);
1136         reg |= (1 << 28) | (1 << 31);
1137         ADM8211_CSR_WRITE(CSR_TEST1, reg);
1138
1139         /* lose link after 4 lost beacons */
1140         reg = (0x04 << 21) | ADM8211_WCSR_TSFTWE | ADM8211_WCSR_LSOE;
1141         ADM8211_CSR_WRITE(WCSR, reg);
1142
1143         /* Disable APM, enable receive FIFO threshold, and set drain receive
1144          * threshold to store-and-forward */
1145         reg = ADM8211_CSR_READ(CMDR);
1146         reg &= ~(ADM8211_CMDR_APM | ADM8211_CMDR_DRT);
1147         reg |= ADM8211_CMDR_RTE | ADM8211_CMDR_DRT_SF;
1148         ADM8211_CSR_WRITE(CMDR, reg);
1149
1150         adm8211_set_rate(dev);
1151
1152         /* 4-bit values:
1153          * PWR1UP   = 8 * 2 ms
1154          * PWR0PAPE = 8 us or 5 us
1155          * PWR1PAPE = 1 us or 3 us
1156          * PWR0TRSW = 5 us
1157          * PWR1TRSW = 12 us
1158          * PWR0PE2  = 13 us
1159          * PWR1PE2  = 1 us
1160          * PWR0TXPE = 8 or 6 */
1161         if (priv->pdev->revision < ADM8211_REV_CA)
1162                 ADM8211_CSR_WRITE(TOFS2, 0x8815cd18);
1163         else
1164                 ADM8211_CSR_WRITE(TOFS2, 0x8535cd16);
1165
1166         /* Enable store and forward for transmit */
1167         priv->nar = ADM8211_NAR_SF | ADM8211_NAR_PB;
1168         ADM8211_CSR_WRITE(NAR, priv->nar);
1169
1170         /* Reset RF */
1171         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_RADIO);
1172         ADM8211_CSR_READ(SYNRF);
1173         msleep(10);
1174         ADM8211_CSR_WRITE(SYNRF, 0);
1175         ADM8211_CSR_READ(SYNRF);
1176         msleep(5);
1177
1178         /* Set CFP Max Duration to 0x10 TU */
1179         reg = ADM8211_CSR_READ(CFPP);
1180         reg &= ~(0xffff << 8);
1181         reg |= 0x0010 << 8;
1182         ADM8211_CSR_WRITE(CFPP, reg);
1183
1184         /* USCNT = 0x16 (number of system clocks, 22 MHz, in 1us
1185          * TUCNT = 0x3ff - Tu counter 1024 us  */
1186         ADM8211_CSR_WRITE(TOFS0, (0x16 << 24) | 0x3ff);
1187
1188         /* SLOT=20 us, SIFS=110 cycles of 22 MHz (5 us),
1189          * DIFS=50 us, EIFS=100 us */
1190         if (priv->pdev->revision < ADM8211_REV_CA)
1191                 ADM8211_CSR_WRITE(IFST, (20 << 23) | (110 << 15) |
1192                                         (50 << 9)  | 100);
1193         else
1194                 ADM8211_CSR_WRITE(IFST, (20 << 23) | (24 << 15) |
1195                                         (50 << 9)  | 100);
1196
1197         /* PCNT = 1 (MAC idle time awake/sleep, unit S)
1198          * RMRD = 2346 * 8 + 1 us (max RX duration)  */
1199         ADM8211_CSR_WRITE(RMD, (1 << 16) | 18769);
1200
1201         /* MART=65535 us, MIRT=256 us, TSFTOFST=0 us */
1202         ADM8211_CSR_WRITE(RSPT, 0xffffff00);
1203
1204         /* Initialize BBP (and SYN) */
1205         adm8211_hw_init_bbp(dev);
1206
1207         /* make sure interrupts are off */
1208         ADM8211_CSR_WRITE(IER, 0);
1209
1210         /* ACK interrupts */
1211         ADM8211_CSR_WRITE(STSR, ADM8211_CSR_READ(STSR));
1212
1213         /* Setup WEP (turns it off for now) */
1214         reg = ADM8211_CSR_READ(MACTEST);
1215         reg &= ~(7 << 20);
1216         ADM8211_CSR_WRITE(MACTEST, reg);
1217
1218         reg = ADM8211_CSR_READ(WEPCTL);
1219         reg &= ~ADM8211_WEPCTL_WEPENABLE;
1220         reg |= ADM8211_WEPCTL_WEPRXBYP;
1221         ADM8211_CSR_WRITE(WEPCTL, reg);
1222
1223         /* Clear the missed-packet counter. */
1224         ADM8211_CSR_READ(LPC);
1225 }
1226
1227 static int adm8211_hw_reset(struct ieee80211_hw *dev)
1228 {
1229         struct adm8211_priv *priv = dev->priv;
1230         u32 reg, tmp;
1231         int timeout = 100;
1232
1233         /* Power-on issue */
1234         /* TODO: check if this is necessary */
1235         ADM8211_CSR_WRITE(FRCTL, 0);
1236
1237         /* Reset the chip */
1238         tmp = ADM8211_CSR_READ(PAR);
1239         ADM8211_CSR_WRITE(PAR, ADM8211_PAR_SWR);
1240
1241         while ((ADM8211_CSR_READ(PAR) & ADM8211_PAR_SWR) && timeout--)
1242                 msleep(50);
1243
1244         if (timeout <= 0)
1245                 return -ETIMEDOUT;
1246
1247         ADM8211_CSR_WRITE(PAR, tmp);
1248
1249         if (priv->pdev->revision == ADM8211_REV_BA &&
1250             (priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER ||
1251              priv->transceiver_type == ADM8211_RFMD2958)) {
1252                 reg = ADM8211_CSR_READ(CSR_TEST1);
1253                 reg |= (1 << 4) | (1 << 5);
1254                 ADM8211_CSR_WRITE(CSR_TEST1, reg);
1255         } else if (priv->pdev->revision == ADM8211_REV_CA) {
1256                 reg = ADM8211_CSR_READ(CSR_TEST1);
1257                 reg &= ~((1 << 4) | (1 << 5));
1258                 ADM8211_CSR_WRITE(CSR_TEST1, reg);
1259         }
1260
1261         ADM8211_CSR_WRITE(FRCTL, 0);
1262
1263         reg = ADM8211_CSR_READ(CSR_TEST0);
1264         reg |= ADM8211_CSR_TEST0_EPRLD; /* EEPROM Recall */
1265         ADM8211_CSR_WRITE(CSR_TEST0, reg);
1266
1267         adm8211_clear_sram(dev);
1268
1269         return 0;
1270 }
1271
1272 static u64 adm8211_get_tsft(struct ieee80211_hw *dev)
1273 {
1274         struct adm8211_priv *priv = dev->priv;
1275         u32 tsftl;
1276         u64 tsft;
1277
1278         tsftl = ADM8211_CSR_READ(TSFTL);
1279         tsft = ADM8211_CSR_READ(TSFTH);
1280         tsft <<= 32;
1281         tsft |= tsftl;
1282
1283         return tsft;
1284 }
1285
1286 static void adm8211_set_interval(struct ieee80211_hw *dev,
1287                                  unsigned short bi, unsigned short li)
1288 {
1289         struct adm8211_priv *priv = dev->priv;
1290         u32 reg;
1291
1292         /* BP (beacon interval) = data->beacon_interval
1293          * LI (listen interval) = data->listen_interval (in beacon intervals) */
1294         reg = (bi << 16) | li;
1295         ADM8211_CSR_WRITE(BPLI, reg);
1296 }
1297
1298 static void adm8211_set_bssid(struct ieee80211_hw *dev, const u8 *bssid)
1299 {
1300         struct adm8211_priv *priv = dev->priv;
1301         u32 reg;
1302
1303         ADM8211_CSR_WRITE(BSSID0, le32_to_cpu(*(__le32 *)bssid));
1304         reg = ADM8211_CSR_READ(ABDA1);
1305         reg &= 0x0000ffff;
1306         reg |= (bssid[4] << 16) | (bssid[5] << 24);
1307         ADM8211_CSR_WRITE(ABDA1, reg);
1308 }
1309
1310 static int adm8211_set_ssid(struct ieee80211_hw *dev, u8 *ssid, size_t ssid_len)
1311 {
1312         struct adm8211_priv *priv = dev->priv;
1313         u8 buf[36];
1314
1315         if (ssid_len > 32)
1316                 return -EINVAL;
1317
1318         memset(buf, 0, sizeof(buf));
1319         buf[0] = ssid_len;
1320         memcpy(buf + 1, ssid, ssid_len);
1321         adm8211_write_sram_bytes(dev, ADM8211_SRAM_SSID, buf, 33);
1322         /* TODO: configure beacon for adhoc? */
1323         return 0;
1324 }
1325
1326 static int adm8211_config(struct ieee80211_hw *dev, struct ieee80211_conf *conf)
1327 {
1328         struct adm8211_priv *priv = dev->priv;
1329         int channel = ieee80211_frequency_to_channel(conf->channel->center_freq);
1330
1331         if (channel != priv->channel) {
1332                 priv->channel = channel;
1333                 adm8211_rf_set_channel(dev, priv->channel);
1334         }
1335
1336         return 0;
1337 }
1338
1339 static int adm8211_config_interface(struct ieee80211_hw *dev,
1340                                     struct ieee80211_vif *vif,
1341                                     struct ieee80211_if_conf *conf)
1342 {
1343         struct adm8211_priv *priv = dev->priv;
1344
1345         if (memcmp(conf->bssid, priv->bssid, ETH_ALEN)) {
1346                 adm8211_set_bssid(dev, conf->bssid);
1347                 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
1348         }
1349
1350         if (conf->ssid_len != priv->ssid_len ||
1351             memcmp(conf->ssid, priv->ssid, conf->ssid_len)) {
1352                 adm8211_set_ssid(dev, conf->ssid, conf->ssid_len);
1353                 priv->ssid_len = conf->ssid_len;
1354                 memcpy(priv->ssid, conf->ssid, conf->ssid_len);
1355         }
1356
1357         return 0;
1358 }
1359
1360 static void adm8211_configure_filter(struct ieee80211_hw *dev,
1361                                      unsigned int changed_flags,
1362                                      unsigned int *total_flags,
1363                                      int mc_count, struct dev_mc_list *mclist)
1364 {
1365         static const u8 bcast[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
1366         struct adm8211_priv *priv = dev->priv;
1367         unsigned int bit_nr, new_flags;
1368         u32 mc_filter[2];
1369         int i;
1370
1371         new_flags = 0;
1372
1373         if (*total_flags & FIF_PROMISC_IN_BSS) {
1374                 new_flags |= FIF_PROMISC_IN_BSS;
1375                 priv->nar |= ADM8211_NAR_PR;
1376                 priv->nar &= ~ADM8211_NAR_MM;
1377                 mc_filter[1] = mc_filter[0] = ~0;
1378         } else if ((*total_flags & FIF_ALLMULTI) || (mc_count > 32)) {
1379                 new_flags |= FIF_ALLMULTI;
1380                 priv->nar &= ~ADM8211_NAR_PR;
1381                 priv->nar |= ADM8211_NAR_MM;
1382                 mc_filter[1] = mc_filter[0] = ~0;
1383         } else {
1384                 priv->nar &= ~(ADM8211_NAR_MM | ADM8211_NAR_PR);
1385                 mc_filter[1] = mc_filter[0] = 0;
1386                 for (i = 0; i < mc_count; i++) {
1387                         if (!mclist)
1388                                 break;
1389                         bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1390
1391                         bit_nr &= 0x3F;
1392                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1393                         mclist = mclist->next;
1394                 }
1395         }
1396
1397         ADM8211_IDLE_RX();
1398
1399         ADM8211_CSR_WRITE(MAR0, mc_filter[0]);
1400         ADM8211_CSR_WRITE(MAR1, mc_filter[1]);
1401         ADM8211_CSR_READ(NAR);
1402
1403         if (priv->nar & ADM8211_NAR_PR)
1404                 dev->flags |= IEEE80211_HW_RX_INCLUDES_FCS;
1405         else
1406                 dev->flags &= ~IEEE80211_HW_RX_INCLUDES_FCS;
1407
1408         if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
1409                 adm8211_set_bssid(dev, bcast);
1410         else
1411                 adm8211_set_bssid(dev, priv->bssid);
1412
1413         ADM8211_RESTORE();
1414
1415         *total_flags = new_flags;
1416 }
1417
1418 static int adm8211_add_interface(struct ieee80211_hw *dev,
1419                                  struct ieee80211_if_init_conf *conf)
1420 {
1421         struct adm8211_priv *priv = dev->priv;
1422         if (priv->mode != IEEE80211_IF_TYPE_MNTR)
1423                 return -EOPNOTSUPP;
1424
1425         switch (conf->type) {
1426         case IEEE80211_IF_TYPE_STA:
1427                 priv->mode = conf->type;
1428                 break;
1429         default:
1430                 return -EOPNOTSUPP;
1431         }
1432
1433         ADM8211_IDLE();
1434
1435         ADM8211_CSR_WRITE(PAR0, le32_to_cpu(*(__le32 *)conf->mac_addr));
1436         ADM8211_CSR_WRITE(PAR1, le16_to_cpu(*(__le16 *)(conf->mac_addr + 4)));
1437
1438         adm8211_update_mode(dev);
1439
1440         ADM8211_RESTORE();
1441
1442         return 0;
1443 }
1444
1445 static void adm8211_remove_interface(struct ieee80211_hw *dev,
1446                                      struct ieee80211_if_init_conf *conf)
1447 {
1448         struct adm8211_priv *priv = dev->priv;
1449         priv->mode = IEEE80211_IF_TYPE_MNTR;
1450 }
1451
1452 static int adm8211_init_rings(struct ieee80211_hw *dev)
1453 {
1454         struct adm8211_priv *priv = dev->priv;
1455         struct adm8211_desc *desc = NULL;
1456         struct adm8211_rx_ring_info *rx_info;
1457         struct adm8211_tx_ring_info *tx_info;
1458         unsigned int i;
1459
1460         for (i = 0; i < priv->rx_ring_size; i++) {
1461                 desc = &priv->rx_ring[i];
1462                 desc->status = 0;
1463                 desc->length = cpu_to_le32(RX_PKT_SIZE);
1464                 priv->rx_buffers[i].skb = NULL;
1465         }
1466         /* Mark the end of RX ring; hw returns to base address after this
1467          * descriptor */
1468         desc->length |= cpu_to_le32(RDES1_CONTROL_RER);
1469
1470         for (i = 0; i < priv->rx_ring_size; i++) {
1471                 desc = &priv->rx_ring[i];
1472                 rx_info = &priv->rx_buffers[i];
1473
1474                 rx_info->skb = dev_alloc_skb(RX_PKT_SIZE);
1475                 if (rx_info->skb == NULL)
1476                         break;
1477                 rx_info->mapping = pci_map_single(priv->pdev,
1478                                                   skb_tail_pointer(rx_info->skb),
1479                                                   RX_PKT_SIZE,
1480                                                   PCI_DMA_FROMDEVICE);
1481                 desc->buffer1 = cpu_to_le32(rx_info->mapping);
1482                 desc->status = cpu_to_le32(RDES0_STATUS_OWN | RDES0_STATUS_SQL);
1483         }
1484
1485         /* Setup TX ring. TX buffers descriptors will be filled in as needed */
1486         for (i = 0; i < priv->tx_ring_size; i++) {
1487                 desc = &priv->tx_ring[i];
1488                 tx_info = &priv->tx_buffers[i];
1489
1490                 tx_info->skb = NULL;
1491                 tx_info->mapping = 0;
1492                 desc->status = 0;
1493         }
1494         desc->length = cpu_to_le32(TDES1_CONTROL_TER);
1495
1496         priv->cur_rx = priv->cur_tx = priv->dirty_tx = 0;
1497         ADM8211_CSR_WRITE(RDB, priv->rx_ring_dma);
1498         ADM8211_CSR_WRITE(TDBD, priv->tx_ring_dma);
1499
1500         return 0;
1501 }
1502
1503 static void adm8211_free_rings(struct ieee80211_hw *dev)
1504 {
1505         struct adm8211_priv *priv = dev->priv;
1506         unsigned int i;
1507
1508         for (i = 0; i < priv->rx_ring_size; i++) {
1509                 if (!priv->rx_buffers[i].skb)
1510                         continue;
1511
1512                 pci_unmap_single(
1513                         priv->pdev,
1514                         priv->rx_buffers[i].mapping,
1515                         RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
1516
1517                 dev_kfree_skb(priv->rx_buffers[i].skb);
1518         }
1519
1520         for (i = 0; i < priv->tx_ring_size; i++) {
1521                 if (!priv->tx_buffers[i].skb)
1522                         continue;
1523
1524                 pci_unmap_single(priv->pdev,
1525                                  priv->tx_buffers[i].mapping,
1526                                  priv->tx_buffers[i].skb->len,
1527                                  PCI_DMA_TODEVICE);
1528
1529                 dev_kfree_skb(priv->tx_buffers[i].skb);
1530         }
1531 }
1532
1533 static int adm8211_start(struct ieee80211_hw *dev)
1534 {
1535         struct adm8211_priv *priv = dev->priv;
1536         int retval;
1537
1538         /* Power up MAC and RF chips */
1539         retval = adm8211_hw_reset(dev);
1540         if (retval) {
1541                 printk(KERN_ERR "%s: hardware reset failed\n",
1542                        wiphy_name(dev->wiphy));
1543                 goto fail;
1544         }
1545
1546         retval = adm8211_init_rings(dev);
1547         if (retval) {
1548                 printk(KERN_ERR "%s: failed to initialize rings\n",
1549                        wiphy_name(dev->wiphy));
1550                 goto fail;
1551         }
1552
1553         /* Init hardware */
1554         adm8211_hw_init(dev);
1555         adm8211_rf_set_channel(dev, priv->channel);
1556
1557         retval = request_irq(priv->pdev->irq, &adm8211_interrupt,
1558                              IRQF_SHARED, "adm8211", dev);
1559         if (retval) {
1560                 printk(KERN_ERR "%s: failed to register IRQ handler\n",
1561                        wiphy_name(dev->wiphy));
1562                 goto fail;
1563         }
1564
1565         ADM8211_CSR_WRITE(IER, ADM8211_IER_NIE | ADM8211_IER_AIE |
1566                                ADM8211_IER_RCIE | ADM8211_IER_TCIE |
1567                                ADM8211_IER_TDUIE | ADM8211_IER_GPTIE);
1568         priv->mode = IEEE80211_IF_TYPE_MNTR;
1569         adm8211_update_mode(dev);
1570         ADM8211_CSR_WRITE(RDR, 0);
1571
1572         adm8211_set_interval(dev, 100, 10);
1573         return 0;
1574
1575 fail:
1576         return retval;
1577 }
1578
1579 static void adm8211_stop(struct ieee80211_hw *dev)
1580 {
1581         struct adm8211_priv *priv = dev->priv;
1582
1583         priv->mode = IEEE80211_IF_TYPE_INVALID;
1584         priv->nar = 0;
1585         ADM8211_CSR_WRITE(NAR, 0);
1586         ADM8211_CSR_WRITE(IER, 0);
1587         ADM8211_CSR_READ(NAR);
1588
1589         free_irq(priv->pdev->irq, dev);
1590
1591         adm8211_free_rings(dev);
1592 }
1593
1594 static void adm8211_calc_durations(int *dur, int *plcp, size_t payload_len, int len,
1595                                    int plcp_signal, int short_preamble)
1596 {
1597         /* Alternative calculation from NetBSD: */
1598
1599 /* IEEE 802.11b durations for DSSS PHY in microseconds */
1600 #define IEEE80211_DUR_DS_LONG_PREAMBLE  144
1601 #define IEEE80211_DUR_DS_SHORT_PREAMBLE 72
1602 #define IEEE80211_DUR_DS_FAST_PLCPHDR   24
1603 #define IEEE80211_DUR_DS_SLOW_PLCPHDR   48
1604 #define IEEE80211_DUR_DS_SLOW_ACK       112
1605 #define IEEE80211_DUR_DS_FAST_ACK       56
1606 #define IEEE80211_DUR_DS_SLOW_CTS       112
1607 #define IEEE80211_DUR_DS_FAST_CTS       56
1608 #define IEEE80211_DUR_DS_SLOT           20
1609 #define IEEE80211_DUR_DS_SIFS           10
1610
1611         int remainder;
1612
1613         *dur = (80 * (24 + payload_len) + plcp_signal - 1)
1614                 / plcp_signal;
1615
1616         if (plcp_signal <= PLCP_SIGNAL_2M)
1617                 /* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */
1618                 *dur += 3 * (IEEE80211_DUR_DS_SIFS +
1619                              IEEE80211_DUR_DS_SHORT_PREAMBLE +
1620                              IEEE80211_DUR_DS_FAST_PLCPHDR) +
1621                              IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK;
1622         else
1623                 /* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */
1624                 *dur += 3 * (IEEE80211_DUR_DS_SIFS +
1625                              IEEE80211_DUR_DS_SHORT_PREAMBLE +
1626                              IEEE80211_DUR_DS_FAST_PLCPHDR) +
1627                              IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK;
1628
1629         /* lengthen duration if long preamble */
1630         if (!short_preamble)
1631                 *dur += 3 * (IEEE80211_DUR_DS_LONG_PREAMBLE -
1632                              IEEE80211_DUR_DS_SHORT_PREAMBLE) +
1633                         3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR -
1634                              IEEE80211_DUR_DS_FAST_PLCPHDR);
1635
1636
1637         *plcp = (80 * len) / plcp_signal;
1638         remainder = (80 * len) % plcp_signal;
1639         if (plcp_signal == PLCP_SIGNAL_11M &&
1640             remainder <= 30 && remainder > 0)
1641                 *plcp = (*plcp | 0x8000) + 1;
1642         else if (remainder)
1643                 (*plcp)++;
1644 }
1645
1646 /* Transmit skb w/adm8211_tx_hdr (802.11 header created by hardware) */
1647 static void adm8211_tx_raw(struct ieee80211_hw *dev, struct sk_buff *skb,
1648                            u16 plcp_signal,
1649                            struct ieee80211_tx_control *control,
1650                            size_t hdrlen)
1651 {
1652         struct adm8211_priv *priv = dev->priv;
1653         unsigned long flags;
1654         dma_addr_t mapping;
1655         unsigned int entry;
1656         u32 flag;
1657
1658         mapping = pci_map_single(priv->pdev, skb->data, skb->len,
1659                                  PCI_DMA_TODEVICE);
1660
1661         spin_lock_irqsave(&priv->lock, flags);
1662
1663         if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size / 2)
1664                 flag = TDES1_CONTROL_IC | TDES1_CONTROL_LS | TDES1_CONTROL_FS;
1665         else
1666                 flag = TDES1_CONTROL_LS | TDES1_CONTROL_FS;
1667
1668         if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size - 2)
1669                 ieee80211_stop_queue(dev, 0);
1670
1671         entry = priv->cur_tx % priv->tx_ring_size;
1672
1673         priv->tx_buffers[entry].skb = skb;
1674         priv->tx_buffers[entry].mapping = mapping;
1675         memcpy(&priv->tx_buffers[entry].tx_control, control, sizeof(*control));
1676         priv->tx_buffers[entry].hdrlen = hdrlen;
1677         priv->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
1678
1679         if (entry == priv->tx_ring_size - 1)
1680                 flag |= TDES1_CONTROL_TER;
1681         priv->tx_ring[entry].length = cpu_to_le32(flag | skb->len);
1682
1683         /* Set TX rate (SIGNAL field in PLCP PPDU format) */
1684         flag = TDES0_CONTROL_OWN | (plcp_signal << 20) | 8 /* ? */;
1685         priv->tx_ring[entry].status = cpu_to_le32(flag);
1686
1687         priv->cur_tx++;
1688
1689         spin_unlock_irqrestore(&priv->lock, flags);
1690
1691         /* Trigger transmit poll */
1692         ADM8211_CSR_WRITE(TDR, 0);
1693 }
1694
1695 /* Put adm8211_tx_hdr on skb and transmit */
1696 static int adm8211_tx(struct ieee80211_hw *dev, struct sk_buff *skb,
1697                       struct ieee80211_tx_control *control)
1698 {
1699         struct adm8211_tx_hdr *txhdr;
1700         u16 fc;
1701         size_t payload_len, hdrlen;
1702         int plcp, dur, len, plcp_signal, short_preamble;
1703         struct ieee80211_hdr *hdr;
1704
1705         short_preamble = !!(control->tx_rate->flags &
1706                                         IEEE80211_TXCTL_SHORT_PREAMBLE);
1707         plcp_signal = control->tx_rate->bitrate;
1708
1709         hdr = (struct ieee80211_hdr *)skb->data;
1710         fc = le16_to_cpu(hdr->frame_control) & ~IEEE80211_FCTL_PROTECTED;
1711         hdrlen = ieee80211_get_hdrlen(fc);
1712         memcpy(skb->cb, skb->data, hdrlen);
1713         hdr = (struct ieee80211_hdr *)skb->cb;
1714         skb_pull(skb, hdrlen);
1715         payload_len = skb->len;
1716
1717         txhdr = (struct adm8211_tx_hdr *) skb_push(skb, sizeof(*txhdr));
1718         memset(txhdr, 0, sizeof(*txhdr));
1719         memcpy(txhdr->da, ieee80211_get_DA(hdr), ETH_ALEN);
1720         txhdr->signal = plcp_signal;
1721         txhdr->frame_body_size = cpu_to_le16(payload_len);
1722         txhdr->frame_control = hdr->frame_control;
1723
1724         len = hdrlen + payload_len + FCS_LEN;
1725         if (fc & IEEE80211_FCTL_PROTECTED)
1726                 len += 8;
1727
1728         txhdr->frag = cpu_to_le16(0x0FFF);
1729         adm8211_calc_durations(&dur, &plcp, payload_len,
1730                                len, plcp_signal, short_preamble);
1731         txhdr->plcp_frag_head_len = cpu_to_le16(plcp);
1732         txhdr->plcp_frag_tail_len = cpu_to_le16(plcp);
1733         txhdr->dur_frag_head = cpu_to_le16(dur);
1734         txhdr->dur_frag_tail = cpu_to_le16(dur);
1735
1736         txhdr->header_control = cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_EXTEND_HEADER);
1737
1738         if (short_preamble)
1739                 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_SHORT_PREAMBLE);
1740
1741         if (control->flags & IEEE80211_TXCTL_USE_RTS_CTS)
1742                 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_RTS);
1743
1744         if (fc & IEEE80211_FCTL_PROTECTED)
1745                 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_WEP_ENGINE);
1746
1747         txhdr->retry_limit = control->retry_limit;
1748
1749         adm8211_tx_raw(dev, skb, plcp_signal, control, hdrlen);
1750
1751         return NETDEV_TX_OK;
1752 }
1753
1754 static int adm8211_alloc_rings(struct ieee80211_hw *dev)
1755 {
1756         struct adm8211_priv *priv = dev->priv;
1757         unsigned int ring_size;
1758
1759         priv->rx_buffers = kmalloc(sizeof(*priv->rx_buffers) * priv->rx_ring_size +
1760                                    sizeof(*priv->tx_buffers) * priv->tx_ring_size, GFP_KERNEL);
1761         if (!priv->rx_buffers)
1762                 return -ENOMEM;
1763
1764         priv->tx_buffers = (void *)priv->rx_buffers +
1765                            sizeof(*priv->rx_buffers) * priv->rx_ring_size;
1766
1767         /* Allocate TX/RX descriptors */
1768         ring_size = sizeof(struct adm8211_desc) * priv->rx_ring_size +
1769                     sizeof(struct adm8211_desc) * priv->tx_ring_size;
1770         priv->rx_ring = pci_alloc_consistent(priv->pdev, ring_size,
1771                                              &priv->rx_ring_dma);
1772
1773         if (!priv->rx_ring) {
1774                 kfree(priv->rx_buffers);
1775                 priv->rx_buffers = NULL;
1776                 priv->tx_buffers = NULL;
1777                 return -ENOMEM;
1778         }
1779
1780         priv->tx_ring = (struct adm8211_desc *)(priv->rx_ring +
1781                                                 priv->rx_ring_size);
1782         priv->tx_ring_dma = priv->rx_ring_dma +
1783                             sizeof(struct adm8211_desc) * priv->rx_ring_size;
1784
1785         return 0;
1786 }
1787
1788 static const struct ieee80211_ops adm8211_ops = {
1789         .tx                     = adm8211_tx,
1790         .start                  = adm8211_start,
1791         .stop                   = adm8211_stop,
1792         .add_interface          = adm8211_add_interface,
1793         .remove_interface       = adm8211_remove_interface,
1794         .config                 = adm8211_config,
1795         .config_interface       = adm8211_config_interface,
1796         .configure_filter       = adm8211_configure_filter,
1797         .get_stats              = adm8211_get_stats,
1798         .get_tx_stats           = adm8211_get_tx_stats,
1799         .get_tsf                = adm8211_get_tsft
1800 };
1801
1802 static int __devinit adm8211_probe(struct pci_dev *pdev,
1803                                    const struct pci_device_id *id)
1804 {
1805         struct ieee80211_hw *dev;
1806         struct adm8211_priv *priv;
1807         unsigned long mem_addr, mem_len;
1808         unsigned int io_addr, io_len;
1809         int err;
1810         u32 reg;
1811         u8 perm_addr[ETH_ALEN];
1812         DECLARE_MAC_BUF(mac);
1813
1814         err = pci_enable_device(pdev);
1815         if (err) {
1816                 printk(KERN_ERR "%s (adm8211): Cannot enable new PCI device\n",
1817                        pci_name(pdev));
1818                 return err;
1819         }
1820
1821         io_addr = pci_resource_start(pdev, 0);
1822         io_len = pci_resource_len(pdev, 0);
1823         mem_addr = pci_resource_start(pdev, 1);
1824         mem_len = pci_resource_len(pdev, 1);
1825         if (io_len < 256 || mem_len < 1024) {
1826                 printk(KERN_ERR "%s (adm8211): Too short PCI resources\n",
1827                        pci_name(pdev));
1828                 goto err_disable_pdev;
1829         }
1830
1831
1832         /* check signature */
1833         pci_read_config_dword(pdev, 0x80 /* CR32 */, &reg);
1834         if (reg != ADM8211_SIG1 && reg != ADM8211_SIG2) {
1835                 printk(KERN_ERR "%s (adm8211): Invalid signature (0x%x)\n",
1836                        pci_name(pdev), reg);
1837                 goto err_disable_pdev;
1838         }
1839
1840         err = pci_request_regions(pdev, "adm8211");
1841         if (err) {
1842                 printk(KERN_ERR "%s (adm8211): Cannot obtain PCI resources\n",
1843                        pci_name(pdev));
1844                 return err; /* someone else grabbed it? don't disable it */
1845         }
1846
1847         if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) ||
1848             pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
1849                 printk(KERN_ERR "%s (adm8211): No suitable DMA available\n",
1850                        pci_name(pdev));
1851                 goto err_free_reg;
1852         }
1853
1854         pci_set_master(pdev);
1855
1856         dev = ieee80211_alloc_hw(sizeof(*priv), &adm8211_ops);
1857         if (!dev) {
1858                 printk(KERN_ERR "%s (adm8211): ieee80211 alloc failed\n",
1859                        pci_name(pdev));
1860                 err = -ENOMEM;
1861                 goto err_free_reg;
1862         }
1863         priv = dev->priv;
1864         priv->pdev = pdev;
1865
1866         spin_lock_init(&priv->lock);
1867
1868         SET_IEEE80211_DEV(dev, &pdev->dev);
1869
1870         pci_set_drvdata(pdev, dev);
1871
1872         priv->map = pci_iomap(pdev, 1, mem_len);
1873         if (!priv->map)
1874                 priv->map = pci_iomap(pdev, 0, io_len);
1875
1876         if (!priv->map) {
1877                 printk(KERN_ERR "%s (adm8211): Cannot map device memory\n",
1878                        pci_name(pdev));
1879                 goto err_free_dev;
1880         }
1881
1882         priv->rx_ring_size = rx_ring_size;
1883         priv->tx_ring_size = tx_ring_size;
1884
1885         if (adm8211_alloc_rings(dev)) {
1886                 printk(KERN_ERR "%s (adm8211): Cannot allocate TX/RX ring\n",
1887                        pci_name(pdev));
1888                 goto err_iounmap;
1889         }
1890
1891         *(__le32 *)perm_addr = cpu_to_le32(ADM8211_CSR_READ(PAR0));
1892         *(__le16 *)&perm_addr[4] =
1893                 cpu_to_le16(ADM8211_CSR_READ(PAR1) & 0xFFFF);
1894
1895         if (!is_valid_ether_addr(perm_addr)) {
1896                 printk(KERN_WARNING "%s (adm8211): Invalid hwaddr in EEPROM!\n",
1897                        pci_name(pdev));
1898                 random_ether_addr(perm_addr);
1899         }
1900         SET_IEEE80211_PERM_ADDR(dev, perm_addr);
1901
1902         dev->extra_tx_headroom = sizeof(struct adm8211_tx_hdr);
1903         /* dev->flags = IEEE80211_HW_RX_INCLUDES_FCS in promisc mode */
1904
1905         dev->channel_change_time = 1000;
1906         dev->max_rssi = 100;    /* FIXME: find better value */
1907
1908         dev->queues = 1; /* ADM8211C supports more, maybe ADM8211B too */
1909
1910         priv->retry_limit = 3;
1911         priv->ant_power = 0x40;
1912         priv->tx_power = 0x40;
1913         priv->lpf_cutoff = 0xFF;
1914         priv->lnags_threshold = 0xFF;
1915         priv->mode = IEEE80211_IF_TYPE_INVALID;
1916
1917         /* Power-on issue. EEPROM won't read correctly without */
1918         if (pdev->revision >= ADM8211_REV_BA) {
1919                 ADM8211_CSR_WRITE(FRCTL, 0);
1920                 ADM8211_CSR_READ(FRCTL);
1921                 ADM8211_CSR_WRITE(FRCTL, 1);
1922                 ADM8211_CSR_READ(FRCTL);
1923                 msleep(100);
1924         }
1925
1926         err = adm8211_read_eeprom(dev);
1927         if (err) {
1928                 printk(KERN_ERR "%s (adm8211): Can't alloc eeprom buffer\n",
1929                        pci_name(pdev));
1930                 goto err_free_desc;
1931         }
1932
1933         priv->channel = 1;
1934
1935         dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
1936
1937         err = ieee80211_register_hw(dev);
1938         if (err) {
1939                 printk(KERN_ERR "%s (adm8211): Cannot register device\n",
1940                        pci_name(pdev));
1941                 goto err_free_desc;
1942         }
1943
1944         printk(KERN_INFO "%s: hwaddr %s, Rev 0x%02x\n",
1945                wiphy_name(dev->wiphy), print_mac(mac, dev->wiphy->perm_addr),
1946                pdev->revision);
1947
1948         return 0;
1949
1950  err_free_desc:
1951         pci_free_consistent(pdev,
1952                             sizeof(struct adm8211_desc) * priv->rx_ring_size +
1953                             sizeof(struct adm8211_desc) * priv->tx_ring_size,
1954                             priv->rx_ring, priv->rx_ring_dma);
1955         kfree(priv->rx_buffers);
1956
1957  err_iounmap:
1958         pci_iounmap(pdev, priv->map);
1959
1960  err_free_dev:
1961         pci_set_drvdata(pdev, NULL);
1962         ieee80211_free_hw(dev);
1963
1964  err_free_reg:
1965         pci_release_regions(pdev);
1966
1967  err_disable_pdev:
1968         pci_disable_device(pdev);
1969         return err;
1970 }
1971
1972
1973 static void __devexit adm8211_remove(struct pci_dev *pdev)
1974 {
1975         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1976         struct adm8211_priv *priv;
1977
1978         if (!dev)
1979                 return;
1980
1981         ieee80211_unregister_hw(dev);
1982
1983         priv = dev->priv;
1984
1985         pci_free_consistent(pdev,
1986                             sizeof(struct adm8211_desc) * priv->rx_ring_size +
1987                             sizeof(struct adm8211_desc) * priv->tx_ring_size,
1988                             priv->rx_ring, priv->rx_ring_dma);
1989
1990         kfree(priv->rx_buffers);
1991         kfree(priv->eeprom);
1992         pci_iounmap(pdev, priv->map);
1993         pci_release_regions(pdev);
1994         pci_disable_device(pdev);
1995         ieee80211_free_hw(dev);
1996 }
1997
1998
1999 #ifdef CONFIG_PM
2000 static int adm8211_suspend(struct pci_dev *pdev, pm_message_t state)
2001 {
2002         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
2003         struct adm8211_priv *priv = dev->priv;
2004
2005         if (priv->mode != IEEE80211_IF_TYPE_INVALID) {
2006                 ieee80211_stop_queues(dev);
2007                 adm8211_stop(dev);
2008         }
2009
2010         pci_save_state(pdev);
2011         pci_set_power_state(pdev, pci_choose_state(pdev, state));
2012         return 0;
2013 }
2014
2015 static int adm8211_resume(struct pci_dev *pdev)
2016 {
2017         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
2018         struct adm8211_priv *priv = dev->priv;
2019
2020         pci_set_power_state(pdev, PCI_D0);
2021         pci_restore_state(pdev);
2022
2023         if (priv->mode != IEEE80211_IF_TYPE_INVALID) {
2024                 adm8211_start(dev);
2025                 ieee80211_start_queues(dev);
2026         }
2027
2028         return 0;
2029 }
2030 #endif /* CONFIG_PM */
2031
2032
2033 MODULE_DEVICE_TABLE(pci, adm8211_pci_id_table);
2034
2035 /* TODO: implement enable_wake */
2036 static struct pci_driver adm8211_driver = {
2037         .name           = "adm8211",
2038         .id_table       = adm8211_pci_id_table,
2039         .probe          = adm8211_probe,
2040         .remove         = __devexit_p(adm8211_remove),
2041 #ifdef CONFIG_PM
2042         .suspend        = adm8211_suspend,
2043         .resume         = adm8211_resume,
2044 #endif /* CONFIG_PM */
2045 };
2046
2047
2048
2049 static int __init adm8211_init(void)
2050 {
2051         return pci_register_driver(&adm8211_driver);
2052 }
2053
2054
2055 static void __exit adm8211_exit(void)
2056 {
2057         pci_unregister_driver(&adm8211_driver);
2058 }
2059
2060
2061 module_init(adm8211_init);
2062 module_exit(adm8211_exit);