57914fbd41d370c15df6c2a9531a069a77731166
[linux-2.6.git] / drivers / net / wan / pc300_drv.c
1 #define USE_PCI_CLOCK
2 static char rcsid[] = 
3 "Revision: 3.4.5 Date: 2002/03/07 ";
4
5 /*
6  * pc300.c      Cyclades-PC300(tm) Driver.
7  *
8  * Author:      Ivan Passos <ivan@cyclades.com>
9  * Maintainer:  PC300 Maintainer <pc300@cyclades.com>
10  *
11  * Copyright:   (c) 1999-2003 Cyclades Corp.
12  *
13  *      This program is free software; you can redistribute it and/or
14  *      modify it under the terms of the GNU General Public License
15  *      as published by the Free Software Foundation; either version
16  *      2 of the License, or (at your option) any later version.
17  *      
18  *      Using tabstop = 4.
19  * 
20  * $Log: pc300_drv.c,v $
21  * Revision 3.23  2002/03/20 13:58:40  henrique
22  * Fixed ortographic mistakes
23  *
24  * Revision 3.22  2002/03/13 16:56:56  henrique
25  * Take out the debug messages
26  *
27  * Revision 3.21  2002/03/07 14:17:09  henrique
28  * License data fixed
29  *
30  * Revision 3.20  2002/01/17 17:58:52  ivan
31  * Support for PC300-TE/M (PMC).
32  *
33  * Revision 3.19  2002/01/03 17:08:47  daniela
34  * Enables DMA reception when the SCA-II disables it improperly.
35  *
36  * Revision 3.18  2001/12/03 18:47:50  daniela
37  * Esthetic changes.
38  *
39  * Revision 3.17  2001/10/19 16:50:13  henrique
40  * Patch to kernel 2.4.12 and new generic hdlc.
41  *
42  * Revision 3.16  2001/10/16 15:12:31  regina
43  * clear statistics
44  *
45  * Revision 3.11 to 3.15  2001/10/11 20:26:04  daniela
46  * More DMA fixes for noisy lines.
47  * Return the size of bad frames in dma_get_rx_frame_size, so that the Rx buffer
48  * descriptors can be cleaned by dma_buf_read (called in cpc_net_rx).
49  * Renamed dma_start routine to rx_dma_start. Improved Rx statistics.
50  * Fixed BOF interrupt treatment. Created dma_start routine.
51  * Changed min and max to cpc_min and cpc_max.
52  *
53  * Revision 3.10  2001/08/06 12:01:51  regina
54  * Fixed problem in DSR_DE bit.
55  *
56  * Revision 3.9  2001/07/18 19:27:26  daniela
57  * Added some history comments.
58  *
59  * Revision 3.8  2001/07/12 13:11:19  regina
60  * bug fix - DCD-OFF in pc300 tty driver
61  *
62  * Revision 3.3 to 3.7  2001/07/06 15:00:20  daniela
63  * Removing kernel 2.4.3 and previous support.
64  * DMA transmission bug fix.
65  * MTU check in cpc_net_rx fixed.
66  * Boot messages reviewed.
67  * New configuration parameters (line code, CRC calculation and clock).
68  *
69  * Revision 3.2 2001/06/22 13:13:02  regina
70  * MLPPP implementation. Changed the header of message trace to include
71  * the device name. New format : "hdlcX[R/T]: ".
72  * Default configuration changed.
73  *
74  * Revision 3.1 2001/06/15 regina
75  * in cpc_queue_xmit, netif_stop_queue is called if don't have free descriptor
76  * upping major version number
77  *
78  * Revision 1.1.1.1  2001/06/13 20:25:04  daniela
79  * PC300 initial CVS version (3.4.0-pre1)
80  *
81  * Revision 3.0.1.2 2001/06/08 daniela
82  * Did some changes in the DMA programming implementation to avoid the 
83  * occurrence of a SCA-II bug when CDA is accessed during a DMA transfer.
84  *
85  * Revision 3.0.1.1 2001/05/02 daniela
86  * Added kernel 2.4.3 support.
87  * 
88  * Revision 3.0.1.0 2001/03/13 daniela, henrique
89  * Added Frame Relay Support.
90  * Driver now uses HDLC generic driver to provide protocol support.
91  * 
92  * Revision 3.0.0.8 2001/03/02 daniela
93  * Fixed ram size detection. 
94  * Changed SIOCGPC300CONF ioctl, to give hw information to pc300util.
95  * 
96  * Revision 3.0.0.7 2001/02/23 daniela
97  * netif_stop_queue called before the SCA-II transmition commands in 
98  * cpc_queue_xmit, and with interrupts disabled to avoid race conditions with 
99  * transmition interrupts.
100  * Fixed falc_check_status for Unframed E1.
101  * 
102  * Revision 3.0.0.6 2000/12/13 daniela
103  * Implemented pc300util support: trace, statistics, status and loopback
104  * tests for the PC300 TE boards.
105  * 
106  * Revision 3.0.0.5 2000/12/12 ivan
107  * Added support for Unframed E1.
108  * Implemented monitor mode.
109  * Fixed DCD sensitivity on the second channel.
110  * Driver now complies with new PCI kernel architecture.
111  *
112  * Revision 3.0.0.4 2000/09/28 ivan
113  * Implemented DCD sensitivity.
114  * Moved hardware-specific open to the end of cpc_open, to avoid race
115  * conditions with early reception interrupts.
116  * Included code for [request|release]_mem_region().
117  * Changed location of pc300.h .
118  * Minor code revision (contrib. of Jeff Garzik).
119  *
120  * Revision 3.0.0.3 2000/07/03 ivan
121  * Previous bugfix for the framing errors with external clock made X21
122  * boards stop working. This version fixes it.
123  *
124  * Revision 3.0.0.2 2000/06/23 ivan
125  * Revisited cpc_queue_xmit to prevent race conditions on Tx DMA buffer
126  * handling when Tx timeouts occur.
127  * Revisited Rx statistics.
128  * Fixed a bug in the SCA-II programming that would cause framing errors
129  * when external clock was configured.
130  *
131  * Revision 3.0.0.1 2000/05/26 ivan
132  * Added logic in the SCA interrupt handler so that no board can monopolize
133  * the driver.
134  * Request PLX I/O region, although driver doesn't use it, to avoid
135  * problems with other drivers accessing it.
136  *
137  * Revision 3.0.0.0 2000/05/15 ivan
138  * Did some changes in the DMA programming implementation to avoid the
139  * occurrence of a SCA-II bug in the second channel.
140  * Implemented workaround for PLX9050 bug that would cause a system lockup
141  * in certain systems, depending on the MMIO addresses allocated to the
142  * board.
143  * Fixed the FALC chip programming to avoid synchronization problems in the
144  * second channel (TE only).
145  * Implemented a cleaner and faster Tx DMA descriptor cleanup procedure in
146  * cpc_queue_xmit().
147  * Changed the built-in driver implementation so that the driver can use the
148  * general 'hdlcN' naming convention instead of proprietary device names.
149  * Driver load messages are now device-centric, instead of board-centric.
150  * Dynamic allocation of net_device structures.
151  * Code is now compliant with the new module interface (module_[init|exit]).
152  * Make use of the PCI helper functions to access PCI resources.
153  *
154  * Revision 2.0.0.0 2000/04/15 ivan
155  * Added support for the PC300/TE boards (T1/FT1/E1/FE1).
156  *
157  * Revision 1.1.0.0 2000/02/28 ivan
158  * Major changes in the driver architecture.
159  * Softnet compliancy implemented.
160  * Driver now reports physical instead of virtual memory addresses.
161  * Added cpc_change_mtu function.
162  *
163  * Revision 1.0.0.0 1999/12/16 ivan
164  * First official release.
165  * Support for 1- and 2-channel boards (which use distinct PCI Device ID's).
166  * Support for monolythic installation (i.e., drv built into the kernel).
167  * X.25 additional checking when lapb_[dis]connect_request returns an error.
168  * SCA programming now covers X.21 as well.
169  *
170  * Revision 0.3.1.0 1999/11/18 ivan
171  * Made X.25 support configuration-dependent (as it depends on external 
172  * modules to work).
173  * Changed X.25-specific function names to comply with adopted convention.
174  * Fixed typos in X.25 functions that would cause compile errors (Daniela).
175  * Fixed bug in ch_config that would disable interrupts on a previously 
176  * enabled channel if the other channel on the same board was enabled later.
177  *
178  * Revision 0.3.0.0 1999/11/16 daniela
179  * X.25 support.
180  *
181  * Revision 0.2.3.0 1999/11/15 ivan
182  * Function cpc_ch_status now provides more detailed information.
183  * Added support for X.21 clock configuration.
184  * Changed TNR1 setting in order to prevent Tx FIFO overaccesses by the SCA.
185  * Now using PCI clock instead of internal oscillator clock for the SCA.
186  *
187  * Revision 0.2.2.0 1999/11/10 ivan
188  * Changed the *_dma_buf_check functions so that they would print only 
189  * the useful info instead of the whole buffer descriptor bank.
190  * Fixed bug in cpc_queue_xmit that would eventually crash the system 
191  * in case of a packet drop.
192  * Implemented TX underrun handling.
193  * Improved SCA fine tuning to boost up its performance.
194  *
195  * Revision 0.2.1.0 1999/11/03 ivan
196  * Added functions *dma_buf_pt_init to allow independent initialization 
197  * of the next-descr. and DMA buffer pointers on the DMA descriptors.
198  * Kernel buffer release and tbusy clearing is now done in the interrupt 
199  * handler.
200  * Fixed bug in cpc_open that would cause an interface reopen to fail.
201  * Added a protocol-specific code section in cpc_net_rx.
202  * Removed printk level defs (they might be added back after the beta phase).
203  *
204  * Revision 0.2.0.0 1999/10/28 ivan
205  * Revisited the code so that new protocols can be easily added / supported. 
206  *
207  * Revision 0.1.0.1 1999/10/20 ivan
208  * Mostly "esthetic" changes.
209  *
210  * Revision 0.1.0.0 1999/10/11 ivan
211  * Initial version.
212  *
213  */
214
215 #include <linux/module.h>
216 #include <linux/kernel.h>
217 #include <linux/mm.h>
218 #include <linux/ioport.h>
219 #include <linux/pci.h>
220 #include <linux/errno.h>
221 #include <linux/string.h>
222 #include <linux/init.h>
223 #include <linux/delay.h>
224 #include <linux/net.h>
225 #include <linux/skbuff.h>
226 #include <linux/if_arp.h>
227 #include <linux/netdevice.h>
228 #include <linux/spinlock.h>
229 #include <linux/if.h>
230
231 #include <net/syncppp.h>
232 #include <net/arp.h>
233
234 #include <asm/io.h>
235 #include <asm/uaccess.h>
236
237 #include "pc300.h"
238
239 #define CPC_LOCK(card,flags)            \
240                 do {                                            \
241                 spin_lock_irqsave(&card->card_lock, flags);     \
242                 } while (0)
243
244 #define CPC_UNLOCK(card,flags)                  \
245                 do {                                                    \
246                 spin_unlock_irqrestore(&card->card_lock, flags);        \
247                 } while (0)
248
249 #undef  PC300_DEBUG_PCI
250 #undef  PC300_DEBUG_INTR
251 #undef  PC300_DEBUG_TX
252 #undef  PC300_DEBUG_RX
253 #undef  PC300_DEBUG_OTHER
254
255 static struct pci_device_id cpc_pci_dev_id[] __devinitdata = {
256         /* PC300/RSV or PC300/X21, 2 chan */
257         {0x120e, 0x300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x300},
258         /* PC300/RSV or PC300/X21, 1 chan */
259         {0x120e, 0x301, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x301},
260         /* PC300/TE, 2 chan */
261         {0x120e, 0x310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x310},
262         /* PC300/TE, 1 chan */
263         {0x120e, 0x311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x311},
264         /* PC300/TE-M, 2 chan */
265         {0x120e, 0x320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x320},
266         /* PC300/TE-M, 1 chan */
267         {0x120e, 0x321, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x321},
268         /* End of table */
269         {0,},
270 };
271 MODULE_DEVICE_TABLE(pci, cpc_pci_dev_id);
272
273 #ifndef cpc_min
274 #define cpc_min(a,b)    (((a)<(b))?(a):(b))
275 #endif
276 #ifndef cpc_max
277 #define cpc_max(a,b)    (((a)>(b))?(a):(b))
278 #endif
279
280 /* prototypes */
281 static void tx_dma_buf_pt_init(pc300_t *, int);
282 static void tx_dma_buf_init(pc300_t *, int);
283 static void rx_dma_buf_pt_init(pc300_t *, int);
284 static void rx_dma_buf_init(pc300_t *, int);
285 static void tx_dma_buf_check(pc300_t *, int);
286 static void rx_dma_buf_check(pc300_t *, int);
287 static irqreturn_t cpc_intr(int, void *);
288 static struct net_device_stats *cpc_get_stats(struct net_device *);
289 static int clock_rate_calc(uclong, uclong, int *);
290 static uclong detect_ram(pc300_t *);
291 static void plx_init(pc300_t *);
292 static void cpc_trace(struct net_device *, struct sk_buff *, char);
293 static int cpc_attach(struct net_device *, unsigned short, unsigned short);
294 static int cpc_close(struct net_device *dev);
295
296 #ifdef CONFIG_PC300_MLPPP
297 void cpc_tty_init(pc300dev_t * dev);
298 void cpc_tty_unregister_service(pc300dev_t * pc300dev);
299 void cpc_tty_receive(pc300dev_t * pc300dev);
300 void cpc_tty_trigger_poll(pc300dev_t * pc300dev);
301 void cpc_tty_reset_var(void);
302 #endif
303
304 /************************/
305 /***   DMA Routines   ***/
306 /************************/
307 static void tx_dma_buf_pt_init(pc300_t * card, int ch)
308 {
309         int i;
310         int ch_factor = ch * N_DMA_TX_BUF;
311         volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
312                                        + DMA_TX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
313
314         for (i = 0; i < N_DMA_TX_BUF; i++, ptdescr++) {
315                 cpc_writel(&ptdescr->next, (uclong) (DMA_TX_BD_BASE +
316                         (ch_factor + ((i + 1) & (N_DMA_TX_BUF - 1))) * sizeof(pcsca_bd_t)));
317                 cpc_writel(&ptdescr->ptbuf, 
318                                                 (uclong) (DMA_TX_BASE + (ch_factor + i) * BD_DEF_LEN));
319         }
320 }
321
322 static void tx_dma_buf_init(pc300_t * card, int ch)
323 {
324         int i;
325         int ch_factor = ch * N_DMA_TX_BUF;
326         volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
327                                + DMA_TX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
328
329         for (i = 0; i < N_DMA_TX_BUF; i++, ptdescr++) {
330                 memset_io(ptdescr, 0, sizeof(pcsca_bd_t));
331                 cpc_writew(&ptdescr->len, 0);
332                 cpc_writeb(&ptdescr->status, DST_OSB);
333         }
334         tx_dma_buf_pt_init(card, ch);
335 }
336
337 static void rx_dma_buf_pt_init(pc300_t * card, int ch)
338 {
339         int i;
340         int ch_factor = ch * N_DMA_RX_BUF;
341         volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
342                                        + DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
343
344         for (i = 0; i < N_DMA_RX_BUF; i++, ptdescr++) {
345                 cpc_writel(&ptdescr->next, (uclong) (DMA_RX_BD_BASE +
346                 (ch_factor + ((i + 1) & (N_DMA_RX_BUF - 1))) * sizeof(pcsca_bd_t)));
347                 cpc_writel(&ptdescr->ptbuf,
348                            (uclong) (DMA_RX_BASE + (ch_factor + i) * BD_DEF_LEN));
349         }
350 }
351
352 static void rx_dma_buf_init(pc300_t * card, int ch)
353 {
354         int i;
355         int ch_factor = ch * N_DMA_RX_BUF;
356         volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
357                                        + DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
358
359         for (i = 0; i < N_DMA_RX_BUF; i++, ptdescr++) {
360                 memset_io(ptdescr, 0, sizeof(pcsca_bd_t));
361                 cpc_writew(&ptdescr->len, 0);
362                 cpc_writeb(&ptdescr->status, 0);
363         }
364         rx_dma_buf_pt_init(card, ch);
365 }
366
367 static void tx_dma_buf_check(pc300_t * card, int ch)
368 {
369         volatile pcsca_bd_t __iomem *ptdescr;
370         int i;
371         ucshort first_bd = card->chan[ch].tx_first_bd;
372         ucshort next_bd = card->chan[ch].tx_next_bd;
373
374         printk("#CH%d: f_bd = %d(0x%08zx), n_bd = %d(0x%08zx)\n", ch,
375                first_bd, TX_BD_ADDR(ch, first_bd),
376                next_bd, TX_BD_ADDR(ch, next_bd));
377         for (i = first_bd,
378              ptdescr = (card->hw.rambase + TX_BD_ADDR(ch, first_bd));
379              i != ((next_bd + 1) & (N_DMA_TX_BUF - 1));
380              i = (i + 1) & (N_DMA_TX_BUF - 1), 
381                  ptdescr = (card->hw.rambase + TX_BD_ADDR(ch, i))) {
382                 printk("\n CH%d TX%d: next=0x%x, ptbuf=0x%x, ST=0x%x, len=%d",
383                        ch, i, cpc_readl(&ptdescr->next),
384                        cpc_readl(&ptdescr->ptbuf),
385                        cpc_readb(&ptdescr->status), cpc_readw(&ptdescr->len));
386         }
387         printk("\n");
388 }
389
390 #ifdef  PC300_DEBUG_OTHER
391 /* Show all TX buffer descriptors */
392 static void tx1_dma_buf_check(pc300_t * card, int ch)
393 {
394         volatile pcsca_bd_t __iomem *ptdescr;
395         int i;
396         ucshort first_bd = card->chan[ch].tx_first_bd;
397         ucshort next_bd = card->chan[ch].tx_next_bd;
398         uclong scabase = card->hw.scabase;
399
400         printk ("\nnfree_tx_bd = %d \n", card->chan[ch].nfree_tx_bd);
401         printk("#CH%d: f_bd = %d(0x%08x), n_bd = %d(0x%08x)\n", ch,
402                first_bd, TX_BD_ADDR(ch, first_bd),
403                next_bd, TX_BD_ADDR(ch, next_bd));
404         printk("TX_CDA=0x%08x, TX_EDA=0x%08x\n",
405                cpc_readl(scabase + DTX_REG(CDAL, ch)),
406                cpc_readl(scabase + DTX_REG(EDAL, ch)));
407         for (i = 0; i < N_DMA_TX_BUF; i++) {
408                 ptdescr = (card->hw.rambase + TX_BD_ADDR(ch, i));
409                 printk("\n CH%d TX%d: next=0x%x, ptbuf=0x%x, ST=0x%x, len=%d",
410                        ch, i, cpc_readl(&ptdescr->next),
411                        cpc_readl(&ptdescr->ptbuf),
412                        cpc_readb(&ptdescr->status), cpc_readw(&ptdescr->len));
413         }
414         printk("\n");
415 }
416 #endif
417                          
418 static void rx_dma_buf_check(pc300_t * card, int ch)
419 {
420         volatile pcsca_bd_t __iomem *ptdescr;
421         int i;
422         ucshort first_bd = card->chan[ch].rx_first_bd;
423         ucshort last_bd = card->chan[ch].rx_last_bd;
424         int ch_factor;
425
426         ch_factor = ch * N_DMA_RX_BUF;
427         printk("#CH%d: f_bd = %d, l_bd = %d\n", ch, first_bd, last_bd);
428         for (i = 0, ptdescr = (card->hw.rambase +
429                                               DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
430              i < N_DMA_RX_BUF; i++, ptdescr++) {
431                 if (cpc_readb(&ptdescr->status) & DST_OSB)
432                         printk ("\n CH%d RX%d: next=0x%x, ptbuf=0x%x, ST=0x%x, len=%d",
433                                  ch, i, cpc_readl(&ptdescr->next),
434                                  cpc_readl(&ptdescr->ptbuf),
435                                  cpc_readb(&ptdescr->status),
436                                  cpc_readw(&ptdescr->len));
437         }
438         printk("\n");
439 }
440
441 static int dma_get_rx_frame_size(pc300_t * card, int ch)
442 {
443         volatile pcsca_bd_t __iomem *ptdescr;
444         ucshort first_bd = card->chan[ch].rx_first_bd;
445         int rcvd = 0;
446         volatile ucchar status;
447
448         ptdescr = (card->hw.rambase + RX_BD_ADDR(ch, first_bd));
449         while ((status = cpc_readb(&ptdescr->status)) & DST_OSB) {
450                 rcvd += cpc_readw(&ptdescr->len);
451                 first_bd = (first_bd + 1) & (N_DMA_RX_BUF - 1);
452                 if ((status & DST_EOM) || (first_bd == card->chan[ch].rx_last_bd)) {
453                         /* Return the size of a good frame or incomplete bad frame 
454                         * (dma_buf_read will clean the buffer descriptors in this case). */
455                         return (rcvd);
456                 }
457                 ptdescr = (card->hw.rambase + cpc_readl(&ptdescr->next));
458         }
459         return (-1);
460 }
461
462 /*
463  * dma_buf_write: writes a frame to the Tx DMA buffers
464  * NOTE: this function writes one frame at a time.
465  */
466 static int dma_buf_write(pc300_t * card, int ch, ucchar * ptdata, int len)
467 {
468         int i, nchar;
469         volatile pcsca_bd_t __iomem *ptdescr;
470         int tosend = len;
471         ucchar nbuf = ((len - 1) / BD_DEF_LEN) + 1;
472
473         if (nbuf >= card->chan[ch].nfree_tx_bd) {
474                 return -ENOMEM;
475         }
476
477         for (i = 0; i < nbuf; i++) {
478                 ptdescr = (card->hw.rambase +
479                                           TX_BD_ADDR(ch, card->chan[ch].tx_next_bd));
480                 nchar = cpc_min(BD_DEF_LEN, tosend);
481                 if (cpc_readb(&ptdescr->status) & DST_OSB) {
482                         memcpy_toio((card->hw.rambase + cpc_readl(&ptdescr->ptbuf)),
483                                     &ptdata[len - tosend], nchar);
484                         cpc_writew(&ptdescr->len, nchar);
485                         card->chan[ch].nfree_tx_bd--;
486                         if ((i + 1) == nbuf) {
487                                 /* This must be the last BD to be used */
488                                 cpc_writeb(&ptdescr->status, DST_EOM);
489                         } else {
490                                 cpc_writeb(&ptdescr->status, 0);
491                         }
492                 } else {
493                         return -ENOMEM;
494                 }
495                 tosend -= nchar;
496                 card->chan[ch].tx_next_bd =
497                         (card->chan[ch].tx_next_bd + 1) & (N_DMA_TX_BUF - 1);
498         }
499         /* If it gets to here, it means we have sent the whole frame */
500         return 0;
501 }
502
503 /*
504  * dma_buf_read: reads a frame from the Rx DMA buffers
505  * NOTE: this function reads one frame at a time.
506  */
507 static int dma_buf_read(pc300_t * card, int ch, struct sk_buff *skb)
508 {
509         int nchar;
510         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
511         volatile pcsca_bd_t __iomem *ptdescr;
512         int rcvd = 0;
513         volatile ucchar status;
514
515         ptdescr = (card->hw.rambase +
516                                   RX_BD_ADDR(ch, chan->rx_first_bd));
517         while ((status = cpc_readb(&ptdescr->status)) & DST_OSB) {
518                 nchar = cpc_readw(&ptdescr->len);
519                 if ((status & (DST_OVR | DST_CRC | DST_RBIT | DST_SHRT | DST_ABT))
520                     || (nchar > BD_DEF_LEN)) {
521
522                         if (nchar > BD_DEF_LEN)
523                                 status |= DST_RBIT;
524                         rcvd = -status;
525                         /* Discard remaining descriptors used by the bad frame */
526                         while (chan->rx_first_bd != chan->rx_last_bd) {
527                                 cpc_writeb(&ptdescr->status, 0);
528                                 chan->rx_first_bd = (chan->rx_first_bd+1) & (N_DMA_RX_BUF-1);
529                                 if (status & DST_EOM)
530                                         break;
531                                 ptdescr = (card->hw.rambase +
532                                                           cpc_readl(&ptdescr->next));
533                                 status = cpc_readb(&ptdescr->status);
534                         }
535                         break;
536                 }
537                 if (nchar != 0) {
538                         if (skb) {
539                                 memcpy_fromio(skb_put(skb, nchar),
540                                  (card->hw.rambase+cpc_readl(&ptdescr->ptbuf)),nchar);
541                         }
542                         rcvd += nchar;
543                 }
544                 cpc_writeb(&ptdescr->status, 0);
545                 cpc_writeb(&ptdescr->len, 0);
546                 chan->rx_first_bd = (chan->rx_first_bd + 1) & (N_DMA_RX_BUF - 1);
547
548                 if (status & DST_EOM)
549                         break;
550
551                 ptdescr = (card->hw.rambase + cpc_readl(&ptdescr->next));
552         }
553
554         if (rcvd != 0) {
555                 /* Update pointer */
556                 chan->rx_last_bd = (chan->rx_first_bd - 1) & (N_DMA_RX_BUF - 1);
557                 /* Update EDA */
558                 cpc_writel(card->hw.scabase + DRX_REG(EDAL, ch),
559                            RX_BD_ADDR(ch, chan->rx_last_bd));
560         }
561         return (rcvd);
562 }
563
564 static void tx_dma_stop(pc300_t * card, int ch)
565 {
566         void __iomem *scabase = card->hw.scabase;
567         ucchar drr_ena_bit = 1 << (5 + 2 * ch);
568         ucchar drr_rst_bit = 1 << (1 + 2 * ch);
569
570         /* Disable DMA */
571         cpc_writeb(scabase + DRR, drr_ena_bit);
572         cpc_writeb(scabase + DRR, drr_rst_bit & ~drr_ena_bit);
573 }
574
575 static void rx_dma_stop(pc300_t * card, int ch)
576 {
577         void __iomem *scabase = card->hw.scabase;
578         ucchar drr_ena_bit = 1 << (4 + 2 * ch);
579         ucchar drr_rst_bit = 1 << (2 * ch);
580
581         /* Disable DMA */
582         cpc_writeb(scabase + DRR, drr_ena_bit);
583         cpc_writeb(scabase + DRR, drr_rst_bit & ~drr_ena_bit);
584 }
585
586 static void rx_dma_start(pc300_t * card, int ch)
587 {
588         void __iomem *scabase = card->hw.scabase;
589         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
590         
591         /* Start DMA */
592         cpc_writel(scabase + DRX_REG(CDAL, ch),
593                    RX_BD_ADDR(ch, chan->rx_first_bd));
594         if (cpc_readl(scabase + DRX_REG(CDAL,ch)) !=
595                                   RX_BD_ADDR(ch, chan->rx_first_bd)) {
596                 cpc_writel(scabase + DRX_REG(CDAL, ch),
597                                    RX_BD_ADDR(ch, chan->rx_first_bd));
598         }
599         cpc_writel(scabase + DRX_REG(EDAL, ch),
600                    RX_BD_ADDR(ch, chan->rx_last_bd));
601         cpc_writew(scabase + DRX_REG(BFLL, ch), BD_DEF_LEN);
602         cpc_writeb(scabase + DSR_RX(ch), DSR_DE);
603         if (!(cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
604         cpc_writeb(scabase + DSR_RX(ch), DSR_DE);
605         }
606 }
607
608 /*************************/
609 /***   FALC Routines   ***/
610 /*************************/
611 static void falc_issue_cmd(pc300_t * card, int ch, ucchar cmd)
612 {
613         void __iomem *falcbase = card->hw.falcbase;
614         unsigned long i = 0;
615
616         while (cpc_readb(falcbase + F_REG(SIS, ch)) & SIS_CEC) {
617                 if (i++ >= PC300_FALC_MAXLOOP) {
618                         printk("%s: FALC command locked(cmd=0x%x).\n",
619                                card->chan[ch].d.name, cmd);
620                         break;
621                 }
622         }
623         cpc_writeb(falcbase + F_REG(CMDR, ch), cmd);
624 }
625
626 static void falc_intr_enable(pc300_t * card, int ch)
627 {
628         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
629         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
630         falc_t *pfalc = (falc_t *) & chan->falc;
631         void __iomem *falcbase = card->hw.falcbase;
632
633         /* Interrupt pins are open-drain */
634         cpc_writeb(falcbase + F_REG(IPC, ch),
635                    cpc_readb(falcbase + F_REG(IPC, ch)) & ~IPC_IC0);
636         /* Conters updated each second */
637         cpc_writeb(falcbase + F_REG(FMR1, ch),
638                    cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_ECM);
639         /* Enable SEC and ES interrupts  */
640         cpc_writeb(falcbase + F_REG(IMR3, ch),
641                    cpc_readb(falcbase + F_REG(IMR3, ch)) & ~(IMR3_SEC | IMR3_ES));
642         if (conf->fr_mode == PC300_FR_UNFRAMED) {
643                 cpc_writeb(falcbase + F_REG(IMR4, ch),
644                            cpc_readb(falcbase + F_REG(IMR4, ch)) & ~(IMR4_LOS));
645         } else {
646                 cpc_writeb(falcbase + F_REG(IMR4, ch),
647                            cpc_readb(falcbase + F_REG(IMR4, ch)) &
648                            ~(IMR4_LFA | IMR4_AIS | IMR4_LOS | IMR4_SLIP));
649         }
650         if (conf->media == IF_IFACE_T1) {
651                 cpc_writeb(falcbase + F_REG(IMR3, ch),
652                            cpc_readb(falcbase + F_REG(IMR3, ch)) & ~IMR3_LLBSC);
653         } else {
654                 cpc_writeb(falcbase + F_REG(IPC, ch),
655                            cpc_readb(falcbase + F_REG(IPC, ch)) | IPC_SCI);
656                 if (conf->fr_mode == PC300_FR_UNFRAMED) {
657                         cpc_writeb(falcbase + F_REG(IMR2, ch),
658                                    cpc_readb(falcbase + F_REG(IMR2, ch)) & ~(IMR2_LOS));
659                 } else {
660                         cpc_writeb(falcbase + F_REG(IMR2, ch),
661                                    cpc_readb(falcbase + F_REG(IMR2, ch)) &
662                                    ~(IMR2_FAR | IMR2_LFA | IMR2_AIS | IMR2_LOS));
663                         if (pfalc->multiframe_mode) {
664                                 cpc_writeb(falcbase + F_REG(IMR2, ch),
665                                            cpc_readb(falcbase + F_REG(IMR2, ch)) & 
666                                            ~(IMR2_T400MS | IMR2_MFAR));
667                         } else {
668                                 cpc_writeb(falcbase + F_REG(IMR2, ch),
669                                            cpc_readb(falcbase + F_REG(IMR2, ch)) | 
670                                            IMR2_T400MS | IMR2_MFAR);
671                         }
672                 }
673         }
674 }
675
676 static void falc_open_timeslot(pc300_t * card, int ch, int timeslot)
677 {
678         void __iomem *falcbase = card->hw.falcbase;
679         ucchar tshf = card->chan[ch].falc.offset;
680
681         cpc_writeb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch),
682                    cpc_readb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch)) & 
683                         ~(0x80 >> ((timeslot - tshf) & 0x07)));
684         cpc_writeb(falcbase + F_REG((TTR1 + timeslot / 8), ch),
685                    cpc_readb(falcbase + F_REG((TTR1 + timeslot / 8), ch)) | 
686                         (0x80 >> (timeslot & 0x07)));
687         cpc_writeb(falcbase + F_REG((RTR1 + timeslot / 8), ch),
688                    cpc_readb(falcbase + F_REG((RTR1 + timeslot / 8), ch)) | 
689                         (0x80 >> (timeslot & 0x07)));
690 }
691
692 static void falc_close_timeslot(pc300_t * card, int ch, int timeslot)
693 {
694         void __iomem *falcbase = card->hw.falcbase;
695         ucchar tshf = card->chan[ch].falc.offset;
696
697         cpc_writeb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch),
698                    cpc_readb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch)) | 
699                    (0x80 >> ((timeslot - tshf) & 0x07)));
700         cpc_writeb(falcbase + F_REG((TTR1 + timeslot / 8), ch),
701                    cpc_readb(falcbase + F_REG((TTR1 + timeslot / 8), ch)) & 
702                    ~(0x80 >> (timeslot & 0x07)));
703         cpc_writeb(falcbase + F_REG((RTR1 + timeslot / 8), ch),
704                    cpc_readb(falcbase + F_REG((RTR1 + timeslot / 8), ch)) & 
705                    ~(0x80 >> (timeslot & 0x07)));
706 }
707
708 static void falc_close_all_timeslots(pc300_t * card, int ch)
709 {
710         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
711         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
712         void __iomem *falcbase = card->hw.falcbase;
713
714         cpc_writeb(falcbase + F_REG(ICB1, ch), 0xff);
715         cpc_writeb(falcbase + F_REG(TTR1, ch), 0);
716         cpc_writeb(falcbase + F_REG(RTR1, ch), 0);
717         cpc_writeb(falcbase + F_REG(ICB2, ch), 0xff);
718         cpc_writeb(falcbase + F_REG(TTR2, ch), 0);
719         cpc_writeb(falcbase + F_REG(RTR2, ch), 0);
720         cpc_writeb(falcbase + F_REG(ICB3, ch), 0xff);
721         cpc_writeb(falcbase + F_REG(TTR3, ch), 0);
722         cpc_writeb(falcbase + F_REG(RTR3, ch), 0);
723         if (conf->media == IF_IFACE_E1) {
724                 cpc_writeb(falcbase + F_REG(ICB4, ch), 0xff);
725                 cpc_writeb(falcbase + F_REG(TTR4, ch), 0);
726                 cpc_writeb(falcbase + F_REG(RTR4, ch), 0);
727         }
728 }
729
730 static void falc_open_all_timeslots(pc300_t * card, int ch)
731 {
732         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
733         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
734         void __iomem *falcbase = card->hw.falcbase;
735
736         cpc_writeb(falcbase + F_REG(ICB1, ch), 0);
737         if (conf->fr_mode == PC300_FR_UNFRAMED) {
738                 cpc_writeb(falcbase + F_REG(TTR1, ch), 0xff);
739                 cpc_writeb(falcbase + F_REG(RTR1, ch), 0xff);
740         } else {
741                 /* Timeslot 0 is never enabled */
742                 cpc_writeb(falcbase + F_REG(TTR1, ch), 0x7f);
743                 cpc_writeb(falcbase + F_REG(RTR1, ch), 0x7f);
744         }
745         cpc_writeb(falcbase + F_REG(ICB2, ch), 0);
746         cpc_writeb(falcbase + F_REG(TTR2, ch), 0xff);
747         cpc_writeb(falcbase + F_REG(RTR2, ch), 0xff);
748         cpc_writeb(falcbase + F_REG(ICB3, ch), 0);
749         cpc_writeb(falcbase + F_REG(TTR3, ch), 0xff);
750         cpc_writeb(falcbase + F_REG(RTR3, ch), 0xff);
751         if (conf->media == IF_IFACE_E1) {
752                 cpc_writeb(falcbase + F_REG(ICB4, ch), 0);
753                 cpc_writeb(falcbase + F_REG(TTR4, ch), 0xff);
754                 cpc_writeb(falcbase + F_REG(RTR4, ch), 0xff);
755         } else {
756                 cpc_writeb(falcbase + F_REG(ICB4, ch), 0xff);
757                 cpc_writeb(falcbase + F_REG(TTR4, ch), 0x80);
758                 cpc_writeb(falcbase + F_REG(RTR4, ch), 0x80);
759         }
760 }
761
762 static void falc_init_timeslot(pc300_t * card, int ch)
763 {
764         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
765         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
766         falc_t *pfalc = (falc_t *) & chan->falc;
767         int tslot;
768
769         for (tslot = 0; tslot < pfalc->num_channels; tslot++) {
770                 if (conf->tslot_bitmap & (1 << tslot)) {
771                         // Channel enabled
772                         falc_open_timeslot(card, ch, tslot + 1);
773                 } else {
774                         // Channel disabled
775                         falc_close_timeslot(card, ch, tslot + 1);
776                 }
777         }
778 }
779
780 static void falc_enable_comm(pc300_t * card, int ch)
781 {
782         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
783         falc_t *pfalc = (falc_t *) & chan->falc;
784
785         if (pfalc->full_bandwidth) {
786                 falc_open_all_timeslots(card, ch);
787         } else {
788                 falc_init_timeslot(card, ch);
789         }
790         // CTS/DCD ON
791         cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
792                    cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) &
793                    ~((CPLD_REG1_FALC_DCD | CPLD_REG1_FALC_CTS) << (2 * ch)));
794 }
795
796 static void falc_disable_comm(pc300_t * card, int ch)
797 {
798         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
799         falc_t *pfalc = (falc_t *) & chan->falc;
800
801         if (pfalc->loop_active != 2) {
802                 falc_close_all_timeslots(card, ch);
803         }
804         // CTS/DCD OFF
805         cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
806                    cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
807                    ((CPLD_REG1_FALC_DCD | CPLD_REG1_FALC_CTS) << (2 * ch)));
808 }
809
810 static void falc_init_t1(pc300_t * card, int ch)
811 {
812         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
813         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
814         falc_t *pfalc = (falc_t *) & chan->falc;
815         void __iomem *falcbase = card->hw.falcbase;
816         ucchar dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0);
817
818         /* Switch to T1 mode (PCM 24) */
819         cpc_writeb(falcbase + F_REG(FMR1, ch), FMR1_PMOD);
820
821         /* Wait 20 us for setup */
822         udelay(20);
823
824         /* Transmit Buffer Size (1 frame) */
825         cpc_writeb(falcbase + F_REG(SIC1, ch), SIC1_XBS0);
826
827         /* Clock mode */
828         if (conf->phys_settings.clock_type == CLOCK_INT) { /* Master mode */
829                 cpc_writeb(falcbase + F_REG(LIM0, ch),
830                            cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_MAS);
831         } else { /* Slave mode */
832                 cpc_writeb(falcbase + F_REG(LIM0, ch),
833                            cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_MAS);
834                 cpc_writeb(falcbase + F_REG(LOOP, ch),
835                            cpc_readb(falcbase + F_REG(LOOP, ch)) & ~LOOP_RTM);
836         }
837
838         cpc_writeb(falcbase + F_REG(IPC, ch), IPC_SCI);
839         cpc_writeb(falcbase + F_REG(FMR0, ch),
840                    cpc_readb(falcbase + F_REG(FMR0, ch)) &
841                    ~(FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1));
842
843         switch (conf->lcode) {
844                 case PC300_LC_AMI:
845                         cpc_writeb(falcbase + F_REG(FMR0, ch),
846                                    cpc_readb(falcbase + F_REG(FMR0, ch)) |
847                                    FMR0_XC1 | FMR0_RC1);
848                         /* Clear Channel register to ON for all channels */
849                         cpc_writeb(falcbase + F_REG(CCB1, ch), 0xff);
850                         cpc_writeb(falcbase + F_REG(CCB2, ch), 0xff);
851                         cpc_writeb(falcbase + F_REG(CCB3, ch), 0xff);
852                         break;
853
854                 case PC300_LC_B8ZS:
855                         cpc_writeb(falcbase + F_REG(FMR0, ch),
856                                    cpc_readb(falcbase + F_REG(FMR0, ch)) |
857                                    FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1);
858                         break;
859
860                 case PC300_LC_NRZ:
861                         cpc_writeb(falcbase + F_REG(FMR0, ch),
862                                    cpc_readb(falcbase + F_REG(FMR0, ch)) | 0x00);
863                         break;
864         }
865
866         cpc_writeb(falcbase + F_REG(LIM0, ch),
867                    cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_ELOS);
868         cpc_writeb(falcbase + F_REG(LIM0, ch),
869                    cpc_readb(falcbase + F_REG(LIM0, ch)) & ~(LIM0_SCL1 | LIM0_SCL0));
870         /* Set interface mode to 2 MBPS */
871         cpc_writeb(falcbase + F_REG(FMR1, ch),
872                    cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_IMOD);
873
874         switch (conf->fr_mode) {
875                 case PC300_FR_ESF:
876                         pfalc->multiframe_mode = 0;
877                         cpc_writeb(falcbase + F_REG(FMR4, ch),
878                                    cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_FM1);
879                         cpc_writeb(falcbase + F_REG(FMR1, ch),
880                                    cpc_readb(falcbase + F_REG(FMR1, ch)) | 
881                                    FMR1_CRC | FMR1_EDL);
882                         cpc_writeb(falcbase + F_REG(XDL1, ch), 0);
883                         cpc_writeb(falcbase + F_REG(XDL2, ch), 0);
884                         cpc_writeb(falcbase + F_REG(XDL3, ch), 0);
885                         cpc_writeb(falcbase + F_REG(FMR0, ch),
886                                    cpc_readb(falcbase + F_REG(FMR0, ch)) & ~FMR0_SRAF);
887                         cpc_writeb(falcbase + F_REG(FMR2, ch),
888                                    cpc_readb(falcbase + F_REG(FMR2,ch)) | FMR2_MCSP | FMR2_SSP);
889                         break;
890
891                 case PC300_FR_D4:
892                         pfalc->multiframe_mode = 1;
893                         cpc_writeb(falcbase + F_REG(FMR4, ch),
894                                    cpc_readb(falcbase + F_REG(FMR4, ch)) &
895                                    ~(FMR4_FM1 | FMR4_FM0));
896                         cpc_writeb(falcbase + F_REG(FMR0, ch),
897                                    cpc_readb(falcbase + F_REG(FMR0, ch)) | FMR0_SRAF);
898                         cpc_writeb(falcbase + F_REG(FMR2, ch),
899                                    cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_SSP);
900                         break;
901         }
902
903         /* Enable Automatic Resynchronization */
904         cpc_writeb(falcbase + F_REG(FMR4, ch),
905                    cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_AUTO);
906
907         /* Transmit Automatic Remote Alarm */
908         cpc_writeb(falcbase + F_REG(FMR2, ch),
909                    cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);
910
911         /* Channel translation mode 1 : one to one */
912         cpc_writeb(falcbase + F_REG(FMR1, ch),
913                    cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_CTM);
914
915         /* No signaling */
916         cpc_writeb(falcbase + F_REG(FMR1, ch),
917                    cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_SIGM);
918         cpc_writeb(falcbase + F_REG(FMR5, ch),
919                    cpc_readb(falcbase + F_REG(FMR5, ch)) &
920                    ~(FMR5_EIBR | FMR5_SRS));
921         cpc_writeb(falcbase + F_REG(CCR1, ch), 0);
922
923         cpc_writeb(falcbase + F_REG(LIM1, ch),
924                    cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RIL0 | LIM1_RIL1);
925
926         switch (conf->lbo) {
927                         /* Provides proper Line Build Out */
928                 case PC300_LBO_0_DB:
929                         cpc_writeb(falcbase + F_REG(LIM2, ch), (LIM2_LOS1 | dja));
930                         cpc_writeb(falcbase + F_REG(XPM0, ch), 0x5a);
931                         cpc_writeb(falcbase + F_REG(XPM1, ch), 0x8f);
932                         cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
933                         break;
934                 case PC300_LBO_7_5_DB:
935                         cpc_writeb(falcbase + F_REG(LIM2, ch), (0x40 | LIM2_LOS1 | dja));
936                         cpc_writeb(falcbase + F_REG(XPM0, ch), 0x11);
937                         cpc_writeb(falcbase + F_REG(XPM1, ch), 0x02);
938                         cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
939                         break;
940                 case PC300_LBO_15_DB:
941                         cpc_writeb(falcbase + F_REG(LIM2, ch), (0x80 | LIM2_LOS1 | dja));
942                         cpc_writeb(falcbase + F_REG(XPM0, ch), 0x8e);
943                         cpc_writeb(falcbase + F_REG(XPM1, ch), 0x01);
944                         cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
945                         break;
946                 case PC300_LBO_22_5_DB:
947                         cpc_writeb(falcbase + F_REG(LIM2, ch), (0xc0 | LIM2_LOS1 | dja));
948                         cpc_writeb(falcbase + F_REG(XPM0, ch), 0x09);
949                         cpc_writeb(falcbase + F_REG(XPM1, ch), 0x01);
950                         cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
951                         break;
952         }
953
954         /* Transmit Clock-Slot Offset */
955         cpc_writeb(falcbase + F_REG(XC0, ch),
956                    cpc_readb(falcbase + F_REG(XC0, ch)) | 0x01);
957         /* Transmit Time-slot Offset */
958         cpc_writeb(falcbase + F_REG(XC1, ch), 0x3e);
959         /* Receive  Clock-Slot offset */
960         cpc_writeb(falcbase + F_REG(RC0, ch), 0x05);
961         /* Receive  Time-slot offset */
962         cpc_writeb(falcbase + F_REG(RC1, ch), 0x00);
963
964         /* LOS Detection after 176 consecutive 0s */
965         cpc_writeb(falcbase + F_REG(PCDR, ch), 0x0a);
966         /* LOS Recovery after 22 ones in the time window of PCD */
967         cpc_writeb(falcbase + F_REG(PCRR, ch), 0x15);
968
969         cpc_writeb(falcbase + F_REG(IDLE, ch), 0x7f);
970
971         if (conf->fr_mode == PC300_FR_ESF_JAPAN) {
972                 cpc_writeb(falcbase + F_REG(RC1, ch),
973                            cpc_readb(falcbase + F_REG(RC1, ch)) | 0x80);
974         }
975
976         falc_close_all_timeslots(card, ch);
977 }
978
979 static void falc_init_e1(pc300_t * card, int ch)
980 {
981         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
982         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
983         falc_t *pfalc = (falc_t *) & chan->falc;
984         void __iomem *falcbase = card->hw.falcbase;
985         ucchar dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0);
986
987         /* Switch to E1 mode (PCM 30) */
988         cpc_writeb(falcbase + F_REG(FMR1, ch),
989                    cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_PMOD);
990
991         /* Clock mode */
992         if (conf->phys_settings.clock_type == CLOCK_INT) { /* Master mode */
993                 cpc_writeb(falcbase + F_REG(LIM0, ch),
994                            cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_MAS);
995         } else { /* Slave mode */
996                 cpc_writeb(falcbase + F_REG(LIM0, ch),
997                            cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_MAS);
998         }
999         cpc_writeb(falcbase + F_REG(LOOP, ch),
1000                    cpc_readb(falcbase + F_REG(LOOP, ch)) & ~LOOP_SFM);
1001
1002         cpc_writeb(falcbase + F_REG(IPC, ch), IPC_SCI);
1003         cpc_writeb(falcbase + F_REG(FMR0, ch),
1004                    cpc_readb(falcbase + F_REG(FMR0, ch)) &
1005                    ~(FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1));
1006
1007         switch (conf->lcode) {
1008                 case PC300_LC_AMI:
1009                         cpc_writeb(falcbase + F_REG(FMR0, ch),
1010                                    cpc_readb(falcbase + F_REG(FMR0, ch)) |
1011                                    FMR0_XC1 | FMR0_RC1);
1012                         break;
1013
1014                 case PC300_LC_HDB3:
1015                         cpc_writeb(falcbase + F_REG(FMR0, ch),
1016                                    cpc_readb(falcbase + F_REG(FMR0, ch)) |
1017                                    FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1);
1018                         break;
1019
1020                 case PC300_LC_NRZ:
1021                         break;
1022         }
1023
1024         cpc_writeb(falcbase + F_REG(LIM0, ch),
1025                    cpc_readb(falcbase + F_REG(LIM0, ch)) & ~(LIM0_SCL1 | LIM0_SCL0));
1026         /* Set interface mode to 2 MBPS */
1027         cpc_writeb(falcbase + F_REG(FMR1, ch),
1028                    cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_IMOD);
1029
1030         cpc_writeb(falcbase + F_REG(XPM0, ch), 0x18);
1031         cpc_writeb(falcbase + F_REG(XPM1, ch), 0x03);
1032         cpc_writeb(falcbase + F_REG(XPM2, ch), 0x00);
1033
1034         switch (conf->fr_mode) {
1035                 case PC300_FR_MF_CRC4:
1036                         pfalc->multiframe_mode = 1;
1037                         cpc_writeb(falcbase + F_REG(FMR1, ch),
1038                                    cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_XFS);
1039                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1040                                    cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_RFS1);
1041                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1042                                    cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_RFS0);
1043                         cpc_writeb(falcbase + F_REG(FMR3, ch),
1044                                    cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_EXTIW);
1045
1046                         /* MultiFrame Resynchronization */
1047                         cpc_writeb(falcbase + F_REG(FMR1, ch),
1048                                    cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_MFCS);
1049
1050                         /* Automatic Loss of Multiframe > 914 CRC errors */
1051                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1052                                    cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_ALMF);
1053
1054                         /* S1 and SI1/SI2 spare Bits set to 1 */
1055                         cpc_writeb(falcbase + F_REG(XSP, ch),
1056                                    cpc_readb(falcbase + F_REG(XSP, ch)) & ~XSP_AXS);
1057                         cpc_writeb(falcbase + F_REG(XSP, ch),
1058                                    cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_EBP);
1059                         cpc_writeb(falcbase + F_REG(XSP, ch),
1060                                    cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_XS13 | XSP_XS15);
1061
1062                         /* Automatic Force Resynchronization */
1063                         cpc_writeb(falcbase + F_REG(FMR1, ch),
1064                                    cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_AFR);
1065
1066                         /* Transmit Automatic Remote Alarm */
1067                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1068                                    cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);
1069
1070                         /* Transmit Spare Bits for National Use (Y, Sn, Sa) */
1071                         cpc_writeb(falcbase + F_REG(XSW, ch),
1072                                    cpc_readb(falcbase + F_REG(XSW, ch)) |
1073                                    XSW_XY0 | XSW_XY1 | XSW_XY2 | XSW_XY3 | XSW_XY4);
1074                         break;
1075
1076                 case PC300_FR_MF_NON_CRC4:
1077                 case PC300_FR_D4:
1078                         pfalc->multiframe_mode = 0;
1079                         cpc_writeb(falcbase + F_REG(FMR1, ch),
1080                                    cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_XFS);
1081                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1082                                    cpc_readb(falcbase + F_REG(FMR2, ch)) & 
1083                                    ~(FMR2_RFS1 | FMR2_RFS0));
1084                         cpc_writeb(falcbase + F_REG(XSW, ch),
1085                                    cpc_readb(falcbase + F_REG(XSW, ch)) | XSW_XSIS);
1086                         cpc_writeb(falcbase + F_REG(XSP, ch),
1087                                    cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_XSIF);
1088
1089                         /* Automatic Force Resynchronization */
1090                         cpc_writeb(falcbase + F_REG(FMR1, ch),
1091                                    cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_AFR);
1092
1093                         /* Transmit Automatic Remote Alarm */
1094                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1095                                    cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);
1096
1097                         /* Transmit Spare Bits for National Use (Y, Sn, Sa) */
1098                         cpc_writeb(falcbase + F_REG(XSW, ch),
1099                                    cpc_readb(falcbase + F_REG(XSW, ch)) |
1100                                    XSW_XY0 | XSW_XY1 | XSW_XY2 | XSW_XY3 | XSW_XY4);
1101                         break;
1102
1103                 case PC300_FR_UNFRAMED:
1104                         pfalc->multiframe_mode = 0;
1105                         cpc_writeb(falcbase + F_REG(FMR1, ch),
1106                                    cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_XFS);
1107                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1108                                    cpc_readb(falcbase + F_REG(FMR2, ch)) & 
1109                                    ~(FMR2_RFS1 | FMR2_RFS0));
1110                         cpc_writeb(falcbase + F_REG(XSP, ch),
1111                                    cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_TT0);
1112                         cpc_writeb(falcbase + F_REG(XSW, ch),
1113                                    cpc_readb(falcbase + F_REG(XSW, ch)) & 
1114                                    ~(XSW_XTM|XSW_XY0|XSW_XY1|XSW_XY2|XSW_XY3|XSW_XY4));
1115                         cpc_writeb(falcbase + F_REG(TSWM, ch), 0xff);
1116                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1117                                    cpc_readb(falcbase + F_REG(FMR2, ch)) |
1118                                    (FMR2_RTM | FMR2_DAIS));
1119                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1120                                    cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_AXRA);
1121                         cpc_writeb(falcbase + F_REG(FMR1, ch),
1122                                    cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_AFR);
1123                         pfalc->sync = 1;
1124                         cpc_writeb(falcbase + card->hw.cpld_reg2,
1125                                    cpc_readb(falcbase + card->hw.cpld_reg2) |
1126                                    (CPLD_REG2_FALC_LED2 << (2 * ch)));
1127                         break;
1128         }
1129
1130         /* No signaling */
1131         cpc_writeb(falcbase + F_REG(XSP, ch),
1132                    cpc_readb(falcbase + F_REG(XSP, ch)) & ~XSP_CASEN);
1133         cpc_writeb(falcbase + F_REG(CCR1, ch), 0);
1134
1135         cpc_writeb(falcbase + F_REG(LIM1, ch),
1136                    cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RIL0 | LIM1_RIL1);
1137         cpc_writeb(falcbase + F_REG(LIM2, ch), (LIM2_LOS1 | dja));
1138
1139         /* Transmit Clock-Slot Offset */
1140         cpc_writeb(falcbase + F_REG(XC0, ch),
1141                    cpc_readb(falcbase + F_REG(XC0, ch)) | 0x01);
1142         /* Transmit Time-slot Offset */
1143         cpc_writeb(falcbase + F_REG(XC1, ch), 0x3e);
1144         /* Receive  Clock-Slot offset */
1145         cpc_writeb(falcbase + F_REG(RC0, ch), 0x05);
1146         /* Receive  Time-slot offset */
1147         cpc_writeb(falcbase + F_REG(RC1, ch), 0x00);
1148
1149         /* LOS Detection after 176 consecutive 0s */
1150         cpc_writeb(falcbase + F_REG(PCDR, ch), 0x0a);
1151         /* LOS Recovery after 22 ones in the time window of PCD */
1152         cpc_writeb(falcbase + F_REG(PCRR, ch), 0x15);
1153
1154         cpc_writeb(falcbase + F_REG(IDLE, ch), 0x7f);
1155
1156         falc_close_all_timeslots(card, ch);
1157 }
1158
1159 static void falc_init_hdlc(pc300_t * card, int ch)
1160 {
1161         void __iomem *falcbase = card->hw.falcbase;
1162         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1163         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1164
1165         /* Enable transparent data transfer */
1166         if (conf->fr_mode == PC300_FR_UNFRAMED) {
1167                 cpc_writeb(falcbase + F_REG(MODE, ch), 0);
1168         } else {
1169                 cpc_writeb(falcbase + F_REG(MODE, ch),
1170                            cpc_readb(falcbase + F_REG(MODE, ch)) |
1171                            (MODE_HRAC | MODE_MDS2));
1172                 cpc_writeb(falcbase + F_REG(RAH2, ch), 0xff);
1173                 cpc_writeb(falcbase + F_REG(RAH1, ch), 0xff);
1174                 cpc_writeb(falcbase + F_REG(RAL2, ch), 0xff);
1175                 cpc_writeb(falcbase + F_REG(RAL1, ch), 0xff);
1176         }
1177
1178         /* Tx/Rx reset  */
1179         falc_issue_cmd(card, ch, CMDR_RRES | CMDR_XRES | CMDR_SRES);
1180
1181         /* Enable interrupt sources */
1182         falc_intr_enable(card, ch);
1183 }
1184
1185 static void te_config(pc300_t * card, int ch)
1186 {
1187         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1188         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1189         falc_t *pfalc = (falc_t *) & chan->falc;
1190         void __iomem *falcbase = card->hw.falcbase;
1191         ucchar dummy;
1192         unsigned long flags;
1193
1194         memset(pfalc, 0, sizeof(falc_t));
1195         switch (conf->media) {
1196                 case IF_IFACE_T1:
1197                         pfalc->num_channels = NUM_OF_T1_CHANNELS;
1198                         pfalc->offset = 1;
1199                         break;
1200                 case IF_IFACE_E1:
1201                         pfalc->num_channels = NUM_OF_E1_CHANNELS;
1202                         pfalc->offset = 0;
1203                         break;
1204         }
1205         if (conf->tslot_bitmap == 0xffffffffUL)
1206                 pfalc->full_bandwidth = 1;
1207         else
1208                 pfalc->full_bandwidth = 0;
1209
1210         CPC_LOCK(card, flags);
1211         /* Reset the FALC chip */
1212         cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
1213                    cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
1214                    (CPLD_REG1_FALC_RESET << (2 * ch)));
1215         udelay(10000);
1216         cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
1217                    cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) &
1218                    ~(CPLD_REG1_FALC_RESET << (2 * ch)));
1219
1220         if (conf->media == IF_IFACE_T1) {
1221                 falc_init_t1(card, ch);
1222         } else {
1223                 falc_init_e1(card, ch);
1224         }
1225         falc_init_hdlc(card, ch);
1226         if (conf->rx_sens == PC300_RX_SENS_SH) {
1227                 cpc_writeb(falcbase + F_REG(LIM0, ch),
1228                            cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_EQON);
1229         } else {
1230                 cpc_writeb(falcbase + F_REG(LIM0, ch),
1231                            cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_EQON);
1232         }
1233         cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1234                    cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) |
1235                    ((CPLD_REG2_FALC_TX_CLK | CPLD_REG2_FALC_RX_CLK) << (2 * ch)));
1236
1237         /* Clear all interrupt registers */
1238         dummy = cpc_readb(falcbase + F_REG(FISR0, ch)) +
1239                 cpc_readb(falcbase + F_REG(FISR1, ch)) +
1240                 cpc_readb(falcbase + F_REG(FISR2, ch)) +
1241                 cpc_readb(falcbase + F_REG(FISR3, ch));
1242         CPC_UNLOCK(card, flags);
1243 }
1244
1245 static void falc_check_status(pc300_t * card, int ch, unsigned char frs0)
1246 {
1247         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1248         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1249         falc_t *pfalc = (falc_t *) & chan->falc;
1250         void __iomem *falcbase = card->hw.falcbase;
1251
1252         /* Verify LOS */
1253         if (frs0 & FRS0_LOS) {
1254                 if (!pfalc->red_alarm) {
1255                         pfalc->red_alarm = 1;
1256                         pfalc->los++;
1257                         if (!pfalc->blue_alarm) {
1258                                 // EVENT_FALC_ABNORMAL
1259                                 if (conf->media == IF_IFACE_T1) {
1260                                         /* Disable this interrupt as it may otherwise interfere 
1261                                          * with other working boards. */
1262                                         cpc_writeb(falcbase + F_REG(IMR0, ch), 
1263                                                    cpc_readb(falcbase + F_REG(IMR0, ch))
1264                                                    | IMR0_PDEN);
1265                                 }
1266                                 falc_disable_comm(card, ch);
1267                                 // EVENT_FALC_ABNORMAL
1268                         }
1269                 }
1270         } else {
1271                 if (pfalc->red_alarm) {
1272                         pfalc->red_alarm = 0;
1273                         pfalc->losr++;
1274                 }
1275         }
1276
1277         if (conf->fr_mode != PC300_FR_UNFRAMED) {
1278                 /* Verify AIS alarm */
1279                 if (frs0 & FRS0_AIS) {
1280                         if (!pfalc->blue_alarm) {
1281                                 pfalc->blue_alarm = 1;
1282                                 pfalc->ais++;
1283                                 // EVENT_AIS
1284                                 if (conf->media == IF_IFACE_T1) {
1285                                         /* Disable this interrupt as it may otherwise interfere with                       other working boards. */
1286                                         cpc_writeb(falcbase + F_REG(IMR0, ch),
1287                                                    cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1288                                 }
1289                                 falc_disable_comm(card, ch);
1290                                 // EVENT_AIS
1291                         }
1292                 } else {
1293                         pfalc->blue_alarm = 0;
1294                 }
1295
1296                 /* Verify LFA */
1297                 if (frs0 & FRS0_LFA) {
1298                         if (!pfalc->loss_fa) {
1299                                 pfalc->loss_fa = 1;
1300                                 pfalc->lfa++;
1301                                 if (!pfalc->blue_alarm && !pfalc->red_alarm) {
1302                                         // EVENT_FALC_ABNORMAL
1303                                         if (conf->media == IF_IFACE_T1) {
1304                                                 /* Disable this interrupt as it may otherwise 
1305                                                  * interfere with other working boards. */
1306                                                 cpc_writeb(falcbase + F_REG(IMR0, ch),
1307                                                            cpc_readb(falcbase + F_REG(IMR0, ch))
1308                                                            | IMR0_PDEN);
1309                                         }
1310                                         falc_disable_comm(card, ch);
1311                                         // EVENT_FALC_ABNORMAL
1312                                 }
1313                         }
1314                 } else {
1315                         if (pfalc->loss_fa) {
1316                                 pfalc->loss_fa = 0;
1317                                 pfalc->farec++;
1318                         }
1319                 }
1320
1321                 /* Verify LMFA */
1322                 if (pfalc->multiframe_mode && (frs0 & FRS0_LMFA)) {
1323                         /* D4 or CRC4 frame mode */
1324                         if (!pfalc->loss_mfa) {
1325                                 pfalc->loss_mfa = 1;
1326                                 pfalc->lmfa++;
1327                                 if (!pfalc->blue_alarm && !pfalc->red_alarm &&
1328                                     !pfalc->loss_fa) {
1329                                         // EVENT_FALC_ABNORMAL
1330                                         if (conf->media == IF_IFACE_T1) {
1331                                                 /* Disable this interrupt as it may otherwise 
1332                                                  * interfere with other working boards. */
1333                                                 cpc_writeb(falcbase + F_REG(IMR0, ch),
1334                                                            cpc_readb(falcbase + F_REG(IMR0, ch))
1335                                                            | IMR0_PDEN);
1336                                         }
1337                                         falc_disable_comm(card, ch);
1338                                         // EVENT_FALC_ABNORMAL
1339                                 }
1340                         }
1341                 } else {
1342                         pfalc->loss_mfa = 0;
1343                 }
1344
1345                 /* Verify Remote Alarm */
1346                 if (frs0 & FRS0_RRA) {
1347                         if (!pfalc->yellow_alarm) {
1348                                 pfalc->yellow_alarm = 1;
1349                                 pfalc->rai++;
1350                                 if (pfalc->sync) {
1351                                         // EVENT_RAI
1352                                         falc_disable_comm(card, ch);
1353                                         // EVENT_RAI
1354                                 }
1355                         }
1356                 } else {
1357                         pfalc->yellow_alarm = 0;
1358                 }
1359         } /* if !PC300_UNFRAMED */
1360
1361         if (pfalc->red_alarm || pfalc->loss_fa ||
1362             pfalc->loss_mfa || pfalc->blue_alarm) {
1363                 if (pfalc->sync) {
1364                         pfalc->sync = 0;
1365                         chan->d.line_off++;
1366                         cpc_writeb(falcbase + card->hw.cpld_reg2,
1367                                    cpc_readb(falcbase + card->hw.cpld_reg2) &
1368                                    ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1369                 }
1370         } else {
1371                 if (!pfalc->sync) {
1372                         pfalc->sync = 1;
1373                         chan->d.line_on++;
1374                         cpc_writeb(falcbase + card->hw.cpld_reg2,
1375                                    cpc_readb(falcbase + card->hw.cpld_reg2) |
1376                                    (CPLD_REG2_FALC_LED2 << (2 * ch)));
1377                 }
1378         }
1379
1380         if (pfalc->sync && !pfalc->yellow_alarm) {
1381                 if (!pfalc->active) {
1382                         // EVENT_FALC_NORMAL
1383                         if (pfalc->loop_active) {
1384                                 return;
1385                         }
1386                         if (conf->media == IF_IFACE_T1) {
1387                                 cpc_writeb(falcbase + F_REG(IMR0, ch),
1388                                            cpc_readb(falcbase + F_REG(IMR0, ch)) & ~IMR0_PDEN);
1389                         }
1390                         falc_enable_comm(card, ch);
1391                         // EVENT_FALC_NORMAL
1392                         pfalc->active = 1;
1393                 }
1394         } else {
1395                 if (pfalc->active) {
1396                         pfalc->active = 0;
1397                 }
1398         }
1399 }
1400
1401 static void falc_update_stats(pc300_t * card, int ch)
1402 {
1403         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1404         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1405         falc_t *pfalc = (falc_t *) & chan->falc;
1406         void __iomem *falcbase = card->hw.falcbase;
1407         ucshort counter;
1408
1409         counter = cpc_readb(falcbase + F_REG(FECL, ch));
1410         counter |= cpc_readb(falcbase + F_REG(FECH, ch)) << 8;
1411         pfalc->fec += counter;
1412
1413         counter = cpc_readb(falcbase + F_REG(CVCL, ch));
1414         counter |= cpc_readb(falcbase + F_REG(CVCH, ch)) << 8;
1415         pfalc->cvc += counter;
1416
1417         counter = cpc_readb(falcbase + F_REG(CECL, ch));
1418         counter |= cpc_readb(falcbase + F_REG(CECH, ch)) << 8;
1419         pfalc->cec += counter;
1420
1421         counter = cpc_readb(falcbase + F_REG(EBCL, ch));
1422         counter |= cpc_readb(falcbase + F_REG(EBCH, ch)) << 8;
1423         pfalc->ebc += counter;
1424
1425         if (cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) {
1426                 mdelay(10);
1427                 counter = cpc_readb(falcbase + F_REG(BECL, ch));
1428                 counter |= cpc_readb(falcbase + F_REG(BECH, ch)) << 8;
1429                 pfalc->bec += counter;
1430
1431                 if (((conf->media == IF_IFACE_T1) &&
1432                      (cpc_readb(falcbase + F_REG(FRS1, ch)) & FRS1_LLBAD) &&
1433                      (!(cpc_readb(falcbase + F_REG(FRS1, ch)) & FRS1_PDEN)))
1434                     ||
1435                     ((conf->media == IF_IFACE_E1) &&
1436                      (cpc_readb(falcbase + F_REG(RSP, ch)) & RSP_LLBAD))) {
1437                         pfalc->prbs = 2;
1438                 } else {
1439                         pfalc->prbs = 1;
1440                 }
1441         }
1442 }
1443
1444 /*----------------------------------------------------------------------------
1445  * falc_remote_loop
1446  *----------------------------------------------------------------------------
1447  * Description: In the remote loopback mode the clock and data recovered
1448  *              from the line inputs RL1/2 or RDIP/RDIN are routed back
1449  *              to the line outputs XL1/2 or XDOP/XDON via the analog
1450  *              transmitter. As in normal mode they are processsed by
1451  *              the synchronizer and then sent to the system interface.
1452  *----------------------------------------------------------------------------
1453  */
1454 static void falc_remote_loop(pc300_t * card, int ch, int loop_on)
1455 {
1456         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1457         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1458         falc_t *pfalc = (falc_t *) & chan->falc;
1459         void __iomem *falcbase = card->hw.falcbase;
1460
1461         if (loop_on) {
1462                 // EVENT_FALC_ABNORMAL
1463                 if (conf->media == IF_IFACE_T1) {
1464                         /* Disable this interrupt as it may otherwise interfere with 
1465                          * other working boards. */
1466                         cpc_writeb(falcbase + F_REG(IMR0, ch),
1467                                    cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1468                 }
1469                 falc_disable_comm(card, ch);
1470                 // EVENT_FALC_ABNORMAL
1471                 cpc_writeb(falcbase + F_REG(LIM1, ch),
1472                            cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RL);
1473                 pfalc->loop_active = 1;
1474         } else {
1475                 cpc_writeb(falcbase + F_REG(LIM1, ch),
1476                            cpc_readb(falcbase + F_REG(LIM1, ch)) & ~LIM1_RL);
1477                 pfalc->sync = 0;
1478                 cpc_writeb(falcbase + card->hw.cpld_reg2,
1479                            cpc_readb(falcbase + card->hw.cpld_reg2) &
1480                            ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1481                 pfalc->active = 0;
1482                 falc_issue_cmd(card, ch, CMDR_XRES);
1483                 pfalc->loop_active = 0;
1484         }
1485 }
1486
1487 /*----------------------------------------------------------------------------
1488  * falc_local_loop
1489  *----------------------------------------------------------------------------
1490  * Description: The local loopback mode disconnects the receive lines 
1491  *              RL1/RL2 resp. RDIP/RDIN from the receiver. Instead of the
1492  *              signals coming from the line the data provided by system
1493  *              interface are routed through the analog receiver back to
1494  *              the system interface. The unipolar bit stream will be
1495  *              undisturbed transmitted on the line. Receiver and transmitter
1496  *              coding must be identical.
1497  *----------------------------------------------------------------------------
1498  */
1499 static void falc_local_loop(pc300_t * card, int ch, int loop_on)
1500 {
1501         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1502         falc_t *pfalc = (falc_t *) & chan->falc;
1503         void __iomem *falcbase = card->hw.falcbase;
1504
1505         if (loop_on) {
1506                 cpc_writeb(falcbase + F_REG(LIM0, ch),
1507                            cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_LL);
1508                 pfalc->loop_active = 1;
1509         } else {
1510                 cpc_writeb(falcbase + F_REG(LIM0, ch),
1511                            cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_LL);
1512                 pfalc->loop_active = 0;
1513         }
1514 }
1515
1516 /*----------------------------------------------------------------------------
1517  * falc_payload_loop
1518  *----------------------------------------------------------------------------
1519  * Description: This routine allows to enable/disable payload loopback.
1520  *              When the payload loop is activated, the received 192 bits
1521  *              of payload data will be looped back to the transmit
1522  *              direction. The framing bits, CRC6 and DL bits are not 
1523  *              looped. They are originated by the FALC-LH transmitter.
1524  *----------------------------------------------------------------------------
1525  */
1526 static void falc_payload_loop(pc300_t * card, int ch, int loop_on)
1527 {
1528         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1529         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1530         falc_t *pfalc = (falc_t *) & chan->falc;
1531         void __iomem *falcbase = card->hw.falcbase;
1532
1533         if (loop_on) {
1534                 // EVENT_FALC_ABNORMAL
1535                 if (conf->media == IF_IFACE_T1) {
1536                         /* Disable this interrupt as it may otherwise interfere with 
1537                          * other working boards. */
1538                         cpc_writeb(falcbase + F_REG(IMR0, ch),
1539                                    cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1540                 }
1541                 falc_disable_comm(card, ch);
1542                 // EVENT_FALC_ABNORMAL
1543                 cpc_writeb(falcbase + F_REG(FMR2, ch),
1544                            cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_PLB);
1545                 if (conf->media == IF_IFACE_T1) {
1546                         cpc_writeb(falcbase + F_REG(FMR4, ch),
1547                                    cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_TM);
1548                 } else {
1549                         cpc_writeb(falcbase + F_REG(FMR5, ch),
1550                                    cpc_readb(falcbase + F_REG(FMR5, ch)) | XSP_TT0);
1551                 }
1552                 falc_open_all_timeslots(card, ch);
1553                 pfalc->loop_active = 2;
1554         } else {
1555                 cpc_writeb(falcbase + F_REG(FMR2, ch),
1556                            cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_PLB);
1557                 if (conf->media == IF_IFACE_T1) {
1558                         cpc_writeb(falcbase + F_REG(FMR4, ch),
1559                                    cpc_readb(falcbase + F_REG(FMR4, ch)) & ~FMR4_TM);
1560                 } else {
1561                         cpc_writeb(falcbase + F_REG(FMR5, ch),
1562                                    cpc_readb(falcbase + F_REG(FMR5, ch)) & ~XSP_TT0);
1563                 }
1564                 pfalc->sync = 0;
1565                 cpc_writeb(falcbase + card->hw.cpld_reg2,
1566                            cpc_readb(falcbase + card->hw.cpld_reg2) &
1567                            ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1568                 pfalc->active = 0;
1569                 falc_issue_cmd(card, ch, CMDR_XRES);
1570                 pfalc->loop_active = 0;
1571         }
1572 }
1573
1574 /*----------------------------------------------------------------------------
1575  * turn_off_xlu
1576  *----------------------------------------------------------------------------
1577  * Description: Turns XLU bit off in the proper register
1578  *----------------------------------------------------------------------------
1579  */
1580 static void turn_off_xlu(pc300_t * card, int ch)
1581 {
1582         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1583         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1584         void __iomem *falcbase = card->hw.falcbase;
1585
1586         if (conf->media == IF_IFACE_T1) {
1587                 cpc_writeb(falcbase + F_REG(FMR5, ch),
1588                            cpc_readb(falcbase + F_REG(FMR5, ch)) & ~FMR5_XLU);
1589         } else {
1590                 cpc_writeb(falcbase + F_REG(FMR3, ch),
1591                            cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_XLU);
1592         }
1593 }
1594
1595 /*----------------------------------------------------------------------------
1596  * turn_off_xld
1597  *----------------------------------------------------------------------------
1598  * Description: Turns XLD bit off in the proper register
1599  *----------------------------------------------------------------------------
1600  */
1601 static void turn_off_xld(pc300_t * card, int ch)
1602 {
1603         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1604         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1605         void __iomem *falcbase = card->hw.falcbase;
1606
1607         if (conf->media == IF_IFACE_T1) {
1608                 cpc_writeb(falcbase + F_REG(FMR5, ch),
1609                            cpc_readb(falcbase + F_REG(FMR5, ch)) & ~FMR5_XLD);
1610         } else {
1611                 cpc_writeb(falcbase + F_REG(FMR3, ch),
1612                            cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_XLD);
1613         }
1614 }
1615
1616 /*----------------------------------------------------------------------------
1617  * falc_generate_loop_up_code
1618  *----------------------------------------------------------------------------
1619  * Description: This routine writes the proper FALC chip register in order
1620  *              to generate a LOOP activation code over a T1/E1 line.
1621  *----------------------------------------------------------------------------
1622  */
1623 static void falc_generate_loop_up_code(pc300_t * card, int ch)
1624 {
1625         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1626         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1627         falc_t *pfalc = (falc_t *) & chan->falc;
1628         void __iomem *falcbase = card->hw.falcbase;
1629
1630         if (conf->media == IF_IFACE_T1) {
1631                 cpc_writeb(falcbase + F_REG(FMR5, ch),
1632                            cpc_readb(falcbase + F_REG(FMR5, ch)) | FMR5_XLU);
1633         } else {
1634                 cpc_writeb(falcbase + F_REG(FMR3, ch),
1635                            cpc_readb(falcbase + F_REG(FMR3, ch)) | FMR3_XLU);
1636         }
1637         // EVENT_FALC_ABNORMAL
1638         if (conf->media == IF_IFACE_T1) {
1639                 /* Disable this interrupt as it may otherwise interfere with 
1640                  * other working boards. */
1641                 cpc_writeb(falcbase + F_REG(IMR0, ch),
1642                            cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1643         }
1644         falc_disable_comm(card, ch);
1645         // EVENT_FALC_ABNORMAL
1646         pfalc->loop_gen = 1;
1647 }
1648
1649 /*----------------------------------------------------------------------------
1650  * falc_generate_loop_down_code
1651  *----------------------------------------------------------------------------
1652  * Description: This routine writes the proper FALC chip register in order
1653  *              to generate a LOOP deactivation code over a T1/E1 line.
1654  *----------------------------------------------------------------------------
1655  */
1656 static void falc_generate_loop_down_code(pc300_t * card, int ch)
1657 {
1658         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1659         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1660         falc_t *pfalc = (falc_t *) & chan->falc;
1661         void __iomem *falcbase = card->hw.falcbase;
1662
1663         if (conf->media == IF_IFACE_T1) {
1664                 cpc_writeb(falcbase + F_REG(FMR5, ch),
1665                            cpc_readb(falcbase + F_REG(FMR5, ch)) | FMR5_XLD);
1666         } else {
1667                 cpc_writeb(falcbase + F_REG(FMR3, ch),
1668                            cpc_readb(falcbase + F_REG(FMR3, ch)) | FMR3_XLD);
1669         }
1670         pfalc->sync = 0;
1671         cpc_writeb(falcbase + card->hw.cpld_reg2,
1672                    cpc_readb(falcbase + card->hw.cpld_reg2) &
1673                    ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1674         pfalc->active = 0;
1675 //?    falc_issue_cmd(card, ch, CMDR_XRES);
1676         pfalc->loop_gen = 0;
1677 }
1678
1679 /*----------------------------------------------------------------------------
1680  * falc_pattern_test
1681  *----------------------------------------------------------------------------
1682  * Description: This routine generates a pattern code and checks
1683  *              it on the reception side.
1684  *----------------------------------------------------------------------------
1685  */
1686 static void falc_pattern_test(pc300_t * card, int ch, unsigned int activate)
1687 {
1688         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1689         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1690         falc_t *pfalc = (falc_t *) & chan->falc;
1691         void __iomem *falcbase = card->hw.falcbase;
1692
1693         if (activate) {
1694                 pfalc->prbs = 1;
1695                 pfalc->bec = 0;
1696                 if (conf->media == IF_IFACE_T1) {
1697                         /* Disable local loop activation/deactivation detect */
1698                         cpc_writeb(falcbase + F_REG(IMR3, ch),
1699                                    cpc_readb(falcbase + F_REG(IMR3, ch)) | IMR3_LLBSC);
1700                 } else {
1701                         /* Disable local loop activation/deactivation detect */
1702                         cpc_writeb(falcbase + F_REG(IMR1, ch),
1703                                    cpc_readb(falcbase + F_REG(IMR1, ch)) | IMR1_LLBSC);
1704                 }
1705                 /* Activates generation and monitoring of PRBS 
1706                  * (Pseudo Random Bit Sequence) */
1707                 cpc_writeb(falcbase + F_REG(LCR1, ch),
1708                            cpc_readb(falcbase + F_REG(LCR1, ch)) | LCR1_EPRM | LCR1_XPRBS);
1709         } else {
1710                 pfalc->prbs = 0;
1711                 /* Deactivates generation and monitoring of PRBS 
1712                  * (Pseudo Random Bit Sequence) */
1713                 cpc_writeb(falcbase + F_REG(LCR1, ch),
1714                            cpc_readb(falcbase+F_REG(LCR1,ch)) & ~(LCR1_EPRM | LCR1_XPRBS));
1715                 if (conf->media == IF_IFACE_T1) {
1716                         /* Enable local loop activation/deactivation detect */
1717                         cpc_writeb(falcbase + F_REG(IMR3, ch),
1718                                    cpc_readb(falcbase + F_REG(IMR3, ch)) & ~IMR3_LLBSC);
1719                 } else {
1720                         /* Enable local loop activation/deactivation detect */
1721                         cpc_writeb(falcbase + F_REG(IMR1, ch),
1722                                    cpc_readb(falcbase + F_REG(IMR1, ch)) & ~IMR1_LLBSC);
1723                 }
1724         }
1725 }
1726
1727 /*----------------------------------------------------------------------------
1728  * falc_pattern_test_error
1729  *----------------------------------------------------------------------------
1730  * Description: This routine returns the bit error counter value
1731  *----------------------------------------------------------------------------
1732  */
1733 static ucshort falc_pattern_test_error(pc300_t * card, int ch)
1734 {
1735         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1736         falc_t *pfalc = (falc_t *) & chan->falc;
1737
1738         return (pfalc->bec);
1739 }
1740
1741 /**********************************/
1742 /***   Net Interface Routines   ***/
1743 /**********************************/
1744
1745 static void
1746 cpc_trace(struct net_device *dev, struct sk_buff *skb_main, char rx_tx)
1747 {
1748         struct sk_buff *skb;
1749
1750         if ((skb = dev_alloc_skb(10 + skb_main->len)) == NULL) {
1751                 printk("%s: out of memory\n", dev->name);
1752                 return;
1753         }
1754         skb_put(skb, 10 + skb_main->len);
1755
1756         skb->dev = dev;
1757         skb->protocol = htons(ETH_P_CUST);
1758         skb_reset_mac_header(skb);
1759         skb->pkt_type = PACKET_HOST;
1760         skb->len = 10 + skb_main->len;
1761
1762         skb_copy_to_linear_data(skb, dev->name, 5);
1763         skb->data[5] = '[';
1764         skb->data[6] = rx_tx;
1765         skb->data[7] = ']';
1766         skb->data[8] = ':';
1767         skb->data[9] = ' ';
1768         skb_copy_from_linear_data(skb_main, &skb->data[10], skb_main->len);
1769
1770         netif_rx(skb);
1771 }
1772
1773 static void cpc_tx_timeout(struct net_device *dev)
1774 {
1775         pc300dev_t *d = (pc300dev_t *) dev->priv;
1776         pc300ch_t *chan = (pc300ch_t *) d->chan;
1777         pc300_t *card = (pc300_t *) chan->card;
1778         struct net_device_stats *stats = hdlc_stats(dev);
1779         int ch = chan->channel;
1780         unsigned long flags;
1781         ucchar ilar;
1782
1783         stats->tx_errors++;
1784         stats->tx_aborted_errors++;
1785         CPC_LOCK(card, flags);
1786         if ((ilar = cpc_readb(card->hw.scabase + ILAR)) != 0) {
1787                 printk("%s: ILAR=0x%x\n", dev->name, ilar);
1788                 cpc_writeb(card->hw.scabase + ILAR, ilar);
1789                 cpc_writeb(card->hw.scabase + DMER, 0x80);
1790         }
1791         if (card->hw.type == PC300_TE) {
1792                 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1793                            cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) &
1794                            ~(CPLD_REG2_FALC_LED1 << (2 * ch)));
1795         }
1796         dev->trans_start = jiffies;
1797         CPC_UNLOCK(card, flags);
1798         netif_wake_queue(dev);
1799 }
1800
1801 static int cpc_queue_xmit(struct sk_buff *skb, struct net_device *dev)
1802 {
1803         pc300dev_t *d = (pc300dev_t *) dev->priv;
1804         pc300ch_t *chan = (pc300ch_t *) d->chan;
1805         pc300_t *card = (pc300_t *) chan->card;
1806         struct net_device_stats *stats = hdlc_stats(dev);
1807         int ch = chan->channel;
1808         unsigned long flags;
1809 #ifdef PC300_DEBUG_TX
1810         int i;
1811 #endif
1812
1813         if (chan->conf.monitor) {
1814                 /* In monitor mode no Tx is done: ignore packet */
1815                 dev_kfree_skb(skb);
1816                 return 0;
1817         } else if (!netif_carrier_ok(dev)) {
1818                 /* DCD must be OFF: drop packet */
1819                 dev_kfree_skb(skb);
1820                 stats->tx_errors++;
1821                 stats->tx_carrier_errors++;
1822                 return 0;
1823         } else if (cpc_readb(card->hw.scabase + M_REG(ST3, ch)) & ST3_DCD) {
1824                 printk("%s: DCD is OFF. Going administrative down.\n", dev->name);
1825                 stats->tx_errors++;
1826                 stats->tx_carrier_errors++;
1827                 dev_kfree_skb(skb);
1828                 netif_carrier_off(dev);
1829                 CPC_LOCK(card, flags);
1830                 cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_TX_BUF_CLR);
1831                 if (card->hw.type == PC300_TE) {
1832                         cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1833                                    cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) & 
1834                                                         ~(CPLD_REG2_FALC_LED1 << (2 * ch)));
1835                 }
1836                 CPC_UNLOCK(card, flags);
1837                 netif_wake_queue(dev);
1838                 return 0;
1839         }
1840
1841         /* Write buffer to DMA buffers */
1842         if (dma_buf_write(card, ch, (ucchar *) skb->data, skb->len) != 0) {
1843 //              printk("%s: write error. Dropping TX packet.\n", dev->name);
1844                 netif_stop_queue(dev);
1845                 dev_kfree_skb(skb);
1846                 stats->tx_errors++;
1847                 stats->tx_dropped++;
1848                 return 0;
1849         }
1850 #ifdef PC300_DEBUG_TX
1851         printk("%s T:", dev->name);
1852         for (i = 0; i < skb->len; i++)
1853                 printk(" %02x", *(skb->data + i));
1854         printk("\n");
1855 #endif
1856
1857         if (d->trace_on) {
1858                 cpc_trace(dev, skb, 'T');
1859         }
1860         dev->trans_start = jiffies;
1861
1862         /* Start transmission */
1863         CPC_LOCK(card, flags);
1864         /* verify if it has more than one free descriptor */
1865         if (card->chan[ch].nfree_tx_bd <= 1) {
1866                 /* don't have so stop the queue */
1867                 netif_stop_queue(dev);
1868         }
1869         cpc_writel(card->hw.scabase + DTX_REG(EDAL, ch),
1870                    TX_BD_ADDR(ch, chan->tx_next_bd));
1871         cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_TX_ENA);
1872         cpc_writeb(card->hw.scabase + DSR_TX(ch), DSR_DE);
1873         if (card->hw.type == PC300_TE) {
1874                 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1875                            cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) |
1876                            (CPLD_REG2_FALC_LED1 << (2 * ch)));
1877         }
1878         CPC_UNLOCK(card, flags);
1879         dev_kfree_skb(skb);
1880
1881         return 0;
1882 }
1883
1884 static void cpc_net_rx(struct net_device *dev)
1885 {
1886         pc300dev_t *d = (pc300dev_t *) dev->priv;
1887         pc300ch_t *chan = (pc300ch_t *) d->chan;
1888         pc300_t *card = (pc300_t *) chan->card;
1889         struct net_device_stats *stats = hdlc_stats(dev);
1890         int ch = chan->channel;
1891 #ifdef PC300_DEBUG_RX
1892         int i;
1893 #endif
1894         int rxb;
1895         struct sk_buff *skb;
1896
1897         while (1) {
1898                 if ((rxb = dma_get_rx_frame_size(card, ch)) == -1)
1899                         return;
1900
1901                 if (!netif_carrier_ok(dev)) {
1902                         /* DCD must be OFF: drop packet */
1903                     printk("%s : DCD is OFF - drop %d rx bytes\n", dev->name, rxb); 
1904                         skb = NULL;
1905                 } else {
1906                         if (rxb > (dev->mtu + 40)) { /* add headers */
1907                                 printk("%s : MTU exceeded %d\n", dev->name, rxb); 
1908                                 skb = NULL;
1909                         } else {
1910                                 skb = dev_alloc_skb(rxb);
1911                                 if (skb == NULL) {
1912                                         printk("%s: Memory squeeze!!\n", dev->name);
1913                                         return;
1914                                 }
1915                                 skb->dev = dev;
1916                         }
1917                 }
1918
1919                 if (((rxb = dma_buf_read(card, ch, skb)) <= 0) || (skb == NULL)) {
1920 #ifdef PC300_DEBUG_RX
1921                         printk("%s: rxb = %x\n", dev->name, rxb);
1922 #endif
1923                         if ((skb == NULL) && (rxb > 0)) {
1924                                 /* rxb > dev->mtu */
1925                                 stats->rx_errors++;
1926                                 stats->rx_length_errors++;
1927                                 continue;
1928                         }
1929
1930                         if (rxb < 0) {  /* Invalid frame */
1931                                 rxb = -rxb;
1932                                 if (rxb & DST_OVR) {
1933                                         stats->rx_errors++;
1934                                         stats->rx_fifo_errors++;
1935                                 }
1936                                 if (rxb & DST_CRC) {
1937                                         stats->rx_errors++;
1938                                         stats->rx_crc_errors++;
1939                                 }
1940                                 if (rxb & (DST_RBIT | DST_SHRT | DST_ABT)) {
1941                                         stats->rx_errors++;
1942                                         stats->rx_frame_errors++;
1943                                 }
1944                         }
1945                         if (skb) {
1946                                 dev_kfree_skb_irq(skb);
1947                         }
1948                         continue;
1949                 }
1950
1951                 stats->rx_bytes += rxb;
1952
1953 #ifdef PC300_DEBUG_RX
1954                 printk("%s R:", dev->name);
1955                 for (i = 0; i < skb->len; i++)
1956                         printk(" %02x", *(skb->data + i));
1957                 printk("\n");
1958 #endif
1959                 if (d->trace_on) {
1960                         cpc_trace(dev, skb, 'R');
1961                 }
1962                 stats->rx_packets++;
1963                 skb->protocol = hdlc_type_trans(skb, dev);
1964                 netif_rx(skb);
1965         }
1966 }
1967
1968 /************************************/
1969 /***   PC300 Interrupt Routines   ***/
1970 /************************************/
1971 static void sca_tx_intr(pc300dev_t *dev)
1972 {
1973         pc300ch_t *chan = (pc300ch_t *)dev->chan; 
1974         pc300_t *card = (pc300_t *)chan->card; 
1975         int ch = chan->channel; 
1976         volatile pcsca_bd_t __iomem * ptdescr; 
1977         struct net_device_stats *stats = hdlc_stats(dev->dev);
1978
1979     /* Clean up descriptors from previous transmission */
1980         ptdescr = (card->hw.rambase +
1981                                                 TX_BD_ADDR(ch,chan->tx_first_bd));
1982         while ((cpc_readl(card->hw.scabase + DTX_REG(CDAL,ch)) != 
1983                                                         TX_BD_ADDR(ch,chan->tx_first_bd)) && 
1984                         (cpc_readb(&ptdescr->status) & DST_OSB)) {
1985                 stats->tx_packets++;
1986                 stats->tx_bytes += cpc_readw(&ptdescr->len);
1987                 cpc_writeb(&ptdescr->status, DST_OSB);
1988                 cpc_writew(&ptdescr->len, 0);
1989                 chan->nfree_tx_bd++;
1990                 chan->tx_first_bd = (chan->tx_first_bd + 1) & (N_DMA_TX_BUF - 1);
1991                 ptdescr = (card->hw.rambase + TX_BD_ADDR(ch,chan->tx_first_bd));
1992     }
1993
1994 #ifdef CONFIG_PC300_MLPPP
1995         if (chan->conf.proto == PC300_PROTO_MLPPP) {
1996                         cpc_tty_trigger_poll(dev);
1997         } else {
1998 #endif
1999         /* Tell the upper layer we are ready to transmit more packets */
2000                 netif_wake_queue(dev->dev);
2001 #ifdef CONFIG_PC300_MLPPP
2002         }
2003 #endif
2004 }
2005
2006 static void sca_intr(pc300_t * card)
2007 {
2008         void __iomem *scabase = card->hw.scabase;
2009         volatile uclong status;
2010         int ch;
2011         int intr_count = 0;
2012         unsigned char dsr_rx;
2013
2014         while ((status = cpc_readl(scabase + ISR0)) != 0) {
2015                 for (ch = 0; ch < card->hw.nchan; ch++) {
2016                         pc300ch_t *chan = &card->chan[ch];
2017                         pc300dev_t *d = &chan->d;
2018                         struct net_device *dev = d->dev;
2019
2020                         spin_lock(&card->card_lock);
2021
2022             /**** Reception ****/
2023                         if (status & IR0_DRX((IR0_DMIA | IR0_DMIB), ch)) {
2024                                 ucchar drx_stat = cpc_readb(scabase + DSR_RX(ch));
2025
2026                                 /* Clear RX interrupts */
2027                                 cpc_writeb(scabase + DSR_RX(ch), drx_stat | DSR_DWE);
2028
2029 #ifdef PC300_DEBUG_INTR
2030                                 printk ("sca_intr: RX intr chan[%d] (st=0x%08lx, dsr=0x%02x)\n",
2031                                          ch, status, drx_stat);
2032 #endif
2033                                 if (status & IR0_DRX(IR0_DMIA, ch)) {
2034                                         if (drx_stat & DSR_BOF) {
2035 #ifdef CONFIG_PC300_MLPPP
2036                                                 if (chan->conf.proto == PC300_PROTO_MLPPP) {
2037                                                         /* verify if driver is TTY */
2038                                                         if ((cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
2039                                                                 rx_dma_stop(card, ch);
2040                                                         }
2041                                                         cpc_tty_receive(d);
2042                                                         rx_dma_start(card, ch);
2043                                                 } else 
2044 #endif
2045                                                 {
2046                                                         if ((cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
2047                                                                 rx_dma_stop(card, ch);
2048                                                         }
2049                                                         cpc_net_rx(dev);
2050                                                         /* Discard invalid frames */
2051                                                         hdlc_stats(dev)->rx_errors++;
2052                                                         hdlc_stats(dev)->rx_over_errors++;
2053                                                         chan->rx_first_bd = 0;
2054                                                         chan->rx_last_bd = N_DMA_RX_BUF - 1;
2055                                                         rx_dma_start(card, ch);
2056                                                 }
2057                                         }
2058                                 }
2059                                 if (status & IR0_DRX(IR0_DMIB, ch)) {
2060                                         if (drx_stat & DSR_EOM) {
2061                                                 if (card->hw.type == PC300_TE) {
2062                                                         cpc_writeb(card->hw.falcbase +
2063                                                                    card->hw.cpld_reg2,
2064                                                                    cpc_readb (card->hw.falcbase +
2065                                                                         card->hw.cpld_reg2) |
2066                                                                    (CPLD_REG2_FALC_LED1 << (2 * ch)));
2067                                                 }
2068 #ifdef CONFIG_PC300_MLPPP
2069                                                 if (chan->conf.proto == PC300_PROTO_MLPPP) {
2070                                                         /* verify if driver is TTY */
2071                                                         cpc_tty_receive(d);
2072                                                 } else {
2073                                                         cpc_net_rx(dev);
2074                                                 }
2075 #else
2076                                                 cpc_net_rx(dev);
2077 #endif
2078                                                 if (card->hw.type == PC300_TE) {
2079                                                         cpc_writeb(card->hw.falcbase +
2080                                                                    card->hw.cpld_reg2,
2081                                                                    cpc_readb (card->hw.falcbase +
2082                                                                                 card->hw.cpld_reg2) &
2083                                                                    ~ (CPLD_REG2_FALC_LED1 << (2 * ch)));
2084                                                 }
2085                                         }
2086                                 }
2087                                 if (!(dsr_rx = cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
2088 #ifdef PC300_DEBUG_INTR
2089                 printk("%s: RX intr chan[%d] (st=0x%08lx, dsr=0x%02x, dsr2=0x%02x)\n",
2090                         dev->name, ch, status, drx_stat, dsr_rx);
2091 #endif
2092                                         cpc_writeb(scabase + DSR_RX(ch), (dsr_rx | DSR_DE) & 0xfe);
2093                                 }
2094                         }
2095
2096             /**** Transmission ****/
2097                         if (status & IR0_DTX((IR0_EFT | IR0_DMIA | IR0_DMIB), ch)) {
2098                                 ucchar dtx_stat = cpc_readb(scabase + DSR_TX(ch));
2099
2100                                 /* Clear TX interrupts */
2101                                 cpc_writeb(scabase + DSR_TX(ch), dtx_stat | DSR_DWE);
2102
2103 #ifdef PC300_DEBUG_INTR
2104                                 printk ("sca_intr: TX intr chan[%d] (st=0x%08lx, dsr=0x%02x)\n",
2105                                          ch, status, dtx_stat);
2106 #endif
2107                                 if (status & IR0_DTX(IR0_EFT, ch)) {
2108                                         if (dtx_stat & DSR_UDRF) {
2109                                                 if (cpc_readb (scabase + M_REG(TBN, ch)) != 0) {
2110                                                         cpc_writeb(scabase + M_REG(CMD,ch), CMD_TX_BUF_CLR);
2111                                                 }
2112                                                 if (card->hw.type == PC300_TE) {
2113                                                         cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
2114                                                                    cpc_readb (card->hw.falcbase + 
2115                                                                                    card->hw.cpld_reg2) &
2116                                                                    ~ (CPLD_REG2_FALC_LED1 << (2 * ch)));
2117                                                 }
2118                                                 hdlc_stats(dev)->tx_errors++;
2119                                                 hdlc_stats(dev)->tx_fifo_errors++;
2120                                                 sca_tx_intr(d);
2121                                         }
2122                                 }
2123                                 if (status & IR0_DTX(IR0_DMIA, ch)) {
2124                                         if (dtx_stat & DSR_BOF) {
2125                                         }
2126                                 }
2127                                 if (status & IR0_DTX(IR0_DMIB, ch)) {
2128                                         if (dtx_stat & DSR_EOM) {
2129                                                 if (card->hw.type == PC300_TE) {
2130                                                         cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
2131                                                                    cpc_readb (card->hw.falcbase +
2132                                                                                         card->hw.cpld_reg2) &
2133                                                                    ~ (CPLD_REG2_FALC_LED1 << (2 * ch)));
2134                                                 }
2135                                                 sca_tx_intr(d);
2136                                         }
2137                                 }
2138                         }
2139
2140             /**** MSCI ****/
2141                         if (status & IR0_M(IR0_RXINTA, ch)) {
2142                                 ucchar st1 = cpc_readb(scabase + M_REG(ST1, ch));
2143
2144                                 /* Clear MSCI interrupts */
2145                                 cpc_writeb(scabase + M_REG(ST1, ch), st1);
2146
2147 #ifdef PC300_DEBUG_INTR
2148                                 printk("sca_intr: MSCI intr chan[%d] (st=0x%08lx, st1=0x%02x)\n",
2149                                          ch, status, st1);
2150 #endif
2151                                 if (st1 & ST1_CDCD) {   /* DCD changed */
2152                                         if (cpc_readb(scabase + M_REG(ST3, ch)) & ST3_DCD) {
2153                                                 printk ("%s: DCD is OFF. Going administrative down.\n",
2154                                                          dev->name);
2155 #ifdef CONFIG_PC300_MLPPP
2156                                                 if (chan->conf.proto != PC300_PROTO_MLPPP) {
2157                                                         netif_carrier_off(dev);
2158                                                 }
2159 #else
2160                                                 netif_carrier_off(dev);
2161
2162 #endif
2163                                                 card->chan[ch].d.line_off++;
2164                                         } else {        /* DCD = 1 */
2165                                                 printk ("%s: DCD is ON. Going administrative up.\n",
2166                                                          dev->name);
2167 #ifdef CONFIG_PC300_MLPPP
2168                                                 if (chan->conf.proto != PC300_PROTO_MLPPP)
2169                                                         /* verify if driver is not TTY */
2170 #endif
2171                                                         netif_carrier_on(dev);
2172                                                 card->chan[ch].d.line_on++;
2173                                         }
2174                                 }
2175                         }
2176                         spin_unlock(&card->card_lock);
2177                 }
2178                 if (++intr_count == 10)
2179                         /* Too much work at this board. Force exit */
2180                         break;
2181         }
2182 }
2183
2184 static void falc_t1_loop_detection(pc300_t * card, int ch, ucchar frs1)
2185 {
2186         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2187         falc_t *pfalc = (falc_t *) & chan->falc;
2188         void __iomem *falcbase = card->hw.falcbase;
2189
2190         if (((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_XPRBS) == 0) &&
2191             !pfalc->loop_gen) {
2192                 if (frs1 & FRS1_LLBDD) {
2193                         // A Line Loop Back Deactivation signal detected
2194                         if (pfalc->loop_active) {
2195                                 falc_remote_loop(card, ch, 0);
2196                         }
2197                 } else {
2198                         if ((frs1 & FRS1_LLBAD) &&
2199                             ((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) == 0)) {
2200                                 // A Line Loop Back Activation signal detected  
2201                                 if (!pfalc->loop_active) {
2202                                         falc_remote_loop(card, ch, 1);
2203                                 }
2204                         }
2205                 }
2206         }
2207 }
2208
2209 static void falc_e1_loop_detection(pc300_t * card, int ch, ucchar rsp)
2210 {
2211         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2212         falc_t *pfalc = (falc_t *) & chan->falc;
2213         void __iomem *falcbase = card->hw.falcbase;
2214
2215         if (((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_XPRBS) == 0) &&
2216             !pfalc->loop_gen) {
2217                 if (rsp & RSP_LLBDD) {
2218                         // A Line Loop Back Deactivation signal detected
2219                         if (pfalc->loop_active) {
2220                                 falc_remote_loop(card, ch, 0);
2221                         }
2222                 } else {
2223                         if ((rsp & RSP_LLBAD) &&
2224                             ((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) == 0)) {
2225                                 // A Line Loop Back Activation signal detected  
2226                                 if (!pfalc->loop_active) {
2227                                         falc_remote_loop(card, ch, 1);
2228                                 }
2229                         }
2230                 }
2231         }
2232 }
2233
2234 static void falc_t1_intr(pc300_t * card, int ch)
2235 {
2236         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2237         falc_t *pfalc = (falc_t *) & chan->falc;
2238         void __iomem *falcbase = card->hw.falcbase;
2239         ucchar isr0, isr3, gis;
2240         ucchar dummy;
2241
2242         while ((gis = cpc_readb(falcbase + F_REG(GIS, ch))) != 0) {
2243                 if (gis & GIS_ISR0) {
2244                         isr0 = cpc_readb(falcbase + F_REG(FISR0, ch));
2245                         if (isr0 & FISR0_PDEN) {
2246                                 /* Read the bit to clear the situation */
2247                                 if (cpc_readb(falcbase + F_REG(FRS1, ch)) &
2248                                     FRS1_PDEN) {
2249                                         pfalc->pden++;
2250                                 }
2251                         }
2252                 }
2253
2254                 if (gis & GIS_ISR1) {
2255                         dummy = cpc_readb(falcbase + F_REG(FISR1, ch));
2256                 }
2257
2258                 if (gis & GIS_ISR2) {
2259                         dummy = cpc_readb(falcbase + F_REG(FISR2, ch));
2260                 }
2261
2262                 if (gis & GIS_ISR3) {
2263                         isr3 = cpc_readb(falcbase + F_REG(FISR3, ch));
2264                         if (isr3 & FISR3_SEC) {
2265                                 pfalc->sec++;
2266                                 falc_update_stats(card, ch);
2267                                 falc_check_status(card, ch,
2268                                                   cpc_readb(falcbase + F_REG(FRS0, ch)));
2269                         }
2270                         if (isr3 & FISR3_ES) {
2271                                 pfalc->es++;
2272                         }
2273                         if (isr3 & FISR3_LLBSC) {
2274                                 falc_t1_loop_detection(card, ch,
2275                                                        cpc_readb(falcbase + F_REG(FRS1, ch)));
2276                         }
2277                 }
2278         }
2279 }
2280
2281 static void falc_e1_intr(pc300_t * card, int ch)
2282 {
2283         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2284         falc_t *pfalc = (falc_t *) & chan->falc;
2285         void __iomem *falcbase = card->hw.falcbase;
2286         ucchar isr1, isr2, isr3, gis, rsp;
2287         ucchar dummy;
2288
2289         while ((gis = cpc_readb(falcbase + F_REG(GIS, ch))) != 0) {
2290                 rsp = cpc_readb(falcbase + F_REG(RSP, ch));
2291
2292                 if (gis & GIS_ISR0) {
2293                         dummy = cpc_readb(falcbase + F_REG(FISR0, ch));
2294                 }
2295                 if (gis & GIS_ISR1) {
2296                         isr1 = cpc_readb(falcbase + F_REG(FISR1, ch));
2297                         if (isr1 & FISR1_XMB) {
2298                                 if ((pfalc->xmb_cause & 2)
2299                                     && pfalc->multiframe_mode) {
2300                                         if (cpc_readb (falcbase + F_REG(FRS0, ch)) & 
2301                                                                         (FRS0_LOS | FRS0_AIS | FRS0_LFA)) {
2302                                                 cpc_writeb(falcbase + F_REG(XSP, ch),
2303                                                            cpc_readb(falcbase + F_REG(XSP, ch))
2304                                                            & ~XSP_AXS);
2305                                         } else {
2306                                                 cpc_writeb(falcbase + F_REG(XSP, ch),
2307                                                            cpc_readb(falcbase + F_REG(XSP, ch))
2308                                                            | XSP_AXS);
2309                                         }
2310                                 }
2311                                 pfalc->xmb_cause = 0;
2312                                 cpc_writeb(falcbase + F_REG(IMR1, ch),
2313                                            cpc_readb(falcbase + F_REG(IMR1, ch)) | IMR1_XMB);
2314                         }
2315                         if (isr1 & FISR1_LLBSC) {
2316                                 falc_e1_loop_detection(card, ch, rsp);
2317                         }
2318                 }
2319                 if (gis & GIS_ISR2) {
2320                         isr2 = cpc_readb(falcbase + F_REG(FISR2, ch));
2321                         if (isr2 & FISR2_T400MS) {
2322                                 cpc_writeb(falcbase + F_REG(XSW, ch),
2323                                            cpc_readb(falcbase + F_REG(XSW, ch)) | XSW_XRA);
2324                         }
2325                         if (isr2 & FISR2_MFAR) {
2326                                 cpc_writeb(falcbase + F_REG(XSW, ch),
2327                                            cpc_readb(falcbase + F_REG(XSW, ch)) & ~XSW_XRA);
2328                         }
2329                         if (isr2 & (FISR2_FAR | FISR2_LFA | FISR2_AIS | FISR2_LOS)) {
2330                                 pfalc->xmb_cause |= 2;
2331                                 cpc_writeb(falcbase + F_REG(IMR1, ch),
2332                                            cpc_readb(falcbase + F_REG(IMR1, ch)) & ~IMR1_XMB);
2333                         }
2334                 }
2335                 if (gis & GIS_ISR3) {
2336                         isr3 = cpc_readb(falcbase + F_REG(FISR3, ch));
2337                         if (isr3 & FISR3_SEC) {
2338                                 pfalc->sec++;
2339                                 falc_update_stats(card, ch);
2340                                 falc_check_status(card, ch,
2341                                                   cpc_readb(falcbase + F_REG(FRS0, ch)));
2342                         }
2343                         if (isr3 & FISR3_ES) {
2344                                 pfalc->es++;
2345                         }
2346                 }
2347         }
2348 }
2349
2350 static void falc_intr(pc300_t * card)
2351 {
2352         int ch;
2353
2354         for (ch = 0; ch < card->hw.nchan; ch++) {
2355                 pc300ch_t *chan = &card->chan[ch];
2356                 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
2357
2358                 if (conf->media == IF_IFACE_T1) {
2359                         falc_t1_intr(card, ch);
2360                 } else {
2361                         falc_e1_intr(card, ch);
2362                 }
2363         }
2364 }
2365
2366 static irqreturn_t cpc_intr(int irq, void *dev_id)
2367 {
2368         pc300_t *card = dev_id;
2369         volatile ucchar plx_status;
2370
2371         if (!card) {
2372 #ifdef PC300_DEBUG_INTR
2373                 printk("cpc_intr: spurious intr %d\n", irq);
2374 #endif
2375                 return IRQ_NONE;                /* spurious intr */
2376         }
2377
2378         if (!card->hw.rambase) {
2379 #ifdef PC300_DEBUG_INTR
2380                 printk("cpc_intr: spurious intr2 %d\n", irq);
2381 #endif
2382                 return IRQ_NONE;                /* spurious intr */
2383         }
2384
2385         switch (card->hw.type) {
2386                 case PC300_RSV:
2387                 case PC300_X21:
2388                         sca_intr(card);
2389                         break;
2390
2391                 case PC300_TE:
2392                         while ( (plx_status = (cpc_readb(card->hw.plxbase + card->hw.intctl_reg) &
2393                                  (PLX_9050_LINT1_STATUS | PLX_9050_LINT2_STATUS))) != 0) {
2394                                 if (plx_status & PLX_9050_LINT1_STATUS) {       /* SCA Interrupt */
2395                                         sca_intr(card);
2396                                 }
2397                                 if (plx_status & PLX_9050_LINT2_STATUS) {       /* FALC Interrupt */
2398                                         falc_intr(card);
2399                                 }
2400                         }
2401                         break;
2402         }
2403         return IRQ_HANDLED;
2404 }
2405
2406 static void cpc_sca_status(pc300_t * card, int ch)
2407 {
2408         ucchar ilar;
2409         void __iomem *scabase = card->hw.scabase;
2410         unsigned long flags;
2411
2412         tx_dma_buf_check(card, ch);
2413         rx_dma_buf_check(card, ch);
2414         ilar = cpc_readb(scabase + ILAR);
2415         printk ("ILAR=0x%02x, WCRL=0x%02x, PCR=0x%02x, BTCR=0x%02x, BOLR=0x%02x\n",
2416                  ilar, cpc_readb(scabase + WCRL), cpc_readb(scabase + PCR),
2417                  cpc_readb(scabase + BTCR), cpc_readb(scabase + BOLR));
2418         printk("TX_CDA=0x%08x, TX_EDA=0x%08x\n",
2419                cpc_readl(scabase + DTX_REG(CDAL, ch)),
2420                cpc_readl(scabase + DTX_REG(EDAL, ch)));
2421         printk("RX_CDA=0x%08x, RX_EDA=0x%08x, BFL=0x%04x\n",
2422                cpc_readl(scabase + DRX_REG(CDAL, ch)),
2423                cpc_readl(scabase + DRX_REG(EDAL, ch)),
2424                cpc_readw(scabase + DRX_REG(BFLL, ch)));
2425         printk("DMER=0x%02x, DSR_TX=0x%02x, DSR_RX=0x%02x\n",
2426                cpc_readb(scabase + DMER), cpc_readb(scabase + DSR_TX(ch)),
2427                cpc_readb(scabase + DSR_RX(ch)));
2428         printk("DMR_TX=0x%02x, DMR_RX=0x%02x, DIR_TX=0x%02x, DIR_RX=0x%02x\n",
2429                cpc_readb(scabase + DMR_TX(ch)), cpc_readb(scabase + DMR_RX(ch)),
2430                cpc_readb(scabase + DIR_TX(ch)),
2431                cpc_readb(scabase + DIR_RX(ch)));
2432         printk("DCR_TX=0x%02x, DCR_RX=0x%02x, FCT_TX=0x%02x, FCT_RX=0x%02x\n",
2433                cpc_readb(scabase + DCR_TX(ch)), cpc_readb(scabase + DCR_RX(ch)),
2434                cpc_readb(scabase + FCT_TX(ch)),
2435                cpc_readb(scabase + FCT_RX(ch)));
2436         printk("MD0=0x%02x, MD1=0x%02x, MD2=0x%02x, MD3=0x%02x, IDL=0x%02x\n",
2437                cpc_readb(scabase + M_REG(MD0, ch)),
2438                cpc_readb(scabase + M_REG(MD1, ch)),
2439                cpc_readb(scabase + M_REG(MD2, ch)),
2440                cpc_readb(scabase + M_REG(MD3, ch)),
2441                cpc_readb(scabase + M_REG(IDL, ch)));
2442         printk("CMD=0x%02x, SA0=0x%02x, SA1=0x%02x, TFN=0x%02x, CTL=0x%02x\n",
2443                cpc_readb(scabase + M_REG(CMD, ch)),
2444                cpc_readb(scabase + M_REG(SA0, ch)),
2445                cpc_readb(scabase + M_REG(SA1, ch)),
2446                cpc_readb(scabase + M_REG(TFN, ch)),
2447                cpc_readb(scabase + M_REG(CTL, ch)));
2448         printk("ST0=0x%02x, ST1=0x%02x, ST2=0x%02x, ST3=0x%02x, ST4=0x%02x\n",
2449                cpc_readb(scabase + M_REG(ST0, ch)),
2450                cpc_readb(scabase + M_REG(ST1, ch)),
2451                cpc_readb(scabase + M_REG(ST2, ch)),
2452                cpc_readb(scabase + M_REG(ST3, ch)),
2453                cpc_readb(scabase + M_REG(ST4, ch)));
2454         printk ("CST0=0x%02x, CST1=0x%02x, CST2=0x%02x, CST3=0x%02x, FST=0x%02x\n",
2455                  cpc_readb(scabase + M_REG(CST0, ch)),
2456                  cpc_readb(scabase + M_REG(CST1, ch)),
2457                  cpc_readb(scabase + M_REG(CST2, ch)),
2458                  cpc_readb(scabase + M_REG(CST3, ch)),
2459                  cpc_readb(scabase + M_REG(FST, ch)));
2460         printk("TRC0=0x%02x, TRC1=0x%02x, RRC=0x%02x, TBN=0x%02x, RBN=0x%02x\n",
2461                cpc_readb(scabase + M_REG(TRC0, ch)),
2462                cpc_readb(scabase + M_REG(TRC1, ch)),
2463                cpc_readb(scabase + M_REG(RRC, ch)),
2464                cpc_readb(scabase + M_REG(TBN, ch)),
2465                cpc_readb(scabase + M_REG(RBN, ch)));
2466         printk("TFS=0x%02x, TNR0=0x%02x, TNR1=0x%02x, RNR=0x%02x\n",
2467                cpc_readb(scabase + M_REG(TFS, ch)),
2468                cpc_readb(scabase + M_REG(TNR0, ch)),
2469                cpc_readb(scabase + M_REG(TNR1, ch)),
2470                cpc_readb(scabase + M_REG(RNR, ch)));
2471         printk("TCR=0x%02x, RCR=0x%02x, TNR1=0x%02x, RNR=0x%02x\n",
2472                cpc_readb(scabase + M_REG(TCR, ch)),
2473                cpc_readb(scabase + M_REG(RCR, ch)),
2474                cpc_readb(scabase + M_REG(TNR1, ch)),
2475                cpc_readb(scabase + M_REG(RNR, ch)));
2476         printk("TXS=0x%02x, RXS=0x%02x, EXS=0x%02x, TMCT=0x%02x, TMCR=0x%02x\n",
2477                cpc_readb(scabase + M_REG(TXS, ch)),
2478                cpc_readb(scabase + M_REG(RXS, ch)),
2479                cpc_readb(scabase + M_REG(EXS, ch)),
2480                cpc_readb(scabase + M_REG(TMCT, ch)),
2481                cpc_readb(scabase + M_REG(TMCR, ch)));
2482         printk("IE0=0x%02x, IE1=0x%02x, IE2=0x%02x, IE4=0x%02x, FIE=0x%02x\n",
2483                cpc_readb(scabase + M_REG(IE0, ch)),
2484                cpc_readb(scabase + M_REG(IE1, ch)),
2485                cpc_readb(scabase + M_REG(IE2, ch)),
2486                cpc_readb(scabase + M_REG(IE4, ch)),
2487                cpc_readb(scabase + M_REG(FIE, ch)));
2488         printk("IER0=0x%08x\n", cpc_readl(scabase + IER0));
2489
2490         if (ilar != 0) {
2491                 CPC_LOCK(card, flags);
2492                 cpc_writeb(scabase + ILAR, ilar);
2493                 cpc_writeb(scabase + DMER, 0x80);
2494                 CPC_UNLOCK(card, flags);
2495         }
2496 }
2497
2498 static void cpc_falc_status(pc300_t * card, int ch)
2499 {
2500         pc300ch_t *chan = &card->chan[ch];
2501         falc_t *pfalc = (falc_t *) & chan->falc;
2502         unsigned long flags;
2503
2504         CPC_LOCK(card, flags);
2505         printk("CH%d:   %s %s  %d channels\n",
2506                ch, (pfalc->sync ? "SYNC" : ""), (pfalc->active ? "ACTIVE" : ""),
2507                pfalc->num_channels);
2508
2509         printk("        pden=%d,  los=%d,  losr=%d,  lfa=%d,  farec=%d\n",
2510                pfalc->pden, pfalc->los, pfalc->losr, pfalc->lfa, pfalc->farec);
2511         printk("        lmfa=%d,  ais=%d,  sec=%d,  es=%d,  rai=%d\n",
2512                pfalc->lmfa, pfalc->ais, pfalc->sec, pfalc->es, pfalc->rai);
2513         printk("        bec=%d,  fec=%d,  cvc=%d,  cec=%d,  ebc=%d\n",
2514                pfalc->bec, pfalc->fec, pfalc->cvc, pfalc->cec, pfalc->ebc);
2515
2516         printk("\n");
2517         printk("        STATUS: %s  %s  %s  %s  %s  %s\n",
2518                (pfalc->red_alarm ? "RED" : ""),
2519                (pfalc->blue_alarm ? "BLU" : ""),
2520                (pfalc->yellow_alarm ? "YEL" : ""),
2521                (pfalc->loss_fa ? "LFA" : ""),
2522                (pfalc->loss_mfa ? "LMF" : ""), (pfalc->prbs ? "PRB" : ""));
2523         CPC_UNLOCK(card, flags);
2524 }
2525
2526 static int cpc_change_mtu(struct net_device *dev, int new_mtu)
2527 {
2528         if ((new_mtu < 128) || (new_mtu > PC300_DEF_MTU))
2529                 return -EINVAL;
2530         dev->mtu = new_mtu;
2531         return 0;
2532 }
2533
2534 static int cpc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2535 {
2536         pc300dev_t *d = (pc300dev_t *) dev->priv;
2537         pc300ch_t *chan = (pc300ch_t *) d->chan;
2538         pc300_t *card = (pc300_t *) chan->card;
2539         pc300conf_t conf_aux;
2540         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
2541         int ch = chan->channel;
2542         void __user *arg = ifr->ifr_data;
2543         struct if_settings *settings = &ifr->ifr_settings;
2544         void __iomem *scabase = card->hw.scabase;
2545
2546         if (!capable(CAP_NET_ADMIN))
2547                 return -EPERM;
2548
2549         switch (cmd) {
2550                 case SIOCGPC300CONF:
2551 #ifdef CONFIG_PC300_MLPPP
2552                         if (conf->proto != PC300_PROTO_MLPPP) {
2553                                 conf->proto = /* FIXME hdlc->proto.id */ 0;
2554                         }
2555 #else
2556                         conf->proto = /* FIXME hdlc->proto.id */ 0;
2557 #endif
2558                         memcpy(&conf_aux.conf, conf, sizeof(pc300chconf_t));
2559                         memcpy(&conf_aux.hw, &card->hw, sizeof(pc300hw_t));
2560                         if (!arg || 
2561                                 copy_to_user(arg, &conf_aux, sizeof(pc300conf_t))) 
2562                                 return -EINVAL;
2563                         return 0;
2564                 case SIOCSPC300CONF:
2565                         if (!capable(CAP_NET_ADMIN))
2566                                 return -EPERM;
2567                         if (!arg || 
2568                                 copy_from_user(&conf_aux.conf, arg, sizeof(pc300chconf_t)))
2569                                 return -EINVAL;
2570                         if (card->hw.cpld_id < 0x02 &&
2571                             conf_aux.conf.fr_mode == PC300_FR_UNFRAMED) {
2572                                 /* CPLD_ID < 0x02 doesn't support Unframed E1 */
2573                                 return -EINVAL;
2574                         }
2575 #ifdef CONFIG_PC300_MLPPP
2576                         if (conf_aux.conf.proto == PC300_PROTO_MLPPP) {
2577                                 if (conf->proto != PC300_PROTO_MLPPP) {
2578                                         memcpy(conf, &conf_aux.conf, sizeof(pc300chconf_t));
2579                                         cpc_tty_init(d);        /* init TTY driver */
2580                                 }
2581                         } else {
2582                                 if (conf_aux.conf.proto == 0xffff) {
2583                                         if (conf->proto == PC300_PROTO_MLPPP){ 
2584                                                 /* ifdown interface */
2585                                                 cpc_close(dev);
2586                                         }
2587                                 } else {
2588                                         memcpy(conf, &conf_aux.conf, sizeof(pc300chconf_t));
2589                                         /* FIXME hdlc->proto.id = conf->proto; */
2590                                 }
2591                         }
2592 #else
2593                         memcpy(conf, &conf_aux.conf, sizeof(pc300chconf_t));
2594                         /* FIXME hdlc->proto.id = conf->proto; */
2595 #endif
2596                         return 0;
2597                 case SIOCGPC300STATUS:
2598                         cpc_sca_status(card, ch);
2599                         return 0;
2600                 case SIOCGPC300FALCSTATUS:
2601                         cpc_falc_status(card, ch);
2602                         return 0;
2603
2604                 case SIOCGPC300UTILSTATS:
2605                         {
2606                                 if (!arg) {     /* clear statistics */
2607                                         memset(hdlc_stats(dev), 0, sizeof(struct net_device_stats));
2608                                         if (card->hw.type == PC300_TE) {
2609                                                 memset(&chan->falc, 0, sizeof(falc_t));
2610                                         }
2611                                 } else {
2612                                         pc300stats_t pc300stats;
2613
2614                                         memset(&pc300stats, 0, sizeof(pc300stats_t));
2615                                         pc300stats.hw_type = card->hw.type;
2616                                         pc300stats.line_on = card->chan[ch].d.line_on;
2617                                         pc300stats.line_off = card->chan[ch].d.line_off;
2618                                         memcpy(&pc300stats.gen_stats, hdlc_stats(dev),
2619                                                sizeof(struct net_device_stats));
2620                                         if (card->hw.type == PC300_TE)
2621                                                 memcpy(&pc300stats.te_stats,&chan->falc,sizeof(falc_t));
2622                                         if (copy_to_user(arg, &pc300stats, sizeof(pc300stats_t)))
2623                                                 return -EFAULT;
2624                                 }
2625                                 return 0;
2626                         }
2627
2628                 case SIOCGPC300UTILSTATUS:
2629                         {
2630                                 struct pc300status pc300status;
2631
2632                                 pc300status.hw_type = card->hw.type;
2633                                 if (card->hw.type == PC300_TE) {
2634                                         pc300status.te_status.sync = chan->falc.sync;
2635                                         pc300status.te_status.red_alarm = chan->falc.red_alarm;
2636                                         pc300status.te_status.blue_alarm = chan->falc.blue_alarm;
2637                                         pc300status.te_status.loss_fa = chan->falc.loss_fa;
2638                                         pc300status.te_status.yellow_alarm =chan->falc.yellow_alarm;
2639                                         pc300status.te_status.loss_mfa = chan->falc.loss_mfa;
2640                                         pc300status.te_status.prbs = chan->falc.prbs;
2641                                 } else {
2642                                         pc300status.gen_status.dcd =
2643                                                 !(cpc_readb (scabase + M_REG(ST3, ch)) & ST3_DCD);
2644                                         pc300status.gen_status.cts =
2645                                                 !(cpc_readb (scabase + M_REG(ST3, ch)) & ST3_CTS);
2646                                         pc300status.gen_status.rts =
2647                                                 !(cpc_readb (scabase + M_REG(CTL, ch)) & CTL_RTS);
2648                                         pc300status.gen_status.dtr =
2649                                                 !(cpc_readb (scabase + M_REG(CTL, ch)) & CTL_DTR);
2650                                         /* There is no DSR in HD64572 */
2651                                 }
2652                                 if (!arg
2653                                     || copy_to_user(arg, &pc300status, sizeof(pc300status_t)))
2654                                                 return -EINVAL;
2655                                 return 0;
2656                         }
2657
2658                 case SIOCSPC300TRACE:
2659                         /* Sets/resets a trace_flag for the respective device */
2660                         if (!arg || copy_from_user(&d->trace_on, arg,sizeof(unsigned char)))
2661                                         return -EINVAL;
2662                         return 0;
2663
2664                 case SIOCSPC300LOOPBACK:
2665                         {
2666                                 struct pc300loopback pc300loop;
2667
2668                                 /* TE boards only */
2669                                 if (card->hw.type != PC300_TE)
2670                                         return -EINVAL;
2671
2672                                 if (!arg || 
2673                                         copy_from_user(&pc300loop, arg, sizeof(pc300loopback_t)))
2674                                                 return -EINVAL;
2675                                 switch (pc300loop.loop_type) {
2676                                         case PC300LOCLOOP:      /* Turn the local loop on/off */
2677                                                 falc_local_loop(card, ch, pc300loop.loop_on);
2678                                                 return 0;
2679
2680                                         case PC300REMLOOP:      /* Turn the remote loop on/off */
2681                                                 falc_remote_loop(card, ch, pc300loop.loop_on);
2682                                                 return 0;
2683
2684                                         case PC300PAYLOADLOOP:  /* Turn the payload loop on/off */
2685                                                 falc_payload_loop(card, ch, pc300loop.loop_on);
2686                                                 return 0;
2687
2688                                         case PC300GENLOOPUP:    /* Generate loop UP */
2689                                                 if (pc300loop.loop_on) {
2690                                                         falc_generate_loop_up_code (card, ch);
2691                                                 } else {
2692                                                         turn_off_xlu(card, ch);
2693                                                 }
2694                                                 return 0;
2695
2696                                         case PC300GENLOOPDOWN:  /* Generate loop DOWN */
2697                                                 if (pc300loop.loop_on) {
2698                                                         falc_generate_loop_down_code (card, ch);
2699                                                 } else {
2700                                                         turn_off_xld(card, ch);
2701                                                 }
2702                                                 return 0;
2703
2704                                         default:
2705                                                 return -EINVAL;
2706                                 }
2707                         }
2708
2709                 case SIOCSPC300PATTERNTEST:
2710                         /* Turn the pattern test on/off and show the errors counter */
2711                         {
2712                                 struct pc300patterntst pc300patrntst;
2713
2714                                 /* TE boards only */
2715                                 if (card->hw.type != PC300_TE)
2716                                         return -EINVAL;
2717
2718                                 if (card->hw.cpld_id < 0x02) {
2719                                         /* CPLD_ID < 0x02 doesn't support pattern test */
2720                                         return -EINVAL;
2721                                 }
2722
2723                                 if (!arg || 
2724                                         copy_from_user(&pc300patrntst,arg,sizeof(pc300patterntst_t)))
2725                                                 return -EINVAL;
2726                                 if (pc300patrntst.patrntst_on == 2) {
2727                                         if (chan->falc.prbs == 0) {
2728                                                 falc_pattern_test(card, ch, 1);
2729                                         }
2730                                         pc300patrntst.num_errors =
2731                                                 falc_pattern_test_error(card, ch);
2732                                         if (!arg
2733                                             || copy_to_user(arg, &pc300patrntst,
2734                                                             sizeof (pc300patterntst_t)))
2735                                                         return -EINVAL;
2736                                 } else {
2737                                         falc_pattern_test(card, ch, pc300patrntst.patrntst_on);
2738                                 }
2739                                 return 0;
2740                         }
2741
2742                 case SIOCWANDEV:
2743                         switch (ifr->ifr_settings.type) {
2744                                 case IF_GET_IFACE:
2745                                 {
2746                                         const size_t size = sizeof(sync_serial_settings);
2747                                         ifr->ifr_settings.type = conf->media;
2748                                         if (ifr->ifr_settings.size < size) {
2749                                                 /* data size wanted */
2750                                                 ifr->ifr_settings.size = size;
2751                                                 return -ENOBUFS;
2752                                         }
2753         
2754                                         if (copy_to_user(settings->ifs_ifsu.sync,
2755                                                          &conf->phys_settings, size)) {
2756                                                 return -EFAULT;
2757                                         }
2758                                         return 0;
2759                                 }
2760
2761                                 case IF_IFACE_V35:
2762                                 case IF_IFACE_V24:
2763                                 case IF_IFACE_X21:
2764                                 {
2765                                         const size_t size = sizeof(sync_serial_settings);
2766
2767                                         if (!capable(CAP_NET_ADMIN)) {
2768                                                 return -EPERM;
2769                                         }
2770                                         /* incorrect data len? */
2771                                         if (ifr->ifr_settings.size != size) {
2772                                                 return -ENOBUFS;
2773                                         }
2774
2775                                         if (copy_from_user(&conf->phys_settings, 
2776                                                            settings->ifs_ifsu.sync, size)) {
2777                                                 return -EFAULT;
2778                                         }
2779
2780                                         if (conf->phys_settings.loopback) {
2781                                                 cpc_writeb(card->hw.scabase + M_REG(MD2, ch),
2782                                                         cpc_readb(card->hw.scabase + M_REG(MD2, ch)) | 
2783                                                         MD2_LOOP_MIR);
2784                                         }
2785                                         conf->media = ifr->ifr_settings.type;
2786                                         return 0;
2787                                 }
2788
2789                                 case IF_IFACE_T1:
2790                                 case IF_IFACE_E1:
2791                                 {
2792                                         const size_t te_size = sizeof(te1_settings);
2793                                         const size_t size = sizeof(sync_serial_settings);
2794
2795                                         if (!capable(CAP_NET_ADMIN)) {
2796                                                 return -EPERM;
2797                                         }
2798
2799                                         /* incorrect data len? */
2800                                         if (ifr->ifr_settings.size != te_size) {
2801                                                 return -ENOBUFS;
2802                                         }
2803
2804                                         if (copy_from_user(&conf->phys_settings, 
2805                                                            settings->ifs_ifsu.te1, size)) {
2806                                                 return -EFAULT;
2807                                         }/* Ignoring HDLC slot_map for a while */
2808                                         
2809                                         if (conf->phys_settings.loopback) {
2810                                                 cpc_writeb(card->hw.scabase + M_REG(MD2, ch),
2811                                                         cpc_readb(card->hw.scabase + M_REG(MD2, ch)) | 
2812                                                         MD2_LOOP_MIR);
2813                                         }
2814                                         conf->media = ifr->ifr_settings.type;
2815                                         return 0;
2816                                 }
2817                                 default:
2818                                         return hdlc_ioctl(dev, ifr, cmd);
2819                         }
2820
2821                 default:
2822                         return hdlc_ioctl(dev, ifr, cmd);
2823         }
2824 }
2825
2826 static struct net_device_stats *cpc_get_stats(struct net_device *dev)
2827 {
2828         return hdlc_stats(dev);
2829 }
2830
2831 static int clock_rate_calc(uclong rate, uclong clock, int *br_io)
2832 {
2833         int br, tc;
2834         int br_pwr, error;
2835
2836         *br_io = 0;
2837
2838         if (rate == 0)
2839                 return (0);
2840
2841         for (br = 0, br_pwr = 1; br <= 9; br++, br_pwr <<= 1) {
2842                 if ((tc = clock / br_pwr / rate) <= 0xff) {
2843                         *br_io = br;
2844                         break;
2845                 }
2846         }
2847
2848         if (tc <= 0xff) {
2849                 error = ((rate - (clock / br_pwr / rate)) / rate) * 1000;
2850                 /* Errors bigger than +/- 1% won't be tolerated */
2851                 if (error < -10 || error > 10)
2852                         return (-1);
2853                 else
2854                         return (tc);
2855         } else {
2856                 return (-1);
2857         }
2858 }
2859
2860 static int ch_config(pc300dev_t * d)
2861 {
2862         pc300ch_t *chan = (pc300ch_t *) d->chan;
2863         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
2864         pc300_t *card = (pc300_t *) chan->card;
2865         void __iomem *scabase = card->hw.scabase;
2866         void __iomem *plxbase = card->hw.plxbase;
2867         int ch = chan->channel;
2868         uclong clkrate = chan->conf.phys_settings.clock_rate;
2869         uclong clktype = chan->conf.phys_settings.clock_type;
2870         ucshort encoding = chan->conf.proto_settings.encoding;
2871         ucshort parity = chan->conf.proto_settings.parity;   
2872         ucchar md0, md2;
2873     
2874         /* Reset the channel */
2875         cpc_writeb(scabase + M_REG(CMD, ch), CMD_CH_RST);
2876
2877         /* Configure the SCA registers */
2878         switch (parity) {
2879                 case PARITY_NONE:
2880                         md0 = MD0_BIT_SYNC;
2881                         break;
2882                 case PARITY_CRC16_PR0:
2883                         md0 = MD0_CRC16_0|MD0_CRCC0|MD0_BIT_SYNC;
2884                         break;
2885                 case PARITY_CRC16_PR1:
2886                         md0 = MD0_CRC16_1|MD0_CRCC0|MD0_BIT_SYNC;
2887                         break;
2888                 case PARITY_CRC32_PR1_CCITT:
2889                         md0 = MD0_CRC32|MD0_CRCC0|MD0_BIT_SYNC;
2890                         break;
2891                 case PARITY_CRC16_PR1_CCITT:
2892                 default:
2893                         md0 = MD0_CRC_CCITT|MD0_CRCC0|MD0_BIT_SYNC;
2894                         break;
2895         }
2896         switch (encoding) {
2897                 case ENCODING_NRZI:
2898                         md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_NRZI;
2899                         break;
2900                 case ENCODING_FM_MARK:  /* FM1 */
2901                         md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_FM1;
2902                         break;
2903                 case ENCODING_FM_SPACE: /* FM0 */
2904                         md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_FM0;
2905                         break;
2906                 case ENCODING_MANCHESTER: /* It's not working... */
2907                         md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_MANCH;
2908                         break;
2909                 case ENCODING_NRZ:
2910                 default:
2911                         md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_NRZ;
2912                         break;
2913         }
2914         cpc_writeb(scabase + M_REG(MD0, ch), md0);
2915         cpc_writeb(scabase + M_REG(MD1, ch), 0);
2916         cpc_writeb(scabase + M_REG(MD2, ch), md2);
2917         cpc_writeb(scabase + M_REG(IDL, ch), 0x7e);
2918         cpc_writeb(scabase + M_REG(CTL, ch), CTL_URSKP | CTL_IDLC);
2919
2920         /* Configure HW media */
2921         switch (card->hw.type) {
2922                 case PC300_RSV:
2923                         if (conf->media == IF_IFACE_V35) {
2924                                 cpc_writel((plxbase + card->hw.gpioc_reg),
2925                                            cpc_readl(plxbase + card->hw.gpioc_reg) | PC300_CHMEDIA_MASK(ch));
2926                         } else {
2927                                 cpc_writel((plxbase + card->hw.gpioc_reg),
2928                                            cpc_readl(plxbase + card->hw.gpioc_reg) & ~PC300_CHMEDIA_MASK(ch));
2929                         }
2930                         break;
2931
2932                 case PC300_X21:
2933                         break;
2934
2935                 case PC300_TE:
2936                         te_config(card, ch);
2937                         break;
2938         }
2939
2940         switch (card->hw.type) {
2941                 case PC300_RSV:
2942                 case PC300_X21:
2943                         if (clktype == CLOCK_INT || clktype == CLOCK_TXINT) {
2944                                 int tmc, br;
2945
2946                                 /* Calculate the clkrate parameters */
2947                                 tmc = clock_rate_calc(clkrate, card->hw.clock, &br);
2948                                 if (tmc < 0)
2949                                         return -EIO;
2950                                 cpc_writeb(scabase + M_REG(TMCT, ch), tmc);
2951                                 cpc_writeb(scabase + M_REG(TXS, ch),
2952                                            (TXS_DTRXC | TXS_IBRG | br));
2953                                 if (clktype == CLOCK_INT) {
2954                                         cpc_writeb(scabase + M_REG(TMCR, ch), tmc);
2955                                         cpc_writeb(scabase + M_REG(RXS, ch), 
2956                                                    (RXS_IBRG | br));
2957                                 } else {
2958                                         cpc_writeb(scabase + M_REG(TMCR, ch), 1);
2959                                         cpc_writeb(scabase + M_REG(RXS, ch), 0);
2960                                 }
2961                                 if (card->hw.type == PC300_X21) {
2962                                         cpc_writeb(scabase + M_REG(GPO, ch), 1);
2963                                         cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1 | EXS_RES1);
2964                                 } else {
2965                                         cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1);
2966                                 }
2967                         } else {
2968                                 cpc_writeb(scabase + M_REG(TMCT, ch), 1);
2969                                 if (clktype == CLOCK_EXT) {
2970                                         cpc_writeb(scabase + M_REG(TXS, ch), 
2971                                                    TXS_DTRXC);
2972                                 } else {
2973                                         cpc_writeb(scabase + M_REG(TXS, ch), 
2974                                                    TXS_DTRXC|TXS_RCLK);
2975                                 }
2976                                 cpc_writeb(scabase + M_REG(TMCR, ch), 1);
2977                                 cpc_writeb(scabase + M_REG(RXS, ch), 0);
2978                                 if (card->hw.type == PC300_X21) {
2979                                         cpc_writeb(scabase + M_REG(GPO, ch), 0);
2980                                         cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1 | EXS_RES1);
2981                                 } else {
2982                                         cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1);
2983                                 }
2984                         }
2985                         break;
2986
2987                 case PC300_TE:
2988                         /* SCA always receives clock from the FALC chip */
2989                         cpc_writeb(scabase + M_REG(TMCT, ch), 1);
2990                         cpc_writeb(scabase + M_REG(TXS, ch), 0);
2991                         cpc_writeb(scabase + M_REG(TMCR, ch), 1);
2992                         cpc_writeb(scabase + M_REG(RXS, ch), 0);
2993                         cpc_writeb(scabase + M_REG(EXS, ch), 0);
2994                         break;
2995         }
2996
2997         /* Enable Interrupts */
2998         cpc_writel(scabase + IER0,
2999                    cpc_readl(scabase + IER0) |
3000                    IR0_M(IR0_RXINTA, ch) |
3001                    IR0_DRX(IR0_EFT | IR0_DMIA | IR0_DMIB, ch) |
3002                    IR0_DTX(IR0_EFT | IR0_DMIA | IR0_DMIB, ch));
3003         cpc_writeb(scabase + M_REG(IE0, ch),
3004                    cpc_readl(scabase + M_REG(IE0, ch)) | IE0_RXINTA);
3005         cpc_writeb(scabase + M_REG(IE1, ch),
3006                    cpc_readl(scabase + M_REG(IE1, ch)) | IE1_CDCD);
3007
3008         return 0;
3009 }
3010
3011 static int rx_config(pc300dev_t * d)
3012 {
3013         pc300ch_t *chan = (pc300ch_t *) d->chan;
3014         pc300_t *card = (pc300_t *) chan->card;
3015         void __iomem *scabase = card->hw.scabase;
3016         int ch = chan->channel;
3017
3018         cpc_writeb(scabase + DSR_RX(ch), 0);
3019
3020         /* General RX settings */
3021         cpc_writeb(scabase + M_REG(RRC, ch), 0);
3022         cpc_writeb(scabase + M_REG(RNR, ch), 16);
3023
3024         /* Enable reception */
3025         cpc_writeb(scabase + M_REG(CMD, ch), CMD_RX_CRC_INIT);
3026         cpc_writeb(scabase + M_REG(CMD, ch), CMD_RX_ENA);
3027
3028         /* Initialize DMA stuff */
3029         chan->rx_first_bd = 0;
3030         chan->rx_last_bd = N_DMA_RX_BUF - 1;
3031         rx_dma_buf_init(card, ch);
3032         cpc_writeb(scabase + DCR_RX(ch), DCR_FCT_CLR);
3033         cpc_writeb(scabase + DMR_RX(ch), (DMR_TMOD | DMR_NF));
3034         cpc_writeb(scabase + DIR_RX(ch), (DIR_EOM | DIR_BOF));
3035
3036         /* Start DMA */
3037         rx_dma_start(card, ch);
3038
3039         return 0;
3040 }
3041
3042 static int tx_config(pc300dev_t * d)
3043 {
3044         pc300ch_t *chan = (pc300ch_t *) d->chan;
3045         pc300_t *card = (pc300_t *) chan->card;
3046         void __iomem *scabase = card->hw.scabase;
3047         int ch = chan->channel;
3048
3049         cpc_writeb(scabase + DSR_TX(ch), 0);
3050
3051         /* General TX settings */
3052         cpc_writeb(scabase + M_REG(TRC0, ch), 0);
3053         cpc_writeb(scabase + M_REG(TFS, ch), 32);
3054         cpc_writeb(scabase + M_REG(TNR0, ch), 20);
3055         cpc_writeb(scabase + M_REG(TNR1, ch), 48);
3056         cpc_writeb(scabase + M_REG(TCR, ch), 8);
3057
3058         /* Enable transmission */
3059         cpc_writeb(scabase + M_REG(CMD, ch), CMD_TX_CRC_INIT);
3060
3061         /* Initialize DMA stuff */
3062         chan->tx_first_bd = 0;
3063         chan->tx_next_bd = 0;
3064         tx_dma_buf_init(card, ch);
3065         cpc_writeb(scabase + DCR_TX(ch), DCR_FCT_CLR);
3066         cpc_writeb(scabase + DMR_TX(ch), (DMR_TMOD | DMR_NF));
3067         cpc_writeb(scabase + DIR_TX(ch), (DIR_EOM | DIR_BOF | DIR_UDRF));
3068         cpc_writel(scabase + DTX_REG(CDAL, ch), TX_BD_ADDR(ch, chan->tx_first_bd));
3069         cpc_writel(scabase + DTX_REG(EDAL, ch), TX_BD_ADDR(ch, chan->tx_next_bd));
3070
3071         return 0;
3072 }
3073
3074 static int cpc_attach(struct net_device *dev, unsigned short encoding,
3075                       unsigned short parity)
3076 {
3077         pc300dev_t *d = (pc300dev_t *)dev->priv;
3078         pc300ch_t *chan = (pc300ch_t *)d->chan;
3079         pc300_t *card = (pc300_t *)chan->card;
3080         pc300chconf_t *conf = (pc300chconf_t *)&chan->conf;
3081
3082         if (card->hw.type == PC300_TE) {
3083                 if (encoding != ENCODING_NRZ && encoding != ENCODING_NRZI) {
3084                         return -EINVAL;
3085                 }
3086         } else {
3087                 if (encoding != ENCODING_NRZ && encoding != ENCODING_NRZI &&
3088                     encoding != ENCODING_FM_MARK && encoding != ENCODING_FM_SPACE) {
3089                         /* Driver doesn't support ENCODING_MANCHESTER yet */
3090                         return -EINVAL;
3091                 }
3092         }
3093
3094         if (parity != PARITY_NONE && parity != PARITY_CRC16_PR0 &&
3095             parity != PARITY_CRC16_PR1 && parity != PARITY_CRC32_PR1_CCITT &&
3096             parity != PARITY_CRC16_PR1_CCITT) {
3097                 return -EINVAL;
3098         }
3099
3100         conf->proto_settings.encoding = encoding;
3101         conf->proto_settings.parity = parity;
3102         return 0;
3103 }
3104
3105 static int cpc_opench(pc300dev_t * d)
3106 {
3107         pc300ch_t *chan = (pc300ch_t *) d->chan;
3108         pc300_t *card = (pc300_t *) chan->card;
3109         int ch = chan->channel, rc;
3110         void __iomem *scabase = card->hw.scabase;
3111
3112         rc = ch_config(d);
3113         if (rc)
3114                 return rc;
3115
3116         rx_config(d);
3117
3118         tx_config(d);
3119
3120         /* Assert RTS and DTR */
3121         cpc_writeb(scabase + M_REG(CTL, ch),
3122                    cpc_readb(scabase + M_REG(CTL, ch)) & ~(CTL_RTS | CTL_DTR));
3123
3124         return 0;
3125 }
3126
3127 static void cpc_closech(pc300dev_t * d)
3128 {
3129         pc300ch_t *chan = (pc300ch_t *) d->chan;
3130         pc300_t *card = (pc300_t *) chan->card;
3131         falc_t *pfalc = (falc_t *) & chan->falc;
3132         int ch = chan->channel;
3133
3134         cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_CH_RST);
3135         rx_dma_stop(card, ch);
3136         tx_dma_stop(card, ch);
3137
3138         if (card->hw.type == PC300_TE) {
3139                 memset(pfalc, 0, sizeof(falc_t));
3140                 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
3141                            cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) &
3142                            ~((CPLD_REG2_FALC_TX_CLK | CPLD_REG2_FALC_RX_CLK |
3143                               CPLD_REG2_FALC_LED2) << (2 * ch)));
3144                 /* Reset the FALC chip */
3145                 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
3146                            cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
3147                            (CPLD_REG1_FALC_RESET << (2 * ch)));
3148                 udelay(10000);
3149                 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
3150                            cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) &
3151                            ~(CPLD_REG1_FALC_RESET << (2 * ch)));
3152         }
3153 }
3154
3155 int cpc_open(struct net_device *dev)
3156 {
3157         pc300dev_t *d = (pc300dev_t *) dev->priv;
3158         struct ifreq ifr;
3159         int result;
3160
3161 #ifdef  PC300_DEBUG_OTHER
3162         printk("pc300: cpc_open");
3163 #endif
3164
3165 #ifdef FIXME
3166         if (hdlc->proto.id == IF_PROTO_PPP) {
3167                 d->if_ptr = &hdlc->state.ppp.pppdev;
3168         }
3169 #endif
3170
3171         result = hdlc_open(dev);
3172         if (/* FIXME hdlc->proto.id == IF_PROTO_PPP*/ 0) {
3173                 dev->priv = d;
3174         }
3175         if (result) {
3176                 return result;
3177         }
3178
3179         sprintf(ifr.ifr_name, "%s", dev->name);
3180         result = cpc_opench(d);
3181         if (result)
3182                 goto err_out;
3183
3184         netif_start_queue(dev);
3185         return 0;
3186
3187 err_out:
3188         hdlc_close(dev);
3189         return result;
3190 }
3191
3192 static int cpc_close(struct net_device *dev)
3193 {
3194         pc300dev_t *d = (pc300dev_t *) dev->priv;
3195         pc300ch_t *chan = (pc300ch_t *) d->chan;
3196         pc300_t *card = (pc300_t *) chan->card;
3197         unsigned long flags;
3198
3199 #ifdef  PC300_DEBUG_OTHER
3200         printk("pc300: cpc_close");
3201 #endif
3202
3203         netif_stop_queue(dev);
3204
3205         CPC_LOCK(card, flags);
3206         cpc_closech(d);
3207         CPC_UNLOCK(card, flags);
3208
3209         hdlc_close(dev);
3210         if (/* FIXME hdlc->proto.id == IF_PROTO_PPP*/ 0) {
3211                 d->if_ptr = NULL;
3212         }
3213 #ifdef CONFIG_PC300_MLPPP
3214         if (chan->conf.proto == PC300_PROTO_MLPPP) {
3215                 cpc_tty_unregister_service(d);
3216                 chan->conf.proto = 0xffff;
3217         }
3218 #endif
3219
3220         return 0;
3221 }
3222
3223 static uclong detect_ram(pc300_t * card)
3224 {
3225         uclong i;
3226         ucchar data;
3227         void __iomem *rambase = card->hw.rambase;
3228
3229         card->hw.ramsize = PC300_RAMSIZE;
3230         /* Let's find out how much RAM is present on this board */
3231         for (i = 0; i < card->hw.ramsize; i++) {
3232                 data = (ucchar) (i & 0xff);
3233                 cpc_writeb(rambase + i, data);
3234                 if (cpc_readb(rambase + i) != data) {
3235                         break;
3236                 }
3237         }
3238         return (i);
3239 }
3240
3241 static void plx_init(pc300_t * card)
3242 {
3243         struct RUNTIME_9050 __iomem *plx_ctl = card->hw.plxbase;
3244
3245         /* Reset PLX */
3246         cpc_writel(&plx_ctl->init_ctrl,
3247                    cpc_readl(&plx_ctl->init_ctrl) | 0x40000000);
3248         udelay(10000L);
3249         cpc_writel(&plx_ctl->init_ctrl,
3250                    cpc_readl(&plx_ctl->init_ctrl) & ~0x40000000);
3251
3252         /* Reload Config. Registers from EEPROM */
3253         cpc_writel(&plx_ctl->init_ctrl,
3254                    cpc_readl(&plx_ctl->init_ctrl) | 0x20000000);
3255         udelay(10000L);
3256         cpc_writel(&plx_ctl->init_ctrl,
3257                    cpc_readl(&plx_ctl->init_ctrl) & ~0x20000000);
3258
3259 }
3260
3261 static inline void show_version(void)
3262 {
3263         char *rcsvers, *rcsdate, *tmp;
3264
3265         rcsvers = strchr(rcsid, ' ');
3266         rcsvers++;
3267         tmp = strchr(rcsvers, ' ');
3268         *tmp++ = '\0';
3269         rcsdate = strchr(tmp, ' ');
3270         rcsdate++;
3271         tmp = strrchr(rcsdate, ' ');
3272         *tmp = '\0';
3273         printk(KERN_INFO "Cyclades-PC300 driver %s %s (built %s %s)\n", 
3274                 rcsvers, rcsdate, __DATE__, __TIME__);
3275 }                               /* show_version */
3276
3277 static void cpc_init_card(pc300_t * card)
3278 {
3279         int i, devcount = 0;
3280         static int board_nbr = 1;
3281
3282         /* Enable interrupts on the PCI bridge */
3283         plx_init(card);
3284         cpc_writew(card->hw.plxbase + card->hw.intctl_reg,
3285                    cpc_readw(card->hw.plxbase + card->hw.intctl_reg) | 0x0040);
3286
3287 #ifdef USE_PCI_CLOCK
3288         /* Set board clock to PCI clock */
3289         cpc_writel(card->hw.plxbase + card->hw.gpioc_reg,
3290                    cpc_readl(card->hw.plxbase + card->hw.gpioc_reg) | 0x00000004UL);
3291         card->hw.clock = PC300_PCI_CLOCK;
3292 #else
3293         /* Set board clock to internal oscillator clock */
3294         cpc_writel(card->hw.plxbase + card->hw.gpioc_reg,
3295                    cpc_readl(card->hw.plxbase + card->hw.gpioc_reg) & ~0x00000004UL);
3296         card->hw.clock = PC300_OSC_CLOCK;
3297 #endif
3298
3299         /* Detect actual on-board RAM size */
3300         card->hw.ramsize = detect_ram(card);
3301
3302         /* Set Global SCA-II registers */
3303         cpc_writeb(card->hw.scabase + PCR, PCR_PR2);
3304         cpc_writeb(card->hw.scabase + BTCR, 0x10);
3305         cpc_writeb(card->hw.scabase + WCRL, 0);
3306         cpc_writeb(card->hw.scabase + DMER, 0x80);
3307
3308         if (card->hw.type == PC300_TE) {
3309                 ucchar reg1;
3310
3311                 /* Check CPLD version */
3312                 reg1 = cpc_readb(card->hw.falcbase + CPLD_REG1);
3313                 cpc_writeb(card->hw.falcbase + CPLD_REG1, (reg1 + 0x5a));
3314                 if (cpc_readb(card->hw.falcbase + CPLD_REG1) == reg1) {
3315                         /* New CPLD */
3316                         card->hw.cpld_id = cpc_readb(card->hw.falcbase + CPLD_ID_REG);
3317                         card->hw.cpld_reg1 = CPLD_V2_REG1;
3318                         card->hw.cpld_reg2 = CPLD_V2_REG2;
3319                 } else {
3320                         /* old CPLD */
3321                         card->hw.cpld_id = 0;
3322                         card->hw.cpld_reg1 = CPLD_REG1;
3323                         card->hw.cpld_reg2 = CPLD_REG2;
3324                         cpc_writeb(card->hw.falcbase + CPLD_REG1, reg1);
3325                 }
3326
3327                 /* Enable the board's global clock */
3328                 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
3329                            cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
3330                            CPLD_REG1_GLOBAL_CLK);
3331
3332         }
3333
3334         for (i = 0; i < card->hw.nchan; i++) {
3335                 pc300ch_t *chan = &card->chan[i];
3336                 pc300dev_t *d = &chan->d;
3337                 hdlc_device *hdlc;
3338                 struct net_device *dev;
3339
3340                 chan->card = card;
3341                 chan->channel = i;
3342                 chan->conf.phys_settings.clock_rate = 0;
3343                 chan->conf.phys_settings.clock_type = CLOCK_EXT;
3344                 chan->conf.proto_settings.encoding = ENCODING_NRZ;
3345                 chan->conf.proto_settings.parity = PARITY_CRC16_PR1_CCITT;
3346                 switch (card->hw.type) {
3347                         case PC300_TE:
3348                                 chan->conf.media = IF_IFACE_T1;
3349                                 chan->conf.lcode = PC300_LC_B8ZS;
3350                                 chan->conf.fr_mode = PC300_FR_ESF;
3351                                 chan->conf.lbo = PC300_LBO_0_DB;
3352                                 chan->conf.rx_sens = PC300_RX_SENS_SH;
3353                                 chan->conf.tslot_bitmap = 0xffffffffUL;
3354                                 break;
3355
3356                         case PC300_X21:
3357                                 chan->conf.media = IF_IFACE_X21;
3358                                 break;
3359
3360                         case PC300_RSV:
3361                         default:
3362                                 chan->conf.media = IF_IFACE_V35;
3363                                 break;
3364                 }
3365                 chan->conf.proto = IF_PROTO_PPP;
3366                 chan->tx_first_bd = 0;
3367                 chan->tx_next_bd = 0;
3368                 chan->rx_first_bd = 0;
3369                 chan->rx_last_bd = N_DMA_RX_BUF - 1;
3370                 chan->nfree_tx_bd = N_DMA_TX_BUF;
3371
3372                 d->chan = chan;
3373                 d->tx_skb = NULL;
3374                 d->trace_on = 0;
3375                 d->line_on = 0;
3376                 d->line_off = 0;
3377
3378                 dev = alloc_hdlcdev(NULL);
3379                 if (dev == NULL)
3380                         continue;
3381
3382                 hdlc = dev_to_hdlc(dev);
3383                 hdlc->xmit = cpc_queue_xmit;
3384                 hdlc->attach = cpc_attach;
3385                 d->dev = dev;
3386                 dev->mem_start = card->hw.ramphys;
3387                 dev->mem_end = card->hw.ramphys + card->hw.ramsize - 1;
3388                 dev->irq = card->hw.irq;
3389                 dev->init = NULL;
3390                 dev->tx_queue_len = PC300_TX_QUEUE_LEN;
3391                 dev->mtu = PC300_DEF_MTU;
3392
3393                 dev->open = cpc_open;
3394                 dev->stop = cpc_close;
3395                 dev->tx_timeout = cpc_tx_timeout;
3396                 dev->watchdog_timeo = PC300_TX_TIMEOUT;
3397                 dev->get_stats = cpc_get_stats;
3398                 dev->set_multicast_list = NULL;
3399                 dev->set_mac_address = NULL;
3400                 dev->change_mtu = cpc_change_mtu;
3401                 dev->do_ioctl = cpc_ioctl;
3402
3403                 if (register_hdlc_device(dev) == 0) {
3404                         dev->priv = d;  /* We need 'priv', hdlc doesn't */
3405                         printk("%s: Cyclades-PC300/", dev->name);
3406                         switch (card->hw.type) {
3407                                 case PC300_TE:
3408                                         if (card->hw.bus == PC300_PMC) {
3409                                                 printk("TE-M");
3410                                         } else {
3411                                                 printk("TE  ");
3412                                         }
3413                                         break;
3414
3415                                 case PC300_X21:
3416                                         printk("X21 ");
3417                                         break;
3418
3419                                 case PC300_RSV:
3420                                 default:
3421                                         printk("RSV ");
3422                                         break;
3423                         }
3424                         printk (" #%d, %dKB of RAM at 0x%08x, IRQ%d, channel %d.\n",
3425                                  board_nbr, card->hw.ramsize / 1024,
3426                                  card->hw.ramphys, card->hw.irq, i + 1);
3427                         devcount++;
3428                 } else {
3429                         printk ("Dev%d on card(0x%08x): unable to allocate i/f name.\n",
3430                                  i + 1, card->hw.ramphys);
3431                         free_netdev(dev);
3432                         continue;
3433                 }
3434         }
3435         spin_lock_init(&card->card_lock);
3436
3437         board_nbr++;
3438 }
3439
3440 static int __devinit
3441 cpc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3442 {
3443         static int first_time = 1;
3444         int err, eeprom_outdated = 0;
3445         ucshort device_id;
3446         pc300_t *card;
3447
3448         if (first_time) {
3449                 first_time = 0;
3450                 show_version();
3451 #ifdef CONFIG_PC300_MLPPP
3452                 cpc_tty_reset_var();
3453 #endif
3454         }
3455
3456         if ((err = pci_enable_device(pdev)) < 0)
3457                 return err;
3458
3459         card = kzalloc(sizeof(pc300_t), GFP_KERNEL);
3460         if (card == NULL) {
3461                 printk("PC300 found at RAM 0x%016llx, "
3462                        "but could not allocate card structure.\n",
3463                        (unsigned long long)pci_resource_start(pdev, 3));
3464                 err = -ENOMEM;
3465                 goto err_disable_dev;
3466         }
3467
3468         err = -ENODEV;
3469
3470         /* read PCI configuration area */
3471         device_id = ent->device;
3472         card->hw.irq = pdev->irq;
3473         card->hw.iophys = pci_resource_start(pdev, 1);
3474         card->hw.iosize = pci_resource_len(pdev, 1);
3475         card->hw.scaphys = pci_resource_start(pdev, 2);
3476         card->hw.scasize = pci_resource_len(pdev, 2);
3477         card->hw.ramphys = pci_resource_start(pdev, 3);
3478         card->hw.alloc_ramsize = pci_resource_len(pdev, 3);
3479         card->hw.falcphys = pci_resource_start(pdev, 4);
3480         card->hw.falcsize = pci_resource_len(pdev, 4);
3481         card->hw.plxphys = pci_resource_start(pdev, 5);
3482         card->hw.plxsize = pci_resource_len(pdev, 5);
3483
3484         switch (device_id) {
3485                 case PCI_DEVICE_ID_PC300_RX_1:
3486                 case PCI_DEVICE_ID_PC300_TE_1:
3487                 case PCI_DEVICE_ID_PC300_TE_M_1:
3488                         card->hw.nchan = 1;
3489                         break;
3490
3491                 case PCI_DEVICE_ID_PC300_RX_2:
3492                 case PCI_DEVICE_ID_PC300_TE_2:
3493                 case PCI_DEVICE_ID_PC300_TE_M_2:
3494                 default:
3495                         card->hw.nchan = PC300_MAXCHAN;
3496                         break;
3497         }
3498 #ifdef PC300_DEBUG_PCI
3499         printk("cpc (bus=0x0%x,pci_id=0x%x,", pdev->bus->number, pdev->devfn);
3500         printk("rev_id=%d) IRQ%d\n", pdev->revision, card->hw.irq);
3501         printk("cpc:found  ramaddr=0x%08lx plxaddr=0x%08lx "
3502                "ctladdr=0x%08lx falcaddr=0x%08lx\n",
3503                card->hw.ramphys, card->hw.plxphys, card->hw.scaphys,
3504                card->hw.falcphys);
3505 #endif
3506         /* Although we don't use this I/O region, we should
3507          * request it from the kernel anyway, to avoid problems
3508          * with other drivers accessing it. */
3509         if (!request_region(card->hw.iophys, card->hw.iosize, "PLX Registers")) {
3510                 /* In case we can't allocate it, warn user */
3511                 printk("WARNING: couldn't allocate I/O region for PC300 board "
3512                        "at 0x%08x!\n", card->hw.ramphys);
3513         }
3514
3515         if (card->hw.plxphys) {
3516                 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, card->hw.plxphys);
3517         } else {
3518                 eeprom_outdated = 1;
3519                 card->hw.plxphys = pci_resource_start(pdev, 0);
3520                 card->hw.plxsize = pci_resource_len(pdev, 0);
3521         }
3522
3523         if (!request_mem_region(card->hw.plxphys, card->hw.plxsize,
3524                                 "PLX Registers")) {
3525                 printk("PC300 found at RAM 0x%08x, "
3526                        "but could not allocate PLX mem region.\n",
3527                        card->hw.ramphys);
3528                 goto err_release_io;
3529         }
3530         if (!request_mem_region(card->hw.ramphys, card->hw.alloc_ramsize,
3531                                 "On-board RAM")) {
3532                 printk("PC300 found at RAM 0x%08x, "
3533                        "but could not allocate RAM mem region.\n",
3534                        card->hw.ramphys);
3535                 goto err_release_plx;
3536         }
3537         if (!request_mem_region(card->hw.scaphys, card->hw.scasize,
3538                                 "SCA-II Registers")) {
3539                 printk("PC300 found at RAM 0x%08x, "
3540                        "but could not allocate SCA mem region.\n",
3541                        card->hw.ramphys);
3542                 goto err_release_ram;
3543         }
3544
3545         card->hw.plxbase = ioremap(card->hw.plxphys, card->hw.plxsize);
3546         card->hw.rambase = ioremap(card->hw.ramphys, card->hw.alloc_ramsize);
3547         card->hw.scabase = ioremap(card->hw.scaphys, card->hw.scasize);
3548         switch (device_id) {
3549                 case PCI_DEVICE_ID_PC300_TE_1:
3550                 case PCI_DEVICE_ID_PC300_TE_2:
3551                 case PCI_DEVICE_ID_PC300_TE_M_1:
3552                 case PCI_DEVICE_ID_PC300_TE_M_2:
3553                         request_mem_region(card->hw.falcphys, card->hw.falcsize,
3554                                            "FALC Registers");
3555                         card->hw.falcbase = ioremap(card->hw.falcphys, card->hw.falcsize);
3556                         break;
3557
3558                 case PCI_DEVICE_ID_PC300_RX_1:
3559                 case PCI_DEVICE_ID_PC300_RX_2:
3560                 default:
3561                         card->hw.falcbase = NULL;
3562                         break;
3563         }
3564
3565 #ifdef PC300_DEBUG_PCI
3566         printk("cpc: relocate ramaddr=0x%08lx plxaddr=0x%08lx "
3567                "ctladdr=0x%08lx falcaddr=0x%08lx\n",
3568                card->hw.rambase, card->hw.plxbase, card->hw.scabase,
3569                card->hw.falcbase);
3570 #endif
3571
3572         /* Set PCI drv pointer to the card structure */
3573         pci_set_drvdata(pdev, card);
3574
3575         /* Set board type */
3576         switch (device_id) {
3577                 case PCI_DEVICE_ID_PC300_TE_1:
3578                 case PCI_DEVICE_ID_PC300_TE_2:
3579                 case PCI_DEVICE_ID_PC300_TE_M_1:
3580                 case PCI_DEVICE_ID_PC300_TE_M_2:
3581                         card->hw.type = PC300_TE;
3582
3583                         if ((device_id == PCI_DEVICE_ID_PC300_TE_M_1) ||
3584                             (device_id == PCI_DEVICE_ID_PC300_TE_M_2)) {
3585                                 card->hw.bus = PC300_PMC;
3586                                 /* Set PLX register offsets */
3587                                 card->hw.gpioc_reg = 0x54;
3588                                 card->hw.intctl_reg = 0x4c;
3589                         } else {
3590                                 card->hw.bus = PC300_PCI;
3591                                 /* Set PLX register offsets */
3592                                 card->hw.gpioc_reg = 0x50;
3593                                 card->hw.intctl_reg = 0x4c;
3594                         }
3595                         break;
3596
3597                 case PCI_DEVICE_ID_PC300_RX_1:
3598                 case PCI_DEVICE_ID_PC300_RX_2:
3599                 default:
3600                         card->hw.bus = PC300_PCI;
3601                         /* Set PLX register offsets */
3602                         card->hw.gpioc_reg = 0x50;
3603                         card->hw.intctl_reg = 0x4c;
3604
3605                         if ((cpc_readl(card->hw.plxbase + card->hw.gpioc_reg) & PC300_CTYPE_MASK)) {
3606                                 card->hw.type = PC300_X21;
3607                         } else {
3608                                 card->hw.type = PC300_RSV;
3609                         }
3610                         break;
3611         }
3612
3613         /* Allocate IRQ */
3614         if (request_irq(card->hw.irq, cpc_intr, IRQF_SHARED, "Cyclades-PC300", card)) {
3615                 printk ("PC300 found at RAM 0x%08x, but could not allocate IRQ%d.\n",
3616                          card->hw.ramphys, card->hw.irq);
3617                 goto err_io_unmap;
3618         }
3619
3620         cpc_init_card(card);
3621
3622         if (eeprom_outdated)
3623                 printk("WARNING: PC300 with outdated EEPROM.\n");
3624         return 0;
3625
3626 err_io_unmap:
3627         iounmap(card->hw.plxbase);
3628         iounmap(card->hw.scabase);
3629         iounmap(card->hw.rambase);
3630         if (card->hw.type == PC300_TE) {
3631                 iounmap(card->hw.falcbase);
3632                 release_mem_region(card->hw.falcphys, card->hw.falcsize);
3633         }
3634         release_mem_region(card->hw.scaphys, card->hw.scasize);
3635 err_release_ram:
3636         release_mem_region(card->hw.ramphys, card->hw.alloc_ramsize);
3637 err_release_plx:
3638         release_mem_region(card->hw.plxphys, card->hw.plxsize);
3639 err_release_io:
3640         release_region(card->hw.iophys, card->hw.iosize);
3641         kfree(card);
3642 err_disable_dev:
3643         pci_disable_device(pdev);
3644         return err;
3645 }
3646
3647 static void __devexit cpc_remove_one(struct pci_dev *pdev)
3648 {
3649         pc300_t *card = pci_get_drvdata(pdev);
3650
3651         if (card->hw.rambase) {
3652                 int i;
3653
3654                 /* Disable interrupts on the PCI bridge */
3655                 cpc_writew(card->hw.plxbase + card->hw.intctl_reg,
3656                            cpc_readw(card->hw.plxbase + card->hw.intctl_reg) & ~(0x0040));
3657
3658                 for (i = 0; i < card->hw.nchan; i++) {
3659                         unregister_hdlc_device(card->chan[i].d.dev);
3660                 }
3661                 iounmap(card->hw.plxbase);
3662                 iounmap(card->hw.scabase);
3663                 iounmap(card->hw.rambase);
3664                 release_mem_region(card->hw.plxphys, card->hw.plxsize);
3665                 release_mem_region(card->hw.ramphys, card->hw.alloc_ramsize);
3666                 release_mem_region(card->hw.scaphys, card->hw.scasize);
3667                 release_region(card->hw.iophys, card->hw.iosize);
3668                 if (card->hw.type == PC300_TE) {
3669                         iounmap(card->hw.falcbase);
3670                         release_mem_region(card->hw.falcphys, card->hw.falcsize);
3671                 }
3672                 for (i = 0; i < card->hw.nchan; i++)
3673                         if (card->chan[i].d.dev)
3674                                 free_netdev(card->chan[i].d.dev);
3675                 if (card->hw.irq)
3676                         free_irq(card->hw.irq, card);
3677                 kfree(card);
3678                 pci_disable_device(pdev);
3679         }
3680 }
3681
3682 static struct pci_driver cpc_driver = {
3683         .name           = "pc300",
3684         .id_table       = cpc_pci_dev_id,
3685         .probe          = cpc_init_one,
3686         .remove         = __devexit_p(cpc_remove_one),
3687 };
3688
3689 static int __init cpc_init(void)
3690 {
3691         return pci_register_driver(&cpc_driver);
3692 }
3693
3694 static void __exit cpc_cleanup_module(void)
3695 {
3696         pci_unregister_driver(&cpc_driver);
3697 }
3698
3699 module_init(cpc_init);
3700 module_exit(cpc_cleanup_module);
3701
3702 MODULE_DESCRIPTION("Cyclades-PC300 cards driver");
3703 MODULE_AUTHOR(  "Author: Ivan Passos <ivan@cyclades.com>\r\n"
3704                 "Maintainer: PC300 Maintainer <pc300@cyclades.com");
3705 MODULE_LICENSE("GPL");
3706