WAN: convert drivers to use built-in netdev_stats
[linux-2.6.git] / drivers / net / wan / pc300_drv.c
1 #define USE_PCI_CLOCK
2 static char rcsid[] = 
3 "Revision: 3.4.5 Date: 2002/03/07 ";
4
5 /*
6  * pc300.c      Cyclades-PC300(tm) Driver.
7  *
8  * Author:      Ivan Passos <ivan@cyclades.com>
9  * Maintainer:  PC300 Maintainer <pc300@cyclades.com>
10  *
11  * Copyright:   (c) 1999-2003 Cyclades Corp.
12  *
13  *      This program is free software; you can redistribute it and/or
14  *      modify it under the terms of the GNU General Public License
15  *      as published by the Free Software Foundation; either version
16  *      2 of the License, or (at your option) any later version.
17  *      
18  *      Using tabstop = 4.
19  * 
20  * $Log: pc300_drv.c,v $
21  * Revision 3.23  2002/03/20 13:58:40  henrique
22  * Fixed ortographic mistakes
23  *
24  * Revision 3.22  2002/03/13 16:56:56  henrique
25  * Take out the debug messages
26  *
27  * Revision 3.21  2002/03/07 14:17:09  henrique
28  * License data fixed
29  *
30  * Revision 3.20  2002/01/17 17:58:52  ivan
31  * Support for PC300-TE/M (PMC).
32  *
33  * Revision 3.19  2002/01/03 17:08:47  daniela
34  * Enables DMA reception when the SCA-II disables it improperly.
35  *
36  * Revision 3.18  2001/12/03 18:47:50  daniela
37  * Esthetic changes.
38  *
39  * Revision 3.17  2001/10/19 16:50:13  henrique
40  * Patch to kernel 2.4.12 and new generic hdlc.
41  *
42  * Revision 3.16  2001/10/16 15:12:31  regina
43  * clear statistics
44  *
45  * Revision 3.11 to 3.15  2001/10/11 20:26:04  daniela
46  * More DMA fixes for noisy lines.
47  * Return the size of bad frames in dma_get_rx_frame_size, so that the Rx buffer
48  * descriptors can be cleaned by dma_buf_read (called in cpc_net_rx).
49  * Renamed dma_start routine to rx_dma_start. Improved Rx statistics.
50  * Fixed BOF interrupt treatment. Created dma_start routine.
51  * Changed min and max to cpc_min and cpc_max.
52  *
53  * Revision 3.10  2001/08/06 12:01:51  regina
54  * Fixed problem in DSR_DE bit.
55  *
56  * Revision 3.9  2001/07/18 19:27:26  daniela
57  * Added some history comments.
58  *
59  * Revision 3.8  2001/07/12 13:11:19  regina
60  * bug fix - DCD-OFF in pc300 tty driver
61  *
62  * Revision 3.3 to 3.7  2001/07/06 15:00:20  daniela
63  * Removing kernel 2.4.3 and previous support.
64  * DMA transmission bug fix.
65  * MTU check in cpc_net_rx fixed.
66  * Boot messages reviewed.
67  * New configuration parameters (line code, CRC calculation and clock).
68  *
69  * Revision 3.2 2001/06/22 13:13:02  regina
70  * MLPPP implementation. Changed the header of message trace to include
71  * the device name. New format : "hdlcX[R/T]: ".
72  * Default configuration changed.
73  *
74  * Revision 3.1 2001/06/15 regina
75  * in cpc_queue_xmit, netif_stop_queue is called if don't have free descriptor
76  * upping major version number
77  *
78  * Revision 1.1.1.1  2001/06/13 20:25:04  daniela
79  * PC300 initial CVS version (3.4.0-pre1)
80  *
81  * Revision 3.0.1.2 2001/06/08 daniela
82  * Did some changes in the DMA programming implementation to avoid the 
83  * occurrence of a SCA-II bug when CDA is accessed during a DMA transfer.
84  *
85  * Revision 3.0.1.1 2001/05/02 daniela
86  * Added kernel 2.4.3 support.
87  * 
88  * Revision 3.0.1.0 2001/03/13 daniela, henrique
89  * Added Frame Relay Support.
90  * Driver now uses HDLC generic driver to provide protocol support.
91  * 
92  * Revision 3.0.0.8 2001/03/02 daniela
93  * Fixed ram size detection. 
94  * Changed SIOCGPC300CONF ioctl, to give hw information to pc300util.
95  * 
96  * Revision 3.0.0.7 2001/02/23 daniela
97  * netif_stop_queue called before the SCA-II transmition commands in 
98  * cpc_queue_xmit, and with interrupts disabled to avoid race conditions with 
99  * transmition interrupts.
100  * Fixed falc_check_status for Unframed E1.
101  * 
102  * Revision 3.0.0.6 2000/12/13 daniela
103  * Implemented pc300util support: trace, statistics, status and loopback
104  * tests for the PC300 TE boards.
105  * 
106  * Revision 3.0.0.5 2000/12/12 ivan
107  * Added support for Unframed E1.
108  * Implemented monitor mode.
109  * Fixed DCD sensitivity on the second channel.
110  * Driver now complies with new PCI kernel architecture.
111  *
112  * Revision 3.0.0.4 2000/09/28 ivan
113  * Implemented DCD sensitivity.
114  * Moved hardware-specific open to the end of cpc_open, to avoid race
115  * conditions with early reception interrupts.
116  * Included code for [request|release]_mem_region().
117  * Changed location of pc300.h .
118  * Minor code revision (contrib. of Jeff Garzik).
119  *
120  * Revision 3.0.0.3 2000/07/03 ivan
121  * Previous bugfix for the framing errors with external clock made X21
122  * boards stop working. This version fixes it.
123  *
124  * Revision 3.0.0.2 2000/06/23 ivan
125  * Revisited cpc_queue_xmit to prevent race conditions on Tx DMA buffer
126  * handling when Tx timeouts occur.
127  * Revisited Rx statistics.
128  * Fixed a bug in the SCA-II programming that would cause framing errors
129  * when external clock was configured.
130  *
131  * Revision 3.0.0.1 2000/05/26 ivan
132  * Added logic in the SCA interrupt handler so that no board can monopolize
133  * the driver.
134  * Request PLX I/O region, although driver doesn't use it, to avoid
135  * problems with other drivers accessing it.
136  *
137  * Revision 3.0.0.0 2000/05/15 ivan
138  * Did some changes in the DMA programming implementation to avoid the
139  * occurrence of a SCA-II bug in the second channel.
140  * Implemented workaround for PLX9050 bug that would cause a system lockup
141  * in certain systems, depending on the MMIO addresses allocated to the
142  * board.
143  * Fixed the FALC chip programming to avoid synchronization problems in the
144  * second channel (TE only).
145  * Implemented a cleaner and faster Tx DMA descriptor cleanup procedure in
146  * cpc_queue_xmit().
147  * Changed the built-in driver implementation so that the driver can use the
148  * general 'hdlcN' naming convention instead of proprietary device names.
149  * Driver load messages are now device-centric, instead of board-centric.
150  * Dynamic allocation of net_device structures.
151  * Code is now compliant with the new module interface (module_[init|exit]).
152  * Make use of the PCI helper functions to access PCI resources.
153  *
154  * Revision 2.0.0.0 2000/04/15 ivan
155  * Added support for the PC300/TE boards (T1/FT1/E1/FE1).
156  *
157  * Revision 1.1.0.0 2000/02/28 ivan
158  * Major changes in the driver architecture.
159  * Softnet compliancy implemented.
160  * Driver now reports physical instead of virtual memory addresses.
161  * Added cpc_change_mtu function.
162  *
163  * Revision 1.0.0.0 1999/12/16 ivan
164  * First official release.
165  * Support for 1- and 2-channel boards (which use distinct PCI Device ID's).
166  * Support for monolythic installation (i.e., drv built into the kernel).
167  * X.25 additional checking when lapb_[dis]connect_request returns an error.
168  * SCA programming now covers X.21 as well.
169  *
170  * Revision 0.3.1.0 1999/11/18 ivan
171  * Made X.25 support configuration-dependent (as it depends on external 
172  * modules to work).
173  * Changed X.25-specific function names to comply with adopted convention.
174  * Fixed typos in X.25 functions that would cause compile errors (Daniela).
175  * Fixed bug in ch_config that would disable interrupts on a previously 
176  * enabled channel if the other channel on the same board was enabled later.
177  *
178  * Revision 0.3.0.0 1999/11/16 daniela
179  * X.25 support.
180  *
181  * Revision 0.2.3.0 1999/11/15 ivan
182  * Function cpc_ch_status now provides more detailed information.
183  * Added support for X.21 clock configuration.
184  * Changed TNR1 setting in order to prevent Tx FIFO overaccesses by the SCA.
185  * Now using PCI clock instead of internal oscillator clock for the SCA.
186  *
187  * Revision 0.2.2.0 1999/11/10 ivan
188  * Changed the *_dma_buf_check functions so that they would print only 
189  * the useful info instead of the whole buffer descriptor bank.
190  * Fixed bug in cpc_queue_xmit that would eventually crash the system 
191  * in case of a packet drop.
192  * Implemented TX underrun handling.
193  * Improved SCA fine tuning to boost up its performance.
194  *
195  * Revision 0.2.1.0 1999/11/03 ivan
196  * Added functions *dma_buf_pt_init to allow independent initialization 
197  * of the next-descr. and DMA buffer pointers on the DMA descriptors.
198  * Kernel buffer release and tbusy clearing is now done in the interrupt 
199  * handler.
200  * Fixed bug in cpc_open that would cause an interface reopen to fail.
201  * Added a protocol-specific code section in cpc_net_rx.
202  * Removed printk level defs (they might be added back after the beta phase).
203  *
204  * Revision 0.2.0.0 1999/10/28 ivan
205  * Revisited the code so that new protocols can be easily added / supported. 
206  *
207  * Revision 0.1.0.1 1999/10/20 ivan
208  * Mostly "esthetic" changes.
209  *
210  * Revision 0.1.0.0 1999/10/11 ivan
211  * Initial version.
212  *
213  */
214
215 #include <linux/module.h>
216 #include <linux/kernel.h>
217 #include <linux/mm.h>
218 #include <linux/ioport.h>
219 #include <linux/pci.h>
220 #include <linux/errno.h>
221 #include <linux/string.h>
222 #include <linux/init.h>
223 #include <linux/delay.h>
224 #include <linux/net.h>
225 #include <linux/skbuff.h>
226 #include <linux/if_arp.h>
227 #include <linux/netdevice.h>
228 #include <linux/spinlock.h>
229 #include <linux/if.h>
230
231 #include <net/syncppp.h>
232 #include <net/arp.h>
233
234 #include <asm/io.h>
235 #include <asm/uaccess.h>
236
237 #include "pc300.h"
238
239 #define CPC_LOCK(card,flags)            \
240                 do {                                            \
241                 spin_lock_irqsave(&card->card_lock, flags);     \
242                 } while (0)
243
244 #define CPC_UNLOCK(card,flags)                  \
245                 do {                                                    \
246                 spin_unlock_irqrestore(&card->card_lock, flags);        \
247                 } while (0)
248
249 #undef  PC300_DEBUG_PCI
250 #undef  PC300_DEBUG_INTR
251 #undef  PC300_DEBUG_TX
252 #undef  PC300_DEBUG_RX
253 #undef  PC300_DEBUG_OTHER
254
255 static struct pci_device_id cpc_pci_dev_id[] __devinitdata = {
256         /* PC300/RSV or PC300/X21, 2 chan */
257         {0x120e, 0x300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x300},
258         /* PC300/RSV or PC300/X21, 1 chan */
259         {0x120e, 0x301, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x301},
260         /* PC300/TE, 2 chan */
261         {0x120e, 0x310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x310},
262         /* PC300/TE, 1 chan */
263         {0x120e, 0x311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x311},
264         /* PC300/TE-M, 2 chan */
265         {0x120e, 0x320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x320},
266         /* PC300/TE-M, 1 chan */
267         {0x120e, 0x321, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x321},
268         /* End of table */
269         {0,},
270 };
271 MODULE_DEVICE_TABLE(pci, cpc_pci_dev_id);
272
273 #ifndef cpc_min
274 #define cpc_min(a,b)    (((a)<(b))?(a):(b))
275 #endif
276 #ifndef cpc_max
277 #define cpc_max(a,b)    (((a)>(b))?(a):(b))
278 #endif
279
280 /* prototypes */
281 static void tx_dma_buf_pt_init(pc300_t *, int);
282 static void tx_dma_buf_init(pc300_t *, int);
283 static void rx_dma_buf_pt_init(pc300_t *, int);
284 static void rx_dma_buf_init(pc300_t *, int);
285 static void tx_dma_buf_check(pc300_t *, int);
286 static void rx_dma_buf_check(pc300_t *, int);
287 static irqreturn_t cpc_intr(int, void *);
288 static int clock_rate_calc(uclong, uclong, int *);
289 static uclong detect_ram(pc300_t *);
290 static void plx_init(pc300_t *);
291 static void cpc_trace(struct net_device *, struct sk_buff *, char);
292 static int cpc_attach(struct net_device *, unsigned short, unsigned short);
293 static int cpc_close(struct net_device *dev);
294
295 #ifdef CONFIG_PC300_MLPPP
296 void cpc_tty_init(pc300dev_t * dev);
297 void cpc_tty_unregister_service(pc300dev_t * pc300dev);
298 void cpc_tty_receive(pc300dev_t * pc300dev);
299 void cpc_tty_trigger_poll(pc300dev_t * pc300dev);
300 void cpc_tty_reset_var(void);
301 #endif
302
303 /************************/
304 /***   DMA Routines   ***/
305 /************************/
306 static void tx_dma_buf_pt_init(pc300_t * card, int ch)
307 {
308         int i;
309         int ch_factor = ch * N_DMA_TX_BUF;
310         volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
311                                        + DMA_TX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
312
313         for (i = 0; i < N_DMA_TX_BUF; i++, ptdescr++) {
314                 cpc_writel(&ptdescr->next, (uclong) (DMA_TX_BD_BASE +
315                         (ch_factor + ((i + 1) & (N_DMA_TX_BUF - 1))) * sizeof(pcsca_bd_t)));
316                 cpc_writel(&ptdescr->ptbuf, 
317                                                 (uclong) (DMA_TX_BASE + (ch_factor + i) * BD_DEF_LEN));
318         }
319 }
320
321 static void tx_dma_buf_init(pc300_t * card, int ch)
322 {
323         int i;
324         int ch_factor = ch * N_DMA_TX_BUF;
325         volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
326                                + DMA_TX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
327
328         for (i = 0; i < N_DMA_TX_BUF; i++, ptdescr++) {
329                 memset_io(ptdescr, 0, sizeof(pcsca_bd_t));
330                 cpc_writew(&ptdescr->len, 0);
331                 cpc_writeb(&ptdescr->status, DST_OSB);
332         }
333         tx_dma_buf_pt_init(card, ch);
334 }
335
336 static void rx_dma_buf_pt_init(pc300_t * card, int ch)
337 {
338         int i;
339         int ch_factor = ch * N_DMA_RX_BUF;
340         volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
341                                        + DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
342
343         for (i = 0; i < N_DMA_RX_BUF; i++, ptdescr++) {
344                 cpc_writel(&ptdescr->next, (uclong) (DMA_RX_BD_BASE +
345                 (ch_factor + ((i + 1) & (N_DMA_RX_BUF - 1))) * sizeof(pcsca_bd_t)));
346                 cpc_writel(&ptdescr->ptbuf,
347                            (uclong) (DMA_RX_BASE + (ch_factor + i) * BD_DEF_LEN));
348         }
349 }
350
351 static void rx_dma_buf_init(pc300_t * card, int ch)
352 {
353         int i;
354         int ch_factor = ch * N_DMA_RX_BUF;
355         volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
356                                        + DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
357
358         for (i = 0; i < N_DMA_RX_BUF; i++, ptdescr++) {
359                 memset_io(ptdescr, 0, sizeof(pcsca_bd_t));
360                 cpc_writew(&ptdescr->len, 0);
361                 cpc_writeb(&ptdescr->status, 0);
362         }
363         rx_dma_buf_pt_init(card, ch);
364 }
365
366 static void tx_dma_buf_check(pc300_t * card, int ch)
367 {
368         volatile pcsca_bd_t __iomem *ptdescr;
369         int i;
370         ucshort first_bd = card->chan[ch].tx_first_bd;
371         ucshort next_bd = card->chan[ch].tx_next_bd;
372
373         printk("#CH%d: f_bd = %d(0x%08zx), n_bd = %d(0x%08zx)\n", ch,
374                first_bd, TX_BD_ADDR(ch, first_bd),
375                next_bd, TX_BD_ADDR(ch, next_bd));
376         for (i = first_bd,
377              ptdescr = (card->hw.rambase + TX_BD_ADDR(ch, first_bd));
378              i != ((next_bd + 1) & (N_DMA_TX_BUF - 1));
379              i = (i + 1) & (N_DMA_TX_BUF - 1), 
380                  ptdescr = (card->hw.rambase + TX_BD_ADDR(ch, i))) {
381                 printk("\n CH%d TX%d: next=0x%x, ptbuf=0x%x, ST=0x%x, len=%d",
382                        ch, i, cpc_readl(&ptdescr->next),
383                        cpc_readl(&ptdescr->ptbuf),
384                        cpc_readb(&ptdescr->status), cpc_readw(&ptdescr->len));
385         }
386         printk("\n");
387 }
388
389 #ifdef  PC300_DEBUG_OTHER
390 /* Show all TX buffer descriptors */
391 static void tx1_dma_buf_check(pc300_t * card, int ch)
392 {
393         volatile pcsca_bd_t __iomem *ptdescr;
394         int i;
395         ucshort first_bd = card->chan[ch].tx_first_bd;
396         ucshort next_bd = card->chan[ch].tx_next_bd;
397         uclong scabase = card->hw.scabase;
398
399         printk ("\nnfree_tx_bd = %d \n", card->chan[ch].nfree_tx_bd);
400         printk("#CH%d: f_bd = %d(0x%08x), n_bd = %d(0x%08x)\n", ch,
401                first_bd, TX_BD_ADDR(ch, first_bd),
402                next_bd, TX_BD_ADDR(ch, next_bd));
403         printk("TX_CDA=0x%08x, TX_EDA=0x%08x\n",
404                cpc_readl(scabase + DTX_REG(CDAL, ch)),
405                cpc_readl(scabase + DTX_REG(EDAL, ch)));
406         for (i = 0; i < N_DMA_TX_BUF; i++) {
407                 ptdescr = (card->hw.rambase + TX_BD_ADDR(ch, i));
408                 printk("\n CH%d TX%d: next=0x%x, ptbuf=0x%x, ST=0x%x, len=%d",
409                        ch, i, cpc_readl(&ptdescr->next),
410                        cpc_readl(&ptdescr->ptbuf),
411                        cpc_readb(&ptdescr->status), cpc_readw(&ptdescr->len));
412         }
413         printk("\n");
414 }
415 #endif
416                          
417 static void rx_dma_buf_check(pc300_t * card, int ch)
418 {
419         volatile pcsca_bd_t __iomem *ptdescr;
420         int i;
421         ucshort first_bd = card->chan[ch].rx_first_bd;
422         ucshort last_bd = card->chan[ch].rx_last_bd;
423         int ch_factor;
424
425         ch_factor = ch * N_DMA_RX_BUF;
426         printk("#CH%d: f_bd = %d, l_bd = %d\n", ch, first_bd, last_bd);
427         for (i = 0, ptdescr = (card->hw.rambase +
428                                               DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
429              i < N_DMA_RX_BUF; i++, ptdescr++) {
430                 if (cpc_readb(&ptdescr->status) & DST_OSB)
431                         printk ("\n CH%d RX%d: next=0x%x, ptbuf=0x%x, ST=0x%x, len=%d",
432                                  ch, i, cpc_readl(&ptdescr->next),
433                                  cpc_readl(&ptdescr->ptbuf),
434                                  cpc_readb(&ptdescr->status),
435                                  cpc_readw(&ptdescr->len));
436         }
437         printk("\n");
438 }
439
440 static int dma_get_rx_frame_size(pc300_t * card, int ch)
441 {
442         volatile pcsca_bd_t __iomem *ptdescr;
443         ucshort first_bd = card->chan[ch].rx_first_bd;
444         int rcvd = 0;
445         volatile ucchar status;
446
447         ptdescr = (card->hw.rambase + RX_BD_ADDR(ch, first_bd));
448         while ((status = cpc_readb(&ptdescr->status)) & DST_OSB) {
449                 rcvd += cpc_readw(&ptdescr->len);
450                 first_bd = (first_bd + 1) & (N_DMA_RX_BUF - 1);
451                 if ((status & DST_EOM) || (first_bd == card->chan[ch].rx_last_bd)) {
452                         /* Return the size of a good frame or incomplete bad frame 
453                         * (dma_buf_read will clean the buffer descriptors in this case). */
454                         return (rcvd);
455                 }
456                 ptdescr = (card->hw.rambase + cpc_readl(&ptdescr->next));
457         }
458         return (-1);
459 }
460
461 /*
462  * dma_buf_write: writes a frame to the Tx DMA buffers
463  * NOTE: this function writes one frame at a time.
464  */
465 static int dma_buf_write(pc300_t * card, int ch, ucchar * ptdata, int len)
466 {
467         int i, nchar;
468         volatile pcsca_bd_t __iomem *ptdescr;
469         int tosend = len;
470         ucchar nbuf = ((len - 1) / BD_DEF_LEN) + 1;
471
472         if (nbuf >= card->chan[ch].nfree_tx_bd) {
473                 return -ENOMEM;
474         }
475
476         for (i = 0; i < nbuf; i++) {
477                 ptdescr = (card->hw.rambase +
478                                           TX_BD_ADDR(ch, card->chan[ch].tx_next_bd));
479                 nchar = cpc_min(BD_DEF_LEN, tosend);
480                 if (cpc_readb(&ptdescr->status) & DST_OSB) {
481                         memcpy_toio((card->hw.rambase + cpc_readl(&ptdescr->ptbuf)),
482                                     &ptdata[len - tosend], nchar);
483                         cpc_writew(&ptdescr->len, nchar);
484                         card->chan[ch].nfree_tx_bd--;
485                         if ((i + 1) == nbuf) {
486                                 /* This must be the last BD to be used */
487                                 cpc_writeb(&ptdescr->status, DST_EOM);
488                         } else {
489                                 cpc_writeb(&ptdescr->status, 0);
490                         }
491                 } else {
492                         return -ENOMEM;
493                 }
494                 tosend -= nchar;
495                 card->chan[ch].tx_next_bd =
496                         (card->chan[ch].tx_next_bd + 1) & (N_DMA_TX_BUF - 1);
497         }
498         /* If it gets to here, it means we have sent the whole frame */
499         return 0;
500 }
501
502 /*
503  * dma_buf_read: reads a frame from the Rx DMA buffers
504  * NOTE: this function reads one frame at a time.
505  */
506 static int dma_buf_read(pc300_t * card, int ch, struct sk_buff *skb)
507 {
508         int nchar;
509         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
510         volatile pcsca_bd_t __iomem *ptdescr;
511         int rcvd = 0;
512         volatile ucchar status;
513
514         ptdescr = (card->hw.rambase +
515                                   RX_BD_ADDR(ch, chan->rx_first_bd));
516         while ((status = cpc_readb(&ptdescr->status)) & DST_OSB) {
517                 nchar = cpc_readw(&ptdescr->len);
518                 if ((status & (DST_OVR | DST_CRC | DST_RBIT | DST_SHRT | DST_ABT))
519                     || (nchar > BD_DEF_LEN)) {
520
521                         if (nchar > BD_DEF_LEN)
522                                 status |= DST_RBIT;
523                         rcvd = -status;
524                         /* Discard remaining descriptors used by the bad frame */
525                         while (chan->rx_first_bd != chan->rx_last_bd) {
526                                 cpc_writeb(&ptdescr->status, 0);
527                                 chan->rx_first_bd = (chan->rx_first_bd+1) & (N_DMA_RX_BUF-1);
528                                 if (status & DST_EOM)
529                                         break;
530                                 ptdescr = (card->hw.rambase +
531                                                           cpc_readl(&ptdescr->next));
532                                 status = cpc_readb(&ptdescr->status);
533                         }
534                         break;
535                 }
536                 if (nchar != 0) {
537                         if (skb) {
538                                 memcpy_fromio(skb_put(skb, nchar),
539                                  (card->hw.rambase+cpc_readl(&ptdescr->ptbuf)),nchar);
540                         }
541                         rcvd += nchar;
542                 }
543                 cpc_writeb(&ptdescr->status, 0);
544                 cpc_writeb(&ptdescr->len, 0);
545                 chan->rx_first_bd = (chan->rx_first_bd + 1) & (N_DMA_RX_BUF - 1);
546
547                 if (status & DST_EOM)
548                         break;
549
550                 ptdescr = (card->hw.rambase + cpc_readl(&ptdescr->next));
551         }
552
553         if (rcvd != 0) {
554                 /* Update pointer */
555                 chan->rx_last_bd = (chan->rx_first_bd - 1) & (N_DMA_RX_BUF - 1);
556                 /* Update EDA */
557                 cpc_writel(card->hw.scabase + DRX_REG(EDAL, ch),
558                            RX_BD_ADDR(ch, chan->rx_last_bd));
559         }
560         return (rcvd);
561 }
562
563 static void tx_dma_stop(pc300_t * card, int ch)
564 {
565         void __iomem *scabase = card->hw.scabase;
566         ucchar drr_ena_bit = 1 << (5 + 2 * ch);
567         ucchar drr_rst_bit = 1 << (1 + 2 * ch);
568
569         /* Disable DMA */
570         cpc_writeb(scabase + DRR, drr_ena_bit);
571         cpc_writeb(scabase + DRR, drr_rst_bit & ~drr_ena_bit);
572 }
573
574 static void rx_dma_stop(pc300_t * card, int ch)
575 {
576         void __iomem *scabase = card->hw.scabase;
577         ucchar drr_ena_bit = 1 << (4 + 2 * ch);
578         ucchar drr_rst_bit = 1 << (2 * ch);
579
580         /* Disable DMA */
581         cpc_writeb(scabase + DRR, drr_ena_bit);
582         cpc_writeb(scabase + DRR, drr_rst_bit & ~drr_ena_bit);
583 }
584
585 static void rx_dma_start(pc300_t * card, int ch)
586 {
587         void __iomem *scabase = card->hw.scabase;
588         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
589         
590         /* Start DMA */
591         cpc_writel(scabase + DRX_REG(CDAL, ch),
592                    RX_BD_ADDR(ch, chan->rx_first_bd));
593         if (cpc_readl(scabase + DRX_REG(CDAL,ch)) !=
594                                   RX_BD_ADDR(ch, chan->rx_first_bd)) {
595                 cpc_writel(scabase + DRX_REG(CDAL, ch),
596                                    RX_BD_ADDR(ch, chan->rx_first_bd));
597         }
598         cpc_writel(scabase + DRX_REG(EDAL, ch),
599                    RX_BD_ADDR(ch, chan->rx_last_bd));
600         cpc_writew(scabase + DRX_REG(BFLL, ch), BD_DEF_LEN);
601         cpc_writeb(scabase + DSR_RX(ch), DSR_DE);
602         if (!(cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
603         cpc_writeb(scabase + DSR_RX(ch), DSR_DE);
604         }
605 }
606
607 /*************************/
608 /***   FALC Routines   ***/
609 /*************************/
610 static void falc_issue_cmd(pc300_t * card, int ch, ucchar cmd)
611 {
612         void __iomem *falcbase = card->hw.falcbase;
613         unsigned long i = 0;
614
615         while (cpc_readb(falcbase + F_REG(SIS, ch)) & SIS_CEC) {
616                 if (i++ >= PC300_FALC_MAXLOOP) {
617                         printk("%s: FALC command locked(cmd=0x%x).\n",
618                                card->chan[ch].d.name, cmd);
619                         break;
620                 }
621         }
622         cpc_writeb(falcbase + F_REG(CMDR, ch), cmd);
623 }
624
625 static void falc_intr_enable(pc300_t * card, int ch)
626 {
627         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
628         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
629         falc_t *pfalc = (falc_t *) & chan->falc;
630         void __iomem *falcbase = card->hw.falcbase;
631
632         /* Interrupt pins are open-drain */
633         cpc_writeb(falcbase + F_REG(IPC, ch),
634                    cpc_readb(falcbase + F_REG(IPC, ch)) & ~IPC_IC0);
635         /* Conters updated each second */
636         cpc_writeb(falcbase + F_REG(FMR1, ch),
637                    cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_ECM);
638         /* Enable SEC and ES interrupts  */
639         cpc_writeb(falcbase + F_REG(IMR3, ch),
640                    cpc_readb(falcbase + F_REG(IMR3, ch)) & ~(IMR3_SEC | IMR3_ES));
641         if (conf->fr_mode == PC300_FR_UNFRAMED) {
642                 cpc_writeb(falcbase + F_REG(IMR4, ch),
643                            cpc_readb(falcbase + F_REG(IMR4, ch)) & ~(IMR4_LOS));
644         } else {
645                 cpc_writeb(falcbase + F_REG(IMR4, ch),
646                            cpc_readb(falcbase + F_REG(IMR4, ch)) &
647                            ~(IMR4_LFA | IMR4_AIS | IMR4_LOS | IMR4_SLIP));
648         }
649         if (conf->media == IF_IFACE_T1) {
650                 cpc_writeb(falcbase + F_REG(IMR3, ch),
651                            cpc_readb(falcbase + F_REG(IMR3, ch)) & ~IMR3_LLBSC);
652         } else {
653                 cpc_writeb(falcbase + F_REG(IPC, ch),
654                            cpc_readb(falcbase + F_REG(IPC, ch)) | IPC_SCI);
655                 if (conf->fr_mode == PC300_FR_UNFRAMED) {
656                         cpc_writeb(falcbase + F_REG(IMR2, ch),
657                                    cpc_readb(falcbase + F_REG(IMR2, ch)) & ~(IMR2_LOS));
658                 } else {
659                         cpc_writeb(falcbase + F_REG(IMR2, ch),
660                                    cpc_readb(falcbase + F_REG(IMR2, ch)) &
661                                    ~(IMR2_FAR | IMR2_LFA | IMR2_AIS | IMR2_LOS));
662                         if (pfalc->multiframe_mode) {
663                                 cpc_writeb(falcbase + F_REG(IMR2, ch),
664                                            cpc_readb(falcbase + F_REG(IMR2, ch)) & 
665                                            ~(IMR2_T400MS | IMR2_MFAR));
666                         } else {
667                                 cpc_writeb(falcbase + F_REG(IMR2, ch),
668                                            cpc_readb(falcbase + F_REG(IMR2, ch)) | 
669                                            IMR2_T400MS | IMR2_MFAR);
670                         }
671                 }
672         }
673 }
674
675 static void falc_open_timeslot(pc300_t * card, int ch, int timeslot)
676 {
677         void __iomem *falcbase = card->hw.falcbase;
678         ucchar tshf = card->chan[ch].falc.offset;
679
680         cpc_writeb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch),
681                    cpc_readb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch)) & 
682                         ~(0x80 >> ((timeslot - tshf) & 0x07)));
683         cpc_writeb(falcbase + F_REG((TTR1 + timeslot / 8), ch),
684                    cpc_readb(falcbase + F_REG((TTR1 + timeslot / 8), ch)) | 
685                         (0x80 >> (timeslot & 0x07)));
686         cpc_writeb(falcbase + F_REG((RTR1 + timeslot / 8), ch),
687                    cpc_readb(falcbase + F_REG((RTR1 + timeslot / 8), ch)) | 
688                         (0x80 >> (timeslot & 0x07)));
689 }
690
691 static void falc_close_timeslot(pc300_t * card, int ch, int timeslot)
692 {
693         void __iomem *falcbase = card->hw.falcbase;
694         ucchar tshf = card->chan[ch].falc.offset;
695
696         cpc_writeb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch),
697                    cpc_readb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch)) | 
698                    (0x80 >> ((timeslot - tshf) & 0x07)));
699         cpc_writeb(falcbase + F_REG((TTR1 + timeslot / 8), ch),
700                    cpc_readb(falcbase + F_REG((TTR1 + timeslot / 8), ch)) & 
701                    ~(0x80 >> (timeslot & 0x07)));
702         cpc_writeb(falcbase + F_REG((RTR1 + timeslot / 8), ch),
703                    cpc_readb(falcbase + F_REG((RTR1 + timeslot / 8), ch)) & 
704                    ~(0x80 >> (timeslot & 0x07)));
705 }
706
707 static void falc_close_all_timeslots(pc300_t * card, int ch)
708 {
709         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
710         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
711         void __iomem *falcbase = card->hw.falcbase;
712
713         cpc_writeb(falcbase + F_REG(ICB1, ch), 0xff);
714         cpc_writeb(falcbase + F_REG(TTR1, ch), 0);
715         cpc_writeb(falcbase + F_REG(RTR1, ch), 0);
716         cpc_writeb(falcbase + F_REG(ICB2, ch), 0xff);
717         cpc_writeb(falcbase + F_REG(TTR2, ch), 0);
718         cpc_writeb(falcbase + F_REG(RTR2, ch), 0);
719         cpc_writeb(falcbase + F_REG(ICB3, ch), 0xff);
720         cpc_writeb(falcbase + F_REG(TTR3, ch), 0);
721         cpc_writeb(falcbase + F_REG(RTR3, ch), 0);
722         if (conf->media == IF_IFACE_E1) {
723                 cpc_writeb(falcbase + F_REG(ICB4, ch), 0xff);
724                 cpc_writeb(falcbase + F_REG(TTR4, ch), 0);
725                 cpc_writeb(falcbase + F_REG(RTR4, ch), 0);
726         }
727 }
728
729 static void falc_open_all_timeslots(pc300_t * card, int ch)
730 {
731         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
732         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
733         void __iomem *falcbase = card->hw.falcbase;
734
735         cpc_writeb(falcbase + F_REG(ICB1, ch), 0);
736         if (conf->fr_mode == PC300_FR_UNFRAMED) {
737                 cpc_writeb(falcbase + F_REG(TTR1, ch), 0xff);
738                 cpc_writeb(falcbase + F_REG(RTR1, ch), 0xff);
739         } else {
740                 /* Timeslot 0 is never enabled */
741                 cpc_writeb(falcbase + F_REG(TTR1, ch), 0x7f);
742                 cpc_writeb(falcbase + F_REG(RTR1, ch), 0x7f);
743         }
744         cpc_writeb(falcbase + F_REG(ICB2, ch), 0);
745         cpc_writeb(falcbase + F_REG(TTR2, ch), 0xff);
746         cpc_writeb(falcbase + F_REG(RTR2, ch), 0xff);
747         cpc_writeb(falcbase + F_REG(ICB3, ch), 0);
748         cpc_writeb(falcbase + F_REG(TTR3, ch), 0xff);
749         cpc_writeb(falcbase + F_REG(RTR3, ch), 0xff);
750         if (conf->media == IF_IFACE_E1) {
751                 cpc_writeb(falcbase + F_REG(ICB4, ch), 0);
752                 cpc_writeb(falcbase + F_REG(TTR4, ch), 0xff);
753                 cpc_writeb(falcbase + F_REG(RTR4, ch), 0xff);
754         } else {
755                 cpc_writeb(falcbase + F_REG(ICB4, ch), 0xff);
756                 cpc_writeb(falcbase + F_REG(TTR4, ch), 0x80);
757                 cpc_writeb(falcbase + F_REG(RTR4, ch), 0x80);
758         }
759 }
760
761 static void falc_init_timeslot(pc300_t * card, int ch)
762 {
763         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
764         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
765         falc_t *pfalc = (falc_t *) & chan->falc;
766         int tslot;
767
768         for (tslot = 0; tslot < pfalc->num_channels; tslot++) {
769                 if (conf->tslot_bitmap & (1 << tslot)) {
770                         // Channel enabled
771                         falc_open_timeslot(card, ch, tslot + 1);
772                 } else {
773                         // Channel disabled
774                         falc_close_timeslot(card, ch, tslot + 1);
775                 }
776         }
777 }
778
779 static void falc_enable_comm(pc300_t * card, int ch)
780 {
781         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
782         falc_t *pfalc = (falc_t *) & chan->falc;
783
784         if (pfalc->full_bandwidth) {
785                 falc_open_all_timeslots(card, ch);
786         } else {
787                 falc_init_timeslot(card, ch);
788         }
789         // CTS/DCD ON
790         cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
791                    cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) &
792                    ~((CPLD_REG1_FALC_DCD | CPLD_REG1_FALC_CTS) << (2 * ch)));
793 }
794
795 static void falc_disable_comm(pc300_t * card, int ch)
796 {
797         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
798         falc_t *pfalc = (falc_t *) & chan->falc;
799
800         if (pfalc->loop_active != 2) {
801                 falc_close_all_timeslots(card, ch);
802         }
803         // CTS/DCD OFF
804         cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
805                    cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
806                    ((CPLD_REG1_FALC_DCD | CPLD_REG1_FALC_CTS) << (2 * ch)));
807 }
808
809 static void falc_init_t1(pc300_t * card, int ch)
810 {
811         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
812         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
813         falc_t *pfalc = (falc_t *) & chan->falc;
814         void __iomem *falcbase = card->hw.falcbase;
815         ucchar dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0);
816
817         /* Switch to T1 mode (PCM 24) */
818         cpc_writeb(falcbase + F_REG(FMR1, ch), FMR1_PMOD);
819
820         /* Wait 20 us for setup */
821         udelay(20);
822
823         /* Transmit Buffer Size (1 frame) */
824         cpc_writeb(falcbase + F_REG(SIC1, ch), SIC1_XBS0);
825
826         /* Clock mode */
827         if (conf->phys_settings.clock_type == CLOCK_INT) { /* Master mode */
828                 cpc_writeb(falcbase + F_REG(LIM0, ch),
829                            cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_MAS);
830         } else { /* Slave mode */
831                 cpc_writeb(falcbase + F_REG(LIM0, ch),
832                            cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_MAS);
833                 cpc_writeb(falcbase + F_REG(LOOP, ch),
834                            cpc_readb(falcbase + F_REG(LOOP, ch)) & ~LOOP_RTM);
835         }
836
837         cpc_writeb(falcbase + F_REG(IPC, ch), IPC_SCI);
838         cpc_writeb(falcbase + F_REG(FMR0, ch),
839                    cpc_readb(falcbase + F_REG(FMR0, ch)) &
840                    ~(FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1));
841
842         switch (conf->lcode) {
843                 case PC300_LC_AMI:
844                         cpc_writeb(falcbase + F_REG(FMR0, ch),
845                                    cpc_readb(falcbase + F_REG(FMR0, ch)) |
846                                    FMR0_XC1 | FMR0_RC1);
847                         /* Clear Channel register to ON for all channels */
848                         cpc_writeb(falcbase + F_REG(CCB1, ch), 0xff);
849                         cpc_writeb(falcbase + F_REG(CCB2, ch), 0xff);
850                         cpc_writeb(falcbase + F_REG(CCB3, ch), 0xff);
851                         break;
852
853                 case PC300_LC_B8ZS:
854                         cpc_writeb(falcbase + F_REG(FMR0, ch),
855                                    cpc_readb(falcbase + F_REG(FMR0, ch)) |
856                                    FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1);
857                         break;
858
859                 case PC300_LC_NRZ:
860                         cpc_writeb(falcbase + F_REG(FMR0, ch),
861                                    cpc_readb(falcbase + F_REG(FMR0, ch)) | 0x00);
862                         break;
863         }
864
865         cpc_writeb(falcbase + F_REG(LIM0, ch),
866                    cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_ELOS);
867         cpc_writeb(falcbase + F_REG(LIM0, ch),
868                    cpc_readb(falcbase + F_REG(LIM0, ch)) & ~(LIM0_SCL1 | LIM0_SCL0));
869         /* Set interface mode to 2 MBPS */
870         cpc_writeb(falcbase + F_REG(FMR1, ch),
871                    cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_IMOD);
872
873         switch (conf->fr_mode) {
874                 case PC300_FR_ESF:
875                         pfalc->multiframe_mode = 0;
876                         cpc_writeb(falcbase + F_REG(FMR4, ch),
877                                    cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_FM1);
878                         cpc_writeb(falcbase + F_REG(FMR1, ch),
879                                    cpc_readb(falcbase + F_REG(FMR1, ch)) | 
880                                    FMR1_CRC | FMR1_EDL);
881                         cpc_writeb(falcbase + F_REG(XDL1, ch), 0);
882                         cpc_writeb(falcbase + F_REG(XDL2, ch), 0);
883                         cpc_writeb(falcbase + F_REG(XDL3, ch), 0);
884                         cpc_writeb(falcbase + F_REG(FMR0, ch),
885                                    cpc_readb(falcbase + F_REG(FMR0, ch)) & ~FMR0_SRAF);
886                         cpc_writeb(falcbase + F_REG(FMR2, ch),
887                                    cpc_readb(falcbase + F_REG(FMR2,ch)) | FMR2_MCSP | FMR2_SSP);
888                         break;
889
890                 case PC300_FR_D4:
891                         pfalc->multiframe_mode = 1;
892                         cpc_writeb(falcbase + F_REG(FMR4, ch),
893                                    cpc_readb(falcbase + F_REG(FMR4, ch)) &
894                                    ~(FMR4_FM1 | FMR4_FM0));
895                         cpc_writeb(falcbase + F_REG(FMR0, ch),
896                                    cpc_readb(falcbase + F_REG(FMR0, ch)) | FMR0_SRAF);
897                         cpc_writeb(falcbase + F_REG(FMR2, ch),
898                                    cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_SSP);
899                         break;
900         }
901
902         /* Enable Automatic Resynchronization */
903         cpc_writeb(falcbase + F_REG(FMR4, ch),
904                    cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_AUTO);
905
906         /* Transmit Automatic Remote Alarm */
907         cpc_writeb(falcbase + F_REG(FMR2, ch),
908                    cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);
909
910         /* Channel translation mode 1 : one to one */
911         cpc_writeb(falcbase + F_REG(FMR1, ch),
912                    cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_CTM);
913
914         /* No signaling */
915         cpc_writeb(falcbase + F_REG(FMR1, ch),
916                    cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_SIGM);
917         cpc_writeb(falcbase + F_REG(FMR5, ch),
918                    cpc_readb(falcbase + F_REG(FMR5, ch)) &
919                    ~(FMR5_EIBR | FMR5_SRS));
920         cpc_writeb(falcbase + F_REG(CCR1, ch), 0);
921
922         cpc_writeb(falcbase + F_REG(LIM1, ch),
923                    cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RIL0 | LIM1_RIL1);
924
925         switch (conf->lbo) {
926                         /* Provides proper Line Build Out */
927                 case PC300_LBO_0_DB:
928                         cpc_writeb(falcbase + F_REG(LIM2, ch), (LIM2_LOS1 | dja));
929                         cpc_writeb(falcbase + F_REG(XPM0, ch), 0x5a);
930                         cpc_writeb(falcbase + F_REG(XPM1, ch), 0x8f);
931                         cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
932                         break;
933                 case PC300_LBO_7_5_DB:
934                         cpc_writeb(falcbase + F_REG(LIM2, ch), (0x40 | LIM2_LOS1 | dja));
935                         cpc_writeb(falcbase + F_REG(XPM0, ch), 0x11);
936                         cpc_writeb(falcbase + F_REG(XPM1, ch), 0x02);
937                         cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
938                         break;
939                 case PC300_LBO_15_DB:
940                         cpc_writeb(falcbase + F_REG(LIM2, ch), (0x80 | LIM2_LOS1 | dja));
941                         cpc_writeb(falcbase + F_REG(XPM0, ch), 0x8e);
942                         cpc_writeb(falcbase + F_REG(XPM1, ch), 0x01);
943                         cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
944                         break;
945                 case PC300_LBO_22_5_DB:
946                         cpc_writeb(falcbase + F_REG(LIM2, ch), (0xc0 | LIM2_LOS1 | dja));
947                         cpc_writeb(falcbase + F_REG(XPM0, ch), 0x09);
948                         cpc_writeb(falcbase + F_REG(XPM1, ch), 0x01);
949                         cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
950                         break;
951         }
952
953         /* Transmit Clock-Slot Offset */
954         cpc_writeb(falcbase + F_REG(XC0, ch),
955                    cpc_readb(falcbase + F_REG(XC0, ch)) | 0x01);
956         /* Transmit Time-slot Offset */
957         cpc_writeb(falcbase + F_REG(XC1, ch), 0x3e);
958         /* Receive  Clock-Slot offset */
959         cpc_writeb(falcbase + F_REG(RC0, ch), 0x05);
960         /* Receive  Time-slot offset */
961         cpc_writeb(falcbase + F_REG(RC1, ch), 0x00);
962
963         /* LOS Detection after 176 consecutive 0s */
964         cpc_writeb(falcbase + F_REG(PCDR, ch), 0x0a);
965         /* LOS Recovery after 22 ones in the time window of PCD */
966         cpc_writeb(falcbase + F_REG(PCRR, ch), 0x15);
967
968         cpc_writeb(falcbase + F_REG(IDLE, ch), 0x7f);
969
970         if (conf->fr_mode == PC300_FR_ESF_JAPAN) {
971                 cpc_writeb(falcbase + F_REG(RC1, ch),
972                            cpc_readb(falcbase + F_REG(RC1, ch)) | 0x80);
973         }
974
975         falc_close_all_timeslots(card, ch);
976 }
977
978 static void falc_init_e1(pc300_t * card, int ch)
979 {
980         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
981         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
982         falc_t *pfalc = (falc_t *) & chan->falc;
983         void __iomem *falcbase = card->hw.falcbase;
984         ucchar dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0);
985
986         /* Switch to E1 mode (PCM 30) */
987         cpc_writeb(falcbase + F_REG(FMR1, ch),
988                    cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_PMOD);
989
990         /* Clock mode */
991         if (conf->phys_settings.clock_type == CLOCK_INT) { /* Master mode */
992                 cpc_writeb(falcbase + F_REG(LIM0, ch),
993                            cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_MAS);
994         } else { /* Slave mode */
995                 cpc_writeb(falcbase + F_REG(LIM0, ch),
996                            cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_MAS);
997         }
998         cpc_writeb(falcbase + F_REG(LOOP, ch),
999                    cpc_readb(falcbase + F_REG(LOOP, ch)) & ~LOOP_SFM);
1000
1001         cpc_writeb(falcbase + F_REG(IPC, ch), IPC_SCI);
1002         cpc_writeb(falcbase + F_REG(FMR0, ch),
1003                    cpc_readb(falcbase + F_REG(FMR0, ch)) &
1004                    ~(FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1));
1005
1006         switch (conf->lcode) {
1007                 case PC300_LC_AMI:
1008                         cpc_writeb(falcbase + F_REG(FMR0, ch),
1009                                    cpc_readb(falcbase + F_REG(FMR0, ch)) |
1010                                    FMR0_XC1 | FMR0_RC1);
1011                         break;
1012
1013                 case PC300_LC_HDB3:
1014                         cpc_writeb(falcbase + F_REG(FMR0, ch),
1015                                    cpc_readb(falcbase + F_REG(FMR0, ch)) |
1016                                    FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1);
1017                         break;
1018
1019                 case PC300_LC_NRZ:
1020                         break;
1021         }
1022
1023         cpc_writeb(falcbase + F_REG(LIM0, ch),
1024                    cpc_readb(falcbase + F_REG(LIM0, ch)) & ~(LIM0_SCL1 | LIM0_SCL0));
1025         /* Set interface mode to 2 MBPS */
1026         cpc_writeb(falcbase + F_REG(FMR1, ch),
1027                    cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_IMOD);
1028
1029         cpc_writeb(falcbase + F_REG(XPM0, ch), 0x18);
1030         cpc_writeb(falcbase + F_REG(XPM1, ch), 0x03);
1031         cpc_writeb(falcbase + F_REG(XPM2, ch), 0x00);
1032
1033         switch (conf->fr_mode) {
1034                 case PC300_FR_MF_CRC4:
1035                         pfalc->multiframe_mode = 1;
1036                         cpc_writeb(falcbase + F_REG(FMR1, ch),
1037                                    cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_XFS);
1038                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1039                                    cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_RFS1);
1040                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1041                                    cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_RFS0);
1042                         cpc_writeb(falcbase + F_REG(FMR3, ch),
1043                                    cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_EXTIW);
1044
1045                         /* MultiFrame Resynchronization */
1046                         cpc_writeb(falcbase + F_REG(FMR1, ch),
1047                                    cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_MFCS);
1048
1049                         /* Automatic Loss of Multiframe > 914 CRC errors */
1050                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1051                                    cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_ALMF);
1052
1053                         /* S1 and SI1/SI2 spare Bits set to 1 */
1054                         cpc_writeb(falcbase + F_REG(XSP, ch),
1055                                    cpc_readb(falcbase + F_REG(XSP, ch)) & ~XSP_AXS);
1056                         cpc_writeb(falcbase + F_REG(XSP, ch),
1057                                    cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_EBP);
1058                         cpc_writeb(falcbase + F_REG(XSP, ch),
1059                                    cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_XS13 | XSP_XS15);
1060
1061                         /* Automatic Force Resynchronization */
1062                         cpc_writeb(falcbase + F_REG(FMR1, ch),
1063                                    cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_AFR);
1064
1065                         /* Transmit Automatic Remote Alarm */
1066                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1067                                    cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);
1068
1069                         /* Transmit Spare Bits for National Use (Y, Sn, Sa) */
1070                         cpc_writeb(falcbase + F_REG(XSW, ch),
1071                                    cpc_readb(falcbase + F_REG(XSW, ch)) |
1072                                    XSW_XY0 | XSW_XY1 | XSW_XY2 | XSW_XY3 | XSW_XY4);
1073                         break;
1074
1075                 case PC300_FR_MF_NON_CRC4:
1076                 case PC300_FR_D4:
1077                         pfalc->multiframe_mode = 0;
1078                         cpc_writeb(falcbase + F_REG(FMR1, ch),
1079                                    cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_XFS);
1080                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1081                                    cpc_readb(falcbase + F_REG(FMR2, ch)) & 
1082                                    ~(FMR2_RFS1 | FMR2_RFS0));
1083                         cpc_writeb(falcbase + F_REG(XSW, ch),
1084                                    cpc_readb(falcbase + F_REG(XSW, ch)) | XSW_XSIS);
1085                         cpc_writeb(falcbase + F_REG(XSP, ch),
1086                                    cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_XSIF);
1087
1088                         /* Automatic Force Resynchronization */
1089                         cpc_writeb(falcbase + F_REG(FMR1, ch),
1090                                    cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_AFR);
1091
1092                         /* Transmit Automatic Remote Alarm */
1093                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1094                                    cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);
1095
1096                         /* Transmit Spare Bits for National Use (Y, Sn, Sa) */
1097                         cpc_writeb(falcbase + F_REG(XSW, ch),
1098                                    cpc_readb(falcbase + F_REG(XSW, ch)) |
1099                                    XSW_XY0 | XSW_XY1 | XSW_XY2 | XSW_XY3 | XSW_XY4);
1100                         break;
1101
1102                 case PC300_FR_UNFRAMED:
1103                         pfalc->multiframe_mode = 0;
1104                         cpc_writeb(falcbase + F_REG(FMR1, ch),
1105                                    cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_XFS);
1106                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1107                                    cpc_readb(falcbase + F_REG(FMR2, ch)) & 
1108                                    ~(FMR2_RFS1 | FMR2_RFS0));
1109                         cpc_writeb(falcbase + F_REG(XSP, ch),
1110                                    cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_TT0);
1111                         cpc_writeb(falcbase + F_REG(XSW, ch),
1112                                    cpc_readb(falcbase + F_REG(XSW, ch)) & 
1113                                    ~(XSW_XTM|XSW_XY0|XSW_XY1|XSW_XY2|XSW_XY3|XSW_XY4));
1114                         cpc_writeb(falcbase + F_REG(TSWM, ch), 0xff);
1115                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1116                                    cpc_readb(falcbase + F_REG(FMR2, ch)) |
1117                                    (FMR2_RTM | FMR2_DAIS));
1118                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1119                                    cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_AXRA);
1120                         cpc_writeb(falcbase + F_REG(FMR1, ch),
1121                                    cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_AFR);
1122                         pfalc->sync = 1;
1123                         cpc_writeb(falcbase + card->hw.cpld_reg2,
1124                                    cpc_readb(falcbase + card->hw.cpld_reg2) |
1125                                    (CPLD_REG2_FALC_LED2 << (2 * ch)));
1126                         break;
1127         }
1128
1129         /* No signaling */
1130         cpc_writeb(falcbase + F_REG(XSP, ch),
1131                    cpc_readb(falcbase + F_REG(XSP, ch)) & ~XSP_CASEN);
1132         cpc_writeb(falcbase + F_REG(CCR1, ch), 0);
1133
1134         cpc_writeb(falcbase + F_REG(LIM1, ch),
1135                    cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RIL0 | LIM1_RIL1);
1136         cpc_writeb(falcbase + F_REG(LIM2, ch), (LIM2_LOS1 | dja));
1137
1138         /* Transmit Clock-Slot Offset */
1139         cpc_writeb(falcbase + F_REG(XC0, ch),
1140                    cpc_readb(falcbase + F_REG(XC0, ch)) | 0x01);
1141         /* Transmit Time-slot Offset */
1142         cpc_writeb(falcbase + F_REG(XC1, ch), 0x3e);
1143         /* Receive  Clock-Slot offset */
1144         cpc_writeb(falcbase + F_REG(RC0, ch), 0x05);
1145         /* Receive  Time-slot offset */
1146         cpc_writeb(falcbase + F_REG(RC1, ch), 0x00);
1147
1148         /* LOS Detection after 176 consecutive 0s */
1149         cpc_writeb(falcbase + F_REG(PCDR, ch), 0x0a);
1150         /* LOS Recovery after 22 ones in the time window of PCD */
1151         cpc_writeb(falcbase + F_REG(PCRR, ch), 0x15);
1152
1153         cpc_writeb(falcbase + F_REG(IDLE, ch), 0x7f);
1154
1155         falc_close_all_timeslots(card, ch);
1156 }
1157
1158 static void falc_init_hdlc(pc300_t * card, int ch)
1159 {
1160         void __iomem *falcbase = card->hw.falcbase;
1161         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1162         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1163
1164         /* Enable transparent data transfer */
1165         if (conf->fr_mode == PC300_FR_UNFRAMED) {
1166                 cpc_writeb(falcbase + F_REG(MODE, ch), 0);
1167         } else {
1168                 cpc_writeb(falcbase + F_REG(MODE, ch),
1169                            cpc_readb(falcbase + F_REG(MODE, ch)) |
1170                            (MODE_HRAC | MODE_MDS2));
1171                 cpc_writeb(falcbase + F_REG(RAH2, ch), 0xff);
1172                 cpc_writeb(falcbase + F_REG(RAH1, ch), 0xff);
1173                 cpc_writeb(falcbase + F_REG(RAL2, ch), 0xff);
1174                 cpc_writeb(falcbase + F_REG(RAL1, ch), 0xff);
1175         }
1176
1177         /* Tx/Rx reset  */
1178         falc_issue_cmd(card, ch, CMDR_RRES | CMDR_XRES | CMDR_SRES);
1179
1180         /* Enable interrupt sources */
1181         falc_intr_enable(card, ch);
1182 }
1183
1184 static void te_config(pc300_t * card, int ch)
1185 {
1186         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1187         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1188         falc_t *pfalc = (falc_t *) & chan->falc;
1189         void __iomem *falcbase = card->hw.falcbase;
1190         ucchar dummy;
1191         unsigned long flags;
1192
1193         memset(pfalc, 0, sizeof(falc_t));
1194         switch (conf->media) {
1195                 case IF_IFACE_T1:
1196                         pfalc->num_channels = NUM_OF_T1_CHANNELS;
1197                         pfalc->offset = 1;
1198                         break;
1199                 case IF_IFACE_E1:
1200                         pfalc->num_channels = NUM_OF_E1_CHANNELS;
1201                         pfalc->offset = 0;
1202                         break;
1203         }
1204         if (conf->tslot_bitmap == 0xffffffffUL)
1205                 pfalc->full_bandwidth = 1;
1206         else
1207                 pfalc->full_bandwidth = 0;
1208
1209         CPC_LOCK(card, flags);
1210         /* Reset the FALC chip */
1211         cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
1212                    cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
1213                    (CPLD_REG1_FALC_RESET << (2 * ch)));
1214         udelay(10000);
1215         cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
1216                    cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) &
1217                    ~(CPLD_REG1_FALC_RESET << (2 * ch)));
1218
1219         if (conf->media == IF_IFACE_T1) {
1220                 falc_init_t1(card, ch);
1221         } else {
1222                 falc_init_e1(card, ch);
1223         }
1224         falc_init_hdlc(card, ch);
1225         if (conf->rx_sens == PC300_RX_SENS_SH) {
1226                 cpc_writeb(falcbase + F_REG(LIM0, ch),
1227                            cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_EQON);
1228         } else {
1229                 cpc_writeb(falcbase + F_REG(LIM0, ch),
1230                            cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_EQON);
1231         }
1232         cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1233                    cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) |
1234                    ((CPLD_REG2_FALC_TX_CLK | CPLD_REG2_FALC_RX_CLK) << (2 * ch)));
1235
1236         /* Clear all interrupt registers */
1237         dummy = cpc_readb(falcbase + F_REG(FISR0, ch)) +
1238                 cpc_readb(falcbase + F_REG(FISR1, ch)) +
1239                 cpc_readb(falcbase + F_REG(FISR2, ch)) +
1240                 cpc_readb(falcbase + F_REG(FISR3, ch));
1241         CPC_UNLOCK(card, flags);
1242 }
1243
1244 static void falc_check_status(pc300_t * card, int ch, unsigned char frs0)
1245 {
1246         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1247         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1248         falc_t *pfalc = (falc_t *) & chan->falc;
1249         void __iomem *falcbase = card->hw.falcbase;
1250
1251         /* Verify LOS */
1252         if (frs0 & FRS0_LOS) {
1253                 if (!pfalc->red_alarm) {
1254                         pfalc->red_alarm = 1;
1255                         pfalc->los++;
1256                         if (!pfalc->blue_alarm) {
1257                                 // EVENT_FALC_ABNORMAL
1258                                 if (conf->media == IF_IFACE_T1) {
1259                                         /* Disable this interrupt as it may otherwise interfere 
1260                                          * with other working boards. */
1261                                         cpc_writeb(falcbase + F_REG(IMR0, ch), 
1262                                                    cpc_readb(falcbase + F_REG(IMR0, ch))
1263                                                    | IMR0_PDEN);
1264                                 }
1265                                 falc_disable_comm(card, ch);
1266                                 // EVENT_FALC_ABNORMAL
1267                         }
1268                 }
1269         } else {
1270                 if (pfalc->red_alarm) {
1271                         pfalc->red_alarm = 0;
1272                         pfalc->losr++;
1273                 }
1274         }
1275
1276         if (conf->fr_mode != PC300_FR_UNFRAMED) {
1277                 /* Verify AIS alarm */
1278                 if (frs0 & FRS0_AIS) {
1279                         if (!pfalc->blue_alarm) {
1280                                 pfalc->blue_alarm = 1;
1281                                 pfalc->ais++;
1282                                 // EVENT_AIS
1283                                 if (conf->media == IF_IFACE_T1) {
1284                                         /* Disable this interrupt as it may otherwise interfere with                       other working boards. */
1285                                         cpc_writeb(falcbase + F_REG(IMR0, ch),
1286                                                    cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1287                                 }
1288                                 falc_disable_comm(card, ch);
1289                                 // EVENT_AIS
1290                         }
1291                 } else {
1292                         pfalc->blue_alarm = 0;
1293                 }
1294
1295                 /* Verify LFA */
1296                 if (frs0 & FRS0_LFA) {
1297                         if (!pfalc->loss_fa) {
1298                                 pfalc->loss_fa = 1;
1299                                 pfalc->lfa++;
1300                                 if (!pfalc->blue_alarm && !pfalc->red_alarm) {
1301                                         // EVENT_FALC_ABNORMAL
1302                                         if (conf->media == IF_IFACE_T1) {
1303                                                 /* Disable this interrupt as it may otherwise 
1304                                                  * interfere with other working boards. */
1305                                                 cpc_writeb(falcbase + F_REG(IMR0, ch),
1306                                                            cpc_readb(falcbase + F_REG(IMR0, ch))
1307                                                            | IMR0_PDEN);
1308                                         }
1309                                         falc_disable_comm(card, ch);
1310                                         // EVENT_FALC_ABNORMAL
1311                                 }
1312                         }
1313                 } else {
1314                         if (pfalc->loss_fa) {
1315                                 pfalc->loss_fa = 0;
1316                                 pfalc->farec++;
1317                         }
1318                 }
1319
1320                 /* Verify LMFA */
1321                 if (pfalc->multiframe_mode && (frs0 & FRS0_LMFA)) {
1322                         /* D4 or CRC4 frame mode */
1323                         if (!pfalc->loss_mfa) {
1324                                 pfalc->loss_mfa = 1;
1325                                 pfalc->lmfa++;
1326                                 if (!pfalc->blue_alarm && !pfalc->red_alarm &&
1327                                     !pfalc->loss_fa) {
1328                                         // EVENT_FALC_ABNORMAL
1329                                         if (conf->media == IF_IFACE_T1) {
1330                                                 /* Disable this interrupt as it may otherwise 
1331                                                  * interfere with other working boards. */
1332                                                 cpc_writeb(falcbase + F_REG(IMR0, ch),
1333                                                            cpc_readb(falcbase + F_REG(IMR0, ch))
1334                                                            | IMR0_PDEN);
1335                                         }
1336                                         falc_disable_comm(card, ch);
1337                                         // EVENT_FALC_ABNORMAL
1338                                 }
1339                         }
1340                 } else {
1341                         pfalc->loss_mfa = 0;
1342                 }
1343
1344                 /* Verify Remote Alarm */
1345                 if (frs0 & FRS0_RRA) {
1346                         if (!pfalc->yellow_alarm) {
1347                                 pfalc->yellow_alarm = 1;
1348                                 pfalc->rai++;
1349                                 if (pfalc->sync) {
1350                                         // EVENT_RAI
1351                                         falc_disable_comm(card, ch);
1352                                         // EVENT_RAI
1353                                 }
1354                         }
1355                 } else {
1356                         pfalc->yellow_alarm = 0;
1357                 }
1358         } /* if !PC300_UNFRAMED */
1359
1360         if (pfalc->red_alarm || pfalc->loss_fa ||
1361             pfalc->loss_mfa || pfalc->blue_alarm) {
1362                 if (pfalc->sync) {
1363                         pfalc->sync = 0;
1364                         chan->d.line_off++;
1365                         cpc_writeb(falcbase + card->hw.cpld_reg2,
1366                                    cpc_readb(falcbase + card->hw.cpld_reg2) &
1367                                    ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1368                 }
1369         } else {
1370                 if (!pfalc->sync) {
1371                         pfalc->sync = 1;
1372                         chan->d.line_on++;
1373                         cpc_writeb(falcbase + card->hw.cpld_reg2,
1374                                    cpc_readb(falcbase + card->hw.cpld_reg2) |
1375                                    (CPLD_REG2_FALC_LED2 << (2 * ch)));
1376                 }
1377         }
1378
1379         if (pfalc->sync && !pfalc->yellow_alarm) {
1380                 if (!pfalc->active) {
1381                         // EVENT_FALC_NORMAL
1382                         if (pfalc->loop_active) {
1383                                 return;
1384                         }
1385                         if (conf->media == IF_IFACE_T1) {
1386                                 cpc_writeb(falcbase + F_REG(IMR0, ch),
1387                                            cpc_readb(falcbase + F_REG(IMR0, ch)) & ~IMR0_PDEN);
1388                         }
1389                         falc_enable_comm(card, ch);
1390                         // EVENT_FALC_NORMAL
1391                         pfalc->active = 1;
1392                 }
1393         } else {
1394                 if (pfalc->active) {
1395                         pfalc->active = 0;
1396                 }
1397         }
1398 }
1399
1400 static void falc_update_stats(pc300_t * card, int ch)
1401 {
1402         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1403         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1404         falc_t *pfalc = (falc_t *) & chan->falc;
1405         void __iomem *falcbase = card->hw.falcbase;
1406         ucshort counter;
1407
1408         counter = cpc_readb(falcbase + F_REG(FECL, ch));
1409         counter |= cpc_readb(falcbase + F_REG(FECH, ch)) << 8;
1410         pfalc->fec += counter;
1411
1412         counter = cpc_readb(falcbase + F_REG(CVCL, ch));
1413         counter |= cpc_readb(falcbase + F_REG(CVCH, ch)) << 8;
1414         pfalc->cvc += counter;
1415
1416         counter = cpc_readb(falcbase + F_REG(CECL, ch));
1417         counter |= cpc_readb(falcbase + F_REG(CECH, ch)) << 8;
1418         pfalc->cec += counter;
1419
1420         counter = cpc_readb(falcbase + F_REG(EBCL, ch));
1421         counter |= cpc_readb(falcbase + F_REG(EBCH, ch)) << 8;
1422         pfalc->ebc += counter;
1423
1424         if (cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) {
1425                 mdelay(10);
1426                 counter = cpc_readb(falcbase + F_REG(BECL, ch));
1427                 counter |= cpc_readb(falcbase + F_REG(BECH, ch)) << 8;
1428                 pfalc->bec += counter;
1429
1430                 if (((conf->media == IF_IFACE_T1) &&
1431                      (cpc_readb(falcbase + F_REG(FRS1, ch)) & FRS1_LLBAD) &&
1432                      (!(cpc_readb(falcbase + F_REG(FRS1, ch)) & FRS1_PDEN)))
1433                     ||
1434                     ((conf->media == IF_IFACE_E1) &&
1435                      (cpc_readb(falcbase + F_REG(RSP, ch)) & RSP_LLBAD))) {
1436                         pfalc->prbs = 2;
1437                 } else {
1438                         pfalc->prbs = 1;
1439                 }
1440         }
1441 }
1442
1443 /*----------------------------------------------------------------------------
1444  * falc_remote_loop
1445  *----------------------------------------------------------------------------
1446  * Description: In the remote loopback mode the clock and data recovered
1447  *              from the line inputs RL1/2 or RDIP/RDIN are routed back
1448  *              to the line outputs XL1/2 or XDOP/XDON via the analog
1449  *              transmitter. As in normal mode they are processsed by
1450  *              the synchronizer and then sent to the system interface.
1451  *----------------------------------------------------------------------------
1452  */
1453 static void falc_remote_loop(pc300_t * card, int ch, int loop_on)
1454 {
1455         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1456         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1457         falc_t *pfalc = (falc_t *) & chan->falc;
1458         void __iomem *falcbase = card->hw.falcbase;
1459
1460         if (loop_on) {
1461                 // EVENT_FALC_ABNORMAL
1462                 if (conf->media == IF_IFACE_T1) {
1463                         /* Disable this interrupt as it may otherwise interfere with 
1464                          * other working boards. */
1465                         cpc_writeb(falcbase + F_REG(IMR0, ch),
1466                                    cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1467                 }
1468                 falc_disable_comm(card, ch);
1469                 // EVENT_FALC_ABNORMAL
1470                 cpc_writeb(falcbase + F_REG(LIM1, ch),
1471                            cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RL);
1472                 pfalc->loop_active = 1;
1473         } else {
1474                 cpc_writeb(falcbase + F_REG(LIM1, ch),
1475                            cpc_readb(falcbase + F_REG(LIM1, ch)) & ~LIM1_RL);
1476                 pfalc->sync = 0;
1477                 cpc_writeb(falcbase + card->hw.cpld_reg2,
1478                            cpc_readb(falcbase + card->hw.cpld_reg2) &
1479                            ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1480                 pfalc->active = 0;
1481                 falc_issue_cmd(card, ch, CMDR_XRES);
1482                 pfalc->loop_active = 0;
1483         }
1484 }
1485
1486 /*----------------------------------------------------------------------------
1487  * falc_local_loop
1488  *----------------------------------------------------------------------------
1489  * Description: The local loopback mode disconnects the receive lines 
1490  *              RL1/RL2 resp. RDIP/RDIN from the receiver. Instead of the
1491  *              signals coming from the line the data provided by system
1492  *              interface are routed through the analog receiver back to
1493  *              the system interface. The unipolar bit stream will be
1494  *              undisturbed transmitted on the line. Receiver and transmitter
1495  *              coding must be identical.
1496  *----------------------------------------------------------------------------
1497  */
1498 static void falc_local_loop(pc300_t * card, int ch, int loop_on)
1499 {
1500         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1501         falc_t *pfalc = (falc_t *) & chan->falc;
1502         void __iomem *falcbase = card->hw.falcbase;
1503
1504         if (loop_on) {
1505                 cpc_writeb(falcbase + F_REG(LIM0, ch),
1506                            cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_LL);
1507                 pfalc->loop_active = 1;
1508         } else {
1509                 cpc_writeb(falcbase + F_REG(LIM0, ch),
1510                            cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_LL);
1511                 pfalc->loop_active = 0;
1512         }
1513 }
1514
1515 /*----------------------------------------------------------------------------
1516  * falc_payload_loop
1517  *----------------------------------------------------------------------------
1518  * Description: This routine allows to enable/disable payload loopback.
1519  *              When the payload loop is activated, the received 192 bits
1520  *              of payload data will be looped back to the transmit
1521  *              direction. The framing bits, CRC6 and DL bits are not 
1522  *              looped. They are originated by the FALC-LH transmitter.
1523  *----------------------------------------------------------------------------
1524  */
1525 static void falc_payload_loop(pc300_t * card, int ch, int loop_on)
1526 {
1527         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1528         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1529         falc_t *pfalc = (falc_t *) & chan->falc;
1530         void __iomem *falcbase = card->hw.falcbase;
1531
1532         if (loop_on) {
1533                 // EVENT_FALC_ABNORMAL
1534                 if (conf->media == IF_IFACE_T1) {
1535                         /* Disable this interrupt as it may otherwise interfere with 
1536                          * other working boards. */
1537                         cpc_writeb(falcbase + F_REG(IMR0, ch),
1538                                    cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1539                 }
1540                 falc_disable_comm(card, ch);
1541                 // EVENT_FALC_ABNORMAL
1542                 cpc_writeb(falcbase + F_REG(FMR2, ch),
1543                            cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_PLB);
1544                 if (conf->media == IF_IFACE_T1) {
1545                         cpc_writeb(falcbase + F_REG(FMR4, ch),
1546                                    cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_TM);
1547                 } else {
1548                         cpc_writeb(falcbase + F_REG(FMR5, ch),
1549                                    cpc_readb(falcbase + F_REG(FMR5, ch)) | XSP_TT0);
1550                 }
1551                 falc_open_all_timeslots(card, ch);
1552                 pfalc->loop_active = 2;
1553         } else {
1554                 cpc_writeb(falcbase + F_REG(FMR2, ch),
1555                            cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_PLB);
1556                 if (conf->media == IF_IFACE_T1) {
1557                         cpc_writeb(falcbase + F_REG(FMR4, ch),
1558                                    cpc_readb(falcbase + F_REG(FMR4, ch)) & ~FMR4_TM);
1559                 } else {
1560                         cpc_writeb(falcbase + F_REG(FMR5, ch),
1561                                    cpc_readb(falcbase + F_REG(FMR5, ch)) & ~XSP_TT0);
1562                 }
1563                 pfalc->sync = 0;
1564                 cpc_writeb(falcbase + card->hw.cpld_reg2,
1565                            cpc_readb(falcbase + card->hw.cpld_reg2) &
1566                            ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1567                 pfalc->active = 0;
1568                 falc_issue_cmd(card, ch, CMDR_XRES);
1569                 pfalc->loop_active = 0;
1570         }
1571 }
1572
1573 /*----------------------------------------------------------------------------
1574  * turn_off_xlu
1575  *----------------------------------------------------------------------------
1576  * Description: Turns XLU bit off in the proper register
1577  *----------------------------------------------------------------------------
1578  */
1579 static void turn_off_xlu(pc300_t * card, int ch)
1580 {
1581         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1582         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1583         void __iomem *falcbase = card->hw.falcbase;
1584
1585         if (conf->media == IF_IFACE_T1) {
1586                 cpc_writeb(falcbase + F_REG(FMR5, ch),
1587                            cpc_readb(falcbase + F_REG(FMR5, ch)) & ~FMR5_XLU);
1588         } else {
1589                 cpc_writeb(falcbase + F_REG(FMR3, ch),
1590                            cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_XLU);
1591         }
1592 }
1593
1594 /*----------------------------------------------------------------------------
1595  * turn_off_xld
1596  *----------------------------------------------------------------------------
1597  * Description: Turns XLD bit off in the proper register
1598  *----------------------------------------------------------------------------
1599  */
1600 static void turn_off_xld(pc300_t * card, int ch)
1601 {
1602         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1603         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1604         void __iomem *falcbase = card->hw.falcbase;
1605
1606         if (conf->media == IF_IFACE_T1) {
1607                 cpc_writeb(falcbase + F_REG(FMR5, ch),
1608                            cpc_readb(falcbase + F_REG(FMR5, ch)) & ~FMR5_XLD);
1609         } else {
1610                 cpc_writeb(falcbase + F_REG(FMR3, ch),
1611                            cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_XLD);
1612         }
1613 }
1614
1615 /*----------------------------------------------------------------------------
1616  * falc_generate_loop_up_code
1617  *----------------------------------------------------------------------------
1618  * Description: This routine writes the proper FALC chip register in order
1619  *              to generate a LOOP activation code over a T1/E1 line.
1620  *----------------------------------------------------------------------------
1621  */
1622 static void falc_generate_loop_up_code(pc300_t * card, int ch)
1623 {
1624         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1625         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1626         falc_t *pfalc = (falc_t *) & chan->falc;
1627         void __iomem *falcbase = card->hw.falcbase;
1628
1629         if (conf->media == IF_IFACE_T1) {
1630                 cpc_writeb(falcbase + F_REG(FMR5, ch),
1631                            cpc_readb(falcbase + F_REG(FMR5, ch)) | FMR5_XLU);
1632         } else {
1633                 cpc_writeb(falcbase + F_REG(FMR3, ch),
1634                            cpc_readb(falcbase + F_REG(FMR3, ch)) | FMR3_XLU);
1635         }
1636         // EVENT_FALC_ABNORMAL
1637         if (conf->media == IF_IFACE_T1) {
1638                 /* Disable this interrupt as it may otherwise interfere with 
1639                  * other working boards. */
1640                 cpc_writeb(falcbase + F_REG(IMR0, ch),
1641                            cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1642         }
1643         falc_disable_comm(card, ch);
1644         // EVENT_FALC_ABNORMAL
1645         pfalc->loop_gen = 1;
1646 }
1647
1648 /*----------------------------------------------------------------------------
1649  * falc_generate_loop_down_code
1650  *----------------------------------------------------------------------------
1651  * Description: This routine writes the proper FALC chip register in order
1652  *              to generate a LOOP deactivation code over a T1/E1 line.
1653  *----------------------------------------------------------------------------
1654  */
1655 static void falc_generate_loop_down_code(pc300_t * card, int ch)
1656 {
1657         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1658         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1659         falc_t *pfalc = (falc_t *) & chan->falc;
1660         void __iomem *falcbase = card->hw.falcbase;
1661
1662         if (conf->media == IF_IFACE_T1) {
1663                 cpc_writeb(falcbase + F_REG(FMR5, ch),
1664                            cpc_readb(falcbase + F_REG(FMR5, ch)) | FMR5_XLD);
1665         } else {
1666                 cpc_writeb(falcbase + F_REG(FMR3, ch),
1667                            cpc_readb(falcbase + F_REG(FMR3, ch)) | FMR3_XLD);
1668         }
1669         pfalc->sync = 0;
1670         cpc_writeb(falcbase + card->hw.cpld_reg2,
1671                    cpc_readb(falcbase + card->hw.cpld_reg2) &
1672                    ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1673         pfalc->active = 0;
1674 //?    falc_issue_cmd(card, ch, CMDR_XRES);
1675         pfalc->loop_gen = 0;
1676 }
1677
1678 /*----------------------------------------------------------------------------
1679  * falc_pattern_test
1680  *----------------------------------------------------------------------------
1681  * Description: This routine generates a pattern code and checks
1682  *              it on the reception side.
1683  *----------------------------------------------------------------------------
1684  */
1685 static void falc_pattern_test(pc300_t * card, int ch, unsigned int activate)
1686 {
1687         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1688         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1689         falc_t *pfalc = (falc_t *) & chan->falc;
1690         void __iomem *falcbase = card->hw.falcbase;
1691
1692         if (activate) {
1693                 pfalc->prbs = 1;
1694                 pfalc->bec = 0;
1695                 if (conf->media == IF_IFACE_T1) {
1696                         /* Disable local loop activation/deactivation detect */
1697                         cpc_writeb(falcbase + F_REG(IMR3, ch),
1698                                    cpc_readb(falcbase + F_REG(IMR3, ch)) | IMR3_LLBSC);
1699                 } else {
1700                         /* Disable local loop activation/deactivation detect */
1701                         cpc_writeb(falcbase + F_REG(IMR1, ch),
1702                                    cpc_readb(falcbase + F_REG(IMR1, ch)) | IMR1_LLBSC);
1703                 }
1704                 /* Activates generation and monitoring of PRBS 
1705                  * (Pseudo Random Bit Sequence) */
1706                 cpc_writeb(falcbase + F_REG(LCR1, ch),
1707                            cpc_readb(falcbase + F_REG(LCR1, ch)) | LCR1_EPRM | LCR1_XPRBS);
1708         } else {
1709                 pfalc->prbs = 0;
1710                 /* Deactivates generation and monitoring of PRBS 
1711                  * (Pseudo Random Bit Sequence) */
1712                 cpc_writeb(falcbase + F_REG(LCR1, ch),
1713                            cpc_readb(falcbase+F_REG(LCR1,ch)) & ~(LCR1_EPRM | LCR1_XPRBS));
1714                 if (conf->media == IF_IFACE_T1) {
1715                         /* Enable local loop activation/deactivation detect */
1716                         cpc_writeb(falcbase + F_REG(IMR3, ch),
1717                                    cpc_readb(falcbase + F_REG(IMR3, ch)) & ~IMR3_LLBSC);
1718                 } else {
1719                         /* Enable local loop activation/deactivation detect */
1720                         cpc_writeb(falcbase + F_REG(IMR1, ch),
1721                                    cpc_readb(falcbase + F_REG(IMR1, ch)) & ~IMR1_LLBSC);
1722                 }
1723         }
1724 }
1725
1726 /*----------------------------------------------------------------------------
1727  * falc_pattern_test_error
1728  *----------------------------------------------------------------------------
1729  * Description: This routine returns the bit error counter value
1730  *----------------------------------------------------------------------------
1731  */
1732 static ucshort falc_pattern_test_error(pc300_t * card, int ch)
1733 {
1734         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1735         falc_t *pfalc = (falc_t *) & chan->falc;
1736
1737         return (pfalc->bec);
1738 }
1739
1740 /**********************************/
1741 /***   Net Interface Routines   ***/
1742 /**********************************/
1743
1744 static void
1745 cpc_trace(struct net_device *dev, struct sk_buff *skb_main, char rx_tx)
1746 {
1747         struct sk_buff *skb;
1748
1749         if ((skb = dev_alloc_skb(10 + skb_main->len)) == NULL) {
1750                 printk("%s: out of memory\n", dev->name);
1751                 return;
1752         }
1753         skb_put(skb, 10 + skb_main->len);
1754
1755         skb->dev = dev;
1756         skb->protocol = htons(ETH_P_CUST);
1757         skb_reset_mac_header(skb);
1758         skb->pkt_type = PACKET_HOST;
1759         skb->len = 10 + skb_main->len;
1760
1761         skb_copy_to_linear_data(skb, dev->name, 5);
1762         skb->data[5] = '[';
1763         skb->data[6] = rx_tx;
1764         skb->data[7] = ']';
1765         skb->data[8] = ':';
1766         skb->data[9] = ' ';
1767         skb_copy_from_linear_data(skb_main, &skb->data[10], skb_main->len);
1768
1769         netif_rx(skb);
1770 }
1771
1772 static void cpc_tx_timeout(struct net_device *dev)
1773 {
1774         pc300dev_t *d = (pc300dev_t *) dev->priv;
1775         pc300ch_t *chan = (pc300ch_t *) d->chan;
1776         pc300_t *card = (pc300_t *) chan->card;
1777         int ch = chan->channel;
1778         unsigned long flags;
1779         ucchar ilar;
1780
1781         dev->stats.tx_errors++;
1782         dev->stats.tx_aborted_errors++;
1783         CPC_LOCK(card, flags);
1784         if ((ilar = cpc_readb(card->hw.scabase + ILAR)) != 0) {
1785                 printk("%s: ILAR=0x%x\n", dev->name, ilar);
1786                 cpc_writeb(card->hw.scabase + ILAR, ilar);
1787                 cpc_writeb(card->hw.scabase + DMER, 0x80);
1788         }
1789         if (card->hw.type == PC300_TE) {
1790                 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1791                            cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) &
1792                            ~(CPLD_REG2_FALC_LED1 << (2 * ch)));
1793         }
1794         dev->trans_start = jiffies;
1795         CPC_UNLOCK(card, flags);
1796         netif_wake_queue(dev);
1797 }
1798
1799 static int cpc_queue_xmit(struct sk_buff *skb, struct net_device *dev)
1800 {
1801         pc300dev_t *d = (pc300dev_t *) dev->priv;
1802         pc300ch_t *chan = (pc300ch_t *) d->chan;
1803         pc300_t *card = (pc300_t *) chan->card;
1804         int ch = chan->channel;
1805         unsigned long flags;
1806 #ifdef PC300_DEBUG_TX
1807         int i;
1808 #endif
1809
1810         if (chan->conf.monitor) {
1811                 /* In monitor mode no Tx is done: ignore packet */
1812                 dev_kfree_skb(skb);
1813                 return 0;
1814         } else if (!netif_carrier_ok(dev)) {
1815                 /* DCD must be OFF: drop packet */
1816                 dev_kfree_skb(skb);
1817                 dev->stats.tx_errors++;
1818                 dev->stats.tx_carrier_errors++;
1819                 return 0;
1820         } else if (cpc_readb(card->hw.scabase + M_REG(ST3, ch)) & ST3_DCD) {
1821                 printk("%s: DCD is OFF. Going administrative down.\n", dev->name);
1822                 dev->stats.tx_errors++;
1823                 dev->stats.tx_carrier_errors++;
1824                 dev_kfree_skb(skb);
1825                 netif_carrier_off(dev);
1826                 CPC_LOCK(card, flags);
1827                 cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_TX_BUF_CLR);
1828                 if (card->hw.type == PC300_TE) {
1829                         cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1830                                    cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) & 
1831                                                         ~(CPLD_REG2_FALC_LED1 << (2 * ch)));
1832                 }
1833                 CPC_UNLOCK(card, flags);
1834                 netif_wake_queue(dev);
1835                 return 0;
1836         }
1837
1838         /* Write buffer to DMA buffers */
1839         if (dma_buf_write(card, ch, (ucchar *) skb->data, skb->len) != 0) {
1840 //              printk("%s: write error. Dropping TX packet.\n", dev->name);
1841                 netif_stop_queue(dev);
1842                 dev_kfree_skb(skb);
1843                 dev->stats.tx_errors++;
1844                 dev->stats.tx_dropped++;
1845                 return 0;
1846         }
1847 #ifdef PC300_DEBUG_TX
1848         printk("%s T:", dev->name);
1849         for (i = 0; i < skb->len; i++)
1850                 printk(" %02x", *(skb->data + i));
1851         printk("\n");
1852 #endif
1853
1854         if (d->trace_on) {
1855                 cpc_trace(dev, skb, 'T');
1856         }
1857         dev->trans_start = jiffies;
1858
1859         /* Start transmission */
1860         CPC_LOCK(card, flags);
1861         /* verify if it has more than one free descriptor */
1862         if (card->chan[ch].nfree_tx_bd <= 1) {
1863                 /* don't have so stop the queue */
1864                 netif_stop_queue(dev);
1865         }
1866         cpc_writel(card->hw.scabase + DTX_REG(EDAL, ch),
1867                    TX_BD_ADDR(ch, chan->tx_next_bd));
1868         cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_TX_ENA);
1869         cpc_writeb(card->hw.scabase + DSR_TX(ch), DSR_DE);
1870         if (card->hw.type == PC300_TE) {
1871                 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1872                            cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) |
1873                            (CPLD_REG2_FALC_LED1 << (2 * ch)));
1874         }
1875         CPC_UNLOCK(card, flags);
1876         dev_kfree_skb(skb);
1877
1878         return 0;
1879 }
1880
1881 static void cpc_net_rx(struct net_device *dev)
1882 {
1883         pc300dev_t *d = (pc300dev_t *) dev->priv;
1884         pc300ch_t *chan = (pc300ch_t *) d->chan;
1885         pc300_t *card = (pc300_t *) chan->card;
1886         int ch = chan->channel;
1887 #ifdef PC300_DEBUG_RX
1888         int i;
1889 #endif
1890         int rxb;
1891         struct sk_buff *skb;
1892
1893         while (1) {
1894                 if ((rxb = dma_get_rx_frame_size(card, ch)) == -1)
1895                         return;
1896
1897                 if (!netif_carrier_ok(dev)) {
1898                         /* DCD must be OFF: drop packet */
1899                     printk("%s : DCD is OFF - drop %d rx bytes\n", dev->name, rxb); 
1900                         skb = NULL;
1901                 } else {
1902                         if (rxb > (dev->mtu + 40)) { /* add headers */
1903                                 printk("%s : MTU exceeded %d\n", dev->name, rxb); 
1904                                 skb = NULL;
1905                         } else {
1906                                 skb = dev_alloc_skb(rxb);
1907                                 if (skb == NULL) {
1908                                         printk("%s: Memory squeeze!!\n", dev->name);
1909                                         return;
1910                                 }
1911                                 skb->dev = dev;
1912                         }
1913                 }
1914
1915                 if (((rxb = dma_buf_read(card, ch, skb)) <= 0) || (skb == NULL)) {
1916 #ifdef PC300_DEBUG_RX
1917                         printk("%s: rxb = %x\n", dev->name, rxb);
1918 #endif
1919                         if ((skb == NULL) && (rxb > 0)) {
1920                                 /* rxb > dev->mtu */
1921                                 dev->stats.rx_errors++;
1922                                 dev->stats.rx_length_errors++;
1923                                 continue;
1924                         }
1925
1926                         if (rxb < 0) {  /* Invalid frame */
1927                                 rxb = -rxb;
1928                                 if (rxb & DST_OVR) {
1929                                         dev->stats.rx_errors++;
1930                                         dev->stats.rx_fifo_errors++;
1931                                 }
1932                                 if (rxb & DST_CRC) {
1933                                         dev->stats.rx_errors++;
1934                                         dev->stats.rx_crc_errors++;
1935                                 }
1936                                 if (rxb & (DST_RBIT | DST_SHRT | DST_ABT)) {
1937                                         dev->stats.rx_errors++;
1938                                         dev->stats.rx_frame_errors++;
1939                                 }
1940                         }
1941                         if (skb) {
1942                                 dev_kfree_skb_irq(skb);
1943                         }
1944                         continue;
1945                 }
1946
1947                 dev->stats.rx_bytes += rxb;
1948
1949 #ifdef PC300_DEBUG_RX
1950                 printk("%s R:", dev->name);
1951                 for (i = 0; i < skb->len; i++)
1952                         printk(" %02x", *(skb->data + i));
1953                 printk("\n");
1954 #endif
1955                 if (d->trace_on) {
1956                         cpc_trace(dev, skb, 'R');
1957                 }
1958                 dev->stats.rx_packets++;
1959                 skb->protocol = hdlc_type_trans(skb, dev);
1960                 netif_rx(skb);
1961         }
1962 }
1963
1964 /************************************/
1965 /***   PC300 Interrupt Routines   ***/
1966 /************************************/
1967 static void sca_tx_intr(pc300dev_t *dev)
1968 {
1969         pc300ch_t *chan = (pc300ch_t *)dev->chan; 
1970         pc300_t *card = (pc300_t *)chan->card; 
1971         int ch = chan->channel; 
1972         volatile pcsca_bd_t __iomem * ptdescr; 
1973
1974     /* Clean up descriptors from previous transmission */
1975         ptdescr = (card->hw.rambase +
1976                                                 TX_BD_ADDR(ch,chan->tx_first_bd));
1977         while ((cpc_readl(card->hw.scabase + DTX_REG(CDAL,ch)) !=
1978                 TX_BD_ADDR(ch,chan->tx_first_bd)) &&
1979                (cpc_readb(&ptdescr->status) & DST_OSB)) {
1980                 dev->dev->stats.tx_packets++;
1981                 dev->dev->stats.tx_bytes += cpc_readw(&ptdescr->len);
1982                 cpc_writeb(&ptdescr->status, DST_OSB);
1983                 cpc_writew(&ptdescr->len, 0);
1984                 chan->nfree_tx_bd++;
1985                 chan->tx_first_bd = (chan->tx_first_bd + 1) & (N_DMA_TX_BUF - 1);
1986                 ptdescr = (card->hw.rambase + TX_BD_ADDR(ch,chan->tx_first_bd));
1987     }
1988
1989 #ifdef CONFIG_PC300_MLPPP
1990         if (chan->conf.proto == PC300_PROTO_MLPPP) {
1991                         cpc_tty_trigger_poll(dev);
1992         } else {
1993 #endif
1994         /* Tell the upper layer we are ready to transmit more packets */
1995                 netif_wake_queue(dev->dev);
1996 #ifdef CONFIG_PC300_MLPPP
1997         }
1998 #endif
1999 }
2000
2001 static void sca_intr(pc300_t * card)
2002 {
2003         void __iomem *scabase = card->hw.scabase;
2004         volatile uclong status;
2005         int ch;
2006         int intr_count = 0;
2007         unsigned char dsr_rx;
2008
2009         while ((status = cpc_readl(scabase + ISR0)) != 0) {
2010                 for (ch = 0; ch < card->hw.nchan; ch++) {
2011                         pc300ch_t *chan = &card->chan[ch];
2012                         pc300dev_t *d = &chan->d;
2013                         struct net_device *dev = d->dev;
2014
2015                         spin_lock(&card->card_lock);
2016
2017             /**** Reception ****/
2018                         if (status & IR0_DRX((IR0_DMIA | IR0_DMIB), ch)) {
2019                                 ucchar drx_stat = cpc_readb(scabase + DSR_RX(ch));
2020
2021                                 /* Clear RX interrupts */
2022                                 cpc_writeb(scabase + DSR_RX(ch), drx_stat | DSR_DWE);
2023
2024 #ifdef PC300_DEBUG_INTR
2025                                 printk ("sca_intr: RX intr chan[%d] (st=0x%08lx, dsr=0x%02x)\n",
2026                                          ch, status, drx_stat);
2027 #endif
2028                                 if (status & IR0_DRX(IR0_DMIA, ch)) {
2029                                         if (drx_stat & DSR_BOF) {
2030 #ifdef CONFIG_PC300_MLPPP
2031                                                 if (chan->conf.proto == PC300_PROTO_MLPPP) {
2032                                                         /* verify if driver is TTY */
2033                                                         if ((cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
2034                                                                 rx_dma_stop(card, ch);
2035                                                         }
2036                                                         cpc_tty_receive(d);
2037                                                         rx_dma_start(card, ch);
2038                                                 } else 
2039 #endif
2040                                                 {
2041                                                         if ((cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
2042                                                                 rx_dma_stop(card, ch);
2043                                                         }
2044                                                         cpc_net_rx(dev);
2045                                                         /* Discard invalid frames */
2046                                                         dev->stats.rx_errors++;
2047                                                         dev->stats.rx_over_errors++;
2048                                                         chan->rx_first_bd = 0;
2049                                                         chan->rx_last_bd = N_DMA_RX_BUF - 1;
2050                                                         rx_dma_start(card, ch);
2051                                                 }
2052                                         }
2053                                 }
2054                                 if (status & IR0_DRX(IR0_DMIB, ch)) {
2055                                         if (drx_stat & DSR_EOM) {
2056                                                 if (card->hw.type == PC300_TE) {
2057                                                         cpc_writeb(card->hw.falcbase +
2058                                                                    card->hw.cpld_reg2,
2059                                                                    cpc_readb (card->hw.falcbase +
2060                                                                         card->hw.cpld_reg2) |
2061                                                                    (CPLD_REG2_FALC_LED1 << (2 * ch)));
2062                                                 }
2063 #ifdef CONFIG_PC300_MLPPP
2064                                                 if (chan->conf.proto == PC300_PROTO_MLPPP) {
2065                                                         /* verify if driver is TTY */
2066                                                         cpc_tty_receive(d);
2067                                                 } else {
2068                                                         cpc_net_rx(dev);
2069                                                 }
2070 #else
2071                                                 cpc_net_rx(dev);
2072 #endif
2073                                                 if (card->hw.type == PC300_TE) {
2074                                                         cpc_writeb(card->hw.falcbase +
2075                                                                    card->hw.cpld_reg2,
2076                                                                    cpc_readb (card->hw.falcbase +
2077                                                                                 card->hw.cpld_reg2) &
2078                                                                    ~ (CPLD_REG2_FALC_LED1 << (2 * ch)));
2079                                                 }
2080                                         }
2081                                 }
2082                                 if (!(dsr_rx = cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
2083 #ifdef PC300_DEBUG_INTR
2084                 printk("%s: RX intr chan[%d] (st=0x%08lx, dsr=0x%02x, dsr2=0x%02x)\n",
2085                         dev->name, ch, status, drx_stat, dsr_rx);
2086 #endif
2087                                         cpc_writeb(scabase + DSR_RX(ch), (dsr_rx | DSR_DE) & 0xfe);
2088                                 }
2089                         }
2090
2091             /**** Transmission ****/
2092                         if (status & IR0_DTX((IR0_EFT | IR0_DMIA | IR0_DMIB), ch)) {
2093                                 ucchar dtx_stat = cpc_readb(scabase + DSR_TX(ch));
2094
2095                                 /* Clear TX interrupts */
2096                                 cpc_writeb(scabase + DSR_TX(ch), dtx_stat | DSR_DWE);
2097
2098 #ifdef PC300_DEBUG_INTR
2099                                 printk ("sca_intr: TX intr chan[%d] (st=0x%08lx, dsr=0x%02x)\n",
2100                                          ch, status, dtx_stat);
2101 #endif
2102                                 if (status & IR0_DTX(IR0_EFT, ch)) {
2103                                         if (dtx_stat & DSR_UDRF) {
2104                                                 if (cpc_readb (scabase + M_REG(TBN, ch)) != 0) {
2105                                                         cpc_writeb(scabase + M_REG(CMD,ch), CMD_TX_BUF_CLR);
2106                                                 }
2107                                                 if (card->hw.type == PC300_TE) {
2108                                                         cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
2109                                                                    cpc_readb (card->hw.falcbase + 
2110                                                                                    card->hw.cpld_reg2) &
2111                                                                    ~ (CPLD_REG2_FALC_LED1 << (2 * ch)));
2112                                                 }
2113                                                 dev->stats.tx_errors++;
2114                                                 dev->stats.tx_fifo_errors++;
2115                                                 sca_tx_intr(d);
2116                                         }
2117                                 }
2118                                 if (status & IR0_DTX(IR0_DMIA, ch)) {
2119                                         if (dtx_stat & DSR_BOF) {
2120                                         }
2121                                 }
2122                                 if (status & IR0_DTX(IR0_DMIB, ch)) {
2123                                         if (dtx_stat & DSR_EOM) {
2124                                                 if (card->hw.type == PC300_TE) {
2125                                                         cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
2126                                                                    cpc_readb (card->hw.falcbase +
2127                                                                                         card->hw.cpld_reg2) &
2128                                                                    ~ (CPLD_REG2_FALC_LED1 << (2 * ch)));
2129                                                 }
2130                                                 sca_tx_intr(d);
2131                                         }
2132                                 }
2133                         }
2134
2135             /**** MSCI ****/
2136                         if (status & IR0_M(IR0_RXINTA, ch)) {
2137                                 ucchar st1 = cpc_readb(scabase + M_REG(ST1, ch));
2138
2139                                 /* Clear MSCI interrupts */
2140                                 cpc_writeb(scabase + M_REG(ST1, ch), st1);
2141
2142 #ifdef PC300_DEBUG_INTR
2143                                 printk("sca_intr: MSCI intr chan[%d] (st=0x%08lx, st1=0x%02x)\n",
2144                                          ch, status, st1);
2145 #endif
2146                                 if (st1 & ST1_CDCD) {   /* DCD changed */
2147                                         if (cpc_readb(scabase + M_REG(ST3, ch)) & ST3_DCD) {
2148                                                 printk ("%s: DCD is OFF. Going administrative down.\n",
2149                                                          dev->name);
2150 #ifdef CONFIG_PC300_MLPPP
2151                                                 if (chan->conf.proto != PC300_PROTO_MLPPP) {
2152                                                         netif_carrier_off(dev);
2153                                                 }
2154 #else
2155                                                 netif_carrier_off(dev);
2156
2157 #endif
2158                                                 card->chan[ch].d.line_off++;
2159                                         } else {        /* DCD = 1 */
2160                                                 printk ("%s: DCD is ON. Going administrative up.\n",
2161                                                          dev->name);
2162 #ifdef CONFIG_PC300_MLPPP
2163                                                 if (chan->conf.proto != PC300_PROTO_MLPPP)
2164                                                         /* verify if driver is not TTY */
2165 #endif
2166                                                         netif_carrier_on(dev);
2167                                                 card->chan[ch].d.line_on++;
2168                                         }
2169                                 }
2170                         }
2171                         spin_unlock(&card->card_lock);
2172                 }
2173                 if (++intr_count == 10)
2174                         /* Too much work at this board. Force exit */
2175                         break;
2176         }
2177 }
2178
2179 static void falc_t1_loop_detection(pc300_t * card, int ch, ucchar frs1)
2180 {
2181         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2182         falc_t *pfalc = (falc_t *) & chan->falc;
2183         void __iomem *falcbase = card->hw.falcbase;
2184
2185         if (((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_XPRBS) == 0) &&
2186             !pfalc->loop_gen) {
2187                 if (frs1 & FRS1_LLBDD) {
2188                         // A Line Loop Back Deactivation signal detected
2189                         if (pfalc->loop_active) {
2190                                 falc_remote_loop(card, ch, 0);
2191                         }
2192                 } else {
2193                         if ((frs1 & FRS1_LLBAD) &&
2194                             ((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) == 0)) {
2195                                 // A Line Loop Back Activation signal detected  
2196                                 if (!pfalc->loop_active) {
2197                                         falc_remote_loop(card, ch, 1);
2198                                 }
2199                         }
2200                 }
2201         }
2202 }
2203
2204 static void falc_e1_loop_detection(pc300_t * card, int ch, ucchar rsp)
2205 {
2206         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2207         falc_t *pfalc = (falc_t *) & chan->falc;
2208         void __iomem *falcbase = card->hw.falcbase;
2209
2210         if (((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_XPRBS) == 0) &&
2211             !pfalc->loop_gen) {
2212                 if (rsp & RSP_LLBDD) {
2213                         // A Line Loop Back Deactivation signal detected
2214                         if (pfalc->loop_active) {
2215                                 falc_remote_loop(card, ch, 0);
2216                         }
2217                 } else {
2218                         if ((rsp & RSP_LLBAD) &&
2219                             ((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) == 0)) {
2220                                 // A Line Loop Back Activation signal detected  
2221                                 if (!pfalc->loop_active) {
2222                                         falc_remote_loop(card, ch, 1);
2223                                 }
2224                         }
2225                 }
2226         }
2227 }
2228
2229 static void falc_t1_intr(pc300_t * card, int ch)
2230 {
2231         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2232         falc_t *pfalc = (falc_t *) & chan->falc;
2233         void __iomem *falcbase = card->hw.falcbase;
2234         ucchar isr0, isr3, gis;
2235         ucchar dummy;
2236
2237         while ((gis = cpc_readb(falcbase + F_REG(GIS, ch))) != 0) {
2238                 if (gis & GIS_ISR0) {
2239                         isr0 = cpc_readb(falcbase + F_REG(FISR0, ch));
2240                         if (isr0 & FISR0_PDEN) {
2241                                 /* Read the bit to clear the situation */
2242                                 if (cpc_readb(falcbase + F_REG(FRS1, ch)) &
2243                                     FRS1_PDEN) {
2244                                         pfalc->pden++;
2245                                 }
2246                         }
2247                 }
2248
2249                 if (gis & GIS_ISR1) {
2250                         dummy = cpc_readb(falcbase + F_REG(FISR1, ch));
2251                 }
2252
2253                 if (gis & GIS_ISR2) {
2254                         dummy = cpc_readb(falcbase + F_REG(FISR2, ch));
2255                 }
2256
2257                 if (gis & GIS_ISR3) {
2258                         isr3 = cpc_readb(falcbase + F_REG(FISR3, ch));
2259                         if (isr3 & FISR3_SEC) {
2260                                 pfalc->sec++;
2261                                 falc_update_stats(card, ch);
2262                                 falc_check_status(card, ch,
2263                                                   cpc_readb(falcbase + F_REG(FRS0, ch)));
2264                         }
2265                         if (isr3 & FISR3_ES) {
2266                                 pfalc->es++;
2267                         }
2268                         if (isr3 & FISR3_LLBSC) {
2269                                 falc_t1_loop_detection(card, ch,
2270                                                        cpc_readb(falcbase + F_REG(FRS1, ch)));
2271                         }
2272                 }
2273         }
2274 }
2275
2276 static void falc_e1_intr(pc300_t * card, int ch)
2277 {
2278         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2279         falc_t *pfalc = (falc_t *) & chan->falc;
2280         void __iomem *falcbase = card->hw.falcbase;
2281         ucchar isr1, isr2, isr3, gis, rsp;
2282         ucchar dummy;
2283
2284         while ((gis = cpc_readb(falcbase + F_REG(GIS, ch))) != 0) {
2285                 rsp = cpc_readb(falcbase + F_REG(RSP, ch));
2286
2287                 if (gis & GIS_ISR0) {
2288                         dummy = cpc_readb(falcbase + F_REG(FISR0, ch));
2289                 }
2290                 if (gis & GIS_ISR1) {
2291                         isr1 = cpc_readb(falcbase + F_REG(FISR1, ch));
2292                         if (isr1 & FISR1_XMB) {
2293                                 if ((pfalc->xmb_cause & 2)
2294                                     && pfalc->multiframe_mode) {
2295                                         if (cpc_readb (falcbase + F_REG(FRS0, ch)) & 
2296                                                                         (FRS0_LOS | FRS0_AIS | FRS0_LFA)) {
2297                                                 cpc_writeb(falcbase + F_REG(XSP, ch),
2298                                                            cpc_readb(falcbase + F_REG(XSP, ch))
2299                                                            & ~XSP_AXS);
2300                                         } else {
2301                                                 cpc_writeb(falcbase + F_REG(XSP, ch),
2302                                                            cpc_readb(falcbase + F_REG(XSP, ch))
2303                                                            | XSP_AXS);
2304                                         }
2305                                 }
2306                                 pfalc->xmb_cause = 0;
2307                                 cpc_writeb(falcbase + F_REG(IMR1, ch),
2308                                            cpc_readb(falcbase + F_REG(IMR1, ch)) | IMR1_XMB);
2309                         }
2310                         if (isr1 & FISR1_LLBSC) {
2311                                 falc_e1_loop_detection(card, ch, rsp);
2312                         }
2313                 }
2314                 if (gis & GIS_ISR2) {
2315                         isr2 = cpc_readb(falcbase + F_REG(FISR2, ch));
2316                         if (isr2 & FISR2_T400MS) {
2317                                 cpc_writeb(falcbase + F_REG(XSW, ch),
2318                                            cpc_readb(falcbase + F_REG(XSW, ch)) | XSW_XRA);
2319                         }
2320                         if (isr2 & FISR2_MFAR) {
2321                                 cpc_writeb(falcbase + F_REG(XSW, ch),
2322                                            cpc_readb(falcbase + F_REG(XSW, ch)) & ~XSW_XRA);
2323                         }
2324                         if (isr2 & (FISR2_FAR | FISR2_LFA | FISR2_AIS | FISR2_LOS)) {
2325                                 pfalc->xmb_cause |= 2;
2326                                 cpc_writeb(falcbase + F_REG(IMR1, ch),
2327                                            cpc_readb(falcbase + F_REG(IMR1, ch)) & ~IMR1_XMB);
2328                         }
2329                 }
2330                 if (gis & GIS_ISR3) {
2331                         isr3 = cpc_readb(falcbase + F_REG(FISR3, ch));
2332                         if (isr3 & FISR3_SEC) {
2333                                 pfalc->sec++;
2334                                 falc_update_stats(card, ch);
2335                                 falc_check_status(card, ch,
2336                                                   cpc_readb(falcbase + F_REG(FRS0, ch)));
2337                         }
2338                         if (isr3 & FISR3_ES) {
2339                                 pfalc->es++;
2340                         }
2341                 }
2342         }
2343 }
2344
2345 static void falc_intr(pc300_t * card)
2346 {
2347         int ch;
2348
2349         for (ch = 0; ch < card->hw.nchan; ch++) {
2350                 pc300ch_t *chan = &card->chan[ch];
2351                 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
2352
2353                 if (conf->media == IF_IFACE_T1) {
2354                         falc_t1_intr(card, ch);
2355                 } else {
2356                         falc_e1_intr(card, ch);
2357                 }
2358         }
2359 }
2360
2361 static irqreturn_t cpc_intr(int irq, void *dev_id)
2362 {
2363         pc300_t *card = dev_id;
2364         volatile ucchar plx_status;
2365
2366         if (!card) {
2367 #ifdef PC300_DEBUG_INTR
2368                 printk("cpc_intr: spurious intr %d\n", irq);
2369 #endif
2370                 return IRQ_NONE;                /* spurious intr */
2371         }
2372
2373         if (!card->hw.rambase) {
2374 #ifdef PC300_DEBUG_INTR
2375                 printk("cpc_intr: spurious intr2 %d\n", irq);
2376 #endif
2377                 return IRQ_NONE;                /* spurious intr */
2378         }
2379
2380         switch (card->hw.type) {
2381                 case PC300_RSV:
2382                 case PC300_X21:
2383                         sca_intr(card);
2384                         break;
2385
2386                 case PC300_TE:
2387                         while ( (plx_status = (cpc_readb(card->hw.plxbase + card->hw.intctl_reg) &
2388                                  (PLX_9050_LINT1_STATUS | PLX_9050_LINT2_STATUS))) != 0) {
2389                                 if (plx_status & PLX_9050_LINT1_STATUS) {       /* SCA Interrupt */
2390                                         sca_intr(card);
2391                                 }
2392                                 if (plx_status & PLX_9050_LINT2_STATUS) {       /* FALC Interrupt */
2393                                         falc_intr(card);
2394                                 }
2395                         }
2396                         break;
2397         }
2398         return IRQ_HANDLED;
2399 }
2400
2401 static void cpc_sca_status(pc300_t * card, int ch)
2402 {
2403         ucchar ilar;
2404         void __iomem *scabase = card->hw.scabase;
2405         unsigned long flags;
2406
2407         tx_dma_buf_check(card, ch);
2408         rx_dma_buf_check(card, ch);
2409         ilar = cpc_readb(scabase + ILAR);
2410         printk ("ILAR=0x%02x, WCRL=0x%02x, PCR=0x%02x, BTCR=0x%02x, BOLR=0x%02x\n",
2411                  ilar, cpc_readb(scabase + WCRL), cpc_readb(scabase + PCR),
2412                  cpc_readb(scabase + BTCR), cpc_readb(scabase + BOLR));
2413         printk("TX_CDA=0x%08x, TX_EDA=0x%08x\n",
2414                cpc_readl(scabase + DTX_REG(CDAL, ch)),
2415                cpc_readl(scabase + DTX_REG(EDAL, ch)));
2416         printk("RX_CDA=0x%08x, RX_EDA=0x%08x, BFL=0x%04x\n",
2417                cpc_readl(scabase + DRX_REG(CDAL, ch)),
2418                cpc_readl(scabase + DRX_REG(EDAL, ch)),
2419                cpc_readw(scabase + DRX_REG(BFLL, ch)));
2420         printk("DMER=0x%02x, DSR_TX=0x%02x, DSR_RX=0x%02x\n",
2421                cpc_readb(scabase + DMER), cpc_readb(scabase + DSR_TX(ch)),
2422                cpc_readb(scabase + DSR_RX(ch)));
2423         printk("DMR_TX=0x%02x, DMR_RX=0x%02x, DIR_TX=0x%02x, DIR_RX=0x%02x\n",
2424                cpc_readb(scabase + DMR_TX(ch)), cpc_readb(scabase + DMR_RX(ch)),
2425                cpc_readb(scabase + DIR_TX(ch)),
2426                cpc_readb(scabase + DIR_RX(ch)));
2427         printk("DCR_TX=0x%02x, DCR_RX=0x%02x, FCT_TX=0x%02x, FCT_RX=0x%02x\n",
2428                cpc_readb(scabase + DCR_TX(ch)), cpc_readb(scabase + DCR_RX(ch)),
2429                cpc_readb(scabase + FCT_TX(ch)),
2430                cpc_readb(scabase + FCT_RX(ch)));
2431         printk("MD0=0x%02x, MD1=0x%02x, MD2=0x%02x, MD3=0x%02x, IDL=0x%02x\n",
2432                cpc_readb(scabase + M_REG(MD0, ch)),
2433                cpc_readb(scabase + M_REG(MD1, ch)),
2434                cpc_readb(scabase + M_REG(MD2, ch)),
2435                cpc_readb(scabase + M_REG(MD3, ch)),
2436                cpc_readb(scabase + M_REG(IDL, ch)));
2437         printk("CMD=0x%02x, SA0=0x%02x, SA1=0x%02x, TFN=0x%02x, CTL=0x%02x\n",
2438                cpc_readb(scabase + M_REG(CMD, ch)),
2439                cpc_readb(scabase + M_REG(SA0, ch)),
2440                cpc_readb(scabase + M_REG(SA1, ch)),
2441                cpc_readb(scabase + M_REG(TFN, ch)),
2442                cpc_readb(scabase + M_REG(CTL, ch)));
2443         printk("ST0=0x%02x, ST1=0x%02x, ST2=0x%02x, ST3=0x%02x, ST4=0x%02x\n",
2444                cpc_readb(scabase + M_REG(ST0, ch)),
2445                cpc_readb(scabase + M_REG(ST1, ch)),
2446                cpc_readb(scabase + M_REG(ST2, ch)),
2447                cpc_readb(scabase + M_REG(ST3, ch)),
2448                cpc_readb(scabase + M_REG(ST4, ch)));
2449         printk ("CST0=0x%02x, CST1=0x%02x, CST2=0x%02x, CST3=0x%02x, FST=0x%02x\n",
2450                  cpc_readb(scabase + M_REG(CST0, ch)),
2451                  cpc_readb(scabase + M_REG(CST1, ch)),
2452                  cpc_readb(scabase + M_REG(CST2, ch)),
2453                  cpc_readb(scabase + M_REG(CST3, ch)),
2454                  cpc_readb(scabase + M_REG(FST, ch)));
2455         printk("TRC0=0x%02x, TRC1=0x%02x, RRC=0x%02x, TBN=0x%02x, RBN=0x%02x\n",
2456                cpc_readb(scabase + M_REG(TRC0, ch)),
2457                cpc_readb(scabase + M_REG(TRC1, ch)),
2458                cpc_readb(scabase + M_REG(RRC, ch)),
2459                cpc_readb(scabase + M_REG(TBN, ch)),
2460                cpc_readb(scabase + M_REG(RBN, ch)));
2461         printk("TFS=0x%02x, TNR0=0x%02x, TNR1=0x%02x, RNR=0x%02x\n",
2462                cpc_readb(scabase + M_REG(TFS, ch)),
2463                cpc_readb(scabase + M_REG(TNR0, ch)),
2464                cpc_readb(scabase + M_REG(TNR1, ch)),
2465                cpc_readb(scabase + M_REG(RNR, ch)));
2466         printk("TCR=0x%02x, RCR=0x%02x, TNR1=0x%02x, RNR=0x%02x\n",
2467                cpc_readb(scabase + M_REG(TCR, ch)),
2468                cpc_readb(scabase + M_REG(RCR, ch)),
2469                cpc_readb(scabase + M_REG(TNR1, ch)),
2470                cpc_readb(scabase + M_REG(RNR, ch)));
2471         printk("TXS=0x%02x, RXS=0x%02x, EXS=0x%02x, TMCT=0x%02x, TMCR=0x%02x\n",
2472                cpc_readb(scabase + M_REG(TXS, ch)),
2473                cpc_readb(scabase + M_REG(RXS, ch)),
2474                cpc_readb(scabase + M_REG(EXS, ch)),
2475                cpc_readb(scabase + M_REG(TMCT, ch)),
2476                cpc_readb(scabase + M_REG(TMCR, ch)));
2477         printk("IE0=0x%02x, IE1=0x%02x, IE2=0x%02x, IE4=0x%02x, FIE=0x%02x\n",
2478                cpc_readb(scabase + M_REG(IE0, ch)),
2479                cpc_readb(scabase + M_REG(IE1, ch)),
2480                cpc_readb(scabase + M_REG(IE2, ch)),
2481                cpc_readb(scabase + M_REG(IE4, ch)),
2482                cpc_readb(scabase + M_REG(FIE, ch)));
2483         printk("IER0=0x%08x\n", cpc_readl(scabase + IER0));
2484
2485         if (ilar != 0) {
2486                 CPC_LOCK(card, flags);
2487                 cpc_writeb(scabase + ILAR, ilar);
2488                 cpc_writeb(scabase + DMER, 0x80);
2489                 CPC_UNLOCK(card, flags);
2490         }
2491 }
2492
2493 static void cpc_falc_status(pc300_t * card, int ch)
2494 {
2495         pc300ch_t *chan = &card->chan[ch];
2496         falc_t *pfalc = (falc_t *) & chan->falc;
2497         unsigned long flags;
2498
2499         CPC_LOCK(card, flags);
2500         printk("CH%d:   %s %s  %d channels\n",
2501                ch, (pfalc->sync ? "SYNC" : ""), (pfalc->active ? "ACTIVE" : ""),
2502                pfalc->num_channels);
2503
2504         printk("        pden=%d,  los=%d,  losr=%d,  lfa=%d,  farec=%d\n",
2505                pfalc->pden, pfalc->los, pfalc->losr, pfalc->lfa, pfalc->farec);
2506         printk("        lmfa=%d,  ais=%d,  sec=%d,  es=%d,  rai=%d\n",
2507                pfalc->lmfa, pfalc->ais, pfalc->sec, pfalc->es, pfalc->rai);
2508         printk("        bec=%d,  fec=%d,  cvc=%d,  cec=%d,  ebc=%d\n",
2509                pfalc->bec, pfalc->fec, pfalc->cvc, pfalc->cec, pfalc->ebc);
2510
2511         printk("\n");
2512         printk("        STATUS: %s  %s  %s  %s  %s  %s\n",
2513                (pfalc->red_alarm ? "RED" : ""),
2514                (pfalc->blue_alarm ? "BLU" : ""),
2515                (pfalc->yellow_alarm ? "YEL" : ""),
2516                (pfalc->loss_fa ? "LFA" : ""),
2517                (pfalc->loss_mfa ? "LMF" : ""), (pfalc->prbs ? "PRB" : ""));
2518         CPC_UNLOCK(card, flags);
2519 }
2520
2521 static int cpc_change_mtu(struct net_device *dev, int new_mtu)
2522 {
2523         if ((new_mtu < 128) || (new_mtu > PC300_DEF_MTU))
2524                 return -EINVAL;
2525         dev->mtu = new_mtu;
2526         return 0;
2527 }
2528
2529 static int cpc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2530 {
2531         pc300dev_t *d = (pc300dev_t *) dev->priv;
2532         pc300ch_t *chan = (pc300ch_t *) d->chan;
2533         pc300_t *card = (pc300_t *) chan->card;
2534         pc300conf_t conf_aux;
2535         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
2536         int ch = chan->channel;
2537         void __user *arg = ifr->ifr_data;
2538         struct if_settings *settings = &ifr->ifr_settings;
2539         void __iomem *scabase = card->hw.scabase;
2540
2541         if (!capable(CAP_NET_ADMIN))
2542                 return -EPERM;
2543
2544         switch (cmd) {
2545                 case SIOCGPC300CONF:
2546 #ifdef CONFIG_PC300_MLPPP
2547                         if (conf->proto != PC300_PROTO_MLPPP) {
2548                                 conf->proto = /* FIXME hdlc->proto.id */ 0;
2549                         }
2550 #else
2551                         conf->proto = /* FIXME hdlc->proto.id */ 0;
2552 #endif
2553                         memcpy(&conf_aux.conf, conf, sizeof(pc300chconf_t));
2554                         memcpy(&conf_aux.hw, &card->hw, sizeof(pc300hw_t));
2555                         if (!arg || 
2556                                 copy_to_user(arg, &conf_aux, sizeof(pc300conf_t))) 
2557                                 return -EINVAL;
2558                         return 0;
2559                 case SIOCSPC300CONF:
2560                         if (!capable(CAP_NET_ADMIN))
2561                                 return -EPERM;
2562                         if (!arg || 
2563                                 copy_from_user(&conf_aux.conf, arg, sizeof(pc300chconf_t)))
2564                                 return -EINVAL;
2565                         if (card->hw.cpld_id < 0x02 &&
2566                             conf_aux.conf.fr_mode == PC300_FR_UNFRAMED) {
2567                                 /* CPLD_ID < 0x02 doesn't support Unframed E1 */
2568                                 return -EINVAL;
2569                         }
2570 #ifdef CONFIG_PC300_MLPPP
2571                         if (conf_aux.conf.proto == PC300_PROTO_MLPPP) {
2572                                 if (conf->proto != PC300_PROTO_MLPPP) {
2573                                         memcpy(conf, &conf_aux.conf, sizeof(pc300chconf_t));
2574                                         cpc_tty_init(d);        /* init TTY driver */
2575                                 }
2576                         } else {
2577                                 if (conf_aux.conf.proto == 0xffff) {
2578                                         if (conf->proto == PC300_PROTO_MLPPP){ 
2579                                                 /* ifdown interface */
2580                                                 cpc_close(dev);
2581                                         }
2582                                 } else {
2583                                         memcpy(conf, &conf_aux.conf, sizeof(pc300chconf_t));
2584                                         /* FIXME hdlc->proto.id = conf->proto; */
2585                                 }
2586                         }
2587 #else
2588                         memcpy(conf, &conf_aux.conf, sizeof(pc300chconf_t));
2589                         /* FIXME hdlc->proto.id = conf->proto; */
2590 #endif
2591                         return 0;
2592                 case SIOCGPC300STATUS:
2593                         cpc_sca_status(card, ch);
2594                         return 0;
2595                 case SIOCGPC300FALCSTATUS:
2596                         cpc_falc_status(card, ch);
2597                         return 0;
2598
2599                 case SIOCGPC300UTILSTATS:
2600                         {
2601                                 if (!arg) {     /* clear statistics */
2602                                         memset(&dev->stats, 0, sizeof(dev->stats));
2603                                         if (card->hw.type == PC300_TE) {
2604                                                 memset(&chan->falc, 0, sizeof(falc_t));
2605                                         }
2606                                 } else {
2607                                         pc300stats_t pc300stats;
2608
2609                                         memset(&pc300stats, 0, sizeof(pc300stats_t));
2610                                         pc300stats.hw_type = card->hw.type;
2611                                         pc300stats.line_on = card->chan[ch].d.line_on;
2612                                         pc300stats.line_off = card->chan[ch].d.line_off;
2613                                         memcpy(&pc300stats.gen_stats, &dev->stats,
2614                                                sizeof(dev->stats));
2615                                         if (card->hw.type == PC300_TE)
2616                                                 memcpy(&pc300stats.te_stats,&chan->falc,sizeof(falc_t));
2617                                         if (copy_to_user(arg, &pc300stats, sizeof(pc300stats_t)))
2618                                                 return -EFAULT;
2619                                 }
2620                                 return 0;
2621                         }
2622
2623                 case SIOCGPC300UTILSTATUS:
2624                         {
2625                                 struct pc300status pc300status;
2626
2627                                 pc300status.hw_type = card->hw.type;
2628                                 if (card->hw.type == PC300_TE) {
2629                                         pc300status.te_status.sync = chan->falc.sync;
2630                                         pc300status.te_status.red_alarm = chan->falc.red_alarm;
2631                                         pc300status.te_status.blue_alarm = chan->falc.blue_alarm;
2632                                         pc300status.te_status.loss_fa = chan->falc.loss_fa;
2633                                         pc300status.te_status.yellow_alarm =chan->falc.yellow_alarm;
2634                                         pc300status.te_status.loss_mfa = chan->falc.loss_mfa;
2635                                         pc300status.te_status.prbs = chan->falc.prbs;
2636                                 } else {
2637                                         pc300status.gen_status.dcd =
2638                                                 !(cpc_readb (scabase + M_REG(ST3, ch)) & ST3_DCD);
2639                                         pc300status.gen_status.cts =
2640                                                 !(cpc_readb (scabase + M_REG(ST3, ch)) & ST3_CTS);
2641                                         pc300status.gen_status.rts =
2642                                                 !(cpc_readb (scabase + M_REG(CTL, ch)) & CTL_RTS);
2643                                         pc300status.gen_status.dtr =
2644                                                 !(cpc_readb (scabase + M_REG(CTL, ch)) & CTL_DTR);
2645                                         /* There is no DSR in HD64572 */
2646                                 }
2647                                 if (!arg
2648                                     || copy_to_user(arg, &pc300status, sizeof(pc300status_t)))
2649                                                 return -EINVAL;
2650                                 return 0;
2651                         }
2652
2653                 case SIOCSPC300TRACE:
2654                         /* Sets/resets a trace_flag for the respective device */
2655                         if (!arg || copy_from_user(&d->trace_on, arg,sizeof(unsigned char)))
2656                                         return -EINVAL;
2657                         return 0;
2658
2659                 case SIOCSPC300LOOPBACK:
2660                         {
2661                                 struct pc300loopback pc300loop;
2662
2663                                 /* TE boards only */
2664                                 if (card->hw.type != PC300_TE)
2665                                         return -EINVAL;
2666
2667                                 if (!arg || 
2668                                         copy_from_user(&pc300loop, arg, sizeof(pc300loopback_t)))
2669                                                 return -EINVAL;
2670                                 switch (pc300loop.loop_type) {
2671                                         case PC300LOCLOOP:      /* Turn the local loop on/off */
2672                                                 falc_local_loop(card, ch, pc300loop.loop_on);
2673                                                 return 0;
2674
2675                                         case PC300REMLOOP:      /* Turn the remote loop on/off */
2676                                                 falc_remote_loop(card, ch, pc300loop.loop_on);
2677                                                 return 0;
2678
2679                                         case PC300PAYLOADLOOP:  /* Turn the payload loop on/off */
2680                                                 falc_payload_loop(card, ch, pc300loop.loop_on);
2681                                                 return 0;
2682
2683                                         case PC300GENLOOPUP:    /* Generate loop UP */
2684                                                 if (pc300loop.loop_on) {
2685                                                         falc_generate_loop_up_code (card, ch);
2686                                                 } else {
2687                                                         turn_off_xlu(card, ch);
2688                                                 }
2689                                                 return 0;
2690
2691                                         case PC300GENLOOPDOWN:  /* Generate loop DOWN */
2692                                                 if (pc300loop.loop_on) {
2693                                                         falc_generate_loop_down_code (card, ch);
2694                                                 } else {
2695                                                         turn_off_xld(card, ch);
2696                                                 }
2697                                                 return 0;
2698
2699                                         default:
2700                                                 return -EINVAL;
2701                                 }
2702                         }
2703
2704                 case SIOCSPC300PATTERNTEST:
2705                         /* Turn the pattern test on/off and show the errors counter */
2706                         {
2707                                 struct pc300patterntst pc300patrntst;
2708
2709                                 /* TE boards only */
2710                                 if (card->hw.type != PC300_TE)
2711                                         return -EINVAL;
2712
2713                                 if (card->hw.cpld_id < 0x02) {
2714                                         /* CPLD_ID < 0x02 doesn't support pattern test */
2715                                         return -EINVAL;
2716                                 }
2717
2718                                 if (!arg || 
2719                                         copy_from_user(&pc300patrntst,arg,sizeof(pc300patterntst_t)))
2720                                                 return -EINVAL;
2721                                 if (pc300patrntst.patrntst_on == 2) {
2722                                         if (chan->falc.prbs == 0) {
2723                                                 falc_pattern_test(card, ch, 1);
2724                                         }
2725                                         pc300patrntst.num_errors =
2726                                                 falc_pattern_test_error(card, ch);
2727                                         if (!arg
2728                                             || copy_to_user(arg, &pc300patrntst,
2729                                                             sizeof (pc300patterntst_t)))
2730                                                         return -EINVAL;
2731                                 } else {
2732                                         falc_pattern_test(card, ch, pc300patrntst.patrntst_on);
2733                                 }
2734                                 return 0;
2735                         }
2736
2737                 case SIOCWANDEV:
2738                         switch (ifr->ifr_settings.type) {
2739                                 case IF_GET_IFACE:
2740                                 {
2741                                         const size_t size = sizeof(sync_serial_settings);
2742                                         ifr->ifr_settings.type = conf->media;
2743                                         if (ifr->ifr_settings.size < size) {
2744                                                 /* data size wanted */
2745                                                 ifr->ifr_settings.size = size;
2746                                                 return -ENOBUFS;
2747                                         }
2748         
2749                                         if (copy_to_user(settings->ifs_ifsu.sync,
2750                                                          &conf->phys_settings, size)) {
2751                                                 return -EFAULT;
2752                                         }
2753                                         return 0;
2754                                 }
2755
2756                                 case IF_IFACE_V35:
2757                                 case IF_IFACE_V24:
2758                                 case IF_IFACE_X21:
2759                                 {
2760                                         const size_t size = sizeof(sync_serial_settings);
2761
2762                                         if (!capable(CAP_NET_ADMIN)) {
2763                                                 return -EPERM;
2764                                         }
2765                                         /* incorrect data len? */
2766                                         if (ifr->ifr_settings.size != size) {
2767                                                 return -ENOBUFS;
2768                                         }
2769
2770                                         if (copy_from_user(&conf->phys_settings, 
2771                                                            settings->ifs_ifsu.sync, size)) {
2772                                                 return -EFAULT;
2773                                         }
2774
2775                                         if (conf->phys_settings.loopback) {
2776                                                 cpc_writeb(card->hw.scabase + M_REG(MD2, ch),
2777                                                         cpc_readb(card->hw.scabase + M_REG(MD2, ch)) | 
2778                                                         MD2_LOOP_MIR);
2779                                         }
2780                                         conf->media = ifr->ifr_settings.type;
2781                                         return 0;
2782                                 }
2783
2784                                 case IF_IFACE_T1:
2785                                 case IF_IFACE_E1:
2786                                 {
2787                                         const size_t te_size = sizeof(te1_settings);
2788                                         const size_t size = sizeof(sync_serial_settings);
2789
2790                                         if (!capable(CAP_NET_ADMIN)) {
2791                                                 return -EPERM;
2792                                         }
2793
2794                                         /* incorrect data len? */
2795                                         if (ifr->ifr_settings.size != te_size) {
2796                                                 return -ENOBUFS;
2797                                         }
2798
2799                                         if (copy_from_user(&conf->phys_settings, 
2800                                                            settings->ifs_ifsu.te1, size)) {
2801                                                 return -EFAULT;
2802                                         }/* Ignoring HDLC slot_map for a while */
2803                                         
2804                                         if (conf->phys_settings.loopback) {
2805                                                 cpc_writeb(card->hw.scabase + M_REG(MD2, ch),
2806                                                         cpc_readb(card->hw.scabase + M_REG(MD2, ch)) | 
2807                                                         MD2_LOOP_MIR);
2808                                         }
2809                                         conf->media = ifr->ifr_settings.type;
2810                                         return 0;
2811                                 }
2812                                 default:
2813                                         return hdlc_ioctl(dev, ifr, cmd);
2814                         }
2815
2816                 default:
2817                         return hdlc_ioctl(dev, ifr, cmd);
2818         }
2819 }
2820
2821 static int clock_rate_calc(uclong rate, uclong clock, int *br_io)
2822 {
2823         int br, tc;
2824         int br_pwr, error;
2825
2826         *br_io = 0;
2827
2828         if (rate == 0)
2829                 return (0);
2830
2831         for (br = 0, br_pwr = 1; br <= 9; br++, br_pwr <<= 1) {
2832                 if ((tc = clock / br_pwr / rate) <= 0xff) {
2833                         *br_io = br;
2834                         break;
2835                 }
2836         }
2837
2838         if (tc <= 0xff) {
2839                 error = ((rate - (clock / br_pwr / rate)) / rate) * 1000;
2840                 /* Errors bigger than +/- 1% won't be tolerated */
2841                 if (error < -10 || error > 10)
2842                         return (-1);
2843                 else
2844                         return (tc);
2845         } else {
2846                 return (-1);
2847         }
2848 }
2849
2850 static int ch_config(pc300dev_t * d)
2851 {
2852         pc300ch_t *chan = (pc300ch_t *) d->chan;
2853         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
2854         pc300_t *card = (pc300_t *) chan->card;
2855         void __iomem *scabase = card->hw.scabase;
2856         void __iomem *plxbase = card->hw.plxbase;
2857         int ch = chan->channel;
2858         uclong clkrate = chan->conf.phys_settings.clock_rate;
2859         uclong clktype = chan->conf.phys_settings.clock_type;
2860         ucshort encoding = chan->conf.proto_settings.encoding;
2861         ucshort parity = chan->conf.proto_settings.parity;   
2862         ucchar md0, md2;
2863     
2864         /* Reset the channel */
2865         cpc_writeb(scabase + M_REG(CMD, ch), CMD_CH_RST);
2866
2867         /* Configure the SCA registers */
2868         switch (parity) {
2869                 case PARITY_NONE:
2870                         md0 = MD0_BIT_SYNC;
2871                         break;
2872                 case PARITY_CRC16_PR0:
2873                         md0 = MD0_CRC16_0|MD0_CRCC0|MD0_BIT_SYNC;
2874                         break;
2875                 case PARITY_CRC16_PR1:
2876                         md0 = MD0_CRC16_1|MD0_CRCC0|MD0_BIT_SYNC;
2877                         break;
2878                 case PARITY_CRC32_PR1_CCITT:
2879                         md0 = MD0_CRC32|MD0_CRCC0|MD0_BIT_SYNC;
2880                         break;
2881                 case PARITY_CRC16_PR1_CCITT:
2882                 default:
2883                         md0 = MD0_CRC_CCITT|MD0_CRCC0|MD0_BIT_SYNC;
2884                         break;
2885         }
2886         switch (encoding) {
2887                 case ENCODING_NRZI:
2888                         md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_NRZI;
2889                         break;
2890                 case ENCODING_FM_MARK:  /* FM1 */
2891                         md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_FM1;
2892                         break;
2893                 case ENCODING_FM_SPACE: /* FM0 */
2894                         md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_FM0;
2895                         break;
2896                 case ENCODING_MANCHESTER: /* It's not working... */
2897                         md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_MANCH;
2898                         break;
2899                 case ENCODING_NRZ:
2900                 default:
2901                         md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_NRZ;
2902                         break;
2903         }
2904         cpc_writeb(scabase + M_REG(MD0, ch), md0);
2905         cpc_writeb(scabase + M_REG(MD1, ch), 0);
2906         cpc_writeb(scabase + M_REG(MD2, ch), md2);
2907         cpc_writeb(scabase + M_REG(IDL, ch), 0x7e);
2908         cpc_writeb(scabase + M_REG(CTL, ch), CTL_URSKP | CTL_IDLC);
2909
2910         /* Configure HW media */
2911         switch (card->hw.type) {
2912                 case PC300_RSV:
2913                         if (conf->media == IF_IFACE_V35) {
2914                                 cpc_writel((plxbase + card->hw.gpioc_reg),
2915                                            cpc_readl(plxbase + card->hw.gpioc_reg) | PC300_CHMEDIA_MASK(ch));
2916                         } else {
2917                                 cpc_writel((plxbase + card->hw.gpioc_reg),
2918                                            cpc_readl(plxbase + card->hw.gpioc_reg) & ~PC300_CHMEDIA_MASK(ch));
2919                         }
2920                         break;
2921
2922                 case PC300_X21:
2923                         break;
2924
2925                 case PC300_TE:
2926                         te_config(card, ch);
2927                         break;
2928         }
2929
2930         switch (card->hw.type) {
2931                 case PC300_RSV:
2932                 case PC300_X21:
2933                         if (clktype == CLOCK_INT || clktype == CLOCK_TXINT) {
2934                                 int tmc, br;
2935
2936                                 /* Calculate the clkrate parameters */
2937                                 tmc = clock_rate_calc(clkrate, card->hw.clock, &br);
2938                                 if (tmc < 0)
2939                                         return -EIO;
2940                                 cpc_writeb(scabase + M_REG(TMCT, ch), tmc);
2941                                 cpc_writeb(scabase + M_REG(TXS, ch),
2942                                            (TXS_DTRXC | TXS_IBRG | br));
2943                                 if (clktype == CLOCK_INT) {
2944                                         cpc_writeb(scabase + M_REG(TMCR, ch), tmc);
2945                                         cpc_writeb(scabase + M_REG(RXS, ch), 
2946                                                    (RXS_IBRG | br));
2947                                 } else {
2948                                         cpc_writeb(scabase + M_REG(TMCR, ch), 1);
2949                                         cpc_writeb(scabase + M_REG(RXS, ch), 0);
2950                                 }
2951                                 if (card->hw.type == PC300_X21) {
2952                                         cpc_writeb(scabase + M_REG(GPO, ch), 1);
2953                                         cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1 | EXS_RES1);
2954                                 } else {
2955                                         cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1);
2956                                 }
2957                         } else {
2958                                 cpc_writeb(scabase + M_REG(TMCT, ch), 1);
2959                                 if (clktype == CLOCK_EXT) {
2960                                         cpc_writeb(scabase + M_REG(TXS, ch), 
2961                                                    TXS_DTRXC);
2962                                 } else {
2963                                         cpc_writeb(scabase + M_REG(TXS, ch), 
2964                                                    TXS_DTRXC|TXS_RCLK);
2965                                 }
2966                                 cpc_writeb(scabase + M_REG(TMCR, ch), 1);
2967                                 cpc_writeb(scabase + M_REG(RXS, ch), 0);
2968                                 if (card->hw.type == PC300_X21) {
2969                                         cpc_writeb(scabase + M_REG(GPO, ch), 0);
2970                                         cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1 | EXS_RES1);
2971                                 } else {
2972                                         cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1);
2973                                 }
2974                         }
2975                         break;
2976
2977                 case PC300_TE:
2978                         /* SCA always receives clock from the FALC chip */
2979                         cpc_writeb(scabase + M_REG(TMCT, ch), 1);
2980                         cpc_writeb(scabase + M_REG(TXS, ch), 0);
2981                         cpc_writeb(scabase + M_REG(TMCR, ch), 1);
2982                         cpc_writeb(scabase + M_REG(RXS, ch), 0);
2983                         cpc_writeb(scabase + M_REG(EXS, ch), 0);
2984                         break;
2985         }
2986
2987         /* Enable Interrupts */
2988         cpc_writel(scabase + IER0,
2989                    cpc_readl(scabase + IER0) |
2990                    IR0_M(IR0_RXINTA, ch) |
2991                    IR0_DRX(IR0_EFT | IR0_DMIA | IR0_DMIB, ch) |
2992                    IR0_DTX(IR0_EFT | IR0_DMIA | IR0_DMIB, ch));
2993         cpc_writeb(scabase + M_REG(IE0, ch),
2994                    cpc_readl(scabase + M_REG(IE0, ch)) | IE0_RXINTA);
2995         cpc_writeb(scabase + M_REG(IE1, ch),
2996                    cpc_readl(scabase + M_REG(IE1, ch)) | IE1_CDCD);
2997
2998         return 0;
2999 }
3000
3001 static int rx_config(pc300dev_t * d)
3002 {
3003         pc300ch_t *chan = (pc300ch_t *) d->chan;
3004         pc300_t *card = (pc300_t *) chan->card;
3005         void __iomem *scabase = card->hw.scabase;
3006         int ch = chan->channel;
3007
3008         cpc_writeb(scabase + DSR_RX(ch), 0);
3009
3010         /* General RX settings */
3011         cpc_writeb(scabase + M_REG(RRC, ch), 0);
3012         cpc_writeb(scabase + M_REG(RNR, ch), 16);
3013
3014         /* Enable reception */
3015         cpc_writeb(scabase + M_REG(CMD, ch), CMD_RX_CRC_INIT);
3016         cpc_writeb(scabase + M_REG(CMD, ch), CMD_RX_ENA);
3017
3018         /* Initialize DMA stuff */
3019         chan->rx_first_bd = 0;
3020         chan->rx_last_bd = N_DMA_RX_BUF - 1;
3021         rx_dma_buf_init(card, ch);
3022         cpc_writeb(scabase + DCR_RX(ch), DCR_FCT_CLR);
3023         cpc_writeb(scabase + DMR_RX(ch), (DMR_TMOD | DMR_NF));
3024         cpc_writeb(scabase + DIR_RX(ch), (DIR_EOM | DIR_BOF));
3025
3026         /* Start DMA */
3027         rx_dma_start(card, ch);
3028
3029         return 0;
3030 }
3031
3032 static int tx_config(pc300dev_t * d)
3033 {
3034         pc300ch_t *chan = (pc300ch_t *) d->chan;
3035         pc300_t *card = (pc300_t *) chan->card;
3036         void __iomem *scabase = card->hw.scabase;
3037         int ch = chan->channel;
3038
3039         cpc_writeb(scabase + DSR_TX(ch), 0);
3040
3041         /* General TX settings */
3042         cpc_writeb(scabase + M_REG(TRC0, ch), 0);
3043         cpc_writeb(scabase + M_REG(TFS, ch), 32);
3044         cpc_writeb(scabase + M_REG(TNR0, ch), 20);
3045         cpc_writeb(scabase + M_REG(TNR1, ch), 48);
3046         cpc_writeb(scabase + M_REG(TCR, ch), 8);
3047
3048         /* Enable transmission */
3049         cpc_writeb(scabase + M_REG(CMD, ch), CMD_TX_CRC_INIT);
3050
3051         /* Initialize DMA stuff */
3052         chan->tx_first_bd = 0;
3053         chan->tx_next_bd = 0;
3054         tx_dma_buf_init(card, ch);
3055         cpc_writeb(scabase + DCR_TX(ch), DCR_FCT_CLR);
3056         cpc_writeb(scabase + DMR_TX(ch), (DMR_TMOD | DMR_NF));
3057         cpc_writeb(scabase + DIR_TX(ch), (DIR_EOM | DIR_BOF | DIR_UDRF));
3058         cpc_writel(scabase + DTX_REG(CDAL, ch), TX_BD_ADDR(ch, chan->tx_first_bd));
3059         cpc_writel(scabase + DTX_REG(EDAL, ch), TX_BD_ADDR(ch, chan->tx_next_bd));
3060
3061         return 0;
3062 }
3063
3064 static int cpc_attach(struct net_device *dev, unsigned short encoding,
3065                       unsigned short parity)
3066 {
3067         pc300dev_t *d = (pc300dev_t *)dev->priv;
3068         pc300ch_t *chan = (pc300ch_t *)d->chan;
3069         pc300_t *card = (pc300_t *)chan->card;
3070         pc300chconf_t *conf = (pc300chconf_t *)&chan->conf;
3071
3072         if (card->hw.type == PC300_TE) {
3073                 if (encoding != ENCODING_NRZ && encoding != ENCODING_NRZI) {
3074                         return -EINVAL;
3075                 }
3076         } else {
3077                 if (encoding != ENCODING_NRZ && encoding != ENCODING_NRZI &&
3078                     encoding != ENCODING_FM_MARK && encoding != ENCODING_FM_SPACE) {
3079                         /* Driver doesn't support ENCODING_MANCHESTER yet */
3080                         return -EINVAL;
3081                 }
3082         }
3083
3084         if (parity != PARITY_NONE && parity != PARITY_CRC16_PR0 &&
3085             parity != PARITY_CRC16_PR1 && parity != PARITY_CRC32_PR1_CCITT &&
3086             parity != PARITY_CRC16_PR1_CCITT) {
3087                 return -EINVAL;
3088         }
3089
3090         conf->proto_settings.encoding = encoding;
3091         conf->proto_settings.parity = parity;
3092         return 0;
3093 }
3094
3095 static int cpc_opench(pc300dev_t * d)
3096 {
3097         pc300ch_t *chan = (pc300ch_t *) d->chan;
3098         pc300_t *card = (pc300_t *) chan->card;
3099         int ch = chan->channel, rc;
3100         void __iomem *scabase = card->hw.scabase;
3101
3102         rc = ch_config(d);
3103         if (rc)
3104                 return rc;
3105
3106         rx_config(d);
3107
3108         tx_config(d);
3109
3110         /* Assert RTS and DTR */
3111         cpc_writeb(scabase + M_REG(CTL, ch),
3112                    cpc_readb(scabase + M_REG(CTL, ch)) & ~(CTL_RTS | CTL_DTR));
3113
3114         return 0;
3115 }
3116
3117 static void cpc_closech(pc300dev_t * d)
3118 {
3119         pc300ch_t *chan = (pc300ch_t *) d->chan;
3120         pc300_t *card = (pc300_t *) chan->card;
3121         falc_t *pfalc = (falc_t *) & chan->falc;
3122         int ch = chan->channel;
3123
3124         cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_CH_RST);
3125         rx_dma_stop(card, ch);
3126         tx_dma_stop(card, ch);
3127
3128         if (card->hw.type == PC300_TE) {
3129                 memset(pfalc, 0, sizeof(falc_t));
3130                 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
3131                            cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) &
3132                            ~((CPLD_REG2_FALC_TX_CLK | CPLD_REG2_FALC_RX_CLK |
3133                               CPLD_REG2_FALC_LED2) << (2 * ch)));
3134                 /* Reset the FALC chip */
3135                 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
3136                            cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
3137                            (CPLD_REG1_FALC_RESET << (2 * ch)));
3138                 udelay(10000);
3139                 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
3140                            cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) &
3141                            ~(CPLD_REG1_FALC_RESET << (2 * ch)));
3142         }
3143 }
3144
3145 int cpc_open(struct net_device *dev)
3146 {
3147         pc300dev_t *d = (pc300dev_t *) dev->priv;
3148         struct ifreq ifr;
3149         int result;
3150
3151 #ifdef  PC300_DEBUG_OTHER
3152         printk("pc300: cpc_open");
3153 #endif
3154
3155 #ifdef FIXME
3156         if (hdlc->proto.id == IF_PROTO_PPP) {
3157                 d->if_ptr = &hdlc->state.ppp.pppdev;
3158         }
3159 #endif
3160
3161         result = hdlc_open(dev);
3162         if (/* FIXME hdlc->proto.id == IF_PROTO_PPP*/ 0) {
3163                 dev->priv = d;
3164         }
3165         if (result) {
3166                 return result;
3167         }
3168
3169         sprintf(ifr.ifr_name, "%s", dev->name);
3170         result = cpc_opench(d);
3171         if (result)
3172                 goto err_out;
3173
3174         netif_start_queue(dev);
3175         return 0;
3176
3177 err_out:
3178         hdlc_close(dev);
3179         return result;
3180 }
3181
3182 static int cpc_close(struct net_device *dev)
3183 {
3184         pc300dev_t *d = (pc300dev_t *) dev->priv;
3185         pc300ch_t *chan = (pc300ch_t *) d->chan;
3186         pc300_t *card = (pc300_t *) chan->card;
3187         unsigned long flags;
3188
3189 #ifdef  PC300_DEBUG_OTHER
3190         printk("pc300: cpc_close");
3191 #endif
3192
3193         netif_stop_queue(dev);
3194
3195         CPC_LOCK(card, flags);
3196         cpc_closech(d);
3197         CPC_UNLOCK(card, flags);
3198
3199         hdlc_close(dev);
3200         if (/* FIXME hdlc->proto.id == IF_PROTO_PPP*/ 0) {
3201                 d->if_ptr = NULL;
3202         }
3203 #ifdef CONFIG_PC300_MLPPP
3204         if (chan->conf.proto == PC300_PROTO_MLPPP) {
3205                 cpc_tty_unregister_service(d);
3206                 chan->conf.proto = 0xffff;
3207         }
3208 #endif
3209
3210         return 0;
3211 }
3212
3213 static uclong detect_ram(pc300_t * card)
3214 {
3215         uclong i;
3216         ucchar data;
3217         void __iomem *rambase = card->hw.rambase;
3218
3219         card->hw.ramsize = PC300_RAMSIZE;
3220         /* Let's find out how much RAM is present on this board */
3221         for (i = 0; i < card->hw.ramsize; i++) {
3222                 data = (ucchar) (i & 0xff);
3223                 cpc_writeb(rambase + i, data);
3224                 if (cpc_readb(rambase + i) != data) {
3225                         break;
3226                 }
3227         }
3228         return (i);
3229 }
3230
3231 static void plx_init(pc300_t * card)
3232 {
3233         struct RUNTIME_9050 __iomem *plx_ctl = card->hw.plxbase;
3234
3235         /* Reset PLX */
3236         cpc_writel(&plx_ctl->init_ctrl,
3237                    cpc_readl(&plx_ctl->init_ctrl) | 0x40000000);
3238         udelay(10000L);
3239         cpc_writel(&plx_ctl->init_ctrl,
3240                    cpc_readl(&plx_ctl->init_ctrl) & ~0x40000000);
3241
3242         /* Reload Config. Registers from EEPROM */
3243         cpc_writel(&plx_ctl->init_ctrl,
3244                    cpc_readl(&plx_ctl->init_ctrl) | 0x20000000);
3245         udelay(10000L);
3246         cpc_writel(&plx_ctl->init_ctrl,
3247                    cpc_readl(&plx_ctl->init_ctrl) & ~0x20000000);
3248
3249 }
3250
3251 static inline void show_version(void)
3252 {
3253         char *rcsvers, *rcsdate, *tmp;
3254
3255         rcsvers = strchr(rcsid, ' ');
3256         rcsvers++;
3257         tmp = strchr(rcsvers, ' ');
3258         *tmp++ = '\0';
3259         rcsdate = strchr(tmp, ' ');
3260         rcsdate++;
3261         tmp = strrchr(rcsdate, ' ');
3262         *tmp = '\0';
3263         printk(KERN_INFO "Cyclades-PC300 driver %s %s (built %s %s)\n", 
3264                 rcsvers, rcsdate, __DATE__, __TIME__);
3265 }                               /* show_version */
3266
3267 static void cpc_init_card(pc300_t * card)
3268 {
3269         int i, devcount = 0;
3270         static int board_nbr = 1;
3271
3272         /* Enable interrupts on the PCI bridge */
3273         plx_init(card);
3274         cpc_writew(card->hw.plxbase + card->hw.intctl_reg,
3275                    cpc_readw(card->hw.plxbase + card->hw.intctl_reg) | 0x0040);
3276
3277 #ifdef USE_PCI_CLOCK
3278         /* Set board clock to PCI clock */
3279         cpc_writel(card->hw.plxbase + card->hw.gpioc_reg,
3280                    cpc_readl(card->hw.plxbase + card->hw.gpioc_reg) | 0x00000004UL);
3281         card->hw.clock = PC300_PCI_CLOCK;
3282 #else
3283         /* Set board clock to internal oscillator clock */
3284         cpc_writel(card->hw.plxbase + card->hw.gpioc_reg,
3285                    cpc_readl(card->hw.plxbase + card->hw.gpioc_reg) & ~0x00000004UL);
3286         card->hw.clock = PC300_OSC_CLOCK;
3287 #endif
3288
3289         /* Detect actual on-board RAM size */
3290         card->hw.ramsize = detect_ram(card);
3291
3292         /* Set Global SCA-II registers */
3293         cpc_writeb(card->hw.scabase + PCR, PCR_PR2);
3294         cpc_writeb(card->hw.scabase + BTCR, 0x10);
3295         cpc_writeb(card->hw.scabase + WCRL, 0);
3296         cpc_writeb(card->hw.scabase + DMER, 0x80);
3297
3298         if (card->hw.type == PC300_TE) {
3299                 ucchar reg1;
3300
3301                 /* Check CPLD version */
3302                 reg1 = cpc_readb(card->hw.falcbase + CPLD_REG1);
3303                 cpc_writeb(card->hw.falcbase + CPLD_REG1, (reg1 + 0x5a));
3304                 if (cpc_readb(card->hw.falcbase + CPLD_REG1) == reg1) {
3305                         /* New CPLD */
3306                         card->hw.cpld_id = cpc_readb(card->hw.falcbase + CPLD_ID_REG);
3307                         card->hw.cpld_reg1 = CPLD_V2_REG1;
3308                         card->hw.cpld_reg2 = CPLD_V2_REG2;
3309                 } else {
3310                         /* old CPLD */
3311                         card->hw.cpld_id = 0;
3312                         card->hw.cpld_reg1 = CPLD_REG1;
3313                         card->hw.cpld_reg2 = CPLD_REG2;
3314                         cpc_writeb(card->hw.falcbase + CPLD_REG1, reg1);
3315                 }
3316
3317                 /* Enable the board's global clock */
3318                 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
3319                            cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
3320                            CPLD_REG1_GLOBAL_CLK);
3321
3322         }
3323
3324         for (i = 0; i < card->hw.nchan; i++) {
3325                 pc300ch_t *chan = &card->chan[i];
3326                 pc300dev_t *d = &chan->d;
3327                 hdlc_device *hdlc;
3328                 struct net_device *dev;
3329
3330                 chan->card = card;
3331                 chan->channel = i;
3332                 chan->conf.phys_settings.clock_rate = 0;
3333                 chan->conf.phys_settings.clock_type = CLOCK_EXT;
3334                 chan->conf.proto_settings.encoding = ENCODING_NRZ;
3335                 chan->conf.proto_settings.parity = PARITY_CRC16_PR1_CCITT;
3336                 switch (card->hw.type) {
3337                         case PC300_TE:
3338                                 chan->conf.media = IF_IFACE_T1;
3339                                 chan->conf.lcode = PC300_LC_B8ZS;
3340                                 chan->conf.fr_mode = PC300_FR_ESF;
3341                                 chan->conf.lbo = PC300_LBO_0_DB;
3342                                 chan->conf.rx_sens = PC300_RX_SENS_SH;
3343                                 chan->conf.tslot_bitmap = 0xffffffffUL;
3344                                 break;
3345
3346                         case PC300_X21:
3347                                 chan->conf.media = IF_IFACE_X21;
3348                                 break;
3349
3350                         case PC300_RSV:
3351                         default:
3352                                 chan->conf.media = IF_IFACE_V35;
3353                                 break;
3354                 }
3355                 chan->conf.proto = IF_PROTO_PPP;
3356                 chan->tx_first_bd = 0;
3357                 chan->tx_next_bd = 0;
3358                 chan->rx_first_bd = 0;
3359                 chan->rx_last_bd = N_DMA_RX_BUF - 1;
3360                 chan->nfree_tx_bd = N_DMA_TX_BUF;
3361
3362                 d->chan = chan;
3363                 d->tx_skb = NULL;
3364                 d->trace_on = 0;
3365                 d->line_on = 0;
3366                 d->line_off = 0;
3367
3368                 dev = alloc_hdlcdev(NULL);
3369                 if (dev == NULL)
3370                         continue;
3371
3372                 hdlc = dev_to_hdlc(dev);
3373                 hdlc->xmit = cpc_queue_xmit;
3374                 hdlc->attach = cpc_attach;
3375                 d->dev = dev;
3376                 dev->mem_start = card->hw.ramphys;
3377                 dev->mem_end = card->hw.ramphys + card->hw.ramsize - 1;
3378                 dev->irq = card->hw.irq;
3379                 dev->init = NULL;
3380                 dev->tx_queue_len = PC300_TX_QUEUE_LEN;
3381                 dev->mtu = PC300_DEF_MTU;
3382
3383                 dev->open = cpc_open;
3384                 dev->stop = cpc_close;
3385                 dev->tx_timeout = cpc_tx_timeout;
3386                 dev->watchdog_timeo = PC300_TX_TIMEOUT;
3387                 dev->set_multicast_list = NULL;
3388                 dev->set_mac_address = NULL;
3389                 dev->change_mtu = cpc_change_mtu;
3390                 dev->do_ioctl = cpc_ioctl;
3391
3392                 if (register_hdlc_device(dev) == 0) {
3393                         dev->priv = d;  /* We need 'priv', hdlc doesn't */
3394                         printk("%s: Cyclades-PC300/", dev->name);
3395                         switch (card->hw.type) {
3396                                 case PC300_TE:
3397                                         if (card->hw.bus == PC300_PMC) {
3398                                                 printk("TE-M");
3399                                         } else {
3400                                                 printk("TE  ");
3401                                         }
3402                                         break;
3403
3404                                 case PC300_X21:
3405                                         printk("X21 ");
3406                                         break;
3407
3408                                 case PC300_RSV:
3409                                 default:
3410                                         printk("RSV ");
3411                                         break;
3412                         }
3413                         printk (" #%d, %dKB of RAM at 0x%08x, IRQ%d, channel %d.\n",
3414                                  board_nbr, card->hw.ramsize / 1024,
3415                                  card->hw.ramphys, card->hw.irq, i + 1);
3416                         devcount++;
3417                 } else {
3418                         printk ("Dev%d on card(0x%08x): unable to allocate i/f name.\n",
3419                                  i + 1, card->hw.ramphys);
3420                         free_netdev(dev);
3421                         continue;
3422                 }
3423         }
3424         spin_lock_init(&card->card_lock);
3425
3426         board_nbr++;
3427 }
3428
3429 static int __devinit
3430 cpc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3431 {
3432         static int first_time = 1;
3433         int err, eeprom_outdated = 0;
3434         ucshort device_id;
3435         pc300_t *card;
3436
3437         if (first_time) {
3438                 first_time = 0;
3439                 show_version();
3440 #ifdef CONFIG_PC300_MLPPP
3441                 cpc_tty_reset_var();
3442 #endif
3443         }
3444
3445         if ((err = pci_enable_device(pdev)) < 0)
3446                 return err;
3447
3448         card = kzalloc(sizeof(pc300_t), GFP_KERNEL);
3449         if (card == NULL) {
3450                 printk("PC300 found at RAM 0x%016llx, "
3451                        "but could not allocate card structure.\n",
3452                        (unsigned long long)pci_resource_start(pdev, 3));
3453                 err = -ENOMEM;
3454                 goto err_disable_dev;
3455         }
3456
3457         err = -ENODEV;
3458
3459         /* read PCI configuration area */
3460         device_id = ent->device;
3461         card->hw.irq = pdev->irq;
3462         card->hw.iophys = pci_resource_start(pdev, 1);
3463         card->hw.iosize = pci_resource_len(pdev, 1);
3464         card->hw.scaphys = pci_resource_start(pdev, 2);
3465         card->hw.scasize = pci_resource_len(pdev, 2);
3466         card->hw.ramphys = pci_resource_start(pdev, 3);
3467         card->hw.alloc_ramsize = pci_resource_len(pdev, 3);
3468         card->hw.falcphys = pci_resource_start(pdev, 4);
3469         card->hw.falcsize = pci_resource_len(pdev, 4);
3470         card->hw.plxphys = pci_resource_start(pdev, 5);
3471         card->hw.plxsize = pci_resource_len(pdev, 5);
3472
3473         switch (device_id) {
3474                 case PCI_DEVICE_ID_PC300_RX_1:
3475                 case PCI_DEVICE_ID_PC300_TE_1:
3476                 case PCI_DEVICE_ID_PC300_TE_M_1:
3477                         card->hw.nchan = 1;
3478                         break;
3479
3480                 case PCI_DEVICE_ID_PC300_RX_2:
3481                 case PCI_DEVICE_ID_PC300_TE_2:
3482                 case PCI_DEVICE_ID_PC300_TE_M_2:
3483                 default:
3484                         card->hw.nchan = PC300_MAXCHAN;
3485                         break;
3486         }
3487 #ifdef PC300_DEBUG_PCI
3488         printk("cpc (bus=0x0%x,pci_id=0x%x,", pdev->bus->number, pdev->devfn);
3489         printk("rev_id=%d) IRQ%d\n", pdev->revision, card->hw.irq);
3490         printk("cpc:found  ramaddr=0x%08lx plxaddr=0x%08lx "
3491                "ctladdr=0x%08lx falcaddr=0x%08lx\n",
3492                card->hw.ramphys, card->hw.plxphys, card->hw.scaphys,
3493                card->hw.falcphys);
3494 #endif
3495         /* Although we don't use this I/O region, we should
3496          * request it from the kernel anyway, to avoid problems
3497          * with other drivers accessing it. */
3498         if (!request_region(card->hw.iophys, card->hw.iosize, "PLX Registers")) {
3499                 /* In case we can't allocate it, warn user */
3500                 printk("WARNING: couldn't allocate I/O region for PC300 board "
3501                        "at 0x%08x!\n", card->hw.ramphys);
3502         }
3503
3504         if (card->hw.plxphys) {
3505                 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, card->hw.plxphys);
3506         } else {
3507                 eeprom_outdated = 1;
3508                 card->hw.plxphys = pci_resource_start(pdev, 0);
3509                 card->hw.plxsize = pci_resource_len(pdev, 0);
3510         }
3511
3512         if (!request_mem_region(card->hw.plxphys, card->hw.plxsize,
3513                                 "PLX Registers")) {
3514                 printk("PC300 found at RAM 0x%08x, "
3515                        "but could not allocate PLX mem region.\n",
3516                        card->hw.ramphys);
3517                 goto err_release_io;
3518         }
3519         if (!request_mem_region(card->hw.ramphys, card->hw.alloc_ramsize,
3520                                 "On-board RAM")) {
3521                 printk("PC300 found at RAM 0x%08x, "
3522                        "but could not allocate RAM mem region.\n",
3523                        card->hw.ramphys);
3524                 goto err_release_plx;
3525         }
3526         if (!request_mem_region(card->hw.scaphys, card->hw.scasize,
3527                                 "SCA-II Registers")) {
3528                 printk("PC300 found at RAM 0x%08x, "
3529                        "but could not allocate SCA mem region.\n",
3530                        card->hw.ramphys);
3531                 goto err_release_ram;
3532         }
3533
3534         card->hw.plxbase = ioremap(card->hw.plxphys, card->hw.plxsize);
3535         card->hw.rambase = ioremap(card->hw.ramphys, card->hw.alloc_ramsize);
3536         card->hw.scabase = ioremap(card->hw.scaphys, card->hw.scasize);
3537         switch (device_id) {
3538                 case PCI_DEVICE_ID_PC300_TE_1:
3539                 case PCI_DEVICE_ID_PC300_TE_2:
3540                 case PCI_DEVICE_ID_PC300_TE_M_1:
3541                 case PCI_DEVICE_ID_PC300_TE_M_2:
3542                         request_mem_region(card->hw.falcphys, card->hw.falcsize,
3543                                            "FALC Registers");
3544                         card->hw.falcbase = ioremap(card->hw.falcphys, card->hw.falcsize);
3545                         break;
3546
3547                 case PCI_DEVICE_ID_PC300_RX_1:
3548                 case PCI_DEVICE_ID_PC300_RX_2:
3549                 default:
3550                         card->hw.falcbase = NULL;
3551                         break;
3552         }
3553
3554 #ifdef PC300_DEBUG_PCI
3555         printk("cpc: relocate ramaddr=0x%08lx plxaddr=0x%08lx "
3556                "ctladdr=0x%08lx falcaddr=0x%08lx\n",
3557                card->hw.rambase, card->hw.plxbase, card->hw.scabase,
3558                card->hw.falcbase);
3559 #endif
3560
3561         /* Set PCI drv pointer to the card structure */
3562         pci_set_drvdata(pdev, card);
3563
3564         /* Set board type */
3565         switch (device_id) {
3566                 case PCI_DEVICE_ID_PC300_TE_1:
3567                 case PCI_DEVICE_ID_PC300_TE_2:
3568                 case PCI_DEVICE_ID_PC300_TE_M_1:
3569                 case PCI_DEVICE_ID_PC300_TE_M_2:
3570                         card->hw.type = PC300_TE;
3571
3572                         if ((device_id == PCI_DEVICE_ID_PC300_TE_M_1) ||
3573                             (device_id == PCI_DEVICE_ID_PC300_TE_M_2)) {
3574                                 card->hw.bus = PC300_PMC;
3575                                 /* Set PLX register offsets */
3576                                 card->hw.gpioc_reg = 0x54;
3577                                 card->hw.intctl_reg = 0x4c;
3578                         } else {
3579                                 card->hw.bus = PC300_PCI;
3580                                 /* Set PLX register offsets */
3581                                 card->hw.gpioc_reg = 0x50;
3582                                 card->hw.intctl_reg = 0x4c;
3583                         }
3584                         break;
3585
3586                 case PCI_DEVICE_ID_PC300_RX_1:
3587                 case PCI_DEVICE_ID_PC300_RX_2:
3588                 default:
3589                         card->hw.bus = PC300_PCI;
3590                         /* Set PLX register offsets */
3591                         card->hw.gpioc_reg = 0x50;
3592                         card->hw.intctl_reg = 0x4c;
3593
3594                         if ((cpc_readl(card->hw.plxbase + card->hw.gpioc_reg) & PC300_CTYPE_MASK)) {
3595                                 card->hw.type = PC300_X21;
3596                         } else {
3597                                 card->hw.type = PC300_RSV;
3598                         }
3599                         break;
3600         }
3601
3602         /* Allocate IRQ */
3603         if (request_irq(card->hw.irq, cpc_intr, IRQF_SHARED, "Cyclades-PC300", card)) {
3604                 printk ("PC300 found at RAM 0x%08x, but could not allocate IRQ%d.\n",
3605                          card->hw.ramphys, card->hw.irq);
3606                 goto err_io_unmap;
3607         }
3608
3609         cpc_init_card(card);
3610
3611         if (eeprom_outdated)
3612                 printk("WARNING: PC300 with outdated EEPROM.\n");
3613         return 0;
3614
3615 err_io_unmap:
3616         iounmap(card->hw.plxbase);
3617         iounmap(card->hw.scabase);
3618         iounmap(card->hw.rambase);
3619         if (card->hw.type == PC300_TE) {
3620                 iounmap(card->hw.falcbase);
3621                 release_mem_region(card->hw.falcphys, card->hw.falcsize);
3622         }
3623         release_mem_region(card->hw.scaphys, card->hw.scasize);
3624 err_release_ram:
3625         release_mem_region(card->hw.ramphys, card->hw.alloc_ramsize);
3626 err_release_plx:
3627         release_mem_region(card->hw.plxphys, card->hw.plxsize);
3628 err_release_io:
3629         release_region(card->hw.iophys, card->hw.iosize);
3630         kfree(card);
3631 err_disable_dev:
3632         pci_disable_device(pdev);
3633         return err;
3634 }
3635
3636 static void __devexit cpc_remove_one(struct pci_dev *pdev)
3637 {
3638         pc300_t *card = pci_get_drvdata(pdev);
3639
3640         if (card->hw.rambase) {
3641                 int i;
3642
3643                 /* Disable interrupts on the PCI bridge */
3644                 cpc_writew(card->hw.plxbase + card->hw.intctl_reg,
3645                            cpc_readw(card->hw.plxbase + card->hw.intctl_reg) & ~(0x0040));
3646
3647                 for (i = 0; i < card->hw.nchan; i++) {
3648                         unregister_hdlc_device(card->chan[i].d.dev);
3649                 }
3650                 iounmap(card->hw.plxbase);
3651                 iounmap(card->hw.scabase);
3652                 iounmap(card->hw.rambase);
3653                 release_mem_region(card->hw.plxphys, card->hw.plxsize);
3654                 release_mem_region(card->hw.ramphys, card->hw.alloc_ramsize);
3655                 release_mem_region(card->hw.scaphys, card->hw.scasize);
3656                 release_region(card->hw.iophys, card->hw.iosize);
3657                 if (card->hw.type == PC300_TE) {
3658                         iounmap(card->hw.falcbase);
3659                         release_mem_region(card->hw.falcphys, card->hw.falcsize);
3660                 }
3661                 for (i = 0; i < card->hw.nchan; i++)
3662                         if (card->chan[i].d.dev)
3663                                 free_netdev(card->chan[i].d.dev);
3664                 if (card->hw.irq)
3665                         free_irq(card->hw.irq, card);
3666                 kfree(card);
3667                 pci_disable_device(pdev);
3668         }
3669 }
3670
3671 static struct pci_driver cpc_driver = {
3672         .name           = "pc300",
3673         .id_table       = cpc_pci_dev_id,
3674         .probe          = cpc_init_one,
3675         .remove         = __devexit_p(cpc_remove_one),
3676 };
3677
3678 static int __init cpc_init(void)
3679 {
3680         return pci_register_driver(&cpc_driver);
3681 }
3682
3683 static void __exit cpc_cleanup_module(void)
3684 {
3685         pci_unregister_driver(&cpc_driver);
3686 }
3687
3688 module_init(cpc_init);
3689 module_exit(cpc_cleanup_module);
3690
3691 MODULE_DESCRIPTION("Cyclades-PC300 cards driver");
3692 MODULE_AUTHOR(  "Author: Ivan Passos <ivan@cyclades.com>\r\n"
3693                 "Maintainer: PC300 Maintainer <pc300@cyclades.com");
3694 MODULE_LICENSE("GPL");
3695