drivers/net: Remove casts of void *
[linux-2.6.git] / drivers / net / vxge / vxge-config.c
1 /******************************************************************************
2  * This software may be used and distributed according to the terms of
3  * the GNU General Public License (GPL), incorporated herein by reference.
4  * Drivers based on or derived from this code fall under the GPL and must
5  * retain the authorship, copyright and license notice.  This file is not
6  * a complete program and may only be used when the entire operating
7  * system is licensed under the GPL.
8  * See the file COPYING in this distribution for more information.
9  *
10  * vxge-config.c: Driver for Exar Corp's X3100 Series 10GbE PCIe I/O
11  *                Virtualized Server Adapter.
12  * Copyright(c) 2002-2010 Exar Corp.
13  ******************************************************************************/
14 #include <linux/vmalloc.h>
15 #include <linux/etherdevice.h>
16 #include <linux/pci.h>
17 #include <linux/pci_hotplug.h>
18 #include <linux/slab.h>
19
20 #include "vxge-traffic.h"
21 #include "vxge-config.h"
22 #include "vxge-main.h"
23
24 #define VXGE_HW_VPATH_STATS_PIO_READ(offset) {                          \
25         status = __vxge_hw_vpath_stats_access(vpath,                    \
26                                               VXGE_HW_STATS_OP_READ,    \
27                                               offset,                   \
28                                               &val64);                  \
29         if (status != VXGE_HW_OK)                                       \
30                 return status;                                          \
31 }
32
33 static void
34 vxge_hw_vpath_set_zero_rx_frm_len(struct vxge_hw_vpath_reg __iomem *vp_reg)
35 {
36         u64 val64;
37
38         val64 = readq(&vp_reg->rxmac_vcfg0);
39         val64 &= ~VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
40         writeq(val64, &vp_reg->rxmac_vcfg0);
41         val64 = readq(&vp_reg->rxmac_vcfg0);
42 }
43
44 /*
45  * vxge_hw_vpath_wait_receive_idle - Wait for Rx to become idle
46  */
47 int vxge_hw_vpath_wait_receive_idle(struct __vxge_hw_device *hldev, u32 vp_id)
48 {
49         struct vxge_hw_vpath_reg __iomem *vp_reg;
50         struct __vxge_hw_virtualpath *vpath;
51         u64 val64, rxd_count, rxd_spat;
52         int count = 0, total_count = 0;
53
54         vpath = &hldev->virtual_paths[vp_id];
55         vp_reg = vpath->vp_reg;
56
57         vxge_hw_vpath_set_zero_rx_frm_len(vp_reg);
58
59         /* Check that the ring controller for this vpath has enough free RxDs
60          * to send frames to the host.  This is done by reading the
61          * PRC_RXD_DOORBELL_VPn register and comparing the read value to the
62          * RXD_SPAT value for the vpath.
63          */
64         val64 = readq(&vp_reg->prc_cfg6);
65         rxd_spat = VXGE_HW_PRC_CFG6_GET_RXD_SPAT(val64) + 1;
66         /* Use a factor of 2 when comparing rxd_count against rxd_spat for some
67          * leg room.
68          */
69         rxd_spat *= 2;
70
71         do {
72                 mdelay(1);
73
74                 rxd_count = readq(&vp_reg->prc_rxd_doorbell);
75
76                 /* Check that the ring controller for this vpath does
77                  * not have any frame in its pipeline.
78                  */
79                 val64 = readq(&vp_reg->frm_in_progress_cnt);
80                 if ((rxd_count <= rxd_spat) || (val64 > 0))
81                         count = 0;
82                 else
83                         count++;
84                 total_count++;
85         } while ((count < VXGE_HW_MIN_SUCCESSIVE_IDLE_COUNT) &&
86                         (total_count < VXGE_HW_MAX_POLLING_COUNT));
87
88         if (total_count >= VXGE_HW_MAX_POLLING_COUNT)
89                 printk(KERN_ALERT "%s: Still Receiving traffic. Abort wait\n",
90                         __func__);
91
92         return total_count;
93 }
94
95 /* vxge_hw_device_wait_receive_idle - This function waits until all frames
96  * stored in the frame buffer for each vpath assigned to the given
97  * function (hldev) have been sent to the host.
98  */
99 void vxge_hw_device_wait_receive_idle(struct __vxge_hw_device *hldev)
100 {
101         int i, total_count = 0;
102
103         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
104                 if (!(hldev->vpaths_deployed & vxge_mBIT(i)))
105                         continue;
106
107                 total_count += vxge_hw_vpath_wait_receive_idle(hldev, i);
108                 if (total_count >= VXGE_HW_MAX_POLLING_COUNT)
109                         break;
110         }
111 }
112
113 /*
114  * __vxge_hw_device_register_poll
115  * Will poll certain register for specified amount of time.
116  * Will poll until masked bit is not cleared.
117  */
118 static enum vxge_hw_status
119 __vxge_hw_device_register_poll(void __iomem *reg, u64 mask, u32 max_millis)
120 {
121         u64 val64;
122         u32 i = 0;
123         enum vxge_hw_status ret = VXGE_HW_FAIL;
124
125         udelay(10);
126
127         do {
128                 val64 = readq(reg);
129                 if (!(val64 & mask))
130                         return VXGE_HW_OK;
131                 udelay(100);
132         } while (++i <= 9);
133
134         i = 0;
135         do {
136                 val64 = readq(reg);
137                 if (!(val64 & mask))
138                         return VXGE_HW_OK;
139                 mdelay(1);
140         } while (++i <= max_millis);
141
142         return ret;
143 }
144
145 static inline enum vxge_hw_status
146 __vxge_hw_pio_mem_write64(u64 val64, void __iomem *addr,
147                           u64 mask, u32 max_millis)
148 {
149         __vxge_hw_pio_mem_write32_lower((u32)vxge_bVALn(val64, 32, 32), addr);
150         wmb();
151         __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32), addr);
152         wmb();
153
154         return __vxge_hw_device_register_poll(addr, mask, max_millis);
155 }
156
157 static enum vxge_hw_status
158 vxge_hw_vpath_fw_api(struct __vxge_hw_virtualpath *vpath, u32 action,
159                      u32 fw_memo, u32 offset, u64 *data0, u64 *data1,
160                      u64 *steer_ctrl)
161 {
162         struct vxge_hw_vpath_reg __iomem *vp_reg = vpath->vp_reg;
163         enum vxge_hw_status status;
164         u64 val64;
165         u32 retry = 0, max_retry = 3;
166
167         spin_lock(&vpath->lock);
168         if (!vpath->vp_open) {
169                 spin_unlock(&vpath->lock);
170                 max_retry = 100;
171         }
172
173         writeq(*data0, &vp_reg->rts_access_steer_data0);
174         writeq(*data1, &vp_reg->rts_access_steer_data1);
175         wmb();
176
177         val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(action) |
178                 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(fw_memo) |
179                 VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(offset) |
180                 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE |
181                 *steer_ctrl;
182
183         status = __vxge_hw_pio_mem_write64(val64,
184                                            &vp_reg->rts_access_steer_ctrl,
185                                            VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
186                                            VXGE_HW_DEF_DEVICE_POLL_MILLIS);
187
188         /* The __vxge_hw_device_register_poll can udelay for a significant
189          * amount of time, blocking other process from the CPU.  If it delays
190          * for ~5secs, a NMI error can occur.  A way around this is to give up
191          * the processor via msleep, but this is not allowed is under lock.
192          * So, only allow it to sleep for ~4secs if open.  Otherwise, delay for
193          * 1sec and sleep for 10ms until the firmware operation has completed
194          * or timed-out.
195          */
196         while ((status != VXGE_HW_OK) && retry++ < max_retry) {
197                 if (!vpath->vp_open)
198                         msleep(20);
199                 status = __vxge_hw_device_register_poll(
200                                         &vp_reg->rts_access_steer_ctrl,
201                                         VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
202                                         VXGE_HW_DEF_DEVICE_POLL_MILLIS);
203         }
204
205         if (status != VXGE_HW_OK)
206                 goto out;
207
208         val64 = readq(&vp_reg->rts_access_steer_ctrl);
209         if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
210                 *data0 = readq(&vp_reg->rts_access_steer_data0);
211                 *data1 = readq(&vp_reg->rts_access_steer_data1);
212                 *steer_ctrl = val64;
213         } else
214                 status = VXGE_HW_FAIL;
215
216 out:
217         if (vpath->vp_open)
218                 spin_unlock(&vpath->lock);
219         return status;
220 }
221
222 enum vxge_hw_status
223 vxge_hw_upgrade_read_version(struct __vxge_hw_device *hldev, u32 *major,
224                              u32 *minor, u32 *build)
225 {
226         u64 data0 = 0, data1 = 0, steer_ctrl = 0;
227         struct __vxge_hw_virtualpath *vpath;
228         enum vxge_hw_status status;
229
230         vpath = &hldev->virtual_paths[hldev->first_vp_id];
231
232         status = vxge_hw_vpath_fw_api(vpath,
233                                       VXGE_HW_FW_UPGRADE_ACTION,
234                                       VXGE_HW_FW_UPGRADE_MEMO,
235                                       VXGE_HW_FW_UPGRADE_OFFSET_READ,
236                                       &data0, &data1, &steer_ctrl);
237         if (status != VXGE_HW_OK)
238                 return status;
239
240         *major = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(data0);
241         *minor = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(data0);
242         *build = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(data0);
243
244         return status;
245 }
246
247 enum vxge_hw_status vxge_hw_flash_fw(struct __vxge_hw_device *hldev)
248 {
249         u64 data0 = 0, data1 = 0, steer_ctrl = 0;
250         struct __vxge_hw_virtualpath *vpath;
251         enum vxge_hw_status status;
252         u32 ret;
253
254         vpath = &hldev->virtual_paths[hldev->first_vp_id];
255
256         status = vxge_hw_vpath_fw_api(vpath,
257                                       VXGE_HW_FW_UPGRADE_ACTION,
258                                       VXGE_HW_FW_UPGRADE_MEMO,
259                                       VXGE_HW_FW_UPGRADE_OFFSET_COMMIT,
260                                       &data0, &data1, &steer_ctrl);
261         if (status != VXGE_HW_OK) {
262                 vxge_debug_init(VXGE_ERR, "%s: FW upgrade failed", __func__);
263                 goto exit;
264         }
265
266         ret = VXGE_HW_RTS_ACCESS_STEER_CTRL_GET_ACTION(steer_ctrl) & 0x7F;
267         if (ret != 1) {
268                 vxge_debug_init(VXGE_ERR, "%s: FW commit failed with error %d",
269                                 __func__, ret);
270                 status = VXGE_HW_FAIL;
271         }
272
273 exit:
274         return status;
275 }
276
277 enum vxge_hw_status
278 vxge_update_fw_image(struct __vxge_hw_device *hldev, const u8 *fwdata, int size)
279 {
280         u64 data0 = 0, data1 = 0, steer_ctrl = 0;
281         struct __vxge_hw_virtualpath *vpath;
282         enum vxge_hw_status status;
283         int ret_code, sec_code;
284
285         vpath = &hldev->virtual_paths[hldev->first_vp_id];
286
287         /* send upgrade start command */
288         status = vxge_hw_vpath_fw_api(vpath,
289                                       VXGE_HW_FW_UPGRADE_ACTION,
290                                       VXGE_HW_FW_UPGRADE_MEMO,
291                                       VXGE_HW_FW_UPGRADE_OFFSET_START,
292                                       &data0, &data1, &steer_ctrl);
293         if (status != VXGE_HW_OK) {
294                 vxge_debug_init(VXGE_ERR, " %s: Upgrade start cmd failed",
295                                 __func__);
296                 return status;
297         }
298
299         /* Transfer fw image to adapter 16 bytes at a time */
300         for (; size > 0; size -= VXGE_HW_FW_UPGRADE_BLK_SIZE) {
301                 steer_ctrl = 0;
302
303                 /* The next 128bits of fwdata to be loaded onto the adapter */
304                 data0 = *((u64 *)fwdata);
305                 data1 = *((u64 *)fwdata + 1);
306
307                 status = vxge_hw_vpath_fw_api(vpath,
308                                               VXGE_HW_FW_UPGRADE_ACTION,
309                                               VXGE_HW_FW_UPGRADE_MEMO,
310                                               VXGE_HW_FW_UPGRADE_OFFSET_SEND,
311                                               &data0, &data1, &steer_ctrl);
312                 if (status != VXGE_HW_OK) {
313                         vxge_debug_init(VXGE_ERR, "%s: Upgrade send failed",
314                                         __func__);
315                         goto out;
316                 }
317
318                 ret_code = VXGE_HW_UPGRADE_GET_RET_ERR_CODE(data0);
319                 switch (ret_code) {
320                 case VXGE_HW_FW_UPGRADE_OK:
321                         /* All OK, send next 16 bytes. */
322                         break;
323                 case VXGE_FW_UPGRADE_BYTES2SKIP:
324                         /* skip bytes in the stream */
325                         fwdata += (data0 >> 8) & 0xFFFFFFFF;
326                         break;
327                 case VXGE_HW_FW_UPGRADE_DONE:
328                         goto out;
329                 case VXGE_HW_FW_UPGRADE_ERR:
330                         sec_code = VXGE_HW_UPGRADE_GET_SEC_ERR_CODE(data0);
331                         switch (sec_code) {
332                         case VXGE_HW_FW_UPGRADE_ERR_CORRUPT_DATA_1:
333                         case VXGE_HW_FW_UPGRADE_ERR_CORRUPT_DATA_7:
334                                 printk(KERN_ERR
335                                        "corrupted data from .ncf file\n");
336                                 break;
337                         case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_3:
338                         case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_4:
339                         case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_5:
340                         case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_6:
341                         case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_8:
342                                 printk(KERN_ERR "invalid .ncf file\n");
343                                 break;
344                         case VXGE_HW_FW_UPGRADE_ERR_BUFFER_OVERFLOW:
345                                 printk(KERN_ERR "buffer overflow\n");
346                                 break;
347                         case VXGE_HW_FW_UPGRADE_ERR_FAILED_TO_FLASH:
348                                 printk(KERN_ERR "failed to flash the image\n");
349                                 break;
350                         case VXGE_HW_FW_UPGRADE_ERR_GENERIC_ERROR_UNKNOWN:
351                                 printk(KERN_ERR
352                                        "generic error. Unknown error type\n");
353                                 break;
354                         default:
355                                 printk(KERN_ERR "Unknown error of type %d\n",
356                                        sec_code);
357                                 break;
358                         }
359                         status = VXGE_HW_FAIL;
360                         goto out;
361                 default:
362                         printk(KERN_ERR "Unknown FW error: %d\n", ret_code);
363                         status = VXGE_HW_FAIL;
364                         goto out;
365                 }
366                 /* point to next 16 bytes */
367                 fwdata += VXGE_HW_FW_UPGRADE_BLK_SIZE;
368         }
369 out:
370         return status;
371 }
372
373 enum vxge_hw_status
374 vxge_hw_vpath_eprom_img_ver_get(struct __vxge_hw_device *hldev,
375                                 struct eprom_image *img)
376 {
377         u64 data0 = 0, data1 = 0, steer_ctrl = 0;
378         struct __vxge_hw_virtualpath *vpath;
379         enum vxge_hw_status status;
380         int i;
381
382         vpath = &hldev->virtual_paths[hldev->first_vp_id];
383
384         for (i = 0; i < VXGE_HW_MAX_ROM_IMAGES; i++) {
385                 data0 = VXGE_HW_RTS_ACCESS_STEER_ROM_IMAGE_INDEX(i);
386                 data1 = steer_ctrl = 0;
387
388                 status = vxge_hw_vpath_fw_api(vpath,
389                         VXGE_HW_FW_API_GET_EPROM_REV,
390                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
391                         0, &data0, &data1, &steer_ctrl);
392                 if (status != VXGE_HW_OK)
393                         break;
394
395                 img[i].is_valid = VXGE_HW_GET_EPROM_IMAGE_VALID(data0);
396                 img[i].index = VXGE_HW_GET_EPROM_IMAGE_INDEX(data0);
397                 img[i].type = VXGE_HW_GET_EPROM_IMAGE_TYPE(data0);
398                 img[i].version = VXGE_HW_GET_EPROM_IMAGE_REV(data0);
399         }
400
401         return status;
402 }
403
404 /*
405  * __vxge_hw_channel_free - Free memory allocated for channel
406  * This function deallocates memory from the channel and various arrays
407  * in the channel
408  */
409 static void __vxge_hw_channel_free(struct __vxge_hw_channel *channel)
410 {
411         kfree(channel->work_arr);
412         kfree(channel->free_arr);
413         kfree(channel->reserve_arr);
414         kfree(channel->orig_arr);
415         kfree(channel);
416 }
417
418 /*
419  * __vxge_hw_channel_initialize - Initialize a channel
420  * This function initializes a channel by properly setting the
421  * various references
422  */
423 static enum vxge_hw_status
424 __vxge_hw_channel_initialize(struct __vxge_hw_channel *channel)
425 {
426         u32 i;
427         struct __vxge_hw_virtualpath *vpath;
428
429         vpath = channel->vph->vpath;
430
431         if ((channel->reserve_arr != NULL) && (channel->orig_arr != NULL)) {
432                 for (i = 0; i < channel->length; i++)
433                         channel->orig_arr[i] = channel->reserve_arr[i];
434         }
435
436         switch (channel->type) {
437         case VXGE_HW_CHANNEL_TYPE_FIFO:
438                 vpath->fifoh = (struct __vxge_hw_fifo *)channel;
439                 channel->stats = &((struct __vxge_hw_fifo *)
440                                 channel)->stats->common_stats;
441                 break;
442         case VXGE_HW_CHANNEL_TYPE_RING:
443                 vpath->ringh = (struct __vxge_hw_ring *)channel;
444                 channel->stats = &((struct __vxge_hw_ring *)
445                                 channel)->stats->common_stats;
446                 break;
447         default:
448                 break;
449         }
450
451         return VXGE_HW_OK;
452 }
453
454 /*
455  * __vxge_hw_channel_reset - Resets a channel
456  * This function resets a channel by properly setting the various references
457  */
458 static enum vxge_hw_status
459 __vxge_hw_channel_reset(struct __vxge_hw_channel *channel)
460 {
461         u32 i;
462
463         for (i = 0; i < channel->length; i++) {
464                 if (channel->reserve_arr != NULL)
465                         channel->reserve_arr[i] = channel->orig_arr[i];
466                 if (channel->free_arr != NULL)
467                         channel->free_arr[i] = NULL;
468                 if (channel->work_arr != NULL)
469                         channel->work_arr[i] = NULL;
470         }
471         channel->free_ptr = channel->length;
472         channel->reserve_ptr = channel->length;
473         channel->reserve_top = 0;
474         channel->post_index = 0;
475         channel->compl_index = 0;
476
477         return VXGE_HW_OK;
478 }
479
480 /*
481  * __vxge_hw_device_pci_e_init
482  * Initialize certain PCI/PCI-X configuration registers
483  * with recommended values. Save config space for future hw resets.
484  */
485 static void __vxge_hw_device_pci_e_init(struct __vxge_hw_device *hldev)
486 {
487         u16 cmd = 0;
488
489         /* Set the PErr Repconse bit and SERR in PCI command register. */
490         pci_read_config_word(hldev->pdev, PCI_COMMAND, &cmd);
491         cmd |= 0x140;
492         pci_write_config_word(hldev->pdev, PCI_COMMAND, cmd);
493
494         pci_save_state(hldev->pdev);
495 }
496
497 /* __vxge_hw_device_vpath_reset_in_prog_check - Check if vpath reset
498  * in progress
499  * This routine checks the vpath reset in progress register is turned zero
500  */
501 static enum vxge_hw_status
502 __vxge_hw_device_vpath_reset_in_prog_check(u64 __iomem *vpath_rst_in_prog)
503 {
504         enum vxge_hw_status status;
505         status = __vxge_hw_device_register_poll(vpath_rst_in_prog,
506                         VXGE_HW_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG(0x1ffff),
507                         VXGE_HW_DEF_DEVICE_POLL_MILLIS);
508         return status;
509 }
510
511 /*
512  * _hw_legacy_swapper_set - Set the swapper bits for the legacy secion.
513  * Set the swapper bits appropriately for the lagacy section.
514  */
515 static enum vxge_hw_status
516 __vxge_hw_legacy_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg)
517 {
518         u64 val64;
519         enum vxge_hw_status status = VXGE_HW_OK;
520
521         val64 = readq(&legacy_reg->toc_swapper_fb);
522
523         wmb();
524
525         switch (val64) {
526         case VXGE_HW_SWAPPER_INITIAL_VALUE:
527                 return status;
528
529         case VXGE_HW_SWAPPER_BYTE_SWAPPED_BIT_FLIPPED:
530                 writeq(VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE,
531                         &legacy_reg->pifm_rd_swap_en);
532                 writeq(VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE,
533                         &legacy_reg->pifm_rd_flip_en);
534                 writeq(VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE,
535                         &legacy_reg->pifm_wr_swap_en);
536                 writeq(VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE,
537                         &legacy_reg->pifm_wr_flip_en);
538                 break;
539
540         case VXGE_HW_SWAPPER_BYTE_SWAPPED:
541                 writeq(VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE,
542                         &legacy_reg->pifm_rd_swap_en);
543                 writeq(VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE,
544                         &legacy_reg->pifm_wr_swap_en);
545                 break;
546
547         case VXGE_HW_SWAPPER_BIT_FLIPPED:
548                 writeq(VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE,
549                         &legacy_reg->pifm_rd_flip_en);
550                 writeq(VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE,
551                         &legacy_reg->pifm_wr_flip_en);
552                 break;
553         }
554
555         wmb();
556
557         val64 = readq(&legacy_reg->toc_swapper_fb);
558
559         if (val64 != VXGE_HW_SWAPPER_INITIAL_VALUE)
560                 status = VXGE_HW_ERR_SWAPPER_CTRL;
561
562         return status;
563 }
564
565 /*
566  * __vxge_hw_device_toc_get
567  * This routine sets the swapper and reads the toc pointer and returns the
568  * memory mapped address of the toc
569  */
570 static struct vxge_hw_toc_reg __iomem *
571 __vxge_hw_device_toc_get(void __iomem *bar0)
572 {
573         u64 val64;
574         struct vxge_hw_toc_reg __iomem *toc = NULL;
575         enum vxge_hw_status status;
576
577         struct vxge_hw_legacy_reg __iomem *legacy_reg =
578                 (struct vxge_hw_legacy_reg __iomem *)bar0;
579
580         status = __vxge_hw_legacy_swapper_set(legacy_reg);
581         if (status != VXGE_HW_OK)
582                 goto exit;
583
584         val64 = readq(&legacy_reg->toc_first_pointer);
585         toc = bar0 + val64;
586 exit:
587         return toc;
588 }
589
590 /*
591  * __vxge_hw_device_reg_addr_get
592  * This routine sets the swapper and reads the toc pointer and initializes the
593  * register location pointers in the device object. It waits until the ric is
594  * completed initializing registers.
595  */
596 static enum vxge_hw_status
597 __vxge_hw_device_reg_addr_get(struct __vxge_hw_device *hldev)
598 {
599         u64 val64;
600         u32 i;
601         enum vxge_hw_status status = VXGE_HW_OK;
602
603         hldev->legacy_reg = hldev->bar0;
604
605         hldev->toc_reg = __vxge_hw_device_toc_get(hldev->bar0);
606         if (hldev->toc_reg  == NULL) {
607                 status = VXGE_HW_FAIL;
608                 goto exit;
609         }
610
611         val64 = readq(&hldev->toc_reg->toc_common_pointer);
612         hldev->common_reg = hldev->bar0 + val64;
613
614         val64 = readq(&hldev->toc_reg->toc_mrpcim_pointer);
615         hldev->mrpcim_reg = hldev->bar0 + val64;
616
617         for (i = 0; i < VXGE_HW_TITAN_SRPCIM_REG_SPACES; i++) {
618                 val64 = readq(&hldev->toc_reg->toc_srpcim_pointer[i]);
619                 hldev->srpcim_reg[i] = hldev->bar0 + val64;
620         }
621
622         for (i = 0; i < VXGE_HW_TITAN_VPMGMT_REG_SPACES; i++) {
623                 val64 = readq(&hldev->toc_reg->toc_vpmgmt_pointer[i]);
624                 hldev->vpmgmt_reg[i] = hldev->bar0 + val64;
625         }
626
627         for (i = 0; i < VXGE_HW_TITAN_VPATH_REG_SPACES; i++) {
628                 val64 = readq(&hldev->toc_reg->toc_vpath_pointer[i]);
629                 hldev->vpath_reg[i] = hldev->bar0 + val64;
630         }
631
632         val64 = readq(&hldev->toc_reg->toc_kdfc);
633
634         switch (VXGE_HW_TOC_GET_KDFC_INITIAL_BIR(val64)) {
635         case 0:
636                 hldev->kdfc = hldev->bar0 + VXGE_HW_TOC_GET_KDFC_INITIAL_OFFSET(val64) ;
637                 break;
638         default:
639                 break;
640         }
641
642         status = __vxge_hw_device_vpath_reset_in_prog_check(
643                         (u64 __iomem *)&hldev->common_reg->vpath_rst_in_prog);
644 exit:
645         return status;
646 }
647
648 /*
649  * __vxge_hw_device_access_rights_get: Get Access Rights of the driver
650  * This routine returns the Access Rights of the driver
651  */
652 static u32
653 __vxge_hw_device_access_rights_get(u32 host_type, u32 func_id)
654 {
655         u32 access_rights = VXGE_HW_DEVICE_ACCESS_RIGHT_VPATH;
656
657         switch (host_type) {
658         case VXGE_HW_NO_MR_NO_SR_NORMAL_FUNCTION:
659                 if (func_id == 0) {
660                         access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM |
661                                         VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
662                 }
663                 break;
664         case VXGE_HW_MR_NO_SR_VH0_BASE_FUNCTION:
665                 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM |
666                                 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
667                 break;
668         case VXGE_HW_NO_MR_SR_VH0_FUNCTION0:
669                 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM |
670                                 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
671                 break;
672         case VXGE_HW_NO_MR_SR_VH0_VIRTUAL_FUNCTION:
673         case VXGE_HW_SR_VH_VIRTUAL_FUNCTION:
674         case VXGE_HW_MR_SR_VH0_INVALID_CONFIG:
675                 break;
676         case VXGE_HW_SR_VH_FUNCTION0:
677         case VXGE_HW_VH_NORMAL_FUNCTION:
678                 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
679                 break;
680         }
681
682         return access_rights;
683 }
684 /*
685  * __vxge_hw_device_is_privilaged
686  * This routine checks if the device function is privilaged or not
687  */
688
689 enum vxge_hw_status
690 __vxge_hw_device_is_privilaged(u32 host_type, u32 func_id)
691 {
692         if (__vxge_hw_device_access_rights_get(host_type,
693                 func_id) &
694                 VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)
695                 return VXGE_HW_OK;
696         else
697                 return VXGE_HW_ERR_PRIVILAGED_OPEARATION;
698 }
699
700 /*
701  * __vxge_hw_vpath_func_id_get - Get the function id of the vpath.
702  * Returns the function number of the vpath.
703  */
704 static u32
705 __vxge_hw_vpath_func_id_get(struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg)
706 {
707         u64 val64;
708
709         val64 = readq(&vpmgmt_reg->vpath_to_func_map_cfg1);
710
711         return
712          (u32)VXGE_HW_VPATH_TO_FUNC_MAP_CFG1_GET_VPATH_TO_FUNC_MAP_CFG1(val64);
713 }
714
715 /*
716  * __vxge_hw_device_host_info_get
717  * This routine returns the host type assignments
718  */
719 static void __vxge_hw_device_host_info_get(struct __vxge_hw_device *hldev)
720 {
721         u64 val64;
722         u32 i;
723
724         val64 = readq(&hldev->common_reg->host_type_assignments);
725
726         hldev->host_type =
727            (u32)VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(val64);
728
729         hldev->vpath_assignments = readq(&hldev->common_reg->vpath_assignments);
730
731         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
732                 if (!(hldev->vpath_assignments & vxge_mBIT(i)))
733                         continue;
734
735                 hldev->func_id =
736                         __vxge_hw_vpath_func_id_get(hldev->vpmgmt_reg[i]);
737
738                 hldev->access_rights = __vxge_hw_device_access_rights_get(
739                         hldev->host_type, hldev->func_id);
740
741                 hldev->virtual_paths[i].vp_open = VXGE_HW_VP_NOT_OPEN;
742                 hldev->virtual_paths[i].vp_reg = hldev->vpath_reg[i];
743
744                 hldev->first_vp_id = i;
745                 break;
746         }
747 }
748
749 /*
750  * __vxge_hw_verify_pci_e_info - Validate the pci-e link parameters such as
751  * link width and signalling rate.
752  */
753 static enum vxge_hw_status
754 __vxge_hw_verify_pci_e_info(struct __vxge_hw_device *hldev)
755 {
756         int exp_cap;
757         u16 lnk;
758
759         /* Get the negotiated link width and speed from PCI config space */
760         exp_cap = pci_find_capability(hldev->pdev, PCI_CAP_ID_EXP);
761         pci_read_config_word(hldev->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
762
763         if ((lnk & PCI_EXP_LNKSTA_CLS) != 1)
764                 return VXGE_HW_ERR_INVALID_PCI_INFO;
765
766         switch ((lnk & PCI_EXP_LNKSTA_NLW) >> 4) {
767         case PCIE_LNK_WIDTH_RESRV:
768         case PCIE_LNK_X1:
769         case PCIE_LNK_X2:
770         case PCIE_LNK_X4:
771         case PCIE_LNK_X8:
772                 break;
773         default:
774                 return VXGE_HW_ERR_INVALID_PCI_INFO;
775         }
776
777         return VXGE_HW_OK;
778 }
779
780 /*
781  * __vxge_hw_device_initialize
782  * Initialize Titan-V hardware.
783  */
784 static enum vxge_hw_status
785 __vxge_hw_device_initialize(struct __vxge_hw_device *hldev)
786 {
787         enum vxge_hw_status status = VXGE_HW_OK;
788
789         if (VXGE_HW_OK == __vxge_hw_device_is_privilaged(hldev->host_type,
790                                 hldev->func_id)) {
791                 /* Validate the pci-e link width and speed */
792                 status = __vxge_hw_verify_pci_e_info(hldev);
793                 if (status != VXGE_HW_OK)
794                         goto exit;
795         }
796
797 exit:
798         return status;
799 }
800
801 /*
802  * __vxge_hw_vpath_fw_ver_get - Get the fw version
803  * Returns FW Version
804  */
805 static enum vxge_hw_status
806 __vxge_hw_vpath_fw_ver_get(struct __vxge_hw_virtualpath *vpath,
807                            struct vxge_hw_device_hw_info *hw_info)
808 {
809         struct vxge_hw_device_version *fw_version = &hw_info->fw_version;
810         struct vxge_hw_device_date *fw_date = &hw_info->fw_date;
811         struct vxge_hw_device_version *flash_version = &hw_info->flash_version;
812         struct vxge_hw_device_date *flash_date = &hw_info->flash_date;
813         u64 data0, data1 = 0, steer_ctrl = 0;
814         enum vxge_hw_status status;
815
816         status = vxge_hw_vpath_fw_api(vpath,
817                         VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY,
818                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
819                         0, &data0, &data1, &steer_ctrl);
820         if (status != VXGE_HW_OK)
821                 goto exit;
822
823         fw_date->day =
824             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_DAY(data0);
825         fw_date->month =
826             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MONTH(data0);
827         fw_date->year =
828             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_YEAR(data0);
829
830         snprintf(fw_date->date, VXGE_HW_FW_STRLEN, "%2.2d/%2.2d/%4.4d",
831                  fw_date->month, fw_date->day, fw_date->year);
832
833         fw_version->major =
834             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(data0);
835         fw_version->minor =
836             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(data0);
837         fw_version->build =
838             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(data0);
839
840         snprintf(fw_version->version, VXGE_HW_FW_STRLEN, "%d.%d.%d",
841                  fw_version->major, fw_version->minor, fw_version->build);
842
843         flash_date->day =
844             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_DAY(data1);
845         flash_date->month =
846             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MONTH(data1);
847         flash_date->year =
848             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_YEAR(data1);
849
850         snprintf(flash_date->date, VXGE_HW_FW_STRLEN, "%2.2d/%2.2d/%4.4d",
851                  flash_date->month, flash_date->day, flash_date->year);
852
853         flash_version->major =
854             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MAJOR(data1);
855         flash_version->minor =
856             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MINOR(data1);
857         flash_version->build =
858             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_BUILD(data1);
859
860         snprintf(flash_version->version, VXGE_HW_FW_STRLEN, "%d.%d.%d",
861                  flash_version->major, flash_version->minor,
862                  flash_version->build);
863
864 exit:
865         return status;
866 }
867
868 /*
869  * __vxge_hw_vpath_card_info_get - Get the serial numbers,
870  * part number and product description.
871  */
872 static enum vxge_hw_status
873 __vxge_hw_vpath_card_info_get(struct __vxge_hw_virtualpath *vpath,
874                               struct vxge_hw_device_hw_info *hw_info)
875 {
876         enum vxge_hw_status status;
877         u64 data0, data1 = 0, steer_ctrl = 0;
878         u8 *serial_number = hw_info->serial_number;
879         u8 *part_number = hw_info->part_number;
880         u8 *product_desc = hw_info->product_desc;
881         u32 i, j = 0;
882
883         data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_SERIAL_NUMBER;
884
885         status = vxge_hw_vpath_fw_api(vpath,
886                         VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY,
887                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
888                         0, &data0, &data1, &steer_ctrl);
889         if (status != VXGE_HW_OK)
890                 return status;
891
892         ((u64 *)serial_number)[0] = be64_to_cpu(data0);
893         ((u64 *)serial_number)[1] = be64_to_cpu(data1);
894
895         data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PART_NUMBER;
896         data1 = steer_ctrl = 0;
897
898         status = vxge_hw_vpath_fw_api(vpath,
899                         VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY,
900                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
901                         0, &data0, &data1, &steer_ctrl);
902         if (status != VXGE_HW_OK)
903                 return status;
904
905         ((u64 *)part_number)[0] = be64_to_cpu(data0);
906         ((u64 *)part_number)[1] = be64_to_cpu(data1);
907
908         for (i = VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_0;
909              i <= VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_3; i++) {
910                 data0 = i;
911                 data1 = steer_ctrl = 0;
912
913                 status = vxge_hw_vpath_fw_api(vpath,
914                         VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY,
915                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
916                         0, &data0, &data1, &steer_ctrl);
917                 if (status != VXGE_HW_OK)
918                         return status;
919
920                 ((u64 *)product_desc)[j++] = be64_to_cpu(data0);
921                 ((u64 *)product_desc)[j++] = be64_to_cpu(data1);
922         }
923
924         return status;
925 }
926
927 /*
928  * __vxge_hw_vpath_pci_func_mode_get - Get the pci mode
929  * Returns pci function mode
930  */
931 static enum vxge_hw_status
932 __vxge_hw_vpath_pci_func_mode_get(struct __vxge_hw_virtualpath *vpath,
933                                   struct vxge_hw_device_hw_info *hw_info)
934 {
935         u64 data0, data1 = 0, steer_ctrl = 0;
936         enum vxge_hw_status status;
937
938         data0 = 0;
939
940         status = vxge_hw_vpath_fw_api(vpath,
941                         VXGE_HW_FW_API_GET_FUNC_MODE,
942                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
943                         0, &data0, &data1, &steer_ctrl);
944         if (status != VXGE_HW_OK)
945                 return status;
946
947         hw_info->function_mode = VXGE_HW_GET_FUNC_MODE_VAL(data0);
948         return status;
949 }
950
951 /*
952  * __vxge_hw_vpath_addr_get - Get the hw address entry for this vpath
953  *               from MAC address table.
954  */
955 static enum vxge_hw_status
956 __vxge_hw_vpath_addr_get(struct __vxge_hw_virtualpath *vpath,
957                          u8 *macaddr, u8 *macaddr_mask)
958 {
959         u64 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY,
960             data0 = 0, data1 = 0, steer_ctrl = 0;
961         enum vxge_hw_status status;
962         int i;
963
964         do {
965                 status = vxge_hw_vpath_fw_api(vpath, action,
966                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA,
967                         0, &data0, &data1, &steer_ctrl);
968                 if (status != VXGE_HW_OK)
969                         goto exit;
970
971                 data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(data0);
972                 data1 = VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(
973                                                                         data1);
974
975                 for (i = ETH_ALEN; i > 0; i--) {
976                         macaddr[i - 1] = (u8) (data0 & 0xFF);
977                         data0 >>= 8;
978
979                         macaddr_mask[i - 1] = (u8) (data1 & 0xFF);
980                         data1 >>= 8;
981                 }
982
983                 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_NEXT_ENTRY;
984                 data0 = 0, data1 = 0, steer_ctrl = 0;
985
986         } while (!is_valid_ether_addr(macaddr));
987 exit:
988         return status;
989 }
990
991 /**
992  * vxge_hw_device_hw_info_get - Get the hw information
993  * Returns the vpath mask that has the bits set for each vpath allocated
994  * for the driver, FW version information, and the first mac address for
995  * each vpath
996  */
997 enum vxge_hw_status __devinit
998 vxge_hw_device_hw_info_get(void __iomem *bar0,
999                            struct vxge_hw_device_hw_info *hw_info)
1000 {
1001         u32 i;
1002         u64 val64;
1003         struct vxge_hw_toc_reg __iomem *toc;
1004         struct vxge_hw_mrpcim_reg __iomem *mrpcim_reg;
1005         struct vxge_hw_common_reg __iomem *common_reg;
1006         struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg;
1007         enum vxge_hw_status status;
1008         struct __vxge_hw_virtualpath vpath;
1009
1010         memset(hw_info, 0, sizeof(struct vxge_hw_device_hw_info));
1011
1012         toc = __vxge_hw_device_toc_get(bar0);
1013         if (toc == NULL) {
1014                 status = VXGE_HW_ERR_CRITICAL;
1015                 goto exit;
1016         }
1017
1018         val64 = readq(&toc->toc_common_pointer);
1019         common_reg = bar0 + val64;
1020
1021         status = __vxge_hw_device_vpath_reset_in_prog_check(
1022                 (u64 __iomem *)&common_reg->vpath_rst_in_prog);
1023         if (status != VXGE_HW_OK)
1024                 goto exit;
1025
1026         hw_info->vpath_mask = readq(&common_reg->vpath_assignments);
1027
1028         val64 = readq(&common_reg->host_type_assignments);
1029
1030         hw_info->host_type =
1031            (u32)VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(val64);
1032
1033         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1034                 if (!((hw_info->vpath_mask) & vxge_mBIT(i)))
1035                         continue;
1036
1037                 val64 = readq(&toc->toc_vpmgmt_pointer[i]);
1038
1039                 vpmgmt_reg = bar0 + val64;
1040
1041                 hw_info->func_id = __vxge_hw_vpath_func_id_get(vpmgmt_reg);
1042                 if (__vxge_hw_device_access_rights_get(hw_info->host_type,
1043                         hw_info->func_id) &
1044                         VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM) {
1045
1046                         val64 = readq(&toc->toc_mrpcim_pointer);
1047
1048                         mrpcim_reg = bar0 + val64;
1049
1050                         writeq(0, &mrpcim_reg->xgmac_gen_fw_memo_mask);
1051                         wmb();
1052                 }
1053
1054                 val64 = readq(&toc->toc_vpath_pointer[i]);
1055
1056                 spin_lock_init(&vpath.lock);
1057                 vpath.vp_reg = bar0 + val64;
1058                 vpath.vp_open = VXGE_HW_VP_NOT_OPEN;
1059
1060                 status = __vxge_hw_vpath_pci_func_mode_get(&vpath, hw_info);
1061                 if (status != VXGE_HW_OK)
1062                         goto exit;
1063
1064                 status = __vxge_hw_vpath_fw_ver_get(&vpath, hw_info);
1065                 if (status != VXGE_HW_OK)
1066                         goto exit;
1067
1068                 status = __vxge_hw_vpath_card_info_get(&vpath, hw_info);
1069                 if (status != VXGE_HW_OK)
1070                         goto exit;
1071
1072                 break;
1073         }
1074
1075         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1076                 if (!((hw_info->vpath_mask) & vxge_mBIT(i)))
1077                         continue;
1078
1079                 val64 = readq(&toc->toc_vpath_pointer[i]);
1080                 vpath.vp_reg = bar0 + val64;
1081                 vpath.vp_open = VXGE_HW_VP_NOT_OPEN;
1082
1083                 status =  __vxge_hw_vpath_addr_get(&vpath,
1084                                 hw_info->mac_addrs[i],
1085                                 hw_info->mac_addr_masks[i]);
1086                 if (status != VXGE_HW_OK)
1087                         goto exit;
1088         }
1089 exit:
1090         return status;
1091 }
1092
1093 /*
1094  * __vxge_hw_blockpool_destroy - Deallocates the block pool
1095  */
1096 static void __vxge_hw_blockpool_destroy(struct __vxge_hw_blockpool *blockpool)
1097 {
1098         struct __vxge_hw_device *hldev;
1099         struct list_head *p, *n;
1100         u16 ret;
1101
1102         if (blockpool == NULL) {
1103                 ret = 1;
1104                 goto exit;
1105         }
1106
1107         hldev = blockpool->hldev;
1108
1109         list_for_each_safe(p, n, &blockpool->free_block_list) {
1110                 pci_unmap_single(hldev->pdev,
1111                         ((struct __vxge_hw_blockpool_entry *)p)->dma_addr,
1112                         ((struct __vxge_hw_blockpool_entry *)p)->length,
1113                         PCI_DMA_BIDIRECTIONAL);
1114
1115                 vxge_os_dma_free(hldev->pdev,
1116                         ((struct __vxge_hw_blockpool_entry *)p)->memblock,
1117                         &((struct __vxge_hw_blockpool_entry *)p)->acc_handle);
1118
1119                 list_del(&((struct __vxge_hw_blockpool_entry *)p)->item);
1120                 kfree(p);
1121                 blockpool->pool_size--;
1122         }
1123
1124         list_for_each_safe(p, n, &blockpool->free_entry_list) {
1125                 list_del(&((struct __vxge_hw_blockpool_entry *)p)->item);
1126                 kfree((void *)p);
1127         }
1128         ret = 0;
1129 exit:
1130         return;
1131 }
1132
1133 /*
1134  * __vxge_hw_blockpool_create - Create block pool
1135  */
1136 static enum vxge_hw_status
1137 __vxge_hw_blockpool_create(struct __vxge_hw_device *hldev,
1138                            struct __vxge_hw_blockpool *blockpool,
1139                            u32 pool_size,
1140                            u32 pool_max)
1141 {
1142         u32 i;
1143         struct __vxge_hw_blockpool_entry *entry = NULL;
1144         void *memblock;
1145         dma_addr_t dma_addr;
1146         struct pci_dev *dma_handle;
1147         struct pci_dev *acc_handle;
1148         enum vxge_hw_status status = VXGE_HW_OK;
1149
1150         if (blockpool == NULL) {
1151                 status = VXGE_HW_FAIL;
1152                 goto blockpool_create_exit;
1153         }
1154
1155         blockpool->hldev = hldev;
1156         blockpool->block_size = VXGE_HW_BLOCK_SIZE;
1157         blockpool->pool_size = 0;
1158         blockpool->pool_max = pool_max;
1159         blockpool->req_out = 0;
1160
1161         INIT_LIST_HEAD(&blockpool->free_block_list);
1162         INIT_LIST_HEAD(&blockpool->free_entry_list);
1163
1164         for (i = 0; i < pool_size + pool_max; i++) {
1165                 entry = kzalloc(sizeof(struct __vxge_hw_blockpool_entry),
1166                                 GFP_KERNEL);
1167                 if (entry == NULL) {
1168                         __vxge_hw_blockpool_destroy(blockpool);
1169                         status = VXGE_HW_ERR_OUT_OF_MEMORY;
1170                         goto blockpool_create_exit;
1171                 }
1172                 list_add(&entry->item, &blockpool->free_entry_list);
1173         }
1174
1175         for (i = 0; i < pool_size; i++) {
1176                 memblock = vxge_os_dma_malloc(
1177                                 hldev->pdev,
1178                                 VXGE_HW_BLOCK_SIZE,
1179                                 &dma_handle,
1180                                 &acc_handle);
1181                 if (memblock == NULL) {
1182                         __vxge_hw_blockpool_destroy(blockpool);
1183                         status = VXGE_HW_ERR_OUT_OF_MEMORY;
1184                         goto blockpool_create_exit;
1185                 }
1186
1187                 dma_addr = pci_map_single(hldev->pdev, memblock,
1188                                 VXGE_HW_BLOCK_SIZE, PCI_DMA_BIDIRECTIONAL);
1189                 if (unlikely(pci_dma_mapping_error(hldev->pdev,
1190                                 dma_addr))) {
1191                         vxge_os_dma_free(hldev->pdev, memblock, &acc_handle);
1192                         __vxge_hw_blockpool_destroy(blockpool);
1193                         status = VXGE_HW_ERR_OUT_OF_MEMORY;
1194                         goto blockpool_create_exit;
1195                 }
1196
1197                 if (!list_empty(&blockpool->free_entry_list))
1198                         entry = (struct __vxge_hw_blockpool_entry *)
1199                                 list_first_entry(&blockpool->free_entry_list,
1200                                         struct __vxge_hw_blockpool_entry,
1201                                         item);
1202
1203                 if (entry == NULL)
1204                         entry =
1205                             kzalloc(sizeof(struct __vxge_hw_blockpool_entry),
1206                                         GFP_KERNEL);
1207                 if (entry != NULL) {
1208                         list_del(&entry->item);
1209                         entry->length = VXGE_HW_BLOCK_SIZE;
1210                         entry->memblock = memblock;
1211                         entry->dma_addr = dma_addr;
1212                         entry->acc_handle = acc_handle;
1213                         entry->dma_handle = dma_handle;
1214                         list_add(&entry->item,
1215                                           &blockpool->free_block_list);
1216                         blockpool->pool_size++;
1217                 } else {
1218                         __vxge_hw_blockpool_destroy(blockpool);
1219                         status = VXGE_HW_ERR_OUT_OF_MEMORY;
1220                         goto blockpool_create_exit;
1221                 }
1222         }
1223
1224 blockpool_create_exit:
1225         return status;
1226 }
1227
1228 /*
1229  * __vxge_hw_device_fifo_config_check - Check fifo configuration.
1230  * Check the fifo configuration
1231  */
1232 static enum vxge_hw_status
1233 __vxge_hw_device_fifo_config_check(struct vxge_hw_fifo_config *fifo_config)
1234 {
1235         if ((fifo_config->fifo_blocks < VXGE_HW_MIN_FIFO_BLOCKS) ||
1236             (fifo_config->fifo_blocks > VXGE_HW_MAX_FIFO_BLOCKS))
1237                 return VXGE_HW_BADCFG_FIFO_BLOCKS;
1238
1239         return VXGE_HW_OK;
1240 }
1241
1242 /*
1243  * __vxge_hw_device_vpath_config_check - Check vpath configuration.
1244  * Check the vpath configuration
1245  */
1246 static enum vxge_hw_status
1247 __vxge_hw_device_vpath_config_check(struct vxge_hw_vp_config *vp_config)
1248 {
1249         enum vxge_hw_status status;
1250
1251         if ((vp_config->min_bandwidth < VXGE_HW_VPATH_BANDWIDTH_MIN) ||
1252             (vp_config->min_bandwidth > VXGE_HW_VPATH_BANDWIDTH_MAX))
1253                 return VXGE_HW_BADCFG_VPATH_MIN_BANDWIDTH;
1254
1255         status = __vxge_hw_device_fifo_config_check(&vp_config->fifo);
1256         if (status != VXGE_HW_OK)
1257                 return status;
1258
1259         if ((vp_config->mtu != VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU) &&
1260                 ((vp_config->mtu < VXGE_HW_VPATH_MIN_INITIAL_MTU) ||
1261                 (vp_config->mtu > VXGE_HW_VPATH_MAX_INITIAL_MTU)))
1262                 return VXGE_HW_BADCFG_VPATH_MTU;
1263
1264         if ((vp_config->rpa_strip_vlan_tag !=
1265                 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT) &&
1266                 (vp_config->rpa_strip_vlan_tag !=
1267                 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_ENABLE) &&
1268                 (vp_config->rpa_strip_vlan_tag !=
1269                 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_DISABLE))
1270                 return VXGE_HW_BADCFG_VPATH_RPA_STRIP_VLAN_TAG;
1271
1272         return VXGE_HW_OK;
1273 }
1274
1275 /*
1276  * __vxge_hw_device_config_check - Check device configuration.
1277  * Check the device configuration
1278  */
1279 static enum vxge_hw_status
1280 __vxge_hw_device_config_check(struct vxge_hw_device_config *new_config)
1281 {
1282         u32 i;
1283         enum vxge_hw_status status;
1284
1285         if ((new_config->intr_mode != VXGE_HW_INTR_MODE_IRQLINE) &&
1286             (new_config->intr_mode != VXGE_HW_INTR_MODE_MSIX) &&
1287             (new_config->intr_mode != VXGE_HW_INTR_MODE_MSIX_ONE_SHOT) &&
1288             (new_config->intr_mode != VXGE_HW_INTR_MODE_DEF))
1289                 return VXGE_HW_BADCFG_INTR_MODE;
1290
1291         if ((new_config->rts_mac_en != VXGE_HW_RTS_MAC_DISABLE) &&
1292             (new_config->rts_mac_en != VXGE_HW_RTS_MAC_ENABLE))
1293                 return VXGE_HW_BADCFG_RTS_MAC_EN;
1294
1295         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1296                 status = __vxge_hw_device_vpath_config_check(
1297                                 &new_config->vp_config[i]);
1298                 if (status != VXGE_HW_OK)
1299                         return status;
1300         }
1301
1302         return VXGE_HW_OK;
1303 }
1304
1305 /*
1306  * vxge_hw_device_initialize - Initialize Titan device.
1307  * Initialize Titan device. Note that all the arguments of this public API
1308  * are 'IN', including @hldev. Driver cooperates with
1309  * OS to find new Titan device, locate its PCI and memory spaces.
1310  *
1311  * When done, the driver allocates sizeof(struct __vxge_hw_device) bytes for HW
1312  * to enable the latter to perform Titan hardware initialization.
1313  */
1314 enum vxge_hw_status __devinit
1315 vxge_hw_device_initialize(
1316         struct __vxge_hw_device **devh,
1317         struct vxge_hw_device_attr *attr,
1318         struct vxge_hw_device_config *device_config)
1319 {
1320         u32 i;
1321         u32 nblocks = 0;
1322         struct __vxge_hw_device *hldev = NULL;
1323         enum vxge_hw_status status = VXGE_HW_OK;
1324
1325         status = __vxge_hw_device_config_check(device_config);
1326         if (status != VXGE_HW_OK)
1327                 goto exit;
1328
1329         hldev = vzalloc(sizeof(struct __vxge_hw_device));
1330         if (hldev == NULL) {
1331                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1332                 goto exit;
1333         }
1334
1335         hldev->magic = VXGE_HW_DEVICE_MAGIC;
1336
1337         vxge_hw_device_debug_set(hldev, VXGE_ERR, VXGE_COMPONENT_ALL);
1338
1339         /* apply config */
1340         memcpy(&hldev->config, device_config,
1341                 sizeof(struct vxge_hw_device_config));
1342
1343         hldev->bar0 = attr->bar0;
1344         hldev->pdev = attr->pdev;
1345
1346         hldev->uld_callbacks.link_up = attr->uld_callbacks.link_up;
1347         hldev->uld_callbacks.link_down = attr->uld_callbacks.link_down;
1348         hldev->uld_callbacks.crit_err = attr->uld_callbacks.crit_err;
1349
1350         __vxge_hw_device_pci_e_init(hldev);
1351
1352         status = __vxge_hw_device_reg_addr_get(hldev);
1353         if (status != VXGE_HW_OK) {
1354                 vfree(hldev);
1355                 goto exit;
1356         }
1357
1358         __vxge_hw_device_host_info_get(hldev);
1359
1360         /* Incrementing for stats blocks */
1361         nblocks++;
1362
1363         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1364                 if (!(hldev->vpath_assignments & vxge_mBIT(i)))
1365                         continue;
1366
1367                 if (device_config->vp_config[i].ring.enable ==
1368                         VXGE_HW_RING_ENABLE)
1369                         nblocks += device_config->vp_config[i].ring.ring_blocks;
1370
1371                 if (device_config->vp_config[i].fifo.enable ==
1372                         VXGE_HW_FIFO_ENABLE)
1373                         nblocks += device_config->vp_config[i].fifo.fifo_blocks;
1374                 nblocks++;
1375         }
1376
1377         if (__vxge_hw_blockpool_create(hldev,
1378                 &hldev->block_pool,
1379                 device_config->dma_blockpool_initial + nblocks,
1380                 device_config->dma_blockpool_max + nblocks) != VXGE_HW_OK) {
1381
1382                 vxge_hw_device_terminate(hldev);
1383                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1384                 goto exit;
1385         }
1386
1387         status = __vxge_hw_device_initialize(hldev);
1388         if (status != VXGE_HW_OK) {
1389                 vxge_hw_device_terminate(hldev);
1390                 goto exit;
1391         }
1392
1393         *devh = hldev;
1394 exit:
1395         return status;
1396 }
1397
1398 /*
1399  * vxge_hw_device_terminate - Terminate Titan device.
1400  * Terminate HW device.
1401  */
1402 void
1403 vxge_hw_device_terminate(struct __vxge_hw_device *hldev)
1404 {
1405         vxge_assert(hldev->magic == VXGE_HW_DEVICE_MAGIC);
1406
1407         hldev->magic = VXGE_HW_DEVICE_DEAD;
1408         __vxge_hw_blockpool_destroy(&hldev->block_pool);
1409         vfree(hldev);
1410 }
1411
1412 /*
1413  * __vxge_hw_vpath_stats_access - Get the statistics from the given location
1414  *                           and offset and perform an operation
1415  */
1416 static enum vxge_hw_status
1417 __vxge_hw_vpath_stats_access(struct __vxge_hw_virtualpath *vpath,
1418                              u32 operation, u32 offset, u64 *stat)
1419 {
1420         u64 val64;
1421         enum vxge_hw_status status = VXGE_HW_OK;
1422         struct vxge_hw_vpath_reg __iomem *vp_reg;
1423
1424         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
1425                 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
1426                 goto vpath_stats_access_exit;
1427         }
1428
1429         vp_reg = vpath->vp_reg;
1430
1431         val64 =  VXGE_HW_XMAC_STATS_ACCESS_CMD_OP(operation) |
1432                  VXGE_HW_XMAC_STATS_ACCESS_CMD_STROBE |
1433                  VXGE_HW_XMAC_STATS_ACCESS_CMD_OFFSET_SEL(offset);
1434
1435         status = __vxge_hw_pio_mem_write64(val64,
1436                                 &vp_reg->xmac_stats_access_cmd,
1437                                 VXGE_HW_XMAC_STATS_ACCESS_CMD_STROBE,
1438                                 vpath->hldev->config.device_poll_millis);
1439         if ((status == VXGE_HW_OK) && (operation == VXGE_HW_STATS_OP_READ))
1440                 *stat = readq(&vp_reg->xmac_stats_access_data);
1441         else
1442                 *stat = 0;
1443
1444 vpath_stats_access_exit:
1445         return status;
1446 }
1447
1448 /*
1449  * __vxge_hw_vpath_xmac_tx_stats_get - Get the TX Statistics of a vpath
1450  */
1451 static enum vxge_hw_status
1452 __vxge_hw_vpath_xmac_tx_stats_get(struct __vxge_hw_virtualpath *vpath,
1453                         struct vxge_hw_xmac_vpath_tx_stats *vpath_tx_stats)
1454 {
1455         u64 *val64;
1456         int i;
1457         u32 offset = VXGE_HW_STATS_VPATH_TX_OFFSET;
1458         enum vxge_hw_status status = VXGE_HW_OK;
1459
1460         val64 = (u64 *)vpath_tx_stats;
1461
1462         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
1463                 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
1464                 goto exit;
1465         }
1466
1467         for (i = 0; i < sizeof(struct vxge_hw_xmac_vpath_tx_stats) / 8; i++) {
1468                 status = __vxge_hw_vpath_stats_access(vpath,
1469                                         VXGE_HW_STATS_OP_READ,
1470                                         offset, val64);
1471                 if (status != VXGE_HW_OK)
1472                         goto exit;
1473                 offset++;
1474                 val64++;
1475         }
1476 exit:
1477         return status;
1478 }
1479
1480 /*
1481  * __vxge_hw_vpath_xmac_rx_stats_get - Get the RX Statistics of a vpath
1482  */
1483 static enum vxge_hw_status
1484 __vxge_hw_vpath_xmac_rx_stats_get(struct __vxge_hw_virtualpath *vpath,
1485                         struct vxge_hw_xmac_vpath_rx_stats *vpath_rx_stats)
1486 {
1487         u64 *val64;
1488         enum vxge_hw_status status = VXGE_HW_OK;
1489         int i;
1490         u32 offset = VXGE_HW_STATS_VPATH_RX_OFFSET;
1491         val64 = (u64 *) vpath_rx_stats;
1492
1493         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
1494                 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
1495                 goto exit;
1496         }
1497         for (i = 0; i < sizeof(struct vxge_hw_xmac_vpath_rx_stats) / 8; i++) {
1498                 status = __vxge_hw_vpath_stats_access(vpath,
1499                                         VXGE_HW_STATS_OP_READ,
1500                                         offset >> 3, val64);
1501                 if (status != VXGE_HW_OK)
1502                         goto exit;
1503
1504                 offset += 8;
1505                 val64++;
1506         }
1507 exit:
1508         return status;
1509 }
1510
1511 /*
1512  * __vxge_hw_vpath_stats_get - Get the vpath hw statistics.
1513  */
1514 static enum vxge_hw_status
1515 __vxge_hw_vpath_stats_get(struct __vxge_hw_virtualpath *vpath,
1516                           struct vxge_hw_vpath_stats_hw_info *hw_stats)
1517 {
1518         u64 val64;
1519         enum vxge_hw_status status = VXGE_HW_OK;
1520         struct vxge_hw_vpath_reg __iomem *vp_reg;
1521
1522         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
1523                 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
1524                 goto exit;
1525         }
1526         vp_reg = vpath->vp_reg;
1527
1528         val64 = readq(&vp_reg->vpath_debug_stats0);
1529         hw_stats->ini_num_mwr_sent =
1530                 (u32)VXGE_HW_VPATH_DEBUG_STATS0_GET_INI_NUM_MWR_SENT(val64);
1531
1532         val64 = readq(&vp_reg->vpath_debug_stats1);
1533         hw_stats->ini_num_mrd_sent =
1534                 (u32)VXGE_HW_VPATH_DEBUG_STATS1_GET_INI_NUM_MRD_SENT(val64);
1535
1536         val64 = readq(&vp_reg->vpath_debug_stats2);
1537         hw_stats->ini_num_cpl_rcvd =
1538                 (u32)VXGE_HW_VPATH_DEBUG_STATS2_GET_INI_NUM_CPL_RCVD(val64);
1539
1540         val64 = readq(&vp_reg->vpath_debug_stats3);
1541         hw_stats->ini_num_mwr_byte_sent =
1542                 VXGE_HW_VPATH_DEBUG_STATS3_GET_INI_NUM_MWR_BYTE_SENT(val64);
1543
1544         val64 = readq(&vp_reg->vpath_debug_stats4);
1545         hw_stats->ini_num_cpl_byte_rcvd =
1546                 VXGE_HW_VPATH_DEBUG_STATS4_GET_INI_NUM_CPL_BYTE_RCVD(val64);
1547
1548         val64 = readq(&vp_reg->vpath_debug_stats5);
1549         hw_stats->wrcrdtarb_xoff =
1550                 (u32)VXGE_HW_VPATH_DEBUG_STATS5_GET_WRCRDTARB_XOFF(val64);
1551
1552         val64 = readq(&vp_reg->vpath_debug_stats6);
1553         hw_stats->rdcrdtarb_xoff =
1554                 (u32)VXGE_HW_VPATH_DEBUG_STATS6_GET_RDCRDTARB_XOFF(val64);
1555
1556         val64 = readq(&vp_reg->vpath_genstats_count01);
1557         hw_stats->vpath_genstats_count0 =
1558         (u32)VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT0(
1559                 val64);
1560
1561         val64 = readq(&vp_reg->vpath_genstats_count01);
1562         hw_stats->vpath_genstats_count1 =
1563         (u32)VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT1(
1564                 val64);
1565
1566         val64 = readq(&vp_reg->vpath_genstats_count23);
1567         hw_stats->vpath_genstats_count2 =
1568         (u32)VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT2(
1569                 val64);
1570
1571         val64 = readq(&vp_reg->vpath_genstats_count01);
1572         hw_stats->vpath_genstats_count3 =
1573         (u32)VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT3(
1574                 val64);
1575
1576         val64 = readq(&vp_reg->vpath_genstats_count4);
1577         hw_stats->vpath_genstats_count4 =
1578         (u32)VXGE_HW_VPATH_GENSTATS_COUNT4_GET_PPIF_VPATH_GENSTATS_COUNT4(
1579                 val64);
1580
1581         val64 = readq(&vp_reg->vpath_genstats_count5);
1582         hw_stats->vpath_genstats_count5 =
1583         (u32)VXGE_HW_VPATH_GENSTATS_COUNT5_GET_PPIF_VPATH_GENSTATS_COUNT5(
1584                 val64);
1585
1586         status = __vxge_hw_vpath_xmac_tx_stats_get(vpath, &hw_stats->tx_stats);
1587         if (status != VXGE_HW_OK)
1588                 goto exit;
1589
1590         status = __vxge_hw_vpath_xmac_rx_stats_get(vpath, &hw_stats->rx_stats);
1591         if (status != VXGE_HW_OK)
1592                 goto exit;
1593
1594         VXGE_HW_VPATH_STATS_PIO_READ(
1595                 VXGE_HW_STATS_VPATH_PROG_EVENT_VNUM0_OFFSET);
1596
1597         hw_stats->prog_event_vnum0 =
1598                         (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM0(val64);
1599
1600         hw_stats->prog_event_vnum1 =
1601                         (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM1(val64);
1602
1603         VXGE_HW_VPATH_STATS_PIO_READ(
1604                 VXGE_HW_STATS_VPATH_PROG_EVENT_VNUM2_OFFSET);
1605
1606         hw_stats->prog_event_vnum2 =
1607                         (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM2(val64);
1608
1609         hw_stats->prog_event_vnum3 =
1610                         (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM3(val64);
1611
1612         val64 = readq(&vp_reg->rx_multi_cast_stats);
1613         hw_stats->rx_multi_cast_frame_discard =
1614                 (u16)VXGE_HW_RX_MULTI_CAST_STATS_GET_FRAME_DISCARD(val64);
1615
1616         val64 = readq(&vp_reg->rx_frm_transferred);
1617         hw_stats->rx_frm_transferred =
1618                 (u32)VXGE_HW_RX_FRM_TRANSFERRED_GET_RX_FRM_TRANSFERRED(val64);
1619
1620         val64 = readq(&vp_reg->rxd_returned);
1621         hw_stats->rxd_returned =
1622                 (u16)VXGE_HW_RXD_RETURNED_GET_RXD_RETURNED(val64);
1623
1624         val64 = readq(&vp_reg->dbg_stats_rx_mpa);
1625         hw_stats->rx_mpa_len_fail_frms =
1626                 (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_LEN_FAIL_FRMS(val64);
1627         hw_stats->rx_mpa_mrk_fail_frms =
1628                 (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_MRK_FAIL_FRMS(val64);
1629         hw_stats->rx_mpa_crc_fail_frms =
1630                 (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_CRC_FAIL_FRMS(val64);
1631
1632         val64 = readq(&vp_reg->dbg_stats_rx_fau);
1633         hw_stats->rx_permitted_frms =
1634                 (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_PERMITTED_FRMS(val64);
1635         hw_stats->rx_vp_reset_discarded_frms =
1636         (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(val64);
1637         hw_stats->rx_wol_frms =
1638                 (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_WOL_FRMS(val64);
1639
1640         val64 = readq(&vp_reg->tx_vp_reset_discarded_frms);
1641         hw_stats->tx_vp_reset_discarded_frms =
1642         (u16)VXGE_HW_TX_VP_RESET_DISCARDED_FRMS_GET_TX_VP_RESET_DISCARDED_FRMS(
1643                 val64);
1644 exit:
1645         return status;
1646 }
1647
1648 /*
1649  * vxge_hw_device_stats_get - Get the device hw statistics.
1650  * Returns the vpath h/w stats for the device.
1651  */
1652 enum vxge_hw_status
1653 vxge_hw_device_stats_get(struct __vxge_hw_device *hldev,
1654                         struct vxge_hw_device_stats_hw_info *hw_stats)
1655 {
1656         u32 i;
1657         enum vxge_hw_status status = VXGE_HW_OK;
1658
1659         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1660                 if (!(hldev->vpaths_deployed & vxge_mBIT(i)) ||
1661                         (hldev->virtual_paths[i].vp_open ==
1662                                 VXGE_HW_VP_NOT_OPEN))
1663                         continue;
1664
1665                 memcpy(hldev->virtual_paths[i].hw_stats_sav,
1666                                 hldev->virtual_paths[i].hw_stats,
1667                                 sizeof(struct vxge_hw_vpath_stats_hw_info));
1668
1669                 status = __vxge_hw_vpath_stats_get(
1670                         &hldev->virtual_paths[i],
1671                         hldev->virtual_paths[i].hw_stats);
1672         }
1673
1674         memcpy(hw_stats, &hldev->stats.hw_dev_info_stats,
1675                         sizeof(struct vxge_hw_device_stats_hw_info));
1676
1677         return status;
1678 }
1679
1680 /*
1681  * vxge_hw_driver_stats_get - Get the device sw statistics.
1682  * Returns the vpath s/w stats for the device.
1683  */
1684 enum vxge_hw_status vxge_hw_driver_stats_get(
1685                         struct __vxge_hw_device *hldev,
1686                         struct vxge_hw_device_stats_sw_info *sw_stats)
1687 {
1688         enum vxge_hw_status status = VXGE_HW_OK;
1689
1690         memcpy(sw_stats, &hldev->stats.sw_dev_info_stats,
1691                 sizeof(struct vxge_hw_device_stats_sw_info));
1692
1693         return status;
1694 }
1695
1696 /*
1697  * vxge_hw_mrpcim_stats_access - Access the statistics from the given location
1698  *                           and offset and perform an operation
1699  * Get the statistics from the given location and offset.
1700  */
1701 enum vxge_hw_status
1702 vxge_hw_mrpcim_stats_access(struct __vxge_hw_device *hldev,
1703                             u32 operation, u32 location, u32 offset, u64 *stat)
1704 {
1705         u64 val64;
1706         enum vxge_hw_status status = VXGE_HW_OK;
1707
1708         status = __vxge_hw_device_is_privilaged(hldev->host_type,
1709                         hldev->func_id);
1710         if (status != VXGE_HW_OK)
1711                 goto exit;
1712
1713         val64 = VXGE_HW_XMAC_STATS_SYS_CMD_OP(operation) |
1714                 VXGE_HW_XMAC_STATS_SYS_CMD_STROBE |
1715                 VXGE_HW_XMAC_STATS_SYS_CMD_LOC_SEL(location) |
1716                 VXGE_HW_XMAC_STATS_SYS_CMD_OFFSET_SEL(offset);
1717
1718         status = __vxge_hw_pio_mem_write64(val64,
1719                                 &hldev->mrpcim_reg->xmac_stats_sys_cmd,
1720                                 VXGE_HW_XMAC_STATS_SYS_CMD_STROBE,
1721                                 hldev->config.device_poll_millis);
1722
1723         if ((status == VXGE_HW_OK) && (operation == VXGE_HW_STATS_OP_READ))
1724                 *stat = readq(&hldev->mrpcim_reg->xmac_stats_sys_data);
1725         else
1726                 *stat = 0;
1727 exit:
1728         return status;
1729 }
1730
1731 /*
1732  * vxge_hw_device_xmac_aggr_stats_get - Get the Statistics on aggregate port
1733  * Get the Statistics on aggregate port
1734  */
1735 static enum vxge_hw_status
1736 vxge_hw_device_xmac_aggr_stats_get(struct __vxge_hw_device *hldev, u32 port,
1737                                    struct vxge_hw_xmac_aggr_stats *aggr_stats)
1738 {
1739         u64 *val64;
1740         int i;
1741         u32 offset = VXGE_HW_STATS_AGGRn_OFFSET;
1742         enum vxge_hw_status status = VXGE_HW_OK;
1743
1744         val64 = (u64 *)aggr_stats;
1745
1746         status = __vxge_hw_device_is_privilaged(hldev->host_type,
1747                         hldev->func_id);
1748         if (status != VXGE_HW_OK)
1749                 goto exit;
1750
1751         for (i = 0; i < sizeof(struct vxge_hw_xmac_aggr_stats) / 8; i++) {
1752                 status = vxge_hw_mrpcim_stats_access(hldev,
1753                                         VXGE_HW_STATS_OP_READ,
1754                                         VXGE_HW_STATS_LOC_AGGR,
1755                                         ((offset + (104 * port)) >> 3), val64);
1756                 if (status != VXGE_HW_OK)
1757                         goto exit;
1758
1759                 offset += 8;
1760                 val64++;
1761         }
1762 exit:
1763         return status;
1764 }
1765
1766 /*
1767  * vxge_hw_device_xmac_port_stats_get - Get the Statistics on a port
1768  * Get the Statistics on port
1769  */
1770 static enum vxge_hw_status
1771 vxge_hw_device_xmac_port_stats_get(struct __vxge_hw_device *hldev, u32 port,
1772                                    struct vxge_hw_xmac_port_stats *port_stats)
1773 {
1774         u64 *val64;
1775         enum vxge_hw_status status = VXGE_HW_OK;
1776         int i;
1777         u32 offset = 0x0;
1778         val64 = (u64 *) port_stats;
1779
1780         status = __vxge_hw_device_is_privilaged(hldev->host_type,
1781                         hldev->func_id);
1782         if (status != VXGE_HW_OK)
1783                 goto exit;
1784
1785         for (i = 0; i < sizeof(struct vxge_hw_xmac_port_stats) / 8; i++) {
1786                 status = vxge_hw_mrpcim_stats_access(hldev,
1787                                         VXGE_HW_STATS_OP_READ,
1788                                         VXGE_HW_STATS_LOC_AGGR,
1789                                         ((offset + (608 * port)) >> 3), val64);
1790                 if (status != VXGE_HW_OK)
1791                         goto exit;
1792
1793                 offset += 8;
1794                 val64++;
1795         }
1796
1797 exit:
1798         return status;
1799 }
1800
1801 /*
1802  * vxge_hw_device_xmac_stats_get - Get the XMAC Statistics
1803  * Get the XMAC Statistics
1804  */
1805 enum vxge_hw_status
1806 vxge_hw_device_xmac_stats_get(struct __vxge_hw_device *hldev,
1807                               struct vxge_hw_xmac_stats *xmac_stats)
1808 {
1809         enum vxge_hw_status status = VXGE_HW_OK;
1810         u32 i;
1811
1812         status = vxge_hw_device_xmac_aggr_stats_get(hldev,
1813                                         0, &xmac_stats->aggr_stats[0]);
1814         if (status != VXGE_HW_OK)
1815                 goto exit;
1816
1817         status = vxge_hw_device_xmac_aggr_stats_get(hldev,
1818                                 1, &xmac_stats->aggr_stats[1]);
1819         if (status != VXGE_HW_OK)
1820                 goto exit;
1821
1822         for (i = 0; i <= VXGE_HW_MAC_MAX_MAC_PORT_ID; i++) {
1823
1824                 status = vxge_hw_device_xmac_port_stats_get(hldev,
1825                                         i, &xmac_stats->port_stats[i]);
1826                 if (status != VXGE_HW_OK)
1827                         goto exit;
1828         }
1829
1830         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1831
1832                 if (!(hldev->vpaths_deployed & vxge_mBIT(i)))
1833                         continue;
1834
1835                 status = __vxge_hw_vpath_xmac_tx_stats_get(
1836                                         &hldev->virtual_paths[i],
1837                                         &xmac_stats->vpath_tx_stats[i]);
1838                 if (status != VXGE_HW_OK)
1839                         goto exit;
1840
1841                 status = __vxge_hw_vpath_xmac_rx_stats_get(
1842                                         &hldev->virtual_paths[i],
1843                                         &xmac_stats->vpath_rx_stats[i]);
1844                 if (status != VXGE_HW_OK)
1845                         goto exit;
1846         }
1847 exit:
1848         return status;
1849 }
1850
1851 /*
1852  * vxge_hw_device_debug_set - Set the debug module, level and timestamp
1853  * This routine is used to dynamically change the debug output
1854  */
1855 void vxge_hw_device_debug_set(struct __vxge_hw_device *hldev,
1856                               enum vxge_debug_level level, u32 mask)
1857 {
1858         if (hldev == NULL)
1859                 return;
1860
1861 #if defined(VXGE_DEBUG_TRACE_MASK) || \
1862         defined(VXGE_DEBUG_ERR_MASK)
1863         hldev->debug_module_mask = mask;
1864         hldev->debug_level = level;
1865 #endif
1866
1867 #if defined(VXGE_DEBUG_ERR_MASK)
1868         hldev->level_err = level & VXGE_ERR;
1869 #endif
1870
1871 #if defined(VXGE_DEBUG_TRACE_MASK)
1872         hldev->level_trace = level & VXGE_TRACE;
1873 #endif
1874 }
1875
1876 /*
1877  * vxge_hw_device_error_level_get - Get the error level
1878  * This routine returns the current error level set
1879  */
1880 u32 vxge_hw_device_error_level_get(struct __vxge_hw_device *hldev)
1881 {
1882 #if defined(VXGE_DEBUG_ERR_MASK)
1883         if (hldev == NULL)
1884                 return VXGE_ERR;
1885         else
1886                 return hldev->level_err;
1887 #else
1888         return 0;
1889 #endif
1890 }
1891
1892 /*
1893  * vxge_hw_device_trace_level_get - Get the trace level
1894  * This routine returns the current trace level set
1895  */
1896 u32 vxge_hw_device_trace_level_get(struct __vxge_hw_device *hldev)
1897 {
1898 #if defined(VXGE_DEBUG_TRACE_MASK)
1899         if (hldev == NULL)
1900                 return VXGE_TRACE;
1901         else
1902                 return hldev->level_trace;
1903 #else
1904         return 0;
1905 #endif
1906 }
1907
1908 /*
1909  * vxge_hw_getpause_data -Pause frame frame generation and reception.
1910  * Returns the Pause frame generation and reception capability of the NIC.
1911  */
1912 enum vxge_hw_status vxge_hw_device_getpause_data(struct __vxge_hw_device *hldev,
1913                                                  u32 port, u32 *tx, u32 *rx)
1914 {
1915         u64 val64;
1916         enum vxge_hw_status status = VXGE_HW_OK;
1917
1918         if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
1919                 status = VXGE_HW_ERR_INVALID_DEVICE;
1920                 goto exit;
1921         }
1922
1923         if (port > VXGE_HW_MAC_MAX_MAC_PORT_ID) {
1924                 status = VXGE_HW_ERR_INVALID_PORT;
1925                 goto exit;
1926         }
1927
1928         if (!(hldev->access_rights & VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) {
1929                 status = VXGE_HW_ERR_PRIVILAGED_OPEARATION;
1930                 goto exit;
1931         }
1932
1933         val64 = readq(&hldev->mrpcim_reg->rxmac_pause_cfg_port[port]);
1934         if (val64 & VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN)
1935                 *tx = 1;
1936         if (val64 & VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN)
1937                 *rx = 1;
1938 exit:
1939         return status;
1940 }
1941
1942 /*
1943  * vxge_hw_device_setpause_data -  set/reset pause frame generation.
1944  * It can be used to set or reset Pause frame generation or reception
1945  * support of the NIC.
1946  */
1947 enum vxge_hw_status vxge_hw_device_setpause_data(struct __vxge_hw_device *hldev,
1948                                                  u32 port, u32 tx, u32 rx)
1949 {
1950         u64 val64;
1951         enum vxge_hw_status status = VXGE_HW_OK;
1952
1953         if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
1954                 status = VXGE_HW_ERR_INVALID_DEVICE;
1955                 goto exit;
1956         }
1957
1958         if (port > VXGE_HW_MAC_MAX_MAC_PORT_ID) {
1959                 status = VXGE_HW_ERR_INVALID_PORT;
1960                 goto exit;
1961         }
1962
1963         status = __vxge_hw_device_is_privilaged(hldev->host_type,
1964                         hldev->func_id);
1965         if (status != VXGE_HW_OK)
1966                 goto exit;
1967
1968         val64 = readq(&hldev->mrpcim_reg->rxmac_pause_cfg_port[port]);
1969         if (tx)
1970                 val64 |= VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN;
1971         else
1972                 val64 &= ~VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN;
1973         if (rx)
1974                 val64 |= VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN;
1975         else
1976                 val64 &= ~VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN;
1977
1978         writeq(val64, &hldev->mrpcim_reg->rxmac_pause_cfg_port[port]);
1979 exit:
1980         return status;
1981 }
1982
1983 u16 vxge_hw_device_link_width_get(struct __vxge_hw_device *hldev)
1984 {
1985         int link_width, exp_cap;
1986         u16 lnk;
1987
1988         exp_cap = pci_find_capability(hldev->pdev, PCI_CAP_ID_EXP);
1989         pci_read_config_word(hldev->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
1990         link_width = (lnk & VXGE_HW_PCI_EXP_LNKCAP_LNK_WIDTH) >> 4;
1991         return link_width;
1992 }
1993
1994 /*
1995  * __vxge_hw_ring_block_memblock_idx - Return the memblock index
1996  * This function returns the index of memory block
1997  */
1998 static inline u32
1999 __vxge_hw_ring_block_memblock_idx(u8 *block)
2000 {
2001         return (u32)*((u64 *)(block + VXGE_HW_RING_MEMBLOCK_IDX_OFFSET));
2002 }
2003
2004 /*
2005  * __vxge_hw_ring_block_memblock_idx_set - Sets the memblock index
2006  * This function sets index to a memory block
2007  */
2008 static inline void
2009 __vxge_hw_ring_block_memblock_idx_set(u8 *block, u32 memblock_idx)
2010 {
2011         *((u64 *)(block + VXGE_HW_RING_MEMBLOCK_IDX_OFFSET)) = memblock_idx;
2012 }
2013
2014 /*
2015  * __vxge_hw_ring_block_next_pointer_set - Sets the next block pointer
2016  * in RxD block
2017  * Sets the next block pointer in RxD block
2018  */
2019 static inline void
2020 __vxge_hw_ring_block_next_pointer_set(u8 *block, dma_addr_t dma_next)
2021 {
2022         *((u64 *)(block + VXGE_HW_RING_NEXT_BLOCK_POINTER_OFFSET)) = dma_next;
2023 }
2024
2025 /*
2026  * __vxge_hw_ring_first_block_address_get - Returns the dma address of the
2027  *             first block
2028  * Returns the dma address of the first RxD block
2029  */
2030 static u64 __vxge_hw_ring_first_block_address_get(struct __vxge_hw_ring *ring)
2031 {
2032         struct vxge_hw_mempool_dma *dma_object;
2033
2034         dma_object = ring->mempool->memblocks_dma_arr;
2035         vxge_assert(dma_object != NULL);
2036
2037         return dma_object->addr;
2038 }
2039
2040 /*
2041  * __vxge_hw_ring_item_dma_addr - Return the dma address of an item
2042  * This function returns the dma address of a given item
2043  */
2044 static dma_addr_t __vxge_hw_ring_item_dma_addr(struct vxge_hw_mempool *mempoolh,
2045                                                void *item)
2046 {
2047         u32 memblock_idx;
2048         void *memblock;
2049         struct vxge_hw_mempool_dma *memblock_dma_object;
2050         ptrdiff_t dma_item_offset;
2051
2052         /* get owner memblock index */
2053         memblock_idx = __vxge_hw_ring_block_memblock_idx(item);
2054
2055         /* get owner memblock by memblock index */
2056         memblock = mempoolh->memblocks_arr[memblock_idx];
2057
2058         /* get memblock DMA object by memblock index */
2059         memblock_dma_object = mempoolh->memblocks_dma_arr + memblock_idx;
2060
2061         /* calculate offset in the memblock of this item */
2062         dma_item_offset = (u8 *)item - (u8 *)memblock;
2063
2064         return memblock_dma_object->addr + dma_item_offset;
2065 }
2066
2067 /*
2068  * __vxge_hw_ring_rxdblock_link - Link the RxD blocks
2069  * This function returns the dma address of a given item
2070  */
2071 static void __vxge_hw_ring_rxdblock_link(struct vxge_hw_mempool *mempoolh,
2072                                          struct __vxge_hw_ring *ring, u32 from,
2073                                          u32 to)
2074 {
2075         u8 *to_item , *from_item;
2076         dma_addr_t to_dma;
2077
2078         /* get "from" RxD block */
2079         from_item = mempoolh->items_arr[from];
2080         vxge_assert(from_item);
2081
2082         /* get "to" RxD block */
2083         to_item = mempoolh->items_arr[to];
2084         vxge_assert(to_item);
2085
2086         /* return address of the beginning of previous RxD block */
2087         to_dma = __vxge_hw_ring_item_dma_addr(mempoolh, to_item);
2088
2089         /* set next pointer for this RxD block to point on
2090          * previous item's DMA start address */
2091         __vxge_hw_ring_block_next_pointer_set(from_item, to_dma);
2092 }
2093
2094 /*
2095  * __vxge_hw_ring_mempool_item_alloc - Allocate List blocks for RxD
2096  * block callback
2097  * This function is callback passed to __vxge_hw_mempool_create to create memory
2098  * pool for RxD block
2099  */
2100 static void
2101 __vxge_hw_ring_mempool_item_alloc(struct vxge_hw_mempool *mempoolh,
2102                                   u32 memblock_index,
2103                                   struct vxge_hw_mempool_dma *dma_object,
2104                                   u32 index, u32 is_last)
2105 {
2106         u32 i;
2107         void *item = mempoolh->items_arr[index];
2108         struct __vxge_hw_ring *ring =
2109                 (struct __vxge_hw_ring *)mempoolh->userdata;
2110
2111         /* format rxds array */
2112         for (i = 0; i < ring->rxds_per_block; i++) {
2113                 void *rxdblock_priv;
2114                 void *uld_priv;
2115                 struct vxge_hw_ring_rxd_1 *rxdp;
2116
2117                 u32 reserve_index = ring->channel.reserve_ptr -
2118                                 (index * ring->rxds_per_block + i + 1);
2119                 u32 memblock_item_idx;
2120
2121                 ring->channel.reserve_arr[reserve_index] = ((u8 *)item) +
2122                                                 i * ring->rxd_size;
2123
2124                 /* Note: memblock_item_idx is index of the item within
2125                  *       the memblock. For instance, in case of three RxD-blocks
2126                  *       per memblock this value can be 0, 1 or 2. */
2127                 rxdblock_priv = __vxge_hw_mempool_item_priv(mempoolh,
2128                                         memblock_index, item,
2129                                         &memblock_item_idx);
2130
2131                 rxdp = ring->channel.reserve_arr[reserve_index];
2132
2133                 uld_priv = ((u8 *)rxdblock_priv + ring->rxd_priv_size * i);
2134
2135                 /* pre-format Host_Control */
2136                 rxdp->host_control = (u64)(size_t)uld_priv;
2137         }
2138
2139         __vxge_hw_ring_block_memblock_idx_set(item, memblock_index);
2140
2141         if (is_last) {
2142                 /* link last one with first one */
2143                 __vxge_hw_ring_rxdblock_link(mempoolh, ring, index, 0);
2144         }
2145
2146         if (index > 0) {
2147                 /* link this RxD block with previous one */
2148                 __vxge_hw_ring_rxdblock_link(mempoolh, ring, index - 1, index);
2149         }
2150 }
2151
2152 /*
2153  * __vxge_hw_ring_replenish - Initial replenish of RxDs
2154  * This function replenishes the RxDs from reserve array to work array
2155  */
2156 enum vxge_hw_status
2157 vxge_hw_ring_replenish(struct __vxge_hw_ring *ring)
2158 {
2159         void *rxd;
2160         struct __vxge_hw_channel *channel;
2161         enum vxge_hw_status status = VXGE_HW_OK;
2162
2163         channel = &ring->channel;
2164
2165         while (vxge_hw_channel_dtr_count(channel) > 0) {
2166
2167                 status = vxge_hw_ring_rxd_reserve(ring, &rxd);
2168
2169                 vxge_assert(status == VXGE_HW_OK);
2170
2171                 if (ring->rxd_init) {
2172                         status = ring->rxd_init(rxd, channel->userdata);
2173                         if (status != VXGE_HW_OK) {
2174                                 vxge_hw_ring_rxd_free(ring, rxd);
2175                                 goto exit;
2176                         }
2177                 }
2178
2179                 vxge_hw_ring_rxd_post(ring, rxd);
2180         }
2181         status = VXGE_HW_OK;
2182 exit:
2183         return status;
2184 }
2185
2186 /*
2187  * __vxge_hw_channel_allocate - Allocate memory for channel
2188  * This function allocates required memory for the channel and various arrays
2189  * in the channel
2190  */
2191 static struct __vxge_hw_channel *
2192 __vxge_hw_channel_allocate(struct __vxge_hw_vpath_handle *vph,
2193                            enum __vxge_hw_channel_type type,
2194                            u32 length, u32 per_dtr_space,
2195                            void *userdata)
2196 {
2197         struct __vxge_hw_channel *channel;
2198         struct __vxge_hw_device *hldev;
2199         int size = 0;
2200         u32 vp_id;
2201
2202         hldev = vph->vpath->hldev;
2203         vp_id = vph->vpath->vp_id;
2204
2205         switch (type) {
2206         case VXGE_HW_CHANNEL_TYPE_FIFO:
2207                 size = sizeof(struct __vxge_hw_fifo);
2208                 break;
2209         case VXGE_HW_CHANNEL_TYPE_RING:
2210                 size = sizeof(struct __vxge_hw_ring);
2211                 break;
2212         default:
2213                 break;
2214         }
2215
2216         channel = kzalloc(size, GFP_KERNEL);
2217         if (channel == NULL)
2218                 goto exit0;
2219         INIT_LIST_HEAD(&channel->item);
2220
2221         channel->common_reg = hldev->common_reg;
2222         channel->first_vp_id = hldev->first_vp_id;
2223         channel->type = type;
2224         channel->devh = hldev;
2225         channel->vph = vph;
2226         channel->userdata = userdata;
2227         channel->per_dtr_space = per_dtr_space;
2228         channel->length = length;
2229         channel->vp_id = vp_id;
2230
2231         channel->work_arr = kzalloc(sizeof(void *)*length, GFP_KERNEL);
2232         if (channel->work_arr == NULL)
2233                 goto exit1;
2234
2235         channel->free_arr = kzalloc(sizeof(void *)*length, GFP_KERNEL);
2236         if (channel->free_arr == NULL)
2237                 goto exit1;
2238         channel->free_ptr = length;
2239
2240         channel->reserve_arr = kzalloc(sizeof(void *)*length, GFP_KERNEL);
2241         if (channel->reserve_arr == NULL)
2242                 goto exit1;
2243         channel->reserve_ptr = length;
2244         channel->reserve_top = 0;
2245
2246         channel->orig_arr = kzalloc(sizeof(void *)*length, GFP_KERNEL);
2247         if (channel->orig_arr == NULL)
2248                 goto exit1;
2249
2250         return channel;
2251 exit1:
2252         __vxge_hw_channel_free(channel);
2253
2254 exit0:
2255         return NULL;
2256 }
2257
2258 /*
2259  * vxge_hw_blockpool_block_add - callback for vxge_os_dma_malloc_async
2260  * Adds a block to block pool
2261  */
2262 static void vxge_hw_blockpool_block_add(struct __vxge_hw_device *devh,
2263                                         void *block_addr,
2264                                         u32 length,
2265                                         struct pci_dev *dma_h,
2266                                         struct pci_dev *acc_handle)
2267 {
2268         struct __vxge_hw_blockpool *blockpool;
2269         struct __vxge_hw_blockpool_entry *entry = NULL;
2270         dma_addr_t dma_addr;
2271         enum vxge_hw_status status = VXGE_HW_OK;
2272         u32 req_out;
2273
2274         blockpool = &devh->block_pool;
2275
2276         if (block_addr == NULL) {
2277                 blockpool->req_out--;
2278                 status = VXGE_HW_FAIL;
2279                 goto exit;
2280         }
2281
2282         dma_addr = pci_map_single(devh->pdev, block_addr, length,
2283                                 PCI_DMA_BIDIRECTIONAL);
2284
2285         if (unlikely(pci_dma_mapping_error(devh->pdev, dma_addr))) {
2286                 vxge_os_dma_free(devh->pdev, block_addr, &acc_handle);
2287                 blockpool->req_out--;
2288                 status = VXGE_HW_FAIL;
2289                 goto exit;
2290         }
2291
2292         if (!list_empty(&blockpool->free_entry_list))
2293                 entry = (struct __vxge_hw_blockpool_entry *)
2294                         list_first_entry(&blockpool->free_entry_list,
2295                                 struct __vxge_hw_blockpool_entry,
2296                                 item);
2297
2298         if (entry == NULL)
2299                 entry = vmalloc(sizeof(struct __vxge_hw_blockpool_entry));
2300         else
2301                 list_del(&entry->item);
2302
2303         if (entry != NULL) {
2304                 entry->length = length;
2305                 entry->memblock = block_addr;
2306                 entry->dma_addr = dma_addr;
2307                 entry->acc_handle = acc_handle;
2308                 entry->dma_handle = dma_h;
2309                 list_add(&entry->item, &blockpool->free_block_list);
2310                 blockpool->pool_size++;
2311                 status = VXGE_HW_OK;
2312         } else
2313                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2314
2315         blockpool->req_out--;
2316
2317         req_out = blockpool->req_out;
2318 exit:
2319         return;
2320 }
2321
2322 static inline void
2323 vxge_os_dma_malloc_async(struct pci_dev *pdev, void *devh, unsigned long size)
2324 {
2325         gfp_t flags;
2326         void *vaddr;
2327
2328         if (in_interrupt())
2329                 flags = GFP_ATOMIC | GFP_DMA;
2330         else
2331                 flags = GFP_KERNEL | GFP_DMA;
2332
2333         vaddr = kmalloc((size), flags);
2334
2335         vxge_hw_blockpool_block_add(devh, vaddr, size, pdev, pdev);
2336 }
2337
2338 /*
2339  * __vxge_hw_blockpool_blocks_add - Request additional blocks
2340  */
2341 static
2342 void __vxge_hw_blockpool_blocks_add(struct __vxge_hw_blockpool *blockpool)
2343 {
2344         u32 nreq = 0, i;
2345
2346         if ((blockpool->pool_size  +  blockpool->req_out) <
2347                 VXGE_HW_MIN_DMA_BLOCK_POOL_SIZE) {
2348                 nreq = VXGE_HW_INCR_DMA_BLOCK_POOL_SIZE;
2349                 blockpool->req_out += nreq;
2350         }
2351
2352         for (i = 0; i < nreq; i++)
2353                 vxge_os_dma_malloc_async(
2354                         ((struct __vxge_hw_device *)blockpool->hldev)->pdev,
2355                         blockpool->hldev, VXGE_HW_BLOCK_SIZE);
2356 }
2357
2358 /*
2359  * __vxge_hw_blockpool_malloc - Allocate a memory block from pool
2360  * Allocates a block of memory of given size, either from block pool
2361  * or by calling vxge_os_dma_malloc()
2362  */
2363 static void *__vxge_hw_blockpool_malloc(struct __vxge_hw_device *devh, u32 size,
2364                                         struct vxge_hw_mempool_dma *dma_object)
2365 {
2366         struct __vxge_hw_blockpool_entry *entry = NULL;
2367         struct __vxge_hw_blockpool  *blockpool;
2368         void *memblock = NULL;
2369         enum vxge_hw_status status = VXGE_HW_OK;
2370
2371         blockpool = &devh->block_pool;
2372
2373         if (size != blockpool->block_size) {
2374
2375                 memblock = vxge_os_dma_malloc(devh->pdev, size,
2376                                                 &dma_object->handle,
2377                                                 &dma_object->acc_handle);
2378
2379                 if (memblock == NULL) {
2380                         status = VXGE_HW_ERR_OUT_OF_MEMORY;
2381                         goto exit;
2382                 }
2383
2384                 dma_object->addr = pci_map_single(devh->pdev, memblock, size,
2385                                         PCI_DMA_BIDIRECTIONAL);
2386
2387                 if (unlikely(pci_dma_mapping_error(devh->pdev,
2388                                 dma_object->addr))) {
2389                         vxge_os_dma_free(devh->pdev, memblock,
2390                                 &dma_object->acc_handle);
2391                         status = VXGE_HW_ERR_OUT_OF_MEMORY;
2392                         goto exit;
2393                 }
2394
2395         } else {
2396
2397                 if (!list_empty(&blockpool->free_block_list))
2398                         entry = (struct __vxge_hw_blockpool_entry *)
2399                                 list_first_entry(&blockpool->free_block_list,
2400                                         struct __vxge_hw_blockpool_entry,
2401                                         item);
2402
2403                 if (entry != NULL) {
2404                         list_del(&entry->item);
2405                         dma_object->addr = entry->dma_addr;
2406                         dma_object->handle = entry->dma_handle;
2407                         dma_object->acc_handle = entry->acc_handle;
2408                         memblock = entry->memblock;
2409
2410                         list_add(&entry->item,
2411                                 &blockpool->free_entry_list);
2412                         blockpool->pool_size--;
2413                 }
2414
2415                 if (memblock != NULL)
2416                         __vxge_hw_blockpool_blocks_add(blockpool);
2417         }
2418 exit:
2419         return memblock;
2420 }
2421
2422 /*
2423  * __vxge_hw_blockpool_blocks_remove - Free additional blocks
2424  */
2425 static void
2426 __vxge_hw_blockpool_blocks_remove(struct __vxge_hw_blockpool *blockpool)
2427 {
2428         struct list_head *p, *n;
2429
2430         list_for_each_safe(p, n, &blockpool->free_block_list) {
2431
2432                 if (blockpool->pool_size < blockpool->pool_max)
2433                         break;
2434
2435                 pci_unmap_single(
2436                         ((struct __vxge_hw_device *)blockpool->hldev)->pdev,
2437                         ((struct __vxge_hw_blockpool_entry *)p)->dma_addr,
2438                         ((struct __vxge_hw_blockpool_entry *)p)->length,
2439                         PCI_DMA_BIDIRECTIONAL);
2440
2441                 vxge_os_dma_free(
2442                         ((struct __vxge_hw_device *)blockpool->hldev)->pdev,
2443                         ((struct __vxge_hw_blockpool_entry *)p)->memblock,
2444                         &((struct __vxge_hw_blockpool_entry *)p)->acc_handle);
2445
2446                 list_del(&((struct __vxge_hw_blockpool_entry *)p)->item);
2447
2448                 list_add(p, &blockpool->free_entry_list);
2449
2450                 blockpool->pool_size--;
2451
2452         }
2453 }
2454
2455 /*
2456  * __vxge_hw_blockpool_free - Frees the memory allcoated with
2457  *                              __vxge_hw_blockpool_malloc
2458  */
2459 static void __vxge_hw_blockpool_free(struct __vxge_hw_device *devh,
2460                                      void *memblock, u32 size,
2461                                      struct vxge_hw_mempool_dma *dma_object)
2462 {
2463         struct __vxge_hw_blockpool_entry *entry = NULL;
2464         struct __vxge_hw_blockpool  *blockpool;
2465         enum vxge_hw_status status = VXGE_HW_OK;
2466
2467         blockpool = &devh->block_pool;
2468
2469         if (size != blockpool->block_size) {
2470                 pci_unmap_single(devh->pdev, dma_object->addr, size,
2471                         PCI_DMA_BIDIRECTIONAL);
2472                 vxge_os_dma_free(devh->pdev, memblock, &dma_object->acc_handle);
2473         } else {
2474
2475                 if (!list_empty(&blockpool->free_entry_list))
2476                         entry = (struct __vxge_hw_blockpool_entry *)
2477                                 list_first_entry(&blockpool->free_entry_list,
2478                                         struct __vxge_hw_blockpool_entry,
2479                                         item);
2480
2481                 if (entry == NULL)
2482                         entry = vmalloc(sizeof(
2483                                         struct __vxge_hw_blockpool_entry));
2484                 else
2485                         list_del(&entry->item);
2486
2487                 if (entry != NULL) {
2488                         entry->length = size;
2489                         entry->memblock = memblock;
2490                         entry->dma_addr = dma_object->addr;
2491                         entry->acc_handle = dma_object->acc_handle;
2492                         entry->dma_handle = dma_object->handle;
2493                         list_add(&entry->item,
2494                                         &blockpool->free_block_list);
2495                         blockpool->pool_size++;
2496                         status = VXGE_HW_OK;
2497                 } else
2498                         status = VXGE_HW_ERR_OUT_OF_MEMORY;
2499
2500                 if (status == VXGE_HW_OK)
2501                         __vxge_hw_blockpool_blocks_remove(blockpool);
2502         }
2503 }
2504
2505 /*
2506  * vxge_hw_mempool_destroy
2507  */
2508 static void __vxge_hw_mempool_destroy(struct vxge_hw_mempool *mempool)
2509 {
2510         u32 i, j;
2511         struct __vxge_hw_device *devh = mempool->devh;
2512
2513         for (i = 0; i < mempool->memblocks_allocated; i++) {
2514                 struct vxge_hw_mempool_dma *dma_object;
2515
2516                 vxge_assert(mempool->memblocks_arr[i]);
2517                 vxge_assert(mempool->memblocks_dma_arr + i);
2518
2519                 dma_object = mempool->memblocks_dma_arr + i;
2520
2521                 for (j = 0; j < mempool->items_per_memblock; j++) {
2522                         u32 index = i * mempool->items_per_memblock + j;
2523
2524                         /* to skip last partially filled(if any) memblock */
2525                         if (index >= mempool->items_current)
2526                                 break;
2527                 }
2528
2529                 vfree(mempool->memblocks_priv_arr[i]);
2530
2531                 __vxge_hw_blockpool_free(devh, mempool->memblocks_arr[i],
2532                                 mempool->memblock_size, dma_object);
2533         }
2534
2535         vfree(mempool->items_arr);
2536         vfree(mempool->memblocks_dma_arr);
2537         vfree(mempool->memblocks_priv_arr);
2538         vfree(mempool->memblocks_arr);
2539         vfree(mempool);
2540 }
2541
2542 /*
2543  * __vxge_hw_mempool_grow
2544  * Will resize mempool up to %num_allocate value.
2545  */
2546 static enum vxge_hw_status
2547 __vxge_hw_mempool_grow(struct vxge_hw_mempool *mempool, u32 num_allocate,
2548                        u32 *num_allocated)
2549 {
2550         u32 i, first_time = mempool->memblocks_allocated == 0 ? 1 : 0;
2551         u32 n_items = mempool->items_per_memblock;
2552         u32 start_block_idx = mempool->memblocks_allocated;
2553         u32 end_block_idx = mempool->memblocks_allocated + num_allocate;
2554         enum vxge_hw_status status = VXGE_HW_OK;
2555
2556         *num_allocated = 0;
2557
2558         if (end_block_idx > mempool->memblocks_max) {
2559                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2560                 goto exit;
2561         }
2562
2563         for (i = start_block_idx; i < end_block_idx; i++) {
2564                 u32 j;
2565                 u32 is_last = ((end_block_idx - 1) == i);
2566                 struct vxge_hw_mempool_dma *dma_object =
2567                         mempool->memblocks_dma_arr + i;
2568                 void *the_memblock;
2569
2570                 /* allocate memblock's private part. Each DMA memblock
2571                  * has a space allocated for item's private usage upon
2572                  * mempool's user request. Each time mempool grows, it will
2573                  * allocate new memblock and its private part at once.
2574                  * This helps to minimize memory usage a lot. */
2575                 mempool->memblocks_priv_arr[i] =
2576                                 vzalloc(mempool->items_priv_size * n_items);
2577                 if (mempool->memblocks_priv_arr[i] == NULL) {
2578                         status = VXGE_HW_ERR_OUT_OF_MEMORY;
2579                         goto exit;
2580                 }
2581
2582                 /* allocate DMA-capable memblock */
2583                 mempool->memblocks_arr[i] =
2584                         __vxge_hw_blockpool_malloc(mempool->devh,
2585                                 mempool->memblock_size, dma_object);
2586                 if (mempool->memblocks_arr[i] == NULL) {
2587                         vfree(mempool->memblocks_priv_arr[i]);
2588                         status = VXGE_HW_ERR_OUT_OF_MEMORY;
2589                         goto exit;
2590                 }
2591
2592                 (*num_allocated)++;
2593                 mempool->memblocks_allocated++;
2594
2595                 memset(mempool->memblocks_arr[i], 0, mempool->memblock_size);
2596
2597                 the_memblock = mempool->memblocks_arr[i];
2598
2599                 /* fill the items hash array */
2600                 for (j = 0; j < n_items; j++) {
2601                         u32 index = i * n_items + j;
2602
2603                         if (first_time && index >= mempool->items_initial)
2604                                 break;
2605
2606                         mempool->items_arr[index] =
2607                                 ((char *)the_memblock + j*mempool->item_size);
2608
2609                         /* let caller to do more job on each item */
2610                         if (mempool->item_func_alloc != NULL)
2611                                 mempool->item_func_alloc(mempool, i,
2612                                         dma_object, index, is_last);
2613
2614                         mempool->items_current = index + 1;
2615                 }
2616
2617                 if (first_time && mempool->items_current ==
2618                                         mempool->items_initial)
2619                         break;
2620         }
2621 exit:
2622         return status;
2623 }
2624
2625 /*
2626  * vxge_hw_mempool_create
2627  * This function will create memory pool object. Pool may grow but will
2628  * never shrink. Pool consists of number of dynamically allocated blocks
2629  * with size enough to hold %items_initial number of items. Memory is
2630  * DMA-able but client must map/unmap before interoperating with the device.
2631  */
2632 static struct vxge_hw_mempool *
2633 __vxge_hw_mempool_create(struct __vxge_hw_device *devh,
2634                          u32 memblock_size,
2635                          u32 item_size,
2636                          u32 items_priv_size,
2637                          u32 items_initial,
2638                          u32 items_max,
2639                          struct vxge_hw_mempool_cbs *mp_callback,
2640                          void *userdata)
2641 {
2642         enum vxge_hw_status status = VXGE_HW_OK;
2643         u32 memblocks_to_allocate;
2644         struct vxge_hw_mempool *mempool = NULL;
2645         u32 allocated;
2646
2647         if (memblock_size < item_size) {
2648                 status = VXGE_HW_FAIL;
2649                 goto exit;
2650         }
2651
2652         mempool = vzalloc(sizeof(struct vxge_hw_mempool));
2653         if (mempool == NULL) {
2654                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2655                 goto exit;
2656         }
2657
2658         mempool->devh                   = devh;
2659         mempool->memblock_size          = memblock_size;
2660         mempool->items_max              = items_max;
2661         mempool->items_initial          = items_initial;
2662         mempool->item_size              = item_size;
2663         mempool->items_priv_size        = items_priv_size;
2664         mempool->item_func_alloc        = mp_callback->item_func_alloc;
2665         mempool->userdata               = userdata;
2666
2667         mempool->memblocks_allocated = 0;
2668
2669         mempool->items_per_memblock = memblock_size / item_size;
2670
2671         mempool->memblocks_max = (items_max + mempool->items_per_memblock - 1) /
2672                                         mempool->items_per_memblock;
2673
2674         /* allocate array of memblocks */
2675         mempool->memblocks_arr =
2676                 vzalloc(sizeof(void *) * mempool->memblocks_max);
2677         if (mempool->memblocks_arr == NULL) {
2678                 __vxge_hw_mempool_destroy(mempool);
2679                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2680                 mempool = NULL;
2681                 goto exit;
2682         }
2683
2684         /* allocate array of private parts of items per memblocks */
2685         mempool->memblocks_priv_arr =
2686                 vzalloc(sizeof(void *) * mempool->memblocks_max);
2687         if (mempool->memblocks_priv_arr == NULL) {
2688                 __vxge_hw_mempool_destroy(mempool);
2689                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2690                 mempool = NULL;
2691                 goto exit;
2692         }
2693
2694         /* allocate array of memblocks DMA objects */
2695         mempool->memblocks_dma_arr =
2696                 vzalloc(sizeof(struct vxge_hw_mempool_dma) *
2697                         mempool->memblocks_max);
2698         if (mempool->memblocks_dma_arr == NULL) {
2699                 __vxge_hw_mempool_destroy(mempool);
2700                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2701                 mempool = NULL;
2702                 goto exit;
2703         }
2704
2705         /* allocate hash array of items */
2706         mempool->items_arr = vzalloc(sizeof(void *) * mempool->items_max);
2707         if (mempool->items_arr == NULL) {
2708                 __vxge_hw_mempool_destroy(mempool);
2709                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2710                 mempool = NULL;
2711                 goto exit;
2712         }
2713
2714         /* calculate initial number of memblocks */
2715         memblocks_to_allocate = (mempool->items_initial +
2716                                  mempool->items_per_memblock - 1) /
2717                                                 mempool->items_per_memblock;
2718
2719         /* pre-allocate the mempool */
2720         status = __vxge_hw_mempool_grow(mempool, memblocks_to_allocate,
2721                                         &allocated);
2722         if (status != VXGE_HW_OK) {
2723                 __vxge_hw_mempool_destroy(mempool);
2724                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2725                 mempool = NULL;
2726                 goto exit;
2727         }
2728
2729 exit:
2730         return mempool;
2731 }
2732
2733 /*
2734  * __vxge_hw_ring_abort - Returns the RxD
2735  * This function terminates the RxDs of ring
2736  */
2737 static enum vxge_hw_status __vxge_hw_ring_abort(struct __vxge_hw_ring *ring)
2738 {
2739         void *rxdh;
2740         struct __vxge_hw_channel *channel;
2741
2742         channel = &ring->channel;
2743
2744         for (;;) {
2745                 vxge_hw_channel_dtr_try_complete(channel, &rxdh);
2746
2747                 if (rxdh == NULL)
2748                         break;
2749
2750                 vxge_hw_channel_dtr_complete(channel);
2751
2752                 if (ring->rxd_term)
2753                         ring->rxd_term(rxdh, VXGE_HW_RXD_STATE_POSTED,
2754                                 channel->userdata);
2755
2756                 vxge_hw_channel_dtr_free(channel, rxdh);
2757         }
2758
2759         return VXGE_HW_OK;
2760 }
2761
2762 /*
2763  * __vxge_hw_ring_reset - Resets the ring
2764  * This function resets the ring during vpath reset operation
2765  */
2766 static enum vxge_hw_status __vxge_hw_ring_reset(struct __vxge_hw_ring *ring)
2767 {
2768         enum vxge_hw_status status = VXGE_HW_OK;
2769         struct __vxge_hw_channel *channel;
2770
2771         channel = &ring->channel;
2772
2773         __vxge_hw_ring_abort(ring);
2774
2775         status = __vxge_hw_channel_reset(channel);
2776
2777         if (status != VXGE_HW_OK)
2778                 goto exit;
2779
2780         if (ring->rxd_init) {
2781                 status = vxge_hw_ring_replenish(ring);
2782                 if (status != VXGE_HW_OK)
2783                         goto exit;
2784         }
2785 exit:
2786         return status;
2787 }
2788
2789 /*
2790  * __vxge_hw_ring_delete - Removes the ring
2791  * This function freeup the memory pool and removes the ring
2792  */
2793 static enum vxge_hw_status
2794 __vxge_hw_ring_delete(struct __vxge_hw_vpath_handle *vp)
2795 {
2796         struct __vxge_hw_ring *ring = vp->vpath->ringh;
2797
2798         __vxge_hw_ring_abort(ring);
2799
2800         if (ring->mempool)
2801                 __vxge_hw_mempool_destroy(ring->mempool);
2802
2803         vp->vpath->ringh = NULL;
2804         __vxge_hw_channel_free(&ring->channel);
2805
2806         return VXGE_HW_OK;
2807 }
2808
2809 /*
2810  * __vxge_hw_ring_create - Create a Ring
2811  * This function creates Ring and initializes it.
2812  */
2813 static enum vxge_hw_status
2814 __vxge_hw_ring_create(struct __vxge_hw_vpath_handle *vp,
2815                       struct vxge_hw_ring_attr *attr)
2816 {
2817         enum vxge_hw_status status = VXGE_HW_OK;
2818         struct __vxge_hw_ring *ring;
2819         u32 ring_length;
2820         struct vxge_hw_ring_config *config;
2821         struct __vxge_hw_device *hldev;
2822         u32 vp_id;
2823         struct vxge_hw_mempool_cbs ring_mp_callback;
2824
2825         if ((vp == NULL) || (attr == NULL)) {
2826                 status = VXGE_HW_FAIL;
2827                 goto exit;
2828         }
2829
2830         hldev = vp->vpath->hldev;
2831         vp_id = vp->vpath->vp_id;
2832
2833         config = &hldev->config.vp_config[vp_id].ring;
2834
2835         ring_length = config->ring_blocks *
2836                         vxge_hw_ring_rxds_per_block_get(config->buffer_mode);
2837
2838         ring = (struct __vxge_hw_ring *)__vxge_hw_channel_allocate(vp,
2839                                                 VXGE_HW_CHANNEL_TYPE_RING,
2840                                                 ring_length,
2841                                                 attr->per_rxd_space,
2842                                                 attr->userdata);
2843         if (ring == NULL) {
2844                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2845                 goto exit;
2846         }
2847
2848         vp->vpath->ringh = ring;
2849         ring->vp_id = vp_id;
2850         ring->vp_reg = vp->vpath->vp_reg;
2851         ring->common_reg = hldev->common_reg;
2852         ring->stats = &vp->vpath->sw_stats->ring_stats;
2853         ring->config = config;
2854         ring->callback = attr->callback;
2855         ring->rxd_init = attr->rxd_init;
2856         ring->rxd_term = attr->rxd_term;
2857         ring->buffer_mode = config->buffer_mode;
2858         ring->tim_rti_cfg1_saved = vp->vpath->tim_rti_cfg1_saved;
2859         ring->tim_rti_cfg3_saved = vp->vpath->tim_rti_cfg3_saved;
2860         ring->rxds_limit = config->rxds_limit;
2861
2862         ring->rxd_size = vxge_hw_ring_rxd_size_get(config->buffer_mode);
2863         ring->rxd_priv_size =
2864                 sizeof(struct __vxge_hw_ring_rxd_priv) + attr->per_rxd_space;
2865         ring->per_rxd_space = attr->per_rxd_space;
2866
2867         ring->rxd_priv_size =
2868                 ((ring->rxd_priv_size + VXGE_CACHE_LINE_SIZE - 1) /
2869                 VXGE_CACHE_LINE_SIZE) * VXGE_CACHE_LINE_SIZE;
2870
2871         /* how many RxDs can fit into one block. Depends on configured
2872          * buffer_mode. */
2873         ring->rxds_per_block =
2874                 vxge_hw_ring_rxds_per_block_get(config->buffer_mode);
2875
2876         /* calculate actual RxD block private size */
2877         ring->rxdblock_priv_size = ring->rxd_priv_size * ring->rxds_per_block;
2878         ring_mp_callback.item_func_alloc = __vxge_hw_ring_mempool_item_alloc;
2879         ring->mempool = __vxge_hw_mempool_create(hldev,
2880                                 VXGE_HW_BLOCK_SIZE,
2881                                 VXGE_HW_BLOCK_SIZE,
2882                                 ring->rxdblock_priv_size,
2883                                 ring->config->ring_blocks,
2884                                 ring->config->ring_blocks,
2885                                 &ring_mp_callback,
2886                                 ring);
2887         if (ring->mempool == NULL) {
2888                 __vxge_hw_ring_delete(vp);
2889                 return VXGE_HW_ERR_OUT_OF_MEMORY;
2890         }
2891
2892         status = __vxge_hw_channel_initialize(&ring->channel);
2893         if (status != VXGE_HW_OK) {
2894                 __vxge_hw_ring_delete(vp);
2895                 goto exit;
2896         }
2897
2898         /* Note:
2899          * Specifying rxd_init callback means two things:
2900          * 1) rxds need to be initialized by driver at channel-open time;
2901          * 2) rxds need to be posted at channel-open time
2902          *    (that's what the initial_replenish() below does)
2903          * Currently we don't have a case when the 1) is done without the 2).
2904          */
2905         if (ring->rxd_init) {
2906                 status = vxge_hw_ring_replenish(ring);
2907                 if (status != VXGE_HW_OK) {
2908                         __vxge_hw_ring_delete(vp);
2909                         goto exit;
2910                 }
2911         }
2912
2913         /* initial replenish will increment the counter in its post() routine,
2914          * we have to reset it */
2915         ring->stats->common_stats.usage_cnt = 0;
2916 exit:
2917         return status;
2918 }
2919
2920 /*
2921  * vxge_hw_device_config_default_get - Initialize device config with defaults.
2922  * Initialize Titan device config with default values.
2923  */
2924 enum vxge_hw_status __devinit
2925 vxge_hw_device_config_default_get(struct vxge_hw_device_config *device_config)
2926 {
2927         u32 i;
2928
2929         device_config->dma_blockpool_initial =
2930                                         VXGE_HW_INITIAL_DMA_BLOCK_POOL_SIZE;
2931         device_config->dma_blockpool_max = VXGE_HW_MAX_DMA_BLOCK_POOL_SIZE;
2932         device_config->intr_mode = VXGE_HW_INTR_MODE_DEF;
2933         device_config->rth_en = VXGE_HW_RTH_DEFAULT;
2934         device_config->rth_it_type = VXGE_HW_RTH_IT_TYPE_DEFAULT;
2935         device_config->device_poll_millis =  VXGE_HW_DEF_DEVICE_POLL_MILLIS;
2936         device_config->rts_mac_en =  VXGE_HW_RTS_MAC_DEFAULT;
2937
2938         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
2939                 device_config->vp_config[i].vp_id = i;
2940
2941                 device_config->vp_config[i].min_bandwidth =
2942                                 VXGE_HW_VPATH_BANDWIDTH_DEFAULT;
2943
2944                 device_config->vp_config[i].ring.enable = VXGE_HW_RING_DEFAULT;
2945
2946                 device_config->vp_config[i].ring.ring_blocks =
2947                                 VXGE_HW_DEF_RING_BLOCKS;
2948
2949                 device_config->vp_config[i].ring.buffer_mode =
2950                                 VXGE_HW_RING_RXD_BUFFER_MODE_DEFAULT;
2951
2952                 device_config->vp_config[i].ring.scatter_mode =
2953                                 VXGE_HW_RING_SCATTER_MODE_USE_FLASH_DEFAULT;
2954
2955                 device_config->vp_config[i].ring.rxds_limit =
2956                                 VXGE_HW_DEF_RING_RXDS_LIMIT;
2957
2958                 device_config->vp_config[i].fifo.enable = VXGE_HW_FIFO_ENABLE;
2959
2960                 device_config->vp_config[i].fifo.fifo_blocks =
2961                                 VXGE_HW_MIN_FIFO_BLOCKS;
2962
2963                 device_config->vp_config[i].fifo.max_frags =
2964                                 VXGE_HW_MAX_FIFO_FRAGS;
2965
2966                 device_config->vp_config[i].fifo.memblock_size =
2967                                 VXGE_HW_DEF_FIFO_MEMBLOCK_SIZE;
2968
2969                 device_config->vp_config[i].fifo.alignment_size =
2970                                 VXGE_HW_DEF_FIFO_ALIGNMENT_SIZE;
2971
2972                 device_config->vp_config[i].fifo.intr =
2973                                 VXGE_HW_FIFO_QUEUE_INTR_DEFAULT;
2974
2975                 device_config->vp_config[i].fifo.no_snoop_bits =
2976                                 VXGE_HW_FIFO_NO_SNOOP_DEFAULT;
2977                 device_config->vp_config[i].tti.intr_enable =
2978                                 VXGE_HW_TIM_INTR_DEFAULT;
2979
2980                 device_config->vp_config[i].tti.btimer_val =
2981                                 VXGE_HW_USE_FLASH_DEFAULT;
2982
2983                 device_config->vp_config[i].tti.timer_ac_en =
2984                                 VXGE_HW_USE_FLASH_DEFAULT;
2985
2986                 device_config->vp_config[i].tti.timer_ci_en =
2987                                 VXGE_HW_USE_FLASH_DEFAULT;
2988
2989                 device_config->vp_config[i].tti.timer_ri_en =
2990                                 VXGE_HW_USE_FLASH_DEFAULT;
2991
2992                 device_config->vp_config[i].tti.rtimer_val =
2993                                 VXGE_HW_USE_FLASH_DEFAULT;
2994
2995                 device_config->vp_config[i].tti.util_sel =
2996                                 VXGE_HW_USE_FLASH_DEFAULT;
2997
2998                 device_config->vp_config[i].tti.ltimer_val =
2999                                 VXGE_HW_USE_FLASH_DEFAULT;
3000
3001                 device_config->vp_config[i].tti.urange_a =
3002                                 VXGE_HW_USE_FLASH_DEFAULT;
3003
3004                 device_config->vp_config[i].tti.uec_a =
3005                                 VXGE_HW_USE_FLASH_DEFAULT;
3006
3007                 device_config->vp_config[i].tti.urange_b =
3008                                 VXGE_HW_USE_FLASH_DEFAULT;
3009
3010                 device_config->vp_config[i].tti.uec_b =
3011                                 VXGE_HW_USE_FLASH_DEFAULT;
3012
3013                 device_config->vp_config[i].tti.urange_c =
3014                                 VXGE_HW_USE_FLASH_DEFAULT;
3015
3016                 device_config->vp_config[i].tti.uec_c =
3017                                 VXGE_HW_USE_FLASH_DEFAULT;
3018
3019                 device_config->vp_config[i].tti.uec_d =
3020                                 VXGE_HW_USE_FLASH_DEFAULT;
3021
3022                 device_config->vp_config[i].rti.intr_enable =
3023                                 VXGE_HW_TIM_INTR_DEFAULT;
3024
3025                 device_config->vp_config[i].rti.btimer_val =
3026                                 VXGE_HW_USE_FLASH_DEFAULT;
3027
3028                 device_config->vp_config[i].rti.timer_ac_en =
3029                                 VXGE_HW_USE_FLASH_DEFAULT;
3030
3031                 device_config->vp_config[i].rti.timer_ci_en =
3032                                 VXGE_HW_USE_FLASH_DEFAULT;
3033
3034                 device_config->vp_config[i].rti.timer_ri_en =
3035                                 VXGE_HW_USE_FLASH_DEFAULT;
3036
3037                 device_config->vp_config[i].rti.rtimer_val =
3038                                 VXGE_HW_USE_FLASH_DEFAULT;
3039
3040                 device_config->vp_config[i].rti.util_sel =
3041                                 VXGE_HW_USE_FLASH_DEFAULT;
3042
3043                 device_config->vp_config[i].rti.ltimer_val =
3044                                 VXGE_HW_USE_FLASH_DEFAULT;
3045
3046                 device_config->vp_config[i].rti.urange_a =
3047                                 VXGE_HW_USE_FLASH_DEFAULT;
3048
3049                 device_config->vp_config[i].rti.uec_a =
3050                                 VXGE_HW_USE_FLASH_DEFAULT;
3051
3052                 device_config->vp_config[i].rti.urange_b =
3053                                 VXGE_HW_USE_FLASH_DEFAULT;
3054
3055                 device_config->vp_config[i].rti.uec_b =
3056                                 VXGE_HW_USE_FLASH_DEFAULT;
3057
3058                 device_config->vp_config[i].rti.urange_c =
3059                                 VXGE_HW_USE_FLASH_DEFAULT;
3060
3061                 device_config->vp_config[i].rti.uec_c =
3062                                 VXGE_HW_USE_FLASH_DEFAULT;
3063
3064                 device_config->vp_config[i].rti.uec_d =
3065                                 VXGE_HW_USE_FLASH_DEFAULT;
3066
3067                 device_config->vp_config[i].mtu =
3068                                 VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU;
3069
3070                 device_config->vp_config[i].rpa_strip_vlan_tag =
3071                         VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT;
3072         }
3073
3074         return VXGE_HW_OK;
3075 }
3076
3077 /*
3078  * __vxge_hw_vpath_swapper_set - Set the swapper bits for the vpath.
3079  * Set the swapper bits appropriately for the vpath.
3080  */
3081 static enum vxge_hw_status
3082 __vxge_hw_vpath_swapper_set(struct vxge_hw_vpath_reg __iomem *vpath_reg)
3083 {
3084 #ifndef __BIG_ENDIAN
3085         u64 val64;
3086
3087         val64 = readq(&vpath_reg->vpath_general_cfg1);
3088         wmb();
3089         val64 |= VXGE_HW_VPATH_GENERAL_CFG1_CTL_BYTE_SWAPEN;
3090         writeq(val64, &vpath_reg->vpath_general_cfg1);
3091         wmb();
3092 #endif
3093         return VXGE_HW_OK;
3094 }
3095
3096 /*
3097  * __vxge_hw_kdfc_swapper_set - Set the swapper bits for the kdfc.
3098  * Set the swapper bits appropriately for the vpath.
3099  */
3100 static enum vxge_hw_status
3101 __vxge_hw_kdfc_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg,
3102                            struct vxge_hw_vpath_reg __iomem *vpath_reg)
3103 {
3104         u64 val64;
3105
3106         val64 = readq(&legacy_reg->pifm_wr_swap_en);
3107
3108         if (val64 == VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE) {
3109                 val64 = readq(&vpath_reg->kdfcctl_cfg0);
3110                 wmb();
3111
3112                 val64 |= VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO0 |
3113                         VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO1  |
3114                         VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO2;
3115
3116                 writeq(val64, &vpath_reg->kdfcctl_cfg0);
3117                 wmb();
3118         }
3119
3120         return VXGE_HW_OK;
3121 }
3122
3123 /*
3124  * vxge_hw_mgmt_reg_read - Read Titan register.
3125  */
3126 enum vxge_hw_status
3127 vxge_hw_mgmt_reg_read(struct __vxge_hw_device *hldev,
3128                       enum vxge_hw_mgmt_reg_type type,
3129                       u32 index, u32 offset, u64 *value)
3130 {
3131         enum vxge_hw_status status = VXGE_HW_OK;
3132
3133         if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
3134                 status = VXGE_HW_ERR_INVALID_DEVICE;
3135                 goto exit;
3136         }
3137
3138         switch (type) {
3139         case vxge_hw_mgmt_reg_type_legacy:
3140                 if (offset > sizeof(struct vxge_hw_legacy_reg) - 8) {
3141                         status = VXGE_HW_ERR_INVALID_OFFSET;
3142                         break;
3143                 }
3144                 *value = readq((void __iomem *)hldev->legacy_reg + offset);
3145                 break;
3146         case vxge_hw_mgmt_reg_type_toc:
3147                 if (offset > sizeof(struct vxge_hw_toc_reg) - 8) {
3148                         status = VXGE_HW_ERR_INVALID_OFFSET;
3149                         break;
3150                 }
3151                 *value = readq((void __iomem *)hldev->toc_reg + offset);
3152                 break;
3153         case vxge_hw_mgmt_reg_type_common:
3154                 if (offset > sizeof(struct vxge_hw_common_reg) - 8) {
3155                         status = VXGE_HW_ERR_INVALID_OFFSET;
3156                         break;
3157                 }
3158                 *value = readq((void __iomem *)hldev->common_reg + offset);
3159                 break;
3160         case vxge_hw_mgmt_reg_type_mrpcim:
3161                 if (!(hldev->access_rights &
3162                         VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) {
3163                         status = VXGE_HW_ERR_PRIVILAGED_OPEARATION;
3164                         break;
3165                 }
3166                 if (offset > sizeof(struct vxge_hw_mrpcim_reg) - 8) {
3167                         status = VXGE_HW_ERR_INVALID_OFFSET;
3168                         break;
3169                 }
3170                 *value = readq((void __iomem *)hldev->mrpcim_reg + offset);
3171                 break;
3172         case vxge_hw_mgmt_reg_type_srpcim:
3173                 if (!(hldev->access_rights &
3174                         VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM)) {
3175                         status = VXGE_HW_ERR_PRIVILAGED_OPEARATION;
3176                         break;
3177                 }
3178                 if (index > VXGE_HW_TITAN_SRPCIM_REG_SPACES - 1) {
3179                         status = VXGE_HW_ERR_INVALID_INDEX;
3180                         break;
3181                 }
3182                 if (offset > sizeof(struct vxge_hw_srpcim_reg) - 8) {
3183                         status = VXGE_HW_ERR_INVALID_OFFSET;
3184                         break;
3185                 }
3186                 *value = readq((void __iomem *)hldev->srpcim_reg[index] +
3187                                 offset);
3188                 break;
3189         case vxge_hw_mgmt_reg_type_vpmgmt:
3190                 if ((index > VXGE_HW_TITAN_VPMGMT_REG_SPACES - 1) ||
3191                         (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
3192                         status = VXGE_HW_ERR_INVALID_INDEX;
3193                         break;
3194                 }
3195                 if (offset > sizeof(struct vxge_hw_vpmgmt_reg) - 8) {
3196                         status = VXGE_HW_ERR_INVALID_OFFSET;
3197                         break;
3198                 }
3199                 *value = readq((void __iomem *)hldev->vpmgmt_reg[index] +
3200                                 offset);
3201                 break;
3202         case vxge_hw_mgmt_reg_type_vpath:
3203                 if ((index > VXGE_HW_TITAN_VPATH_REG_SPACES - 1) ||
3204                         (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
3205                         status = VXGE_HW_ERR_INVALID_INDEX;
3206                         break;
3207                 }
3208                 if (index > VXGE_HW_TITAN_VPATH_REG_SPACES - 1) {
3209                         status = VXGE_HW_ERR_INVALID_INDEX;
3210                         break;
3211                 }
3212                 if (offset > sizeof(struct vxge_hw_vpath_reg) - 8) {
3213                         status = VXGE_HW_ERR_INVALID_OFFSET;
3214                         break;
3215                 }
3216                 *value = readq((void __iomem *)hldev->vpath_reg[index] +
3217                                 offset);
3218                 break;
3219         default:
3220                 status = VXGE_HW_ERR_INVALID_TYPE;
3221                 break;
3222         }
3223
3224 exit:
3225         return status;
3226 }
3227
3228 /*
3229  * vxge_hw_vpath_strip_fcs_check - Check for FCS strip.
3230  */
3231 enum vxge_hw_status
3232 vxge_hw_vpath_strip_fcs_check(struct __vxge_hw_device *hldev, u64 vpath_mask)
3233 {
3234         struct vxge_hw_vpmgmt_reg       __iomem *vpmgmt_reg;
3235         enum vxge_hw_status status = VXGE_HW_OK;
3236         int i = 0, j = 0;
3237
3238         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
3239                 if (!((vpath_mask) & vxge_mBIT(i)))
3240                         continue;
3241                 vpmgmt_reg = hldev->vpmgmt_reg[i];
3242                 for (j = 0; j < VXGE_HW_MAC_MAX_MAC_PORT_ID; j++) {
3243                         if (readq(&vpmgmt_reg->rxmac_cfg0_port_vpmgmt_clone[j])
3244                         & VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_STRIP_FCS)
3245                                 return VXGE_HW_FAIL;
3246                 }
3247         }
3248         return status;
3249 }
3250 /*
3251  * vxge_hw_mgmt_reg_Write - Write Titan register.
3252  */
3253 enum vxge_hw_status
3254 vxge_hw_mgmt_reg_write(struct __vxge_hw_device *hldev,
3255                       enum vxge_hw_mgmt_reg_type type,
3256                       u32 index, u32 offset, u64 value)
3257 {
3258         enum vxge_hw_status status = VXGE_HW_OK;
3259
3260         if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
3261                 status = VXGE_HW_ERR_INVALID_DEVICE;
3262                 goto exit;
3263         }
3264
3265         switch (type) {
3266         case vxge_hw_mgmt_reg_type_legacy:
3267                 if (offset > sizeof(struct vxge_hw_legacy_reg) - 8) {
3268                         status = VXGE_HW_ERR_INVALID_OFFSET;
3269                         break;
3270                 }
3271                 writeq(value, (void __iomem *)hldev->legacy_reg + offset);
3272                 break;
3273         case vxge_hw_mgmt_reg_type_toc:
3274                 if (offset > sizeof(struct vxge_hw_toc_reg) - 8) {
3275                         status = VXGE_HW_ERR_INVALID_OFFSET;
3276                         break;
3277                 }
3278                 writeq(value, (void __iomem *)hldev->toc_reg + offset);
3279                 break;
3280         case vxge_hw_mgmt_reg_type_common:
3281                 if (offset > sizeof(struct vxge_hw_common_reg) - 8) {
3282                         status = VXGE_HW_ERR_INVALID_OFFSET;
3283                         break;
3284                 }
3285                 writeq(value, (void __iomem *)hldev->common_reg + offset);
3286                 break;
3287         case vxge_hw_mgmt_reg_type_mrpcim:
3288                 if (!(hldev->access_rights &
3289                         VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) {
3290                         status = VXGE_HW_ERR_PRIVILAGED_OPEARATION;
3291                         break;
3292                 }
3293                 if (offset > sizeof(struct vxge_hw_mrpcim_reg) - 8) {
3294                         status = VXGE_HW_ERR_INVALID_OFFSET;
3295                         break;
3296                 }
3297                 writeq(value, (void __iomem *)hldev->mrpcim_reg + offset);
3298                 break;
3299         case vxge_hw_mgmt_reg_type_srpcim:
3300                 if (!(hldev->access_rights &
3301                         VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM)) {
3302                         status = VXGE_HW_ERR_PRIVILAGED_OPEARATION;
3303                         break;
3304                 }
3305                 if (index > VXGE_HW_TITAN_SRPCIM_REG_SPACES - 1) {
3306                         status = VXGE_HW_ERR_INVALID_INDEX;
3307                         break;
3308                 }
3309                 if (offset > sizeof(struct vxge_hw_srpcim_reg) - 8) {
3310                         status = VXGE_HW_ERR_INVALID_OFFSET;
3311                         break;
3312                 }
3313                 writeq(value, (void __iomem *)hldev->srpcim_reg[index] +
3314                         offset);
3315
3316                 break;
3317         case vxge_hw_mgmt_reg_type_vpmgmt:
3318                 if ((index > VXGE_HW_TITAN_VPMGMT_REG_SPACES - 1) ||
3319                         (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
3320                         status = VXGE_HW_ERR_INVALID_INDEX;
3321                         break;
3322                 }
3323                 if (offset > sizeof(struct vxge_hw_vpmgmt_reg) - 8) {
3324                         status = VXGE_HW_ERR_INVALID_OFFSET;
3325                         break;
3326                 }
3327                 writeq(value, (void __iomem *)hldev->vpmgmt_reg[index] +
3328                         offset);
3329                 break;
3330         case vxge_hw_mgmt_reg_type_vpath:
3331                 if ((index > VXGE_HW_TITAN_VPATH_REG_SPACES-1) ||
3332                         (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
3333                         status = VXGE_HW_ERR_INVALID_INDEX;
3334                         break;
3335                 }
3336                 if (offset > sizeof(struct vxge_hw_vpath_reg) - 8) {
3337                         status = VXGE_HW_ERR_INVALID_OFFSET;
3338                         break;
3339                 }
3340                 writeq(value, (void __iomem *)hldev->vpath_reg[index] +
3341                         offset);
3342                 break;
3343         default:
3344                 status = VXGE_HW_ERR_INVALID_TYPE;
3345                 break;
3346         }
3347 exit:
3348         return status;
3349 }
3350
3351 /*
3352  * __vxge_hw_fifo_abort - Returns the TxD
3353  * This function terminates the TxDs of fifo
3354  */
3355 static enum vxge_hw_status __vxge_hw_fifo_abort(struct __vxge_hw_fifo *fifo)
3356 {
3357         void *txdlh;
3358
3359         for (;;) {
3360                 vxge_hw_channel_dtr_try_complete(&fifo->channel, &txdlh);
3361
3362                 if (txdlh == NULL)
3363                         break;
3364
3365                 vxge_hw_channel_dtr_complete(&fifo->channel);
3366
3367                 if (fifo->txdl_term) {
3368                         fifo->txdl_term(txdlh,
3369                         VXGE_HW_TXDL_STATE_POSTED,
3370                         fifo->channel.userdata);
3371                 }
3372
3373                 vxge_hw_channel_dtr_free(&fifo->channel, txdlh);
3374         }
3375
3376         return VXGE_HW_OK;
3377 }
3378
3379 /*
3380  * __vxge_hw_fifo_reset - Resets the fifo
3381  * This function resets the fifo during vpath reset operation
3382  */
3383 static enum vxge_hw_status __vxge_hw_fifo_reset(struct __vxge_hw_fifo *fifo)
3384 {
3385         enum vxge_hw_status status = VXGE_HW_OK;
3386
3387         __vxge_hw_fifo_abort(fifo);
3388         status = __vxge_hw_channel_reset(&fifo->channel);
3389
3390         return status;
3391 }
3392
3393 /*
3394  * __vxge_hw_fifo_delete - Removes the FIFO
3395  * This function freeup the memory pool and removes the FIFO
3396  */
3397 static enum vxge_hw_status
3398 __vxge_hw_fifo_delete(struct __vxge_hw_vpath_handle *vp)
3399 {
3400         struct __vxge_hw_fifo *fifo = vp->vpath->fifoh;
3401
3402         __vxge_hw_fifo_abort(fifo);
3403
3404         if (fifo->mempool)
3405                 __vxge_hw_mempool_destroy(fifo->mempool);
3406
3407         vp->vpath->fifoh = NULL;
3408
3409         __vxge_hw_channel_free(&fifo->channel);
3410
3411         return VXGE_HW_OK;
3412 }
3413
3414 /*
3415  * __vxge_hw_fifo_mempool_item_alloc - Allocate List blocks for TxD
3416  * list callback
3417  * This function is callback passed to __vxge_hw_mempool_create to create memory
3418  * pool for TxD list
3419  */
3420 static void
3421 __vxge_hw_fifo_mempool_item_alloc(
3422         struct vxge_hw_mempool *mempoolh,
3423         u32 memblock_index, struct vxge_hw_mempool_dma *dma_object,
3424         u32 index, u32 is_last)
3425 {
3426         u32 memblock_item_idx;
3427         struct __vxge_hw_fifo_txdl_priv *txdl_priv;
3428         struct vxge_hw_fifo_txd *txdp =
3429                 (struct vxge_hw_fifo_txd *)mempoolh->items_arr[index];
3430         struct __vxge_hw_fifo *fifo =
3431                         (struct __vxge_hw_fifo *)mempoolh->userdata;
3432         void *memblock = mempoolh->memblocks_arr[memblock_index];
3433
3434         vxge_assert(txdp);
3435
3436         txdp->host_control = (u64) (size_t)
3437         __vxge_hw_mempool_item_priv(mempoolh, memblock_index, txdp,
3438                                         &memblock_item_idx);
3439
3440         txdl_priv = __vxge_hw_fifo_txdl_priv(fifo, txdp);
3441
3442         vxge_assert(txdl_priv);
3443
3444         fifo->channel.reserve_arr[fifo->channel.reserve_ptr - 1 - index] = txdp;
3445
3446         /* pre-format HW's TxDL's private */
3447         txdl_priv->dma_offset = (char *)txdp - (char *)memblock;
3448         txdl_priv->dma_addr = dma_object->addr + txdl_priv->dma_offset;
3449         txdl_priv->dma_handle = dma_object->handle;
3450         txdl_priv->memblock   = memblock;
3451         txdl_priv->first_txdp = txdp;
3452         txdl_priv->next_txdl_priv = NULL;
3453         txdl_priv->alloc_frags = 0;
3454 }
3455
3456 /*
3457  * __vxge_hw_fifo_create - Create a FIFO
3458  * This function creates FIFO and initializes it.
3459  */
3460 static enum vxge_hw_status
3461 __vxge_hw_fifo_create(struct __vxge_hw_vpath_handle *vp,
3462                       struct vxge_hw_fifo_attr *attr)
3463 {
3464         enum vxge_hw_status status = VXGE_HW_OK;
3465         struct __vxge_hw_fifo *fifo;
3466         struct vxge_hw_fifo_config *config;
3467         u32 txdl_size, txdl_per_memblock;
3468         struct vxge_hw_mempool_cbs fifo_mp_callback;
3469         struct __vxge_hw_virtualpath *vpath;
3470
3471         if ((vp == NULL) || (attr == NULL)) {
3472                 status = VXGE_HW_ERR_INVALID_HANDLE;
3473                 goto exit;
3474         }
3475         vpath = vp->vpath;
3476         config = &vpath->hldev->config.vp_config[vpath->vp_id].fifo;
3477
3478         txdl_size = config->max_frags * sizeof(struct vxge_hw_fifo_txd);
3479
3480         txdl_per_memblock = config->memblock_size / txdl_size;
3481
3482         fifo = (struct __vxge_hw_fifo *)__vxge_hw_channel_allocate(vp,
3483                                         VXGE_HW_CHANNEL_TYPE_FIFO,
3484                                         config->fifo_blocks * txdl_per_memblock,
3485                                         attr->per_txdl_space, attr->userdata);
3486
3487         if (fifo == NULL) {
3488                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
3489                 goto exit;
3490         }
3491
3492         vpath->fifoh = fifo;
3493         fifo->nofl_db = vpath->nofl_db;
3494
3495         fifo->vp_id = vpath->vp_id;
3496         fifo->vp_reg = vpath->vp_reg;
3497         fifo->stats = &vpath->sw_stats->fifo_stats;
3498
3499         fifo->config = config;
3500
3501         /* apply "interrupts per txdl" attribute */
3502         fifo->interrupt_type = VXGE_HW_FIFO_TXD_INT_TYPE_UTILZ;
3503         fifo->tim_tti_cfg1_saved = vpath->tim_tti_cfg1_saved;
3504         fifo->tim_tti_cfg3_saved = vpath->tim_tti_cfg3_saved;
3505
3506         if (fifo->config->intr)
3507                 fifo->interrupt_type = VXGE_HW_FIFO_TXD_INT_TYPE_PER_LIST;
3508
3509         fifo->no_snoop_bits = config->no_snoop_bits;
3510
3511         /*
3512          * FIFO memory management strategy:
3513          *
3514          * TxDL split into three independent parts:
3515          *      - set of TxD's
3516          *      - TxD HW private part
3517          *      - driver private part
3518          *
3519          * Adaptative memory allocation used. i.e. Memory allocated on
3520          * demand with the size which will fit into one memory block.
3521          * One memory block may contain more than one TxDL.
3522          *
3523          * During "reserve" operations more memory can be allocated on demand
3524          * for example due to FIFO full condition.
3525          *
3526          * Pool of memory memblocks never shrinks except in __vxge_hw_fifo_close
3527          * routine which will essentially stop the channel and free resources.
3528          */
3529
3530         /* TxDL common private size == TxDL private  +  driver private */
3531         fifo->priv_size =
3532                 sizeof(struct __vxge_hw_fifo_txdl_priv) + attr->per_txdl_space;
3533         fifo->priv_size = ((fifo->priv_size  +  VXGE_CACHE_LINE_SIZE - 1) /
3534                         VXGE_CACHE_LINE_SIZE) * VXGE_CACHE_LINE_SIZE;
3535
3536         fifo->per_txdl_space = attr->per_txdl_space;
3537
3538         /* recompute txdl size to be cacheline aligned */
3539         fifo->txdl_size = txdl_size;
3540         fifo->txdl_per_memblock = txdl_per_memblock;
3541
3542         fifo->txdl_term = attr->txdl_term;
3543         fifo->callback = attr->callback;
3544
3545         if (fifo->txdl_per_memblock == 0) {
3546                 __vxge_hw_fifo_delete(vp);
3547                 status = VXGE_HW_ERR_INVALID_BLOCK_SIZE;
3548                 goto exit;
3549         }
3550
3551         fifo_mp_callback.item_func_alloc = __vxge_hw_fifo_mempool_item_alloc;
3552
3553         fifo->mempool =
3554                 __vxge_hw_mempool_create(vpath->hldev,
3555                         fifo->config->memblock_size,
3556                         fifo->txdl_size,
3557                         fifo->priv_size,
3558                         (fifo->config->fifo_blocks * fifo->txdl_per_memblock),
3559                         (fifo->config->fifo_blocks * fifo->txdl_per_memblock),
3560                         &fifo_mp_callback,
3561                         fifo);
3562
3563         if (fifo->mempool == NULL) {
3564                 __vxge_hw_fifo_delete(vp);
3565                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
3566                 goto exit;
3567         }
3568
3569         status = __vxge_hw_channel_initialize(&fifo->channel);
3570         if (status != VXGE_HW_OK) {
3571                 __vxge_hw_fifo_delete(vp);
3572                 goto exit;
3573         }
3574
3575         vxge_assert(fifo->channel.reserve_ptr);
3576 exit:
3577         return status;
3578 }
3579
3580 /*
3581  * __vxge_hw_vpath_pci_read - Read the content of given address
3582  *                          in pci config space.
3583  * Read from the vpath pci config space.
3584  */
3585 static enum vxge_hw_status
3586 __vxge_hw_vpath_pci_read(struct __vxge_hw_virtualpath *vpath,
3587                          u32 phy_func_0, u32 offset, u32 *val)
3588 {
3589         u64 val64;
3590         enum vxge_hw_status status = VXGE_HW_OK;
3591         struct vxge_hw_vpath_reg __iomem *vp_reg = vpath->vp_reg;
3592
3593         val64 = VXGE_HW_PCI_CONFIG_ACCESS_CFG1_ADDRESS(offset);
3594
3595         if (phy_func_0)
3596                 val64 |= VXGE_HW_PCI_CONFIG_ACCESS_CFG1_SEL_FUNC0;
3597
3598         writeq(val64, &vp_reg->pci_config_access_cfg1);
3599         wmb();
3600         writeq(VXGE_HW_PCI_CONFIG_ACCESS_CFG2_REQ,
3601                         &vp_reg->pci_config_access_cfg2);
3602         wmb();
3603
3604         status = __vxge_hw_device_register_poll(
3605                         &vp_reg->pci_config_access_cfg2,
3606                         VXGE_HW_INTR_MASK_ALL, VXGE_HW_DEF_DEVICE_POLL_MILLIS);
3607
3608         if (status != VXGE_HW_OK)
3609                 goto exit;
3610
3611         val64 = readq(&vp_reg->pci_config_access_status);
3612
3613         if (val64 & VXGE_HW_PCI_CONFIG_ACCESS_STATUS_ACCESS_ERR) {
3614                 status = VXGE_HW_FAIL;
3615                 *val = 0;
3616         } else
3617                 *val = (u32)vxge_bVALn(val64, 32, 32);
3618 exit:
3619         return status;
3620 }
3621
3622 /**
3623  * vxge_hw_device_flick_link_led - Flick (blink) link LED.
3624  * @hldev: HW device.
3625  * @on_off: TRUE if flickering to be on, FALSE to be off
3626  *
3627  * Flicker the link LED.
3628  */
3629 enum vxge_hw_status
3630 vxge_hw_device_flick_link_led(struct __vxge_hw_device *hldev, u64 on_off)
3631 {
3632         struct __vxge_hw_virtualpath *vpath;
3633         u64 data0, data1 = 0, steer_ctrl = 0;
3634         enum vxge_hw_status status;
3635
3636         if (hldev == NULL) {
3637                 status = VXGE_HW_ERR_INVALID_DEVICE;
3638                 goto exit;
3639         }
3640
3641         vpath = &hldev->virtual_paths[hldev->first_vp_id];
3642
3643         data0 = on_off;
3644         status = vxge_hw_vpath_fw_api(vpath,
3645                         VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LED_CONTROL,
3646                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
3647                         0, &data0, &data1, &steer_ctrl);
3648 exit:
3649         return status;
3650 }
3651
3652 /*
3653  * __vxge_hw_vpath_rts_table_get - Get the entries from RTS access tables
3654  */
3655 enum vxge_hw_status
3656 __vxge_hw_vpath_rts_table_get(struct __vxge_hw_vpath_handle *vp,
3657                               u32 action, u32 rts_table, u32 offset,
3658                               u64 *data0, u64 *data1)
3659 {
3660         enum vxge_hw_status status;
3661         u64 steer_ctrl = 0;
3662
3663         if (vp == NULL) {
3664                 status = VXGE_HW_ERR_INVALID_HANDLE;
3665                 goto exit;
3666         }
3667
3668         if ((rts_table ==
3669              VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT) ||
3670             (rts_table ==
3671              VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT) ||
3672             (rts_table ==
3673              VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK) ||
3674             (rts_table ==
3675              VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY)) {
3676                 steer_ctrl = VXGE_HW_RTS_ACCESS_STEER_CTRL_TABLE_SEL;
3677         }
3678
3679         status = vxge_hw_vpath_fw_api(vp->vpath, action, rts_table, offset,
3680                                       data0, data1, &steer_ctrl);
3681         if (status != VXGE_HW_OK)
3682                 goto exit;
3683
3684         if ((rts_table != VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) &&
3685             (rts_table !=
3686              VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT))
3687                 *data1 = 0;
3688 exit:
3689         return status;
3690 }
3691
3692 /*
3693  * __vxge_hw_vpath_rts_table_set - Set the entries of RTS access tables
3694  */
3695 enum vxge_hw_status
3696 __vxge_hw_vpath_rts_table_set(struct __vxge_hw_vpath_handle *vp, u32 action,
3697                               u32 rts_table, u32 offset, u64 steer_data0,
3698                               u64 steer_data1)
3699 {
3700         u64 data0, data1 = 0, steer_ctrl = 0;
3701         enum vxge_hw_status status;
3702
3703         if (vp == NULL) {
3704                 status = VXGE_HW_ERR_INVALID_HANDLE;
3705                 goto exit;
3706         }
3707
3708         data0 = steer_data0;
3709
3710         if ((rts_table == VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) ||
3711             (rts_table ==
3712              VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT))
3713                 data1 = steer_data1;
3714
3715         status = vxge_hw_vpath_fw_api(vp->vpath, action, rts_table, offset,
3716                                       &data0, &data1, &steer_ctrl);
3717 exit:
3718         return status;
3719 }
3720
3721 /*
3722  * vxge_hw_vpath_rts_rth_set - Set/configure RTS hashing.
3723  */
3724 enum vxge_hw_status vxge_hw_vpath_rts_rth_set(
3725                         struct __vxge_hw_vpath_handle *vp,
3726                         enum vxge_hw_rth_algoritms algorithm,
3727                         struct vxge_hw_rth_hash_types *hash_type,
3728                         u16 bucket_size)
3729 {
3730         u64 data0, data1;
3731         enum vxge_hw_status status = VXGE_HW_OK;
3732
3733         if (vp == NULL) {
3734                 status = VXGE_HW_ERR_INVALID_HANDLE;
3735                 goto exit;
3736         }
3737
3738         status = __vxge_hw_vpath_rts_table_get(vp,
3739                      VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY,
3740                      VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG,
3741                         0, &data0, &data1);
3742         if (status != VXGE_HW_OK)
3743                 goto exit;
3744
3745         data0 &= ~(VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(0xf) |
3746                         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL(0x3));
3747
3748         data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_EN |
3749         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(bucket_size) |
3750         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL(algorithm);
3751
3752         if (hash_type->hash_type_tcpipv4_en)
3753                 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV4_EN;
3754
3755         if (hash_type->hash_type_ipv4_en)
3756                 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV4_EN;
3757
3758         if (hash_type->hash_type_tcpipv6_en)
3759                 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EN;
3760
3761         if (hash_type->hash_type_ipv6_en)
3762                 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EN;
3763
3764         if (hash_type->hash_type_tcpipv6ex_en)
3765                 data0 |=
3766                 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EX_EN;
3767
3768         if (hash_type->hash_type_ipv6ex_en)
3769                 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EX_EN;
3770
3771         if (VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ACTIVE_TABLE(data0))
3772                 data0 &= ~VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE;
3773         else
3774                 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE;
3775
3776         status = __vxge_hw_vpath_rts_table_set(vp,
3777                 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY,
3778                 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG,
3779                 0, data0, 0);
3780 exit:
3781         return status;
3782 }
3783
3784 static void
3785 vxge_hw_rts_rth_data0_data1_get(u32 j, u64 *data0, u64 *data1,
3786                                 u16 flag, u8 *itable)
3787 {
3788         switch (flag) {
3789         case 1:
3790                 *data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_NUM(j)|
3791                         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_ENTRY_EN |
3792                         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_DATA(
3793                         itable[j]);
3794         case 2:
3795                 *data0 |=
3796                         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_NUM(j)|
3797                         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_ENTRY_EN |
3798                         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_DATA(
3799                         itable[j]);
3800         case 3:
3801                 *data1 = VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_NUM(j)|
3802                         VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_ENTRY_EN |
3803                         VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_DATA(
3804                         itable[j]);
3805         case 4:
3806                 *data1 |=
3807                         VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_NUM(j)|
3808                         VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_ENTRY_EN |
3809                         VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_DATA(
3810                         itable[j]);
3811         default:
3812                 return;
3813         }
3814 }
3815 /*
3816  * vxge_hw_vpath_rts_rth_itable_set - Set/configure indirection table (IT).
3817  */
3818 enum vxge_hw_status vxge_hw_vpath_rts_rth_itable_set(
3819                         struct __vxge_hw_vpath_handle **vpath_handles,
3820                         u32 vpath_count,
3821                         u8 *mtable,
3822                         u8 *itable,
3823                         u32 itable_size)
3824 {
3825         u32 i, j, action, rts_table;
3826         u64 data0;
3827         u64 data1;
3828         u32 max_entries;
3829         enum vxge_hw_status status = VXGE_HW_OK;
3830         struct __vxge_hw_vpath_handle *vp = vpath_handles[0];
3831
3832         if (vp == NULL) {
3833                 status = VXGE_HW_ERR_INVALID_HANDLE;
3834                 goto exit;
3835         }
3836
3837         max_entries = (((u32)1) << itable_size);
3838
3839         if (vp->vpath->hldev->config.rth_it_type
3840                                 == VXGE_HW_RTH_IT_TYPE_SOLO_IT) {
3841                 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY;
3842                 rts_table =
3843                         VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT;
3844
3845                 for (j = 0; j < max_entries; j++) {
3846
3847                         data1 = 0;
3848
3849                         data0 =
3850                         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_BUCKET_DATA(
3851                                 itable[j]);
3852
3853                         status = __vxge_hw_vpath_rts_table_set(vpath_handles[0],
3854                                 action, rts_table, j, data0, data1);
3855
3856                         if (status != VXGE_HW_OK)
3857                                 goto exit;
3858                 }
3859
3860                 for (j = 0; j < max_entries; j++) {
3861
3862                         data1 = 0;
3863
3864                         data0 =
3865                         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_ENTRY_EN |
3866                         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_BUCKET_DATA(
3867                                 itable[j]);
3868
3869                         status = __vxge_hw_vpath_rts_table_set(
3870                                 vpath_handles[mtable[itable[j]]], action,
3871                                 rts_table, j, data0, data1);
3872
3873                         if (status != VXGE_HW_OK)
3874                                 goto exit;
3875                 }
3876         } else {
3877                 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY;
3878                 rts_table =
3879                         VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT;
3880                 for (i = 0; i < vpath_count; i++) {
3881
3882                         for (j = 0; j < max_entries;) {
3883
3884                                 data0 = 0;
3885                                 data1 = 0;
3886
3887                                 while (j < max_entries) {
3888                                         if (mtable[itable[j]] != i) {
3889                                                 j++;
3890                                                 continue;
3891                                         }
3892                                         vxge_hw_rts_rth_data0_data1_get(j,
3893                                                 &data0, &data1, 1, itable);
3894                                         j++;
3895                                         break;
3896                                 }
3897
3898                                 while (j < max_entries) {
3899                                         if (mtable[itable[j]] != i) {
3900                                                 j++;
3901                                                 continue;
3902                                         }
3903                                         vxge_hw_rts_rth_data0_data1_get(j,
3904                                                 &data0, &data1, 2, itable);
3905                                         j++;
3906                                         break;
3907                                 }
3908
3909                                 while (j < max_entries) {
3910                                         if (mtable[itable[j]] != i) {
3911                                                 j++;
3912                                                 continue;
3913                                         }
3914                                         vxge_hw_rts_rth_data0_data1_get(j,
3915                                                 &data0, &data1, 3, itable);
3916                                         j++;
3917                                         break;
3918                                 }
3919
3920                                 while (j < max_entries) {
3921                                         if (mtable[itable[j]] != i) {
3922                                                 j++;
3923                                                 continue;
3924                                         }
3925                                         vxge_hw_rts_rth_data0_data1_get(j,
3926                                                 &data0, &data1, 4, itable);
3927                                         j++;
3928                                         break;
3929                                 }
3930
3931                                 if (data0 != 0) {
3932                                         status = __vxge_hw_vpath_rts_table_set(
3933                                                         vpath_handles[i],
3934                                                         action, rts_table,
3935                                                         0, data0, data1);
3936
3937                                         if (status != VXGE_HW_OK)
3938                                                 goto exit;
3939                                 }
3940                         }
3941                 }
3942         }
3943 exit:
3944         return status;
3945 }
3946
3947 /**
3948  * vxge_hw_vpath_check_leak - Check for memory leak
3949  * @ringh: Handle to the ring object used for receive
3950  *
3951  * If PRC_RXD_DOORBELL_VPn.NEW_QW_CNT is larger or equal to
3952  * PRC_CFG6_VPn.RXD_SPAT then a leak has occurred.
3953  * Returns: VXGE_HW_FAIL, if leak has occurred.
3954  *
3955  */
3956 enum vxge_hw_status
3957 vxge_hw_vpath_check_leak(struct __vxge_hw_ring *ring)
3958 {
3959         enum vxge_hw_status status = VXGE_HW_OK;
3960         u64 rxd_new_count, rxd_spat;
3961
3962         if (ring == NULL)
3963                 return status;
3964
3965         rxd_new_count = readl(&ring->vp_reg->prc_rxd_doorbell);
3966         rxd_spat = readq(&ring->vp_reg->prc_cfg6);
3967         rxd_spat = VXGE_HW_PRC_CFG6_RXD_SPAT(rxd_spat);
3968
3969         if (rxd_new_count >= rxd_spat)
3970                 status = VXGE_HW_FAIL;
3971
3972         return status;
3973 }
3974
3975 /*
3976  * __vxge_hw_vpath_mgmt_read
3977  * This routine reads the vpath_mgmt registers
3978  */
3979 static enum vxge_hw_status
3980 __vxge_hw_vpath_mgmt_read(
3981         struct __vxge_hw_device *hldev,
3982         struct __vxge_hw_virtualpath *vpath)
3983 {
3984         u32 i, mtu = 0, max_pyld = 0;
3985         u64 val64;
3986         enum vxge_hw_status status = VXGE_HW_OK;
3987
3988         for (i = 0; i < VXGE_HW_MAC_MAX_MAC_PORT_ID; i++) {
3989
3990                 val64 = readq(&vpath->vpmgmt_reg->
3991                                 rxmac_cfg0_port_vpmgmt_clone[i]);
3992                 max_pyld =
3993                         (u32)
3994                         VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_GET_MAX_PYLD_LEN
3995                         (val64);
3996                 if (mtu < max_pyld)
3997                         mtu = max_pyld;
3998         }
3999
4000         vpath->max_mtu = mtu + VXGE_HW_MAC_HEADER_MAX_SIZE;
4001
4002         val64 = readq(&vpath->vpmgmt_reg->xmac_vsport_choices_vp);
4003
4004         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
4005                 if (val64 & vxge_mBIT(i))
4006                         vpath->vsport_number = i;
4007         }
4008
4009         val64 = readq(&vpath->vpmgmt_reg->xgmac_gen_status_vpmgmt_clone);
4010
4011         if (val64 & VXGE_HW_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_OK)
4012                 VXGE_HW_DEVICE_LINK_STATE_SET(vpath->hldev, VXGE_HW_LINK_UP);
4013         else
4014                 VXGE_HW_DEVICE_LINK_STATE_SET(vpath->hldev, VXGE_HW_LINK_DOWN);
4015
4016         return status;
4017 }
4018
4019 /*
4020  * __vxge_hw_vpath_reset_check - Check if resetting the vpath completed
4021  * This routine checks the vpath_rst_in_prog register to see if
4022  * adapter completed the reset process for the vpath
4023  */
4024 static enum vxge_hw_status
4025 __vxge_hw_vpath_reset_check(struct __vxge_hw_virtualpath *vpath)
4026 {
4027         enum vxge_hw_status status;
4028
4029         status = __vxge_hw_device_register_poll(
4030                         &vpath->hldev->common_reg->vpath_rst_in_prog,
4031                         VXGE_HW_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG(
4032                                 1 << (16 - vpath->vp_id)),
4033                         vpath->hldev->config.device_poll_millis);
4034
4035         return status;
4036 }
4037
4038 /*
4039  * __vxge_hw_vpath_reset
4040  * This routine resets the vpath on the device
4041  */
4042 static enum vxge_hw_status
4043 __vxge_hw_vpath_reset(struct __vxge_hw_device *hldev, u32 vp_id)
4044 {
4045         u64 val64;
4046         enum vxge_hw_status status = VXGE_HW_OK;
4047
4048         val64 = VXGE_HW_CMN_RSTHDLR_CFG0_SW_RESET_VPATH(1 << (16 - vp_id));
4049
4050         __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32),
4051                                 &hldev->common_reg->cmn_rsthdlr_cfg0);
4052
4053         return status;
4054 }
4055
4056 /*
4057  * __vxge_hw_vpath_sw_reset
4058  * This routine resets the vpath structures
4059  */
4060 static enum vxge_hw_status
4061 __vxge_hw_vpath_sw_reset(struct __vxge_hw_device *hldev, u32 vp_id)
4062 {
4063         enum vxge_hw_status status = VXGE_HW_OK;
4064         struct __vxge_hw_virtualpath *vpath;
4065
4066         vpath = (struct __vxge_hw_virtualpath *)&hldev->virtual_paths[vp_id];
4067
4068         if (vpath->ringh) {
4069                 status = __vxge_hw_ring_reset(vpath->ringh);
4070                 if (status != VXGE_HW_OK)
4071                         goto exit;
4072         }
4073
4074         if (vpath->fifoh)
4075                 status = __vxge_hw_fifo_reset(vpath->fifoh);
4076 exit:
4077         return status;
4078 }
4079
4080 /*
4081  * __vxge_hw_vpath_prc_configure
4082  * This routine configures the prc registers of virtual path using the config
4083  * passed
4084  */
4085 static void
4086 __vxge_hw_vpath_prc_configure(struct __vxge_hw_device *hldev, u32 vp_id)
4087 {
4088         u64 val64;
4089         struct __vxge_hw_virtualpath *vpath;
4090         struct vxge_hw_vp_config *vp_config;
4091         struct vxge_hw_vpath_reg __iomem *vp_reg;
4092
4093         vpath = &hldev->virtual_paths[vp_id];
4094         vp_reg = vpath->vp_reg;
4095         vp_config = vpath->vp_config;
4096
4097         if (vp_config->ring.enable == VXGE_HW_RING_DISABLE)
4098                 return;
4099
4100         val64 = readq(&vp_reg->prc_cfg1);
4101         val64 |= VXGE_HW_PRC_CFG1_RTI_TINT_DISABLE;
4102         writeq(val64, &vp_reg->prc_cfg1);
4103
4104         val64 = readq(&vpath->vp_reg->prc_cfg6);
4105         val64 |= VXGE_HW_PRC_CFG6_DOORBELL_MODE_EN;
4106         writeq(val64, &vpath->vp_reg->prc_cfg6);
4107
4108         val64 = readq(&vp_reg->prc_cfg7);
4109
4110         if (vpath->vp_config->ring.scatter_mode !=
4111                 VXGE_HW_RING_SCATTER_MODE_USE_FLASH_DEFAULT) {
4112
4113                 val64 &= ~VXGE_HW_PRC_CFG7_SCATTER_MODE(0x3);
4114
4115                 switch (vpath->vp_config->ring.scatter_mode) {
4116                 case VXGE_HW_RING_SCATTER_MODE_A:
4117                         val64 |= VXGE_HW_PRC_CFG7_SCATTER_MODE(
4118                                         VXGE_HW_PRC_CFG7_SCATTER_MODE_A);
4119                         break;
4120                 case VXGE_HW_RING_SCATTER_MODE_B:
4121                         val64 |= VXGE_HW_PRC_CFG7_SCATTER_MODE(
4122                                         VXGE_HW_PRC_CFG7_SCATTER_MODE_B);
4123                         break;
4124                 case VXGE_HW_RING_SCATTER_MODE_C:
4125                         val64 |= VXGE_HW_PRC_CFG7_SCATTER_MODE(
4126                                         VXGE_HW_PRC_CFG7_SCATTER_MODE_C);
4127                         break;
4128                 }
4129         }
4130
4131         writeq(val64, &vp_reg->prc_cfg7);
4132
4133         writeq(VXGE_HW_PRC_CFG5_RXD0_ADD(
4134                                 __vxge_hw_ring_first_block_address_get(
4135                                         vpath->ringh) >> 3), &vp_reg->prc_cfg5);
4136
4137         val64 = readq(&vp_reg->prc_cfg4);
4138         val64 |= VXGE_HW_PRC_CFG4_IN_SVC;
4139         val64 &= ~VXGE_HW_PRC_CFG4_RING_MODE(0x3);
4140
4141         val64 |= VXGE_HW_PRC_CFG4_RING_MODE(
4142                         VXGE_HW_PRC_CFG4_RING_MODE_ONE_BUFFER);
4143
4144         if (hldev->config.rth_en == VXGE_HW_RTH_DISABLE)
4145                 val64 |= VXGE_HW_PRC_CFG4_RTH_DISABLE;
4146         else
4147                 val64 &= ~VXGE_HW_PRC_CFG4_RTH_DISABLE;
4148
4149         writeq(val64, &vp_reg->prc_cfg4);
4150 }
4151
4152 /*
4153  * __vxge_hw_vpath_kdfc_configure
4154  * This routine configures the kdfc registers of virtual path using the
4155  * config passed
4156  */
4157 static enum vxge_hw_status
4158 __vxge_hw_vpath_kdfc_configure(struct __vxge_hw_device *hldev, u32 vp_id)
4159 {
4160         u64 val64;
4161         u64 vpath_stride;
4162         enum vxge_hw_status status = VXGE_HW_OK;
4163         struct __vxge_hw_virtualpath *vpath;
4164         struct vxge_hw_vpath_reg __iomem *vp_reg;
4165
4166         vpath = &hldev->virtual_paths[vp_id];
4167         vp_reg = vpath->vp_reg;
4168         status = __vxge_hw_kdfc_swapper_set(hldev->legacy_reg, vp_reg);
4169
4170         if (status != VXGE_HW_OK)
4171                 goto exit;
4172
4173         val64 = readq(&vp_reg->kdfc_drbl_triplet_total);
4174
4175         vpath->max_kdfc_db =
4176                 (u32)VXGE_HW_KDFC_DRBL_TRIPLET_TOTAL_GET_KDFC_MAX_SIZE(
4177                         val64+1)/2;
4178
4179         if (vpath->vp_config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
4180
4181                 vpath->max_nofl_db = vpath->max_kdfc_db;
4182
4183                 if (vpath->max_nofl_db <
4184                         ((vpath->vp_config->fifo.memblock_size /
4185                         (vpath->vp_config->fifo.max_frags *
4186                         sizeof(struct vxge_hw_fifo_txd))) *
4187                         vpath->vp_config->fifo.fifo_blocks)) {
4188
4189                         return VXGE_HW_BADCFG_FIFO_BLOCKS;
4190                 }
4191                 val64 = VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_0(
4192                                 (vpath->max_nofl_db*2)-1);
4193         }
4194
4195         writeq(val64, &vp_reg->kdfc_fifo_trpl_partition);
4196
4197         writeq(VXGE_HW_KDFC_FIFO_TRPL_CTRL_TRIPLET_ENABLE,
4198                 &vp_reg->kdfc_fifo_trpl_ctrl);
4199
4200         val64 = readq(&vp_reg->kdfc_trpl_fifo_0_ctrl);
4201
4202         val64 &= ~(VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE(0x3) |
4203                    VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(0xFF));
4204
4205         val64 |= VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE(
4206                  VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_NON_OFFLOAD_ONLY) |
4207 #ifndef __BIG_ENDIAN
4208                  VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SWAP_EN |
4209 #endif
4210                  VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(0);
4211
4212         writeq(val64, &vp_reg->kdfc_trpl_fifo_0_ctrl);
4213         writeq((u64)0, &vp_reg->kdfc_trpl_fifo_0_wb_address);
4214         wmb();
4215         vpath_stride = readq(&hldev->toc_reg->toc_kdfc_vpath_stride);
4216
4217         vpath->nofl_db =
4218                 (struct __vxge_hw_non_offload_db_wrapper __iomem *)
4219                 (hldev->kdfc + (vp_id *
4220                 VXGE_HW_TOC_KDFC_VPATH_STRIDE_GET_TOC_KDFC_VPATH_STRIDE(
4221                                         vpath_stride)));
4222 exit:
4223         return status;
4224 }
4225
4226 /*
4227  * __vxge_hw_vpath_mac_configure
4228  * This routine configures the mac of virtual path using the config passed
4229  */
4230 static enum vxge_hw_status
4231 __vxge_hw_vpath_mac_configure(struct __vxge_hw_device *hldev, u32 vp_id)
4232 {
4233         u64 val64;
4234         enum vxge_hw_status status = VXGE_HW_OK;
4235         struct __vxge_hw_virtualpath *vpath;
4236         struct vxge_hw_vp_config *vp_config;
4237         struct vxge_hw_vpath_reg __iomem *vp_reg;
4238
4239         vpath = &hldev->virtual_paths[vp_id];
4240         vp_reg = vpath->vp_reg;
4241         vp_config = vpath->vp_config;
4242
4243         writeq(VXGE_HW_XMAC_VSPORT_CHOICE_VSPORT_NUMBER(
4244                         vpath->vsport_number), &vp_reg->xmac_vsport_choice);
4245
4246         if (vp_config->ring.enable == VXGE_HW_RING_ENABLE) {
4247
4248                 val64 = readq(&vp_reg->xmac_rpa_vcfg);
4249
4250                 if (vp_config->rpa_strip_vlan_tag !=
4251                         VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT) {
4252                         if (vp_config->rpa_strip_vlan_tag)
4253                                 val64 |= VXGE_HW_XMAC_RPA_VCFG_STRIP_VLAN_TAG;
4254                         else
4255                                 val64 &= ~VXGE_HW_XMAC_RPA_VCFG_STRIP_VLAN_TAG;
4256                 }
4257
4258                 writeq(val64, &vp_reg->xmac_rpa_vcfg);
4259                 val64 = readq(&vp_reg->rxmac_vcfg0);
4260
4261                 if (vp_config->mtu !=
4262                                 VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU) {
4263                         val64 &= ~VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
4264                         if ((vp_config->mtu  +
4265                                 VXGE_HW_MAC_HEADER_MAX_SIZE) < vpath->max_mtu)
4266                                 val64 |= VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(
4267                                         vp_config->mtu  +
4268                                         VXGE_HW_MAC_HEADER_MAX_SIZE);
4269                         else
4270                                 val64 |= VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(
4271                                         vpath->max_mtu);
4272                 }
4273
4274                 writeq(val64, &vp_reg->rxmac_vcfg0);
4275
4276                 val64 = readq(&vp_reg->rxmac_vcfg1);
4277
4278                 val64 &= ~(VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(0x3) |
4279                         VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE);
4280
4281                 if (hldev->config.rth_it_type ==
4282                                 VXGE_HW_RTH_IT_TYPE_MULTI_IT) {
4283                         val64 |= VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(
4284                                 0x2) |
4285                                 VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE;
4286                 }
4287
4288                 writeq(val64, &vp_reg->rxmac_vcfg1);
4289         }
4290         return status;
4291 }
4292
4293 /*
4294  * __vxge_hw_vpath_tim_configure
4295  * This routine configures the tim registers of virtual path using the config
4296  * passed
4297  */
4298 static enum vxge_hw_status
4299 __vxge_hw_vpath_tim_configure(struct __vxge_hw_device *hldev, u32 vp_id)
4300 {
4301         u64 val64;
4302         enum vxge_hw_status status = VXGE_HW_OK;
4303         struct __vxge_hw_virtualpath *vpath;
4304         struct vxge_hw_vpath_reg __iomem *vp_reg;
4305         struct vxge_hw_vp_config *config;
4306
4307         vpath = &hldev->virtual_paths[vp_id];
4308         vp_reg = vpath->vp_reg;
4309         config = vpath->vp_config;
4310
4311         writeq(0, &vp_reg->tim_dest_addr);
4312         writeq(0, &vp_reg->tim_vpath_map);
4313         writeq(0, &vp_reg->tim_bitmap);
4314         writeq(0, &vp_reg->tim_remap);
4315
4316         if (config->ring.enable == VXGE_HW_RING_ENABLE)
4317                 writeq(VXGE_HW_TIM_RING_ASSN_INT_NUM(
4318                         (vp_id * VXGE_HW_MAX_INTR_PER_VP) +
4319                         VXGE_HW_VPATH_INTR_RX), &vp_reg->tim_ring_assn);
4320
4321         val64 = readq(&vp_reg->tim_pci_cfg);
4322         val64 |= VXGE_HW_TIM_PCI_CFG_ADD_PAD;
4323         writeq(val64, &vp_reg->tim_pci_cfg);
4324
4325         if (config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
4326
4327                 val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
4328
4329                 if (config->tti.btimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4330                         val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
4331                                 0x3ffffff);
4332                         val64 |= VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
4333                                         config->tti.btimer_val);
4334                 }
4335
4336                 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BITMP_EN;
4337
4338                 if (config->tti.timer_ac_en != VXGE_HW_USE_FLASH_DEFAULT) {
4339                         if (config->tti.timer_ac_en)
4340                                 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
4341                         else
4342                                 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
4343                 }
4344
4345                 if (config->tti.timer_ci_en != VXGE_HW_USE_FLASH_DEFAULT) {
4346                         if (config->tti.timer_ci_en)
4347                                 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
4348                         else
4349                                 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
4350                 }
4351
4352                 if (config->tti.urange_a != VXGE_HW_USE_FLASH_DEFAULT) {
4353                         val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(0x3f);
4354                         val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(
4355                                         config->tti.urange_a);
4356                 }
4357
4358                 if (config->tti.urange_b != VXGE_HW_USE_FLASH_DEFAULT) {
4359                         val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(0x3f);
4360                         val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(
4361                                         config->tti.urange_b);
4362                 }
4363
4364                 if (config->tti.urange_c != VXGE_HW_USE_FLASH_DEFAULT) {
4365                         val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(0x3f);
4366                         val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(
4367                                         config->tti.urange_c);
4368                 }
4369
4370                 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
4371                 vpath->tim_tti_cfg1_saved = val64;
4372
4373                 val64 = readq(&vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]);
4374
4375                 if (config->tti.uec_a != VXGE_HW_USE_FLASH_DEFAULT) {
4376                         val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(0xffff);
4377                         val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(
4378                                                 config->tti.uec_a);
4379                 }
4380
4381                 if (config->tti.uec_b != VXGE_HW_USE_FLASH_DEFAULT) {
4382                         val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(0xffff);
4383                         val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(
4384                                                 config->tti.uec_b);
4385                 }
4386
4387                 if (config->tti.uec_c != VXGE_HW_USE_FLASH_DEFAULT) {
4388                         val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(0xffff);
4389                         val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(
4390                                                 config->tti.uec_c);
4391                 }
4392
4393                 if (config->tti.uec_d != VXGE_HW_USE_FLASH_DEFAULT) {
4394                         val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(0xffff);
4395                         val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(
4396                                                 config->tti.uec_d);
4397                 }
4398
4399                 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]);
4400                 val64 = readq(&vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]);
4401
4402                 if (config->tti.timer_ri_en != VXGE_HW_USE_FLASH_DEFAULT) {
4403                         if (config->tti.timer_ri_en)
4404                                 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
4405                         else
4406                                 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
4407                 }
4408
4409                 if (config->tti.rtimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4410                         val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
4411                                         0x3ffffff);
4412                         val64 |= VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
4413                                         config->tti.rtimer_val);
4414                 }
4415
4416                 if (config->tti.util_sel != VXGE_HW_USE_FLASH_DEFAULT) {
4417                         val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(0x3f);
4418                         val64 |= VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(vp_id);
4419                 }
4420
4421                 if (config->tti.ltimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4422                         val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
4423                                         0x3ffffff);
4424                         val64 |= VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
4425                                         config->tti.ltimer_val);
4426                 }
4427
4428                 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]);
4429                 vpath->tim_tti_cfg3_saved = val64;
4430         }
4431
4432         if (config->ring.enable == VXGE_HW_RING_ENABLE) {
4433
4434                 val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]);
4435
4436                 if (config->rti.btimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4437                         val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
4438                                         0x3ffffff);
4439                         val64 |= VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
4440                                         config->rti.btimer_val);
4441                 }
4442
4443                 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BITMP_EN;
4444
4445                 if (config->rti.timer_ac_en != VXGE_HW_USE_FLASH_DEFAULT) {
4446                         if (config->rti.timer_ac_en)
4447                                 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
4448                         else
4449                                 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
4450                 }
4451
4452                 if (config->rti.timer_ci_en != VXGE_HW_USE_FLASH_DEFAULT) {
4453                         if (config->rti.timer_ci_en)
4454                                 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
4455                         else
4456                                 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
4457                 }
4458
4459                 if (config->rti.urange_a != VXGE_HW_USE_FLASH_DEFAULT) {
4460                         val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(0x3f);
4461                         val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(
4462                                         config->rti.urange_a);
4463                 }
4464
4465                 if (config->rti.urange_b != VXGE_HW_USE_FLASH_DEFAULT) {
4466                         val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(0x3f);
4467                         val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(
4468                                         config->rti.urange_b);
4469                 }
4470
4471                 if (config->rti.urange_c != VXGE_HW_USE_FLASH_DEFAULT) {
4472                         val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(0x3f);
4473                         val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(
4474                                         config->rti.urange_c);
4475                 }
4476
4477                 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]);
4478                 vpath->tim_rti_cfg1_saved = val64;
4479
4480                 val64 = readq(&vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]);
4481
4482                 if (config->rti.uec_a != VXGE_HW_USE_FLASH_DEFAULT) {
4483                         val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(0xffff);
4484                         val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(
4485                                                 config->rti.uec_a);
4486                 }
4487
4488                 if (config->rti.uec_b != VXGE_HW_USE_FLASH_DEFAULT) {
4489                         val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(0xffff);
4490                         val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(
4491                                                 config->rti.uec_b);
4492                 }
4493
4494                 if (config->rti.uec_c != VXGE_HW_USE_FLASH_DEFAULT) {
4495                         val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(0xffff);
4496                         val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(
4497                                                 config->rti.uec_c);
4498                 }
4499
4500                 if (config->rti.uec_d != VXGE_HW_USE_FLASH_DEFAULT) {
4501                         val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(0xffff);
4502                         val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(
4503                                                 config->rti.uec_d);
4504                 }
4505
4506                 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]);
4507                 val64 = readq(&vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]);
4508
4509                 if (config->rti.timer_ri_en != VXGE_HW_USE_FLASH_DEFAULT) {
4510                         if (config->rti.timer_ri_en)
4511                                 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
4512                         else
4513                                 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
4514                 }
4515
4516                 if (config->rti.rtimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4517                         val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
4518                                         0x3ffffff);
4519                         val64 |= VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
4520                                         config->rti.rtimer_val);
4521                 }
4522
4523                 if (config->rti.util_sel != VXGE_HW_USE_FLASH_DEFAULT) {
4524                         val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(0x3f);
4525                         val64 |= VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(vp_id);
4526                 }
4527
4528                 if (config->rti.ltimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4529                         val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
4530                                         0x3ffffff);
4531                         val64 |= VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
4532                                         config->rti.ltimer_val);
4533                 }
4534
4535                 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]);
4536                 vpath->tim_rti_cfg3_saved = val64;
4537         }
4538
4539         val64 = 0;
4540         writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_EINTA]);
4541         writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_EINTA]);
4542         writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_EINTA]);
4543         writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_BMAP]);
4544         writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_BMAP]);
4545         writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_BMAP]);
4546
4547         val64 = VXGE_HW_TIM_WRKLD_CLC_WRKLD_EVAL_PRD(150);
4548         val64 |= VXGE_HW_TIM_WRKLD_CLC_WRKLD_EVAL_DIV(0);
4549         val64 |= VXGE_HW_TIM_WRKLD_CLC_CNT_RX_TX(3);
4550         writeq(val64, &vp_reg->tim_wrkld_clc);
4551
4552         return status;
4553 }
4554
4555 /*
4556  * __vxge_hw_vpath_initialize
4557  * This routine is the final phase of init which initializes the
4558  * registers of the vpath using the configuration passed.
4559  */
4560 static enum vxge_hw_status
4561 __vxge_hw_vpath_initialize(struct __vxge_hw_device *hldev, u32 vp_id)
4562 {
4563         u64 val64;
4564         u32 val32;
4565         enum vxge_hw_status status = VXGE_HW_OK;
4566         struct __vxge_hw_virtualpath *vpath;
4567         struct vxge_hw_vpath_reg __iomem *vp_reg;
4568
4569         vpath = &hldev->virtual_paths[vp_id];
4570
4571         if (!(hldev->vpath_assignments & vxge_mBIT(vp_id))) {
4572                 status = VXGE_HW_ERR_VPATH_NOT_AVAILABLE;
4573                 goto exit;
4574         }
4575         vp_reg = vpath->vp_reg;
4576
4577         status =  __vxge_hw_vpath_swapper_set(vpath->vp_reg);
4578         if (status != VXGE_HW_OK)
4579                 goto exit;
4580
4581         status =  __vxge_hw_vpath_mac_configure(hldev, vp_id);
4582         if (status != VXGE_HW_OK)
4583                 goto exit;
4584
4585         status =  __vxge_hw_vpath_kdfc_configure(hldev, vp_id);
4586         if (status != VXGE_HW_OK)
4587                 goto exit;
4588
4589         status = __vxge_hw_vpath_tim_configure(hldev, vp_id);
4590         if (status != VXGE_HW_OK)
4591                 goto exit;
4592
4593         val64 = readq(&vp_reg->rtdma_rd_optimization_ctrl);
4594
4595         /* Get MRRS value from device control */
4596         status  = __vxge_hw_vpath_pci_read(vpath, 1, 0x78, &val32);
4597         if (status == VXGE_HW_OK) {
4598                 val32 = (val32 & VXGE_HW_PCI_EXP_DEVCTL_READRQ) >> 12;
4599                 val64 &=
4600                     ~(VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(7));
4601                 val64 |=
4602                     VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(val32);
4603
4604                 val64 |= VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_WAIT_FOR_SPACE;
4605         }
4606
4607         val64 &= ~(VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY(7));
4608         val64 |=
4609             VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY(
4610                     VXGE_HW_MAX_PAYLOAD_SIZE_512);
4611
4612         val64 |= VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY_EN;
4613         writeq(val64, &vp_reg->rtdma_rd_optimization_ctrl);
4614
4615 exit:
4616         return status;
4617 }
4618
4619 /*
4620  * __vxge_hw_vp_terminate - Terminate Virtual Path structure
4621  * This routine closes all channels it opened and freeup memory
4622  */
4623 static void __vxge_hw_vp_terminate(struct __vxge_hw_device *hldev, u32 vp_id)
4624 {
4625         struct __vxge_hw_virtualpath *vpath;
4626
4627         vpath = &hldev->virtual_paths[vp_id];
4628
4629         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN)
4630                 goto exit;
4631
4632         VXGE_HW_DEVICE_TIM_INT_MASK_RESET(vpath->hldev->tim_int_mask0,
4633                 vpath->hldev->tim_int_mask1, vpath->vp_id);
4634         hldev->stats.hw_dev_info_stats.vpath_info[vpath->vp_id] = NULL;
4635
4636         /* If the whole struct __vxge_hw_virtualpath is zeroed, nothing will
4637          * work after the interface is brought down.
4638          */
4639         spin_lock(&vpath->lock);
4640         vpath->vp_open = VXGE_HW_VP_NOT_OPEN;
4641         spin_unlock(&vpath->lock);
4642
4643         vpath->vpmgmt_reg = NULL;
4644         vpath->nofl_db = NULL;
4645         vpath->max_mtu = 0;
4646         vpath->vsport_number = 0;
4647         vpath->max_kdfc_db = 0;
4648         vpath->max_nofl_db = 0;
4649         vpath->ringh = NULL;
4650         vpath->fifoh = NULL;
4651         memset(&vpath->vpath_handles, 0, sizeof(struct list_head));
4652         vpath->stats_block = 0;
4653         vpath->hw_stats = NULL;
4654         vpath->hw_stats_sav = NULL;
4655         vpath->sw_stats = NULL;
4656
4657 exit:
4658         return;
4659 }
4660
4661 /*
4662  * __vxge_hw_vp_initialize - Initialize Virtual Path structure
4663  * This routine is the initial phase of init which resets the vpath and
4664  * initializes the software support structures.
4665  */
4666 static enum vxge_hw_status
4667 __vxge_hw_vp_initialize(struct __vxge_hw_device *hldev, u32 vp_id,
4668                         struct vxge_hw_vp_config *config)
4669 {
4670         struct __vxge_hw_virtualpath *vpath;
4671         enum vxge_hw_status status = VXGE_HW_OK;
4672
4673         if (!(hldev->vpath_assignments & vxge_mBIT(vp_id))) {
4674                 status = VXGE_HW_ERR_VPATH_NOT_AVAILABLE;
4675                 goto exit;
4676         }
4677
4678         vpath = &hldev->virtual_paths[vp_id];
4679
4680         spin_lock_init(&vpath->lock);
4681         vpath->vp_id = vp_id;
4682         vpath->vp_open = VXGE_HW_VP_OPEN;
4683         vpath->hldev = hldev;
4684         vpath->vp_config = config;
4685         vpath->vp_reg = hldev->vpath_reg[vp_id];
4686         vpath->vpmgmt_reg = hldev->vpmgmt_reg[vp_id];
4687
4688         __vxge_hw_vpath_reset(hldev, vp_id);
4689
4690         status = __vxge_hw_vpath_reset_check(vpath);
4691         if (status != VXGE_HW_OK) {
4692                 memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath));
4693                 goto exit;
4694         }
4695
4696         status = __vxge_hw_vpath_mgmt_read(hldev, vpath);
4697         if (status != VXGE_HW_OK) {
4698                 memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath));
4699                 goto exit;
4700         }
4701
4702         INIT_LIST_HEAD(&vpath->vpath_handles);
4703
4704         vpath->sw_stats = &hldev->stats.sw_dev_info_stats.vpath_info[vp_id];
4705
4706         VXGE_HW_DEVICE_TIM_INT_MASK_SET(hldev->tim_int_mask0,
4707                 hldev->tim_int_mask1, vp_id);
4708
4709         status = __vxge_hw_vpath_initialize(hldev, vp_id);
4710         if (status != VXGE_HW_OK)
4711                 __vxge_hw_vp_terminate(hldev, vp_id);
4712 exit:
4713         return status;
4714 }
4715
4716 /*
4717  * vxge_hw_vpath_mtu_set - Set MTU.
4718  * Set new MTU value. Example, to use jumbo frames:
4719  * vxge_hw_vpath_mtu_set(my_device, 9600);
4720  */
4721 enum vxge_hw_status
4722 vxge_hw_vpath_mtu_set(struct __vxge_hw_vpath_handle *vp, u32 new_mtu)
4723 {
4724         u64 val64;
4725         enum vxge_hw_status status = VXGE_HW_OK;
4726         struct __vxge_hw_virtualpath *vpath;
4727
4728         if (vp == NULL) {
4729                 status = VXGE_HW_ERR_INVALID_HANDLE;
4730                 goto exit;
4731         }
4732         vpath = vp->vpath;
4733
4734         new_mtu += VXGE_HW_MAC_HEADER_MAX_SIZE;
4735
4736         if ((new_mtu < VXGE_HW_MIN_MTU) || (new_mtu > vpath->max_mtu))
4737                 status = VXGE_HW_ERR_INVALID_MTU_SIZE;
4738
4739         val64 = readq(&vpath->vp_reg->rxmac_vcfg0);
4740
4741         val64 &= ~VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
4742         val64 |= VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(new_mtu);
4743
4744         writeq(val64, &vpath->vp_reg->rxmac_vcfg0);
4745
4746         vpath->vp_config->mtu = new_mtu - VXGE_HW_MAC_HEADER_MAX_SIZE;
4747
4748 exit:
4749         return status;
4750 }
4751
4752 /*
4753  * vxge_hw_vpath_stats_enable - Enable vpath h/wstatistics.
4754  * Enable the DMA vpath statistics. The function is to be called to re-enable
4755  * the adapter to update stats into the host memory
4756  */
4757 static enum vxge_hw_status
4758 vxge_hw_vpath_stats_enable(struct __vxge_hw_vpath_handle *vp)
4759 {
4760         enum vxge_hw_status status = VXGE_HW_OK;
4761         struct __vxge_hw_virtualpath *vpath;
4762
4763         vpath = vp->vpath;
4764
4765         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4766                 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4767                 goto exit;
4768         }
4769
4770         memcpy(vpath->hw_stats_sav, vpath->hw_stats,
4771                         sizeof(struct vxge_hw_vpath_stats_hw_info));
4772
4773         status = __vxge_hw_vpath_stats_get(vpath, vpath->hw_stats);
4774 exit:
4775         return status;
4776 }
4777
4778 /*
4779  * __vxge_hw_blockpool_block_allocate - Allocates a block from block pool
4780  * This function allocates a block from block pool or from the system
4781  */
4782 static struct __vxge_hw_blockpool_entry *
4783 __vxge_hw_blockpool_block_allocate(struct __vxge_hw_device *devh, u32 size)
4784 {
4785         struct __vxge_hw_blockpool_entry *entry = NULL;
4786         struct __vxge_hw_blockpool  *blockpool;
4787
4788         blockpool = &devh->block_pool;
4789
4790         if (size == blockpool->block_size) {
4791
4792                 if (!list_empty(&blockpool->free_block_list))
4793                         entry = (struct __vxge_hw_blockpool_entry *)
4794                                 list_first_entry(&blockpool->free_block_list,
4795                                         struct __vxge_hw_blockpool_entry,
4796                                         item);
4797
4798                 if (entry != NULL) {
4799                         list_del(&entry->item);
4800                         blockpool->pool_size--;
4801                 }
4802         }
4803
4804         if (entry != NULL)
4805                 __vxge_hw_blockpool_blocks_add(blockpool);
4806
4807         return entry;
4808 }
4809
4810 /*
4811  * vxge_hw_vpath_open - Open a virtual path on a given adapter
4812  * This function is used to open access to virtual path of an
4813  * adapter for offload, GRO operations. This function returns
4814  * synchronously.
4815  */
4816 enum vxge_hw_status
4817 vxge_hw_vpath_open(struct __vxge_hw_device *hldev,
4818                    struct vxge_hw_vpath_attr *attr,
4819                    struct __vxge_hw_vpath_handle **vpath_handle)
4820 {
4821         struct __vxge_hw_virtualpath *vpath;
4822         struct __vxge_hw_vpath_handle *vp;
4823         enum vxge_hw_status status;
4824
4825         vpath = &hldev->virtual_paths[attr->vp_id];
4826
4827         if (vpath->vp_open == VXGE_HW_VP_OPEN) {
4828                 status = VXGE_HW_ERR_INVALID_STATE;
4829                 goto vpath_open_exit1;
4830         }
4831
4832         status = __vxge_hw_vp_initialize(hldev, attr->vp_id,
4833                         &hldev->config.vp_config[attr->vp_id]);
4834         if (status != VXGE_HW_OK)
4835                 goto vpath_open_exit1;
4836
4837         vp = vzalloc(sizeof(struct __vxge_hw_vpath_handle));
4838         if (vp == NULL) {
4839                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4840                 goto vpath_open_exit2;
4841         }
4842
4843         vp->vpath = vpath;
4844
4845         if (vpath->vp_config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
4846                 status = __vxge_hw_fifo_create(vp, &attr->fifo_attr);
4847                 if (status != VXGE_HW_OK)
4848                         goto vpath_open_exit6;
4849         }
4850
4851         if (vpath->vp_config->ring.enable == VXGE_HW_RING_ENABLE) {
4852                 status = __vxge_hw_ring_create(vp, &attr->ring_attr);
4853                 if (status != VXGE_HW_OK)
4854                         goto vpath_open_exit7;
4855
4856                 __vxge_hw_vpath_prc_configure(hldev, attr->vp_id);
4857         }
4858
4859         vpath->fifoh->tx_intr_num =
4860                 (attr->vp_id * VXGE_HW_MAX_INTR_PER_VP)  +
4861                         VXGE_HW_VPATH_INTR_TX;
4862
4863         vpath->stats_block = __vxge_hw_blockpool_block_allocate(hldev,
4864                                 VXGE_HW_BLOCK_SIZE);
4865         if (vpath->stats_block == NULL) {
4866                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4867                 goto vpath_open_exit8;
4868         }
4869
4870         vpath->hw_stats = vpath->stats_block->memblock;
4871         memset(vpath->hw_stats, 0,
4872                 sizeof(struct vxge_hw_vpath_stats_hw_info));
4873
4874         hldev->stats.hw_dev_info_stats.vpath_info[attr->vp_id] =
4875                                                 vpath->hw_stats;
4876
4877         vpath->hw_stats_sav =
4878                 &hldev->stats.hw_dev_info_stats.vpath_info_sav[attr->vp_id];
4879         memset(vpath->hw_stats_sav, 0,
4880                         sizeof(struct vxge_hw_vpath_stats_hw_info));
4881
4882         writeq(vpath->stats_block->dma_addr, &vpath->vp_reg->stats_cfg);
4883
4884         status = vxge_hw_vpath_stats_enable(vp);
4885         if (status != VXGE_HW_OK)
4886                 goto vpath_open_exit8;
4887
4888         list_add(&vp->item, &vpath->vpath_handles);
4889
4890         hldev->vpaths_deployed |= vxge_mBIT(vpath->vp_id);
4891
4892         *vpath_handle = vp;
4893
4894         attr->fifo_attr.userdata = vpath->fifoh;
4895         attr->ring_attr.userdata = vpath->ringh;
4896
4897         return VXGE_HW_OK;
4898
4899 vpath_open_exit8:
4900         if (vpath->ringh != NULL)
4901                 __vxge_hw_ring_delete(vp);
4902 vpath_open_exit7:
4903         if (vpath->fifoh != NULL)
4904                 __vxge_hw_fifo_delete(vp);
4905 vpath_open_exit6:
4906         vfree(vp);
4907 vpath_open_exit2:
4908         __vxge_hw_vp_terminate(hldev, attr->vp_id);
4909 vpath_open_exit1:
4910
4911         return status;
4912 }
4913
4914 /**
4915  * vxge_hw_vpath_rx_doorbell_post - Close the handle got from previous vpath
4916  * (vpath) open
4917  * @vp: Handle got from previous vpath open
4918  *
4919  * This function is used to close access to virtual path opened
4920  * earlier.
4921  */
4922 void vxge_hw_vpath_rx_doorbell_init(struct __vxge_hw_vpath_handle *vp)
4923 {
4924         struct __vxge_hw_virtualpath *vpath = vp->vpath;
4925         struct __vxge_hw_ring *ring = vpath->ringh;
4926         struct vxgedev *vdev = netdev_priv(vpath->hldev->ndev);
4927         u64 new_count, val64, val164;
4928
4929         if (vdev->titan1) {
4930                 new_count = readq(&vpath->vp_reg->rxdmem_size);
4931                 new_count &= 0x1fff;
4932         } else
4933                 new_count = ring->config->ring_blocks * VXGE_HW_BLOCK_SIZE / 8;
4934
4935         val164 = VXGE_HW_RXDMEM_SIZE_PRC_RXDMEM_SIZE(new_count);
4936
4937         writeq(VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT(val164),
4938                 &vpath->vp_reg->prc_rxd_doorbell);
4939         readl(&vpath->vp_reg->prc_rxd_doorbell);
4940
4941         val164 /= 2;
4942         val64 = readq(&vpath->vp_reg->prc_cfg6);
4943         val64 = VXGE_HW_PRC_CFG6_RXD_SPAT(val64);
4944         val64 &= 0x1ff;
4945
4946         /*
4947          * Each RxD is of 4 qwords
4948          */
4949         new_count -= (val64 + 1);
4950         val64 = min(val164, new_count) / 4;
4951
4952         ring->rxds_limit = min(ring->rxds_limit, val64);
4953         if (ring->rxds_limit < 4)
4954                 ring->rxds_limit = 4;
4955 }
4956
4957 /*
4958  * __vxge_hw_blockpool_block_free - Frees a block from block pool
4959  * @devh: Hal device
4960  * @entry: Entry of block to be freed
4961  *
4962  * This function frees a block from block pool
4963  */
4964 static void
4965 __vxge_hw_blockpool_block_free(struct __vxge_hw_device *devh,
4966                                struct __vxge_hw_blockpool_entry *entry)
4967 {
4968         struct __vxge_hw_blockpool  *blockpool;
4969
4970         blockpool = &devh->block_pool;
4971
4972         if (entry->length == blockpool->block_size) {
4973                 list_add(&entry->item, &blockpool->free_block_list);
4974                 blockpool->pool_size++;
4975         }
4976
4977         __vxge_hw_blockpool_blocks_remove(blockpool);
4978 }
4979
4980 /*
4981  * vxge_hw_vpath_close - Close the handle got from previous vpath (vpath) open
4982  * This function is used to close access to virtual path opened
4983  * earlier.
4984  */
4985 enum vxge_hw_status vxge_hw_vpath_close(struct __vxge_hw_vpath_handle *vp)
4986 {
4987         struct __vxge_hw_virtualpath *vpath = NULL;
4988         struct __vxge_hw_device *devh = NULL;
4989         u32 vp_id = vp->vpath->vp_id;
4990         u32 is_empty = TRUE;
4991         enum vxge_hw_status status = VXGE_HW_OK;
4992
4993         vpath = vp->vpath;
4994         devh = vpath->hldev;
4995
4996         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4997                 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4998                 goto vpath_close_exit;
4999         }
5000
5001         list_del(&vp->item);
5002
5003         if (!list_empty(&vpath->vpath_handles)) {
5004                 list_add(&vp->item, &vpath->vpath_handles);
5005                 is_empty = FALSE;
5006         }
5007
5008         if (!is_empty) {
5009                 status = VXGE_HW_FAIL;
5010                 goto vpath_close_exit;
5011         }
5012
5013         devh->vpaths_deployed &= ~vxge_mBIT(vp_id);
5014
5015         if (vpath->ringh != NULL)
5016                 __vxge_hw_ring_delete(vp);
5017
5018         if (vpath->fifoh != NULL)
5019                 __vxge_hw_fifo_delete(vp);
5020
5021         if (vpath->stats_block != NULL)
5022                 __vxge_hw_blockpool_block_free(devh, vpath->stats_block);
5023
5024         vfree(vp);
5025
5026         __vxge_hw_vp_terminate(devh, vp_id);
5027
5028 vpath_close_exit:
5029         return status;
5030 }
5031
5032 /*
5033  * vxge_hw_vpath_reset - Resets vpath
5034  * This function is used to request a reset of vpath
5035  */
5036 enum vxge_hw_status vxge_hw_vpath_reset(struct __vxge_hw_vpath_handle *vp)
5037 {
5038         enum vxge_hw_status status;
5039         u32 vp_id;
5040         struct __vxge_hw_virtualpath *vpath = vp->vpath;
5041
5042         vp_id = vpath->vp_id;
5043
5044         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
5045                 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
5046                 goto exit;
5047         }
5048
5049         status = __vxge_hw_vpath_reset(vpath->hldev, vp_id);
5050         if (status == VXGE_HW_OK)
5051                 vpath->sw_stats->soft_reset_cnt++;
5052 exit:
5053         return status;
5054 }
5055
5056 /*
5057  * vxge_hw_vpath_recover_from_reset - Poll for reset complete and re-initialize.
5058  * This function poll's for the vpath reset completion and re initializes
5059  * the vpath.
5060  */
5061 enum vxge_hw_status
5062 vxge_hw_vpath_recover_from_reset(struct __vxge_hw_vpath_handle *vp)
5063 {
5064         struct __vxge_hw_virtualpath *vpath = NULL;
5065         enum vxge_hw_status status;
5066         struct __vxge_hw_device *hldev;
5067         u32 vp_id;
5068
5069         vp_id = vp->vpath->vp_id;
5070         vpath = vp->vpath;
5071         hldev = vpath->hldev;
5072
5073         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
5074                 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
5075                 goto exit;
5076         }
5077
5078         status = __vxge_hw_vpath_reset_check(vpath);
5079         if (status != VXGE_HW_OK)
5080                 goto exit;
5081
5082         status = __vxge_hw_vpath_sw_reset(hldev, vp_id);
5083         if (status != VXGE_HW_OK)
5084                 goto exit;
5085
5086         status = __vxge_hw_vpath_initialize(hldev, vp_id);
5087         if (status != VXGE_HW_OK)
5088                 goto exit;
5089
5090         if (vpath->ringh != NULL)
5091                 __vxge_hw_vpath_prc_configure(hldev, vp_id);
5092
5093         memset(vpath->hw_stats, 0,
5094                 sizeof(struct vxge_hw_vpath_stats_hw_info));
5095
5096         memset(vpath->hw_stats_sav, 0,
5097                 sizeof(struct vxge_hw_vpath_stats_hw_info));
5098
5099         writeq(vpath->stats_block->dma_addr,
5100                 &vpath->vp_reg->stats_cfg);
5101
5102         status = vxge_hw_vpath_stats_enable(vp);
5103
5104 exit:
5105         return status;
5106 }
5107
5108 /*
5109  * vxge_hw_vpath_enable - Enable vpath.
5110  * This routine clears the vpath reset thereby enabling a vpath
5111  * to start forwarding frames and generating interrupts.
5112  */
5113 void
5114 vxge_hw_vpath_enable(struct __vxge_hw_vpath_handle *vp)
5115 {
5116         struct __vxge_hw_device *hldev;
5117         u64 val64;
5118
5119         hldev = vp->vpath->hldev;
5120
5121         val64 = VXGE_HW_CMN_RSTHDLR_CFG1_CLR_VPATH_RESET(
5122                 1 << (16 - vp->vpath->vp_id));
5123
5124         __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32),
5125                 &hldev->common_reg->cmn_rsthdlr_cfg1);
5126 }