e3a25e64a6525f38a2329125b09e01bb116e8ae2
[linux-2.6.git] / drivers / net / ucc_geth.h
1 /*
2  * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
3  *
4  * Author: Shlomi Gridish <gridish@freescale.com>
5  *
6  * Description:
7  * Internal header file for UCC Gigabit Ethernet unit routines.
8  *
9  * Changelog:
10  * Jun 28, 2006 Li Yang <LeoLi@freescale.com>
11  * - Rearrange code and style fixes
12  *
13  * This program is free software; you can redistribute  it and/or modify it
14  * under  the terms of  the GNU General  Public License as published by the
15  * Free Software Foundation;  either version 2 of the  License, or (at your
16  * option) any later version.
17  */
18 #ifndef __UCC_GETH_H__
19 #define __UCC_GETH_H__
20
21 #include <linux/kernel.h>
22 #include <linux/list.h>
23 #include <linux/fsl_devices.h>
24
25 #include <asm/immap_qe.h>
26 #include <asm/qe.h>
27
28 #include <asm/ucc.h>
29 #include <asm/ucc_fast.h>
30
31 #define DRV_DESC "QE UCC Gigabit Ethernet Controller"
32 #define DRV_NAME "ucc_geth"
33 #define DRV_VERSION "1.1"
34
35 #define NUM_TX_QUEUES                   8
36 #define NUM_RX_QUEUES                   8
37 #define NUM_BDS_IN_PREFETCHED_BDS       4
38 #define TX_IP_OFFSET_ENTRY_MAX          8
39 #define NUM_OF_PADDRS                   4
40 #define ENET_INIT_PARAM_MAX_ENTRIES_RX  9
41 #define ENET_INIT_PARAM_MAX_ENTRIES_TX  8
42
43 struct ucc_geth {
44         struct ucc_fast uccf;
45         u8 res0[0x100 - sizeof(struct ucc_fast)];
46
47         u32 maccfg1;            /* mac configuration reg. 1 */
48         u32 maccfg2;            /* mac configuration reg. 2 */
49         u32 ipgifg;             /* interframe gap reg.  */
50         u32 hafdup;             /* half-duplex reg.  */
51         u8 res1[0x10];
52         u8 miimng[0x18];        /* MII management structure moved to _mii.h */
53         u32 ifctl;              /* interface control reg */
54         u32 ifstat;             /* interface statux reg */
55         u32 macstnaddr1;        /* mac station address part 1 reg */
56         u32 macstnaddr2;        /* mac station address part 2 reg */
57         u8 res2[0x8];
58         u32 uempr;              /* UCC Ethernet Mac parameter reg */
59         u32 utbipar;            /* UCC tbi address reg */
60         u16 uescr;              /* UCC Ethernet statistics control reg */
61         u8 res3[0x180 - 0x15A];
62         u32 tx64;               /* Total number of frames (including bad
63                                    frames) transmitted that were exactly of the
64                                    minimal length (64 for un tagged, 68 for
65                                    tagged, or with length exactly equal to the
66                                    parameter MINLength */
67         u32 tx127;              /* Total number of frames (including bad
68                                    frames) transmitted that were between
69                                    MINLength (Including FCS length==4) and 127
70                                    octets */
71         u32 tx255;              /* Total number of frames (including bad
72                                    frames) transmitted that were between 128
73                                    (Including FCS length==4) and 255 octets */
74         u32 rx64;               /* Total number of frames received including
75                                    bad frames that were exactly of the mninimal
76                                    length (64 bytes) */
77         u32 rx127;              /* Total number of frames (including bad
78                                    frames) received that were between MINLength
79                                    (Including FCS length==4) and 127 octets */
80         u32 rx255;              /* Total number of frames (including bad
81                                    frames) received that were between 128
82                                    (Including FCS length==4) and 255 octets */
83         u32 txok;               /* Total number of octets residing in frames
84                                    that where involved in succesfull
85                                    transmission */
86         u16 txcf;               /* Total number of PAUSE control frames
87                                    transmitted by this MAC */
88         u8 res4[0x2];
89         u32 tmca;               /* Total number of frames that were transmitted
90                                    succesfully with the group address bit set
91                                    that are not broadcast frames */
92         u32 tbca;               /* Total number of frames transmitted
93                                    succesfully that had destination address
94                                    field equal to the broadcast address */
95         u32 rxfok;              /* Total number of frames received OK */
96         u32 rxbok;              /* Total number of octets received OK */
97         u32 rbyt;               /* Total number of octets received including
98                                    octets in bad frames. Must be implemented in
99                                    HW because it includes octets in frames that
100                                    never even reach the UCC */
101         u32 rmca;               /* Total number of frames that were received
102                                    succesfully with the group address bit set
103                                    that are not broadcast frames */
104         u32 rbca;               /* Total number of frames received succesfully
105                                    that had destination address equal to the
106                                    broadcast address */
107         u32 scar;               /* Statistics carry register */
108         u32 scam;               /* Statistics caryy mask register */
109         u8 res5[0x200 - 0x1c4];
110 } __attribute__ ((packed));
111
112 /* UCC GETH TEMODR Register */
113 #define TEMODER_TX_RMON_STATISTICS_ENABLE       0x0100  /* enable Tx statistics
114                                                          */
115 #define TEMODER_SCHEDULER_ENABLE                0x2000  /* enable scheduler */
116 #define TEMODER_IP_CHECKSUM_GENERATE            0x0400  /* generate IPv4
117                                                            checksums */
118 #define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1  0x0200  /* enable performance
119                                                            optimization
120                                                            enhancement (mode1) */
121 #define TEMODER_RMON_STATISTICS                 0x0100  /* enable tx statistics
122                                                          */
123 #define TEMODER_NUM_OF_QUEUES_SHIFT             (15-15) /* Number of queues <<
124                                                            shift */
125
126 /* UCC GETH TEMODR Register */
127 #define REMODER_RX_RMON_STATISTICS_ENABLE       0x00001000      /* enable Rx
128                                                                    statistics */
129 #define REMODER_RX_EXTENDED_FEATURES            0x80000000      /* enable
130                                                                    extended
131                                                                    features */
132 #define REMODER_VLAN_OPERATION_TAGGED_SHIFT     (31-9 ) /* vlan operation
133                                                            tagged << shift */
134 #define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31-10) /* vlan operation non
135                                                            tagged << shift */
136 #define REMODER_RX_QOS_MODE_SHIFT               (31-15) /* rx QoS mode << shift
137                                                          */
138 #define REMODER_RMON_STATISTICS                 0x00001000      /* enable rx
139                                                                    statistics */
140 #define REMODER_RX_EXTENDED_FILTERING           0x00000800      /* extended
141                                                                    filtering
142                                                                    vs.
143                                                                    mpc82xx-like
144                                                                    filtering */
145 #define REMODER_NUM_OF_QUEUES_SHIFT             (31-23) /* Number of queues <<
146                                                            shift */
147 #define REMODER_DYNAMIC_MAX_FRAME_LENGTH        0x00000008      /* enable
148                                                                    dynamic max
149                                                                    frame length
150                                                                  */
151 #define REMODER_DYNAMIC_MIN_FRAME_LENGTH        0x00000004      /* enable
152                                                                    dynamic min
153                                                                    frame length
154                                                                  */
155 #define REMODER_IP_CHECKSUM_CHECK               0x00000002      /* check IPv4
156                                                                    checksums */
157 #define REMODER_IP_ADDRESS_ALIGNMENT            0x00000001      /* align ip
158                                                                    address to
159                                                                    4-byte
160                                                                    boundary */
161
162 /* UCC GETH Event Register */
163 #define UCCE_TXB   (UCC_GETH_UCCE_TXB7 | UCC_GETH_UCCE_TXB6 | \
164                     UCC_GETH_UCCE_TXB5 | UCC_GETH_UCCE_TXB4 | \
165                     UCC_GETH_UCCE_TXB3 | UCC_GETH_UCCE_TXB2 | \
166                     UCC_GETH_UCCE_TXB1 | UCC_GETH_UCCE_TXB0)
167
168 #define UCCE_RXB   (UCC_GETH_UCCE_RXB7 | UCC_GETH_UCCE_RXB6 | \
169                     UCC_GETH_UCCE_RXB5 | UCC_GETH_UCCE_RXB4 | \
170                     UCC_GETH_UCCE_RXB3 | UCC_GETH_UCCE_RXB2 | \
171                     UCC_GETH_UCCE_RXB1 | UCC_GETH_UCCE_RXB0)
172
173 #define UCCE_RXF   (UCC_GETH_UCCE_RXF7 | UCC_GETH_UCCE_RXF6 | \
174                     UCC_GETH_UCCE_RXF5 | UCC_GETH_UCCE_RXF4 | \
175                     UCC_GETH_UCCE_RXF3 | UCC_GETH_UCCE_RXF2 | \
176                     UCC_GETH_UCCE_RXF1 | UCC_GETH_UCCE_RXF0)
177
178 #define UCCE_OTHER (UCC_GETH_UCCE_SCAR | UCC_GETH_UCCE_GRA | \
179                     UCC_GETH_UCCE_CBPR | UCC_GETH_UCCE_BSY | \
180                     UCC_GETH_UCCE_RXC  | UCC_GETH_UCCE_TXC | UCC_GETH_UCCE_TXE)
181
182 #define UCCE_RX_EVENTS  (UCCE_RXF | UCC_GETH_UCCE_BSY)
183 #define UCCE_TX_EVENTS  (UCCE_TXB | UCC_GETH_UCCE_TXE)
184
185 /* TBI defines */
186 #define ENET_TBI_MII_CR         0x00    /* Control */
187 #define ENET_TBI_MII_SR         0x01    /* Status */
188 #define ENET_TBI_MII_ANA        0x04    /* AN advertisement */
189 #define ENET_TBI_MII_ANLPBPA    0x05    /* AN link partner base page ability */
190 #define ENET_TBI_MII_ANEX       0x06    /* AN expansion */
191 #define ENET_TBI_MII_ANNPT      0x07    /* AN next page transmit */
192 #define ENET_TBI_MII_ANLPANP    0x08    /* AN link partner ability next page */
193 #define ENET_TBI_MII_EXST       0x0F    /* Extended status */
194 #define ENET_TBI_MII_JD         0x10    /* Jitter diagnostics */
195 #define ENET_TBI_MII_TBICON     0x11    /* TBI control */
196
197 /* UCC GETH MACCFG1 (MAC Configuration 1 Register) */
198 #define MACCFG1_FLOW_RX                         0x00000020      /* Flow Control
199                                                                    Rx */
200 #define MACCFG1_FLOW_TX                         0x00000010      /* Flow Control
201                                                                    Tx */
202 #define MACCFG1_ENABLE_SYNCHED_RX               0x00000008      /* Rx Enable
203                                                                    synchronized
204                                                                    to Rx stream
205                                                                  */
206 #define MACCFG1_ENABLE_RX                       0x00000004      /* Enable Rx */
207 #define MACCFG1_ENABLE_SYNCHED_TX               0x00000002      /* Tx Enable
208                                                                    synchronized
209                                                                    to Tx stream
210                                                                  */
211 #define MACCFG1_ENABLE_TX                       0x00000001      /* Enable Tx */
212
213 /* UCC GETH MACCFG2 (MAC Configuration 2 Register) */
214 #define MACCFG2_PREL_SHIFT                      (31 - 19)       /* Preamble
215                                                                    Length <<
216                                                                    shift */
217 #define MACCFG2_PREL_MASK                       0x0000f000      /* Preamble
218                                                                    Length mask */
219 #define MACCFG2_SRP                             0x00000080      /* Soft Receive
220                                                                    Preamble */
221 #define MACCFG2_STP                             0x00000040      /* Soft
222                                                                    Transmit
223                                                                    Preamble */
224 #define MACCFG2_RESERVED_1                      0x00000020      /* Reserved -
225                                                                    must be set
226                                                                    to 1 */
227 #define MACCFG2_LC                              0x00000010      /* Length Check
228                                                                  */
229 #define MACCFG2_MPE                             0x00000008      /* Magic packet
230                                                                    detect */
231 #define MACCFG2_FDX                             0x00000001      /* Full Duplex */
232 #define MACCFG2_FDX_MASK                        0x00000001      /* Full Duplex
233                                                                    mask */
234 #define MACCFG2_PAD_CRC                         0x00000004
235 #define MACCFG2_CRC_EN                          0x00000002
236 #define MACCFG2_PAD_AND_CRC_MODE_NONE           0x00000000      /* Neither
237                                                                    Padding
238                                                                    short frames
239                                                                    nor CRC */
240 #define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY       0x00000002      /* Append CRC
241                                                                    only */
242 #define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC    0x00000004
243 #define MACCFG2_INTERFACE_MODE_NIBBLE           0x00000100      /* nibble mode
244                                                                    (MII/RMII/RGMII
245                                                                    10/100bps) */
246 #define MACCFG2_INTERFACE_MODE_BYTE             0x00000200      /* byte mode
247                                                                    (GMII/TBI/RTB/RGMII
248                                                                    1000bps ) */
249 #define MACCFG2_INTERFACE_MODE_MASK             0x00000300      /* mask
250                                                                    covering all
251                                                                    relevant
252                                                                    bits */
253
254 /* UCC GETH IPGIFG (Inter-frame Gap / Inter-Frame Gap Register) */
255 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT (31 -  7)       /* Non
256                                                                    back-to-back
257                                                                    inter frame
258                                                                    gap part 1.
259                                                                    << shift */
260 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT (31 - 15)       /* Non
261                                                                    back-to-back
262                                                                    inter frame
263                                                                    gap part 2.
264                                                                    << shift */
265 #define IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT    (31 - 23)       /* Mimimum IFG
266                                                                    Enforcement
267                                                                    << shift */
268 #define IPGIFG_BACK_TO_BACK_IFG_SHIFT           (31 - 31)       /* back-to-back
269                                                                    inter frame
270                                                                    gap << shift
271                                                                  */
272 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX   127     /* Non back-to-back
273                                                            inter frame gap part
274                                                            1. max val */
275 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX   127     /* Non back-to-back
276                                                            inter frame gap part
277                                                            2. max val */
278 #define IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX      255     /* Mimimum IFG
279                                                            Enforcement max val */
280 #define IPGIFG_BACK_TO_BACK_IFG_MAX             127     /* back-to-back inter
281                                                            frame gap max val */
282 #define IPGIFG_NBTB_CS_IPG_MASK                 0x7F000000
283 #define IPGIFG_NBTB_IPG_MASK                    0x007F0000
284 #define IPGIFG_MIN_IFG_MASK                     0x0000FF00
285 #define IPGIFG_BTB_IPG_MASK                     0x0000007F
286
287 /* UCC GETH HAFDUP (Half Duplex Register) */
288 #define HALFDUP_ALT_BEB_TRUNCATION_SHIFT        (31 - 11)       /* Alternate
289                                                                    Binary
290                                                                    Exponential
291                                                                    Backoff
292                                                                    Truncation
293                                                                    << shift */
294 #define HALFDUP_ALT_BEB_TRUNCATION_MAX          0xf     /* Alternate Binary
295                                                            Exponential Backoff
296                                                            Truncation max val */
297 #define HALFDUP_ALT_BEB                         0x00080000      /* Alternate
298                                                                    Binary
299                                                                    Exponential
300                                                                    Backoff */
301 #define HALFDUP_BACK_PRESSURE_NO_BACKOFF        0x00040000      /* Back
302                                                                    pressure no
303                                                                    backoff */
304 #define HALFDUP_NO_BACKOFF                      0x00020000      /* No Backoff */
305 #define HALFDUP_EXCESSIVE_DEFER                 0x00010000      /* Excessive
306                                                                    Defer */
307 #define HALFDUP_MAX_RETRANSMISSION_SHIFT        (31 - 19)       /* Maximum
308                                                                    Retransmission
309                                                                    << shift */
310 #define HALFDUP_MAX_RETRANSMISSION_MAX          0xf     /* Maximum
311                                                            Retransmission max
312                                                            val */
313 #define HALFDUP_COLLISION_WINDOW_SHIFT          (31 - 31)       /* Collision
314                                                                    Window <<
315                                                                    shift */
316 #define HALFDUP_COLLISION_WINDOW_MAX            0x3f    /* Collision Window max
317                                                            val */
318 #define HALFDUP_ALT_BEB_TR_MASK                 0x00F00000
319 #define HALFDUP_RETRANS_MASK                    0x0000F000
320 #define HALFDUP_COL_WINDOW_MASK                 0x0000003F
321
322 /* UCC GETH UCCS (Ethernet Status Register) */
323 #define UCCS_BPR                                0x02    /* Back pressure (in
324                                                            half duplex mode) */
325 #define UCCS_PAU                                0x02    /* Pause state (in full
326                                                            duplex mode) */
327 #define UCCS_MPD                                0x01    /* Magic Packet
328                                                            Detected */
329
330 /* UCC GETH IFSTAT (Interface Status Register) */
331 #define IFSTAT_EXCESS_DEFER                     0x00000200      /* Excessive
332                                                                    transmission
333                                                                    defer */
334
335 /* UCC GETH MACSTNADDR1 (Station Address Part 1 Register) */
336 #define MACSTNADDR1_OCTET_6_SHIFT               (31 -  7)       /* Station
337                                                                    address 6th
338                                                                    octet <<
339                                                                    shift */
340 #define MACSTNADDR1_OCTET_5_SHIFT               (31 - 15)       /* Station
341                                                                    address 5th
342                                                                    octet <<
343                                                                    shift */
344 #define MACSTNADDR1_OCTET_4_SHIFT               (31 - 23)       /* Station
345                                                                    address 4th
346                                                                    octet <<
347                                                                    shift */
348 #define MACSTNADDR1_OCTET_3_SHIFT               (31 - 31)       /* Station
349                                                                    address 3rd
350                                                                    octet <<
351                                                                    shift */
352
353 /* UCC GETH MACSTNADDR2 (Station Address Part 2 Register) */
354 #define MACSTNADDR2_OCTET_2_SHIFT               (31 -  7)       /* Station
355                                                                    address 2nd
356                                                                    octet <<
357                                                                    shift */
358 #define MACSTNADDR2_OCTET_1_SHIFT               (31 - 15)       /* Station
359                                                                    address 1st
360                                                                    octet <<
361                                                                    shift */
362
363 /* UCC GETH UEMPR (Ethernet Mac Parameter Register) */
364 #define UEMPR_PAUSE_TIME_VALUE_SHIFT            (31 - 15)       /* Pause time
365                                                                    value <<
366                                                                    shift */
367 #define UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT   (31 - 31)       /* Extended
368                                                                    pause time
369                                                                    value <<
370                                                                    shift */
371
372 /* UCC GETH UTBIPAR (Ten Bit Interface Physical Address Register) */
373 #define UTBIPAR_PHY_ADDRESS_SHIFT               (31 - 31)       /* Phy address
374                                                                    << shift */
375 #define UTBIPAR_PHY_ADDRESS_MASK                0x0000001f      /* Phy address
376                                                                    mask */
377
378 /* UCC GETH UESCR (Ethernet Statistics Control Register) */
379 #define UESCR_AUTOZ                             0x8000  /* Automatically zero
380                                                            addressed
381                                                            statistical counter
382                                                            values */
383 #define UESCR_CLRCNT                            0x4000  /* Clear all statistics
384                                                            counters */
385 #define UESCR_MAXCOV_SHIFT                      (15 -  7)       /* Max
386                                                                    Coalescing
387                                                                    Value <<
388                                                                    shift */
389 #define UESCR_SCOV_SHIFT                        (15 - 15)       /* Status
390                                                                    Coalescing
391                                                                    Value <<
392                                                                    shift */
393
394 /* UCC GETH UDSR (Data Synchronization Register) */
395 #define UDSR_MAGIC                              0x067E
396
397 struct ucc_geth_thread_data_tx {
398         u8 res0[104];
399 } __attribute__ ((packed));
400
401 struct ucc_geth_thread_data_rx {
402         u8 res0[40];
403 } __attribute__ ((packed));
404
405 /* Send Queue Queue-Descriptor */
406 struct ucc_geth_send_queue_qd {
407         u32 bd_ring_base;       /* pointer to BD ring base address */
408         u8 res0[0x8];
409         u32 last_bd_completed_address;/* initialize to last entry in BD ring */
410         u8 res1[0x30];
411 } __attribute__ ((packed));
412
413 struct ucc_geth_send_queue_mem_region {
414         struct ucc_geth_send_queue_qd sqqd[NUM_TX_QUEUES];
415 } __attribute__ ((packed));
416
417 struct ucc_geth_thread_tx_pram {
418         u8 res0[64];
419 } __attribute__ ((packed));
420
421 struct ucc_geth_thread_rx_pram {
422         u8 res0[128];
423 } __attribute__ ((packed));
424
425 #define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING        64
426 #define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8      64
427 #define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16     96
428
429 struct ucc_geth_scheduler {
430         u16 cpucount0;          /* CPU packet counter */
431         u16 cpucount1;          /* CPU packet counter */
432         u16 cecount0;           /* QE packet counter */
433         u16 cecount1;           /* QE packet counter */
434         u16 cpucount2;          /* CPU packet counter */
435         u16 cpucount3;          /* CPU packet counter */
436         u16 cecount2;           /* QE packet counter */
437         u16 cecount3;           /* QE packet counter */
438         u16 cpucount4;          /* CPU packet counter */
439         u16 cpucount5;          /* CPU packet counter */
440         u16 cecount4;           /* QE packet counter */
441         u16 cecount5;           /* QE packet counter */
442         u16 cpucount6;          /* CPU packet counter */
443         u16 cpucount7;          /* CPU packet counter */
444         u16 cecount6;           /* QE packet counter */
445         u16 cecount7;           /* QE packet counter */
446         u32 weightstatus[NUM_TX_QUEUES];        /* accumulated weight factor */
447         u32 rtsrshadow;         /* temporary variable handled by QE */
448         u32 time;               /* temporary variable handled by QE */
449         u32 ttl;                /* temporary variable handled by QE */
450         u32 mblinterval;        /* max burst length interval */
451         u16 nortsrbytetime;     /* normalized value of byte time in tsr units */
452         u8 fracsiz;             /* radix 2 log value of denom. of
453                                    NorTSRByteTime */
454         u8 res0[1];
455         u8 strictpriorityq;     /* Strict Priority Mask register */
456         u8 txasap;              /* Transmit ASAP register */
457         u8 extrabw;             /* Extra BandWidth register */
458         u8 oldwfqmask;          /* temporary variable handled by QE */
459         u8 weightfactor[NUM_TX_QUEUES];
460                                       /**< weight factor for queues   */
461         u32 minw;               /* temporary variable handled by QE */
462         u8 res1[0x70 - 0x64];
463 } __attribute__ ((packed));
464
465 struct ucc_geth_tx_firmware_statistics_pram {
466         u32 sicoltx;            /* single collision */
467         u32 mulcoltx;           /* multiple collision */
468         u32 latecoltxfr;        /* late collision */
469         u32 frabortduecol;      /* frames aborted due to transmit collision */
470         u32 frlostinmactxer;    /* frames lost due to internal MAC error
471                                    transmission that are not counted on any
472                                    other counter */
473         u32 carriersenseertx;   /* carrier sense error */
474         u32 frtxok;             /* frames transmitted OK */
475         u32 txfrexcessivedefer; /* frames with defferal time greater than
476                                    specified threshold */
477         u32 txpkts256;          /* total packets (including bad) between 256
478                                    and 511 octets */
479         u32 txpkts512;          /* total packets (including bad) between 512
480                                    and 1023 octets */
481         u32 txpkts1024;         /* total packets (including bad) between 1024
482                                    and 1518 octets */
483         u32 txpktsjumbo;        /* total packets (including bad) between 1024
484                                    and MAXLength octets */
485 } __attribute__ ((packed));
486
487 struct ucc_geth_rx_firmware_statistics_pram {
488         u32 frrxfcser;          /* frames with crc error */
489         u32 fraligner;          /* frames with alignment error */
490         u32 inrangelenrxer;     /* in range length error */
491         u32 outrangelenrxer;    /* out of range length error */
492         u32 frtoolong;          /* frame too long */
493         u32 runt;               /* runt */
494         u32 verylongevent;      /* very long event */
495         u32 symbolerror;        /* symbol error */
496         u32 dropbsy;            /* drop because of BD not ready */
497         u8 res0[0x8];
498         u32 mismatchdrop;       /* drop because of MAC filtering (e.g. address
499                                    or type mismatch) */
500         u32 underpkts;          /* total frames less than 64 octets */
501         u32 pkts256;            /* total frames (including bad) between 256 and
502                                    511 octets */
503         u32 pkts512;            /* total frames (including bad) between 512 and
504                                    1023 octets */
505         u32 pkts1024;           /* total frames (including bad) between 1024
506                                    and 1518 octets */
507         u32 pktsjumbo;          /* total frames (including bad) between 1024
508                                    and MAXLength octets */
509         u32 frlossinmacer;      /* frames lost because of internal MAC error
510                                    that is not counted in any other counter */
511         u32 pausefr;            /* pause frames */
512         u8 res1[0x4];
513         u32 removevlan;         /* total frames that had their VLAN tag removed
514                                  */
515         u32 replacevlan;        /* total frames that had their VLAN tag
516                                    replaced */
517         u32 insertvlan;         /* total frames that had their VLAN tag
518                                    inserted */
519 } __attribute__ ((packed));
520
521 struct ucc_geth_rx_interrupt_coalescing_entry {
522         u32 interruptcoalescingmaxvalue;        /* interrupt coalescing max
523                                                    value */
524         u32 interruptcoalescingcounter; /* interrupt coalescing counter,
525                                            initialize to
526                                            interruptcoalescingmaxvalue */
527 } __attribute__ ((packed));
528
529 struct ucc_geth_rx_interrupt_coalescing_table {
530         struct ucc_geth_rx_interrupt_coalescing_entry coalescingentry[NUM_RX_QUEUES];
531                                        /**< interrupt coalescing entry */
532 } __attribute__ ((packed));
533
534 struct ucc_geth_rx_prefetched_bds {
535         struct qe_bd bd[NUM_BDS_IN_PREFETCHED_BDS];     /* prefetched bd */
536 } __attribute__ ((packed));
537
538 struct ucc_geth_rx_bd_queues_entry {
539         u32 bdbaseptr;          /* BD base pointer */
540         u32 bdptr;              /* BD pointer */
541         u32 externalbdbaseptr;  /* external BD base pointer */
542         u32 externalbdptr;      /* external BD pointer */
543 } __attribute__ ((packed));
544
545 struct ucc_geth_tx_global_pram {
546         u16 temoder;
547         u8 res0[0x38 - 0x02];
548         u32 sqptr;              /* a base pointer to send queue memory region */
549         u32 schedulerbasepointer;       /* a base pointer to scheduler memory
550                                            region */
551         u32 txrmonbaseptr;      /* base pointer to Tx RMON statistics counter */
552         u32 tstate;             /* tx internal state. High byte contains
553                                    function code */
554         u8 iphoffset[TX_IP_OFFSET_ENTRY_MAX];
555         u32 vtagtable[0x8];     /* 8 4-byte VLAN tags */
556         u32 tqptr;              /* a base pointer to the Tx Queues Memory
557                                    Region */
558         u8 res2[0x80 - 0x74];
559 } __attribute__ ((packed));
560
561 /* structure representing Extended Filtering Global Parameters in PRAM */
562 struct ucc_geth_exf_global_pram {
563         u32 l2pcdptr;           /* individual address filter, high */
564         u8 res0[0x10 - 0x04];
565 } __attribute__ ((packed));
566
567 struct ucc_geth_rx_global_pram {
568         u32 remoder;            /* ethernet mode reg. */
569         u32 rqptr;              /* base pointer to the Rx Queues Memory Region*/
570         u32 res0[0x1];
571         u8 res1[0x20 - 0xC];
572         u16 typeorlen;          /* cutoff point less than which, type/len field
573                                    is considered length */
574         u8 res2[0x1];
575         u8 rxgstpack;           /* acknowledgement on GRACEFUL STOP RX command*/
576         u32 rxrmonbaseptr;      /* base pointer to Rx RMON statistics counter */
577         u8 res3[0x30 - 0x28];
578         u32 intcoalescingptr;   /* Interrupt coalescing table pointer */
579         u8 res4[0x36 - 0x34];
580         u8 rstate;              /* rx internal state. High byte contains
581                                    function code */
582         u8 res5[0x46 - 0x37];
583         u16 mrblr;              /* max receive buffer length reg. */
584         u32 rbdqptr;            /* base pointer to RxBD parameter table
585                                    description */
586         u16 mflr;               /* max frame length reg. */
587         u16 minflr;             /* min frame length reg. */
588         u16 maxd1;              /* max dma1 length reg. */
589         u16 maxd2;              /* max dma2 length reg. */
590         u32 ecamptr;            /* external CAM address */
591         u32 l2qt;               /* VLAN priority mapping table. */
592         u32 l3qt[0x8];          /* IP priority mapping table. */
593         u16 vlantype;           /* vlan type */
594         u16 vlantci;            /* default vlan tci */
595         u8 addressfiltering[64];        /* address filtering data structure */
596         u32 exfGlobalParam;     /* base address for extended filtering global
597                                    parameters */
598         u8 res6[0x100 - 0xC4];  /* Initialize to zero */
599 } __attribute__ ((packed));
600
601 #define GRACEFUL_STOP_ACKNOWLEDGE_RX            0x01
602
603 /* structure representing InitEnet command */
604 struct ucc_geth_init_pram {
605         u8 resinit1;
606         u8 resinit2;
607         u8 resinit3;
608         u8 resinit4;
609         u16 resinit5;
610         u8 res1[0x1];
611         u8 largestexternallookupkeysize;
612         u32 rgftgfrxglobal;
613         u32 rxthread[ENET_INIT_PARAM_MAX_ENTRIES_RX];   /* rx threads */
614         u8 res2[0x38 - 0x30];
615         u32 txglobal;           /* tx global */
616         u32 txthread[ENET_INIT_PARAM_MAX_ENTRIES_TX];   /* tx threads */
617         u8 res3[0x1];
618 } __attribute__ ((packed));
619
620 #define ENET_INIT_PARAM_RGF_SHIFT               (32 - 4)
621 #define ENET_INIT_PARAM_TGF_SHIFT               (32 - 8)
622
623 #define ENET_INIT_PARAM_RISC_MASK               0x0000003f
624 #define ENET_INIT_PARAM_PTR_MASK                0x00ffffc0
625 #define ENET_INIT_PARAM_SNUM_MASK               0xff000000
626 #define ENET_INIT_PARAM_SNUM_SHIFT              24
627
628 #define ENET_INIT_PARAM_MAGIC_RES_INIT1         0x06
629 #define ENET_INIT_PARAM_MAGIC_RES_INIT2         0x30
630 #define ENET_INIT_PARAM_MAGIC_RES_INIT3         0xff
631 #define ENET_INIT_PARAM_MAGIC_RES_INIT4         0x00
632 #define ENET_INIT_PARAM_MAGIC_RES_INIT5         0x0400
633
634 /* structure representing 82xx Address Filtering Enet Address in PRAM */
635 struct ucc_geth_82xx_enet_address {
636         u8 res1[0x2];
637         u16 h;                  /* address (MSB) */
638         u16 m;                  /* address */
639         u16 l;                  /* address (LSB) */
640 } __attribute__ ((packed));
641
642 /* structure representing 82xx Address Filtering PRAM */
643 struct ucc_geth_82xx_address_filtering_pram {
644         u32 iaddr_h;            /* individual address filter, high */
645         u32 iaddr_l;            /* individual address filter, low */
646         u32 gaddr_h;            /* group address filter, high */
647         u32 gaddr_l;            /* group address filter, low */
648         struct ucc_geth_82xx_enet_address __iomem taddr;
649         struct ucc_geth_82xx_enet_address __iomem paddr[NUM_OF_PADDRS];
650         u8 res0[0x40 - 0x38];
651 } __attribute__ ((packed));
652
653 /* GETH Tx firmware statistics structure, used when calling
654    UCC_GETH_GetStatistics. */
655 struct ucc_geth_tx_firmware_statistics {
656         u32 sicoltx;            /* single collision */
657         u32 mulcoltx;           /* multiple collision */
658         u32 latecoltxfr;        /* late collision */
659         u32 frabortduecol;      /* frames aborted due to transmit collision */
660         u32 frlostinmactxer;    /* frames lost due to internal MAC error
661                                    transmission that are not counted on any
662                                    other counter */
663         u32 carriersenseertx;   /* carrier sense error */
664         u32 frtxok;             /* frames transmitted OK */
665         u32 txfrexcessivedefer; /* frames with defferal time greater than
666                                    specified threshold */
667         u32 txpkts256;          /* total packets (including bad) between 256
668                                    and 511 octets */
669         u32 txpkts512;          /* total packets (including bad) between 512
670                                    and 1023 octets */
671         u32 txpkts1024;         /* total packets (including bad) between 1024
672                                    and 1518 octets */
673         u32 txpktsjumbo;        /* total packets (including bad) between 1024
674                                    and MAXLength octets */
675 } __attribute__ ((packed));
676
677 /* GETH Rx firmware statistics structure, used when calling
678    UCC_GETH_GetStatistics. */
679 struct ucc_geth_rx_firmware_statistics {
680         u32 frrxfcser;          /* frames with crc error */
681         u32 fraligner;          /* frames with alignment error */
682         u32 inrangelenrxer;     /* in range length error */
683         u32 outrangelenrxer;    /* out of range length error */
684         u32 frtoolong;          /* frame too long */
685         u32 runt;               /* runt */
686         u32 verylongevent;      /* very long event */
687         u32 symbolerror;        /* symbol error */
688         u32 dropbsy;            /* drop because of BD not ready */
689         u8 res0[0x8];
690         u32 mismatchdrop;       /* drop because of MAC filtering (e.g. address
691                                    or type mismatch) */
692         u32 underpkts;          /* total frames less than 64 octets */
693         u32 pkts256;            /* total frames (including bad) between 256 and
694                                    511 octets */
695         u32 pkts512;            /* total frames (including bad) between 512 and
696                                    1023 octets */
697         u32 pkts1024;           /* total frames (including bad) between 1024
698                                    and 1518 octets */
699         u32 pktsjumbo;          /* total frames (including bad) between 1024
700                                    and MAXLength octets */
701         u32 frlossinmacer;      /* frames lost because of internal MAC error
702                                    that is not counted in any other counter */
703         u32 pausefr;            /* pause frames */
704         u8 res1[0x4];
705         u32 removevlan;         /* total frames that had their VLAN tag removed
706                                  */
707         u32 replacevlan;        /* total frames that had their VLAN tag
708                                    replaced */
709         u32 insertvlan;         /* total frames that had their VLAN tag
710                                    inserted */
711 } __attribute__ ((packed));
712
713 /* GETH hardware statistics structure, used when calling
714    UCC_GETH_GetStatistics. */
715 struct ucc_geth_hardware_statistics {
716         u32 tx64;               /* Total number of frames (including bad
717                                    frames) transmitted that were exactly of the
718                                    minimal length (64 for un tagged, 68 for
719                                    tagged, or with length exactly equal to the
720                                    parameter MINLength */
721         u32 tx127;              /* Total number of frames (including bad
722                                    frames) transmitted that were between
723                                    MINLength (Including FCS length==4) and 127
724                                    octets */
725         u32 tx255;              /* Total number of frames (including bad
726                                    frames) transmitted that were between 128
727                                    (Including FCS length==4) and 255 octets */
728         u32 rx64;               /* Total number of frames received including
729                                    bad frames that were exactly of the mninimal
730                                    length (64 bytes) */
731         u32 rx127;              /* Total number of frames (including bad
732                                    frames) received that were between MINLength
733                                    (Including FCS length==4) and 127 octets */
734         u32 rx255;              /* Total number of frames (including bad
735                                    frames) received that were between 128
736                                    (Including FCS length==4) and 255 octets */
737         u32 txok;               /* Total number of octets residing in frames
738                                    that where involved in succesfull
739                                    transmission */
740         u16 txcf;               /* Total number of PAUSE control frames
741                                    transmitted by this MAC */
742         u32 tmca;               /* Total number of frames that were transmitted
743                                    succesfully with the group address bit set
744                                    that are not broadcast frames */
745         u32 tbca;               /* Total number of frames transmitted
746                                    succesfully that had destination address
747                                    field equal to the broadcast address */
748         u32 rxfok;              /* Total number of frames received OK */
749         u32 rxbok;              /* Total number of octets received OK */
750         u32 rbyt;               /* Total number of octets received including
751                                    octets in bad frames. Must be implemented in
752                                    HW because it includes octets in frames that
753                                    never even reach the UCC */
754         u32 rmca;               /* Total number of frames that were received
755                                    succesfully with the group address bit set
756                                    that are not broadcast frames */
757         u32 rbca;               /* Total number of frames received succesfully
758                                    that had destination address equal to the
759                                    broadcast address */
760 } __attribute__ ((packed));
761
762 /* UCC GETH Tx errors returned via TxConf callback */
763 #define TX_ERRORS_DEF      0x0200
764 #define TX_ERRORS_EXDEF    0x0100
765 #define TX_ERRORS_LC       0x0080
766 #define TX_ERRORS_RL       0x0040
767 #define TX_ERRORS_RC_MASK  0x003C
768 #define TX_ERRORS_RC_SHIFT 2
769 #define TX_ERRORS_UN       0x0002
770 #define TX_ERRORS_CSL      0x0001
771
772 /* UCC GETH Rx errors returned via RxStore callback */
773 #define RX_ERRORS_CMR      0x0200
774 #define RX_ERRORS_M        0x0100
775 #define RX_ERRORS_BC       0x0080
776 #define RX_ERRORS_MC       0x0040
777
778 /* Transmit BD. These are in addition to values defined in uccf. */
779 #define T_VID      0x003c0000   /* insert VLAN id index mask. */
780 #define T_DEF      (((u32) TX_ERRORS_DEF     ) << 16)
781 #define T_EXDEF    (((u32) TX_ERRORS_EXDEF   ) << 16)
782 #define T_LC       (((u32) TX_ERRORS_LC      ) << 16)
783 #define T_RL       (((u32) TX_ERRORS_RL      ) << 16)
784 #define T_RC_MASK  (((u32) TX_ERRORS_RC_MASK ) << 16)
785 #define T_UN       (((u32) TX_ERRORS_UN      ) << 16)
786 #define T_CSL      (((u32) TX_ERRORS_CSL     ) << 16)
787 #define T_ERRORS_REPORT  (T_DEF | T_EXDEF | T_LC | T_RL | T_RC_MASK \
788                 | T_UN | T_CSL) /* transmit errors to report */
789
790 /* Receive BD. These are in addition to values defined in uccf. */
791 #define R_LG    0x00200000      /* Frame length violation.  */
792 #define R_NO    0x00100000      /* Non-octet aligned frame.  */
793 #define R_SH    0x00080000      /* Short frame.  */
794 #define R_CR    0x00040000      /* CRC error.  */
795 #define R_OV    0x00020000      /* Overrun.  */
796 #define R_IPCH  0x00010000      /* IP checksum check failed. */
797 #define R_CMR   (((u32) RX_ERRORS_CMR  ) << 16)
798 #define R_M     (((u32) RX_ERRORS_M    ) << 16)
799 #define R_BC    (((u32) RX_ERRORS_BC   ) << 16)
800 #define R_MC    (((u32) RX_ERRORS_MC   ) << 16)
801 #define R_ERRORS_REPORT (R_CMR | R_M | R_BC | R_MC)     /* receive errors to
802                                                            report */
803 #define R_ERRORS_FATAL  (R_LG  | R_NO | R_SH | R_CR | \
804                 R_OV | R_IPCH)  /* receive errors to discard */
805
806 /* Alignments */
807 #define UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT       256
808 #define UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT       128
809 #define UCC_GETH_THREAD_RX_PRAM_ALIGNMENT       128
810 #define UCC_GETH_THREAD_TX_PRAM_ALIGNMENT       64
811 #define UCC_GETH_THREAD_DATA_ALIGNMENT          256     /* spec gives values
812                                                            based on num of
813                                                            threads, but always
814                                                            using the maximum is
815                                                            easier */
816 #define UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT  32
817 #define UCC_GETH_SCHEDULER_ALIGNMENT            4       /* This is a guess */
818 #define UCC_GETH_TX_STATISTICS_ALIGNMENT        4       /* This is a guess */
819 #define UCC_GETH_RX_STATISTICS_ALIGNMENT        4       /* This is a guess */
820 #define UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT      64
821 #define UCC_GETH_RX_BD_QUEUES_ALIGNMENT         8       /* This is a guess */
822 #define UCC_GETH_RX_PREFETCHED_BDS_ALIGNMENT    128     /* This is a guess */
823 #define UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 4    /* This
824                                                                            is a
825                                                                            guess
826                                                                          */
827 #define UCC_GETH_RX_BD_RING_ALIGNMENT           32
828 #define UCC_GETH_TX_BD_RING_ALIGNMENT           32
829 #define UCC_GETH_MRBLR_ALIGNMENT                128
830 #define UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT      4
831 #define UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT       32
832 #define UCC_GETH_RX_DATA_BUF_ALIGNMENT          64
833
834 #define UCC_GETH_TAD_EF                         0x80
835 #define UCC_GETH_TAD_V                          0x40
836 #define UCC_GETH_TAD_REJ                        0x20
837 #define UCC_GETH_TAD_VTAG_OP_RIGHT_SHIFT        2
838 #define UCC_GETH_TAD_VTAG_OP_SHIFT              6
839 #define UCC_GETH_TAD_V_NON_VTAG_OP              0x20
840 #define UCC_GETH_TAD_RQOS_SHIFT                 0
841 #define UCC_GETH_TAD_V_PRIORITY_SHIFT           5
842 #define UCC_GETH_TAD_CFI                        0x10
843
844 #define UCC_GETH_VLAN_PRIORITY_MAX              8
845 #define UCC_GETH_IP_PRIORITY_MAX                64
846 #define UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX        8
847 #define UCC_GETH_RX_BD_RING_SIZE_MIN            8
848 #define UCC_GETH_TX_BD_RING_SIZE_MIN            2
849 #define UCC_GETH_BD_RING_SIZE_MAX               0xffff
850
851 #define UCC_GETH_SIZE_OF_BD                     QE_SIZEOF_BD
852
853 /* Driver definitions */
854 #define TX_BD_RING_LEN                          0x10
855 #define RX_BD_RING_LEN                          0x10
856 #define UCC_GETH_DEV_WEIGHT                     TX_BD_RING_LEN
857
858 #define TX_RING_MOD_MASK(size)                  (size-1)
859 #define RX_RING_MOD_MASK(size)                  (size-1)
860
861 #define ENET_NUM_OCTETS_PER_ADDRESS             6
862 #define ENET_GROUP_ADDR                         0x01    /* Group address mask
863                                                            for ethernet
864                                                            addresses */
865
866 #define TX_TIMEOUT                              (1*HZ)
867 #define SKB_ALLOC_TIMEOUT                       100000
868 #define PHY_INIT_TIMEOUT                        100000
869 #define PHY_CHANGE_TIME                         2
870
871 /* Fast Ethernet (10/100 Mbps) */
872 #define UCC_GETH_URFS_INIT                      512     /* Rx virtual FIFO size
873                                                          */
874 #define UCC_GETH_URFET_INIT                     256     /* 1/2 urfs */
875 #define UCC_GETH_URFSET_INIT                    384     /* 3/4 urfs */
876 #define UCC_GETH_UTFS_INIT                      512     /* Tx virtual FIFO size
877                                                          */
878 #define UCC_GETH_UTFET_INIT                     256     /* 1/2 utfs */
879 #define UCC_GETH_UTFTT_INIT                     128
880 /* Gigabit Ethernet (1000 Mbps) */
881 #define UCC_GETH_URFS_GIGA_INIT                 4096/*2048*/    /* Rx virtual
882                                                                    FIFO size */
883 #define UCC_GETH_URFET_GIGA_INIT                2048/*1024*/    /* 1/2 urfs */
884 #define UCC_GETH_URFSET_GIGA_INIT               3072/*1536*/    /* 3/4 urfs */
885 #define UCC_GETH_UTFS_GIGA_INIT                 8192/*2048*/    /* Tx virtual
886                                                                    FIFO size */
887 #define UCC_GETH_UTFET_GIGA_INIT                4096/*1024*/    /* 1/2 utfs */
888 #define UCC_GETH_UTFTT_GIGA_INIT                0x400/*0x40*/   /* */
889
890 #define UCC_GETH_REMODER_INIT                   0       /* bits that must be
891                                                            set */
892 #define UCC_GETH_TEMODER_INIT                   0xC000  /* bits that must */
893
894 /* Initial value for UPSMR */
895 #define UCC_GETH_UPSMR_INIT                     UCC_GETH_UPSMR_RES1
896
897 #define UCC_GETH_MACCFG1_INIT                   0
898 #define UCC_GETH_MACCFG2_INIT                   (MACCFG2_RESERVED_1)
899
900 /* Ethernet Address Type. */
901 enum enet_addr_type {
902         ENET_ADDR_TYPE_INDIVIDUAL,
903         ENET_ADDR_TYPE_GROUP,
904         ENET_ADDR_TYPE_BROADCAST
905 };
906
907 /* UCC GETH 82xx Ethernet Address Recognition Location */
908 enum ucc_geth_enet_address_recognition_location {
909         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_STATION_ADDRESS,/* station
910                                                                       address */
911         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR_FIRST, /* additional
912                                                                    station
913                                                                    address
914                                                                    paddr1 */
915         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR2,      /* additional
916                                                                    station
917                                                                    address
918                                                                    paddr2 */
919         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR3,      /* additional
920                                                                    station
921                                                                    address
922                                                                    paddr3 */
923         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR_LAST,  /* additional
924                                                                    station
925                                                                    address
926                                                                    paddr4 */
927         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_GROUP_HASH,  /* group hash */
928         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_INDIVIDUAL_HASH /* individual
929                                                                       hash */
930 };
931
932 /* UCC GETH vlan operation tagged */
933 enum ucc_geth_vlan_operation_tagged {
934         UCC_GETH_VLAN_OPERATION_TAGGED_NOP = 0x0,       /* Tagged - nop */
935         UCC_GETH_VLAN_OPERATION_TAGGED_REPLACE_VID_PORTION_OF_Q_TAG
936                 = 0x1,  /* Tagged - replace vid portion of q tag */
937         UCC_GETH_VLAN_OPERATION_TAGGED_IF_VID0_REPLACE_VID_WITH_DEFAULT_VALUE
938                 = 0x2,  /* Tagged - if vid0 replace vid with default value  */
939         UCC_GETH_VLAN_OPERATION_TAGGED_EXTRACT_Q_TAG_FROM_FRAME
940                 = 0x3   /* Tagged - extract q tag from frame */
941 };
942
943 /* UCC GETH vlan operation non-tagged */
944 enum ucc_geth_vlan_operation_non_tagged {
945         UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP = 0x0,   /* Non tagged - nop */
946         UCC_GETH_VLAN_OPERATION_NON_TAGGED_Q_TAG_INSERT = 0x1   /* Non tagged -
947                                                                    q tag insert
948                                                                  */
949 };
950
951 /* UCC GETH Rx Quality of Service Mode */
952 enum ucc_geth_qos_mode {
953         UCC_GETH_QOS_MODE_DEFAULT = 0x0,        /* default queue */
954         UCC_GETH_QOS_MODE_QUEUE_NUM_FROM_L2_CRITERIA = 0x1,     /* queue
955                                                                    determined
956                                                                    by L2
957                                                                    criteria */
958         UCC_GETH_QOS_MODE_QUEUE_NUM_FROM_L3_CRITERIA = 0x2      /* queue
959                                                                    determined
960                                                                    by L3
961                                                                    criteria */
962 };
963
964 /* UCC GETH Statistics Gathering Mode - These are bit flags, 'or' them together
965    for combined functionality */
966 enum ucc_geth_statistics_gathering_mode {
967         UCC_GETH_STATISTICS_GATHERING_MODE_NONE = 0x00000000,   /* No
968                                                                    statistics
969                                                                    gathering */
970         UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE = 0x00000001,/* Enable
971                                                                     hardware
972                                                                     statistics
973                                                                     gathering
974                                                                   */
975         UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX = 0x00000004,/*Enable
976                                                                       firmware
977                                                                       tx
978                                                                       statistics
979                                                                       gathering
980                                                                      */
981         UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX = 0x00000008/* Enable
982                                                                       firmware
983                                                                       rx
984                                                                       statistics
985                                                                       gathering
986                                                                     */
987 };
988
989 /* UCC GETH Pad and CRC Mode - Note, Padding without CRC is not possible */
990 enum ucc_geth_maccfg2_pad_and_crc_mode {
991         UCC_GETH_PAD_AND_CRC_MODE_NONE
992                 = MACCFG2_PAD_AND_CRC_MODE_NONE,        /* Neither Padding
993                                                            short frames
994                                                            nor CRC */
995         UCC_GETH_PAD_AND_CRC_MODE_CRC_ONLY
996                 = MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY,    /* Append
997                                                            CRC only */
998         UCC_GETH_PAD_AND_CRC_MODE_PAD_AND_CRC =
999             MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC
1000 };
1001
1002 /* UCC GETH upsmr Flow Control Mode */
1003 enum ucc_geth_flow_control_mode {
1004         UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE = 0x00000000,    /* No automatic
1005                                                                    flow control
1006                                                                  */
1007         UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_PAUSE_WHEN_EMERGENCY
1008                 = 0x00004000    /* Send pause frame when RxFIFO reaches its
1009                                    emergency threshold */
1010 };
1011
1012 /* UCC GETH number of threads */
1013 enum ucc_geth_num_of_threads {
1014         UCC_GETH_NUM_OF_THREADS_1 = 0x1,        /* 1 */
1015         UCC_GETH_NUM_OF_THREADS_2 = 0x2,        /* 2 */
1016         UCC_GETH_NUM_OF_THREADS_4 = 0x0,        /* 4 */
1017         UCC_GETH_NUM_OF_THREADS_6 = 0x3,        /* 6 */
1018         UCC_GETH_NUM_OF_THREADS_8 = 0x4 /* 8 */
1019 };
1020
1021 /* UCC GETH number of station addresses */
1022 enum ucc_geth_num_of_station_addresses {
1023         UCC_GETH_NUM_OF_STATION_ADDRESSES_1,    /* 1 */
1024         UCC_GETH_NUM_OF_STATION_ADDRESSES_5     /* 5 */
1025 };
1026
1027 /* UCC GETH 82xx Ethernet Address Container */
1028 struct enet_addr_container {
1029         u8 address[ENET_NUM_OCTETS_PER_ADDRESS];        /* ethernet address */
1030         enum ucc_geth_enet_address_recognition_location location;       /* location in
1031                                                                    82xx address
1032                                                                    recognition
1033                                                                    hardware */
1034         struct list_head node;
1035 };
1036
1037 #define ENET_ADDR_CONT_ENTRY(ptr) list_entry(ptr, struct enet_addr_container, node)
1038
1039 /* UCC GETH Termination Action Descriptor (TAD) structure. */
1040 struct ucc_geth_tad_params {
1041         int rx_non_dynamic_extended_features_mode;
1042         int reject_frame;
1043         enum ucc_geth_vlan_operation_tagged vtag_op;
1044         enum ucc_geth_vlan_operation_non_tagged vnontag_op;
1045         enum ucc_geth_qos_mode rqos;
1046         u8 vpri;
1047         u16 vid;
1048 };
1049
1050 /* GETH protocol initialization structure */
1051 struct ucc_geth_info {
1052         struct ucc_fast_info uf_info;
1053         u8 numQueuesTx;
1054         u8 numQueuesRx;
1055         int ipCheckSumCheck;
1056         int ipCheckSumGenerate;
1057         int rxExtendedFiltering;
1058         u32 extendedFilteringChainPointer;
1059         u16 typeorlen;
1060         int dynamicMaxFrameLength;
1061         int dynamicMinFrameLength;
1062         u8 nonBackToBackIfgPart1;
1063         u8 nonBackToBackIfgPart2;
1064         u8 miminumInterFrameGapEnforcement;
1065         u8 backToBackInterFrameGap;
1066         int ipAddressAlignment;
1067         int lengthCheckRx;
1068         u32 mblinterval;
1069         u16 nortsrbytetime;
1070         u8 fracsiz;
1071         u8 strictpriorityq;
1072         u8 txasap;
1073         u8 extrabw;
1074         int miiPreambleSupress;
1075         u8 altBebTruncation;
1076         int altBeb;
1077         int backPressureNoBackoff;
1078         int noBackoff;
1079         int excessDefer;
1080         u8 maxRetransmission;
1081         u8 collisionWindow;
1082         int pro;
1083         int cap;
1084         int rsh;
1085         int rlpb;
1086         int cam;
1087         int bro;
1088         int ecm;
1089         int receiveFlowControl;
1090         int transmitFlowControl;
1091         u8 maxGroupAddrInHash;
1092         u8 maxIndAddrInHash;
1093         u8 prel;
1094         u16 maxFrameLength;
1095         u16 minFrameLength;
1096         u16 maxD1Length;
1097         u16 maxD2Length;
1098         u16 vlantype;
1099         u16 vlantci;
1100         u32 ecamptr;
1101         u32 eventRegMask;
1102         u16 pausePeriod;
1103         u16 extensionField;
1104         char phy_bus_id[BUS_ID_SIZE];
1105         u8 weightfactor[NUM_TX_QUEUES];
1106         u8 interruptcoalescingmaxvalue[NUM_RX_QUEUES];
1107         u8 l2qt[UCC_GETH_VLAN_PRIORITY_MAX];
1108         u8 l3qt[UCC_GETH_IP_PRIORITY_MAX];
1109         u32 vtagtable[UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX];
1110         u8 iphoffset[TX_IP_OFFSET_ENTRY_MAX];
1111         u16 bdRingLenTx[NUM_TX_QUEUES];
1112         u16 bdRingLenRx[NUM_RX_QUEUES];
1113         enum ucc_geth_num_of_station_addresses numStationAddresses;
1114         enum qe_fltr_largest_external_tbl_lookup_key_size
1115             largestexternallookupkeysize;
1116         enum ucc_geth_statistics_gathering_mode statisticsMode;
1117         enum ucc_geth_vlan_operation_tagged vlanOperationTagged;
1118         enum ucc_geth_vlan_operation_non_tagged vlanOperationNonTagged;
1119         enum ucc_geth_qos_mode rxQoSMode;
1120         enum ucc_geth_flow_control_mode aufc;
1121         enum ucc_geth_maccfg2_pad_and_crc_mode padAndCrc;
1122         enum ucc_geth_num_of_threads numThreadsTx;
1123         enum ucc_geth_num_of_threads numThreadsRx;
1124         enum qe_risc_allocation riscTx;
1125         enum qe_risc_allocation riscRx;
1126 };
1127
1128 /* structure representing UCC GETH */
1129 struct ucc_geth_private {
1130         struct ucc_geth_info *ug_info;
1131         struct ucc_fast_private *uccf;
1132         struct net_device *dev;
1133         struct napi_struct napi;
1134         struct work_struct timeout_work;
1135         struct ucc_geth __iomem *ug_regs;
1136         struct ucc_geth_init_pram *p_init_enet_param_shadow;
1137         struct ucc_geth_exf_global_pram __iomem *p_exf_glbl_param;
1138         u32 exf_glbl_param_offset;
1139         struct ucc_geth_rx_global_pram __iomem *p_rx_glbl_pram;
1140         u32 rx_glbl_pram_offset;
1141         struct ucc_geth_tx_global_pram __iomem *p_tx_glbl_pram;
1142         u32 tx_glbl_pram_offset;
1143         struct ucc_geth_send_queue_mem_region __iomem *p_send_q_mem_reg;
1144         u32 send_q_mem_reg_offset;
1145         struct ucc_geth_thread_data_tx __iomem *p_thread_data_tx;
1146         u32 thread_dat_tx_offset;
1147         struct ucc_geth_thread_data_rx __iomem *p_thread_data_rx;
1148         u32 thread_dat_rx_offset;
1149         struct ucc_geth_scheduler __iomem *p_scheduler;
1150         u32 scheduler_offset;
1151         struct ucc_geth_tx_firmware_statistics_pram __iomem *p_tx_fw_statistics_pram;
1152         u32 tx_fw_statistics_pram_offset;
1153         struct ucc_geth_rx_firmware_statistics_pram __iomem *p_rx_fw_statistics_pram;
1154         u32 rx_fw_statistics_pram_offset;
1155         struct ucc_geth_rx_interrupt_coalescing_table __iomem *p_rx_irq_coalescing_tbl;
1156         u32 rx_irq_coalescing_tbl_offset;
1157         struct ucc_geth_rx_bd_queues_entry __iomem *p_rx_bd_qs_tbl;
1158         u32 rx_bd_qs_tbl_offset;
1159         u8 __iomem *p_tx_bd_ring[NUM_TX_QUEUES];
1160         u32 tx_bd_ring_offset[NUM_TX_QUEUES];
1161         u8 __iomem *p_rx_bd_ring[NUM_RX_QUEUES];
1162         u32 rx_bd_ring_offset[NUM_RX_QUEUES];
1163         u8 __iomem *confBd[NUM_TX_QUEUES];
1164         u8 __iomem *txBd[NUM_TX_QUEUES];
1165         u8 __iomem *rxBd[NUM_RX_QUEUES];
1166         int badFrame[NUM_RX_QUEUES];
1167         u16 cpucount[NUM_TX_QUEUES];
1168         u16 __iomem *p_cpucount[NUM_TX_QUEUES];
1169         int indAddrRegUsed[NUM_OF_PADDRS];
1170         u8 paddr[NUM_OF_PADDRS][ENET_NUM_OCTETS_PER_ADDRESS];   /* ethernet address */
1171         u8 numGroupAddrInHash;
1172         u8 numIndAddrInHash;
1173         u8 numIndAddrInReg;
1174         int rx_extended_features;
1175         int rx_non_dynamic_extended_features;
1176         struct list_head conf_skbs;
1177         struct list_head group_hash_q;
1178         struct list_head ind_hash_q;
1179         u32 saved_uccm;
1180         spinlock_t lock;
1181         /* pointers to arrays of skbuffs for tx and rx */
1182         struct sk_buff **tx_skbuff[NUM_TX_QUEUES];
1183         struct sk_buff **rx_skbuff[NUM_RX_QUEUES];
1184         /* indices pointing to the next free sbk in skb arrays */
1185         u16 skb_curtx[NUM_TX_QUEUES];
1186         u16 skb_currx[NUM_RX_QUEUES];
1187         /* index of the first skb which hasn't been transmitted yet. */
1188         u16 skb_dirtytx[NUM_TX_QUEUES];
1189
1190         struct ugeth_mii_info *mii_info;
1191         struct phy_device *phydev;
1192         phy_interface_t phy_interface;
1193         int max_speed;
1194         uint32_t msg_enable;
1195         int oldspeed;
1196         int oldduplex;
1197         int oldlink;
1198
1199         struct device_node *node;
1200 };
1201
1202 void uec_set_ethtool_ops(struct net_device *netdev);
1203 int init_flow_control_params(u32 automatic_flow_control_mode,
1204                 int rx_flow_control_enable, int tx_flow_control_enable,
1205                 u16 pause_period, u16 extension_field,
1206                 u32 __iomem *upsmr_register, u32 __iomem *uempr_register,
1207                 u32 __iomem *maccfg1_register);
1208
1209
1210 #endif                          /* __UCC_GETH_H__ */