ucc_geth: add ethtool support
[linux-2.6.git] / drivers / net / ucc_geth.c
1 /*
2  * Copyright (C) 2006-2007 Freescale Semicondutor, Inc. All rights reserved.
3  *
4  * Author: Shlomi Gridish <gridish@freescale.com>
5  *         Li Yang <leoli@freescale.com>
6  *
7  * Description:
8  * QE UCC Gigabit Ethernet Driver
9  *
10  * This program is free software; you can redistribute  it and/or modify it
11  * under  the terms of  the GNU General  Public License as published by the
12  * Free Software Foundation;  either version 2 of the  License, or (at your
13  * option) any later version.
14  */
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/slab.h>
19 #include <linux/stddef.h>
20 #include <linux/interrupt.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/skbuff.h>
24 #include <linux/spinlock.h>
25 #include <linux/mm.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/fsl_devices.h>
28 #include <linux/mii.h>
29 #include <linux/phy.h>
30 #include <linux/workqueue.h>
31
32 #include <asm/of_platform.h>
33 #include <asm/uaccess.h>
34 #include <asm/irq.h>
35 #include <asm/io.h>
36 #include <asm/immap_qe.h>
37 #include <asm/qe.h>
38 #include <asm/ucc.h>
39 #include <asm/ucc_fast.h>
40
41 #include "ucc_geth.h"
42 #include "ucc_geth_mii.h"
43
44 #undef DEBUG
45
46 #define ugeth_printk(level, format, arg...)  \
47         printk(level format "\n", ## arg)
48
49 #define ugeth_dbg(format, arg...)            \
50         ugeth_printk(KERN_DEBUG , format , ## arg)
51 #define ugeth_err(format, arg...)            \
52         ugeth_printk(KERN_ERR , format , ## arg)
53 #define ugeth_info(format, arg...)           \
54         ugeth_printk(KERN_INFO , format , ## arg)
55 #define ugeth_warn(format, arg...)           \
56         ugeth_printk(KERN_WARNING , format , ## arg)
57
58 #ifdef UGETH_VERBOSE_DEBUG
59 #define ugeth_vdbg ugeth_dbg
60 #else
61 #define ugeth_vdbg(fmt, args...) do { } while (0)
62 #endif                          /* UGETH_VERBOSE_DEBUG */
63
64 void uec_set_ethtool_ops(struct net_device *netdev);
65         
66 static DEFINE_SPINLOCK(ugeth_lock);
67
68 static struct ucc_geth_info ugeth_primary_info = {
69         .uf_info = {
70                     .bd_mem_part = MEM_PART_SYSTEM,
71                     .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES,
72                     .max_rx_buf_length = 1536,
73                     /* adjusted at startup if max-speed 1000 */
74                     .urfs = UCC_GETH_URFS_INIT,
75                     .urfet = UCC_GETH_URFET_INIT,
76                     .urfset = UCC_GETH_URFSET_INIT,
77                     .utfs = UCC_GETH_UTFS_INIT,
78                     .utfet = UCC_GETH_UTFET_INIT,
79                     .utftt = UCC_GETH_UTFTT_INIT,
80                     .ufpt = 256,
81                     .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET,
82                     .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
83                     .tenc = UCC_FAST_TX_ENCODING_NRZ,
84                     .renc = UCC_FAST_RX_ENCODING_NRZ,
85                     .tcrc = UCC_FAST_16_BIT_CRC,
86                     .synl = UCC_FAST_SYNC_LEN_NOT_USED,
87                     },
88         .numQueuesTx = 1,
89         .numQueuesRx = 1,
90         .extendedFilteringChainPointer = ((uint32_t) NULL),
91         .typeorlen = 3072 /*1536 */ ,
92         .nonBackToBackIfgPart1 = 0x40,
93         .nonBackToBackIfgPart2 = 0x60,
94         .miminumInterFrameGapEnforcement = 0x50,
95         .backToBackInterFrameGap = 0x60,
96         .mblinterval = 128,
97         .nortsrbytetime = 5,
98         .fracsiz = 1,
99         .strictpriorityq = 0xff,
100         .altBebTruncation = 0xa,
101         .excessDefer = 1,
102         .maxRetransmission = 0xf,
103         .collisionWindow = 0x37,
104         .receiveFlowControl = 1,
105         .transmitFlowControl = 1,
106         .maxGroupAddrInHash = 4,
107         .maxIndAddrInHash = 4,
108         .prel = 7,
109         .maxFrameLength = 1518,
110         .minFrameLength = 64,
111         .maxD1Length = 1520,
112         .maxD2Length = 1520,
113         .vlantype = 0x8100,
114         .ecamptr = ((uint32_t) NULL),
115         .eventRegMask = UCCE_OTHER,
116         .pausePeriod = 0xf000,
117         .interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1},
118         .bdRingLenTx = {
119                         TX_BD_RING_LEN,
120                         TX_BD_RING_LEN,
121                         TX_BD_RING_LEN,
122                         TX_BD_RING_LEN,
123                         TX_BD_RING_LEN,
124                         TX_BD_RING_LEN,
125                         TX_BD_RING_LEN,
126                         TX_BD_RING_LEN},
127
128         .bdRingLenRx = {
129                         RX_BD_RING_LEN,
130                         RX_BD_RING_LEN,
131                         RX_BD_RING_LEN,
132                         RX_BD_RING_LEN,
133                         RX_BD_RING_LEN,
134                         RX_BD_RING_LEN,
135                         RX_BD_RING_LEN,
136                         RX_BD_RING_LEN},
137
138         .numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1,
139         .largestexternallookupkeysize =
140             QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE,
141         .statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE |
142                 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX |
143                 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX,
144         .vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP,
145         .vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP,
146         .rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT,
147         .aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE,
148         .padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC,
149         .numThreadsTx = UCC_GETH_NUM_OF_THREADS_4,
150         .numThreadsRx = UCC_GETH_NUM_OF_THREADS_4,
151         .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
152         .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
153 };
154
155 static struct ucc_geth_info ugeth_info[8];
156
157 #ifdef DEBUG
158 static void mem_disp(u8 *addr, int size)
159 {
160         u8 *i;
161         int size16Aling = (size >> 4) << 4;
162         int size4Aling = (size >> 2) << 2;
163         int notAlign = 0;
164         if (size % 16)
165                 notAlign = 1;
166
167         for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16)
168                 printk("0x%08x: %08x %08x %08x %08x\r\n",
169                        (u32) i,
170                        *((u32 *) (i)),
171                        *((u32 *) (i + 4)),
172                        *((u32 *) (i + 8)), *((u32 *) (i + 12)));
173         if (notAlign == 1)
174                 printk("0x%08x: ", (u32) i);
175         for (; (u32) i < (u32) addr + size4Aling; i += 4)
176                 printk("%08x ", *((u32 *) (i)));
177         for (; (u32) i < (u32) addr + size; i++)
178                 printk("%02x", *((u8 *) (i)));
179         if (notAlign == 1)
180                 printk("\r\n");
181 }
182 #endif /* DEBUG */
183
184 #ifdef CONFIG_UGETH_FILTERING
185 static void enqueue(struct list_head *node, struct list_head *lh)
186 {
187         unsigned long flags;
188
189         spin_lock_irqsave(&ugeth_lock, flags);
190         list_add_tail(node, lh);
191         spin_unlock_irqrestore(&ugeth_lock, flags);
192 }
193 #endif /* CONFIG_UGETH_FILTERING */
194
195 static struct list_head *dequeue(struct list_head *lh)
196 {
197         unsigned long flags;
198
199         spin_lock_irqsave(&ugeth_lock, flags);
200         if (!list_empty(lh)) {
201                 struct list_head *node = lh->next;
202                 list_del(node);
203                 spin_unlock_irqrestore(&ugeth_lock, flags);
204                 return node;
205         } else {
206                 spin_unlock_irqrestore(&ugeth_lock, flags);
207                 return NULL;
208         }
209 }
210
211 static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth, u8 *bd)
212 {
213         struct sk_buff *skb = NULL;
214
215         skb = dev_alloc_skb(ugeth->ug_info->uf_info.max_rx_buf_length +
216                                   UCC_GETH_RX_DATA_BUF_ALIGNMENT);
217
218         if (skb == NULL)
219                 return NULL;
220
221         /* We need the data buffer to be aligned properly.  We will reserve
222          * as many bytes as needed to align the data properly
223          */
224         skb_reserve(skb,
225                     UCC_GETH_RX_DATA_BUF_ALIGNMENT -
226                     (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT -
227                                               1)));
228
229         skb->dev = ugeth->dev;
230
231         out_be32(&((struct qe_bd *)bd)->buf,
232                       dma_map_single(NULL,
233                                      skb->data,
234                                      ugeth->ug_info->uf_info.max_rx_buf_length +
235                                      UCC_GETH_RX_DATA_BUF_ALIGNMENT,
236                                      DMA_FROM_DEVICE));
237
238         out_be32((u32 *)bd, (R_E | R_I | (in_be32((u32 *)bd) & R_W)));
239
240         return skb;
241 }
242
243 static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ)
244 {
245         u8 *bd;
246         u32 bd_status;
247         struct sk_buff *skb;
248         int i;
249
250         bd = ugeth->p_rx_bd_ring[rxQ];
251         i = 0;
252
253         do {
254                 bd_status = in_be32((u32*)bd);
255                 skb = get_new_skb(ugeth, bd);
256
257                 if (!skb)       /* If can not allocate data buffer,
258                                 abort. Cleanup will be elsewhere */
259                         return -ENOMEM;
260
261                 ugeth->rx_skbuff[rxQ][i] = skb;
262
263                 /* advance the BD pointer */
264                 bd += sizeof(struct qe_bd);
265                 i++;
266         } while (!(bd_status & R_W));
267
268         return 0;
269 }
270
271 static int fill_init_enet_entries(struct ucc_geth_private *ugeth,
272                                   volatile u32 *p_start,
273                                   u8 num_entries,
274                                   u32 thread_size,
275                                   u32 thread_alignment,
276                                   enum qe_risc_allocation risc,
277                                   int skip_page_for_first_entry)
278 {
279         u32 init_enet_offset;
280         u8 i;
281         int snum;
282
283         for (i = 0; i < num_entries; i++) {
284                 if ((snum = qe_get_snum()) < 0) {
285                         ugeth_err("fill_init_enet_entries: Can not get SNUM.");
286                         return snum;
287                 }
288                 if ((i == 0) && skip_page_for_first_entry)
289                 /* First entry of Rx does not have page */
290                         init_enet_offset = 0;
291                 else {
292                         init_enet_offset =
293                             qe_muram_alloc(thread_size, thread_alignment);
294                         if (IS_ERR_VALUE(init_enet_offset)) {
295                                 ugeth_err
296                 ("fill_init_enet_entries: Can not allocate DPRAM memory.");
297                                 qe_put_snum((u8) snum);
298                                 return -ENOMEM;
299                         }
300                 }
301                 *(p_start++) =
302                     ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset
303                     | risc;
304         }
305
306         return 0;
307 }
308
309 static int return_init_enet_entries(struct ucc_geth_private *ugeth,
310                                     volatile u32 *p_start,
311                                     u8 num_entries,
312                                     enum qe_risc_allocation risc,
313                                     int skip_page_for_first_entry)
314 {
315         u32 init_enet_offset;
316         u8 i;
317         int snum;
318
319         for (i = 0; i < num_entries; i++) {
320                 /* Check that this entry was actually valid --
321                 needed in case failed in allocations */
322                 if ((*p_start & ENET_INIT_PARAM_RISC_MASK) == risc) {
323                         snum =
324                             (u32) (*p_start & ENET_INIT_PARAM_SNUM_MASK) >>
325                             ENET_INIT_PARAM_SNUM_SHIFT;
326                         qe_put_snum((u8) snum);
327                         if (!((i == 0) && skip_page_for_first_entry)) {
328                         /* First entry of Rx does not have page */
329                                 init_enet_offset =
330                                     (in_be32(p_start) &
331                                      ENET_INIT_PARAM_PTR_MASK);
332                                 qe_muram_free(init_enet_offset);
333                         }
334                         *(p_start++) = 0;       /* Just for cosmetics */
335                 }
336         }
337
338         return 0;
339 }
340
341 #ifdef DEBUG
342 static int dump_init_enet_entries(struct ucc_geth_private *ugeth,
343                                   volatile u32 *p_start,
344                                   u8 num_entries,
345                                   u32 thread_size,
346                                   enum qe_risc_allocation risc,
347                                   int skip_page_for_first_entry)
348 {
349         u32 init_enet_offset;
350         u8 i;
351         int snum;
352
353         for (i = 0; i < num_entries; i++) {
354                 /* Check that this entry was actually valid --
355                 needed in case failed in allocations */
356                 if ((*p_start & ENET_INIT_PARAM_RISC_MASK) == risc) {
357                         snum =
358                             (u32) (*p_start & ENET_INIT_PARAM_SNUM_MASK) >>
359                             ENET_INIT_PARAM_SNUM_SHIFT;
360                         qe_put_snum((u8) snum);
361                         if (!((i == 0) && skip_page_for_first_entry)) {
362                         /* First entry of Rx does not have page */
363                                 init_enet_offset =
364                                     (in_be32(p_start) &
365                                      ENET_INIT_PARAM_PTR_MASK);
366                                 ugeth_info("Init enet entry %d:", i);
367                                 ugeth_info("Base address: 0x%08x",
368                                            (u32)
369                                            qe_muram_addr(init_enet_offset));
370                                 mem_disp(qe_muram_addr(init_enet_offset),
371                                          thread_size);
372                         }
373                         p_start++;
374                 }
375         }
376
377         return 0;
378 }
379 #endif
380
381 #ifdef CONFIG_UGETH_FILTERING
382 static struct enet_addr_container *get_enet_addr_container(void)
383 {
384         struct enet_addr_container *enet_addr_cont;
385
386         /* allocate memory */
387         enet_addr_cont = kmalloc(sizeof(struct enet_addr_container), GFP_KERNEL);
388         if (!enet_addr_cont) {
389                 ugeth_err("%s: No memory for enet_addr_container object.",
390                           __FUNCTION__);
391                 return NULL;
392         }
393
394         return enet_addr_cont;
395 }
396 #endif /* CONFIG_UGETH_FILTERING */
397
398 static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont)
399 {
400         kfree(enet_addr_cont);
401 }
402
403 static void set_mac_addr(__be16 __iomem *reg, u8 *mac)
404 {
405         out_be16(&reg[0], ((u16)mac[5] << 8) | mac[4]);
406         out_be16(&reg[1], ((u16)mac[3] << 8) | mac[2]);
407         out_be16(&reg[2], ((u16)mac[1] << 8) | mac[0]);
408 }
409
410 #ifdef CONFIG_UGETH_FILTERING
411 static int hw_add_addr_in_paddr(struct ucc_geth_private *ugeth,
412                                 u8 *p_enet_addr, u8 paddr_num)
413 {
414         struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
415
416         if (!(paddr_num < NUM_OF_PADDRS)) {
417                 ugeth_warn("%s: Illegal paddr_num.", __FUNCTION__);
418                 return -EINVAL;
419         }
420
421         p_82xx_addr_filt =
422             (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
423             addressfiltering;
424
425         /* Ethernet frames are defined in Little Endian mode,    */
426         /* therefore to insert the address we reverse the bytes. */
427         set_mac_addr(&p_82xx_addr_filt->paddr[paddr_num].h, p_enet_addr);
428         return 0;
429 }
430 #endif /* CONFIG_UGETH_FILTERING */
431
432 static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num)
433 {
434         struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
435
436         if (!(paddr_num < NUM_OF_PADDRS)) {
437                 ugeth_warn("%s: Illagel paddr_num.", __FUNCTION__);
438                 return -EINVAL;
439         }
440
441         p_82xx_addr_filt =
442             (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
443             addressfiltering;
444
445         /* Writing address ff.ff.ff.ff.ff.ff disables address
446         recognition for this register */
447         out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff);
448         out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff);
449         out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff);
450
451         return 0;
452 }
453
454 static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth,
455                                 u8 *p_enet_addr)
456 {
457         struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
458         u32 cecr_subblock;
459
460         p_82xx_addr_filt =
461             (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
462             addressfiltering;
463
464         cecr_subblock =
465             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
466
467         /* Ethernet frames are defined in Little Endian mode,
468         therefor to insert */
469         /* the address to the hash (Big Endian mode), we reverse the bytes.*/
470
471         set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr);
472
473         qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock,
474                      QE_CR_PROTOCOL_ETHERNET, 0);
475 }
476
477 #ifdef CONFIG_UGETH_MAGIC_PACKET
478 static void magic_packet_detection_enable(struct ucc_geth_private *ugeth)
479 {
480         struct ucc_fast_private *uccf;
481         struct ucc_geth *ug_regs;
482         u32 maccfg2, uccm;
483
484         uccf = ugeth->uccf;
485         ug_regs = ugeth->ug_regs;
486
487         /* Enable interrupts for magic packet detection */
488         uccm = in_be32(uccf->p_uccm);
489         uccm |= UCCE_MPD;
490         out_be32(uccf->p_uccm, uccm);
491
492         /* Enable magic packet detection */
493         maccfg2 = in_be32(&ug_regs->maccfg2);
494         maccfg2 |= MACCFG2_MPE;
495         out_be32(&ug_regs->maccfg2, maccfg2);
496 }
497
498 static void magic_packet_detection_disable(struct ucc_geth_private *ugeth)
499 {
500         struct ucc_fast_private *uccf;
501         struct ucc_geth *ug_regs;
502         u32 maccfg2, uccm;
503
504         uccf = ugeth->uccf;
505         ug_regs = ugeth->ug_regs;
506
507         /* Disable interrupts for magic packet detection */
508         uccm = in_be32(uccf->p_uccm);
509         uccm &= ~UCCE_MPD;
510         out_be32(uccf->p_uccm, uccm);
511
512         /* Disable magic packet detection */
513         maccfg2 = in_be32(&ug_regs->maccfg2);
514         maccfg2 &= ~MACCFG2_MPE;
515         out_be32(&ug_regs->maccfg2, maccfg2);
516 }
517 #endif /* MAGIC_PACKET */
518
519 static inline int compare_addr(u8 **addr1, u8 **addr2)
520 {
521         return memcmp(addr1, addr2, ENET_NUM_OCTETS_PER_ADDRESS);
522 }
523
524 #ifdef DEBUG
525 static void get_statistics(struct ucc_geth_private *ugeth,
526                            struct ucc_geth_tx_firmware_statistics *
527                            tx_firmware_statistics,
528                            struct ucc_geth_rx_firmware_statistics *
529                            rx_firmware_statistics,
530                            struct ucc_geth_hardware_statistics *hardware_statistics)
531 {
532         struct ucc_fast *uf_regs;
533         struct ucc_geth *ug_regs;
534         struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram;
535         struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram;
536
537         ug_regs = ugeth->ug_regs;
538         uf_regs = (struct ucc_fast *) ug_regs;
539         p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram;
540         p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram;
541
542         /* Tx firmware only if user handed pointer and driver actually
543         gathers Tx firmware statistics */
544         if (tx_firmware_statistics && p_tx_fw_statistics_pram) {
545                 tx_firmware_statistics->sicoltx =
546                     in_be32(&p_tx_fw_statistics_pram->sicoltx);
547                 tx_firmware_statistics->mulcoltx =
548                     in_be32(&p_tx_fw_statistics_pram->mulcoltx);
549                 tx_firmware_statistics->latecoltxfr =
550                     in_be32(&p_tx_fw_statistics_pram->latecoltxfr);
551                 tx_firmware_statistics->frabortduecol =
552                     in_be32(&p_tx_fw_statistics_pram->frabortduecol);
553                 tx_firmware_statistics->frlostinmactxer =
554                     in_be32(&p_tx_fw_statistics_pram->frlostinmactxer);
555                 tx_firmware_statistics->carriersenseertx =
556                     in_be32(&p_tx_fw_statistics_pram->carriersenseertx);
557                 tx_firmware_statistics->frtxok =
558                     in_be32(&p_tx_fw_statistics_pram->frtxok);
559                 tx_firmware_statistics->txfrexcessivedefer =
560                     in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer);
561                 tx_firmware_statistics->txpkts256 =
562                     in_be32(&p_tx_fw_statistics_pram->txpkts256);
563                 tx_firmware_statistics->txpkts512 =
564                     in_be32(&p_tx_fw_statistics_pram->txpkts512);
565                 tx_firmware_statistics->txpkts1024 =
566                     in_be32(&p_tx_fw_statistics_pram->txpkts1024);
567                 tx_firmware_statistics->txpktsjumbo =
568                     in_be32(&p_tx_fw_statistics_pram->txpktsjumbo);
569         }
570
571         /* Rx firmware only if user handed pointer and driver actually
572          * gathers Rx firmware statistics */
573         if (rx_firmware_statistics && p_rx_fw_statistics_pram) {
574                 int i;
575                 rx_firmware_statistics->frrxfcser =
576                     in_be32(&p_rx_fw_statistics_pram->frrxfcser);
577                 rx_firmware_statistics->fraligner =
578                     in_be32(&p_rx_fw_statistics_pram->fraligner);
579                 rx_firmware_statistics->inrangelenrxer =
580                     in_be32(&p_rx_fw_statistics_pram->inrangelenrxer);
581                 rx_firmware_statistics->outrangelenrxer =
582                     in_be32(&p_rx_fw_statistics_pram->outrangelenrxer);
583                 rx_firmware_statistics->frtoolong =
584                     in_be32(&p_rx_fw_statistics_pram->frtoolong);
585                 rx_firmware_statistics->runt =
586                     in_be32(&p_rx_fw_statistics_pram->runt);
587                 rx_firmware_statistics->verylongevent =
588                     in_be32(&p_rx_fw_statistics_pram->verylongevent);
589                 rx_firmware_statistics->symbolerror =
590                     in_be32(&p_rx_fw_statistics_pram->symbolerror);
591                 rx_firmware_statistics->dropbsy =
592                     in_be32(&p_rx_fw_statistics_pram->dropbsy);
593                 for (i = 0; i < 0x8; i++)
594                         rx_firmware_statistics->res0[i] =
595                             p_rx_fw_statistics_pram->res0[i];
596                 rx_firmware_statistics->mismatchdrop =
597                     in_be32(&p_rx_fw_statistics_pram->mismatchdrop);
598                 rx_firmware_statistics->underpkts =
599                     in_be32(&p_rx_fw_statistics_pram->underpkts);
600                 rx_firmware_statistics->pkts256 =
601                     in_be32(&p_rx_fw_statistics_pram->pkts256);
602                 rx_firmware_statistics->pkts512 =
603                     in_be32(&p_rx_fw_statistics_pram->pkts512);
604                 rx_firmware_statistics->pkts1024 =
605                     in_be32(&p_rx_fw_statistics_pram->pkts1024);
606                 rx_firmware_statistics->pktsjumbo =
607                     in_be32(&p_rx_fw_statistics_pram->pktsjumbo);
608                 rx_firmware_statistics->frlossinmacer =
609                     in_be32(&p_rx_fw_statistics_pram->frlossinmacer);
610                 rx_firmware_statistics->pausefr =
611                     in_be32(&p_rx_fw_statistics_pram->pausefr);
612                 for (i = 0; i < 0x4; i++)
613                         rx_firmware_statistics->res1[i] =
614                             p_rx_fw_statistics_pram->res1[i];
615                 rx_firmware_statistics->removevlan =
616                     in_be32(&p_rx_fw_statistics_pram->removevlan);
617                 rx_firmware_statistics->replacevlan =
618                     in_be32(&p_rx_fw_statistics_pram->replacevlan);
619                 rx_firmware_statistics->insertvlan =
620                     in_be32(&p_rx_fw_statistics_pram->insertvlan);
621         }
622
623         /* Hardware only if user handed pointer and driver actually
624         gathers hardware statistics */
625         if (hardware_statistics && (in_be32(&uf_regs->upsmr) & UPSMR_HSE)) {
626                 hardware_statistics->tx64 = in_be32(&ug_regs->tx64);
627                 hardware_statistics->tx127 = in_be32(&ug_regs->tx127);
628                 hardware_statistics->tx255 = in_be32(&ug_regs->tx255);
629                 hardware_statistics->rx64 = in_be32(&ug_regs->rx64);
630                 hardware_statistics->rx127 = in_be32(&ug_regs->rx127);
631                 hardware_statistics->rx255 = in_be32(&ug_regs->rx255);
632                 hardware_statistics->txok = in_be32(&ug_regs->txok);
633                 hardware_statistics->txcf = in_be16(&ug_regs->txcf);
634                 hardware_statistics->tmca = in_be32(&ug_regs->tmca);
635                 hardware_statistics->tbca = in_be32(&ug_regs->tbca);
636                 hardware_statistics->rxfok = in_be32(&ug_regs->rxfok);
637                 hardware_statistics->rxbok = in_be32(&ug_regs->rxbok);
638                 hardware_statistics->rbyt = in_be32(&ug_regs->rbyt);
639                 hardware_statistics->rmca = in_be32(&ug_regs->rmca);
640                 hardware_statistics->rbca = in_be32(&ug_regs->rbca);
641         }
642 }
643
644 static void dump_bds(struct ucc_geth_private *ugeth)
645 {
646         int i;
647         int length;
648
649         for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
650                 if (ugeth->p_tx_bd_ring[i]) {
651                         length =
652                             (ugeth->ug_info->bdRingLenTx[i] *
653                              sizeof(struct qe_bd));
654                         ugeth_info("TX BDs[%d]", i);
655                         mem_disp(ugeth->p_tx_bd_ring[i], length);
656                 }
657         }
658         for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
659                 if (ugeth->p_rx_bd_ring[i]) {
660                         length =
661                             (ugeth->ug_info->bdRingLenRx[i] *
662                              sizeof(struct qe_bd));
663                         ugeth_info("RX BDs[%d]", i);
664                         mem_disp(ugeth->p_rx_bd_ring[i], length);
665                 }
666         }
667 }
668
669 static void dump_regs(struct ucc_geth_private *ugeth)
670 {
671         int i;
672
673         ugeth_info("UCC%d Geth registers:", ugeth->ug_info->uf_info.ucc_num);
674         ugeth_info("Base address: 0x%08x", (u32) ugeth->ug_regs);
675
676         ugeth_info("maccfg1    : addr - 0x%08x, val - 0x%08x",
677                    (u32) & ugeth->ug_regs->maccfg1,
678                    in_be32(&ugeth->ug_regs->maccfg1));
679         ugeth_info("maccfg2    : addr - 0x%08x, val - 0x%08x",
680                    (u32) & ugeth->ug_regs->maccfg2,
681                    in_be32(&ugeth->ug_regs->maccfg2));
682         ugeth_info("ipgifg     : addr - 0x%08x, val - 0x%08x",
683                    (u32) & ugeth->ug_regs->ipgifg,
684                    in_be32(&ugeth->ug_regs->ipgifg));
685         ugeth_info("hafdup     : addr - 0x%08x, val - 0x%08x",
686                    (u32) & ugeth->ug_regs->hafdup,
687                    in_be32(&ugeth->ug_regs->hafdup));
688         ugeth_info("ifctl      : addr - 0x%08x, val - 0x%08x",
689                    (u32) & ugeth->ug_regs->ifctl,
690                    in_be32(&ugeth->ug_regs->ifctl));
691         ugeth_info("ifstat     : addr - 0x%08x, val - 0x%08x",
692                    (u32) & ugeth->ug_regs->ifstat,
693                    in_be32(&ugeth->ug_regs->ifstat));
694         ugeth_info("macstnaddr1: addr - 0x%08x, val - 0x%08x",
695                    (u32) & ugeth->ug_regs->macstnaddr1,
696                    in_be32(&ugeth->ug_regs->macstnaddr1));
697         ugeth_info("macstnaddr2: addr - 0x%08x, val - 0x%08x",
698                    (u32) & ugeth->ug_regs->macstnaddr2,
699                    in_be32(&ugeth->ug_regs->macstnaddr2));
700         ugeth_info("uempr      : addr - 0x%08x, val - 0x%08x",
701                    (u32) & ugeth->ug_regs->uempr,
702                    in_be32(&ugeth->ug_regs->uempr));
703         ugeth_info("utbipar    : addr - 0x%08x, val - 0x%08x",
704                    (u32) & ugeth->ug_regs->utbipar,
705                    in_be32(&ugeth->ug_regs->utbipar));
706         ugeth_info("uescr      : addr - 0x%08x, val - 0x%04x",
707                    (u32) & ugeth->ug_regs->uescr,
708                    in_be16(&ugeth->ug_regs->uescr));
709         ugeth_info("tx64       : addr - 0x%08x, val - 0x%08x",
710                    (u32) & ugeth->ug_regs->tx64,
711                    in_be32(&ugeth->ug_regs->tx64));
712         ugeth_info("tx127      : addr - 0x%08x, val - 0x%08x",
713                    (u32) & ugeth->ug_regs->tx127,
714                    in_be32(&ugeth->ug_regs->tx127));
715         ugeth_info("tx255      : addr - 0x%08x, val - 0x%08x",
716                    (u32) & ugeth->ug_regs->tx255,
717                    in_be32(&ugeth->ug_regs->tx255));
718         ugeth_info("rx64       : addr - 0x%08x, val - 0x%08x",
719                    (u32) & ugeth->ug_regs->rx64,
720                    in_be32(&ugeth->ug_regs->rx64));
721         ugeth_info("rx127      : addr - 0x%08x, val - 0x%08x",
722                    (u32) & ugeth->ug_regs->rx127,
723                    in_be32(&ugeth->ug_regs->rx127));
724         ugeth_info("rx255      : addr - 0x%08x, val - 0x%08x",
725                    (u32) & ugeth->ug_regs->rx255,
726                    in_be32(&ugeth->ug_regs->rx255));
727         ugeth_info("txok       : addr - 0x%08x, val - 0x%08x",
728                    (u32) & ugeth->ug_regs->txok,
729                    in_be32(&ugeth->ug_regs->txok));
730         ugeth_info("txcf       : addr - 0x%08x, val - 0x%04x",
731                    (u32) & ugeth->ug_regs->txcf,
732                    in_be16(&ugeth->ug_regs->txcf));
733         ugeth_info("tmca       : addr - 0x%08x, val - 0x%08x",
734                    (u32) & ugeth->ug_regs->tmca,
735                    in_be32(&ugeth->ug_regs->tmca));
736         ugeth_info("tbca       : addr - 0x%08x, val - 0x%08x",
737                    (u32) & ugeth->ug_regs->tbca,
738                    in_be32(&ugeth->ug_regs->tbca));
739         ugeth_info("rxfok      : addr - 0x%08x, val - 0x%08x",
740                    (u32) & ugeth->ug_regs->rxfok,
741                    in_be32(&ugeth->ug_regs->rxfok));
742         ugeth_info("rxbok      : addr - 0x%08x, val - 0x%08x",
743                    (u32) & ugeth->ug_regs->rxbok,
744                    in_be32(&ugeth->ug_regs->rxbok));
745         ugeth_info("rbyt       : addr - 0x%08x, val - 0x%08x",
746                    (u32) & ugeth->ug_regs->rbyt,
747                    in_be32(&ugeth->ug_regs->rbyt));
748         ugeth_info("rmca       : addr - 0x%08x, val - 0x%08x",
749                    (u32) & ugeth->ug_regs->rmca,
750                    in_be32(&ugeth->ug_regs->rmca));
751         ugeth_info("rbca       : addr - 0x%08x, val - 0x%08x",
752                    (u32) & ugeth->ug_regs->rbca,
753                    in_be32(&ugeth->ug_regs->rbca));
754         ugeth_info("scar       : addr - 0x%08x, val - 0x%08x",
755                    (u32) & ugeth->ug_regs->scar,
756                    in_be32(&ugeth->ug_regs->scar));
757         ugeth_info("scam       : addr - 0x%08x, val - 0x%08x",
758                    (u32) & ugeth->ug_regs->scam,
759                    in_be32(&ugeth->ug_regs->scam));
760
761         if (ugeth->p_thread_data_tx) {
762                 int numThreadsTxNumerical;
763                 switch (ugeth->ug_info->numThreadsTx) {
764                 case UCC_GETH_NUM_OF_THREADS_1:
765                         numThreadsTxNumerical = 1;
766                         break;
767                 case UCC_GETH_NUM_OF_THREADS_2:
768                         numThreadsTxNumerical = 2;
769                         break;
770                 case UCC_GETH_NUM_OF_THREADS_4:
771                         numThreadsTxNumerical = 4;
772                         break;
773                 case UCC_GETH_NUM_OF_THREADS_6:
774                         numThreadsTxNumerical = 6;
775                         break;
776                 case UCC_GETH_NUM_OF_THREADS_8:
777                         numThreadsTxNumerical = 8;
778                         break;
779                 default:
780                         numThreadsTxNumerical = 0;
781                         break;
782                 }
783
784                 ugeth_info("Thread data TXs:");
785                 ugeth_info("Base address: 0x%08x",
786                            (u32) ugeth->p_thread_data_tx);
787                 for (i = 0; i < numThreadsTxNumerical; i++) {
788                         ugeth_info("Thread data TX[%d]:", i);
789                         ugeth_info("Base address: 0x%08x",
790                                    (u32) & ugeth->p_thread_data_tx[i]);
791                         mem_disp((u8 *) & ugeth->p_thread_data_tx[i],
792                                  sizeof(struct ucc_geth_thread_data_tx));
793                 }
794         }
795         if (ugeth->p_thread_data_rx) {
796                 int numThreadsRxNumerical;
797                 switch (ugeth->ug_info->numThreadsRx) {
798                 case UCC_GETH_NUM_OF_THREADS_1:
799                         numThreadsRxNumerical = 1;
800                         break;
801                 case UCC_GETH_NUM_OF_THREADS_2:
802                         numThreadsRxNumerical = 2;
803                         break;
804                 case UCC_GETH_NUM_OF_THREADS_4:
805                         numThreadsRxNumerical = 4;
806                         break;
807                 case UCC_GETH_NUM_OF_THREADS_6:
808                         numThreadsRxNumerical = 6;
809                         break;
810                 case UCC_GETH_NUM_OF_THREADS_8:
811                         numThreadsRxNumerical = 8;
812                         break;
813                 default:
814                         numThreadsRxNumerical = 0;
815                         break;
816                 }
817
818                 ugeth_info("Thread data RX:");
819                 ugeth_info("Base address: 0x%08x",
820                            (u32) ugeth->p_thread_data_rx);
821                 for (i = 0; i < numThreadsRxNumerical; i++) {
822                         ugeth_info("Thread data RX[%d]:", i);
823                         ugeth_info("Base address: 0x%08x",
824                                    (u32) & ugeth->p_thread_data_rx[i]);
825                         mem_disp((u8 *) & ugeth->p_thread_data_rx[i],
826                                  sizeof(struct ucc_geth_thread_data_rx));
827                 }
828         }
829         if (ugeth->p_exf_glbl_param) {
830                 ugeth_info("EXF global param:");
831                 ugeth_info("Base address: 0x%08x",
832                            (u32) ugeth->p_exf_glbl_param);
833                 mem_disp((u8 *) ugeth->p_exf_glbl_param,
834                          sizeof(*ugeth->p_exf_glbl_param));
835         }
836         if (ugeth->p_tx_glbl_pram) {
837                 ugeth_info("TX global param:");
838                 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_tx_glbl_pram);
839                 ugeth_info("temoder      : addr - 0x%08x, val - 0x%04x",
840                            (u32) & ugeth->p_tx_glbl_pram->temoder,
841                            in_be16(&ugeth->p_tx_glbl_pram->temoder));
842                 ugeth_info("sqptr        : addr - 0x%08x, val - 0x%08x",
843                            (u32) & ugeth->p_tx_glbl_pram->sqptr,
844                            in_be32(&ugeth->p_tx_glbl_pram->sqptr));
845                 ugeth_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x",
846                            (u32) & ugeth->p_tx_glbl_pram->schedulerbasepointer,
847                            in_be32(&ugeth->p_tx_glbl_pram->
848                                    schedulerbasepointer));
849                 ugeth_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x",
850                            (u32) & ugeth->p_tx_glbl_pram->txrmonbaseptr,
851                            in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr));
852                 ugeth_info("tstate       : addr - 0x%08x, val - 0x%08x",
853                            (u32) & ugeth->p_tx_glbl_pram->tstate,
854                            in_be32(&ugeth->p_tx_glbl_pram->tstate));
855                 ugeth_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x",
856                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[0],
857                            ugeth->p_tx_glbl_pram->iphoffset[0]);
858                 ugeth_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x",
859                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[1],
860                            ugeth->p_tx_glbl_pram->iphoffset[1]);
861                 ugeth_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x",
862                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[2],
863                            ugeth->p_tx_glbl_pram->iphoffset[2]);
864                 ugeth_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x",
865                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[3],
866                            ugeth->p_tx_glbl_pram->iphoffset[3]);
867                 ugeth_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x",
868                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[4],
869                            ugeth->p_tx_glbl_pram->iphoffset[4]);
870                 ugeth_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x",
871                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[5],
872                            ugeth->p_tx_glbl_pram->iphoffset[5]);
873                 ugeth_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x",
874                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[6],
875                            ugeth->p_tx_glbl_pram->iphoffset[6]);
876                 ugeth_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x",
877                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[7],
878                            ugeth->p_tx_glbl_pram->iphoffset[7]);
879                 ugeth_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x",
880                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[0],
881                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0]));
882                 ugeth_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x",
883                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[1],
884                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1]));
885                 ugeth_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x",
886                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[2],
887                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2]));
888                 ugeth_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x",
889                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[3],
890                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3]));
891                 ugeth_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x",
892                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[4],
893                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4]));
894                 ugeth_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x",
895                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[5],
896                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5]));
897                 ugeth_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x",
898                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[6],
899                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6]));
900                 ugeth_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x",
901                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[7],
902                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7]));
903                 ugeth_info("tqptr        : addr - 0x%08x, val - 0x%08x",
904                            (u32) & ugeth->p_tx_glbl_pram->tqptr,
905                            in_be32(&ugeth->p_tx_glbl_pram->tqptr));
906         }
907         if (ugeth->p_rx_glbl_pram) {
908                 ugeth_info("RX global param:");
909                 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_glbl_pram);
910                 ugeth_info("remoder         : addr - 0x%08x, val - 0x%08x",
911                            (u32) & ugeth->p_rx_glbl_pram->remoder,
912                            in_be32(&ugeth->p_rx_glbl_pram->remoder));
913                 ugeth_info("rqptr           : addr - 0x%08x, val - 0x%08x",
914                            (u32) & ugeth->p_rx_glbl_pram->rqptr,
915                            in_be32(&ugeth->p_rx_glbl_pram->rqptr));
916                 ugeth_info("typeorlen       : addr - 0x%08x, val - 0x%04x",
917                            (u32) & ugeth->p_rx_glbl_pram->typeorlen,
918                            in_be16(&ugeth->p_rx_glbl_pram->typeorlen));
919                 ugeth_info("rxgstpack       : addr - 0x%08x, val - 0x%02x",
920                            (u32) & ugeth->p_rx_glbl_pram->rxgstpack,
921                            ugeth->p_rx_glbl_pram->rxgstpack);
922                 ugeth_info("rxrmonbaseptr   : addr - 0x%08x, val - 0x%08x",
923                            (u32) & ugeth->p_rx_glbl_pram->rxrmonbaseptr,
924                            in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr));
925                 ugeth_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x",
926                            (u32) & ugeth->p_rx_glbl_pram->intcoalescingptr,
927                            in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr));
928                 ugeth_info("rstate          : addr - 0x%08x, val - 0x%02x",
929                            (u32) & ugeth->p_rx_glbl_pram->rstate,
930                            ugeth->p_rx_glbl_pram->rstate);
931                 ugeth_info("mrblr           : addr - 0x%08x, val - 0x%04x",
932                            (u32) & ugeth->p_rx_glbl_pram->mrblr,
933                            in_be16(&ugeth->p_rx_glbl_pram->mrblr));
934                 ugeth_info("rbdqptr         : addr - 0x%08x, val - 0x%08x",
935                            (u32) & ugeth->p_rx_glbl_pram->rbdqptr,
936                            in_be32(&ugeth->p_rx_glbl_pram->rbdqptr));
937                 ugeth_info("mflr            : addr - 0x%08x, val - 0x%04x",
938                            (u32) & ugeth->p_rx_glbl_pram->mflr,
939                            in_be16(&ugeth->p_rx_glbl_pram->mflr));
940                 ugeth_info("minflr          : addr - 0x%08x, val - 0x%04x",
941                            (u32) & ugeth->p_rx_glbl_pram->minflr,
942                            in_be16(&ugeth->p_rx_glbl_pram->minflr));
943                 ugeth_info("maxd1           : addr - 0x%08x, val - 0x%04x",
944                            (u32) & ugeth->p_rx_glbl_pram->maxd1,
945                            in_be16(&ugeth->p_rx_glbl_pram->maxd1));
946                 ugeth_info("maxd2           : addr - 0x%08x, val - 0x%04x",
947                            (u32) & ugeth->p_rx_glbl_pram->maxd2,
948                            in_be16(&ugeth->p_rx_glbl_pram->maxd2));
949                 ugeth_info("ecamptr         : addr - 0x%08x, val - 0x%08x",
950                            (u32) & ugeth->p_rx_glbl_pram->ecamptr,
951                            in_be32(&ugeth->p_rx_glbl_pram->ecamptr));
952                 ugeth_info("l2qt            : addr - 0x%08x, val - 0x%08x",
953                            (u32) & ugeth->p_rx_glbl_pram->l2qt,
954                            in_be32(&ugeth->p_rx_glbl_pram->l2qt));
955                 ugeth_info("l3qt[0]         : addr - 0x%08x, val - 0x%08x",
956                            (u32) & ugeth->p_rx_glbl_pram->l3qt[0],
957                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[0]));
958                 ugeth_info("l3qt[1]         : addr - 0x%08x, val - 0x%08x",
959                            (u32) & ugeth->p_rx_glbl_pram->l3qt[1],
960                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[1]));
961                 ugeth_info("l3qt[2]         : addr - 0x%08x, val - 0x%08x",
962                            (u32) & ugeth->p_rx_glbl_pram->l3qt[2],
963                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[2]));
964                 ugeth_info("l3qt[3]         : addr - 0x%08x, val - 0x%08x",
965                            (u32) & ugeth->p_rx_glbl_pram->l3qt[3],
966                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[3]));
967                 ugeth_info("l3qt[4]         : addr - 0x%08x, val - 0x%08x",
968                            (u32) & ugeth->p_rx_glbl_pram->l3qt[4],
969                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[4]));
970                 ugeth_info("l3qt[5]         : addr - 0x%08x, val - 0x%08x",
971                            (u32) & ugeth->p_rx_glbl_pram->l3qt[5],
972                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[5]));
973                 ugeth_info("l3qt[6]         : addr - 0x%08x, val - 0x%08x",
974                            (u32) & ugeth->p_rx_glbl_pram->l3qt[6],
975                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[6]));
976                 ugeth_info("l3qt[7]         : addr - 0x%08x, val - 0x%08x",
977                            (u32) & ugeth->p_rx_glbl_pram->l3qt[7],
978                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[7]));
979                 ugeth_info("vlantype        : addr - 0x%08x, val - 0x%04x",
980                            (u32) & ugeth->p_rx_glbl_pram->vlantype,
981                            in_be16(&ugeth->p_rx_glbl_pram->vlantype));
982                 ugeth_info("vlantci         : addr - 0x%08x, val - 0x%04x",
983                            (u32) & ugeth->p_rx_glbl_pram->vlantci,
984                            in_be16(&ugeth->p_rx_glbl_pram->vlantci));
985                 for (i = 0; i < 64; i++)
986                         ugeth_info
987                     ("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x",
988                              i,
989                              (u32) & ugeth->p_rx_glbl_pram->addressfiltering[i],
990                              ugeth->p_rx_glbl_pram->addressfiltering[i]);
991                 ugeth_info("exfGlobalParam  : addr - 0x%08x, val - 0x%08x",
992                            (u32) & ugeth->p_rx_glbl_pram->exfGlobalParam,
993                            in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam));
994         }
995         if (ugeth->p_send_q_mem_reg) {
996                 ugeth_info("Send Q memory registers:");
997                 ugeth_info("Base address: 0x%08x",
998                            (u32) ugeth->p_send_q_mem_reg);
999                 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
1000                         ugeth_info("SQQD[%d]:", i);
1001                         ugeth_info("Base address: 0x%08x",
1002                                    (u32) & ugeth->p_send_q_mem_reg->sqqd[i]);
1003                         mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i],
1004                                  sizeof(struct ucc_geth_send_queue_qd));
1005                 }
1006         }
1007         if (ugeth->p_scheduler) {
1008                 ugeth_info("Scheduler:");
1009                 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_scheduler);
1010                 mem_disp((u8 *) ugeth->p_scheduler,
1011                          sizeof(*ugeth->p_scheduler));
1012         }
1013         if (ugeth->p_tx_fw_statistics_pram) {
1014                 ugeth_info("TX FW statistics pram:");
1015                 ugeth_info("Base address: 0x%08x",
1016                            (u32) ugeth->p_tx_fw_statistics_pram);
1017                 mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram,
1018                          sizeof(*ugeth->p_tx_fw_statistics_pram));
1019         }
1020         if (ugeth->p_rx_fw_statistics_pram) {
1021                 ugeth_info("RX FW statistics pram:");
1022                 ugeth_info("Base address: 0x%08x",
1023                            (u32) ugeth->p_rx_fw_statistics_pram);
1024                 mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram,
1025                          sizeof(*ugeth->p_rx_fw_statistics_pram));
1026         }
1027         if (ugeth->p_rx_irq_coalescing_tbl) {
1028                 ugeth_info("RX IRQ coalescing tables:");
1029                 ugeth_info("Base address: 0x%08x",
1030                            (u32) ugeth->p_rx_irq_coalescing_tbl);
1031                 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1032                         ugeth_info("RX IRQ coalescing table entry[%d]:", i);
1033                         ugeth_info("Base address: 0x%08x",
1034                                    (u32) & ugeth->p_rx_irq_coalescing_tbl->
1035                                    coalescingentry[i]);
1036                         ugeth_info
1037                 ("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x",
1038                              (u32) & ugeth->p_rx_irq_coalescing_tbl->
1039                              coalescingentry[i].interruptcoalescingmaxvalue,
1040                              in_be32(&ugeth->p_rx_irq_coalescing_tbl->
1041                                      coalescingentry[i].
1042                                      interruptcoalescingmaxvalue));
1043                         ugeth_info
1044                 ("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x",
1045                              (u32) & ugeth->p_rx_irq_coalescing_tbl->
1046                              coalescingentry[i].interruptcoalescingcounter,
1047                              in_be32(&ugeth->p_rx_irq_coalescing_tbl->
1048                                      coalescingentry[i].
1049                                      interruptcoalescingcounter));
1050                 }
1051         }
1052         if (ugeth->p_rx_bd_qs_tbl) {
1053                 ugeth_info("RX BD QS tables:");
1054                 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_bd_qs_tbl);
1055                 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1056                         ugeth_info("RX BD QS table[%d]:", i);
1057                         ugeth_info("Base address: 0x%08x",
1058                                    (u32) & ugeth->p_rx_bd_qs_tbl[i]);
1059                         ugeth_info
1060                             ("bdbaseptr        : addr - 0x%08x, val - 0x%08x",
1061                              (u32) & ugeth->p_rx_bd_qs_tbl[i].bdbaseptr,
1062                              in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr));
1063                         ugeth_info
1064                             ("bdptr            : addr - 0x%08x, val - 0x%08x",
1065                              (u32) & ugeth->p_rx_bd_qs_tbl[i].bdptr,
1066                              in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr));
1067                         ugeth_info
1068                             ("externalbdbaseptr: addr - 0x%08x, val - 0x%08x",
1069                              (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
1070                              in_be32(&ugeth->p_rx_bd_qs_tbl[i].
1071                                      externalbdbaseptr));
1072                         ugeth_info
1073                             ("externalbdptr    : addr - 0x%08x, val - 0x%08x",
1074                              (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdptr,
1075                              in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr));
1076                         ugeth_info("ucode RX Prefetched BDs:");
1077                         ugeth_info("Base address: 0x%08x",
1078                                    (u32)
1079                                    qe_muram_addr(in_be32
1080                                                  (&ugeth->p_rx_bd_qs_tbl[i].
1081                                                   bdbaseptr)));
1082                         mem_disp((u8 *)
1083                                  qe_muram_addr(in_be32
1084                                                (&ugeth->p_rx_bd_qs_tbl[i].
1085                                                 bdbaseptr)),
1086                                  sizeof(struct ucc_geth_rx_prefetched_bds));
1087                 }
1088         }
1089         if (ugeth->p_init_enet_param_shadow) {
1090                 int size;
1091                 ugeth_info("Init enet param shadow:");
1092                 ugeth_info("Base address: 0x%08x",
1093                            (u32) ugeth->p_init_enet_param_shadow);
1094                 mem_disp((u8 *) ugeth->p_init_enet_param_shadow,
1095                          sizeof(*ugeth->p_init_enet_param_shadow));
1096
1097                 size = sizeof(struct ucc_geth_thread_rx_pram);
1098                 if (ugeth->ug_info->rxExtendedFiltering) {
1099                         size +=
1100                             THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
1101                         if (ugeth->ug_info->largestexternallookupkeysize ==
1102                             QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
1103                                 size +=
1104                         THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
1105                         if (ugeth->ug_info->largestexternallookupkeysize ==
1106                             QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
1107                                 size +=
1108                         THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
1109                 }
1110
1111                 dump_init_enet_entries(ugeth,
1112                                        &(ugeth->p_init_enet_param_shadow->
1113                                          txthread[0]),
1114                                        ENET_INIT_PARAM_MAX_ENTRIES_TX,
1115                                        sizeof(struct ucc_geth_thread_tx_pram),
1116                                        ugeth->ug_info->riscTx, 0);
1117                 dump_init_enet_entries(ugeth,
1118                                        &(ugeth->p_init_enet_param_shadow->
1119                                          rxthread[0]),
1120                                        ENET_INIT_PARAM_MAX_ENTRIES_RX, size,
1121                                        ugeth->ug_info->riscRx, 1);
1122         }
1123 }
1124 #endif /* DEBUG */
1125
1126 static void init_default_reg_vals(volatile u32 *upsmr_register,
1127                                   volatile u32 *maccfg1_register,
1128                                   volatile u32 *maccfg2_register)
1129 {
1130         out_be32(upsmr_register, UCC_GETH_UPSMR_INIT);
1131         out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT);
1132         out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT);
1133 }
1134
1135 static int init_half_duplex_params(int alt_beb,
1136                                    int back_pressure_no_backoff,
1137                                    int no_backoff,
1138                                    int excess_defer,
1139                                    u8 alt_beb_truncation,
1140                                    u8 max_retransmissions,
1141                                    u8 collision_window,
1142                                    volatile u32 *hafdup_register)
1143 {
1144         u32 value = 0;
1145
1146         if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) ||
1147             (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) ||
1148             (collision_window > HALFDUP_COLLISION_WINDOW_MAX))
1149                 return -EINVAL;
1150
1151         value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT);
1152
1153         if (alt_beb)
1154                 value |= HALFDUP_ALT_BEB;
1155         if (back_pressure_no_backoff)
1156                 value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF;
1157         if (no_backoff)
1158                 value |= HALFDUP_NO_BACKOFF;
1159         if (excess_defer)
1160                 value |= HALFDUP_EXCESSIVE_DEFER;
1161
1162         value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT);
1163
1164         value |= collision_window;
1165
1166         out_be32(hafdup_register, value);
1167         return 0;
1168 }
1169
1170 static int init_inter_frame_gap_params(u8 non_btb_cs_ipg,
1171                                        u8 non_btb_ipg,
1172                                        u8 min_ifg,
1173                                        u8 btb_ipg,
1174                                        volatile u32 *ipgifg_register)
1175 {
1176         u32 value = 0;
1177
1178         /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back
1179         IPG part 2 */
1180         if (non_btb_cs_ipg > non_btb_ipg)
1181                 return -EINVAL;
1182
1183         if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) ||
1184             (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) ||
1185             /*(min_ifg        > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */
1186             (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX))
1187                 return -EINVAL;
1188
1189         value |=
1190             ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) &
1191              IPGIFG_NBTB_CS_IPG_MASK);
1192         value |=
1193             ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) &
1194              IPGIFG_NBTB_IPG_MASK);
1195         value |=
1196             ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) &
1197              IPGIFG_MIN_IFG_MASK);
1198         value |= (btb_ipg & IPGIFG_BTB_IPG_MASK);
1199
1200         out_be32(ipgifg_register, value);
1201         return 0;
1202 }
1203
1204 int init_flow_control_params(u32 automatic_flow_control_mode,
1205                                     int rx_flow_control_enable,
1206                                     int tx_flow_control_enable,
1207                                     u16 pause_period,
1208                                     u16 extension_field,
1209                                     volatile u32 *upsmr_register,
1210                                     volatile u32 *uempr_register,
1211                                     volatile u32 *maccfg1_register)
1212 {
1213         u32 value = 0;
1214
1215         /* Set UEMPR register */
1216         value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT;
1217         value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT;
1218         out_be32(uempr_register, value);
1219
1220         /* Set UPSMR register */
1221         value = in_be32(upsmr_register);
1222         value |= automatic_flow_control_mode;
1223         out_be32(upsmr_register, value);
1224
1225         value = in_be32(maccfg1_register);
1226         if (rx_flow_control_enable)
1227                 value |= MACCFG1_FLOW_RX;
1228         if (tx_flow_control_enable)
1229                 value |= MACCFG1_FLOW_TX;
1230         out_be32(maccfg1_register, value);
1231
1232         return 0;
1233 }
1234
1235 static int init_hw_statistics_gathering_mode(int enable_hardware_statistics,
1236                                              int auto_zero_hardware_statistics,
1237                                              volatile u32 *upsmr_register,
1238                                              volatile u16 *uescr_register)
1239 {
1240         u32 upsmr_value = 0;
1241         u16 uescr_value = 0;
1242         /* Enable hardware statistics gathering if requested */
1243         if (enable_hardware_statistics) {
1244                 upsmr_value = in_be32(upsmr_register);
1245                 upsmr_value |= UPSMR_HSE;
1246                 out_be32(upsmr_register, upsmr_value);
1247         }
1248
1249         /* Clear hardware statistics counters */
1250         uescr_value = in_be16(uescr_register);
1251         uescr_value |= UESCR_CLRCNT;
1252         /* Automatically zero hardware statistics counters on read,
1253         if requested */
1254         if (auto_zero_hardware_statistics)
1255                 uescr_value |= UESCR_AUTOZ;
1256         out_be16(uescr_register, uescr_value);
1257
1258         return 0;
1259 }
1260
1261 static int init_firmware_statistics_gathering_mode(int
1262                 enable_tx_firmware_statistics,
1263                 int enable_rx_firmware_statistics,
1264                 volatile u32 *tx_rmon_base_ptr,
1265                 u32 tx_firmware_statistics_structure_address,
1266                 volatile u32 *rx_rmon_base_ptr,
1267                 u32 rx_firmware_statistics_structure_address,
1268                 volatile u16 *temoder_register,
1269                 volatile u32 *remoder_register)
1270 {
1271         /* Note: this function does not check if */
1272         /* the parameters it receives are NULL   */
1273         u16 temoder_value;
1274         u32 remoder_value;
1275
1276         if (enable_tx_firmware_statistics) {
1277                 out_be32(tx_rmon_base_ptr,
1278                          tx_firmware_statistics_structure_address);
1279                 temoder_value = in_be16(temoder_register);
1280                 temoder_value |= TEMODER_TX_RMON_STATISTICS_ENABLE;
1281                 out_be16(temoder_register, temoder_value);
1282         }
1283
1284         if (enable_rx_firmware_statistics) {
1285                 out_be32(rx_rmon_base_ptr,
1286                          rx_firmware_statistics_structure_address);
1287                 remoder_value = in_be32(remoder_register);
1288                 remoder_value |= REMODER_RX_RMON_STATISTICS_ENABLE;
1289                 out_be32(remoder_register, remoder_value);
1290         }
1291
1292         return 0;
1293 }
1294
1295 static int init_mac_station_addr_regs(u8 address_byte_0,
1296                                       u8 address_byte_1,
1297                                       u8 address_byte_2,
1298                                       u8 address_byte_3,
1299                                       u8 address_byte_4,
1300                                       u8 address_byte_5,
1301                                       volatile u32 *macstnaddr1_register,
1302                                       volatile u32 *macstnaddr2_register)
1303 {
1304         u32 value = 0;
1305
1306         /* Example: for a station address of 0x12345678ABCD, */
1307         /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */
1308
1309         /* MACSTNADDR1 Register: */
1310
1311         /* 0                      7   8                      15  */
1312         /* station address byte 5     station address byte 4     */
1313         /* 16                     23  24                     31  */
1314         /* station address byte 3     station address byte 2     */
1315         value |= (u32) ((address_byte_2 << 0) & 0x000000FF);
1316         value |= (u32) ((address_byte_3 << 8) & 0x0000FF00);
1317         value |= (u32) ((address_byte_4 << 16) & 0x00FF0000);
1318         value |= (u32) ((address_byte_5 << 24) & 0xFF000000);
1319
1320         out_be32(macstnaddr1_register, value);
1321
1322         /* MACSTNADDR2 Register: */
1323
1324         /* 0                      7   8                      15  */
1325         /* station address byte 1     station address byte 0     */
1326         /* 16                     23  24                     31  */
1327         /*         reserved                   reserved           */
1328         value = 0;
1329         value |= (u32) ((address_byte_0 << 16) & 0x00FF0000);
1330         value |= (u32) ((address_byte_1 << 24) & 0xFF000000);
1331
1332         out_be32(macstnaddr2_register, value);
1333
1334         return 0;
1335 }
1336
1337 static int init_check_frame_length_mode(int length_check,
1338                                         volatile u32 *maccfg2_register)
1339 {
1340         u32 value = 0;
1341
1342         value = in_be32(maccfg2_register);
1343
1344         if (length_check)
1345                 value |= MACCFG2_LC;
1346         else
1347                 value &= ~MACCFG2_LC;
1348
1349         out_be32(maccfg2_register, value);
1350         return 0;
1351 }
1352
1353 static int init_preamble_length(u8 preamble_length,
1354                                 volatile u32 *maccfg2_register)
1355 {
1356         u32 value = 0;
1357
1358         if ((preamble_length < 3) || (preamble_length > 7))
1359                 return -EINVAL;
1360
1361         value = in_be32(maccfg2_register);
1362         value &= ~MACCFG2_PREL_MASK;
1363         value |= (preamble_length << MACCFG2_PREL_SHIFT);
1364         out_be32(maccfg2_register, value);
1365         return 0;
1366 }
1367
1368 static int init_rx_parameters(int reject_broadcast,
1369                               int receive_short_frames,
1370                               int promiscuous, volatile u32 *upsmr_register)
1371 {
1372         u32 value = 0;
1373
1374         value = in_be32(upsmr_register);
1375
1376         if (reject_broadcast)
1377                 value |= UPSMR_BRO;
1378         else
1379                 value &= ~UPSMR_BRO;
1380
1381         if (receive_short_frames)
1382                 value |= UPSMR_RSH;
1383         else
1384                 value &= ~UPSMR_RSH;
1385
1386         if (promiscuous)
1387                 value |= UPSMR_PRO;
1388         else
1389                 value &= ~UPSMR_PRO;
1390
1391         out_be32(upsmr_register, value);
1392
1393         return 0;
1394 }
1395
1396 static int init_max_rx_buff_len(u16 max_rx_buf_len,
1397                                 volatile u16 *mrblr_register)
1398 {
1399         /* max_rx_buf_len value must be a multiple of 128 */
1400         if ((max_rx_buf_len == 0)
1401             || (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT))
1402                 return -EINVAL;
1403
1404         out_be16(mrblr_register, max_rx_buf_len);
1405         return 0;
1406 }
1407
1408 static int init_min_frame_len(u16 min_frame_length,
1409                               volatile u16 *minflr_register,
1410                               volatile u16 *mrblr_register)
1411 {
1412         u16 mrblr_value = 0;
1413
1414         mrblr_value = in_be16(mrblr_register);
1415         if (min_frame_length >= (mrblr_value - 4))
1416                 return -EINVAL;
1417
1418         out_be16(minflr_register, min_frame_length);
1419         return 0;
1420 }
1421
1422 static int adjust_enet_interface(struct ucc_geth_private *ugeth)
1423 {
1424         struct ucc_geth_info *ug_info;
1425         struct ucc_geth *ug_regs;
1426         struct ucc_fast *uf_regs;
1427         int ret_val;
1428         u32 upsmr, maccfg2, tbiBaseAddress;
1429         u16 value;
1430
1431         ugeth_vdbg("%s: IN", __FUNCTION__);
1432
1433         ug_info = ugeth->ug_info;
1434         ug_regs = ugeth->ug_regs;
1435         uf_regs = ugeth->uccf->uf_regs;
1436
1437         /*                    Set MACCFG2                    */
1438         maccfg2 = in_be32(&ug_regs->maccfg2);
1439         maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
1440         if ((ugeth->max_speed == SPEED_10) ||
1441             (ugeth->max_speed == SPEED_100))
1442                 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
1443         else if (ugeth->max_speed == SPEED_1000)
1444                 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
1445         maccfg2 |= ug_info->padAndCrc;
1446         out_be32(&ug_regs->maccfg2, maccfg2);
1447
1448         /*                    Set UPSMR                      */
1449         upsmr = in_be32(&uf_regs->upsmr);
1450         upsmr &= ~(UPSMR_RPM | UPSMR_R10M | UPSMR_TBIM | UPSMR_RMM);
1451         if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1452             (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1453             (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1454             (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1455                 upsmr |= UPSMR_RPM;
1456                 switch (ugeth->max_speed) {
1457                 case SPEED_10:
1458                         upsmr |= UPSMR_R10M;
1459                         /* FALLTHROUGH */
1460                 case SPEED_100:
1461                         if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI)
1462                                 upsmr |= UPSMR_RMM;
1463                 }
1464         }
1465         if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1466             (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1467                 upsmr |= UPSMR_TBIM;
1468         }
1469         out_be32(&uf_regs->upsmr, upsmr);
1470
1471         /* Disable autonegotiation in tbi mode, because by default it
1472         comes up in autonegotiation mode. */
1473         /* Note that this depends on proper setting in utbipar register. */
1474         if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1475             (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1476                 tbiBaseAddress = in_be32(&ug_regs->utbipar);
1477                 tbiBaseAddress &= UTBIPAR_PHY_ADDRESS_MASK;
1478                 tbiBaseAddress >>= UTBIPAR_PHY_ADDRESS_SHIFT;
1479                 value = ugeth->phydev->bus->read(ugeth->phydev->bus,
1480                                 (u8) tbiBaseAddress, ENET_TBI_MII_CR);
1481                 value &= ~0x1000;       /* Turn off autonegotiation */
1482                 ugeth->phydev->bus->write(ugeth->phydev->bus,
1483                                 (u8) tbiBaseAddress, ENET_TBI_MII_CR, value);
1484         }
1485
1486         init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2);
1487
1488         ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2);
1489         if (ret_val != 0) {
1490                 ugeth_err
1491                     ("%s: Preamble length must be between 3 and 7 inclusive.",
1492                      __FUNCTION__);
1493                 return ret_val;
1494         }
1495
1496         return 0;
1497 }
1498
1499 /* Called every time the controller might need to be made
1500  * aware of new link state.  The PHY code conveys this
1501  * information through variables in the ugeth structure, and this
1502  * function converts those variables into the appropriate
1503  * register values, and can bring down the device if needed.
1504  */
1505
1506 static void adjust_link(struct net_device *dev)
1507 {
1508         struct ucc_geth_private *ugeth = netdev_priv(dev);
1509         struct ucc_geth *ug_regs;
1510         struct ucc_fast *uf_regs;
1511         struct phy_device *phydev = ugeth->phydev;
1512         unsigned long flags;
1513         int new_state = 0;
1514
1515         ug_regs = ugeth->ug_regs;
1516         uf_regs = ugeth->uccf->uf_regs;
1517
1518         spin_lock_irqsave(&ugeth->lock, flags);
1519
1520         if (phydev->link) {
1521                 u32 tempval = in_be32(&ug_regs->maccfg2);
1522                 u32 upsmr = in_be32(&uf_regs->upsmr);
1523                 /* Now we make sure that we can be in full duplex mode.
1524                  * If not, we operate in half-duplex mode. */
1525                 if (phydev->duplex != ugeth->oldduplex) {
1526                         new_state = 1;
1527                         if (!(phydev->duplex))
1528                                 tempval &= ~(MACCFG2_FDX);
1529                         else
1530                                 tempval |= MACCFG2_FDX;
1531                         ugeth->oldduplex = phydev->duplex;
1532                 }
1533
1534                 if (phydev->speed != ugeth->oldspeed) {
1535                         new_state = 1;
1536                         switch (phydev->speed) {
1537                         case SPEED_1000:
1538                                 tempval = ((tempval &
1539                                             ~(MACCFG2_INTERFACE_MODE_MASK)) |
1540                                             MACCFG2_INTERFACE_MODE_BYTE);
1541                                 break;
1542                         case SPEED_100:
1543                         case SPEED_10:
1544                                 tempval = ((tempval &
1545                                             ~(MACCFG2_INTERFACE_MODE_MASK)) |
1546                                             MACCFG2_INTERFACE_MODE_NIBBLE);
1547                                 /* if reduced mode, re-set UPSMR.R10M */
1548                                 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1549                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1550                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1551                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1552                                         if (phydev->speed == SPEED_10)
1553                                                 upsmr |= UPSMR_R10M;
1554                                         else
1555                                                 upsmr &= ~(UPSMR_R10M);
1556                                 }
1557                                 break;
1558                         default:
1559                                 if (netif_msg_link(ugeth))
1560                                         ugeth_warn(
1561                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!",
1562                                                 dev->name, phydev->speed);
1563                                 break;
1564                         }
1565                         ugeth->oldspeed = phydev->speed;
1566                 }
1567
1568                 out_be32(&ug_regs->maccfg2, tempval);
1569                 out_be32(&uf_regs->upsmr, upsmr);
1570
1571                 if (!ugeth->oldlink) {
1572                         new_state = 1;
1573                         ugeth->oldlink = 1;
1574                         netif_schedule(dev);
1575                 }
1576         } else if (ugeth->oldlink) {
1577                         new_state = 1;
1578                         ugeth->oldlink = 0;
1579                         ugeth->oldspeed = 0;
1580                         ugeth->oldduplex = -1;
1581         }
1582
1583         if (new_state && netif_msg_link(ugeth))
1584                 phy_print_status(phydev);
1585
1586         spin_unlock_irqrestore(&ugeth->lock, flags);
1587 }
1588
1589 /* Configure the PHY for dev.
1590  * returns 0 if success.  -1 if failure
1591  */
1592 static int init_phy(struct net_device *dev)
1593 {
1594         struct ucc_geth_private *priv = netdev_priv(dev);
1595         struct phy_device *phydev;
1596         char phy_id[BUS_ID_SIZE];
1597
1598         priv->oldlink = 0;
1599         priv->oldspeed = 0;
1600         priv->oldduplex = -1;
1601
1602         snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT, priv->ug_info->mdio_bus,
1603                         priv->ug_info->phy_address);
1604
1605         phydev = phy_connect(dev, phy_id, &adjust_link, 0, priv->phy_interface);
1606
1607         if (IS_ERR(phydev)) {
1608                 printk("%s: Could not attach to PHY\n", dev->name);
1609                 return PTR_ERR(phydev);
1610         }
1611
1612         phydev->supported &= (ADVERTISED_10baseT_Half |
1613                                  ADVERTISED_10baseT_Full |
1614                                  ADVERTISED_100baseT_Half |
1615                                  ADVERTISED_100baseT_Full);
1616
1617         if (priv->max_speed == SPEED_1000)
1618                 phydev->supported |= ADVERTISED_1000baseT_Full;
1619
1620         phydev->advertising = phydev->supported;
1621
1622         priv->phydev = phydev;
1623
1624         return 0;
1625 }
1626
1627
1628
1629 static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth)
1630 {
1631         struct ucc_fast_private *uccf;
1632         u32 cecr_subblock;
1633         u32 temp;
1634
1635         uccf = ugeth->uccf;
1636
1637         /* Mask GRACEFUL STOP TX interrupt bit and clear it */
1638         temp = in_be32(uccf->p_uccm);
1639         temp &= ~UCCE_GRA;
1640         out_be32(uccf->p_uccm, temp);
1641         out_be32(uccf->p_ucce, UCCE_GRA);       /* clear by writing 1 */
1642
1643         /* Issue host command */
1644         cecr_subblock =
1645             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1646         qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
1647                      QE_CR_PROTOCOL_ETHERNET, 0);
1648
1649         /* Wait for command to complete */
1650         do {
1651                 temp = in_be32(uccf->p_ucce);
1652         } while (!(temp & UCCE_GRA));
1653
1654         uccf->stopped_tx = 1;
1655
1656         return 0;
1657 }
1658
1659 static int ugeth_graceful_stop_rx(struct ucc_geth_private * ugeth)
1660 {
1661         struct ucc_fast_private *uccf;
1662         u32 cecr_subblock;
1663         u8 temp;
1664
1665         uccf = ugeth->uccf;
1666
1667         /* Clear acknowledge bit */
1668         temp = ugeth->p_rx_glbl_pram->rxgstpack;
1669         temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
1670         ugeth->p_rx_glbl_pram->rxgstpack = temp;
1671
1672         /* Keep issuing command and checking acknowledge bit until
1673         it is asserted, according to spec */
1674         do {
1675                 /* Issue host command */
1676                 cecr_subblock =
1677                     ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.
1678                                                 ucc_num);
1679                 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
1680                              QE_CR_PROTOCOL_ETHERNET, 0);
1681
1682                 temp = ugeth->p_rx_glbl_pram->rxgstpack;
1683         } while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX));
1684
1685         uccf->stopped_rx = 1;
1686
1687         return 0;
1688 }
1689
1690 static int ugeth_restart_tx(struct ucc_geth_private *ugeth)
1691 {
1692         struct ucc_fast_private *uccf;
1693         u32 cecr_subblock;
1694
1695         uccf = ugeth->uccf;
1696
1697         cecr_subblock =
1698             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1699         qe_issue_cmd(QE_RESTART_TX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 0);
1700         uccf->stopped_tx = 0;
1701
1702         return 0;
1703 }
1704
1705 static int ugeth_restart_rx(struct ucc_geth_private *ugeth)
1706 {
1707         struct ucc_fast_private *uccf;
1708         u32 cecr_subblock;
1709
1710         uccf = ugeth->uccf;
1711
1712         cecr_subblock =
1713             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1714         qe_issue_cmd(QE_RESTART_RX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
1715                      0);
1716         uccf->stopped_rx = 0;
1717
1718         return 0;
1719 }
1720
1721 static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1722 {
1723         struct ucc_fast_private *uccf;
1724         int enabled_tx, enabled_rx;
1725
1726         uccf = ugeth->uccf;
1727
1728         /* check if the UCC number is in range. */
1729         if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1730                 ugeth_err("%s: ucc_num out of range.", __FUNCTION__);
1731                 return -EINVAL;
1732         }
1733
1734         enabled_tx = uccf->enabled_tx;
1735         enabled_rx = uccf->enabled_rx;
1736
1737         /* Get Tx and Rx going again, in case this channel was actively
1738         disabled. */
1739         if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx)
1740                 ugeth_restart_tx(ugeth);
1741         if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx)
1742                 ugeth_restart_rx(ugeth);
1743
1744         ucc_fast_enable(uccf, mode);    /* OK to do even if not disabled */
1745
1746         return 0;
1747
1748 }
1749
1750 static int ugeth_disable(struct ucc_geth_private * ugeth, enum comm_dir mode)
1751 {
1752         struct ucc_fast_private *uccf;
1753
1754         uccf = ugeth->uccf;
1755
1756         /* check if the UCC number is in range. */
1757         if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1758                 ugeth_err("%s: ucc_num out of range.", __FUNCTION__);
1759                 return -EINVAL;
1760         }
1761
1762         /* Stop any transmissions */
1763         if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx)
1764                 ugeth_graceful_stop_tx(ugeth);
1765
1766         /* Stop any receptions */
1767         if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx)
1768                 ugeth_graceful_stop_rx(ugeth);
1769
1770         ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */
1771
1772         return 0;
1773 }
1774
1775 static void ugeth_dump_regs(struct ucc_geth_private *ugeth)
1776 {
1777 #ifdef DEBUG
1778         ucc_fast_dump_regs(ugeth->uccf);
1779         dump_regs(ugeth);
1780         dump_bds(ugeth);
1781 #endif
1782 }
1783
1784 #ifdef CONFIG_UGETH_FILTERING
1785 static int ugeth_ext_filtering_serialize_tad(struct ucc_geth_tad_params *
1786                                              p_UccGethTadParams,
1787                                              struct qe_fltr_tad *qe_fltr_tad)
1788 {
1789         u16 temp;
1790
1791         /* Zero serialized TAD */
1792         memset(qe_fltr_tad, 0, QE_FLTR_TAD_SIZE);
1793
1794         qe_fltr_tad->serialized[0] |= UCC_GETH_TAD_V;   /* Must have this */
1795         if (p_UccGethTadParams->rx_non_dynamic_extended_features_mode ||
1796             (p_UccGethTadParams->vtag_op != UCC_GETH_VLAN_OPERATION_TAGGED_NOP)
1797             || (p_UccGethTadParams->vnontag_op !=
1798                 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP)
1799             )
1800                 qe_fltr_tad->serialized[0] |= UCC_GETH_TAD_EF;
1801         if (p_UccGethTadParams->reject_frame)
1802                 qe_fltr_tad->serialized[0] |= UCC_GETH_TAD_REJ;
1803         temp =
1804             (u16) (((u16) p_UccGethTadParams->
1805                     vtag_op) << UCC_GETH_TAD_VTAG_OP_SHIFT);
1806         qe_fltr_tad->serialized[0] |= (u8) (temp >> 8); /* upper bits */
1807
1808         qe_fltr_tad->serialized[1] |= (u8) (temp & 0x00ff);     /* lower bits */
1809         if (p_UccGethTadParams->vnontag_op ==
1810             UCC_GETH_VLAN_OPERATION_NON_TAGGED_Q_TAG_INSERT)
1811                 qe_fltr_tad->serialized[1] |= UCC_GETH_TAD_V_NON_VTAG_OP;
1812         qe_fltr_tad->serialized[1] |=
1813             p_UccGethTadParams->rqos << UCC_GETH_TAD_RQOS_SHIFT;
1814
1815         qe_fltr_tad->serialized[2] |=
1816             p_UccGethTadParams->vpri << UCC_GETH_TAD_V_PRIORITY_SHIFT;
1817         /* upper bits */
1818         qe_fltr_tad->serialized[2] |= (u8) (p_UccGethTadParams->vid >> 8);
1819         /* lower bits */
1820         qe_fltr_tad->serialized[3] |= (u8) (p_UccGethTadParams->vid & 0x00ff);
1821
1822         return 0;
1823 }
1824
1825 static struct enet_addr_container_t
1826     *ugeth_82xx_filtering_get_match_addr_in_hash(struct ucc_geth_private *ugeth,
1827                                                  struct enet_addr *p_enet_addr)
1828 {
1829         struct enet_addr_container *enet_addr_cont;
1830         struct list_head *p_lh;
1831         u16 i, num;
1832         int32_t j;
1833         u8 *p_counter;
1834
1835         if ((*p_enet_addr)[0] & ENET_GROUP_ADDR) {
1836                 p_lh = &ugeth->group_hash_q;
1837                 p_counter = &(ugeth->numGroupAddrInHash);
1838         } else {
1839                 p_lh = &ugeth->ind_hash_q;
1840                 p_counter = &(ugeth->numIndAddrInHash);
1841         }
1842
1843         if (!p_lh)
1844                 return NULL;
1845
1846         num = *p_counter;
1847
1848         for (i = 0; i < num; i++) {
1849                 enet_addr_cont =
1850                     (struct enet_addr_container *)
1851                     ENET_ADDR_CONT_ENTRY(dequeue(p_lh));
1852                 for (j = ENET_NUM_OCTETS_PER_ADDRESS - 1; j >= 0; j--) {
1853                         if ((*p_enet_addr)[j] != (enet_addr_cont->address)[j])
1854                                 break;
1855                         if (j == 0)
1856                                 return enet_addr_cont;  /* Found */
1857                 }
1858                 enqueue(p_lh, &enet_addr_cont->node);   /* Put it back */
1859         }
1860         return NULL;
1861 }
1862
1863 static int ugeth_82xx_filtering_add_addr_in_hash(struct ucc_geth_private *ugeth,
1864                                                  struct enet_addr *p_enet_addr)
1865 {
1866         enum ucc_geth_enet_address_recognition_location location;
1867         struct enet_addr_container *enet_addr_cont;
1868         struct list_head *p_lh;
1869         u8 i;
1870         u32 limit;
1871         u8 *p_counter;
1872
1873         if ((*p_enet_addr)[0] & ENET_GROUP_ADDR) {
1874                 p_lh = &ugeth->group_hash_q;
1875                 limit = ugeth->ug_info->maxGroupAddrInHash;
1876                 location =
1877                     UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_GROUP_HASH;
1878                 p_counter = &(ugeth->numGroupAddrInHash);
1879         } else {
1880                 p_lh = &ugeth->ind_hash_q;
1881                 limit = ugeth->ug_info->maxIndAddrInHash;
1882                 location =
1883                     UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_INDIVIDUAL_HASH;
1884                 p_counter = &(ugeth->numIndAddrInHash);
1885         }
1886
1887         if ((enet_addr_cont =
1888              ugeth_82xx_filtering_get_match_addr_in_hash(ugeth, p_enet_addr))) {
1889                 list_add(p_lh, &enet_addr_cont->node);  /* Put it back */
1890                 return 0;
1891         }
1892         if ((!p_lh) || (!(*p_counter < limit)))
1893                 return -EBUSY;
1894         if (!(enet_addr_cont = get_enet_addr_container()))
1895                 return -ENOMEM;
1896         for (i = 0; i < ENET_NUM_OCTETS_PER_ADDRESS; i++)
1897                 (enet_addr_cont->address)[i] = (*p_enet_addr)[i];
1898         enet_addr_cont->location = location;
1899         enqueue(p_lh, &enet_addr_cont->node);   /* Put it back */
1900         ++(*p_counter);
1901
1902         hw_add_addr_in_hash(ugeth, enet_addr_cont->address);
1903         return 0;
1904 }
1905
1906 static int ugeth_82xx_filtering_clear_addr_in_hash(struct ucc_geth_private *ugeth,
1907                                                    struct enet_addr *p_enet_addr)
1908 {
1909         struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
1910         struct enet_addr_container *enet_addr_cont;
1911         struct ucc_fast_private *uccf;
1912         enum comm_dir comm_dir;
1913         u16 i, num;
1914         struct list_head *p_lh;
1915         u32 *addr_h, *addr_l;
1916         u8 *p_counter;
1917
1918         uccf = ugeth->uccf;
1919
1920         p_82xx_addr_filt =
1921             (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
1922             addressfiltering;
1923
1924         if (!
1925             (enet_addr_cont =
1926              ugeth_82xx_filtering_get_match_addr_in_hash(ugeth, p_enet_addr)))
1927                 return -ENOENT;
1928
1929         /* It's been found and removed from the CQ. */
1930         /* Now destroy its container */
1931         put_enet_addr_container(enet_addr_cont);
1932
1933         if ((*p_enet_addr)[0] & ENET_GROUP_ADDR) {
1934                 addr_h = &(p_82xx_addr_filt->gaddr_h);
1935                 addr_l = &(p_82xx_addr_filt->gaddr_l);
1936                 p_lh = &ugeth->group_hash_q;
1937                 p_counter = &(ugeth->numGroupAddrInHash);
1938         } else {
1939                 addr_h = &(p_82xx_addr_filt->iaddr_h);
1940                 addr_l = &(p_82xx_addr_filt->iaddr_l);
1941                 p_lh = &ugeth->ind_hash_q;
1942                 p_counter = &(ugeth->numIndAddrInHash);
1943         }
1944
1945         comm_dir = 0;
1946         if (uccf->enabled_tx)
1947                 comm_dir |= COMM_DIR_TX;
1948         if (uccf->enabled_rx)
1949                 comm_dir |= COMM_DIR_RX;
1950         if (comm_dir)
1951                 ugeth_disable(ugeth, comm_dir);
1952
1953         /* Clear the hash table. */
1954         out_be32(addr_h, 0x00000000);
1955         out_be32(addr_l, 0x00000000);
1956
1957         /* Add all remaining CQ elements back into hash */
1958         num = --(*p_counter);
1959         for (i = 0; i < num; i++) {
1960                 enet_addr_cont =
1961                     (struct enet_addr_container *)
1962                     ENET_ADDR_CONT_ENTRY(dequeue(p_lh));
1963                 hw_add_addr_in_hash(ugeth, enet_addr_cont->address);
1964                 enqueue(p_lh, &enet_addr_cont->node);   /* Put it back */
1965         }
1966
1967         if (comm_dir)
1968                 ugeth_enable(ugeth, comm_dir);
1969
1970         return 0;
1971 }
1972 #endif /* CONFIG_UGETH_FILTERING */
1973
1974 static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private *
1975                                                        ugeth,
1976                                                        enum enet_addr_type
1977                                                        enet_addr_type)
1978 {
1979         struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
1980         struct ucc_fast_private *uccf;
1981         enum comm_dir comm_dir;
1982         struct list_head *p_lh;
1983         u16 i, num;
1984         u32 *addr_h, *addr_l;
1985         u8 *p_counter;
1986
1987         uccf = ugeth->uccf;
1988
1989         p_82xx_addr_filt =
1990             (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
1991             addressfiltering;
1992
1993         if (enet_addr_type == ENET_ADDR_TYPE_GROUP) {
1994                 addr_h = &(p_82xx_addr_filt->gaddr_h);
1995                 addr_l = &(p_82xx_addr_filt->gaddr_l);
1996                 p_lh = &ugeth->group_hash_q;
1997                 p_counter = &(ugeth->numGroupAddrInHash);
1998         } else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) {
1999                 addr_h = &(p_82xx_addr_filt->iaddr_h);
2000                 addr_l = &(p_82xx_addr_filt->iaddr_l);
2001                 p_lh = &ugeth->ind_hash_q;
2002                 p_counter = &(ugeth->numIndAddrInHash);
2003         } else
2004                 return -EINVAL;
2005
2006         comm_dir = 0;
2007         if (uccf->enabled_tx)
2008                 comm_dir |= COMM_DIR_TX;
2009         if (uccf->enabled_rx)
2010                 comm_dir |= COMM_DIR_RX;
2011         if (comm_dir)
2012                 ugeth_disable(ugeth, comm_dir);
2013
2014         /* Clear the hash table. */
2015         out_be32(addr_h, 0x00000000);
2016         out_be32(addr_l, 0x00000000);
2017
2018         if (!p_lh)
2019                 return 0;
2020
2021         num = *p_counter;
2022
2023         /* Delete all remaining CQ elements */
2024         for (i = 0; i < num; i++)
2025                 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh)));
2026
2027         *p_counter = 0;
2028
2029         if (comm_dir)
2030                 ugeth_enable(ugeth, comm_dir);
2031
2032         return 0;
2033 }
2034
2035 #ifdef CONFIG_UGETH_FILTERING
2036 static int ugeth_82xx_filtering_add_addr_in_paddr(struct ucc_geth_private *ugeth,
2037                                                   struct enet_addr *p_enet_addr,
2038                                                   u8 paddr_num)
2039 {
2040         int i;
2041
2042         if ((*p_enet_addr)[0] & ENET_GROUP_ADDR)
2043                 ugeth_warn
2044                     ("%s: multicast address added to paddr will have no "
2045                      "effect - is this what you wanted?",
2046                      __FUNCTION__);
2047
2048         ugeth->indAddrRegUsed[paddr_num] = 1;   /* mark this paddr as used */
2049         /* store address in our database */
2050         for (i = 0; i < ENET_NUM_OCTETS_PER_ADDRESS; i++)
2051                 ugeth->paddr[paddr_num][i] = (*p_enet_addr)[i];
2052         /* put in hardware */
2053         return hw_add_addr_in_paddr(ugeth, p_enet_addr, paddr_num);
2054 }
2055 #endif /* CONFIG_UGETH_FILTERING */
2056
2057 static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth,
2058                                                     u8 paddr_num)
2059 {
2060         ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */
2061         return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */
2062 }
2063
2064 static void ucc_geth_memclean(struct ucc_geth_private *ugeth)
2065 {
2066         u16 i, j;
2067         u8 *bd;
2068
2069         if (!ugeth)
2070                 return;
2071
2072         if (ugeth->uccf)
2073                 ucc_fast_free(ugeth->uccf);
2074
2075         if (ugeth->p_thread_data_tx) {
2076                 qe_muram_free(ugeth->thread_dat_tx_offset);
2077                 ugeth->p_thread_data_tx = NULL;
2078         }
2079         if (ugeth->p_thread_data_rx) {
2080                 qe_muram_free(ugeth->thread_dat_rx_offset);
2081                 ugeth->p_thread_data_rx = NULL;
2082         }
2083         if (ugeth->p_exf_glbl_param) {
2084                 qe_muram_free(ugeth->exf_glbl_param_offset);
2085                 ugeth->p_exf_glbl_param = NULL;
2086         }
2087         if (ugeth->p_rx_glbl_pram) {
2088                 qe_muram_free(ugeth->rx_glbl_pram_offset);
2089                 ugeth->p_rx_glbl_pram = NULL;
2090         }
2091         if (ugeth->p_tx_glbl_pram) {
2092                 qe_muram_free(ugeth->tx_glbl_pram_offset);
2093                 ugeth->p_tx_glbl_pram = NULL;
2094         }
2095         if (ugeth->p_send_q_mem_reg) {
2096                 qe_muram_free(ugeth->send_q_mem_reg_offset);
2097                 ugeth->p_send_q_mem_reg = NULL;
2098         }
2099         if (ugeth->p_scheduler) {
2100                 qe_muram_free(ugeth->scheduler_offset);
2101                 ugeth->p_scheduler = NULL;
2102         }
2103         if (ugeth->p_tx_fw_statistics_pram) {
2104                 qe_muram_free(ugeth->tx_fw_statistics_pram_offset);
2105                 ugeth->p_tx_fw_statistics_pram = NULL;
2106         }
2107         if (ugeth->p_rx_fw_statistics_pram) {
2108                 qe_muram_free(ugeth->rx_fw_statistics_pram_offset);
2109                 ugeth->p_rx_fw_statistics_pram = NULL;
2110         }
2111         if (ugeth->p_rx_irq_coalescing_tbl) {
2112                 qe_muram_free(ugeth->rx_irq_coalescing_tbl_offset);
2113                 ugeth->p_rx_irq_coalescing_tbl = NULL;
2114         }
2115         if (ugeth->p_rx_bd_qs_tbl) {
2116                 qe_muram_free(ugeth->rx_bd_qs_tbl_offset);
2117                 ugeth->p_rx_bd_qs_tbl = NULL;
2118         }
2119         if (ugeth->p_init_enet_param_shadow) {
2120                 return_init_enet_entries(ugeth,
2121                                          &(ugeth->p_init_enet_param_shadow->
2122                                            rxthread[0]),
2123                                          ENET_INIT_PARAM_MAX_ENTRIES_RX,
2124                                          ugeth->ug_info->riscRx, 1);
2125                 return_init_enet_entries(ugeth,
2126                                          &(ugeth->p_init_enet_param_shadow->
2127                                            txthread[0]),
2128                                          ENET_INIT_PARAM_MAX_ENTRIES_TX,
2129                                          ugeth->ug_info->riscTx, 0);
2130                 kfree(ugeth->p_init_enet_param_shadow);
2131                 ugeth->p_init_enet_param_shadow = NULL;
2132         }
2133         for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
2134                 bd = ugeth->p_tx_bd_ring[i];
2135                 if (!bd)
2136                         continue;
2137                 for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) {
2138                         if (ugeth->tx_skbuff[i][j]) {
2139                                 dma_unmap_single(NULL,
2140                                                  ((qe_bd_t *)bd)->buf,
2141                                                  (in_be32((u32 *)bd) &
2142                                                   BD_LENGTH_MASK),
2143                                                  DMA_TO_DEVICE);
2144                                 dev_kfree_skb_any(ugeth->tx_skbuff[i][j]);
2145                                 ugeth->tx_skbuff[i][j] = NULL;
2146                         }
2147                 }
2148
2149                 kfree(ugeth->tx_skbuff[i]);
2150
2151                 if (ugeth->p_tx_bd_ring[i]) {
2152                         if (ugeth->ug_info->uf_info.bd_mem_part ==
2153                             MEM_PART_SYSTEM)
2154                                 kfree((void *)ugeth->tx_bd_ring_offset[i]);
2155                         else if (ugeth->ug_info->uf_info.bd_mem_part ==
2156                                  MEM_PART_MURAM)
2157                                 qe_muram_free(ugeth->tx_bd_ring_offset[i]);
2158                         ugeth->p_tx_bd_ring[i] = NULL;
2159                 }
2160         }
2161         for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
2162                 if (ugeth->p_rx_bd_ring[i]) {
2163                         /* Return existing data buffers in ring */
2164                         bd = ugeth->p_rx_bd_ring[i];
2165                         for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) {
2166                                 if (ugeth->rx_skbuff[i][j]) {
2167                                         dma_unmap_single(NULL,
2168                                                 ((struct qe_bd *)bd)->buf,
2169                                                 ugeth->ug_info->
2170                                                 uf_info.max_rx_buf_length +
2171                                                 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
2172                                                 DMA_FROM_DEVICE);
2173                                         dev_kfree_skb_any(
2174                                                 ugeth->rx_skbuff[i][j]);
2175                                         ugeth->rx_skbuff[i][j] = NULL;
2176                                 }
2177                                 bd += sizeof(struct qe_bd);
2178                         }
2179
2180                         kfree(ugeth->rx_skbuff[i]);
2181
2182                         if (ugeth->ug_info->uf_info.bd_mem_part ==
2183                             MEM_PART_SYSTEM)
2184                                 kfree((void *)ugeth->rx_bd_ring_offset[i]);
2185                         else if (ugeth->ug_info->uf_info.bd_mem_part ==
2186                                  MEM_PART_MURAM)
2187                                 qe_muram_free(ugeth->rx_bd_ring_offset[i]);
2188                         ugeth->p_rx_bd_ring[i] = NULL;
2189                 }
2190         }
2191         while (!list_empty(&ugeth->group_hash_q))
2192                 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
2193                                         (dequeue(&ugeth->group_hash_q)));
2194         while (!list_empty(&ugeth->ind_hash_q))
2195                 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
2196                                         (dequeue(&ugeth->ind_hash_q)));
2197
2198 }
2199
2200 static void ucc_geth_set_multi(struct net_device *dev)
2201 {
2202         struct ucc_geth_private *ugeth;
2203         struct dev_mc_list *dmi;
2204         struct ucc_fast *uf_regs;
2205         struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
2206         u8 tempaddr[6];
2207         u8 *mcptr, *tdptr;
2208         int i, j;
2209
2210         ugeth = netdev_priv(dev);
2211
2212         uf_regs = ugeth->uccf->uf_regs;
2213
2214         if (dev->flags & IFF_PROMISC) {
2215
2216                 uf_regs->upsmr |= UPSMR_PRO;
2217
2218         } else {
2219
2220                 uf_regs->upsmr &= ~UPSMR_PRO;
2221
2222                 p_82xx_addr_filt =
2223                     (struct ucc_geth_82xx_address_filtering_pram *) ugeth->
2224                     p_rx_glbl_pram->addressfiltering;
2225
2226                 if (dev->flags & IFF_ALLMULTI) {
2227                         /* Catch all multicast addresses, so set the
2228                          * filter to all 1's.
2229                          */
2230                         out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff);
2231                         out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff);
2232                 } else {
2233                         /* Clear filter and add the addresses in the list.
2234                          */
2235                         out_be32(&p_82xx_addr_filt->gaddr_h, 0x0);
2236                         out_be32(&p_82xx_addr_filt->gaddr_l, 0x0);
2237
2238                         dmi = dev->mc_list;
2239
2240                         for (i = 0; i < dev->mc_count; i++, dmi = dmi->next) {
2241
2242                                 /* Only support group multicast for now.
2243                                  */
2244                                 if (!(dmi->dmi_addr[0] & 1))
2245                                         continue;
2246
2247                                 /* The address in dmi_addr is LSB first,
2248                                  * and taddr is MSB first.  We have to
2249                                  * copy bytes MSB first from dmi_addr.
2250                                  */
2251                                 mcptr = (u8 *) dmi->dmi_addr + 5;
2252                                 tdptr = (u8 *) tempaddr;
2253                                 for (j = 0; j < 6; j++)
2254                                         *tdptr++ = *mcptr--;
2255
2256                                 /* Ask CPM to run CRC and set bit in
2257                                  * filter mask.
2258                                  */
2259                                 hw_add_addr_in_hash(ugeth, tempaddr);
2260                         }
2261                 }
2262         }
2263 }
2264
2265 static void ucc_geth_stop(struct ucc_geth_private *ugeth)
2266 {
2267         struct ucc_geth *ug_regs = ugeth->ug_regs;
2268         struct phy_device *phydev = ugeth->phydev;
2269         u32 tempval;
2270
2271         ugeth_vdbg("%s: IN", __FUNCTION__);
2272
2273         /* Disable the controller */
2274         ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
2275
2276         /* Tell the kernel the link is down */
2277         phy_stop(phydev);
2278
2279         /* Mask all interrupts */
2280         out_be32(ugeth->uccf->p_uccm, 0x00000000);
2281
2282         /* Clear all interrupts */
2283         out_be32(ugeth->uccf->p_ucce, 0xffffffff);
2284
2285         /* Disable Rx and Tx */
2286         tempval = in_be32(&ug_regs->maccfg1);
2287         tempval &= ~(MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2288         out_be32(&ug_regs->maccfg1, tempval);
2289
2290         free_irq(ugeth->ug_info->uf_info.irq, ugeth->dev);
2291
2292         ucc_geth_memclean(ugeth);
2293 }
2294
2295 static int ucc_struct_init(struct ucc_geth_private *ugeth)
2296 {
2297         struct ucc_geth_info *ug_info;
2298         struct ucc_fast_info *uf_info;
2299         int i;
2300
2301         ug_info = ugeth->ug_info;
2302         uf_info = &ug_info->uf_info;
2303
2304         /* Create CQs for hash tables */
2305         INIT_LIST_HEAD(&ugeth->group_hash_q);
2306         INIT_LIST_HEAD(&ugeth->ind_hash_q);
2307
2308         if (!((uf_info->bd_mem_part == MEM_PART_SYSTEM) ||
2309               (uf_info->bd_mem_part == MEM_PART_MURAM))) {
2310                 ugeth_err("%s: Bad memory partition value.", __FUNCTION__);
2311                 return -EINVAL;
2312         }
2313
2314         /* Rx BD lengths */
2315         for (i = 0; i < ug_info->numQueuesRx; i++) {
2316                 if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) ||
2317                     (ug_info->bdRingLenRx[i] %
2318                      UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) {
2319                         ugeth_err
2320                             ("%s: Rx BD ring length must be multiple of 4,"
2321                                 " no smaller than 8.", __FUNCTION__);
2322                         return -EINVAL;
2323                 }
2324         }
2325
2326         /* Tx BD lengths */
2327         for (i = 0; i < ug_info->numQueuesTx; i++) {
2328                 if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) {
2329                         ugeth_err
2330                             ("%s: Tx BD ring length must be no smaller than 2.",
2331                              __FUNCTION__);
2332                         return -EINVAL;
2333                 }
2334         }
2335
2336         /* mrblr */
2337         if ((uf_info->max_rx_buf_length == 0) ||
2338             (uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) {
2339                 ugeth_err
2340                     ("%s: max_rx_buf_length must be non-zero multiple of 128.",
2341                      __FUNCTION__);
2342                 return -EINVAL;
2343         }
2344
2345         /* num Tx queues */
2346         if (ug_info->numQueuesTx > NUM_TX_QUEUES) {
2347                 ugeth_err("%s: number of tx queues too large.", __FUNCTION__);
2348                 return -EINVAL;
2349         }
2350
2351         /* num Rx queues */
2352         if (ug_info->numQueuesRx > NUM_RX_QUEUES) {
2353                 ugeth_err("%s: number of rx queues too large.", __FUNCTION__);
2354                 return -EINVAL;
2355         }
2356
2357         /* l2qt */
2358         for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) {
2359                 if (ug_info->l2qt[i] >= ug_info->numQueuesRx) {
2360                         ugeth_err
2361                             ("%s: VLAN priority table entry must not be"
2362                                 " larger than number of Rx queues.",
2363                              __FUNCTION__);
2364                         return -EINVAL;
2365                 }
2366         }
2367
2368         /* l3qt */
2369         for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) {
2370                 if (ug_info->l3qt[i] >= ug_info->numQueuesRx) {
2371                         ugeth_err
2372                             ("%s: IP priority table entry must not be"
2373                                 " larger than number of Rx queues.",
2374                              __FUNCTION__);
2375                         return -EINVAL;
2376                 }
2377         }
2378
2379         if (ug_info->cam && !ug_info->ecamptr) {
2380                 ugeth_err("%s: If cam mode is chosen, must supply cam ptr.",
2381                           __FUNCTION__);
2382                 return -EINVAL;
2383         }
2384
2385         if ((ug_info->numStationAddresses !=
2386              UCC_GETH_NUM_OF_STATION_ADDRESSES_1)
2387             && ug_info->rxExtendedFiltering) {
2388                 ugeth_err("%s: Number of station addresses greater than 1 "
2389                           "not allowed in extended parsing mode.",
2390                           __FUNCTION__);
2391                 return -EINVAL;
2392         }
2393
2394         /* Generate uccm_mask for receive */
2395         uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */
2396         for (i = 0; i < ug_info->numQueuesRx; i++)
2397                 uf_info->uccm_mask |= (UCCE_RXBF_SINGLE_MASK << i);
2398
2399         for (i = 0; i < ug_info->numQueuesTx; i++)
2400                 uf_info->uccm_mask |= (UCCE_TXBF_SINGLE_MASK << i);
2401         /* Initialize the general fast UCC block. */
2402         if (ucc_fast_init(uf_info, &ugeth->uccf)) {
2403                 ugeth_err("%s: Failed to init uccf.", __FUNCTION__);
2404                 ucc_geth_memclean(ugeth);
2405                 return -ENOMEM;
2406         }
2407
2408         ugeth->ug_regs = (struct ucc_geth *) ioremap(uf_info->regs, sizeof(struct ucc_geth));
2409
2410         return 0;
2411 }
2412
2413 static int ucc_geth_startup(struct ucc_geth_private *ugeth)
2414 {
2415         struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
2416         struct ucc_geth_init_pram *p_init_enet_pram;
2417         struct ucc_fast_private *uccf;
2418         struct ucc_geth_info *ug_info;
2419         struct ucc_fast_info *uf_info;
2420         struct ucc_fast *uf_regs;
2421         struct ucc_geth *ug_regs;
2422         int ret_val = -EINVAL;
2423         u32 remoder = UCC_GETH_REMODER_INIT;
2424         u32 init_enet_pram_offset, cecr_subblock, command, maccfg1;
2425         u32 ifstat, i, j, size, l2qt, l3qt, length;
2426         u16 temoder = UCC_GETH_TEMODER_INIT;
2427         u16 test;
2428         u8 function_code = 0;
2429         u8 *bd, *endOfRing;
2430         u8 numThreadsRxNumerical, numThreadsTxNumerical;
2431
2432         ugeth_vdbg("%s: IN", __FUNCTION__);
2433         uccf = ugeth->uccf;
2434         ug_info = ugeth->ug_info;
2435         uf_info = &ug_info->uf_info;
2436         uf_regs = uccf->uf_regs;
2437         ug_regs = ugeth->ug_regs;
2438
2439         switch (ug_info->numThreadsRx) {
2440         case UCC_GETH_NUM_OF_THREADS_1:
2441                 numThreadsRxNumerical = 1;
2442                 break;
2443         case UCC_GETH_NUM_OF_THREADS_2:
2444                 numThreadsRxNumerical = 2;
2445                 break;
2446         case UCC_GETH_NUM_OF_THREADS_4:
2447                 numThreadsRxNumerical = 4;
2448                 break;
2449         case UCC_GETH_NUM_OF_THREADS_6:
2450                 numThreadsRxNumerical = 6;
2451                 break;
2452         case UCC_GETH_NUM_OF_THREADS_8:
2453                 numThreadsRxNumerical = 8;
2454                 break;
2455         default:
2456                 ugeth_err("%s: Bad number of Rx threads value.", __FUNCTION__);
2457                 ucc_geth_memclean(ugeth);
2458                 return -EINVAL;
2459                 break;
2460         }
2461
2462         switch (ug_info->numThreadsTx) {
2463         case UCC_GETH_NUM_OF_THREADS_1:
2464                 numThreadsTxNumerical = 1;
2465                 break;
2466         case UCC_GETH_NUM_OF_THREADS_2:
2467                 numThreadsTxNumerical = 2;
2468                 break;
2469         case UCC_GETH_NUM_OF_THREADS_4:
2470                 numThreadsTxNumerical = 4;
2471                 break;
2472         case UCC_GETH_NUM_OF_THREADS_6:
2473                 numThreadsTxNumerical = 6;
2474                 break;
2475         case UCC_GETH_NUM_OF_THREADS_8:
2476                 numThreadsTxNumerical = 8;
2477                 break;
2478         default:
2479                 ugeth_err("%s: Bad number of Tx threads value.", __FUNCTION__);
2480                 ucc_geth_memclean(ugeth);
2481                 return -EINVAL;
2482                 break;
2483         }
2484
2485         /* Calculate rx_extended_features */
2486         ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck ||
2487             ug_info->ipAddressAlignment ||
2488             (ug_info->numStationAddresses !=
2489              UCC_GETH_NUM_OF_STATION_ADDRESSES_1);
2490
2491         ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features ||
2492             (ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP)
2493             || (ug_info->vlanOperationNonTagged !=
2494                 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP);
2495
2496         init_default_reg_vals(&uf_regs->upsmr,
2497                               &ug_regs->maccfg1, &ug_regs->maccfg2);
2498
2499         /*                    Set UPSMR                      */
2500         /* For more details see the hardware spec.           */
2501         init_rx_parameters(ug_info->bro,
2502                            ug_info->rsh, ug_info->pro, &uf_regs->upsmr);
2503
2504         /* We're going to ignore other registers for now, */
2505         /* except as needed to get up and running         */
2506
2507         /*                    Set MACCFG1                    */
2508         /* For more details see the hardware spec.           */
2509         init_flow_control_params(ug_info->aufc,
2510                                  ug_info->receiveFlowControl,
2511                                  ug_info->transmitFlowControl,
2512                                  ug_info->pausePeriod,
2513                                  ug_info->extensionField,
2514                                  &uf_regs->upsmr,
2515                                  &ug_regs->uempr, &ug_regs->maccfg1);
2516
2517         maccfg1 = in_be32(&ug_regs->maccfg1);
2518         maccfg1 |= MACCFG1_ENABLE_RX;
2519         maccfg1 |= MACCFG1_ENABLE_TX;
2520         out_be32(&ug_regs->maccfg1, maccfg1);
2521
2522         /*                    Set IPGIFG                     */
2523         /* For more details see the hardware spec.           */
2524         ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1,
2525                                               ug_info->nonBackToBackIfgPart2,
2526                                               ug_info->
2527                                               miminumInterFrameGapEnforcement,
2528                                               ug_info->backToBackInterFrameGap,
2529                                               &ug_regs->ipgifg);
2530         if (ret_val != 0) {
2531                 ugeth_err("%s: IPGIFG initialization parameter too large.",
2532                           __FUNCTION__);
2533                 ucc_geth_memclean(ugeth);
2534                 return ret_val;
2535         }
2536
2537         /*                    Set HAFDUP                     */
2538         /* For more details see the hardware spec.           */
2539         ret_val = init_half_duplex_params(ug_info->altBeb,
2540                                           ug_info->backPressureNoBackoff,
2541                                           ug_info->noBackoff,
2542                                           ug_info->excessDefer,
2543                                           ug_info->altBebTruncation,
2544                                           ug_info->maxRetransmission,
2545                                           ug_info->collisionWindow,
2546                                           &ug_regs->hafdup);
2547         if (ret_val != 0) {
2548                 ugeth_err("%s: Half Duplex initialization parameter too large.",
2549                           __FUNCTION__);
2550                 ucc_geth_memclean(ugeth);
2551                 return ret_val;
2552         }
2553
2554         /*                    Set IFSTAT                     */
2555         /* For more details see the hardware spec.           */
2556         /* Read only - resets upon read                      */
2557         ifstat = in_be32(&ug_regs->ifstat);
2558
2559         /*                    Clear UEMPR                    */
2560         /* For more details see the hardware spec.           */
2561         out_be32(&ug_regs->uempr, 0);
2562
2563         /*                    Set UESCR                      */
2564         /* For more details see the hardware spec.           */
2565         init_hw_statistics_gathering_mode((ug_info->statisticsMode &
2566                                 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE),
2567                                 0, &uf_regs->upsmr, &ug_regs->uescr);
2568
2569         /* Allocate Tx bds */
2570         for (j = 0; j < ug_info->numQueuesTx; j++) {
2571                 /* Allocate in multiple of
2572                    UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT,
2573                    according to spec */
2574                 length = ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd))
2575                           / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2576                     * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2577                 if ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) %
2578                     UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2579                         length += UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2580                 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2581                         u32 align = 4;
2582                         if (UCC_GETH_TX_BD_RING_ALIGNMENT > 4)
2583                                 align = UCC_GETH_TX_BD_RING_ALIGNMENT;
2584                         ugeth->tx_bd_ring_offset[j] =
2585                                 kmalloc((u32) (length + align), GFP_KERNEL);
2586
2587                         if (ugeth->tx_bd_ring_offset[j] != 0)
2588                                 ugeth->p_tx_bd_ring[j] =
2589                                         (void*)((ugeth->tx_bd_ring_offset[j] +
2590                                         align) & ~(align - 1));
2591                 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2592                         ugeth->tx_bd_ring_offset[j] =
2593                             qe_muram_alloc(length,
2594                                            UCC_GETH_TX_BD_RING_ALIGNMENT);
2595                         if (!IS_ERR_VALUE(ugeth->tx_bd_ring_offset[j]))
2596                                 ugeth->p_tx_bd_ring[j] =
2597                                     (u8 *) qe_muram_addr(ugeth->
2598                                                          tx_bd_ring_offset[j]);
2599                 }
2600                 if (!ugeth->p_tx_bd_ring[j]) {
2601                         ugeth_err
2602                             ("%s: Can not allocate memory for Tx bd rings.",
2603                              __FUNCTION__);
2604                         ucc_geth_memclean(ugeth);
2605                         return -ENOMEM;
2606                 }
2607                 /* Zero unused end of bd ring, according to spec */
2608                 memset(ugeth->p_tx_bd_ring[j] +
2609                        ug_info->bdRingLenTx[j] * sizeof(struct qe_bd), 0,
2610                        length - ug_info->bdRingLenTx[j] * sizeof(struct qe_bd));
2611         }
2612
2613         /* Allocate Rx bds */
2614         for (j = 0; j < ug_info->numQueuesRx; j++) {
2615                 length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd);
2616                 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2617                         u32 align = 4;
2618                         if (UCC_GETH_RX_BD_RING_ALIGNMENT > 4)
2619                                 align = UCC_GETH_RX_BD_RING_ALIGNMENT;
2620                         ugeth->rx_bd_ring_offset[j] =
2621                                 kmalloc((u32) (length + align), GFP_KERNEL);
2622                         if (ugeth->rx_bd_ring_offset[j] != 0)
2623                                 ugeth->p_rx_bd_ring[j] =
2624                                         (void*)((ugeth->rx_bd_ring_offset[j] +
2625                                         align) & ~(align - 1));
2626                 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2627                         ugeth->rx_bd_ring_offset[j] =
2628                             qe_muram_alloc(length,
2629                                            UCC_GETH_RX_BD_RING_ALIGNMENT);
2630                         if (!IS_ERR_VALUE(ugeth->rx_bd_ring_offset[j]))
2631                                 ugeth->p_rx_bd_ring[j] =
2632                                     (u8 *) qe_muram_addr(ugeth->
2633                                                          rx_bd_ring_offset[j]);
2634                 }
2635                 if (!ugeth->p_rx_bd_ring[j]) {
2636                         ugeth_err
2637                             ("%s: Can not allocate memory for Rx bd rings.",
2638                              __FUNCTION__);
2639                         ucc_geth_memclean(ugeth);
2640                         return -ENOMEM;
2641                 }
2642         }
2643
2644         /* Init Tx bds */
2645         for (j = 0; j < ug_info->numQueuesTx; j++) {
2646                 /* Setup the skbuff rings */
2647                 ugeth->tx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2648                                               ugeth->ug_info->bdRingLenTx[j],
2649                                               GFP_KERNEL);
2650
2651                 if (ugeth->tx_skbuff[j] == NULL) {
2652                         ugeth_err("%s: Could not allocate tx_skbuff",
2653                                   __FUNCTION__);
2654                         ucc_geth_memclean(ugeth);
2655                         return -ENOMEM;
2656                 }
2657
2658                 for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++)
2659                         ugeth->tx_skbuff[j][i] = NULL;
2660
2661                 ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0;
2662                 bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j];
2663                 for (i = 0; i < ug_info->bdRingLenTx[j]; i++) {
2664                         /* clear bd buffer */
2665                         out_be32(&((struct qe_bd *)bd)->buf, 0);
2666                         /* set bd status and length */
2667                         out_be32((u32 *)bd, 0);
2668                         bd += sizeof(struct qe_bd);
2669                 }
2670                 bd -= sizeof(struct qe_bd);
2671                 /* set bd status and length */
2672                 out_be32((u32 *)bd, T_W);       /* for last BD set Wrap bit */
2673         }
2674
2675         /* Init Rx bds */
2676         for (j = 0; j < ug_info->numQueuesRx; j++) {
2677                 /* Setup the skbuff rings */
2678                 ugeth->rx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2679                                               ugeth->ug_info->bdRingLenRx[j],
2680                                               GFP_KERNEL);
2681
2682                 if (ugeth->rx_skbuff[j] == NULL) {
2683                         ugeth_err("%s: Could not allocate rx_skbuff",
2684                                   __FUNCTION__);
2685                         ucc_geth_memclean(ugeth);
2686                         return -ENOMEM;
2687                 }
2688
2689                 for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++)
2690                         ugeth->rx_skbuff[j][i] = NULL;
2691
2692                 ugeth->skb_currx[j] = 0;
2693                 bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j];
2694                 for (i = 0; i < ug_info->bdRingLenRx[j]; i++) {
2695                         /* set bd status and length */
2696                         out_be32((u32 *)bd, R_I);
2697                         /* clear bd buffer */
2698                         out_be32(&((struct qe_bd *)bd)->buf, 0);
2699                         bd += sizeof(struct qe_bd);
2700                 }
2701                 bd -= sizeof(struct qe_bd);
2702                 /* set bd status and length */
2703                 out_be32((u32 *)bd, R_W); /* for last BD set Wrap bit */
2704         }
2705
2706         /*
2707          * Global PRAM
2708          */
2709         /* Tx global PRAM */
2710         /* Allocate global tx parameter RAM page */
2711         ugeth->tx_glbl_pram_offset =
2712             qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram),
2713                            UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT);
2714         if (IS_ERR_VALUE(ugeth->tx_glbl_pram_offset)) {
2715                 ugeth_err
2716                     ("%s: Can not allocate DPRAM memory for p_tx_glbl_pram.",
2717                      __FUNCTION__);
2718                 ucc_geth_memclean(ugeth);
2719                 return -ENOMEM;
2720         }
2721         ugeth->p_tx_glbl_pram =
2722             (struct ucc_geth_tx_global_pram *) qe_muram_addr(ugeth->
2723                                                         tx_glbl_pram_offset);
2724         /* Zero out p_tx_glbl_pram */
2725         memset(ugeth->p_tx_glbl_pram, 0, sizeof(struct ucc_geth_tx_global_pram));
2726
2727         /* Fill global PRAM */
2728
2729         /* TQPTR */
2730         /* Size varies with number of Tx threads */
2731         ugeth->thread_dat_tx_offset =
2732             qe_muram_alloc(numThreadsTxNumerical *
2733                            sizeof(struct ucc_geth_thread_data_tx) +
2734                            32 * (numThreadsTxNumerical == 1),
2735                            UCC_GETH_THREAD_DATA_ALIGNMENT);
2736         if (IS_ERR_VALUE(ugeth->thread_dat_tx_offset)) {
2737                 ugeth_err
2738                     ("%s: Can not allocate DPRAM memory for p_thread_data_tx.",
2739                      __FUNCTION__);
2740                 ucc_geth_memclean(ugeth);
2741                 return -ENOMEM;
2742         }
2743
2744         ugeth->p_thread_data_tx =
2745             (struct ucc_geth_thread_data_tx *) qe_muram_addr(ugeth->
2746                                                         thread_dat_tx_offset);
2747         out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset);
2748
2749         /* vtagtable */
2750         for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++)
2751                 out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i],
2752                          ug_info->vtagtable[i]);
2753
2754         /* iphoffset */
2755         for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++)
2756                 ugeth->p_tx_glbl_pram->iphoffset[i] = ug_info->iphoffset[i];
2757
2758         /* SQPTR */
2759         /* Size varies with number of Tx queues */
2760         ugeth->send_q_mem_reg_offset =
2761             qe_muram_alloc(ug_info->numQueuesTx *
2762                            sizeof(struct ucc_geth_send_queue_qd),
2763                            UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
2764         if (IS_ERR_VALUE(ugeth->send_q_mem_reg_offset)) {
2765                 ugeth_err
2766                     ("%s: Can not allocate DPRAM memory for p_send_q_mem_reg.",
2767                      __FUNCTION__);
2768                 ucc_geth_memclean(ugeth);
2769                 return -ENOMEM;
2770         }
2771
2772         ugeth->p_send_q_mem_reg =
2773             (struct ucc_geth_send_queue_mem_region *) qe_muram_addr(ugeth->
2774                         send_q_mem_reg_offset);
2775         out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset);
2776
2777         /* Setup the table */
2778         /* Assume BD rings are already established */
2779         for (i = 0; i < ug_info->numQueuesTx; i++) {
2780                 endOfRing =
2781                     ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] -
2782                                               1) * sizeof(struct qe_bd);
2783                 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2784                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2785                                  (u32) virt_to_phys(ugeth->p_tx_bd_ring[i]));
2786                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2787                                  last_bd_completed_address,
2788                                  (u32) virt_to_phys(endOfRing));
2789                 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2790                            MEM_PART_MURAM) {
2791                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2792                                  (u32) immrbar_virt_to_phys(ugeth->
2793                                                             p_tx_bd_ring[i]));
2794                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2795                                  last_bd_completed_address,
2796                                  (u32) immrbar_virt_to_phys(endOfRing));
2797                 }
2798         }
2799
2800         /* schedulerbasepointer */
2801
2802         if (ug_info->numQueuesTx > 1) {
2803         /* scheduler exists only if more than 1 tx queue */
2804                 ugeth->scheduler_offset =
2805                     qe_muram_alloc(sizeof(struct ucc_geth_scheduler),
2806                                    UCC_GETH_SCHEDULER_ALIGNMENT);
2807                 if (IS_ERR_VALUE(ugeth->scheduler_offset)) {
2808                         ugeth_err
2809                          ("%s: Can not allocate DPRAM memory for p_scheduler.",
2810                              __FUNCTION__);
2811                         ucc_geth_memclean(ugeth);
2812                         return -ENOMEM;
2813                 }
2814
2815                 ugeth->p_scheduler =
2816                     (struct ucc_geth_scheduler *) qe_muram_addr(ugeth->
2817                                                            scheduler_offset);
2818                 out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer,
2819                          ugeth->scheduler_offset);
2820                 /* Zero out p_scheduler */
2821                 memset(ugeth->p_scheduler, 0, sizeof(struct ucc_geth_scheduler));
2822
2823                 /* Set values in scheduler */
2824                 out_be32(&ugeth->p_scheduler->mblinterval,
2825                          ug_info->mblinterval);
2826                 out_be16(&ugeth->p_scheduler->nortsrbytetime,
2827                          ug_info->nortsrbytetime);
2828                 ugeth->p_scheduler->fracsiz = ug_info->fracsiz;
2829                 ugeth->p_scheduler->strictpriorityq = ug_info->strictpriorityq;
2830                 ugeth->p_scheduler->txasap = ug_info->txasap;
2831                 ugeth->p_scheduler->extrabw = ug_info->extrabw;
2832                 for (i = 0; i < NUM_TX_QUEUES; i++)
2833                         ugeth->p_scheduler->weightfactor[i] =
2834                             ug_info->weightfactor[i];
2835
2836                 /* Set pointers to cpucount registers in scheduler */
2837                 ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0);
2838                 ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1);
2839                 ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2);
2840                 ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3);
2841                 ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4);
2842                 ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5);
2843                 ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6);
2844                 ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7);
2845         }
2846
2847         /* schedulerbasepointer */
2848         /* TxRMON_PTR (statistics) */
2849         if (ug_info->
2850             statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) {
2851                 ugeth->tx_fw_statistics_pram_offset =
2852                     qe_muram_alloc(sizeof
2853                                    (struct ucc_geth_tx_firmware_statistics_pram),
2854                                    UCC_GETH_TX_STATISTICS_ALIGNMENT);
2855                 if (IS_ERR_VALUE(ugeth->tx_fw_statistics_pram_offset)) {
2856                         ugeth_err
2857                             ("%s: Can not allocate DPRAM memory for"
2858                                 " p_tx_fw_statistics_pram.", __FUNCTION__);
2859                         ucc_geth_memclean(ugeth);
2860                         return -ENOMEM;
2861                 }
2862                 ugeth->p_tx_fw_statistics_pram =
2863                     (struct ucc_geth_tx_firmware_statistics_pram *)
2864                     qe_muram_addr(ugeth->tx_fw_statistics_pram_offset);
2865                 /* Zero out p_tx_fw_statistics_pram */
2866                 memset(ugeth->p_tx_fw_statistics_pram,
2867                        0, sizeof(struct ucc_geth_tx_firmware_statistics_pram));
2868         }
2869
2870         /* temoder */
2871         /* Already has speed set */
2872
2873         if (ug_info->numQueuesTx > 1)
2874                 temoder |= TEMODER_SCHEDULER_ENABLE;
2875         if (ug_info->ipCheckSumGenerate)
2876                 temoder |= TEMODER_IP_CHECKSUM_GENERATE;
2877         temoder |= ((ug_info->numQueuesTx - 1) << TEMODER_NUM_OF_QUEUES_SHIFT);
2878         out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder);
2879
2880         test = in_be16(&ugeth->p_tx_glbl_pram->temoder);
2881
2882         /* Function code register value to be used later */
2883         function_code = QE_BMR_BYTE_ORDER_BO_MOT | UCC_FAST_FUNCTION_CODE_GBL;
2884         /* Required for QE */
2885
2886         /* function code register */
2887         out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24);
2888
2889         /* Rx global PRAM */
2890         /* Allocate global rx parameter RAM page */
2891         ugeth->rx_glbl_pram_offset =
2892             qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram),
2893                            UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT);
2894         if (IS_ERR_VALUE(ugeth->rx_glbl_pram_offset)) {
2895                 ugeth_err
2896                     ("%s: Can not allocate DPRAM memory for p_rx_glbl_pram.",
2897                      __FUNCTION__);
2898                 ucc_geth_memclean(ugeth);
2899                 return -ENOMEM;
2900         }
2901         ugeth->p_rx_glbl_pram =
2902             (struct ucc_geth_rx_global_pram *) qe_muram_addr(ugeth->
2903                                                         rx_glbl_pram_offset);
2904         /* Zero out p_rx_glbl_pram */
2905         memset(ugeth->p_rx_glbl_pram, 0, sizeof(struct ucc_geth_rx_global_pram));
2906
2907         /* Fill global PRAM */
2908
2909         /* RQPTR */
2910         /* Size varies with number of Rx threads */
2911         ugeth->thread_dat_rx_offset =
2912             qe_muram_alloc(numThreadsRxNumerical *
2913                            sizeof(struct ucc_geth_thread_data_rx),
2914                            UCC_GETH_THREAD_DATA_ALIGNMENT);
2915         if (IS_ERR_VALUE(ugeth->thread_dat_rx_offset)) {
2916                 ugeth_err
2917                     ("%s: Can not allocate DPRAM memory for p_thread_data_rx.",
2918                      __FUNCTION__);
2919                 ucc_geth_memclean(ugeth);
2920                 return -ENOMEM;
2921         }
2922
2923         ugeth->p_thread_data_rx =
2924             (struct ucc_geth_thread_data_rx *) qe_muram_addr(ugeth->
2925                                                         thread_dat_rx_offset);
2926         out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset);
2927
2928         /* typeorlen */
2929         out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen);
2930
2931         /* rxrmonbaseptr (statistics) */
2932         if (ug_info->
2933             statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) {
2934                 ugeth->rx_fw_statistics_pram_offset =
2935                     qe_muram_alloc(sizeof
2936                                    (struct ucc_geth_rx_firmware_statistics_pram),
2937                                    UCC_GETH_RX_STATISTICS_ALIGNMENT);
2938                 if (IS_ERR_VALUE(ugeth->rx_fw_statistics_pram_offset)) {
2939                         ugeth_err
2940                                 ("%s: Can not allocate DPRAM memory for"
2941                                 " p_rx_fw_statistics_pram.", __FUNCTION__);
2942                         ucc_geth_memclean(ugeth);
2943                         return -ENOMEM;
2944                 }
2945                 ugeth->p_rx_fw_statistics_pram =
2946                     (struct ucc_geth_rx_firmware_statistics_pram *)
2947                     qe_muram_addr(ugeth->rx_fw_statistics_pram_offset);
2948                 /* Zero out p_rx_fw_statistics_pram */
2949                 memset(ugeth->p_rx_fw_statistics_pram, 0,
2950                        sizeof(struct ucc_geth_rx_firmware_statistics_pram));
2951         }
2952
2953         /* intCoalescingPtr */
2954
2955         /* Size varies with number of Rx queues */
2956         ugeth->rx_irq_coalescing_tbl_offset =
2957             qe_muram_alloc(ug_info->numQueuesRx *
2958                            sizeof(struct ucc_geth_rx_interrupt_coalescing_entry)
2959                            + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT);
2960         if (IS_ERR_VALUE(ugeth->rx_irq_coalescing_tbl_offset)) {
2961                 ugeth_err
2962                     ("%s: Can not allocate DPRAM memory for"
2963                         " p_rx_irq_coalescing_tbl.", __FUNCTION__);
2964                 ucc_geth_memclean(ugeth);
2965                 return -ENOMEM;
2966         }
2967
2968         ugeth->p_rx_irq_coalescing_tbl =
2969             (struct ucc_geth_rx_interrupt_coalescing_table *)
2970             qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset);
2971         out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr,
2972                  ugeth->rx_irq_coalescing_tbl_offset);
2973
2974         /* Fill interrupt coalescing table */
2975         for (i = 0; i < ug_info->numQueuesRx; i++) {
2976                 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2977                          interruptcoalescingmaxvalue,
2978                          ug_info->interruptcoalescingmaxvalue[i]);
2979                 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2980                          interruptcoalescingcounter,
2981                          ug_info->interruptcoalescingmaxvalue[i]);
2982         }
2983
2984         /* MRBLR */
2985         init_max_rx_buff_len(uf_info->max_rx_buf_length,
2986                              &ugeth->p_rx_glbl_pram->mrblr);
2987         /* MFLR */
2988         out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength);
2989         /* MINFLR */
2990         init_min_frame_len(ug_info->minFrameLength,
2991                            &ugeth->p_rx_glbl_pram->minflr,
2992                            &ugeth->p_rx_glbl_pram->mrblr);
2993         /* MAXD1 */
2994         out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length);
2995         /* MAXD2 */
2996         out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length);
2997
2998         /* l2qt */
2999         l2qt = 0;
3000         for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++)
3001                 l2qt |= (ug_info->l2qt[i] << (28 - 4 * i));
3002         out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt);
3003
3004         /* l3qt */
3005         for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) {
3006                 l3qt = 0;
3007                 for (i = 0; i < 8; i++)
3008                         l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i));
3009                 out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt);
3010         }
3011
3012         /* vlantype */
3013         out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype);
3014
3015         /* vlantci */
3016         out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci);
3017
3018         /* ecamptr */
3019         out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr);
3020
3021         /* RBDQPTR */
3022         /* Size varies with number of Rx queues */
3023         ugeth->rx_bd_qs_tbl_offset =
3024             qe_muram_alloc(ug_info->numQueuesRx *
3025                            (sizeof(struct ucc_geth_rx_bd_queues_entry) +
3026                             sizeof(struct ucc_geth_rx_prefetched_bds)),
3027                            UCC_GETH_RX_BD_QUEUES_ALIGNMENT);
3028         if (IS_ERR_VALUE(ugeth->rx_bd_qs_tbl_offset)) {
3029                 ugeth_err
3030                     ("%s: Can not allocate DPRAM memory for p_rx_bd_qs_tbl.",
3031                      __FUNCTION__);
3032                 ucc_geth_memclean(ugeth);
3033                 return -ENOMEM;
3034         }
3035
3036         ugeth->p_rx_bd_qs_tbl =
3037             (struct ucc_geth_rx_bd_queues_entry *) qe_muram_addr(ugeth->
3038                                     rx_bd_qs_tbl_offset);
3039         out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset);
3040         /* Zero out p_rx_bd_qs_tbl */
3041         memset(ugeth->p_rx_bd_qs_tbl,
3042                0,
3043                ug_info->numQueuesRx * (sizeof(struct ucc_geth_rx_bd_queues_entry) +
3044                                        sizeof(struct ucc_geth_rx_prefetched_bds)));
3045
3046         /* Setup the table */
3047         /* Assume BD rings are already established */
3048         for (i = 0; i < ug_info->numQueuesRx; i++) {
3049                 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
3050                         out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
3051                                  (u32) virt_to_phys(ugeth->p_rx_bd_ring[i]));
3052                 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
3053                            MEM_PART_MURAM) {
3054                         out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
3055                                  (u32) immrbar_virt_to_phys(ugeth->
3056                                                             p_rx_bd_ring[i]));
3057                 }
3058                 /* rest of fields handled by QE */
3059         }
3060
3061         /* remoder */
3062         /* Already has speed set */
3063
3064         if (ugeth->rx_extended_features)
3065                 remoder |= REMODER_RX_EXTENDED_FEATURES;
3066         if (ug_info->rxExtendedFiltering)
3067                 remoder |= REMODER_RX_EXTENDED_FILTERING;
3068         if (ug_info->dynamicMaxFrameLength)
3069                 remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH;
3070         if (ug_info->dynamicMinFrameLength)
3071                 remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH;
3072         remoder |=
3073             ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT;
3074         remoder |=
3075             ug_info->
3076             vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT;
3077         remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT;
3078         remoder |= ((ug_info->numQueuesRx - 1) << REMODER_NUM_OF_QUEUES_SHIFT);
3079         if (ug_info->ipCheckSumCheck)
3080                 remoder |= REMODER_IP_CHECKSUM_CHECK;
3081         if (ug_info->ipAddressAlignment)
3082                 remoder |= REMODER_IP_ADDRESS_ALIGNMENT;
3083         out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder);
3084
3085         /* Note that this function must be called */
3086         /* ONLY AFTER p_tx_fw_statistics_pram */
3087         /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */
3088         init_firmware_statistics_gathering_mode((ug_info->
3089                 statisticsMode &
3090                 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX),
3091                 (ug_info->statisticsMode &
3092                 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX),
3093                 &ugeth->p_tx_glbl_pram->txrmonbaseptr,
3094                 ugeth->tx_fw_statistics_pram_offset,
3095                 &ugeth->p_rx_glbl_pram->rxrmonbaseptr,
3096                 ugeth->rx_fw_statistics_pram_offset,
3097                 &ugeth->p_tx_glbl_pram->temoder,
3098                 &ugeth->p_rx_glbl_pram->remoder);
3099
3100         /* function code register */
3101         ugeth->p_rx_glbl_pram->rstate = function_code;
3102
3103         /* initialize extended filtering */
3104         if (ug_info->rxExtendedFiltering) {
3105                 if (!ug_info->extendedFilteringChainPointer) {
3106                         ugeth_err("%s: Null Extended Filtering Chain Pointer.",
3107                                   __FUNCTION__);
3108                         ucc_geth_memclean(ugeth);
3109                         return -EINVAL;
3110                 }
3111
3112                 /* Allocate memory for extended filtering Mode Global
3113                 Parameters */
3114                 ugeth->exf_glbl_param_offset =
3115                     qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram),
3116                 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT);
3117                 if (IS_ERR_VALUE(ugeth->exf_glbl_param_offset)) {
3118                         ugeth_err
3119                                 ("%s: Can not allocate DPRAM memory for"
3120                                 " p_exf_glbl_param.", __FUNCTION__);
3121                         ucc_geth_memclean(ugeth);
3122                         return -ENOMEM;
3123                 }
3124
3125                 ugeth->p_exf_glbl_param =
3126                     (struct ucc_geth_exf_global_pram *) qe_muram_addr(ugeth->
3127                                  exf_glbl_param_offset);
3128                 out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam,
3129                          ugeth->exf_glbl_param_offset);
3130                 out_be32(&ugeth->p_exf_glbl_param->l2pcdptr,
3131                          (u32) ug_info->extendedFilteringChainPointer);
3132
3133         } else {                /* initialize 82xx style address filtering */
3134
3135                 /* Init individual address recognition registers to disabled */
3136
3137                 for (j = 0; j < NUM_OF_PADDRS; j++)
3138                         ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j);
3139
3140                 p_82xx_addr_filt =
3141                     (struct ucc_geth_82xx_address_filtering_pram *) ugeth->
3142                     p_rx_glbl_pram->addressfiltering;
3143
3144                 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
3145                         ENET_ADDR_TYPE_GROUP);
3146                 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
3147                         ENET_ADDR_TYPE_INDIVIDUAL);
3148         }
3149
3150         /*
3151          * Initialize UCC at QE level
3152          */
3153
3154         command = QE_INIT_TX_RX;
3155
3156         /* Allocate shadow InitEnet command parameter structure.
3157          * This is needed because after the InitEnet command is executed,
3158          * the structure in DPRAM is released, because DPRAM is a premium
3159          * resource.
3160          * This shadow structure keeps a copy of what was done so that the
3161          * allocated resources can be released when the channel is freed.
3162          */
3163         if (!(ugeth->p_init_enet_param_shadow =
3164               kmalloc(sizeof(struct ucc_geth_init_pram), GFP_KERNEL))) {
3165                 ugeth_err
3166                     ("%s: Can not allocate memory for"
3167                         " p_UccInitEnetParamShadows.", __FUNCTION__);
3168                 ucc_geth_memclean(ugeth);
3169                 return -ENOMEM;
3170         }
3171         /* Zero out *p_init_enet_param_shadow */
3172         memset((char *)ugeth->p_init_enet_param_shadow,
3173                0, sizeof(struct ucc_geth_init_pram));
3174
3175         /* Fill shadow InitEnet command parameter structure */
3176
3177         ugeth->p_init_enet_param_shadow->resinit1 =
3178             ENET_INIT_PARAM_MAGIC_RES_INIT1;
3179         ugeth->p_init_enet_param_shadow->resinit2 =
3180             ENET_INIT_PARAM_MAGIC_RES_INIT2;
3181         ugeth->p_init_enet_param_shadow->resinit3 =
3182             ENET_INIT_PARAM_MAGIC_RES_INIT3;
3183         ugeth->p_init_enet_param_shadow->resinit4 =
3184             ENET_INIT_PARAM_MAGIC_RES_INIT4;
3185         ugeth->p_init_enet_param_shadow->resinit5 =
3186             ENET_INIT_PARAM_MAGIC_RES_INIT5;
3187         ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
3188             ((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT;
3189         ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
3190             ((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT;
3191
3192         ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
3193             ugeth->rx_glbl_pram_offset | ug_info->riscRx;
3194         if ((ug_info->largestexternallookupkeysize !=
3195              QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE)
3196             && (ug_info->largestexternallookupkeysize !=
3197                 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
3198             && (ug_info->largestexternallookupkeysize !=
3199                 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)) {
3200                 ugeth_err("%s: Invalid largest External Lookup Key Size.",
3201                           __FUNCTION__);
3202                 ucc_geth_memclean(ugeth);
3203                 return -EINVAL;
3204         }
3205         ugeth->p_init_enet_param_shadow->largestexternallookupkeysize =
3206             ug_info->largestexternallookupkeysize;
3207         size = sizeof(struct ucc_geth_thread_rx_pram);
3208         if (ug_info->rxExtendedFiltering) {
3209                 size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
3210                 if (ug_info->largestexternallookupkeysize ==
3211                     QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
3212                         size +=
3213                             THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
3214                 if (ug_info->largestexternallookupkeysize ==
3215                     QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
3216                         size +=
3217                             THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
3218         }
3219
3220         if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth->
3221                 p_init_enet_param_shadow->rxthread[0]),
3222                 (u8) (numThreadsRxNumerical + 1)
3223                 /* Rx needs one extra for terminator */
3224                 , size, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT,
3225                 ug_info->riscRx, 1)) != 0) {
3226                         ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
3227                                 __FUNCTION__);
3228                 ucc_geth_memclean(ugeth);
3229                 return ret_val;
3230         }
3231
3232         ugeth->p_init_enet_param_shadow->txglobal =
3233             ugeth->tx_glbl_pram_offset | ug_info->riscTx;
3234         if ((ret_val =
3235              fill_init_enet_entries(ugeth,
3236                                     &(ugeth->p_init_enet_param_shadow->
3237                                       txthread[0]), numThreadsTxNumerical,
3238                                     sizeof(struct ucc_geth_thread_tx_pram),
3239                                     UCC_GETH_THREAD_TX_PRAM_ALIGNMENT,
3240                                     ug_info->riscTx, 0)) != 0) {
3241                 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
3242                           __FUNCTION__);
3243                 ucc_geth_memclean(ugeth);
3244                 return ret_val;
3245         }
3246
3247         /* Load Rx bds with buffers */
3248         for (i = 0; i < ug_info->numQueuesRx; i++) {
3249                 if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) {
3250                         ugeth_err("%s: Can not fill Rx bds with buffers.",
3251                                   __FUNCTION__);
3252                         ucc_geth_memclean(ugeth);
3253                         return ret_val;
3254                 }
3255         }
3256
3257         /* Allocate InitEnet command parameter structure */
3258         init_enet_pram_offset = qe_muram_alloc(sizeof(struct ucc_geth_init_pram), 4);
3259         if (IS_ERR_VALUE(init_enet_pram_offset)) {
3260                 ugeth_err
3261                     ("%s: Can not allocate DPRAM memory for p_init_enet_pram.",
3262                      __FUNCTION__);
3263                 ucc_geth_memclean(ugeth);
3264                 return -ENOMEM;
3265         }
3266         p_init_enet_pram =
3267             (struct ucc_geth_init_pram *) qe_muram_addr(init_enet_pram_offset);
3268
3269         /* Copy shadow InitEnet command parameter structure into PRAM */
3270         p_init_enet_pram->resinit1 = ugeth->p_init_enet_param_shadow->resinit1;
3271         p_init_enet_pram->resinit2 = ugeth->p_init_enet_param_shadow->resinit2;
3272         p_init_enet_pram->resinit3 = ugeth->p_init_enet_param_shadow->resinit3;
3273         p_init_enet_pram->resinit4 = ugeth->p_init_enet_param_shadow->resinit4;
3274         out_be16(&p_init_enet_pram->resinit5,
3275                  ugeth->p_init_enet_param_shadow->resinit5);
3276         p_init_enet_pram->largestexternallookupkeysize =
3277             ugeth->p_init_enet_param_shadow->largestexternallookupkeysize;
3278         out_be32(&p_init_enet_pram->rgftgfrxglobal,
3279                  ugeth->p_init_enet_param_shadow->rgftgfrxglobal);
3280         for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_RX; i++)
3281                 out_be32(&p_init_enet_pram->rxthread[i],
3282                          ugeth->p_init_enet_param_shadow->rxthread[i]);
3283         out_be32(&p_init_enet_pram->txglobal,
3284                  ugeth->p_init_enet_param_shadow->txglobal);
3285         for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_TX; i++)
3286                 out_be32(&p_init_enet_pram->txthread[i],
3287                          ugeth->p_init_enet_param_shadow->txthread[i]);
3288
3289         /* Issue QE command */
3290         cecr_subblock =
3291             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
3292         qe_issue_cmd(command, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
3293                      init_enet_pram_offset);
3294
3295         /* Free InitEnet command parameter */
3296         qe_muram_free(init_enet_pram_offset);
3297
3298         return 0;
3299 }
3300
3301 /* returns a net_device_stats structure pointer */
3302 static struct net_device_stats *ucc_geth_get_stats(struct net_device *dev)
3303 {
3304         struct ucc_geth_private *ugeth = netdev_priv(dev);
3305
3306         return &(ugeth->stats);
3307 }
3308
3309 /* ucc_geth_timeout gets called when a packet has not been
3310  * transmitted after a set amount of time.
3311  * For now, assume that clearing out all the structures, and
3312  * starting over will fix the problem. */
3313 static void ucc_geth_timeout(struct net_device *dev)
3314 {
3315         struct ucc_geth_private *ugeth = netdev_priv(dev);
3316
3317         ugeth_vdbg("%s: IN", __FUNCTION__);
3318
3319         ugeth->stats.tx_errors++;
3320
3321         ugeth_dump_regs(ugeth);
3322
3323         if (dev->flags & IFF_UP) {
3324                 ucc_geth_stop(ugeth);
3325                 ucc_geth_startup(ugeth);
3326         }
3327
3328         netif_schedule(dev);
3329 }
3330
3331 /* This is called by the kernel when a frame is ready for transmission. */
3332 /* It is pointed to by the dev->hard_start_xmit function pointer */
3333 static int ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev)
3334 {
3335         struct ucc_geth_private *ugeth = netdev_priv(dev);
3336 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3337         struct ucc_fast_private *uccf;
3338 #endif
3339         u8 *bd;                 /* BD pointer */
3340         u32 bd_status;
3341         u8 txQ = 0;
3342
3343         ugeth_vdbg("%s: IN", __FUNCTION__);
3344
3345         spin_lock_irq(&ugeth->lock);
3346
3347         ugeth->stats.tx_bytes += skb->len;
3348
3349         /* Start from the next BD that should be filled */
3350         bd = ugeth->txBd[txQ];
3351         bd_status = in_be32((u32 *)bd);
3352         /* Save the skb pointer so we can free it later */
3353         ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb;
3354
3355         /* Update the current skb pointer (wrapping if this was the last) */
3356         ugeth->skb_curtx[txQ] =
3357             (ugeth->skb_curtx[txQ] +
3358              1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3359
3360         /* set up the buffer descriptor */
3361         out_be32(&((struct qe_bd *)bd)->buf,
3362                       dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE));
3363
3364         /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */
3365
3366         bd_status = (bd_status & T_W) | T_R | T_I | T_L | skb->len;
3367
3368         /* set bd status and length */
3369         out_be32((u32 *)bd, bd_status);
3370
3371         dev->trans_start = jiffies;
3372
3373         /* Move to next BD in the ring */
3374         if (!(bd_status & T_W))
3375                 bd += sizeof(struct qe_bd);
3376         else
3377                 bd = ugeth->p_tx_bd_ring[txQ];
3378
3379         /* If the next BD still needs to be cleaned up, then the bds
3380            are full.  We need to tell the kernel to stop sending us stuff. */
3381         if (bd == ugeth->confBd[txQ]) {
3382                 if (!netif_queue_stopped(dev))
3383                         netif_stop_queue(dev);
3384         }
3385
3386         ugeth->txBd[txQ] = bd;
3387
3388         if (ugeth->p_scheduler) {
3389                 ugeth->cpucount[txQ]++;
3390                 /* Indicate to QE that there are more Tx bds ready for
3391                 transmission */
3392                 /* This is done by writing a running counter of the bd
3393                 count to the scheduler PRAM. */
3394                 out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]);
3395         }
3396
3397 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3398         uccf = ugeth->uccf;
3399         out_be16(uccf->p_utodr, UCC_FAST_TOD);
3400 #endif
3401         spin_unlock_irq(&ugeth->lock);
3402
3403         return 0;
3404 }
3405
3406 static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit)
3407 {
3408         struct sk_buff *skb;
3409         u8 *bd;
3410         u16 length, howmany = 0;
3411         u32 bd_status;
3412         u8 *bdBuffer;
3413
3414         ugeth_vdbg("%s: IN", __FUNCTION__);
3415
3416         /* collect received buffers */
3417         bd = ugeth->rxBd[rxQ];
3418
3419         bd_status = in_be32((u32 *)bd);
3420
3421         /* while there are received buffers and BD is full (~R_E) */
3422         while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) {
3423                 bdBuffer = (u8 *) in_be32(&((struct qe_bd *)bd)->buf);
3424                 length = (u16) ((bd_status & BD_LENGTH_MASK) - 4);
3425                 skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]];
3426
3427                 /* determine whether buffer is first, last, first and last
3428                 (single buffer frame) or middle (not first and not last) */
3429                 if (!skb ||
3430                     (!(bd_status & (R_F | R_L))) ||
3431                     (bd_status & R_ERRORS_FATAL)) {
3432                         ugeth_vdbg("%s, %d: ERROR!!! skb - 0x%08x",
3433                                    __FUNCTION__, __LINE__, (u32) skb);
3434                         if (skb)
3435                                 dev_kfree_skb_any(skb);
3436
3437                         ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL;
3438                         ugeth->stats.rx_dropped++;
3439                 } else {
3440                         ugeth->stats.rx_packets++;
3441                         howmany++;
3442
3443                         /* Prep the skb for the packet */
3444                         skb_put(skb, length);
3445
3446                         /* Tell the skb what kind of packet this is */
3447                         skb->protocol = eth_type_trans(skb, ugeth->dev);
3448
3449                         ugeth->stats.rx_bytes += length;
3450                         /* Send the packet up the stack */
3451 #ifdef CONFIG_UGETH_NAPI
3452                         netif_receive_skb(skb);
3453 #else
3454                         netif_rx(skb);
3455 #endif                          /* CONFIG_UGETH_NAPI */
3456                 }
3457
3458                 ugeth->dev->last_rx = jiffies;
3459
3460                 skb = get_new_skb(ugeth, bd);
3461                 if (!skb) {
3462                         ugeth_warn("%s: No Rx Data Buffer", __FUNCTION__);
3463                         ugeth->stats.rx_dropped++;
3464                         break;
3465                 }
3466
3467                 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb;
3468
3469                 /* update to point at the next skb */
3470                 ugeth->skb_currx[rxQ] =
3471                     (ugeth->skb_currx[rxQ] +
3472                      1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]);
3473
3474                 if (bd_status & R_W)
3475                         bd = ugeth->p_rx_bd_ring[rxQ];
3476                 else
3477                         bd += sizeof(struct qe_bd);
3478
3479                 bd_status = in_be32((u32 *)bd);
3480         }
3481
3482         ugeth->rxBd[rxQ] = bd;
3483         return howmany;
3484 }
3485
3486 static int ucc_geth_tx(struct net_device *dev, u8 txQ)
3487 {
3488         /* Start from the next BD that should be filled */
3489         struct ucc_geth_private *ugeth = netdev_priv(dev);
3490         u8 *bd;                 /* BD pointer */
3491         u32 bd_status;
3492
3493         bd = ugeth->confBd[txQ];
3494         bd_status = in_be32((u32 *)bd);
3495
3496         /* Normal processing. */
3497         while ((bd_status & T_R) == 0) {
3498                 /* BD contains already transmitted buffer.   */
3499                 /* Handle the transmitted buffer and release */
3500                 /* the BD to be used with the current frame  */
3501
3502                 if ((bd == ugeth->txBd[txQ]) && (netif_queue_stopped(dev) == 0))
3503                         break;
3504
3505                 ugeth->stats.tx_packets++;
3506
3507                 /* Free the sk buffer associated with this TxBD */
3508                 dev_kfree_skb_irq(ugeth->
3509                                   tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]]);
3510                 ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL;
3511                 ugeth->skb_dirtytx[txQ] =
3512                     (ugeth->skb_dirtytx[txQ] +
3513                      1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3514
3515                 /* We freed a buffer, so now we can restart transmission */
3516                 if (netif_queue_stopped(dev))
3517                         netif_wake_queue(dev);
3518
3519                 /* Advance the confirmation BD pointer */
3520                 if (!(bd_status & T_W))
3521                         bd += sizeof(struct qe_bd);
3522                 else
3523                         bd = ugeth->p_tx_bd_ring[txQ];
3524                 bd_status = in_be32((u32 *)bd);
3525         }
3526         ugeth->confBd[txQ] = bd;
3527         return 0;
3528 }
3529
3530 #ifdef CONFIG_UGETH_NAPI
3531 static int ucc_geth_poll(struct net_device *dev, int *budget)
3532 {
3533         struct ucc_geth_private *ugeth = netdev_priv(dev);
3534         struct ucc_geth_info *ug_info;
3535         struct ucc_fast_private *uccf;
3536         int howmany;
3537         u8 i;
3538         int rx_work_limit;
3539         register u32 uccm;
3540
3541         ug_info = ugeth->ug_info;
3542
3543         rx_work_limit = *budget;
3544         if (rx_work_limit > dev->quota)
3545                 rx_work_limit = dev->quota;
3546
3547         howmany = 0;
3548
3549         for (i = 0; i < ug_info->numQueuesRx; i++) {
3550                 howmany += ucc_geth_rx(ugeth, i, rx_work_limit);
3551         }
3552
3553         dev->quota -= howmany;
3554         rx_work_limit -= howmany;
3555         *budget -= howmany;
3556
3557         if (rx_work_limit > 0) {
3558                 netif_rx_complete(dev);
3559                 uccf = ugeth->uccf;
3560                 uccm = in_be32(uccf->p_uccm);
3561                 uccm |= UCCE_RX_EVENTS;
3562                 out_be32(uccf->p_uccm, uccm);
3563         }
3564
3565         return (rx_work_limit > 0) ? 0 : 1;
3566 }
3567 #endif                          /* CONFIG_UGETH_NAPI */
3568
3569 static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
3570 {
3571         struct net_device *dev = (struct net_device *)info;
3572         struct ucc_geth_private *ugeth = netdev_priv(dev);
3573         struct ucc_fast_private *uccf;
3574         struct ucc_geth_info *ug_info;
3575         register u32 ucce;
3576         register u32 uccm;
3577 #ifndef CONFIG_UGETH_NAPI
3578         register u32 rx_mask;
3579 #endif
3580         register u32 tx_mask;
3581         u8 i;
3582
3583         ugeth_vdbg("%s: IN", __FUNCTION__);
3584
3585         if (!ugeth)
3586                 return IRQ_NONE;
3587
3588         uccf = ugeth->uccf;
3589         ug_info = ugeth->ug_info;
3590
3591         /* read and clear events */
3592         ucce = (u32) in_be32(uccf->p_ucce);
3593         uccm = (u32) in_be32(uccf->p_uccm);
3594         ucce &= uccm;
3595         out_be32(uccf->p_ucce, ucce);
3596
3597         /* check for receive events that require processing */
3598         if (ucce & UCCE_RX_EVENTS) {
3599 #ifdef CONFIG_UGETH_NAPI
3600                 if (netif_rx_schedule_prep(dev)) {
3601                 uccm &= ~UCCE_RX_EVENTS;
3602                         out_be32(uccf->p_uccm, uccm);
3603                         __netif_rx_schedule(dev);
3604                 }
3605 #else
3606                 rx_mask = UCCE_RXBF_SINGLE_MASK;
3607                 for (i = 0; i < ug_info->numQueuesRx; i++) {
3608                         if (ucce & rx_mask)
3609                                 ucc_geth_rx(ugeth, i, (int)ugeth->ug_info->bdRingLenRx[i]);
3610                         ucce &= ~rx_mask;
3611                         rx_mask <<= 1;
3612                 }
3613 #endif /* CONFIG_UGETH_NAPI */
3614         }
3615
3616         /* Tx event processing */
3617         if (ucce & UCCE_TX_EVENTS) {
3618                 spin_lock(&ugeth->lock);
3619                 tx_mask = UCCE_TXBF_SINGLE_MASK;
3620                 for (i = 0; i < ug_info->numQueuesTx; i++) {
3621                         if (ucce & tx_mask)
3622                                 ucc_geth_tx(dev, i);
3623                         ucce &= ~tx_mask;
3624                         tx_mask <<= 1;
3625                 }
3626                 spin_unlock(&ugeth->lock);
3627         }
3628
3629         /* Errors and other events */
3630         if (ucce & UCCE_OTHER) {
3631                 if (ucce & UCCE_BSY) {
3632                         ugeth->stats.rx_errors++;
3633                 }
3634                 if (ucce & UCCE_TXE) {
3635                         ugeth->stats.tx_errors++;
3636                 }
3637         }
3638
3639         return IRQ_HANDLED;
3640 }
3641
3642 /* Called when something needs to use the ethernet device */
3643 /* Returns 0 for success. */
3644 static int ucc_geth_open(struct net_device *dev)
3645 {
3646         struct ucc_geth_private *ugeth = netdev_priv(dev);
3647         int err;
3648
3649         ugeth_vdbg("%s: IN", __FUNCTION__);
3650
3651         /* Test station address */
3652         if (dev->dev_addr[0] & ENET_GROUP_ADDR) {
3653                 ugeth_err("%s: Multicast address used for station address"
3654                           " - is this what you wanted?", __FUNCTION__);
3655                 return -EINVAL;
3656         }
3657
3658         err = ucc_struct_init(ugeth);
3659         if (err) {
3660                 ugeth_err("%s: Cannot configure internal struct, aborting.", dev->name);
3661                 return err;
3662         }
3663
3664         err = ucc_geth_startup(ugeth);
3665         if (err) {
3666                 ugeth_err("%s: Cannot configure net device, aborting.",
3667                           dev->name);
3668                 return err;
3669         }
3670
3671         err = adjust_enet_interface(ugeth);
3672         if (err) {
3673                 ugeth_err("%s: Cannot configure net device, aborting.",
3674                           dev->name);
3675                 return err;
3676         }
3677
3678         /*       Set MACSTNADDR1, MACSTNADDR2                */
3679         /* For more details see the hardware spec.           */
3680         init_mac_station_addr_regs(dev->dev_addr[0],
3681                                    dev->dev_addr[1],
3682                                    dev->dev_addr[2],
3683                                    dev->dev_addr[3],
3684                                    dev->dev_addr[4],
3685                                    dev->dev_addr[5],
3686                                    &ugeth->ug_regs->macstnaddr1,
3687                                    &ugeth->ug_regs->macstnaddr2);
3688
3689         err = init_phy(dev);
3690         if (err) {
3691                 ugeth_err("%s: Cannot initialize PHY, aborting.", dev->name);
3692                 return err;
3693         }
3694
3695         phy_start(ugeth->phydev);
3696
3697         err =
3698             request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler, 0,
3699                         "UCC Geth", dev);
3700         if (err) {
3701                 ugeth_err("%s: Cannot get IRQ for net device, aborting.",
3702                           dev->name);
3703                 ucc_geth_stop(ugeth);
3704                 return err;
3705         }
3706
3707         err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
3708         if (err) {
3709                 ugeth_err("%s: Cannot enable net device, aborting.", dev->name);
3710                 ucc_geth_stop(ugeth);
3711                 return err;
3712         }
3713
3714         netif_start_queue(dev);
3715
3716         return err;
3717 }
3718
3719 /* Stops the kernel queue, and halts the controller */
3720 static int ucc_geth_close(struct net_device *dev)
3721 {
3722         struct ucc_geth_private *ugeth = netdev_priv(dev);
3723
3724         ugeth_vdbg("%s: IN", __FUNCTION__);
3725
3726         ucc_geth_stop(ugeth);
3727
3728         phy_disconnect(ugeth->phydev);
3729         ugeth->phydev = NULL;
3730
3731         netif_stop_queue(dev);
3732
3733         return 0;
3734 }
3735
3736 static phy_interface_t to_phy_interface(const char *phy_connection_type)
3737 {
3738         if (strcasecmp(phy_connection_type, "mii") == 0)
3739                 return PHY_INTERFACE_MODE_MII;
3740         if (strcasecmp(phy_connection_type, "gmii") == 0)
3741                 return PHY_INTERFACE_MODE_GMII;
3742         if (strcasecmp(phy_connection_type, "tbi") == 0)
3743                 return PHY_INTERFACE_MODE_TBI;
3744         if (strcasecmp(phy_connection_type, "rmii") == 0)
3745                 return PHY_INTERFACE_MODE_RMII;
3746         if (strcasecmp(phy_connection_type, "rgmii") == 0)
3747                 return PHY_INTERFACE_MODE_RGMII;
3748         if (strcasecmp(phy_connection_type, "rgmii-id") == 0)
3749                 return PHY_INTERFACE_MODE_RGMII_ID;
3750         if (strcasecmp(phy_connection_type, "rtbi") == 0)
3751                 return PHY_INTERFACE_MODE_RTBI;
3752
3753         return PHY_INTERFACE_MODE_MII;
3754 }
3755
3756 static int ucc_geth_probe(struct of_device* ofdev, const struct of_device_id *match)
3757 {
3758         struct device *device = &ofdev->dev;
3759         struct device_node *np = ofdev->node;
3760         struct device_node *mdio;
3761         struct net_device *dev = NULL;
3762         struct ucc_geth_private *ugeth = NULL;
3763         struct ucc_geth_info *ug_info;
3764         struct resource res;
3765         struct device_node *phy;
3766         int err, ucc_num, max_speed = 0;
3767         const phandle *ph;
3768         const unsigned int *prop;
3769         const void *mac_addr;
3770         phy_interface_t phy_interface;
3771         static const int enet_to_speed[] = {
3772                 SPEED_10, SPEED_10, SPEED_10,
3773                 SPEED_100, SPEED_100, SPEED_100,
3774                 SPEED_1000, SPEED_1000, SPEED_1000, SPEED_1000,
3775         };
3776         static const phy_interface_t enet_to_phy_interface[] = {
3777                 PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_RMII,
3778                 PHY_INTERFACE_MODE_RGMII, PHY_INTERFACE_MODE_MII,
3779                 PHY_INTERFACE_MODE_RMII, PHY_INTERFACE_MODE_RGMII,
3780                 PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_RGMII,
3781                 PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RTBI,
3782         };
3783
3784         ugeth_vdbg("%s: IN", __FUNCTION__);
3785
3786         prop = of_get_property(np, "device-id", NULL);
3787         ucc_num = *prop - 1;
3788         if ((ucc_num < 0) || (ucc_num > 7))
3789                 return -ENODEV;
3790
3791         ug_info = &ugeth_info[ucc_num];
3792         ug_info->uf_info.ucc_num = ucc_num;
3793
3794         prop = of_get_property(np, "rx-clock", NULL);
3795         ug_info->uf_info.rx_clock = *prop;
3796         prop = of_get_property(np, "tx-clock", NULL);
3797         ug_info->uf_info.tx_clock = *prop;
3798         err = of_address_to_resource(np, 0, &res);
3799         if (err)
3800                 return -EINVAL;
3801
3802         ug_info->uf_info.regs = res.start;
3803         ug_info->uf_info.irq = irq_of_parse_and_map(np, 0);
3804
3805         ph = of_get_property(np, "phy-handle", NULL);
3806         phy = of_find_node_by_phandle(*ph);
3807
3808         if (phy == NULL)
3809                 return -ENODEV;
3810
3811         /* set the PHY address */
3812         prop = of_get_property(phy, "reg", NULL);
3813         if (prop == NULL)
3814                 return -1;
3815         ug_info->phy_address = *prop;
3816
3817         /* get the phy interface type, or default to MII */
3818         prop = of_get_property(np, "phy-connection-type", NULL);
3819         if (!prop) {
3820                 /* handle interface property present in old trees */
3821                 prop = of_get_property(phy, "interface", NULL);
3822                 if (prop != NULL) {
3823                         phy_interface = enet_to_phy_interface[*prop];
3824                         max_speed = enet_to_speed[*prop];
3825                 } else
3826                         phy_interface = PHY_INTERFACE_MODE_MII;
3827         } else {
3828                 phy_interface = to_phy_interface((const char *)prop);
3829         }
3830
3831         /* get speed, or derive from PHY interface */
3832         if (max_speed == 0)
3833                 switch (phy_interface) {
3834                 case PHY_INTERFACE_MODE_GMII:
3835                 case PHY_INTERFACE_MODE_RGMII:
3836                 case PHY_INTERFACE_MODE_RGMII_ID:
3837                 case PHY_INTERFACE_MODE_TBI:
3838                 case PHY_INTERFACE_MODE_RTBI:
3839                         max_speed = SPEED_1000;
3840                         break;
3841                 default:
3842                         max_speed = SPEED_100;
3843                         break;
3844                 }
3845
3846         if (max_speed == SPEED_1000) {
3847                 /* configure muram FIFOs for gigabit operation */
3848                 ug_info->uf_info.urfs = UCC_GETH_URFS_GIGA_INIT;
3849                 ug_info->uf_info.urfet = UCC_GETH_URFET_GIGA_INIT;
3850                 ug_info->uf_info.urfset = UCC_GETH_URFSET_GIGA_INIT;
3851                 ug_info->uf_info.utfs = UCC_GETH_UTFS_GIGA_INIT;
3852                 ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT;
3853                 ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT;
3854         }
3855
3856         /* Set the bus id */
3857         mdio = of_get_parent(phy);
3858
3859         if (mdio == NULL)
3860                 return -1;
3861
3862         err = of_address_to_resource(mdio, 0, &res);
3863         of_node_put(mdio);
3864
3865         if (err)
3866                 return -1;
3867
3868         ug_info->mdio_bus = res.start;
3869
3870         printk(KERN_INFO "ucc_geth: UCC%1d at 0x%8x (irq = %d) \n",
3871                 ug_info->uf_info.ucc_num + 1, ug_info->uf_info.regs,
3872                 ug_info->uf_info.irq);
3873
3874         if (ug_info == NULL) {
3875                 ugeth_err("%s: [%d] Missing additional data!", __FUNCTION__,
3876                           ucc_num);
3877                 return -ENODEV;
3878         }
3879
3880         /* Create an ethernet device instance */
3881         dev = alloc_etherdev(sizeof(*ugeth));
3882
3883         if (dev == NULL)
3884                 return -ENOMEM;
3885
3886         ugeth = netdev_priv(dev);
3887         spin_lock_init(&ugeth->lock);
3888
3889         dev_set_drvdata(device, dev);
3890
3891         /* Set the dev->base_addr to the gfar reg region */
3892         dev->base_addr = (unsigned long)(ug_info->uf_info.regs);
3893
3894         SET_MODULE_OWNER(dev);
3895         SET_NETDEV_DEV(dev, device);
3896
3897         /* Fill in the dev structure */
3898         uec_set_ethtool_ops(dev);
3899         dev->open = ucc_geth_open;
3900         dev->hard_start_xmit = ucc_geth_start_xmit;
3901         dev->tx_timeout = ucc_geth_timeout;
3902         dev->watchdog_timeo = TX_TIMEOUT;
3903 #ifdef CONFIG_UGETH_NAPI
3904         dev->poll = ucc_geth_poll;
3905         dev->weight = UCC_GETH_DEV_WEIGHT;
3906 #endif                          /* CONFIG_UGETH_NAPI */
3907         dev->stop = ucc_geth_close;
3908         dev->get_stats = ucc_geth_get_stats;
3909 //    dev->change_mtu = ucc_geth_change_mtu;
3910         dev->mtu = 1500;
3911         dev->set_multicast_list = ucc_geth_set_multi;
3912
3913         ugeth->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
3914         ugeth->phy_interface = phy_interface;
3915         ugeth->max_speed = max_speed;
3916
3917         err = register_netdev(dev);
3918         if (err) {
3919                 ugeth_err("%s: Cannot register net device, aborting.",
3920                           dev->name);
3921                 free_netdev(dev);
3922                 return err;
3923         }
3924
3925         mac_addr = of_get_mac_address(np);
3926         if (mac_addr)
3927                 memcpy(dev->dev_addr, mac_addr, 6);
3928
3929         ugeth->ug_info = ug_info;
3930         ugeth->dev = dev;
3931
3932         return 0;
3933 }
3934
3935 static int ucc_geth_remove(struct of_device* ofdev)
3936 {
3937         struct device *device = &ofdev->dev;
3938         struct net_device *dev = dev_get_drvdata(device);
3939         struct ucc_geth_private *ugeth = netdev_priv(dev);
3940
3941         dev_set_drvdata(device, NULL);
3942         ucc_geth_memclean(ugeth);
3943         free_netdev(dev);
3944
3945         return 0;
3946 }
3947
3948 static struct of_device_id ucc_geth_match[] = {
3949         {
3950                 .type = "network",
3951                 .compatible = "ucc_geth",
3952         },
3953         {},
3954 };
3955
3956 MODULE_DEVICE_TABLE(of, ucc_geth_match);
3957
3958 static struct of_platform_driver ucc_geth_driver = {
3959         .name           = DRV_NAME,
3960         .match_table    = ucc_geth_match,
3961         .probe          = ucc_geth_probe,
3962         .remove         = ucc_geth_remove,
3963 };
3964
3965 static int __init ucc_geth_init(void)
3966 {
3967         int i, ret;
3968
3969         ret = uec_mdio_init();
3970
3971         if (ret)
3972                 return ret;
3973
3974         printk(KERN_INFO "ucc_geth: " DRV_DESC "\n");
3975         for (i = 0; i < 8; i++)
3976                 memcpy(&(ugeth_info[i]), &ugeth_primary_info,
3977                        sizeof(ugeth_primary_info));
3978
3979         ret = of_register_platform_driver(&ucc_geth_driver);
3980
3981         if (ret)
3982                 uec_mdio_exit();
3983
3984         return ret;
3985 }
3986
3987 static void __exit ucc_geth_exit(void)
3988 {
3989         of_unregister_platform_driver(&ucc_geth_driver);
3990         uec_mdio_exit();
3991 }
3992
3993 module_init(ucc_geth_init);
3994 module_exit(ucc_geth_exit);
3995
3996 MODULE_AUTHOR("Freescale Semiconductor, Inc");
3997 MODULE_DESCRIPTION(DRV_DESC);
3998 MODULE_VERSION(DRV_VERSION);
3999 MODULE_LICENSE("GPL");