UCC Ether driver: kmalloc casting cleanups
[linux-2.6.git] / drivers / net / ucc_geth.c
1 /*
2  * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
3  *
4  * Author: Shlomi Gridish <gridish@freescale.com>
5  *         Li Yang <leoli@freescale.com>
6  *
7  * Description:
8  * QE UCC Gigabit Ethernet Driver
9  *
10  * This program is free software; you can redistribute  it and/or modify it
11  * under  the terms of  the GNU General  Public License as published by the
12  * Free Software Foundation;  either version 2 of the  License, or (at your
13  * option) any later version.
14  */
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/slab.h>
19 #include <linux/stddef.h>
20 #include <linux/interrupt.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/skbuff.h>
24 #include <linux/spinlock.h>
25 #include <linux/mm.h>
26 #include <linux/ethtool.h>
27 #include <linux/delay.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/fsl_devices.h>
30 #include <linux/ethtool.h>
31 #include <linux/mii.h>
32 #include <linux/workqueue.h>
33
34 #include <asm/of_platform.h>
35 #include <asm/uaccess.h>
36 #include <asm/irq.h>
37 #include <asm/io.h>
38 #include <asm/immap_qe.h>
39 #include <asm/qe.h>
40 #include <asm/ucc.h>
41 #include <asm/ucc_fast.h>
42
43 #include "ucc_geth.h"
44 #include "ucc_geth_phy.h"
45
46 #undef DEBUG
47
48 #define DRV_DESC "QE UCC Gigabit Ethernet Controller version:Sept 11, 2006"
49 #define DRV_NAME "ucc_geth"
50
51 #define ugeth_printk(level, format, arg...)  \
52         printk(level format "\n", ## arg)
53
54 #define ugeth_dbg(format, arg...)            \
55         ugeth_printk(KERN_DEBUG , format , ## arg)
56 #define ugeth_err(format, arg...)            \
57         ugeth_printk(KERN_ERR , format , ## arg)
58 #define ugeth_info(format, arg...)           \
59         ugeth_printk(KERN_INFO , format , ## arg)
60 #define ugeth_warn(format, arg...)           \
61         ugeth_printk(KERN_WARNING , format , ## arg)
62
63 #ifdef UGETH_VERBOSE_DEBUG
64 #define ugeth_vdbg ugeth_dbg
65 #else
66 #define ugeth_vdbg(fmt, args...) do { } while (0)
67 #endif                          /* UGETH_VERBOSE_DEBUG */
68
69 static DEFINE_SPINLOCK(ugeth_lock);
70
71 static struct ucc_geth_info ugeth_primary_info = {
72         .uf_info = {
73                     .bd_mem_part = MEM_PART_SYSTEM,
74                     .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES,
75                     .max_rx_buf_length = 1536,
76 /* FIXME: should be changed in run time for 1G and 100M */
77 #ifdef CONFIG_UGETH_HAS_GIGA
78                     .urfs = UCC_GETH_URFS_GIGA_INIT,
79                     .urfet = UCC_GETH_URFET_GIGA_INIT,
80                     .urfset = UCC_GETH_URFSET_GIGA_INIT,
81                     .utfs = UCC_GETH_UTFS_GIGA_INIT,
82                     .utfet = UCC_GETH_UTFET_GIGA_INIT,
83                     .utftt = UCC_GETH_UTFTT_GIGA_INIT,
84 #else
85                     .urfs = UCC_GETH_URFS_INIT,
86                     .urfet = UCC_GETH_URFET_INIT,
87                     .urfset = UCC_GETH_URFSET_INIT,
88                     .utfs = UCC_GETH_UTFS_INIT,
89                     .utfet = UCC_GETH_UTFET_INIT,
90                     .utftt = UCC_GETH_UTFTT_INIT,
91 #endif
92                     .ufpt = 256,
93                     .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET,
94                     .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
95                     .tenc = UCC_FAST_TX_ENCODING_NRZ,
96                     .renc = UCC_FAST_RX_ENCODING_NRZ,
97                     .tcrc = UCC_FAST_16_BIT_CRC,
98                     .synl = UCC_FAST_SYNC_LEN_NOT_USED,
99                     },
100         .numQueuesTx = 1,
101         .numQueuesRx = 1,
102         .extendedFilteringChainPointer = ((uint32_t) NULL),
103         .typeorlen = 3072 /*1536 */ ,
104         .nonBackToBackIfgPart1 = 0x40,
105         .nonBackToBackIfgPart2 = 0x60,
106         .miminumInterFrameGapEnforcement = 0x50,
107         .backToBackInterFrameGap = 0x60,
108         .mblinterval = 128,
109         .nortsrbytetime = 5,
110         .fracsiz = 1,
111         .strictpriorityq = 0xff,
112         .altBebTruncation = 0xa,
113         .excessDefer = 1,
114         .maxRetransmission = 0xf,
115         .collisionWindow = 0x37,
116         .receiveFlowControl = 1,
117         .maxGroupAddrInHash = 4,
118         .maxIndAddrInHash = 4,
119         .prel = 7,
120         .maxFrameLength = 1518,
121         .minFrameLength = 64,
122         .maxD1Length = 1520,
123         .maxD2Length = 1520,
124         .vlantype = 0x8100,
125         .ecamptr = ((uint32_t) NULL),
126         .eventRegMask = UCCE_OTHER,
127         .pausePeriod = 0xf000,
128         .interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1},
129         .bdRingLenTx = {
130                         TX_BD_RING_LEN,
131                         TX_BD_RING_LEN,
132                         TX_BD_RING_LEN,
133                         TX_BD_RING_LEN,
134                         TX_BD_RING_LEN,
135                         TX_BD_RING_LEN,
136                         TX_BD_RING_LEN,
137                         TX_BD_RING_LEN},
138
139         .bdRingLenRx = {
140                         RX_BD_RING_LEN,
141                         RX_BD_RING_LEN,
142                         RX_BD_RING_LEN,
143                         RX_BD_RING_LEN,
144                         RX_BD_RING_LEN,
145                         RX_BD_RING_LEN,
146                         RX_BD_RING_LEN,
147                         RX_BD_RING_LEN},
148
149         .numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1,
150         .largestexternallookupkeysize =
151             QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE,
152         .statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_NONE,
153         .vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP,
154         .vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP,
155         .rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT,
156         .aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE,
157         .padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC,
158         .numThreadsTx = UCC_GETH_NUM_OF_THREADS_4,
159         .numThreadsRx = UCC_GETH_NUM_OF_THREADS_4,
160         .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
161         .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
162 };
163
164 static struct ucc_geth_info ugeth_info[8];
165
166 #ifdef DEBUG
167 static void mem_disp(u8 *addr, int size)
168 {
169         u8 *i;
170         int size16Aling = (size >> 4) << 4;
171         int size4Aling = (size >> 2) << 2;
172         int notAlign = 0;
173         if (size % 16)
174                 notAlign = 1;
175
176         for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16)
177                 printk("0x%08x: %08x %08x %08x %08x\r\n",
178                        (u32) i,
179                        *((u32 *) (i)),
180                        *((u32 *) (i + 4)),
181                        *((u32 *) (i + 8)), *((u32 *) (i + 12)));
182         if (notAlign == 1)
183                 printk("0x%08x: ", (u32) i);
184         for (; (u32) i < (u32) addr + size4Aling; i += 4)
185                 printk("%08x ", *((u32 *) (i)));
186         for (; (u32) i < (u32) addr + size; i++)
187                 printk("%02x", *((u8 *) (i)));
188         if (notAlign == 1)
189                 printk("\r\n");
190 }
191 #endif /* DEBUG */
192
193 #ifdef CONFIG_UGETH_FILTERING
194 static void enqueue(struct list_head *node, struct list_head *lh)
195 {
196         unsigned long flags;
197
198         spin_lock_irqsave(&ugeth_lock, flags);
199         list_add_tail(node, lh);
200         spin_unlock_irqrestore(&ugeth_lock, flags);
201 }
202 #endif /* CONFIG_UGETH_FILTERING */
203
204 static struct list_head *dequeue(struct list_head *lh)
205 {
206         unsigned long flags;
207
208         spin_lock_irqsave(&ugeth_lock, flags);
209         if (!list_empty(lh)) {
210                 struct list_head *node = lh->next;
211                 list_del(node);
212                 spin_unlock_irqrestore(&ugeth_lock, flags);
213                 return node;
214         } else {
215                 spin_unlock_irqrestore(&ugeth_lock, flags);
216                 return NULL;
217         }
218 }
219
220 static int get_interface_details(enum enet_interface enet_interface,
221                                  enum enet_speed *speed,
222                                  int *r10m,
223                                  int *rmm,
224                                  int *rpm,
225                                  int *tbi, int *limited_to_full_duplex)
226 {
227         /* Analyze enet_interface according to Interface Mode
228         Configuration table */
229         switch (enet_interface) {
230         case ENET_10_MII:
231                 *speed = ENET_SPEED_10BT;
232                 break;
233         case ENET_10_RMII:
234                 *speed = ENET_SPEED_10BT;
235                 *r10m = 1;
236                 *rmm = 1;
237                 break;
238         case ENET_10_RGMII:
239                 *speed = ENET_SPEED_10BT;
240                 *rpm = 1;
241                 *r10m = 1;
242                 *limited_to_full_duplex = 1;
243                 break;
244         case ENET_100_MII:
245                 *speed = ENET_SPEED_100BT;
246                 break;
247         case ENET_100_RMII:
248                 *speed = ENET_SPEED_100BT;
249                 *rmm = 1;
250                 break;
251         case ENET_100_RGMII:
252                 *speed = ENET_SPEED_100BT;
253                 *rpm = 1;
254                 *limited_to_full_duplex = 1;
255                 break;
256         case ENET_1000_GMII:
257                 *speed = ENET_SPEED_1000BT;
258                 *limited_to_full_duplex = 1;
259                 break;
260         case ENET_1000_RGMII:
261                 *speed = ENET_SPEED_1000BT;
262                 *rpm = 1;
263                 *limited_to_full_duplex = 1;
264                 break;
265         case ENET_1000_TBI:
266                 *speed = ENET_SPEED_1000BT;
267                 *tbi = 1;
268                 *limited_to_full_duplex = 1;
269                 break;
270         case ENET_1000_RTBI:
271                 *speed = ENET_SPEED_1000BT;
272                 *rpm = 1;
273                 *tbi = 1;
274                 *limited_to_full_duplex = 1;
275                 break;
276         default:
277                 return -EINVAL;
278                 break;
279         }
280
281         return 0;
282 }
283
284 static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth, u8 *bd)
285 {
286         struct sk_buff *skb = NULL;
287
288         skb = dev_alloc_skb(ugeth->ug_info->uf_info.max_rx_buf_length +
289                                   UCC_GETH_RX_DATA_BUF_ALIGNMENT);
290
291         if (skb == NULL)
292                 return NULL;
293
294         /* We need the data buffer to be aligned properly.  We will reserve
295          * as many bytes as needed to align the data properly
296          */
297         skb_reserve(skb,
298                     UCC_GETH_RX_DATA_BUF_ALIGNMENT -
299                     (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT -
300                                               1)));
301
302         skb->dev = ugeth->dev;
303
304         out_be32(&((struct qe_bd *)bd)->buf,
305                       dma_map_single(NULL,
306                                      skb->data,
307                                      ugeth->ug_info->uf_info.max_rx_buf_length +
308                                      UCC_GETH_RX_DATA_BUF_ALIGNMENT,
309                                      DMA_FROM_DEVICE));
310
311         out_be32((u32 *)bd, (R_E | R_I | (in_be32((u32 *)bd) & R_W)));
312
313         return skb;
314 }
315
316 static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ)
317 {
318         u8 *bd;
319         u32 bd_status;
320         struct sk_buff *skb;
321         int i;
322
323         bd = ugeth->p_rx_bd_ring[rxQ];
324         i = 0;
325
326         do {
327                 bd_status = in_be32((u32*)bd);
328                 skb = get_new_skb(ugeth, bd);
329
330                 if (!skb)       /* If can not allocate data buffer,
331                                 abort. Cleanup will be elsewhere */
332                         return -ENOMEM;
333
334                 ugeth->rx_skbuff[rxQ][i] = skb;
335
336                 /* advance the BD pointer */
337                 bd += sizeof(struct qe_bd);
338                 i++;
339         } while (!(bd_status & R_W));
340
341         return 0;
342 }
343
344 static int fill_init_enet_entries(struct ucc_geth_private *ugeth,
345                                   volatile u32 *p_start,
346                                   u8 num_entries,
347                                   u32 thread_size,
348                                   u32 thread_alignment,
349                                   enum qe_risc_allocation risc,
350                                   int skip_page_for_first_entry)
351 {
352         u32 init_enet_offset;
353         u8 i;
354         int snum;
355
356         for (i = 0; i < num_entries; i++) {
357                 if ((snum = qe_get_snum()) < 0) {
358                         ugeth_err("fill_init_enet_entries: Can not get SNUM.");
359                         return snum;
360                 }
361                 if ((i == 0) && skip_page_for_first_entry)
362                 /* First entry of Rx does not have page */
363                         init_enet_offset = 0;
364                 else {
365                         init_enet_offset =
366                             qe_muram_alloc(thread_size, thread_alignment);
367                         if (IS_MURAM_ERR(init_enet_offset)) {
368                                 ugeth_err
369                 ("fill_init_enet_entries: Can not allocate DPRAM memory.");
370                                 qe_put_snum((u8) snum);
371                                 return -ENOMEM;
372                         }
373                 }
374                 *(p_start++) =
375                     ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset
376                     | risc;
377         }
378
379         return 0;
380 }
381
382 static int return_init_enet_entries(struct ucc_geth_private *ugeth,
383                                     volatile u32 *p_start,
384                                     u8 num_entries,
385                                     enum qe_risc_allocation risc,
386                                     int skip_page_for_first_entry)
387 {
388         u32 init_enet_offset;
389         u8 i;
390         int snum;
391
392         for (i = 0; i < num_entries; i++) {
393                 /* Check that this entry was actually valid --
394                 needed in case failed in allocations */
395                 if ((*p_start & ENET_INIT_PARAM_RISC_MASK) == risc) {
396                         snum =
397                             (u32) (*p_start & ENET_INIT_PARAM_SNUM_MASK) >>
398                             ENET_INIT_PARAM_SNUM_SHIFT;
399                         qe_put_snum((u8) snum);
400                         if (!((i == 0) && skip_page_for_first_entry)) {
401                         /* First entry of Rx does not have page */
402                                 init_enet_offset =
403                                     (in_be32(p_start) &
404                                      ENET_INIT_PARAM_PTR_MASK);
405                                 qe_muram_free(init_enet_offset);
406                         }
407                         *(p_start++) = 0;       /* Just for cosmetics */
408                 }
409         }
410
411         return 0;
412 }
413
414 #ifdef DEBUG
415 static int dump_init_enet_entries(struct ucc_geth_private *ugeth,
416                                   volatile u32 *p_start,
417                                   u8 num_entries,
418                                   u32 thread_size,
419                                   enum qe_risc_allocation risc,
420                                   int skip_page_for_first_entry)
421 {
422         u32 init_enet_offset;
423         u8 i;
424         int snum;
425
426         for (i = 0; i < num_entries; i++) {
427                 /* Check that this entry was actually valid --
428                 needed in case failed in allocations */
429                 if ((*p_start & ENET_INIT_PARAM_RISC_MASK) == risc) {
430                         snum =
431                             (u32) (*p_start & ENET_INIT_PARAM_SNUM_MASK) >>
432                             ENET_INIT_PARAM_SNUM_SHIFT;
433                         qe_put_snum((u8) snum);
434                         if (!((i == 0) && skip_page_for_first_entry)) {
435                         /* First entry of Rx does not have page */
436                                 init_enet_offset =
437                                     (in_be32(p_start) &
438                                      ENET_INIT_PARAM_PTR_MASK);
439                                 ugeth_info("Init enet entry %d:", i);
440                                 ugeth_info("Base address: 0x%08x",
441                                            (u32)
442                                            qe_muram_addr(init_enet_offset));
443                                 mem_disp(qe_muram_addr(init_enet_offset),
444                                          thread_size);
445                         }
446                         p_start++;
447                 }
448         }
449
450         return 0;
451 }
452 #endif
453
454 #ifdef CONFIG_UGETH_FILTERING
455 static struct enet_addr_container *get_enet_addr_container(void)
456 {
457         struct enet_addr_container *enet_addr_cont;
458
459         /* allocate memory */
460         enet_addr_cont = kmalloc(sizeof(struct enet_addr_container), GFP_KERNEL);
461         if (!enet_addr_cont) {
462                 ugeth_err("%s: No memory for enet_addr_container object.",
463                           __FUNCTION__);
464                 return NULL;
465         }
466
467         return enet_addr_cont;
468 }
469 #endif /* CONFIG_UGETH_FILTERING */
470
471 static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont)
472 {
473         kfree(enet_addr_cont);
474 }
475
476 static void set_mac_addr(__be16 __iomem *reg, u8 *mac)
477 {
478         out_be16(&reg[0], ((u16)mac[5] << 8) | mac[4]);
479         out_be16(&reg[1], ((u16)mac[3] << 8) | mac[2]);
480         out_be16(&reg[2], ((u16)mac[1] << 8) | mac[0]);
481 }
482
483 #ifdef CONFIG_UGETH_FILTERING
484 static int hw_add_addr_in_paddr(struct ucc_geth_private *ugeth,
485                                 u8 *p_enet_addr, u8 paddr_num)
486 {
487         struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
488
489         if (!(paddr_num < NUM_OF_PADDRS)) {
490                 ugeth_warn("%s: Illegal paddr_num.", __FUNCTION__);
491                 return -EINVAL;
492         }
493
494         p_82xx_addr_filt =
495             (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
496             addressfiltering;
497
498         /* Ethernet frames are defined in Little Endian mode,    */
499         /* therefore to insert the address we reverse the bytes. */
500         set_mac_addr(&p_82xx_addr_filt->paddr[paddr_num].h, p_enet_addr);
501         return 0;
502 }
503 #endif /* CONFIG_UGETH_FILTERING */
504
505 static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num)
506 {
507         struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
508
509         if (!(paddr_num < NUM_OF_PADDRS)) {
510                 ugeth_warn("%s: Illagel paddr_num.", __FUNCTION__);
511                 return -EINVAL;
512         }
513
514         p_82xx_addr_filt =
515             (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
516             addressfiltering;
517
518         /* Writing address ff.ff.ff.ff.ff.ff disables address
519         recognition for this register */
520         out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff);
521         out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff);
522         out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff);
523
524         return 0;
525 }
526
527 static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth,
528                                 u8 *p_enet_addr)
529 {
530         struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
531         u32 cecr_subblock;
532
533         p_82xx_addr_filt =
534             (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
535             addressfiltering;
536
537         cecr_subblock =
538             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
539
540         /* Ethernet frames are defined in Little Endian mode,
541         therefor to insert */
542         /* the address to the hash (Big Endian mode), we reverse the bytes.*/
543
544         set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr);
545
546         qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock,
547                      QE_CR_PROTOCOL_ETHERNET, 0);
548 }
549
550 #ifdef CONFIG_UGETH_MAGIC_PACKET
551 static void magic_packet_detection_enable(struct ucc_geth_private *ugeth)
552 {
553         struct ucc_fast_private *uccf;
554         struct ucc_geth *ug_regs;
555         u32 maccfg2, uccm;
556
557         uccf = ugeth->uccf;
558         ug_regs = ugeth->ug_regs;
559
560         /* Enable interrupts for magic packet detection */
561         uccm = in_be32(uccf->p_uccm);
562         uccm |= UCCE_MPD;
563         out_be32(uccf->p_uccm, uccm);
564
565         /* Enable magic packet detection */
566         maccfg2 = in_be32(&ug_regs->maccfg2);
567         maccfg2 |= MACCFG2_MPE;
568         out_be32(&ug_regs->maccfg2, maccfg2);
569 }
570
571 static void magic_packet_detection_disable(struct ucc_geth_private *ugeth)
572 {
573         struct ucc_fast_private *uccf;
574         struct ucc_geth *ug_regs;
575         u32 maccfg2, uccm;
576
577         uccf = ugeth->uccf;
578         ug_regs = ugeth->ug_regs;
579
580         /* Disable interrupts for magic packet detection */
581         uccm = in_be32(uccf->p_uccm);
582         uccm &= ~UCCE_MPD;
583         out_be32(uccf->p_uccm, uccm);
584
585         /* Disable magic packet detection */
586         maccfg2 = in_be32(&ug_regs->maccfg2);
587         maccfg2 &= ~MACCFG2_MPE;
588         out_be32(&ug_regs->maccfg2, maccfg2);
589 }
590 #endif /* MAGIC_PACKET */
591
592 static inline int compare_addr(u8 **addr1, u8 **addr2)
593 {
594         return memcmp(addr1, addr2, ENET_NUM_OCTETS_PER_ADDRESS);
595 }
596
597 #ifdef DEBUG
598 static void get_statistics(struct ucc_geth_private *ugeth,
599                            struct ucc_geth_tx_firmware_statistics *
600                            tx_firmware_statistics,
601                            struct ucc_geth_rx_firmware_statistics *
602                            rx_firmware_statistics,
603                            struct ucc_geth_hardware_statistics *hardware_statistics)
604 {
605         struct ucc_fast *uf_regs;
606         struct ucc_geth *ug_regs;
607         struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram;
608         struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram;
609
610         ug_regs = ugeth->ug_regs;
611         uf_regs = (struct ucc_fast *) ug_regs;
612         p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram;
613         p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram;
614
615         /* Tx firmware only if user handed pointer and driver actually
616         gathers Tx firmware statistics */
617         if (tx_firmware_statistics && p_tx_fw_statistics_pram) {
618                 tx_firmware_statistics->sicoltx =
619                     in_be32(&p_tx_fw_statistics_pram->sicoltx);
620                 tx_firmware_statistics->mulcoltx =
621                     in_be32(&p_tx_fw_statistics_pram->mulcoltx);
622                 tx_firmware_statistics->latecoltxfr =
623                     in_be32(&p_tx_fw_statistics_pram->latecoltxfr);
624                 tx_firmware_statistics->frabortduecol =
625                     in_be32(&p_tx_fw_statistics_pram->frabortduecol);
626                 tx_firmware_statistics->frlostinmactxer =
627                     in_be32(&p_tx_fw_statistics_pram->frlostinmactxer);
628                 tx_firmware_statistics->carriersenseertx =
629                     in_be32(&p_tx_fw_statistics_pram->carriersenseertx);
630                 tx_firmware_statistics->frtxok =
631                     in_be32(&p_tx_fw_statistics_pram->frtxok);
632                 tx_firmware_statistics->txfrexcessivedefer =
633                     in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer);
634                 tx_firmware_statistics->txpkts256 =
635                     in_be32(&p_tx_fw_statistics_pram->txpkts256);
636                 tx_firmware_statistics->txpkts512 =
637                     in_be32(&p_tx_fw_statistics_pram->txpkts512);
638                 tx_firmware_statistics->txpkts1024 =
639                     in_be32(&p_tx_fw_statistics_pram->txpkts1024);
640                 tx_firmware_statistics->txpktsjumbo =
641                     in_be32(&p_tx_fw_statistics_pram->txpktsjumbo);
642         }
643
644         /* Rx firmware only if user handed pointer and driver actually
645          * gathers Rx firmware statistics */
646         if (rx_firmware_statistics && p_rx_fw_statistics_pram) {
647                 int i;
648                 rx_firmware_statistics->frrxfcser =
649                     in_be32(&p_rx_fw_statistics_pram->frrxfcser);
650                 rx_firmware_statistics->fraligner =
651                     in_be32(&p_rx_fw_statistics_pram->fraligner);
652                 rx_firmware_statistics->inrangelenrxer =
653                     in_be32(&p_rx_fw_statistics_pram->inrangelenrxer);
654                 rx_firmware_statistics->outrangelenrxer =
655                     in_be32(&p_rx_fw_statistics_pram->outrangelenrxer);
656                 rx_firmware_statistics->frtoolong =
657                     in_be32(&p_rx_fw_statistics_pram->frtoolong);
658                 rx_firmware_statistics->runt =
659                     in_be32(&p_rx_fw_statistics_pram->runt);
660                 rx_firmware_statistics->verylongevent =
661                     in_be32(&p_rx_fw_statistics_pram->verylongevent);
662                 rx_firmware_statistics->symbolerror =
663                     in_be32(&p_rx_fw_statistics_pram->symbolerror);
664                 rx_firmware_statistics->dropbsy =
665                     in_be32(&p_rx_fw_statistics_pram->dropbsy);
666                 for (i = 0; i < 0x8; i++)
667                         rx_firmware_statistics->res0[i] =
668                             p_rx_fw_statistics_pram->res0[i];
669                 rx_firmware_statistics->mismatchdrop =
670                     in_be32(&p_rx_fw_statistics_pram->mismatchdrop);
671                 rx_firmware_statistics->underpkts =
672                     in_be32(&p_rx_fw_statistics_pram->underpkts);
673                 rx_firmware_statistics->pkts256 =
674                     in_be32(&p_rx_fw_statistics_pram->pkts256);
675                 rx_firmware_statistics->pkts512 =
676                     in_be32(&p_rx_fw_statistics_pram->pkts512);
677                 rx_firmware_statistics->pkts1024 =
678                     in_be32(&p_rx_fw_statistics_pram->pkts1024);
679                 rx_firmware_statistics->pktsjumbo =
680                     in_be32(&p_rx_fw_statistics_pram->pktsjumbo);
681                 rx_firmware_statistics->frlossinmacer =
682                     in_be32(&p_rx_fw_statistics_pram->frlossinmacer);
683                 rx_firmware_statistics->pausefr =
684                     in_be32(&p_rx_fw_statistics_pram->pausefr);
685                 for (i = 0; i < 0x4; i++)
686                         rx_firmware_statistics->res1[i] =
687                             p_rx_fw_statistics_pram->res1[i];
688                 rx_firmware_statistics->removevlan =
689                     in_be32(&p_rx_fw_statistics_pram->removevlan);
690                 rx_firmware_statistics->replacevlan =
691                     in_be32(&p_rx_fw_statistics_pram->replacevlan);
692                 rx_firmware_statistics->insertvlan =
693                     in_be32(&p_rx_fw_statistics_pram->insertvlan);
694         }
695
696         /* Hardware only if user handed pointer and driver actually
697         gathers hardware statistics */
698         if (hardware_statistics && (in_be32(&uf_regs->upsmr) & UPSMR_HSE)) {
699                 hardware_statistics->tx64 = in_be32(&ug_regs->tx64);
700                 hardware_statistics->tx127 = in_be32(&ug_regs->tx127);
701                 hardware_statistics->tx255 = in_be32(&ug_regs->tx255);
702                 hardware_statistics->rx64 = in_be32(&ug_regs->rx64);
703                 hardware_statistics->rx127 = in_be32(&ug_regs->rx127);
704                 hardware_statistics->rx255 = in_be32(&ug_regs->rx255);
705                 hardware_statistics->txok = in_be32(&ug_regs->txok);
706                 hardware_statistics->txcf = in_be16(&ug_regs->txcf);
707                 hardware_statistics->tmca = in_be32(&ug_regs->tmca);
708                 hardware_statistics->tbca = in_be32(&ug_regs->tbca);
709                 hardware_statistics->rxfok = in_be32(&ug_regs->rxfok);
710                 hardware_statistics->rxbok = in_be32(&ug_regs->rxbok);
711                 hardware_statistics->rbyt = in_be32(&ug_regs->rbyt);
712                 hardware_statistics->rmca = in_be32(&ug_regs->rmca);
713                 hardware_statistics->rbca = in_be32(&ug_regs->rbca);
714         }
715 }
716
717 static void dump_bds(struct ucc_geth_private *ugeth)
718 {
719         int i;
720         int length;
721
722         for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
723                 if (ugeth->p_tx_bd_ring[i]) {
724                         length =
725                             (ugeth->ug_info->bdRingLenTx[i] *
726                              sizeof(struct qe_bd));
727                         ugeth_info("TX BDs[%d]", i);
728                         mem_disp(ugeth->p_tx_bd_ring[i], length);
729                 }
730         }
731         for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
732                 if (ugeth->p_rx_bd_ring[i]) {
733                         length =
734                             (ugeth->ug_info->bdRingLenRx[i] *
735                              sizeof(struct qe_bd));
736                         ugeth_info("RX BDs[%d]", i);
737                         mem_disp(ugeth->p_rx_bd_ring[i], length);
738                 }
739         }
740 }
741
742 static void dump_regs(struct ucc_geth_private *ugeth)
743 {
744         int i;
745
746         ugeth_info("UCC%d Geth registers:", ugeth->ug_info->uf_info.ucc_num);
747         ugeth_info("Base address: 0x%08x", (u32) ugeth->ug_regs);
748
749         ugeth_info("maccfg1    : addr - 0x%08x, val - 0x%08x",
750                    (u32) & ugeth->ug_regs->maccfg1,
751                    in_be32(&ugeth->ug_regs->maccfg1));
752         ugeth_info("maccfg2    : addr - 0x%08x, val - 0x%08x",
753                    (u32) & ugeth->ug_regs->maccfg2,
754                    in_be32(&ugeth->ug_regs->maccfg2));
755         ugeth_info("ipgifg     : addr - 0x%08x, val - 0x%08x",
756                    (u32) & ugeth->ug_regs->ipgifg,
757                    in_be32(&ugeth->ug_regs->ipgifg));
758         ugeth_info("hafdup     : addr - 0x%08x, val - 0x%08x",
759                    (u32) & ugeth->ug_regs->hafdup,
760                    in_be32(&ugeth->ug_regs->hafdup));
761         ugeth_info("miimcfg    : addr - 0x%08x, val - 0x%08x",
762                    (u32) & ugeth->ug_regs->miimng.miimcfg,
763                    in_be32(&ugeth->ug_regs->miimng.miimcfg));
764         ugeth_info("miimcom    : addr - 0x%08x, val - 0x%08x",
765                    (u32) & ugeth->ug_regs->miimng.miimcom,
766                    in_be32(&ugeth->ug_regs->miimng.miimcom));
767         ugeth_info("miimadd    : addr - 0x%08x, val - 0x%08x",
768                    (u32) & ugeth->ug_regs->miimng.miimadd,
769                    in_be32(&ugeth->ug_regs->miimng.miimadd));
770         ugeth_info("miimcon    : addr - 0x%08x, val - 0x%08x",
771                    (u32) & ugeth->ug_regs->miimng.miimcon,
772                    in_be32(&ugeth->ug_regs->miimng.miimcon));
773         ugeth_info("miimstat   : addr - 0x%08x, val - 0x%08x",
774                    (u32) & ugeth->ug_regs->miimng.miimstat,
775                    in_be32(&ugeth->ug_regs->miimng.miimstat));
776         ugeth_info("miimmind   : addr - 0x%08x, val - 0x%08x",
777                    (u32) & ugeth->ug_regs->miimng.miimind,
778                    in_be32(&ugeth->ug_regs->miimng.miimind));
779         ugeth_info("ifctl      : addr - 0x%08x, val - 0x%08x",
780                    (u32) & ugeth->ug_regs->ifctl,
781                    in_be32(&ugeth->ug_regs->ifctl));
782         ugeth_info("ifstat     : addr - 0x%08x, val - 0x%08x",
783                    (u32) & ugeth->ug_regs->ifstat,
784                    in_be32(&ugeth->ug_regs->ifstat));
785         ugeth_info("macstnaddr1: addr - 0x%08x, val - 0x%08x",
786                    (u32) & ugeth->ug_regs->macstnaddr1,
787                    in_be32(&ugeth->ug_regs->macstnaddr1));
788         ugeth_info("macstnaddr2: addr - 0x%08x, val - 0x%08x",
789                    (u32) & ugeth->ug_regs->macstnaddr2,
790                    in_be32(&ugeth->ug_regs->macstnaddr2));
791         ugeth_info("uempr      : addr - 0x%08x, val - 0x%08x",
792                    (u32) & ugeth->ug_regs->uempr,
793                    in_be32(&ugeth->ug_regs->uempr));
794         ugeth_info("utbipar    : addr - 0x%08x, val - 0x%08x",
795                    (u32) & ugeth->ug_regs->utbipar,
796                    in_be32(&ugeth->ug_regs->utbipar));
797         ugeth_info("uescr      : addr - 0x%08x, val - 0x%04x",
798                    (u32) & ugeth->ug_regs->uescr,
799                    in_be16(&ugeth->ug_regs->uescr));
800         ugeth_info("tx64       : addr - 0x%08x, val - 0x%08x",
801                    (u32) & ugeth->ug_regs->tx64,
802                    in_be32(&ugeth->ug_regs->tx64));
803         ugeth_info("tx127      : addr - 0x%08x, val - 0x%08x",
804                    (u32) & ugeth->ug_regs->tx127,
805                    in_be32(&ugeth->ug_regs->tx127));
806         ugeth_info("tx255      : addr - 0x%08x, val - 0x%08x",
807                    (u32) & ugeth->ug_regs->tx255,
808                    in_be32(&ugeth->ug_regs->tx255));
809         ugeth_info("rx64       : addr - 0x%08x, val - 0x%08x",
810                    (u32) & ugeth->ug_regs->rx64,
811                    in_be32(&ugeth->ug_regs->rx64));
812         ugeth_info("rx127      : addr - 0x%08x, val - 0x%08x",
813                    (u32) & ugeth->ug_regs->rx127,
814                    in_be32(&ugeth->ug_regs->rx127));
815         ugeth_info("rx255      : addr - 0x%08x, val - 0x%08x",
816                    (u32) & ugeth->ug_regs->rx255,
817                    in_be32(&ugeth->ug_regs->rx255));
818         ugeth_info("txok       : addr - 0x%08x, val - 0x%08x",
819                    (u32) & ugeth->ug_regs->txok,
820                    in_be32(&ugeth->ug_regs->txok));
821         ugeth_info("txcf       : addr - 0x%08x, val - 0x%04x",
822                    (u32) & ugeth->ug_regs->txcf,
823                    in_be16(&ugeth->ug_regs->txcf));
824         ugeth_info("tmca       : addr - 0x%08x, val - 0x%08x",
825                    (u32) & ugeth->ug_regs->tmca,
826                    in_be32(&ugeth->ug_regs->tmca));
827         ugeth_info("tbca       : addr - 0x%08x, val - 0x%08x",
828                    (u32) & ugeth->ug_regs->tbca,
829                    in_be32(&ugeth->ug_regs->tbca));
830         ugeth_info("rxfok      : addr - 0x%08x, val - 0x%08x",
831                    (u32) & ugeth->ug_regs->rxfok,
832                    in_be32(&ugeth->ug_regs->rxfok));
833         ugeth_info("rxbok      : addr - 0x%08x, val - 0x%08x",
834                    (u32) & ugeth->ug_regs->rxbok,
835                    in_be32(&ugeth->ug_regs->rxbok));
836         ugeth_info("rbyt       : addr - 0x%08x, val - 0x%08x",
837                    (u32) & ugeth->ug_regs->rbyt,
838                    in_be32(&ugeth->ug_regs->rbyt));
839         ugeth_info("rmca       : addr - 0x%08x, val - 0x%08x",
840                    (u32) & ugeth->ug_regs->rmca,
841                    in_be32(&ugeth->ug_regs->rmca));
842         ugeth_info("rbca       : addr - 0x%08x, val - 0x%08x",
843                    (u32) & ugeth->ug_regs->rbca,
844                    in_be32(&ugeth->ug_regs->rbca));
845         ugeth_info("scar       : addr - 0x%08x, val - 0x%08x",
846                    (u32) & ugeth->ug_regs->scar,
847                    in_be32(&ugeth->ug_regs->scar));
848         ugeth_info("scam       : addr - 0x%08x, val - 0x%08x",
849                    (u32) & ugeth->ug_regs->scam,
850                    in_be32(&ugeth->ug_regs->scam));
851
852         if (ugeth->p_thread_data_tx) {
853                 int numThreadsTxNumerical;
854                 switch (ugeth->ug_info->numThreadsTx) {
855                 case UCC_GETH_NUM_OF_THREADS_1:
856                         numThreadsTxNumerical = 1;
857                         break;
858                 case UCC_GETH_NUM_OF_THREADS_2:
859                         numThreadsTxNumerical = 2;
860                         break;
861                 case UCC_GETH_NUM_OF_THREADS_4:
862                         numThreadsTxNumerical = 4;
863                         break;
864                 case UCC_GETH_NUM_OF_THREADS_6:
865                         numThreadsTxNumerical = 6;
866                         break;
867                 case UCC_GETH_NUM_OF_THREADS_8:
868                         numThreadsTxNumerical = 8;
869                         break;
870                 default:
871                         numThreadsTxNumerical = 0;
872                         break;
873                 }
874
875                 ugeth_info("Thread data TXs:");
876                 ugeth_info("Base address: 0x%08x",
877                            (u32) ugeth->p_thread_data_tx);
878                 for (i = 0; i < numThreadsTxNumerical; i++) {
879                         ugeth_info("Thread data TX[%d]:", i);
880                         ugeth_info("Base address: 0x%08x",
881                                    (u32) & ugeth->p_thread_data_tx[i]);
882                         mem_disp((u8 *) & ugeth->p_thread_data_tx[i],
883                                  sizeof(struct ucc_geth_thread_data_tx));
884                 }
885         }
886         if (ugeth->p_thread_data_rx) {
887                 int numThreadsRxNumerical;
888                 switch (ugeth->ug_info->numThreadsRx) {
889                 case UCC_GETH_NUM_OF_THREADS_1:
890                         numThreadsRxNumerical = 1;
891                         break;
892                 case UCC_GETH_NUM_OF_THREADS_2:
893                         numThreadsRxNumerical = 2;
894                         break;
895                 case UCC_GETH_NUM_OF_THREADS_4:
896                         numThreadsRxNumerical = 4;
897                         break;
898                 case UCC_GETH_NUM_OF_THREADS_6:
899                         numThreadsRxNumerical = 6;
900                         break;
901                 case UCC_GETH_NUM_OF_THREADS_8:
902                         numThreadsRxNumerical = 8;
903                         break;
904                 default:
905                         numThreadsRxNumerical = 0;
906                         break;
907                 }
908
909                 ugeth_info("Thread data RX:");
910                 ugeth_info("Base address: 0x%08x",
911                            (u32) ugeth->p_thread_data_rx);
912                 for (i = 0; i < numThreadsRxNumerical; i++) {
913                         ugeth_info("Thread data RX[%d]:", i);
914                         ugeth_info("Base address: 0x%08x",
915                                    (u32) & ugeth->p_thread_data_rx[i]);
916                         mem_disp((u8 *) & ugeth->p_thread_data_rx[i],
917                                  sizeof(struct ucc_geth_thread_data_rx));
918                 }
919         }
920         if (ugeth->p_exf_glbl_param) {
921                 ugeth_info("EXF global param:");
922                 ugeth_info("Base address: 0x%08x",
923                            (u32) ugeth->p_exf_glbl_param);
924                 mem_disp((u8 *) ugeth->p_exf_glbl_param,
925                          sizeof(*ugeth->p_exf_glbl_param));
926         }
927         if (ugeth->p_tx_glbl_pram) {
928                 ugeth_info("TX global param:");
929                 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_tx_glbl_pram);
930                 ugeth_info("temoder      : addr - 0x%08x, val - 0x%04x",
931                            (u32) & ugeth->p_tx_glbl_pram->temoder,
932                            in_be16(&ugeth->p_tx_glbl_pram->temoder));
933                 ugeth_info("sqptr        : addr - 0x%08x, val - 0x%08x",
934                            (u32) & ugeth->p_tx_glbl_pram->sqptr,
935                            in_be32(&ugeth->p_tx_glbl_pram->sqptr));
936                 ugeth_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x",
937                            (u32) & ugeth->p_tx_glbl_pram->schedulerbasepointer,
938                            in_be32(&ugeth->p_tx_glbl_pram->
939                                    schedulerbasepointer));
940                 ugeth_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x",
941                            (u32) & ugeth->p_tx_glbl_pram->txrmonbaseptr,
942                            in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr));
943                 ugeth_info("tstate       : addr - 0x%08x, val - 0x%08x",
944                            (u32) & ugeth->p_tx_glbl_pram->tstate,
945                            in_be32(&ugeth->p_tx_glbl_pram->tstate));
946                 ugeth_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x",
947                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[0],
948                            ugeth->p_tx_glbl_pram->iphoffset[0]);
949                 ugeth_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x",
950                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[1],
951                            ugeth->p_tx_glbl_pram->iphoffset[1]);
952                 ugeth_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x",
953                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[2],
954                            ugeth->p_tx_glbl_pram->iphoffset[2]);
955                 ugeth_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x",
956                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[3],
957                            ugeth->p_tx_glbl_pram->iphoffset[3]);
958                 ugeth_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x",
959                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[4],
960                            ugeth->p_tx_glbl_pram->iphoffset[4]);
961                 ugeth_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x",
962                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[5],
963                            ugeth->p_tx_glbl_pram->iphoffset[5]);
964                 ugeth_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x",
965                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[6],
966                            ugeth->p_tx_glbl_pram->iphoffset[6]);
967                 ugeth_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x",
968                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[7],
969                            ugeth->p_tx_glbl_pram->iphoffset[7]);
970                 ugeth_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x",
971                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[0],
972                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0]));
973                 ugeth_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x",
974                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[1],
975                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1]));
976                 ugeth_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x",
977                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[2],
978                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2]));
979                 ugeth_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x",
980                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[3],
981                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3]));
982                 ugeth_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x",
983                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[4],
984                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4]));
985                 ugeth_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x",
986                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[5],
987                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5]));
988                 ugeth_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x",
989                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[6],
990                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6]));
991                 ugeth_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x",
992                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[7],
993                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7]));
994                 ugeth_info("tqptr        : addr - 0x%08x, val - 0x%08x",
995                            (u32) & ugeth->p_tx_glbl_pram->tqptr,
996                            in_be32(&ugeth->p_tx_glbl_pram->tqptr));
997         }
998         if (ugeth->p_rx_glbl_pram) {
999                 ugeth_info("RX global param:");
1000                 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_glbl_pram);
1001                 ugeth_info("remoder         : addr - 0x%08x, val - 0x%08x",
1002                            (u32) & ugeth->p_rx_glbl_pram->remoder,
1003                            in_be32(&ugeth->p_rx_glbl_pram->remoder));
1004                 ugeth_info("rqptr           : addr - 0x%08x, val - 0x%08x",
1005                            (u32) & ugeth->p_rx_glbl_pram->rqptr,
1006                            in_be32(&ugeth->p_rx_glbl_pram->rqptr));
1007                 ugeth_info("typeorlen       : addr - 0x%08x, val - 0x%04x",
1008                            (u32) & ugeth->p_rx_glbl_pram->typeorlen,
1009                            in_be16(&ugeth->p_rx_glbl_pram->typeorlen));
1010                 ugeth_info("rxgstpack       : addr - 0x%08x, val - 0x%02x",
1011                            (u32) & ugeth->p_rx_glbl_pram->rxgstpack,
1012                            ugeth->p_rx_glbl_pram->rxgstpack);
1013                 ugeth_info("rxrmonbaseptr   : addr - 0x%08x, val - 0x%08x",
1014                            (u32) & ugeth->p_rx_glbl_pram->rxrmonbaseptr,
1015                            in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr));
1016                 ugeth_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x",
1017                            (u32) & ugeth->p_rx_glbl_pram->intcoalescingptr,
1018                            in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr));
1019                 ugeth_info("rstate          : addr - 0x%08x, val - 0x%02x",
1020                            (u32) & ugeth->p_rx_glbl_pram->rstate,
1021                            ugeth->p_rx_glbl_pram->rstate);
1022                 ugeth_info("mrblr           : addr - 0x%08x, val - 0x%04x",
1023                            (u32) & ugeth->p_rx_glbl_pram->mrblr,
1024                            in_be16(&ugeth->p_rx_glbl_pram->mrblr));
1025                 ugeth_info("rbdqptr         : addr - 0x%08x, val - 0x%08x",
1026                            (u32) & ugeth->p_rx_glbl_pram->rbdqptr,
1027                            in_be32(&ugeth->p_rx_glbl_pram->rbdqptr));
1028                 ugeth_info("mflr            : addr - 0x%08x, val - 0x%04x",
1029                            (u32) & ugeth->p_rx_glbl_pram->mflr,
1030                            in_be16(&ugeth->p_rx_glbl_pram->mflr));
1031                 ugeth_info("minflr          : addr - 0x%08x, val - 0x%04x",
1032                            (u32) & ugeth->p_rx_glbl_pram->minflr,
1033                            in_be16(&ugeth->p_rx_glbl_pram->minflr));
1034                 ugeth_info("maxd1           : addr - 0x%08x, val - 0x%04x",
1035                            (u32) & ugeth->p_rx_glbl_pram->maxd1,
1036                            in_be16(&ugeth->p_rx_glbl_pram->maxd1));
1037                 ugeth_info("maxd2           : addr - 0x%08x, val - 0x%04x",
1038                            (u32) & ugeth->p_rx_glbl_pram->maxd2,
1039                            in_be16(&ugeth->p_rx_glbl_pram->maxd2));
1040                 ugeth_info("ecamptr         : addr - 0x%08x, val - 0x%08x",
1041                            (u32) & ugeth->p_rx_glbl_pram->ecamptr,
1042                            in_be32(&ugeth->p_rx_glbl_pram->ecamptr));
1043                 ugeth_info("l2qt            : addr - 0x%08x, val - 0x%08x",
1044                            (u32) & ugeth->p_rx_glbl_pram->l2qt,
1045                            in_be32(&ugeth->p_rx_glbl_pram->l2qt));
1046                 ugeth_info("l3qt[0]         : addr - 0x%08x, val - 0x%08x",
1047                            (u32) & ugeth->p_rx_glbl_pram->l3qt[0],
1048                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[0]));
1049                 ugeth_info("l3qt[1]         : addr - 0x%08x, val - 0x%08x",
1050                            (u32) & ugeth->p_rx_glbl_pram->l3qt[1],
1051                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[1]));
1052                 ugeth_info("l3qt[2]         : addr - 0x%08x, val - 0x%08x",
1053                            (u32) & ugeth->p_rx_glbl_pram->l3qt[2],
1054                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[2]));
1055                 ugeth_info("l3qt[3]         : addr - 0x%08x, val - 0x%08x",
1056                            (u32) & ugeth->p_rx_glbl_pram->l3qt[3],
1057                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[3]));
1058                 ugeth_info("l3qt[4]         : addr - 0x%08x, val - 0x%08x",
1059                            (u32) & ugeth->p_rx_glbl_pram->l3qt[4],
1060                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[4]));
1061                 ugeth_info("l3qt[5]         : addr - 0x%08x, val - 0x%08x",
1062                            (u32) & ugeth->p_rx_glbl_pram->l3qt[5],
1063                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[5]));
1064                 ugeth_info("l3qt[6]         : addr - 0x%08x, val - 0x%08x",
1065                            (u32) & ugeth->p_rx_glbl_pram->l3qt[6],
1066                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[6]));
1067                 ugeth_info("l3qt[7]         : addr - 0x%08x, val - 0x%08x",
1068                            (u32) & ugeth->p_rx_glbl_pram->l3qt[7],
1069                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[7]));
1070                 ugeth_info("vlantype        : addr - 0x%08x, val - 0x%04x",
1071                            (u32) & ugeth->p_rx_glbl_pram->vlantype,
1072                            in_be16(&ugeth->p_rx_glbl_pram->vlantype));
1073                 ugeth_info("vlantci         : addr - 0x%08x, val - 0x%04x",
1074                            (u32) & ugeth->p_rx_glbl_pram->vlantci,
1075                            in_be16(&ugeth->p_rx_glbl_pram->vlantci));
1076                 for (i = 0; i < 64; i++)
1077                         ugeth_info
1078                     ("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x",
1079                              i,
1080                              (u32) & ugeth->p_rx_glbl_pram->addressfiltering[i],
1081                              ugeth->p_rx_glbl_pram->addressfiltering[i]);
1082                 ugeth_info("exfGlobalParam  : addr - 0x%08x, val - 0x%08x",
1083                            (u32) & ugeth->p_rx_glbl_pram->exfGlobalParam,
1084                            in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam));
1085         }
1086         if (ugeth->p_send_q_mem_reg) {
1087                 ugeth_info("Send Q memory registers:");
1088                 ugeth_info("Base address: 0x%08x",
1089                            (u32) ugeth->p_send_q_mem_reg);
1090                 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
1091                         ugeth_info("SQQD[%d]:", i);
1092                         ugeth_info("Base address: 0x%08x",
1093                                    (u32) & ugeth->p_send_q_mem_reg->sqqd[i]);
1094                         mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i],
1095                                  sizeof(struct ucc_geth_send_queue_qd));
1096                 }
1097         }
1098         if (ugeth->p_scheduler) {
1099                 ugeth_info("Scheduler:");
1100                 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_scheduler);
1101                 mem_disp((u8 *) ugeth->p_scheduler,
1102                          sizeof(*ugeth->p_scheduler));
1103         }
1104         if (ugeth->p_tx_fw_statistics_pram) {
1105                 ugeth_info("TX FW statistics pram:");
1106                 ugeth_info("Base address: 0x%08x",
1107                            (u32) ugeth->p_tx_fw_statistics_pram);
1108                 mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram,
1109                          sizeof(*ugeth->p_tx_fw_statistics_pram));
1110         }
1111         if (ugeth->p_rx_fw_statistics_pram) {
1112                 ugeth_info("RX FW statistics pram:");
1113                 ugeth_info("Base address: 0x%08x",
1114                            (u32) ugeth->p_rx_fw_statistics_pram);
1115                 mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram,
1116                          sizeof(*ugeth->p_rx_fw_statistics_pram));
1117         }
1118         if (ugeth->p_rx_irq_coalescing_tbl) {
1119                 ugeth_info("RX IRQ coalescing tables:");
1120                 ugeth_info("Base address: 0x%08x",
1121                            (u32) ugeth->p_rx_irq_coalescing_tbl);
1122                 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1123                         ugeth_info("RX IRQ coalescing table entry[%d]:", i);
1124                         ugeth_info("Base address: 0x%08x",
1125                                    (u32) & ugeth->p_rx_irq_coalescing_tbl->
1126                                    coalescingentry[i]);
1127                         ugeth_info
1128                 ("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x",
1129                              (u32) & ugeth->p_rx_irq_coalescing_tbl->
1130                              coalescingentry[i].interruptcoalescingmaxvalue,
1131                              in_be32(&ugeth->p_rx_irq_coalescing_tbl->
1132                                      coalescingentry[i].
1133                                      interruptcoalescingmaxvalue));
1134                         ugeth_info
1135                 ("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x",
1136                              (u32) & ugeth->p_rx_irq_coalescing_tbl->
1137                              coalescingentry[i].interruptcoalescingcounter,
1138                              in_be32(&ugeth->p_rx_irq_coalescing_tbl->
1139                                      coalescingentry[i].
1140                                      interruptcoalescingcounter));
1141                 }
1142         }
1143         if (ugeth->p_rx_bd_qs_tbl) {
1144                 ugeth_info("RX BD QS tables:");
1145                 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_bd_qs_tbl);
1146                 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1147                         ugeth_info("RX BD QS table[%d]:", i);
1148                         ugeth_info("Base address: 0x%08x",
1149                                    (u32) & ugeth->p_rx_bd_qs_tbl[i]);
1150                         ugeth_info
1151                             ("bdbaseptr        : addr - 0x%08x, val - 0x%08x",
1152                              (u32) & ugeth->p_rx_bd_qs_tbl[i].bdbaseptr,
1153                              in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr));
1154                         ugeth_info
1155                             ("bdptr            : addr - 0x%08x, val - 0x%08x",
1156                              (u32) & ugeth->p_rx_bd_qs_tbl[i].bdptr,
1157                              in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr));
1158                         ugeth_info
1159                             ("externalbdbaseptr: addr - 0x%08x, val - 0x%08x",
1160                              (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
1161                              in_be32(&ugeth->p_rx_bd_qs_tbl[i].
1162                                      externalbdbaseptr));
1163                         ugeth_info
1164                             ("externalbdptr    : addr - 0x%08x, val - 0x%08x",
1165                              (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdptr,
1166                              in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr));
1167                         ugeth_info("ucode RX Prefetched BDs:");
1168                         ugeth_info("Base address: 0x%08x",
1169                                    (u32)
1170                                    qe_muram_addr(in_be32
1171                                                  (&ugeth->p_rx_bd_qs_tbl[i].
1172                                                   bdbaseptr)));
1173                         mem_disp((u8 *)
1174                                  qe_muram_addr(in_be32
1175                                                (&ugeth->p_rx_bd_qs_tbl[i].
1176                                                 bdbaseptr)),
1177                                  sizeof(struct ucc_geth_rx_prefetched_bds));
1178                 }
1179         }
1180         if (ugeth->p_init_enet_param_shadow) {
1181                 int size;
1182                 ugeth_info("Init enet param shadow:");
1183                 ugeth_info("Base address: 0x%08x",
1184                            (u32) ugeth->p_init_enet_param_shadow);
1185                 mem_disp((u8 *) ugeth->p_init_enet_param_shadow,
1186                          sizeof(*ugeth->p_init_enet_param_shadow));
1187
1188                 size = sizeof(struct ucc_geth_thread_rx_pram);
1189                 if (ugeth->ug_info->rxExtendedFiltering) {
1190                         size +=
1191                             THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
1192                         if (ugeth->ug_info->largestexternallookupkeysize ==
1193                             QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
1194                                 size +=
1195                         THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
1196                         if (ugeth->ug_info->largestexternallookupkeysize ==
1197                             QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
1198                                 size +=
1199                         THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
1200                 }
1201
1202                 dump_init_enet_entries(ugeth,
1203                                        &(ugeth->p_init_enet_param_shadow->
1204                                          txthread[0]),
1205                                        ENET_INIT_PARAM_MAX_ENTRIES_TX,
1206                                        sizeof(struct ucc_geth_thread_tx_pram),
1207                                        ugeth->ug_info->riscTx, 0);
1208                 dump_init_enet_entries(ugeth,
1209                                        &(ugeth->p_init_enet_param_shadow->
1210                                          rxthread[0]),
1211                                        ENET_INIT_PARAM_MAX_ENTRIES_RX, size,
1212                                        ugeth->ug_info->riscRx, 1);
1213         }
1214 }
1215 #endif /* DEBUG */
1216
1217 static void init_default_reg_vals(volatile u32 *upsmr_register,
1218                                   volatile u32 *maccfg1_register,
1219                                   volatile u32 *maccfg2_register)
1220 {
1221         out_be32(upsmr_register, UCC_GETH_UPSMR_INIT);
1222         out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT);
1223         out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT);
1224 }
1225
1226 static int init_half_duplex_params(int alt_beb,
1227                                    int back_pressure_no_backoff,
1228                                    int no_backoff,
1229                                    int excess_defer,
1230                                    u8 alt_beb_truncation,
1231                                    u8 max_retransmissions,
1232                                    u8 collision_window,
1233                                    volatile u32 *hafdup_register)
1234 {
1235         u32 value = 0;
1236
1237         if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) ||
1238             (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) ||
1239             (collision_window > HALFDUP_COLLISION_WINDOW_MAX))
1240                 return -EINVAL;
1241
1242         value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT);
1243
1244         if (alt_beb)
1245                 value |= HALFDUP_ALT_BEB;
1246         if (back_pressure_no_backoff)
1247                 value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF;
1248         if (no_backoff)
1249                 value |= HALFDUP_NO_BACKOFF;
1250         if (excess_defer)
1251                 value |= HALFDUP_EXCESSIVE_DEFER;
1252
1253         value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT);
1254
1255         value |= collision_window;
1256
1257         out_be32(hafdup_register, value);
1258         return 0;
1259 }
1260
1261 static int init_inter_frame_gap_params(u8 non_btb_cs_ipg,
1262                                        u8 non_btb_ipg,
1263                                        u8 min_ifg,
1264                                        u8 btb_ipg,
1265                                        volatile u32 *ipgifg_register)
1266 {
1267         u32 value = 0;
1268
1269         /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back
1270         IPG part 2 */
1271         if (non_btb_cs_ipg > non_btb_ipg)
1272                 return -EINVAL;
1273
1274         if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) ||
1275             (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) ||
1276             /*(min_ifg        > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */
1277             (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX))
1278                 return -EINVAL;
1279
1280         value |=
1281             ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) &
1282              IPGIFG_NBTB_CS_IPG_MASK);
1283         value |=
1284             ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) &
1285              IPGIFG_NBTB_IPG_MASK);
1286         value |=
1287             ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) &
1288              IPGIFG_MIN_IFG_MASK);
1289         value |= (btb_ipg & IPGIFG_BTB_IPG_MASK);
1290
1291         out_be32(ipgifg_register, value);
1292         return 0;
1293 }
1294
1295 static int init_flow_control_params(u32 automatic_flow_control_mode,
1296                                     int rx_flow_control_enable,
1297                                     int tx_flow_control_enable,
1298                                     u16 pause_period,
1299                                     u16 extension_field,
1300                                     volatile u32 *upsmr_register,
1301                                     volatile u32 *uempr_register,
1302                                     volatile u32 *maccfg1_register)
1303 {
1304         u32 value = 0;
1305
1306         /* Set UEMPR register */
1307         value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT;
1308         value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT;
1309         out_be32(uempr_register, value);
1310
1311         /* Set UPSMR register */
1312         value = in_be32(upsmr_register);
1313         value |= automatic_flow_control_mode;
1314         out_be32(upsmr_register, value);
1315
1316         value = in_be32(maccfg1_register);
1317         if (rx_flow_control_enable)
1318                 value |= MACCFG1_FLOW_RX;
1319         if (tx_flow_control_enable)
1320                 value |= MACCFG1_FLOW_TX;
1321         out_be32(maccfg1_register, value);
1322
1323         return 0;
1324 }
1325
1326 static int init_hw_statistics_gathering_mode(int enable_hardware_statistics,
1327                                              int auto_zero_hardware_statistics,
1328                                              volatile u32 *upsmr_register,
1329                                              volatile u16 *uescr_register)
1330 {
1331         u32 upsmr_value = 0;
1332         u16 uescr_value = 0;
1333         /* Enable hardware statistics gathering if requested */
1334         if (enable_hardware_statistics) {
1335                 upsmr_value = in_be32(upsmr_register);
1336                 upsmr_value |= UPSMR_HSE;
1337                 out_be32(upsmr_register, upsmr_value);
1338         }
1339
1340         /* Clear hardware statistics counters */
1341         uescr_value = in_be16(uescr_register);
1342         uescr_value |= UESCR_CLRCNT;
1343         /* Automatically zero hardware statistics counters on read,
1344         if requested */
1345         if (auto_zero_hardware_statistics)
1346                 uescr_value |= UESCR_AUTOZ;
1347         out_be16(uescr_register, uescr_value);
1348
1349         return 0;
1350 }
1351
1352 static int init_firmware_statistics_gathering_mode(int
1353                 enable_tx_firmware_statistics,
1354                 int enable_rx_firmware_statistics,
1355                 volatile u32 *tx_rmon_base_ptr,
1356                 u32 tx_firmware_statistics_structure_address,
1357                 volatile u32 *rx_rmon_base_ptr,
1358                 u32 rx_firmware_statistics_structure_address,
1359                 volatile u16 *temoder_register,
1360                 volatile u32 *remoder_register)
1361 {
1362         /* Note: this function does not check if */
1363         /* the parameters it receives are NULL   */
1364         u16 temoder_value;
1365         u32 remoder_value;
1366
1367         if (enable_tx_firmware_statistics) {
1368                 out_be32(tx_rmon_base_ptr,
1369                          tx_firmware_statistics_structure_address);
1370                 temoder_value = in_be16(temoder_register);
1371                 temoder_value |= TEMODER_TX_RMON_STATISTICS_ENABLE;
1372                 out_be16(temoder_register, temoder_value);
1373         }
1374
1375         if (enable_rx_firmware_statistics) {
1376                 out_be32(rx_rmon_base_ptr,
1377                          rx_firmware_statistics_structure_address);
1378                 remoder_value = in_be32(remoder_register);
1379                 remoder_value |= REMODER_RX_RMON_STATISTICS_ENABLE;
1380                 out_be32(remoder_register, remoder_value);
1381         }
1382
1383         return 0;
1384 }
1385
1386 static int init_mac_station_addr_regs(u8 address_byte_0,
1387                                       u8 address_byte_1,
1388                                       u8 address_byte_2,
1389                                       u8 address_byte_3,
1390                                       u8 address_byte_4,
1391                                       u8 address_byte_5,
1392                                       volatile u32 *macstnaddr1_register,
1393                                       volatile u32 *macstnaddr2_register)
1394 {
1395         u32 value = 0;
1396
1397         /* Example: for a station address of 0x12345678ABCD, */
1398         /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */
1399
1400         /* MACSTNADDR1 Register: */
1401
1402         /* 0                      7   8                      15  */
1403         /* station address byte 5     station address byte 4     */
1404         /* 16                     23  24                     31  */
1405         /* station address byte 3     station address byte 2     */
1406         value |= (u32) ((address_byte_2 << 0) & 0x000000FF);
1407         value |= (u32) ((address_byte_3 << 8) & 0x0000FF00);
1408         value |= (u32) ((address_byte_4 << 16) & 0x00FF0000);
1409         value |= (u32) ((address_byte_5 << 24) & 0xFF000000);
1410
1411         out_be32(macstnaddr1_register, value);
1412
1413         /* MACSTNADDR2 Register: */
1414
1415         /* 0                      7   8                      15  */
1416         /* station address byte 1     station address byte 0     */
1417         /* 16                     23  24                     31  */
1418         /*         reserved                   reserved           */
1419         value = 0;
1420         value |= (u32) ((address_byte_0 << 16) & 0x00FF0000);
1421         value |= (u32) ((address_byte_1 << 24) & 0xFF000000);
1422
1423         out_be32(macstnaddr2_register, value);
1424
1425         return 0;
1426 }
1427
1428 static int init_mac_duplex_mode(int full_duplex,
1429                                 int limited_to_full_duplex,
1430                                 volatile u32 *maccfg2_register)
1431 {
1432         u32 value = 0;
1433
1434         /* some interfaces must work in full duplex mode */
1435         if ((full_duplex == 0) && (limited_to_full_duplex == 1))
1436                 return -EINVAL;
1437
1438         value = in_be32(maccfg2_register);
1439
1440         if (full_duplex)
1441                 value |= MACCFG2_FDX;
1442         else
1443                 value &= ~MACCFG2_FDX;
1444
1445         out_be32(maccfg2_register, value);
1446         return 0;
1447 }
1448
1449 static int init_check_frame_length_mode(int length_check,
1450                                         volatile u32 *maccfg2_register)
1451 {
1452         u32 value = 0;
1453
1454         value = in_be32(maccfg2_register);
1455
1456         if (length_check)
1457                 value |= MACCFG2_LC;
1458         else
1459                 value &= ~MACCFG2_LC;
1460
1461         out_be32(maccfg2_register, value);
1462         return 0;
1463 }
1464
1465 static int init_preamble_length(u8 preamble_length,
1466                                 volatile u32 *maccfg2_register)
1467 {
1468         u32 value = 0;
1469
1470         if ((preamble_length < 3) || (preamble_length > 7))
1471                 return -EINVAL;
1472
1473         value = in_be32(maccfg2_register);
1474         value &= ~MACCFG2_PREL_MASK;
1475         value |= (preamble_length << MACCFG2_PREL_SHIFT);
1476         out_be32(maccfg2_register, value);
1477         return 0;
1478 }
1479
1480 static int init_mii_management_configuration(int reset_mgmt,
1481                                              int preamble_supress,
1482                                              volatile u32 *miimcfg_register,
1483                                              volatile u32 *miimind_register)
1484 {
1485         unsigned int timeout = PHY_INIT_TIMEOUT;
1486         u32 value = 0;
1487
1488         value = in_be32(miimcfg_register);
1489         if (reset_mgmt) {
1490                 value |= MIIMCFG_RESET_MANAGEMENT;
1491                 out_be32(miimcfg_register, value);
1492         }
1493
1494         value = 0;
1495
1496         if (preamble_supress)
1497                 value |= MIIMCFG_NO_PREAMBLE;
1498
1499         value |= UCC_GETH_MIIMCFG_MNGMNT_CLC_DIV_INIT;
1500         out_be32(miimcfg_register, value);
1501
1502         /* Wait until the bus is free */
1503         while ((in_be32(miimind_register) & MIIMIND_BUSY) && timeout--)
1504                 cpu_relax();
1505
1506         if (timeout <= 0) {
1507                 ugeth_err("%s: The MII Bus is stuck!", __FUNCTION__);
1508                 return -ETIMEDOUT;
1509         }
1510
1511         return 0;
1512 }
1513
1514 static int init_rx_parameters(int reject_broadcast,
1515                               int receive_short_frames,
1516                               int promiscuous, volatile u32 *upsmr_register)
1517 {
1518         u32 value = 0;
1519
1520         value = in_be32(upsmr_register);
1521
1522         if (reject_broadcast)
1523                 value |= UPSMR_BRO;
1524         else
1525                 value &= ~UPSMR_BRO;
1526
1527         if (receive_short_frames)
1528                 value |= UPSMR_RSH;
1529         else
1530                 value &= ~UPSMR_RSH;
1531
1532         if (promiscuous)
1533                 value |= UPSMR_PRO;
1534         else
1535                 value &= ~UPSMR_PRO;
1536
1537         out_be32(upsmr_register, value);
1538
1539         return 0;
1540 }
1541
1542 static int init_max_rx_buff_len(u16 max_rx_buf_len,
1543                                 volatile u16 *mrblr_register)
1544 {
1545         /* max_rx_buf_len value must be a multiple of 128 */
1546         if ((max_rx_buf_len == 0)
1547             || (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT))
1548                 return -EINVAL;
1549
1550         out_be16(mrblr_register, max_rx_buf_len);
1551         return 0;
1552 }
1553
1554 static int init_min_frame_len(u16 min_frame_length,
1555                               volatile u16 *minflr_register,
1556                               volatile u16 *mrblr_register)
1557 {
1558         u16 mrblr_value = 0;
1559
1560         mrblr_value = in_be16(mrblr_register);
1561         if (min_frame_length >= (mrblr_value - 4))
1562                 return -EINVAL;
1563
1564         out_be16(minflr_register, min_frame_length);
1565         return 0;
1566 }
1567
1568 static int adjust_enet_interface(struct ucc_geth_private *ugeth)
1569 {
1570         struct ucc_geth_info *ug_info;
1571         struct ucc_geth *ug_regs;
1572         struct ucc_fast *uf_regs;
1573         enum enet_speed speed;
1574         int ret_val, rpm = 0, tbi = 0, r10m = 0, rmm =
1575             0, limited_to_full_duplex = 0;
1576         u32 upsmr, maccfg2, utbipar, tbiBaseAddress;
1577         u16 value;
1578
1579         ugeth_vdbg("%s: IN", __FUNCTION__);
1580
1581         ug_info = ugeth->ug_info;
1582         ug_regs = ugeth->ug_regs;
1583         uf_regs = ugeth->uccf->uf_regs;
1584
1585         /* Analyze enet_interface according to Interface Mode Configuration
1586         table */
1587         ret_val =
1588             get_interface_details(ug_info->enet_interface, &speed, &r10m, &rmm,
1589                                   &rpm, &tbi, &limited_to_full_duplex);
1590         if (ret_val != 0) {
1591                 ugeth_err
1592                   ("%s: half duplex not supported in requested configuration.",
1593                      __FUNCTION__);
1594                 return ret_val;
1595         }
1596
1597         /*                    Set MACCFG2                    */
1598         maccfg2 = in_be32(&ug_regs->maccfg2);
1599         maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
1600         if ((speed == ENET_SPEED_10BT) || (speed == ENET_SPEED_100BT))
1601                 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
1602         else if (speed == ENET_SPEED_1000BT)
1603                 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
1604         maccfg2 |= ug_info->padAndCrc;
1605         out_be32(&ug_regs->maccfg2, maccfg2);
1606
1607         /*                    Set UPSMR                      */
1608         upsmr = in_be32(&uf_regs->upsmr);
1609         upsmr &= ~(UPSMR_RPM | UPSMR_R10M | UPSMR_TBIM | UPSMR_RMM);
1610         if (rpm)
1611                 upsmr |= UPSMR_RPM;
1612         if (r10m)
1613                 upsmr |= UPSMR_R10M;
1614         if (tbi)
1615                 upsmr |= UPSMR_TBIM;
1616         if (rmm)
1617                 upsmr |= UPSMR_RMM;
1618         out_be32(&uf_regs->upsmr, upsmr);
1619
1620         /*                    Set UTBIPAR                    */
1621         utbipar = in_be32(&ug_regs->utbipar);
1622         utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK;
1623         if (tbi)
1624                 utbipar |=
1625                     (ug_info->phy_address +
1626                      ugeth->ug_info->uf_info.
1627                      ucc_num) << UTBIPAR_PHY_ADDRESS_SHIFT;
1628         else
1629                 utbipar |=
1630                     (0x10 +
1631                      ugeth->ug_info->uf_info.
1632                      ucc_num) << UTBIPAR_PHY_ADDRESS_SHIFT;
1633         out_be32(&ug_regs->utbipar, utbipar);
1634
1635         /* Disable autonegotiation in tbi mode, because by default it
1636         comes up in autonegotiation mode. */
1637         /* Note that this depends on proper setting in utbipar register. */
1638         if (tbi) {
1639                 tbiBaseAddress = in_be32(&ug_regs->utbipar);
1640                 tbiBaseAddress &= UTBIPAR_PHY_ADDRESS_MASK;
1641                 tbiBaseAddress >>= UTBIPAR_PHY_ADDRESS_SHIFT;
1642                 value =
1643                     ugeth->mii_info->mdio_read(ugeth->dev, (u8) tbiBaseAddress,
1644                                                ENET_TBI_MII_CR);
1645                 value &= ~0x1000;       /* Turn off autonegotiation */
1646                 ugeth->mii_info->mdio_write(ugeth->dev, (u8) tbiBaseAddress,
1647                                             ENET_TBI_MII_CR, value);
1648         }
1649
1650         ret_val = init_mac_duplex_mode(1,
1651                                        limited_to_full_duplex,
1652                                        &ug_regs->maccfg2);
1653         if (ret_val != 0) {
1654                 ugeth_err
1655                 ("%s: half duplex not supported in requested configuration.",
1656                      __FUNCTION__);
1657                 return ret_val;
1658         }
1659
1660         init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2);
1661
1662         ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2);
1663         if (ret_val != 0) {
1664                 ugeth_err
1665                     ("%s: Preamble length must be between 3 and 7 inclusive.",
1666                      __FUNCTION__);
1667                 return ret_val;
1668         }
1669
1670         return 0;
1671 }
1672
1673 /* Called every time the controller might need to be made
1674  * aware of new link state.  The PHY code conveys this
1675  * information through variables in the ugeth structure, and this
1676  * function converts those variables into the appropriate
1677  * register values, and can bring down the device if needed.
1678  */
1679 static void adjust_link(struct net_device *dev)
1680 {
1681         struct ucc_geth_private *ugeth = netdev_priv(dev);
1682         struct ucc_geth *ug_regs;
1683         u32 tempval;
1684         struct ugeth_mii_info *mii_info = ugeth->mii_info;
1685
1686         ug_regs = ugeth->ug_regs;
1687
1688         if (mii_info->link) {
1689                 /* Now we make sure that we can be in full duplex mode.
1690                  * If not, we operate in half-duplex mode. */
1691                 if (mii_info->duplex != ugeth->oldduplex) {
1692                         if (!(mii_info->duplex)) {
1693                                 tempval = in_be32(&ug_regs->maccfg2);
1694                                 tempval &= ~(MACCFG2_FDX);
1695                                 out_be32(&ug_regs->maccfg2, tempval);
1696
1697                                 ugeth_info("%s: Half Duplex", dev->name);
1698                         } else {
1699                                 tempval = in_be32(&ug_regs->maccfg2);
1700                                 tempval |= MACCFG2_FDX;
1701                                 out_be32(&ug_regs->maccfg2, tempval);
1702
1703                                 ugeth_info("%s: Full Duplex", dev->name);
1704                         }
1705
1706                         ugeth->oldduplex = mii_info->duplex;
1707                 }
1708
1709                 if (mii_info->speed != ugeth->oldspeed) {
1710                         switch (mii_info->speed) {
1711                         case 1000:
1712 #ifdef CONFIG_PPC_MPC836x
1713 /* FIXME: This code is for 100Mbs BUG fixing,
1714 remove this when it is fixed!!! */
1715                                 if (ugeth->ug_info->enet_interface ==
1716                                     ENET_1000_GMII)
1717                                 /* Run the commands which initialize the PHY */
1718                                 {
1719                                         tempval =
1720                                             (u32) mii_info->mdio_read(ugeth->
1721                                                 dev, mii_info->mii_id, 0x1b);
1722                                         tempval |= 0x000f;
1723                                         mii_info->mdio_write(ugeth->dev,
1724                                                 mii_info->mii_id, 0x1b,
1725                                                 (u16) tempval);
1726                                         tempval =
1727                                             (u32) mii_info->mdio_read(ugeth->
1728                                                 dev, mii_info->mii_id,
1729                                                 MII_BMCR);
1730                                         mii_info->mdio_write(ugeth->dev,
1731                                                 mii_info->mii_id, MII_BMCR,
1732                                                 (u16) (tempval | BMCR_RESET));
1733                                 } else if (ugeth->ug_info->enet_interface ==
1734                                            ENET_1000_RGMII)
1735                                 /* Run the commands which initialize the PHY */
1736                                 {
1737                                         tempval =
1738                                             (u32) mii_info->mdio_read(ugeth->
1739                                                 dev, mii_info->mii_id, 0x1b);
1740                                         tempval = (tempval & ~0x000f) | 0x000b;
1741                                         mii_info->mdio_write(ugeth->dev,
1742                                                 mii_info->mii_id, 0x1b,
1743                                                 (u16) tempval);
1744                                         tempval =
1745                                             (u32) mii_info->mdio_read(ugeth->
1746                                                 dev, mii_info->mii_id,
1747                                                 MII_BMCR);
1748                                         mii_info->mdio_write(ugeth->dev,
1749                                                 mii_info->mii_id, MII_BMCR,
1750                                                 (u16) (tempval | BMCR_RESET));
1751                                 }
1752                                 msleep(4000);
1753 #endif                          /* CONFIG_MPC8360 */
1754                                 adjust_enet_interface(ugeth);
1755                                 break;
1756                         case 100:
1757                         case 10:
1758 #ifdef CONFIG_PPC_MPC836x
1759 /* FIXME: This code is for 100Mbs BUG fixing,
1760 remove this lines when it will be fixed!!! */
1761                                 ugeth->ug_info->enet_interface = ENET_100_RGMII;
1762                                 tempval =
1763                                     (u32) mii_info->mdio_read(ugeth->dev,
1764                                                               mii_info->mii_id,
1765                                                               0x1b);
1766                                 tempval = (tempval & ~0x000f) | 0x000b;
1767                                 mii_info->mdio_write(ugeth->dev,
1768                                                      mii_info->mii_id, 0x1b,
1769                                                      (u16) tempval);
1770                                 tempval =
1771                                     (u32) mii_info->mdio_read(ugeth->dev,
1772                                                               mii_info->mii_id,
1773                                                               MII_BMCR);
1774                                 mii_info->mdio_write(ugeth->dev,
1775                                                      mii_info->mii_id, MII_BMCR,
1776                                                      (u16) (tempval |
1777                                                             BMCR_RESET));
1778                                 msleep(4000);
1779 #endif                          /* CONFIG_MPC8360 */
1780                                 adjust_enet_interface(ugeth);
1781                                 break;
1782                         default:
1783                                 ugeth_warn
1784                                     ("%s: Ack!  Speed (%d) is not 10/100/1000!",
1785                                      dev->name, mii_info->speed);
1786                                 break;
1787                         }
1788
1789                         ugeth_info("%s: Speed %dBT", dev->name,
1790                                    mii_info->speed);
1791
1792                         ugeth->oldspeed = mii_info->speed;
1793                 }
1794
1795                 if (!ugeth->oldlink) {
1796                         ugeth_info("%s: Link is up", dev->name);
1797                         ugeth->oldlink = 1;
1798                         netif_carrier_on(dev);
1799                         netif_schedule(dev);
1800                 }
1801         } else {
1802                 if (ugeth->oldlink) {
1803                         ugeth_info("%s: Link is down", dev->name);
1804                         ugeth->oldlink = 0;
1805                         ugeth->oldspeed = 0;
1806                         ugeth->oldduplex = -1;
1807                         netif_carrier_off(dev);
1808                 }
1809         }
1810 }
1811
1812 /* Configure the PHY for dev.
1813  * returns 0 if success.  -1 if failure
1814  */
1815 static int init_phy(struct net_device *dev)
1816 {
1817         struct ucc_geth_private *ugeth = netdev_priv(dev);
1818         struct phy_info *curphy;
1819         struct ucc_mii_mng *mii_regs;
1820         struct ugeth_mii_info *mii_info;
1821         int err;
1822
1823         mii_regs = &ugeth->ug_regs->miimng;
1824
1825         ugeth->oldlink = 0;
1826         ugeth->oldspeed = 0;
1827         ugeth->oldduplex = -1;
1828
1829         mii_info = kmalloc(sizeof(struct ugeth_mii_info), GFP_KERNEL);
1830
1831         if (NULL == mii_info) {
1832                 ugeth_err("%s: Could not allocate mii_info", dev->name);
1833                 return -ENOMEM;
1834         }
1835
1836         mii_info->mii_regs = mii_regs;
1837         mii_info->speed = SPEED_1000;
1838         mii_info->duplex = DUPLEX_FULL;
1839         mii_info->pause = 0;
1840         mii_info->link = 0;
1841
1842         mii_info->advertising = (ADVERTISED_10baseT_Half |
1843                                  ADVERTISED_10baseT_Full |
1844                                  ADVERTISED_100baseT_Half |
1845                                  ADVERTISED_100baseT_Full |
1846                                  ADVERTISED_1000baseT_Full);
1847         mii_info->autoneg = 1;
1848
1849         mii_info->mii_id = ugeth->ug_info->phy_address;
1850
1851         mii_info->dev = dev;
1852
1853         mii_info->mdio_read = &read_phy_reg;
1854         mii_info->mdio_write = &write_phy_reg;
1855
1856         spin_lock_init(&mii_info->mdio_lock);
1857
1858         ugeth->mii_info = mii_info;
1859
1860         spin_lock_irq(&ugeth->lock);
1861
1862         /* Set this UCC to be the master of the MII managment */
1863         ucc_set_qe_mux_mii_mng(ugeth->ug_info->uf_info.ucc_num);
1864
1865         if (init_mii_management_configuration(1,
1866                                               ugeth->ug_info->
1867                                               miiPreambleSupress,
1868                                               &mii_regs->miimcfg,
1869                                               &mii_regs->miimind)) {
1870                 ugeth_err("%s: The MII Bus is stuck!", dev->name);
1871                 err = -1;
1872                 goto bus_fail;
1873         }
1874
1875         spin_unlock_irq(&ugeth->lock);
1876
1877         /* get info for this PHY */
1878         curphy = get_phy_info(ugeth->mii_info);
1879
1880         if (curphy == NULL) {
1881                 ugeth_err("%s: No PHY found", dev->name);
1882                 err = -1;
1883                 goto no_phy;
1884         }
1885
1886         mii_info->phyinfo = curphy;
1887
1888         /* Run the commands which initialize the PHY */
1889         if (curphy->init) {
1890                 err = curphy->init(ugeth->mii_info);
1891                 if (err)
1892                         goto phy_init_fail;
1893         }
1894
1895         return 0;
1896
1897       phy_init_fail:
1898       no_phy:
1899       bus_fail:
1900         kfree(mii_info);
1901
1902         return err;
1903 }
1904
1905 #ifdef CONFIG_UGETH_TX_ON_DEMOND
1906 static int ugeth_transmit_on_demand(struct ucc_geth_private *ugeth)
1907 {
1908         struct ucc_fastransmit_on_demand(ugeth->uccf);
1909
1910         return 0;
1911 }
1912 #endif
1913
1914 static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth)
1915 {
1916         struct ucc_fast_private *uccf;
1917         u32 cecr_subblock;
1918         u32 temp;
1919
1920         uccf = ugeth->uccf;
1921
1922         /* Mask GRACEFUL STOP TX interrupt bit and clear it */
1923         temp = in_be32(uccf->p_uccm);
1924         temp &= ~UCCE_GRA;
1925         out_be32(uccf->p_uccm, temp);
1926         out_be32(uccf->p_ucce, UCCE_GRA);       /* clear by writing 1 */
1927
1928         /* Issue host command */
1929         cecr_subblock =
1930             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1931         qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
1932                      QE_CR_PROTOCOL_ETHERNET, 0);
1933
1934         /* Wait for command to complete */
1935         do {
1936                 temp = in_be32(uccf->p_ucce);
1937         } while (!(temp & UCCE_GRA));
1938
1939         uccf->stopped_tx = 1;
1940
1941         return 0;
1942 }
1943
1944 static int ugeth_graceful_stop_rx(struct ucc_geth_private * ugeth)
1945 {
1946         struct ucc_fast_private *uccf;
1947         u32 cecr_subblock;
1948         u8 temp;
1949
1950         uccf = ugeth->uccf;
1951
1952         /* Clear acknowledge bit */
1953         temp = ugeth->p_rx_glbl_pram->rxgstpack;
1954         temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
1955         ugeth->p_rx_glbl_pram->rxgstpack = temp;
1956
1957         /* Keep issuing command and checking acknowledge bit until
1958         it is asserted, according to spec */
1959         do {
1960                 /* Issue host command */
1961                 cecr_subblock =
1962                     ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.
1963                                                 ucc_num);
1964                 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
1965                              QE_CR_PROTOCOL_ETHERNET, 0);
1966
1967                 temp = ugeth->p_rx_glbl_pram->rxgstpack;
1968         } while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX));
1969
1970         uccf->stopped_rx = 1;
1971
1972         return 0;
1973 }
1974
1975 static int ugeth_restart_tx(struct ucc_geth_private *ugeth)
1976 {
1977         struct ucc_fast_private *uccf;
1978         u32 cecr_subblock;
1979
1980         uccf = ugeth->uccf;
1981
1982         cecr_subblock =
1983             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1984         qe_issue_cmd(QE_RESTART_TX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 0);
1985         uccf->stopped_tx = 0;
1986
1987         return 0;
1988 }
1989
1990 static int ugeth_restart_rx(struct ucc_geth_private *ugeth)
1991 {
1992         struct ucc_fast_private *uccf;
1993         u32 cecr_subblock;
1994
1995         uccf = ugeth->uccf;
1996
1997         cecr_subblock =
1998             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1999         qe_issue_cmd(QE_RESTART_RX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
2000                      0);
2001         uccf->stopped_rx = 0;
2002
2003         return 0;
2004 }
2005
2006 static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode)
2007 {
2008         struct ucc_fast_private *uccf;
2009         int enabled_tx, enabled_rx;
2010
2011         uccf = ugeth->uccf;
2012
2013         /* check if the UCC number is in range. */
2014         if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
2015                 ugeth_err("%s: ucc_num out of range.", __FUNCTION__);
2016                 return -EINVAL;
2017         }
2018
2019         enabled_tx = uccf->enabled_tx;
2020         enabled_rx = uccf->enabled_rx;
2021
2022         /* Get Tx and Rx going again, in case this channel was actively
2023         disabled. */
2024         if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx)
2025                 ugeth_restart_tx(ugeth);
2026         if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx)
2027                 ugeth_restart_rx(ugeth);
2028
2029         ucc_fast_enable(uccf, mode);    /* OK to do even if not disabled */
2030
2031         return 0;
2032
2033 }
2034
2035 static int ugeth_disable(struct ucc_geth_private * ugeth, enum comm_dir mode)
2036 {
2037         struct ucc_fast_private *uccf;
2038
2039         uccf = ugeth->uccf;
2040
2041         /* check if the UCC number is in range. */
2042         if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
2043                 ugeth_err("%s: ucc_num out of range.", __FUNCTION__);
2044                 return -EINVAL;
2045         }
2046
2047         /* Stop any transmissions */
2048         if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx)
2049                 ugeth_graceful_stop_tx(ugeth);
2050
2051         /* Stop any receptions */
2052         if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx)
2053                 ugeth_graceful_stop_rx(ugeth);
2054
2055         ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */
2056
2057         return 0;
2058 }
2059
2060 static void ugeth_dump_regs(struct ucc_geth_private *ugeth)
2061 {
2062 #ifdef DEBUG
2063         ucc_fast_dump_regs(ugeth->uccf);
2064         dump_regs(ugeth);
2065         dump_bds(ugeth);
2066 #endif
2067 }
2068
2069 #ifdef CONFIG_UGETH_FILTERING
2070 static int ugeth_ext_filtering_serialize_tad(struct ucc_geth_tad_params *
2071                                              p_UccGethTadParams,
2072                                              struct qe_fltr_tad *qe_fltr_tad)
2073 {
2074         u16 temp;
2075
2076         /* Zero serialized TAD */
2077         memset(qe_fltr_tad, 0, QE_FLTR_TAD_SIZE);
2078
2079         qe_fltr_tad->serialized[0] |= UCC_GETH_TAD_V;   /* Must have this */
2080         if (p_UccGethTadParams->rx_non_dynamic_extended_features_mode ||
2081             (p_UccGethTadParams->vtag_op != UCC_GETH_VLAN_OPERATION_TAGGED_NOP)
2082             || (p_UccGethTadParams->vnontag_op !=
2083                 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP)
2084             )
2085                 qe_fltr_tad->serialized[0] |= UCC_GETH_TAD_EF;
2086         if (p_UccGethTadParams->reject_frame)
2087                 qe_fltr_tad->serialized[0] |= UCC_GETH_TAD_REJ;
2088         temp =
2089             (u16) (((u16) p_UccGethTadParams->
2090                     vtag_op) << UCC_GETH_TAD_VTAG_OP_SHIFT);
2091         qe_fltr_tad->serialized[0] |= (u8) (temp >> 8); /* upper bits */
2092
2093         qe_fltr_tad->serialized[1] |= (u8) (temp & 0x00ff);     /* lower bits */
2094         if (p_UccGethTadParams->vnontag_op ==
2095             UCC_GETH_VLAN_OPERATION_NON_TAGGED_Q_TAG_INSERT)
2096                 qe_fltr_tad->serialized[1] |= UCC_GETH_TAD_V_NON_VTAG_OP;
2097         qe_fltr_tad->serialized[1] |=
2098             p_UccGethTadParams->rqos << UCC_GETH_TAD_RQOS_SHIFT;
2099
2100         qe_fltr_tad->serialized[2] |=
2101             p_UccGethTadParams->vpri << UCC_GETH_TAD_V_PRIORITY_SHIFT;
2102         /* upper bits */
2103         qe_fltr_tad->serialized[2] |= (u8) (p_UccGethTadParams->vid >> 8);
2104         /* lower bits */
2105         qe_fltr_tad->serialized[3] |= (u8) (p_UccGethTadParams->vid & 0x00ff);
2106
2107         return 0;
2108 }
2109
2110 static struct enet_addr_container_t
2111     *ugeth_82xx_filtering_get_match_addr_in_hash(struct ucc_geth_private *ugeth,
2112                                                  struct enet_addr *p_enet_addr)
2113 {
2114         struct enet_addr_container *enet_addr_cont;
2115         struct list_head *p_lh;
2116         u16 i, num;
2117         int32_t j;
2118         u8 *p_counter;
2119
2120         if ((*p_enet_addr)[0] & ENET_GROUP_ADDR) {
2121                 p_lh = &ugeth->group_hash_q;
2122                 p_counter = &(ugeth->numGroupAddrInHash);
2123         } else {
2124                 p_lh = &ugeth->ind_hash_q;
2125                 p_counter = &(ugeth->numIndAddrInHash);
2126         }
2127
2128         if (!p_lh)
2129                 return NULL;
2130
2131         num = *p_counter;
2132
2133         for (i = 0; i < num; i++) {
2134                 enet_addr_cont =
2135                     (struct enet_addr_container *)
2136                     ENET_ADDR_CONT_ENTRY(dequeue(p_lh));
2137                 for (j = ENET_NUM_OCTETS_PER_ADDRESS - 1; j >= 0; j--) {
2138                         if ((*p_enet_addr)[j] != (enet_addr_cont->address)[j])
2139                                 break;
2140                         if (j == 0)
2141                                 return enet_addr_cont;  /* Found */
2142                 }
2143                 enqueue(p_lh, &enet_addr_cont->node);   /* Put it back */
2144         }
2145         return NULL;
2146 }
2147
2148 static int ugeth_82xx_filtering_add_addr_in_hash(struct ucc_geth_private *ugeth,
2149                                                  struct enet_addr *p_enet_addr)
2150 {
2151         enum ucc_geth_enet_address_recognition_location location;
2152         struct enet_addr_container *enet_addr_cont;
2153         struct list_head *p_lh;
2154         u8 i;
2155         u32 limit;
2156         u8 *p_counter;
2157
2158         if ((*p_enet_addr)[0] & ENET_GROUP_ADDR) {
2159                 p_lh = &ugeth->group_hash_q;
2160                 limit = ugeth->ug_info->maxGroupAddrInHash;
2161                 location =
2162                     UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_GROUP_HASH;
2163                 p_counter = &(ugeth->numGroupAddrInHash);
2164         } else {
2165                 p_lh = &ugeth->ind_hash_q;
2166                 limit = ugeth->ug_info->maxIndAddrInHash;
2167                 location =
2168                     UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_INDIVIDUAL_HASH;
2169                 p_counter = &(ugeth->numIndAddrInHash);
2170         }
2171
2172         if ((enet_addr_cont =
2173              ugeth_82xx_filtering_get_match_addr_in_hash(ugeth, p_enet_addr))) {
2174                 list_add(p_lh, &enet_addr_cont->node);  /* Put it back */
2175                 return 0;
2176         }
2177         if ((!p_lh) || (!(*p_counter < limit)))
2178                 return -EBUSY;
2179         if (!(enet_addr_cont = get_enet_addr_container()))
2180                 return -ENOMEM;
2181         for (i = 0; i < ENET_NUM_OCTETS_PER_ADDRESS; i++)
2182                 (enet_addr_cont->address)[i] = (*p_enet_addr)[i];
2183         enet_addr_cont->location = location;
2184         enqueue(p_lh, &enet_addr_cont->node);   /* Put it back */
2185         ++(*p_counter);
2186
2187         hw_add_addr_in_hash(ugeth, enet_addr_cont->address);
2188         return 0;
2189 }
2190
2191 static int ugeth_82xx_filtering_clear_addr_in_hash(struct ucc_geth_private *ugeth,
2192                                                    struct enet_addr *p_enet_addr)
2193 {
2194         struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
2195         struct enet_addr_container *enet_addr_cont;
2196         struct ucc_fast_private *uccf;
2197         enum comm_dir comm_dir;
2198         u16 i, num;
2199         struct list_head *p_lh;
2200         u32 *addr_h, *addr_l;
2201         u8 *p_counter;
2202
2203         uccf = ugeth->uccf;
2204
2205         p_82xx_addr_filt =
2206             (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
2207             addressfiltering;
2208
2209         if (!
2210             (enet_addr_cont =
2211              ugeth_82xx_filtering_get_match_addr_in_hash(ugeth, p_enet_addr)))
2212                 return -ENOENT;
2213
2214         /* It's been found and removed from the CQ. */
2215         /* Now destroy its container */
2216         put_enet_addr_container(enet_addr_cont);
2217
2218         if ((*p_enet_addr)[0] & ENET_GROUP_ADDR) {
2219                 addr_h = &(p_82xx_addr_filt->gaddr_h);
2220                 addr_l = &(p_82xx_addr_filt->gaddr_l);
2221                 p_lh = &ugeth->group_hash_q;
2222                 p_counter = &(ugeth->numGroupAddrInHash);
2223         } else {
2224                 addr_h = &(p_82xx_addr_filt->iaddr_h);
2225                 addr_l = &(p_82xx_addr_filt->iaddr_l);
2226                 p_lh = &ugeth->ind_hash_q;
2227                 p_counter = &(ugeth->numIndAddrInHash);
2228         }
2229
2230         comm_dir = 0;
2231         if (uccf->enabled_tx)
2232                 comm_dir |= COMM_DIR_TX;
2233         if (uccf->enabled_rx)
2234                 comm_dir |= COMM_DIR_RX;
2235         if (comm_dir)
2236                 ugeth_disable(ugeth, comm_dir);
2237
2238         /* Clear the hash table. */
2239         out_be32(addr_h, 0x00000000);
2240         out_be32(addr_l, 0x00000000);
2241
2242         /* Add all remaining CQ elements back into hash */
2243         num = --(*p_counter);
2244         for (i = 0; i < num; i++) {
2245                 enet_addr_cont =
2246                     (struct enet_addr_container *)
2247                     ENET_ADDR_CONT_ENTRY(dequeue(p_lh));
2248                 hw_add_addr_in_hash(ugeth, enet_addr_cont->address);
2249                 enqueue(p_lh, &enet_addr_cont->node);   /* Put it back */
2250         }
2251
2252         if (comm_dir)
2253                 ugeth_enable(ugeth, comm_dir);
2254
2255         return 0;
2256 }
2257 #endif /* CONFIG_UGETH_FILTERING */
2258
2259 static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private *
2260                                                        ugeth,
2261                                                        enum enet_addr_type
2262                                                        enet_addr_type)
2263 {
2264         struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
2265         struct ucc_fast_private *uccf;
2266         enum comm_dir comm_dir;
2267         struct list_head *p_lh;
2268         u16 i, num;
2269         u32 *addr_h, *addr_l;
2270         u8 *p_counter;
2271
2272         uccf = ugeth->uccf;
2273
2274         p_82xx_addr_filt =
2275             (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
2276             addressfiltering;
2277
2278         if (enet_addr_type == ENET_ADDR_TYPE_GROUP) {
2279                 addr_h = &(p_82xx_addr_filt->gaddr_h);
2280                 addr_l = &(p_82xx_addr_filt->gaddr_l);
2281                 p_lh = &ugeth->group_hash_q;
2282                 p_counter = &(ugeth->numGroupAddrInHash);
2283         } else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) {
2284                 addr_h = &(p_82xx_addr_filt->iaddr_h);
2285                 addr_l = &(p_82xx_addr_filt->iaddr_l);
2286                 p_lh = &ugeth->ind_hash_q;
2287                 p_counter = &(ugeth->numIndAddrInHash);
2288         } else
2289                 return -EINVAL;
2290
2291         comm_dir = 0;
2292         if (uccf->enabled_tx)
2293                 comm_dir |= COMM_DIR_TX;
2294         if (uccf->enabled_rx)
2295                 comm_dir |= COMM_DIR_RX;
2296         if (comm_dir)
2297                 ugeth_disable(ugeth, comm_dir);
2298
2299         /* Clear the hash table. */
2300         out_be32(addr_h, 0x00000000);
2301         out_be32(addr_l, 0x00000000);
2302
2303         if (!p_lh)
2304                 return 0;
2305
2306         num = *p_counter;
2307
2308         /* Delete all remaining CQ elements */
2309         for (i = 0; i < num; i++)
2310                 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh)));
2311
2312         *p_counter = 0;
2313
2314         if (comm_dir)
2315                 ugeth_enable(ugeth, comm_dir);
2316
2317         return 0;
2318 }
2319
2320 #ifdef CONFIG_UGETH_FILTERING
2321 static int ugeth_82xx_filtering_add_addr_in_paddr(struct ucc_geth_private *ugeth,
2322                                                   struct enet_addr *p_enet_addr,
2323                                                   u8 paddr_num)
2324 {
2325         int i;
2326
2327         if ((*p_enet_addr)[0] & ENET_GROUP_ADDR)
2328                 ugeth_warn
2329                     ("%s: multicast address added to paddr will have no "
2330                      "effect - is this what you wanted?",
2331                      __FUNCTION__);
2332
2333         ugeth->indAddrRegUsed[paddr_num] = 1;   /* mark this paddr as used */
2334         /* store address in our database */
2335         for (i = 0; i < ENET_NUM_OCTETS_PER_ADDRESS; i++)
2336                 ugeth->paddr[paddr_num][i] = (*p_enet_addr)[i];
2337         /* put in hardware */
2338         return hw_add_addr_in_paddr(ugeth, p_enet_addr, paddr_num);
2339 }
2340 #endif /* CONFIG_UGETH_FILTERING */
2341
2342 static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth,
2343                                                     u8 paddr_num)
2344 {
2345         ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */
2346         return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */
2347 }
2348
2349 static void ucc_geth_memclean(struct ucc_geth_private *ugeth)
2350 {
2351         u16 i, j;
2352         u8 *bd;
2353
2354         if (!ugeth)
2355                 return;
2356
2357         if (ugeth->uccf)
2358                 ucc_fast_free(ugeth->uccf);
2359
2360         if (ugeth->p_thread_data_tx) {
2361                 qe_muram_free(ugeth->thread_dat_tx_offset);
2362                 ugeth->p_thread_data_tx = NULL;
2363         }
2364         if (ugeth->p_thread_data_rx) {
2365                 qe_muram_free(ugeth->thread_dat_rx_offset);
2366                 ugeth->p_thread_data_rx = NULL;
2367         }
2368         if (ugeth->p_exf_glbl_param) {
2369                 qe_muram_free(ugeth->exf_glbl_param_offset);
2370                 ugeth->p_exf_glbl_param = NULL;
2371         }
2372         if (ugeth->p_rx_glbl_pram) {
2373                 qe_muram_free(ugeth->rx_glbl_pram_offset);
2374                 ugeth->p_rx_glbl_pram = NULL;
2375         }
2376         if (ugeth->p_tx_glbl_pram) {
2377                 qe_muram_free(ugeth->tx_glbl_pram_offset);
2378                 ugeth->p_tx_glbl_pram = NULL;
2379         }
2380         if (ugeth->p_send_q_mem_reg) {
2381                 qe_muram_free(ugeth->send_q_mem_reg_offset);
2382                 ugeth->p_send_q_mem_reg = NULL;
2383         }
2384         if (ugeth->p_scheduler) {
2385                 qe_muram_free(ugeth->scheduler_offset);
2386                 ugeth->p_scheduler = NULL;
2387         }
2388         if (ugeth->p_tx_fw_statistics_pram) {
2389                 qe_muram_free(ugeth->tx_fw_statistics_pram_offset);
2390                 ugeth->p_tx_fw_statistics_pram = NULL;
2391         }
2392         if (ugeth->p_rx_fw_statistics_pram) {
2393                 qe_muram_free(ugeth->rx_fw_statistics_pram_offset);
2394                 ugeth->p_rx_fw_statistics_pram = NULL;
2395         }
2396         if (ugeth->p_rx_irq_coalescing_tbl) {
2397                 qe_muram_free(ugeth->rx_irq_coalescing_tbl_offset);
2398                 ugeth->p_rx_irq_coalescing_tbl = NULL;
2399         }
2400         if (ugeth->p_rx_bd_qs_tbl) {
2401                 qe_muram_free(ugeth->rx_bd_qs_tbl_offset);
2402                 ugeth->p_rx_bd_qs_tbl = NULL;
2403         }
2404         if (ugeth->p_init_enet_param_shadow) {
2405                 return_init_enet_entries(ugeth,
2406                                          &(ugeth->p_init_enet_param_shadow->
2407                                            rxthread[0]),
2408                                          ENET_INIT_PARAM_MAX_ENTRIES_RX,
2409                                          ugeth->ug_info->riscRx, 1);
2410                 return_init_enet_entries(ugeth,
2411                                          &(ugeth->p_init_enet_param_shadow->
2412                                            txthread[0]),
2413                                          ENET_INIT_PARAM_MAX_ENTRIES_TX,
2414                                          ugeth->ug_info->riscTx, 0);
2415                 kfree(ugeth->p_init_enet_param_shadow);
2416                 ugeth->p_init_enet_param_shadow = NULL;
2417         }
2418         for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
2419                 bd = ugeth->p_tx_bd_ring[i];
2420                 for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) {
2421                         if (ugeth->tx_skbuff[i][j]) {
2422                                 dma_unmap_single(NULL,
2423                                                  ((qe_bd_t *)bd)->buf,
2424                                                  (in_be32((u32 *)bd) &
2425                                                   BD_LENGTH_MASK),
2426                                                  DMA_TO_DEVICE);
2427                                 dev_kfree_skb_any(ugeth->tx_skbuff[i][j]);
2428                                 ugeth->tx_skbuff[i][j] = NULL;
2429                         }
2430                 }
2431
2432                 kfree(ugeth->tx_skbuff[i]);
2433
2434                 if (ugeth->p_tx_bd_ring[i]) {
2435                         if (ugeth->ug_info->uf_info.bd_mem_part ==
2436                             MEM_PART_SYSTEM)
2437                                 kfree((void *)ugeth->tx_bd_ring_offset[i]);
2438                         else if (ugeth->ug_info->uf_info.bd_mem_part ==
2439                                  MEM_PART_MURAM)
2440                                 qe_muram_free(ugeth->tx_bd_ring_offset[i]);
2441                         ugeth->p_tx_bd_ring[i] = NULL;
2442                 }
2443         }
2444         for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
2445                 if (ugeth->p_rx_bd_ring[i]) {
2446                         /* Return existing data buffers in ring */
2447                         bd = ugeth->p_rx_bd_ring[i];
2448                         for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) {
2449                                 if (ugeth->rx_skbuff[i][j]) {
2450                                         dma_unmap_single(NULL,
2451                                                 ((struct qe_bd *)bd)->buf,
2452                                                 ugeth->ug_info->
2453                                                 uf_info.max_rx_buf_length +
2454                                                 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
2455                                                 DMA_FROM_DEVICE);
2456                                         dev_kfree_skb_any(
2457                                                 ugeth->rx_skbuff[i][j]);
2458                                         ugeth->rx_skbuff[i][j] = NULL;
2459                                 }
2460                                 bd += sizeof(struct qe_bd);
2461                         }
2462
2463                         kfree(ugeth->rx_skbuff[i]);
2464
2465                         if (ugeth->ug_info->uf_info.bd_mem_part ==
2466                             MEM_PART_SYSTEM)
2467                                 kfree((void *)ugeth->rx_bd_ring_offset[i]);
2468                         else if (ugeth->ug_info->uf_info.bd_mem_part ==
2469                                  MEM_PART_MURAM)
2470                                 qe_muram_free(ugeth->rx_bd_ring_offset[i]);
2471                         ugeth->p_rx_bd_ring[i] = NULL;
2472                 }
2473         }
2474         while (!list_empty(&ugeth->group_hash_q))
2475                 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
2476                                         (dequeue(&ugeth->group_hash_q)));
2477         while (!list_empty(&ugeth->ind_hash_q))
2478                 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
2479                                         (dequeue(&ugeth->ind_hash_q)));
2480
2481 }
2482
2483 static void ucc_geth_set_multi(struct net_device *dev)
2484 {
2485         struct ucc_geth_private *ugeth;
2486         struct dev_mc_list *dmi;
2487         struct ucc_fast *uf_regs;
2488         struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
2489         u8 tempaddr[6];
2490         u8 *mcptr, *tdptr;
2491         int i, j;
2492
2493         ugeth = netdev_priv(dev);
2494
2495         uf_regs = ugeth->uccf->uf_regs;
2496
2497         if (dev->flags & IFF_PROMISC) {
2498
2499                 uf_regs->upsmr |= UPSMR_PRO;
2500
2501         } else {
2502
2503                 uf_regs->upsmr &= ~UPSMR_PRO;
2504
2505                 p_82xx_addr_filt =
2506                     (struct ucc_geth_82xx_address_filtering_pram *) ugeth->
2507                     p_rx_glbl_pram->addressfiltering;
2508
2509                 if (dev->flags & IFF_ALLMULTI) {
2510                         /* Catch all multicast addresses, so set the
2511                          * filter to all 1's.
2512                          */
2513                         out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff);
2514                         out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff);
2515                 } else {
2516                         /* Clear filter and add the addresses in the list.
2517                          */
2518                         out_be32(&p_82xx_addr_filt->gaddr_h, 0x0);
2519                         out_be32(&p_82xx_addr_filt->gaddr_l, 0x0);
2520
2521                         dmi = dev->mc_list;
2522
2523                         for (i = 0; i < dev->mc_count; i++, dmi = dmi->next) {
2524
2525                                 /* Only support group multicast for now.
2526                                  */
2527                                 if (!(dmi->dmi_addr[0] & 1))
2528                                         continue;
2529
2530                                 /* The address in dmi_addr is LSB first,
2531                                  * and taddr is MSB first.  We have to
2532                                  * copy bytes MSB first from dmi_addr.
2533                                  */
2534                                 mcptr = (u8 *) dmi->dmi_addr + 5;
2535                                 tdptr = (u8 *) tempaddr;
2536                                 for (j = 0; j < 6; j++)
2537                                         *tdptr++ = *mcptr--;
2538
2539                                 /* Ask CPM to run CRC and set bit in
2540                                  * filter mask.
2541                                  */
2542                                 hw_add_addr_in_hash(ugeth, tempaddr);
2543                         }
2544                 }
2545         }
2546 }
2547
2548 static void ucc_geth_stop(struct ucc_geth_private *ugeth)
2549 {
2550         struct ucc_geth *ug_regs = ugeth->ug_regs;
2551         u32 tempval;
2552
2553         ugeth_vdbg("%s: IN", __FUNCTION__);
2554
2555         /* Disable the controller */
2556         ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
2557
2558         /* Tell the kernel the link is down */
2559         ugeth->mii_info->link = 0;
2560         adjust_link(ugeth->dev);
2561
2562         /* Mask all interrupts */
2563         out_be32(ugeth->uccf->p_ucce, 0x00000000);
2564
2565         /* Clear all interrupts */
2566         out_be32(ugeth->uccf->p_ucce, 0xffffffff);
2567
2568         /* Disable Rx and Tx */
2569         tempval = in_be32(&ug_regs->maccfg1);
2570         tempval &= ~(MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2571         out_be32(&ug_regs->maccfg1, tempval);
2572
2573         if (ugeth->ug_info->board_flags & FSL_UGETH_BRD_HAS_PHY_INTR) {
2574                 /* Clear any pending interrupts */
2575                 mii_clear_phy_interrupt(ugeth->mii_info);
2576
2577                 /* Disable PHY Interrupts */
2578                 mii_configure_phy_interrupt(ugeth->mii_info,
2579                                             MII_INTERRUPT_DISABLED);
2580         }
2581
2582         free_irq(ugeth->ug_info->uf_info.irq, ugeth->dev);
2583
2584         if (ugeth->ug_info->board_flags & FSL_UGETH_BRD_HAS_PHY_INTR) {
2585                 free_irq(ugeth->ug_info->phy_interrupt, ugeth->dev);
2586         } else {
2587                 del_timer_sync(&ugeth->phy_info_timer);
2588         }
2589
2590         ucc_geth_memclean(ugeth);
2591 }
2592
2593 static int ucc_geth_startup(struct ucc_geth_private *ugeth)
2594 {
2595         struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
2596         struct ucc_geth_init_pram *p_init_enet_pram;
2597         struct ucc_fast_private *uccf;
2598         struct ucc_geth_info *ug_info;
2599         struct ucc_fast_info *uf_info;
2600         struct ucc_fast *uf_regs;
2601         struct ucc_geth *ug_regs;
2602         int ret_val = -EINVAL;
2603         u32 remoder = UCC_GETH_REMODER_INIT;
2604         u32 init_enet_pram_offset, cecr_subblock, command, maccfg1;
2605         u32 ifstat, i, j, size, l2qt, l3qt, length;
2606         u16 temoder = UCC_GETH_TEMODER_INIT;
2607         u16 test;
2608         u8 function_code = 0;
2609         u8 *bd, *endOfRing;
2610         u8 numThreadsRxNumerical, numThreadsTxNumerical;
2611
2612         ugeth_vdbg("%s: IN", __FUNCTION__);
2613
2614         ug_info = ugeth->ug_info;
2615         uf_info = &ug_info->uf_info;
2616
2617         if (!((uf_info->bd_mem_part == MEM_PART_SYSTEM) ||
2618               (uf_info->bd_mem_part == MEM_PART_MURAM))) {
2619                 ugeth_err("%s: Bad memory partition value.", __FUNCTION__);
2620                 return -EINVAL;
2621         }
2622
2623         /* Rx BD lengths */
2624         for (i = 0; i < ug_info->numQueuesRx; i++) {
2625                 if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) ||
2626                     (ug_info->bdRingLenRx[i] %
2627                      UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) {
2628                         ugeth_err
2629                             ("%s: Rx BD ring length must be multiple of 4,"
2630                                 " no smaller than 8.", __FUNCTION__);
2631                         return -EINVAL;
2632                 }
2633         }
2634
2635         /* Tx BD lengths */
2636         for (i = 0; i < ug_info->numQueuesTx; i++) {
2637                 if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) {
2638                         ugeth_err
2639                             ("%s: Tx BD ring length must be no smaller than 2.",
2640                              __FUNCTION__);
2641                         return -EINVAL;
2642                 }
2643         }
2644
2645         /* mrblr */
2646         if ((uf_info->max_rx_buf_length == 0) ||
2647             (uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) {
2648                 ugeth_err
2649                     ("%s: max_rx_buf_length must be non-zero multiple of 128.",
2650                      __FUNCTION__);
2651                 return -EINVAL;
2652         }
2653
2654         /* num Tx queues */
2655         if (ug_info->numQueuesTx > NUM_TX_QUEUES) {
2656                 ugeth_err("%s: number of tx queues too large.", __FUNCTION__);
2657                 return -EINVAL;
2658         }
2659
2660         /* num Rx queues */
2661         if (ug_info->numQueuesRx > NUM_RX_QUEUES) {
2662                 ugeth_err("%s: number of rx queues too large.", __FUNCTION__);
2663                 return -EINVAL;
2664         }
2665
2666         /* l2qt */
2667         for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) {
2668                 if (ug_info->l2qt[i] >= ug_info->numQueuesRx) {
2669                         ugeth_err
2670                             ("%s: VLAN priority table entry must not be"
2671                                 " larger than number of Rx queues.",
2672                              __FUNCTION__);
2673                         return -EINVAL;
2674                 }
2675         }
2676
2677         /* l3qt */
2678         for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) {
2679                 if (ug_info->l3qt[i] >= ug_info->numQueuesRx) {
2680                         ugeth_err
2681                             ("%s: IP priority table entry must not be"
2682                                 " larger than number of Rx queues.",
2683                              __FUNCTION__);
2684                         return -EINVAL;
2685                 }
2686         }
2687
2688         if (ug_info->cam && !ug_info->ecamptr) {
2689                 ugeth_err("%s: If cam mode is chosen, must supply cam ptr.",
2690                           __FUNCTION__);
2691                 return -EINVAL;
2692         }
2693
2694         if ((ug_info->numStationAddresses !=
2695              UCC_GETH_NUM_OF_STATION_ADDRESSES_1)
2696             && ug_info->rxExtendedFiltering) {
2697                 ugeth_err("%s: Number of station addresses greater than 1 "
2698                           "not allowed in extended parsing mode.",
2699                           __FUNCTION__);
2700                 return -EINVAL;
2701         }
2702
2703         /* Generate uccm_mask for receive */
2704         uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */
2705         for (i = 0; i < ug_info->numQueuesRx; i++)
2706                 uf_info->uccm_mask |= (UCCE_RXBF_SINGLE_MASK << i);
2707
2708         for (i = 0; i < ug_info->numQueuesTx; i++)
2709                 uf_info->uccm_mask |= (UCCE_TXBF_SINGLE_MASK << i);
2710         /* Initialize the general fast UCC block. */
2711         if (ucc_fast_init(uf_info, &uccf)) {
2712                 ugeth_err("%s: Failed to init uccf.", __FUNCTION__);
2713                 ucc_geth_memclean(ugeth);
2714                 return -ENOMEM;
2715         }
2716         ugeth->uccf = uccf;
2717
2718         switch (ug_info->numThreadsRx) {
2719         case UCC_GETH_NUM_OF_THREADS_1:
2720                 numThreadsRxNumerical = 1;
2721                 break;
2722         case UCC_GETH_NUM_OF_THREADS_2:
2723                 numThreadsRxNumerical = 2;
2724                 break;
2725         case UCC_GETH_NUM_OF_THREADS_4:
2726                 numThreadsRxNumerical = 4;
2727                 break;
2728         case UCC_GETH_NUM_OF_THREADS_6:
2729                 numThreadsRxNumerical = 6;
2730                 break;
2731         case UCC_GETH_NUM_OF_THREADS_8:
2732                 numThreadsRxNumerical = 8;
2733                 break;
2734         default:
2735                 ugeth_err("%s: Bad number of Rx threads value.", __FUNCTION__);
2736                 ucc_geth_memclean(ugeth);
2737                 return -EINVAL;
2738                 break;
2739         }
2740
2741         switch (ug_info->numThreadsTx) {
2742         case UCC_GETH_NUM_OF_THREADS_1:
2743                 numThreadsTxNumerical = 1;
2744                 break;
2745         case UCC_GETH_NUM_OF_THREADS_2:
2746                 numThreadsTxNumerical = 2;
2747                 break;
2748         case UCC_GETH_NUM_OF_THREADS_4:
2749                 numThreadsTxNumerical = 4;
2750                 break;
2751         case UCC_GETH_NUM_OF_THREADS_6:
2752                 numThreadsTxNumerical = 6;
2753                 break;
2754         case UCC_GETH_NUM_OF_THREADS_8:
2755                 numThreadsTxNumerical = 8;
2756                 break;
2757         default:
2758                 ugeth_err("%s: Bad number of Tx threads value.", __FUNCTION__);
2759                 ucc_geth_memclean(ugeth);
2760                 return -EINVAL;
2761                 break;
2762         }
2763
2764         /* Calculate rx_extended_features */
2765         ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck ||
2766             ug_info->ipAddressAlignment ||
2767             (ug_info->numStationAddresses !=
2768              UCC_GETH_NUM_OF_STATION_ADDRESSES_1);
2769
2770         ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features ||
2771             (ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP)
2772             || (ug_info->vlanOperationNonTagged !=
2773                 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP);
2774
2775         uf_regs = uccf->uf_regs;
2776         ug_regs = (struct ucc_geth *) (uccf->uf_regs);
2777         ugeth->ug_regs = ug_regs;
2778
2779         init_default_reg_vals(&uf_regs->upsmr,
2780                               &ug_regs->maccfg1, &ug_regs->maccfg2);
2781
2782         /*                    Set UPSMR                      */
2783         /* For more details see the hardware spec.           */
2784         init_rx_parameters(ug_info->bro,
2785                            ug_info->rsh, ug_info->pro, &uf_regs->upsmr);
2786
2787         /* We're going to ignore other registers for now, */
2788         /* except as needed to get up and running         */
2789
2790         /*                    Set MACCFG1                    */
2791         /* For more details see the hardware spec.           */
2792         init_flow_control_params(ug_info->aufc,
2793                                  ug_info->receiveFlowControl,
2794                                  1,
2795                                  ug_info->pausePeriod,
2796                                  ug_info->extensionField,
2797                                  &uf_regs->upsmr,
2798                                  &ug_regs->uempr, &ug_regs->maccfg1);
2799
2800         maccfg1 = in_be32(&ug_regs->maccfg1);
2801         maccfg1 |= MACCFG1_ENABLE_RX;
2802         maccfg1 |= MACCFG1_ENABLE_TX;
2803         out_be32(&ug_regs->maccfg1, maccfg1);
2804
2805         /*                    Set IPGIFG                     */
2806         /* For more details see the hardware spec.           */
2807         ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1,
2808                                               ug_info->nonBackToBackIfgPart2,
2809                                               ug_info->
2810                                               miminumInterFrameGapEnforcement,
2811                                               ug_info->backToBackInterFrameGap,
2812                                               &ug_regs->ipgifg);
2813         if (ret_val != 0) {
2814                 ugeth_err("%s: IPGIFG initialization parameter too large.",
2815                           __FUNCTION__);
2816                 ucc_geth_memclean(ugeth);
2817                 return ret_val;
2818         }
2819
2820         /*                    Set HAFDUP                     */
2821         /* For more details see the hardware spec.           */
2822         ret_val = init_half_duplex_params(ug_info->altBeb,
2823                                           ug_info->backPressureNoBackoff,
2824                                           ug_info->noBackoff,
2825                                           ug_info->excessDefer,
2826                                           ug_info->altBebTruncation,
2827                                           ug_info->maxRetransmission,
2828                                           ug_info->collisionWindow,
2829                                           &ug_regs->hafdup);
2830         if (ret_val != 0) {
2831                 ugeth_err("%s: Half Duplex initialization parameter too large.",
2832                           __FUNCTION__);
2833                 ucc_geth_memclean(ugeth);
2834                 return ret_val;
2835         }
2836
2837         /*                    Set IFSTAT                     */
2838         /* For more details see the hardware spec.           */
2839         /* Read only - resets upon read                      */
2840         ifstat = in_be32(&ug_regs->ifstat);
2841
2842         /*                    Clear UEMPR                    */
2843         /* For more details see the hardware spec.           */
2844         out_be32(&ug_regs->uempr, 0);
2845
2846         /*                    Set UESCR                      */
2847         /* For more details see the hardware spec.           */
2848         init_hw_statistics_gathering_mode((ug_info->statisticsMode &
2849                                 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE),
2850                                 0, &uf_regs->upsmr, &ug_regs->uescr);
2851
2852         /* Allocate Tx bds */
2853         for (j = 0; j < ug_info->numQueuesTx; j++) {
2854                 /* Allocate in multiple of
2855                    UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT,
2856                    according to spec */
2857                 length = ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd))
2858                           / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2859                     * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2860                 if ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) %
2861                     UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2862                         length += UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2863                 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2864                         u32 align = 4;
2865                         if (UCC_GETH_TX_BD_RING_ALIGNMENT > 4)
2866                                 align = UCC_GETH_TX_BD_RING_ALIGNMENT;
2867                         ugeth->tx_bd_ring_offset[j] =
2868                                 kmalloc((u32) (length + align), GFP_KERNEL);
2869
2870                         if (ugeth->tx_bd_ring_offset[j] != 0)
2871                                 ugeth->p_tx_bd_ring[j] =
2872                                         (void*)((ugeth->tx_bd_ring_offset[j] +
2873                                         align) & ~(align - 1));
2874                 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2875                         ugeth->tx_bd_ring_offset[j] =
2876                             qe_muram_alloc(length,
2877                                            UCC_GETH_TX_BD_RING_ALIGNMENT);
2878                         if (!IS_MURAM_ERR(ugeth->tx_bd_ring_offset[j]))
2879                                 ugeth->p_tx_bd_ring[j] =
2880                                     (u8 *) qe_muram_addr(ugeth->
2881                                                          tx_bd_ring_offset[j]);
2882                 }
2883                 if (!ugeth->p_tx_bd_ring[j]) {
2884                         ugeth_err
2885                             ("%s: Can not allocate memory for Tx bd rings.",
2886                              __FUNCTION__);
2887                         ucc_geth_memclean(ugeth);
2888                         return -ENOMEM;
2889                 }
2890                 /* Zero unused end of bd ring, according to spec */
2891                 memset(ugeth->p_tx_bd_ring[j] +
2892                        ug_info->bdRingLenTx[j] * sizeof(struct qe_bd), 0,
2893                        length - ug_info->bdRingLenTx[j] * sizeof(struct qe_bd));
2894         }
2895
2896         /* Allocate Rx bds */
2897         for (j = 0; j < ug_info->numQueuesRx; j++) {
2898                 length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd);
2899                 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2900                         u32 align = 4;
2901                         if (UCC_GETH_RX_BD_RING_ALIGNMENT > 4)
2902                                 align = UCC_GETH_RX_BD_RING_ALIGNMENT;
2903                         ugeth->rx_bd_ring_offset[j] =
2904                                 kmalloc((u32) (length + align), GFP_KERNEL);
2905                         if (ugeth->rx_bd_ring_offset[j] != 0)
2906                                 ugeth->p_rx_bd_ring[j] =
2907                                         (void*)((ugeth->rx_bd_ring_offset[j] +
2908                                         align) & ~(align - 1));
2909                 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2910                         ugeth->rx_bd_ring_offset[j] =
2911                             qe_muram_alloc(length,
2912                                            UCC_GETH_RX_BD_RING_ALIGNMENT);
2913                         if (!IS_MURAM_ERR(ugeth->rx_bd_ring_offset[j]))
2914                                 ugeth->p_rx_bd_ring[j] =
2915                                     (u8 *) qe_muram_addr(ugeth->
2916                                                          rx_bd_ring_offset[j]);
2917                 }
2918                 if (!ugeth->p_rx_bd_ring[j]) {
2919                         ugeth_err
2920                             ("%s: Can not allocate memory for Rx bd rings.",
2921                              __FUNCTION__);
2922                         ucc_geth_memclean(ugeth);
2923                         return -ENOMEM;
2924                 }
2925         }
2926
2927         /* Init Tx bds */
2928         for (j = 0; j < ug_info->numQueuesTx; j++) {
2929                 /* Setup the skbuff rings */
2930                 ugeth->tx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2931                                               ugeth->ug_info->bdRingLenTx[j],
2932                                               GFP_KERNEL);
2933
2934                 if (ugeth->tx_skbuff[j] == NULL) {
2935                         ugeth_err("%s: Could not allocate tx_skbuff",
2936                                   __FUNCTION__);
2937                         ucc_geth_memclean(ugeth);
2938                         return -ENOMEM;
2939                 }
2940
2941                 for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++)
2942                         ugeth->tx_skbuff[j][i] = NULL;
2943
2944                 ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0;
2945                 bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j];
2946                 for (i = 0; i < ug_info->bdRingLenTx[j]; i++) {
2947                         /* clear bd buffer */
2948                         out_be32(&((struct qe_bd *)bd)->buf, 0);
2949                         /* set bd status and length */
2950                         out_be32((u32 *)bd, 0);
2951                         bd += sizeof(struct qe_bd);
2952                 }
2953                 bd -= sizeof(struct qe_bd);
2954                 /* set bd status and length */
2955                 out_be32((u32 *)bd, T_W);       /* for last BD set Wrap bit */
2956         }
2957
2958         /* Init Rx bds */
2959         for (j = 0; j < ug_info->numQueuesRx; j++) {
2960                 /* Setup the skbuff rings */
2961                 ugeth->rx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2962                                               ugeth->ug_info->bdRingLenRx[j],
2963                                               GFP_KERNEL);
2964
2965                 if (ugeth->rx_skbuff[j] == NULL) {
2966                         ugeth_err("%s: Could not allocate rx_skbuff",
2967                                   __FUNCTION__);
2968                         ucc_geth_memclean(ugeth);
2969                         return -ENOMEM;
2970                 }
2971
2972                 for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++)
2973                         ugeth->rx_skbuff[j][i] = NULL;
2974
2975                 ugeth->skb_currx[j] = 0;
2976                 bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j];
2977                 for (i = 0; i < ug_info->bdRingLenRx[j]; i++) {
2978                         /* set bd status and length */
2979                         out_be32((u32 *)bd, R_I);
2980                         /* clear bd buffer */
2981                         out_be32(&((struct qe_bd *)bd)->buf, 0);
2982                         bd += sizeof(struct qe_bd);
2983                 }
2984                 bd -= sizeof(struct qe_bd);
2985                 /* set bd status and length */
2986                 out_be32((u32 *)bd, R_W); /* for last BD set Wrap bit */
2987         }
2988
2989         /*
2990          * Global PRAM
2991          */
2992         /* Tx global PRAM */
2993         /* Allocate global tx parameter RAM page */
2994         ugeth->tx_glbl_pram_offset =
2995             qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram),
2996                            UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT);
2997         if (IS_MURAM_ERR(ugeth->tx_glbl_pram_offset)) {
2998                 ugeth_err
2999                     ("%s: Can not allocate DPRAM memory for p_tx_glbl_pram.",
3000                      __FUNCTION__);
3001                 ucc_geth_memclean(ugeth);
3002                 return -ENOMEM;
3003         }
3004         ugeth->p_tx_glbl_pram =
3005             (struct ucc_geth_tx_global_pram *) qe_muram_addr(ugeth->
3006                                                         tx_glbl_pram_offset);
3007         /* Zero out p_tx_glbl_pram */
3008         memset(ugeth->p_tx_glbl_pram, 0, sizeof(struct ucc_geth_tx_global_pram));
3009
3010         /* Fill global PRAM */
3011
3012         /* TQPTR */
3013         /* Size varies with number of Tx threads */
3014         ugeth->thread_dat_tx_offset =
3015             qe_muram_alloc(numThreadsTxNumerical *
3016                            sizeof(struct ucc_geth_thread_data_tx) +
3017                            32 * (numThreadsTxNumerical == 1),
3018                            UCC_GETH_THREAD_DATA_ALIGNMENT);
3019         if (IS_MURAM_ERR(ugeth->thread_dat_tx_offset)) {
3020                 ugeth_err
3021                     ("%s: Can not allocate DPRAM memory for p_thread_data_tx.",
3022                      __FUNCTION__);
3023                 ucc_geth_memclean(ugeth);
3024                 return -ENOMEM;
3025         }
3026
3027         ugeth->p_thread_data_tx =
3028             (struct ucc_geth_thread_data_tx *) qe_muram_addr(ugeth->
3029                                                         thread_dat_tx_offset);
3030         out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset);
3031
3032         /* vtagtable */
3033         for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++)
3034                 out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i],
3035                          ug_info->vtagtable[i]);
3036
3037         /* iphoffset */
3038         for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++)
3039                 ugeth->p_tx_glbl_pram->iphoffset[i] = ug_info->iphoffset[i];
3040
3041         /* SQPTR */
3042         /* Size varies with number of Tx queues */
3043         ugeth->send_q_mem_reg_offset =
3044             qe_muram_alloc(ug_info->numQueuesTx *
3045                            sizeof(struct ucc_geth_send_queue_qd),
3046                            UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
3047         if (IS_MURAM_ERR(ugeth->send_q_mem_reg_offset)) {
3048                 ugeth_err
3049                     ("%s: Can not allocate DPRAM memory for p_send_q_mem_reg.",
3050                      __FUNCTION__);
3051                 ucc_geth_memclean(ugeth);
3052                 return -ENOMEM;
3053         }
3054
3055         ugeth->p_send_q_mem_reg =
3056             (struct ucc_geth_send_queue_mem_region *) qe_muram_addr(ugeth->
3057                         send_q_mem_reg_offset);
3058         out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset);
3059
3060         /* Setup the table */
3061         /* Assume BD rings are already established */
3062         for (i = 0; i < ug_info->numQueuesTx; i++) {
3063                 endOfRing =
3064                     ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] -
3065                                               1) * sizeof(struct qe_bd);
3066                 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
3067                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
3068                                  (u32) virt_to_phys(ugeth->p_tx_bd_ring[i]));
3069                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
3070                                  last_bd_completed_address,
3071                                  (u32) virt_to_phys(endOfRing));
3072                 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
3073                            MEM_PART_MURAM) {
3074                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
3075                                  (u32) immrbar_virt_to_phys(ugeth->
3076                                                             p_tx_bd_ring[i]));
3077                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
3078                                  last_bd_completed_address,
3079                                  (u32) immrbar_virt_to_phys(endOfRing));
3080                 }
3081         }
3082
3083         /* schedulerbasepointer */
3084
3085         if (ug_info->numQueuesTx > 1) {
3086         /* scheduler exists only if more than 1 tx queue */
3087                 ugeth->scheduler_offset =
3088                     qe_muram_alloc(sizeof(struct ucc_geth_scheduler),
3089                                    UCC_GETH_SCHEDULER_ALIGNMENT);
3090                 if (IS_MURAM_ERR(ugeth->scheduler_offset)) {
3091                         ugeth_err
3092                          ("%s: Can not allocate DPRAM memory for p_scheduler.",
3093                              __FUNCTION__);
3094                         ucc_geth_memclean(ugeth);
3095                         return -ENOMEM;
3096                 }
3097
3098                 ugeth->p_scheduler =
3099                     (struct ucc_geth_scheduler *) qe_muram_addr(ugeth->
3100                                                            scheduler_offset);
3101                 out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer,
3102                          ugeth->scheduler_offset);
3103                 /* Zero out p_scheduler */
3104                 memset(ugeth->p_scheduler, 0, sizeof(struct ucc_geth_scheduler));
3105
3106                 /* Set values in scheduler */
3107                 out_be32(&ugeth->p_scheduler->mblinterval,
3108                          ug_info->mblinterval);
3109                 out_be16(&ugeth->p_scheduler->nortsrbytetime,
3110                          ug_info->nortsrbytetime);
3111                 ugeth->p_scheduler->fracsiz = ug_info->fracsiz;
3112                 ugeth->p_scheduler->strictpriorityq = ug_info->strictpriorityq;
3113                 ugeth->p_scheduler->txasap = ug_info->txasap;
3114                 ugeth->p_scheduler->extrabw = ug_info->extrabw;
3115                 for (i = 0; i < NUM_TX_QUEUES; i++)
3116                         ugeth->p_scheduler->weightfactor[i] =
3117                             ug_info->weightfactor[i];
3118
3119                 /* Set pointers to cpucount registers in scheduler */
3120                 ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0);
3121                 ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1);
3122                 ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2);
3123                 ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3);
3124                 ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4);
3125                 ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5);
3126                 ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6);
3127                 ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7);
3128         }
3129
3130         /* schedulerbasepointer */
3131         /* TxRMON_PTR (statistics) */
3132         if (ug_info->
3133             statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) {
3134                 ugeth->tx_fw_statistics_pram_offset =
3135                     qe_muram_alloc(sizeof
3136                                    (struct ucc_geth_tx_firmware_statistics_pram),
3137                                    UCC_GETH_TX_STATISTICS_ALIGNMENT);
3138                 if (IS_MURAM_ERR(ugeth->tx_fw_statistics_pram_offset)) {
3139                         ugeth_err
3140                             ("%s: Can not allocate DPRAM memory for"
3141                                 " p_tx_fw_statistics_pram.", __FUNCTION__);
3142                         ucc_geth_memclean(ugeth);
3143                         return -ENOMEM;
3144                 }
3145                 ugeth->p_tx_fw_statistics_pram =
3146                     (struct ucc_geth_tx_firmware_statistics_pram *)
3147                     qe_muram_addr(ugeth->tx_fw_statistics_pram_offset);
3148                 /* Zero out p_tx_fw_statistics_pram */
3149                 memset(ugeth->p_tx_fw_statistics_pram,
3150                        0, sizeof(struct ucc_geth_tx_firmware_statistics_pram));
3151         }
3152
3153         /* temoder */
3154         /* Already has speed set */
3155
3156         if (ug_info->numQueuesTx > 1)
3157                 temoder |= TEMODER_SCHEDULER_ENABLE;
3158         if (ug_info->ipCheckSumGenerate)
3159                 temoder |= TEMODER_IP_CHECKSUM_GENERATE;
3160         temoder |= ((ug_info->numQueuesTx - 1) << TEMODER_NUM_OF_QUEUES_SHIFT);
3161         out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder);
3162
3163         test = in_be16(&ugeth->p_tx_glbl_pram->temoder);
3164
3165         /* Function code register value to be used later */
3166         function_code = QE_BMR_BYTE_ORDER_BO_MOT | UCC_FAST_FUNCTION_CODE_GBL;
3167         /* Required for QE */
3168
3169         /* function code register */
3170         out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24);
3171
3172         /* Rx global PRAM */
3173         /* Allocate global rx parameter RAM page */
3174         ugeth->rx_glbl_pram_offset =
3175             qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram),
3176                            UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT);
3177         if (IS_MURAM_ERR(ugeth->rx_glbl_pram_offset)) {
3178                 ugeth_err
3179                     ("%s: Can not allocate DPRAM memory for p_rx_glbl_pram.",
3180                      __FUNCTION__);
3181                 ucc_geth_memclean(ugeth);
3182                 return -ENOMEM;
3183         }
3184         ugeth->p_rx_glbl_pram =
3185             (struct ucc_geth_rx_global_pram *) qe_muram_addr(ugeth->
3186                                                         rx_glbl_pram_offset);
3187         /* Zero out p_rx_glbl_pram */
3188         memset(ugeth->p_rx_glbl_pram, 0, sizeof(struct ucc_geth_rx_global_pram));
3189
3190         /* Fill global PRAM */
3191
3192         /* RQPTR */
3193         /* Size varies with number of Rx threads */
3194         ugeth->thread_dat_rx_offset =
3195             qe_muram_alloc(numThreadsRxNumerical *
3196                            sizeof(struct ucc_geth_thread_data_rx),
3197                            UCC_GETH_THREAD_DATA_ALIGNMENT);
3198         if (IS_MURAM_ERR(ugeth->thread_dat_rx_offset)) {
3199                 ugeth_err
3200                     ("%s: Can not allocate DPRAM memory for p_thread_data_rx.",
3201                      __FUNCTION__);
3202                 ucc_geth_memclean(ugeth);
3203                 return -ENOMEM;
3204         }
3205
3206         ugeth->p_thread_data_rx =
3207             (struct ucc_geth_thread_data_rx *) qe_muram_addr(ugeth->
3208                                                         thread_dat_rx_offset);
3209         out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset);
3210
3211         /* typeorlen */
3212         out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen);
3213
3214         /* rxrmonbaseptr (statistics) */
3215         if (ug_info->
3216             statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) {
3217                 ugeth->rx_fw_statistics_pram_offset =
3218                     qe_muram_alloc(sizeof
3219                                    (struct ucc_geth_rx_firmware_statistics_pram),
3220                                    UCC_GETH_RX_STATISTICS_ALIGNMENT);
3221                 if (IS_MURAM_ERR(ugeth->rx_fw_statistics_pram_offset)) {
3222                         ugeth_err
3223                                 ("%s: Can not allocate DPRAM memory for"
3224                                 " p_rx_fw_statistics_pram.", __FUNCTION__);
3225                         ucc_geth_memclean(ugeth);
3226                         return -ENOMEM;
3227                 }
3228                 ugeth->p_rx_fw_statistics_pram =
3229                     (struct ucc_geth_rx_firmware_statistics_pram *)
3230                     qe_muram_addr(ugeth->rx_fw_statistics_pram_offset);
3231                 /* Zero out p_rx_fw_statistics_pram */
3232                 memset(ugeth->p_rx_fw_statistics_pram, 0,
3233                        sizeof(struct ucc_geth_rx_firmware_statistics_pram));
3234         }
3235
3236         /* intCoalescingPtr */
3237
3238         /* Size varies with number of Rx queues */
3239         ugeth->rx_irq_coalescing_tbl_offset =
3240             qe_muram_alloc(ug_info->numQueuesRx *
3241                            sizeof(struct ucc_geth_rx_interrupt_coalescing_entry),
3242                            UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT);
3243         if (IS_MURAM_ERR(ugeth->rx_irq_coalescing_tbl_offset)) {
3244                 ugeth_err
3245                     ("%s: Can not allocate DPRAM memory for"
3246                         " p_rx_irq_coalescing_tbl.", __FUNCTION__);
3247                 ucc_geth_memclean(ugeth);
3248                 return -ENOMEM;
3249         }
3250
3251         ugeth->p_rx_irq_coalescing_tbl =
3252             (struct ucc_geth_rx_interrupt_coalescing_table *)
3253             qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset);
3254         out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr,
3255                  ugeth->rx_irq_coalescing_tbl_offset);
3256
3257         /* Fill interrupt coalescing table */
3258         for (i = 0; i < ug_info->numQueuesRx; i++) {
3259                 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
3260                          interruptcoalescingmaxvalue,
3261                          ug_info->interruptcoalescingmaxvalue[i]);
3262                 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
3263                          interruptcoalescingcounter,
3264                          ug_info->interruptcoalescingmaxvalue[i]);
3265         }
3266
3267         /* MRBLR */
3268         init_max_rx_buff_len(uf_info->max_rx_buf_length,
3269                              &ugeth->p_rx_glbl_pram->mrblr);
3270         /* MFLR */
3271         out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength);
3272         /* MINFLR */
3273         init_min_frame_len(ug_info->minFrameLength,
3274                            &ugeth->p_rx_glbl_pram->minflr,
3275                            &ugeth->p_rx_glbl_pram->mrblr);
3276         /* MAXD1 */
3277         out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length);
3278         /* MAXD2 */
3279         out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length);
3280
3281         /* l2qt */
3282         l2qt = 0;
3283         for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++)
3284                 l2qt |= (ug_info->l2qt[i] << (28 - 4 * i));
3285         out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt);
3286
3287         /* l3qt */
3288         for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) {
3289                 l3qt = 0;
3290                 for (i = 0; i < 8; i++)
3291                         l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i));
3292                 out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt);
3293         }
3294
3295         /* vlantype */
3296         out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype);
3297
3298         /* vlantci */
3299         out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci);
3300
3301         /* ecamptr */
3302         out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr);
3303
3304         /* RBDQPTR */
3305         /* Size varies with number of Rx queues */
3306         ugeth->rx_bd_qs_tbl_offset =
3307             qe_muram_alloc(ug_info->numQueuesRx *
3308                            (sizeof(struct ucc_geth_rx_bd_queues_entry) +
3309                             sizeof(struct ucc_geth_rx_prefetched_bds)),
3310                            UCC_GETH_RX_BD_QUEUES_ALIGNMENT);
3311         if (IS_MURAM_ERR(ugeth->rx_bd_qs_tbl_offset)) {
3312                 ugeth_err
3313                     ("%s: Can not allocate DPRAM memory for p_rx_bd_qs_tbl.",
3314                      __FUNCTION__);
3315                 ucc_geth_memclean(ugeth);
3316                 return -ENOMEM;
3317         }
3318
3319         ugeth->p_rx_bd_qs_tbl =
3320             (struct ucc_geth_rx_bd_queues_entry *) qe_muram_addr(ugeth->
3321                                     rx_bd_qs_tbl_offset);
3322         out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset);
3323         /* Zero out p_rx_bd_qs_tbl */
3324         memset(ugeth->p_rx_bd_qs_tbl,
3325                0,
3326                ug_info->numQueuesRx * (sizeof(struct ucc_geth_rx_bd_queues_entry) +
3327                                        sizeof(struct ucc_geth_rx_prefetched_bds)));
3328
3329         /* Setup the table */
3330         /* Assume BD rings are already established */
3331         for (i = 0; i < ug_info->numQueuesRx; i++) {
3332                 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
3333                         out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
3334                                  (u32) virt_to_phys(ugeth->p_rx_bd_ring[i]));
3335                 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
3336                            MEM_PART_MURAM) {
3337                         out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
3338                                  (u32) immrbar_virt_to_phys(ugeth->
3339                                                             p_rx_bd_ring[i]));
3340                 }
3341                 /* rest of fields handled by QE */
3342         }
3343
3344         /* remoder */
3345         /* Already has speed set */
3346
3347         if (ugeth->rx_extended_features)
3348                 remoder |= REMODER_RX_EXTENDED_FEATURES;
3349         if (ug_info->rxExtendedFiltering)
3350                 remoder |= REMODER_RX_EXTENDED_FILTERING;
3351         if (ug_info->dynamicMaxFrameLength)
3352                 remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH;
3353         if (ug_info->dynamicMinFrameLength)
3354                 remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH;
3355         remoder |=
3356             ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT;
3357         remoder |=
3358             ug_info->
3359             vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT;
3360         remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT;
3361         remoder |= ((ug_info->numQueuesRx - 1) << REMODER_NUM_OF_QUEUES_SHIFT);
3362         if (ug_info->ipCheckSumCheck)
3363                 remoder |= REMODER_IP_CHECKSUM_CHECK;
3364         if (ug_info->ipAddressAlignment)
3365                 remoder |= REMODER_IP_ADDRESS_ALIGNMENT;
3366         out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder);
3367
3368         /* Note that this function must be called */
3369         /* ONLY AFTER p_tx_fw_statistics_pram */
3370         /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */
3371         init_firmware_statistics_gathering_mode((ug_info->
3372                 statisticsMode &
3373                 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX),
3374                 (ug_info->statisticsMode &
3375                 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX),
3376                 &ugeth->p_tx_glbl_pram->txrmonbaseptr,
3377                 ugeth->tx_fw_statistics_pram_offset,
3378                 &ugeth->p_rx_glbl_pram->rxrmonbaseptr,
3379                 ugeth->rx_fw_statistics_pram_offset,
3380                 &ugeth->p_tx_glbl_pram->temoder,
3381                 &ugeth->p_rx_glbl_pram->remoder);
3382
3383         /* function code register */
3384         ugeth->p_rx_glbl_pram->rstate = function_code;
3385
3386         /* initialize extended filtering */
3387         if (ug_info->rxExtendedFiltering) {
3388                 if (!ug_info->extendedFilteringChainPointer) {
3389                         ugeth_err("%s: Null Extended Filtering Chain Pointer.",
3390                                   __FUNCTION__);
3391                         ucc_geth_memclean(ugeth);
3392                         return -EINVAL;
3393                 }
3394
3395                 /* Allocate memory for extended filtering Mode Global
3396                 Parameters */
3397                 ugeth->exf_glbl_param_offset =
3398                     qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram),
3399                 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT);
3400                 if (IS_MURAM_ERR(ugeth->exf_glbl_param_offset)) {
3401                         ugeth_err
3402                                 ("%s: Can not allocate DPRAM memory for"
3403                                 " p_exf_glbl_param.", __FUNCTION__);
3404                         ucc_geth_memclean(ugeth);
3405                         return -ENOMEM;
3406                 }
3407
3408                 ugeth->p_exf_glbl_param =
3409                     (struct ucc_geth_exf_global_pram *) qe_muram_addr(ugeth->
3410                                  exf_glbl_param_offset);
3411                 out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam,
3412                          ugeth->exf_glbl_param_offset);
3413                 out_be32(&ugeth->p_exf_glbl_param->l2pcdptr,
3414                          (u32) ug_info->extendedFilteringChainPointer);
3415
3416         } else {                /* initialize 82xx style address filtering */
3417
3418                 /* Init individual address recognition registers to disabled */
3419
3420                 for (j = 0; j < NUM_OF_PADDRS; j++)
3421                         ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j);
3422
3423                 /* Create CQs for hash tables */
3424                 if (ug_info->maxGroupAddrInHash > 0) {
3425                         INIT_LIST_HEAD(&ugeth->group_hash_q);
3426                 }
3427                 if (ug_info->maxIndAddrInHash > 0) {
3428                         INIT_LIST_HEAD(&ugeth->ind_hash_q);
3429                 }
3430                 p_82xx_addr_filt =
3431                     (struct ucc_geth_82xx_address_filtering_pram *) ugeth->
3432                     p_rx_glbl_pram->addressfiltering;
3433
3434                 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
3435                         ENET_ADDR_TYPE_GROUP);
3436                 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
3437                         ENET_ADDR_TYPE_INDIVIDUAL);
3438         }
3439
3440         /*
3441          * Initialize UCC at QE level
3442          */
3443
3444         command = QE_INIT_TX_RX;
3445
3446         /* Allocate shadow InitEnet command parameter structure.
3447          * This is needed because after the InitEnet command is executed,
3448          * the structure in DPRAM is released, because DPRAM is a premium
3449          * resource.
3450          * This shadow structure keeps a copy of what was done so that the
3451          * allocated resources can be released when the channel is freed.
3452          */
3453         if (!(ugeth->p_init_enet_param_shadow =
3454               kmalloc(sizeof(struct ucc_geth_init_pram), GFP_KERNEL))) {
3455                 ugeth_err
3456                     ("%s: Can not allocate memory for"
3457                         " p_UccInitEnetParamShadows.", __FUNCTION__);
3458                 ucc_geth_memclean(ugeth);
3459                 return -ENOMEM;
3460         }
3461         /* Zero out *p_init_enet_param_shadow */
3462         memset((char *)ugeth->p_init_enet_param_shadow,
3463                0, sizeof(struct ucc_geth_init_pram));
3464
3465         /* Fill shadow InitEnet command parameter structure */
3466
3467         ugeth->p_init_enet_param_shadow->resinit1 =
3468             ENET_INIT_PARAM_MAGIC_RES_INIT1;
3469         ugeth->p_init_enet_param_shadow->resinit2 =
3470             ENET_INIT_PARAM_MAGIC_RES_INIT2;
3471         ugeth->p_init_enet_param_shadow->resinit3 =
3472             ENET_INIT_PARAM_MAGIC_RES_INIT3;
3473         ugeth->p_init_enet_param_shadow->resinit4 =
3474             ENET_INIT_PARAM_MAGIC_RES_INIT4;
3475         ugeth->p_init_enet_param_shadow->resinit5 =
3476             ENET_INIT_PARAM_MAGIC_RES_INIT5;
3477         ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
3478             ((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT;
3479         ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
3480             ((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT;
3481
3482         ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
3483             ugeth->rx_glbl_pram_offset | ug_info->riscRx;
3484         if ((ug_info->largestexternallookupkeysize !=
3485              QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE)
3486             && (ug_info->largestexternallookupkeysize !=
3487                 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
3488             && (ug_info->largestexternallookupkeysize !=
3489                 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)) {
3490                 ugeth_err("%s: Invalid largest External Lookup Key Size.",
3491                           __FUNCTION__);
3492                 ucc_geth_memclean(ugeth);
3493                 return -EINVAL;
3494         }
3495         ugeth->p_init_enet_param_shadow->largestexternallookupkeysize =
3496             ug_info->largestexternallookupkeysize;
3497         size = sizeof(struct ucc_geth_thread_rx_pram);
3498         if (ug_info->rxExtendedFiltering) {
3499                 size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
3500                 if (ug_info->largestexternallookupkeysize ==
3501                     QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
3502                         size +=
3503                             THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
3504                 if (ug_info->largestexternallookupkeysize ==
3505                     QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
3506                         size +=
3507                             THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
3508         }
3509
3510         if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth->
3511                 p_init_enet_param_shadow->rxthread[0]),
3512                 (u8) (numThreadsRxNumerical + 1)
3513                 /* Rx needs one extra for terminator */
3514                 , size, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT,
3515                 ug_info->riscRx, 1)) != 0) {
3516                         ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
3517                                 __FUNCTION__);
3518                 ucc_geth_memclean(ugeth);
3519                 return ret_val;
3520         }
3521
3522         ugeth->p_init_enet_param_shadow->txglobal =
3523             ugeth->tx_glbl_pram_offset | ug_info->riscTx;
3524         if ((ret_val =
3525              fill_init_enet_entries(ugeth,
3526                                     &(ugeth->p_init_enet_param_shadow->
3527                                       txthread[0]), numThreadsTxNumerical,
3528                                     sizeof(struct ucc_geth_thread_tx_pram),
3529                                     UCC_GETH_THREAD_TX_PRAM_ALIGNMENT,
3530                                     ug_info->riscTx, 0)) != 0) {
3531                 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
3532                           __FUNCTION__);
3533                 ucc_geth_memclean(ugeth);
3534                 return ret_val;
3535         }
3536
3537         /* Load Rx bds with buffers */
3538         for (i = 0; i < ug_info->numQueuesRx; i++) {
3539                 if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) {
3540                         ugeth_err("%s: Can not fill Rx bds with buffers.",
3541                                   __FUNCTION__);
3542                         ucc_geth_memclean(ugeth);
3543                         return ret_val;
3544                 }
3545         }
3546
3547         /* Allocate InitEnet command parameter structure */
3548         init_enet_pram_offset = qe_muram_alloc(sizeof(struct ucc_geth_init_pram), 4);
3549         if (IS_MURAM_ERR(init_enet_pram_offset)) {
3550                 ugeth_err
3551                     ("%s: Can not allocate DPRAM memory for p_init_enet_pram.",
3552                      __FUNCTION__);
3553                 ucc_geth_memclean(ugeth);
3554                 return -ENOMEM;
3555         }
3556         p_init_enet_pram =
3557             (struct ucc_geth_init_pram *) qe_muram_addr(init_enet_pram_offset);
3558
3559         /* Copy shadow InitEnet command parameter structure into PRAM */
3560         p_init_enet_pram->resinit1 = ugeth->p_init_enet_param_shadow->resinit1;
3561         p_init_enet_pram->resinit2 = ugeth->p_init_enet_param_shadow->resinit2;
3562         p_init_enet_pram->resinit3 = ugeth->p_init_enet_param_shadow->resinit3;
3563         p_init_enet_pram->resinit4 = ugeth->p_init_enet_param_shadow->resinit4;
3564         out_be16(&p_init_enet_pram->resinit5,
3565                  ugeth->p_init_enet_param_shadow->resinit5);
3566         p_init_enet_pram->largestexternallookupkeysize =
3567             ugeth->p_init_enet_param_shadow->largestexternallookupkeysize;
3568         out_be32(&p_init_enet_pram->rgftgfrxglobal,
3569                  ugeth->p_init_enet_param_shadow->rgftgfrxglobal);
3570         for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_RX; i++)
3571                 out_be32(&p_init_enet_pram->rxthread[i],
3572                          ugeth->p_init_enet_param_shadow->rxthread[i]);
3573         out_be32(&p_init_enet_pram->txglobal,
3574                  ugeth->p_init_enet_param_shadow->txglobal);
3575         for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_TX; i++)
3576                 out_be32(&p_init_enet_pram->txthread[i],
3577                          ugeth->p_init_enet_param_shadow->txthread[i]);
3578
3579         /* Issue QE command */
3580         cecr_subblock =
3581             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
3582         qe_issue_cmd(command, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
3583                      init_enet_pram_offset);
3584
3585         /* Free InitEnet command parameter */
3586         qe_muram_free(init_enet_pram_offset);
3587
3588         return 0;
3589 }
3590
3591 /* returns a net_device_stats structure pointer */
3592 static struct net_device_stats *ucc_geth_get_stats(struct net_device *dev)
3593 {
3594         struct ucc_geth_private *ugeth = netdev_priv(dev);
3595
3596         return &(ugeth->stats);
3597 }
3598
3599 /* ucc_geth_timeout gets called when a packet has not been
3600  * transmitted after a set amount of time.
3601  * For now, assume that clearing out all the structures, and
3602  * starting over will fix the problem. */
3603 static void ucc_geth_timeout(struct net_device *dev)
3604 {
3605         struct ucc_geth_private *ugeth = netdev_priv(dev);
3606
3607         ugeth_vdbg("%s: IN", __FUNCTION__);
3608
3609         ugeth->stats.tx_errors++;
3610
3611         ugeth_dump_regs(ugeth);
3612
3613         if (dev->flags & IFF_UP) {
3614                 ucc_geth_stop(ugeth);
3615                 ucc_geth_startup(ugeth);
3616         }
3617
3618         netif_schedule(dev);
3619 }
3620
3621 /* This is called by the kernel when a frame is ready for transmission. */
3622 /* It is pointed to by the dev->hard_start_xmit function pointer */
3623 static int ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev)
3624 {
3625         struct ucc_geth_private *ugeth = netdev_priv(dev);
3626         u8 *bd;                 /* BD pointer */
3627         u32 bd_status;
3628         u8 txQ = 0;
3629
3630         ugeth_vdbg("%s: IN", __FUNCTION__);
3631
3632         spin_lock_irq(&ugeth->lock);
3633
3634         ugeth->stats.tx_bytes += skb->len;
3635
3636         /* Start from the next BD that should be filled */
3637         bd = ugeth->txBd[txQ];
3638         bd_status = in_be32((u32 *)bd);
3639         /* Save the skb pointer so we can free it later */
3640         ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb;
3641
3642         /* Update the current skb pointer (wrapping if this was the last) */
3643         ugeth->skb_curtx[txQ] =
3644             (ugeth->skb_curtx[txQ] +
3645              1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3646
3647         /* set up the buffer descriptor */
3648         out_be32(&((struct qe_bd *)bd)->buf,
3649                       dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE));
3650
3651         /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */
3652
3653         bd_status = (bd_status & T_W) | T_R | T_I | T_L | skb->len;
3654
3655         /* set bd status and length */
3656         out_be32((u32 *)bd, bd_status);
3657
3658         dev->trans_start = jiffies;
3659
3660         /* Move to next BD in the ring */
3661         if (!(bd_status & T_W))
3662                 ugeth->txBd[txQ] = bd + sizeof(struct qe_bd);
3663         else
3664                 ugeth->txBd[txQ] = ugeth->p_tx_bd_ring[txQ];
3665
3666         /* If the next BD still needs to be cleaned up, then the bds
3667            are full.  We need to tell the kernel to stop sending us stuff. */
3668         if (bd == ugeth->confBd[txQ]) {
3669                 if (!netif_queue_stopped(dev))
3670                         netif_stop_queue(dev);
3671         }
3672
3673         if (ugeth->p_scheduler) {
3674                 ugeth->cpucount[txQ]++;
3675                 /* Indicate to QE that there are more Tx bds ready for
3676                 transmission */
3677                 /* This is done by writing a running counter of the bd
3678                 count to the scheduler PRAM. */
3679                 out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]);
3680         }
3681
3682         spin_unlock_irq(&ugeth->lock);
3683
3684         return 0;
3685 }
3686
3687 static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit)
3688 {
3689         struct sk_buff *skb;
3690         u8 *bd;
3691         u16 length, howmany = 0;
3692         u32 bd_status;
3693         u8 *bdBuffer;
3694
3695         ugeth_vdbg("%s: IN", __FUNCTION__);
3696
3697         spin_lock(&ugeth->lock);
3698         /* collect received buffers */
3699         bd = ugeth->rxBd[rxQ];
3700
3701         bd_status = in_be32((u32 *)bd);
3702
3703         /* while there are received buffers and BD is full (~R_E) */
3704         while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) {
3705                 bdBuffer = (u8 *) in_be32(&((struct qe_bd *)bd)->buf);
3706                 length = (u16) ((bd_status & BD_LENGTH_MASK) - 4);
3707                 skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]];
3708
3709                 /* determine whether buffer is first, last, first and last
3710                 (single buffer frame) or middle (not first and not last) */
3711                 if (!skb ||
3712                     (!(bd_status & (R_F | R_L))) ||
3713                     (bd_status & R_ERRORS_FATAL)) {
3714                         ugeth_vdbg("%s, %d: ERROR!!! skb - 0x%08x",
3715                                    __FUNCTION__, __LINE__, (u32) skb);
3716                         if (skb)
3717                                 dev_kfree_skb_any(skb);
3718
3719                         ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL;
3720                         ugeth->stats.rx_dropped++;
3721                 } else {
3722                         ugeth->stats.rx_packets++;
3723                         howmany++;
3724
3725                         /* Prep the skb for the packet */
3726                         skb_put(skb, length);
3727
3728                         /* Tell the skb what kind of packet this is */
3729                         skb->protocol = eth_type_trans(skb, ugeth->dev);
3730
3731                         ugeth->stats.rx_bytes += length;
3732                         /* Send the packet up the stack */
3733 #ifdef CONFIG_UGETH_NAPI
3734                         netif_receive_skb(skb);
3735 #else
3736                         netif_rx(skb);
3737 #endif                          /* CONFIG_UGETH_NAPI */
3738                 }
3739
3740                 ugeth->dev->last_rx = jiffies;
3741
3742                 skb = get_new_skb(ugeth, bd);
3743                 if (!skb) {
3744                         ugeth_warn("%s: No Rx Data Buffer", __FUNCTION__);
3745                         spin_unlock(&ugeth->lock);
3746                         ugeth->stats.rx_dropped++;
3747                         break;
3748                 }
3749
3750                 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb;
3751
3752                 /* update to point at the next skb */
3753                 ugeth->skb_currx[rxQ] =
3754                     (ugeth->skb_currx[rxQ] +
3755                      1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]);
3756
3757                 if (bd_status & R_W)
3758                         bd = ugeth->p_rx_bd_ring[rxQ];
3759                 else
3760                         bd += sizeof(struct qe_bd);
3761
3762                 bd_status = in_be32((u32 *)bd);
3763         }
3764
3765         ugeth->rxBd[rxQ] = bd;
3766         spin_unlock(&ugeth->lock);
3767         return howmany;
3768 }
3769
3770 static int ucc_geth_tx(struct net_device *dev, u8 txQ)
3771 {
3772         /* Start from the next BD that should be filled */
3773         struct ucc_geth_private *ugeth = netdev_priv(dev);
3774         u8 *bd;                 /* BD pointer */
3775         u32 bd_status;
3776
3777         bd = ugeth->confBd[txQ];
3778         bd_status = in_be32((u32 *)bd);
3779
3780         /* Normal processing. */
3781         while ((bd_status & T_R) == 0) {
3782                 /* BD contains already transmitted buffer.   */
3783                 /* Handle the transmitted buffer and release */
3784                 /* the BD to be used with the current frame  */
3785
3786                 if ((bd = ugeth->txBd[txQ]) && (netif_queue_stopped(dev) == 0))
3787                         break;
3788
3789                 ugeth->stats.tx_packets++;
3790
3791                 /* Free the sk buffer associated with this TxBD */
3792                 dev_kfree_skb_irq(ugeth->
3793                                   tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]]);
3794                 ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL;
3795                 ugeth->skb_dirtytx[txQ] =
3796                     (ugeth->skb_dirtytx[txQ] +
3797                      1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3798
3799                 /* We freed a buffer, so now we can restart transmission */
3800                 if (netif_queue_stopped(dev))
3801                         netif_wake_queue(dev);
3802
3803                 /* Advance the confirmation BD pointer */
3804                 if (!(bd_status & T_W))
3805                         ugeth->confBd[txQ] += sizeof(struct qe_bd);
3806                 else
3807                         ugeth->confBd[txQ] = ugeth->p_tx_bd_ring[txQ];
3808         }
3809         return 0;
3810 }
3811
3812 #ifdef CONFIG_UGETH_NAPI
3813 static int ucc_geth_poll(struct net_device *dev, int *budget)
3814 {
3815         struct ucc_geth_private *ugeth = netdev_priv(dev);
3816         int howmany;
3817         int rx_work_limit = *budget;
3818         u8 rxQ = 0;
3819
3820         if (rx_work_limit > dev->quota)
3821                 rx_work_limit = dev->quota;
3822
3823         howmany = ucc_geth_rx(ugeth, rxQ, rx_work_limit);
3824
3825         dev->quota -= howmany;
3826         rx_work_limit -= howmany;
3827         *budget -= howmany;
3828
3829         if (rx_work_limit >= 0)
3830                 netif_rx_complete(dev);
3831
3832         return (rx_work_limit < 0) ? 1 : 0;
3833 }
3834 #endif                          /* CONFIG_UGETH_NAPI */
3835
3836 static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
3837 {
3838         struct net_device *dev = (struct net_device *)info;
3839         struct ucc_geth_private *ugeth = netdev_priv(dev);
3840         struct ucc_fast_private *uccf;
3841         struct ucc_geth_info *ug_info;
3842         register u32 ucce = 0;
3843         register u32 bit_mask = UCCE_RXBF_SINGLE_MASK;
3844         register u32 tx_mask = UCCE_TXBF_SINGLE_MASK;
3845         register u8 i;
3846
3847         ugeth_vdbg("%s: IN", __FUNCTION__);
3848
3849         if (!ugeth)
3850                 return IRQ_NONE;
3851
3852         uccf = ugeth->uccf;
3853         ug_info = ugeth->ug_info;
3854
3855         do {
3856                 ucce |= (u32) (in_be32(uccf->p_ucce) & in_be32(uccf->p_uccm));
3857
3858                 /* clear event bits for next time */
3859                 /* Side effect here is to mask ucce variable
3860                 for future processing below. */
3861                 out_be32(uccf->p_ucce, ucce);   /* Clear with ones,
3862                                                 but only bits in UCCM */
3863
3864                 /* We ignore Tx interrupts because Tx confirmation is
3865                 done inside Tx routine */
3866
3867                 for (i = 0; i < ug_info->numQueuesRx; i++) {
3868                         if (ucce & bit_mask)
3869                                 ucc_geth_rx(ugeth, i,
3870                                             (int)ugeth->ug_info->
3871                                             bdRingLenRx[i]);
3872                         ucce &= ~bit_mask;
3873                         bit_mask <<= 1;
3874                 }
3875
3876                 for (i = 0; i < ug_info->numQueuesTx; i++) {
3877                         if (ucce & tx_mask)
3878                                 ucc_geth_tx(dev, i);
3879                         ucce &= ~tx_mask;
3880                         tx_mask <<= 1;
3881                 }
3882
3883                 /* Exceptions */
3884                 if (ucce & UCCE_BSY) {
3885                         ugeth_vdbg("Got BUSY irq!!!!");
3886                         ugeth->stats.rx_errors++;
3887                         ucce &= ~UCCE_BSY;
3888                 }
3889                 if (ucce & UCCE_OTHER) {
3890                         ugeth_vdbg("Got frame with error (ucce - 0x%08x)!!!!",
3891                                    ucce);
3892                         ugeth->stats.rx_errors++;
3893                         ucce &= ~ucce;
3894                 }
3895         }
3896         while (ucce);
3897
3898         return IRQ_HANDLED;
3899 }
3900
3901 static irqreturn_t phy_interrupt(int irq, void *dev_id)
3902 {
3903         struct net_device *dev = (struct net_device *)dev_id;
3904         struct ucc_geth_private *ugeth = netdev_priv(dev);
3905
3906         ugeth_vdbg("%s: IN", __FUNCTION__);
3907
3908         /* Clear the interrupt */
3909         mii_clear_phy_interrupt(ugeth->mii_info);
3910
3911         /* Disable PHY interrupts */
3912         mii_configure_phy_interrupt(ugeth->mii_info, MII_INTERRUPT_DISABLED);
3913
3914         /* Schedule the phy change */
3915         schedule_work(&ugeth->tq);
3916
3917         return IRQ_HANDLED;
3918 }
3919
3920 /* Scheduled by the phy_interrupt/timer to handle PHY changes */
3921 static void ugeth_phy_change(struct work_struct *work)
3922 {
3923         struct ucc_geth_private *ugeth =
3924                 container_of(work, struct ucc_geth_private, tq);
3925         struct net_device *dev = ugeth->dev;
3926         struct ucc_geth *ug_regs;
3927         int result = 0;
3928
3929         ugeth_vdbg("%s: IN", __FUNCTION__);
3930
3931         ug_regs = ugeth->ug_regs;
3932
3933         /* Delay to give the PHY a chance to change the
3934          * register state */
3935         msleep(1);
3936
3937         /* Update the link, speed, duplex */
3938         result = ugeth->mii_info->phyinfo->read_status(ugeth->mii_info);
3939
3940         /* Adjust the known status as long as the link
3941          * isn't still coming up */
3942         if ((0 == result) || (ugeth->mii_info->link == 0))
3943                 adjust_link(dev);
3944
3945         /* Reenable interrupts, if needed */
3946         if (ugeth->ug_info->board_flags & FSL_UGETH_BRD_HAS_PHY_INTR)
3947                 mii_configure_phy_interrupt(ugeth->mii_info,
3948                                             MII_INTERRUPT_ENABLED);
3949 }
3950
3951 /* Called every so often on systems that don't interrupt
3952  * the core for PHY changes */
3953 static void ugeth_phy_timer(unsigned long data)
3954 {
3955         struct net_device *dev = (struct net_device *)data;
3956         struct ucc_geth_private *ugeth = netdev_priv(dev);
3957
3958         schedule_work(&ugeth->tq);
3959
3960         mod_timer(&ugeth->phy_info_timer, jiffies + PHY_CHANGE_TIME * HZ);
3961 }
3962
3963 /* Keep trying aneg for some time
3964  * If, after GFAR_AN_TIMEOUT seconds, it has not
3965  * finished, we switch to forced.
3966  * Either way, once the process has completed, we either
3967  * request the interrupt, or switch the timer over to
3968  * using ugeth_phy_timer to check status */
3969 static void ugeth_phy_startup_timer(unsigned long data)
3970 {
3971         struct ugeth_mii_info *mii_info = (struct ugeth_mii_info *)data;
3972         struct ucc_geth_private *ugeth = netdev_priv(mii_info->dev);
3973         static int secondary = UGETH_AN_TIMEOUT;
3974         int result;
3975
3976         /* Configure the Auto-negotiation */
3977         result = mii_info->phyinfo->config_aneg(mii_info);
3978
3979         /* If autonegotiation failed to start, and
3980          * we haven't timed out, reset the timer, and return */
3981         if (result && secondary--) {
3982                 mod_timer(&ugeth->phy_info_timer, jiffies + HZ);
3983                 return;
3984         } else if (result) {
3985                 /* Couldn't start autonegotiation.
3986                  * Try switching to forced */
3987                 mii_info->autoneg = 0;
3988                 result = mii_info->phyinfo->config_aneg(mii_info);
3989
3990                 /* Forcing failed!  Give up */
3991                 if (result) {
3992                         ugeth_err("%s: Forcing failed!", mii_info->dev->name);
3993                         return;
3994                 }
3995         }
3996
3997         /* Kill the timer so it can be restarted */
3998         del_timer_sync(&ugeth->phy_info_timer);
3999
4000         /* Grab the PHY interrupt, if necessary/possible */
4001         if (ugeth->ug_info->board_flags & FSL_UGETH_BRD_HAS_PHY_INTR) {
4002                 if (request_irq(ugeth->ug_info->phy_interrupt,
4003                                 phy_interrupt,
4004                                 SA_SHIRQ, "phy_interrupt", mii_info->dev) < 0) {
4005                         ugeth_err("%s: Can't get IRQ %d (PHY)",
4006                                   mii_info->dev->name,
4007                                   ugeth->ug_info->phy_interrupt);
4008                 } else {
4009                         mii_configure_phy_interrupt(ugeth->mii_info,
4010                                                     MII_INTERRUPT_ENABLED);
4011                         return;
4012                 }
4013         }
4014
4015         /* Start the timer again, this time in order to
4016          * handle a change in status */
4017         init_timer(&ugeth->phy_info_timer);
4018         ugeth->phy_info_timer.function = &ugeth_phy_timer;
4019         ugeth->phy_info_timer.data = (unsigned long)mii_info->dev;
4020         mod_timer(&ugeth->phy_info_timer, jiffies + PHY_CHANGE_TIME * HZ);
4021 }
4022
4023 /* Called when something needs to use the ethernet device */
4024 /* Returns 0 for success. */
4025 static int ucc_geth_open(struct net_device *dev)
4026 {
4027         struct ucc_geth_private *ugeth = netdev_priv(dev);
4028         int err;
4029
4030         ugeth_vdbg("%s: IN", __FUNCTION__);
4031
4032         /* Test station address */
4033         if (dev->dev_addr[0] & ENET_GROUP_ADDR) {
4034                 ugeth_err("%s: Multicast address used for station address"
4035                           " - is this what you wanted?", __FUNCTION__);
4036                 return -EINVAL;
4037         }
4038
4039         err = ucc_geth_startup(ugeth);
4040         if (err) {
4041                 ugeth_err("%s: Cannot configure net device, aborting.",
4042                           dev->name);
4043                 return err;
4044         }
4045
4046         err = adjust_enet_interface(ugeth);
4047         if (err) {
4048                 ugeth_err("%s: Cannot configure net device, aborting.",
4049                           dev->name);
4050                 return err;
4051         }
4052
4053         /*       Set MACSTNADDR1, MACSTNADDR2                */
4054         /* For more details see the hardware spec.           */
4055         init_mac_station_addr_regs(dev->dev_addr[0],
4056                                    dev->dev_addr[1],
4057                                    dev->dev_addr[2],
4058                                    dev->dev_addr[3],
4059                                    dev->dev_addr[4],
4060                                    dev->dev_addr[5],
4061                                    &ugeth->ug_regs->macstnaddr1,
4062                                    &ugeth->ug_regs->macstnaddr2);
4063
4064         err = init_phy(dev);
4065         if (err) {
4066                 ugeth_err("%s: Cannot initialzie PHY, aborting.", dev->name);
4067                 return err;
4068         }
4069 #ifndef CONFIG_UGETH_NAPI
4070         err =
4071             request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler, 0,
4072                         "UCC Geth", dev);
4073         if (err) {
4074                 ugeth_err("%s: Cannot get IRQ for net device, aborting.",
4075                           dev->name);
4076                 ucc_geth_stop(ugeth);
4077                 return err;
4078         }
4079 #endif                          /* CONFIG_UGETH_NAPI */
4080
4081         /* Set up the PHY change work queue */
4082         INIT_WORK(&ugeth->tq, ugeth_phy_change);
4083
4084         init_timer(&ugeth->phy_info_timer);
4085         ugeth->phy_info_timer.function = &ugeth_phy_startup_timer;
4086         ugeth->phy_info_timer.data = (unsigned long)ugeth->mii_info;
4087         mod_timer(&ugeth->phy_info_timer, jiffies + HZ);
4088
4089         err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
4090         if (err) {
4091                 ugeth_err("%s: Cannot enable net device, aborting.", dev->name);
4092                 ucc_geth_stop(ugeth);
4093                 return err;
4094         }
4095
4096         netif_start_queue(dev);
4097
4098         return err;
4099 }
4100
4101 /* Stops the kernel queue, and halts the controller */
4102 static int ucc_geth_close(struct net_device *dev)
4103 {
4104         struct ucc_geth_private *ugeth = netdev_priv(dev);
4105
4106         ugeth_vdbg("%s: IN", __FUNCTION__);
4107
4108         ucc_geth_stop(ugeth);
4109
4110         /* Shutdown the PHY */
4111         if (ugeth->mii_info->phyinfo->close)
4112                 ugeth->mii_info->phyinfo->close(ugeth->mii_info);
4113
4114         kfree(ugeth->mii_info);
4115
4116         netif_stop_queue(dev);
4117
4118         return 0;
4119 }
4120
4121 const struct ethtool_ops ucc_geth_ethtool_ops = { };
4122
4123 static int ucc_geth_probe(struct of_device* ofdev, const struct of_device_id *match)
4124 {
4125         struct device *device = &ofdev->dev;
4126         struct device_node *np = ofdev->node;
4127         struct net_device *dev = NULL;
4128         struct ucc_geth_private *ugeth = NULL;
4129         struct ucc_geth_info *ug_info;
4130         struct resource res;
4131         struct device_node *phy;
4132         int err, ucc_num, phy_interface;
4133         static int mii_mng_configured = 0;
4134         const phandle *ph;
4135         const unsigned int *prop;
4136
4137         ugeth_vdbg("%s: IN", __FUNCTION__);
4138
4139         prop = get_property(np, "device-id", NULL);
4140         ucc_num = *prop - 1;
4141         if ((ucc_num < 0) || (ucc_num > 7))
4142                 return -ENODEV;
4143
4144         ug_info = &ugeth_info[ucc_num];
4145         ug_info->uf_info.ucc_num = ucc_num;
4146         prop = get_property(np, "rx-clock", NULL);
4147         ug_info->uf_info.rx_clock = *prop;
4148         prop = get_property(np, "tx-clock", NULL);
4149         ug_info->uf_info.tx_clock = *prop;
4150         err = of_address_to_resource(np, 0, &res);
4151         if (err)
4152                 return -EINVAL;
4153
4154         ug_info->uf_info.regs = res.start;
4155         ug_info->uf_info.irq = irq_of_parse_and_map(np, 0);
4156
4157         ph = get_property(np, "phy-handle", NULL);
4158         phy = of_find_node_by_phandle(*ph);
4159
4160         if (phy == NULL)
4161                 return -ENODEV;
4162
4163         prop = get_property(phy, "reg", NULL);
4164         ug_info->phy_address = *prop;
4165         prop = get_property(phy, "interface", NULL);
4166         ug_info->enet_interface = *prop;
4167         ug_info->phy_interrupt = irq_of_parse_and_map(phy, 0);
4168         ug_info->board_flags = (ug_info->phy_interrupt == NO_IRQ)?
4169                         0:FSL_UGETH_BRD_HAS_PHY_INTR;
4170
4171         printk(KERN_INFO "ucc_geth: UCC%1d at 0x%8x (irq = %d) \n",
4172                 ug_info->uf_info.ucc_num + 1, ug_info->uf_info.regs,
4173                 ug_info->uf_info.irq);
4174
4175         if (ug_info == NULL) {
4176                 ugeth_err("%s: [%d] Missing additional data!", __FUNCTION__,
4177                           ucc_num);
4178                 return -ENODEV;
4179         }
4180
4181         /* FIXME: Work around for early chip rev.               */
4182         /* There's a bug in initial chip rev(s) in the RGMII ac */
4183         /* timing.                                              */
4184         /* The following compensates by writing to the reserved */
4185         /* QE Port Output Hold Registers (CPOH1?).              */
4186         prop = get_property(phy, "interface", NULL);
4187         phy_interface = *prop;
4188         if ((phy_interface == ENET_1000_RGMII) ||
4189                         (phy_interface == ENET_100_RGMII) ||
4190                         (phy_interface == ENET_10_RGMII)) {
4191                 struct device_node *soc;
4192                 phys_addr_t immrbase = -1;
4193                 u32 *tmp_reg;
4194                 u32 tmp_val;
4195
4196                 soc = of_find_node_by_type(NULL, "soc");
4197                 if (soc) {
4198                         unsigned int size;
4199                         const void *prop = get_property(soc, "reg", &size);
4200                         immrbase = of_translate_address(soc, prop);
4201                         of_node_put(soc);
4202                 };
4203
4204                 tmp_reg = (u32 *) ioremap(immrbase + 0x14A8, 0x4);
4205                 tmp_val = in_be32(tmp_reg);
4206                 if (ucc_num == 1)
4207                         out_be32(tmp_reg, tmp_val | 0x00003000);
4208                 else if (ucc_num == 2)
4209                         out_be32(tmp_reg, tmp_val | 0x0c000000);
4210                 iounmap(tmp_reg);
4211         }
4212
4213         if (!mii_mng_configured) {
4214                 ucc_set_qe_mux_mii_mng(ucc_num);
4215                 mii_mng_configured = 1;
4216         }
4217
4218         /* Create an ethernet device instance */
4219         dev = alloc_etherdev(sizeof(*ugeth));
4220
4221         if (dev == NULL)
4222                 return -ENOMEM;
4223
4224         ugeth = netdev_priv(dev);
4225         spin_lock_init(&ugeth->lock);
4226
4227         dev_set_drvdata(device, dev);
4228
4229         /* Set the dev->base_addr to the gfar reg region */
4230         dev->base_addr = (unsigned long)(ug_info->uf_info.regs);
4231
4232         SET_MODULE_OWNER(dev);
4233         SET_NETDEV_DEV(dev, device);
4234
4235         /* Fill in the dev structure */
4236         dev->open = ucc_geth_open;
4237         dev->hard_start_xmit = ucc_geth_start_xmit;
4238         dev->tx_timeout = ucc_geth_timeout;
4239         dev->watchdog_timeo = TX_TIMEOUT;
4240 #ifdef CONFIG_UGETH_NAPI
4241         dev->poll = ucc_geth_poll;
4242         dev->weight = UCC_GETH_DEV_WEIGHT;
4243 #endif                          /* CONFIG_UGETH_NAPI */
4244         dev->stop = ucc_geth_close;
4245         dev->get_stats = ucc_geth_get_stats;
4246 //    dev->change_mtu = ucc_geth_change_mtu;
4247         dev->mtu = 1500;
4248         dev->set_multicast_list = ucc_geth_set_multi;
4249         dev->ethtool_ops = &ucc_geth_ethtool_ops;
4250
4251         err = register_netdev(dev);
4252         if (err) {
4253                 ugeth_err("%s: Cannot register net device, aborting.",
4254                           dev->name);
4255                 free_netdev(dev);
4256                 return err;
4257         }
4258
4259         ugeth->ug_info = ug_info;
4260         ugeth->dev = dev;
4261         memcpy(dev->dev_addr, get_property(np, "mac-address", NULL), 6);
4262
4263         return 0;
4264 }
4265
4266 static int ucc_geth_remove(struct of_device* ofdev)
4267 {
4268         struct device *device = &ofdev->dev;
4269         struct net_device *dev = dev_get_drvdata(device);
4270         struct ucc_geth_private *ugeth = netdev_priv(dev);
4271
4272         dev_set_drvdata(device, NULL);
4273         ucc_geth_memclean(ugeth);
4274         free_netdev(dev);
4275
4276         return 0;
4277 }
4278
4279 static struct of_device_id ucc_geth_match[] = {
4280         {
4281                 .type = "network",
4282                 .compatible = "ucc_geth",
4283         },
4284         {},
4285 };
4286
4287 MODULE_DEVICE_TABLE(of, ucc_geth_match);
4288
4289 static struct of_platform_driver ucc_geth_driver = {
4290         .name           = DRV_NAME,
4291         .match_table    = ucc_geth_match,
4292         .probe          = ucc_geth_probe,
4293         .remove         = ucc_geth_remove,
4294 };
4295
4296 static int __init ucc_geth_init(void)
4297 {
4298         int i;
4299
4300         printk(KERN_INFO "ucc_geth: " DRV_DESC "\n");
4301         for (i = 0; i < 8; i++)
4302                 memcpy(&(ugeth_info[i]), &ugeth_primary_info,
4303                        sizeof(ugeth_primary_info));
4304
4305         return of_register_platform_driver(&ucc_geth_driver);
4306 }
4307
4308 static void __exit ucc_geth_exit(void)
4309 {
4310         of_unregister_platform_driver(&ucc_geth_driver);
4311 }
4312
4313 module_init(ucc_geth_init);
4314 module_exit(ucc_geth_exit);
4315
4316 MODULE_AUTHOR("Freescale Semiconductor, Inc");
4317 MODULE_DESCRIPTION(DRV_DESC);
4318 MODULE_LICENSE("GPL");