6750de10a087de4dcc76099868028e0786a51a88
[linux-2.6.git] / drivers / net / ucc_geth.c
1 /*
2  * Copyright (C) 2006-2009 Freescale Semicondutor, Inc. All rights reserved.
3  *
4  * Author: Shlomi Gridish <gridish@freescale.com>
5  *         Li Yang <leoli@freescale.com>
6  *
7  * Description:
8  * QE UCC Gigabit Ethernet Driver
9  *
10  * This program is free software; you can redistribute  it and/or modify it
11  * under  the terms of  the GNU General  Public License as published by the
12  * Free Software Foundation;  either version 2 of the  License, or (at your
13  * option) any later version.
14  */
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/slab.h>
19 #include <linux/stddef.h>
20 #include <linux/interrupt.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/skbuff.h>
24 #include <linux/spinlock.h>
25 #include <linux/mm.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/mii.h>
28 #include <linux/phy.h>
29 #include <linux/workqueue.h>
30 #include <linux/of_mdio.h>
31 #include <linux/of_platform.h>
32
33 #include <asm/uaccess.h>
34 #include <asm/irq.h>
35 #include <asm/io.h>
36 #include <asm/immap_qe.h>
37 #include <asm/qe.h>
38 #include <asm/ucc.h>
39 #include <asm/ucc_fast.h>
40 #include <asm/machdep.h>
41
42 #include "ucc_geth.h"
43 #include "fsl_pq_mdio.h"
44
45 #undef DEBUG
46
47 #define ugeth_printk(level, format, arg...)  \
48         printk(level format "\n", ## arg)
49
50 #define ugeth_dbg(format, arg...)            \
51         ugeth_printk(KERN_DEBUG , format , ## arg)
52 #define ugeth_err(format, arg...)            \
53         ugeth_printk(KERN_ERR , format , ## arg)
54 #define ugeth_info(format, arg...)           \
55         ugeth_printk(KERN_INFO , format , ## arg)
56 #define ugeth_warn(format, arg...)           \
57         ugeth_printk(KERN_WARNING , format , ## arg)
58
59 #ifdef UGETH_VERBOSE_DEBUG
60 #define ugeth_vdbg ugeth_dbg
61 #else
62 #define ugeth_vdbg(fmt, args...) do { } while (0)
63 #endif                          /* UGETH_VERBOSE_DEBUG */
64 #define UGETH_MSG_DEFAULT       (NETIF_MSG_IFUP << 1 ) - 1
65
66
67 static DEFINE_SPINLOCK(ugeth_lock);
68
69 static struct {
70         u32 msg_enable;
71 } debug = { -1 };
72
73 module_param_named(debug, debug.msg_enable, int, 0);
74 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 0xffff=all)");
75
76 static struct ucc_geth_info ugeth_primary_info = {
77         .uf_info = {
78                     .bd_mem_part = MEM_PART_SYSTEM,
79                     .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES,
80                     .max_rx_buf_length = 1536,
81                     /* adjusted at startup if max-speed 1000 */
82                     .urfs = UCC_GETH_URFS_INIT,
83                     .urfet = UCC_GETH_URFET_INIT,
84                     .urfset = UCC_GETH_URFSET_INIT,
85                     .utfs = UCC_GETH_UTFS_INIT,
86                     .utfet = UCC_GETH_UTFET_INIT,
87                     .utftt = UCC_GETH_UTFTT_INIT,
88                     .ufpt = 256,
89                     .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET,
90                     .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
91                     .tenc = UCC_FAST_TX_ENCODING_NRZ,
92                     .renc = UCC_FAST_RX_ENCODING_NRZ,
93                     .tcrc = UCC_FAST_16_BIT_CRC,
94                     .synl = UCC_FAST_SYNC_LEN_NOT_USED,
95                     },
96         .numQueuesTx = 1,
97         .numQueuesRx = 1,
98         .extendedFilteringChainPointer = ((uint32_t) NULL),
99         .typeorlen = 3072 /*1536 */ ,
100         .nonBackToBackIfgPart1 = 0x40,
101         .nonBackToBackIfgPart2 = 0x60,
102         .miminumInterFrameGapEnforcement = 0x50,
103         .backToBackInterFrameGap = 0x60,
104         .mblinterval = 128,
105         .nortsrbytetime = 5,
106         .fracsiz = 1,
107         .strictpriorityq = 0xff,
108         .altBebTruncation = 0xa,
109         .excessDefer = 1,
110         .maxRetransmission = 0xf,
111         .collisionWindow = 0x37,
112         .receiveFlowControl = 1,
113         .transmitFlowControl = 1,
114         .maxGroupAddrInHash = 4,
115         .maxIndAddrInHash = 4,
116         .prel = 7,
117         .maxFrameLength = 1518,
118         .minFrameLength = 64,
119         .maxD1Length = 1520,
120         .maxD2Length = 1520,
121         .vlantype = 0x8100,
122         .ecamptr = ((uint32_t) NULL),
123         .eventRegMask = UCCE_OTHER,
124         .pausePeriod = 0xf000,
125         .interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1},
126         .bdRingLenTx = {
127                         TX_BD_RING_LEN,
128                         TX_BD_RING_LEN,
129                         TX_BD_RING_LEN,
130                         TX_BD_RING_LEN,
131                         TX_BD_RING_LEN,
132                         TX_BD_RING_LEN,
133                         TX_BD_RING_LEN,
134                         TX_BD_RING_LEN},
135
136         .bdRingLenRx = {
137                         RX_BD_RING_LEN,
138                         RX_BD_RING_LEN,
139                         RX_BD_RING_LEN,
140                         RX_BD_RING_LEN,
141                         RX_BD_RING_LEN,
142                         RX_BD_RING_LEN,
143                         RX_BD_RING_LEN,
144                         RX_BD_RING_LEN},
145
146         .numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1,
147         .largestexternallookupkeysize =
148             QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE,
149         .statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE |
150                 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX |
151                 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX,
152         .vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP,
153         .vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP,
154         .rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT,
155         .aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE,
156         .padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC,
157         .numThreadsTx = UCC_GETH_NUM_OF_THREADS_1,
158         .numThreadsRx = UCC_GETH_NUM_OF_THREADS_1,
159         .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
160         .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
161 };
162
163 static struct ucc_geth_info ugeth_info[8];
164
165 #ifdef DEBUG
166 static void mem_disp(u8 *addr, int size)
167 {
168         u8 *i;
169         int size16Aling = (size >> 4) << 4;
170         int size4Aling = (size >> 2) << 2;
171         int notAlign = 0;
172         if (size % 16)
173                 notAlign = 1;
174
175         for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16)
176                 printk("0x%08x: %08x %08x %08x %08x\r\n",
177                        (u32) i,
178                        *((u32 *) (i)),
179                        *((u32 *) (i + 4)),
180                        *((u32 *) (i + 8)), *((u32 *) (i + 12)));
181         if (notAlign == 1)
182                 printk("0x%08x: ", (u32) i);
183         for (; (u32) i < (u32) addr + size4Aling; i += 4)
184                 printk("%08x ", *((u32 *) (i)));
185         for (; (u32) i < (u32) addr + size; i++)
186                 printk("%02x", *((u8 *) (i)));
187         if (notAlign == 1)
188                 printk("\r\n");
189 }
190 #endif /* DEBUG */
191
192 static struct list_head *dequeue(struct list_head *lh)
193 {
194         unsigned long flags;
195
196         spin_lock_irqsave(&ugeth_lock, flags);
197         if (!list_empty(lh)) {
198                 struct list_head *node = lh->next;
199                 list_del(node);
200                 spin_unlock_irqrestore(&ugeth_lock, flags);
201                 return node;
202         } else {
203                 spin_unlock_irqrestore(&ugeth_lock, flags);
204                 return NULL;
205         }
206 }
207
208 static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth,
209                 u8 __iomem *bd)
210 {
211         struct sk_buff *skb = NULL;
212
213         skb = __skb_dequeue(&ugeth->rx_recycle);
214         if (!skb)
215                 skb = dev_alloc_skb(ugeth->ug_info->uf_info.max_rx_buf_length +
216                                     UCC_GETH_RX_DATA_BUF_ALIGNMENT);
217         if (skb == NULL)
218                 return NULL;
219
220         /* We need the data buffer to be aligned properly.  We will reserve
221          * as many bytes as needed to align the data properly
222          */
223         skb_reserve(skb,
224                     UCC_GETH_RX_DATA_BUF_ALIGNMENT -
225                     (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT -
226                                               1)));
227
228         skb->dev = ugeth->ndev;
229
230         out_be32(&((struct qe_bd __iomem *)bd)->buf,
231                       dma_map_single(ugeth->dev,
232                                      skb->data,
233                                      ugeth->ug_info->uf_info.max_rx_buf_length +
234                                      UCC_GETH_RX_DATA_BUF_ALIGNMENT,
235                                      DMA_FROM_DEVICE));
236
237         out_be32((u32 __iomem *)bd,
238                         (R_E | R_I | (in_be32((u32 __iomem*)bd) & R_W)));
239
240         return skb;
241 }
242
243 static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ)
244 {
245         u8 __iomem *bd;
246         u32 bd_status;
247         struct sk_buff *skb;
248         int i;
249
250         bd = ugeth->p_rx_bd_ring[rxQ];
251         i = 0;
252
253         do {
254                 bd_status = in_be32((u32 __iomem *)bd);
255                 skb = get_new_skb(ugeth, bd);
256
257                 if (!skb)       /* If can not allocate data buffer,
258                                 abort. Cleanup will be elsewhere */
259                         return -ENOMEM;
260
261                 ugeth->rx_skbuff[rxQ][i] = skb;
262
263                 /* advance the BD pointer */
264                 bd += sizeof(struct qe_bd);
265                 i++;
266         } while (!(bd_status & R_W));
267
268         return 0;
269 }
270
271 static int fill_init_enet_entries(struct ucc_geth_private *ugeth,
272                                   u32 *p_start,
273                                   u8 num_entries,
274                                   u32 thread_size,
275                                   u32 thread_alignment,
276                                   unsigned int risc,
277                                   int skip_page_for_first_entry)
278 {
279         u32 init_enet_offset;
280         u8 i;
281         int snum;
282
283         for (i = 0; i < num_entries; i++) {
284                 if ((snum = qe_get_snum()) < 0) {
285                         if (netif_msg_ifup(ugeth))
286                                 ugeth_err("fill_init_enet_entries: Can not get SNUM.");
287                         return snum;
288                 }
289                 if ((i == 0) && skip_page_for_first_entry)
290                 /* First entry of Rx does not have page */
291                         init_enet_offset = 0;
292                 else {
293                         init_enet_offset =
294                             qe_muram_alloc(thread_size, thread_alignment);
295                         if (IS_ERR_VALUE(init_enet_offset)) {
296                                 if (netif_msg_ifup(ugeth))
297                                         ugeth_err("fill_init_enet_entries: Can not allocate DPRAM memory.");
298                                 qe_put_snum((u8) snum);
299                                 return -ENOMEM;
300                         }
301                 }
302                 *(p_start++) =
303                     ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset
304                     | risc;
305         }
306
307         return 0;
308 }
309
310 static int return_init_enet_entries(struct ucc_geth_private *ugeth,
311                                     u32 *p_start,
312                                     u8 num_entries,
313                                     unsigned int risc,
314                                     int skip_page_for_first_entry)
315 {
316         u32 init_enet_offset;
317         u8 i;
318         int snum;
319
320         for (i = 0; i < num_entries; i++) {
321                 u32 val = *p_start;
322
323                 /* Check that this entry was actually valid --
324                 needed in case failed in allocations */
325                 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
326                         snum =
327                             (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
328                             ENET_INIT_PARAM_SNUM_SHIFT;
329                         qe_put_snum((u8) snum);
330                         if (!((i == 0) && skip_page_for_first_entry)) {
331                         /* First entry of Rx does not have page */
332                                 init_enet_offset =
333                                     (val & ENET_INIT_PARAM_PTR_MASK);
334                                 qe_muram_free(init_enet_offset);
335                         }
336                         *p_start++ = 0;
337                 }
338         }
339
340         return 0;
341 }
342
343 #ifdef DEBUG
344 static int dump_init_enet_entries(struct ucc_geth_private *ugeth,
345                                   u32 __iomem *p_start,
346                                   u8 num_entries,
347                                   u32 thread_size,
348                                   unsigned int risc,
349                                   int skip_page_for_first_entry)
350 {
351         u32 init_enet_offset;
352         u8 i;
353         int snum;
354
355         for (i = 0; i < num_entries; i++) {
356                 u32 val = in_be32(p_start);
357
358                 /* Check that this entry was actually valid --
359                 needed in case failed in allocations */
360                 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
361                         snum =
362                             (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
363                             ENET_INIT_PARAM_SNUM_SHIFT;
364                         qe_put_snum((u8) snum);
365                         if (!((i == 0) && skip_page_for_first_entry)) {
366                         /* First entry of Rx does not have page */
367                                 init_enet_offset =
368                                     (in_be32(p_start) &
369                                      ENET_INIT_PARAM_PTR_MASK);
370                                 ugeth_info("Init enet entry %d:", i);
371                                 ugeth_info("Base address: 0x%08x",
372                                            (u32)
373                                            qe_muram_addr(init_enet_offset));
374                                 mem_disp(qe_muram_addr(init_enet_offset),
375                                          thread_size);
376                         }
377                         p_start++;
378                 }
379         }
380
381         return 0;
382 }
383 #endif
384
385 static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont)
386 {
387         kfree(enet_addr_cont);
388 }
389
390 static void set_mac_addr(__be16 __iomem *reg, u8 *mac)
391 {
392         out_be16(&reg[0], ((u16)mac[5] << 8) | mac[4]);
393         out_be16(&reg[1], ((u16)mac[3] << 8) | mac[2]);
394         out_be16(&reg[2], ((u16)mac[1] << 8) | mac[0]);
395 }
396
397 static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num)
398 {
399         struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
400
401         if (!(paddr_num < NUM_OF_PADDRS)) {
402                 ugeth_warn("%s: Illagel paddr_num.", __func__);
403                 return -EINVAL;
404         }
405
406         p_82xx_addr_filt =
407             (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
408             addressfiltering;
409
410         /* Writing address ff.ff.ff.ff.ff.ff disables address
411         recognition for this register */
412         out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff);
413         out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff);
414         out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff);
415
416         return 0;
417 }
418
419 static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth,
420                                 u8 *p_enet_addr)
421 {
422         struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
423         u32 cecr_subblock;
424
425         p_82xx_addr_filt =
426             (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
427             addressfiltering;
428
429         cecr_subblock =
430             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
431
432         /* Ethernet frames are defined in Little Endian mode,
433         therefor to insert */
434         /* the address to the hash (Big Endian mode), we reverse the bytes.*/
435
436         set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr);
437
438         qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock,
439                      QE_CR_PROTOCOL_ETHERNET, 0);
440 }
441
442 static inline int compare_addr(u8 **addr1, u8 **addr2)
443 {
444         return memcmp(addr1, addr2, ENET_NUM_OCTETS_PER_ADDRESS);
445 }
446
447 #ifdef DEBUG
448 static void get_statistics(struct ucc_geth_private *ugeth,
449                            struct ucc_geth_tx_firmware_statistics *
450                            tx_firmware_statistics,
451                            struct ucc_geth_rx_firmware_statistics *
452                            rx_firmware_statistics,
453                            struct ucc_geth_hardware_statistics *hardware_statistics)
454 {
455         struct ucc_fast __iomem *uf_regs;
456         struct ucc_geth __iomem *ug_regs;
457         struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram;
458         struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram;
459
460         ug_regs = ugeth->ug_regs;
461         uf_regs = (struct ucc_fast __iomem *) ug_regs;
462         p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram;
463         p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram;
464
465         /* Tx firmware only if user handed pointer and driver actually
466         gathers Tx firmware statistics */
467         if (tx_firmware_statistics && p_tx_fw_statistics_pram) {
468                 tx_firmware_statistics->sicoltx =
469                     in_be32(&p_tx_fw_statistics_pram->sicoltx);
470                 tx_firmware_statistics->mulcoltx =
471                     in_be32(&p_tx_fw_statistics_pram->mulcoltx);
472                 tx_firmware_statistics->latecoltxfr =
473                     in_be32(&p_tx_fw_statistics_pram->latecoltxfr);
474                 tx_firmware_statistics->frabortduecol =
475                     in_be32(&p_tx_fw_statistics_pram->frabortduecol);
476                 tx_firmware_statistics->frlostinmactxer =
477                     in_be32(&p_tx_fw_statistics_pram->frlostinmactxer);
478                 tx_firmware_statistics->carriersenseertx =
479                     in_be32(&p_tx_fw_statistics_pram->carriersenseertx);
480                 tx_firmware_statistics->frtxok =
481                     in_be32(&p_tx_fw_statistics_pram->frtxok);
482                 tx_firmware_statistics->txfrexcessivedefer =
483                     in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer);
484                 tx_firmware_statistics->txpkts256 =
485                     in_be32(&p_tx_fw_statistics_pram->txpkts256);
486                 tx_firmware_statistics->txpkts512 =
487                     in_be32(&p_tx_fw_statistics_pram->txpkts512);
488                 tx_firmware_statistics->txpkts1024 =
489                     in_be32(&p_tx_fw_statistics_pram->txpkts1024);
490                 tx_firmware_statistics->txpktsjumbo =
491                     in_be32(&p_tx_fw_statistics_pram->txpktsjumbo);
492         }
493
494         /* Rx firmware only if user handed pointer and driver actually
495          * gathers Rx firmware statistics */
496         if (rx_firmware_statistics && p_rx_fw_statistics_pram) {
497                 int i;
498                 rx_firmware_statistics->frrxfcser =
499                     in_be32(&p_rx_fw_statistics_pram->frrxfcser);
500                 rx_firmware_statistics->fraligner =
501                     in_be32(&p_rx_fw_statistics_pram->fraligner);
502                 rx_firmware_statistics->inrangelenrxer =
503                     in_be32(&p_rx_fw_statistics_pram->inrangelenrxer);
504                 rx_firmware_statistics->outrangelenrxer =
505                     in_be32(&p_rx_fw_statistics_pram->outrangelenrxer);
506                 rx_firmware_statistics->frtoolong =
507                     in_be32(&p_rx_fw_statistics_pram->frtoolong);
508                 rx_firmware_statistics->runt =
509                     in_be32(&p_rx_fw_statistics_pram->runt);
510                 rx_firmware_statistics->verylongevent =
511                     in_be32(&p_rx_fw_statistics_pram->verylongevent);
512                 rx_firmware_statistics->symbolerror =
513                     in_be32(&p_rx_fw_statistics_pram->symbolerror);
514                 rx_firmware_statistics->dropbsy =
515                     in_be32(&p_rx_fw_statistics_pram->dropbsy);
516                 for (i = 0; i < 0x8; i++)
517                         rx_firmware_statistics->res0[i] =
518                             p_rx_fw_statistics_pram->res0[i];
519                 rx_firmware_statistics->mismatchdrop =
520                     in_be32(&p_rx_fw_statistics_pram->mismatchdrop);
521                 rx_firmware_statistics->underpkts =
522                     in_be32(&p_rx_fw_statistics_pram->underpkts);
523                 rx_firmware_statistics->pkts256 =
524                     in_be32(&p_rx_fw_statistics_pram->pkts256);
525                 rx_firmware_statistics->pkts512 =
526                     in_be32(&p_rx_fw_statistics_pram->pkts512);
527                 rx_firmware_statistics->pkts1024 =
528                     in_be32(&p_rx_fw_statistics_pram->pkts1024);
529                 rx_firmware_statistics->pktsjumbo =
530                     in_be32(&p_rx_fw_statistics_pram->pktsjumbo);
531                 rx_firmware_statistics->frlossinmacer =
532                     in_be32(&p_rx_fw_statistics_pram->frlossinmacer);
533                 rx_firmware_statistics->pausefr =
534                     in_be32(&p_rx_fw_statistics_pram->pausefr);
535                 for (i = 0; i < 0x4; i++)
536                         rx_firmware_statistics->res1[i] =
537                             p_rx_fw_statistics_pram->res1[i];
538                 rx_firmware_statistics->removevlan =
539                     in_be32(&p_rx_fw_statistics_pram->removevlan);
540                 rx_firmware_statistics->replacevlan =
541                     in_be32(&p_rx_fw_statistics_pram->replacevlan);
542                 rx_firmware_statistics->insertvlan =
543                     in_be32(&p_rx_fw_statistics_pram->insertvlan);
544         }
545
546         /* Hardware only if user handed pointer and driver actually
547         gathers hardware statistics */
548         if (hardware_statistics &&
549             (in_be32(&uf_regs->upsmr) & UCC_GETH_UPSMR_HSE)) {
550                 hardware_statistics->tx64 = in_be32(&ug_regs->tx64);
551                 hardware_statistics->tx127 = in_be32(&ug_regs->tx127);
552                 hardware_statistics->tx255 = in_be32(&ug_regs->tx255);
553                 hardware_statistics->rx64 = in_be32(&ug_regs->rx64);
554                 hardware_statistics->rx127 = in_be32(&ug_regs->rx127);
555                 hardware_statistics->rx255 = in_be32(&ug_regs->rx255);
556                 hardware_statistics->txok = in_be32(&ug_regs->txok);
557                 hardware_statistics->txcf = in_be16(&ug_regs->txcf);
558                 hardware_statistics->tmca = in_be32(&ug_regs->tmca);
559                 hardware_statistics->tbca = in_be32(&ug_regs->tbca);
560                 hardware_statistics->rxfok = in_be32(&ug_regs->rxfok);
561                 hardware_statistics->rxbok = in_be32(&ug_regs->rxbok);
562                 hardware_statistics->rbyt = in_be32(&ug_regs->rbyt);
563                 hardware_statistics->rmca = in_be32(&ug_regs->rmca);
564                 hardware_statistics->rbca = in_be32(&ug_regs->rbca);
565         }
566 }
567
568 static void dump_bds(struct ucc_geth_private *ugeth)
569 {
570         int i;
571         int length;
572
573         for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
574                 if (ugeth->p_tx_bd_ring[i]) {
575                         length =
576                             (ugeth->ug_info->bdRingLenTx[i] *
577                              sizeof(struct qe_bd));
578                         ugeth_info("TX BDs[%d]", i);
579                         mem_disp(ugeth->p_tx_bd_ring[i], length);
580                 }
581         }
582         for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
583                 if (ugeth->p_rx_bd_ring[i]) {
584                         length =
585                             (ugeth->ug_info->bdRingLenRx[i] *
586                              sizeof(struct qe_bd));
587                         ugeth_info("RX BDs[%d]", i);
588                         mem_disp(ugeth->p_rx_bd_ring[i], length);
589                 }
590         }
591 }
592
593 static void dump_regs(struct ucc_geth_private *ugeth)
594 {
595         int i;
596
597         ugeth_info("UCC%d Geth registers:", ugeth->ug_info->uf_info.ucc_num);
598         ugeth_info("Base address: 0x%08x", (u32) ugeth->ug_regs);
599
600         ugeth_info("maccfg1    : addr - 0x%08x, val - 0x%08x",
601                    (u32) & ugeth->ug_regs->maccfg1,
602                    in_be32(&ugeth->ug_regs->maccfg1));
603         ugeth_info("maccfg2    : addr - 0x%08x, val - 0x%08x",
604                    (u32) & ugeth->ug_regs->maccfg2,
605                    in_be32(&ugeth->ug_regs->maccfg2));
606         ugeth_info("ipgifg     : addr - 0x%08x, val - 0x%08x",
607                    (u32) & ugeth->ug_regs->ipgifg,
608                    in_be32(&ugeth->ug_regs->ipgifg));
609         ugeth_info("hafdup     : addr - 0x%08x, val - 0x%08x",
610                    (u32) & ugeth->ug_regs->hafdup,
611                    in_be32(&ugeth->ug_regs->hafdup));
612         ugeth_info("ifctl      : addr - 0x%08x, val - 0x%08x",
613                    (u32) & ugeth->ug_regs->ifctl,
614                    in_be32(&ugeth->ug_regs->ifctl));
615         ugeth_info("ifstat     : addr - 0x%08x, val - 0x%08x",
616                    (u32) & ugeth->ug_regs->ifstat,
617                    in_be32(&ugeth->ug_regs->ifstat));
618         ugeth_info("macstnaddr1: addr - 0x%08x, val - 0x%08x",
619                    (u32) & ugeth->ug_regs->macstnaddr1,
620                    in_be32(&ugeth->ug_regs->macstnaddr1));
621         ugeth_info("macstnaddr2: addr - 0x%08x, val - 0x%08x",
622                    (u32) & ugeth->ug_regs->macstnaddr2,
623                    in_be32(&ugeth->ug_regs->macstnaddr2));
624         ugeth_info("uempr      : addr - 0x%08x, val - 0x%08x",
625                    (u32) & ugeth->ug_regs->uempr,
626                    in_be32(&ugeth->ug_regs->uempr));
627         ugeth_info("utbipar    : addr - 0x%08x, val - 0x%08x",
628                    (u32) & ugeth->ug_regs->utbipar,
629                    in_be32(&ugeth->ug_regs->utbipar));
630         ugeth_info("uescr      : addr - 0x%08x, val - 0x%04x",
631                    (u32) & ugeth->ug_regs->uescr,
632                    in_be16(&ugeth->ug_regs->uescr));
633         ugeth_info("tx64       : addr - 0x%08x, val - 0x%08x",
634                    (u32) & ugeth->ug_regs->tx64,
635                    in_be32(&ugeth->ug_regs->tx64));
636         ugeth_info("tx127      : addr - 0x%08x, val - 0x%08x",
637                    (u32) & ugeth->ug_regs->tx127,
638                    in_be32(&ugeth->ug_regs->tx127));
639         ugeth_info("tx255      : addr - 0x%08x, val - 0x%08x",
640                    (u32) & ugeth->ug_regs->tx255,
641                    in_be32(&ugeth->ug_regs->tx255));
642         ugeth_info("rx64       : addr - 0x%08x, val - 0x%08x",
643                    (u32) & ugeth->ug_regs->rx64,
644                    in_be32(&ugeth->ug_regs->rx64));
645         ugeth_info("rx127      : addr - 0x%08x, val - 0x%08x",
646                    (u32) & ugeth->ug_regs->rx127,
647                    in_be32(&ugeth->ug_regs->rx127));
648         ugeth_info("rx255      : addr - 0x%08x, val - 0x%08x",
649                    (u32) & ugeth->ug_regs->rx255,
650                    in_be32(&ugeth->ug_regs->rx255));
651         ugeth_info("txok       : addr - 0x%08x, val - 0x%08x",
652                    (u32) & ugeth->ug_regs->txok,
653                    in_be32(&ugeth->ug_regs->txok));
654         ugeth_info("txcf       : addr - 0x%08x, val - 0x%04x",
655                    (u32) & ugeth->ug_regs->txcf,
656                    in_be16(&ugeth->ug_regs->txcf));
657         ugeth_info("tmca       : addr - 0x%08x, val - 0x%08x",
658                    (u32) & ugeth->ug_regs->tmca,
659                    in_be32(&ugeth->ug_regs->tmca));
660         ugeth_info("tbca       : addr - 0x%08x, val - 0x%08x",
661                    (u32) & ugeth->ug_regs->tbca,
662                    in_be32(&ugeth->ug_regs->tbca));
663         ugeth_info("rxfok      : addr - 0x%08x, val - 0x%08x",
664                    (u32) & ugeth->ug_regs->rxfok,
665                    in_be32(&ugeth->ug_regs->rxfok));
666         ugeth_info("rxbok      : addr - 0x%08x, val - 0x%08x",
667                    (u32) & ugeth->ug_regs->rxbok,
668                    in_be32(&ugeth->ug_regs->rxbok));
669         ugeth_info("rbyt       : addr - 0x%08x, val - 0x%08x",
670                    (u32) & ugeth->ug_regs->rbyt,
671                    in_be32(&ugeth->ug_regs->rbyt));
672         ugeth_info("rmca       : addr - 0x%08x, val - 0x%08x",
673                    (u32) & ugeth->ug_regs->rmca,
674                    in_be32(&ugeth->ug_regs->rmca));
675         ugeth_info("rbca       : addr - 0x%08x, val - 0x%08x",
676                    (u32) & ugeth->ug_regs->rbca,
677                    in_be32(&ugeth->ug_regs->rbca));
678         ugeth_info("scar       : addr - 0x%08x, val - 0x%08x",
679                    (u32) & ugeth->ug_regs->scar,
680                    in_be32(&ugeth->ug_regs->scar));
681         ugeth_info("scam       : addr - 0x%08x, val - 0x%08x",
682                    (u32) & ugeth->ug_regs->scam,
683                    in_be32(&ugeth->ug_regs->scam));
684
685         if (ugeth->p_thread_data_tx) {
686                 int numThreadsTxNumerical;
687                 switch (ugeth->ug_info->numThreadsTx) {
688                 case UCC_GETH_NUM_OF_THREADS_1:
689                         numThreadsTxNumerical = 1;
690                         break;
691                 case UCC_GETH_NUM_OF_THREADS_2:
692                         numThreadsTxNumerical = 2;
693                         break;
694                 case UCC_GETH_NUM_OF_THREADS_4:
695                         numThreadsTxNumerical = 4;
696                         break;
697                 case UCC_GETH_NUM_OF_THREADS_6:
698                         numThreadsTxNumerical = 6;
699                         break;
700                 case UCC_GETH_NUM_OF_THREADS_8:
701                         numThreadsTxNumerical = 8;
702                         break;
703                 default:
704                         numThreadsTxNumerical = 0;
705                         break;
706                 }
707
708                 ugeth_info("Thread data TXs:");
709                 ugeth_info("Base address: 0x%08x",
710                            (u32) ugeth->p_thread_data_tx);
711                 for (i = 0; i < numThreadsTxNumerical; i++) {
712                         ugeth_info("Thread data TX[%d]:", i);
713                         ugeth_info("Base address: 0x%08x",
714                                    (u32) & ugeth->p_thread_data_tx[i]);
715                         mem_disp((u8 *) & ugeth->p_thread_data_tx[i],
716                                  sizeof(struct ucc_geth_thread_data_tx));
717                 }
718         }
719         if (ugeth->p_thread_data_rx) {
720                 int numThreadsRxNumerical;
721                 switch (ugeth->ug_info->numThreadsRx) {
722                 case UCC_GETH_NUM_OF_THREADS_1:
723                         numThreadsRxNumerical = 1;
724                         break;
725                 case UCC_GETH_NUM_OF_THREADS_2:
726                         numThreadsRxNumerical = 2;
727                         break;
728                 case UCC_GETH_NUM_OF_THREADS_4:
729                         numThreadsRxNumerical = 4;
730                         break;
731                 case UCC_GETH_NUM_OF_THREADS_6:
732                         numThreadsRxNumerical = 6;
733                         break;
734                 case UCC_GETH_NUM_OF_THREADS_8:
735                         numThreadsRxNumerical = 8;
736                         break;
737                 default:
738                         numThreadsRxNumerical = 0;
739                         break;
740                 }
741
742                 ugeth_info("Thread data RX:");
743                 ugeth_info("Base address: 0x%08x",
744                            (u32) ugeth->p_thread_data_rx);
745                 for (i = 0; i < numThreadsRxNumerical; i++) {
746                         ugeth_info("Thread data RX[%d]:", i);
747                         ugeth_info("Base address: 0x%08x",
748                                    (u32) & ugeth->p_thread_data_rx[i]);
749                         mem_disp((u8 *) & ugeth->p_thread_data_rx[i],
750                                  sizeof(struct ucc_geth_thread_data_rx));
751                 }
752         }
753         if (ugeth->p_exf_glbl_param) {
754                 ugeth_info("EXF global param:");
755                 ugeth_info("Base address: 0x%08x",
756                            (u32) ugeth->p_exf_glbl_param);
757                 mem_disp((u8 *) ugeth->p_exf_glbl_param,
758                          sizeof(*ugeth->p_exf_glbl_param));
759         }
760         if (ugeth->p_tx_glbl_pram) {
761                 ugeth_info("TX global param:");
762                 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_tx_glbl_pram);
763                 ugeth_info("temoder      : addr - 0x%08x, val - 0x%04x",
764                            (u32) & ugeth->p_tx_glbl_pram->temoder,
765                            in_be16(&ugeth->p_tx_glbl_pram->temoder));
766                 ugeth_info("sqptr        : addr - 0x%08x, val - 0x%08x",
767                            (u32) & ugeth->p_tx_glbl_pram->sqptr,
768                            in_be32(&ugeth->p_tx_glbl_pram->sqptr));
769                 ugeth_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x",
770                            (u32) & ugeth->p_tx_glbl_pram->schedulerbasepointer,
771                            in_be32(&ugeth->p_tx_glbl_pram->
772                                    schedulerbasepointer));
773                 ugeth_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x",
774                            (u32) & ugeth->p_tx_glbl_pram->txrmonbaseptr,
775                            in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr));
776                 ugeth_info("tstate       : addr - 0x%08x, val - 0x%08x",
777                            (u32) & ugeth->p_tx_glbl_pram->tstate,
778                            in_be32(&ugeth->p_tx_glbl_pram->tstate));
779                 ugeth_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x",
780                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[0],
781                            ugeth->p_tx_glbl_pram->iphoffset[0]);
782                 ugeth_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x",
783                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[1],
784                            ugeth->p_tx_glbl_pram->iphoffset[1]);
785                 ugeth_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x",
786                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[2],
787                            ugeth->p_tx_glbl_pram->iphoffset[2]);
788                 ugeth_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x",
789                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[3],
790                            ugeth->p_tx_glbl_pram->iphoffset[3]);
791                 ugeth_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x",
792                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[4],
793                            ugeth->p_tx_glbl_pram->iphoffset[4]);
794                 ugeth_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x",
795                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[5],
796                            ugeth->p_tx_glbl_pram->iphoffset[5]);
797                 ugeth_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x",
798                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[6],
799                            ugeth->p_tx_glbl_pram->iphoffset[6]);
800                 ugeth_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x",
801                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[7],
802                            ugeth->p_tx_glbl_pram->iphoffset[7]);
803                 ugeth_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x",
804                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[0],
805                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0]));
806                 ugeth_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x",
807                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[1],
808                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1]));
809                 ugeth_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x",
810                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[2],
811                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2]));
812                 ugeth_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x",
813                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[3],
814                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3]));
815                 ugeth_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x",
816                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[4],
817                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4]));
818                 ugeth_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x",
819                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[5],
820                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5]));
821                 ugeth_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x",
822                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[6],
823                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6]));
824                 ugeth_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x",
825                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[7],
826                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7]));
827                 ugeth_info("tqptr        : addr - 0x%08x, val - 0x%08x",
828                            (u32) & ugeth->p_tx_glbl_pram->tqptr,
829                            in_be32(&ugeth->p_tx_glbl_pram->tqptr));
830         }
831         if (ugeth->p_rx_glbl_pram) {
832                 ugeth_info("RX global param:");
833                 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_glbl_pram);
834                 ugeth_info("remoder         : addr - 0x%08x, val - 0x%08x",
835                            (u32) & ugeth->p_rx_glbl_pram->remoder,
836                            in_be32(&ugeth->p_rx_glbl_pram->remoder));
837                 ugeth_info("rqptr           : addr - 0x%08x, val - 0x%08x",
838                            (u32) & ugeth->p_rx_glbl_pram->rqptr,
839                            in_be32(&ugeth->p_rx_glbl_pram->rqptr));
840                 ugeth_info("typeorlen       : addr - 0x%08x, val - 0x%04x",
841                            (u32) & ugeth->p_rx_glbl_pram->typeorlen,
842                            in_be16(&ugeth->p_rx_glbl_pram->typeorlen));
843                 ugeth_info("rxgstpack       : addr - 0x%08x, val - 0x%02x",
844                            (u32) & ugeth->p_rx_glbl_pram->rxgstpack,
845                            ugeth->p_rx_glbl_pram->rxgstpack);
846                 ugeth_info("rxrmonbaseptr   : addr - 0x%08x, val - 0x%08x",
847                            (u32) & ugeth->p_rx_glbl_pram->rxrmonbaseptr,
848                            in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr));
849                 ugeth_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x",
850                            (u32) & ugeth->p_rx_glbl_pram->intcoalescingptr,
851                            in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr));
852                 ugeth_info("rstate          : addr - 0x%08x, val - 0x%02x",
853                            (u32) & ugeth->p_rx_glbl_pram->rstate,
854                            ugeth->p_rx_glbl_pram->rstate);
855                 ugeth_info("mrblr           : addr - 0x%08x, val - 0x%04x",
856                            (u32) & ugeth->p_rx_glbl_pram->mrblr,
857                            in_be16(&ugeth->p_rx_glbl_pram->mrblr));
858                 ugeth_info("rbdqptr         : addr - 0x%08x, val - 0x%08x",
859                            (u32) & ugeth->p_rx_glbl_pram->rbdqptr,
860                            in_be32(&ugeth->p_rx_glbl_pram->rbdqptr));
861                 ugeth_info("mflr            : addr - 0x%08x, val - 0x%04x",
862                            (u32) & ugeth->p_rx_glbl_pram->mflr,
863                            in_be16(&ugeth->p_rx_glbl_pram->mflr));
864                 ugeth_info("minflr          : addr - 0x%08x, val - 0x%04x",
865                            (u32) & ugeth->p_rx_glbl_pram->minflr,
866                            in_be16(&ugeth->p_rx_glbl_pram->minflr));
867                 ugeth_info("maxd1           : addr - 0x%08x, val - 0x%04x",
868                            (u32) & ugeth->p_rx_glbl_pram->maxd1,
869                            in_be16(&ugeth->p_rx_glbl_pram->maxd1));
870                 ugeth_info("maxd2           : addr - 0x%08x, val - 0x%04x",
871                            (u32) & ugeth->p_rx_glbl_pram->maxd2,
872                            in_be16(&ugeth->p_rx_glbl_pram->maxd2));
873                 ugeth_info("ecamptr         : addr - 0x%08x, val - 0x%08x",
874                            (u32) & ugeth->p_rx_glbl_pram->ecamptr,
875                            in_be32(&ugeth->p_rx_glbl_pram->ecamptr));
876                 ugeth_info("l2qt            : addr - 0x%08x, val - 0x%08x",
877                            (u32) & ugeth->p_rx_glbl_pram->l2qt,
878                            in_be32(&ugeth->p_rx_glbl_pram->l2qt));
879                 ugeth_info("l3qt[0]         : addr - 0x%08x, val - 0x%08x",
880                            (u32) & ugeth->p_rx_glbl_pram->l3qt[0],
881                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[0]));
882                 ugeth_info("l3qt[1]         : addr - 0x%08x, val - 0x%08x",
883                            (u32) & ugeth->p_rx_glbl_pram->l3qt[1],
884                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[1]));
885                 ugeth_info("l3qt[2]         : addr - 0x%08x, val - 0x%08x",
886                            (u32) & ugeth->p_rx_glbl_pram->l3qt[2],
887                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[2]));
888                 ugeth_info("l3qt[3]         : addr - 0x%08x, val - 0x%08x",
889                            (u32) & ugeth->p_rx_glbl_pram->l3qt[3],
890                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[3]));
891                 ugeth_info("l3qt[4]         : addr - 0x%08x, val - 0x%08x",
892                            (u32) & ugeth->p_rx_glbl_pram->l3qt[4],
893                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[4]));
894                 ugeth_info("l3qt[5]         : addr - 0x%08x, val - 0x%08x",
895                            (u32) & ugeth->p_rx_glbl_pram->l3qt[5],
896                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[5]));
897                 ugeth_info("l3qt[6]         : addr - 0x%08x, val - 0x%08x",
898                            (u32) & ugeth->p_rx_glbl_pram->l3qt[6],
899                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[6]));
900                 ugeth_info("l3qt[7]         : addr - 0x%08x, val - 0x%08x",
901                            (u32) & ugeth->p_rx_glbl_pram->l3qt[7],
902                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[7]));
903                 ugeth_info("vlantype        : addr - 0x%08x, val - 0x%04x",
904                            (u32) & ugeth->p_rx_glbl_pram->vlantype,
905                            in_be16(&ugeth->p_rx_glbl_pram->vlantype));
906                 ugeth_info("vlantci         : addr - 0x%08x, val - 0x%04x",
907                            (u32) & ugeth->p_rx_glbl_pram->vlantci,
908                            in_be16(&ugeth->p_rx_glbl_pram->vlantci));
909                 for (i = 0; i < 64; i++)
910                         ugeth_info
911                     ("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x",
912                              i,
913                              (u32) & ugeth->p_rx_glbl_pram->addressfiltering[i],
914                              ugeth->p_rx_glbl_pram->addressfiltering[i]);
915                 ugeth_info("exfGlobalParam  : addr - 0x%08x, val - 0x%08x",
916                            (u32) & ugeth->p_rx_glbl_pram->exfGlobalParam,
917                            in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam));
918         }
919         if (ugeth->p_send_q_mem_reg) {
920                 ugeth_info("Send Q memory registers:");
921                 ugeth_info("Base address: 0x%08x",
922                            (u32) ugeth->p_send_q_mem_reg);
923                 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
924                         ugeth_info("SQQD[%d]:", i);
925                         ugeth_info("Base address: 0x%08x",
926                                    (u32) & ugeth->p_send_q_mem_reg->sqqd[i]);
927                         mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i],
928                                  sizeof(struct ucc_geth_send_queue_qd));
929                 }
930         }
931         if (ugeth->p_scheduler) {
932                 ugeth_info("Scheduler:");
933                 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_scheduler);
934                 mem_disp((u8 *) ugeth->p_scheduler,
935                          sizeof(*ugeth->p_scheduler));
936         }
937         if (ugeth->p_tx_fw_statistics_pram) {
938                 ugeth_info("TX FW statistics pram:");
939                 ugeth_info("Base address: 0x%08x",
940                            (u32) ugeth->p_tx_fw_statistics_pram);
941                 mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram,
942                          sizeof(*ugeth->p_tx_fw_statistics_pram));
943         }
944         if (ugeth->p_rx_fw_statistics_pram) {
945                 ugeth_info("RX FW statistics pram:");
946                 ugeth_info("Base address: 0x%08x",
947                            (u32) ugeth->p_rx_fw_statistics_pram);
948                 mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram,
949                          sizeof(*ugeth->p_rx_fw_statistics_pram));
950         }
951         if (ugeth->p_rx_irq_coalescing_tbl) {
952                 ugeth_info("RX IRQ coalescing tables:");
953                 ugeth_info("Base address: 0x%08x",
954                            (u32) ugeth->p_rx_irq_coalescing_tbl);
955                 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
956                         ugeth_info("RX IRQ coalescing table entry[%d]:", i);
957                         ugeth_info("Base address: 0x%08x",
958                                    (u32) & ugeth->p_rx_irq_coalescing_tbl->
959                                    coalescingentry[i]);
960                         ugeth_info
961                 ("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x",
962                              (u32) & ugeth->p_rx_irq_coalescing_tbl->
963                              coalescingentry[i].interruptcoalescingmaxvalue,
964                              in_be32(&ugeth->p_rx_irq_coalescing_tbl->
965                                      coalescingentry[i].
966                                      interruptcoalescingmaxvalue));
967                         ugeth_info
968                 ("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x",
969                              (u32) & ugeth->p_rx_irq_coalescing_tbl->
970                              coalescingentry[i].interruptcoalescingcounter,
971                              in_be32(&ugeth->p_rx_irq_coalescing_tbl->
972                                      coalescingentry[i].
973                                      interruptcoalescingcounter));
974                 }
975         }
976         if (ugeth->p_rx_bd_qs_tbl) {
977                 ugeth_info("RX BD QS tables:");
978                 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_bd_qs_tbl);
979                 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
980                         ugeth_info("RX BD QS table[%d]:", i);
981                         ugeth_info("Base address: 0x%08x",
982                                    (u32) & ugeth->p_rx_bd_qs_tbl[i]);
983                         ugeth_info
984                             ("bdbaseptr        : addr - 0x%08x, val - 0x%08x",
985                              (u32) & ugeth->p_rx_bd_qs_tbl[i].bdbaseptr,
986                              in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr));
987                         ugeth_info
988                             ("bdptr            : addr - 0x%08x, val - 0x%08x",
989                              (u32) & ugeth->p_rx_bd_qs_tbl[i].bdptr,
990                              in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr));
991                         ugeth_info
992                             ("externalbdbaseptr: addr - 0x%08x, val - 0x%08x",
993                              (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
994                              in_be32(&ugeth->p_rx_bd_qs_tbl[i].
995                                      externalbdbaseptr));
996                         ugeth_info
997                             ("externalbdptr    : addr - 0x%08x, val - 0x%08x",
998                              (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdptr,
999                              in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr));
1000                         ugeth_info("ucode RX Prefetched BDs:");
1001                         ugeth_info("Base address: 0x%08x",
1002                                    (u32)
1003                                    qe_muram_addr(in_be32
1004                                                  (&ugeth->p_rx_bd_qs_tbl[i].
1005                                                   bdbaseptr)));
1006                         mem_disp((u8 *)
1007                                  qe_muram_addr(in_be32
1008                                                (&ugeth->p_rx_bd_qs_tbl[i].
1009                                                 bdbaseptr)),
1010                                  sizeof(struct ucc_geth_rx_prefetched_bds));
1011                 }
1012         }
1013         if (ugeth->p_init_enet_param_shadow) {
1014                 int size;
1015                 ugeth_info("Init enet param shadow:");
1016                 ugeth_info("Base address: 0x%08x",
1017                            (u32) ugeth->p_init_enet_param_shadow);
1018                 mem_disp((u8 *) ugeth->p_init_enet_param_shadow,
1019                          sizeof(*ugeth->p_init_enet_param_shadow));
1020
1021                 size = sizeof(struct ucc_geth_thread_rx_pram);
1022                 if (ugeth->ug_info->rxExtendedFiltering) {
1023                         size +=
1024                             THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
1025                         if (ugeth->ug_info->largestexternallookupkeysize ==
1026                             QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
1027                                 size +=
1028                         THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
1029                         if (ugeth->ug_info->largestexternallookupkeysize ==
1030                             QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
1031                                 size +=
1032                         THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
1033                 }
1034
1035                 dump_init_enet_entries(ugeth,
1036                                        &(ugeth->p_init_enet_param_shadow->
1037                                          txthread[0]),
1038                                        ENET_INIT_PARAM_MAX_ENTRIES_TX,
1039                                        sizeof(struct ucc_geth_thread_tx_pram),
1040                                        ugeth->ug_info->riscTx, 0);
1041                 dump_init_enet_entries(ugeth,
1042                                        &(ugeth->p_init_enet_param_shadow->
1043                                          rxthread[0]),
1044                                        ENET_INIT_PARAM_MAX_ENTRIES_RX, size,
1045                                        ugeth->ug_info->riscRx, 1);
1046         }
1047 }
1048 #endif /* DEBUG */
1049
1050 static void init_default_reg_vals(u32 __iomem *upsmr_register,
1051                                   u32 __iomem *maccfg1_register,
1052                                   u32 __iomem *maccfg2_register)
1053 {
1054         out_be32(upsmr_register, UCC_GETH_UPSMR_INIT);
1055         out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT);
1056         out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT);
1057 }
1058
1059 static int init_half_duplex_params(int alt_beb,
1060                                    int back_pressure_no_backoff,
1061                                    int no_backoff,
1062                                    int excess_defer,
1063                                    u8 alt_beb_truncation,
1064                                    u8 max_retransmissions,
1065                                    u8 collision_window,
1066                                    u32 __iomem *hafdup_register)
1067 {
1068         u32 value = 0;
1069
1070         if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) ||
1071             (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) ||
1072             (collision_window > HALFDUP_COLLISION_WINDOW_MAX))
1073                 return -EINVAL;
1074
1075         value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT);
1076
1077         if (alt_beb)
1078                 value |= HALFDUP_ALT_BEB;
1079         if (back_pressure_no_backoff)
1080                 value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF;
1081         if (no_backoff)
1082                 value |= HALFDUP_NO_BACKOFF;
1083         if (excess_defer)
1084                 value |= HALFDUP_EXCESSIVE_DEFER;
1085
1086         value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT);
1087
1088         value |= collision_window;
1089
1090         out_be32(hafdup_register, value);
1091         return 0;
1092 }
1093
1094 static int init_inter_frame_gap_params(u8 non_btb_cs_ipg,
1095                                        u8 non_btb_ipg,
1096                                        u8 min_ifg,
1097                                        u8 btb_ipg,
1098                                        u32 __iomem *ipgifg_register)
1099 {
1100         u32 value = 0;
1101
1102         /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back
1103         IPG part 2 */
1104         if (non_btb_cs_ipg > non_btb_ipg)
1105                 return -EINVAL;
1106
1107         if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) ||
1108             (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) ||
1109             /*(min_ifg        > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */
1110             (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX))
1111                 return -EINVAL;
1112
1113         value |=
1114             ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) &
1115              IPGIFG_NBTB_CS_IPG_MASK);
1116         value |=
1117             ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) &
1118              IPGIFG_NBTB_IPG_MASK);
1119         value |=
1120             ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) &
1121              IPGIFG_MIN_IFG_MASK);
1122         value |= (btb_ipg & IPGIFG_BTB_IPG_MASK);
1123
1124         out_be32(ipgifg_register, value);
1125         return 0;
1126 }
1127
1128 int init_flow_control_params(u32 automatic_flow_control_mode,
1129                                     int rx_flow_control_enable,
1130                                     int tx_flow_control_enable,
1131                                     u16 pause_period,
1132                                     u16 extension_field,
1133                                     u32 __iomem *upsmr_register,
1134                                     u32 __iomem *uempr_register,
1135                                     u32 __iomem *maccfg1_register)
1136 {
1137         u32 value = 0;
1138
1139         /* Set UEMPR register */
1140         value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT;
1141         value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT;
1142         out_be32(uempr_register, value);
1143
1144         /* Set UPSMR register */
1145         setbits32(upsmr_register, automatic_flow_control_mode);
1146
1147         value = in_be32(maccfg1_register);
1148         if (rx_flow_control_enable)
1149                 value |= MACCFG1_FLOW_RX;
1150         if (tx_flow_control_enable)
1151                 value |= MACCFG1_FLOW_TX;
1152         out_be32(maccfg1_register, value);
1153
1154         return 0;
1155 }
1156
1157 static int init_hw_statistics_gathering_mode(int enable_hardware_statistics,
1158                                              int auto_zero_hardware_statistics,
1159                                              u32 __iomem *upsmr_register,
1160                                              u16 __iomem *uescr_register)
1161 {
1162         u16 uescr_value = 0;
1163
1164         /* Enable hardware statistics gathering if requested */
1165         if (enable_hardware_statistics)
1166                 setbits32(upsmr_register, UCC_GETH_UPSMR_HSE);
1167
1168         /* Clear hardware statistics counters */
1169         uescr_value = in_be16(uescr_register);
1170         uescr_value |= UESCR_CLRCNT;
1171         /* Automatically zero hardware statistics counters on read,
1172         if requested */
1173         if (auto_zero_hardware_statistics)
1174                 uescr_value |= UESCR_AUTOZ;
1175         out_be16(uescr_register, uescr_value);
1176
1177         return 0;
1178 }
1179
1180 static int init_firmware_statistics_gathering_mode(int
1181                 enable_tx_firmware_statistics,
1182                 int enable_rx_firmware_statistics,
1183                 u32 __iomem *tx_rmon_base_ptr,
1184                 u32 tx_firmware_statistics_structure_address,
1185                 u32 __iomem *rx_rmon_base_ptr,
1186                 u32 rx_firmware_statistics_structure_address,
1187                 u16 __iomem *temoder_register,
1188                 u32 __iomem *remoder_register)
1189 {
1190         /* Note: this function does not check if */
1191         /* the parameters it receives are NULL   */
1192
1193         if (enable_tx_firmware_statistics) {
1194                 out_be32(tx_rmon_base_ptr,
1195                          tx_firmware_statistics_structure_address);
1196                 setbits16(temoder_register, TEMODER_TX_RMON_STATISTICS_ENABLE);
1197         }
1198
1199         if (enable_rx_firmware_statistics) {
1200                 out_be32(rx_rmon_base_ptr,
1201                          rx_firmware_statistics_structure_address);
1202                 setbits32(remoder_register, REMODER_RX_RMON_STATISTICS_ENABLE);
1203         }
1204
1205         return 0;
1206 }
1207
1208 static int init_mac_station_addr_regs(u8 address_byte_0,
1209                                       u8 address_byte_1,
1210                                       u8 address_byte_2,
1211                                       u8 address_byte_3,
1212                                       u8 address_byte_4,
1213                                       u8 address_byte_5,
1214                                       u32 __iomem *macstnaddr1_register,
1215                                       u32 __iomem *macstnaddr2_register)
1216 {
1217         u32 value = 0;
1218
1219         /* Example: for a station address of 0x12345678ABCD, */
1220         /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */
1221
1222         /* MACSTNADDR1 Register: */
1223
1224         /* 0                      7   8                      15  */
1225         /* station address byte 5     station address byte 4     */
1226         /* 16                     23  24                     31  */
1227         /* station address byte 3     station address byte 2     */
1228         value |= (u32) ((address_byte_2 << 0) & 0x000000FF);
1229         value |= (u32) ((address_byte_3 << 8) & 0x0000FF00);
1230         value |= (u32) ((address_byte_4 << 16) & 0x00FF0000);
1231         value |= (u32) ((address_byte_5 << 24) & 0xFF000000);
1232
1233         out_be32(macstnaddr1_register, value);
1234
1235         /* MACSTNADDR2 Register: */
1236
1237         /* 0                      7   8                      15  */
1238         /* station address byte 1     station address byte 0     */
1239         /* 16                     23  24                     31  */
1240         /*         reserved                   reserved           */
1241         value = 0;
1242         value |= (u32) ((address_byte_0 << 16) & 0x00FF0000);
1243         value |= (u32) ((address_byte_1 << 24) & 0xFF000000);
1244
1245         out_be32(macstnaddr2_register, value);
1246
1247         return 0;
1248 }
1249
1250 static int init_check_frame_length_mode(int length_check,
1251                                         u32 __iomem *maccfg2_register)
1252 {
1253         u32 value = 0;
1254
1255         value = in_be32(maccfg2_register);
1256
1257         if (length_check)
1258                 value |= MACCFG2_LC;
1259         else
1260                 value &= ~MACCFG2_LC;
1261
1262         out_be32(maccfg2_register, value);
1263         return 0;
1264 }
1265
1266 static int init_preamble_length(u8 preamble_length,
1267                                 u32 __iomem *maccfg2_register)
1268 {
1269         if ((preamble_length < 3) || (preamble_length > 7))
1270                 return -EINVAL;
1271
1272         clrsetbits_be32(maccfg2_register, MACCFG2_PREL_MASK,
1273                         preamble_length << MACCFG2_PREL_SHIFT);
1274
1275         return 0;
1276 }
1277
1278 static int init_rx_parameters(int reject_broadcast,
1279                               int receive_short_frames,
1280                               int promiscuous, u32 __iomem *upsmr_register)
1281 {
1282         u32 value = 0;
1283
1284         value = in_be32(upsmr_register);
1285
1286         if (reject_broadcast)
1287                 value |= UCC_GETH_UPSMR_BRO;
1288         else
1289                 value &= ~UCC_GETH_UPSMR_BRO;
1290
1291         if (receive_short_frames)
1292                 value |= UCC_GETH_UPSMR_RSH;
1293         else
1294                 value &= ~UCC_GETH_UPSMR_RSH;
1295
1296         if (promiscuous)
1297                 value |= UCC_GETH_UPSMR_PRO;
1298         else
1299                 value &= ~UCC_GETH_UPSMR_PRO;
1300
1301         out_be32(upsmr_register, value);
1302
1303         return 0;
1304 }
1305
1306 static int init_max_rx_buff_len(u16 max_rx_buf_len,
1307                                 u16 __iomem *mrblr_register)
1308 {
1309         /* max_rx_buf_len value must be a multiple of 128 */
1310         if ((max_rx_buf_len == 0) ||
1311             (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT))
1312                 return -EINVAL;
1313
1314         out_be16(mrblr_register, max_rx_buf_len);
1315         return 0;
1316 }
1317
1318 static int init_min_frame_len(u16 min_frame_length,
1319                               u16 __iomem *minflr_register,
1320                               u16 __iomem *mrblr_register)
1321 {
1322         u16 mrblr_value = 0;
1323
1324         mrblr_value = in_be16(mrblr_register);
1325         if (min_frame_length >= (mrblr_value - 4))
1326                 return -EINVAL;
1327
1328         out_be16(minflr_register, min_frame_length);
1329         return 0;
1330 }
1331
1332 static int adjust_enet_interface(struct ucc_geth_private *ugeth)
1333 {
1334         struct ucc_geth_info *ug_info;
1335         struct ucc_geth __iomem *ug_regs;
1336         struct ucc_fast __iomem *uf_regs;
1337         int ret_val;
1338         u32 upsmr, maccfg2;
1339         u16 value;
1340
1341         ugeth_vdbg("%s: IN", __func__);
1342
1343         ug_info = ugeth->ug_info;
1344         ug_regs = ugeth->ug_regs;
1345         uf_regs = ugeth->uccf->uf_regs;
1346
1347         /*                    Set MACCFG2                    */
1348         maccfg2 = in_be32(&ug_regs->maccfg2);
1349         maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
1350         if ((ugeth->max_speed == SPEED_10) ||
1351             (ugeth->max_speed == SPEED_100))
1352                 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
1353         else if (ugeth->max_speed == SPEED_1000)
1354                 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
1355         maccfg2 |= ug_info->padAndCrc;
1356         out_be32(&ug_regs->maccfg2, maccfg2);
1357
1358         /*                    Set UPSMR                      */
1359         upsmr = in_be32(&uf_regs->upsmr);
1360         upsmr &= ~(UCC_GETH_UPSMR_RPM | UCC_GETH_UPSMR_R10M |
1361                    UCC_GETH_UPSMR_TBIM | UCC_GETH_UPSMR_RMM);
1362         if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1363             (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1364             (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1365             (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1366             (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
1367             (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1368                 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RMII)
1369                         upsmr |= UCC_GETH_UPSMR_RPM;
1370                 switch (ugeth->max_speed) {
1371                 case SPEED_10:
1372                         upsmr |= UCC_GETH_UPSMR_R10M;
1373                         /* FALLTHROUGH */
1374                 case SPEED_100:
1375                         if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI)
1376                                 upsmr |= UCC_GETH_UPSMR_RMM;
1377                 }
1378         }
1379         if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1380             (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1381                 upsmr |= UCC_GETH_UPSMR_TBIM;
1382         }
1383         if ((ugeth->phy_interface == PHY_INTERFACE_MODE_SGMII))
1384                 upsmr |= UCC_GETH_UPSMR_SGMM;
1385
1386         out_be32(&uf_regs->upsmr, upsmr);
1387
1388         /* Disable autonegotiation in tbi mode, because by default it
1389         comes up in autonegotiation mode. */
1390         /* Note that this depends on proper setting in utbipar register. */
1391         if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1392             (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1393                 struct ucc_geth_info *ug_info = ugeth->ug_info;
1394                 struct phy_device *tbiphy;
1395
1396                 if (!ug_info->tbi_node)
1397                         ugeth_warn("TBI mode requires that the device "
1398                                 "tree specify a tbi-handle\n");
1399
1400                 tbiphy = of_phy_find_device(ug_info->tbi_node);
1401                 if (!tbiphy)
1402                         ugeth_warn("Could not get TBI device\n");
1403
1404                 value = phy_read(tbiphy, ENET_TBI_MII_CR);
1405                 value &= ~0x1000;       /* Turn off autonegotiation */
1406                 phy_write(tbiphy, ENET_TBI_MII_CR, value);
1407         }
1408
1409         init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2);
1410
1411         ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2);
1412         if (ret_val != 0) {
1413                 if (netif_msg_probe(ugeth))
1414                         ugeth_err("%s: Preamble length must be between 3 and 7 inclusive.",
1415                              __func__);
1416                 return ret_val;
1417         }
1418
1419         return 0;
1420 }
1421
1422 static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth)
1423 {
1424         struct ucc_fast_private *uccf;
1425         u32 cecr_subblock;
1426         u32 temp;
1427         int i = 10;
1428
1429         uccf = ugeth->uccf;
1430
1431         /* Mask GRACEFUL STOP TX interrupt bit and clear it */
1432         clrbits32(uccf->p_uccm, UCC_GETH_UCCE_GRA);
1433         out_be32(uccf->p_ucce, UCC_GETH_UCCE_GRA);  /* clear by writing 1 */
1434
1435         /* Issue host command */
1436         cecr_subblock =
1437             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1438         qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
1439                      QE_CR_PROTOCOL_ETHERNET, 0);
1440
1441         /* Wait for command to complete */
1442         do {
1443                 msleep(10);
1444                 temp = in_be32(uccf->p_ucce);
1445         } while (!(temp & UCC_GETH_UCCE_GRA) && --i);
1446
1447         uccf->stopped_tx = 1;
1448
1449         return 0;
1450 }
1451
1452 static int ugeth_graceful_stop_rx(struct ucc_geth_private *ugeth)
1453 {
1454         struct ucc_fast_private *uccf;
1455         u32 cecr_subblock;
1456         u8 temp;
1457         int i = 10;
1458
1459         uccf = ugeth->uccf;
1460
1461         /* Clear acknowledge bit */
1462         temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1463         temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
1464         out_8(&ugeth->p_rx_glbl_pram->rxgstpack, temp);
1465
1466         /* Keep issuing command and checking acknowledge bit until
1467         it is asserted, according to spec */
1468         do {
1469                 /* Issue host command */
1470                 cecr_subblock =
1471                     ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.
1472                                                 ucc_num);
1473                 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
1474                              QE_CR_PROTOCOL_ETHERNET, 0);
1475                 msleep(10);
1476                 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1477         } while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX) && --i);
1478
1479         uccf->stopped_rx = 1;
1480
1481         return 0;
1482 }
1483
1484 static int ugeth_restart_tx(struct ucc_geth_private *ugeth)
1485 {
1486         struct ucc_fast_private *uccf;
1487         u32 cecr_subblock;
1488
1489         uccf = ugeth->uccf;
1490
1491         cecr_subblock =
1492             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1493         qe_issue_cmd(QE_RESTART_TX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 0);
1494         uccf->stopped_tx = 0;
1495
1496         return 0;
1497 }
1498
1499 static int ugeth_restart_rx(struct ucc_geth_private *ugeth)
1500 {
1501         struct ucc_fast_private *uccf;
1502         u32 cecr_subblock;
1503
1504         uccf = ugeth->uccf;
1505
1506         cecr_subblock =
1507             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1508         qe_issue_cmd(QE_RESTART_RX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
1509                      0);
1510         uccf->stopped_rx = 0;
1511
1512         return 0;
1513 }
1514
1515 static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1516 {
1517         struct ucc_fast_private *uccf;
1518         int enabled_tx, enabled_rx;
1519
1520         uccf = ugeth->uccf;
1521
1522         /* check if the UCC number is in range. */
1523         if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1524                 if (netif_msg_probe(ugeth))
1525                         ugeth_err("%s: ucc_num out of range.", __func__);
1526                 return -EINVAL;
1527         }
1528
1529         enabled_tx = uccf->enabled_tx;
1530         enabled_rx = uccf->enabled_rx;
1531
1532         /* Get Tx and Rx going again, in case this channel was actively
1533         disabled. */
1534         if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx)
1535                 ugeth_restart_tx(ugeth);
1536         if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx)
1537                 ugeth_restart_rx(ugeth);
1538
1539         ucc_fast_enable(uccf, mode);    /* OK to do even if not disabled */
1540
1541         return 0;
1542
1543 }
1544
1545 static int ugeth_disable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1546 {
1547         struct ucc_fast_private *uccf;
1548
1549         uccf = ugeth->uccf;
1550
1551         /* check if the UCC number is in range. */
1552         if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1553                 if (netif_msg_probe(ugeth))
1554                         ugeth_err("%s: ucc_num out of range.", __func__);
1555                 return -EINVAL;
1556         }
1557
1558         /* Stop any transmissions */
1559         if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx)
1560                 ugeth_graceful_stop_tx(ugeth);
1561
1562         /* Stop any receptions */
1563         if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx)
1564                 ugeth_graceful_stop_rx(ugeth);
1565
1566         ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */
1567
1568         return 0;
1569 }
1570
1571 static void ugeth_quiesce(struct ucc_geth_private *ugeth)
1572 {
1573         /* Prevent any further xmits, plus detach the device. */
1574         netif_device_detach(ugeth->ndev);
1575
1576         /* Wait for any current xmits to finish. */
1577         netif_tx_disable(ugeth->ndev);
1578
1579         /* Disable the interrupt to avoid NAPI rescheduling. */
1580         disable_irq(ugeth->ug_info->uf_info.irq);
1581
1582         /* Stop NAPI, and possibly wait for its completion. */
1583         napi_disable(&ugeth->napi);
1584 }
1585
1586 static void ugeth_activate(struct ucc_geth_private *ugeth)
1587 {
1588         napi_enable(&ugeth->napi);
1589         enable_irq(ugeth->ug_info->uf_info.irq);
1590         netif_device_attach(ugeth->ndev);
1591 }
1592
1593 /* Called every time the controller might need to be made
1594  * aware of new link state.  The PHY code conveys this
1595  * information through variables in the ugeth structure, and this
1596  * function converts those variables into the appropriate
1597  * register values, and can bring down the device if needed.
1598  */
1599
1600 static void adjust_link(struct net_device *dev)
1601 {
1602         struct ucc_geth_private *ugeth = netdev_priv(dev);
1603         struct ucc_geth __iomem *ug_regs;
1604         struct ucc_fast __iomem *uf_regs;
1605         struct phy_device *phydev = ugeth->phydev;
1606         int new_state = 0;
1607
1608         ug_regs = ugeth->ug_regs;
1609         uf_regs = ugeth->uccf->uf_regs;
1610
1611         if (phydev->link) {
1612                 u32 tempval = in_be32(&ug_regs->maccfg2);
1613                 u32 upsmr = in_be32(&uf_regs->upsmr);
1614                 /* Now we make sure that we can be in full duplex mode.
1615                  * If not, we operate in half-duplex mode. */
1616                 if (phydev->duplex != ugeth->oldduplex) {
1617                         new_state = 1;
1618                         if (!(phydev->duplex))
1619                                 tempval &= ~(MACCFG2_FDX);
1620                         else
1621                                 tempval |= MACCFG2_FDX;
1622                         ugeth->oldduplex = phydev->duplex;
1623                 }
1624
1625                 if (phydev->speed != ugeth->oldspeed) {
1626                         new_state = 1;
1627                         switch (phydev->speed) {
1628                         case SPEED_1000:
1629                                 tempval = ((tempval &
1630                                             ~(MACCFG2_INTERFACE_MODE_MASK)) |
1631                                             MACCFG2_INTERFACE_MODE_BYTE);
1632                                 break;
1633                         case SPEED_100:
1634                         case SPEED_10:
1635                                 tempval = ((tempval &
1636                                             ~(MACCFG2_INTERFACE_MODE_MASK)) |
1637                                             MACCFG2_INTERFACE_MODE_NIBBLE);
1638                                 /* if reduced mode, re-set UPSMR.R10M */
1639                                 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1640                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1641                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1642                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1643                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
1644                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1645                                         if (phydev->speed == SPEED_10)
1646                                                 upsmr |= UCC_GETH_UPSMR_R10M;
1647                                         else
1648                                                 upsmr &= ~UCC_GETH_UPSMR_R10M;
1649                                 }
1650                                 break;
1651                         default:
1652                                 if (netif_msg_link(ugeth))
1653                                         ugeth_warn(
1654                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!",
1655                                                 dev->name, phydev->speed);
1656                                 break;
1657                         }
1658                         ugeth->oldspeed = phydev->speed;
1659                 }
1660
1661                 if (!ugeth->oldlink) {
1662                         new_state = 1;
1663                         ugeth->oldlink = 1;
1664                 }
1665
1666                 if (new_state) {
1667                         /*
1668                          * To change the MAC configuration we need to disable
1669                          * the controller. To do so, we have to either grab
1670                          * ugeth->lock, which is a bad idea since 'graceful
1671                          * stop' commands might take quite a while, or we can
1672                          * quiesce driver's activity.
1673                          */
1674                         ugeth_quiesce(ugeth);
1675                         ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
1676
1677                         out_be32(&ug_regs->maccfg2, tempval);
1678                         out_be32(&uf_regs->upsmr, upsmr);
1679
1680                         ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
1681                         ugeth_activate(ugeth);
1682                 }
1683         } else if (ugeth->oldlink) {
1684                         new_state = 1;
1685                         ugeth->oldlink = 0;
1686                         ugeth->oldspeed = 0;
1687                         ugeth->oldduplex = -1;
1688         }
1689
1690         if (new_state && netif_msg_link(ugeth))
1691                 phy_print_status(phydev);
1692 }
1693
1694 /* Initialize TBI PHY interface for communicating with the
1695  * SERDES lynx PHY on the chip.  We communicate with this PHY
1696  * through the MDIO bus on each controller, treating it as a
1697  * "normal" PHY at the address found in the UTBIPA register.  We assume
1698  * that the UTBIPA register is valid.  Either the MDIO bus code will set
1699  * it to a value that doesn't conflict with other PHYs on the bus, or the
1700  * value doesn't matter, as there are no other PHYs on the bus.
1701  */
1702 static void uec_configure_serdes(struct net_device *dev)
1703 {
1704         struct ucc_geth_private *ugeth = netdev_priv(dev);
1705         struct ucc_geth_info *ug_info = ugeth->ug_info;
1706         struct phy_device *tbiphy;
1707
1708         if (!ug_info->tbi_node) {
1709                 dev_warn(&dev->dev, "SGMII mode requires that the device "
1710                         "tree specify a tbi-handle\n");
1711                 return;
1712         }
1713
1714         tbiphy = of_phy_find_device(ug_info->tbi_node);
1715         if (!tbiphy) {
1716                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1717                 return;
1718         }
1719
1720         /*
1721          * If the link is already up, we must already be ok, and don't need to
1722          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1723          * everything for us?  Resetting it takes the link down and requires
1724          * several seconds for it to come back.
1725          */
1726         if (phy_read(tbiphy, ENET_TBI_MII_SR) & TBISR_LSTATUS)
1727                 return;
1728
1729         /* Single clk mode, mii mode off(for serdes communication) */
1730         phy_write(tbiphy, ENET_TBI_MII_ANA, TBIANA_SETTINGS);
1731
1732         phy_write(tbiphy, ENET_TBI_MII_TBICON, TBICON_CLK_SELECT);
1733
1734         phy_write(tbiphy, ENET_TBI_MII_CR, TBICR_SETTINGS);
1735 }
1736
1737 /* Configure the PHY for dev.
1738  * returns 0 if success.  -1 if failure
1739  */
1740 static int init_phy(struct net_device *dev)
1741 {
1742         struct ucc_geth_private *priv = netdev_priv(dev);
1743         struct ucc_geth_info *ug_info = priv->ug_info;
1744         struct phy_device *phydev;
1745
1746         priv->oldlink = 0;
1747         priv->oldspeed = 0;
1748         priv->oldduplex = -1;
1749
1750         phydev = of_phy_connect(dev, ug_info->phy_node, &adjust_link, 0,
1751                                 priv->phy_interface);
1752         if (!phydev)
1753                 phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1754                                                    priv->phy_interface);
1755         if (!phydev) {
1756                 dev_err(&dev->dev, "Could not attach to PHY\n");
1757                 return -ENODEV;
1758         }
1759
1760         if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII)
1761                 uec_configure_serdes(dev);
1762
1763         phydev->supported &= (ADVERTISED_10baseT_Half |
1764                                  ADVERTISED_10baseT_Full |
1765                                  ADVERTISED_100baseT_Half |
1766                                  ADVERTISED_100baseT_Full);
1767
1768         if (priv->max_speed == SPEED_1000)
1769                 phydev->supported |= ADVERTISED_1000baseT_Full;
1770
1771         phydev->advertising = phydev->supported;
1772
1773         priv->phydev = phydev;
1774
1775         return 0;
1776 }
1777
1778 static void ugeth_dump_regs(struct ucc_geth_private *ugeth)
1779 {
1780 #ifdef DEBUG
1781         ucc_fast_dump_regs(ugeth->uccf);
1782         dump_regs(ugeth);
1783         dump_bds(ugeth);
1784 #endif
1785 }
1786
1787 static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private *
1788                                                        ugeth,
1789                                                        enum enet_addr_type
1790                                                        enet_addr_type)
1791 {
1792         struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
1793         struct ucc_fast_private *uccf;
1794         enum comm_dir comm_dir;
1795         struct list_head *p_lh;
1796         u16 i, num;
1797         u32 __iomem *addr_h;
1798         u32 __iomem *addr_l;
1799         u8 *p_counter;
1800
1801         uccf = ugeth->uccf;
1802
1803         p_82xx_addr_filt =
1804             (struct ucc_geth_82xx_address_filtering_pram __iomem *)
1805             ugeth->p_rx_glbl_pram->addressfiltering;
1806
1807         if (enet_addr_type == ENET_ADDR_TYPE_GROUP) {
1808                 addr_h = &(p_82xx_addr_filt->gaddr_h);
1809                 addr_l = &(p_82xx_addr_filt->gaddr_l);
1810                 p_lh = &ugeth->group_hash_q;
1811                 p_counter = &(ugeth->numGroupAddrInHash);
1812         } else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) {
1813                 addr_h = &(p_82xx_addr_filt->iaddr_h);
1814                 addr_l = &(p_82xx_addr_filt->iaddr_l);
1815                 p_lh = &ugeth->ind_hash_q;
1816                 p_counter = &(ugeth->numIndAddrInHash);
1817         } else
1818                 return -EINVAL;
1819
1820         comm_dir = 0;
1821         if (uccf->enabled_tx)
1822                 comm_dir |= COMM_DIR_TX;
1823         if (uccf->enabled_rx)
1824                 comm_dir |= COMM_DIR_RX;
1825         if (comm_dir)
1826                 ugeth_disable(ugeth, comm_dir);
1827
1828         /* Clear the hash table. */
1829         out_be32(addr_h, 0x00000000);
1830         out_be32(addr_l, 0x00000000);
1831
1832         if (!p_lh)
1833                 return 0;
1834
1835         num = *p_counter;
1836
1837         /* Delete all remaining CQ elements */
1838         for (i = 0; i < num; i++)
1839                 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh)));
1840
1841         *p_counter = 0;
1842
1843         if (comm_dir)
1844                 ugeth_enable(ugeth, comm_dir);
1845
1846         return 0;
1847 }
1848
1849 static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth,
1850                                                     u8 paddr_num)
1851 {
1852         ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */
1853         return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */
1854 }
1855
1856 static void ucc_geth_memclean(struct ucc_geth_private *ugeth)
1857 {
1858         u16 i, j;
1859         u8 __iomem *bd;
1860
1861         if (!ugeth)
1862                 return;
1863
1864         if (ugeth->uccf) {
1865                 ucc_fast_free(ugeth->uccf);
1866                 ugeth->uccf = NULL;
1867         }
1868
1869         if (ugeth->p_thread_data_tx) {
1870                 qe_muram_free(ugeth->thread_dat_tx_offset);
1871                 ugeth->p_thread_data_tx = NULL;
1872         }
1873         if (ugeth->p_thread_data_rx) {
1874                 qe_muram_free(ugeth->thread_dat_rx_offset);
1875                 ugeth->p_thread_data_rx = NULL;
1876         }
1877         if (ugeth->p_exf_glbl_param) {
1878                 qe_muram_free(ugeth->exf_glbl_param_offset);
1879                 ugeth->p_exf_glbl_param = NULL;
1880         }
1881         if (ugeth->p_rx_glbl_pram) {
1882                 qe_muram_free(ugeth->rx_glbl_pram_offset);
1883                 ugeth->p_rx_glbl_pram = NULL;
1884         }
1885         if (ugeth->p_tx_glbl_pram) {
1886                 qe_muram_free(ugeth->tx_glbl_pram_offset);
1887                 ugeth->p_tx_glbl_pram = NULL;
1888         }
1889         if (ugeth->p_send_q_mem_reg) {
1890                 qe_muram_free(ugeth->send_q_mem_reg_offset);
1891                 ugeth->p_send_q_mem_reg = NULL;
1892         }
1893         if (ugeth->p_scheduler) {
1894                 qe_muram_free(ugeth->scheduler_offset);
1895                 ugeth->p_scheduler = NULL;
1896         }
1897         if (ugeth->p_tx_fw_statistics_pram) {
1898                 qe_muram_free(ugeth->tx_fw_statistics_pram_offset);
1899                 ugeth->p_tx_fw_statistics_pram = NULL;
1900         }
1901         if (ugeth->p_rx_fw_statistics_pram) {
1902                 qe_muram_free(ugeth->rx_fw_statistics_pram_offset);
1903                 ugeth->p_rx_fw_statistics_pram = NULL;
1904         }
1905         if (ugeth->p_rx_irq_coalescing_tbl) {
1906                 qe_muram_free(ugeth->rx_irq_coalescing_tbl_offset);
1907                 ugeth->p_rx_irq_coalescing_tbl = NULL;
1908         }
1909         if (ugeth->p_rx_bd_qs_tbl) {
1910                 qe_muram_free(ugeth->rx_bd_qs_tbl_offset);
1911                 ugeth->p_rx_bd_qs_tbl = NULL;
1912         }
1913         if (ugeth->p_init_enet_param_shadow) {
1914                 return_init_enet_entries(ugeth,
1915                                          &(ugeth->p_init_enet_param_shadow->
1916                                            rxthread[0]),
1917                                          ENET_INIT_PARAM_MAX_ENTRIES_RX,
1918                                          ugeth->ug_info->riscRx, 1);
1919                 return_init_enet_entries(ugeth,
1920                                          &(ugeth->p_init_enet_param_shadow->
1921                                            txthread[0]),
1922                                          ENET_INIT_PARAM_MAX_ENTRIES_TX,
1923                                          ugeth->ug_info->riscTx, 0);
1924                 kfree(ugeth->p_init_enet_param_shadow);
1925                 ugeth->p_init_enet_param_shadow = NULL;
1926         }
1927         for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
1928                 bd = ugeth->p_tx_bd_ring[i];
1929                 if (!bd)
1930                         continue;
1931                 for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) {
1932                         if (ugeth->tx_skbuff[i][j]) {
1933                                 dma_unmap_single(ugeth->dev,
1934                                                  in_be32(&((struct qe_bd __iomem *)bd)->buf),
1935                                                  (in_be32((u32 __iomem *)bd) &
1936                                                   BD_LENGTH_MASK),
1937                                                  DMA_TO_DEVICE);
1938                                 dev_kfree_skb_any(ugeth->tx_skbuff[i][j]);
1939                                 ugeth->tx_skbuff[i][j] = NULL;
1940                         }
1941                 }
1942
1943                 kfree(ugeth->tx_skbuff[i]);
1944
1945                 if (ugeth->p_tx_bd_ring[i]) {
1946                         if (ugeth->ug_info->uf_info.bd_mem_part ==
1947                             MEM_PART_SYSTEM)
1948                                 kfree((void *)ugeth->tx_bd_ring_offset[i]);
1949                         else if (ugeth->ug_info->uf_info.bd_mem_part ==
1950                                  MEM_PART_MURAM)
1951                                 qe_muram_free(ugeth->tx_bd_ring_offset[i]);
1952                         ugeth->p_tx_bd_ring[i] = NULL;
1953                 }
1954         }
1955         for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1956                 if (ugeth->p_rx_bd_ring[i]) {
1957                         /* Return existing data buffers in ring */
1958                         bd = ugeth->p_rx_bd_ring[i];
1959                         for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) {
1960                                 if (ugeth->rx_skbuff[i][j]) {
1961                                         dma_unmap_single(ugeth->dev,
1962                                                 in_be32(&((struct qe_bd __iomem *)bd)->buf),
1963                                                 ugeth->ug_info->
1964                                                 uf_info.max_rx_buf_length +
1965                                                 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
1966                                                 DMA_FROM_DEVICE);
1967                                         dev_kfree_skb_any(
1968                                                 ugeth->rx_skbuff[i][j]);
1969                                         ugeth->rx_skbuff[i][j] = NULL;
1970                                 }
1971                                 bd += sizeof(struct qe_bd);
1972                         }
1973
1974                         kfree(ugeth->rx_skbuff[i]);
1975
1976                         if (ugeth->ug_info->uf_info.bd_mem_part ==
1977                             MEM_PART_SYSTEM)
1978                                 kfree((void *)ugeth->rx_bd_ring_offset[i]);
1979                         else if (ugeth->ug_info->uf_info.bd_mem_part ==
1980                                  MEM_PART_MURAM)
1981                                 qe_muram_free(ugeth->rx_bd_ring_offset[i]);
1982                         ugeth->p_rx_bd_ring[i] = NULL;
1983                 }
1984         }
1985         while (!list_empty(&ugeth->group_hash_q))
1986                 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1987                                         (dequeue(&ugeth->group_hash_q)));
1988         while (!list_empty(&ugeth->ind_hash_q))
1989                 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1990                                         (dequeue(&ugeth->ind_hash_q)));
1991         if (ugeth->ug_regs) {
1992                 iounmap(ugeth->ug_regs);
1993                 ugeth->ug_regs = NULL;
1994         }
1995
1996         skb_queue_purge(&ugeth->rx_recycle);
1997 }
1998
1999 static void ucc_geth_set_multi(struct net_device *dev)
2000 {
2001         struct ucc_geth_private *ugeth;
2002         struct dev_mc_list *dmi;
2003         struct ucc_fast __iomem *uf_regs;
2004         struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
2005         int i;
2006
2007         ugeth = netdev_priv(dev);
2008
2009         uf_regs = ugeth->uccf->uf_regs;
2010
2011         if (dev->flags & IFF_PROMISC) {
2012                 setbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
2013         } else {
2014                 clrbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
2015
2016                 p_82xx_addr_filt =
2017                     (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
2018                     p_rx_glbl_pram->addressfiltering;
2019
2020                 if (dev->flags & IFF_ALLMULTI) {
2021                         /* Catch all multicast addresses, so set the
2022                          * filter to all 1's.
2023                          */
2024                         out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff);
2025                         out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff);
2026                 } else {
2027                         /* Clear filter and add the addresses in the list.
2028                          */
2029                         out_be32(&p_82xx_addr_filt->gaddr_h, 0x0);
2030                         out_be32(&p_82xx_addr_filt->gaddr_l, 0x0);
2031
2032                         dmi = dev->mc_list;
2033
2034                         for (i = 0; i < dev->mc_count; i++, dmi = dmi->next) {
2035
2036                                 /* Only support group multicast for now.
2037                                  */
2038                                 if (!(dmi->dmi_addr[0] & 1))
2039                                         continue;
2040
2041                                 /* Ask CPM to run CRC and set bit in
2042                                  * filter mask.
2043                                  */
2044                                 hw_add_addr_in_hash(ugeth, dmi->dmi_addr);
2045                         }
2046                 }
2047         }
2048 }
2049
2050 static void ucc_geth_stop(struct ucc_geth_private *ugeth)
2051 {
2052         struct ucc_geth __iomem *ug_regs = ugeth->ug_regs;
2053         struct phy_device *phydev = ugeth->phydev;
2054
2055         ugeth_vdbg("%s: IN", __func__);
2056
2057         /* Disable the controller */
2058         ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
2059
2060         /* Tell the kernel the link is down */
2061         phy_stop(phydev);
2062
2063         /* Mask all interrupts */
2064         out_be32(ugeth->uccf->p_uccm, 0x00000000);
2065
2066         /* Clear all interrupts */
2067         out_be32(ugeth->uccf->p_ucce, 0xffffffff);
2068
2069         /* Disable Rx and Tx */
2070         clrbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2071
2072         phy_disconnect(ugeth->phydev);
2073         ugeth->phydev = NULL;
2074
2075         ucc_geth_memclean(ugeth);
2076 }
2077
2078 static int ucc_struct_init(struct ucc_geth_private *ugeth)
2079 {
2080         struct ucc_geth_info *ug_info;
2081         struct ucc_fast_info *uf_info;
2082         int i;
2083
2084         ug_info = ugeth->ug_info;
2085         uf_info = &ug_info->uf_info;
2086
2087         if (!((uf_info->bd_mem_part == MEM_PART_SYSTEM) ||
2088               (uf_info->bd_mem_part == MEM_PART_MURAM))) {
2089                 if (netif_msg_probe(ugeth))
2090                         ugeth_err("%s: Bad memory partition value.",
2091                                         __func__);
2092                 return -EINVAL;
2093         }
2094
2095         /* Rx BD lengths */
2096         for (i = 0; i < ug_info->numQueuesRx; i++) {
2097                 if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) ||
2098                     (ug_info->bdRingLenRx[i] %
2099                      UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) {
2100                         if (netif_msg_probe(ugeth))
2101                                 ugeth_err
2102                                     ("%s: Rx BD ring length must be multiple of 4, no smaller than 8.",
2103                                         __func__);
2104                         return -EINVAL;
2105                 }
2106         }
2107
2108         /* Tx BD lengths */
2109         for (i = 0; i < ug_info->numQueuesTx; i++) {
2110                 if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) {
2111                         if (netif_msg_probe(ugeth))
2112                                 ugeth_err
2113                                     ("%s: Tx BD ring length must be no smaller than 2.",
2114                                      __func__);
2115                         return -EINVAL;
2116                 }
2117         }
2118
2119         /* mrblr */
2120         if ((uf_info->max_rx_buf_length == 0) ||
2121             (uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) {
2122                 if (netif_msg_probe(ugeth))
2123                         ugeth_err
2124                             ("%s: max_rx_buf_length must be non-zero multiple of 128.",
2125                              __func__);
2126                 return -EINVAL;
2127         }
2128
2129         /* num Tx queues */
2130         if (ug_info->numQueuesTx > NUM_TX_QUEUES) {
2131                 if (netif_msg_probe(ugeth))
2132                         ugeth_err("%s: number of tx queues too large.", __func__);
2133                 return -EINVAL;
2134         }
2135
2136         /* num Rx queues */
2137         if (ug_info->numQueuesRx > NUM_RX_QUEUES) {
2138                 if (netif_msg_probe(ugeth))
2139                         ugeth_err("%s: number of rx queues too large.", __func__);
2140                 return -EINVAL;
2141         }
2142
2143         /* l2qt */
2144         for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) {
2145                 if (ug_info->l2qt[i] >= ug_info->numQueuesRx) {
2146                         if (netif_msg_probe(ugeth))
2147                                 ugeth_err
2148                                     ("%s: VLAN priority table entry must not be"
2149                                         " larger than number of Rx queues.",
2150                                      __func__);
2151                         return -EINVAL;
2152                 }
2153         }
2154
2155         /* l3qt */
2156         for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) {
2157                 if (ug_info->l3qt[i] >= ug_info->numQueuesRx) {
2158                         if (netif_msg_probe(ugeth))
2159                                 ugeth_err
2160                                     ("%s: IP priority table entry must not be"
2161                                         " larger than number of Rx queues.",
2162                                      __func__);
2163                         return -EINVAL;
2164                 }
2165         }
2166
2167         if (ug_info->cam && !ug_info->ecamptr) {
2168                 if (netif_msg_probe(ugeth))
2169                         ugeth_err("%s: If cam mode is chosen, must supply cam ptr.",
2170                                   __func__);
2171                 return -EINVAL;
2172         }
2173
2174         if ((ug_info->numStationAddresses !=
2175              UCC_GETH_NUM_OF_STATION_ADDRESSES_1) &&
2176             ug_info->rxExtendedFiltering) {
2177                 if (netif_msg_probe(ugeth))
2178                         ugeth_err("%s: Number of station addresses greater than 1 "
2179                                   "not allowed in extended parsing mode.",
2180                                   __func__);
2181                 return -EINVAL;
2182         }
2183
2184         /* Generate uccm_mask for receive */
2185         uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */
2186         for (i = 0; i < ug_info->numQueuesRx; i++)
2187                 uf_info->uccm_mask |= (UCC_GETH_UCCE_RXF0 << i);
2188
2189         for (i = 0; i < ug_info->numQueuesTx; i++)
2190                 uf_info->uccm_mask |= (UCC_GETH_UCCE_TXB0 << i);
2191         /* Initialize the general fast UCC block. */
2192         if (ucc_fast_init(uf_info, &ugeth->uccf)) {
2193                 if (netif_msg_probe(ugeth))
2194                         ugeth_err("%s: Failed to init uccf.", __func__);
2195                 return -ENOMEM;
2196         }
2197
2198         /* read the number of risc engines, update the riscTx and riscRx
2199          * if there are 4 riscs in QE
2200          */
2201         if (qe_get_num_of_risc() == 4) {
2202                 ug_info->riscTx = QE_RISC_ALLOCATION_FOUR_RISCS;
2203                 ug_info->riscRx = QE_RISC_ALLOCATION_FOUR_RISCS;
2204         }
2205
2206         ugeth->ug_regs = ioremap(uf_info->regs, sizeof(*ugeth->ug_regs));
2207         if (!ugeth->ug_regs) {
2208                 if (netif_msg_probe(ugeth))
2209                         ugeth_err("%s: Failed to ioremap regs.", __func__);
2210                 return -ENOMEM;
2211         }
2212
2213         skb_queue_head_init(&ugeth->rx_recycle);
2214
2215         return 0;
2216 }
2217
2218 static int ucc_geth_startup(struct ucc_geth_private *ugeth)
2219 {
2220         struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
2221         struct ucc_geth_init_pram __iomem *p_init_enet_pram;
2222         struct ucc_fast_private *uccf;
2223         struct ucc_geth_info *ug_info;
2224         struct ucc_fast_info *uf_info;
2225         struct ucc_fast __iomem *uf_regs;
2226         struct ucc_geth __iomem *ug_regs;
2227         int ret_val = -EINVAL;
2228         u32 remoder = UCC_GETH_REMODER_INIT;
2229         u32 init_enet_pram_offset, cecr_subblock, command;
2230         u32 ifstat, i, j, size, l2qt, l3qt, length;
2231         u16 temoder = UCC_GETH_TEMODER_INIT;
2232         u16 test;
2233         u8 function_code = 0;
2234         u8 __iomem *bd;
2235         u8 __iomem *endOfRing;
2236         u8 numThreadsRxNumerical, numThreadsTxNumerical;
2237
2238         ugeth_vdbg("%s: IN", __func__);
2239         uccf = ugeth->uccf;
2240         ug_info = ugeth->ug_info;
2241         uf_info = &ug_info->uf_info;
2242         uf_regs = uccf->uf_regs;
2243         ug_regs = ugeth->ug_regs;
2244
2245         switch (ug_info->numThreadsRx) {
2246         case UCC_GETH_NUM_OF_THREADS_1:
2247                 numThreadsRxNumerical = 1;
2248                 break;
2249         case UCC_GETH_NUM_OF_THREADS_2:
2250                 numThreadsRxNumerical = 2;
2251                 break;
2252         case UCC_GETH_NUM_OF_THREADS_4:
2253                 numThreadsRxNumerical = 4;
2254                 break;
2255         case UCC_GETH_NUM_OF_THREADS_6:
2256                 numThreadsRxNumerical = 6;
2257                 break;
2258         case UCC_GETH_NUM_OF_THREADS_8:
2259                 numThreadsRxNumerical = 8;
2260                 break;
2261         default:
2262                 if (netif_msg_ifup(ugeth))
2263                         ugeth_err("%s: Bad number of Rx threads value.",
2264                                         __func__);
2265                 return -EINVAL;
2266                 break;
2267         }
2268
2269         switch (ug_info->numThreadsTx) {
2270         case UCC_GETH_NUM_OF_THREADS_1:
2271                 numThreadsTxNumerical = 1;
2272                 break;
2273         case UCC_GETH_NUM_OF_THREADS_2:
2274                 numThreadsTxNumerical = 2;
2275                 break;
2276         case UCC_GETH_NUM_OF_THREADS_4:
2277                 numThreadsTxNumerical = 4;
2278                 break;
2279         case UCC_GETH_NUM_OF_THREADS_6:
2280                 numThreadsTxNumerical = 6;
2281                 break;
2282         case UCC_GETH_NUM_OF_THREADS_8:
2283                 numThreadsTxNumerical = 8;
2284                 break;
2285         default:
2286                 if (netif_msg_ifup(ugeth))
2287                         ugeth_err("%s: Bad number of Tx threads value.",
2288                                         __func__);
2289                 return -EINVAL;
2290                 break;
2291         }
2292
2293         /* Calculate rx_extended_features */
2294         ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck ||
2295             ug_info->ipAddressAlignment ||
2296             (ug_info->numStationAddresses !=
2297              UCC_GETH_NUM_OF_STATION_ADDRESSES_1);
2298
2299         ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features ||
2300                 (ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP) ||
2301                 (ug_info->vlanOperationNonTagged !=
2302                  UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP);
2303
2304         init_default_reg_vals(&uf_regs->upsmr,
2305                               &ug_regs->maccfg1, &ug_regs->maccfg2);
2306
2307         /*                    Set UPSMR                      */
2308         /* For more details see the hardware spec.           */
2309         init_rx_parameters(ug_info->bro,
2310                            ug_info->rsh, ug_info->pro, &uf_regs->upsmr);
2311
2312         /* We're going to ignore other registers for now, */
2313         /* except as needed to get up and running         */
2314
2315         /*                    Set MACCFG1                    */
2316         /* For more details see the hardware spec.           */
2317         init_flow_control_params(ug_info->aufc,
2318                                  ug_info->receiveFlowControl,
2319                                  ug_info->transmitFlowControl,
2320                                  ug_info->pausePeriod,
2321                                  ug_info->extensionField,
2322                                  &uf_regs->upsmr,
2323                                  &ug_regs->uempr, &ug_regs->maccfg1);
2324
2325         setbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2326
2327         /*                    Set IPGIFG                     */
2328         /* For more details see the hardware spec.           */
2329         ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1,
2330                                               ug_info->nonBackToBackIfgPart2,
2331                                               ug_info->
2332                                               miminumInterFrameGapEnforcement,
2333                                               ug_info->backToBackInterFrameGap,
2334                                               &ug_regs->ipgifg);
2335         if (ret_val != 0) {
2336                 if (netif_msg_ifup(ugeth))
2337                         ugeth_err("%s: IPGIFG initialization parameter too large.",
2338                                   __func__);
2339                 return ret_val;
2340         }
2341
2342         /*                    Set HAFDUP                     */
2343         /* For more details see the hardware spec.           */
2344         ret_val = init_half_duplex_params(ug_info->altBeb,
2345                                           ug_info->backPressureNoBackoff,
2346                                           ug_info->noBackoff,
2347                                           ug_info->excessDefer,
2348                                           ug_info->altBebTruncation,
2349                                           ug_info->maxRetransmission,
2350                                           ug_info->collisionWindow,
2351                                           &ug_regs->hafdup);
2352         if (ret_val != 0) {
2353                 if (netif_msg_ifup(ugeth))
2354                         ugeth_err("%s: Half Duplex initialization parameter too large.",
2355                           __func__);
2356                 return ret_val;
2357         }
2358
2359         /*                    Set IFSTAT                     */
2360         /* For more details see the hardware spec.           */
2361         /* Read only - resets upon read                      */
2362         ifstat = in_be32(&ug_regs->ifstat);
2363
2364         /*                    Clear UEMPR                    */
2365         /* For more details see the hardware spec.           */
2366         out_be32(&ug_regs->uempr, 0);
2367
2368         /*                    Set UESCR                      */
2369         /* For more details see the hardware spec.           */
2370         init_hw_statistics_gathering_mode((ug_info->statisticsMode &
2371                                 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE),
2372                                 0, &uf_regs->upsmr, &ug_regs->uescr);
2373
2374         /* Allocate Tx bds */
2375         for (j = 0; j < ug_info->numQueuesTx; j++) {
2376                 /* Allocate in multiple of
2377                    UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT,
2378                    according to spec */
2379                 length = ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd))
2380                           / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2381                     * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2382                 if ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) %
2383                     UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2384                         length += UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2385                 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2386                         u32 align = 4;
2387                         if (UCC_GETH_TX_BD_RING_ALIGNMENT > 4)
2388                                 align = UCC_GETH_TX_BD_RING_ALIGNMENT;
2389                         ugeth->tx_bd_ring_offset[j] =
2390                                 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
2391
2392                         if (ugeth->tx_bd_ring_offset[j] != 0)
2393                                 ugeth->p_tx_bd_ring[j] =
2394                                         (u8 __iomem *)((ugeth->tx_bd_ring_offset[j] +
2395                                         align) & ~(align - 1));
2396                 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2397                         ugeth->tx_bd_ring_offset[j] =
2398                             qe_muram_alloc(length,
2399                                            UCC_GETH_TX_BD_RING_ALIGNMENT);
2400                         if (!IS_ERR_VALUE(ugeth->tx_bd_ring_offset[j]))
2401                                 ugeth->p_tx_bd_ring[j] =
2402                                     (u8 __iomem *) qe_muram_addr(ugeth->
2403                                                          tx_bd_ring_offset[j]);
2404                 }
2405                 if (!ugeth->p_tx_bd_ring[j]) {
2406                         if (netif_msg_ifup(ugeth))
2407                                 ugeth_err
2408                                     ("%s: Can not allocate memory for Tx bd rings.",
2409                                      __func__);
2410                         return -ENOMEM;
2411                 }
2412                 /* Zero unused end of bd ring, according to spec */
2413                 memset_io((void __iomem *)(ugeth->p_tx_bd_ring[j] +
2414                        ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)), 0,
2415                        length - ug_info->bdRingLenTx[j] * sizeof(struct qe_bd));
2416         }
2417
2418         /* Allocate Rx bds */
2419         for (j = 0; j < ug_info->numQueuesRx; j++) {
2420                 length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd);
2421                 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2422                         u32 align = 4;
2423                         if (UCC_GETH_RX_BD_RING_ALIGNMENT > 4)
2424                                 align = UCC_GETH_RX_BD_RING_ALIGNMENT;
2425                         ugeth->rx_bd_ring_offset[j] =
2426                                 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
2427                         if (ugeth->rx_bd_ring_offset[j] != 0)
2428                                 ugeth->p_rx_bd_ring[j] =
2429                                         (u8 __iomem *)((ugeth->rx_bd_ring_offset[j] +
2430                                         align) & ~(align - 1));
2431                 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2432                         ugeth->rx_bd_ring_offset[j] =
2433                             qe_muram_alloc(length,
2434                                            UCC_GETH_RX_BD_RING_ALIGNMENT);
2435                         if (!IS_ERR_VALUE(ugeth->rx_bd_ring_offset[j]))
2436                                 ugeth->p_rx_bd_ring[j] =
2437                                     (u8 __iomem *) qe_muram_addr(ugeth->
2438                                                          rx_bd_ring_offset[j]);
2439                 }
2440                 if (!ugeth->p_rx_bd_ring[j]) {
2441                         if (netif_msg_ifup(ugeth))
2442                                 ugeth_err
2443                                     ("%s: Can not allocate memory for Rx bd rings.",
2444                                      __func__);
2445                         return -ENOMEM;
2446                 }
2447         }
2448
2449         /* Init Tx bds */
2450         for (j = 0; j < ug_info->numQueuesTx; j++) {
2451                 /* Setup the skbuff rings */
2452                 ugeth->tx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2453                                               ugeth->ug_info->bdRingLenTx[j],
2454                                               GFP_KERNEL);
2455
2456                 if (ugeth->tx_skbuff[j] == NULL) {
2457                         if (netif_msg_ifup(ugeth))
2458                                 ugeth_err("%s: Could not allocate tx_skbuff",
2459                                           __func__);
2460                         return -ENOMEM;
2461                 }
2462
2463                 for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++)
2464                         ugeth->tx_skbuff[j][i] = NULL;
2465
2466                 ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0;
2467                 bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j];
2468                 for (i = 0; i < ug_info->bdRingLenTx[j]; i++) {
2469                         /* clear bd buffer */
2470                         out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
2471                         /* set bd status and length */
2472                         out_be32((u32 __iomem *)bd, 0);
2473                         bd += sizeof(struct qe_bd);
2474                 }
2475                 bd -= sizeof(struct qe_bd);
2476                 /* set bd status and length */
2477                 out_be32((u32 __iomem *)bd, T_W); /* for last BD set Wrap bit */
2478         }
2479
2480         /* Init Rx bds */
2481         for (j = 0; j < ug_info->numQueuesRx; j++) {
2482                 /* Setup the skbuff rings */
2483                 ugeth->rx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2484                                               ugeth->ug_info->bdRingLenRx[j],
2485                                               GFP_KERNEL);
2486
2487                 if (ugeth->rx_skbuff[j] == NULL) {
2488                         if (netif_msg_ifup(ugeth))
2489                                 ugeth_err("%s: Could not allocate rx_skbuff",
2490                                           __func__);
2491                         return -ENOMEM;
2492                 }
2493
2494                 for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++)
2495                         ugeth->rx_skbuff[j][i] = NULL;
2496
2497                 ugeth->skb_currx[j] = 0;
2498                 bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j];
2499                 for (i = 0; i < ug_info->bdRingLenRx[j]; i++) {
2500                         /* set bd status and length */
2501                         out_be32((u32 __iomem *)bd, R_I);
2502                         /* clear bd buffer */
2503                         out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
2504                         bd += sizeof(struct qe_bd);
2505                 }
2506                 bd -= sizeof(struct qe_bd);
2507                 /* set bd status and length */
2508                 out_be32((u32 __iomem *)bd, R_W); /* for last BD set Wrap bit */
2509         }
2510
2511         /*
2512          * Global PRAM
2513          */
2514         /* Tx global PRAM */
2515         /* Allocate global tx parameter RAM page */
2516         ugeth->tx_glbl_pram_offset =
2517             qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram),
2518                            UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT);
2519         if (IS_ERR_VALUE(ugeth->tx_glbl_pram_offset)) {
2520                 if (netif_msg_ifup(ugeth))
2521                         ugeth_err
2522                             ("%s: Can not allocate DPRAM memory for p_tx_glbl_pram.",
2523                              __func__);
2524                 return -ENOMEM;
2525         }
2526         ugeth->p_tx_glbl_pram =
2527             (struct ucc_geth_tx_global_pram __iomem *) qe_muram_addr(ugeth->
2528                                                         tx_glbl_pram_offset);
2529         /* Zero out p_tx_glbl_pram */
2530         memset_io((void __iomem *)ugeth->p_tx_glbl_pram, 0, sizeof(struct ucc_geth_tx_global_pram));
2531
2532         /* Fill global PRAM */
2533
2534         /* TQPTR */
2535         /* Size varies with number of Tx threads */
2536         ugeth->thread_dat_tx_offset =
2537             qe_muram_alloc(numThreadsTxNumerical *
2538                            sizeof(struct ucc_geth_thread_data_tx) +
2539                            32 * (numThreadsTxNumerical == 1),
2540                            UCC_GETH_THREAD_DATA_ALIGNMENT);
2541         if (IS_ERR_VALUE(ugeth->thread_dat_tx_offset)) {
2542                 if (netif_msg_ifup(ugeth))
2543                         ugeth_err
2544                             ("%s: Can not allocate DPRAM memory for p_thread_data_tx.",
2545                              __func__);
2546                 return -ENOMEM;
2547         }
2548
2549         ugeth->p_thread_data_tx =
2550             (struct ucc_geth_thread_data_tx __iomem *) qe_muram_addr(ugeth->
2551                                                         thread_dat_tx_offset);
2552         out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset);
2553
2554         /* vtagtable */
2555         for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++)
2556                 out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i],
2557                          ug_info->vtagtable[i]);
2558
2559         /* iphoffset */
2560         for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++)
2561                 out_8(&ugeth->p_tx_glbl_pram->iphoffset[i],
2562                                 ug_info->iphoffset[i]);
2563
2564         /* SQPTR */
2565         /* Size varies with number of Tx queues */
2566         ugeth->send_q_mem_reg_offset =
2567             qe_muram_alloc(ug_info->numQueuesTx *
2568                            sizeof(struct ucc_geth_send_queue_qd),
2569                            UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
2570         if (IS_ERR_VALUE(ugeth->send_q_mem_reg_offset)) {
2571                 if (netif_msg_ifup(ugeth))
2572                         ugeth_err
2573                             ("%s: Can not allocate DPRAM memory for p_send_q_mem_reg.",
2574                              __func__);
2575                 return -ENOMEM;
2576         }
2577
2578         ugeth->p_send_q_mem_reg =
2579             (struct ucc_geth_send_queue_mem_region __iomem *) qe_muram_addr(ugeth->
2580                         send_q_mem_reg_offset);
2581         out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset);
2582
2583         /* Setup the table */
2584         /* Assume BD rings are already established */
2585         for (i = 0; i < ug_info->numQueuesTx; i++) {
2586                 endOfRing =
2587                     ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] -
2588                                               1) * sizeof(struct qe_bd);
2589                 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2590                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2591                                  (u32) virt_to_phys(ugeth->p_tx_bd_ring[i]));
2592                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2593                                  last_bd_completed_address,
2594                                  (u32) virt_to_phys(endOfRing));
2595                 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2596                            MEM_PART_MURAM) {
2597                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2598                                  (u32) immrbar_virt_to_phys(ugeth->
2599                                                             p_tx_bd_ring[i]));
2600                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2601                                  last_bd_completed_address,
2602                                  (u32) immrbar_virt_to_phys(endOfRing));
2603                 }
2604         }
2605
2606         /* schedulerbasepointer */
2607
2608         if (ug_info->numQueuesTx > 1) {
2609         /* scheduler exists only if more than 1 tx queue */
2610                 ugeth->scheduler_offset =
2611                     qe_muram_alloc(sizeof(struct ucc_geth_scheduler),
2612                                    UCC_GETH_SCHEDULER_ALIGNMENT);
2613                 if (IS_ERR_VALUE(ugeth->scheduler_offset)) {
2614                         if (netif_msg_ifup(ugeth))
2615                                 ugeth_err
2616                                  ("%s: Can not allocate DPRAM memory for p_scheduler.",
2617                                      __func__);
2618                         return -ENOMEM;
2619                 }
2620
2621                 ugeth->p_scheduler =
2622                     (struct ucc_geth_scheduler __iomem *) qe_muram_addr(ugeth->
2623                                                            scheduler_offset);
2624                 out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer,
2625                          ugeth->scheduler_offset);
2626                 /* Zero out p_scheduler */
2627                 memset_io((void __iomem *)ugeth->p_scheduler, 0, sizeof(struct ucc_geth_scheduler));
2628
2629                 /* Set values in scheduler */
2630                 out_be32(&ugeth->p_scheduler->mblinterval,
2631                          ug_info->mblinterval);
2632                 out_be16(&ugeth->p_scheduler->nortsrbytetime,
2633                          ug_info->nortsrbytetime);
2634                 out_8(&ugeth->p_scheduler->fracsiz, ug_info->fracsiz);
2635                 out_8(&ugeth->p_scheduler->strictpriorityq,
2636                                 ug_info->strictpriorityq);
2637                 out_8(&ugeth->p_scheduler->txasap, ug_info->txasap);
2638                 out_8(&ugeth->p_scheduler->extrabw, ug_info->extrabw);
2639                 for (i = 0; i < NUM_TX_QUEUES; i++)
2640                         out_8(&ugeth->p_scheduler->weightfactor[i],
2641                             ug_info->weightfactor[i]);
2642
2643                 /* Set pointers to cpucount registers in scheduler */
2644                 ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0);
2645                 ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1);
2646                 ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2);
2647                 ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3);
2648                 ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4);
2649                 ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5);
2650                 ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6);
2651                 ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7);
2652         }
2653
2654         /* schedulerbasepointer */
2655         /* TxRMON_PTR (statistics) */
2656         if (ug_info->
2657             statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) {
2658                 ugeth->tx_fw_statistics_pram_offset =
2659                     qe_muram_alloc(sizeof
2660                                    (struct ucc_geth_tx_firmware_statistics_pram),
2661                                    UCC_GETH_TX_STATISTICS_ALIGNMENT);
2662                 if (IS_ERR_VALUE(ugeth->tx_fw_statistics_pram_offset)) {
2663                         if (netif_msg_ifup(ugeth))
2664                                 ugeth_err
2665                                     ("%s: Can not allocate DPRAM memory for"
2666                                         " p_tx_fw_statistics_pram.",
2667                                         __func__);
2668                         return -ENOMEM;
2669                 }
2670                 ugeth->p_tx_fw_statistics_pram =
2671                     (struct ucc_geth_tx_firmware_statistics_pram __iomem *)
2672                     qe_muram_addr(ugeth->tx_fw_statistics_pram_offset);
2673                 /* Zero out p_tx_fw_statistics_pram */
2674                 memset_io((void __iomem *)ugeth->p_tx_fw_statistics_pram,
2675                        0, sizeof(struct ucc_geth_tx_firmware_statistics_pram));
2676         }
2677
2678         /* temoder */
2679         /* Already has speed set */
2680
2681         if (ug_info->numQueuesTx > 1)
2682                 temoder |= TEMODER_SCHEDULER_ENABLE;
2683         if (ug_info->ipCheckSumGenerate)
2684                 temoder |= TEMODER_IP_CHECKSUM_GENERATE;
2685         temoder |= ((ug_info->numQueuesTx - 1) << TEMODER_NUM_OF_QUEUES_SHIFT);
2686         out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder);
2687
2688         test = in_be16(&ugeth->p_tx_glbl_pram->temoder);
2689
2690         /* Function code register value to be used later */
2691         function_code = UCC_BMR_BO_BE | UCC_BMR_GBL;
2692         /* Required for QE */
2693
2694         /* function code register */
2695         out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24);
2696
2697         /* Rx global PRAM */
2698         /* Allocate global rx parameter RAM page */
2699         ugeth->rx_glbl_pram_offset =
2700             qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram),
2701                            UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT);
2702         if (IS_ERR_VALUE(ugeth->rx_glbl_pram_offset)) {
2703                 if (netif_msg_ifup(ugeth))
2704                         ugeth_err
2705                             ("%s: Can not allocate DPRAM memory for p_rx_glbl_pram.",
2706                              __func__);
2707                 return -ENOMEM;
2708         }
2709         ugeth->p_rx_glbl_pram =
2710             (struct ucc_geth_rx_global_pram __iomem *) qe_muram_addr(ugeth->
2711                                                         rx_glbl_pram_offset);
2712         /* Zero out p_rx_glbl_pram */
2713         memset_io((void __iomem *)ugeth->p_rx_glbl_pram, 0, sizeof(struct ucc_geth_rx_global_pram));
2714
2715         /* Fill global PRAM */
2716
2717         /* RQPTR */
2718         /* Size varies with number of Rx threads */
2719         ugeth->thread_dat_rx_offset =
2720             qe_muram_alloc(numThreadsRxNumerical *
2721                            sizeof(struct ucc_geth_thread_data_rx),
2722                            UCC_GETH_THREAD_DATA_ALIGNMENT);
2723         if (IS_ERR_VALUE(ugeth->thread_dat_rx_offset)) {
2724                 if (netif_msg_ifup(ugeth))
2725                         ugeth_err
2726                             ("%s: Can not allocate DPRAM memory for p_thread_data_rx.",
2727                              __func__);
2728                 return -ENOMEM;
2729         }
2730
2731         ugeth->p_thread_data_rx =
2732             (struct ucc_geth_thread_data_rx __iomem *) qe_muram_addr(ugeth->
2733                                                         thread_dat_rx_offset);
2734         out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset);
2735
2736         /* typeorlen */
2737         out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen);
2738
2739         /* rxrmonbaseptr (statistics) */
2740         if (ug_info->
2741             statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) {
2742                 ugeth->rx_fw_statistics_pram_offset =
2743                     qe_muram_alloc(sizeof
2744                                    (struct ucc_geth_rx_firmware_statistics_pram),
2745                                    UCC_GETH_RX_STATISTICS_ALIGNMENT);
2746                 if (IS_ERR_VALUE(ugeth->rx_fw_statistics_pram_offset)) {
2747                         if (netif_msg_ifup(ugeth))
2748                                 ugeth_err
2749                                         ("%s: Can not allocate DPRAM memory for"
2750                                         " p_rx_fw_statistics_pram.", __func__);
2751                         return -ENOMEM;
2752                 }
2753                 ugeth->p_rx_fw_statistics_pram =
2754                     (struct ucc_geth_rx_firmware_statistics_pram __iomem *)
2755                     qe_muram_addr(ugeth->rx_fw_statistics_pram_offset);
2756                 /* Zero out p_rx_fw_statistics_pram */
2757                 memset_io((void __iomem *)ugeth->p_rx_fw_statistics_pram, 0,
2758                        sizeof(struct ucc_geth_rx_firmware_statistics_pram));
2759         }
2760
2761         /* intCoalescingPtr */
2762
2763         /* Size varies with number of Rx queues */
2764         ugeth->rx_irq_coalescing_tbl_offset =
2765             qe_muram_alloc(ug_info->numQueuesRx *
2766                            sizeof(struct ucc_geth_rx_interrupt_coalescing_entry)
2767                            + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT);
2768         if (IS_ERR_VALUE(ugeth->rx_irq_coalescing_tbl_offset)) {
2769                 if (netif_msg_ifup(ugeth))
2770                         ugeth_err
2771                             ("%s: Can not allocate DPRAM memory for"
2772                                 " p_rx_irq_coalescing_tbl.", __func__);
2773                 return -ENOMEM;
2774         }
2775
2776         ugeth->p_rx_irq_coalescing_tbl =
2777             (struct ucc_geth_rx_interrupt_coalescing_table __iomem *)
2778             qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset);
2779         out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr,
2780                  ugeth->rx_irq_coalescing_tbl_offset);
2781
2782         /* Fill interrupt coalescing table */
2783         for (i = 0; i < ug_info->numQueuesRx; i++) {
2784                 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2785                          interruptcoalescingmaxvalue,
2786                          ug_info->interruptcoalescingmaxvalue[i]);
2787                 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2788                          interruptcoalescingcounter,
2789                          ug_info->interruptcoalescingmaxvalue[i]);
2790         }
2791
2792         /* MRBLR */
2793         init_max_rx_buff_len(uf_info->max_rx_buf_length,
2794                              &ugeth->p_rx_glbl_pram->mrblr);
2795         /* MFLR */
2796         out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength);
2797         /* MINFLR */
2798         init_min_frame_len(ug_info->minFrameLength,
2799                            &ugeth->p_rx_glbl_pram->minflr,
2800                            &ugeth->p_rx_glbl_pram->mrblr);
2801         /* MAXD1 */
2802         out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length);
2803         /* MAXD2 */
2804         out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length);
2805
2806         /* l2qt */
2807         l2qt = 0;
2808         for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++)
2809                 l2qt |= (ug_info->l2qt[i] << (28 - 4 * i));
2810         out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt);
2811
2812         /* l3qt */
2813         for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) {
2814                 l3qt = 0;
2815                 for (i = 0; i < 8; i++)
2816                         l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i));
2817                 out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt);
2818         }
2819
2820         /* vlantype */
2821         out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype);
2822
2823         /* vlantci */
2824         out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci);
2825
2826         /* ecamptr */
2827         out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr);
2828
2829         /* RBDQPTR */
2830         /* Size varies with number of Rx queues */
2831         ugeth->rx_bd_qs_tbl_offset =
2832             qe_muram_alloc(ug_info->numQueuesRx *
2833                            (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2834                             sizeof(struct ucc_geth_rx_prefetched_bds)),
2835                            UCC_GETH_RX_BD_QUEUES_ALIGNMENT);
2836         if (IS_ERR_VALUE(ugeth->rx_bd_qs_tbl_offset)) {
2837                 if (netif_msg_ifup(ugeth))
2838                         ugeth_err
2839                             ("%s: Can not allocate DPRAM memory for p_rx_bd_qs_tbl.",
2840                              __func__);
2841                 return -ENOMEM;
2842         }
2843
2844         ugeth->p_rx_bd_qs_tbl =
2845             (struct ucc_geth_rx_bd_queues_entry __iomem *) qe_muram_addr(ugeth->
2846                                     rx_bd_qs_tbl_offset);
2847         out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset);
2848         /* Zero out p_rx_bd_qs_tbl */
2849         memset_io((void __iomem *)ugeth->p_rx_bd_qs_tbl,
2850                0,
2851                ug_info->numQueuesRx * (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2852                                        sizeof(struct ucc_geth_rx_prefetched_bds)));
2853
2854         /* Setup the table */
2855         /* Assume BD rings are already established */
2856         for (i = 0; i < ug_info->numQueuesRx; i++) {
2857                 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2858                         out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2859                                  (u32) virt_to_phys(ugeth->p_rx_bd_ring[i]));
2860                 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2861                            MEM_PART_MURAM) {
2862                         out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2863                                  (u32) immrbar_virt_to_phys(ugeth->
2864                                                             p_rx_bd_ring[i]));
2865                 }
2866                 /* rest of fields handled by QE */
2867         }
2868
2869         /* remoder */
2870         /* Already has speed set */
2871
2872         if (ugeth->rx_extended_features)
2873                 remoder |= REMODER_RX_EXTENDED_FEATURES;
2874         if (ug_info->rxExtendedFiltering)
2875                 remoder |= REMODER_RX_EXTENDED_FILTERING;
2876         if (ug_info->dynamicMaxFrameLength)
2877                 remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH;
2878         if (ug_info->dynamicMinFrameLength)
2879                 remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH;
2880         remoder |=
2881             ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT;
2882         remoder |=
2883             ug_info->
2884             vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT;
2885         remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT;
2886         remoder |= ((ug_info->numQueuesRx - 1) << REMODER_NUM_OF_QUEUES_SHIFT);
2887         if (ug_info->ipCheckSumCheck)
2888                 remoder |= REMODER_IP_CHECKSUM_CHECK;
2889         if (ug_info->ipAddressAlignment)
2890                 remoder |= REMODER_IP_ADDRESS_ALIGNMENT;
2891         out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder);
2892
2893         /* Note that this function must be called */
2894         /* ONLY AFTER p_tx_fw_statistics_pram */
2895         /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */
2896         init_firmware_statistics_gathering_mode((ug_info->
2897                 statisticsMode &
2898                 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX),
2899                 (ug_info->statisticsMode &
2900                 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX),
2901                 &ugeth->p_tx_glbl_pram->txrmonbaseptr,
2902                 ugeth->tx_fw_statistics_pram_offset,
2903                 &ugeth->p_rx_glbl_pram->rxrmonbaseptr,
2904                 ugeth->rx_fw_statistics_pram_offset,
2905                 &ugeth->p_tx_glbl_pram->temoder,
2906                 &ugeth->p_rx_glbl_pram->remoder);
2907
2908         /* function code register */
2909         out_8(&ugeth->p_rx_glbl_pram->rstate, function_code);
2910
2911         /* initialize extended filtering */
2912         if (ug_info->rxExtendedFiltering) {
2913                 if (!ug_info->extendedFilteringChainPointer) {
2914                         if (netif_msg_ifup(ugeth))
2915                                 ugeth_err("%s: Null Extended Filtering Chain Pointer.",
2916                                           __func__);
2917                         return -EINVAL;
2918                 }
2919
2920                 /* Allocate memory for extended filtering Mode Global
2921                 Parameters */
2922                 ugeth->exf_glbl_param_offset =
2923                     qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram),
2924                 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT);
2925                 if (IS_ERR_VALUE(ugeth->exf_glbl_param_offset)) {
2926                         if (netif_msg_ifup(ugeth))
2927                                 ugeth_err
2928                                         ("%s: Can not allocate DPRAM memory for"
2929                                         " p_exf_glbl_param.", __func__);
2930                         return -ENOMEM;
2931                 }
2932
2933                 ugeth->p_exf_glbl_param =
2934                     (struct ucc_geth_exf_global_pram __iomem *) qe_muram_addr(ugeth->
2935                                  exf_glbl_param_offset);
2936                 out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam,
2937                          ugeth->exf_glbl_param_offset);
2938                 out_be32(&ugeth->p_exf_glbl_param->l2pcdptr,
2939                          (u32) ug_info->extendedFilteringChainPointer);
2940
2941         } else {                /* initialize 82xx style address filtering */
2942
2943                 /* Init individual address recognition registers to disabled */
2944
2945                 for (j = 0; j < NUM_OF_PADDRS; j++)
2946                         ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j);
2947
2948                 p_82xx_addr_filt =
2949                     (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
2950                     p_rx_glbl_pram->addressfiltering;
2951
2952                 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2953                         ENET_ADDR_TYPE_GROUP);
2954                 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2955                         ENET_ADDR_TYPE_INDIVIDUAL);
2956         }
2957
2958         /*
2959          * Initialize UCC at QE level
2960          */
2961
2962         command = QE_INIT_TX_RX;
2963
2964         /* Allocate shadow InitEnet command parameter structure.
2965          * This is needed because after the InitEnet command is executed,
2966          * the structure in DPRAM is released, because DPRAM is a premium
2967          * resource.
2968          * This shadow structure keeps a copy of what was done so that the
2969          * allocated resources can be released when the channel is freed.
2970          */
2971         if (!(ugeth->p_init_enet_param_shadow =
2972               kmalloc(sizeof(struct ucc_geth_init_pram), GFP_KERNEL))) {
2973                 if (netif_msg_ifup(ugeth))
2974                         ugeth_err
2975                             ("%s: Can not allocate memory for"
2976                                 " p_UccInitEnetParamShadows.", __func__);
2977                 return -ENOMEM;
2978         }
2979         /* Zero out *p_init_enet_param_shadow */
2980         memset((char *)ugeth->p_init_enet_param_shadow,
2981                0, sizeof(struct ucc_geth_init_pram));
2982
2983         /* Fill shadow InitEnet command parameter structure */
2984
2985         ugeth->p_init_enet_param_shadow->resinit1 =
2986             ENET_INIT_PARAM_MAGIC_RES_INIT1;
2987         ugeth->p_init_enet_param_shadow->resinit2 =
2988             ENET_INIT_PARAM_MAGIC_RES_INIT2;
2989         ugeth->p_init_enet_param_shadow->resinit3 =
2990             ENET_INIT_PARAM_MAGIC_RES_INIT3;
2991         ugeth->p_init_enet_param_shadow->resinit4 =
2992             ENET_INIT_PARAM_MAGIC_RES_INIT4;
2993         ugeth->p_init_enet_param_shadow->resinit5 =
2994             ENET_INIT_PARAM_MAGIC_RES_INIT5;
2995         ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2996             ((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT;
2997         ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2998             ((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT;
2999
3000         ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
3001             ugeth->rx_glbl_pram_offset | ug_info->riscRx;
3002         if ((ug_info->largestexternallookupkeysize !=
3003              QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE) &&
3004             (ug_info->largestexternallookupkeysize !=
3005              QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES) &&
3006             (ug_info->largestexternallookupkeysize !=
3007              QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)) {
3008                 if (netif_msg_ifup(ugeth))
3009                         ugeth_err("%s: Invalid largest External Lookup Key Size.",
3010                                   __func__);
3011                 return -EINVAL;
3012         }
3013         ugeth->p_init_enet_param_shadow->largestexternallookupkeysize =
3014             ug_info->largestexternallookupkeysize;
3015         size = sizeof(struct ucc_geth_thread_rx_pram);
3016         if (ug_info->rxExtendedFiltering) {
3017                 size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
3018                 if (ug_info->largestexternallookupkeysize ==
3019                     QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
3020                         size +=
3021                             THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
3022                 if (ug_info->largestexternallookupkeysize ==
3023                     QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
3024                         size +=
3025                             THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
3026         }
3027
3028         if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth->
3029                 p_init_enet_param_shadow->rxthread[0]),
3030                 (u8) (numThreadsRxNumerical + 1)
3031                 /* Rx needs one extra for terminator */
3032                 , size, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT,
3033                 ug_info->riscRx, 1)) != 0) {
3034                 if (netif_msg_ifup(ugeth))
3035                                 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
3036                                         __func__);
3037                 return ret_val;
3038         }
3039
3040         ugeth->p_init_enet_param_shadow->txglobal =
3041             ugeth->tx_glbl_pram_offset | ug_info->riscTx;
3042         if ((ret_val =
3043              fill_init_enet_entries(ugeth,
3044                                     &(ugeth->p_init_enet_param_shadow->
3045                                       txthread[0]), numThreadsTxNumerical,
3046                                     sizeof(struct ucc_geth_thread_tx_pram),
3047                                     UCC_GETH_THREAD_TX_PRAM_ALIGNMENT,
3048                                     ug_info->riscTx, 0)) != 0) {
3049                 if (netif_msg_ifup(ugeth))
3050                         ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
3051                                   __func__);
3052                 return ret_val;
3053         }
3054
3055         /* Load Rx bds with buffers */
3056         for (i = 0; i < ug_info->numQueuesRx; i++) {
3057                 if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) {
3058                         if (netif_msg_ifup(ugeth))
3059                                 ugeth_err("%s: Can not fill Rx bds with buffers.",
3060                                           __func__);
3061                         return ret_val;
3062                 }
3063         }
3064
3065         /* Allocate InitEnet command parameter structure */
3066         init_enet_pram_offset = qe_muram_alloc(sizeof(struct ucc_geth_init_pram), 4);
3067         if (IS_ERR_VALUE(init_enet_pram_offset)) {
3068                 if (netif_msg_ifup(ugeth))
3069                         ugeth_err
3070                             ("%s: Can not allocate DPRAM memory for p_init_enet_pram.",
3071                              __func__);
3072                 return -ENOMEM;
3073         }
3074         p_init_enet_pram =
3075             (struct ucc_geth_init_pram __iomem *) qe_muram_addr(init_enet_pram_offset);
3076
3077         /* Copy shadow InitEnet command parameter structure into PRAM */
3078         out_8(&p_init_enet_pram->resinit1,
3079                         ugeth->p_init_enet_param_shadow->resinit1);
3080         out_8(&p_init_enet_pram->resinit2,
3081                         ugeth->p_init_enet_param_shadow->resinit2);
3082         out_8(&p_init_enet_pram->resinit3,
3083                         ugeth->p_init_enet_param_shadow->resinit3);
3084         out_8(&p_init_enet_pram->resinit4,
3085                         ugeth->p_init_enet_param_shadow->resinit4);
3086         out_be16(&p_init_enet_pram->resinit5,
3087                  ugeth->p_init_enet_param_shadow->resinit5);
3088         out_8(&p_init_enet_pram->largestexternallookupkeysize,
3089             ugeth->p_init_enet_param_shadow->largestexternallookupkeysize);
3090         out_be32(&p_init_enet_pram->rgftgfrxglobal,
3091                  ugeth->p_init_enet_param_shadow->rgftgfrxglobal);
3092         for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_RX; i++)
3093                 out_be32(&p_init_enet_pram->rxthread[i],
3094                          ugeth->p_init_enet_param_shadow->rxthread[i]);
3095         out_be32(&p_init_enet_pram->txglobal,
3096                  ugeth->p_init_enet_param_shadow->txglobal);
3097         for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_TX; i++)
3098                 out_be32(&p_init_enet_pram->txthread[i],
3099                          ugeth->p_init_enet_param_shadow->txthread[i]);
3100
3101         /* Issue QE command */
3102         cecr_subblock =
3103             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
3104         qe_issue_cmd(command, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
3105                      init_enet_pram_offset);
3106
3107         /* Free InitEnet command parameter */
3108         qe_muram_free(init_enet_pram_offset);
3109
3110         return 0;
3111 }
3112
3113 /* This is called by the kernel when a frame is ready for transmission. */
3114 /* It is pointed to by the dev->hard_start_xmit function pointer */
3115 static int ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev)
3116 {
3117         struct ucc_geth_private *ugeth = netdev_priv(dev);
3118 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3119         struct ucc_fast_private *uccf;
3120 #endif
3121         u8 __iomem *bd;                 /* BD pointer */
3122         u32 bd_status;
3123         u8 txQ = 0;
3124         unsigned long flags;
3125
3126         ugeth_vdbg("%s: IN", __func__);
3127
3128         spin_lock_irqsave(&ugeth->lock, flags);
3129
3130         dev->stats.tx_bytes += skb->len;
3131
3132         /* Start from the next BD that should be filled */
3133         bd = ugeth->txBd[txQ];
3134         bd_status = in_be32((u32 __iomem *)bd);
3135         /* Save the skb pointer so we can free it later */
3136         ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb;
3137
3138         /* Update the current skb pointer (wrapping if this was the last) */
3139         ugeth->skb_curtx[txQ] =
3140             (ugeth->skb_curtx[txQ] +
3141              1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3142
3143         /* set up the buffer descriptor */
3144         out_be32(&((struct qe_bd __iomem *)bd)->buf,
3145                       dma_map_single(ugeth->dev, skb->data,
3146                               skb->len, DMA_TO_DEVICE));
3147
3148         /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */
3149
3150         bd_status = (bd_status & T_W) | T_R | T_I | T_L | skb->len;
3151
3152         /* set bd status and length */
3153         out_be32((u32 __iomem *)bd, bd_status);
3154
3155         dev->trans_start = jiffies;
3156
3157         /* Move to next BD in the ring */
3158         if (!(bd_status & T_W))
3159                 bd += sizeof(struct qe_bd);
3160         else
3161                 bd = ugeth->p_tx_bd_ring[txQ];
3162
3163         /* If the next BD still needs to be cleaned up, then the bds
3164            are full.  We need to tell the kernel to stop sending us stuff. */
3165         if (bd == ugeth->confBd[txQ]) {
3166                 if (!netif_queue_stopped(dev))
3167                         netif_stop_queue(dev);
3168         }
3169
3170         ugeth->txBd[txQ] = bd;
3171
3172         if (ugeth->p_scheduler) {
3173                 ugeth->cpucount[txQ]++;
3174                 /* Indicate to QE that there are more Tx bds ready for
3175                 transmission */
3176                 /* This is done by writing a running counter of the bd
3177                 count to the scheduler PRAM. */
3178                 out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]);
3179         }
3180
3181 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3182         uccf = ugeth->uccf;
3183         out_be16(uccf->p_utodr, UCC_FAST_TOD);
3184 #endif
3185         spin_unlock_irqrestore(&ugeth->lock, flags);
3186
3187         return NETDEV_TX_OK;
3188 }
3189
3190 static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit)
3191 {
3192         struct sk_buff *skb;
3193         u8 __iomem *bd;
3194         u16 length, howmany = 0;
3195         u32 bd_status;
3196         u8 *bdBuffer;
3197         struct net_device *dev;
3198
3199         ugeth_vdbg("%s: IN", __func__);
3200
3201         dev = ugeth->ndev;
3202
3203         /* collect received buffers */
3204         bd = ugeth->rxBd[rxQ];
3205
3206         bd_status = in_be32((u32 __iomem *)bd);
3207
3208         /* while there are received buffers and BD is full (~R_E) */
3209         while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) {
3210                 bdBuffer = (u8 *) in_be32(&((struct qe_bd __iomem *)bd)->buf);
3211                 length = (u16) ((bd_status & BD_LENGTH_MASK) - 4);
3212                 skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]];
3213
3214                 /* determine whether buffer is first, last, first and last
3215                 (single buffer frame) or middle (not first and not last) */
3216                 if (!skb ||
3217                     (!(bd_status & (R_F | R_L))) ||
3218                     (bd_status & R_ERRORS_FATAL)) {
3219                         if (netif_msg_rx_err(ugeth))
3220                                 ugeth_err("%s, %d: ERROR!!! skb - 0x%08x",
3221                                            __func__, __LINE__, (u32) skb);
3222                         if (skb) {
3223                                 skb->data = skb->head + NET_SKB_PAD;
3224                                 __skb_queue_head(&ugeth->rx_recycle, skb);
3225                         }
3226
3227                         ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL;
3228                         dev->stats.rx_dropped++;
3229                 } else {
3230                         dev->stats.rx_packets++;
3231                         howmany++;
3232
3233                         /* Prep the skb for the packet */
3234                         skb_put(skb, length);
3235
3236                         /* Tell the skb what kind of packet this is */
3237                         skb->protocol = eth_type_trans(skb, ugeth->ndev);
3238
3239                         dev->stats.rx_bytes += length;
3240                         /* Send the packet up the stack */
3241                         netif_receive_skb(skb);
3242                 }
3243
3244                 skb = get_new_skb(ugeth, bd);
3245                 if (!skb) {
3246                         if (netif_msg_rx_err(ugeth))
3247                                 ugeth_warn("%s: No Rx Data Buffer", __func__);
3248                         dev->stats.rx_dropped++;
3249                         break;
3250                 }
3251
3252                 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb;
3253
3254                 /* update to point at the next skb */
3255                 ugeth->skb_currx[rxQ] =
3256                     (ugeth->skb_currx[rxQ] +
3257                      1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]);
3258
3259                 if (bd_status & R_W)
3260                         bd = ugeth->p_rx_bd_ring[rxQ];
3261                 else
3262                         bd += sizeof(struct qe_bd);
3263
3264                 bd_status = in_be32((u32 __iomem *)bd);
3265         }
3266
3267         ugeth->rxBd[rxQ] = bd;
3268         return howmany;
3269 }
3270
3271 static int ucc_geth_tx(struct net_device *dev, u8 txQ)
3272 {
3273         /* Start from the next BD that should be filled */
3274         struct ucc_geth_private *ugeth = netdev_priv(dev);
3275         u8 __iomem *bd;         /* BD pointer */
3276         u32 bd_status;
3277
3278         bd = ugeth->confBd[txQ];
3279         bd_status = in_be32((u32 __iomem *)bd);
3280
3281         /* Normal processing. */
3282         while ((bd_status & T_R) == 0) {
3283                 struct sk_buff *skb;
3284
3285                 /* BD contains already transmitted buffer.   */
3286                 /* Handle the transmitted buffer and release */
3287                 /* the BD to be used with the current frame  */
3288
3289                 if (bd == ugeth->txBd[txQ]) /* queue empty? */
3290                         break;
3291
3292                 dev->stats.tx_packets++;
3293
3294                 skb = ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]];
3295
3296                 if (skb_queue_len(&ugeth->rx_recycle) < RX_BD_RING_LEN &&
3297                              skb_recycle_check(skb,
3298                                     ugeth->ug_info->uf_info.max_rx_buf_length +
3299                                     UCC_GETH_RX_DATA_BUF_ALIGNMENT))
3300                         __skb_queue_head(&ugeth->rx_recycle, skb);
3301                 else
3302                         dev_kfree_skb(skb);
3303
3304                 ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL;
3305                 ugeth->skb_dirtytx[txQ] =
3306                     (ugeth->skb_dirtytx[txQ] +
3307                      1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3308
3309                 /* We freed a buffer, so now we can restart transmission */
3310                 if (netif_queue_stopped(dev))
3311                         netif_wake_queue(dev);
3312
3313                 /* Advance the confirmation BD pointer */
3314                 if (!(bd_status & T_W))
3315                         bd += sizeof(struct qe_bd);
3316                 else
3317                         bd = ugeth->p_tx_bd_ring[txQ];
3318                 bd_status = in_be32((u32 __iomem *)bd);
3319         }
3320         ugeth->confBd[txQ] = bd;
3321         return 0;
3322 }
3323
3324 static int ucc_geth_poll(struct napi_struct *napi, int budget)
3325 {
3326         struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi);
3327         struct ucc_geth_info *ug_info;
3328         int howmany, i;
3329
3330         ug_info = ugeth->ug_info;
3331
3332         /* Tx event processing */
3333         spin_lock(&ugeth->lock);
3334         for (i = 0; i < ug_info->numQueuesTx; i++)
3335                 ucc_geth_tx(ugeth->ndev, i);
3336         spin_unlock(&ugeth->lock);
3337
3338         howmany = 0;
3339         for (i = 0; i < ug_info->numQueuesRx; i++)
3340                 howmany += ucc_geth_rx(ugeth, i, budget - howmany);
3341
3342         if (howmany < budget) {
3343                 napi_complete(napi);
3344                 setbits32(ugeth->uccf->p_uccm, UCCE_RX_EVENTS | UCCE_TX_EVENTS);
3345         }
3346
3347         return howmany;
3348 }
3349
3350 static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
3351 {
3352         struct net_device *dev = info;
3353         struct ucc_geth_private *ugeth = netdev_priv(dev);
3354         struct ucc_fast_private *uccf;
3355         struct ucc_geth_info *ug_info;
3356         register u32 ucce;
3357         register u32 uccm;
3358
3359         ugeth_vdbg("%s: IN", __func__);
3360
3361         uccf = ugeth->uccf;
3362         ug_info = ugeth->ug_info;
3363
3364         /* read and clear events */
3365         ucce = (u32) in_be32(uccf->p_ucce);
3366         uccm = (u32) in_be32(uccf->p_uccm);
3367         ucce &= uccm;
3368         out_be32(uccf->p_ucce, ucce);
3369
3370         /* check for receive events that require processing */
3371         if (ucce & (UCCE_RX_EVENTS | UCCE_TX_EVENTS)) {
3372                 if (napi_schedule_prep(&ugeth->napi)) {
3373                         uccm &= ~(UCCE_RX_EVENTS | UCCE_TX_EVENTS);
3374                         out_be32(uccf->p_uccm, uccm);
3375                         __napi_schedule(&ugeth->napi);
3376                 }
3377         }
3378
3379         /* Errors and other events */
3380         if (ucce & UCCE_OTHER) {
3381                 if (ucce & UCC_GETH_UCCE_BSY)
3382                         dev->stats.rx_errors++;
3383                 if (ucce & UCC_GETH_UCCE_TXE)
3384                         dev->stats.tx_errors++;
3385         }
3386
3387         return IRQ_HANDLED;
3388 }
3389
3390 #ifdef CONFIG_NET_POLL_CONTROLLER
3391 /*
3392  * Polling 'interrupt' - used by things like netconsole to send skbs
3393  * without having to re-enable interrupts. It's not called while
3394  * the interrupt routine is executing.
3395  */
3396 static void ucc_netpoll(struct net_device *dev)
3397 {
3398         struct ucc_geth_private *ugeth = netdev_priv(dev);
3399         int irq = ugeth->ug_info->uf_info.irq;
3400
3401         disable_irq(irq);
3402         ucc_geth_irq_handler(irq, dev);
3403         enable_irq(irq);
3404 }
3405 #endif /* CONFIG_NET_POLL_CONTROLLER */
3406
3407 static int ucc_geth_set_mac_addr(struct net_device *dev, void *p)
3408 {
3409         struct ucc_geth_private *ugeth = netdev_priv(dev);
3410         struct sockaddr *addr = p;
3411
3412         if (!is_valid_ether_addr(addr->sa_data))
3413                 return -EADDRNOTAVAIL;
3414
3415         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3416
3417         /*
3418          * If device is not running, we will set mac addr register
3419          * when opening the device.
3420          */
3421         if (!netif_running(dev))
3422                 return 0;
3423
3424         spin_lock_irq(&ugeth->lock);
3425         init_mac_station_addr_regs(dev->dev_addr[0],
3426                                    dev->dev_addr[1],
3427                                    dev->dev_addr[2],
3428                                    dev->dev_addr[3],
3429                                    dev->dev_addr[4],
3430                                    dev->dev_addr[5],
3431                                    &ugeth->ug_regs->macstnaddr1,
3432                                    &ugeth->ug_regs->macstnaddr2);
3433         spin_unlock_irq(&ugeth->lock);
3434
3435         return 0;
3436 }
3437
3438 static int ucc_geth_init_mac(struct ucc_geth_private *ugeth)
3439 {
3440         struct net_device *dev = ugeth->ndev;
3441         int err;
3442
3443         err = ucc_struct_init(ugeth);
3444         if (err) {
3445                 if (netif_msg_ifup(ugeth))
3446                         ugeth_err("%s: Cannot configure internal struct, "
3447                                   "aborting.", dev->name);
3448                 goto err;
3449         }
3450
3451         err = ucc_geth_startup(ugeth);
3452         if (err) {
3453                 if (netif_msg_ifup(ugeth))
3454                         ugeth_err("%s: Cannot configure net device, aborting.",
3455                                   dev->name);
3456                 goto err;
3457         }
3458
3459         err = adjust_enet_interface(ugeth);
3460         if (err) {
3461                 if (netif_msg_ifup(ugeth))
3462                         ugeth_err("%s: Cannot configure net device, aborting.",
3463                                   dev->name);
3464                 goto err;
3465         }
3466
3467         /*       Set MACSTNADDR1, MACSTNADDR2                */
3468         /* For more details see the hardware spec.           */
3469         init_mac_station_addr_regs(dev->dev_addr[0],
3470                                    dev->dev_addr[1],
3471                                    dev->dev_addr[2],
3472                                    dev->dev_addr[3],
3473                                    dev->dev_addr[4],
3474                                    dev->dev_addr[5],
3475                                    &ugeth->ug_regs->macstnaddr1,
3476                                    &ugeth->ug_regs->macstnaddr2);
3477
3478         err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
3479         if (err) {
3480                 if (netif_msg_ifup(ugeth))
3481                         ugeth_err("%s: Cannot enable net device, aborting.", dev->name);
3482                 goto err;
3483         }
3484
3485         return 0;
3486 err:
3487         ucc_geth_stop(ugeth);
3488         return err;
3489 }
3490
3491 /* Called when something needs to use the ethernet device */
3492 /* Returns 0 for success. */
3493 static int ucc_geth_open(struct net_device *dev)
3494 {
3495         struct ucc_geth_private *ugeth = netdev_priv(dev);
3496         int err;
3497
3498         ugeth_vdbg("%s: IN", __func__);
3499
3500         /* Test station address */
3501         if (dev->dev_addr[0] & ENET_GROUP_ADDR) {
3502                 if (netif_msg_ifup(ugeth))
3503                         ugeth_err("%s: Multicast address used for station "
3504                                   "address - is this what you wanted?",
3505                                   __func__);
3506                 return -EINVAL;
3507         }
3508
3509         err = init_phy(dev);
3510         if (err) {
3511                 if (netif_msg_ifup(ugeth))
3512                         ugeth_err("%s: Cannot initialize PHY, aborting.",
3513                                   dev->name);
3514                 return err;
3515         }
3516
3517         err = ucc_geth_init_mac(ugeth);
3518         if (err) {
3519                 if (netif_msg_ifup(ugeth))
3520                         ugeth_err("%s: Cannot initialize MAC, aborting.",
3521                                   dev->name);
3522                 goto err;
3523         }
3524
3525         err = request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler,
3526                           0, "UCC Geth", dev);
3527         if (err) {
3528                 if (netif_msg_ifup(ugeth))
3529                         ugeth_err("%s: Cannot get IRQ for net device, aborting.",
3530                                   dev->name);
3531                 goto err;
3532         }
3533
3534         phy_start(ugeth->phydev);
3535         napi_enable(&ugeth->napi);
3536         netif_start_queue(dev);
3537
3538         device_set_wakeup_capable(&dev->dev,
3539                         qe_alive_during_sleep() || ugeth->phydev->irq);
3540         device_set_wakeup_enable(&dev->dev, ugeth->wol_en);
3541
3542         return err;
3543
3544 err:
3545         ucc_geth_stop(ugeth);
3546         return err;
3547 }
3548
3549 /* Stops the kernel queue, and halts the controller */
3550 static int ucc_geth_close(struct net_device *dev)
3551 {
3552         struct ucc_geth_private *ugeth = netdev_priv(dev);
3553
3554         ugeth_vdbg("%s: IN", __func__);
3555
3556         napi_disable(&ugeth->napi);
3557
3558         ucc_geth_stop(ugeth);
3559
3560         free_irq(ugeth->ug_info->uf_info.irq, ugeth->ndev);
3561
3562         netif_stop_queue(dev);
3563
3564         return 0;
3565 }
3566
3567 /* Reopen device. This will reset the MAC and PHY. */
3568 static void ucc_geth_timeout_work(struct work_struct *work)
3569 {
3570         struct ucc_geth_private *ugeth;
3571         struct net_device *dev;
3572
3573         ugeth = container_of(work, struct ucc_geth_private, timeout_work);
3574         dev = ugeth->ndev;
3575
3576         ugeth_vdbg("%s: IN", __func__);
3577
3578         dev->stats.tx_errors++;
3579
3580         ugeth_dump_regs(ugeth);
3581
3582         if (dev->flags & IFF_UP) {
3583                 /*
3584                  * Must reset MAC *and* PHY. This is done by reopening
3585                  * the device.
3586                  */
3587                 ucc_geth_close(dev);
3588                 ucc_geth_open(dev);
3589         }
3590
3591         netif_tx_schedule_all(dev);
3592 }
3593
3594 /*
3595  * ucc_geth_timeout gets called when a packet has not been
3596  * transmitted after a set amount of time.
3597  */
3598 static void ucc_geth_timeout(struct net_device *dev)
3599 {
3600         struct ucc_geth_private *ugeth = netdev_priv(dev);
3601
3602         netif_carrier_off(dev);
3603         schedule_work(&ugeth->timeout_work);
3604 }
3605
3606
3607 #ifdef CONFIG_PM
3608
3609 static int ucc_geth_suspend(struct of_device *ofdev, pm_message_t state)
3610 {
3611         struct net_device *ndev = dev_get_drvdata(&ofdev->dev);
3612         struct ucc_geth_private *ugeth = netdev_priv(ndev);
3613
3614         if (!netif_running(ndev))
3615                 return 0;
3616
3617         netif_device_detach(ndev);
3618         napi_disable(&ugeth->napi);
3619
3620         /*
3621          * Disable the controller, otherwise we'll wakeup on any network
3622          * activity.
3623          */
3624         ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
3625
3626         if (ugeth->wol_en & WAKE_MAGIC) {
3627                 setbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD);
3628                 setbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE);
3629                 ucc_fast_enable(ugeth->uccf, COMM_DIR_RX_AND_TX);
3630         } else if (!(ugeth->wol_en & WAKE_PHY)) {
3631                 phy_stop(ugeth->phydev);
3632         }
3633
3634         return 0;
3635 }
3636
3637 static int ucc_geth_resume(struct of_device *ofdev)
3638 {
3639         struct net_device *ndev = dev_get_drvdata(&ofdev->dev);
3640         struct ucc_geth_private *ugeth = netdev_priv(ndev);
3641         int err;
3642
3643         if (!netif_running(ndev))
3644                 return 0;
3645
3646         if (qe_alive_during_sleep()) {
3647                 if (ugeth->wol_en & WAKE_MAGIC) {
3648                         ucc_fast_disable(ugeth->uccf, COMM_DIR_RX_AND_TX);
3649                         clrbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE);
3650                         clrbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD);
3651                 }
3652                 ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
3653         } else {
3654                 /*
3655                  * Full reinitialization is required if QE shuts down
3656                  * during sleep.
3657                  */
3658                 ucc_geth_memclean(ugeth);
3659
3660                 err = ucc_geth_init_mac(ugeth);
3661                 if (err) {
3662                         ugeth_err("%s: Cannot initialize MAC, aborting.",
3663                                   ndev->name);
3664                         return err;
3665                 }
3666         }
3667
3668         ugeth->oldlink = 0;
3669         ugeth->oldspeed = 0;
3670         ugeth->oldduplex = -1;
3671
3672         phy_stop(ugeth->phydev);
3673         phy_start(ugeth->phydev);
3674
3675         napi_enable(&ugeth->napi);
3676         netif_device_attach(ndev);
3677
3678         return 0;
3679 }
3680
3681 #else
3682 #define ucc_geth_suspend NULL
3683 #define ucc_geth_resume NULL
3684 #endif
3685
3686 static phy_interface_t to_phy_interface(const char *phy_connection_type)
3687 {
3688         if (strcasecmp(phy_connection_type, "mii") == 0)
3689                 return PHY_INTERFACE_MODE_MII;
3690         if (strcasecmp(phy_connection_type, "gmii") == 0)
3691                 return PHY_INTERFACE_MODE_GMII;
3692         if (strcasecmp(phy_connection_type, "tbi") == 0)
3693                 return PHY_INTERFACE_MODE_TBI;
3694         if (strcasecmp(phy_connection_type, "rmii") == 0)
3695                 return PHY_INTERFACE_MODE_RMII;
3696         if (strcasecmp(phy_connection_type, "rgmii") == 0)
3697                 return PHY_INTERFACE_MODE_RGMII;
3698         if (strcasecmp(phy_connection_type, "rgmii-id") == 0)
3699                 return PHY_INTERFACE_MODE_RGMII_ID;
3700         if (strcasecmp(phy_connection_type, "rgmii-txid") == 0)
3701                 return PHY_INTERFACE_MODE_RGMII_TXID;
3702         if (strcasecmp(phy_connection_type, "rgmii-rxid") == 0)
3703                 return PHY_INTERFACE_MODE_RGMII_RXID;
3704         if (strcasecmp(phy_connection_type, "rtbi") == 0)
3705                 return PHY_INTERFACE_MODE_RTBI;
3706         if (strcasecmp(phy_connection_type, "sgmii") == 0)
3707                 return PHY_INTERFACE_MODE_SGMII;
3708
3709         return PHY_INTERFACE_MODE_MII;
3710 }
3711
3712 static const struct net_device_ops ucc_geth_netdev_ops = {
3713         .ndo_open               = ucc_geth_open,
3714         .ndo_stop               = ucc_geth_close,
3715         .ndo_start_xmit         = ucc_geth_start_xmit,
3716         .ndo_validate_addr      = eth_validate_addr,
3717         .ndo_set_mac_address    = ucc_geth_set_mac_addr,
3718         .ndo_change_mtu         = eth_change_mtu,
3719         .ndo_set_multicast_list = ucc_geth_set_multi,
3720         .ndo_tx_timeout         = ucc_geth_timeout,
3721 #ifdef CONFIG_NET_POLL_CONTROLLER
3722         .ndo_poll_controller    = ucc_netpoll,
3723 #endif
3724 };
3725
3726 static int ucc_geth_probe(struct of_device* ofdev, const struct of_device_id *match)
3727 {
3728         struct device *device = &ofdev->dev;
3729         struct device_node *np = ofdev->node;
3730         struct net_device *dev = NULL;
3731         struct ucc_geth_private *ugeth = NULL;
3732         struct ucc_geth_info *ug_info;
3733         struct resource res;
3734         int err, ucc_num, max_speed = 0;
3735         const unsigned int *prop;
3736         const char *sprop;
3737         const void *mac_addr;
3738         phy_interface_t phy_interface;
3739         static const int enet_to_speed[] = {
3740                 SPEED_10, SPEED_10, SPEED_10,
3741                 SPEED_100, SPEED_100, SPEED_100,
3742                 SPEED_1000, SPEED_1000, SPEED_1000, SPEED_1000,
3743         };
3744         static const phy_interface_t enet_to_phy_interface[] = {
3745                 PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_RMII,
3746                 PHY_INTERFACE_MODE_RGMII, PHY_INTERFACE_MODE_MII,
3747                 PHY_INTERFACE_MODE_RMII, PHY_INTERFACE_MODE_RGMII,
3748                 PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_RGMII,
3749                 PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RTBI,
3750                 PHY_INTERFACE_MODE_SGMII,
3751         };
3752
3753         ugeth_vdbg("%s: IN", __func__);
3754
3755         prop = of_get_property(np, "cell-index", NULL);
3756         if (!prop) {
3757                 prop = of_get_property(np, "device-id", NULL);
3758                 if (!prop)
3759                         return -ENODEV;
3760         }
3761
3762         ucc_num = *prop - 1;
3763         if ((ucc_num < 0) || (ucc_num > 7))
3764                 return -ENODEV;
3765
3766         ug_info = &ugeth_info[ucc_num];
3767         if (ug_info == NULL) {
3768                 if (netif_msg_probe(&debug))
3769                         ugeth_err("%s: [%d] Missing additional data!",
3770                                         __func__, ucc_num);
3771                 return -ENODEV;
3772         }
3773
3774         ug_info->uf_info.ucc_num = ucc_num;
3775
3776         sprop = of_get_property(np, "rx-clock-name", NULL);
3777         if (sprop) {
3778                 ug_info->uf_info.rx_clock = qe_clock_source(sprop);
3779                 if ((ug_info->uf_info.rx_clock < QE_CLK_NONE) ||
3780                     (ug_info->uf_info.rx_clock > QE_CLK24)) {
3781                         printk(KERN_ERR
3782                                 "ucc_geth: invalid rx-clock-name property\n");
3783                         return -EINVAL;
3784                 }
3785         } else {
3786                 prop = of_get_property(np, "rx-clock", NULL);
3787                 if (!prop) {
3788                         /* If both rx-clock-name and rx-clock are missing,
3789                            we want to tell people to use rx-clock-name. */
3790                         printk(KERN_ERR
3791                                 "ucc_geth: missing rx-clock-name property\n");
3792                         return -EINVAL;
3793                 }
3794                 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3795                         printk(KERN_ERR
3796                                 "ucc_geth: invalid rx-clock propperty\n");
3797                         return -EINVAL;
3798                 }
3799                 ug_info->uf_info.rx_clock = *prop;
3800         }
3801
3802         sprop = of_get_property(np, "tx-clock-name", NULL);
3803         if (sprop) {
3804                 ug_info->uf_info.tx_clock = qe_clock_source(sprop);
3805                 if ((ug_info->uf_info.tx_clock < QE_CLK_NONE) ||
3806                     (ug_info->uf_info.tx_clock > QE_CLK24)) {
3807                         printk(KERN_ERR
3808                                 "ucc_geth: invalid tx-clock-name property\n");
3809                         return -EINVAL;
3810                 }
3811         } else {
3812                 prop = of_get_property(np, "tx-clock", NULL);
3813                 if (!prop) {
3814                         printk(KERN_ERR
3815                                 "ucc_geth: missing tx-clock-name property\n");
3816                         return -EINVAL;
3817                 }
3818                 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3819                         printk(KERN_ERR
3820                                 "ucc_geth: invalid tx-clock property\n");
3821                         return -EINVAL;
3822                 }
3823                 ug_info->uf_info.tx_clock = *prop;
3824         }
3825
3826         err = of_address_to_resource(np, 0, &res);
3827         if (err)
3828                 return -EINVAL;
3829
3830         ug_info->uf_info.regs = res.start;
3831         ug_info->uf_info.irq = irq_of_parse_and_map(np, 0);
3832
3833         ug_info->phy_node = of_parse_phandle(np, "phy-handle", 0);
3834
3835         /* Find the TBI PHY node.  If it's not there, we don't support SGMII */
3836         ug_info->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
3837
3838         /* get the phy interface type, or default to MII */
3839         prop = of_get_property(np, "phy-connection-type", NULL);
3840         if (!prop) {
3841                 /* handle interface property present in old trees */
3842                 prop = of_get_property(ug_info->phy_node, "interface", NULL);
3843                 if (prop != NULL) {
3844                         phy_interface = enet_to_phy_interface[*prop];
3845                         max_speed = enet_to_speed[*prop];
3846                 } else
3847                         phy_interface = PHY_INTERFACE_MODE_MII;
3848         } else {
3849                 phy_interface = to_phy_interface((const char *)prop);
3850         }
3851
3852         /* get speed, or derive from PHY interface */
3853         if (max_speed == 0)
3854                 switch (phy_interface) {
3855                 case PHY_INTERFACE_MODE_GMII:
3856                 case PHY_INTERFACE_MODE_RGMII:
3857                 case PHY_INTERFACE_MODE_RGMII_ID:
3858                 case PHY_INTERFACE_MODE_RGMII_RXID:
3859                 case PHY_INTERFACE_MODE_RGMII_TXID:
3860                 case PHY_INTERFACE_MODE_TBI:
3861                 case PHY_INTERFACE_MODE_RTBI:
3862                 case PHY_INTERFACE_MODE_SGMII:
3863                         max_speed = SPEED_1000;
3864                         break;
3865                 default:
3866                         max_speed = SPEED_100;
3867                         break;
3868                 }
3869
3870         if (max_speed == SPEED_1000) {
3871                 /* configure muram FIFOs for gigabit operation */
3872                 ug_info->uf_info.urfs = UCC_GETH_URFS_GIGA_INIT;
3873                 ug_info->uf_info.urfet = UCC_GETH_URFET_GIGA_INIT;
3874                 ug_info->uf_info.urfset = UCC_GETH_URFSET_GIGA_INIT;
3875                 ug_info->uf_info.utfs = UCC_GETH_UTFS_GIGA_INIT;
3876                 ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT;
3877                 ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT;
3878                 ug_info->numThreadsTx = UCC_GETH_NUM_OF_THREADS_4;
3879
3880                 /* If QE's snum number is 46 which means we need to support
3881                  * 4 UECs at 1000Base-T simultaneously, we need to allocate
3882                  * more Threads to Rx.
3883                  */
3884                 if (qe_get_num_of_snums() == 46)
3885                         ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_6;
3886                 else
3887                         ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4;
3888         }
3889
3890         if (netif_msg_probe(&debug))
3891                 printk(KERN_INFO "ucc_geth: UCC%1d at 0x%8x (irq = %d) \n",
3892                         ug_info->uf_info.ucc_num + 1, ug_info->uf_info.regs,
3893                         ug_info->uf_info.irq);
3894
3895         /* Create an ethernet device instance */
3896         dev = alloc_etherdev(sizeof(*ugeth));
3897
3898         if (dev == NULL)
3899                 return -ENOMEM;
3900
3901         ugeth = netdev_priv(dev);
3902         spin_lock_init(&ugeth->lock);
3903
3904         /* Create CQs for hash tables */
3905         INIT_LIST_HEAD(&ugeth->group_hash_q);
3906         INIT_LIST_HEAD(&ugeth->ind_hash_q);
3907
3908         dev_set_drvdata(device, dev);
3909
3910         /* Set the dev->base_addr to the gfar reg region */
3911         dev->base_addr = (unsigned long)(ug_info->uf_info.regs);
3912
3913         SET_NETDEV_DEV(dev, device);
3914
3915         /* Fill in the dev structure */
3916         uec_set_ethtool_ops(dev);
3917         dev->netdev_ops = &ucc_geth_netdev_ops;
3918         dev->watchdog_timeo = TX_TIMEOUT;
3919         INIT_WORK(&ugeth->timeout_work, ucc_geth_timeout_work);
3920         netif_napi_add(dev, &ugeth->napi, ucc_geth_poll, 64);
3921         dev->mtu = 1500;
3922
3923         ugeth->msg_enable = netif_msg_init(debug.msg_enable, UGETH_MSG_DEFAULT);
3924         ugeth->phy_interface = phy_interface;
3925         ugeth->max_speed = max_speed;
3926
3927         err = register_netdev(dev);
3928         if (err) {
3929                 if (netif_msg_probe(ugeth))
3930                         ugeth_err("%s: Cannot register net device, aborting.",
3931                                   dev->name);
3932                 free_netdev(dev);
3933                 return err;
3934         }
3935
3936         mac_addr = of_get_mac_address(np);
3937         if (mac_addr)
3938                 memcpy(dev->dev_addr, mac_addr, 6);
3939
3940         ugeth->ug_info = ug_info;
3941         ugeth->dev = device;
3942         ugeth->ndev = dev;
3943         ugeth->node = np;
3944
3945         return 0;
3946 }
3947
3948 static int ucc_geth_remove(struct of_device* ofdev)
3949 {
3950         struct device *device = &ofdev->dev;
3951         struct net_device *dev = dev_get_drvdata(device);
3952         struct ucc_geth_private *ugeth = netdev_priv(dev);
3953
3954         unregister_netdev(dev);
3955         free_netdev(dev);
3956         ucc_geth_memclean(ugeth);
3957         dev_set_drvdata(device, NULL);
3958
3959         return 0;
3960 }
3961
3962 static struct of_device_id ucc_geth_match[] = {
3963         {
3964                 .type = "network",
3965                 .compatible = "ucc_geth",
3966         },
3967         {},
3968 };
3969
3970 MODULE_DEVICE_TABLE(of, ucc_geth_match);
3971
3972 static struct of_platform_driver ucc_geth_driver = {
3973         .name           = DRV_NAME,
3974         .match_table    = ucc_geth_match,
3975         .probe          = ucc_geth_probe,
3976         .remove         = ucc_geth_remove,
3977         .suspend        = ucc_geth_suspend,
3978         .resume         = ucc_geth_resume,
3979 };
3980
3981 static int __init ucc_geth_init(void)
3982 {
3983         int i, ret;
3984
3985         if (netif_msg_drv(&debug))
3986                 printk(KERN_INFO "ucc_geth: " DRV_DESC "\n");
3987         for (i = 0; i < 8; i++)
3988                 memcpy(&(ugeth_info[i]), &ugeth_primary_info,
3989                        sizeof(ugeth_primary_info));
3990
3991         ret = of_register_platform_driver(&ucc_geth_driver);
3992
3993         return ret;
3994 }
3995
3996 static void __exit ucc_geth_exit(void)
3997 {
3998         of_unregister_platform_driver(&ucc_geth_driver);
3999 }
4000
4001 module_init(ucc_geth_init);
4002 module_exit(ucc_geth_exit);
4003
4004 MODULE_AUTHOR("Freescale Semiconductor, Inc");
4005 MODULE_DESCRIPTION(DRV_DESC);
4006 MODULE_VERSION(DRV_VERSION);
4007 MODULE_LICENSE("GPL");