52a6750b82015c85ee808bd530cf94f233361041
[linux-2.6.git] / drivers / net / ucc_geth.c
1 /*
2  * Copyright (C) 2006-2009 Freescale Semicondutor, Inc. All rights reserved.
3  *
4  * Author: Shlomi Gridish <gridish@freescale.com>
5  *         Li Yang <leoli@freescale.com>
6  *
7  * Description:
8  * QE UCC Gigabit Ethernet Driver
9  *
10  * This program is free software; you can redistribute  it and/or modify it
11  * under  the terms of  the GNU General  Public License as published by the
12  * Free Software Foundation;  either version 2 of the  License, or (at your
13  * option) any later version.
14  */
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/slab.h>
19 #include <linux/stddef.h>
20 #include <linux/interrupt.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/skbuff.h>
24 #include <linux/spinlock.h>
25 #include <linux/mm.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/mii.h>
28 #include <linux/phy.h>
29 #include <linux/workqueue.h>
30 #include <linux/of_mdio.h>
31 #include <linux/of_platform.h>
32
33 #include <asm/uaccess.h>
34 #include <asm/irq.h>
35 #include <asm/io.h>
36 #include <asm/immap_qe.h>
37 #include <asm/qe.h>
38 #include <asm/ucc.h>
39 #include <asm/ucc_fast.h>
40
41 #include "ucc_geth.h"
42 #include "fsl_pq_mdio.h"
43
44 #undef DEBUG
45
46 #define ugeth_printk(level, format, arg...)  \
47         printk(level format "\n", ## arg)
48
49 #define ugeth_dbg(format, arg...)            \
50         ugeth_printk(KERN_DEBUG , format , ## arg)
51 #define ugeth_err(format, arg...)            \
52         ugeth_printk(KERN_ERR , format , ## arg)
53 #define ugeth_info(format, arg...)           \
54         ugeth_printk(KERN_INFO , format , ## arg)
55 #define ugeth_warn(format, arg...)           \
56         ugeth_printk(KERN_WARNING , format , ## arg)
57
58 #ifdef UGETH_VERBOSE_DEBUG
59 #define ugeth_vdbg ugeth_dbg
60 #else
61 #define ugeth_vdbg(fmt, args...) do { } while (0)
62 #endif                          /* UGETH_VERBOSE_DEBUG */
63 #define UGETH_MSG_DEFAULT       (NETIF_MSG_IFUP << 1 ) - 1
64
65
66 static DEFINE_SPINLOCK(ugeth_lock);
67
68 static struct {
69         u32 msg_enable;
70 } debug = { -1 };
71
72 module_param_named(debug, debug.msg_enable, int, 0);
73 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 0xffff=all)");
74
75 static struct ucc_geth_info ugeth_primary_info = {
76         .uf_info = {
77                     .bd_mem_part = MEM_PART_SYSTEM,
78                     .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES,
79                     .max_rx_buf_length = 1536,
80                     /* adjusted at startup if max-speed 1000 */
81                     .urfs = UCC_GETH_URFS_INIT,
82                     .urfet = UCC_GETH_URFET_INIT,
83                     .urfset = UCC_GETH_URFSET_INIT,
84                     .utfs = UCC_GETH_UTFS_INIT,
85                     .utfet = UCC_GETH_UTFET_INIT,
86                     .utftt = UCC_GETH_UTFTT_INIT,
87                     .ufpt = 256,
88                     .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET,
89                     .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
90                     .tenc = UCC_FAST_TX_ENCODING_NRZ,
91                     .renc = UCC_FAST_RX_ENCODING_NRZ,
92                     .tcrc = UCC_FAST_16_BIT_CRC,
93                     .synl = UCC_FAST_SYNC_LEN_NOT_USED,
94                     },
95         .numQueuesTx = 1,
96         .numQueuesRx = 1,
97         .extendedFilteringChainPointer = ((uint32_t) NULL),
98         .typeorlen = 3072 /*1536 */ ,
99         .nonBackToBackIfgPart1 = 0x40,
100         .nonBackToBackIfgPart2 = 0x60,
101         .miminumInterFrameGapEnforcement = 0x50,
102         .backToBackInterFrameGap = 0x60,
103         .mblinterval = 128,
104         .nortsrbytetime = 5,
105         .fracsiz = 1,
106         .strictpriorityq = 0xff,
107         .altBebTruncation = 0xa,
108         .excessDefer = 1,
109         .maxRetransmission = 0xf,
110         .collisionWindow = 0x37,
111         .receiveFlowControl = 1,
112         .transmitFlowControl = 1,
113         .maxGroupAddrInHash = 4,
114         .maxIndAddrInHash = 4,
115         .prel = 7,
116         .maxFrameLength = 1518,
117         .minFrameLength = 64,
118         .maxD1Length = 1520,
119         .maxD2Length = 1520,
120         .vlantype = 0x8100,
121         .ecamptr = ((uint32_t) NULL),
122         .eventRegMask = UCCE_OTHER,
123         .pausePeriod = 0xf000,
124         .interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1},
125         .bdRingLenTx = {
126                         TX_BD_RING_LEN,
127                         TX_BD_RING_LEN,
128                         TX_BD_RING_LEN,
129                         TX_BD_RING_LEN,
130                         TX_BD_RING_LEN,
131                         TX_BD_RING_LEN,
132                         TX_BD_RING_LEN,
133                         TX_BD_RING_LEN},
134
135         .bdRingLenRx = {
136                         RX_BD_RING_LEN,
137                         RX_BD_RING_LEN,
138                         RX_BD_RING_LEN,
139                         RX_BD_RING_LEN,
140                         RX_BD_RING_LEN,
141                         RX_BD_RING_LEN,
142                         RX_BD_RING_LEN,
143                         RX_BD_RING_LEN},
144
145         .numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1,
146         .largestexternallookupkeysize =
147             QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE,
148         .statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE |
149                 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX |
150                 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX,
151         .vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP,
152         .vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP,
153         .rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT,
154         .aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE,
155         .padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC,
156         .numThreadsTx = UCC_GETH_NUM_OF_THREADS_1,
157         .numThreadsRx = UCC_GETH_NUM_OF_THREADS_1,
158         .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
159         .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
160 };
161
162 static struct ucc_geth_info ugeth_info[8];
163
164 #ifdef DEBUG
165 static void mem_disp(u8 *addr, int size)
166 {
167         u8 *i;
168         int size16Aling = (size >> 4) << 4;
169         int size4Aling = (size >> 2) << 2;
170         int notAlign = 0;
171         if (size % 16)
172                 notAlign = 1;
173
174         for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16)
175                 printk("0x%08x: %08x %08x %08x %08x\r\n",
176                        (u32) i,
177                        *((u32 *) (i)),
178                        *((u32 *) (i + 4)),
179                        *((u32 *) (i + 8)), *((u32 *) (i + 12)));
180         if (notAlign == 1)
181                 printk("0x%08x: ", (u32) i);
182         for (; (u32) i < (u32) addr + size4Aling; i += 4)
183                 printk("%08x ", *((u32 *) (i)));
184         for (; (u32) i < (u32) addr + size; i++)
185                 printk("%02x", *((u8 *) (i)));
186         if (notAlign == 1)
187                 printk("\r\n");
188 }
189 #endif /* DEBUG */
190
191 static struct list_head *dequeue(struct list_head *lh)
192 {
193         unsigned long flags;
194
195         spin_lock_irqsave(&ugeth_lock, flags);
196         if (!list_empty(lh)) {
197                 struct list_head *node = lh->next;
198                 list_del(node);
199                 spin_unlock_irqrestore(&ugeth_lock, flags);
200                 return node;
201         } else {
202                 spin_unlock_irqrestore(&ugeth_lock, flags);
203                 return NULL;
204         }
205 }
206
207 static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth,
208                 u8 __iomem *bd)
209 {
210         struct sk_buff *skb = NULL;
211
212         skb = __skb_dequeue(&ugeth->rx_recycle);
213         if (!skb)
214                 skb = dev_alloc_skb(ugeth->ug_info->uf_info.max_rx_buf_length +
215                                     UCC_GETH_RX_DATA_BUF_ALIGNMENT);
216         if (skb == NULL)
217                 return NULL;
218
219         /* We need the data buffer to be aligned properly.  We will reserve
220          * as many bytes as needed to align the data properly
221          */
222         skb_reserve(skb,
223                     UCC_GETH_RX_DATA_BUF_ALIGNMENT -
224                     (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT -
225                                               1)));
226
227         skb->dev = ugeth->ndev;
228
229         out_be32(&((struct qe_bd __iomem *)bd)->buf,
230                       dma_map_single(ugeth->dev,
231                                      skb->data,
232                                      ugeth->ug_info->uf_info.max_rx_buf_length +
233                                      UCC_GETH_RX_DATA_BUF_ALIGNMENT,
234                                      DMA_FROM_DEVICE));
235
236         out_be32((u32 __iomem *)bd,
237                         (R_E | R_I | (in_be32((u32 __iomem*)bd) & R_W)));
238
239         return skb;
240 }
241
242 static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ)
243 {
244         u8 __iomem *bd;
245         u32 bd_status;
246         struct sk_buff *skb;
247         int i;
248
249         bd = ugeth->p_rx_bd_ring[rxQ];
250         i = 0;
251
252         do {
253                 bd_status = in_be32((u32 __iomem *)bd);
254                 skb = get_new_skb(ugeth, bd);
255
256                 if (!skb)       /* If can not allocate data buffer,
257                                 abort. Cleanup will be elsewhere */
258                         return -ENOMEM;
259
260                 ugeth->rx_skbuff[rxQ][i] = skb;
261
262                 /* advance the BD pointer */
263                 bd += sizeof(struct qe_bd);
264                 i++;
265         } while (!(bd_status & R_W));
266
267         return 0;
268 }
269
270 static int fill_init_enet_entries(struct ucc_geth_private *ugeth,
271                                   u32 *p_start,
272                                   u8 num_entries,
273                                   u32 thread_size,
274                                   u32 thread_alignment,
275                                   unsigned int risc,
276                                   int skip_page_for_first_entry)
277 {
278         u32 init_enet_offset;
279         u8 i;
280         int snum;
281
282         for (i = 0; i < num_entries; i++) {
283                 if ((snum = qe_get_snum()) < 0) {
284                         if (netif_msg_ifup(ugeth))
285                                 ugeth_err("fill_init_enet_entries: Can not get SNUM.");
286                         return snum;
287                 }
288                 if ((i == 0) && skip_page_for_first_entry)
289                 /* First entry of Rx does not have page */
290                         init_enet_offset = 0;
291                 else {
292                         init_enet_offset =
293                             qe_muram_alloc(thread_size, thread_alignment);
294                         if (IS_ERR_VALUE(init_enet_offset)) {
295                                 if (netif_msg_ifup(ugeth))
296                                         ugeth_err("fill_init_enet_entries: Can not allocate DPRAM memory.");
297                                 qe_put_snum((u8) snum);
298                                 return -ENOMEM;
299                         }
300                 }
301                 *(p_start++) =
302                     ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset
303                     | risc;
304         }
305
306         return 0;
307 }
308
309 static int return_init_enet_entries(struct ucc_geth_private *ugeth,
310                                     u32 *p_start,
311                                     u8 num_entries,
312                                     unsigned int risc,
313                                     int skip_page_for_first_entry)
314 {
315         u32 init_enet_offset;
316         u8 i;
317         int snum;
318
319         for (i = 0; i < num_entries; i++) {
320                 u32 val = *p_start;
321
322                 /* Check that this entry was actually valid --
323                 needed in case failed in allocations */
324                 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
325                         snum =
326                             (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
327                             ENET_INIT_PARAM_SNUM_SHIFT;
328                         qe_put_snum((u8) snum);
329                         if (!((i == 0) && skip_page_for_first_entry)) {
330                         /* First entry of Rx does not have page */
331                                 init_enet_offset =
332                                     (val & ENET_INIT_PARAM_PTR_MASK);
333                                 qe_muram_free(init_enet_offset);
334                         }
335                         *p_start++ = 0;
336                 }
337         }
338
339         return 0;
340 }
341
342 #ifdef DEBUG
343 static int dump_init_enet_entries(struct ucc_geth_private *ugeth,
344                                   u32 __iomem *p_start,
345                                   u8 num_entries,
346                                   u32 thread_size,
347                                   unsigned int risc,
348                                   int skip_page_for_first_entry)
349 {
350         u32 init_enet_offset;
351         u8 i;
352         int snum;
353
354         for (i = 0; i < num_entries; i++) {
355                 u32 val = in_be32(p_start);
356
357                 /* Check that this entry was actually valid --
358                 needed in case failed in allocations */
359                 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
360                         snum =
361                             (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
362                             ENET_INIT_PARAM_SNUM_SHIFT;
363                         qe_put_snum((u8) snum);
364                         if (!((i == 0) && skip_page_for_first_entry)) {
365                         /* First entry of Rx does not have page */
366                                 init_enet_offset =
367                                     (in_be32(p_start) &
368                                      ENET_INIT_PARAM_PTR_MASK);
369                                 ugeth_info("Init enet entry %d:", i);
370                                 ugeth_info("Base address: 0x%08x",
371                                            (u32)
372                                            qe_muram_addr(init_enet_offset));
373                                 mem_disp(qe_muram_addr(init_enet_offset),
374                                          thread_size);
375                         }
376                         p_start++;
377                 }
378         }
379
380         return 0;
381 }
382 #endif
383
384 static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont)
385 {
386         kfree(enet_addr_cont);
387 }
388
389 static void set_mac_addr(__be16 __iomem *reg, u8 *mac)
390 {
391         out_be16(&reg[0], ((u16)mac[5] << 8) | mac[4]);
392         out_be16(&reg[1], ((u16)mac[3] << 8) | mac[2]);
393         out_be16(&reg[2], ((u16)mac[1] << 8) | mac[0]);
394 }
395
396 static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num)
397 {
398         struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
399
400         if (!(paddr_num < NUM_OF_PADDRS)) {
401                 ugeth_warn("%s: Illagel paddr_num.", __func__);
402                 return -EINVAL;
403         }
404
405         p_82xx_addr_filt =
406             (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
407             addressfiltering;
408
409         /* Writing address ff.ff.ff.ff.ff.ff disables address
410         recognition for this register */
411         out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff);
412         out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff);
413         out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff);
414
415         return 0;
416 }
417
418 static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth,
419                                 u8 *p_enet_addr)
420 {
421         struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
422         u32 cecr_subblock;
423
424         p_82xx_addr_filt =
425             (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
426             addressfiltering;
427
428         cecr_subblock =
429             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
430
431         /* Ethernet frames are defined in Little Endian mode,
432         therefor to insert */
433         /* the address to the hash (Big Endian mode), we reverse the bytes.*/
434
435         set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr);
436
437         qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock,
438                      QE_CR_PROTOCOL_ETHERNET, 0);
439 }
440
441 #ifdef CONFIG_UGETH_MAGIC_PACKET
442 static void magic_packet_detection_enable(struct ucc_geth_private *ugeth)
443 {
444         struct ucc_fast_private *uccf;
445         struct ucc_geth __iomem *ug_regs;
446
447         uccf = ugeth->uccf;
448         ug_regs = ugeth->ug_regs;
449
450         /* Enable interrupts for magic packet detection */
451         setbits32(uccf->p_uccm, UCC_GETH_UCCE_MPD);
452
453         /* Enable magic packet detection */
454         setbits32(&ug_regs->maccfg2, MACCFG2_MPE);
455 }
456
457 static void magic_packet_detection_disable(struct ucc_geth_private *ugeth)
458 {
459         struct ucc_fast_private *uccf;
460         struct ucc_geth __iomem *ug_regs;
461
462         uccf = ugeth->uccf;
463         ug_regs = ugeth->ug_regs;
464
465         /* Disable interrupts for magic packet detection */
466         clrbits32(uccf->p_uccm, UCC_GETH_UCCE_MPD);
467
468         /* Disable magic packet detection */
469         clrbits32(&ug_regs->maccfg2, MACCFG2_MPE);
470 }
471 #endif /* MAGIC_PACKET */
472
473 static inline int compare_addr(u8 **addr1, u8 **addr2)
474 {
475         return memcmp(addr1, addr2, ENET_NUM_OCTETS_PER_ADDRESS);
476 }
477
478 #ifdef DEBUG
479 static void get_statistics(struct ucc_geth_private *ugeth,
480                            struct ucc_geth_tx_firmware_statistics *
481                            tx_firmware_statistics,
482                            struct ucc_geth_rx_firmware_statistics *
483                            rx_firmware_statistics,
484                            struct ucc_geth_hardware_statistics *hardware_statistics)
485 {
486         struct ucc_fast __iomem *uf_regs;
487         struct ucc_geth __iomem *ug_regs;
488         struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram;
489         struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram;
490
491         ug_regs = ugeth->ug_regs;
492         uf_regs = (struct ucc_fast __iomem *) ug_regs;
493         p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram;
494         p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram;
495
496         /* Tx firmware only if user handed pointer and driver actually
497         gathers Tx firmware statistics */
498         if (tx_firmware_statistics && p_tx_fw_statistics_pram) {
499                 tx_firmware_statistics->sicoltx =
500                     in_be32(&p_tx_fw_statistics_pram->sicoltx);
501                 tx_firmware_statistics->mulcoltx =
502                     in_be32(&p_tx_fw_statistics_pram->mulcoltx);
503                 tx_firmware_statistics->latecoltxfr =
504                     in_be32(&p_tx_fw_statistics_pram->latecoltxfr);
505                 tx_firmware_statistics->frabortduecol =
506                     in_be32(&p_tx_fw_statistics_pram->frabortduecol);
507                 tx_firmware_statistics->frlostinmactxer =
508                     in_be32(&p_tx_fw_statistics_pram->frlostinmactxer);
509                 tx_firmware_statistics->carriersenseertx =
510                     in_be32(&p_tx_fw_statistics_pram->carriersenseertx);
511                 tx_firmware_statistics->frtxok =
512                     in_be32(&p_tx_fw_statistics_pram->frtxok);
513                 tx_firmware_statistics->txfrexcessivedefer =
514                     in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer);
515                 tx_firmware_statistics->txpkts256 =
516                     in_be32(&p_tx_fw_statistics_pram->txpkts256);
517                 tx_firmware_statistics->txpkts512 =
518                     in_be32(&p_tx_fw_statistics_pram->txpkts512);
519                 tx_firmware_statistics->txpkts1024 =
520                     in_be32(&p_tx_fw_statistics_pram->txpkts1024);
521                 tx_firmware_statistics->txpktsjumbo =
522                     in_be32(&p_tx_fw_statistics_pram->txpktsjumbo);
523         }
524
525         /* Rx firmware only if user handed pointer and driver actually
526          * gathers Rx firmware statistics */
527         if (rx_firmware_statistics && p_rx_fw_statistics_pram) {
528                 int i;
529                 rx_firmware_statistics->frrxfcser =
530                     in_be32(&p_rx_fw_statistics_pram->frrxfcser);
531                 rx_firmware_statistics->fraligner =
532                     in_be32(&p_rx_fw_statistics_pram->fraligner);
533                 rx_firmware_statistics->inrangelenrxer =
534                     in_be32(&p_rx_fw_statistics_pram->inrangelenrxer);
535                 rx_firmware_statistics->outrangelenrxer =
536                     in_be32(&p_rx_fw_statistics_pram->outrangelenrxer);
537                 rx_firmware_statistics->frtoolong =
538                     in_be32(&p_rx_fw_statistics_pram->frtoolong);
539                 rx_firmware_statistics->runt =
540                     in_be32(&p_rx_fw_statistics_pram->runt);
541                 rx_firmware_statistics->verylongevent =
542                     in_be32(&p_rx_fw_statistics_pram->verylongevent);
543                 rx_firmware_statistics->symbolerror =
544                     in_be32(&p_rx_fw_statistics_pram->symbolerror);
545                 rx_firmware_statistics->dropbsy =
546                     in_be32(&p_rx_fw_statistics_pram->dropbsy);
547                 for (i = 0; i < 0x8; i++)
548                         rx_firmware_statistics->res0[i] =
549                             p_rx_fw_statistics_pram->res0[i];
550                 rx_firmware_statistics->mismatchdrop =
551                     in_be32(&p_rx_fw_statistics_pram->mismatchdrop);
552                 rx_firmware_statistics->underpkts =
553                     in_be32(&p_rx_fw_statistics_pram->underpkts);
554                 rx_firmware_statistics->pkts256 =
555                     in_be32(&p_rx_fw_statistics_pram->pkts256);
556                 rx_firmware_statistics->pkts512 =
557                     in_be32(&p_rx_fw_statistics_pram->pkts512);
558                 rx_firmware_statistics->pkts1024 =
559                     in_be32(&p_rx_fw_statistics_pram->pkts1024);
560                 rx_firmware_statistics->pktsjumbo =
561                     in_be32(&p_rx_fw_statistics_pram->pktsjumbo);
562                 rx_firmware_statistics->frlossinmacer =
563                     in_be32(&p_rx_fw_statistics_pram->frlossinmacer);
564                 rx_firmware_statistics->pausefr =
565                     in_be32(&p_rx_fw_statistics_pram->pausefr);
566                 for (i = 0; i < 0x4; i++)
567                         rx_firmware_statistics->res1[i] =
568                             p_rx_fw_statistics_pram->res1[i];
569                 rx_firmware_statistics->removevlan =
570                     in_be32(&p_rx_fw_statistics_pram->removevlan);
571                 rx_firmware_statistics->replacevlan =
572                     in_be32(&p_rx_fw_statistics_pram->replacevlan);
573                 rx_firmware_statistics->insertvlan =
574                     in_be32(&p_rx_fw_statistics_pram->insertvlan);
575         }
576
577         /* Hardware only if user handed pointer and driver actually
578         gathers hardware statistics */
579         if (hardware_statistics &&
580             (in_be32(&uf_regs->upsmr) & UCC_GETH_UPSMR_HSE)) {
581                 hardware_statistics->tx64 = in_be32(&ug_regs->tx64);
582                 hardware_statistics->tx127 = in_be32(&ug_regs->tx127);
583                 hardware_statistics->tx255 = in_be32(&ug_regs->tx255);
584                 hardware_statistics->rx64 = in_be32(&ug_regs->rx64);
585                 hardware_statistics->rx127 = in_be32(&ug_regs->rx127);
586                 hardware_statistics->rx255 = in_be32(&ug_regs->rx255);
587                 hardware_statistics->txok = in_be32(&ug_regs->txok);
588                 hardware_statistics->txcf = in_be16(&ug_regs->txcf);
589                 hardware_statistics->tmca = in_be32(&ug_regs->tmca);
590                 hardware_statistics->tbca = in_be32(&ug_regs->tbca);
591                 hardware_statistics->rxfok = in_be32(&ug_regs->rxfok);
592                 hardware_statistics->rxbok = in_be32(&ug_regs->rxbok);
593                 hardware_statistics->rbyt = in_be32(&ug_regs->rbyt);
594                 hardware_statistics->rmca = in_be32(&ug_regs->rmca);
595                 hardware_statistics->rbca = in_be32(&ug_regs->rbca);
596         }
597 }
598
599 static void dump_bds(struct ucc_geth_private *ugeth)
600 {
601         int i;
602         int length;
603
604         for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
605                 if (ugeth->p_tx_bd_ring[i]) {
606                         length =
607                             (ugeth->ug_info->bdRingLenTx[i] *
608                              sizeof(struct qe_bd));
609                         ugeth_info("TX BDs[%d]", i);
610                         mem_disp(ugeth->p_tx_bd_ring[i], length);
611                 }
612         }
613         for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
614                 if (ugeth->p_rx_bd_ring[i]) {
615                         length =
616                             (ugeth->ug_info->bdRingLenRx[i] *
617                              sizeof(struct qe_bd));
618                         ugeth_info("RX BDs[%d]", i);
619                         mem_disp(ugeth->p_rx_bd_ring[i], length);
620                 }
621         }
622 }
623
624 static void dump_regs(struct ucc_geth_private *ugeth)
625 {
626         int i;
627
628         ugeth_info("UCC%d Geth registers:", ugeth->ug_info->uf_info.ucc_num);
629         ugeth_info("Base address: 0x%08x", (u32) ugeth->ug_regs);
630
631         ugeth_info("maccfg1    : addr - 0x%08x, val - 0x%08x",
632                    (u32) & ugeth->ug_regs->maccfg1,
633                    in_be32(&ugeth->ug_regs->maccfg1));
634         ugeth_info("maccfg2    : addr - 0x%08x, val - 0x%08x",
635                    (u32) & ugeth->ug_regs->maccfg2,
636                    in_be32(&ugeth->ug_regs->maccfg2));
637         ugeth_info("ipgifg     : addr - 0x%08x, val - 0x%08x",
638                    (u32) & ugeth->ug_regs->ipgifg,
639                    in_be32(&ugeth->ug_regs->ipgifg));
640         ugeth_info("hafdup     : addr - 0x%08x, val - 0x%08x",
641                    (u32) & ugeth->ug_regs->hafdup,
642                    in_be32(&ugeth->ug_regs->hafdup));
643         ugeth_info("ifctl      : addr - 0x%08x, val - 0x%08x",
644                    (u32) & ugeth->ug_regs->ifctl,
645                    in_be32(&ugeth->ug_regs->ifctl));
646         ugeth_info("ifstat     : addr - 0x%08x, val - 0x%08x",
647                    (u32) & ugeth->ug_regs->ifstat,
648                    in_be32(&ugeth->ug_regs->ifstat));
649         ugeth_info("macstnaddr1: addr - 0x%08x, val - 0x%08x",
650                    (u32) & ugeth->ug_regs->macstnaddr1,
651                    in_be32(&ugeth->ug_regs->macstnaddr1));
652         ugeth_info("macstnaddr2: addr - 0x%08x, val - 0x%08x",
653                    (u32) & ugeth->ug_regs->macstnaddr2,
654                    in_be32(&ugeth->ug_regs->macstnaddr2));
655         ugeth_info("uempr      : addr - 0x%08x, val - 0x%08x",
656                    (u32) & ugeth->ug_regs->uempr,
657                    in_be32(&ugeth->ug_regs->uempr));
658         ugeth_info("utbipar    : addr - 0x%08x, val - 0x%08x",
659                    (u32) & ugeth->ug_regs->utbipar,
660                    in_be32(&ugeth->ug_regs->utbipar));
661         ugeth_info("uescr      : addr - 0x%08x, val - 0x%04x",
662                    (u32) & ugeth->ug_regs->uescr,
663                    in_be16(&ugeth->ug_regs->uescr));
664         ugeth_info("tx64       : addr - 0x%08x, val - 0x%08x",
665                    (u32) & ugeth->ug_regs->tx64,
666                    in_be32(&ugeth->ug_regs->tx64));
667         ugeth_info("tx127      : addr - 0x%08x, val - 0x%08x",
668                    (u32) & ugeth->ug_regs->tx127,
669                    in_be32(&ugeth->ug_regs->tx127));
670         ugeth_info("tx255      : addr - 0x%08x, val - 0x%08x",
671                    (u32) & ugeth->ug_regs->tx255,
672                    in_be32(&ugeth->ug_regs->tx255));
673         ugeth_info("rx64       : addr - 0x%08x, val - 0x%08x",
674                    (u32) & ugeth->ug_regs->rx64,
675                    in_be32(&ugeth->ug_regs->rx64));
676         ugeth_info("rx127      : addr - 0x%08x, val - 0x%08x",
677                    (u32) & ugeth->ug_regs->rx127,
678                    in_be32(&ugeth->ug_regs->rx127));
679         ugeth_info("rx255      : addr - 0x%08x, val - 0x%08x",
680                    (u32) & ugeth->ug_regs->rx255,
681                    in_be32(&ugeth->ug_regs->rx255));
682         ugeth_info("txok       : addr - 0x%08x, val - 0x%08x",
683                    (u32) & ugeth->ug_regs->txok,
684                    in_be32(&ugeth->ug_regs->txok));
685         ugeth_info("txcf       : addr - 0x%08x, val - 0x%04x",
686                    (u32) & ugeth->ug_regs->txcf,
687                    in_be16(&ugeth->ug_regs->txcf));
688         ugeth_info("tmca       : addr - 0x%08x, val - 0x%08x",
689                    (u32) & ugeth->ug_regs->tmca,
690                    in_be32(&ugeth->ug_regs->tmca));
691         ugeth_info("tbca       : addr - 0x%08x, val - 0x%08x",
692                    (u32) & ugeth->ug_regs->tbca,
693                    in_be32(&ugeth->ug_regs->tbca));
694         ugeth_info("rxfok      : addr - 0x%08x, val - 0x%08x",
695                    (u32) & ugeth->ug_regs->rxfok,
696                    in_be32(&ugeth->ug_regs->rxfok));
697         ugeth_info("rxbok      : addr - 0x%08x, val - 0x%08x",
698                    (u32) & ugeth->ug_regs->rxbok,
699                    in_be32(&ugeth->ug_regs->rxbok));
700         ugeth_info("rbyt       : addr - 0x%08x, val - 0x%08x",
701                    (u32) & ugeth->ug_regs->rbyt,
702                    in_be32(&ugeth->ug_regs->rbyt));
703         ugeth_info("rmca       : addr - 0x%08x, val - 0x%08x",
704                    (u32) & ugeth->ug_regs->rmca,
705                    in_be32(&ugeth->ug_regs->rmca));
706         ugeth_info("rbca       : addr - 0x%08x, val - 0x%08x",
707                    (u32) & ugeth->ug_regs->rbca,
708                    in_be32(&ugeth->ug_regs->rbca));
709         ugeth_info("scar       : addr - 0x%08x, val - 0x%08x",
710                    (u32) & ugeth->ug_regs->scar,
711                    in_be32(&ugeth->ug_regs->scar));
712         ugeth_info("scam       : addr - 0x%08x, val - 0x%08x",
713                    (u32) & ugeth->ug_regs->scam,
714                    in_be32(&ugeth->ug_regs->scam));
715
716         if (ugeth->p_thread_data_tx) {
717                 int numThreadsTxNumerical;
718                 switch (ugeth->ug_info->numThreadsTx) {
719                 case UCC_GETH_NUM_OF_THREADS_1:
720                         numThreadsTxNumerical = 1;
721                         break;
722                 case UCC_GETH_NUM_OF_THREADS_2:
723                         numThreadsTxNumerical = 2;
724                         break;
725                 case UCC_GETH_NUM_OF_THREADS_4:
726                         numThreadsTxNumerical = 4;
727                         break;
728                 case UCC_GETH_NUM_OF_THREADS_6:
729                         numThreadsTxNumerical = 6;
730                         break;
731                 case UCC_GETH_NUM_OF_THREADS_8:
732                         numThreadsTxNumerical = 8;
733                         break;
734                 default:
735                         numThreadsTxNumerical = 0;
736                         break;
737                 }
738
739                 ugeth_info("Thread data TXs:");
740                 ugeth_info("Base address: 0x%08x",
741                            (u32) ugeth->p_thread_data_tx);
742                 for (i = 0; i < numThreadsTxNumerical; i++) {
743                         ugeth_info("Thread data TX[%d]:", i);
744                         ugeth_info("Base address: 0x%08x",
745                                    (u32) & ugeth->p_thread_data_tx[i]);
746                         mem_disp((u8 *) & ugeth->p_thread_data_tx[i],
747                                  sizeof(struct ucc_geth_thread_data_tx));
748                 }
749         }
750         if (ugeth->p_thread_data_rx) {
751                 int numThreadsRxNumerical;
752                 switch (ugeth->ug_info->numThreadsRx) {
753                 case UCC_GETH_NUM_OF_THREADS_1:
754                         numThreadsRxNumerical = 1;
755                         break;
756                 case UCC_GETH_NUM_OF_THREADS_2:
757                         numThreadsRxNumerical = 2;
758                         break;
759                 case UCC_GETH_NUM_OF_THREADS_4:
760                         numThreadsRxNumerical = 4;
761                         break;
762                 case UCC_GETH_NUM_OF_THREADS_6:
763                         numThreadsRxNumerical = 6;
764                         break;
765                 case UCC_GETH_NUM_OF_THREADS_8:
766                         numThreadsRxNumerical = 8;
767                         break;
768                 default:
769                         numThreadsRxNumerical = 0;
770                         break;
771                 }
772
773                 ugeth_info("Thread data RX:");
774                 ugeth_info("Base address: 0x%08x",
775                            (u32) ugeth->p_thread_data_rx);
776                 for (i = 0; i < numThreadsRxNumerical; i++) {
777                         ugeth_info("Thread data RX[%d]:", i);
778                         ugeth_info("Base address: 0x%08x",
779                                    (u32) & ugeth->p_thread_data_rx[i]);
780                         mem_disp((u8 *) & ugeth->p_thread_data_rx[i],
781                                  sizeof(struct ucc_geth_thread_data_rx));
782                 }
783         }
784         if (ugeth->p_exf_glbl_param) {
785                 ugeth_info("EXF global param:");
786                 ugeth_info("Base address: 0x%08x",
787                            (u32) ugeth->p_exf_glbl_param);
788                 mem_disp((u8 *) ugeth->p_exf_glbl_param,
789                          sizeof(*ugeth->p_exf_glbl_param));
790         }
791         if (ugeth->p_tx_glbl_pram) {
792                 ugeth_info("TX global param:");
793                 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_tx_glbl_pram);
794                 ugeth_info("temoder      : addr - 0x%08x, val - 0x%04x",
795                            (u32) & ugeth->p_tx_glbl_pram->temoder,
796                            in_be16(&ugeth->p_tx_glbl_pram->temoder));
797                 ugeth_info("sqptr        : addr - 0x%08x, val - 0x%08x",
798                            (u32) & ugeth->p_tx_glbl_pram->sqptr,
799                            in_be32(&ugeth->p_tx_glbl_pram->sqptr));
800                 ugeth_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x",
801                            (u32) & ugeth->p_tx_glbl_pram->schedulerbasepointer,
802                            in_be32(&ugeth->p_tx_glbl_pram->
803                                    schedulerbasepointer));
804                 ugeth_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x",
805                            (u32) & ugeth->p_tx_glbl_pram->txrmonbaseptr,
806                            in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr));
807                 ugeth_info("tstate       : addr - 0x%08x, val - 0x%08x",
808                            (u32) & ugeth->p_tx_glbl_pram->tstate,
809                            in_be32(&ugeth->p_tx_glbl_pram->tstate));
810                 ugeth_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x",
811                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[0],
812                            ugeth->p_tx_glbl_pram->iphoffset[0]);
813                 ugeth_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x",
814                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[1],
815                            ugeth->p_tx_glbl_pram->iphoffset[1]);
816                 ugeth_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x",
817                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[2],
818                            ugeth->p_tx_glbl_pram->iphoffset[2]);
819                 ugeth_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x",
820                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[3],
821                            ugeth->p_tx_glbl_pram->iphoffset[3]);
822                 ugeth_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x",
823                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[4],
824                            ugeth->p_tx_glbl_pram->iphoffset[4]);
825                 ugeth_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x",
826                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[5],
827                            ugeth->p_tx_glbl_pram->iphoffset[5]);
828                 ugeth_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x",
829                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[6],
830                            ugeth->p_tx_glbl_pram->iphoffset[6]);
831                 ugeth_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x",
832                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[7],
833                            ugeth->p_tx_glbl_pram->iphoffset[7]);
834                 ugeth_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x",
835                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[0],
836                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0]));
837                 ugeth_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x",
838                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[1],
839                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1]));
840                 ugeth_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x",
841                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[2],
842                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2]));
843                 ugeth_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x",
844                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[3],
845                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3]));
846                 ugeth_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x",
847                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[4],
848                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4]));
849                 ugeth_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x",
850                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[5],
851                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5]));
852                 ugeth_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x",
853                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[6],
854                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6]));
855                 ugeth_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x",
856                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[7],
857                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7]));
858                 ugeth_info("tqptr        : addr - 0x%08x, val - 0x%08x",
859                            (u32) & ugeth->p_tx_glbl_pram->tqptr,
860                            in_be32(&ugeth->p_tx_glbl_pram->tqptr));
861         }
862         if (ugeth->p_rx_glbl_pram) {
863                 ugeth_info("RX global param:");
864                 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_glbl_pram);
865                 ugeth_info("remoder         : addr - 0x%08x, val - 0x%08x",
866                            (u32) & ugeth->p_rx_glbl_pram->remoder,
867                            in_be32(&ugeth->p_rx_glbl_pram->remoder));
868                 ugeth_info("rqptr           : addr - 0x%08x, val - 0x%08x",
869                            (u32) & ugeth->p_rx_glbl_pram->rqptr,
870                            in_be32(&ugeth->p_rx_glbl_pram->rqptr));
871                 ugeth_info("typeorlen       : addr - 0x%08x, val - 0x%04x",
872                            (u32) & ugeth->p_rx_glbl_pram->typeorlen,
873                            in_be16(&ugeth->p_rx_glbl_pram->typeorlen));
874                 ugeth_info("rxgstpack       : addr - 0x%08x, val - 0x%02x",
875                            (u32) & ugeth->p_rx_glbl_pram->rxgstpack,
876                            ugeth->p_rx_glbl_pram->rxgstpack);
877                 ugeth_info("rxrmonbaseptr   : addr - 0x%08x, val - 0x%08x",
878                            (u32) & ugeth->p_rx_glbl_pram->rxrmonbaseptr,
879                            in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr));
880                 ugeth_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x",
881                            (u32) & ugeth->p_rx_glbl_pram->intcoalescingptr,
882                            in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr));
883                 ugeth_info("rstate          : addr - 0x%08x, val - 0x%02x",
884                            (u32) & ugeth->p_rx_glbl_pram->rstate,
885                            ugeth->p_rx_glbl_pram->rstate);
886                 ugeth_info("mrblr           : addr - 0x%08x, val - 0x%04x",
887                            (u32) & ugeth->p_rx_glbl_pram->mrblr,
888                            in_be16(&ugeth->p_rx_glbl_pram->mrblr));
889                 ugeth_info("rbdqptr         : addr - 0x%08x, val - 0x%08x",
890                            (u32) & ugeth->p_rx_glbl_pram->rbdqptr,
891                            in_be32(&ugeth->p_rx_glbl_pram->rbdqptr));
892                 ugeth_info("mflr            : addr - 0x%08x, val - 0x%04x",
893                            (u32) & ugeth->p_rx_glbl_pram->mflr,
894                            in_be16(&ugeth->p_rx_glbl_pram->mflr));
895                 ugeth_info("minflr          : addr - 0x%08x, val - 0x%04x",
896                            (u32) & ugeth->p_rx_glbl_pram->minflr,
897                            in_be16(&ugeth->p_rx_glbl_pram->minflr));
898                 ugeth_info("maxd1           : addr - 0x%08x, val - 0x%04x",
899                            (u32) & ugeth->p_rx_glbl_pram->maxd1,
900                            in_be16(&ugeth->p_rx_glbl_pram->maxd1));
901                 ugeth_info("maxd2           : addr - 0x%08x, val - 0x%04x",
902                            (u32) & ugeth->p_rx_glbl_pram->maxd2,
903                            in_be16(&ugeth->p_rx_glbl_pram->maxd2));
904                 ugeth_info("ecamptr         : addr - 0x%08x, val - 0x%08x",
905                            (u32) & ugeth->p_rx_glbl_pram->ecamptr,
906                            in_be32(&ugeth->p_rx_glbl_pram->ecamptr));
907                 ugeth_info("l2qt            : addr - 0x%08x, val - 0x%08x",
908                            (u32) & ugeth->p_rx_glbl_pram->l2qt,
909                            in_be32(&ugeth->p_rx_glbl_pram->l2qt));
910                 ugeth_info("l3qt[0]         : addr - 0x%08x, val - 0x%08x",
911                            (u32) & ugeth->p_rx_glbl_pram->l3qt[0],
912                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[0]));
913                 ugeth_info("l3qt[1]         : addr - 0x%08x, val - 0x%08x",
914                            (u32) & ugeth->p_rx_glbl_pram->l3qt[1],
915                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[1]));
916                 ugeth_info("l3qt[2]         : addr - 0x%08x, val - 0x%08x",
917                            (u32) & ugeth->p_rx_glbl_pram->l3qt[2],
918                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[2]));
919                 ugeth_info("l3qt[3]         : addr - 0x%08x, val - 0x%08x",
920                            (u32) & ugeth->p_rx_glbl_pram->l3qt[3],
921                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[3]));
922                 ugeth_info("l3qt[4]         : addr - 0x%08x, val - 0x%08x",
923                            (u32) & ugeth->p_rx_glbl_pram->l3qt[4],
924                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[4]));
925                 ugeth_info("l3qt[5]         : addr - 0x%08x, val - 0x%08x",
926                            (u32) & ugeth->p_rx_glbl_pram->l3qt[5],
927                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[5]));
928                 ugeth_info("l3qt[6]         : addr - 0x%08x, val - 0x%08x",
929                            (u32) & ugeth->p_rx_glbl_pram->l3qt[6],
930                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[6]));
931                 ugeth_info("l3qt[7]         : addr - 0x%08x, val - 0x%08x",
932                            (u32) & ugeth->p_rx_glbl_pram->l3qt[7],
933                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[7]));
934                 ugeth_info("vlantype        : addr - 0x%08x, val - 0x%04x",
935                            (u32) & ugeth->p_rx_glbl_pram->vlantype,
936                            in_be16(&ugeth->p_rx_glbl_pram->vlantype));
937                 ugeth_info("vlantci         : addr - 0x%08x, val - 0x%04x",
938                            (u32) & ugeth->p_rx_glbl_pram->vlantci,
939                            in_be16(&ugeth->p_rx_glbl_pram->vlantci));
940                 for (i = 0; i < 64; i++)
941                         ugeth_info
942                     ("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x",
943                              i,
944                              (u32) & ugeth->p_rx_glbl_pram->addressfiltering[i],
945                              ugeth->p_rx_glbl_pram->addressfiltering[i]);
946                 ugeth_info("exfGlobalParam  : addr - 0x%08x, val - 0x%08x",
947                            (u32) & ugeth->p_rx_glbl_pram->exfGlobalParam,
948                            in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam));
949         }
950         if (ugeth->p_send_q_mem_reg) {
951                 ugeth_info("Send Q memory registers:");
952                 ugeth_info("Base address: 0x%08x",
953                            (u32) ugeth->p_send_q_mem_reg);
954                 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
955                         ugeth_info("SQQD[%d]:", i);
956                         ugeth_info("Base address: 0x%08x",
957                                    (u32) & ugeth->p_send_q_mem_reg->sqqd[i]);
958                         mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i],
959                                  sizeof(struct ucc_geth_send_queue_qd));
960                 }
961         }
962         if (ugeth->p_scheduler) {
963                 ugeth_info("Scheduler:");
964                 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_scheduler);
965                 mem_disp((u8 *) ugeth->p_scheduler,
966                          sizeof(*ugeth->p_scheduler));
967         }
968         if (ugeth->p_tx_fw_statistics_pram) {
969                 ugeth_info("TX FW statistics pram:");
970                 ugeth_info("Base address: 0x%08x",
971                            (u32) ugeth->p_tx_fw_statistics_pram);
972                 mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram,
973                          sizeof(*ugeth->p_tx_fw_statistics_pram));
974         }
975         if (ugeth->p_rx_fw_statistics_pram) {
976                 ugeth_info("RX FW statistics pram:");
977                 ugeth_info("Base address: 0x%08x",
978                            (u32) ugeth->p_rx_fw_statistics_pram);
979                 mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram,
980                          sizeof(*ugeth->p_rx_fw_statistics_pram));
981         }
982         if (ugeth->p_rx_irq_coalescing_tbl) {
983                 ugeth_info("RX IRQ coalescing tables:");
984                 ugeth_info("Base address: 0x%08x",
985                            (u32) ugeth->p_rx_irq_coalescing_tbl);
986                 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
987                         ugeth_info("RX IRQ coalescing table entry[%d]:", i);
988                         ugeth_info("Base address: 0x%08x",
989                                    (u32) & ugeth->p_rx_irq_coalescing_tbl->
990                                    coalescingentry[i]);
991                         ugeth_info
992                 ("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x",
993                              (u32) & ugeth->p_rx_irq_coalescing_tbl->
994                              coalescingentry[i].interruptcoalescingmaxvalue,
995                              in_be32(&ugeth->p_rx_irq_coalescing_tbl->
996                                      coalescingentry[i].
997                                      interruptcoalescingmaxvalue));
998                         ugeth_info
999                 ("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x",
1000                              (u32) & ugeth->p_rx_irq_coalescing_tbl->
1001                              coalescingentry[i].interruptcoalescingcounter,
1002                              in_be32(&ugeth->p_rx_irq_coalescing_tbl->
1003                                      coalescingentry[i].
1004                                      interruptcoalescingcounter));
1005                 }
1006         }
1007         if (ugeth->p_rx_bd_qs_tbl) {
1008                 ugeth_info("RX BD QS tables:");
1009                 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_bd_qs_tbl);
1010                 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1011                         ugeth_info("RX BD QS table[%d]:", i);
1012                         ugeth_info("Base address: 0x%08x",
1013                                    (u32) & ugeth->p_rx_bd_qs_tbl[i]);
1014                         ugeth_info
1015                             ("bdbaseptr        : addr - 0x%08x, val - 0x%08x",
1016                              (u32) & ugeth->p_rx_bd_qs_tbl[i].bdbaseptr,
1017                              in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr));
1018                         ugeth_info
1019                             ("bdptr            : addr - 0x%08x, val - 0x%08x",
1020                              (u32) & ugeth->p_rx_bd_qs_tbl[i].bdptr,
1021                              in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr));
1022                         ugeth_info
1023                             ("externalbdbaseptr: addr - 0x%08x, val - 0x%08x",
1024                              (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
1025                              in_be32(&ugeth->p_rx_bd_qs_tbl[i].
1026                                      externalbdbaseptr));
1027                         ugeth_info
1028                             ("externalbdptr    : addr - 0x%08x, val - 0x%08x",
1029                              (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdptr,
1030                              in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr));
1031                         ugeth_info("ucode RX Prefetched BDs:");
1032                         ugeth_info("Base address: 0x%08x",
1033                                    (u32)
1034                                    qe_muram_addr(in_be32
1035                                                  (&ugeth->p_rx_bd_qs_tbl[i].
1036                                                   bdbaseptr)));
1037                         mem_disp((u8 *)
1038                                  qe_muram_addr(in_be32
1039                                                (&ugeth->p_rx_bd_qs_tbl[i].
1040                                                 bdbaseptr)),
1041                                  sizeof(struct ucc_geth_rx_prefetched_bds));
1042                 }
1043         }
1044         if (ugeth->p_init_enet_param_shadow) {
1045                 int size;
1046                 ugeth_info("Init enet param shadow:");
1047                 ugeth_info("Base address: 0x%08x",
1048                            (u32) ugeth->p_init_enet_param_shadow);
1049                 mem_disp((u8 *) ugeth->p_init_enet_param_shadow,
1050                          sizeof(*ugeth->p_init_enet_param_shadow));
1051
1052                 size = sizeof(struct ucc_geth_thread_rx_pram);
1053                 if (ugeth->ug_info->rxExtendedFiltering) {
1054                         size +=
1055                             THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
1056                         if (ugeth->ug_info->largestexternallookupkeysize ==
1057                             QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
1058                                 size +=
1059                         THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
1060                         if (ugeth->ug_info->largestexternallookupkeysize ==
1061                             QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
1062                                 size +=
1063                         THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
1064                 }
1065
1066                 dump_init_enet_entries(ugeth,
1067                                        &(ugeth->p_init_enet_param_shadow->
1068                                          txthread[0]),
1069                                        ENET_INIT_PARAM_MAX_ENTRIES_TX,
1070                                        sizeof(struct ucc_geth_thread_tx_pram),
1071                                        ugeth->ug_info->riscTx, 0);
1072                 dump_init_enet_entries(ugeth,
1073                                        &(ugeth->p_init_enet_param_shadow->
1074                                          rxthread[0]),
1075                                        ENET_INIT_PARAM_MAX_ENTRIES_RX, size,
1076                                        ugeth->ug_info->riscRx, 1);
1077         }
1078 }
1079 #endif /* DEBUG */
1080
1081 static void init_default_reg_vals(u32 __iomem *upsmr_register,
1082                                   u32 __iomem *maccfg1_register,
1083                                   u32 __iomem *maccfg2_register)
1084 {
1085         out_be32(upsmr_register, UCC_GETH_UPSMR_INIT);
1086         out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT);
1087         out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT);
1088 }
1089
1090 static int init_half_duplex_params(int alt_beb,
1091                                    int back_pressure_no_backoff,
1092                                    int no_backoff,
1093                                    int excess_defer,
1094                                    u8 alt_beb_truncation,
1095                                    u8 max_retransmissions,
1096                                    u8 collision_window,
1097                                    u32 __iomem *hafdup_register)
1098 {
1099         u32 value = 0;
1100
1101         if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) ||
1102             (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) ||
1103             (collision_window > HALFDUP_COLLISION_WINDOW_MAX))
1104                 return -EINVAL;
1105
1106         value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT);
1107
1108         if (alt_beb)
1109                 value |= HALFDUP_ALT_BEB;
1110         if (back_pressure_no_backoff)
1111                 value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF;
1112         if (no_backoff)
1113                 value |= HALFDUP_NO_BACKOFF;
1114         if (excess_defer)
1115                 value |= HALFDUP_EXCESSIVE_DEFER;
1116
1117         value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT);
1118
1119         value |= collision_window;
1120
1121         out_be32(hafdup_register, value);
1122         return 0;
1123 }
1124
1125 static int init_inter_frame_gap_params(u8 non_btb_cs_ipg,
1126                                        u8 non_btb_ipg,
1127                                        u8 min_ifg,
1128                                        u8 btb_ipg,
1129                                        u32 __iomem *ipgifg_register)
1130 {
1131         u32 value = 0;
1132
1133         /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back
1134         IPG part 2 */
1135         if (non_btb_cs_ipg > non_btb_ipg)
1136                 return -EINVAL;
1137
1138         if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) ||
1139             (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) ||
1140             /*(min_ifg        > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */
1141             (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX))
1142                 return -EINVAL;
1143
1144         value |=
1145             ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) &
1146              IPGIFG_NBTB_CS_IPG_MASK);
1147         value |=
1148             ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) &
1149              IPGIFG_NBTB_IPG_MASK);
1150         value |=
1151             ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) &
1152              IPGIFG_MIN_IFG_MASK);
1153         value |= (btb_ipg & IPGIFG_BTB_IPG_MASK);
1154
1155         out_be32(ipgifg_register, value);
1156         return 0;
1157 }
1158
1159 int init_flow_control_params(u32 automatic_flow_control_mode,
1160                                     int rx_flow_control_enable,
1161                                     int tx_flow_control_enable,
1162                                     u16 pause_period,
1163                                     u16 extension_field,
1164                                     u32 __iomem *upsmr_register,
1165                                     u32 __iomem *uempr_register,
1166                                     u32 __iomem *maccfg1_register)
1167 {
1168         u32 value = 0;
1169
1170         /* Set UEMPR register */
1171         value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT;
1172         value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT;
1173         out_be32(uempr_register, value);
1174
1175         /* Set UPSMR register */
1176         setbits32(upsmr_register, automatic_flow_control_mode);
1177
1178         value = in_be32(maccfg1_register);
1179         if (rx_flow_control_enable)
1180                 value |= MACCFG1_FLOW_RX;
1181         if (tx_flow_control_enable)
1182                 value |= MACCFG1_FLOW_TX;
1183         out_be32(maccfg1_register, value);
1184
1185         return 0;
1186 }
1187
1188 static int init_hw_statistics_gathering_mode(int enable_hardware_statistics,
1189                                              int auto_zero_hardware_statistics,
1190                                              u32 __iomem *upsmr_register,
1191                                              u16 __iomem *uescr_register)
1192 {
1193         u16 uescr_value = 0;
1194
1195         /* Enable hardware statistics gathering if requested */
1196         if (enable_hardware_statistics)
1197                 setbits32(upsmr_register, UCC_GETH_UPSMR_HSE);
1198
1199         /* Clear hardware statistics counters */
1200         uescr_value = in_be16(uescr_register);
1201         uescr_value |= UESCR_CLRCNT;
1202         /* Automatically zero hardware statistics counters on read,
1203         if requested */
1204         if (auto_zero_hardware_statistics)
1205                 uescr_value |= UESCR_AUTOZ;
1206         out_be16(uescr_register, uescr_value);
1207
1208         return 0;
1209 }
1210
1211 static int init_firmware_statistics_gathering_mode(int
1212                 enable_tx_firmware_statistics,
1213                 int enable_rx_firmware_statistics,
1214                 u32 __iomem *tx_rmon_base_ptr,
1215                 u32 tx_firmware_statistics_structure_address,
1216                 u32 __iomem *rx_rmon_base_ptr,
1217                 u32 rx_firmware_statistics_structure_address,
1218                 u16 __iomem *temoder_register,
1219                 u32 __iomem *remoder_register)
1220 {
1221         /* Note: this function does not check if */
1222         /* the parameters it receives are NULL   */
1223
1224         if (enable_tx_firmware_statistics) {
1225                 out_be32(tx_rmon_base_ptr,
1226                          tx_firmware_statistics_structure_address);
1227                 setbits16(temoder_register, TEMODER_TX_RMON_STATISTICS_ENABLE);
1228         }
1229
1230         if (enable_rx_firmware_statistics) {
1231                 out_be32(rx_rmon_base_ptr,
1232                          rx_firmware_statistics_structure_address);
1233                 setbits32(remoder_register, REMODER_RX_RMON_STATISTICS_ENABLE);
1234         }
1235
1236         return 0;
1237 }
1238
1239 static int init_mac_station_addr_regs(u8 address_byte_0,
1240                                       u8 address_byte_1,
1241                                       u8 address_byte_2,
1242                                       u8 address_byte_3,
1243                                       u8 address_byte_4,
1244                                       u8 address_byte_5,
1245                                       u32 __iomem *macstnaddr1_register,
1246                                       u32 __iomem *macstnaddr2_register)
1247 {
1248         u32 value = 0;
1249
1250         /* Example: for a station address of 0x12345678ABCD, */
1251         /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */
1252
1253         /* MACSTNADDR1 Register: */
1254
1255         /* 0                      7   8                      15  */
1256         /* station address byte 5     station address byte 4     */
1257         /* 16                     23  24                     31  */
1258         /* station address byte 3     station address byte 2     */
1259         value |= (u32) ((address_byte_2 << 0) & 0x000000FF);
1260         value |= (u32) ((address_byte_3 << 8) & 0x0000FF00);
1261         value |= (u32) ((address_byte_4 << 16) & 0x00FF0000);
1262         value |= (u32) ((address_byte_5 << 24) & 0xFF000000);
1263
1264         out_be32(macstnaddr1_register, value);
1265
1266         /* MACSTNADDR2 Register: */
1267
1268         /* 0                      7   8                      15  */
1269         /* station address byte 1     station address byte 0     */
1270         /* 16                     23  24                     31  */
1271         /*         reserved                   reserved           */
1272         value = 0;
1273         value |= (u32) ((address_byte_0 << 16) & 0x00FF0000);
1274         value |= (u32) ((address_byte_1 << 24) & 0xFF000000);
1275
1276         out_be32(macstnaddr2_register, value);
1277
1278         return 0;
1279 }
1280
1281 static int init_check_frame_length_mode(int length_check,
1282                                         u32 __iomem *maccfg2_register)
1283 {
1284         u32 value = 0;
1285
1286         value = in_be32(maccfg2_register);
1287
1288         if (length_check)
1289                 value |= MACCFG2_LC;
1290         else
1291                 value &= ~MACCFG2_LC;
1292
1293         out_be32(maccfg2_register, value);
1294         return 0;
1295 }
1296
1297 static int init_preamble_length(u8 preamble_length,
1298                                 u32 __iomem *maccfg2_register)
1299 {
1300         if ((preamble_length < 3) || (preamble_length > 7))
1301                 return -EINVAL;
1302
1303         clrsetbits_be32(maccfg2_register, MACCFG2_PREL_MASK,
1304                         preamble_length << MACCFG2_PREL_SHIFT);
1305
1306         return 0;
1307 }
1308
1309 static int init_rx_parameters(int reject_broadcast,
1310                               int receive_short_frames,
1311                               int promiscuous, u32 __iomem *upsmr_register)
1312 {
1313         u32 value = 0;
1314
1315         value = in_be32(upsmr_register);
1316
1317         if (reject_broadcast)
1318                 value |= UCC_GETH_UPSMR_BRO;
1319         else
1320                 value &= ~UCC_GETH_UPSMR_BRO;
1321
1322         if (receive_short_frames)
1323                 value |= UCC_GETH_UPSMR_RSH;
1324         else
1325                 value &= ~UCC_GETH_UPSMR_RSH;
1326
1327         if (promiscuous)
1328                 value |= UCC_GETH_UPSMR_PRO;
1329         else
1330                 value &= ~UCC_GETH_UPSMR_PRO;
1331
1332         out_be32(upsmr_register, value);
1333
1334         return 0;
1335 }
1336
1337 static int init_max_rx_buff_len(u16 max_rx_buf_len,
1338                                 u16 __iomem *mrblr_register)
1339 {
1340         /* max_rx_buf_len value must be a multiple of 128 */
1341         if ((max_rx_buf_len == 0)
1342             || (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT))
1343                 return -EINVAL;
1344
1345         out_be16(mrblr_register, max_rx_buf_len);
1346         return 0;
1347 }
1348
1349 static int init_min_frame_len(u16 min_frame_length,
1350                               u16 __iomem *minflr_register,
1351                               u16 __iomem *mrblr_register)
1352 {
1353         u16 mrblr_value = 0;
1354
1355         mrblr_value = in_be16(mrblr_register);
1356         if (min_frame_length >= (mrblr_value - 4))
1357                 return -EINVAL;
1358
1359         out_be16(minflr_register, min_frame_length);
1360         return 0;
1361 }
1362
1363 static int adjust_enet_interface(struct ucc_geth_private *ugeth)
1364 {
1365         struct ucc_geth_info *ug_info;
1366         struct ucc_geth __iomem *ug_regs;
1367         struct ucc_fast __iomem *uf_regs;
1368         int ret_val;
1369         u32 upsmr, maccfg2, tbiBaseAddress;
1370         u16 value;
1371
1372         ugeth_vdbg("%s: IN", __func__);
1373
1374         ug_info = ugeth->ug_info;
1375         ug_regs = ugeth->ug_regs;
1376         uf_regs = ugeth->uccf->uf_regs;
1377
1378         /*                    Set MACCFG2                    */
1379         maccfg2 = in_be32(&ug_regs->maccfg2);
1380         maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
1381         if ((ugeth->max_speed == SPEED_10) ||
1382             (ugeth->max_speed == SPEED_100))
1383                 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
1384         else if (ugeth->max_speed == SPEED_1000)
1385                 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
1386         maccfg2 |= ug_info->padAndCrc;
1387         out_be32(&ug_regs->maccfg2, maccfg2);
1388
1389         /*                    Set UPSMR                      */
1390         upsmr = in_be32(&uf_regs->upsmr);
1391         upsmr &= ~(UCC_GETH_UPSMR_RPM | UCC_GETH_UPSMR_R10M |
1392                    UCC_GETH_UPSMR_TBIM | UCC_GETH_UPSMR_RMM);
1393         if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1394             (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1395             (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1396             (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1397             (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
1398             (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1399                 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RMII)
1400                         upsmr |= UCC_GETH_UPSMR_RPM;
1401                 switch (ugeth->max_speed) {
1402                 case SPEED_10:
1403                         upsmr |= UCC_GETH_UPSMR_R10M;
1404                         /* FALLTHROUGH */
1405                 case SPEED_100:
1406                         if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI)
1407                                 upsmr |= UCC_GETH_UPSMR_RMM;
1408                 }
1409         }
1410         if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1411             (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1412                 upsmr |= UCC_GETH_UPSMR_TBIM;
1413         }
1414         if ((ugeth->phy_interface == PHY_INTERFACE_MODE_SGMII))
1415                 upsmr |= UCC_GETH_UPSMR_SGMM;
1416
1417         out_be32(&uf_regs->upsmr, upsmr);
1418
1419         /* Disable autonegotiation in tbi mode, because by default it
1420         comes up in autonegotiation mode. */
1421         /* Note that this depends on proper setting in utbipar register. */
1422         if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1423             (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1424                 tbiBaseAddress = in_be32(&ug_regs->utbipar);
1425                 tbiBaseAddress &= UTBIPAR_PHY_ADDRESS_MASK;
1426                 tbiBaseAddress >>= UTBIPAR_PHY_ADDRESS_SHIFT;
1427                 value = ugeth->phydev->bus->read(ugeth->phydev->bus,
1428                                 (u8) tbiBaseAddress, ENET_TBI_MII_CR);
1429                 value &= ~0x1000;       /* Turn off autonegotiation */
1430                 ugeth->phydev->bus->write(ugeth->phydev->bus,
1431                                 (u8) tbiBaseAddress, ENET_TBI_MII_CR, value);
1432         }
1433
1434         init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2);
1435
1436         ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2);
1437         if (ret_val != 0) {
1438                 if (netif_msg_probe(ugeth))
1439                         ugeth_err("%s: Preamble length must be between 3 and 7 inclusive.",
1440                              __func__);
1441                 return ret_val;
1442         }
1443
1444         return 0;
1445 }
1446
1447 /* Called every time the controller might need to be made
1448  * aware of new link state.  The PHY code conveys this
1449  * information through variables in the ugeth structure, and this
1450  * function converts those variables into the appropriate
1451  * register values, and can bring down the device if needed.
1452  */
1453
1454 static void adjust_link(struct net_device *dev)
1455 {
1456         struct ucc_geth_private *ugeth = netdev_priv(dev);
1457         struct ucc_geth __iomem *ug_regs;
1458         struct ucc_fast __iomem *uf_regs;
1459         struct phy_device *phydev = ugeth->phydev;
1460         unsigned long flags;
1461         int new_state = 0;
1462
1463         ug_regs = ugeth->ug_regs;
1464         uf_regs = ugeth->uccf->uf_regs;
1465
1466         spin_lock_irqsave(&ugeth->lock, flags);
1467
1468         if (phydev->link) {
1469                 u32 tempval = in_be32(&ug_regs->maccfg2);
1470                 u32 upsmr = in_be32(&uf_regs->upsmr);
1471                 /* Now we make sure that we can be in full duplex mode.
1472                  * If not, we operate in half-duplex mode. */
1473                 if (phydev->duplex != ugeth->oldduplex) {
1474                         new_state = 1;
1475                         if (!(phydev->duplex))
1476                                 tempval &= ~(MACCFG2_FDX);
1477                         else
1478                                 tempval |= MACCFG2_FDX;
1479                         ugeth->oldduplex = phydev->duplex;
1480                 }
1481
1482                 if (phydev->speed != ugeth->oldspeed) {
1483                         new_state = 1;
1484                         switch (phydev->speed) {
1485                         case SPEED_1000:
1486                                 tempval = ((tempval &
1487                                             ~(MACCFG2_INTERFACE_MODE_MASK)) |
1488                                             MACCFG2_INTERFACE_MODE_BYTE);
1489                                 break;
1490                         case SPEED_100:
1491                         case SPEED_10:
1492                                 tempval = ((tempval &
1493                                             ~(MACCFG2_INTERFACE_MODE_MASK)) |
1494                                             MACCFG2_INTERFACE_MODE_NIBBLE);
1495                                 /* if reduced mode, re-set UPSMR.R10M */
1496                                 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1497                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1498                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1499                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1500                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
1501                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1502                                         if (phydev->speed == SPEED_10)
1503                                                 upsmr |= UCC_GETH_UPSMR_R10M;
1504                                         else
1505                                                 upsmr &= ~UCC_GETH_UPSMR_R10M;
1506                                 }
1507                                 break;
1508                         default:
1509                                 if (netif_msg_link(ugeth))
1510                                         ugeth_warn(
1511                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!",
1512                                                 dev->name, phydev->speed);
1513                                 break;
1514                         }
1515                         ugeth->oldspeed = phydev->speed;
1516                 }
1517
1518                 out_be32(&ug_regs->maccfg2, tempval);
1519                 out_be32(&uf_regs->upsmr, upsmr);
1520
1521                 if (!ugeth->oldlink) {
1522                         new_state = 1;
1523                         ugeth->oldlink = 1;
1524                 }
1525         } else if (ugeth->oldlink) {
1526                         new_state = 1;
1527                         ugeth->oldlink = 0;
1528                         ugeth->oldspeed = 0;
1529                         ugeth->oldduplex = -1;
1530         }
1531
1532         if (new_state && netif_msg_link(ugeth))
1533                 phy_print_status(phydev);
1534
1535         spin_unlock_irqrestore(&ugeth->lock, flags);
1536 }
1537
1538 /* Initialize TBI PHY interface for communicating with the
1539  * SERDES lynx PHY on the chip.  We communicate with this PHY
1540  * through the MDIO bus on each controller, treating it as a
1541  * "normal" PHY at the address found in the UTBIPA register.  We assume
1542  * that the UTBIPA register is valid.  Either the MDIO bus code will set
1543  * it to a value that doesn't conflict with other PHYs on the bus, or the
1544  * value doesn't matter, as there are no other PHYs on the bus.
1545  */
1546 static void uec_configure_serdes(struct net_device *dev)
1547 {
1548         struct ucc_geth_private *ugeth = netdev_priv(dev);
1549         struct ucc_geth_info *ug_info = ugeth->ug_info;
1550         struct phy_device *tbiphy;
1551
1552         if (!ug_info->tbi_node) {
1553                 dev_warn(&dev->dev, "SGMII mode requires that the device "
1554                         "tree specify a tbi-handle\n");
1555                 return;
1556         }
1557
1558         tbiphy = of_phy_find_device(ug_info->tbi_node);
1559         if (!tbiphy) {
1560                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1561                 return;
1562         }
1563
1564         /*
1565          * If the link is already up, we must already be ok, and don't need to
1566          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1567          * everything for us?  Resetting it takes the link down and requires
1568          * several seconds for it to come back.
1569          */
1570         if (phy_read(tbiphy, ENET_TBI_MII_SR) & TBISR_LSTATUS)
1571                 return;
1572
1573         /* Single clk mode, mii mode off(for serdes communication) */
1574         phy_write(tbiphy, ENET_TBI_MII_ANA, TBIANA_SETTINGS);
1575
1576         phy_write(tbiphy, ENET_TBI_MII_TBICON, TBICON_CLK_SELECT);
1577
1578         phy_write(tbiphy, ENET_TBI_MII_CR, TBICR_SETTINGS);
1579 }
1580
1581 /* Configure the PHY for dev.
1582  * returns 0 if success.  -1 if failure
1583  */
1584 static int init_phy(struct net_device *dev)
1585 {
1586         struct ucc_geth_private *priv = netdev_priv(dev);
1587         struct ucc_geth_info *ug_info = priv->ug_info;
1588         struct phy_device *phydev;
1589
1590         priv->oldlink = 0;
1591         priv->oldspeed = 0;
1592         priv->oldduplex = -1;
1593
1594         phydev = of_phy_connect(dev, ug_info->phy_node, &adjust_link, 0,
1595                                 priv->phy_interface);
1596         if (!phydev)
1597                 phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1598                                                    priv->phy_interface);
1599         if (!phydev) {
1600                 dev_err(&dev->dev, "Could not attach to PHY\n");
1601                 return -ENODEV;
1602         }
1603
1604         if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII)
1605                 uec_configure_serdes(dev);
1606
1607         phydev->supported &= (ADVERTISED_10baseT_Half |
1608                                  ADVERTISED_10baseT_Full |
1609                                  ADVERTISED_100baseT_Half |
1610                                  ADVERTISED_100baseT_Full);
1611
1612         if (priv->max_speed == SPEED_1000)
1613                 phydev->supported |= ADVERTISED_1000baseT_Full;
1614
1615         phydev->advertising = phydev->supported;
1616
1617         priv->phydev = phydev;
1618
1619         return 0;
1620 }
1621
1622
1623
1624 static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth)
1625 {
1626         struct ucc_fast_private *uccf;
1627         u32 cecr_subblock;
1628         u32 temp;
1629         int i = 10;
1630
1631         uccf = ugeth->uccf;
1632
1633         /* Mask GRACEFUL STOP TX interrupt bit and clear it */
1634         clrbits32(uccf->p_uccm, UCC_GETH_UCCE_GRA);
1635         out_be32(uccf->p_ucce, UCC_GETH_UCCE_GRA);  /* clear by writing 1 */
1636
1637         /* Issue host command */
1638         cecr_subblock =
1639             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1640         qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
1641                      QE_CR_PROTOCOL_ETHERNET, 0);
1642
1643         /* Wait for command to complete */
1644         do {
1645                 msleep(10);
1646                 temp = in_be32(uccf->p_ucce);
1647         } while (!(temp & UCC_GETH_UCCE_GRA) && --i);
1648
1649         uccf->stopped_tx = 1;
1650
1651         return 0;
1652 }
1653
1654 static int ugeth_graceful_stop_rx(struct ucc_geth_private * ugeth)
1655 {
1656         struct ucc_fast_private *uccf;
1657         u32 cecr_subblock;
1658         u8 temp;
1659         int i = 10;
1660
1661         uccf = ugeth->uccf;
1662
1663         /* Clear acknowledge bit */
1664         temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1665         temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
1666         out_8(&ugeth->p_rx_glbl_pram->rxgstpack, temp);
1667
1668         /* Keep issuing command and checking acknowledge bit until
1669         it is asserted, according to spec */
1670         do {
1671                 /* Issue host command */
1672                 cecr_subblock =
1673                     ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.
1674                                                 ucc_num);
1675                 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
1676                              QE_CR_PROTOCOL_ETHERNET, 0);
1677                 msleep(10);
1678                 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1679         } while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX) && --i);
1680
1681         uccf->stopped_rx = 1;
1682
1683         return 0;
1684 }
1685
1686 static int ugeth_restart_tx(struct ucc_geth_private *ugeth)
1687 {
1688         struct ucc_fast_private *uccf;
1689         u32 cecr_subblock;
1690
1691         uccf = ugeth->uccf;
1692
1693         cecr_subblock =
1694             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1695         qe_issue_cmd(QE_RESTART_TX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 0);
1696         uccf->stopped_tx = 0;
1697
1698         return 0;
1699 }
1700
1701 static int ugeth_restart_rx(struct ucc_geth_private *ugeth)
1702 {
1703         struct ucc_fast_private *uccf;
1704         u32 cecr_subblock;
1705
1706         uccf = ugeth->uccf;
1707
1708         cecr_subblock =
1709             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1710         qe_issue_cmd(QE_RESTART_RX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
1711                      0);
1712         uccf->stopped_rx = 0;
1713
1714         return 0;
1715 }
1716
1717 static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1718 {
1719         struct ucc_fast_private *uccf;
1720         int enabled_tx, enabled_rx;
1721
1722         uccf = ugeth->uccf;
1723
1724         /* check if the UCC number is in range. */
1725         if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1726                 if (netif_msg_probe(ugeth))
1727                         ugeth_err("%s: ucc_num out of range.", __func__);
1728                 return -EINVAL;
1729         }
1730
1731         enabled_tx = uccf->enabled_tx;
1732         enabled_rx = uccf->enabled_rx;
1733
1734         /* Get Tx and Rx going again, in case this channel was actively
1735         disabled. */
1736         if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx)
1737                 ugeth_restart_tx(ugeth);
1738         if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx)
1739                 ugeth_restart_rx(ugeth);
1740
1741         ucc_fast_enable(uccf, mode);    /* OK to do even if not disabled */
1742
1743         return 0;
1744
1745 }
1746
1747 static int ugeth_disable(struct ucc_geth_private * ugeth, enum comm_dir mode)
1748 {
1749         struct ucc_fast_private *uccf;
1750
1751         uccf = ugeth->uccf;
1752
1753         /* check if the UCC number is in range. */
1754         if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1755                 if (netif_msg_probe(ugeth))
1756                         ugeth_err("%s: ucc_num out of range.", __func__);
1757                 return -EINVAL;
1758         }
1759
1760         /* Stop any transmissions */
1761         if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx)
1762                 ugeth_graceful_stop_tx(ugeth);
1763
1764         /* Stop any receptions */
1765         if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx)
1766                 ugeth_graceful_stop_rx(ugeth);
1767
1768         ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */
1769
1770         return 0;
1771 }
1772
1773 static void ugeth_dump_regs(struct ucc_geth_private *ugeth)
1774 {
1775 #ifdef DEBUG
1776         ucc_fast_dump_regs(ugeth->uccf);
1777         dump_regs(ugeth);
1778         dump_bds(ugeth);
1779 #endif
1780 }
1781
1782 static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private *
1783                                                        ugeth,
1784                                                        enum enet_addr_type
1785                                                        enet_addr_type)
1786 {
1787         struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
1788         struct ucc_fast_private *uccf;
1789         enum comm_dir comm_dir;
1790         struct list_head *p_lh;
1791         u16 i, num;
1792         u32 __iomem *addr_h;
1793         u32 __iomem *addr_l;
1794         u8 *p_counter;
1795
1796         uccf = ugeth->uccf;
1797
1798         p_82xx_addr_filt =
1799             (struct ucc_geth_82xx_address_filtering_pram __iomem *)
1800             ugeth->p_rx_glbl_pram->addressfiltering;
1801
1802         if (enet_addr_type == ENET_ADDR_TYPE_GROUP) {
1803                 addr_h = &(p_82xx_addr_filt->gaddr_h);
1804                 addr_l = &(p_82xx_addr_filt->gaddr_l);
1805                 p_lh = &ugeth->group_hash_q;
1806                 p_counter = &(ugeth->numGroupAddrInHash);
1807         } else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) {
1808                 addr_h = &(p_82xx_addr_filt->iaddr_h);
1809                 addr_l = &(p_82xx_addr_filt->iaddr_l);
1810                 p_lh = &ugeth->ind_hash_q;
1811                 p_counter = &(ugeth->numIndAddrInHash);
1812         } else
1813                 return -EINVAL;
1814
1815         comm_dir = 0;
1816         if (uccf->enabled_tx)
1817                 comm_dir |= COMM_DIR_TX;
1818         if (uccf->enabled_rx)
1819                 comm_dir |= COMM_DIR_RX;
1820         if (comm_dir)
1821                 ugeth_disable(ugeth, comm_dir);
1822
1823         /* Clear the hash table. */
1824         out_be32(addr_h, 0x00000000);
1825         out_be32(addr_l, 0x00000000);
1826
1827         if (!p_lh)
1828                 return 0;
1829
1830         num = *p_counter;
1831
1832         /* Delete all remaining CQ elements */
1833         for (i = 0; i < num; i++)
1834                 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh)));
1835
1836         *p_counter = 0;
1837
1838         if (comm_dir)
1839                 ugeth_enable(ugeth, comm_dir);
1840
1841         return 0;
1842 }
1843
1844 static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth,
1845                                                     u8 paddr_num)
1846 {
1847         ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */
1848         return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */
1849 }
1850
1851 static void ucc_geth_memclean(struct ucc_geth_private *ugeth)
1852 {
1853         u16 i, j;
1854         u8 __iomem *bd;
1855
1856         if (!ugeth)
1857                 return;
1858
1859         if (ugeth->uccf) {
1860                 ucc_fast_free(ugeth->uccf);
1861                 ugeth->uccf = NULL;
1862         }
1863
1864         if (ugeth->p_thread_data_tx) {
1865                 qe_muram_free(ugeth->thread_dat_tx_offset);
1866                 ugeth->p_thread_data_tx = NULL;
1867         }
1868         if (ugeth->p_thread_data_rx) {
1869                 qe_muram_free(ugeth->thread_dat_rx_offset);
1870                 ugeth->p_thread_data_rx = NULL;
1871         }
1872         if (ugeth->p_exf_glbl_param) {
1873                 qe_muram_free(ugeth->exf_glbl_param_offset);
1874                 ugeth->p_exf_glbl_param = NULL;
1875         }
1876         if (ugeth->p_rx_glbl_pram) {
1877                 qe_muram_free(ugeth->rx_glbl_pram_offset);
1878                 ugeth->p_rx_glbl_pram = NULL;
1879         }
1880         if (ugeth->p_tx_glbl_pram) {
1881                 qe_muram_free(ugeth->tx_glbl_pram_offset);
1882                 ugeth->p_tx_glbl_pram = NULL;
1883         }
1884         if (ugeth->p_send_q_mem_reg) {
1885                 qe_muram_free(ugeth->send_q_mem_reg_offset);
1886                 ugeth->p_send_q_mem_reg = NULL;
1887         }
1888         if (ugeth->p_scheduler) {
1889                 qe_muram_free(ugeth->scheduler_offset);
1890                 ugeth->p_scheduler = NULL;
1891         }
1892         if (ugeth->p_tx_fw_statistics_pram) {
1893                 qe_muram_free(ugeth->tx_fw_statistics_pram_offset);
1894                 ugeth->p_tx_fw_statistics_pram = NULL;
1895         }
1896         if (ugeth->p_rx_fw_statistics_pram) {
1897                 qe_muram_free(ugeth->rx_fw_statistics_pram_offset);
1898                 ugeth->p_rx_fw_statistics_pram = NULL;
1899         }
1900         if (ugeth->p_rx_irq_coalescing_tbl) {
1901                 qe_muram_free(ugeth->rx_irq_coalescing_tbl_offset);
1902                 ugeth->p_rx_irq_coalescing_tbl = NULL;
1903         }
1904         if (ugeth->p_rx_bd_qs_tbl) {
1905                 qe_muram_free(ugeth->rx_bd_qs_tbl_offset);
1906                 ugeth->p_rx_bd_qs_tbl = NULL;
1907         }
1908         if (ugeth->p_init_enet_param_shadow) {
1909                 return_init_enet_entries(ugeth,
1910                                          &(ugeth->p_init_enet_param_shadow->
1911                                            rxthread[0]),
1912                                          ENET_INIT_PARAM_MAX_ENTRIES_RX,
1913                                          ugeth->ug_info->riscRx, 1);
1914                 return_init_enet_entries(ugeth,
1915                                          &(ugeth->p_init_enet_param_shadow->
1916                                            txthread[0]),
1917                                          ENET_INIT_PARAM_MAX_ENTRIES_TX,
1918                                          ugeth->ug_info->riscTx, 0);
1919                 kfree(ugeth->p_init_enet_param_shadow);
1920                 ugeth->p_init_enet_param_shadow = NULL;
1921         }
1922         for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
1923                 bd = ugeth->p_tx_bd_ring[i];
1924                 if (!bd)
1925                         continue;
1926                 for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) {
1927                         if (ugeth->tx_skbuff[i][j]) {
1928                                 dma_unmap_single(ugeth->dev,
1929                                                  in_be32(&((struct qe_bd __iomem *)bd)->buf),
1930                                                  (in_be32((u32 __iomem *)bd) &
1931                                                   BD_LENGTH_MASK),
1932                                                  DMA_TO_DEVICE);
1933                                 dev_kfree_skb_any(ugeth->tx_skbuff[i][j]);
1934                                 ugeth->tx_skbuff[i][j] = NULL;
1935                         }
1936                 }
1937
1938                 kfree(ugeth->tx_skbuff[i]);
1939
1940                 if (ugeth->p_tx_bd_ring[i]) {
1941                         if (ugeth->ug_info->uf_info.bd_mem_part ==
1942                             MEM_PART_SYSTEM)
1943                                 kfree((void *)ugeth->tx_bd_ring_offset[i]);
1944                         else if (ugeth->ug_info->uf_info.bd_mem_part ==
1945                                  MEM_PART_MURAM)
1946                                 qe_muram_free(ugeth->tx_bd_ring_offset[i]);
1947                         ugeth->p_tx_bd_ring[i] = NULL;
1948                 }
1949         }
1950         for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1951                 if (ugeth->p_rx_bd_ring[i]) {
1952                         /* Return existing data buffers in ring */
1953                         bd = ugeth->p_rx_bd_ring[i];
1954                         for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) {
1955                                 if (ugeth->rx_skbuff[i][j]) {
1956                                         dma_unmap_single(ugeth->dev,
1957                                                 in_be32(&((struct qe_bd __iomem *)bd)->buf),
1958                                                 ugeth->ug_info->
1959                                                 uf_info.max_rx_buf_length +
1960                                                 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
1961                                                 DMA_FROM_DEVICE);
1962                                         dev_kfree_skb_any(
1963                                                 ugeth->rx_skbuff[i][j]);
1964                                         ugeth->rx_skbuff[i][j] = NULL;
1965                                 }
1966                                 bd += sizeof(struct qe_bd);
1967                         }
1968
1969                         kfree(ugeth->rx_skbuff[i]);
1970
1971                         if (ugeth->ug_info->uf_info.bd_mem_part ==
1972                             MEM_PART_SYSTEM)
1973                                 kfree((void *)ugeth->rx_bd_ring_offset[i]);
1974                         else if (ugeth->ug_info->uf_info.bd_mem_part ==
1975                                  MEM_PART_MURAM)
1976                                 qe_muram_free(ugeth->rx_bd_ring_offset[i]);
1977                         ugeth->p_rx_bd_ring[i] = NULL;
1978                 }
1979         }
1980         while (!list_empty(&ugeth->group_hash_q))
1981                 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1982                                         (dequeue(&ugeth->group_hash_q)));
1983         while (!list_empty(&ugeth->ind_hash_q))
1984                 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1985                                         (dequeue(&ugeth->ind_hash_q)));
1986         if (ugeth->ug_regs) {
1987                 iounmap(ugeth->ug_regs);
1988                 ugeth->ug_regs = NULL;
1989         }
1990
1991         skb_queue_purge(&ugeth->rx_recycle);
1992 }
1993
1994 static void ucc_geth_set_multi(struct net_device *dev)
1995 {
1996         struct ucc_geth_private *ugeth;
1997         struct dev_mc_list *dmi;
1998         struct ucc_fast __iomem *uf_regs;
1999         struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
2000         int i;
2001
2002         ugeth = netdev_priv(dev);
2003
2004         uf_regs = ugeth->uccf->uf_regs;
2005
2006         if (dev->flags & IFF_PROMISC) {
2007                 setbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
2008         } else {
2009                 clrbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
2010
2011                 p_82xx_addr_filt =
2012                     (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
2013                     p_rx_glbl_pram->addressfiltering;
2014
2015                 if (dev->flags & IFF_ALLMULTI) {
2016                         /* Catch all multicast addresses, so set the
2017                          * filter to all 1's.
2018                          */
2019                         out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff);
2020                         out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff);
2021                 } else {
2022                         /* Clear filter and add the addresses in the list.
2023                          */
2024                         out_be32(&p_82xx_addr_filt->gaddr_h, 0x0);
2025                         out_be32(&p_82xx_addr_filt->gaddr_l, 0x0);
2026
2027                         dmi = dev->mc_list;
2028
2029                         for (i = 0; i < dev->mc_count; i++, dmi = dmi->next) {
2030
2031                                 /* Only support group multicast for now.
2032                                  */
2033                                 if (!(dmi->dmi_addr[0] & 1))
2034                                         continue;
2035
2036                                 /* Ask CPM to run CRC and set bit in
2037                                  * filter mask.
2038                                  */
2039                                 hw_add_addr_in_hash(ugeth, dmi->dmi_addr);
2040                         }
2041                 }
2042         }
2043 }
2044
2045 static void ucc_geth_stop(struct ucc_geth_private *ugeth)
2046 {
2047         struct ucc_geth __iomem *ug_regs = ugeth->ug_regs;
2048         struct phy_device *phydev = ugeth->phydev;
2049
2050         ugeth_vdbg("%s: IN", __func__);
2051
2052         /* Disable the controller */
2053         ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
2054
2055         /* Tell the kernel the link is down */
2056         phy_stop(phydev);
2057
2058         /* Mask all interrupts */
2059         out_be32(ugeth->uccf->p_uccm, 0x00000000);
2060
2061         /* Clear all interrupts */
2062         out_be32(ugeth->uccf->p_ucce, 0xffffffff);
2063
2064         /* Disable Rx and Tx */
2065         clrbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2066
2067         phy_disconnect(ugeth->phydev);
2068         ugeth->phydev = NULL;
2069
2070         ucc_geth_memclean(ugeth);
2071 }
2072
2073 static int ucc_struct_init(struct ucc_geth_private *ugeth)
2074 {
2075         struct ucc_geth_info *ug_info;
2076         struct ucc_fast_info *uf_info;
2077         int i;
2078
2079         ug_info = ugeth->ug_info;
2080         uf_info = &ug_info->uf_info;
2081
2082         if (!((uf_info->bd_mem_part == MEM_PART_SYSTEM) ||
2083               (uf_info->bd_mem_part == MEM_PART_MURAM))) {
2084                 if (netif_msg_probe(ugeth))
2085                         ugeth_err("%s: Bad memory partition value.",
2086                                         __func__);
2087                 return -EINVAL;
2088         }
2089
2090         /* Rx BD lengths */
2091         for (i = 0; i < ug_info->numQueuesRx; i++) {
2092                 if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) ||
2093                     (ug_info->bdRingLenRx[i] %
2094                      UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) {
2095                         if (netif_msg_probe(ugeth))
2096                                 ugeth_err
2097                                     ("%s: Rx BD ring length must be multiple of 4, no smaller than 8.",
2098                                         __func__);
2099                         return -EINVAL;
2100                 }
2101         }
2102
2103         /* Tx BD lengths */
2104         for (i = 0; i < ug_info->numQueuesTx; i++) {
2105                 if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) {
2106                         if (netif_msg_probe(ugeth))
2107                                 ugeth_err
2108                                     ("%s: Tx BD ring length must be no smaller than 2.",
2109                                      __func__);
2110                         return -EINVAL;
2111                 }
2112         }
2113
2114         /* mrblr */
2115         if ((uf_info->max_rx_buf_length == 0) ||
2116             (uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) {
2117                 if (netif_msg_probe(ugeth))
2118                         ugeth_err
2119                             ("%s: max_rx_buf_length must be non-zero multiple of 128.",
2120                              __func__);
2121                 return -EINVAL;
2122         }
2123
2124         /* num Tx queues */
2125         if (ug_info->numQueuesTx > NUM_TX_QUEUES) {
2126                 if (netif_msg_probe(ugeth))
2127                         ugeth_err("%s: number of tx queues too large.", __func__);
2128                 return -EINVAL;
2129         }
2130
2131         /* num Rx queues */
2132         if (ug_info->numQueuesRx > NUM_RX_QUEUES) {
2133                 if (netif_msg_probe(ugeth))
2134                         ugeth_err("%s: number of rx queues too large.", __func__);
2135                 return -EINVAL;
2136         }
2137
2138         /* l2qt */
2139         for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) {
2140                 if (ug_info->l2qt[i] >= ug_info->numQueuesRx) {
2141                         if (netif_msg_probe(ugeth))
2142                                 ugeth_err
2143                                     ("%s: VLAN priority table entry must not be"
2144                                         " larger than number of Rx queues.",
2145                                      __func__);
2146                         return -EINVAL;
2147                 }
2148         }
2149
2150         /* l3qt */
2151         for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) {
2152                 if (ug_info->l3qt[i] >= ug_info->numQueuesRx) {
2153                         if (netif_msg_probe(ugeth))
2154                                 ugeth_err
2155                                     ("%s: IP priority table entry must not be"
2156                                         " larger than number of Rx queues.",
2157                                      __func__);
2158                         return -EINVAL;
2159                 }
2160         }
2161
2162         if (ug_info->cam && !ug_info->ecamptr) {
2163                 if (netif_msg_probe(ugeth))
2164                         ugeth_err("%s: If cam mode is chosen, must supply cam ptr.",
2165                                   __func__);
2166                 return -EINVAL;
2167         }
2168
2169         if ((ug_info->numStationAddresses !=
2170              UCC_GETH_NUM_OF_STATION_ADDRESSES_1)
2171             && ug_info->rxExtendedFiltering) {
2172                 if (netif_msg_probe(ugeth))
2173                         ugeth_err("%s: Number of station addresses greater than 1 "
2174                                   "not allowed in extended parsing mode.",
2175                                   __func__);
2176                 return -EINVAL;
2177         }
2178
2179         /* Generate uccm_mask for receive */
2180         uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */
2181         for (i = 0; i < ug_info->numQueuesRx; i++)
2182                 uf_info->uccm_mask |= (UCC_GETH_UCCE_RXF0 << i);
2183
2184         for (i = 0; i < ug_info->numQueuesTx; i++)
2185                 uf_info->uccm_mask |= (UCC_GETH_UCCE_TXB0 << i);
2186         /* Initialize the general fast UCC block. */
2187         if (ucc_fast_init(uf_info, &ugeth->uccf)) {
2188                 if (netif_msg_probe(ugeth))
2189                         ugeth_err("%s: Failed to init uccf.", __func__);
2190                 return -ENOMEM;
2191         }
2192
2193         /* read the number of risc engines, update the riscTx and riscRx
2194          * if there are 4 riscs in QE
2195          */
2196         if (qe_get_num_of_risc() == 4) {
2197                 ug_info->riscTx = QE_RISC_ALLOCATION_FOUR_RISCS;
2198                 ug_info->riscRx = QE_RISC_ALLOCATION_FOUR_RISCS;
2199         }
2200
2201         ugeth->ug_regs = ioremap(uf_info->regs, sizeof(*ugeth->ug_regs));
2202         if (!ugeth->ug_regs) {
2203                 if (netif_msg_probe(ugeth))
2204                         ugeth_err("%s: Failed to ioremap regs.", __func__);
2205                 return -ENOMEM;
2206         }
2207
2208         skb_queue_head_init(&ugeth->rx_recycle);
2209
2210         return 0;
2211 }
2212
2213 static int ucc_geth_startup(struct ucc_geth_private *ugeth)
2214 {
2215         struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
2216         struct ucc_geth_init_pram __iomem *p_init_enet_pram;
2217         struct ucc_fast_private *uccf;
2218         struct ucc_geth_info *ug_info;
2219         struct ucc_fast_info *uf_info;
2220         struct ucc_fast __iomem *uf_regs;
2221         struct ucc_geth __iomem *ug_regs;
2222         int ret_val = -EINVAL;
2223         u32 remoder = UCC_GETH_REMODER_INIT;
2224         u32 init_enet_pram_offset, cecr_subblock, command;
2225         u32 ifstat, i, j, size, l2qt, l3qt, length;
2226         u16 temoder = UCC_GETH_TEMODER_INIT;
2227         u16 test;
2228         u8 function_code = 0;
2229         u8 __iomem *bd;
2230         u8 __iomem *endOfRing;
2231         u8 numThreadsRxNumerical, numThreadsTxNumerical;
2232
2233         ugeth_vdbg("%s: IN", __func__);
2234         uccf = ugeth->uccf;
2235         ug_info = ugeth->ug_info;
2236         uf_info = &ug_info->uf_info;
2237         uf_regs = uccf->uf_regs;
2238         ug_regs = ugeth->ug_regs;
2239
2240         switch (ug_info->numThreadsRx) {
2241         case UCC_GETH_NUM_OF_THREADS_1:
2242                 numThreadsRxNumerical = 1;
2243                 break;
2244         case UCC_GETH_NUM_OF_THREADS_2:
2245                 numThreadsRxNumerical = 2;
2246                 break;
2247         case UCC_GETH_NUM_OF_THREADS_4:
2248                 numThreadsRxNumerical = 4;
2249                 break;
2250         case UCC_GETH_NUM_OF_THREADS_6:
2251                 numThreadsRxNumerical = 6;
2252                 break;
2253         case UCC_GETH_NUM_OF_THREADS_8:
2254                 numThreadsRxNumerical = 8;
2255                 break;
2256         default:
2257                 if (netif_msg_ifup(ugeth))
2258                         ugeth_err("%s: Bad number of Rx threads value.",
2259                                         __func__);
2260                 return -EINVAL;
2261                 break;
2262         }
2263
2264         switch (ug_info->numThreadsTx) {
2265         case UCC_GETH_NUM_OF_THREADS_1:
2266                 numThreadsTxNumerical = 1;
2267                 break;
2268         case UCC_GETH_NUM_OF_THREADS_2:
2269                 numThreadsTxNumerical = 2;
2270                 break;
2271         case UCC_GETH_NUM_OF_THREADS_4:
2272                 numThreadsTxNumerical = 4;
2273                 break;
2274         case UCC_GETH_NUM_OF_THREADS_6:
2275                 numThreadsTxNumerical = 6;
2276                 break;
2277         case UCC_GETH_NUM_OF_THREADS_8:
2278                 numThreadsTxNumerical = 8;
2279                 break;
2280         default:
2281                 if (netif_msg_ifup(ugeth))
2282                         ugeth_err("%s: Bad number of Tx threads value.",
2283                                         __func__);
2284                 return -EINVAL;
2285                 break;
2286         }
2287
2288         /* Calculate rx_extended_features */
2289         ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck ||
2290             ug_info->ipAddressAlignment ||
2291             (ug_info->numStationAddresses !=
2292              UCC_GETH_NUM_OF_STATION_ADDRESSES_1);
2293
2294         ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features ||
2295             (ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP)
2296             || (ug_info->vlanOperationNonTagged !=
2297                 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP);
2298
2299         init_default_reg_vals(&uf_regs->upsmr,
2300                               &ug_regs->maccfg1, &ug_regs->maccfg2);
2301
2302         /*                    Set UPSMR                      */
2303         /* For more details see the hardware spec.           */
2304         init_rx_parameters(ug_info->bro,
2305                            ug_info->rsh, ug_info->pro, &uf_regs->upsmr);
2306
2307         /* We're going to ignore other registers for now, */
2308         /* except as needed to get up and running         */
2309
2310         /*                    Set MACCFG1                    */
2311         /* For more details see the hardware spec.           */
2312         init_flow_control_params(ug_info->aufc,
2313                                  ug_info->receiveFlowControl,
2314                                  ug_info->transmitFlowControl,
2315                                  ug_info->pausePeriod,
2316                                  ug_info->extensionField,
2317                                  &uf_regs->upsmr,
2318                                  &ug_regs->uempr, &ug_regs->maccfg1);
2319
2320         setbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2321
2322         /*                    Set IPGIFG                     */
2323         /* For more details see the hardware spec.           */
2324         ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1,
2325                                               ug_info->nonBackToBackIfgPart2,
2326                                               ug_info->
2327                                               miminumInterFrameGapEnforcement,
2328                                               ug_info->backToBackInterFrameGap,
2329                                               &ug_regs->ipgifg);
2330         if (ret_val != 0) {
2331                 if (netif_msg_ifup(ugeth))
2332                         ugeth_err("%s: IPGIFG initialization parameter too large.",
2333                                   __func__);
2334                 return ret_val;
2335         }
2336
2337         /*                    Set HAFDUP                     */
2338         /* For more details see the hardware spec.           */
2339         ret_val = init_half_duplex_params(ug_info->altBeb,
2340                                           ug_info->backPressureNoBackoff,
2341                                           ug_info->noBackoff,
2342                                           ug_info->excessDefer,
2343                                           ug_info->altBebTruncation,
2344                                           ug_info->maxRetransmission,
2345                                           ug_info->collisionWindow,
2346                                           &ug_regs->hafdup);
2347         if (ret_val != 0) {
2348                 if (netif_msg_ifup(ugeth))
2349                         ugeth_err("%s: Half Duplex initialization parameter too large.",
2350                           __func__);
2351                 return ret_val;
2352         }
2353
2354         /*                    Set IFSTAT                     */
2355         /* For more details see the hardware spec.           */
2356         /* Read only - resets upon read                      */
2357         ifstat = in_be32(&ug_regs->ifstat);
2358
2359         /*                    Clear UEMPR                    */
2360         /* For more details see the hardware spec.           */
2361         out_be32(&ug_regs->uempr, 0);
2362
2363         /*                    Set UESCR                      */
2364         /* For more details see the hardware spec.           */
2365         init_hw_statistics_gathering_mode((ug_info->statisticsMode &
2366                                 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE),
2367                                 0, &uf_regs->upsmr, &ug_regs->uescr);
2368
2369         /* Allocate Tx bds */
2370         for (j = 0; j < ug_info->numQueuesTx; j++) {
2371                 /* Allocate in multiple of
2372                    UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT,
2373                    according to spec */
2374                 length = ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd))
2375                           / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2376                     * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2377                 if ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) %
2378                     UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2379                         length += UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2380                 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2381                         u32 align = 4;
2382                         if (UCC_GETH_TX_BD_RING_ALIGNMENT > 4)
2383                                 align = UCC_GETH_TX_BD_RING_ALIGNMENT;
2384                         ugeth->tx_bd_ring_offset[j] =
2385                                 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
2386
2387                         if (ugeth->tx_bd_ring_offset[j] != 0)
2388                                 ugeth->p_tx_bd_ring[j] =
2389                                         (u8 __iomem *)((ugeth->tx_bd_ring_offset[j] +
2390                                         align) & ~(align - 1));
2391                 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2392                         ugeth->tx_bd_ring_offset[j] =
2393                             qe_muram_alloc(length,
2394                                            UCC_GETH_TX_BD_RING_ALIGNMENT);
2395                         if (!IS_ERR_VALUE(ugeth->tx_bd_ring_offset[j]))
2396                                 ugeth->p_tx_bd_ring[j] =
2397                                     (u8 __iomem *) qe_muram_addr(ugeth->
2398                                                          tx_bd_ring_offset[j]);
2399                 }
2400                 if (!ugeth->p_tx_bd_ring[j]) {
2401                         if (netif_msg_ifup(ugeth))
2402                                 ugeth_err
2403                                     ("%s: Can not allocate memory for Tx bd rings.",
2404                                      __func__);
2405                         return -ENOMEM;
2406                 }
2407                 /* Zero unused end of bd ring, according to spec */
2408                 memset_io((void __iomem *)(ugeth->p_tx_bd_ring[j] +
2409                        ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)), 0,
2410                        length - ug_info->bdRingLenTx[j] * sizeof(struct qe_bd));
2411         }
2412
2413         /* Allocate Rx bds */
2414         for (j = 0; j < ug_info->numQueuesRx; j++) {
2415                 length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd);
2416                 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2417                         u32 align = 4;
2418                         if (UCC_GETH_RX_BD_RING_ALIGNMENT > 4)
2419                                 align = UCC_GETH_RX_BD_RING_ALIGNMENT;
2420                         ugeth->rx_bd_ring_offset[j] =
2421                                 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
2422                         if (ugeth->rx_bd_ring_offset[j] != 0)
2423                                 ugeth->p_rx_bd_ring[j] =
2424                                         (u8 __iomem *)((ugeth->rx_bd_ring_offset[j] +
2425                                         align) & ~(align - 1));
2426                 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2427                         ugeth->rx_bd_ring_offset[j] =
2428                             qe_muram_alloc(length,
2429                                            UCC_GETH_RX_BD_RING_ALIGNMENT);
2430                         if (!IS_ERR_VALUE(ugeth->rx_bd_ring_offset[j]))
2431                                 ugeth->p_rx_bd_ring[j] =
2432                                     (u8 __iomem *) qe_muram_addr(ugeth->
2433                                                          rx_bd_ring_offset[j]);
2434                 }
2435                 if (!ugeth->p_rx_bd_ring[j]) {
2436                         if (netif_msg_ifup(ugeth))
2437                                 ugeth_err
2438                                     ("%s: Can not allocate memory for Rx bd rings.",
2439                                      __func__);
2440                         return -ENOMEM;
2441                 }
2442         }
2443
2444         /* Init Tx bds */
2445         for (j = 0; j < ug_info->numQueuesTx; j++) {
2446                 /* Setup the skbuff rings */
2447                 ugeth->tx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2448                                               ugeth->ug_info->bdRingLenTx[j],
2449                                               GFP_KERNEL);
2450
2451                 if (ugeth->tx_skbuff[j] == NULL) {
2452                         if (netif_msg_ifup(ugeth))
2453                                 ugeth_err("%s: Could not allocate tx_skbuff",
2454                                           __func__);
2455                         return -ENOMEM;
2456                 }
2457
2458                 for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++)
2459                         ugeth->tx_skbuff[j][i] = NULL;
2460
2461                 ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0;
2462                 bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j];
2463                 for (i = 0; i < ug_info->bdRingLenTx[j]; i++) {
2464                         /* clear bd buffer */
2465                         out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
2466                         /* set bd status and length */
2467                         out_be32((u32 __iomem *)bd, 0);
2468                         bd += sizeof(struct qe_bd);
2469                 }
2470                 bd -= sizeof(struct qe_bd);
2471                 /* set bd status and length */
2472                 out_be32((u32 __iomem *)bd, T_W); /* for last BD set Wrap bit */
2473         }
2474
2475         /* Init Rx bds */
2476         for (j = 0; j < ug_info->numQueuesRx; j++) {
2477                 /* Setup the skbuff rings */
2478                 ugeth->rx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2479                                               ugeth->ug_info->bdRingLenRx[j],
2480                                               GFP_KERNEL);
2481
2482                 if (ugeth->rx_skbuff[j] == NULL) {
2483                         if (netif_msg_ifup(ugeth))
2484                                 ugeth_err("%s: Could not allocate rx_skbuff",
2485                                           __func__);
2486                         return -ENOMEM;
2487                 }
2488
2489                 for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++)
2490                         ugeth->rx_skbuff[j][i] = NULL;
2491
2492                 ugeth->skb_currx[j] = 0;
2493                 bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j];
2494                 for (i = 0; i < ug_info->bdRingLenRx[j]; i++) {
2495                         /* set bd status and length */
2496                         out_be32((u32 __iomem *)bd, R_I);
2497                         /* clear bd buffer */
2498                         out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
2499                         bd += sizeof(struct qe_bd);
2500                 }
2501                 bd -= sizeof(struct qe_bd);
2502                 /* set bd status and length */
2503                 out_be32((u32 __iomem *)bd, R_W); /* for last BD set Wrap bit */
2504         }
2505
2506         /*
2507          * Global PRAM
2508          */
2509         /* Tx global PRAM */
2510         /* Allocate global tx parameter RAM page */
2511         ugeth->tx_glbl_pram_offset =
2512             qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram),
2513                            UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT);
2514         if (IS_ERR_VALUE(ugeth->tx_glbl_pram_offset)) {
2515                 if (netif_msg_ifup(ugeth))
2516                         ugeth_err
2517                             ("%s: Can not allocate DPRAM memory for p_tx_glbl_pram.",
2518                              __func__);
2519                 return -ENOMEM;
2520         }
2521         ugeth->p_tx_glbl_pram =
2522             (struct ucc_geth_tx_global_pram __iomem *) qe_muram_addr(ugeth->
2523                                                         tx_glbl_pram_offset);
2524         /* Zero out p_tx_glbl_pram */
2525         memset_io((void __iomem *)ugeth->p_tx_glbl_pram, 0, sizeof(struct ucc_geth_tx_global_pram));
2526
2527         /* Fill global PRAM */
2528
2529         /* TQPTR */
2530         /* Size varies with number of Tx threads */
2531         ugeth->thread_dat_tx_offset =
2532             qe_muram_alloc(numThreadsTxNumerical *
2533                            sizeof(struct ucc_geth_thread_data_tx) +
2534                            32 * (numThreadsTxNumerical == 1),
2535                            UCC_GETH_THREAD_DATA_ALIGNMENT);
2536         if (IS_ERR_VALUE(ugeth->thread_dat_tx_offset)) {
2537                 if (netif_msg_ifup(ugeth))
2538                         ugeth_err
2539                             ("%s: Can not allocate DPRAM memory for p_thread_data_tx.",
2540                              __func__);
2541                 return -ENOMEM;
2542         }
2543
2544         ugeth->p_thread_data_tx =
2545             (struct ucc_geth_thread_data_tx __iomem *) qe_muram_addr(ugeth->
2546                                                         thread_dat_tx_offset);
2547         out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset);
2548
2549         /* vtagtable */
2550         for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++)
2551                 out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i],
2552                          ug_info->vtagtable[i]);
2553
2554         /* iphoffset */
2555         for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++)
2556                 out_8(&ugeth->p_tx_glbl_pram->iphoffset[i],
2557                                 ug_info->iphoffset[i]);
2558
2559         /* SQPTR */
2560         /* Size varies with number of Tx queues */
2561         ugeth->send_q_mem_reg_offset =
2562             qe_muram_alloc(ug_info->numQueuesTx *
2563                            sizeof(struct ucc_geth_send_queue_qd),
2564                            UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
2565         if (IS_ERR_VALUE(ugeth->send_q_mem_reg_offset)) {
2566                 if (netif_msg_ifup(ugeth))
2567                         ugeth_err
2568                             ("%s: Can not allocate DPRAM memory for p_send_q_mem_reg.",
2569                              __func__);
2570                 return -ENOMEM;
2571         }
2572
2573         ugeth->p_send_q_mem_reg =
2574             (struct ucc_geth_send_queue_mem_region __iomem *) qe_muram_addr(ugeth->
2575                         send_q_mem_reg_offset);
2576         out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset);
2577
2578         /* Setup the table */
2579         /* Assume BD rings are already established */
2580         for (i = 0; i < ug_info->numQueuesTx; i++) {
2581                 endOfRing =
2582                     ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] -
2583                                               1) * sizeof(struct qe_bd);
2584                 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2585                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2586                                  (u32) virt_to_phys(ugeth->p_tx_bd_ring[i]));
2587                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2588                                  last_bd_completed_address,
2589                                  (u32) virt_to_phys(endOfRing));
2590                 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2591                            MEM_PART_MURAM) {
2592                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2593                                  (u32) immrbar_virt_to_phys(ugeth->
2594                                                             p_tx_bd_ring[i]));
2595                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2596                                  last_bd_completed_address,
2597                                  (u32) immrbar_virt_to_phys(endOfRing));
2598                 }
2599         }
2600
2601         /* schedulerbasepointer */
2602
2603         if (ug_info->numQueuesTx > 1) {
2604         /* scheduler exists only if more than 1 tx queue */
2605                 ugeth->scheduler_offset =
2606                     qe_muram_alloc(sizeof(struct ucc_geth_scheduler),
2607                                    UCC_GETH_SCHEDULER_ALIGNMENT);
2608                 if (IS_ERR_VALUE(ugeth->scheduler_offset)) {
2609                         if (netif_msg_ifup(ugeth))
2610                                 ugeth_err
2611                                  ("%s: Can not allocate DPRAM memory for p_scheduler.",
2612                                      __func__);
2613                         return -ENOMEM;
2614                 }
2615
2616                 ugeth->p_scheduler =
2617                     (struct ucc_geth_scheduler __iomem *) qe_muram_addr(ugeth->
2618                                                            scheduler_offset);
2619                 out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer,
2620                          ugeth->scheduler_offset);
2621                 /* Zero out p_scheduler */
2622                 memset_io((void __iomem *)ugeth->p_scheduler, 0, sizeof(struct ucc_geth_scheduler));
2623
2624                 /* Set values in scheduler */
2625                 out_be32(&ugeth->p_scheduler->mblinterval,
2626                          ug_info->mblinterval);
2627                 out_be16(&ugeth->p_scheduler->nortsrbytetime,
2628                          ug_info->nortsrbytetime);
2629                 out_8(&ugeth->p_scheduler->fracsiz, ug_info->fracsiz);
2630                 out_8(&ugeth->p_scheduler->strictpriorityq,
2631                                 ug_info->strictpriorityq);
2632                 out_8(&ugeth->p_scheduler->txasap, ug_info->txasap);
2633                 out_8(&ugeth->p_scheduler->extrabw, ug_info->extrabw);
2634                 for (i = 0; i < NUM_TX_QUEUES; i++)
2635                         out_8(&ugeth->p_scheduler->weightfactor[i],
2636                             ug_info->weightfactor[i]);
2637
2638                 /* Set pointers to cpucount registers in scheduler */
2639                 ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0);
2640                 ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1);
2641                 ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2);
2642                 ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3);
2643                 ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4);
2644                 ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5);
2645                 ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6);
2646                 ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7);
2647         }
2648
2649         /* schedulerbasepointer */
2650         /* TxRMON_PTR (statistics) */
2651         if (ug_info->
2652             statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) {
2653                 ugeth->tx_fw_statistics_pram_offset =
2654                     qe_muram_alloc(sizeof
2655                                    (struct ucc_geth_tx_firmware_statistics_pram),
2656                                    UCC_GETH_TX_STATISTICS_ALIGNMENT);
2657                 if (IS_ERR_VALUE(ugeth->tx_fw_statistics_pram_offset)) {
2658                         if (netif_msg_ifup(ugeth))
2659                                 ugeth_err
2660                                     ("%s: Can not allocate DPRAM memory for"
2661                                         " p_tx_fw_statistics_pram.",
2662                                         __func__);
2663                         return -ENOMEM;
2664                 }
2665                 ugeth->p_tx_fw_statistics_pram =
2666                     (struct ucc_geth_tx_firmware_statistics_pram __iomem *)
2667                     qe_muram_addr(ugeth->tx_fw_statistics_pram_offset);
2668                 /* Zero out p_tx_fw_statistics_pram */
2669                 memset_io((void __iomem *)ugeth->p_tx_fw_statistics_pram,
2670                        0, sizeof(struct ucc_geth_tx_firmware_statistics_pram));
2671         }
2672
2673         /* temoder */
2674         /* Already has speed set */
2675
2676         if (ug_info->numQueuesTx > 1)
2677                 temoder |= TEMODER_SCHEDULER_ENABLE;
2678         if (ug_info->ipCheckSumGenerate)
2679                 temoder |= TEMODER_IP_CHECKSUM_GENERATE;
2680         temoder |= ((ug_info->numQueuesTx - 1) << TEMODER_NUM_OF_QUEUES_SHIFT);
2681         out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder);
2682
2683         test = in_be16(&ugeth->p_tx_glbl_pram->temoder);
2684
2685         /* Function code register value to be used later */
2686         function_code = UCC_BMR_BO_BE | UCC_BMR_GBL;
2687         /* Required for QE */
2688
2689         /* function code register */
2690         out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24);
2691
2692         /* Rx global PRAM */
2693         /* Allocate global rx parameter RAM page */
2694         ugeth->rx_glbl_pram_offset =
2695             qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram),
2696                            UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT);
2697         if (IS_ERR_VALUE(ugeth->rx_glbl_pram_offset)) {
2698                 if (netif_msg_ifup(ugeth))
2699                         ugeth_err
2700                             ("%s: Can not allocate DPRAM memory for p_rx_glbl_pram.",
2701                              __func__);
2702                 return -ENOMEM;
2703         }
2704         ugeth->p_rx_glbl_pram =
2705             (struct ucc_geth_rx_global_pram __iomem *) qe_muram_addr(ugeth->
2706                                                         rx_glbl_pram_offset);
2707         /* Zero out p_rx_glbl_pram */
2708         memset_io((void __iomem *)ugeth->p_rx_glbl_pram, 0, sizeof(struct ucc_geth_rx_global_pram));
2709
2710         /* Fill global PRAM */
2711
2712         /* RQPTR */
2713         /* Size varies with number of Rx threads */
2714         ugeth->thread_dat_rx_offset =
2715             qe_muram_alloc(numThreadsRxNumerical *
2716                            sizeof(struct ucc_geth_thread_data_rx),
2717                            UCC_GETH_THREAD_DATA_ALIGNMENT);
2718         if (IS_ERR_VALUE(ugeth->thread_dat_rx_offset)) {
2719                 if (netif_msg_ifup(ugeth))
2720                         ugeth_err
2721                             ("%s: Can not allocate DPRAM memory for p_thread_data_rx.",
2722                              __func__);
2723                 return -ENOMEM;
2724         }
2725
2726         ugeth->p_thread_data_rx =
2727             (struct ucc_geth_thread_data_rx __iomem *) qe_muram_addr(ugeth->
2728                                                         thread_dat_rx_offset);
2729         out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset);
2730
2731         /* typeorlen */
2732         out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen);
2733
2734         /* rxrmonbaseptr (statistics) */
2735         if (ug_info->
2736             statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) {
2737                 ugeth->rx_fw_statistics_pram_offset =
2738                     qe_muram_alloc(sizeof
2739                                    (struct ucc_geth_rx_firmware_statistics_pram),
2740                                    UCC_GETH_RX_STATISTICS_ALIGNMENT);
2741                 if (IS_ERR_VALUE(ugeth->rx_fw_statistics_pram_offset)) {
2742                         if (netif_msg_ifup(ugeth))
2743                                 ugeth_err
2744                                         ("%s: Can not allocate DPRAM memory for"
2745                                         " p_rx_fw_statistics_pram.", __func__);
2746                         return -ENOMEM;
2747                 }
2748                 ugeth->p_rx_fw_statistics_pram =
2749                     (struct ucc_geth_rx_firmware_statistics_pram __iomem *)
2750                     qe_muram_addr(ugeth->rx_fw_statistics_pram_offset);
2751                 /* Zero out p_rx_fw_statistics_pram */
2752                 memset_io((void __iomem *)ugeth->p_rx_fw_statistics_pram, 0,
2753                        sizeof(struct ucc_geth_rx_firmware_statistics_pram));
2754         }
2755
2756         /* intCoalescingPtr */
2757
2758         /* Size varies with number of Rx queues */
2759         ugeth->rx_irq_coalescing_tbl_offset =
2760             qe_muram_alloc(ug_info->numQueuesRx *
2761                            sizeof(struct ucc_geth_rx_interrupt_coalescing_entry)
2762                            + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT);
2763         if (IS_ERR_VALUE(ugeth->rx_irq_coalescing_tbl_offset)) {
2764                 if (netif_msg_ifup(ugeth))
2765                         ugeth_err
2766                             ("%s: Can not allocate DPRAM memory for"
2767                                 " p_rx_irq_coalescing_tbl.", __func__);
2768                 return -ENOMEM;
2769         }
2770
2771         ugeth->p_rx_irq_coalescing_tbl =
2772             (struct ucc_geth_rx_interrupt_coalescing_table __iomem *)
2773             qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset);
2774         out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr,
2775                  ugeth->rx_irq_coalescing_tbl_offset);
2776
2777         /* Fill interrupt coalescing table */
2778         for (i = 0; i < ug_info->numQueuesRx; i++) {
2779                 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2780                          interruptcoalescingmaxvalue,
2781                          ug_info->interruptcoalescingmaxvalue[i]);
2782                 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2783                          interruptcoalescingcounter,
2784                          ug_info->interruptcoalescingmaxvalue[i]);
2785         }
2786
2787         /* MRBLR */
2788         init_max_rx_buff_len(uf_info->max_rx_buf_length,
2789                              &ugeth->p_rx_glbl_pram->mrblr);
2790         /* MFLR */
2791         out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength);
2792         /* MINFLR */
2793         init_min_frame_len(ug_info->minFrameLength,
2794                            &ugeth->p_rx_glbl_pram->minflr,
2795                            &ugeth->p_rx_glbl_pram->mrblr);
2796         /* MAXD1 */
2797         out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length);
2798         /* MAXD2 */
2799         out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length);
2800
2801         /* l2qt */
2802         l2qt = 0;
2803         for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++)
2804                 l2qt |= (ug_info->l2qt[i] << (28 - 4 * i));
2805         out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt);
2806
2807         /* l3qt */
2808         for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) {
2809                 l3qt = 0;
2810                 for (i = 0; i < 8; i++)
2811                         l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i));
2812                 out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt);
2813         }
2814
2815         /* vlantype */
2816         out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype);
2817
2818         /* vlantci */
2819         out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci);
2820
2821         /* ecamptr */
2822         out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr);
2823
2824         /* RBDQPTR */
2825         /* Size varies with number of Rx queues */
2826         ugeth->rx_bd_qs_tbl_offset =
2827             qe_muram_alloc(ug_info->numQueuesRx *
2828                            (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2829                             sizeof(struct ucc_geth_rx_prefetched_bds)),
2830                            UCC_GETH_RX_BD_QUEUES_ALIGNMENT);
2831         if (IS_ERR_VALUE(ugeth->rx_bd_qs_tbl_offset)) {
2832                 if (netif_msg_ifup(ugeth))
2833                         ugeth_err
2834                             ("%s: Can not allocate DPRAM memory for p_rx_bd_qs_tbl.",
2835                              __func__);
2836                 return -ENOMEM;
2837         }
2838
2839         ugeth->p_rx_bd_qs_tbl =
2840             (struct ucc_geth_rx_bd_queues_entry __iomem *) qe_muram_addr(ugeth->
2841                                     rx_bd_qs_tbl_offset);
2842         out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset);
2843         /* Zero out p_rx_bd_qs_tbl */
2844         memset_io((void __iomem *)ugeth->p_rx_bd_qs_tbl,
2845                0,
2846                ug_info->numQueuesRx * (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2847                                        sizeof(struct ucc_geth_rx_prefetched_bds)));
2848
2849         /* Setup the table */
2850         /* Assume BD rings are already established */
2851         for (i = 0; i < ug_info->numQueuesRx; i++) {
2852                 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2853                         out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2854                                  (u32) virt_to_phys(ugeth->p_rx_bd_ring[i]));
2855                 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2856                            MEM_PART_MURAM) {
2857                         out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2858                                  (u32) immrbar_virt_to_phys(ugeth->
2859                                                             p_rx_bd_ring[i]));
2860                 }
2861                 /* rest of fields handled by QE */
2862         }
2863
2864         /* remoder */
2865         /* Already has speed set */
2866
2867         if (ugeth->rx_extended_features)
2868                 remoder |= REMODER_RX_EXTENDED_FEATURES;
2869         if (ug_info->rxExtendedFiltering)
2870                 remoder |= REMODER_RX_EXTENDED_FILTERING;
2871         if (ug_info->dynamicMaxFrameLength)
2872                 remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH;
2873         if (ug_info->dynamicMinFrameLength)
2874                 remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH;
2875         remoder |=
2876             ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT;
2877         remoder |=
2878             ug_info->
2879             vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT;
2880         remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT;
2881         remoder |= ((ug_info->numQueuesRx - 1) << REMODER_NUM_OF_QUEUES_SHIFT);
2882         if (ug_info->ipCheckSumCheck)
2883                 remoder |= REMODER_IP_CHECKSUM_CHECK;
2884         if (ug_info->ipAddressAlignment)
2885                 remoder |= REMODER_IP_ADDRESS_ALIGNMENT;
2886         out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder);
2887
2888         /* Note that this function must be called */
2889         /* ONLY AFTER p_tx_fw_statistics_pram */
2890         /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */
2891         init_firmware_statistics_gathering_mode((ug_info->
2892                 statisticsMode &
2893                 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX),
2894                 (ug_info->statisticsMode &
2895                 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX),
2896                 &ugeth->p_tx_glbl_pram->txrmonbaseptr,
2897                 ugeth->tx_fw_statistics_pram_offset,
2898                 &ugeth->p_rx_glbl_pram->rxrmonbaseptr,
2899                 ugeth->rx_fw_statistics_pram_offset,
2900                 &ugeth->p_tx_glbl_pram->temoder,
2901                 &ugeth->p_rx_glbl_pram->remoder);
2902
2903         /* function code register */
2904         out_8(&ugeth->p_rx_glbl_pram->rstate, function_code);
2905
2906         /* initialize extended filtering */
2907         if (ug_info->rxExtendedFiltering) {
2908                 if (!ug_info->extendedFilteringChainPointer) {
2909                         if (netif_msg_ifup(ugeth))
2910                                 ugeth_err("%s: Null Extended Filtering Chain Pointer.",
2911                                           __func__);
2912                         return -EINVAL;
2913                 }
2914
2915                 /* Allocate memory for extended filtering Mode Global
2916                 Parameters */
2917                 ugeth->exf_glbl_param_offset =
2918                     qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram),
2919                 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT);
2920                 if (IS_ERR_VALUE(ugeth->exf_glbl_param_offset)) {
2921                         if (netif_msg_ifup(ugeth))
2922                                 ugeth_err
2923                                         ("%s: Can not allocate DPRAM memory for"
2924                                         " p_exf_glbl_param.", __func__);
2925                         return -ENOMEM;
2926                 }
2927
2928                 ugeth->p_exf_glbl_param =
2929                     (struct ucc_geth_exf_global_pram __iomem *) qe_muram_addr(ugeth->
2930                                  exf_glbl_param_offset);
2931                 out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam,
2932                          ugeth->exf_glbl_param_offset);
2933                 out_be32(&ugeth->p_exf_glbl_param->l2pcdptr,
2934                          (u32) ug_info->extendedFilteringChainPointer);
2935
2936         } else {                /* initialize 82xx style address filtering */
2937
2938                 /* Init individual address recognition registers to disabled */
2939
2940                 for (j = 0; j < NUM_OF_PADDRS; j++)
2941                         ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j);
2942
2943                 p_82xx_addr_filt =
2944                     (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
2945                     p_rx_glbl_pram->addressfiltering;
2946
2947                 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2948                         ENET_ADDR_TYPE_GROUP);
2949                 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2950                         ENET_ADDR_TYPE_INDIVIDUAL);
2951         }
2952
2953         /*
2954          * Initialize UCC at QE level
2955          */
2956
2957         command = QE_INIT_TX_RX;
2958
2959         /* Allocate shadow InitEnet command parameter structure.
2960          * This is needed because after the InitEnet command is executed,
2961          * the structure in DPRAM is released, because DPRAM is a premium
2962          * resource.
2963          * This shadow structure keeps a copy of what was done so that the
2964          * allocated resources can be released when the channel is freed.
2965          */
2966         if (!(ugeth->p_init_enet_param_shadow =
2967               kmalloc(sizeof(struct ucc_geth_init_pram), GFP_KERNEL))) {
2968                 if (netif_msg_ifup(ugeth))
2969                         ugeth_err
2970                             ("%s: Can not allocate memory for"
2971                                 " p_UccInitEnetParamShadows.", __func__);
2972                 return -ENOMEM;
2973         }
2974         /* Zero out *p_init_enet_param_shadow */
2975         memset((char *)ugeth->p_init_enet_param_shadow,
2976                0, sizeof(struct ucc_geth_init_pram));
2977
2978         /* Fill shadow InitEnet command parameter structure */
2979
2980         ugeth->p_init_enet_param_shadow->resinit1 =
2981             ENET_INIT_PARAM_MAGIC_RES_INIT1;
2982         ugeth->p_init_enet_param_shadow->resinit2 =
2983             ENET_INIT_PARAM_MAGIC_RES_INIT2;
2984         ugeth->p_init_enet_param_shadow->resinit3 =
2985             ENET_INIT_PARAM_MAGIC_RES_INIT3;
2986         ugeth->p_init_enet_param_shadow->resinit4 =
2987             ENET_INIT_PARAM_MAGIC_RES_INIT4;
2988         ugeth->p_init_enet_param_shadow->resinit5 =
2989             ENET_INIT_PARAM_MAGIC_RES_INIT5;
2990         ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2991             ((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT;
2992         ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2993             ((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT;
2994
2995         ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2996             ugeth->rx_glbl_pram_offset | ug_info->riscRx;
2997         if ((ug_info->largestexternallookupkeysize !=
2998              QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE)
2999             && (ug_info->largestexternallookupkeysize !=
3000                 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
3001             && (ug_info->largestexternallookupkeysize !=
3002                 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)) {
3003                 if (netif_msg_ifup(ugeth))
3004                         ugeth_err("%s: Invalid largest External Lookup Key Size.",
3005                                   __func__);
3006                 return -EINVAL;
3007         }
3008         ugeth->p_init_enet_param_shadow->largestexternallookupkeysize =
3009             ug_info->largestexternallookupkeysize;
3010         size = sizeof(struct ucc_geth_thread_rx_pram);
3011         if (ug_info->rxExtendedFiltering) {
3012                 size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
3013                 if (ug_info->largestexternallookupkeysize ==
3014                     QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
3015                         size +=
3016                             THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
3017                 if (ug_info->largestexternallookupkeysize ==
3018                     QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
3019                         size +=
3020                             THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
3021         }
3022
3023         if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth->
3024                 p_init_enet_param_shadow->rxthread[0]),
3025                 (u8) (numThreadsRxNumerical + 1)
3026                 /* Rx needs one extra for terminator */
3027                 , size, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT,
3028                 ug_info->riscRx, 1)) != 0) {
3029                 if (netif_msg_ifup(ugeth))
3030                                 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
3031                                         __func__);
3032                 return ret_val;
3033         }
3034
3035         ugeth->p_init_enet_param_shadow->txglobal =
3036             ugeth->tx_glbl_pram_offset | ug_info->riscTx;
3037         if ((ret_val =
3038              fill_init_enet_entries(ugeth,
3039                                     &(ugeth->p_init_enet_param_shadow->
3040                                       txthread[0]), numThreadsTxNumerical,
3041                                     sizeof(struct ucc_geth_thread_tx_pram),
3042                                     UCC_GETH_THREAD_TX_PRAM_ALIGNMENT,
3043                                     ug_info->riscTx, 0)) != 0) {
3044                 if (netif_msg_ifup(ugeth))
3045                         ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
3046                                   __func__);
3047                 return ret_val;
3048         }
3049
3050         /* Load Rx bds with buffers */
3051         for (i = 0; i < ug_info->numQueuesRx; i++) {
3052                 if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) {
3053                         if (netif_msg_ifup(ugeth))
3054                                 ugeth_err("%s: Can not fill Rx bds with buffers.",
3055                                           __func__);
3056                         return ret_val;
3057                 }
3058         }
3059
3060         /* Allocate InitEnet command parameter structure */
3061         init_enet_pram_offset = qe_muram_alloc(sizeof(struct ucc_geth_init_pram), 4);
3062         if (IS_ERR_VALUE(init_enet_pram_offset)) {
3063                 if (netif_msg_ifup(ugeth))
3064                         ugeth_err
3065                             ("%s: Can not allocate DPRAM memory for p_init_enet_pram.",
3066                              __func__);
3067                 return -ENOMEM;
3068         }
3069         p_init_enet_pram =
3070             (struct ucc_geth_init_pram __iomem *) qe_muram_addr(init_enet_pram_offset);
3071
3072         /* Copy shadow InitEnet command parameter structure into PRAM */
3073         out_8(&p_init_enet_pram->resinit1,
3074                         ugeth->p_init_enet_param_shadow->resinit1);
3075         out_8(&p_init_enet_pram->resinit2,
3076                         ugeth->p_init_enet_param_shadow->resinit2);
3077         out_8(&p_init_enet_pram->resinit3,
3078                         ugeth->p_init_enet_param_shadow->resinit3);
3079         out_8(&p_init_enet_pram->resinit4,
3080                         ugeth->p_init_enet_param_shadow->resinit4);
3081         out_be16(&p_init_enet_pram->resinit5,
3082                  ugeth->p_init_enet_param_shadow->resinit5);
3083         out_8(&p_init_enet_pram->largestexternallookupkeysize,
3084             ugeth->p_init_enet_param_shadow->largestexternallookupkeysize);
3085         out_be32(&p_init_enet_pram->rgftgfrxglobal,
3086                  ugeth->p_init_enet_param_shadow->rgftgfrxglobal);
3087         for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_RX; i++)
3088                 out_be32(&p_init_enet_pram->rxthread[i],
3089                          ugeth->p_init_enet_param_shadow->rxthread[i]);
3090         out_be32(&p_init_enet_pram->txglobal,
3091                  ugeth->p_init_enet_param_shadow->txglobal);
3092         for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_TX; i++)
3093                 out_be32(&p_init_enet_pram->txthread[i],
3094                          ugeth->p_init_enet_param_shadow->txthread[i]);
3095
3096         /* Issue QE command */
3097         cecr_subblock =
3098             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
3099         qe_issue_cmd(command, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
3100                      init_enet_pram_offset);
3101
3102         /* Free InitEnet command parameter */
3103         qe_muram_free(init_enet_pram_offset);
3104
3105         return 0;
3106 }
3107
3108 /* This is called by the kernel when a frame is ready for transmission. */
3109 /* It is pointed to by the dev->hard_start_xmit function pointer */
3110 static int ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev)
3111 {
3112         struct ucc_geth_private *ugeth = netdev_priv(dev);
3113 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3114         struct ucc_fast_private *uccf;
3115 #endif
3116         u8 __iomem *bd;                 /* BD pointer */
3117         u32 bd_status;
3118         u8 txQ = 0;
3119
3120         ugeth_vdbg("%s: IN", __func__);
3121
3122         spin_lock_irq(&ugeth->lock);
3123
3124         dev->stats.tx_bytes += skb->len;
3125
3126         /* Start from the next BD that should be filled */
3127         bd = ugeth->txBd[txQ];
3128         bd_status = in_be32((u32 __iomem *)bd);
3129         /* Save the skb pointer so we can free it later */
3130         ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb;
3131
3132         /* Update the current skb pointer (wrapping if this was the last) */
3133         ugeth->skb_curtx[txQ] =
3134             (ugeth->skb_curtx[txQ] +
3135              1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3136
3137         /* set up the buffer descriptor */
3138         out_be32(&((struct qe_bd __iomem *)bd)->buf,
3139                       dma_map_single(ugeth->dev, skb->data,
3140                               skb->len, DMA_TO_DEVICE));
3141
3142         /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */
3143
3144         bd_status = (bd_status & T_W) | T_R | T_I | T_L | skb->len;
3145
3146         /* set bd status and length */
3147         out_be32((u32 __iomem *)bd, bd_status);
3148
3149         dev->trans_start = jiffies;
3150
3151         /* Move to next BD in the ring */
3152         if (!(bd_status & T_W))
3153                 bd += sizeof(struct qe_bd);
3154         else
3155                 bd = ugeth->p_tx_bd_ring[txQ];
3156
3157         /* If the next BD still needs to be cleaned up, then the bds
3158            are full.  We need to tell the kernel to stop sending us stuff. */
3159         if (bd == ugeth->confBd[txQ]) {
3160                 if (!netif_queue_stopped(dev))
3161                         netif_stop_queue(dev);
3162         }
3163
3164         ugeth->txBd[txQ] = bd;
3165
3166         if (ugeth->p_scheduler) {
3167                 ugeth->cpucount[txQ]++;
3168                 /* Indicate to QE that there are more Tx bds ready for
3169                 transmission */
3170                 /* This is done by writing a running counter of the bd
3171                 count to the scheduler PRAM. */
3172                 out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]);
3173         }
3174
3175 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3176         uccf = ugeth->uccf;
3177         out_be16(uccf->p_utodr, UCC_FAST_TOD);
3178 #endif
3179         spin_unlock_irq(&ugeth->lock);
3180
3181         return NETDEV_TX_OK;
3182 }
3183
3184 static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit)
3185 {
3186         struct sk_buff *skb;
3187         u8 __iomem *bd;
3188         u16 length, howmany = 0;
3189         u32 bd_status;
3190         u8 *bdBuffer;
3191         struct net_device *dev;
3192
3193         ugeth_vdbg("%s: IN", __func__);
3194
3195         dev = ugeth->ndev;
3196
3197         /* collect received buffers */
3198         bd = ugeth->rxBd[rxQ];
3199
3200         bd_status = in_be32((u32 __iomem *)bd);
3201
3202         /* while there are received buffers and BD is full (~R_E) */
3203         while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) {
3204                 bdBuffer = (u8 *) in_be32(&((struct qe_bd __iomem *)bd)->buf);
3205                 length = (u16) ((bd_status & BD_LENGTH_MASK) - 4);
3206                 skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]];
3207
3208                 /* determine whether buffer is first, last, first and last
3209                 (single buffer frame) or middle (not first and not last) */
3210                 if (!skb ||
3211                     (!(bd_status & (R_F | R_L))) ||
3212                     (bd_status & R_ERRORS_FATAL)) {
3213                         if (netif_msg_rx_err(ugeth))
3214                                 ugeth_err("%s, %d: ERROR!!! skb - 0x%08x",
3215                                            __func__, __LINE__, (u32) skb);
3216                         if (skb) {
3217                                 skb->data = skb->head + NET_SKB_PAD;
3218                                 __skb_queue_head(&ugeth->rx_recycle, skb);
3219                         }
3220
3221                         ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL;
3222                         dev->stats.rx_dropped++;
3223                 } else {
3224                         dev->stats.rx_packets++;
3225                         howmany++;
3226
3227                         /* Prep the skb for the packet */
3228                         skb_put(skb, length);
3229
3230                         /* Tell the skb what kind of packet this is */
3231                         skb->protocol = eth_type_trans(skb, ugeth->ndev);
3232
3233                         dev->stats.rx_bytes += length;
3234                         /* Send the packet up the stack */
3235                         netif_receive_skb(skb);
3236                 }
3237
3238                 skb = get_new_skb(ugeth, bd);
3239                 if (!skb) {
3240                         if (netif_msg_rx_err(ugeth))
3241                                 ugeth_warn("%s: No Rx Data Buffer", __func__);
3242                         dev->stats.rx_dropped++;
3243                         break;
3244                 }
3245
3246                 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb;
3247
3248                 /* update to point at the next skb */
3249                 ugeth->skb_currx[rxQ] =
3250                     (ugeth->skb_currx[rxQ] +
3251                      1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]);
3252
3253                 if (bd_status & R_W)
3254                         bd = ugeth->p_rx_bd_ring[rxQ];
3255                 else
3256                         bd += sizeof(struct qe_bd);
3257
3258                 bd_status = in_be32((u32 __iomem *)bd);
3259         }
3260
3261         ugeth->rxBd[rxQ] = bd;
3262         return howmany;
3263 }
3264
3265 static int ucc_geth_tx(struct net_device *dev, u8 txQ)
3266 {
3267         /* Start from the next BD that should be filled */
3268         struct ucc_geth_private *ugeth = netdev_priv(dev);
3269         u8 __iomem *bd;         /* BD pointer */
3270         u32 bd_status;
3271
3272         bd = ugeth->confBd[txQ];
3273         bd_status = in_be32((u32 __iomem *)bd);
3274
3275         /* Normal processing. */
3276         while ((bd_status & T_R) == 0) {
3277                 struct sk_buff *skb;
3278
3279                 /* BD contains already transmitted buffer.   */
3280                 /* Handle the transmitted buffer and release */
3281                 /* the BD to be used with the current frame  */
3282
3283                 if ((bd == ugeth->txBd[txQ]) && (netif_queue_stopped(dev) == 0))
3284                         break;
3285
3286                 dev->stats.tx_packets++;
3287
3288                 skb = ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]];
3289
3290                 if (skb_queue_len(&ugeth->rx_recycle) < RX_BD_RING_LEN &&
3291                              skb_recycle_check(skb,
3292                                     ugeth->ug_info->uf_info.max_rx_buf_length +
3293                                     UCC_GETH_RX_DATA_BUF_ALIGNMENT))
3294                         __skb_queue_head(&ugeth->rx_recycle, skb);
3295                 else
3296                         dev_kfree_skb(skb);
3297
3298                 ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL;
3299                 ugeth->skb_dirtytx[txQ] =
3300                     (ugeth->skb_dirtytx[txQ] +
3301                      1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3302
3303                 /* We freed a buffer, so now we can restart transmission */
3304                 if (netif_queue_stopped(dev))
3305                         netif_wake_queue(dev);
3306
3307                 /* Advance the confirmation BD pointer */
3308                 if (!(bd_status & T_W))
3309                         bd += sizeof(struct qe_bd);
3310                 else
3311                         bd = ugeth->p_tx_bd_ring[txQ];
3312                 bd_status = in_be32((u32 __iomem *)bd);
3313         }
3314         ugeth->confBd[txQ] = bd;
3315         return 0;
3316 }
3317
3318 static int ucc_geth_poll(struct napi_struct *napi, int budget)
3319 {
3320         struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi);
3321         struct ucc_geth_info *ug_info;
3322         int howmany, i;
3323
3324         ug_info = ugeth->ug_info;
3325
3326         /* Tx event processing */
3327         spin_lock(&ugeth->lock);
3328         for (i = 0; i < ug_info->numQueuesTx; i++)
3329                 ucc_geth_tx(ugeth->ndev, i);
3330         spin_unlock(&ugeth->lock);
3331
3332         howmany = 0;
3333         for (i = 0; i < ug_info->numQueuesRx; i++)
3334                 howmany += ucc_geth_rx(ugeth, i, budget - howmany);
3335
3336         if (howmany < budget) {
3337                 napi_complete(napi);
3338                 setbits32(ugeth->uccf->p_uccm, UCCE_RX_EVENTS | UCCE_TX_EVENTS);
3339         }
3340
3341         return howmany;
3342 }
3343
3344 static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
3345 {
3346         struct net_device *dev = info;
3347         struct ucc_geth_private *ugeth = netdev_priv(dev);
3348         struct ucc_fast_private *uccf;
3349         struct ucc_geth_info *ug_info;
3350         register u32 ucce;
3351         register u32 uccm;
3352
3353         ugeth_vdbg("%s: IN", __func__);
3354
3355         uccf = ugeth->uccf;
3356         ug_info = ugeth->ug_info;
3357
3358         /* read and clear events */
3359         ucce = (u32) in_be32(uccf->p_ucce);
3360         uccm = (u32) in_be32(uccf->p_uccm);
3361         ucce &= uccm;
3362         out_be32(uccf->p_ucce, ucce);
3363
3364         /* check for receive events that require processing */
3365         if (ucce & (UCCE_RX_EVENTS | UCCE_TX_EVENTS)) {
3366                 if (napi_schedule_prep(&ugeth->napi)) {
3367                         uccm &= ~(UCCE_RX_EVENTS | UCCE_TX_EVENTS);
3368                         out_be32(uccf->p_uccm, uccm);
3369                         __napi_schedule(&ugeth->napi);
3370                 }
3371         }
3372
3373         /* Errors and other events */
3374         if (ucce & UCCE_OTHER) {
3375                 if (ucce & UCC_GETH_UCCE_BSY)
3376                         dev->stats.rx_errors++;
3377                 if (ucce & UCC_GETH_UCCE_TXE)
3378                         dev->stats.tx_errors++;
3379         }
3380
3381         return IRQ_HANDLED;
3382 }
3383
3384 #ifdef CONFIG_NET_POLL_CONTROLLER
3385 /*
3386  * Polling 'interrupt' - used by things like netconsole to send skbs
3387  * without having to re-enable interrupts. It's not called while
3388  * the interrupt routine is executing.
3389  */
3390 static void ucc_netpoll(struct net_device *dev)
3391 {
3392         struct ucc_geth_private *ugeth = netdev_priv(dev);
3393         int irq = ugeth->ug_info->uf_info.irq;
3394
3395         disable_irq(irq);
3396         ucc_geth_irq_handler(irq, dev);
3397         enable_irq(irq);
3398 }
3399 #endif /* CONFIG_NET_POLL_CONTROLLER */
3400
3401 static int ucc_geth_set_mac_addr(struct net_device *dev, void *p)
3402 {
3403         struct ucc_geth_private *ugeth = netdev_priv(dev);
3404         struct sockaddr *addr = p;
3405
3406         if (!is_valid_ether_addr(addr->sa_data))
3407                 return -EADDRNOTAVAIL;
3408
3409         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3410
3411         /*
3412          * If device is not running, we will set mac addr register
3413          * when opening the device.
3414          */
3415         if (!netif_running(dev))
3416                 return 0;
3417
3418         spin_lock_irq(&ugeth->lock);
3419         init_mac_station_addr_regs(dev->dev_addr[0],
3420                                    dev->dev_addr[1],
3421                                    dev->dev_addr[2],
3422                                    dev->dev_addr[3],
3423                                    dev->dev_addr[4],
3424                                    dev->dev_addr[5],
3425                                    &ugeth->ug_regs->macstnaddr1,
3426                                    &ugeth->ug_regs->macstnaddr2);
3427         spin_unlock_irq(&ugeth->lock);
3428
3429         return 0;
3430 }
3431
3432 /* Called when something needs to use the ethernet device */
3433 /* Returns 0 for success. */
3434 static int ucc_geth_open(struct net_device *dev)
3435 {
3436         struct ucc_geth_private *ugeth = netdev_priv(dev);
3437         int err;
3438
3439         ugeth_vdbg("%s: IN", __func__);
3440
3441         /* Test station address */
3442         if (dev->dev_addr[0] & ENET_GROUP_ADDR) {
3443                 if (netif_msg_ifup(ugeth))
3444                         ugeth_err("%s: Multicast address used for station address"
3445                                   " - is this what you wanted?", __func__);
3446                 return -EINVAL;
3447         }
3448
3449         err = init_phy(dev);
3450         if (err) {
3451                 if (netif_msg_ifup(ugeth))
3452                         ugeth_err("%s: Cannot initialize PHY, aborting.",
3453                                   dev->name);
3454                 return err;
3455         }
3456
3457         err = ucc_struct_init(ugeth);
3458         if (err) {
3459                 if (netif_msg_ifup(ugeth))
3460                         ugeth_err("%s: Cannot configure internal struct, aborting.", dev->name);
3461                 goto out_err_stop;
3462         }
3463
3464         napi_enable(&ugeth->napi);
3465
3466         err = ucc_geth_startup(ugeth);
3467         if (err) {
3468                 if (netif_msg_ifup(ugeth))
3469                         ugeth_err("%s: Cannot configure net device, aborting.",
3470                                   dev->name);
3471                 goto out_err;
3472         }
3473
3474         err = adjust_enet_interface(ugeth);
3475         if (err) {
3476                 if (netif_msg_ifup(ugeth))
3477                         ugeth_err("%s: Cannot configure net device, aborting.",
3478                                   dev->name);
3479                 goto out_err;
3480         }
3481
3482         /*       Set MACSTNADDR1, MACSTNADDR2                */
3483         /* For more details see the hardware spec.           */
3484         init_mac_station_addr_regs(dev->dev_addr[0],
3485                                    dev->dev_addr[1],
3486                                    dev->dev_addr[2],
3487                                    dev->dev_addr[3],
3488                                    dev->dev_addr[4],
3489                                    dev->dev_addr[5],
3490                                    &ugeth->ug_regs->macstnaddr1,
3491                                    &ugeth->ug_regs->macstnaddr2);
3492
3493         phy_start(ugeth->phydev);
3494
3495         err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
3496         if (err) {
3497                 if (netif_msg_ifup(ugeth))
3498                         ugeth_err("%s: Cannot enable net device, aborting.", dev->name);
3499                 goto out_err;
3500         }
3501
3502         err = request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler,
3503                           0, "UCC Geth", dev);
3504         if (err) {
3505                 if (netif_msg_ifup(ugeth))
3506                         ugeth_err("%s: Cannot get IRQ for net device, aborting.",
3507                                   dev->name);
3508                 goto out_err;
3509         }
3510
3511         netif_start_queue(dev);
3512
3513         return err;
3514
3515 out_err:
3516         napi_disable(&ugeth->napi);
3517 out_err_stop:
3518         ucc_geth_stop(ugeth);
3519         return err;
3520 }
3521
3522 /* Stops the kernel queue, and halts the controller */
3523 static int ucc_geth_close(struct net_device *dev)
3524 {
3525         struct ucc_geth_private *ugeth = netdev_priv(dev);
3526
3527         ugeth_vdbg("%s: IN", __func__);
3528
3529         napi_disable(&ugeth->napi);
3530
3531         ucc_geth_stop(ugeth);
3532
3533         free_irq(ugeth->ug_info->uf_info.irq, ugeth->ndev);
3534
3535         netif_stop_queue(dev);
3536
3537         return 0;
3538 }
3539
3540 /* Reopen device. This will reset the MAC and PHY. */
3541 static void ucc_geth_timeout_work(struct work_struct *work)
3542 {
3543         struct ucc_geth_private *ugeth;
3544         struct net_device *dev;
3545
3546         ugeth = container_of(work, struct ucc_geth_private, timeout_work);
3547         dev = ugeth->ndev;
3548
3549         ugeth_vdbg("%s: IN", __func__);
3550
3551         dev->stats.tx_errors++;
3552
3553         ugeth_dump_regs(ugeth);
3554
3555         if (dev->flags & IFF_UP) {
3556                 /*
3557                  * Must reset MAC *and* PHY. This is done by reopening
3558                  * the device.
3559                  */
3560                 ucc_geth_close(dev);
3561                 ucc_geth_open(dev);
3562         }
3563
3564         netif_tx_schedule_all(dev);
3565 }
3566
3567 /*
3568  * ucc_geth_timeout gets called when a packet has not been
3569  * transmitted after a set amount of time.
3570  */
3571 static void ucc_geth_timeout(struct net_device *dev)
3572 {
3573         struct ucc_geth_private *ugeth = netdev_priv(dev);
3574
3575         netif_carrier_off(dev);
3576         schedule_work(&ugeth->timeout_work);
3577 }
3578
3579 static phy_interface_t to_phy_interface(const char *phy_connection_type)
3580 {
3581         if (strcasecmp(phy_connection_type, "mii") == 0)
3582                 return PHY_INTERFACE_MODE_MII;
3583         if (strcasecmp(phy_connection_type, "gmii") == 0)
3584                 return PHY_INTERFACE_MODE_GMII;
3585         if (strcasecmp(phy_connection_type, "tbi") == 0)
3586                 return PHY_INTERFACE_MODE_TBI;
3587         if (strcasecmp(phy_connection_type, "rmii") == 0)
3588                 return PHY_INTERFACE_MODE_RMII;
3589         if (strcasecmp(phy_connection_type, "rgmii") == 0)
3590                 return PHY_INTERFACE_MODE_RGMII;
3591         if (strcasecmp(phy_connection_type, "rgmii-id") == 0)
3592                 return PHY_INTERFACE_MODE_RGMII_ID;
3593         if (strcasecmp(phy_connection_type, "rgmii-txid") == 0)
3594                 return PHY_INTERFACE_MODE_RGMII_TXID;
3595         if (strcasecmp(phy_connection_type, "rgmii-rxid") == 0)
3596                 return PHY_INTERFACE_MODE_RGMII_RXID;
3597         if (strcasecmp(phy_connection_type, "rtbi") == 0)
3598                 return PHY_INTERFACE_MODE_RTBI;
3599         if (strcasecmp(phy_connection_type, "sgmii") == 0)
3600                 return PHY_INTERFACE_MODE_SGMII;
3601
3602         return PHY_INTERFACE_MODE_MII;
3603 }
3604
3605 static const struct net_device_ops ucc_geth_netdev_ops = {
3606         .ndo_open               = ucc_geth_open,
3607         .ndo_stop               = ucc_geth_close,
3608         .ndo_start_xmit         = ucc_geth_start_xmit,
3609         .ndo_validate_addr      = eth_validate_addr,
3610         .ndo_set_mac_address    = ucc_geth_set_mac_addr,
3611         .ndo_change_mtu         = eth_change_mtu,
3612         .ndo_set_multicast_list = ucc_geth_set_multi,
3613         .ndo_tx_timeout         = ucc_geth_timeout,
3614 #ifdef CONFIG_NET_POLL_CONTROLLER
3615         .ndo_poll_controller    = ucc_netpoll,
3616 #endif
3617 };
3618
3619 static int ucc_geth_probe(struct of_device* ofdev, const struct of_device_id *match)
3620 {
3621         struct device *device = &ofdev->dev;
3622         struct device_node *np = ofdev->node;
3623         struct net_device *dev = NULL;
3624         struct ucc_geth_private *ugeth = NULL;
3625         struct ucc_geth_info *ug_info;
3626         struct resource res;
3627         int err, ucc_num, max_speed = 0;
3628         const unsigned int *prop;
3629         const char *sprop;
3630         const void *mac_addr;
3631         phy_interface_t phy_interface;
3632         static const int enet_to_speed[] = {
3633                 SPEED_10, SPEED_10, SPEED_10,
3634                 SPEED_100, SPEED_100, SPEED_100,
3635                 SPEED_1000, SPEED_1000, SPEED_1000, SPEED_1000,
3636         };
3637         static const phy_interface_t enet_to_phy_interface[] = {
3638                 PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_RMII,
3639                 PHY_INTERFACE_MODE_RGMII, PHY_INTERFACE_MODE_MII,
3640                 PHY_INTERFACE_MODE_RMII, PHY_INTERFACE_MODE_RGMII,
3641                 PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_RGMII,
3642                 PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RTBI,
3643                 PHY_INTERFACE_MODE_SGMII,
3644         };
3645
3646         ugeth_vdbg("%s: IN", __func__);
3647
3648         prop = of_get_property(np, "cell-index", NULL);
3649         if (!prop) {
3650                 prop = of_get_property(np, "device-id", NULL);
3651                 if (!prop)
3652                         return -ENODEV;
3653         }
3654
3655         ucc_num = *prop - 1;
3656         if ((ucc_num < 0) || (ucc_num > 7))
3657                 return -ENODEV;
3658
3659         ug_info = &ugeth_info[ucc_num];
3660         if (ug_info == NULL) {
3661                 if (netif_msg_probe(&debug))
3662                         ugeth_err("%s: [%d] Missing additional data!",
3663                                         __func__, ucc_num);
3664                 return -ENODEV;
3665         }
3666
3667         ug_info->uf_info.ucc_num = ucc_num;
3668
3669         sprop = of_get_property(np, "rx-clock-name", NULL);
3670         if (sprop) {
3671                 ug_info->uf_info.rx_clock = qe_clock_source(sprop);
3672                 if ((ug_info->uf_info.rx_clock < QE_CLK_NONE) ||
3673                     (ug_info->uf_info.rx_clock > QE_CLK24)) {
3674                         printk(KERN_ERR
3675                                 "ucc_geth: invalid rx-clock-name property\n");
3676                         return -EINVAL;
3677                 }
3678         } else {
3679                 prop = of_get_property(np, "rx-clock", NULL);
3680                 if (!prop) {
3681                         /* If both rx-clock-name and rx-clock are missing,
3682                            we want to tell people to use rx-clock-name. */
3683                         printk(KERN_ERR
3684                                 "ucc_geth: missing rx-clock-name property\n");
3685                         return -EINVAL;
3686                 }
3687                 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3688                         printk(KERN_ERR
3689                                 "ucc_geth: invalid rx-clock propperty\n");
3690                         return -EINVAL;
3691                 }
3692                 ug_info->uf_info.rx_clock = *prop;
3693         }
3694
3695         sprop = of_get_property(np, "tx-clock-name", NULL);
3696         if (sprop) {
3697                 ug_info->uf_info.tx_clock = qe_clock_source(sprop);
3698                 if ((ug_info->uf_info.tx_clock < QE_CLK_NONE) ||
3699                     (ug_info->uf_info.tx_clock > QE_CLK24)) {
3700                         printk(KERN_ERR
3701                                 "ucc_geth: invalid tx-clock-name property\n");
3702                         return -EINVAL;
3703                 }
3704         } else {
3705                 prop = of_get_property(np, "tx-clock", NULL);
3706                 if (!prop) {
3707                         printk(KERN_ERR
3708                                 "ucc_geth: mising tx-clock-name property\n");
3709                         return -EINVAL;
3710                 }
3711                 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3712                         printk(KERN_ERR
3713                                 "ucc_geth: invalid tx-clock property\n");
3714                         return -EINVAL;
3715                 }
3716                 ug_info->uf_info.tx_clock = *prop;
3717         }
3718
3719         err = of_address_to_resource(np, 0, &res);
3720         if (err)
3721                 return -EINVAL;
3722
3723         ug_info->uf_info.regs = res.start;
3724         ug_info->uf_info.irq = irq_of_parse_and_map(np, 0);
3725
3726         ug_info->phy_node = of_parse_phandle(np, "phy-handle", 0);
3727
3728         /* Find the TBI PHY node.  If it's not there, we don't support SGMII */
3729         ug_info->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
3730
3731         /* get the phy interface type, or default to MII */
3732         prop = of_get_property(np, "phy-connection-type", NULL);
3733         if (!prop) {
3734                 /* handle interface property present in old trees */
3735                 prop = of_get_property(ug_info->phy_node, "interface", NULL);
3736                 if (prop != NULL) {
3737                         phy_interface = enet_to_phy_interface[*prop];
3738                         max_speed = enet_to_speed[*prop];
3739                 } else
3740                         phy_interface = PHY_INTERFACE_MODE_MII;
3741         } else {
3742                 phy_interface = to_phy_interface((const char *)prop);
3743         }
3744
3745         /* get speed, or derive from PHY interface */
3746         if (max_speed == 0)
3747                 switch (phy_interface) {
3748                 case PHY_INTERFACE_MODE_GMII:
3749                 case PHY_INTERFACE_MODE_RGMII:
3750                 case PHY_INTERFACE_MODE_RGMII_ID:
3751                 case PHY_INTERFACE_MODE_RGMII_RXID:
3752                 case PHY_INTERFACE_MODE_RGMII_TXID:
3753                 case PHY_INTERFACE_MODE_TBI:
3754                 case PHY_INTERFACE_MODE_RTBI:
3755                 case PHY_INTERFACE_MODE_SGMII:
3756                         max_speed = SPEED_1000;
3757                         break;
3758                 default:
3759                         max_speed = SPEED_100;
3760                         break;
3761                 }
3762
3763         if (max_speed == SPEED_1000) {
3764                 /* configure muram FIFOs for gigabit operation */
3765                 ug_info->uf_info.urfs = UCC_GETH_URFS_GIGA_INIT;
3766                 ug_info->uf_info.urfet = UCC_GETH_URFET_GIGA_INIT;
3767                 ug_info->uf_info.urfset = UCC_GETH_URFSET_GIGA_INIT;
3768                 ug_info->uf_info.utfs = UCC_GETH_UTFS_GIGA_INIT;
3769                 ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT;
3770                 ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT;
3771                 ug_info->numThreadsTx = UCC_GETH_NUM_OF_THREADS_4;
3772
3773                 /* If QE's snum number is 46 which means we need to support
3774                  * 4 UECs at 1000Base-T simultaneously, we need to allocate
3775                  * more Threads to Rx.
3776                  */
3777                 if (qe_get_num_of_snums() == 46)
3778                         ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_6;
3779                 else
3780                         ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4;
3781         }
3782
3783         if (netif_msg_probe(&debug))
3784                 printk(KERN_INFO "ucc_geth: UCC%1d at 0x%8x (irq = %d) \n",
3785                         ug_info->uf_info.ucc_num + 1, ug_info->uf_info.regs,
3786                         ug_info->uf_info.irq);
3787
3788         /* Create an ethernet device instance */
3789         dev = alloc_etherdev(sizeof(*ugeth));
3790
3791         if (dev == NULL)
3792                 return -ENOMEM;
3793
3794         ugeth = netdev_priv(dev);
3795         spin_lock_init(&ugeth->lock);
3796
3797         /* Create CQs for hash tables */
3798         INIT_LIST_HEAD(&ugeth->group_hash_q);
3799         INIT_LIST_HEAD(&ugeth->ind_hash_q);
3800
3801         dev_set_drvdata(device, dev);
3802
3803         /* Set the dev->base_addr to the gfar reg region */
3804         dev->base_addr = (unsigned long)(ug_info->uf_info.regs);
3805
3806         SET_NETDEV_DEV(dev, device);
3807
3808         /* Fill in the dev structure */
3809         uec_set_ethtool_ops(dev);
3810         dev->netdev_ops = &ucc_geth_netdev_ops;
3811         dev->watchdog_timeo = TX_TIMEOUT;
3812         INIT_WORK(&ugeth->timeout_work, ucc_geth_timeout_work);
3813         netif_napi_add(dev, &ugeth->napi, ucc_geth_poll, 64);
3814         dev->mtu = 1500;
3815
3816         ugeth->msg_enable = netif_msg_init(debug.msg_enable, UGETH_MSG_DEFAULT);
3817         ugeth->phy_interface = phy_interface;
3818         ugeth->max_speed = max_speed;
3819
3820         err = register_netdev(dev);
3821         if (err) {
3822                 if (netif_msg_probe(ugeth))
3823                         ugeth_err("%s: Cannot register net device, aborting.",
3824                                   dev->name);
3825                 free_netdev(dev);
3826                 return err;
3827         }
3828
3829         mac_addr = of_get_mac_address(np);
3830         if (mac_addr)
3831                 memcpy(dev->dev_addr, mac_addr, 6);
3832
3833         ugeth->ug_info = ug_info;
3834         ugeth->dev = device;
3835         ugeth->ndev = dev;
3836         ugeth->node = np;
3837
3838         return 0;
3839 }
3840
3841 static int ucc_geth_remove(struct of_device* ofdev)
3842 {
3843         struct device *device = &ofdev->dev;
3844         struct net_device *dev = dev_get_drvdata(device);
3845         struct ucc_geth_private *ugeth = netdev_priv(dev);
3846
3847         unregister_netdev(dev);
3848         free_netdev(dev);
3849         ucc_geth_memclean(ugeth);
3850         dev_set_drvdata(device, NULL);
3851
3852         return 0;
3853 }
3854
3855 static struct of_device_id ucc_geth_match[] = {
3856         {
3857                 .type = "network",
3858                 .compatible = "ucc_geth",
3859         },
3860         {},
3861 };
3862
3863 MODULE_DEVICE_TABLE(of, ucc_geth_match);
3864
3865 static struct of_platform_driver ucc_geth_driver = {
3866         .name           = DRV_NAME,
3867         .match_table    = ucc_geth_match,
3868         .probe          = ucc_geth_probe,
3869         .remove         = ucc_geth_remove,
3870 };
3871
3872 static int __init ucc_geth_init(void)
3873 {
3874         int i, ret;
3875
3876         if (netif_msg_drv(&debug))
3877                 printk(KERN_INFO "ucc_geth: " DRV_DESC "\n");
3878         for (i = 0; i < 8; i++)
3879                 memcpy(&(ugeth_info[i]), &ugeth_primary_info,
3880                        sizeof(ugeth_primary_info));
3881
3882         ret = of_register_platform_driver(&ucc_geth_driver);
3883
3884         return ret;
3885 }
3886
3887 static void __exit ucc_geth_exit(void)
3888 {
3889         of_unregister_platform_driver(&ucc_geth_driver);
3890 }
3891
3892 module_init(ucc_geth_init);
3893 module_exit(ucc_geth_exit);
3894
3895 MODULE_AUTHOR("Freescale Semiconductor, Inc");
3896 MODULE_DESCRIPTION(DRV_DESC);
3897 MODULE_VERSION(DRV_VERSION);
3898 MODULE_LICENSE("GPL");