drivers/net: const-ify ethtool_ops declarations
[linux-2.6.git] / drivers / net / typhoon.h
1 /* typhoon.h:   chip info for the 3Com 3CR990 family of controllers */
2 /*
3         Written 2002-2003 by David Dillow <dave@thedillows.org>
4
5         This software may be used and distributed according to the terms of
6         the GNU General Public License (GPL), incorporated herein by reference.
7         Drivers based on or derived from this code fall under the GPL and must
8         retain the authorship, copyright and license notice.  This file is not
9         a complete program and may only be used when the entire operating
10         system is licensed under the GPL.
11
12         This software is available on a public web site. It may enable
13         cryptographic capabilities of the 3Com hardware, and may be
14         exported from the United States under License Exception "TSU"
15         pursuant to 15 C.F.R. Section 740.13(e).
16
17         This work was funded by the National Library of Medicine under
18         the Department of Energy project number 0274DD06D1 and NLM project
19         number Y1-LM-2015-01.
20 */
21
22 /* All Typhoon ring positions are specificed in bytes, and point to the
23  * first "clean" entry in the ring -- ie the next entry we use for whatever
24  * purpose.
25  */
26
27 /* The Typhoon basic ring
28  * ringBase:  where this ring lives (our virtual address)
29  * lastWrite: the next entry we'll use
30  */
31 struct basic_ring {
32         u8 *ringBase;
33         u32 lastWrite;
34 };
35
36 /* The Typoon transmit ring -- same as a basic ring, plus:
37  * lastRead:      where we're at in regard to cleaning up the ring
38  * writeRegister: register to use for writing (different for Hi & Lo rings)
39  */
40 struct transmit_ring {
41         u8 *ringBase;
42         u32 lastWrite;
43         u32 lastRead;
44         int writeRegister;
45 };
46
47 /* The host<->Typhoon ring index structure
48  * This indicates the current positions in the rings
49  *
50  * All values must be in little endian format for the 3XP
51  *
52  * rxHiCleared:   entry we've cleared to in the Hi receive ring
53  * rxLoCleared:   entry we've cleared to in the Lo receive ring
54  * rxBuffReady:   next entry we'll put a free buffer in
55  * respCleared:   entry we've cleared to in the response ring
56  *
57  * txLoCleared:   entry the NIC has cleared to in the Lo transmit ring
58  * txHiCleared:   entry the NIC has cleared to in the Hi transmit ring
59  * rxLoReady:     entry the NIC has filled to in the Lo receive ring
60  * rxBuffCleared: entry the NIC has cleared in the free buffer ring
61  * cmdCleared:    entry the NIC has cleared in the command ring
62  * respReady:     entry the NIC has filled to in the response ring
63  * rxHiReady:     entry the NIC has filled to in the Hi receive ring
64  */
65 struct typhoon_indexes {
66         /* The first four are written by the host, and read by the NIC */
67         volatile u32 rxHiCleared;
68         volatile u32 rxLoCleared;
69         volatile u32 rxBuffReady;
70         volatile u32 respCleared;
71
72         /* The remaining are written by the NIC, and read by the host */
73         volatile u32 txLoCleared;
74         volatile u32 txHiCleared;
75         volatile u32 rxLoReady;
76         volatile u32 rxBuffCleared;
77         volatile u32 cmdCleared;
78         volatile u32 respReady;
79         volatile u32 rxHiReady;
80 } __attribute__ ((packed));
81
82 /* The host<->Typhoon interface
83  * Our means of communicating where things are
84  *
85  * All values must be in little endian format for the 3XP
86  *
87  * ringIndex:   64 bit bus address of the index structure
88  * txLoAddr:    64 bit bus address of the Lo transmit ring
89  * txLoSize:    size (in bytes) of the Lo transmit ring
90  * txHi*:       as above for the Hi priority transmit ring
91  * rxLo*:       as above for the Lo priority receive ring
92  * rxBuff*:     as above for the free buffer ring
93  * cmd*:        as above for the command ring
94  * resp*:       as above for the response ring
95  * zeroAddr:    64 bit bus address of a zero word (for DMA)
96  * rxHi*:       as above for the Hi Priority receive ring
97  *
98  * While there is room for 64 bit addresses, current versions of the 3XP
99  * only do 32 bit addresses, so the *Hi for each of the above will always
100  * be zero.
101  */
102 struct typhoon_interface {
103         u32 ringIndex;
104         u32 ringIndexHi;
105         u32 txLoAddr;
106         u32 txLoAddrHi;
107         u32 txLoSize;
108         u32 txHiAddr;
109         u32 txHiAddrHi;
110         u32 txHiSize;
111         u32 rxLoAddr;
112         u32 rxLoAddrHi;
113         u32 rxLoSize;
114         u32 rxBuffAddr;
115         u32 rxBuffAddrHi;
116         u32 rxBuffSize;
117         u32 cmdAddr;
118         u32 cmdAddrHi;
119         u32 cmdSize;
120         u32 respAddr;
121         u32 respAddrHi;
122         u32 respSize;
123         u32 zeroAddr;
124         u32 zeroAddrHi;
125         u32 rxHiAddr;
126         u32 rxHiAddrHi;
127         u32 rxHiSize;
128 } __attribute__ ((packed));
129
130 /* The Typhoon transmit/fragment descriptor
131  *
132  * A packet is described by a packet descriptor, followed by option descriptors,
133  * if any, then one or more fragment descriptors.
134  *
135  * Packet descriptor:
136  * flags:       Descriptor type
137  * len:i        zero, or length of this packet
138  * addr*:       8 bytes of opaque data to the firmware -- for skb pointer
139  * processFlags: Determine offload tasks to perform on this packet.
140  *
141  * Fragment descriptor:
142  * flags:       Descriptor type
143  * len:i        length of this fragment
144  * addr:        low bytes of DMA address for this part of the packet
145  * addrHi:      hi bytes of DMA address for this part of the packet
146  * processFlags: must be zero
147  *
148  * TYPHOON_DESC_VALID is not mentioned in their docs, but their Linux
149  * driver uses it.
150  */
151 struct tx_desc {
152         u8  flags;
153 #define TYPHOON_TYPE_MASK       0x07
154 #define         TYPHOON_FRAG_DESC       0x00
155 #define         TYPHOON_TX_DESC         0x01
156 #define         TYPHOON_CMD_DESC        0x02
157 #define         TYPHOON_OPT_DESC        0x03
158 #define         TYPHOON_RX_DESC         0x04
159 #define         TYPHOON_RESP_DESC       0x05
160 #define TYPHOON_OPT_TYPE_MASK   0xf0
161 #define         TYPHOON_OPT_IPSEC       0x00
162 #define         TYPHOON_OPT_TCP_SEG     0x10
163 #define TYPHOON_CMD_RESPOND     0x40
164 #define TYPHOON_RESP_ERROR      0x40
165 #define TYPHOON_RX_ERROR        0x40
166 #define TYPHOON_DESC_VALID      0x80
167         u8  numDesc;
168         u16 len;
169         u32 addr;
170         u32 addrHi;
171         u32 processFlags;
172 #define TYPHOON_TX_PF_NO_CRC            __constant_cpu_to_le32(0x00000001)
173 #define TYPHOON_TX_PF_IP_CHKSUM         __constant_cpu_to_le32(0x00000002)
174 #define TYPHOON_TX_PF_TCP_CHKSUM        __constant_cpu_to_le32(0x00000004)
175 #define TYPHOON_TX_PF_TCP_SEGMENT       __constant_cpu_to_le32(0x00000008)
176 #define TYPHOON_TX_PF_INSERT_VLAN       __constant_cpu_to_le32(0x00000010)
177 #define TYPHOON_TX_PF_IPSEC             __constant_cpu_to_le32(0x00000020)
178 #define TYPHOON_TX_PF_VLAN_PRIORITY     __constant_cpu_to_le32(0x00000040)
179 #define TYPHOON_TX_PF_UDP_CHKSUM        __constant_cpu_to_le32(0x00000080)
180 #define TYPHOON_TX_PF_PAD_FRAME         __constant_cpu_to_le32(0x00000100)
181 #define TYPHOON_TX_PF_RESERVED          __constant_cpu_to_le32(0x00000e00)
182 #define TYPHOON_TX_PF_VLAN_MASK         __constant_cpu_to_le32(0x0ffff000)
183 #define TYPHOON_TX_PF_INTERNAL          __constant_cpu_to_le32(0xf0000000)
184 #define TYPHOON_TX_PF_VLAN_TAG_SHIFT    12
185 } __attribute__ ((packed));
186
187 /* The TCP Segmentation offload option descriptor
188  *
189  * flags:       descriptor type
190  * numDesc:     must be 1
191  * mss_flags:   bits 0-11 (little endian) are MSS, 12 is first TSO descriptor
192  *                      13 is list TSO descriptor, set both if only one TSO
193  * respAddrLo:  low bytes of address of the bytesTx field of this descriptor
194  * bytesTx:     total number of bytes in this TSO request
195  * status:      0 on completion
196  */
197 struct tcpopt_desc {
198         u8  flags;
199         u8  numDesc;
200         u16 mss_flags;
201 #define TYPHOON_TSO_FIRST               __constant_cpu_to_le16(0x1000)
202 #define TYPHOON_TSO_LAST                __constant_cpu_to_le16(0x2000)
203         u32 respAddrLo;
204         u32 bytesTx;
205         u32 status;
206 } __attribute__ ((packed));
207
208 /* The IPSEC Offload descriptor
209  *
210  * flags:       descriptor type
211  * numDesc:     must be 1
212  * ipsecFlags:  bit 0: 0 -- generate IV, 1 -- use supplied IV
213  * sa1, sa2:    Security Association IDs for this packet
214  * reserved:    set to 0
215  */
216 struct ipsec_desc {
217         u8  flags;
218         u8  numDesc;
219         u16 ipsecFlags;
220 #define TYPHOON_IPSEC_GEN_IV    __constant_cpu_to_le16(0x0000)
221 #define TYPHOON_IPSEC_USE_IV    __constant_cpu_to_le16(0x0001)
222         u32 sa1;
223         u32 sa2;
224         u32 reserved;
225 } __attribute__ ((packed));
226
227 /* The Typhoon receive descriptor (Updated by NIC)
228  *
229  * flags:         Descriptor type, error indication
230  * numDesc:       Always zero
231  * frameLen:      the size of the packet received
232  * addr:          low 32 bytes of the virtual addr passed in for this buffer
233  * addrHi:        high 32 bytes of the virtual addr passed in for this buffer
234  * rxStatus:      Error if set in flags, otherwise result of offload processing
235  * filterResults: results of filtering on packet, not used
236  * ipsecResults:  Results of IPSEC processing
237  * vlanTag:       the 801.2q TCI from the packet
238  */
239 struct rx_desc {
240         u8  flags;
241         u8  numDesc;
242         u16 frameLen;
243         u32 addr;
244         u32 addrHi;
245         u32 rxStatus;
246 #define TYPHOON_RX_ERR_INTERNAL         __constant_cpu_to_le32(0x00000000)
247 #define TYPHOON_RX_ERR_FIFO_UNDERRUN    __constant_cpu_to_le32(0x00000001)
248 #define TYPHOON_RX_ERR_BAD_SSD          __constant_cpu_to_le32(0x00000002)
249 #define TYPHOON_RX_ERR_RUNT             __constant_cpu_to_le32(0x00000003)
250 #define TYPHOON_RX_ERR_CRC              __constant_cpu_to_le32(0x00000004)
251 #define TYPHOON_RX_ERR_OVERSIZE         __constant_cpu_to_le32(0x00000005)
252 #define TYPHOON_RX_ERR_ALIGN            __constant_cpu_to_le32(0x00000006)
253 #define TYPHOON_RX_ERR_DRIBBLE          __constant_cpu_to_le32(0x00000007)
254 #define TYPHOON_RX_PROTO_MASK           __constant_cpu_to_le32(0x00000003)
255 #define TYPHOON_RX_PROTO_UNKNOWN        __constant_cpu_to_le32(0x00000000)
256 #define TYPHOON_RX_PROTO_IP             __constant_cpu_to_le32(0x00000001)
257 #define TYPHOON_RX_PROTO_IPX            __constant_cpu_to_le32(0x00000002)
258 #define TYPHOON_RX_VLAN                 __constant_cpu_to_le32(0x00000004)
259 #define TYPHOON_RX_IP_FRAG              __constant_cpu_to_le32(0x00000008)
260 #define TYPHOON_RX_IPSEC                __constant_cpu_to_le32(0x00000010)
261 #define TYPHOON_RX_IP_CHK_FAIL          __constant_cpu_to_le32(0x00000020)
262 #define TYPHOON_RX_TCP_CHK_FAIL         __constant_cpu_to_le32(0x00000040)
263 #define TYPHOON_RX_UDP_CHK_FAIL         __constant_cpu_to_le32(0x00000080)
264 #define TYPHOON_RX_IP_CHK_GOOD          __constant_cpu_to_le32(0x00000100)
265 #define TYPHOON_RX_TCP_CHK_GOOD         __constant_cpu_to_le32(0x00000200)
266 #define TYPHOON_RX_UDP_CHK_GOOD         __constant_cpu_to_le32(0x00000400)
267         u16 filterResults;
268 #define TYPHOON_RX_FILTER_MASK          __constant_cpu_to_le16(0x7fff)
269 #define TYPHOON_RX_FILTERED             __constant_cpu_to_le16(0x8000)
270         u16 ipsecResults;
271 #define TYPHOON_RX_OUTER_AH_GOOD        __constant_cpu_to_le16(0x0001)
272 #define TYPHOON_RX_OUTER_ESP_GOOD       __constant_cpu_to_le16(0x0002)
273 #define TYPHOON_RX_INNER_AH_GOOD        __constant_cpu_to_le16(0x0004)
274 #define TYPHOON_RX_INNER_ESP_GOOD       __constant_cpu_to_le16(0x0008)
275 #define TYPHOON_RX_OUTER_AH_FAIL        __constant_cpu_to_le16(0x0010)
276 #define TYPHOON_RX_OUTER_ESP_FAIL       __constant_cpu_to_le16(0x0020)
277 #define TYPHOON_RX_INNER_AH_FAIL        __constant_cpu_to_le16(0x0040)
278 #define TYPHOON_RX_INNER_ESP_FAIL       __constant_cpu_to_le16(0x0080)
279 #define TYPHOON_RX_UNKNOWN_SA           __constant_cpu_to_le16(0x0100)
280 #define TYPHOON_RX_ESP_FORMAT_ERR       __constant_cpu_to_le16(0x0200)
281         u32 vlanTag;
282 } __attribute__ ((packed));
283
284 /* The Typhoon free buffer descriptor, used to give a buffer to the NIC
285  *
286  * physAddr:    low 32 bits of the bus address of the buffer
287  * physAddrHi:  high 32 bits of the bus address of the buffer, always zero
288  * virtAddr:    low 32 bits of the skb address
289  * virtAddrHi:  high 32 bits of the skb address, always zero
290  *
291  * the virt* address is basically two 32 bit cookies, just passed back
292  * from the NIC
293  */
294 struct rx_free {
295         u32 physAddr;
296         u32 physAddrHi;
297         u32 virtAddr;
298         u32 virtAddrHi;
299 } __attribute__ ((packed));
300
301 /* The Typhoon command descriptor, used for commands and responses
302  *
303  * flags:   descriptor type
304  * numDesc: number of descriptors following in this command/response,
305  *                              ie, zero for a one descriptor command
306  * cmd:     the command
307  * seqNo:   sequence number (unused)
308  * parm1:   use varies by command
309  * parm2:   use varies by command
310  * parm3:   use varies by command
311  */
312 struct cmd_desc {
313         u8  flags;
314         u8  numDesc;
315         u16 cmd;
316 #define TYPHOON_CMD_TX_ENABLE           __constant_cpu_to_le16(0x0001)
317 #define TYPHOON_CMD_TX_DISABLE          __constant_cpu_to_le16(0x0002)
318 #define TYPHOON_CMD_RX_ENABLE           __constant_cpu_to_le16(0x0003)
319 #define TYPHOON_CMD_RX_DISABLE          __constant_cpu_to_le16(0x0004)
320 #define TYPHOON_CMD_SET_RX_FILTER       __constant_cpu_to_le16(0x0005)
321 #define TYPHOON_CMD_READ_STATS          __constant_cpu_to_le16(0x0007)
322 #define TYPHOON_CMD_XCVR_SELECT         __constant_cpu_to_le16(0x0013)
323 #define TYPHOON_CMD_SET_MAX_PKT_SIZE    __constant_cpu_to_le16(0x001a)
324 #define TYPHOON_CMD_READ_MEDIA_STATUS   __constant_cpu_to_le16(0x001b)
325 #define TYPHOON_CMD_GOTO_SLEEP          __constant_cpu_to_le16(0x0023)
326 #define TYPHOON_CMD_SET_MULTICAST_HASH  __constant_cpu_to_le16(0x0025)
327 #define TYPHOON_CMD_SET_MAC_ADDRESS     __constant_cpu_to_le16(0x0026)
328 #define TYPHOON_CMD_READ_MAC_ADDRESS    __constant_cpu_to_le16(0x0027)
329 #define TYPHOON_CMD_VLAN_TYPE_WRITE     __constant_cpu_to_le16(0x002b)
330 #define TYPHOON_CMD_CREATE_SA           __constant_cpu_to_le16(0x0034)
331 #define TYPHOON_CMD_DELETE_SA           __constant_cpu_to_le16(0x0035)
332 #define TYPHOON_CMD_READ_VERSIONS       __constant_cpu_to_le16(0x0043)
333 #define TYPHOON_CMD_IRQ_COALESCE_CTRL   __constant_cpu_to_le16(0x0045)
334 #define TYPHOON_CMD_ENABLE_WAKE_EVENTS  __constant_cpu_to_le16(0x0049)
335 #define TYPHOON_CMD_SET_OFFLOAD_TASKS   __constant_cpu_to_le16(0x004f)
336 #define TYPHOON_CMD_HELLO_RESP          __constant_cpu_to_le16(0x0057)
337 #define TYPHOON_CMD_HALT                __constant_cpu_to_le16(0x005d)
338 #define TYPHOON_CMD_READ_IPSEC_INFO     __constant_cpu_to_le16(0x005e)
339 #define TYPHOON_CMD_GET_IPSEC_ENABLE    __constant_cpu_to_le16(0x0067)
340 #define TYPHOON_CMD_GET_CMD_LVL         __constant_cpu_to_le16(0x0069)
341         u16 seqNo;
342         u16 parm1;
343         u32 parm2;
344         u32 parm3;
345 } __attribute__ ((packed));
346
347 /* The Typhoon response descriptor, see command descriptor for details
348  */
349 struct resp_desc {
350         u8  flags;
351         u8  numDesc;
352         u16 cmd;
353         u16 seqNo;
354         u16 parm1;
355         u32 parm2;
356         u32 parm3;
357 } __attribute__ ((packed));
358
359 #define INIT_COMMAND_NO_RESPONSE(x, command)                            \
360         do { struct cmd_desc *_ptr = (x);                               \
361                 memset(_ptr, 0, sizeof(struct cmd_desc));               \
362                 _ptr->flags = TYPHOON_CMD_DESC | TYPHOON_DESC_VALID;    \
363                 _ptr->cmd = command;                                    \
364         } while(0)
365
366 /* We set seqNo to 1 if we're expecting a response from this command */
367 #define INIT_COMMAND_WITH_RESPONSE(x, command)                          \
368         do { struct cmd_desc *_ptr = (x);                               \
369                 memset(_ptr, 0, sizeof(struct cmd_desc));               \
370                 _ptr->flags = TYPHOON_CMD_RESPOND | TYPHOON_CMD_DESC;   \
371                 _ptr->flags |= TYPHOON_DESC_VALID;                      \
372                 _ptr->cmd = command;                                    \
373                 _ptr->seqNo = 1;                                        \
374         } while(0)
375
376 /* TYPHOON_CMD_SET_RX_FILTER filter bits (cmd.parm1)
377  */
378 #define TYPHOON_RX_FILTER_DIRECTED      __constant_cpu_to_le16(0x0001)
379 #define TYPHOON_RX_FILTER_ALL_MCAST     __constant_cpu_to_le16(0x0002)
380 #define TYPHOON_RX_FILTER_BROADCAST     __constant_cpu_to_le16(0x0004)
381 #define TYPHOON_RX_FILTER_PROMISCOUS    __constant_cpu_to_le16(0x0008)
382 #define TYPHOON_RX_FILTER_MCAST_HASH    __constant_cpu_to_le16(0x0010)
383
384 /* TYPHOON_CMD_READ_STATS response format
385  */
386 struct stats_resp {
387         u8  flags;
388         u8  numDesc;
389         u16 cmd;
390         u16 seqNo;
391         u16 unused;
392         u32 txPackets;
393         u64 txBytes;
394         u32 txDeferred;
395         u32 txLateCollisions;
396         u32 txCollisions;
397         u32 txCarrierLost;
398         u32 txMultipleCollisions;
399         u32 txExcessiveCollisions;
400         u32 txFifoUnderruns;
401         u32 txMulticastTxOverflows;
402         u32 txFiltered;
403         u32 rxPacketsGood;
404         u64 rxBytesGood;
405         u32 rxFifoOverruns;
406         u32 BadSSD;
407         u32 rxCrcErrors;
408         u32 rxOversized;
409         u32 rxBroadcast;
410         u32 rxMulticast;
411         u32 rxOverflow;
412         u32 rxFiltered;
413         u32 linkStatus;
414 #define TYPHOON_LINK_STAT_MASK          __constant_cpu_to_le32(0x00000001)
415 #define TYPHOON_LINK_GOOD               __constant_cpu_to_le32(0x00000001)
416 #define TYPHOON_LINK_BAD                __constant_cpu_to_le32(0x00000000)
417 #define TYPHOON_LINK_SPEED_MASK         __constant_cpu_to_le32(0x00000002)
418 #define TYPHOON_LINK_100MBPS            __constant_cpu_to_le32(0x00000002)
419 #define TYPHOON_LINK_10MBPS             __constant_cpu_to_le32(0x00000000)
420 #define TYPHOON_LINK_DUPLEX_MASK        __constant_cpu_to_le32(0x00000004)
421 #define TYPHOON_LINK_FULL_DUPLEX        __constant_cpu_to_le32(0x00000004)
422 #define TYPHOON_LINK_HALF_DUPLEX        __constant_cpu_to_le32(0x00000000)
423         u32 unused2;
424         u32 unused3;
425 } __attribute__ ((packed));
426
427 /* TYPHOON_CMD_XCVR_SELECT xcvr values (resp.parm1)
428  */
429 #define TYPHOON_XCVR_10HALF     __constant_cpu_to_le16(0x0000)
430 #define TYPHOON_XCVR_10FULL     __constant_cpu_to_le16(0x0001)
431 #define TYPHOON_XCVR_100HALF    __constant_cpu_to_le16(0x0002)
432 #define TYPHOON_XCVR_100FULL    __constant_cpu_to_le16(0x0003)
433 #define TYPHOON_XCVR_AUTONEG    __constant_cpu_to_le16(0x0004)
434
435 /* TYPHOON_CMD_READ_MEDIA_STATUS (resp.parm1)
436  */
437 #define TYPHOON_MEDIA_STAT_CRC_STRIP_DISABLE    __constant_cpu_to_le16(0x0004)
438 #define TYPHOON_MEDIA_STAT_COLLISION_DETECT     __constant_cpu_to_le16(0x0010)
439 #define TYPHOON_MEDIA_STAT_CARRIER_SENSE        __constant_cpu_to_le16(0x0020)
440 #define TYPHOON_MEDIA_STAT_POLARITY_REV         __constant_cpu_to_le16(0x0400)
441 #define TYPHOON_MEDIA_STAT_NO_LINK              __constant_cpu_to_le16(0x0800)
442
443 /* TYPHOON_CMD_SET_MULTICAST_HASH enable values (cmd.parm1)
444  */
445 #define TYPHOON_MCAST_HASH_DISABLE      __constant_cpu_to_le16(0x0000)
446 #define TYPHOON_MCAST_HASH_ENABLE       __constant_cpu_to_le16(0x0001)
447 #define TYPHOON_MCAST_HASH_SET          __constant_cpu_to_le16(0x0002)
448
449 /* TYPHOON_CMD_CREATE_SA descriptor and settings
450  */
451 struct sa_descriptor {
452         u8  flags;
453         u8  numDesc;
454         u16 cmd;
455         u16 seqNo;
456         u16 mode;
457 #define TYPHOON_SA_MODE_NULL            __constant_cpu_to_le16(0x0000)
458 #define TYPHOON_SA_MODE_AH              __constant_cpu_to_le16(0x0001)
459 #define TYPHOON_SA_MODE_ESP             __constant_cpu_to_le16(0x0002)
460         u8  hashFlags;
461 #define TYPHOON_SA_HASH_ENABLE          0x01
462 #define TYPHOON_SA_HASH_SHA1            0x02
463 #define TYPHOON_SA_HASH_MD5             0x04
464         u8  direction;
465 #define TYPHOON_SA_DIR_RX               0x00
466 #define TYPHOON_SA_DIR_TX               0x01
467         u8  encryptionFlags;
468 #define TYPHOON_SA_ENCRYPT_ENABLE       0x01
469 #define TYPHOON_SA_ENCRYPT_DES          0x02
470 #define TYPHOON_SA_ENCRYPT_3DES         0x00
471 #define TYPHOON_SA_ENCRYPT_3DES_2KEY    0x00
472 #define TYPHOON_SA_ENCRYPT_3DES_3KEY    0x04
473 #define TYPHOON_SA_ENCRYPT_CBC          0x08
474 #define TYPHOON_SA_ENCRYPT_ECB          0x00
475         u8  specifyIndex;
476 #define TYPHOON_SA_SPECIFY_INDEX        0x01
477 #define TYPHOON_SA_GENERATE_INDEX       0x00
478         u32 SPI;
479         u32 destAddr;
480         u32 destMask;
481         u8  integKey[20];
482         u8  confKey[24];
483         u32 index;
484         u32 unused;
485         u32 unused2;
486 } __attribute__ ((packed));
487
488 /* TYPHOON_CMD_SET_OFFLOAD_TASKS bits (cmd.parm2 (Tx) & cmd.parm3 (Rx))
489  * This is all for IPv4.
490  */
491 #define TYPHOON_OFFLOAD_TCP_CHKSUM      __constant_cpu_to_le32(0x00000002)
492 #define TYPHOON_OFFLOAD_UDP_CHKSUM      __constant_cpu_to_le32(0x00000004)
493 #define TYPHOON_OFFLOAD_IP_CHKSUM       __constant_cpu_to_le32(0x00000008)
494 #define TYPHOON_OFFLOAD_IPSEC           __constant_cpu_to_le32(0x00000010)
495 #define TYPHOON_OFFLOAD_BCAST_THROTTLE  __constant_cpu_to_le32(0x00000020)
496 #define TYPHOON_OFFLOAD_DHCP_PREVENT    __constant_cpu_to_le32(0x00000040)
497 #define TYPHOON_OFFLOAD_VLAN            __constant_cpu_to_le32(0x00000080)
498 #define TYPHOON_OFFLOAD_FILTERING       __constant_cpu_to_le32(0x00000100)
499 #define TYPHOON_OFFLOAD_TCP_SEGMENT     __constant_cpu_to_le32(0x00000200)
500
501 /* TYPHOON_CMD_ENABLE_WAKE_EVENTS bits (cmd.parm1)
502  */
503 #define TYPHOON_WAKE_MAGIC_PKT          __constant_cpu_to_le16(0x01)
504 #define TYPHOON_WAKE_LINK_EVENT         __constant_cpu_to_le16(0x02)
505 #define TYPHOON_WAKE_ICMP_ECHO          __constant_cpu_to_le16(0x04)
506 #define TYPHOON_WAKE_ARP                __constant_cpu_to_le16(0x08)
507
508 /* These are used to load the firmware image on the NIC
509  */
510 struct typhoon_file_header {
511         u8  tag[8];
512         u32 version;
513         u32 numSections;
514         u32 startAddr;
515         u32 hmacDigest[5];
516 } __attribute__ ((packed));
517
518 struct typhoon_section_header {
519         u32 len;
520         u16 checksum;
521         u16 reserved;
522         u32 startAddr;
523 } __attribute__ ((packed));
524
525 /* The Typhoon Register offsets
526  */
527 #define TYPHOON_REG_SOFT_RESET                  0x00
528 #define TYPHOON_REG_INTR_STATUS                 0x04
529 #define TYPHOON_REG_INTR_ENABLE                 0x08
530 #define TYPHOON_REG_INTR_MASK                   0x0c
531 #define TYPHOON_REG_SELF_INTERRUPT              0x10
532 #define TYPHOON_REG_HOST2ARM7                   0x14
533 #define TYPHOON_REG_HOST2ARM6                   0x18
534 #define TYPHOON_REG_HOST2ARM5                   0x1c
535 #define TYPHOON_REG_HOST2ARM4                   0x20
536 #define TYPHOON_REG_HOST2ARM3                   0x24
537 #define TYPHOON_REG_HOST2ARM2                   0x28
538 #define TYPHOON_REG_HOST2ARM1                   0x2c
539 #define TYPHOON_REG_HOST2ARM0                   0x30
540 #define TYPHOON_REG_ARM2HOST3                   0x34
541 #define TYPHOON_REG_ARM2HOST2                   0x38
542 #define TYPHOON_REG_ARM2HOST1                   0x3c
543 #define TYPHOON_REG_ARM2HOST0                   0x40
544
545 #define TYPHOON_REG_BOOT_DATA_LO                TYPHOON_REG_HOST2ARM5
546 #define TYPHOON_REG_BOOT_DATA_HI                TYPHOON_REG_HOST2ARM4
547 #define TYPHOON_REG_BOOT_DEST_ADDR              TYPHOON_REG_HOST2ARM3
548 #define TYPHOON_REG_BOOT_CHECKSUM               TYPHOON_REG_HOST2ARM2
549 #define TYPHOON_REG_BOOT_LENGTH                 TYPHOON_REG_HOST2ARM1
550
551 #define TYPHOON_REG_DOWNLOAD_BOOT_ADDR          TYPHOON_REG_HOST2ARM1
552 #define TYPHOON_REG_DOWNLOAD_HMAC_0             TYPHOON_REG_HOST2ARM2
553 #define TYPHOON_REG_DOWNLOAD_HMAC_1             TYPHOON_REG_HOST2ARM3
554 #define TYPHOON_REG_DOWNLOAD_HMAC_2             TYPHOON_REG_HOST2ARM4
555 #define TYPHOON_REG_DOWNLOAD_HMAC_3             TYPHOON_REG_HOST2ARM5
556 #define TYPHOON_REG_DOWNLOAD_HMAC_4             TYPHOON_REG_HOST2ARM6
557
558 #define TYPHOON_REG_BOOT_RECORD_ADDR_HI         TYPHOON_REG_HOST2ARM2
559 #define TYPHOON_REG_BOOT_RECORD_ADDR_LO         TYPHOON_REG_HOST2ARM1
560
561 #define TYPHOON_REG_TX_LO_READY                 TYPHOON_REG_HOST2ARM3
562 #define TYPHOON_REG_CMD_READY                   TYPHOON_REG_HOST2ARM2
563 #define TYPHOON_REG_TX_HI_READY                 TYPHOON_REG_HOST2ARM1
564
565 #define TYPHOON_REG_COMMAND                     TYPHOON_REG_HOST2ARM0
566 #define TYPHOON_REG_HEARTBEAT                   TYPHOON_REG_ARM2HOST3
567 #define TYPHOON_REG_STATUS                      TYPHOON_REG_ARM2HOST0
568
569 /* 3XP Reset values (TYPHOON_REG_SOFT_RESET)
570  */
571 #define TYPHOON_RESET_ALL       0x7f
572 #define TYPHOON_RESET_NONE      0x00
573
574 /* 3XP irq bits (TYPHOON_REG_INTR{STATUS,ENABLE,MASK})
575  *
576  * Some of these came from OpenBSD, as the 3Com docs have it wrong
577  * (INTR_SELF) or don't list it at all (INTR_*_ABORT)
578  *
579  * Enabling irqs on the Heartbeat reg (ArmToHost3) gets you an irq
580  * about every 8ms, so don't do it.
581  */
582 #define TYPHOON_INTR_HOST_INT           0x00000001
583 #define TYPHOON_INTR_ARM2HOST0          0x00000002
584 #define TYPHOON_INTR_ARM2HOST1          0x00000004
585 #define TYPHOON_INTR_ARM2HOST2          0x00000008
586 #define TYPHOON_INTR_ARM2HOST3          0x00000010
587 #define TYPHOON_INTR_DMA0               0x00000020
588 #define TYPHOON_INTR_DMA1               0x00000040
589 #define TYPHOON_INTR_DMA2               0x00000080
590 #define TYPHOON_INTR_DMA3               0x00000100
591 #define TYPHOON_INTR_MASTER_ABORT       0x00000200
592 #define TYPHOON_INTR_TARGET_ABORT       0x00000400
593 #define TYPHOON_INTR_SELF               0x00000800
594 #define TYPHOON_INTR_RESERVED           0xfffff000
595
596 #define TYPHOON_INTR_BOOTCMD            TYPHOON_INTR_ARM2HOST0
597
598 #define TYPHOON_INTR_ENABLE_ALL         0xffffffef
599 #define TYPHOON_INTR_ALL                0xffffffff
600 #define TYPHOON_INTR_NONE               0x00000000
601
602 /* The commands for the 3XP chip (TYPHOON_REG_COMMAND)
603  */
604 #define TYPHOON_BOOTCMD_BOOT                    0x00
605 #define TYPHOON_BOOTCMD_WAKEUP                  0xfa
606 #define TYPHOON_BOOTCMD_DNLD_COMPLETE           0xfb
607 #define TYPHOON_BOOTCMD_SEG_AVAILABLE           0xfc
608 #define TYPHOON_BOOTCMD_RUNTIME_IMAGE           0xfd
609 #define TYPHOON_BOOTCMD_REG_BOOT_RECORD         0xff
610
611 /* 3XP Status values (TYPHOON_REG_STATUS)
612  */
613 #define TYPHOON_STATUS_WAITING_FOR_BOOT         0x07
614 #define TYPHOON_STATUS_SECOND_INIT              0x08
615 #define TYPHOON_STATUS_RUNNING                  0x09
616 #define TYPHOON_STATUS_WAITING_FOR_HOST         0x0d
617 #define TYPHOON_STATUS_WAITING_FOR_SEGMENT      0x10
618 #define TYPHOON_STATUS_SLEEPING                 0x11
619 #define TYPHOON_STATUS_HALTED                   0x14