tg3: Add MDIO bus address assignments
[linux-2.6.git] / drivers / net / tg3.h
1 /* $Id: tg3.h,v 1.37.2.32 2002/03/11 12:18:18 davem Exp $
2  * tg3.h: Definitions for Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  */
8
9 #ifndef _T3_H
10 #define _T3_H
11
12 #define TG3_64BIT_REG_HIGH              0x00UL
13 #define TG3_64BIT_REG_LOW               0x04UL
14
15 /* Descriptor block info. */
16 #define TG3_BDINFO_HOST_ADDR            0x0UL /* 64-bit */
17 #define TG3_BDINFO_MAXLEN_FLAGS         0x8UL /* 32-bit */
18 #define  BDINFO_FLAGS_USE_EXT_RECV       0x00000001 /* ext rx_buffer_desc */
19 #define  BDINFO_FLAGS_DISABLED           0x00000002
20 #define  BDINFO_FLAGS_MAXLEN_MASK        0xffff0000
21 #define  BDINFO_FLAGS_MAXLEN_SHIFT       16
22 #define TG3_BDINFO_NIC_ADDR             0xcUL /* 32-bit */
23 #define TG3_BDINFO_SIZE                 0x10UL
24
25 #define RX_COPY_THRESHOLD               256
26
27 #define TG3_RX_INTERNAL_RING_SZ_5906    32
28
29 #define RX_STD_MAX_SIZE                 1536
30 #define RX_STD_MAX_SIZE_5705            512
31 #define RX_JUMBO_MAX_SIZE               0xdeadbeef /* XXX */
32
33 /* First 256 bytes are a mirror of PCI config space. */
34 #define TG3PCI_VENDOR                   0x00000000
35 #define  TG3PCI_VENDOR_BROADCOM          0x14e4
36 #define TG3PCI_DEVICE                   0x00000002
37 #define  TG3PCI_DEVICE_TIGON3_1          0x1644 /* BCM5700 */
38 #define  TG3PCI_DEVICE_TIGON3_2          0x1645 /* BCM5701 */
39 #define  TG3PCI_DEVICE_TIGON3_3          0x1646 /* BCM5702 */
40 #define  TG3PCI_DEVICE_TIGON3_4          0x1647 /* BCM5703 */
41 #define  TG3PCI_DEVICE_TIGON3_5761S      0x1688
42 #define  TG3PCI_DEVICE_TIGON3_5761SE     0x1689
43 #define  TG3PCI_DEVICE_TIGON3_57780      0x1692
44 #define  TG3PCI_DEVICE_TIGON3_57760      0x1690
45 #define  TG3PCI_DEVICE_TIGON3_57790      0x1694
46 #define  TG3PCI_DEVICE_TIGON3_57788      0x1691
47 #define  TG3PCI_DEVICE_TIGON3_5785_G     0x1699 /* GPHY */
48 #define  TG3PCI_DEVICE_TIGON3_5785_F     0x16a0 /* 10/100 only */
49 #define  TG3PCI_DEVICE_TIGON3_5717C      0x1655
50 #define  TG3PCI_DEVICE_TIGON3_5717S      0x1656
51 #define  TG3PCI_DEVICE_TIGON3_5718C      0x1665
52 #define  TG3PCI_DEVICE_TIGON3_5718S      0x1666
53 /* 0x04 --> 0x64 unused */
54 #define TG3PCI_MSI_DATA                 0x00000064
55 /* 0x66 --> 0x68 unused */
56 #define TG3PCI_MISC_HOST_CTRL           0x00000068
57 #define  MISC_HOST_CTRL_CLEAR_INT        0x00000001
58 #define  MISC_HOST_CTRL_MASK_PCI_INT     0x00000002
59 #define  MISC_HOST_CTRL_BYTE_SWAP        0x00000004
60 #define  MISC_HOST_CTRL_WORD_SWAP        0x00000008
61 #define  MISC_HOST_CTRL_PCISTATE_RW      0x00000010
62 #define  MISC_HOST_CTRL_CLKREG_RW        0x00000020
63 #define  MISC_HOST_CTRL_REGWORD_SWAP     0x00000040
64 #define  MISC_HOST_CTRL_INDIR_ACCESS     0x00000080
65 #define  MISC_HOST_CTRL_IRQ_MASK_MODE    0x00000100
66 #define  MISC_HOST_CTRL_TAGGED_STATUS    0x00000200
67 #define  MISC_HOST_CTRL_CHIPREV          0xffff0000
68 #define  MISC_HOST_CTRL_CHIPREV_SHIFT    16
69 #define  GET_CHIP_REV_ID(MISC_HOST_CTRL) \
70          (((MISC_HOST_CTRL) & MISC_HOST_CTRL_CHIPREV) >> \
71           MISC_HOST_CTRL_CHIPREV_SHIFT)
72 #define  CHIPREV_ID_5700_A0              0x7000
73 #define  CHIPREV_ID_5700_A1              0x7001
74 #define  CHIPREV_ID_5700_B0              0x7100
75 #define  CHIPREV_ID_5700_B1              0x7101
76 #define  CHIPREV_ID_5700_B3              0x7102
77 #define  CHIPREV_ID_5700_ALTIMA          0x7104
78 #define  CHIPREV_ID_5700_C0              0x7200
79 #define  CHIPREV_ID_5701_A0              0x0000
80 #define  CHIPREV_ID_5701_B0              0x0100
81 #define  CHIPREV_ID_5701_B2              0x0102
82 #define  CHIPREV_ID_5701_B5              0x0105
83 #define  CHIPREV_ID_5703_A0              0x1000
84 #define  CHIPREV_ID_5703_A1              0x1001
85 #define  CHIPREV_ID_5703_A2              0x1002
86 #define  CHIPREV_ID_5703_A3              0x1003
87 #define  CHIPREV_ID_5704_A0              0x2000
88 #define  CHIPREV_ID_5704_A1              0x2001
89 #define  CHIPREV_ID_5704_A2              0x2002
90 #define  CHIPREV_ID_5704_A3              0x2003
91 #define  CHIPREV_ID_5705_A0              0x3000
92 #define  CHIPREV_ID_5705_A1              0x3001
93 #define  CHIPREV_ID_5705_A2              0x3002
94 #define  CHIPREV_ID_5705_A3              0x3003
95 #define  CHIPREV_ID_5750_A0              0x4000
96 #define  CHIPREV_ID_5750_A1              0x4001
97 #define  CHIPREV_ID_5750_A3              0x4003
98 #define  CHIPREV_ID_5750_C2              0x4202
99 #define  CHIPREV_ID_5752_A0_HW           0x5000
100 #define  CHIPREV_ID_5752_A0              0x6000
101 #define  CHIPREV_ID_5752_A1              0x6001
102 #define  CHIPREV_ID_5714_A2              0x9002
103 #define  CHIPREV_ID_5906_A1              0xc001
104 #define  CHIPREV_ID_57780_A0             0x57780000
105 #define  CHIPREV_ID_57780_A1             0x57780001
106 #define  GET_ASIC_REV(CHIP_REV_ID)      ((CHIP_REV_ID) >> 12)
107 #define   ASIC_REV_5700                  0x07
108 #define   ASIC_REV_5701                  0x00
109 #define   ASIC_REV_5703                  0x01
110 #define   ASIC_REV_5704                  0x02
111 #define   ASIC_REV_5705                  0x03
112 #define   ASIC_REV_5750                  0x04
113 #define   ASIC_REV_5752                  0x06
114 #define   ASIC_REV_5780                  0x08
115 #define   ASIC_REV_5714                  0x09
116 #define   ASIC_REV_5755                  0x0a
117 #define   ASIC_REV_5787                  0x0b
118 #define   ASIC_REV_5906                  0x0c
119 #define   ASIC_REV_USE_PROD_ID_REG       0x0f
120 #define   ASIC_REV_5784                  0x5784
121 #define   ASIC_REV_5761                  0x5761
122 #define   ASIC_REV_5785                  0x5785
123 #define   ASIC_REV_57780                 0x57780
124 #define   ASIC_REV_5717                  0x5717
125 #define  GET_CHIP_REV(CHIP_REV_ID)      ((CHIP_REV_ID) >> 8)
126 #define   CHIPREV_5700_AX                0x70
127 #define   CHIPREV_5700_BX                0x71
128 #define   CHIPREV_5700_CX                0x72
129 #define   CHIPREV_5701_AX                0x00
130 #define   CHIPREV_5703_AX                0x10
131 #define   CHIPREV_5704_AX                0x20
132 #define   CHIPREV_5704_BX                0x21
133 #define   CHIPREV_5750_AX                0x40
134 #define   CHIPREV_5750_BX                0x41
135 #define   CHIPREV_5784_AX                0x57840
136 #define   CHIPREV_5761_AX                0x57610
137 #define  GET_METAL_REV(CHIP_REV_ID)     ((CHIP_REV_ID) & 0xff)
138 #define   METAL_REV_A0                   0x00
139 #define   METAL_REV_A1                   0x01
140 #define   METAL_REV_B0                   0x00
141 #define   METAL_REV_B1                   0x01
142 #define   METAL_REV_B2                   0x02
143 #define TG3PCI_DMA_RW_CTRL              0x0000006c
144 #define  DMA_RWCTRL_MIN_DMA              0x000000ff
145 #define  DMA_RWCTRL_MIN_DMA_SHIFT        0
146 #define  DMA_RWCTRL_READ_BNDRY_MASK      0x00000700
147 #define  DMA_RWCTRL_READ_BNDRY_DISAB     0x00000000
148 #define  DMA_RWCTRL_READ_BNDRY_16        0x00000100
149 #define  DMA_RWCTRL_READ_BNDRY_128_PCIX  0x00000100
150 #define  DMA_RWCTRL_READ_BNDRY_32        0x00000200
151 #define  DMA_RWCTRL_READ_BNDRY_256_PCIX  0x00000200
152 #define  DMA_RWCTRL_READ_BNDRY_64        0x00000300
153 #define  DMA_RWCTRL_READ_BNDRY_384_PCIX  0x00000300
154 #define  DMA_RWCTRL_READ_BNDRY_128       0x00000400
155 #define  DMA_RWCTRL_READ_BNDRY_256       0x00000500
156 #define  DMA_RWCTRL_READ_BNDRY_512       0x00000600
157 #define  DMA_RWCTRL_READ_BNDRY_1024      0x00000700
158 #define  DMA_RWCTRL_WRITE_BNDRY_MASK     0x00003800
159 #define  DMA_RWCTRL_WRITE_BNDRY_DISAB    0x00000000
160 #define  DMA_RWCTRL_WRITE_BNDRY_16       0x00000800
161 #define  DMA_RWCTRL_WRITE_BNDRY_128_PCIX 0x00000800
162 #define  DMA_RWCTRL_WRITE_BNDRY_32       0x00001000
163 #define  DMA_RWCTRL_WRITE_BNDRY_256_PCIX 0x00001000
164 #define  DMA_RWCTRL_WRITE_BNDRY_64       0x00001800
165 #define  DMA_RWCTRL_WRITE_BNDRY_384_PCIX 0x00001800
166 #define  DMA_RWCTRL_WRITE_BNDRY_128      0x00002000
167 #define  DMA_RWCTRL_WRITE_BNDRY_256      0x00002800
168 #define  DMA_RWCTRL_WRITE_BNDRY_512      0x00003000
169 #define  DMA_RWCTRL_WRITE_BNDRY_1024     0x00003800
170 #define  DMA_RWCTRL_ONE_DMA              0x00004000
171 #define  DMA_RWCTRL_READ_WATER           0x00070000
172 #define  DMA_RWCTRL_READ_WATER_SHIFT     16
173 #define  DMA_RWCTRL_WRITE_WATER          0x00380000
174 #define  DMA_RWCTRL_WRITE_WATER_SHIFT    19
175 #define  DMA_RWCTRL_USE_MEM_READ_MULT    0x00400000
176 #define  DMA_RWCTRL_ASSERT_ALL_BE        0x00800000
177 #define  DMA_RWCTRL_PCI_READ_CMD         0x0f000000
178 #define  DMA_RWCTRL_PCI_READ_CMD_SHIFT   24
179 #define  DMA_RWCTRL_PCI_WRITE_CMD        0xf0000000
180 #define  DMA_RWCTRL_PCI_WRITE_CMD_SHIFT  28
181 #define  DMA_RWCTRL_WRITE_BNDRY_64_PCIE  0x10000000
182 #define  DMA_RWCTRL_WRITE_BNDRY_128_PCIE 0x30000000
183 #define  DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE 0x70000000
184 #define TG3PCI_PCISTATE                 0x00000070
185 #define  PCISTATE_FORCE_RESET            0x00000001
186 #define  PCISTATE_INT_NOT_ACTIVE         0x00000002
187 #define  PCISTATE_CONV_PCI_MODE          0x00000004
188 #define  PCISTATE_BUS_SPEED_HIGH         0x00000008
189 #define  PCISTATE_BUS_32BIT              0x00000010
190 #define  PCISTATE_ROM_ENABLE             0x00000020
191 #define  PCISTATE_ROM_RETRY_ENABLE       0x00000040
192 #define  PCISTATE_FLAT_VIEW              0x00000100
193 #define  PCISTATE_RETRY_SAME_DMA         0x00002000
194 #define  PCISTATE_ALLOW_APE_CTLSPC_WR    0x00010000
195 #define  PCISTATE_ALLOW_APE_SHMEM_WR     0x00020000
196 #define TG3PCI_CLOCK_CTRL               0x00000074
197 #define  CLOCK_CTRL_CORECLK_DISABLE      0x00000200
198 #define  CLOCK_CTRL_RXCLK_DISABLE        0x00000400
199 #define  CLOCK_CTRL_TXCLK_DISABLE        0x00000800
200 #define  CLOCK_CTRL_ALTCLK               0x00001000
201 #define  CLOCK_CTRL_PWRDOWN_PLL133       0x00008000
202 #define  CLOCK_CTRL_44MHZ_CORE           0x00040000
203 #define  CLOCK_CTRL_625_CORE             0x00100000
204 #define  CLOCK_CTRL_FORCE_CLKRUN         0x00200000
205 #define  CLOCK_CTRL_CLKRUN_OENABLE       0x00400000
206 #define  CLOCK_CTRL_DELAY_PCI_GRANT      0x80000000
207 #define TG3PCI_REG_BASE_ADDR            0x00000078
208 #define TG3PCI_MEM_WIN_BASE_ADDR        0x0000007c
209 #define TG3PCI_REG_DATA                 0x00000080
210 #define TG3PCI_MEM_WIN_DATA             0x00000084
211 #define TG3PCI_MISC_LOCAL_CTRL          0x00000090
212 /* 0x94 --> 0x98 unused */
213 #define TG3PCI_STD_RING_PROD_IDX        0x00000098 /* 64-bit */
214 #define TG3PCI_RCV_RET_RING_CON_IDX     0x000000a0 /* 64-bit */
215 /* 0xa0 --> 0xb8 unused */
216 #define TG3PCI_DUAL_MAC_CTRL            0x000000b8
217 #define  DUAL_MAC_CTRL_CH_MASK           0x00000003
218 #define  DUAL_MAC_CTRL_ID                0x00000004
219 #define TG3PCI_PRODID_ASICREV           0x000000bc
220 #define  PROD_ID_ASIC_REV_MASK           0x0fffffff
221 /* 0xc0 --> 0xf4 unused */
222
223 #define TG3PCI_GEN2_PRODID_ASICREV      0x000000f4
224 /* 0xf8 --> 0x200 unused */
225
226 #define TG3_CORR_ERR_STAT               0x00000110
227 #define  TG3_CORR_ERR_STAT_CLEAR        0xffffffff
228 /* 0x114 --> 0x200 unused */
229
230 /* Mailbox registers */
231 #define MAILBOX_INTERRUPT_0             0x00000200 /* 64-bit */
232 #define MAILBOX_INTERRUPT_1             0x00000208 /* 64-bit */
233 #define MAILBOX_INTERRUPT_2             0x00000210 /* 64-bit */
234 #define MAILBOX_INTERRUPT_3             0x00000218 /* 64-bit */
235 #define MAILBOX_GENERAL_0               0x00000220 /* 64-bit */
236 #define MAILBOX_GENERAL_1               0x00000228 /* 64-bit */
237 #define MAILBOX_GENERAL_2               0x00000230 /* 64-bit */
238 #define MAILBOX_GENERAL_3               0x00000238 /* 64-bit */
239 #define MAILBOX_GENERAL_4               0x00000240 /* 64-bit */
240 #define MAILBOX_GENERAL_5               0x00000248 /* 64-bit */
241 #define MAILBOX_GENERAL_6               0x00000250 /* 64-bit */
242 #define MAILBOX_GENERAL_7               0x00000258 /* 64-bit */
243 #define MAILBOX_RELOAD_STAT             0x00000260 /* 64-bit */
244 #define MAILBOX_RCV_STD_PROD_IDX        0x00000268 /* 64-bit */
245 #define MAILBOX_RCV_JUMBO_PROD_IDX      0x00000270 /* 64-bit */
246 #define MAILBOX_RCV_MINI_PROD_IDX       0x00000278 /* 64-bit */
247 #define MAILBOX_RCVRET_CON_IDX_0        0x00000280 /* 64-bit */
248 #define MAILBOX_RCVRET_CON_IDX_1        0x00000288 /* 64-bit */
249 #define MAILBOX_RCVRET_CON_IDX_2        0x00000290 /* 64-bit */
250 #define MAILBOX_RCVRET_CON_IDX_3        0x00000298 /* 64-bit */
251 #define MAILBOX_RCVRET_CON_IDX_4        0x000002a0 /* 64-bit */
252 #define MAILBOX_RCVRET_CON_IDX_5        0x000002a8 /* 64-bit */
253 #define MAILBOX_RCVRET_CON_IDX_6        0x000002b0 /* 64-bit */
254 #define MAILBOX_RCVRET_CON_IDX_7        0x000002b8 /* 64-bit */
255 #define MAILBOX_RCVRET_CON_IDX_8        0x000002c0 /* 64-bit */
256 #define MAILBOX_RCVRET_CON_IDX_9        0x000002c8 /* 64-bit */
257 #define MAILBOX_RCVRET_CON_IDX_10       0x000002d0 /* 64-bit */
258 #define MAILBOX_RCVRET_CON_IDX_11       0x000002d8 /* 64-bit */
259 #define MAILBOX_RCVRET_CON_IDX_12       0x000002e0 /* 64-bit */
260 #define MAILBOX_RCVRET_CON_IDX_13       0x000002e8 /* 64-bit */
261 #define MAILBOX_RCVRET_CON_IDX_14       0x000002f0 /* 64-bit */
262 #define MAILBOX_RCVRET_CON_IDX_15       0x000002f8 /* 64-bit */
263 #define MAILBOX_SNDHOST_PROD_IDX_0      0x00000300 /* 64-bit */
264 #define MAILBOX_SNDHOST_PROD_IDX_1      0x00000308 /* 64-bit */
265 #define MAILBOX_SNDHOST_PROD_IDX_2      0x00000310 /* 64-bit */
266 #define MAILBOX_SNDHOST_PROD_IDX_3      0x00000318 /* 64-bit */
267 #define MAILBOX_SNDHOST_PROD_IDX_4      0x00000320 /* 64-bit */
268 #define MAILBOX_SNDHOST_PROD_IDX_5      0x00000328 /* 64-bit */
269 #define MAILBOX_SNDHOST_PROD_IDX_6      0x00000330 /* 64-bit */
270 #define MAILBOX_SNDHOST_PROD_IDX_7      0x00000338 /* 64-bit */
271 #define MAILBOX_SNDHOST_PROD_IDX_8      0x00000340 /* 64-bit */
272 #define MAILBOX_SNDHOST_PROD_IDX_9      0x00000348 /* 64-bit */
273 #define MAILBOX_SNDHOST_PROD_IDX_10     0x00000350 /* 64-bit */
274 #define MAILBOX_SNDHOST_PROD_IDX_11     0x00000358 /* 64-bit */
275 #define MAILBOX_SNDHOST_PROD_IDX_12     0x00000360 /* 64-bit */
276 #define MAILBOX_SNDHOST_PROD_IDX_13     0x00000368 /* 64-bit */
277 #define MAILBOX_SNDHOST_PROD_IDX_14     0x00000370 /* 64-bit */
278 #define MAILBOX_SNDHOST_PROD_IDX_15     0x00000378 /* 64-bit */
279 #define MAILBOX_SNDNIC_PROD_IDX_0       0x00000380 /* 64-bit */
280 #define MAILBOX_SNDNIC_PROD_IDX_1       0x00000388 /* 64-bit */
281 #define MAILBOX_SNDNIC_PROD_IDX_2       0x00000390 /* 64-bit */
282 #define MAILBOX_SNDNIC_PROD_IDX_3       0x00000398 /* 64-bit */
283 #define MAILBOX_SNDNIC_PROD_IDX_4       0x000003a0 /* 64-bit */
284 #define MAILBOX_SNDNIC_PROD_IDX_5       0x000003a8 /* 64-bit */
285 #define MAILBOX_SNDNIC_PROD_IDX_6       0x000003b0 /* 64-bit */
286 #define MAILBOX_SNDNIC_PROD_IDX_7       0x000003b8 /* 64-bit */
287 #define MAILBOX_SNDNIC_PROD_IDX_8       0x000003c0 /* 64-bit */
288 #define MAILBOX_SNDNIC_PROD_IDX_9       0x000003c8 /* 64-bit */
289 #define MAILBOX_SNDNIC_PROD_IDX_10      0x000003d0 /* 64-bit */
290 #define MAILBOX_SNDNIC_PROD_IDX_11      0x000003d8 /* 64-bit */
291 #define MAILBOX_SNDNIC_PROD_IDX_12      0x000003e0 /* 64-bit */
292 #define MAILBOX_SNDNIC_PROD_IDX_13      0x000003e8 /* 64-bit */
293 #define MAILBOX_SNDNIC_PROD_IDX_14      0x000003f0 /* 64-bit */
294 #define MAILBOX_SNDNIC_PROD_IDX_15      0x000003f8 /* 64-bit */
295
296 /* MAC control registers */
297 #define MAC_MODE                        0x00000400
298 #define  MAC_MODE_RESET                  0x00000001
299 #define  MAC_MODE_HALF_DUPLEX            0x00000002
300 #define  MAC_MODE_PORT_MODE_MASK         0x0000000c
301 #define  MAC_MODE_PORT_MODE_TBI          0x0000000c
302 #define  MAC_MODE_PORT_MODE_GMII         0x00000008
303 #define  MAC_MODE_PORT_MODE_MII          0x00000004
304 #define  MAC_MODE_PORT_MODE_NONE         0x00000000
305 #define  MAC_MODE_PORT_INT_LPBACK        0x00000010
306 #define  MAC_MODE_TAGGED_MAC_CTRL        0x00000080
307 #define  MAC_MODE_TX_BURSTING            0x00000100
308 #define  MAC_MODE_MAX_DEFER              0x00000200
309 #define  MAC_MODE_LINK_POLARITY          0x00000400
310 #define  MAC_MODE_RXSTAT_ENABLE          0x00000800
311 #define  MAC_MODE_RXSTAT_CLEAR           0x00001000
312 #define  MAC_MODE_RXSTAT_FLUSH           0x00002000
313 #define  MAC_MODE_TXSTAT_ENABLE          0x00004000
314 #define  MAC_MODE_TXSTAT_CLEAR           0x00008000
315 #define  MAC_MODE_TXSTAT_FLUSH           0x00010000
316 #define  MAC_MODE_SEND_CONFIGS           0x00020000
317 #define  MAC_MODE_MAGIC_PKT_ENABLE       0x00040000
318 #define  MAC_MODE_ACPI_ENABLE            0x00080000
319 #define  MAC_MODE_MIP_ENABLE             0x00100000
320 #define  MAC_MODE_TDE_ENABLE             0x00200000
321 #define  MAC_MODE_RDE_ENABLE             0x00400000
322 #define  MAC_MODE_FHDE_ENABLE            0x00800000
323 #define  MAC_MODE_KEEP_FRAME_IN_WOL      0x01000000
324 #define  MAC_MODE_APE_RX_EN              0x08000000
325 #define  MAC_MODE_APE_TX_EN              0x10000000
326 #define MAC_STATUS                      0x00000404
327 #define  MAC_STATUS_PCS_SYNCED           0x00000001
328 #define  MAC_STATUS_SIGNAL_DET           0x00000002
329 #define  MAC_STATUS_RCVD_CFG             0x00000004
330 #define  MAC_STATUS_CFG_CHANGED          0x00000008
331 #define  MAC_STATUS_SYNC_CHANGED         0x00000010
332 #define  MAC_STATUS_PORT_DEC_ERR         0x00000400
333 #define  MAC_STATUS_LNKSTATE_CHANGED     0x00001000
334 #define  MAC_STATUS_MI_COMPLETION        0x00400000
335 #define  MAC_STATUS_MI_INTERRUPT         0x00800000
336 #define  MAC_STATUS_AP_ERROR             0x01000000
337 #define  MAC_STATUS_ODI_ERROR            0x02000000
338 #define  MAC_STATUS_RXSTAT_OVERRUN       0x04000000
339 #define  MAC_STATUS_TXSTAT_OVERRUN       0x08000000
340 #define MAC_EVENT                       0x00000408
341 #define  MAC_EVENT_PORT_DECODE_ERR       0x00000400
342 #define  MAC_EVENT_LNKSTATE_CHANGED      0x00001000
343 #define  MAC_EVENT_MI_COMPLETION         0x00400000
344 #define  MAC_EVENT_MI_INTERRUPT          0x00800000
345 #define  MAC_EVENT_AP_ERROR              0x01000000
346 #define  MAC_EVENT_ODI_ERROR             0x02000000
347 #define  MAC_EVENT_RXSTAT_OVERRUN        0x04000000
348 #define  MAC_EVENT_TXSTAT_OVERRUN        0x08000000
349 #define MAC_LED_CTRL                    0x0000040c
350 #define  LED_CTRL_LNKLED_OVERRIDE        0x00000001
351 #define  LED_CTRL_1000MBPS_ON            0x00000002
352 #define  LED_CTRL_100MBPS_ON             0x00000004
353 #define  LED_CTRL_10MBPS_ON              0x00000008
354 #define  LED_CTRL_TRAFFIC_OVERRIDE       0x00000010
355 #define  LED_CTRL_TRAFFIC_BLINK          0x00000020
356 #define  LED_CTRL_TRAFFIC_LED            0x00000040
357 #define  LED_CTRL_1000MBPS_STATUS        0x00000080
358 #define  LED_CTRL_100MBPS_STATUS         0x00000100
359 #define  LED_CTRL_10MBPS_STATUS          0x00000200
360 #define  LED_CTRL_TRAFFIC_STATUS         0x00000400
361 #define  LED_CTRL_MODE_MAC               0x00000000
362 #define  LED_CTRL_MODE_PHY_1             0x00000800
363 #define  LED_CTRL_MODE_PHY_2             0x00001000
364 #define  LED_CTRL_MODE_SHASTA_MAC        0x00002000
365 #define  LED_CTRL_MODE_SHARED            0x00004000
366 #define  LED_CTRL_MODE_COMBO             0x00008000
367 #define  LED_CTRL_BLINK_RATE_MASK        0x7ff80000
368 #define  LED_CTRL_BLINK_RATE_SHIFT       19
369 #define  LED_CTRL_BLINK_PER_OVERRIDE     0x00080000
370 #define  LED_CTRL_BLINK_RATE_OVERRIDE    0x80000000
371 #define MAC_ADDR_0_HIGH                 0x00000410 /* upper 2 bytes */
372 #define MAC_ADDR_0_LOW                  0x00000414 /* lower 4 bytes */
373 #define MAC_ADDR_1_HIGH                 0x00000418 /* upper 2 bytes */
374 #define MAC_ADDR_1_LOW                  0x0000041c /* lower 4 bytes */
375 #define MAC_ADDR_2_HIGH                 0x00000420 /* upper 2 bytes */
376 #define MAC_ADDR_2_LOW                  0x00000424 /* lower 4 bytes */
377 #define MAC_ADDR_3_HIGH                 0x00000428 /* upper 2 bytes */
378 #define MAC_ADDR_3_LOW                  0x0000042c /* lower 4 bytes */
379 #define MAC_ACPI_MBUF_PTR               0x00000430
380 #define MAC_ACPI_LEN_OFFSET             0x00000434
381 #define  ACPI_LENOFF_LEN_MASK            0x0000ffff
382 #define  ACPI_LENOFF_LEN_SHIFT           0
383 #define  ACPI_LENOFF_OFF_MASK            0x0fff0000
384 #define  ACPI_LENOFF_OFF_SHIFT           16
385 #define MAC_TX_BACKOFF_SEED             0x00000438
386 #define  TX_BACKOFF_SEED_MASK            0x000003ff
387 #define MAC_RX_MTU_SIZE                 0x0000043c
388 #define  RX_MTU_SIZE_MASK                0x0000ffff
389 #define MAC_PCS_TEST                    0x00000440
390 #define  PCS_TEST_PATTERN_MASK           0x000fffff
391 #define  PCS_TEST_PATTERN_SHIFT          0
392 #define  PCS_TEST_ENABLE                 0x00100000
393 #define MAC_TX_AUTO_NEG                 0x00000444
394 #define  TX_AUTO_NEG_MASK                0x0000ffff
395 #define  TX_AUTO_NEG_SHIFT               0
396 #define MAC_RX_AUTO_NEG                 0x00000448
397 #define  RX_AUTO_NEG_MASK                0x0000ffff
398 #define  RX_AUTO_NEG_SHIFT               0
399 #define MAC_MI_COM                      0x0000044c
400 #define  MI_COM_CMD_MASK                 0x0c000000
401 #define  MI_COM_CMD_WRITE                0x04000000
402 #define  MI_COM_CMD_READ                 0x08000000
403 #define  MI_COM_READ_FAILED              0x10000000
404 #define  MI_COM_START                    0x20000000
405 #define  MI_COM_BUSY                     0x20000000
406 #define  MI_COM_PHY_ADDR_MASK            0x03e00000
407 #define  MI_COM_PHY_ADDR_SHIFT           21
408 #define  MI_COM_REG_ADDR_MASK            0x001f0000
409 #define  MI_COM_REG_ADDR_SHIFT           16
410 #define  MI_COM_DATA_MASK                0x0000ffff
411 #define MAC_MI_STAT                     0x00000450
412 #define  MAC_MI_STAT_LNKSTAT_ATTN_ENAB   0x00000001
413 #define  MAC_MI_STAT_10MBPS_MODE         0x00000002
414 #define MAC_MI_MODE                     0x00000454
415 #define  MAC_MI_MODE_CLK_10MHZ           0x00000001
416 #define  MAC_MI_MODE_SHORT_PREAMBLE      0x00000002
417 #define  MAC_MI_MODE_AUTO_POLL           0x00000010
418 #define  MAC_MI_MODE_500KHZ_CONST        0x00008000
419 #define  MAC_MI_MODE_BASE                0x000c0000 /* XXX magic values XXX */
420 #define MAC_AUTO_POLL_STATUS            0x00000458
421 #define  MAC_AUTO_POLL_ERROR             0x00000001
422 #define MAC_TX_MODE                     0x0000045c
423 #define  TX_MODE_RESET                   0x00000001
424 #define  TX_MODE_ENABLE                  0x00000002
425 #define  TX_MODE_FLOW_CTRL_ENABLE        0x00000010
426 #define  TX_MODE_BIG_BCKOFF_ENABLE       0x00000020
427 #define  TX_MODE_LONG_PAUSE_ENABLE       0x00000040
428 #define MAC_TX_STATUS                   0x00000460
429 #define  TX_STATUS_XOFFED                0x00000001
430 #define  TX_STATUS_SENT_XOFF             0x00000002
431 #define  TX_STATUS_SENT_XON              0x00000004
432 #define  TX_STATUS_LINK_UP               0x00000008
433 #define  TX_STATUS_ODI_UNDERRUN          0x00000010
434 #define  TX_STATUS_ODI_OVERRUN           0x00000020
435 #define MAC_TX_LENGTHS                  0x00000464
436 #define  TX_LENGTHS_SLOT_TIME_MASK       0x000000ff
437 #define  TX_LENGTHS_SLOT_TIME_SHIFT      0
438 #define  TX_LENGTHS_IPG_MASK             0x00000f00
439 #define  TX_LENGTHS_IPG_SHIFT            8
440 #define  TX_LENGTHS_IPG_CRS_MASK         0x00003000
441 #define  TX_LENGTHS_IPG_CRS_SHIFT        12
442 #define MAC_RX_MODE                     0x00000468
443 #define  RX_MODE_RESET                   0x00000001
444 #define  RX_MODE_ENABLE                  0x00000002
445 #define  RX_MODE_FLOW_CTRL_ENABLE        0x00000004
446 #define  RX_MODE_KEEP_MAC_CTRL           0x00000008
447 #define  RX_MODE_KEEP_PAUSE              0x00000010
448 #define  RX_MODE_ACCEPT_OVERSIZED        0x00000020
449 #define  RX_MODE_ACCEPT_RUNTS            0x00000040
450 #define  RX_MODE_LEN_CHECK               0x00000080
451 #define  RX_MODE_PROMISC                 0x00000100
452 #define  RX_MODE_NO_CRC_CHECK            0x00000200
453 #define  RX_MODE_KEEP_VLAN_TAG           0x00000400
454 #define  RX_MODE_RSS_IPV4_HASH_EN        0x00010000
455 #define  RX_MODE_RSS_TCP_IPV4_HASH_EN    0x00020000
456 #define  RX_MODE_RSS_IPV6_HASH_EN        0x00040000
457 #define  RX_MODE_RSS_TCP_IPV6_HASH_EN    0x00080000
458 #define  RX_MODE_RSS_ITBL_HASH_BITS_7    0x00700000
459 #define  RX_MODE_RSS_ENABLE              0x00800000
460 #define  RX_MODE_IPV6_CSUM_ENABLE        0x01000000
461 #define MAC_RX_STATUS                   0x0000046c
462 #define  RX_STATUS_REMOTE_TX_XOFFED      0x00000001
463 #define  RX_STATUS_XOFF_RCVD             0x00000002
464 #define  RX_STATUS_XON_RCVD              0x00000004
465 #define MAC_HASH_REG_0                  0x00000470
466 #define MAC_HASH_REG_1                  0x00000474
467 #define MAC_HASH_REG_2                  0x00000478
468 #define MAC_HASH_REG_3                  0x0000047c
469 #define MAC_RCV_RULE_0                  0x00000480
470 #define MAC_RCV_VALUE_0                 0x00000484
471 #define MAC_RCV_RULE_1                  0x00000488
472 #define MAC_RCV_VALUE_1                 0x0000048c
473 #define MAC_RCV_RULE_2                  0x00000490
474 #define MAC_RCV_VALUE_2                 0x00000494
475 #define MAC_RCV_RULE_3                  0x00000498
476 #define MAC_RCV_VALUE_3                 0x0000049c
477 #define MAC_RCV_RULE_4                  0x000004a0
478 #define MAC_RCV_VALUE_4                 0x000004a4
479 #define MAC_RCV_RULE_5                  0x000004a8
480 #define MAC_RCV_VALUE_5                 0x000004ac
481 #define MAC_RCV_RULE_6                  0x000004b0
482 #define MAC_RCV_VALUE_6                 0x000004b4
483 #define MAC_RCV_RULE_7                  0x000004b8
484 #define MAC_RCV_VALUE_7                 0x000004bc
485 #define MAC_RCV_RULE_8                  0x000004c0
486 #define MAC_RCV_VALUE_8                 0x000004c4
487 #define MAC_RCV_RULE_9                  0x000004c8
488 #define MAC_RCV_VALUE_9                 0x000004cc
489 #define MAC_RCV_RULE_10                 0x000004d0
490 #define MAC_RCV_VALUE_10                0x000004d4
491 #define MAC_RCV_RULE_11                 0x000004d8
492 #define MAC_RCV_VALUE_11                0x000004dc
493 #define MAC_RCV_RULE_12                 0x000004e0
494 #define MAC_RCV_VALUE_12                0x000004e4
495 #define MAC_RCV_RULE_13                 0x000004e8
496 #define MAC_RCV_VALUE_13                0x000004ec
497 #define MAC_RCV_RULE_14                 0x000004f0
498 #define MAC_RCV_VALUE_14                0x000004f4
499 #define MAC_RCV_RULE_15                 0x000004f8
500 #define MAC_RCV_VALUE_15                0x000004fc
501 #define  RCV_RULE_DISABLE_MASK           0x7fffffff
502 #define MAC_RCV_RULE_CFG                0x00000500
503 #define  RCV_RULE_CFG_DEFAULT_CLASS     0x00000008
504 #define MAC_LOW_WMARK_MAX_RX_FRAME      0x00000504
505 /* 0x508 --> 0x520 unused */
506 #define MAC_HASHREGU_0                  0x00000520
507 #define MAC_HASHREGU_1                  0x00000524
508 #define MAC_HASHREGU_2                  0x00000528
509 #define MAC_HASHREGU_3                  0x0000052c
510 #define MAC_EXTADDR_0_HIGH              0x00000530
511 #define MAC_EXTADDR_0_LOW               0x00000534
512 #define MAC_EXTADDR_1_HIGH              0x00000538
513 #define MAC_EXTADDR_1_LOW               0x0000053c
514 #define MAC_EXTADDR_2_HIGH              0x00000540
515 #define MAC_EXTADDR_2_LOW               0x00000544
516 #define MAC_EXTADDR_3_HIGH              0x00000548
517 #define MAC_EXTADDR_3_LOW               0x0000054c
518 #define MAC_EXTADDR_4_HIGH              0x00000550
519 #define MAC_EXTADDR_4_LOW               0x00000554
520 #define MAC_EXTADDR_5_HIGH              0x00000558
521 #define MAC_EXTADDR_5_LOW               0x0000055c
522 #define MAC_EXTADDR_6_HIGH              0x00000560
523 #define MAC_EXTADDR_6_LOW               0x00000564
524 #define MAC_EXTADDR_7_HIGH              0x00000568
525 #define MAC_EXTADDR_7_LOW               0x0000056c
526 #define MAC_EXTADDR_8_HIGH              0x00000570
527 #define MAC_EXTADDR_8_LOW               0x00000574
528 #define MAC_EXTADDR_9_HIGH              0x00000578
529 #define MAC_EXTADDR_9_LOW               0x0000057c
530 #define MAC_EXTADDR_10_HIGH             0x00000580
531 #define MAC_EXTADDR_10_LOW              0x00000584
532 #define MAC_EXTADDR_11_HIGH             0x00000588
533 #define MAC_EXTADDR_11_LOW              0x0000058c
534 #define MAC_SERDES_CFG                  0x00000590
535 #define  MAC_SERDES_CFG_EDGE_SELECT      0x00001000
536 #define MAC_SERDES_STAT                 0x00000594
537 /* 0x598 --> 0x5a0 unused */
538 #define MAC_PHYCFG1                     0x000005a0
539 #define  MAC_PHYCFG1_RGMII_INT           0x00000001
540 #define  MAC_PHYCFG1_RXCLK_TO_MASK       0x00001ff0
541 #define  MAC_PHYCFG1_RXCLK_TIMEOUT       0x00001000
542 #define  MAC_PHYCFG1_TXCLK_TO_MASK       0x01ff0000
543 #define  MAC_PHYCFG1_TXCLK_TIMEOUT       0x01000000
544 #define  MAC_PHYCFG1_RGMII_EXT_RX_DEC    0x02000000
545 #define  MAC_PHYCFG1_RGMII_SND_STAT_EN   0x04000000
546 #define  MAC_PHYCFG1_TXC_DRV             0x20000000
547 #define MAC_PHYCFG2                     0x000005a4
548 #define  MAC_PHYCFG2_INBAND_ENABLE       0x00000001
549 #define  MAC_PHYCFG2_EMODE_MASK_MASK     0x000001c0
550 #define  MAC_PHYCFG2_EMODE_MASK_AC131    0x000000c0
551 #define  MAC_PHYCFG2_EMODE_MASK_50610    0x00000100
552 #define  MAC_PHYCFG2_EMODE_MASK_RT8211   0x00000000
553 #define  MAC_PHYCFG2_EMODE_MASK_RT8201   0x000001c0
554 #define  MAC_PHYCFG2_EMODE_COMP_MASK     0x00000e00
555 #define  MAC_PHYCFG2_EMODE_COMP_AC131    0x00000600
556 #define  MAC_PHYCFG2_EMODE_COMP_50610    0x00000400
557 #define  MAC_PHYCFG2_EMODE_COMP_RT8211   0x00000800
558 #define  MAC_PHYCFG2_EMODE_COMP_RT8201   0x00000000
559 #define  MAC_PHYCFG2_FMODE_MASK_MASK     0x00007000
560 #define  MAC_PHYCFG2_FMODE_MASK_AC131    0x00006000
561 #define  MAC_PHYCFG2_FMODE_MASK_50610    0x00004000
562 #define  MAC_PHYCFG2_FMODE_MASK_RT8211   0x00000000
563 #define  MAC_PHYCFG2_FMODE_MASK_RT8201   0x00007000
564 #define  MAC_PHYCFG2_FMODE_COMP_MASK     0x00038000
565 #define  MAC_PHYCFG2_FMODE_COMP_AC131    0x00030000
566 #define  MAC_PHYCFG2_FMODE_COMP_50610    0x00008000
567 #define  MAC_PHYCFG2_FMODE_COMP_RT8211   0x00038000
568 #define  MAC_PHYCFG2_FMODE_COMP_RT8201   0x00000000
569 #define  MAC_PHYCFG2_GMODE_MASK_MASK     0x001c0000
570 #define  MAC_PHYCFG2_GMODE_MASK_AC131    0x001c0000
571 #define  MAC_PHYCFG2_GMODE_MASK_50610    0x00100000
572 #define  MAC_PHYCFG2_GMODE_MASK_RT8211   0x00000000
573 #define  MAC_PHYCFG2_GMODE_MASK_RT8201   0x001c0000
574 #define  MAC_PHYCFG2_GMODE_COMP_MASK     0x00e00000
575 #define  MAC_PHYCFG2_GMODE_COMP_AC131    0x00e00000
576 #define  MAC_PHYCFG2_GMODE_COMP_50610    0x00000000
577 #define  MAC_PHYCFG2_GMODE_COMP_RT8211   0x00200000
578 #define  MAC_PHYCFG2_GMODE_COMP_RT8201   0x00000000
579 #define  MAC_PHYCFG2_ACT_MASK_MASK       0x03000000
580 #define  MAC_PHYCFG2_ACT_MASK_AC131      0x03000000
581 #define  MAC_PHYCFG2_ACT_MASK_50610      0x01000000
582 #define  MAC_PHYCFG2_ACT_MASK_RT8211     0x03000000
583 #define  MAC_PHYCFG2_ACT_MASK_RT8201     0x01000000
584 #define  MAC_PHYCFG2_ACT_COMP_MASK       0x0c000000
585 #define  MAC_PHYCFG2_ACT_COMP_AC131      0x00000000
586 #define  MAC_PHYCFG2_ACT_COMP_50610      0x00000000
587 #define  MAC_PHYCFG2_ACT_COMP_RT8211     0x00000000
588 #define  MAC_PHYCFG2_ACT_COMP_RT8201     0x08000000
589 #define  MAC_PHYCFG2_QUAL_MASK_MASK      0x30000000
590 #define  MAC_PHYCFG2_QUAL_MASK_AC131     0x30000000
591 #define  MAC_PHYCFG2_QUAL_MASK_50610     0x30000000
592 #define  MAC_PHYCFG2_QUAL_MASK_RT8211    0x30000000
593 #define  MAC_PHYCFG2_QUAL_MASK_RT8201    0x30000000
594 #define  MAC_PHYCFG2_QUAL_COMP_MASK      0xc0000000
595 #define  MAC_PHYCFG2_QUAL_COMP_AC131     0x00000000
596 #define  MAC_PHYCFG2_QUAL_COMP_50610     0x00000000
597 #define  MAC_PHYCFG2_QUAL_COMP_RT8211    0x00000000
598 #define  MAC_PHYCFG2_QUAL_COMP_RT8201    0x00000000
599 #define MAC_PHYCFG2_50610_LED_MODES \
600         (MAC_PHYCFG2_EMODE_MASK_50610 | \
601          MAC_PHYCFG2_EMODE_COMP_50610 | \
602          MAC_PHYCFG2_FMODE_MASK_50610 | \
603          MAC_PHYCFG2_FMODE_COMP_50610 | \
604          MAC_PHYCFG2_GMODE_MASK_50610 | \
605          MAC_PHYCFG2_GMODE_COMP_50610 | \
606          MAC_PHYCFG2_ACT_MASK_50610 | \
607          MAC_PHYCFG2_ACT_COMP_50610 | \
608          MAC_PHYCFG2_QUAL_MASK_50610 | \
609          MAC_PHYCFG2_QUAL_COMP_50610)
610 #define MAC_PHYCFG2_AC131_LED_MODES \
611         (MAC_PHYCFG2_EMODE_MASK_AC131 | \
612          MAC_PHYCFG2_EMODE_COMP_AC131 | \
613          MAC_PHYCFG2_FMODE_MASK_AC131 | \
614          MAC_PHYCFG2_FMODE_COMP_AC131 | \
615          MAC_PHYCFG2_GMODE_MASK_AC131 | \
616          MAC_PHYCFG2_GMODE_COMP_AC131 | \
617          MAC_PHYCFG2_ACT_MASK_AC131 | \
618          MAC_PHYCFG2_ACT_COMP_AC131 | \
619          MAC_PHYCFG2_QUAL_MASK_AC131 | \
620          MAC_PHYCFG2_QUAL_COMP_AC131)
621 #define MAC_PHYCFG2_RTL8211C_LED_MODES \
622         (MAC_PHYCFG2_EMODE_MASK_RT8211 | \
623          MAC_PHYCFG2_EMODE_COMP_RT8211 | \
624          MAC_PHYCFG2_FMODE_MASK_RT8211 | \
625          MAC_PHYCFG2_FMODE_COMP_RT8211 | \
626          MAC_PHYCFG2_GMODE_MASK_RT8211 | \
627          MAC_PHYCFG2_GMODE_COMP_RT8211 | \
628          MAC_PHYCFG2_ACT_MASK_RT8211 | \
629          MAC_PHYCFG2_ACT_COMP_RT8211 | \
630          MAC_PHYCFG2_QUAL_MASK_RT8211 | \
631          MAC_PHYCFG2_QUAL_COMP_RT8211)
632 #define MAC_PHYCFG2_RTL8201E_LED_MODES \
633         (MAC_PHYCFG2_EMODE_MASK_RT8201 | \
634          MAC_PHYCFG2_EMODE_COMP_RT8201 | \
635          MAC_PHYCFG2_FMODE_MASK_RT8201 | \
636          MAC_PHYCFG2_FMODE_COMP_RT8201 | \
637          MAC_PHYCFG2_GMODE_MASK_RT8201 | \
638          MAC_PHYCFG2_GMODE_COMP_RT8201 | \
639          MAC_PHYCFG2_ACT_MASK_RT8201 | \
640          MAC_PHYCFG2_ACT_COMP_RT8201 | \
641          MAC_PHYCFG2_QUAL_MASK_RT8201 | \
642          MAC_PHYCFG2_QUAL_COMP_RT8201)
643 #define MAC_EXT_RGMII_MODE              0x000005a8
644 #define  MAC_RGMII_MODE_TX_ENABLE        0x00000001
645 #define  MAC_RGMII_MODE_TX_LOWPWR        0x00000002
646 #define  MAC_RGMII_MODE_TX_RESET         0x00000004
647 #define  MAC_RGMII_MODE_RX_INT_B         0x00000100
648 #define  MAC_RGMII_MODE_RX_QUALITY       0x00000200
649 #define  MAC_RGMII_MODE_RX_ACTIVITY      0x00000400
650 #define  MAC_RGMII_MODE_RX_ENG_DET       0x00000800
651 /* 0x5ac --> 0x5b0 unused */
652 #define SERDES_RX_CTRL                  0x000005b0      /* 5780/5714 only */
653 #define  SERDES_RX_SIG_DETECT            0x00000400
654 #define SG_DIG_CTRL                     0x000005b0
655 #define  SG_DIG_USING_HW_AUTONEG         0x80000000
656 #define  SG_DIG_SOFT_RESET               0x40000000
657 #define  SG_DIG_DISABLE_LINKRDY          0x20000000
658 #define  SG_DIG_CRC16_CLEAR_N            0x01000000
659 #define  SG_DIG_EN10B                    0x00800000
660 #define  SG_DIG_CLEAR_STATUS             0x00400000
661 #define  SG_DIG_LOCAL_DUPLEX_STATUS      0x00200000
662 #define  SG_DIG_LOCAL_LINK_STATUS        0x00100000
663 #define  SG_DIG_SPEED_STATUS_MASK        0x000c0000
664 #define  SG_DIG_SPEED_STATUS_SHIFT       18
665 #define  SG_DIG_JUMBO_PACKET_DISABLE     0x00020000
666 #define  SG_DIG_RESTART_AUTONEG          0x00010000
667 #define  SG_DIG_FIBER_MODE               0x00008000
668 #define  SG_DIG_REMOTE_FAULT_MASK        0x00006000
669 #define  SG_DIG_PAUSE_MASK               0x00001800
670 #define  SG_DIG_PAUSE_CAP                0x00000800
671 #define  SG_DIG_ASYM_PAUSE               0x00001000
672 #define  SG_DIG_GBIC_ENABLE              0x00000400
673 #define  SG_DIG_CHECK_END_ENABLE         0x00000200
674 #define  SG_DIG_SGMII_AUTONEG_TIMER      0x00000100
675 #define  SG_DIG_CLOCK_PHASE_SELECT       0x00000080
676 #define  SG_DIG_GMII_INPUT_SELECT        0x00000040
677 #define  SG_DIG_MRADV_CRC16_SELECT       0x00000020
678 #define  SG_DIG_COMMA_DETECT_ENABLE      0x00000010
679 #define  SG_DIG_AUTONEG_TIMER_REDUCE     0x00000008
680 #define  SG_DIG_AUTONEG_LOW_ENABLE       0x00000004
681 #define  SG_DIG_REMOTE_LOOPBACK          0x00000002
682 #define  SG_DIG_LOOPBACK                 0x00000001
683 #define  SG_DIG_COMMON_SETUP (SG_DIG_CRC16_CLEAR_N | \
684                               SG_DIG_LOCAL_DUPLEX_STATUS | \
685                               SG_DIG_LOCAL_LINK_STATUS | \
686                               (0x2 << SG_DIG_SPEED_STATUS_SHIFT) | \
687                               SG_DIG_FIBER_MODE | SG_DIG_GBIC_ENABLE)
688 #define SG_DIG_STATUS                   0x000005b4
689 #define  SG_DIG_CRC16_BUS_MASK           0xffff0000
690 #define  SG_DIG_PARTNER_FAULT_MASK       0x00600000 /* If !MRADV_CRC16_SELECT */
691 #define  SG_DIG_PARTNER_ASYM_PAUSE       0x00100000 /* If !MRADV_CRC16_SELECT */
692 #define  SG_DIG_PARTNER_PAUSE_CAPABLE    0x00080000 /* If !MRADV_CRC16_SELECT */
693 #define  SG_DIG_PARTNER_HALF_DUPLEX      0x00040000 /* If !MRADV_CRC16_SELECT */
694 #define  SG_DIG_PARTNER_FULL_DUPLEX      0x00020000 /* If !MRADV_CRC16_SELECT */
695 #define  SG_DIG_PARTNER_NEXT_PAGE        0x00010000 /* If !MRADV_CRC16_SELECT */
696 #define  SG_DIG_AUTONEG_STATE_MASK       0x00000ff0
697 #define  SG_DIG_IS_SERDES                0x00000100
698 #define  SG_DIG_COMMA_DETECTOR           0x00000008
699 #define  SG_DIG_MAC_ACK_STATUS           0x00000004
700 #define  SG_DIG_AUTONEG_COMPLETE         0x00000002
701 #define  SG_DIG_AUTONEG_ERROR            0x00000001
702 /* 0x5b8 --> 0x600 unused */
703 #define MAC_TX_MAC_STATE_BASE           0x00000600 /* 16 bytes */
704 #define MAC_RX_MAC_STATE_BASE           0x00000610 /* 20 bytes */
705 /* 0x624 --> 0x670 unused */
706
707 #define MAC_RSS_INDIR_TBL_0             0x00000630
708
709 #define MAC_RSS_HASH_KEY_0              0x00000670
710 #define MAC_RSS_HASH_KEY_1              0x00000674
711 #define MAC_RSS_HASH_KEY_2              0x00000678
712 #define MAC_RSS_HASH_KEY_3              0x0000067c
713 #define MAC_RSS_HASH_KEY_4              0x00000680
714 #define MAC_RSS_HASH_KEY_5              0x00000684
715 #define MAC_RSS_HASH_KEY_6              0x00000688
716 #define MAC_RSS_HASH_KEY_7              0x0000068c
717 #define MAC_RSS_HASH_KEY_8              0x00000690
718 #define MAC_RSS_HASH_KEY_9              0x00000694
719 /* 0x698 --> 0x800 unused */
720
721 #define MAC_TX_STATS_OCTETS             0x00000800
722 #define MAC_TX_STATS_RESV1              0x00000804
723 #define MAC_TX_STATS_COLLISIONS         0x00000808
724 #define MAC_TX_STATS_XON_SENT           0x0000080c
725 #define MAC_TX_STATS_XOFF_SENT          0x00000810
726 #define MAC_TX_STATS_RESV2              0x00000814
727 #define MAC_TX_STATS_MAC_ERRORS         0x00000818
728 #define MAC_TX_STATS_SINGLE_COLLISIONS  0x0000081c
729 #define MAC_TX_STATS_MULT_COLLISIONS    0x00000820
730 #define MAC_TX_STATS_DEFERRED           0x00000824
731 #define MAC_TX_STATS_RESV3              0x00000828
732 #define MAC_TX_STATS_EXCESSIVE_COL      0x0000082c
733 #define MAC_TX_STATS_LATE_COL           0x00000830
734 #define MAC_TX_STATS_RESV4_1            0x00000834
735 #define MAC_TX_STATS_RESV4_2            0x00000838
736 #define MAC_TX_STATS_RESV4_3            0x0000083c
737 #define MAC_TX_STATS_RESV4_4            0x00000840
738 #define MAC_TX_STATS_RESV4_5            0x00000844
739 #define MAC_TX_STATS_RESV4_6            0x00000848
740 #define MAC_TX_STATS_RESV4_7            0x0000084c
741 #define MAC_TX_STATS_RESV4_8            0x00000850
742 #define MAC_TX_STATS_RESV4_9            0x00000854
743 #define MAC_TX_STATS_RESV4_10           0x00000858
744 #define MAC_TX_STATS_RESV4_11           0x0000085c
745 #define MAC_TX_STATS_RESV4_12           0x00000860
746 #define MAC_TX_STATS_RESV4_13           0x00000864
747 #define MAC_TX_STATS_RESV4_14           0x00000868
748 #define MAC_TX_STATS_UCAST              0x0000086c
749 #define MAC_TX_STATS_MCAST              0x00000870
750 #define MAC_TX_STATS_BCAST              0x00000874
751 #define MAC_TX_STATS_RESV5_1            0x00000878
752 #define MAC_TX_STATS_RESV5_2            0x0000087c
753 #define MAC_RX_STATS_OCTETS             0x00000880
754 #define MAC_RX_STATS_RESV1              0x00000884
755 #define MAC_RX_STATS_FRAGMENTS          0x00000888
756 #define MAC_RX_STATS_UCAST              0x0000088c
757 #define MAC_RX_STATS_MCAST              0x00000890
758 #define MAC_RX_STATS_BCAST              0x00000894
759 #define MAC_RX_STATS_FCS_ERRORS         0x00000898
760 #define MAC_RX_STATS_ALIGN_ERRORS       0x0000089c
761 #define MAC_RX_STATS_XON_PAUSE_RECVD    0x000008a0
762 #define MAC_RX_STATS_XOFF_PAUSE_RECVD   0x000008a4
763 #define MAC_RX_STATS_MAC_CTRL_RECVD     0x000008a8
764 #define MAC_RX_STATS_XOFF_ENTERED       0x000008ac
765 #define MAC_RX_STATS_FRAME_TOO_LONG     0x000008b0
766 #define MAC_RX_STATS_JABBERS            0x000008b4
767 #define MAC_RX_STATS_UNDERSIZE          0x000008b8
768 /* 0x8bc --> 0xc00 unused */
769
770 /* Send data initiator control registers */
771 #define SNDDATAI_MODE                   0x00000c00
772 #define  SNDDATAI_MODE_RESET             0x00000001
773 #define  SNDDATAI_MODE_ENABLE            0x00000002
774 #define  SNDDATAI_MODE_STAT_OFLOW_ENAB   0x00000004
775 #define SNDDATAI_STATUS                 0x00000c04
776 #define  SNDDATAI_STATUS_STAT_OFLOW      0x00000004
777 #define SNDDATAI_STATSCTRL              0x00000c08
778 #define  SNDDATAI_SCTRL_ENABLE           0x00000001
779 #define  SNDDATAI_SCTRL_FASTUPD          0x00000002
780 #define  SNDDATAI_SCTRL_CLEAR            0x00000004
781 #define  SNDDATAI_SCTRL_FLUSH            0x00000008
782 #define  SNDDATAI_SCTRL_FORCE_ZERO       0x00000010
783 #define SNDDATAI_STATSENAB              0x00000c0c
784 #define SNDDATAI_STATSINCMASK           0x00000c10
785 #define ISO_PKT_TX                      0x00000c20
786 /* 0xc24 --> 0xc80 unused */
787 #define SNDDATAI_COS_CNT_0              0x00000c80
788 #define SNDDATAI_COS_CNT_1              0x00000c84
789 #define SNDDATAI_COS_CNT_2              0x00000c88
790 #define SNDDATAI_COS_CNT_3              0x00000c8c
791 #define SNDDATAI_COS_CNT_4              0x00000c90
792 #define SNDDATAI_COS_CNT_5              0x00000c94
793 #define SNDDATAI_COS_CNT_6              0x00000c98
794 #define SNDDATAI_COS_CNT_7              0x00000c9c
795 #define SNDDATAI_COS_CNT_8              0x00000ca0
796 #define SNDDATAI_COS_CNT_9              0x00000ca4
797 #define SNDDATAI_COS_CNT_10             0x00000ca8
798 #define SNDDATAI_COS_CNT_11             0x00000cac
799 #define SNDDATAI_COS_CNT_12             0x00000cb0
800 #define SNDDATAI_COS_CNT_13             0x00000cb4
801 #define SNDDATAI_COS_CNT_14             0x00000cb8
802 #define SNDDATAI_COS_CNT_15             0x00000cbc
803 #define SNDDATAI_DMA_RDQ_FULL_CNT       0x00000cc0
804 #define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT  0x00000cc4
805 #define SNDDATAI_SDCQ_FULL_CNT          0x00000cc8
806 #define SNDDATAI_NICRNG_SSND_PIDX_CNT   0x00000ccc
807 #define SNDDATAI_STATS_UPDATED_CNT      0x00000cd0
808 #define SNDDATAI_INTERRUPTS_CNT         0x00000cd4
809 #define SNDDATAI_AVOID_INTERRUPTS_CNT   0x00000cd8
810 #define SNDDATAI_SND_THRESH_HIT_CNT     0x00000cdc
811 /* 0xce0 --> 0x1000 unused */
812
813 /* Send data completion control registers */
814 #define SNDDATAC_MODE                   0x00001000
815 #define  SNDDATAC_MODE_RESET             0x00000001
816 #define  SNDDATAC_MODE_ENABLE            0x00000002
817 #define  SNDDATAC_MODE_CDELAY            0x00000010
818 /* 0x1004 --> 0x1400 unused */
819
820 /* Send BD ring selector */
821 #define SNDBDS_MODE                     0x00001400
822 #define  SNDBDS_MODE_RESET               0x00000001
823 #define  SNDBDS_MODE_ENABLE              0x00000002
824 #define  SNDBDS_MODE_ATTN_ENABLE         0x00000004
825 #define SNDBDS_STATUS                   0x00001404
826 #define  SNDBDS_STATUS_ERROR_ATTN        0x00000004
827 #define SNDBDS_HWDIAG                   0x00001408
828 /* 0x140c --> 0x1440 */
829 #define SNDBDS_SEL_CON_IDX_0            0x00001440
830 #define SNDBDS_SEL_CON_IDX_1            0x00001444
831 #define SNDBDS_SEL_CON_IDX_2            0x00001448
832 #define SNDBDS_SEL_CON_IDX_3            0x0000144c
833 #define SNDBDS_SEL_CON_IDX_4            0x00001450
834 #define SNDBDS_SEL_CON_IDX_5            0x00001454
835 #define SNDBDS_SEL_CON_IDX_6            0x00001458
836 #define SNDBDS_SEL_CON_IDX_7            0x0000145c
837 #define SNDBDS_SEL_CON_IDX_8            0x00001460
838 #define SNDBDS_SEL_CON_IDX_9            0x00001464
839 #define SNDBDS_SEL_CON_IDX_10           0x00001468
840 #define SNDBDS_SEL_CON_IDX_11           0x0000146c
841 #define SNDBDS_SEL_CON_IDX_12           0x00001470
842 #define SNDBDS_SEL_CON_IDX_13           0x00001474
843 #define SNDBDS_SEL_CON_IDX_14           0x00001478
844 #define SNDBDS_SEL_CON_IDX_15           0x0000147c
845 /* 0x1480 --> 0x1800 unused */
846
847 /* Send BD initiator control registers */
848 #define SNDBDI_MODE                     0x00001800
849 #define  SNDBDI_MODE_RESET               0x00000001
850 #define  SNDBDI_MODE_ENABLE              0x00000002
851 #define  SNDBDI_MODE_ATTN_ENABLE         0x00000004
852 #define  SNDBDI_MODE_MULTI_TXQ_EN        0x00000020
853 #define SNDBDI_STATUS                   0x00001804
854 #define  SNDBDI_STATUS_ERROR_ATTN        0x00000004
855 #define SNDBDI_IN_PROD_IDX_0            0x00001808
856 #define SNDBDI_IN_PROD_IDX_1            0x0000180c
857 #define SNDBDI_IN_PROD_IDX_2            0x00001810
858 #define SNDBDI_IN_PROD_IDX_3            0x00001814
859 #define SNDBDI_IN_PROD_IDX_4            0x00001818
860 #define SNDBDI_IN_PROD_IDX_5            0x0000181c
861 #define SNDBDI_IN_PROD_IDX_6            0x00001820
862 #define SNDBDI_IN_PROD_IDX_7            0x00001824
863 #define SNDBDI_IN_PROD_IDX_8            0x00001828
864 #define SNDBDI_IN_PROD_IDX_9            0x0000182c
865 #define SNDBDI_IN_PROD_IDX_10           0x00001830
866 #define SNDBDI_IN_PROD_IDX_11           0x00001834
867 #define SNDBDI_IN_PROD_IDX_12           0x00001838
868 #define SNDBDI_IN_PROD_IDX_13           0x0000183c
869 #define SNDBDI_IN_PROD_IDX_14           0x00001840
870 #define SNDBDI_IN_PROD_IDX_15           0x00001844
871 /* 0x1848 --> 0x1c00 unused */
872
873 /* Send BD completion control registers */
874 #define SNDBDC_MODE                     0x00001c00
875 #define SNDBDC_MODE_RESET                0x00000001
876 #define SNDBDC_MODE_ENABLE               0x00000002
877 #define SNDBDC_MODE_ATTN_ENABLE          0x00000004
878 /* 0x1c04 --> 0x2000 unused */
879
880 /* Receive list placement control registers */
881 #define RCVLPC_MODE                     0x00002000
882 #define  RCVLPC_MODE_RESET               0x00000001
883 #define  RCVLPC_MODE_ENABLE              0x00000002
884 #define  RCVLPC_MODE_CLASS0_ATTN_ENAB    0x00000004
885 #define  RCVLPC_MODE_MAPOOR_AATTN_ENAB   0x00000008
886 #define  RCVLPC_MODE_STAT_OFLOW_ENAB     0x00000010
887 #define RCVLPC_STATUS                   0x00002004
888 #define  RCVLPC_STATUS_CLASS0            0x00000004
889 #define  RCVLPC_STATUS_MAPOOR            0x00000008
890 #define  RCVLPC_STATUS_STAT_OFLOW        0x00000010
891 #define RCVLPC_LOCK                     0x00002008
892 #define  RCVLPC_LOCK_REQ_MASK            0x0000ffff
893 #define  RCVLPC_LOCK_REQ_SHIFT           0
894 #define  RCVLPC_LOCK_GRANT_MASK          0xffff0000
895 #define  RCVLPC_LOCK_GRANT_SHIFT         16
896 #define RCVLPC_NON_EMPTY_BITS           0x0000200c
897 #define  RCVLPC_NON_EMPTY_BITS_MASK      0x0000ffff
898 #define RCVLPC_CONFIG                   0x00002010
899 #define RCVLPC_STATSCTRL                0x00002014
900 #define  RCVLPC_STATSCTRL_ENABLE         0x00000001
901 #define  RCVLPC_STATSCTRL_FASTUPD        0x00000002
902 #define RCVLPC_STATS_ENABLE             0x00002018
903 #define  RCVLPC_STATSENAB_ASF_FIX        0x00000002
904 #define  RCVLPC_STATSENAB_DACK_FIX       0x00040000
905 #define  RCVLPC_STATSENAB_LNGBRST_RFIX   0x00400000
906 #define RCVLPC_STATS_INCMASK            0x0000201c
907 /* 0x2020 --> 0x2100 unused */
908 #define RCVLPC_SELLST_BASE              0x00002100 /* 16 16-byte entries */
909 #define  SELLST_TAIL                    0x00000004
910 #define  SELLST_CONT                    0x00000008
911 #define  SELLST_UNUSED                  0x0000000c
912 #define RCVLPC_COS_CNTL_BASE            0x00002200 /* 16 4-byte entries */
913 #define RCVLPC_DROP_FILTER_CNT          0x00002240
914 #define RCVLPC_DMA_WQ_FULL_CNT          0x00002244
915 #define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT   0x00002248
916 #define RCVLPC_NO_RCV_BD_CNT            0x0000224c
917 #define RCVLPC_IN_DISCARDS_CNT          0x00002250
918 #define RCVLPC_IN_ERRORS_CNT            0x00002254
919 #define RCVLPC_RCV_THRESH_HIT_CNT       0x00002258
920 /* 0x225c --> 0x2400 unused */
921
922 /* Receive Data and Receive BD Initiator Control */
923 #define RCVDBDI_MODE                    0x00002400
924 #define  RCVDBDI_MODE_RESET              0x00000001
925 #define  RCVDBDI_MODE_ENABLE             0x00000002
926 #define  RCVDBDI_MODE_JUMBOBD_NEEDED     0x00000004
927 #define  RCVDBDI_MODE_FRM_TOO_BIG        0x00000008
928 #define  RCVDBDI_MODE_INV_RING_SZ        0x00000010
929 #define RCVDBDI_STATUS                  0x00002404
930 #define  RCVDBDI_STATUS_JUMBOBD_NEEDED   0x00000004
931 #define  RCVDBDI_STATUS_FRM_TOO_BIG      0x00000008
932 #define  RCVDBDI_STATUS_INV_RING_SZ      0x00000010
933 #define RCVDBDI_SPLIT_FRAME_MINSZ       0x00002408
934 /* 0x240c --> 0x2440 unused */
935 #define RCVDBDI_JUMBO_BD                0x00002440 /* TG3_BDINFO_... */
936 #define RCVDBDI_STD_BD                  0x00002450 /* TG3_BDINFO_... */
937 #define RCVDBDI_MINI_BD                 0x00002460 /* TG3_BDINFO_... */
938 #define RCVDBDI_JUMBO_CON_IDX           0x00002470
939 #define RCVDBDI_STD_CON_IDX             0x00002474
940 #define RCVDBDI_MINI_CON_IDX            0x00002478
941 /* 0x247c --> 0x2480 unused */
942 #define RCVDBDI_BD_PROD_IDX_0           0x00002480
943 #define RCVDBDI_BD_PROD_IDX_1           0x00002484
944 #define RCVDBDI_BD_PROD_IDX_2           0x00002488
945 #define RCVDBDI_BD_PROD_IDX_3           0x0000248c
946 #define RCVDBDI_BD_PROD_IDX_4           0x00002490
947 #define RCVDBDI_BD_PROD_IDX_5           0x00002494
948 #define RCVDBDI_BD_PROD_IDX_6           0x00002498
949 #define RCVDBDI_BD_PROD_IDX_7           0x0000249c
950 #define RCVDBDI_BD_PROD_IDX_8           0x000024a0
951 #define RCVDBDI_BD_PROD_IDX_9           0x000024a4
952 #define RCVDBDI_BD_PROD_IDX_10          0x000024a8
953 #define RCVDBDI_BD_PROD_IDX_11          0x000024ac
954 #define RCVDBDI_BD_PROD_IDX_12          0x000024b0
955 #define RCVDBDI_BD_PROD_IDX_13          0x000024b4
956 #define RCVDBDI_BD_PROD_IDX_14          0x000024b8
957 #define RCVDBDI_BD_PROD_IDX_15          0x000024bc
958 #define RCVDBDI_HWDIAG                  0x000024c0
959 /* 0x24c4 --> 0x2800 unused */
960
961 /* Receive Data Completion Control */
962 #define RCVDCC_MODE                     0x00002800
963 #define  RCVDCC_MODE_RESET               0x00000001
964 #define  RCVDCC_MODE_ENABLE              0x00000002
965 #define  RCVDCC_MODE_ATTN_ENABLE         0x00000004
966 /* 0x2804 --> 0x2c00 unused */
967
968 /* Receive BD Initiator Control Registers */
969 #define RCVBDI_MODE                     0x00002c00
970 #define  RCVBDI_MODE_RESET               0x00000001
971 #define  RCVBDI_MODE_ENABLE              0x00000002
972 #define  RCVBDI_MODE_RCB_ATTN_ENAB       0x00000004
973 #define RCVBDI_STATUS                   0x00002c04
974 #define  RCVBDI_STATUS_RCB_ATTN          0x00000004
975 #define RCVBDI_JUMBO_PROD_IDX           0x00002c08
976 #define RCVBDI_STD_PROD_IDX             0x00002c0c
977 #define RCVBDI_MINI_PROD_IDX            0x00002c10
978 #define RCVBDI_MINI_THRESH              0x00002c14
979 #define RCVBDI_STD_THRESH               0x00002c18
980 #define RCVBDI_JUMBO_THRESH             0x00002c1c
981 /* 0x2c20 --> 0x2d00 unused */
982
983 #define STD_REPLENISH_LWM               0x00002d00
984 #define JMB_REPLENISH_LWM               0x00002d04
985 /* 0x2d08 --> 0x3000 unused */
986
987 /* Receive BD Completion Control Registers */
988 #define RCVCC_MODE                      0x00003000
989 #define  RCVCC_MODE_RESET                0x00000001
990 #define  RCVCC_MODE_ENABLE               0x00000002
991 #define  RCVCC_MODE_ATTN_ENABLE          0x00000004
992 #define RCVCC_STATUS                    0x00003004
993 #define  RCVCC_STATUS_ERROR_ATTN         0x00000004
994 #define RCVCC_JUMP_PROD_IDX             0x00003008
995 #define RCVCC_STD_PROD_IDX              0x0000300c
996 #define RCVCC_MINI_PROD_IDX             0x00003010
997 /* 0x3014 --> 0x3400 unused */
998
999 /* Receive list selector control registers */
1000 #define RCVLSC_MODE                     0x00003400
1001 #define  RCVLSC_MODE_RESET               0x00000001
1002 #define  RCVLSC_MODE_ENABLE              0x00000002
1003 #define  RCVLSC_MODE_ATTN_ENABLE         0x00000004
1004 #define RCVLSC_STATUS                   0x00003404
1005 #define  RCVLSC_STATUS_ERROR_ATTN        0x00000004
1006 /* 0x3408 --> 0x3600 unused */
1007
1008 /* CPMU registers */
1009 #define TG3_CPMU_CTRL                   0x00003600
1010 #define  CPMU_CTRL_LINK_IDLE_MODE        0x00000200
1011 #define  CPMU_CTRL_LINK_AWARE_MODE       0x00000400
1012 #define  CPMU_CTRL_LINK_SPEED_MODE       0x00004000
1013 #define  CPMU_CTRL_GPHY_10MB_RXONLY      0x00010000
1014 #define TG3_CPMU_LSPD_10MB_CLK          0x00003604
1015 #define  CPMU_LSPD_10MB_MACCLK_MASK      0x001f0000
1016 #define  CPMU_LSPD_10MB_MACCLK_6_25      0x00130000
1017 /* 0x3608 --> 0x360c unused */
1018
1019 #define TG3_CPMU_LSPD_1000MB_CLK        0x0000360c
1020 #define  CPMU_LSPD_1000MB_MACCLK_62_5    0x00000000
1021 #define  CPMU_LSPD_1000MB_MACCLK_12_5    0x00110000
1022 #define  CPMU_LSPD_1000MB_MACCLK_MASK    0x001f0000
1023 #define TG3_CPMU_LNK_AWARE_PWRMD        0x00003610
1024 #define  CPMU_LNK_AWARE_MACCLK_MASK      0x001f0000
1025 #define  CPMU_LNK_AWARE_MACCLK_6_25      0x00130000
1026 /* 0x3614 --> 0x361c unused */
1027
1028 #define TG3_CPMU_HST_ACC                0x0000361c
1029 #define  CPMU_HST_ACC_MACCLK_MASK        0x001f0000
1030 #define  CPMU_HST_ACC_MACCLK_6_25        0x00130000
1031 /* 0x3620 --> 0x362c unused */
1032
1033 #define TG3_CPMU_STATUS                 0x0000362c
1034 #define  TG3_CPMU_STATUS_PCIE_FUNC       0x20000000
1035 #define TG3_CPMU_CLCK_STAT              0x00003630
1036 #define  CPMU_CLCK_STAT_MAC_CLCK_MASK    0x001f0000
1037 #define  CPMU_CLCK_STAT_MAC_CLCK_62_5    0x00000000
1038 #define  CPMU_CLCK_STAT_MAC_CLCK_12_5    0x00110000
1039 #define  CPMU_CLCK_STAT_MAC_CLCK_6_25    0x00130000
1040 /* 0x3634 --> 0x365c unused */
1041
1042 #define TG3_CPMU_MUTEX_REQ              0x0000365c
1043 #define  CPMU_MUTEX_REQ_DRIVER           0x00001000
1044 #define TG3_CPMU_MUTEX_GNT              0x00003660
1045 #define  CPMU_MUTEX_GNT_DRIVER           0x00001000
1046 /* 0x3664 --> 0x3800 unused */
1047
1048 /* Mbuf cluster free registers */
1049 #define MBFREE_MODE                     0x00003800
1050 #define  MBFREE_MODE_RESET               0x00000001
1051 #define  MBFREE_MODE_ENABLE              0x00000002
1052 #define MBFREE_STATUS                   0x00003804
1053 /* 0x3808 --> 0x3c00 unused */
1054
1055 /* Host coalescing control registers */
1056 #define HOSTCC_MODE                     0x00003c00
1057 #define  HOSTCC_MODE_RESET               0x00000001
1058 #define  HOSTCC_MODE_ENABLE              0x00000002
1059 #define  HOSTCC_MODE_ATTN                0x00000004
1060 #define  HOSTCC_MODE_NOW                 0x00000008
1061 #define  HOSTCC_MODE_FULL_STATUS         0x00000000
1062 #define  HOSTCC_MODE_64BYTE              0x00000080
1063 #define  HOSTCC_MODE_32BYTE              0x00000100
1064 #define  HOSTCC_MODE_CLRTICK_RXBD        0x00000200
1065 #define  HOSTCC_MODE_CLRTICK_TXBD        0x00000400
1066 #define  HOSTCC_MODE_NOINT_ON_NOW        0x00000800
1067 #define  HOSTCC_MODE_NOINT_ON_FORCE      0x00001000
1068 #define  HOSTCC_MODE_COAL_VEC1_NOW       0x00002000
1069 #define HOSTCC_STATUS                   0x00003c04
1070 #define  HOSTCC_STATUS_ERROR_ATTN        0x00000004
1071 #define HOSTCC_RXCOL_TICKS              0x00003c08
1072 #define  LOW_RXCOL_TICKS                 0x00000032
1073 #define  LOW_RXCOL_TICKS_CLRTCKS         0x00000014
1074 #define  DEFAULT_RXCOL_TICKS             0x00000048
1075 #define  HIGH_RXCOL_TICKS                0x00000096
1076 #define  MAX_RXCOL_TICKS                 0x000003ff
1077 #define HOSTCC_TXCOL_TICKS              0x00003c0c
1078 #define  LOW_TXCOL_TICKS                 0x00000096
1079 #define  LOW_TXCOL_TICKS_CLRTCKS         0x00000048
1080 #define  DEFAULT_TXCOL_TICKS             0x0000012c
1081 #define  HIGH_TXCOL_TICKS                0x00000145
1082 #define  MAX_TXCOL_TICKS                 0x000003ff
1083 #define HOSTCC_RXMAX_FRAMES             0x00003c10
1084 #define  LOW_RXMAX_FRAMES                0x00000005
1085 #define  DEFAULT_RXMAX_FRAMES            0x00000008
1086 #define  HIGH_RXMAX_FRAMES               0x00000012
1087 #define  MAX_RXMAX_FRAMES                0x000000ff
1088 #define HOSTCC_TXMAX_FRAMES             0x00003c14
1089 #define  LOW_TXMAX_FRAMES                0x00000035
1090 #define  DEFAULT_TXMAX_FRAMES            0x0000004b
1091 #define  HIGH_TXMAX_FRAMES               0x00000052
1092 #define  MAX_TXMAX_FRAMES                0x000000ff
1093 #define HOSTCC_RXCOAL_TICK_INT          0x00003c18
1094 #define  DEFAULT_RXCOAL_TICK_INT         0x00000019
1095 #define  DEFAULT_RXCOAL_TICK_INT_CLRTCKS 0x00000014
1096 #define  MAX_RXCOAL_TICK_INT             0x000003ff
1097 #define HOSTCC_TXCOAL_TICK_INT          0x00003c1c
1098 #define  DEFAULT_TXCOAL_TICK_INT         0x00000019
1099 #define  DEFAULT_TXCOAL_TICK_INT_CLRTCKS 0x00000014
1100 #define  MAX_TXCOAL_TICK_INT             0x000003ff
1101 #define HOSTCC_RXCOAL_MAXF_INT          0x00003c20
1102 #define  DEFAULT_RXCOAL_MAXF_INT         0x00000005
1103 #define  MAX_RXCOAL_MAXF_INT             0x000000ff
1104 #define HOSTCC_TXCOAL_MAXF_INT          0x00003c24
1105 #define  DEFAULT_TXCOAL_MAXF_INT         0x00000005
1106 #define  MAX_TXCOAL_MAXF_INT             0x000000ff
1107 #define HOSTCC_STAT_COAL_TICKS          0x00003c28
1108 #define  DEFAULT_STAT_COAL_TICKS         0x000f4240
1109 #define  MAX_STAT_COAL_TICKS             0xd693d400
1110 #define  MIN_STAT_COAL_TICKS             0x00000064
1111 /* 0x3c2c --> 0x3c30 unused */
1112 #define HOSTCC_STATS_BLK_HOST_ADDR      0x00003c30 /* 64-bit */
1113 #define HOSTCC_STATUS_BLK_HOST_ADDR     0x00003c38 /* 64-bit */
1114 #define HOSTCC_STATS_BLK_NIC_ADDR       0x00003c40
1115 #define HOSTCC_STATUS_BLK_NIC_ADDR      0x00003c44
1116 #define HOSTCC_FLOW_ATTN                0x00003c48
1117 /* 0x3c4c --> 0x3c50 unused */
1118 #define HOSTCC_JUMBO_CON_IDX            0x00003c50
1119 #define HOSTCC_STD_CON_IDX              0x00003c54
1120 #define HOSTCC_MINI_CON_IDX             0x00003c58
1121 /* 0x3c5c --> 0x3c80 unused */
1122 #define HOSTCC_RET_PROD_IDX_0           0x00003c80
1123 #define HOSTCC_RET_PROD_IDX_1           0x00003c84
1124 #define HOSTCC_RET_PROD_IDX_2           0x00003c88
1125 #define HOSTCC_RET_PROD_IDX_3           0x00003c8c
1126 #define HOSTCC_RET_PROD_IDX_4           0x00003c90
1127 #define HOSTCC_RET_PROD_IDX_5           0x00003c94
1128 #define HOSTCC_RET_PROD_IDX_6           0x00003c98
1129 #define HOSTCC_RET_PROD_IDX_7           0x00003c9c
1130 #define HOSTCC_RET_PROD_IDX_8           0x00003ca0
1131 #define HOSTCC_RET_PROD_IDX_9           0x00003ca4
1132 #define HOSTCC_RET_PROD_IDX_10          0x00003ca8
1133 #define HOSTCC_RET_PROD_IDX_11          0x00003cac
1134 #define HOSTCC_RET_PROD_IDX_12          0x00003cb0
1135 #define HOSTCC_RET_PROD_IDX_13          0x00003cb4
1136 #define HOSTCC_RET_PROD_IDX_14          0x00003cb8
1137 #define HOSTCC_RET_PROD_IDX_15          0x00003cbc
1138 #define HOSTCC_SND_CON_IDX_0            0x00003cc0
1139 #define HOSTCC_SND_CON_IDX_1            0x00003cc4
1140 #define HOSTCC_SND_CON_IDX_2            0x00003cc8
1141 #define HOSTCC_SND_CON_IDX_3            0x00003ccc
1142 #define HOSTCC_SND_CON_IDX_4            0x00003cd0
1143 #define HOSTCC_SND_CON_IDX_5            0x00003cd4
1144 #define HOSTCC_SND_CON_IDX_6            0x00003cd8
1145 #define HOSTCC_SND_CON_IDX_7            0x00003cdc
1146 #define HOSTCC_SND_CON_IDX_8            0x00003ce0
1147 #define HOSTCC_SND_CON_IDX_9            0x00003ce4
1148 #define HOSTCC_SND_CON_IDX_10           0x00003ce8
1149 #define HOSTCC_SND_CON_IDX_11           0x00003cec
1150 #define HOSTCC_SND_CON_IDX_12           0x00003cf0
1151 #define HOSTCC_SND_CON_IDX_13           0x00003cf4
1152 #define HOSTCC_SND_CON_IDX_14           0x00003cf8
1153 #define HOSTCC_SND_CON_IDX_15           0x00003cfc
1154 #define HOSTCC_STATBLCK_RING1           0x00003d00
1155 /* 0x3d00 --> 0x3d80 unused */
1156
1157 #define HOSTCC_RXCOL_TICKS_VEC1         0x00003d80
1158 #define HOSTCC_TXCOL_TICKS_VEC1         0x00003d84
1159 #define HOSTCC_RXMAX_FRAMES_VEC1        0x00003d88
1160 #define HOSTCC_TXMAX_FRAMES_VEC1        0x00003d8c
1161 #define HOSTCC_RXCOAL_MAXF_INT_VEC1     0x00003d90
1162 #define HOSTCC_TXCOAL_MAXF_INT_VEC1     0x00003d94
1163 /* 0x3d98 --> 0x4000 unused */
1164
1165 /* Memory arbiter control registers */
1166 #define MEMARB_MODE                     0x00004000
1167 #define  MEMARB_MODE_RESET               0x00000001
1168 #define  MEMARB_MODE_ENABLE              0x00000002
1169 #define MEMARB_STATUS                   0x00004004
1170 #define MEMARB_TRAP_ADDR_LOW            0x00004008
1171 #define MEMARB_TRAP_ADDR_HIGH           0x0000400c
1172 /* 0x4010 --> 0x4400 unused */
1173
1174 /* Buffer manager control registers */
1175 #define BUFMGR_MODE                     0x00004400
1176 #define  BUFMGR_MODE_RESET               0x00000001
1177 #define  BUFMGR_MODE_ENABLE              0x00000002
1178 #define  BUFMGR_MODE_ATTN_ENABLE         0x00000004
1179 #define  BUFMGR_MODE_BM_TEST             0x00000008
1180 #define  BUFMGR_MODE_MBLOW_ATTN_ENAB     0x00000010
1181 #define BUFMGR_STATUS                   0x00004404
1182 #define  BUFMGR_STATUS_ERROR             0x00000004
1183 #define  BUFMGR_STATUS_MBLOW             0x00000010
1184 #define BUFMGR_MB_POOL_ADDR             0x00004408
1185 #define BUFMGR_MB_POOL_SIZE             0x0000440c
1186 #define BUFMGR_MB_RDMA_LOW_WATER        0x00004410
1187 #define  DEFAULT_MB_RDMA_LOW_WATER       0x00000050
1188 #define  DEFAULT_MB_RDMA_LOW_WATER_5705  0x00000000
1189 #define  DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130
1190 #define  DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780 0x00000000
1191 #define BUFMGR_MB_MACRX_LOW_WATER       0x00004414
1192 #define  DEFAULT_MB_MACRX_LOW_WATER       0x00000020
1193 #define  DEFAULT_MB_MACRX_LOW_WATER_5705  0x00000010
1194 #define  DEFAULT_MB_MACRX_LOW_WATER_5906  0x00000004
1195 #define  DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
1196 #define  DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b
1197 #define BUFMGR_MB_HIGH_WATER            0x00004418
1198 #define  DEFAULT_MB_HIGH_WATER           0x00000060
1199 #define  DEFAULT_MB_HIGH_WATER_5705      0x00000060
1200 #define  DEFAULT_MB_HIGH_WATER_5906      0x00000010
1201 #define  DEFAULT_MB_HIGH_WATER_JUMBO     0x0000017c
1202 #define  DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096
1203 #define BUFMGR_RX_MB_ALLOC_REQ          0x0000441c
1204 #define  BUFMGR_MB_ALLOC_BIT             0x10000000
1205 #define BUFMGR_RX_MB_ALLOC_RESP         0x00004420
1206 #define BUFMGR_TX_MB_ALLOC_REQ          0x00004424
1207 #define BUFMGR_TX_MB_ALLOC_RESP         0x00004428
1208 #define BUFMGR_DMA_DESC_POOL_ADDR       0x0000442c
1209 #define BUFMGR_DMA_DESC_POOL_SIZE       0x00004430
1210 #define BUFMGR_DMA_LOW_WATER            0x00004434
1211 #define  DEFAULT_DMA_LOW_WATER           0x00000005
1212 #define BUFMGR_DMA_HIGH_WATER           0x00004438
1213 #define  DEFAULT_DMA_HIGH_WATER          0x0000000a
1214 #define BUFMGR_RX_DMA_ALLOC_REQ         0x0000443c
1215 #define BUFMGR_RX_DMA_ALLOC_RESP        0x00004440
1216 #define BUFMGR_TX_DMA_ALLOC_REQ         0x00004444
1217 #define BUFMGR_TX_DMA_ALLOC_RESP        0x00004448
1218 #define BUFMGR_HWDIAG_0                 0x0000444c
1219 #define BUFMGR_HWDIAG_1                 0x00004450
1220 #define BUFMGR_HWDIAG_2                 0x00004454
1221 /* 0x4458 --> 0x4800 unused */
1222
1223 /* Read DMA control registers */
1224 #define RDMAC_MODE                      0x00004800
1225 #define  RDMAC_MODE_RESET                0x00000001
1226 #define  RDMAC_MODE_ENABLE               0x00000002
1227 #define  RDMAC_MODE_TGTABORT_ENAB        0x00000004
1228 #define  RDMAC_MODE_MSTABORT_ENAB        0x00000008
1229 #define  RDMAC_MODE_PARITYERR_ENAB       0x00000010
1230 #define  RDMAC_MODE_ADDROFLOW_ENAB       0x00000020
1231 #define  RDMAC_MODE_FIFOOFLOW_ENAB       0x00000040
1232 #define  RDMAC_MODE_FIFOURUN_ENAB        0x00000080
1233 #define  RDMAC_MODE_FIFOOREAD_ENAB       0x00000100
1234 #define  RDMAC_MODE_LNGREAD_ENAB         0x00000200
1235 #define  RDMAC_MODE_SPLIT_ENABLE         0x00000800
1236 #define  RDMAC_MODE_BD_SBD_CRPT_ENAB     0x00000800
1237 #define  RDMAC_MODE_SPLIT_RESET          0x00001000
1238 #define  RDMAC_MODE_MBUF_RBD_CRPT_ENAB   0x00001000
1239 #define  RDMAC_MODE_MBUF_SBD_CRPT_ENAB   0x00002000
1240 #define  RDMAC_MODE_FIFO_SIZE_128        0x00020000
1241 #define  RDMAC_MODE_FIFO_LONG_BURST      0x00030000
1242 #define  RDMAC_MODE_IPV4_LSO_EN          0x08000000
1243 #define  RDMAC_MODE_IPV6_LSO_EN          0x10000000
1244 #define RDMAC_STATUS                    0x00004804
1245 #define  RDMAC_STATUS_TGTABORT           0x00000004
1246 #define  RDMAC_STATUS_MSTABORT           0x00000008
1247 #define  RDMAC_STATUS_PARITYERR          0x00000010
1248 #define  RDMAC_STATUS_ADDROFLOW          0x00000020
1249 #define  RDMAC_STATUS_FIFOOFLOW          0x00000040
1250 #define  RDMAC_STATUS_FIFOURUN           0x00000080
1251 #define  RDMAC_STATUS_FIFOOREAD          0x00000100
1252 #define  RDMAC_STATUS_LNGREAD            0x00000200
1253 /* 0x4808 --> 0x4c00 unused */
1254
1255 /* Write DMA control registers */
1256 #define WDMAC_MODE                      0x00004c00
1257 #define  WDMAC_MODE_RESET                0x00000001
1258 #define  WDMAC_MODE_ENABLE               0x00000002
1259 #define  WDMAC_MODE_TGTABORT_ENAB        0x00000004
1260 #define  WDMAC_MODE_MSTABORT_ENAB        0x00000008
1261 #define  WDMAC_MODE_PARITYERR_ENAB       0x00000010
1262 #define  WDMAC_MODE_ADDROFLOW_ENAB       0x00000020
1263 #define  WDMAC_MODE_FIFOOFLOW_ENAB       0x00000040
1264 #define  WDMAC_MODE_FIFOURUN_ENAB        0x00000080
1265 #define  WDMAC_MODE_FIFOOREAD_ENAB       0x00000100
1266 #define  WDMAC_MODE_LNGREAD_ENAB         0x00000200
1267 #define  WDMAC_MODE_RX_ACCEL             0x00000400
1268 #define  WDMAC_MODE_STATUS_TAG_FIX       0x20000000
1269 #define WDMAC_STATUS                    0x00004c04
1270 #define  WDMAC_STATUS_TGTABORT           0x00000004
1271 #define  WDMAC_STATUS_MSTABORT           0x00000008
1272 #define  WDMAC_STATUS_PARITYERR          0x00000010
1273 #define  WDMAC_STATUS_ADDROFLOW          0x00000020
1274 #define  WDMAC_STATUS_FIFOOFLOW          0x00000040
1275 #define  WDMAC_STATUS_FIFOURUN           0x00000080
1276 #define  WDMAC_STATUS_FIFOOREAD          0x00000100
1277 #define  WDMAC_STATUS_LNGREAD            0x00000200
1278 /* 0x4c08 --> 0x5000 unused */
1279
1280 /* Per-cpu register offsets (arm9) */
1281 #define CPU_MODE                        0x00000000
1282 #define  CPU_MODE_RESET                  0x00000001
1283 #define  CPU_MODE_HALT                   0x00000400
1284 #define CPU_STATE                       0x00000004
1285 #define CPU_EVTMASK                     0x00000008
1286 /* 0xc --> 0x1c reserved */
1287 #define CPU_PC                          0x0000001c
1288 #define CPU_INSN                        0x00000020
1289 #define CPU_SPAD_UFLOW                  0x00000024
1290 #define CPU_WDOG_CLEAR                  0x00000028
1291 #define CPU_WDOG_VECTOR                 0x0000002c
1292 #define CPU_WDOG_PC                     0x00000030
1293 #define CPU_HW_BP                       0x00000034
1294 /* 0x38 --> 0x44 unused */
1295 #define CPU_WDOG_SAVED_STATE            0x00000044
1296 #define CPU_LAST_BRANCH_ADDR            0x00000048
1297 #define CPU_SPAD_UFLOW_SET              0x0000004c
1298 /* 0x50 --> 0x200 unused */
1299 #define CPU_R0                          0x00000200
1300 #define CPU_R1                          0x00000204
1301 #define CPU_R2                          0x00000208
1302 #define CPU_R3                          0x0000020c
1303 #define CPU_R4                          0x00000210
1304 #define CPU_R5                          0x00000214
1305 #define CPU_R6                          0x00000218
1306 #define CPU_R7                          0x0000021c
1307 #define CPU_R8                          0x00000220
1308 #define CPU_R9                          0x00000224
1309 #define CPU_R10                         0x00000228
1310 #define CPU_R11                         0x0000022c
1311 #define CPU_R12                         0x00000230
1312 #define CPU_R13                         0x00000234
1313 #define CPU_R14                         0x00000238
1314 #define CPU_R15                         0x0000023c
1315 #define CPU_R16                         0x00000240
1316 #define CPU_R17                         0x00000244
1317 #define CPU_R18                         0x00000248
1318 #define CPU_R19                         0x0000024c
1319 #define CPU_R20                         0x00000250
1320 #define CPU_R21                         0x00000254
1321 #define CPU_R22                         0x00000258
1322 #define CPU_R23                         0x0000025c
1323 #define CPU_R24                         0x00000260
1324 #define CPU_R25                         0x00000264
1325 #define CPU_R26                         0x00000268
1326 #define CPU_R27                         0x0000026c
1327 #define CPU_R28                         0x00000270
1328 #define CPU_R29                         0x00000274
1329 #define CPU_R30                         0x00000278
1330 #define CPU_R31                         0x0000027c
1331 /* 0x280 --> 0x400 unused */
1332
1333 #define RX_CPU_BASE                     0x00005000
1334 #define RX_CPU_MODE                     0x00005000
1335 #define RX_CPU_STATE                    0x00005004
1336 #define RX_CPU_PGMCTR                   0x0000501c
1337 #define RX_CPU_HWBKPT                   0x00005034
1338 #define TX_CPU_BASE                     0x00005400
1339 #define TX_CPU_MODE                     0x00005400
1340 #define TX_CPU_STATE                    0x00005404
1341 #define TX_CPU_PGMCTR                   0x0000541c
1342
1343 #define VCPU_STATUS                     0x00005100
1344 #define  VCPU_STATUS_INIT_DONE           0x04000000
1345 #define  VCPU_STATUS_DRV_RESET           0x08000000
1346
1347 #define VCPU_CFGSHDW                    0x00005104
1348 #define  VCPU_CFGSHDW_WOL_ENABLE         0x00000001
1349 #define  VCPU_CFGSHDW_WOL_MAGPKT         0x00000004
1350 #define  VCPU_CFGSHDW_ASPM_DBNC          0x00001000
1351
1352 /* Mailboxes */
1353 #define GRCMBOX_BASE                    0x00005600
1354 #define GRCMBOX_INTERRUPT_0             0x00005800 /* 64-bit */
1355 #define GRCMBOX_INTERRUPT_1             0x00005808 /* 64-bit */
1356 #define GRCMBOX_INTERRUPT_2             0x00005810 /* 64-bit */
1357 #define GRCMBOX_INTERRUPT_3             0x00005818 /* 64-bit */
1358 #define GRCMBOX_GENERAL_0               0x00005820 /* 64-bit */
1359 #define GRCMBOX_GENERAL_1               0x00005828 /* 64-bit */
1360 #define GRCMBOX_GENERAL_2               0x00005830 /* 64-bit */
1361 #define GRCMBOX_GENERAL_3               0x00005838 /* 64-bit */
1362 #define GRCMBOX_GENERAL_4               0x00005840 /* 64-bit */
1363 #define GRCMBOX_GENERAL_5               0x00005848 /* 64-bit */
1364 #define GRCMBOX_GENERAL_6               0x00005850 /* 64-bit */
1365 #define GRCMBOX_GENERAL_7               0x00005858 /* 64-bit */
1366 #define GRCMBOX_RELOAD_STAT             0x00005860 /* 64-bit */
1367 #define GRCMBOX_RCVSTD_PROD_IDX         0x00005868 /* 64-bit */
1368 #define GRCMBOX_RCVJUMBO_PROD_IDX       0x00005870 /* 64-bit */
1369 #define GRCMBOX_RCVMINI_PROD_IDX        0x00005878 /* 64-bit */
1370 #define GRCMBOX_RCVRET_CON_IDX_0        0x00005880 /* 64-bit */
1371 #define GRCMBOX_RCVRET_CON_IDX_1        0x00005888 /* 64-bit */
1372 #define GRCMBOX_RCVRET_CON_IDX_2        0x00005890 /* 64-bit */
1373 #define GRCMBOX_RCVRET_CON_IDX_3        0x00005898 /* 64-bit */
1374 #define GRCMBOX_RCVRET_CON_IDX_4        0x000058a0 /* 64-bit */
1375 #define GRCMBOX_RCVRET_CON_IDX_5        0x000058a8 /* 64-bit */
1376 #define GRCMBOX_RCVRET_CON_IDX_6        0x000058b0 /* 64-bit */
1377 #define GRCMBOX_RCVRET_CON_IDX_7        0x000058b8 /* 64-bit */
1378 #define GRCMBOX_RCVRET_CON_IDX_8        0x000058c0 /* 64-bit */
1379 #define GRCMBOX_RCVRET_CON_IDX_9        0x000058c8 /* 64-bit */
1380 #define GRCMBOX_RCVRET_CON_IDX_10       0x000058d0 /* 64-bit */
1381 #define GRCMBOX_RCVRET_CON_IDX_11       0x000058d8 /* 64-bit */
1382 #define GRCMBOX_RCVRET_CON_IDX_12       0x000058e0 /* 64-bit */
1383 #define GRCMBOX_RCVRET_CON_IDX_13       0x000058e8 /* 64-bit */
1384 #define GRCMBOX_RCVRET_CON_IDX_14       0x000058f0 /* 64-bit */
1385 #define GRCMBOX_RCVRET_CON_IDX_15       0x000058f8 /* 64-bit */
1386 #define GRCMBOX_SNDHOST_PROD_IDX_0      0x00005900 /* 64-bit */
1387 #define GRCMBOX_SNDHOST_PROD_IDX_1      0x00005908 /* 64-bit */
1388 #define GRCMBOX_SNDHOST_PROD_IDX_2      0x00005910 /* 64-bit */
1389 #define GRCMBOX_SNDHOST_PROD_IDX_3      0x00005918 /* 64-bit */
1390 #define GRCMBOX_SNDHOST_PROD_IDX_4      0x00005920 /* 64-bit */
1391 #define GRCMBOX_SNDHOST_PROD_IDX_5      0x00005928 /* 64-bit */
1392 #define GRCMBOX_SNDHOST_PROD_IDX_6      0x00005930 /* 64-bit */
1393 #define GRCMBOX_SNDHOST_PROD_IDX_7      0x00005938 /* 64-bit */
1394 #define GRCMBOX_SNDHOST_PROD_IDX_8      0x00005940 /* 64-bit */
1395 #define GRCMBOX_SNDHOST_PROD_IDX_9      0x00005948 /* 64-bit */
1396 #define GRCMBOX_SNDHOST_PROD_IDX_10     0x00005950 /* 64-bit */
1397 #define GRCMBOX_SNDHOST_PROD_IDX_11     0x00005958 /* 64-bit */
1398 #define GRCMBOX_SNDHOST_PROD_IDX_12     0x00005960 /* 64-bit */
1399 #define GRCMBOX_SNDHOST_PROD_IDX_13     0x00005968 /* 64-bit */
1400 #define GRCMBOX_SNDHOST_PROD_IDX_14     0x00005970 /* 64-bit */
1401 #define GRCMBOX_SNDHOST_PROD_IDX_15     0x00005978 /* 64-bit */
1402 #define GRCMBOX_SNDNIC_PROD_IDX_0       0x00005980 /* 64-bit */
1403 #define GRCMBOX_SNDNIC_PROD_IDX_1       0x00005988 /* 64-bit */
1404 #define GRCMBOX_SNDNIC_PROD_IDX_2       0x00005990 /* 64-bit */
1405 #define GRCMBOX_SNDNIC_PROD_IDX_3       0x00005998 /* 64-bit */
1406 #define GRCMBOX_SNDNIC_PROD_IDX_4       0x000059a0 /* 64-bit */
1407 #define GRCMBOX_SNDNIC_PROD_IDX_5       0x000059a8 /* 64-bit */
1408 #define GRCMBOX_SNDNIC_PROD_IDX_6       0x000059b0 /* 64-bit */
1409 #define GRCMBOX_SNDNIC_PROD_IDX_7       0x000059b8 /* 64-bit */
1410 #define GRCMBOX_SNDNIC_PROD_IDX_8       0x000059c0 /* 64-bit */
1411 #define GRCMBOX_SNDNIC_PROD_IDX_9       0x000059c8 /* 64-bit */
1412 #define GRCMBOX_SNDNIC_PROD_IDX_10      0x000059d0 /* 64-bit */
1413 #define GRCMBOX_SNDNIC_PROD_IDX_11      0x000059d8 /* 64-bit */
1414 #define GRCMBOX_SNDNIC_PROD_IDX_12      0x000059e0 /* 64-bit */
1415 #define GRCMBOX_SNDNIC_PROD_IDX_13      0x000059e8 /* 64-bit */
1416 #define GRCMBOX_SNDNIC_PROD_IDX_14      0x000059f0 /* 64-bit */
1417 #define GRCMBOX_SNDNIC_PROD_IDX_15      0x000059f8 /* 64-bit */
1418 #define GRCMBOX_HIGH_PRIO_EV_VECTOR     0x00005a00
1419 #define GRCMBOX_HIGH_PRIO_EV_MASK       0x00005a04
1420 #define GRCMBOX_LOW_PRIO_EV_VEC         0x00005a08
1421 #define GRCMBOX_LOW_PRIO_EV_MASK        0x00005a0c
1422 /* 0x5a10 --> 0x5c00 */
1423
1424 /* Flow Through queues */
1425 #define FTQ_RESET                       0x00005c00
1426 /* 0x5c04 --> 0x5c10 unused */
1427 #define FTQ_DMA_NORM_READ_CTL           0x00005c10
1428 #define FTQ_DMA_NORM_READ_FULL_CNT      0x00005c14
1429 #define FTQ_DMA_NORM_READ_FIFO_ENQDEQ   0x00005c18
1430 #define FTQ_DMA_NORM_READ_WRITE_PEEK    0x00005c1c
1431 #define FTQ_DMA_HIGH_READ_CTL           0x00005c20
1432 #define FTQ_DMA_HIGH_READ_FULL_CNT      0x00005c24
1433 #define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ   0x00005c28
1434 #define FTQ_DMA_HIGH_READ_WRITE_PEEK    0x00005c2c
1435 #define FTQ_DMA_COMP_DISC_CTL           0x00005c30
1436 #define FTQ_DMA_COMP_DISC_FULL_CNT      0x00005c34
1437 #define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ   0x00005c38
1438 #define FTQ_DMA_COMP_DISC_WRITE_PEEK    0x00005c3c
1439 #define FTQ_SEND_BD_COMP_CTL            0x00005c40
1440 #define FTQ_SEND_BD_COMP_FULL_CNT       0x00005c44
1441 #define FTQ_SEND_BD_COMP_FIFO_ENQDEQ    0x00005c48
1442 #define FTQ_SEND_BD_COMP_WRITE_PEEK     0x00005c4c
1443 #define FTQ_SEND_DATA_INIT_CTL          0x00005c50
1444 #define FTQ_SEND_DATA_INIT_FULL_CNT     0x00005c54
1445 #define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ  0x00005c58
1446 #define FTQ_SEND_DATA_INIT_WRITE_PEEK   0x00005c5c
1447 #define FTQ_DMA_NORM_WRITE_CTL          0x00005c60
1448 #define FTQ_DMA_NORM_WRITE_FULL_CNT     0x00005c64
1449 #define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ  0x00005c68
1450 #define FTQ_DMA_NORM_WRITE_WRITE_PEEK   0x00005c6c
1451 #define FTQ_DMA_HIGH_WRITE_CTL          0x00005c70
1452 #define FTQ_DMA_HIGH_WRITE_FULL_CNT     0x00005c74
1453 #define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ  0x00005c78
1454 #define FTQ_DMA_HIGH_WRITE_WRITE_PEEK   0x00005c7c
1455 #define FTQ_SWTYPE1_CTL                 0x00005c80
1456 #define FTQ_SWTYPE1_FULL_CNT            0x00005c84
1457 #define FTQ_SWTYPE1_FIFO_ENQDEQ         0x00005c88
1458 #define FTQ_SWTYPE1_WRITE_PEEK          0x00005c8c
1459 #define FTQ_SEND_DATA_COMP_CTL          0x00005c90
1460 #define FTQ_SEND_DATA_COMP_FULL_CNT     0x00005c94
1461 #define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ  0x00005c98
1462 #define FTQ_SEND_DATA_COMP_WRITE_PEEK   0x00005c9c
1463 #define FTQ_HOST_COAL_CTL               0x00005ca0
1464 #define FTQ_HOST_COAL_FULL_CNT          0x00005ca4
1465 #define FTQ_HOST_COAL_FIFO_ENQDEQ       0x00005ca8
1466 #define FTQ_HOST_COAL_WRITE_PEEK        0x00005cac
1467 #define FTQ_MAC_TX_CTL                  0x00005cb0
1468 #define FTQ_MAC_TX_FULL_CNT             0x00005cb4
1469 #define FTQ_MAC_TX_FIFO_ENQDEQ          0x00005cb8
1470 #define FTQ_MAC_TX_WRITE_PEEK           0x00005cbc
1471 #define FTQ_MB_FREE_CTL                 0x00005cc0
1472 #define FTQ_MB_FREE_FULL_CNT            0x00005cc4
1473 #define FTQ_MB_FREE_FIFO_ENQDEQ         0x00005cc8
1474 #define FTQ_MB_FREE_WRITE_PEEK          0x00005ccc
1475 #define FTQ_RCVBD_COMP_CTL              0x00005cd0
1476 #define FTQ_RCVBD_COMP_FULL_CNT         0x00005cd4
1477 #define FTQ_RCVBD_COMP_FIFO_ENQDEQ      0x00005cd8
1478 #define FTQ_RCVBD_COMP_WRITE_PEEK       0x00005cdc
1479 #define FTQ_RCVLST_PLMT_CTL             0x00005ce0
1480 #define FTQ_RCVLST_PLMT_FULL_CNT        0x00005ce4
1481 #define FTQ_RCVLST_PLMT_FIFO_ENQDEQ     0x00005ce8
1482 #define FTQ_RCVLST_PLMT_WRITE_PEEK      0x00005cec
1483 #define FTQ_RCVDATA_INI_CTL             0x00005cf0
1484 #define FTQ_RCVDATA_INI_FULL_CNT        0x00005cf4
1485 #define FTQ_RCVDATA_INI_FIFO_ENQDEQ     0x00005cf8
1486 #define FTQ_RCVDATA_INI_WRITE_PEEK      0x00005cfc
1487 #define FTQ_RCVDATA_COMP_CTL            0x00005d00
1488 #define FTQ_RCVDATA_COMP_FULL_CNT       0x00005d04
1489 #define FTQ_RCVDATA_COMP_FIFO_ENQDEQ    0x00005d08
1490 #define FTQ_RCVDATA_COMP_WRITE_PEEK     0x00005d0c
1491 #define FTQ_SWTYPE2_CTL                 0x00005d10
1492 #define FTQ_SWTYPE2_FULL_CNT            0x00005d14
1493 #define FTQ_SWTYPE2_FIFO_ENQDEQ         0x00005d18
1494 #define FTQ_SWTYPE2_WRITE_PEEK          0x00005d1c
1495 /* 0x5d20 --> 0x6000 unused */
1496
1497 /* Message signaled interrupt registers */
1498 #define MSGINT_MODE                     0x00006000
1499 #define  MSGINT_MODE_RESET               0x00000001
1500 #define  MSGINT_MODE_ENABLE              0x00000002
1501 #define  MSGINT_MODE_ONE_SHOT_DISABLE    0x00000020
1502 #define  MSGINT_MODE_MULTIVEC_EN         0x00000080
1503 #define MSGINT_STATUS                   0x00006004
1504 #define MSGINT_FIFO                     0x00006008
1505 /* 0x600c --> 0x6400 unused */
1506
1507 /* DMA completion registers */
1508 #define DMAC_MODE                       0x00006400
1509 #define  DMAC_MODE_RESET                 0x00000001
1510 #define  DMAC_MODE_ENABLE                0x00000002
1511 /* 0x6404 --> 0x6800 unused */
1512
1513 /* GRC registers */
1514 #define GRC_MODE                        0x00006800
1515 #define  GRC_MODE_UPD_ON_COAL           0x00000001
1516 #define  GRC_MODE_BSWAP_NONFRM_DATA     0x00000002
1517 #define  GRC_MODE_WSWAP_NONFRM_DATA     0x00000004
1518 #define  GRC_MODE_BSWAP_DATA            0x00000010
1519 #define  GRC_MODE_WSWAP_DATA            0x00000020
1520 #define  GRC_MODE_SPLITHDR              0x00000100
1521 #define  GRC_MODE_NOFRM_CRACKING        0x00000200
1522 #define  GRC_MODE_INCL_CRC              0x00000400
1523 #define  GRC_MODE_ALLOW_BAD_FRMS        0x00000800
1524 #define  GRC_MODE_NOIRQ_ON_SENDS        0x00002000
1525 #define  GRC_MODE_NOIRQ_ON_RCV          0x00004000
1526 #define  GRC_MODE_FORCE_PCI32BIT        0x00008000
1527 #define  GRC_MODE_HOST_STACKUP          0x00010000
1528 #define  GRC_MODE_HOST_SENDBDS          0x00020000
1529 #define  GRC_MODE_NO_TX_PHDR_CSUM       0x00100000
1530 #define  GRC_MODE_NVRAM_WR_ENABLE       0x00200000
1531 #define  GRC_MODE_NO_RX_PHDR_CSUM       0x00800000
1532 #define  GRC_MODE_IRQ_ON_TX_CPU_ATTN    0x01000000
1533 #define  GRC_MODE_IRQ_ON_RX_CPU_ATTN    0x02000000
1534 #define  GRC_MODE_IRQ_ON_MAC_ATTN       0x04000000
1535 #define  GRC_MODE_IRQ_ON_DMA_ATTN       0x08000000
1536 #define  GRC_MODE_IRQ_ON_FLOW_ATTN      0x10000000
1537 #define  GRC_MODE_4X_NIC_SEND_RINGS     0x20000000
1538 #define  GRC_MODE_MCAST_FRM_ENABLE      0x40000000
1539 #define GRC_MISC_CFG                    0x00006804
1540 #define  GRC_MISC_CFG_CORECLK_RESET     0x00000001
1541 #define  GRC_MISC_CFG_PRESCALAR_MASK    0x000000fe
1542 #define  GRC_MISC_CFG_PRESCALAR_SHIFT   1
1543 #define  GRC_MISC_CFG_BOARD_ID_MASK     0x0001e000
1544 #define  GRC_MISC_CFG_BOARD_ID_5700     0x0001e000
1545 #define  GRC_MISC_CFG_BOARD_ID_5701     0x00000000
1546 #define  GRC_MISC_CFG_BOARD_ID_5702FE   0x00004000
1547 #define  GRC_MISC_CFG_BOARD_ID_5703     0x00000000
1548 #define  GRC_MISC_CFG_BOARD_ID_5703S    0x00002000
1549 #define  GRC_MISC_CFG_BOARD_ID_5704     0x00000000
1550 #define  GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000
1551 #define  GRC_MISC_CFG_BOARD_ID_5704_A2  0x00008000
1552 #define  GRC_MISC_CFG_BOARD_ID_5788     0x00010000
1553 #define  GRC_MISC_CFG_BOARD_ID_5788M    0x00018000
1554 #define  GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000
1555 #define  GRC_MISC_CFG_EPHY_IDDQ         0x00200000
1556 #define  GRC_MISC_CFG_KEEP_GPHY_POWER   0x04000000
1557 #define GRC_LOCAL_CTRL                  0x00006808
1558 #define  GRC_LCLCTRL_INT_ACTIVE         0x00000001
1559 #define  GRC_LCLCTRL_CLEARINT           0x00000002
1560 #define  GRC_LCLCTRL_SETINT             0x00000004
1561 #define  GRC_LCLCTRL_INT_ON_ATTN        0x00000008
1562 #define  GRC_LCLCTRL_GPIO_UART_SEL      0x00000010      /* 5755 only */
1563 #define  GRC_LCLCTRL_USE_SIG_DETECT     0x00000010      /* 5714/5780 only */
1564 #define  GRC_LCLCTRL_USE_EXT_SIG_DETECT 0x00000020      /* 5714/5780 only */
1565 #define  GRC_LCLCTRL_GPIO_INPUT3        0x00000020
1566 #define  GRC_LCLCTRL_GPIO_OE3           0x00000040
1567 #define  GRC_LCLCTRL_GPIO_OUTPUT3       0x00000080
1568 #define  GRC_LCLCTRL_GPIO_INPUT0        0x00000100
1569 #define  GRC_LCLCTRL_GPIO_INPUT1        0x00000200
1570 #define  GRC_LCLCTRL_GPIO_INPUT2        0x00000400
1571 #define  GRC_LCLCTRL_GPIO_OE0           0x00000800
1572 #define  GRC_LCLCTRL_GPIO_OE1           0x00001000
1573 #define  GRC_LCLCTRL_GPIO_OE2           0x00002000
1574 #define  GRC_LCLCTRL_GPIO_OUTPUT0       0x00004000
1575 #define  GRC_LCLCTRL_GPIO_OUTPUT1       0x00008000
1576 #define  GRC_LCLCTRL_GPIO_OUTPUT2       0x00010000
1577 #define  GRC_LCLCTRL_EXTMEM_ENABLE      0x00020000
1578 #define  GRC_LCLCTRL_MEMSZ_MASK         0x001c0000
1579 #define  GRC_LCLCTRL_MEMSZ_256K         0x00000000
1580 #define  GRC_LCLCTRL_MEMSZ_512K         0x00040000
1581 #define  GRC_LCLCTRL_MEMSZ_1M           0x00080000
1582 #define  GRC_LCLCTRL_MEMSZ_2M           0x000c0000
1583 #define  GRC_LCLCTRL_MEMSZ_4M           0x00100000
1584 #define  GRC_LCLCTRL_MEMSZ_8M           0x00140000
1585 #define  GRC_LCLCTRL_MEMSZ_16M          0x00180000
1586 #define  GRC_LCLCTRL_BANK_SELECT        0x00200000
1587 #define  GRC_LCLCTRL_SSRAM_TYPE         0x00400000
1588 #define  GRC_LCLCTRL_AUTO_SEEPROM       0x01000000
1589 #define GRC_TIMER                       0x0000680c
1590 #define GRC_RX_CPU_EVENT                0x00006810
1591 #define  GRC_RX_CPU_DRIVER_EVENT        0x00004000
1592 #define GRC_RX_TIMER_REF                0x00006814
1593 #define GRC_RX_CPU_SEM                  0x00006818
1594 #define GRC_REMOTE_RX_CPU_ATTN          0x0000681c
1595 #define GRC_TX_CPU_EVENT                0x00006820
1596 #define GRC_TX_TIMER_REF                0x00006824
1597 #define GRC_TX_CPU_SEM                  0x00006828
1598 #define GRC_REMOTE_TX_CPU_ATTN          0x0000682c
1599 #define GRC_MEM_POWER_UP                0x00006830 /* 64-bit */
1600 #define GRC_EEPROM_ADDR                 0x00006838
1601 #define  EEPROM_ADDR_WRITE              0x00000000
1602 #define  EEPROM_ADDR_READ               0x80000000
1603 #define  EEPROM_ADDR_COMPLETE           0x40000000
1604 #define  EEPROM_ADDR_FSM_RESET          0x20000000
1605 #define  EEPROM_ADDR_DEVID_MASK         0x1c000000
1606 #define  EEPROM_ADDR_DEVID_SHIFT        26
1607 #define  EEPROM_ADDR_START              0x02000000
1608 #define  EEPROM_ADDR_CLKPERD_SHIFT      16
1609 #define  EEPROM_ADDR_ADDR_MASK          0x0000ffff
1610 #define  EEPROM_ADDR_ADDR_SHIFT         0
1611 #define  EEPROM_DEFAULT_CLOCK_PERIOD    0x60
1612 #define  EEPROM_CHIP_SIZE               (64 * 1024)
1613 #define GRC_EEPROM_DATA                 0x0000683c
1614 #define GRC_EEPROM_CTRL                 0x00006840
1615 #define GRC_MDI_CTRL                    0x00006844
1616 #define GRC_SEEPROM_DELAY               0x00006848
1617 /* 0x684c --> 0x6890 unused */
1618 #define GRC_VCPU_EXT_CTRL               0x00006890
1619 #define GRC_VCPU_EXT_CTRL_HALT_CPU       0x00400000
1620 #define GRC_VCPU_EXT_CTRL_DISABLE_WOL    0x20000000
1621 #define GRC_FASTBOOT_PC                 0x00006894      /* 5752, 5755, 5787 */
1622
1623 /* 0x6c00 --> 0x7000 unused */
1624
1625 /* NVRAM Control registers */
1626 #define NVRAM_CMD                       0x00007000
1627 #define  NVRAM_CMD_RESET                 0x00000001
1628 #define  NVRAM_CMD_DONE                  0x00000008
1629 #define  NVRAM_CMD_GO                    0x00000010
1630 #define  NVRAM_CMD_WR                    0x00000020
1631 #define  NVRAM_CMD_RD                    0x00000000
1632 #define  NVRAM_CMD_ERASE                 0x00000040
1633 #define  NVRAM_CMD_FIRST                 0x00000080
1634 #define  NVRAM_CMD_LAST                  0x00000100
1635 #define  NVRAM_CMD_WREN                  0x00010000
1636 #define  NVRAM_CMD_WRDI                  0x00020000
1637 #define NVRAM_STAT                      0x00007004
1638 #define NVRAM_WRDATA                    0x00007008
1639 #define NVRAM_ADDR                      0x0000700c
1640 #define  NVRAM_ADDR_MSK                 0x00ffffff
1641 #define NVRAM_RDDATA                    0x00007010
1642 #define NVRAM_CFG1                      0x00007014
1643 #define  NVRAM_CFG1_FLASHIF_ENAB         0x00000001
1644 #define  NVRAM_CFG1_BUFFERED_MODE        0x00000002
1645 #define  NVRAM_CFG1_PASS_THRU            0x00000004
1646 #define  NVRAM_CFG1_STATUS_BITS          0x00000070
1647 #define  NVRAM_CFG1_BIT_BANG             0x00000008
1648 #define  NVRAM_CFG1_FLASH_SIZE           0x02000000
1649 #define  NVRAM_CFG1_COMPAT_BYPASS        0x80000000
1650 #define  NVRAM_CFG1_VENDOR_MASK          0x03000003
1651 #define  FLASH_VENDOR_ATMEL_EEPROM       0x02000000
1652 #define  FLASH_VENDOR_ATMEL_FLASH_BUFFERED       0x02000003
1653 #define  FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED     0x00000003
1654 #define  FLASH_VENDOR_ST                         0x03000001
1655 #define  FLASH_VENDOR_SAIFUN             0x01000003
1656 #define  FLASH_VENDOR_SST_SMALL          0x00000001
1657 #define  FLASH_VENDOR_SST_LARGE          0x02000001
1658 #define  NVRAM_CFG1_5752VENDOR_MASK      0x03c00003
1659 #define  FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ     0x00000000
1660 #define  FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ    0x02000000
1661 #define  FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED   0x02000003
1662 #define  FLASH_5752VENDOR_ST_M45PE10     0x02400000
1663 #define  FLASH_5752VENDOR_ST_M45PE20     0x02400002
1664 #define  FLASH_5752VENDOR_ST_M45PE40     0x02400001
1665 #define  FLASH_5755VENDOR_ATMEL_FLASH_1  0x03400001
1666 #define  FLASH_5755VENDOR_ATMEL_FLASH_2  0x03400002
1667 #define  FLASH_5755VENDOR_ATMEL_FLASH_3  0x03400000
1668 #define  FLASH_5755VENDOR_ATMEL_FLASH_4  0x00000003
1669 #define  FLASH_5755VENDOR_ATMEL_FLASH_5  0x02000003
1670 #define  FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ     0x03c00003
1671 #define  FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ    0x03c00002
1672 #define  FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ     0x03000003
1673 #define  FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ    0x03000002
1674 #define  FLASH_5787VENDOR_MICRO_EEPROM_64KHZ     0x03000000
1675 #define  FLASH_5787VENDOR_MICRO_EEPROM_376KHZ    0x02000000
1676 #define  FLASH_5761VENDOR_ATMEL_MDB021D  0x00800003
1677 #define  FLASH_5761VENDOR_ATMEL_MDB041D  0x00800000
1678 #define  FLASH_5761VENDOR_ATMEL_MDB081D  0x00800002
1679 #define  FLASH_5761VENDOR_ATMEL_MDB161D  0x00800001
1680 #define  FLASH_5761VENDOR_ATMEL_ADB021D  0x00000003
1681 #define  FLASH_5761VENDOR_ATMEL_ADB041D  0x00000000
1682 #define  FLASH_5761VENDOR_ATMEL_ADB081D  0x00000002
1683 #define  FLASH_5761VENDOR_ATMEL_ADB161D  0x00000001
1684 #define  FLASH_5761VENDOR_ST_M_M45PE20   0x02800001
1685 #define  FLASH_5761VENDOR_ST_M_M45PE40   0x02800000
1686 #define  FLASH_5761VENDOR_ST_M_M45PE80   0x02800002
1687 #define  FLASH_5761VENDOR_ST_M_M45PE16   0x02800003
1688 #define  FLASH_5761VENDOR_ST_A_M45PE20   0x02000001
1689 #define  FLASH_5761VENDOR_ST_A_M45PE40   0x02000000
1690 #define  FLASH_5761VENDOR_ST_A_M45PE80   0x02000002
1691 #define  FLASH_5761VENDOR_ST_A_M45PE16   0x02000003
1692 #define  FLASH_57780VENDOR_ATMEL_AT45DB011D 0x00400000
1693 #define  FLASH_57780VENDOR_ATMEL_AT45DB011B 0x03400000
1694 #define  FLASH_57780VENDOR_ATMEL_AT45DB021D 0x00400002
1695 #define  FLASH_57780VENDOR_ATMEL_AT45DB021B 0x03400002
1696 #define  FLASH_57780VENDOR_ATMEL_AT45DB041D 0x00400001
1697 #define  FLASH_57780VENDOR_ATMEL_AT45DB041B 0x03400001
1698 #define  FLASH_5717VENDOR_ATMEL_EEPROM   0x02000001
1699 #define  FLASH_5717VENDOR_MICRO_EEPROM   0x02000003
1700 #define  FLASH_5717VENDOR_ATMEL_MDB011D  0x01000001
1701 #define  FLASH_5717VENDOR_ATMEL_MDB021D  0x01000003
1702 #define  FLASH_5717VENDOR_ST_M_M25PE10   0x02000000
1703 #define  FLASH_5717VENDOR_ST_M_M25PE20   0x02000002
1704 #define  FLASH_5717VENDOR_ST_M_M45PE10   0x00000001
1705 #define  FLASH_5717VENDOR_ST_M_M45PE20   0x00000003
1706 #define  FLASH_5717VENDOR_ATMEL_ADB011B  0x01400000
1707 #define  FLASH_5717VENDOR_ATMEL_ADB021B  0x01400002
1708 #define  FLASH_5717VENDOR_ATMEL_ADB011D  0x01400001
1709 #define  FLASH_5717VENDOR_ATMEL_ADB021D  0x01400003
1710 #define  FLASH_5717VENDOR_ST_A_M25PE10   0x02400000
1711 #define  FLASH_5717VENDOR_ST_A_M25PE20   0x02400002
1712 #define  FLASH_5717VENDOR_ST_A_M45PE10   0x02400001
1713 #define  FLASH_5717VENDOR_ST_A_M45PE20   0x02400003
1714 #define  FLASH_5717VENDOR_ATMEL_45USPT   0x03400000
1715 #define  FLASH_5717VENDOR_ST_25USPT      0x03400002
1716 #define  FLASH_5717VENDOR_ST_45USPT      0x03400001
1717 #define  NVRAM_CFG1_5752PAGE_SIZE_MASK   0x70000000
1718 #define  FLASH_5752PAGE_SIZE_256         0x00000000
1719 #define  FLASH_5752PAGE_SIZE_512         0x10000000
1720 #define  FLASH_5752PAGE_SIZE_1K          0x20000000
1721 #define  FLASH_5752PAGE_SIZE_2K          0x30000000
1722 #define  FLASH_5752PAGE_SIZE_4K          0x40000000
1723 #define  FLASH_5752PAGE_SIZE_264         0x50000000
1724 #define  FLASH_5752PAGE_SIZE_528         0x60000000
1725 #define NVRAM_CFG2                      0x00007018
1726 #define NVRAM_CFG3                      0x0000701c
1727 #define NVRAM_SWARB                     0x00007020
1728 #define  SWARB_REQ_SET0                  0x00000001
1729 #define  SWARB_REQ_SET1                  0x00000002
1730 #define  SWARB_REQ_SET2                  0x00000004
1731 #define  SWARB_REQ_SET3                  0x00000008
1732 #define  SWARB_REQ_CLR0                  0x00000010
1733 #define  SWARB_REQ_CLR1                  0x00000020
1734 #define  SWARB_REQ_CLR2                  0x00000040
1735 #define  SWARB_REQ_CLR3                  0x00000080
1736 #define  SWARB_GNT0                      0x00000100
1737 #define  SWARB_GNT1                      0x00000200
1738 #define  SWARB_GNT2                      0x00000400
1739 #define  SWARB_GNT3                      0x00000800
1740 #define  SWARB_REQ0                      0x00001000
1741 #define  SWARB_REQ1                      0x00002000
1742 #define  SWARB_REQ2                      0x00004000
1743 #define  SWARB_REQ3                      0x00008000
1744 #define NVRAM_ACCESS                    0x00007024
1745 #define  ACCESS_ENABLE                   0x00000001
1746 #define  ACCESS_WR_ENABLE                0x00000002
1747 #define NVRAM_WRITE1                    0x00007028
1748 /* 0x702c unused */
1749
1750 #define NVRAM_ADDR_LOCKOUT              0x00007030
1751 /* 0x7034 --> 0x7500 unused */
1752
1753 #define OTP_MODE                        0x00007500
1754 #define OTP_MODE_OTP_THRU_GRC            0x00000001
1755 #define OTP_CTRL                        0x00007504
1756 #define OTP_CTRL_OTP_PROG_ENABLE         0x00200000
1757 #define OTP_CTRL_OTP_CMD_READ            0x00000000
1758 #define OTP_CTRL_OTP_CMD_INIT            0x00000008
1759 #define OTP_CTRL_OTP_CMD_START           0x00000001
1760 #define OTP_STATUS                      0x00007508
1761 #define OTP_STATUS_CMD_DONE              0x00000001
1762 #define OTP_ADDRESS                     0x0000750c
1763 #define OTP_ADDRESS_MAGIC1               0x000000a0
1764 #define OTP_ADDRESS_MAGIC2               0x00000080
1765 /* 0x7510 unused */
1766
1767 #define OTP_READ_DATA                   0x00007514
1768 /* 0x7518 --> 0x7c04 unused */
1769
1770 #define PCIE_TRANSACTION_CFG            0x00007c04
1771 #define PCIE_TRANS_CFG_1SHOT_MSI         0x20000000
1772 #define PCIE_TRANS_CFG_LOM               0x00000020
1773 /* 0x7c08 --> 0x7d28 unused */
1774
1775 #define PCIE_PWR_MGMT_THRESH            0x00007d28
1776 #define PCIE_PWR_MGMT_L1_THRESH_MSK      0x0000ff00
1777 #define PCIE_PWR_MGMT_L1_THRESH_4MS      0x0000ff00
1778 #define PCIE_PWR_MGMT_EXT_ASPM_TMR_EN    0x01000000
1779 /* 0x7d2c --> 0x7d54 unused */
1780
1781 #define TG3_PCIE_LNKCTL                 0x00007d54
1782 #define  TG3_PCIE_LNKCTL_L1_PLL_PD_EN    0x00000008
1783 #define  TG3_PCIE_LNKCTL_L1_PLL_PD_DIS   0x00000080
1784 /* 0x7d58 --> 0x7e70 unused */
1785
1786 #define TG3_PCIE_EIDLE_DELAY            0x00007e70
1787 #define  TG3_PCIE_EIDLE_DELAY_MASK       0x0000001f
1788 #define  TG3_PCIE_EIDLE_DELAY_13_CLKS    0x0000000c
1789 /* 0x7e74 --> 0x8000 unused */
1790
1791
1792 /* OTP bit definitions */
1793 #define TG3_OTP_AGCTGT_MASK             0x000000e0
1794 #define TG3_OTP_AGCTGT_SHIFT            1
1795 #define TG3_OTP_HPFFLTR_MASK            0x00000300
1796 #define TG3_OTP_HPFFLTR_SHIFT           1
1797 #define TG3_OTP_HPFOVER_MASK            0x00000400
1798 #define TG3_OTP_HPFOVER_SHIFT           1
1799 #define TG3_OTP_LPFDIS_MASK             0x00000800
1800 #define TG3_OTP_LPFDIS_SHIFT            11
1801 #define TG3_OTP_VDAC_MASK               0xff000000
1802 #define TG3_OTP_VDAC_SHIFT              24
1803 #define TG3_OTP_10BTAMP_MASK            0x0000f000
1804 #define TG3_OTP_10BTAMP_SHIFT           8
1805 #define TG3_OTP_ROFF_MASK               0x00e00000
1806 #define TG3_OTP_ROFF_SHIFT              11
1807 #define TG3_OTP_RCOFF_MASK              0x001c0000
1808 #define TG3_OTP_RCOFF_SHIFT             16
1809
1810 #define TG3_OTP_DEFAULT                 0x286c1640
1811
1812 /* Hardware Selfboot NVRAM layout */
1813 #define TG3_NVM_HWSB_CFG1               0x00000004
1814 #define  TG3_NVM_HWSB_CFG1_MAJMSK       0xf8000000
1815 #define  TG3_NVM_HWSB_CFG1_MAJSFT       27
1816 #define  TG3_NVM_HWSB_CFG1_MINMSK       0x07c00000
1817 #define  TG3_NVM_HWSB_CFG1_MINSFT       22
1818
1819 #define TG3_EEPROM_MAGIC                0x669955aa
1820 #define TG3_EEPROM_MAGIC_FW             0xa5000000
1821 #define TG3_EEPROM_MAGIC_FW_MSK         0xff000000
1822 #define TG3_EEPROM_SB_FORMAT_MASK       0x00e00000
1823 #define TG3_EEPROM_SB_FORMAT_1          0x00200000
1824 #define TG3_EEPROM_SB_REVISION_MASK     0x001f0000
1825 #define TG3_EEPROM_SB_REVISION_0        0x00000000
1826 #define TG3_EEPROM_SB_REVISION_2        0x00020000
1827 #define TG3_EEPROM_SB_REVISION_3        0x00030000
1828 #define TG3_EEPROM_MAGIC_HW             0xabcd
1829 #define TG3_EEPROM_MAGIC_HW_MSK         0xffff
1830
1831 #define TG3_NVM_DIR_START               0x18
1832 #define TG3_NVM_DIR_END                 0x78
1833 #define TG3_NVM_DIRENT_SIZE             0xc
1834 #define TG3_NVM_DIRTYPE_SHIFT           24
1835 #define TG3_NVM_DIRTYPE_ASFINI          1
1836 #define TG3_NVM_PTREV_BCVER             0x94
1837 #define TG3_NVM_BCVER_MAJMSK            0x0000ff00
1838 #define TG3_NVM_BCVER_MAJSFT            8
1839 #define TG3_NVM_BCVER_MINMSK            0x000000ff
1840
1841 #define TG3_EEPROM_SB_F1R0_EDH_OFF      0x10
1842 #define TG3_EEPROM_SB_F1R2_EDH_OFF      0x14
1843 #define TG3_EEPROM_SB_F1R2_MBA_OFF      0x10
1844 #define TG3_EEPROM_SB_F1R3_EDH_OFF      0x18
1845 #define TG3_EEPROM_SB_EDH_MAJ_MASK      0x00000700
1846 #define TG3_EEPROM_SB_EDH_MAJ_SHFT      8
1847 #define TG3_EEPROM_SB_EDH_MIN_MASK      0x000000ff
1848 #define TG3_EEPROM_SB_EDH_BLD_MASK      0x0000f800
1849 #define TG3_EEPROM_SB_EDH_BLD_SHFT      11
1850
1851
1852 /* 32K Window into NIC internal memory */
1853 #define NIC_SRAM_WIN_BASE               0x00008000
1854
1855 /* Offsets into first 32k of NIC internal memory. */
1856 #define NIC_SRAM_PAGE_ZERO              0x00000000
1857 #define NIC_SRAM_SEND_RCB               0x00000100 /* 16 * TG3_BDINFO_... */
1858 #define NIC_SRAM_RCV_RET_RCB            0x00000200 /* 16 * TG3_BDINFO_... */
1859 #define NIC_SRAM_STATS_BLK              0x00000300
1860 #define NIC_SRAM_STATUS_BLK             0x00000b00
1861
1862 #define NIC_SRAM_FIRMWARE_MBOX          0x00000b50
1863 #define  NIC_SRAM_FIRMWARE_MBOX_MAGIC1   0x4B657654
1864 #define  NIC_SRAM_FIRMWARE_MBOX_MAGIC2   0x4861764b /* !dma on linkchg */
1865
1866 #define NIC_SRAM_DATA_SIG               0x00000b54
1867 #define  NIC_SRAM_DATA_SIG_MAGIC         0x4b657654 /* ascii for 'KevT' */
1868
1869 #define NIC_SRAM_DATA_CFG                       0x00000b58
1870 #define  NIC_SRAM_DATA_CFG_LED_MODE_MASK         0x0000000c
1871 #define  NIC_SRAM_DATA_CFG_LED_MODE_MAC          0x00000000
1872 #define  NIC_SRAM_DATA_CFG_LED_MODE_PHY_1        0x00000004
1873 #define  NIC_SRAM_DATA_CFG_LED_MODE_PHY_2        0x00000008
1874 #define  NIC_SRAM_DATA_CFG_PHY_TYPE_MASK         0x00000030
1875 #define  NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN      0x00000000
1876 #define  NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER       0x00000010
1877 #define  NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER        0x00000020
1878 #define  NIC_SRAM_DATA_CFG_WOL_ENABLE            0x00000040
1879 #define  NIC_SRAM_DATA_CFG_ASF_ENABLE            0x00000080
1880 #define  NIC_SRAM_DATA_CFG_EEPROM_WP             0x00000100
1881 #define  NIC_SRAM_DATA_CFG_MINI_PCI              0x00001000
1882 #define  NIC_SRAM_DATA_CFG_FIBER_WOL             0x00004000
1883 #define  NIC_SRAM_DATA_CFG_NO_GPIO2              0x00100000
1884 #define  NIC_SRAM_DATA_CFG_APE_ENABLE            0x00200000
1885
1886 #define NIC_SRAM_DATA_VER                       0x00000b5c
1887 #define  NIC_SRAM_DATA_VER_SHIFT                 16
1888
1889 #define NIC_SRAM_DATA_PHY_ID            0x00000b74
1890 #define  NIC_SRAM_DATA_PHY_ID1_MASK      0xffff0000
1891 #define  NIC_SRAM_DATA_PHY_ID2_MASK      0x0000ffff
1892
1893 #define NIC_SRAM_FW_CMD_MBOX            0x00000b78
1894 #define  FWCMD_NICDRV_ALIVE              0x00000001
1895 #define  FWCMD_NICDRV_PAUSE_FW           0x00000002
1896 #define  FWCMD_NICDRV_IPV4ADDR_CHG       0x00000003
1897 #define  FWCMD_NICDRV_IPV6ADDR_CHG       0x00000004
1898 #define  FWCMD_NICDRV_FIX_DMAR           0x00000005
1899 #define  FWCMD_NICDRV_FIX_DMAW           0x00000006
1900 #define  FWCMD_NICDRV_LINK_UPDATE        0x0000000c
1901 #define  FWCMD_NICDRV_ALIVE2             0x0000000d
1902 #define  FWCMD_NICDRV_ALIVE3             0x0000000e
1903 #define NIC_SRAM_FW_CMD_LEN_MBOX        0x00000b7c
1904 #define NIC_SRAM_FW_CMD_DATA_MBOX       0x00000b80
1905 #define NIC_SRAM_FW_ASF_STATUS_MBOX     0x00000c00
1906 #define NIC_SRAM_FW_DRV_STATE_MBOX      0x00000c04
1907 #define  DRV_STATE_START                 0x00000001
1908 #define  DRV_STATE_START_DONE            0x80000001
1909 #define  DRV_STATE_UNLOAD                0x00000002
1910 #define  DRV_STATE_UNLOAD_DONE           0x80000002
1911 #define  DRV_STATE_WOL                   0x00000003
1912 #define  DRV_STATE_SUSPEND               0x00000004
1913
1914 #define NIC_SRAM_FW_RESET_TYPE_MBOX     0x00000c08
1915
1916 #define NIC_SRAM_MAC_ADDR_HIGH_MBOX     0x00000c14
1917 #define NIC_SRAM_MAC_ADDR_LOW_MBOX      0x00000c18
1918
1919 #define NIC_SRAM_WOL_MBOX               0x00000d30
1920 #define  WOL_SIGNATURE                   0x474c0000
1921 #define  WOL_DRV_STATE_SHUTDOWN          0x00000001
1922 #define  WOL_DRV_WOL                     0x00000002
1923 #define  WOL_SET_MAGIC_PKT               0x00000004
1924
1925 #define NIC_SRAM_DATA_CFG_2             0x00000d38
1926
1927 #define  NIC_SRAM_DATA_CFG_2_APD_EN      0x00000400
1928 #define  SHASTA_EXT_LED_MODE_MASK        0x00018000
1929 #define  SHASTA_EXT_LED_LEGACY           0x00000000
1930 #define  SHASTA_EXT_LED_SHARED           0x00008000
1931 #define  SHASTA_EXT_LED_MAC              0x00010000
1932 #define  SHASTA_EXT_LED_COMBO            0x00018000
1933
1934 #define NIC_SRAM_DATA_CFG_3             0x00000d3c
1935 #define  NIC_SRAM_ASPM_DEBOUNCE          0x00000002
1936
1937 #define NIC_SRAM_DATA_CFG_4             0x00000d60
1938 #define  NIC_SRAM_GMII_MODE              0x00000002
1939 #define  NIC_SRAM_RGMII_STD_IBND_DISABLE 0x00000004
1940 #define  NIC_SRAM_RGMII_EXT_IBND_RX_EN   0x00000008
1941 #define  NIC_SRAM_RGMII_EXT_IBND_TX_EN   0x00000010
1942
1943 #define NIC_SRAM_RX_MINI_BUFFER_DESC    0x00001000
1944
1945 #define NIC_SRAM_DMA_DESC_POOL_BASE     0x00002000
1946 #define  NIC_SRAM_DMA_DESC_POOL_SIZE     0x00002000
1947 #define NIC_SRAM_TX_BUFFER_DESC         0x00004000 /* 512 entries */
1948 #define NIC_SRAM_RX_BUFFER_DESC         0x00006000 /* 256 entries */
1949 #define NIC_SRAM_RX_JUMBO_BUFFER_DESC   0x00007000 /* 256 entries */
1950 #define NIC_SRAM_MBUF_POOL_BASE         0x00008000
1951 #define  NIC_SRAM_MBUF_POOL_SIZE96       0x00018000
1952 #define  NIC_SRAM_MBUF_POOL_SIZE64       0x00010000
1953 #define  NIC_SRAM_MBUF_POOL_BASE5705    0x00010000
1954 #define  NIC_SRAM_MBUF_POOL_SIZE5705    0x0000e000
1955
1956 /* Currently this is fixed. */
1957 #define PHY_ADDR                0x01
1958
1959 /* Tigon3 specific PHY MII registers. */
1960 #define  TG3_BMCR_SPEED1000             0x0040
1961
1962 #define MII_TG3_CTRL                    0x09 /* 1000-baseT control register */
1963 #define  MII_TG3_CTRL_ADV_1000_HALF     0x0100
1964 #define  MII_TG3_CTRL_ADV_1000_FULL     0x0200
1965 #define  MII_TG3_CTRL_AS_MASTER         0x0800
1966 #define  MII_TG3_CTRL_ENABLE_AS_MASTER  0x1000
1967
1968 #define MII_TG3_EXT_CTRL                0x10 /* Extended control register */
1969 #define  MII_TG3_EXT_CTRL_FIFO_ELASTIC  0x0001
1970 #define  MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002
1971 #define  MII_TG3_EXT_CTRL_FORCE_LED_OFF 0x0008
1972 #define  MII_TG3_EXT_CTRL_TBI           0x8000
1973
1974 #define MII_TG3_EXT_STAT                0x11 /* Extended status register */
1975 #define  MII_TG3_EXT_STAT_LPASS         0x0100
1976
1977 #define MII_TG3_DSP_RW_PORT             0x15 /* DSP coefficient read/write port */
1978
1979 #define MII_TG3_DSP_ADDRESS             0x17 /* DSP address register */
1980
1981 #define MII_TG3_DSP_TAP1                0x0001
1982 #define  MII_TG3_DSP_TAP1_AGCTGT_DFLT   0x0007
1983 #define MII_TG3_DSP_AADJ1CH0            0x001f
1984 #define MII_TG3_DSP_AADJ1CH3            0x601f
1985 #define  MII_TG3_DSP_AADJ1CH3_ADCCKADJ  0x0002
1986 #define MII_TG3_DSP_EXP8                0x0708
1987 #define  MII_TG3_DSP_EXP8_REJ2MHz       0x0001
1988 #define  MII_TG3_DSP_EXP8_AEDW          0x0200
1989 #define MII_TG3_DSP_EXP75               0x0f75
1990 #define MII_TG3_DSP_EXP96               0x0f96
1991 #define MII_TG3_DSP_EXP97               0x0f97
1992
1993 #define MII_TG3_AUX_CTRL                0x18 /* auxilliary control register */
1994
1995 #define MII_TG3_AUXCTL_PCTL_100TX_LPWR  0x0010
1996 #define MII_TG3_AUXCTL_PCTL_SPR_ISOLATE 0x0020
1997 #define MII_TG3_AUXCTL_PCTL_VREG_11V    0x0180
1998 #define MII_TG3_AUXCTL_SHDWSEL_PWRCTL   0x0002
1999
2000 #define MII_TG3_AUXCTL_MISC_WREN        0x8000
2001 #define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200
2002 #define MII_TG3_AUXCTL_MISC_RDSEL_MISC  0x7000
2003 #define MII_TG3_AUXCTL_SHDWSEL_MISC     0x0007
2004
2005 #define MII_TG3_AUXCTL_ACTL_SMDSP_ENA   0x0800
2006 #define MII_TG3_AUXCTL_ACTL_TX_6DB      0x0400
2007 #define MII_TG3_AUXCTL_SHDWSEL_AUXCTL   0x0000
2008
2009 #define MII_TG3_AUX_STAT                0x19 /* auxilliary status register */
2010 #define MII_TG3_AUX_STAT_LPASS          0x0004
2011 #define MII_TG3_AUX_STAT_SPDMASK        0x0700
2012 #define MII_TG3_AUX_STAT_10HALF         0x0100
2013 #define MII_TG3_AUX_STAT_10FULL         0x0200
2014 #define MII_TG3_AUX_STAT_100HALF        0x0300
2015 #define MII_TG3_AUX_STAT_100_4          0x0400
2016 #define MII_TG3_AUX_STAT_100FULL        0x0500
2017 #define MII_TG3_AUX_STAT_1000HALF       0x0600
2018 #define MII_TG3_AUX_STAT_1000FULL       0x0700
2019 #define MII_TG3_AUX_STAT_100            0x0008
2020 #define MII_TG3_AUX_STAT_FULL           0x0001
2021
2022 #define MII_TG3_ISTAT                   0x1a /* IRQ status register */
2023 #define MII_TG3_IMASK                   0x1b /* IRQ mask register */
2024
2025 /* ISTAT/IMASK event bits */
2026 #define MII_TG3_INT_LINKCHG             0x0002
2027 #define MII_TG3_INT_SPEEDCHG            0x0004
2028 #define MII_TG3_INT_DUPLEXCHG           0x0008
2029 #define MII_TG3_INT_ANEG_PAGE_RX        0x0400
2030
2031 #define MII_TG3_MISC_SHDW               0x1c
2032 #define MII_TG3_MISC_SHDW_WREN          0x8000
2033
2034 #define MII_TG3_MISC_SHDW_APD_WKTM_84MS 0x0001
2035 #define MII_TG3_MISC_SHDW_APD_ENABLE    0x0020
2036 #define MII_TG3_MISC_SHDW_APD_SEL       0x2800
2037
2038 #define MII_TG3_MISC_SHDW_SCR5_C125OE   0x0001
2039 #define MII_TG3_MISC_SHDW_SCR5_DLLAPD   0x0002
2040 #define MII_TG3_MISC_SHDW_SCR5_SDTL     0x0004
2041 #define MII_TG3_MISC_SHDW_SCR5_DLPTLM   0x0008
2042 #define MII_TG3_MISC_SHDW_SCR5_LPED     0x0010
2043 #define MII_TG3_MISC_SHDW_SCR5_SEL      0x1400
2044
2045 #define MII_TG3_TEST1                   0x1e
2046 #define MII_TG3_TEST1_TRIM_EN           0x0010
2047 #define MII_TG3_TEST1_CRC_EN            0x8000
2048
2049
2050 /* Fast Ethernet Tranceiver definitions */
2051 #define MII_TG3_FET_PTEST               0x17
2052 #define MII_TG3_FET_TEST                0x1f
2053 #define  MII_TG3_FET_SHADOW_EN          0x0080
2054
2055 #define MII_TG3_FET_SHDW_MISCCTRL       0x10
2056 #define  MII_TG3_FET_SHDW_MISCCTRL_MDIX 0x4000
2057
2058 #define MII_TG3_FET_SHDW_AUXSTAT2       0x1b
2059 #define  MII_TG3_FET_SHDW_AUXSTAT2_APD  0x0020
2060
2061
2062 /* APE registers.  Accessible through BAR1 */
2063 #define TG3_APE_EVENT                   0x000c
2064 #define  APE_EVENT_1                     0x00000001
2065 #define TG3_APE_LOCK_REQ                0x002c
2066 #define  APE_LOCK_REQ_DRIVER             0x00001000
2067 #define TG3_APE_LOCK_GRANT              0x004c
2068 #define  APE_LOCK_GRANT_DRIVER           0x00001000
2069 #define TG3_APE_SEG_SIG                 0x4000
2070 #define  APE_SEG_SIG_MAGIC               0x41504521
2071
2072 /* APE shared memory.  Accessible through BAR1 */
2073 #define TG3_APE_FW_STATUS               0x400c
2074 #define  APE_FW_STATUS_READY             0x00000100
2075 #define TG3_APE_FW_VERSION              0x4018
2076 #define  APE_FW_VERSION_MAJMSK           0xff000000
2077 #define  APE_FW_VERSION_MAJSFT           24
2078 #define  APE_FW_VERSION_MINMSK           0x00ff0000
2079 #define  APE_FW_VERSION_MINSFT           16
2080 #define  APE_FW_VERSION_REVMSK           0x0000ff00
2081 #define  APE_FW_VERSION_REVSFT           8
2082 #define  APE_FW_VERSION_BLDMSK           0x000000ff
2083 #define TG3_APE_HOST_SEG_SIG            0x4200
2084 #define  APE_HOST_SEG_SIG_MAGIC          0x484f5354
2085 #define TG3_APE_HOST_SEG_LEN            0x4204
2086 #define  APE_HOST_SEG_LEN_MAGIC          0x0000001c
2087 #define TG3_APE_HOST_INIT_COUNT         0x4208
2088 #define TG3_APE_HOST_DRIVER_ID          0x420c
2089 #define  APE_HOST_DRIVER_ID_MAGIC        0xf0035100
2090 #define TG3_APE_HOST_BEHAVIOR           0x4210
2091 #define  APE_HOST_BEHAV_NO_PHYLOCK       0x00000001
2092 #define TG3_APE_HOST_HEARTBEAT_INT_MS   0x4214
2093 #define  APE_HOST_HEARTBEAT_INT_DISABLE  0
2094 #define  APE_HOST_HEARTBEAT_INT_5SEC     5000
2095 #define TG3_APE_HOST_HEARTBEAT_COUNT    0x4218
2096
2097 #define TG3_APE_EVENT_STATUS            0x4300
2098
2099 #define  APE_EVENT_STATUS_DRIVER_EVNT    0x00000010
2100 #define  APE_EVENT_STATUS_STATE_CHNGE    0x00000500
2101 #define  APE_EVENT_STATUS_STATE_START    0x00010000
2102 #define  APE_EVENT_STATUS_STATE_UNLOAD   0x00020000
2103 #define  APE_EVENT_STATUS_STATE_WOL      0x00030000
2104 #define  APE_EVENT_STATUS_STATE_SUSPEND  0x00040000
2105 #define  APE_EVENT_STATUS_EVENT_PENDING  0x80000000
2106
2107 /* APE convenience enumerations. */
2108 #define TG3_APE_LOCK_GRC                1
2109 #define TG3_APE_LOCK_MEM                4
2110
2111 #define TG3_EEPROM_SB_F1R2_MBA_OFF      0x10
2112
2113
2114 /* There are two ways to manage the TX descriptors on the tigon3.
2115  * Either the descriptors are in host DMA'able memory, or they
2116  * exist only in the cards on-chip SRAM.  All 16 send bds are under
2117  * the same mode, they may not be configured individually.
2118  *
2119  * This driver always uses host memory TX descriptors.
2120  *
2121  * To use host memory TX descriptors:
2122  *      1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register.
2123  *         Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear.
2124  *      2) Allocate DMA'able memory.
2125  *      3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
2126  *         a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory
2127  *            obtained in step 2
2128  *         b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC.
2129  *         c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number
2130  *            of TX descriptors.  Leave flags field clear.
2131  *      4) Access TX descriptors via host memory.  The chip
2132  *         will refetch into local SRAM as needed when producer
2133  *         index mailboxes are updated.
2134  *
2135  * To use on-chip TX descriptors:
2136  *      1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register.
2137  *         Make sure GRC_MODE_HOST_SENDBDS is clear.
2138  *      2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
2139  *         a) Set TG3_BDINFO_HOST_ADDR to zero.
2140  *         b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC
2141  *         c) TG3_BDINFO_MAXLEN_FLAGS is don't care.
2142  *      3) Access TX descriptors directly in on-chip SRAM
2143  *         using normal {read,write}l().  (and not using
2144  *         pointer dereferencing of ioremap()'d memory like
2145  *         the broken Broadcom driver does)
2146  *
2147  * Note that BDINFO_FLAGS_DISABLED should be set in the flags field of
2148  * TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices.
2149  */
2150 struct tg3_tx_buffer_desc {
2151         u32                             addr_hi;
2152         u32                             addr_lo;
2153
2154         u32                             len_flags;
2155 #define TXD_FLAG_TCPUDP_CSUM            0x0001
2156 #define TXD_FLAG_IP_CSUM                0x0002
2157 #define TXD_FLAG_END                    0x0004
2158 #define TXD_FLAG_IP_FRAG                0x0008
2159 #define TXD_FLAG_JMB_PKT                0x0008
2160 #define TXD_FLAG_IP_FRAG_END            0x0010
2161 #define TXD_FLAG_VLAN                   0x0040
2162 #define TXD_FLAG_COAL_NOW               0x0080
2163 #define TXD_FLAG_CPU_PRE_DMA            0x0100
2164 #define TXD_FLAG_CPU_POST_DMA           0x0200
2165 #define TXD_FLAG_ADD_SRC_ADDR           0x1000
2166 #define TXD_FLAG_CHOOSE_SRC_ADDR        0x6000
2167 #define TXD_FLAG_NO_CRC                 0x8000
2168 #define TXD_LEN_SHIFT                   16
2169
2170         u32                             vlan_tag;
2171 #define TXD_VLAN_TAG_SHIFT              0
2172 #define TXD_MSS_SHIFT                   16
2173 };
2174
2175 #define TXD_ADDR                        0x00UL /* 64-bit */
2176 #define TXD_LEN_FLAGS                   0x08UL /* 32-bit (upper 16-bits are len) */
2177 #define TXD_VLAN_TAG                    0x0cUL /* 32-bit (upper 16-bits are tag) */
2178 #define TXD_SIZE                        0x10UL
2179
2180 struct tg3_rx_buffer_desc {
2181         u32                             addr_hi;
2182         u32                             addr_lo;
2183
2184         u32                             idx_len;
2185 #define RXD_IDX_MASK    0xffff0000
2186 #define RXD_IDX_SHIFT   16
2187 #define RXD_LEN_MASK    0x0000ffff
2188 #define RXD_LEN_SHIFT   0
2189
2190         u32                             type_flags;
2191 #define RXD_TYPE_SHIFT  16
2192 #define RXD_FLAGS_SHIFT 0
2193
2194 #define RXD_FLAG_END                    0x0004
2195 #define RXD_FLAG_MINI                   0x0800
2196 #define RXD_FLAG_JUMBO                  0x0020
2197 #define RXD_FLAG_VLAN                   0x0040
2198 #define RXD_FLAG_ERROR                  0x0400
2199 #define RXD_FLAG_IP_CSUM                0x1000
2200 #define RXD_FLAG_TCPUDP_CSUM            0x2000
2201 #define RXD_FLAG_IS_TCP                 0x4000
2202
2203         u32                             ip_tcp_csum;
2204 #define RXD_IPCSUM_MASK         0xffff0000
2205 #define RXD_IPCSUM_SHIFT        16
2206 #define RXD_TCPCSUM_MASK        0x0000ffff
2207 #define RXD_TCPCSUM_SHIFT       0
2208
2209         u32                             err_vlan;
2210
2211 #define RXD_VLAN_MASK                   0x0000ffff
2212
2213 #define RXD_ERR_BAD_CRC                 0x00010000
2214 #define RXD_ERR_COLLISION               0x00020000
2215 #define RXD_ERR_LINK_LOST               0x00040000
2216 #define RXD_ERR_PHY_DECODE              0x00080000
2217 #define RXD_ERR_ODD_NIBBLE_RCVD_MII     0x00100000
2218 #define RXD_ERR_MAC_ABRT                0x00200000
2219 #define RXD_ERR_TOO_SMALL               0x00400000
2220 #define RXD_ERR_NO_RESOURCES            0x00800000
2221 #define RXD_ERR_HUGE_FRAME              0x01000000
2222 #define RXD_ERR_MASK                    0xffff0000
2223
2224         u32                             reserved;
2225         u32                             opaque;
2226 #define RXD_OPAQUE_INDEX_MASK           0x0000ffff
2227 #define RXD_OPAQUE_INDEX_SHIFT          0
2228 #define RXD_OPAQUE_RING_STD             0x00010000
2229 #define RXD_OPAQUE_RING_JUMBO           0x00020000
2230 #define RXD_OPAQUE_RING_MINI            0x00040000
2231 #define RXD_OPAQUE_RING_MASK            0x00070000
2232 };
2233
2234 struct tg3_ext_rx_buffer_desc {
2235         struct {
2236                 u32                     addr_hi;
2237                 u32                     addr_lo;
2238         }                               addrlist[3];
2239         u32                             len2_len1;
2240         u32                             resv_len3;
2241         struct tg3_rx_buffer_desc       std;
2242 };
2243
2244 /* We only use this when testing out the DMA engine
2245  * at probe time.  This is the internal format of buffer
2246  * descriptors used by the chip at NIC_SRAM_DMA_DESCS.
2247  */
2248 struct tg3_internal_buffer_desc {
2249         u32                             addr_hi;
2250         u32                             addr_lo;
2251         u32                             nic_mbuf;
2252         /* XXX FIX THIS */
2253 #ifdef __BIG_ENDIAN
2254         u16                             cqid_sqid;
2255         u16                             len;
2256 #else
2257         u16                             len;
2258         u16                             cqid_sqid;
2259 #endif
2260         u32                             flags;
2261         u32                             __cookie1;
2262         u32                             __cookie2;
2263         u32                             __cookie3;
2264 };
2265
2266 #define TG3_HW_STATUS_SIZE              0x50
2267 struct tg3_hw_status {
2268         u32                             status;
2269 #define SD_STATUS_UPDATED               0x00000001
2270 #define SD_STATUS_LINK_CHG              0x00000002
2271 #define SD_STATUS_ERROR                 0x00000004
2272
2273         u32                             status_tag;
2274
2275 #ifdef __BIG_ENDIAN
2276         u16                             rx_consumer;
2277         u16                             rx_jumbo_consumer;
2278 #else
2279         u16                             rx_jumbo_consumer;
2280         u16                             rx_consumer;
2281 #endif
2282
2283 #ifdef __BIG_ENDIAN
2284         u16                             reserved;
2285         u16                             rx_mini_consumer;
2286 #else
2287         u16                             rx_mini_consumer;
2288         u16                             reserved;
2289 #endif
2290         struct {
2291 #ifdef __BIG_ENDIAN
2292                 u16                     tx_consumer;
2293                 u16                     rx_producer;
2294 #else
2295                 u16                     rx_producer;
2296                 u16                     tx_consumer;
2297 #endif
2298         }                               idx[16];
2299 };
2300
2301 typedef struct {
2302         u32 high, low;
2303 } tg3_stat64_t;
2304
2305 struct tg3_hw_stats {
2306         u8                              __reserved0[0x400-0x300];
2307
2308         /* Statistics maintained by Receive MAC. */
2309         tg3_stat64_t                    rx_octets;
2310         u64                             __reserved1;
2311         tg3_stat64_t                    rx_fragments;
2312         tg3_stat64_t                    rx_ucast_packets;
2313         tg3_stat64_t                    rx_mcast_packets;
2314         tg3_stat64_t                    rx_bcast_packets;
2315         tg3_stat64_t                    rx_fcs_errors;
2316         tg3_stat64_t                    rx_align_errors;
2317         tg3_stat64_t                    rx_xon_pause_rcvd;
2318         tg3_stat64_t                    rx_xoff_pause_rcvd;
2319         tg3_stat64_t                    rx_mac_ctrl_rcvd;
2320         tg3_stat64_t                    rx_xoff_entered;
2321         tg3_stat64_t                    rx_frame_too_long_errors;
2322         tg3_stat64_t                    rx_jabbers;
2323         tg3_stat64_t                    rx_undersize_packets;
2324         tg3_stat64_t                    rx_in_length_errors;
2325         tg3_stat64_t                    rx_out_length_errors;
2326         tg3_stat64_t                    rx_64_or_less_octet_packets;
2327         tg3_stat64_t                    rx_65_to_127_octet_packets;
2328         tg3_stat64_t                    rx_128_to_255_octet_packets;
2329         tg3_stat64_t                    rx_256_to_511_octet_packets;
2330         tg3_stat64_t                    rx_512_to_1023_octet_packets;
2331         tg3_stat64_t                    rx_1024_to_1522_octet_packets;
2332         tg3_stat64_t                    rx_1523_to_2047_octet_packets;
2333         tg3_stat64_t                    rx_2048_to_4095_octet_packets;
2334         tg3_stat64_t                    rx_4096_to_8191_octet_packets;
2335         tg3_stat64_t                    rx_8192_to_9022_octet_packets;
2336
2337         u64                             __unused0[37];
2338
2339         /* Statistics maintained by Transmit MAC. */
2340         tg3_stat64_t                    tx_octets;
2341         u64                             __reserved2;
2342         tg3_stat64_t                    tx_collisions;
2343         tg3_stat64_t                    tx_xon_sent;
2344         tg3_stat64_t                    tx_xoff_sent;
2345         tg3_stat64_t                    tx_flow_control;
2346         tg3_stat64_t                    tx_mac_errors;
2347         tg3_stat64_t                    tx_single_collisions;
2348         tg3_stat64_t                    tx_mult_collisions;
2349         tg3_stat64_t                    tx_deferred;
2350         u64                             __reserved3;
2351         tg3_stat64_t                    tx_excessive_collisions;
2352         tg3_stat64_t                    tx_late_collisions;
2353         tg3_stat64_t                    tx_collide_2times;
2354         tg3_stat64_t                    tx_collide_3times;
2355         tg3_stat64_t                    tx_collide_4times;
2356         tg3_stat64_t                    tx_collide_5times;
2357         tg3_stat64_t                    tx_collide_6times;
2358         tg3_stat64_t                    tx_collide_7times;
2359         tg3_stat64_t                    tx_collide_8times;
2360         tg3_stat64_t                    tx_collide_9times;
2361         tg3_stat64_t                    tx_collide_10times;
2362         tg3_stat64_t                    tx_collide_11times;
2363         tg3_stat64_t                    tx_collide_12times;
2364         tg3_stat64_t                    tx_collide_13times;
2365         tg3_stat64_t                    tx_collide_14times;
2366         tg3_stat64_t                    tx_collide_15times;
2367         tg3_stat64_t                    tx_ucast_packets;
2368         tg3_stat64_t                    tx_mcast_packets;
2369         tg3_stat64_t                    tx_bcast_packets;
2370         tg3_stat64_t                    tx_carrier_sense_errors;
2371         tg3_stat64_t                    tx_discards;
2372         tg3_stat64_t                    tx_errors;
2373
2374         u64                             __unused1[31];
2375
2376         /* Statistics maintained by Receive List Placement. */
2377         tg3_stat64_t                    COS_rx_packets[16];
2378         tg3_stat64_t                    COS_rx_filter_dropped;
2379         tg3_stat64_t                    dma_writeq_full;
2380         tg3_stat64_t                    dma_write_prioq_full;
2381         tg3_stat64_t                    rxbds_empty;
2382         tg3_stat64_t                    rx_discards;
2383         tg3_stat64_t                    rx_errors;
2384         tg3_stat64_t                    rx_threshold_hit;
2385
2386         u64                             __unused2[9];
2387
2388         /* Statistics maintained by Send Data Initiator. */
2389         tg3_stat64_t                    COS_out_packets[16];
2390         tg3_stat64_t                    dma_readq_full;
2391         tg3_stat64_t                    dma_read_prioq_full;
2392         tg3_stat64_t                    tx_comp_queue_full;
2393
2394         /* Statistics maintained by Host Coalescing. */
2395         tg3_stat64_t                    ring_set_send_prod_index;
2396         tg3_stat64_t                    ring_status_update;
2397         tg3_stat64_t                    nic_irqs;
2398         tg3_stat64_t                    nic_avoided_irqs;
2399         tg3_stat64_t                    nic_tx_threshold_hit;
2400
2401         u8                              __reserved4[0xb00-0x9c0];
2402 };
2403
2404 /* 'mapping' is superfluous as the chip does not write into
2405  * the tx/rx post rings so we could just fetch it from there.
2406  * But the cache behavior is better how we are doing it now.
2407  */
2408 struct ring_info {
2409         struct sk_buff                  *skb;
2410         DECLARE_PCI_UNMAP_ADDR(mapping)
2411 };
2412
2413 struct tx_ring_info {
2414         struct sk_buff                  *skb;
2415         u32                             prev_vlan_tag;
2416 };
2417
2418 struct tg3_config_info {
2419         u32                             flags;
2420 };
2421
2422 struct tg3_link_config {
2423         /* Describes what we're trying to get. */
2424         u32                             advertising;
2425         u16                             speed;
2426         u8                              duplex;
2427         u8                              autoneg;
2428         u8                              flowctrl;
2429
2430         /* Describes what we actually have. */
2431         u8                              active_flowctrl;
2432
2433         u8                              active_duplex;
2434 #define SPEED_INVALID           0xffff
2435 #define DUPLEX_INVALID          0xff
2436 #define AUTONEG_INVALID         0xff
2437         u16                             active_speed;
2438
2439         /* When we go in and out of low power mode we need
2440          * to swap with this state.
2441          */
2442         int                             phy_is_low_power;
2443         u16                             orig_speed;
2444         u8                              orig_duplex;
2445         u8                              orig_autoneg;
2446         u32                             orig_advertising;
2447 };
2448
2449 struct tg3_bufmgr_config {
2450         u32             mbuf_read_dma_low_water;
2451         u32             mbuf_mac_rx_low_water;
2452         u32             mbuf_high_water;
2453
2454         u32             mbuf_read_dma_low_water_jumbo;
2455         u32             mbuf_mac_rx_low_water_jumbo;
2456         u32             mbuf_high_water_jumbo;
2457
2458         u32             dma_low_water;
2459         u32             dma_high_water;
2460 };
2461
2462 struct tg3_ethtool_stats {
2463         /* Statistics maintained by Receive MAC. */
2464         u64             rx_octets;
2465         u64             rx_fragments;
2466         u64             rx_ucast_packets;
2467         u64             rx_mcast_packets;
2468         u64             rx_bcast_packets;
2469         u64             rx_fcs_errors;
2470         u64             rx_align_errors;
2471         u64             rx_xon_pause_rcvd;
2472         u64             rx_xoff_pause_rcvd;
2473         u64             rx_mac_ctrl_rcvd;
2474         u64             rx_xoff_entered;
2475         u64             rx_frame_too_long_errors;
2476         u64             rx_jabbers;
2477         u64             rx_undersize_packets;
2478         u64             rx_in_length_errors;
2479         u64             rx_out_length_errors;
2480         u64             rx_64_or_less_octet_packets;
2481         u64             rx_65_to_127_octet_packets;
2482         u64             rx_128_to_255_octet_packets;
2483         u64             rx_256_to_511_octet_packets;
2484         u64             rx_512_to_1023_octet_packets;
2485         u64             rx_1024_to_1522_octet_packets;
2486         u64             rx_1523_to_2047_octet_packets;
2487         u64             rx_2048_to_4095_octet_packets;
2488         u64             rx_4096_to_8191_octet_packets;
2489         u64             rx_8192_to_9022_octet_packets;
2490
2491         /* Statistics maintained by Transmit MAC. */
2492         u64             tx_octets;
2493         u64             tx_collisions;
2494         u64             tx_xon_sent;
2495         u64             tx_xoff_sent;
2496         u64             tx_flow_control;
2497         u64             tx_mac_errors;
2498         u64             tx_single_collisions;
2499         u64             tx_mult_collisions;
2500         u64             tx_deferred;
2501         u64             tx_excessive_collisions;
2502         u64             tx_late_collisions;
2503         u64             tx_collide_2times;
2504         u64             tx_collide_3times;
2505         u64             tx_collide_4times;
2506         u64             tx_collide_5times;
2507         u64             tx_collide_6times;
2508         u64             tx_collide_7times;
2509         u64             tx_collide_8times;
2510         u64             tx_collide_9times;
2511         u64             tx_collide_10times;
2512         u64             tx_collide_11times;
2513         u64             tx_collide_12times;
2514         u64             tx_collide_13times;
2515         u64             tx_collide_14times;
2516         u64             tx_collide_15times;
2517         u64             tx_ucast_packets;
2518         u64             tx_mcast_packets;
2519         u64             tx_bcast_packets;
2520         u64             tx_carrier_sense_errors;
2521         u64             tx_discards;
2522         u64             tx_errors;
2523
2524         /* Statistics maintained by Receive List Placement. */
2525         u64             dma_writeq_full;
2526         u64             dma_write_prioq_full;
2527         u64             rxbds_empty;
2528         u64             rx_discards;
2529         u64             rx_errors;
2530         u64             rx_threshold_hit;
2531
2532         /* Statistics maintained by Send Data Initiator. */
2533         u64             dma_readq_full;
2534         u64             dma_read_prioq_full;
2535         u64             tx_comp_queue_full;
2536
2537         /* Statistics maintained by Host Coalescing. */
2538         u64             ring_set_send_prod_index;
2539         u64             ring_status_update;
2540         u64             nic_irqs;
2541         u64             nic_avoided_irqs;
2542         u64             nic_tx_threshold_hit;
2543 };
2544
2545 struct tg3_rx_prodring_set {
2546         u32                             rx_std_ptr;
2547         u32                             rx_jmb_ptr;
2548         struct tg3_rx_buffer_desc       *rx_std;
2549         struct tg3_ext_rx_buffer_desc   *rx_jmb;
2550         struct ring_info                *rx_std_buffers;
2551         struct ring_info                *rx_jmb_buffers;
2552         dma_addr_t                      rx_std_mapping;
2553         dma_addr_t                      rx_jmb_mapping;
2554 };
2555
2556 #define TG3_IRQ_MAX_VECS 5
2557
2558 struct tg3_napi {
2559         struct napi_struct              napi    ____cacheline_aligned;
2560         struct tg3                      *tp;
2561         struct tg3_hw_status            *hw_status;
2562
2563         u32                             last_tag;
2564         u32                             last_irq_tag;
2565         u32                             int_mbox;
2566         u32                             coal_now;
2567         u32                             tx_prod;
2568         u32                             tx_cons;
2569         u32                             tx_pending;
2570         u32                             prodmbox;
2571
2572         u32                             consmbox;
2573         u32                             rx_rcb_ptr;
2574         u16                             *rx_rcb_prod_idx;
2575
2576         struct tg3_rx_buffer_desc       *rx_rcb;
2577         struct tg3_tx_buffer_desc       *tx_ring;
2578         struct tx_ring_info             *tx_buffers;
2579
2580         dma_addr_t                      status_mapping;
2581         dma_addr_t                      rx_rcb_mapping;
2582         dma_addr_t                      tx_desc_mapping;
2583
2584         char                            irq_lbl[IFNAMSIZ];
2585         unsigned int                    irq_vec;
2586 };
2587
2588 struct tg3 {
2589         /* begin "general, frequently-used members" cacheline section */
2590
2591         /* If the IRQ handler (which runs lockless) needs to be
2592          * quiesced, the following bitmask state is used.  The
2593          * SYNC flag is set by non-IRQ context code to initiate
2594          * the quiescence.
2595          *
2596          * When the IRQ handler notices that SYNC is set, it
2597          * disables interrupts and returns.
2598          *
2599          * When all outstanding IRQ handlers have returned after
2600          * the SYNC flag has been set, the setter can be assured
2601          * that interrupts will no longer get run.
2602          *
2603          * In this way all SMP driver locks are never acquired
2604          * in hw IRQ context, only sw IRQ context or lower.
2605          */
2606         unsigned int                    irq_sync;
2607
2608         /* SMP locking strategy:
2609          *
2610          * lock: Held during reset, PHY access, timer, and when
2611          *       updating tg3_flags and tg3_flags2.
2612          *
2613          * netif_tx_lock: Held during tg3_start_xmit. tg3_tx holds
2614          *                netif_tx_lock when it needs to call
2615          *                netif_wake_queue.
2616          *
2617          * Both of these locks are to be held with BH safety.
2618          *
2619          * Because the IRQ handler, tg3_poll, and tg3_start_xmit
2620          * are running lockless, it is necessary to completely
2621          * quiesce the chip with tg3_netif_stop and tg3_full_lock
2622          * before reconfiguring the device.
2623          *
2624          * indirect_lock: Held when accessing registers indirectly
2625          *                with IRQ disabling.
2626          */
2627         spinlock_t                      lock;
2628         spinlock_t                      indirect_lock;
2629
2630         u32                             (*read32) (struct tg3 *, u32);
2631         void                            (*write32) (struct tg3 *, u32, u32);
2632         u32                             (*read32_mbox) (struct tg3 *, u32);
2633         void                            (*write32_mbox) (struct tg3 *, u32,
2634                                                          u32);
2635         void __iomem                    *regs;
2636         void __iomem                    *aperegs;
2637         struct net_device               *dev;
2638         struct pci_dev                  *pdev;
2639
2640         u32                             msg_enable;
2641
2642         /* begin "tx thread" cacheline section */
2643         void                            (*write32_tx_mbox) (struct tg3 *, u32,
2644                                                             u32);
2645
2646         /* begin "rx thread" cacheline section */
2647         struct tg3_napi                 napi[TG3_IRQ_MAX_VECS];
2648         void                            (*write32_rx_mbox) (struct tg3 *, u32,
2649                                                             u32);
2650         u32                             rx_pending;
2651         u32                             rx_jumbo_pending;
2652         u32                             rx_std_max_post;
2653         u32                             rx_pkt_map_sz;
2654 #if TG3_VLAN_TAG_USED
2655         struct vlan_group               *vlgrp;
2656 #endif
2657
2658         struct tg3_rx_prodring_set      prodring[1];
2659
2660
2661         /* begin "everything else" cacheline(s) section */
2662         struct net_device_stats         net_stats;
2663         struct net_device_stats         net_stats_prev;
2664         struct tg3_ethtool_stats        estats;
2665         struct tg3_ethtool_stats        estats_prev;
2666
2667         union {
2668         unsigned long                   phy_crc_errors;
2669         unsigned long                   last_event_jiffies;
2670         };
2671
2672         u32                             rx_offset;
2673         u32                             tg3_flags;
2674 #define TG3_FLAG_TAGGED_STATUS          0x00000001
2675 #define TG3_FLAG_TXD_MBOX_HWBUG         0x00000002
2676 #define TG3_FLAG_RX_CHECKSUMS           0x00000004
2677 #define TG3_FLAG_USE_LINKCHG_REG        0x00000008
2678 #define TG3_FLAG_USE_MI_INTERRUPT       0x00000010
2679 #define TG3_FLAG_ENABLE_ASF             0x00000020
2680 #define TG3_FLAG_ASPM_WORKAROUND        0x00000040
2681 #define TG3_FLAG_POLL_SERDES            0x00000080
2682 #define TG3_FLAG_MBOX_WRITE_REORDER     0x00000100
2683 #define TG3_FLAG_PCIX_TARGET_HWBUG      0x00000200
2684 #define TG3_FLAG_WOL_SPEED_100MB        0x00000400
2685 #define TG3_FLAG_WOL_ENABLE             0x00000800
2686 #define TG3_FLAG_EEPROM_WRITE_PROT      0x00001000
2687 #define TG3_FLAG_NVRAM                  0x00002000
2688 #define TG3_FLAG_NVRAM_BUFFERED         0x00004000
2689 #define TG3_FLAG_SUPPORT_MSI            0x00008000
2690 #define TG3_FLAG_SUPPORT_MSIX           0x00010000
2691 #define TG3_FLAG_SUPPORT_MSI_OR_MSIX    (TG3_FLAG_SUPPORT_MSI | \
2692                                          TG3_FLAG_SUPPORT_MSIX)
2693 #define TG3_FLAG_PCIX_MODE              0x00020000
2694 #define TG3_FLAG_PCI_HIGH_SPEED         0x00040000
2695 #define TG3_FLAG_PCI_32BIT              0x00080000
2696 #define TG3_FLAG_SRAM_USE_CONFIG        0x00100000
2697 #define TG3_FLAG_TX_RECOVERY_PENDING    0x00200000
2698 #define TG3_FLAG_WOL_CAP                0x00400000
2699 #define TG3_FLAG_JUMBO_RING_ENABLE      0x00800000
2700 #define TG3_FLAG_10_100_ONLY            0x01000000
2701 #define TG3_FLAG_PAUSE_AUTONEG          0x02000000
2702 #define TG3_FLAG_CPMU_PRESENT           0x04000000
2703 #define TG3_FLAG_40BIT_DMA_BUG          0x08000000
2704 #define TG3_FLAG_BROKEN_CHECKSUMS       0x10000000
2705 #define TG3_FLAG_JUMBO_CAPABLE          0x20000000
2706 #define TG3_FLAG_CHIP_RESETTING         0x40000000
2707 #define TG3_FLAG_INIT_COMPLETE          0x80000000
2708         u32                             tg3_flags2;
2709 #define TG3_FLG2_RESTART_TIMER          0x00000001
2710 #define TG3_FLG2_TSO_BUG                0x00000002
2711 #define TG3_FLG2_NO_ETH_WIRE_SPEED      0x00000004
2712 #define TG3_FLG2_IS_5788                0x00000008
2713 #define TG3_FLG2_MAX_RXPEND_64          0x00000010
2714 #define TG3_FLG2_TSO_CAPABLE            0x00000020
2715 #define TG3_FLG2_PHY_ADC_BUG            0x00000040
2716 #define TG3_FLG2_PHY_5704_A0_BUG        0x00000080
2717 #define TG3_FLG2_PHY_BER_BUG            0x00000100
2718 #define TG3_FLG2_PCI_EXPRESS            0x00000200
2719 #define TG3_FLG2_ASF_NEW_HANDSHAKE      0x00000400
2720 #define TG3_FLG2_HW_AUTONEG             0x00000800
2721 #define TG3_FLG2_IS_NIC                 0x00001000
2722 #define TG3_FLG2_PHY_SERDES             0x00002000
2723 #define TG3_FLG2_CAPACITIVE_COUPLING    0x00004000
2724 #define TG3_FLG2_FLASH                  0x00008000
2725 #define TG3_FLG2_HW_TSO_1               0x00010000
2726 #define TG3_FLG2_SERDES_PREEMPHASIS     0x00020000
2727 #define TG3_FLG2_5705_PLUS              0x00040000
2728 #define TG3_FLG2_5750_PLUS              0x00080000
2729 #define TG3_FLG2_PROTECTED_NVRAM        0x00100000
2730 #define TG3_FLG2_USING_MSI              0x00200000
2731 #define TG3_FLG2_USING_MSIX             0x00400000
2732 #define TG3_FLG2_USING_MSI_OR_MSIX      (TG3_FLG2_USING_MSI | \
2733                                         TG3_FLG2_USING_MSIX)
2734 #define TG3_FLG2_MII_SERDES             0x00800000
2735 #define TG3_FLG2_ANY_SERDES             (TG3_FLG2_PHY_SERDES |  \
2736                                         TG3_FLG2_MII_SERDES)
2737 #define TG3_FLG2_PARALLEL_DETECT        0x01000000
2738 #define TG3_FLG2_ICH_WORKAROUND         0x02000000
2739 #define TG3_FLG2_5780_CLASS             0x04000000
2740 #define TG3_FLG2_HW_TSO_2               0x08000000
2741 #define TG3_FLG2_HW_TSO                 (TG3_FLG2_HW_TSO_1 | TG3_FLG2_HW_TSO_2)
2742 #define TG3_FLG2_1SHOT_MSI              0x10000000
2743 #define TG3_FLG2_PHY_JITTER_BUG         0x20000000
2744 #define TG3_FLG2_NO_FWARE_REPORTED      0x40000000
2745 #define TG3_FLG2_PHY_ADJUST_TRIM        0x80000000
2746         u32                             tg3_flags3;
2747 #define TG3_FLG3_NO_NVRAM_ADDR_TRANS    0x00000001
2748 #define TG3_FLG3_ENABLE_APE             0x00000002
2749 #define TG3_FLG3_5701_DMA_BUG           0x00000008
2750 #define TG3_FLG3_USE_PHYLIB             0x00000010
2751 #define TG3_FLG3_MDIOBUS_INITED         0x00000020
2752 #define TG3_FLG3_MDIOBUS_PAUSED         0x00000040
2753 #define TG3_FLG3_PHY_CONNECTED          0x00000080
2754 #define TG3_FLG3_RGMII_STD_IBND_DISABLE 0x00000100
2755 #define TG3_FLG3_RGMII_EXT_IBND_RX_EN   0x00000200
2756 #define TG3_FLG3_RGMII_EXT_IBND_TX_EN   0x00000400
2757 #define TG3_FLG3_CLKREQ_BUG             0x00000800
2758 #define TG3_FLG3_PHY_ENABLE_APD         0x00001000
2759 #define TG3_FLG3_5755_PLUS              0x00002000
2760 #define TG3_FLG3_NO_NVRAM               0x00004000
2761 #define TG3_FLG3_TOGGLE_10_100_L1PLLPD  0x00008000
2762 #define TG3_FLG3_PHY_IS_FET             0x00010000
2763 #define TG3_FLG3_ENABLE_RSS             0x00020000
2764
2765         struct timer_list               timer;
2766         u16                             timer_counter;
2767         u16                             timer_multiplier;
2768         u32                             timer_offset;
2769         u16                             asf_counter;
2770         u16                             asf_multiplier;
2771
2772         /* 1 second counter for transient serdes link events */
2773         u32                             serdes_counter;
2774 #define SERDES_AN_TIMEOUT_5704S         2
2775 #define SERDES_PARALLEL_DET_TIMEOUT     1
2776 #define SERDES_AN_TIMEOUT_5714S         1
2777
2778         struct tg3_link_config          link_config;
2779         struct tg3_bufmgr_config        bufmgr_config;
2780
2781         /* cache h/w values, often passed straight to h/w */
2782         u32                             rx_mode;
2783         u32                             tx_mode;
2784         u32                             mac_mode;
2785         u32                             mi_mode;
2786         u32                             misc_host_ctrl;
2787         u32                             grc_mode;
2788         u32                             grc_local_ctrl;
2789         u32                             dma_rwctrl;
2790         u32                             coalesce_mode;
2791         u32                             pwrmgmt_thresh;
2792
2793         /* PCI block */
2794         u32                             pci_chip_rev_id;
2795         u16                             pci_cmd;
2796         u8                              pci_cacheline_sz;
2797         u8                              pci_lat_timer;
2798
2799         int                             pm_cap;
2800         int                             msi_cap;
2801         union {
2802         int                             pcix_cap;
2803         int                             pcie_cap;
2804         };
2805
2806         struct mii_bus                  *mdio_bus;
2807         int                             mdio_irq[PHY_MAX_ADDR];
2808
2809         u8                              phy_addr;
2810
2811         /* PHY info */
2812         u32                             phy_id;
2813 #define PHY_ID_MASK                     0xfffffff0
2814 #define PHY_ID_BCM5400                  0x60008040
2815 #define PHY_ID_BCM5401                  0x60008050
2816 #define PHY_ID_BCM5411                  0x60008070
2817 #define PHY_ID_BCM5701                  0x60008110
2818 #define PHY_ID_BCM5703                  0x60008160
2819 #define PHY_ID_BCM5704                  0x60008190
2820 #define PHY_ID_BCM5705                  0x600081a0
2821 #define PHY_ID_BCM5750                  0x60008180
2822 #define PHY_ID_BCM5752                  0x60008100
2823 #define PHY_ID_BCM5714                  0x60008340
2824 #define PHY_ID_BCM5780                  0x60008350
2825 #define PHY_ID_BCM5755                  0xbc050cc0
2826 #define PHY_ID_BCM5787                  0xbc050ce0
2827 #define PHY_ID_BCM5756                  0xbc050ed0
2828 #define PHY_ID_BCM5784                  0xbc050fa0
2829 #define PHY_ID_BCM5761                  0xbc050fd0
2830 #define PHY_ID_BCM5906                  0xdc00ac40
2831 #define PHY_ID_BCM8002                  0x60010140
2832 #define PHY_ID_INVALID                  0xffffffff
2833 #define PHY_ID_REV_MASK                 0x0000000f
2834 #define PHY_REV_BCM5401_B0              0x1
2835 #define PHY_REV_BCM5401_B2              0x3
2836 #define PHY_REV_BCM5401_C0              0x6
2837 #define PHY_REV_BCM5411_X0              0x1 /* Found on Netgear GA302T */
2838 #define TG3_PHY_ID_BCM50610             0x143bd60
2839 #define TG3_PHY_ID_BCMAC131             0x143bc70
2840 #define TG3_PHY_ID_RTL8211C             0x001cc910
2841 #define TG3_PHY_ID_RTL8201E             0x00008200
2842 #define TG3_PHY_ID_BCM57780             0x03625d90
2843 #define TG3_PHY_OUI_MASK                0xfffffc00
2844 #define TG3_PHY_OUI_1                   0x00206000
2845 #define TG3_PHY_OUI_2                   0x0143bc00
2846 #define TG3_PHY_OUI_3                   0x03625c00
2847
2848         u32                             led_ctrl;
2849         u32                             phy_otp;
2850
2851         char                            board_part_number[24];
2852 #define TG3_VER_SIZE 32
2853         char                            fw_ver[TG3_VER_SIZE];
2854         u32                             nic_sram_data_cfg;
2855         u32                             pci_clock_ctrl;
2856         struct pci_dev                  *pdev_peer;
2857
2858         /* This macro assumes the passed PHY ID is already masked
2859          * with PHY_ID_MASK.
2860          */
2861 #define KNOWN_PHY_ID(X)         \
2862         ((X) == PHY_ID_BCM5400 || (X) == PHY_ID_BCM5401 || \
2863          (X) == PHY_ID_BCM5411 || (X) == PHY_ID_BCM5701 || \
2864          (X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \
2865          (X) == PHY_ID_BCM5705 || (X) == PHY_ID_BCM5750 || \
2866          (X) == PHY_ID_BCM5752 || (X) == PHY_ID_BCM5714 || \
2867          (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
2868          (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \
2869          (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM5761 || \
2870          (X) == PHY_ID_BCM8002)
2871
2872         struct tg3_hw_stats             *hw_stats;
2873         dma_addr_t                      stats_mapping;
2874         struct work_struct              reset_task;
2875
2876         int                             nvram_lock_cnt;
2877         u32                             nvram_size;
2878 #define TG3_NVRAM_SIZE_64KB             0x00010000
2879 #define TG3_NVRAM_SIZE_128KB            0x00020000
2880 #define TG3_NVRAM_SIZE_256KB            0x00040000
2881 #define TG3_NVRAM_SIZE_512KB            0x00080000
2882 #define TG3_NVRAM_SIZE_1MB              0x00100000
2883 #define TG3_NVRAM_SIZE_2MB              0x00200000
2884
2885         u32                             nvram_pagesize;
2886         u32                             nvram_jedecnum;
2887
2888 #define JEDEC_ATMEL                     0x1f
2889 #define JEDEC_ST                        0x20
2890 #define JEDEC_SAIFUN                    0x4f
2891 #define JEDEC_SST                       0xbf
2892
2893 #define ATMEL_AT24C64_CHIP_SIZE         TG3_NVRAM_SIZE_64KB
2894 #define ATMEL_AT24C64_PAGE_SIZE         (32)
2895
2896 #define ATMEL_AT24C512_CHIP_SIZE        TG3_NVRAM_SIZE_512KB
2897 #define ATMEL_AT24C512_PAGE_SIZE        (128)
2898
2899 #define ATMEL_AT45DB0X1B_PAGE_POS       9
2900 #define ATMEL_AT45DB0X1B_PAGE_SIZE      264
2901
2902 #define ATMEL_AT25F512_PAGE_SIZE        256
2903
2904 #define ST_M45PEX0_PAGE_SIZE            256
2905
2906 #define SAIFUN_SA25F0XX_PAGE_SIZE       256
2907
2908 #define SST_25VF0X0_PAGE_SIZE           4098
2909
2910         unsigned int                    irq_max;
2911         unsigned int                    irq_cnt;
2912
2913         struct ethtool_coalesce         coal;
2914
2915         /* firmware info */
2916         const char                      *fw_needed;
2917         const struct firmware           *fw;
2918         u32                             fw_len; /* includes BSS */
2919 };
2920
2921 #endif /* !(_T3_H) */