Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[linux-2.6.git] / drivers / net / tg3.h
1 /* $Id: tg3.h,v 1.37.2.32 2002/03/11 12:18:18 davem Exp $
2  * tg3.h: Definitions for Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  * Copyright (C) 2007-2010 Broadcom Corporation.
8  */
9
10 #ifndef _T3_H
11 #define _T3_H
12
13 #define TG3_64BIT_REG_HIGH              0x00UL
14 #define TG3_64BIT_REG_LOW               0x04UL
15
16 /* Descriptor block info. */
17 #define TG3_BDINFO_HOST_ADDR            0x0UL /* 64-bit */
18 #define TG3_BDINFO_MAXLEN_FLAGS         0x8UL /* 32-bit */
19 #define  BDINFO_FLAGS_USE_EXT_RECV       0x00000001 /* ext rx_buffer_desc */
20 #define  BDINFO_FLAGS_DISABLED           0x00000002
21 #define  BDINFO_FLAGS_MAXLEN_MASK        0xffff0000
22 #define  BDINFO_FLAGS_MAXLEN_SHIFT       16
23 #define TG3_BDINFO_NIC_ADDR             0xcUL /* 32-bit */
24 #define TG3_BDINFO_SIZE                 0x10UL
25
26 #define TG3_RX_INTERNAL_RING_SZ_5906    32
27
28 #define RX_STD_MAX_SIZE_5705            512
29 #define RX_STD_MAX_SIZE_5717            2048
30 #define RX_JUMBO_MAX_SIZE               0xdeadbeef /* XXX */
31
32 /* First 256 bytes are a mirror of PCI config space. */
33 #define TG3PCI_VENDOR                   0x00000000
34 #define  TG3PCI_VENDOR_BROADCOM          0x14e4
35 #define TG3PCI_DEVICE                   0x00000002
36 #define  TG3PCI_DEVICE_TIGON3_1          0x1644 /* BCM5700 */
37 #define  TG3PCI_DEVICE_TIGON3_2          0x1645 /* BCM5701 */
38 #define  TG3PCI_DEVICE_TIGON3_3          0x1646 /* BCM5702 */
39 #define  TG3PCI_DEVICE_TIGON3_4          0x1647 /* BCM5703 */
40 #define  TG3PCI_DEVICE_TIGON3_5761S      0x1688
41 #define  TG3PCI_DEVICE_TIGON3_5761SE     0x1689
42 #define  TG3PCI_DEVICE_TIGON3_57780      0x1692
43 #define  TG3PCI_DEVICE_TIGON3_57760      0x1690
44 #define  TG3PCI_DEVICE_TIGON3_57790      0x1694
45 #define  TG3PCI_DEVICE_TIGON3_57788      0x1691
46 #define  TG3PCI_DEVICE_TIGON3_5785_G     0x1699 /* GPHY */
47 #define  TG3PCI_DEVICE_TIGON3_5785_F     0x16a0 /* 10/100 only */
48 #define  TG3PCI_DEVICE_TIGON3_5717       0x1655
49 #define  TG3PCI_DEVICE_TIGON3_5718       0x1656
50 #define  TG3PCI_DEVICE_TIGON3_57781      0x16b1
51 #define  TG3PCI_DEVICE_TIGON3_57785      0x16b5
52 #define  TG3PCI_DEVICE_TIGON3_57761      0x16b0
53 #define  TG3PCI_DEVICE_TIGON3_57765      0x16b4
54 #define  TG3PCI_DEVICE_TIGON3_57791      0x16b2
55 #define  TG3PCI_DEVICE_TIGON3_57795      0x16b6
56 #define  TG3PCI_DEVICE_TIGON3_5719       0x1657
57 /* 0x04 --> 0x2c unused */
58 #define TG3PCI_SUBVENDOR_ID_BROADCOM            PCI_VENDOR_ID_BROADCOM
59 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6    0x1644
60 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5    0x0001
61 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6    0x0002
62 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9    0x0003
63 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1    0x0005
64 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8    0x0006
65 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7    0x0007
66 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10   0x0008
67 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12   0x8008
68 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1   0x0009
69 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2   0x8009
70 #define TG3PCI_SUBVENDOR_ID_3COM                PCI_VENDOR_ID_3COM
71 #define TG3PCI_SUBDEVICE_ID_3COM_3C996T         0x1000
72 #define TG3PCI_SUBDEVICE_ID_3COM_3C996BT        0x1006
73 #define TG3PCI_SUBDEVICE_ID_3COM_3C996SX        0x1004
74 #define TG3PCI_SUBDEVICE_ID_3COM_3C1000T        0x1007
75 #define TG3PCI_SUBDEVICE_ID_3COM_3C940BR01      0x1008
76 #define TG3PCI_SUBVENDOR_ID_DELL                PCI_VENDOR_ID_DELL
77 #define TG3PCI_SUBDEVICE_ID_DELL_VIPER          0x00d1
78 #define TG3PCI_SUBDEVICE_ID_DELL_JAGUAR         0x0106
79 #define TG3PCI_SUBDEVICE_ID_DELL_MERLOT         0x0109
80 #define TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT    0x010a
81 #define TG3PCI_SUBVENDOR_ID_COMPAQ              PCI_VENDOR_ID_COMPAQ
82 #define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE      0x007c
83 #define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2    0x009a
84 #define TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING   0x007d
85 #define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780       0x0085
86 #define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2     0x0099
87 #define TG3PCI_SUBVENDOR_ID_IBM                 PCI_VENDOR_ID_IBM
88 #define TG3PCI_SUBDEVICE_ID_IBM_5703SAX2        0x0281
89 /* 0x30 --> 0x64 unused */
90 #define TG3PCI_MSI_DATA                 0x00000064
91 /* 0x66 --> 0x68 unused */
92 #define TG3PCI_MISC_HOST_CTRL           0x00000068
93 #define  MISC_HOST_CTRL_CLEAR_INT        0x00000001
94 #define  MISC_HOST_CTRL_MASK_PCI_INT     0x00000002
95 #define  MISC_HOST_CTRL_BYTE_SWAP        0x00000004
96 #define  MISC_HOST_CTRL_WORD_SWAP        0x00000008
97 #define  MISC_HOST_CTRL_PCISTATE_RW      0x00000010
98 #define  MISC_HOST_CTRL_CLKREG_RW        0x00000020
99 #define  MISC_HOST_CTRL_REGWORD_SWAP     0x00000040
100 #define  MISC_HOST_CTRL_INDIR_ACCESS     0x00000080
101 #define  MISC_HOST_CTRL_IRQ_MASK_MODE    0x00000100
102 #define  MISC_HOST_CTRL_TAGGED_STATUS    0x00000200
103 #define  MISC_HOST_CTRL_CHIPREV          0xffff0000
104 #define  MISC_HOST_CTRL_CHIPREV_SHIFT    16
105 #define  GET_CHIP_REV_ID(MISC_HOST_CTRL) \
106          (((MISC_HOST_CTRL) & MISC_HOST_CTRL_CHIPREV) >> \
107           MISC_HOST_CTRL_CHIPREV_SHIFT)
108 #define  CHIPREV_ID_5700_A0              0x7000
109 #define  CHIPREV_ID_5700_A1              0x7001
110 #define  CHIPREV_ID_5700_B0              0x7100
111 #define  CHIPREV_ID_5700_B1              0x7101
112 #define  CHIPREV_ID_5700_B3              0x7102
113 #define  CHIPREV_ID_5700_ALTIMA          0x7104
114 #define  CHIPREV_ID_5700_C0              0x7200
115 #define  CHIPREV_ID_5701_A0              0x0000
116 #define  CHIPREV_ID_5701_B0              0x0100
117 #define  CHIPREV_ID_5701_B2              0x0102
118 #define  CHIPREV_ID_5701_B5              0x0105
119 #define  CHIPREV_ID_5703_A0              0x1000
120 #define  CHIPREV_ID_5703_A1              0x1001
121 #define  CHIPREV_ID_5703_A2              0x1002
122 #define  CHIPREV_ID_5703_A3              0x1003
123 #define  CHIPREV_ID_5704_A0              0x2000
124 #define  CHIPREV_ID_5704_A1              0x2001
125 #define  CHIPREV_ID_5704_A2              0x2002
126 #define  CHIPREV_ID_5704_A3              0x2003
127 #define  CHIPREV_ID_5705_A0              0x3000
128 #define  CHIPREV_ID_5705_A1              0x3001
129 #define  CHIPREV_ID_5705_A2              0x3002
130 #define  CHIPREV_ID_5705_A3              0x3003
131 #define  CHIPREV_ID_5750_A0              0x4000
132 #define  CHIPREV_ID_5750_A1              0x4001
133 #define  CHIPREV_ID_5750_A3              0x4003
134 #define  CHIPREV_ID_5750_C2              0x4202
135 #define  CHIPREV_ID_5752_A0_HW           0x5000
136 #define  CHIPREV_ID_5752_A0              0x6000
137 #define  CHIPREV_ID_5752_A1              0x6001
138 #define  CHIPREV_ID_5714_A2              0x9002
139 #define  CHIPREV_ID_5906_A1              0xc001
140 #define  CHIPREV_ID_57780_A0             0x57780000
141 #define  CHIPREV_ID_57780_A1             0x57780001
142 #define  CHIPREV_ID_5717_A0              0x05717000
143 #define  CHIPREV_ID_57765_A0             0x57785000
144 #define  GET_ASIC_REV(CHIP_REV_ID)      ((CHIP_REV_ID) >> 12)
145 #define   ASIC_REV_5700                  0x07
146 #define   ASIC_REV_5701                  0x00
147 #define   ASIC_REV_5703                  0x01
148 #define   ASIC_REV_5704                  0x02
149 #define   ASIC_REV_5705                  0x03
150 #define   ASIC_REV_5750                  0x04
151 #define   ASIC_REV_5752                  0x06
152 #define   ASIC_REV_5780                  0x08
153 #define   ASIC_REV_5714                  0x09
154 #define   ASIC_REV_5755                  0x0a
155 #define   ASIC_REV_5787                  0x0b
156 #define   ASIC_REV_5906                  0x0c
157 #define   ASIC_REV_USE_PROD_ID_REG       0x0f
158 #define   ASIC_REV_5784                  0x5784
159 #define   ASIC_REV_5761                  0x5761
160 #define   ASIC_REV_5785                  0x5785
161 #define   ASIC_REV_57780                 0x57780
162 #define   ASIC_REV_5717                  0x5717
163 #define   ASIC_REV_57765                 0x57785
164 #define   ASIC_REV_5719                  0x5719
165 #define  GET_CHIP_REV(CHIP_REV_ID)      ((CHIP_REV_ID) >> 8)
166 #define   CHIPREV_5700_AX                0x70
167 #define   CHIPREV_5700_BX                0x71
168 #define   CHIPREV_5700_CX                0x72
169 #define   CHIPREV_5701_AX                0x00
170 #define   CHIPREV_5703_AX                0x10
171 #define   CHIPREV_5704_AX                0x20
172 #define   CHIPREV_5704_BX                0x21
173 #define   CHIPREV_5750_AX                0x40
174 #define   CHIPREV_5750_BX                0x41
175 #define   CHIPREV_5784_AX                0x57840
176 #define   CHIPREV_5761_AX                0x57610
177 #define  GET_METAL_REV(CHIP_REV_ID)     ((CHIP_REV_ID) & 0xff)
178 #define   METAL_REV_A0                   0x00
179 #define   METAL_REV_A1                   0x01
180 #define   METAL_REV_B0                   0x00
181 #define   METAL_REV_B1                   0x01
182 #define   METAL_REV_B2                   0x02
183 #define TG3PCI_DMA_RW_CTRL              0x0000006c
184 #define  DMA_RWCTRL_DIS_CACHE_ALIGNMENT  0x00000001
185 #define  DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK 0x00000380
186 #define  DMA_RWCTRL_READ_BNDRY_MASK      0x00000700
187 #define  DMA_RWCTRL_READ_BNDRY_DISAB     0x00000000
188 #define  DMA_RWCTRL_READ_BNDRY_16        0x00000100
189 #define  DMA_RWCTRL_READ_BNDRY_128_PCIX  0x00000100
190 #define  DMA_RWCTRL_READ_BNDRY_32        0x00000200
191 #define  DMA_RWCTRL_READ_BNDRY_256_PCIX  0x00000200
192 #define  DMA_RWCTRL_READ_BNDRY_64        0x00000300
193 #define  DMA_RWCTRL_READ_BNDRY_384_PCIX  0x00000300
194 #define  DMA_RWCTRL_READ_BNDRY_128       0x00000400
195 #define  DMA_RWCTRL_READ_BNDRY_256       0x00000500
196 #define  DMA_RWCTRL_READ_BNDRY_512       0x00000600
197 #define  DMA_RWCTRL_READ_BNDRY_1024      0x00000700
198 #define  DMA_RWCTRL_WRITE_BNDRY_MASK     0x00003800
199 #define  DMA_RWCTRL_WRITE_BNDRY_DISAB    0x00000000
200 #define  DMA_RWCTRL_WRITE_BNDRY_16       0x00000800
201 #define  DMA_RWCTRL_WRITE_BNDRY_128_PCIX 0x00000800
202 #define  DMA_RWCTRL_WRITE_BNDRY_32       0x00001000
203 #define  DMA_RWCTRL_WRITE_BNDRY_256_PCIX 0x00001000
204 #define  DMA_RWCTRL_WRITE_BNDRY_64       0x00001800
205 #define  DMA_RWCTRL_WRITE_BNDRY_384_PCIX 0x00001800
206 #define  DMA_RWCTRL_WRITE_BNDRY_128      0x00002000
207 #define  DMA_RWCTRL_WRITE_BNDRY_256      0x00002800
208 #define  DMA_RWCTRL_WRITE_BNDRY_512      0x00003000
209 #define  DMA_RWCTRL_WRITE_BNDRY_1024     0x00003800
210 #define  DMA_RWCTRL_ONE_DMA              0x00004000
211 #define  DMA_RWCTRL_READ_WATER           0x00070000
212 #define  DMA_RWCTRL_READ_WATER_SHIFT     16
213 #define  DMA_RWCTRL_WRITE_WATER          0x00380000
214 #define  DMA_RWCTRL_WRITE_WATER_SHIFT    19
215 #define  DMA_RWCTRL_USE_MEM_READ_MULT    0x00400000
216 #define  DMA_RWCTRL_ASSERT_ALL_BE        0x00800000
217 #define  DMA_RWCTRL_PCI_READ_CMD         0x0f000000
218 #define  DMA_RWCTRL_PCI_READ_CMD_SHIFT   24
219 #define  DMA_RWCTRL_PCI_WRITE_CMD        0xf0000000
220 #define  DMA_RWCTRL_PCI_WRITE_CMD_SHIFT  28
221 #define  DMA_RWCTRL_WRITE_BNDRY_64_PCIE  0x10000000
222 #define  DMA_RWCTRL_WRITE_BNDRY_128_PCIE 0x30000000
223 #define  DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE 0x70000000
224 #define TG3PCI_PCISTATE                 0x00000070
225 #define  PCISTATE_FORCE_RESET            0x00000001
226 #define  PCISTATE_INT_NOT_ACTIVE         0x00000002
227 #define  PCISTATE_CONV_PCI_MODE          0x00000004
228 #define  PCISTATE_BUS_SPEED_HIGH         0x00000008
229 #define  PCISTATE_BUS_32BIT              0x00000010
230 #define  PCISTATE_ROM_ENABLE             0x00000020
231 #define  PCISTATE_ROM_RETRY_ENABLE       0x00000040
232 #define  PCISTATE_FLAT_VIEW              0x00000100
233 #define  PCISTATE_RETRY_SAME_DMA         0x00002000
234 #define  PCISTATE_ALLOW_APE_CTLSPC_WR    0x00010000
235 #define  PCISTATE_ALLOW_APE_SHMEM_WR     0x00020000
236 #define  PCISTATE_ALLOW_APE_PSPACE_WR    0x00040000
237 #define TG3PCI_CLOCK_CTRL               0x00000074
238 #define  CLOCK_CTRL_CORECLK_DISABLE      0x00000200
239 #define  CLOCK_CTRL_RXCLK_DISABLE        0x00000400
240 #define  CLOCK_CTRL_TXCLK_DISABLE        0x00000800
241 #define  CLOCK_CTRL_ALTCLK               0x00001000
242 #define  CLOCK_CTRL_PWRDOWN_PLL133       0x00008000
243 #define  CLOCK_CTRL_44MHZ_CORE           0x00040000
244 #define  CLOCK_CTRL_625_CORE             0x00100000
245 #define  CLOCK_CTRL_FORCE_CLKRUN         0x00200000
246 #define  CLOCK_CTRL_CLKRUN_OENABLE       0x00400000
247 #define  CLOCK_CTRL_DELAY_PCI_GRANT      0x80000000
248 #define TG3PCI_REG_BASE_ADDR            0x00000078
249 #define TG3PCI_MEM_WIN_BASE_ADDR        0x0000007c
250 #define TG3PCI_REG_DATA                 0x00000080
251 #define TG3PCI_MEM_WIN_DATA             0x00000084
252 #define TG3PCI_MISC_LOCAL_CTRL          0x00000090
253 /* 0x94 --> 0x98 unused */
254 #define TG3PCI_STD_RING_PROD_IDX        0x00000098 /* 64-bit */
255 #define TG3PCI_RCV_RET_RING_CON_IDX     0x000000a0 /* 64-bit */
256 /* 0xa8 --> 0xb8 unused */
257 #define TG3PCI_DUAL_MAC_CTRL            0x000000b8
258 #define  DUAL_MAC_CTRL_CH_MASK           0x00000003
259 #define  DUAL_MAC_CTRL_ID                0x00000004
260 #define TG3PCI_PRODID_ASICREV           0x000000bc
261 #define  PROD_ID_ASIC_REV_MASK           0x0fffffff
262 /* 0xc0 --> 0xf4 unused */
263
264 #define TG3PCI_GEN2_PRODID_ASICREV      0x000000f4
265 #define TG3PCI_GEN15_PRODID_ASICREV     0x000000fc
266 /* 0xf8 --> 0x200 unused */
267
268 #define TG3_CORR_ERR_STAT               0x00000110
269 #define  TG3_CORR_ERR_STAT_CLEAR        0xffffffff
270 /* 0x114 --> 0x200 unused */
271
272 /* Mailbox registers */
273 #define MAILBOX_INTERRUPT_0             0x00000200 /* 64-bit */
274 #define MAILBOX_INTERRUPT_1             0x00000208 /* 64-bit */
275 #define MAILBOX_INTERRUPT_2             0x00000210 /* 64-bit */
276 #define MAILBOX_INTERRUPT_3             0x00000218 /* 64-bit */
277 #define MAILBOX_GENERAL_0               0x00000220 /* 64-bit */
278 #define MAILBOX_GENERAL_1               0x00000228 /* 64-bit */
279 #define MAILBOX_GENERAL_2               0x00000230 /* 64-bit */
280 #define MAILBOX_GENERAL_3               0x00000238 /* 64-bit */
281 #define MAILBOX_GENERAL_4               0x00000240 /* 64-bit */
282 #define MAILBOX_GENERAL_5               0x00000248 /* 64-bit */
283 #define MAILBOX_GENERAL_6               0x00000250 /* 64-bit */
284 #define MAILBOX_GENERAL_7               0x00000258 /* 64-bit */
285 #define MAILBOX_RELOAD_STAT             0x00000260 /* 64-bit */
286 #define MAILBOX_RCV_STD_PROD_IDX        0x00000268 /* 64-bit */
287 #define TG3_RX_STD_PROD_IDX_REG         (MAILBOX_RCV_STD_PROD_IDX + \
288                                          TG3_64BIT_REG_LOW)
289 #define MAILBOX_RCV_JUMBO_PROD_IDX      0x00000270 /* 64-bit */
290 #define TG3_RX_JMB_PROD_IDX_REG         (MAILBOX_RCV_JUMBO_PROD_IDX + \
291                                          TG3_64BIT_REG_LOW)
292 #define MAILBOX_RCV_MINI_PROD_IDX       0x00000278 /* 64-bit */
293 #define MAILBOX_RCVRET_CON_IDX_0        0x00000280 /* 64-bit */
294 #define MAILBOX_RCVRET_CON_IDX_1        0x00000288 /* 64-bit */
295 #define MAILBOX_RCVRET_CON_IDX_2        0x00000290 /* 64-bit */
296 #define MAILBOX_RCVRET_CON_IDX_3        0x00000298 /* 64-bit */
297 #define MAILBOX_RCVRET_CON_IDX_4        0x000002a0 /* 64-bit */
298 #define MAILBOX_RCVRET_CON_IDX_5        0x000002a8 /* 64-bit */
299 #define MAILBOX_RCVRET_CON_IDX_6        0x000002b0 /* 64-bit */
300 #define MAILBOX_RCVRET_CON_IDX_7        0x000002b8 /* 64-bit */
301 #define MAILBOX_RCVRET_CON_IDX_8        0x000002c0 /* 64-bit */
302 #define MAILBOX_RCVRET_CON_IDX_9        0x000002c8 /* 64-bit */
303 #define MAILBOX_RCVRET_CON_IDX_10       0x000002d0 /* 64-bit */
304 #define MAILBOX_RCVRET_CON_IDX_11       0x000002d8 /* 64-bit */
305 #define MAILBOX_RCVRET_CON_IDX_12       0x000002e0 /* 64-bit */
306 #define MAILBOX_RCVRET_CON_IDX_13       0x000002e8 /* 64-bit */
307 #define MAILBOX_RCVRET_CON_IDX_14       0x000002f0 /* 64-bit */
308 #define MAILBOX_RCVRET_CON_IDX_15       0x000002f8 /* 64-bit */
309 #define MAILBOX_SNDHOST_PROD_IDX_0      0x00000300 /* 64-bit */
310 #define MAILBOX_SNDHOST_PROD_IDX_1      0x00000308 /* 64-bit */
311 #define MAILBOX_SNDHOST_PROD_IDX_2      0x00000310 /* 64-bit */
312 #define MAILBOX_SNDHOST_PROD_IDX_3      0x00000318 /* 64-bit */
313 #define MAILBOX_SNDHOST_PROD_IDX_4      0x00000320 /* 64-bit */
314 #define MAILBOX_SNDHOST_PROD_IDX_5      0x00000328 /* 64-bit */
315 #define MAILBOX_SNDHOST_PROD_IDX_6      0x00000330 /* 64-bit */
316 #define MAILBOX_SNDHOST_PROD_IDX_7      0x00000338 /* 64-bit */
317 #define MAILBOX_SNDHOST_PROD_IDX_8      0x00000340 /* 64-bit */
318 #define MAILBOX_SNDHOST_PROD_IDX_9      0x00000348 /* 64-bit */
319 #define MAILBOX_SNDHOST_PROD_IDX_10     0x00000350 /* 64-bit */
320 #define MAILBOX_SNDHOST_PROD_IDX_11     0x00000358 /* 64-bit */
321 #define MAILBOX_SNDHOST_PROD_IDX_12     0x00000360 /* 64-bit */
322 #define MAILBOX_SNDHOST_PROD_IDX_13     0x00000368 /* 64-bit */
323 #define MAILBOX_SNDHOST_PROD_IDX_14     0x00000370 /* 64-bit */
324 #define MAILBOX_SNDHOST_PROD_IDX_15     0x00000378 /* 64-bit */
325 #define MAILBOX_SNDNIC_PROD_IDX_0       0x00000380 /* 64-bit */
326 #define MAILBOX_SNDNIC_PROD_IDX_1       0x00000388 /* 64-bit */
327 #define MAILBOX_SNDNIC_PROD_IDX_2       0x00000390 /* 64-bit */
328 #define MAILBOX_SNDNIC_PROD_IDX_3       0x00000398 /* 64-bit */
329 #define MAILBOX_SNDNIC_PROD_IDX_4       0x000003a0 /* 64-bit */
330 #define MAILBOX_SNDNIC_PROD_IDX_5       0x000003a8 /* 64-bit */
331 #define MAILBOX_SNDNIC_PROD_IDX_6       0x000003b0 /* 64-bit */
332 #define MAILBOX_SNDNIC_PROD_IDX_7       0x000003b8 /* 64-bit */
333 #define MAILBOX_SNDNIC_PROD_IDX_8       0x000003c0 /* 64-bit */
334 #define MAILBOX_SNDNIC_PROD_IDX_9       0x000003c8 /* 64-bit */
335 #define MAILBOX_SNDNIC_PROD_IDX_10      0x000003d0 /* 64-bit */
336 #define MAILBOX_SNDNIC_PROD_IDX_11      0x000003d8 /* 64-bit */
337 #define MAILBOX_SNDNIC_PROD_IDX_12      0x000003e0 /* 64-bit */
338 #define MAILBOX_SNDNIC_PROD_IDX_13      0x000003e8 /* 64-bit */
339 #define MAILBOX_SNDNIC_PROD_IDX_14      0x000003f0 /* 64-bit */
340 #define MAILBOX_SNDNIC_PROD_IDX_15      0x000003f8 /* 64-bit */
341
342 /* MAC control registers */
343 #define MAC_MODE                        0x00000400
344 #define  MAC_MODE_RESET                  0x00000001
345 #define  MAC_MODE_HALF_DUPLEX            0x00000002
346 #define  MAC_MODE_PORT_MODE_MASK         0x0000000c
347 #define  MAC_MODE_PORT_MODE_TBI          0x0000000c
348 #define  MAC_MODE_PORT_MODE_GMII         0x00000008
349 #define  MAC_MODE_PORT_MODE_MII          0x00000004
350 #define  MAC_MODE_PORT_MODE_NONE         0x00000000
351 #define  MAC_MODE_PORT_INT_LPBACK        0x00000010
352 #define  MAC_MODE_TAGGED_MAC_CTRL        0x00000080
353 #define  MAC_MODE_TX_BURSTING            0x00000100
354 #define  MAC_MODE_MAX_DEFER              0x00000200
355 #define  MAC_MODE_LINK_POLARITY          0x00000400
356 #define  MAC_MODE_RXSTAT_ENABLE          0x00000800
357 #define  MAC_MODE_RXSTAT_CLEAR           0x00001000
358 #define  MAC_MODE_RXSTAT_FLUSH           0x00002000
359 #define  MAC_MODE_TXSTAT_ENABLE          0x00004000
360 #define  MAC_MODE_TXSTAT_CLEAR           0x00008000
361 #define  MAC_MODE_TXSTAT_FLUSH           0x00010000
362 #define  MAC_MODE_SEND_CONFIGS           0x00020000
363 #define  MAC_MODE_MAGIC_PKT_ENABLE       0x00040000
364 #define  MAC_MODE_ACPI_ENABLE            0x00080000
365 #define  MAC_MODE_MIP_ENABLE             0x00100000
366 #define  MAC_MODE_TDE_ENABLE             0x00200000
367 #define  MAC_MODE_RDE_ENABLE             0x00400000
368 #define  MAC_MODE_FHDE_ENABLE            0x00800000
369 #define  MAC_MODE_KEEP_FRAME_IN_WOL      0x01000000
370 #define  MAC_MODE_APE_RX_EN              0x08000000
371 #define  MAC_MODE_APE_TX_EN              0x10000000
372 #define MAC_STATUS                      0x00000404
373 #define  MAC_STATUS_PCS_SYNCED           0x00000001
374 #define  MAC_STATUS_SIGNAL_DET           0x00000002
375 #define  MAC_STATUS_RCVD_CFG             0x00000004
376 #define  MAC_STATUS_CFG_CHANGED          0x00000008
377 #define  MAC_STATUS_SYNC_CHANGED         0x00000010
378 #define  MAC_STATUS_PORT_DEC_ERR         0x00000400
379 #define  MAC_STATUS_LNKSTATE_CHANGED     0x00001000
380 #define  MAC_STATUS_MI_COMPLETION        0x00400000
381 #define  MAC_STATUS_MI_INTERRUPT         0x00800000
382 #define  MAC_STATUS_AP_ERROR             0x01000000
383 #define  MAC_STATUS_ODI_ERROR            0x02000000
384 #define  MAC_STATUS_RXSTAT_OVERRUN       0x04000000
385 #define  MAC_STATUS_TXSTAT_OVERRUN       0x08000000
386 #define MAC_EVENT                       0x00000408
387 #define  MAC_EVENT_PORT_DECODE_ERR       0x00000400
388 #define  MAC_EVENT_LNKSTATE_CHANGED      0x00001000
389 #define  MAC_EVENT_MI_COMPLETION         0x00400000
390 #define  MAC_EVENT_MI_INTERRUPT          0x00800000
391 #define  MAC_EVENT_AP_ERROR              0x01000000
392 #define  MAC_EVENT_ODI_ERROR             0x02000000
393 #define  MAC_EVENT_RXSTAT_OVERRUN        0x04000000
394 #define  MAC_EVENT_TXSTAT_OVERRUN        0x08000000
395 #define MAC_LED_CTRL                    0x0000040c
396 #define  LED_CTRL_LNKLED_OVERRIDE        0x00000001
397 #define  LED_CTRL_1000MBPS_ON            0x00000002
398 #define  LED_CTRL_100MBPS_ON             0x00000004
399 #define  LED_CTRL_10MBPS_ON              0x00000008
400 #define  LED_CTRL_TRAFFIC_OVERRIDE       0x00000010
401 #define  LED_CTRL_TRAFFIC_BLINK          0x00000020
402 #define  LED_CTRL_TRAFFIC_LED            0x00000040
403 #define  LED_CTRL_1000MBPS_STATUS        0x00000080
404 #define  LED_CTRL_100MBPS_STATUS         0x00000100
405 #define  LED_CTRL_10MBPS_STATUS          0x00000200
406 #define  LED_CTRL_TRAFFIC_STATUS         0x00000400
407 #define  LED_CTRL_MODE_MAC               0x00000000
408 #define  LED_CTRL_MODE_PHY_1             0x00000800
409 #define  LED_CTRL_MODE_PHY_2             0x00001000
410 #define  LED_CTRL_MODE_SHASTA_MAC        0x00002000
411 #define  LED_CTRL_MODE_SHARED            0x00004000
412 #define  LED_CTRL_MODE_COMBO             0x00008000
413 #define  LED_CTRL_BLINK_RATE_MASK        0x7ff80000
414 #define  LED_CTRL_BLINK_RATE_SHIFT       19
415 #define  LED_CTRL_BLINK_PER_OVERRIDE     0x00080000
416 #define  LED_CTRL_BLINK_RATE_OVERRIDE    0x80000000
417 #define MAC_ADDR_0_HIGH                 0x00000410 /* upper 2 bytes */
418 #define MAC_ADDR_0_LOW                  0x00000414 /* lower 4 bytes */
419 #define MAC_ADDR_1_HIGH                 0x00000418 /* upper 2 bytes */
420 #define MAC_ADDR_1_LOW                  0x0000041c /* lower 4 bytes */
421 #define MAC_ADDR_2_HIGH                 0x00000420 /* upper 2 bytes */
422 #define MAC_ADDR_2_LOW                  0x00000424 /* lower 4 bytes */
423 #define MAC_ADDR_3_HIGH                 0x00000428 /* upper 2 bytes */
424 #define MAC_ADDR_3_LOW                  0x0000042c /* lower 4 bytes */
425 #define MAC_ACPI_MBUF_PTR               0x00000430
426 #define MAC_ACPI_LEN_OFFSET             0x00000434
427 #define  ACPI_LENOFF_LEN_MASK            0x0000ffff
428 #define  ACPI_LENOFF_LEN_SHIFT           0
429 #define  ACPI_LENOFF_OFF_MASK            0x0fff0000
430 #define  ACPI_LENOFF_OFF_SHIFT           16
431 #define MAC_TX_BACKOFF_SEED             0x00000438
432 #define  TX_BACKOFF_SEED_MASK            0x000003ff
433 #define MAC_RX_MTU_SIZE                 0x0000043c
434 #define  RX_MTU_SIZE_MASK                0x0000ffff
435 #define MAC_PCS_TEST                    0x00000440
436 #define  PCS_TEST_PATTERN_MASK           0x000fffff
437 #define  PCS_TEST_PATTERN_SHIFT          0
438 #define  PCS_TEST_ENABLE                 0x00100000
439 #define MAC_TX_AUTO_NEG                 0x00000444
440 #define  TX_AUTO_NEG_MASK                0x0000ffff
441 #define  TX_AUTO_NEG_SHIFT               0
442 #define MAC_RX_AUTO_NEG                 0x00000448
443 #define  RX_AUTO_NEG_MASK                0x0000ffff
444 #define  RX_AUTO_NEG_SHIFT               0
445 #define MAC_MI_COM                      0x0000044c
446 #define  MI_COM_CMD_MASK                 0x0c000000
447 #define  MI_COM_CMD_WRITE                0x04000000
448 #define  MI_COM_CMD_READ                 0x08000000
449 #define  MI_COM_READ_FAILED              0x10000000
450 #define  MI_COM_START                    0x20000000
451 #define  MI_COM_BUSY                     0x20000000
452 #define  MI_COM_PHY_ADDR_MASK            0x03e00000
453 #define  MI_COM_PHY_ADDR_SHIFT           21
454 #define  MI_COM_REG_ADDR_MASK            0x001f0000
455 #define  MI_COM_REG_ADDR_SHIFT           16
456 #define  MI_COM_DATA_MASK                0x0000ffff
457 #define MAC_MI_STAT                     0x00000450
458 #define  MAC_MI_STAT_LNKSTAT_ATTN_ENAB   0x00000001
459 #define  MAC_MI_STAT_10MBPS_MODE         0x00000002
460 #define MAC_MI_MODE                     0x00000454
461 #define  MAC_MI_MODE_CLK_10MHZ           0x00000001
462 #define  MAC_MI_MODE_SHORT_PREAMBLE      0x00000002
463 #define  MAC_MI_MODE_AUTO_POLL           0x00000010
464 #define  MAC_MI_MODE_500KHZ_CONST        0x00008000
465 #define  MAC_MI_MODE_BASE                0x000c0000 /* XXX magic values XXX */
466 #define MAC_AUTO_POLL_STATUS            0x00000458
467 #define  MAC_AUTO_POLL_ERROR             0x00000001
468 #define MAC_TX_MODE                     0x0000045c
469 #define  TX_MODE_RESET                   0x00000001
470 #define  TX_MODE_ENABLE                  0x00000002
471 #define  TX_MODE_FLOW_CTRL_ENABLE        0x00000010
472 #define  TX_MODE_BIG_BCKOFF_ENABLE       0x00000020
473 #define  TX_MODE_LONG_PAUSE_ENABLE       0x00000040
474 #define  TX_MODE_MBUF_LOCKUP_FIX         0x00000100
475 #define MAC_TX_STATUS                   0x00000460
476 #define  TX_STATUS_XOFFED                0x00000001
477 #define  TX_STATUS_SENT_XOFF             0x00000002
478 #define  TX_STATUS_SENT_XON              0x00000004
479 #define  TX_STATUS_LINK_UP               0x00000008
480 #define  TX_STATUS_ODI_UNDERRUN          0x00000010
481 #define  TX_STATUS_ODI_OVERRUN           0x00000020
482 #define MAC_TX_LENGTHS                  0x00000464
483 #define  TX_LENGTHS_SLOT_TIME_MASK       0x000000ff
484 #define  TX_LENGTHS_SLOT_TIME_SHIFT      0
485 #define  TX_LENGTHS_IPG_MASK             0x00000f00
486 #define  TX_LENGTHS_IPG_SHIFT            8
487 #define  TX_LENGTHS_IPG_CRS_MASK         0x00003000
488 #define  TX_LENGTHS_IPG_CRS_SHIFT        12
489 #define MAC_RX_MODE                     0x00000468
490 #define  RX_MODE_RESET                   0x00000001
491 #define  RX_MODE_ENABLE                  0x00000002
492 #define  RX_MODE_FLOW_CTRL_ENABLE        0x00000004
493 #define  RX_MODE_KEEP_MAC_CTRL           0x00000008
494 #define  RX_MODE_KEEP_PAUSE              0x00000010
495 #define  RX_MODE_ACCEPT_OVERSIZED        0x00000020
496 #define  RX_MODE_ACCEPT_RUNTS            0x00000040
497 #define  RX_MODE_LEN_CHECK               0x00000080
498 #define  RX_MODE_PROMISC                 0x00000100
499 #define  RX_MODE_NO_CRC_CHECK            0x00000200
500 #define  RX_MODE_KEEP_VLAN_TAG           0x00000400
501 #define  RX_MODE_RSS_IPV4_HASH_EN        0x00010000
502 #define  RX_MODE_RSS_TCP_IPV4_HASH_EN    0x00020000
503 #define  RX_MODE_RSS_IPV6_HASH_EN        0x00040000
504 #define  RX_MODE_RSS_TCP_IPV6_HASH_EN    0x00080000
505 #define  RX_MODE_RSS_ITBL_HASH_BITS_7    0x00700000
506 #define  RX_MODE_RSS_ENABLE              0x00800000
507 #define  RX_MODE_IPV6_CSUM_ENABLE        0x01000000
508 #define MAC_RX_STATUS                   0x0000046c
509 #define  RX_STATUS_REMOTE_TX_XOFFED      0x00000001
510 #define  RX_STATUS_XOFF_RCVD             0x00000002
511 #define  RX_STATUS_XON_RCVD              0x00000004
512 #define MAC_HASH_REG_0                  0x00000470
513 #define MAC_HASH_REG_1                  0x00000474
514 #define MAC_HASH_REG_2                  0x00000478
515 #define MAC_HASH_REG_3                  0x0000047c
516 #define MAC_RCV_RULE_0                  0x00000480
517 #define MAC_RCV_VALUE_0                 0x00000484
518 #define MAC_RCV_RULE_1                  0x00000488
519 #define MAC_RCV_VALUE_1                 0x0000048c
520 #define MAC_RCV_RULE_2                  0x00000490
521 #define MAC_RCV_VALUE_2                 0x00000494
522 #define MAC_RCV_RULE_3                  0x00000498
523 #define MAC_RCV_VALUE_3                 0x0000049c
524 #define MAC_RCV_RULE_4                  0x000004a0
525 #define MAC_RCV_VALUE_4                 0x000004a4
526 #define MAC_RCV_RULE_5                  0x000004a8
527 #define MAC_RCV_VALUE_5                 0x000004ac
528 #define MAC_RCV_RULE_6                  0x000004b0
529 #define MAC_RCV_VALUE_6                 0x000004b4
530 #define MAC_RCV_RULE_7                  0x000004b8
531 #define MAC_RCV_VALUE_7                 0x000004bc
532 #define MAC_RCV_RULE_8                  0x000004c0
533 #define MAC_RCV_VALUE_8                 0x000004c4
534 #define MAC_RCV_RULE_9                  0x000004c8
535 #define MAC_RCV_VALUE_9                 0x000004cc
536 #define MAC_RCV_RULE_10                 0x000004d0
537 #define MAC_RCV_VALUE_10                0x000004d4
538 #define MAC_RCV_RULE_11                 0x000004d8
539 #define MAC_RCV_VALUE_11                0x000004dc
540 #define MAC_RCV_RULE_12                 0x000004e0
541 #define MAC_RCV_VALUE_12                0x000004e4
542 #define MAC_RCV_RULE_13                 0x000004e8
543 #define MAC_RCV_VALUE_13                0x000004ec
544 #define MAC_RCV_RULE_14                 0x000004f0
545 #define MAC_RCV_VALUE_14                0x000004f4
546 #define MAC_RCV_RULE_15                 0x000004f8
547 #define MAC_RCV_VALUE_15                0x000004fc
548 #define  RCV_RULE_DISABLE_MASK           0x7fffffff
549 #define MAC_RCV_RULE_CFG                0x00000500
550 #define  RCV_RULE_CFG_DEFAULT_CLASS     0x00000008
551 #define MAC_LOW_WMARK_MAX_RX_FRAME      0x00000504
552 /* 0x508 --> 0x520 unused */
553 #define MAC_HASHREGU_0                  0x00000520
554 #define MAC_HASHREGU_1                  0x00000524
555 #define MAC_HASHREGU_2                  0x00000528
556 #define MAC_HASHREGU_3                  0x0000052c
557 #define MAC_EXTADDR_0_HIGH              0x00000530
558 #define MAC_EXTADDR_0_LOW               0x00000534
559 #define MAC_EXTADDR_1_HIGH              0x00000538
560 #define MAC_EXTADDR_1_LOW               0x0000053c
561 #define MAC_EXTADDR_2_HIGH              0x00000540
562 #define MAC_EXTADDR_2_LOW               0x00000544
563 #define MAC_EXTADDR_3_HIGH              0x00000548
564 #define MAC_EXTADDR_3_LOW               0x0000054c
565 #define MAC_EXTADDR_4_HIGH              0x00000550
566 #define MAC_EXTADDR_4_LOW               0x00000554
567 #define MAC_EXTADDR_5_HIGH              0x00000558
568 #define MAC_EXTADDR_5_LOW               0x0000055c
569 #define MAC_EXTADDR_6_HIGH              0x00000560
570 #define MAC_EXTADDR_6_LOW               0x00000564
571 #define MAC_EXTADDR_7_HIGH              0x00000568
572 #define MAC_EXTADDR_7_LOW               0x0000056c
573 #define MAC_EXTADDR_8_HIGH              0x00000570
574 #define MAC_EXTADDR_8_LOW               0x00000574
575 #define MAC_EXTADDR_9_HIGH              0x00000578
576 #define MAC_EXTADDR_9_LOW               0x0000057c
577 #define MAC_EXTADDR_10_HIGH             0x00000580
578 #define MAC_EXTADDR_10_LOW              0x00000584
579 #define MAC_EXTADDR_11_HIGH             0x00000588
580 #define MAC_EXTADDR_11_LOW              0x0000058c
581 #define MAC_SERDES_CFG                  0x00000590
582 #define  MAC_SERDES_CFG_EDGE_SELECT      0x00001000
583 #define MAC_SERDES_STAT                 0x00000594
584 /* 0x598 --> 0x5a0 unused */
585 #define MAC_PHYCFG1                     0x000005a0
586 #define  MAC_PHYCFG1_RGMII_INT           0x00000001
587 #define  MAC_PHYCFG1_RXCLK_TO_MASK       0x00001ff0
588 #define  MAC_PHYCFG1_RXCLK_TIMEOUT       0x00001000
589 #define  MAC_PHYCFG1_TXCLK_TO_MASK       0x01ff0000
590 #define  MAC_PHYCFG1_TXCLK_TIMEOUT       0x01000000
591 #define  MAC_PHYCFG1_RGMII_EXT_RX_DEC    0x02000000
592 #define  MAC_PHYCFG1_RGMII_SND_STAT_EN   0x04000000
593 #define  MAC_PHYCFG1_TXC_DRV             0x20000000
594 #define MAC_PHYCFG2                     0x000005a4
595 #define  MAC_PHYCFG2_INBAND_ENABLE       0x00000001
596 #define  MAC_PHYCFG2_EMODE_MASK_MASK     0x000001c0
597 #define  MAC_PHYCFG2_EMODE_MASK_AC131    0x000000c0
598 #define  MAC_PHYCFG2_EMODE_MASK_50610    0x00000100
599 #define  MAC_PHYCFG2_EMODE_MASK_RT8211   0x00000000
600 #define  MAC_PHYCFG2_EMODE_MASK_RT8201   0x000001c0
601 #define  MAC_PHYCFG2_EMODE_COMP_MASK     0x00000e00
602 #define  MAC_PHYCFG2_EMODE_COMP_AC131    0x00000600
603 #define  MAC_PHYCFG2_EMODE_COMP_50610    0x00000400
604 #define  MAC_PHYCFG2_EMODE_COMP_RT8211   0x00000800
605 #define  MAC_PHYCFG2_EMODE_COMP_RT8201   0x00000000
606 #define  MAC_PHYCFG2_FMODE_MASK_MASK     0x00007000
607 #define  MAC_PHYCFG2_FMODE_MASK_AC131    0x00006000
608 #define  MAC_PHYCFG2_FMODE_MASK_50610    0x00004000
609 #define  MAC_PHYCFG2_FMODE_MASK_RT8211   0x00000000
610 #define  MAC_PHYCFG2_FMODE_MASK_RT8201   0x00007000
611 #define  MAC_PHYCFG2_FMODE_COMP_MASK     0x00038000
612 #define  MAC_PHYCFG2_FMODE_COMP_AC131    0x00030000
613 #define  MAC_PHYCFG2_FMODE_COMP_50610    0x00008000
614 #define  MAC_PHYCFG2_FMODE_COMP_RT8211   0x00038000
615 #define  MAC_PHYCFG2_FMODE_COMP_RT8201   0x00000000
616 #define  MAC_PHYCFG2_GMODE_MASK_MASK     0x001c0000
617 #define  MAC_PHYCFG2_GMODE_MASK_AC131    0x001c0000
618 #define  MAC_PHYCFG2_GMODE_MASK_50610    0x00100000
619 #define  MAC_PHYCFG2_GMODE_MASK_RT8211   0x00000000
620 #define  MAC_PHYCFG2_GMODE_MASK_RT8201   0x001c0000
621 #define  MAC_PHYCFG2_GMODE_COMP_MASK     0x00e00000
622 #define  MAC_PHYCFG2_GMODE_COMP_AC131    0x00e00000
623 #define  MAC_PHYCFG2_GMODE_COMP_50610    0x00000000
624 #define  MAC_PHYCFG2_GMODE_COMP_RT8211   0x00200000
625 #define  MAC_PHYCFG2_GMODE_COMP_RT8201   0x00000000
626 #define  MAC_PHYCFG2_ACT_MASK_MASK       0x03000000
627 #define  MAC_PHYCFG2_ACT_MASK_AC131      0x03000000
628 #define  MAC_PHYCFG2_ACT_MASK_50610      0x01000000
629 #define  MAC_PHYCFG2_ACT_MASK_RT8211     0x03000000
630 #define  MAC_PHYCFG2_ACT_MASK_RT8201     0x01000000
631 #define  MAC_PHYCFG2_ACT_COMP_MASK       0x0c000000
632 #define  MAC_PHYCFG2_ACT_COMP_AC131      0x00000000
633 #define  MAC_PHYCFG2_ACT_COMP_50610      0x00000000
634 #define  MAC_PHYCFG2_ACT_COMP_RT8211     0x00000000
635 #define  MAC_PHYCFG2_ACT_COMP_RT8201     0x08000000
636 #define  MAC_PHYCFG2_QUAL_MASK_MASK      0x30000000
637 #define  MAC_PHYCFG2_QUAL_MASK_AC131     0x30000000
638 #define  MAC_PHYCFG2_QUAL_MASK_50610     0x30000000
639 #define  MAC_PHYCFG2_QUAL_MASK_RT8211    0x30000000
640 #define  MAC_PHYCFG2_QUAL_MASK_RT8201    0x30000000
641 #define  MAC_PHYCFG2_QUAL_COMP_MASK      0xc0000000
642 #define  MAC_PHYCFG2_QUAL_COMP_AC131     0x00000000
643 #define  MAC_PHYCFG2_QUAL_COMP_50610     0x00000000
644 #define  MAC_PHYCFG2_QUAL_COMP_RT8211    0x00000000
645 #define  MAC_PHYCFG2_QUAL_COMP_RT8201    0x00000000
646 #define MAC_PHYCFG2_50610_LED_MODES \
647         (MAC_PHYCFG2_EMODE_MASK_50610 | \
648          MAC_PHYCFG2_EMODE_COMP_50610 | \
649          MAC_PHYCFG2_FMODE_MASK_50610 | \
650          MAC_PHYCFG2_FMODE_COMP_50610 | \
651          MAC_PHYCFG2_GMODE_MASK_50610 | \
652          MAC_PHYCFG2_GMODE_COMP_50610 | \
653          MAC_PHYCFG2_ACT_MASK_50610 | \
654          MAC_PHYCFG2_ACT_COMP_50610 | \
655          MAC_PHYCFG2_QUAL_MASK_50610 | \
656          MAC_PHYCFG2_QUAL_COMP_50610)
657 #define MAC_PHYCFG2_AC131_LED_MODES \
658         (MAC_PHYCFG2_EMODE_MASK_AC131 | \
659          MAC_PHYCFG2_EMODE_COMP_AC131 | \
660          MAC_PHYCFG2_FMODE_MASK_AC131 | \
661          MAC_PHYCFG2_FMODE_COMP_AC131 | \
662          MAC_PHYCFG2_GMODE_MASK_AC131 | \
663          MAC_PHYCFG2_GMODE_COMP_AC131 | \
664          MAC_PHYCFG2_ACT_MASK_AC131 | \
665          MAC_PHYCFG2_ACT_COMP_AC131 | \
666          MAC_PHYCFG2_QUAL_MASK_AC131 | \
667          MAC_PHYCFG2_QUAL_COMP_AC131)
668 #define MAC_PHYCFG2_RTL8211C_LED_MODES \
669         (MAC_PHYCFG2_EMODE_MASK_RT8211 | \
670          MAC_PHYCFG2_EMODE_COMP_RT8211 | \
671          MAC_PHYCFG2_FMODE_MASK_RT8211 | \
672          MAC_PHYCFG2_FMODE_COMP_RT8211 | \
673          MAC_PHYCFG2_GMODE_MASK_RT8211 | \
674          MAC_PHYCFG2_GMODE_COMP_RT8211 | \
675          MAC_PHYCFG2_ACT_MASK_RT8211 | \
676          MAC_PHYCFG2_ACT_COMP_RT8211 | \
677          MAC_PHYCFG2_QUAL_MASK_RT8211 | \
678          MAC_PHYCFG2_QUAL_COMP_RT8211)
679 #define MAC_PHYCFG2_RTL8201E_LED_MODES \
680         (MAC_PHYCFG2_EMODE_MASK_RT8201 | \
681          MAC_PHYCFG2_EMODE_COMP_RT8201 | \
682          MAC_PHYCFG2_FMODE_MASK_RT8201 | \
683          MAC_PHYCFG2_FMODE_COMP_RT8201 | \
684          MAC_PHYCFG2_GMODE_MASK_RT8201 | \
685          MAC_PHYCFG2_GMODE_COMP_RT8201 | \
686          MAC_PHYCFG2_ACT_MASK_RT8201 | \
687          MAC_PHYCFG2_ACT_COMP_RT8201 | \
688          MAC_PHYCFG2_QUAL_MASK_RT8201 | \
689          MAC_PHYCFG2_QUAL_COMP_RT8201)
690 #define MAC_EXT_RGMII_MODE              0x000005a8
691 #define  MAC_RGMII_MODE_TX_ENABLE        0x00000001
692 #define  MAC_RGMII_MODE_TX_LOWPWR        0x00000002
693 #define  MAC_RGMII_MODE_TX_RESET         0x00000004
694 #define  MAC_RGMII_MODE_RX_INT_B         0x00000100
695 #define  MAC_RGMII_MODE_RX_QUALITY       0x00000200
696 #define  MAC_RGMII_MODE_RX_ACTIVITY      0x00000400
697 #define  MAC_RGMII_MODE_RX_ENG_DET       0x00000800
698 /* 0x5ac --> 0x5b0 unused */
699 #define SERDES_RX_CTRL                  0x000005b0      /* 5780/5714 only */
700 #define  SERDES_RX_SIG_DETECT            0x00000400
701 #define SG_DIG_CTRL                     0x000005b0
702 #define  SG_DIG_USING_HW_AUTONEG         0x80000000
703 #define  SG_DIG_SOFT_RESET               0x40000000
704 #define  SG_DIG_DISABLE_LINKRDY          0x20000000
705 #define  SG_DIG_CRC16_CLEAR_N            0x01000000
706 #define  SG_DIG_EN10B                    0x00800000
707 #define  SG_DIG_CLEAR_STATUS             0x00400000
708 #define  SG_DIG_LOCAL_DUPLEX_STATUS      0x00200000
709 #define  SG_DIG_LOCAL_LINK_STATUS        0x00100000
710 #define  SG_DIG_SPEED_STATUS_MASK        0x000c0000
711 #define  SG_DIG_SPEED_STATUS_SHIFT       18
712 #define  SG_DIG_JUMBO_PACKET_DISABLE     0x00020000
713 #define  SG_DIG_RESTART_AUTONEG          0x00010000
714 #define  SG_DIG_FIBER_MODE               0x00008000
715 #define  SG_DIG_REMOTE_FAULT_MASK        0x00006000
716 #define  SG_DIG_PAUSE_MASK               0x00001800
717 #define  SG_DIG_PAUSE_CAP                0x00000800
718 #define  SG_DIG_ASYM_PAUSE               0x00001000
719 #define  SG_DIG_GBIC_ENABLE              0x00000400
720 #define  SG_DIG_CHECK_END_ENABLE         0x00000200
721 #define  SG_DIG_SGMII_AUTONEG_TIMER      0x00000100
722 #define  SG_DIG_CLOCK_PHASE_SELECT       0x00000080
723 #define  SG_DIG_GMII_INPUT_SELECT        0x00000040
724 #define  SG_DIG_MRADV_CRC16_SELECT       0x00000020
725 #define  SG_DIG_COMMA_DETECT_ENABLE      0x00000010
726 #define  SG_DIG_AUTONEG_TIMER_REDUCE     0x00000008
727 #define  SG_DIG_AUTONEG_LOW_ENABLE       0x00000004
728 #define  SG_DIG_REMOTE_LOOPBACK          0x00000002
729 #define  SG_DIG_LOOPBACK                 0x00000001
730 #define  SG_DIG_COMMON_SETUP (SG_DIG_CRC16_CLEAR_N | \
731                               SG_DIG_LOCAL_DUPLEX_STATUS | \
732                               SG_DIG_LOCAL_LINK_STATUS | \
733                               (0x2 << SG_DIG_SPEED_STATUS_SHIFT) | \
734                               SG_DIG_FIBER_MODE | SG_DIG_GBIC_ENABLE)
735 #define SG_DIG_STATUS                   0x000005b4
736 #define  SG_DIG_CRC16_BUS_MASK           0xffff0000
737 #define  SG_DIG_PARTNER_FAULT_MASK       0x00600000 /* If !MRADV_CRC16_SELECT */
738 #define  SG_DIG_PARTNER_ASYM_PAUSE       0x00100000 /* If !MRADV_CRC16_SELECT */
739 #define  SG_DIG_PARTNER_PAUSE_CAPABLE    0x00080000 /* If !MRADV_CRC16_SELECT */
740 #define  SG_DIG_PARTNER_HALF_DUPLEX      0x00040000 /* If !MRADV_CRC16_SELECT */
741 #define  SG_DIG_PARTNER_FULL_DUPLEX      0x00020000 /* If !MRADV_CRC16_SELECT */
742 #define  SG_DIG_PARTNER_NEXT_PAGE        0x00010000 /* If !MRADV_CRC16_SELECT */
743 #define  SG_DIG_AUTONEG_STATE_MASK       0x00000ff0
744 #define  SG_DIG_IS_SERDES                0x00000100
745 #define  SG_DIG_COMMA_DETECTOR           0x00000008
746 #define  SG_DIG_MAC_ACK_STATUS           0x00000004
747 #define  SG_DIG_AUTONEG_COMPLETE         0x00000002
748 #define  SG_DIG_AUTONEG_ERROR            0x00000001
749 /* 0x5b8 --> 0x600 unused */
750 #define MAC_TX_MAC_STATE_BASE           0x00000600 /* 16 bytes */
751 #define MAC_RX_MAC_STATE_BASE           0x00000610 /* 20 bytes */
752 /* 0x624 --> 0x670 unused */
753
754 #define MAC_RSS_INDIR_TBL_0             0x00000630
755
756 #define MAC_RSS_HASH_KEY_0              0x00000670
757 #define MAC_RSS_HASH_KEY_1              0x00000674
758 #define MAC_RSS_HASH_KEY_2              0x00000678
759 #define MAC_RSS_HASH_KEY_3              0x0000067c
760 #define MAC_RSS_HASH_KEY_4              0x00000680
761 #define MAC_RSS_HASH_KEY_5              0x00000684
762 #define MAC_RSS_HASH_KEY_6              0x00000688
763 #define MAC_RSS_HASH_KEY_7              0x0000068c
764 #define MAC_RSS_HASH_KEY_8              0x00000690
765 #define MAC_RSS_HASH_KEY_9              0x00000694
766 /* 0x698 --> 0x800 unused */
767
768 #define MAC_TX_STATS_OCTETS             0x00000800
769 #define MAC_TX_STATS_RESV1              0x00000804
770 #define MAC_TX_STATS_COLLISIONS         0x00000808
771 #define MAC_TX_STATS_XON_SENT           0x0000080c
772 #define MAC_TX_STATS_XOFF_SENT          0x00000810
773 #define MAC_TX_STATS_RESV2              0x00000814
774 #define MAC_TX_STATS_MAC_ERRORS         0x00000818
775 #define MAC_TX_STATS_SINGLE_COLLISIONS  0x0000081c
776 #define MAC_TX_STATS_MULT_COLLISIONS    0x00000820
777 #define MAC_TX_STATS_DEFERRED           0x00000824
778 #define MAC_TX_STATS_RESV3              0x00000828
779 #define MAC_TX_STATS_EXCESSIVE_COL      0x0000082c
780 #define MAC_TX_STATS_LATE_COL           0x00000830
781 #define MAC_TX_STATS_RESV4_1            0x00000834
782 #define MAC_TX_STATS_RESV4_2            0x00000838
783 #define MAC_TX_STATS_RESV4_3            0x0000083c
784 #define MAC_TX_STATS_RESV4_4            0x00000840
785 #define MAC_TX_STATS_RESV4_5            0x00000844
786 #define MAC_TX_STATS_RESV4_6            0x00000848
787 #define MAC_TX_STATS_RESV4_7            0x0000084c
788 #define MAC_TX_STATS_RESV4_8            0x00000850
789 #define MAC_TX_STATS_RESV4_9            0x00000854
790 #define MAC_TX_STATS_RESV4_10           0x00000858
791 #define MAC_TX_STATS_RESV4_11           0x0000085c
792 #define MAC_TX_STATS_RESV4_12           0x00000860
793 #define MAC_TX_STATS_RESV4_13           0x00000864
794 #define MAC_TX_STATS_RESV4_14           0x00000868
795 #define MAC_TX_STATS_UCAST              0x0000086c
796 #define MAC_TX_STATS_MCAST              0x00000870
797 #define MAC_TX_STATS_BCAST              0x00000874
798 #define MAC_TX_STATS_RESV5_1            0x00000878
799 #define MAC_TX_STATS_RESV5_2            0x0000087c
800 #define MAC_RX_STATS_OCTETS             0x00000880
801 #define MAC_RX_STATS_RESV1              0x00000884
802 #define MAC_RX_STATS_FRAGMENTS          0x00000888
803 #define MAC_RX_STATS_UCAST              0x0000088c
804 #define MAC_RX_STATS_MCAST              0x00000890
805 #define MAC_RX_STATS_BCAST              0x00000894
806 #define MAC_RX_STATS_FCS_ERRORS         0x00000898
807 #define MAC_RX_STATS_ALIGN_ERRORS       0x0000089c
808 #define MAC_RX_STATS_XON_PAUSE_RECVD    0x000008a0
809 #define MAC_RX_STATS_XOFF_PAUSE_RECVD   0x000008a4
810 #define MAC_RX_STATS_MAC_CTRL_RECVD     0x000008a8
811 #define MAC_RX_STATS_XOFF_ENTERED       0x000008ac
812 #define MAC_RX_STATS_FRAME_TOO_LONG     0x000008b0
813 #define MAC_RX_STATS_JABBERS            0x000008b4
814 #define MAC_RX_STATS_UNDERSIZE          0x000008b8
815 /* 0x8bc --> 0xc00 unused */
816
817 /* Send data initiator control registers */
818 #define SNDDATAI_MODE                   0x00000c00
819 #define  SNDDATAI_MODE_RESET             0x00000001
820 #define  SNDDATAI_MODE_ENABLE            0x00000002
821 #define  SNDDATAI_MODE_STAT_OFLOW_ENAB   0x00000004
822 #define SNDDATAI_STATUS                 0x00000c04
823 #define  SNDDATAI_STATUS_STAT_OFLOW      0x00000004
824 #define SNDDATAI_STATSCTRL              0x00000c08
825 #define  SNDDATAI_SCTRL_ENABLE           0x00000001
826 #define  SNDDATAI_SCTRL_FASTUPD          0x00000002
827 #define  SNDDATAI_SCTRL_CLEAR            0x00000004
828 #define  SNDDATAI_SCTRL_FLUSH            0x00000008
829 #define  SNDDATAI_SCTRL_FORCE_ZERO       0x00000010
830 #define SNDDATAI_STATSENAB              0x00000c0c
831 #define SNDDATAI_STATSINCMASK           0x00000c10
832 #define ISO_PKT_TX                      0x00000c20
833 /* 0xc24 --> 0xc80 unused */
834 #define SNDDATAI_COS_CNT_0              0x00000c80
835 #define SNDDATAI_COS_CNT_1              0x00000c84
836 #define SNDDATAI_COS_CNT_2              0x00000c88
837 #define SNDDATAI_COS_CNT_3              0x00000c8c
838 #define SNDDATAI_COS_CNT_4              0x00000c90
839 #define SNDDATAI_COS_CNT_5              0x00000c94
840 #define SNDDATAI_COS_CNT_6              0x00000c98
841 #define SNDDATAI_COS_CNT_7              0x00000c9c
842 #define SNDDATAI_COS_CNT_8              0x00000ca0
843 #define SNDDATAI_COS_CNT_9              0x00000ca4
844 #define SNDDATAI_COS_CNT_10             0x00000ca8
845 #define SNDDATAI_COS_CNT_11             0x00000cac
846 #define SNDDATAI_COS_CNT_12             0x00000cb0
847 #define SNDDATAI_COS_CNT_13             0x00000cb4
848 #define SNDDATAI_COS_CNT_14             0x00000cb8
849 #define SNDDATAI_COS_CNT_15             0x00000cbc
850 #define SNDDATAI_DMA_RDQ_FULL_CNT       0x00000cc0
851 #define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT  0x00000cc4
852 #define SNDDATAI_SDCQ_FULL_CNT          0x00000cc8
853 #define SNDDATAI_NICRNG_SSND_PIDX_CNT   0x00000ccc
854 #define SNDDATAI_STATS_UPDATED_CNT      0x00000cd0
855 #define SNDDATAI_INTERRUPTS_CNT         0x00000cd4
856 #define SNDDATAI_AVOID_INTERRUPTS_CNT   0x00000cd8
857 #define SNDDATAI_SND_THRESH_HIT_CNT     0x00000cdc
858 /* 0xce0 --> 0x1000 unused */
859
860 /* Send data completion control registers */
861 #define SNDDATAC_MODE                   0x00001000
862 #define  SNDDATAC_MODE_RESET             0x00000001
863 #define  SNDDATAC_MODE_ENABLE            0x00000002
864 #define  SNDDATAC_MODE_CDELAY            0x00000010
865 /* 0x1004 --> 0x1400 unused */
866
867 /* Send BD ring selector */
868 #define SNDBDS_MODE                     0x00001400
869 #define  SNDBDS_MODE_RESET               0x00000001
870 #define  SNDBDS_MODE_ENABLE              0x00000002
871 #define  SNDBDS_MODE_ATTN_ENABLE         0x00000004
872 #define SNDBDS_STATUS                   0x00001404
873 #define  SNDBDS_STATUS_ERROR_ATTN        0x00000004
874 #define SNDBDS_HWDIAG                   0x00001408
875 /* 0x140c --> 0x1440 */
876 #define SNDBDS_SEL_CON_IDX_0            0x00001440
877 #define SNDBDS_SEL_CON_IDX_1            0x00001444
878 #define SNDBDS_SEL_CON_IDX_2            0x00001448
879 #define SNDBDS_SEL_CON_IDX_3            0x0000144c
880 #define SNDBDS_SEL_CON_IDX_4            0x00001450
881 #define SNDBDS_SEL_CON_IDX_5            0x00001454
882 #define SNDBDS_SEL_CON_IDX_6            0x00001458
883 #define SNDBDS_SEL_CON_IDX_7            0x0000145c
884 #define SNDBDS_SEL_CON_IDX_8            0x00001460
885 #define SNDBDS_SEL_CON_IDX_9            0x00001464
886 #define SNDBDS_SEL_CON_IDX_10           0x00001468
887 #define SNDBDS_SEL_CON_IDX_11           0x0000146c
888 #define SNDBDS_SEL_CON_IDX_12           0x00001470
889 #define SNDBDS_SEL_CON_IDX_13           0x00001474
890 #define SNDBDS_SEL_CON_IDX_14           0x00001478
891 #define SNDBDS_SEL_CON_IDX_15           0x0000147c
892 /* 0x1480 --> 0x1800 unused */
893
894 /* Send BD initiator control registers */
895 #define SNDBDI_MODE                     0x00001800
896 #define  SNDBDI_MODE_RESET               0x00000001
897 #define  SNDBDI_MODE_ENABLE              0x00000002
898 #define  SNDBDI_MODE_ATTN_ENABLE         0x00000004
899 #define  SNDBDI_MODE_MULTI_TXQ_EN        0x00000020
900 #define SNDBDI_STATUS                   0x00001804
901 #define  SNDBDI_STATUS_ERROR_ATTN        0x00000004
902 #define SNDBDI_IN_PROD_IDX_0            0x00001808
903 #define SNDBDI_IN_PROD_IDX_1            0x0000180c
904 #define SNDBDI_IN_PROD_IDX_2            0x00001810
905 #define SNDBDI_IN_PROD_IDX_3            0x00001814
906 #define SNDBDI_IN_PROD_IDX_4            0x00001818
907 #define SNDBDI_IN_PROD_IDX_5            0x0000181c
908 #define SNDBDI_IN_PROD_IDX_6            0x00001820
909 #define SNDBDI_IN_PROD_IDX_7            0x00001824
910 #define SNDBDI_IN_PROD_IDX_8            0x00001828
911 #define SNDBDI_IN_PROD_IDX_9            0x0000182c
912 #define SNDBDI_IN_PROD_IDX_10           0x00001830
913 #define SNDBDI_IN_PROD_IDX_11           0x00001834
914 #define SNDBDI_IN_PROD_IDX_12           0x00001838
915 #define SNDBDI_IN_PROD_IDX_13           0x0000183c
916 #define SNDBDI_IN_PROD_IDX_14           0x00001840
917 #define SNDBDI_IN_PROD_IDX_15           0x00001844
918 /* 0x1848 --> 0x1c00 unused */
919
920 /* Send BD completion control registers */
921 #define SNDBDC_MODE                     0x00001c00
922 #define SNDBDC_MODE_RESET                0x00000001
923 #define SNDBDC_MODE_ENABLE               0x00000002
924 #define SNDBDC_MODE_ATTN_ENABLE          0x00000004
925 /* 0x1c04 --> 0x2000 unused */
926
927 /* Receive list placement control registers */
928 #define RCVLPC_MODE                     0x00002000
929 #define  RCVLPC_MODE_RESET               0x00000001
930 #define  RCVLPC_MODE_ENABLE              0x00000002
931 #define  RCVLPC_MODE_CLASS0_ATTN_ENAB    0x00000004
932 #define  RCVLPC_MODE_MAPOOR_AATTN_ENAB   0x00000008
933 #define  RCVLPC_MODE_STAT_OFLOW_ENAB     0x00000010
934 #define RCVLPC_STATUS                   0x00002004
935 #define  RCVLPC_STATUS_CLASS0            0x00000004
936 #define  RCVLPC_STATUS_MAPOOR            0x00000008
937 #define  RCVLPC_STATUS_STAT_OFLOW        0x00000010
938 #define RCVLPC_LOCK                     0x00002008
939 #define  RCVLPC_LOCK_REQ_MASK            0x0000ffff
940 #define  RCVLPC_LOCK_REQ_SHIFT           0
941 #define  RCVLPC_LOCK_GRANT_MASK          0xffff0000
942 #define  RCVLPC_LOCK_GRANT_SHIFT         16
943 #define RCVLPC_NON_EMPTY_BITS           0x0000200c
944 #define  RCVLPC_NON_EMPTY_BITS_MASK      0x0000ffff
945 #define RCVLPC_CONFIG                   0x00002010
946 #define RCVLPC_STATSCTRL                0x00002014
947 #define  RCVLPC_STATSCTRL_ENABLE         0x00000001
948 #define  RCVLPC_STATSCTRL_FASTUPD        0x00000002
949 #define RCVLPC_STATS_ENABLE             0x00002018
950 #define  RCVLPC_STATSENAB_ASF_FIX        0x00000002
951 #define  RCVLPC_STATSENAB_DACK_FIX       0x00040000
952 #define  RCVLPC_STATSENAB_LNGBRST_RFIX   0x00400000
953 #define RCVLPC_STATS_INCMASK            0x0000201c
954 /* 0x2020 --> 0x2100 unused */
955 #define RCVLPC_SELLST_BASE              0x00002100 /* 16 16-byte entries */
956 #define  SELLST_TAIL                    0x00000004
957 #define  SELLST_CONT                    0x00000008
958 #define  SELLST_UNUSED                  0x0000000c
959 #define RCVLPC_COS_CNTL_BASE            0x00002200 /* 16 4-byte entries */
960 #define RCVLPC_DROP_FILTER_CNT          0x00002240
961 #define RCVLPC_DMA_WQ_FULL_CNT          0x00002244
962 #define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT   0x00002248
963 #define RCVLPC_NO_RCV_BD_CNT            0x0000224c
964 #define RCVLPC_IN_DISCARDS_CNT          0x00002250
965 #define RCVLPC_IN_ERRORS_CNT            0x00002254
966 #define RCVLPC_RCV_THRESH_HIT_CNT       0x00002258
967 /* 0x225c --> 0x2400 unused */
968
969 /* Receive Data and Receive BD Initiator Control */
970 #define RCVDBDI_MODE                    0x00002400
971 #define  RCVDBDI_MODE_RESET              0x00000001
972 #define  RCVDBDI_MODE_ENABLE             0x00000002
973 #define  RCVDBDI_MODE_JUMBOBD_NEEDED     0x00000004
974 #define  RCVDBDI_MODE_FRM_TOO_BIG        0x00000008
975 #define  RCVDBDI_MODE_INV_RING_SZ        0x00000010
976 #define  RCVDBDI_MODE_LRG_RING_SZ        0x00010000
977 #define RCVDBDI_STATUS                  0x00002404
978 #define  RCVDBDI_STATUS_JUMBOBD_NEEDED   0x00000004
979 #define  RCVDBDI_STATUS_FRM_TOO_BIG      0x00000008
980 #define  RCVDBDI_STATUS_INV_RING_SZ      0x00000010
981 #define RCVDBDI_SPLIT_FRAME_MINSZ       0x00002408
982 /* 0x240c --> 0x2440 unused */
983 #define RCVDBDI_JUMBO_BD                0x00002440 /* TG3_BDINFO_... */
984 #define RCVDBDI_STD_BD                  0x00002450 /* TG3_BDINFO_... */
985 #define RCVDBDI_MINI_BD                 0x00002460 /* TG3_BDINFO_... */
986 #define RCVDBDI_JUMBO_CON_IDX           0x00002470
987 #define RCVDBDI_STD_CON_IDX             0x00002474
988 #define RCVDBDI_MINI_CON_IDX            0x00002478
989 /* 0x247c --> 0x2480 unused */
990 #define RCVDBDI_BD_PROD_IDX_0           0x00002480
991 #define RCVDBDI_BD_PROD_IDX_1           0x00002484
992 #define RCVDBDI_BD_PROD_IDX_2           0x00002488
993 #define RCVDBDI_BD_PROD_IDX_3           0x0000248c
994 #define RCVDBDI_BD_PROD_IDX_4           0x00002490
995 #define RCVDBDI_BD_PROD_IDX_5           0x00002494
996 #define RCVDBDI_BD_PROD_IDX_6           0x00002498
997 #define RCVDBDI_BD_PROD_IDX_7           0x0000249c
998 #define RCVDBDI_BD_PROD_IDX_8           0x000024a0
999 #define RCVDBDI_BD_PROD_IDX_9           0x000024a4
1000 #define RCVDBDI_BD_PROD_IDX_10          0x000024a8
1001 #define RCVDBDI_BD_PROD_IDX_11          0x000024ac
1002 #define RCVDBDI_BD_PROD_IDX_12          0x000024b0
1003 #define RCVDBDI_BD_PROD_IDX_13          0x000024b4
1004 #define RCVDBDI_BD_PROD_IDX_14          0x000024b8
1005 #define RCVDBDI_BD_PROD_IDX_15          0x000024bc
1006 #define RCVDBDI_HWDIAG                  0x000024c0
1007 /* 0x24c4 --> 0x2800 unused */
1008
1009 /* Receive Data Completion Control */
1010 #define RCVDCC_MODE                     0x00002800
1011 #define  RCVDCC_MODE_RESET               0x00000001
1012 #define  RCVDCC_MODE_ENABLE              0x00000002
1013 #define  RCVDCC_MODE_ATTN_ENABLE         0x00000004
1014 /* 0x2804 --> 0x2c00 unused */
1015
1016 /* Receive BD Initiator Control Registers */
1017 #define RCVBDI_MODE                     0x00002c00
1018 #define  RCVBDI_MODE_RESET               0x00000001
1019 #define  RCVBDI_MODE_ENABLE              0x00000002
1020 #define  RCVBDI_MODE_RCB_ATTN_ENAB       0x00000004
1021 #define RCVBDI_STATUS                   0x00002c04
1022 #define  RCVBDI_STATUS_RCB_ATTN          0x00000004
1023 #define RCVBDI_JUMBO_PROD_IDX           0x00002c08
1024 #define RCVBDI_STD_PROD_IDX             0x00002c0c
1025 #define RCVBDI_MINI_PROD_IDX            0x00002c10
1026 #define RCVBDI_MINI_THRESH              0x00002c14
1027 #define RCVBDI_STD_THRESH               0x00002c18
1028 #define RCVBDI_JUMBO_THRESH             0x00002c1c
1029 /* 0x2c20 --> 0x2d00 unused */
1030
1031 #define STD_REPLENISH_LWM               0x00002d00
1032 #define JMB_REPLENISH_LWM               0x00002d04
1033 /* 0x2d08 --> 0x3000 unused */
1034
1035 /* Receive BD Completion Control Registers */
1036 #define RCVCC_MODE                      0x00003000
1037 #define  RCVCC_MODE_RESET                0x00000001
1038 #define  RCVCC_MODE_ENABLE               0x00000002
1039 #define  RCVCC_MODE_ATTN_ENABLE          0x00000004
1040 #define RCVCC_STATUS                    0x00003004
1041 #define  RCVCC_STATUS_ERROR_ATTN         0x00000004
1042 #define RCVCC_JUMP_PROD_IDX             0x00003008
1043 #define RCVCC_STD_PROD_IDX              0x0000300c
1044 #define RCVCC_MINI_PROD_IDX             0x00003010
1045 /* 0x3014 --> 0x3400 unused */
1046
1047 /* Receive list selector control registers */
1048 #define RCVLSC_MODE                     0x00003400
1049 #define  RCVLSC_MODE_RESET               0x00000001
1050 #define  RCVLSC_MODE_ENABLE              0x00000002
1051 #define  RCVLSC_MODE_ATTN_ENABLE         0x00000004
1052 #define RCVLSC_STATUS                   0x00003404
1053 #define  RCVLSC_STATUS_ERROR_ATTN        0x00000004
1054 /* 0x3408 --> 0x3600 unused */
1055
1056 /* CPMU registers */
1057 #define TG3_CPMU_CTRL                   0x00003600
1058 #define  CPMU_CTRL_LINK_IDLE_MODE        0x00000200
1059 #define  CPMU_CTRL_LINK_AWARE_MODE       0x00000400
1060 #define  CPMU_CTRL_LINK_SPEED_MODE       0x00004000
1061 #define  CPMU_CTRL_GPHY_10MB_RXONLY      0x00010000
1062 #define TG3_CPMU_LSPD_10MB_CLK          0x00003604
1063 #define  CPMU_LSPD_10MB_MACCLK_MASK      0x001f0000
1064 #define  CPMU_LSPD_10MB_MACCLK_6_25      0x00130000
1065 /* 0x3608 --> 0x360c unused */
1066
1067 #define TG3_CPMU_LSPD_1000MB_CLK        0x0000360c
1068 #define  CPMU_LSPD_1000MB_MACCLK_62_5    0x00000000
1069 #define  CPMU_LSPD_1000MB_MACCLK_12_5    0x00110000
1070 #define  CPMU_LSPD_1000MB_MACCLK_MASK    0x001f0000
1071 #define TG3_CPMU_LNK_AWARE_PWRMD        0x00003610
1072 #define  CPMU_LNK_AWARE_MACCLK_MASK      0x001f0000
1073 #define  CPMU_LNK_AWARE_MACCLK_6_25      0x00130000
1074 /* 0x3614 --> 0x361c unused */
1075
1076 #define TG3_CPMU_HST_ACC                0x0000361c
1077 #define  CPMU_HST_ACC_MACCLK_MASK        0x001f0000
1078 #define  CPMU_HST_ACC_MACCLK_6_25        0x00130000
1079 /* 0x3620 --> 0x3630 unused */
1080
1081 #define TG3_CPMU_CLCK_STAT              0x00003630
1082 #define  CPMU_CLCK_STAT_MAC_CLCK_MASK    0x001f0000
1083 #define  CPMU_CLCK_STAT_MAC_CLCK_62_5    0x00000000
1084 #define  CPMU_CLCK_STAT_MAC_CLCK_12_5    0x00110000
1085 #define  CPMU_CLCK_STAT_MAC_CLCK_6_25    0x00130000
1086 /* 0x3634 --> 0x365c unused */
1087
1088 #define TG3_CPMU_MUTEX_REQ              0x0000365c
1089 #define  CPMU_MUTEX_REQ_DRIVER           0x00001000
1090 #define TG3_CPMU_MUTEX_GNT              0x00003660
1091 #define  CPMU_MUTEX_GNT_DRIVER           0x00001000
1092 #define TG3_CPMU_PHY_STRAP              0x00003664
1093 #define TG3_CPMU_PHY_STRAP_IS_SERDES     0x00000020
1094 /* 0x3664 --> 0x36b0 unused */
1095
1096 #define TG3_CPMU_EEE_MODE               0x000036b0
1097 #define TG3_CPMU_EEEMD_ERLY_L1_XIT_DET   0x00000008
1098 #define TG3_CPMU_EEEMD_LPI_ENABLE        0x00000080
1099 #define TG3_CPMU_EEEMD_LPI_IN_TX         0x00000100
1100 #define TG3_CPMU_EEEMD_LPI_IN_RX         0x00000200
1101 #define TG3_CPMU_EEEMD_EEE_ENABLE        0x00100000
1102 /* 0x36b4 --> 0x36b8 unused */
1103
1104 #define TG3_CPMU_EEE_LNKIDL_CTRL        0x000036bc
1105 #define  TG3_CPMU_EEE_LNKIDL_PCIE_NL0    0x01000000
1106 #define  TG3_CPMU_EEE_LNKIDL_UART_IDL    0x00000004
1107 /* 0x36c0 --> 0x36d0 unused */
1108
1109 #define TG3_CPMU_EEE_CTRL               0x000036d0
1110 #define TG3_CPMU_EEE_CTRL_EXIT_16_5_US   0x0000019d
1111 #define TG3_CPMU_EEE_CTRL_EXIT_36_US     0x00000384
1112 #define TG3_CPMU_EEE_CTRL_EXIT_20_1_US   0x000001f8
1113 /* 0x36d4 --> 0x3800 unused */
1114
1115 /* Mbuf cluster free registers */
1116 #define MBFREE_MODE                     0x00003800
1117 #define  MBFREE_MODE_RESET               0x00000001
1118 #define  MBFREE_MODE_ENABLE              0x00000002
1119 #define MBFREE_STATUS                   0x00003804
1120 /* 0x3808 --> 0x3c00 unused */
1121
1122 /* Host coalescing control registers */
1123 #define HOSTCC_MODE                     0x00003c00
1124 #define  HOSTCC_MODE_RESET               0x00000001
1125 #define  HOSTCC_MODE_ENABLE              0x00000002
1126 #define  HOSTCC_MODE_ATTN                0x00000004
1127 #define  HOSTCC_MODE_NOW                 0x00000008
1128 #define  HOSTCC_MODE_FULL_STATUS         0x00000000
1129 #define  HOSTCC_MODE_64BYTE              0x00000080
1130 #define  HOSTCC_MODE_32BYTE              0x00000100
1131 #define  HOSTCC_MODE_CLRTICK_RXBD        0x00000200
1132 #define  HOSTCC_MODE_CLRTICK_TXBD        0x00000400
1133 #define  HOSTCC_MODE_NOINT_ON_NOW        0x00000800
1134 #define  HOSTCC_MODE_NOINT_ON_FORCE      0x00001000
1135 #define  HOSTCC_MODE_COAL_VEC1_NOW       0x00002000
1136 #define HOSTCC_STATUS                   0x00003c04
1137 #define  HOSTCC_STATUS_ERROR_ATTN        0x00000004
1138 #define HOSTCC_RXCOL_TICKS              0x00003c08
1139 #define  LOW_RXCOL_TICKS                 0x00000032
1140 #define  LOW_RXCOL_TICKS_CLRTCKS         0x00000014
1141 #define  DEFAULT_RXCOL_TICKS             0x00000048
1142 #define  HIGH_RXCOL_TICKS                0x00000096
1143 #define  MAX_RXCOL_TICKS                 0x000003ff
1144 #define HOSTCC_TXCOL_TICKS              0x00003c0c
1145 #define  LOW_TXCOL_TICKS                 0x00000096
1146 #define  LOW_TXCOL_TICKS_CLRTCKS         0x00000048
1147 #define  DEFAULT_TXCOL_TICKS             0x0000012c
1148 #define  HIGH_TXCOL_TICKS                0x00000145
1149 #define  MAX_TXCOL_TICKS                 0x000003ff
1150 #define HOSTCC_RXMAX_FRAMES             0x00003c10
1151 #define  LOW_RXMAX_FRAMES                0x00000005
1152 #define  DEFAULT_RXMAX_FRAMES            0x00000008
1153 #define  HIGH_RXMAX_FRAMES               0x00000012
1154 #define  MAX_RXMAX_FRAMES                0x000000ff
1155 #define HOSTCC_TXMAX_FRAMES             0x00003c14
1156 #define  LOW_TXMAX_FRAMES                0x00000035
1157 #define  DEFAULT_TXMAX_FRAMES            0x0000004b
1158 #define  HIGH_TXMAX_FRAMES               0x00000052
1159 #define  MAX_TXMAX_FRAMES                0x000000ff
1160 #define HOSTCC_RXCOAL_TICK_INT          0x00003c18
1161 #define  DEFAULT_RXCOAL_TICK_INT         0x00000019
1162 #define  DEFAULT_RXCOAL_TICK_INT_CLRTCKS 0x00000014
1163 #define  MAX_RXCOAL_TICK_INT             0x000003ff
1164 #define HOSTCC_TXCOAL_TICK_INT          0x00003c1c
1165 #define  DEFAULT_TXCOAL_TICK_INT         0x00000019
1166 #define  DEFAULT_TXCOAL_TICK_INT_CLRTCKS 0x00000014
1167 #define  MAX_TXCOAL_TICK_INT             0x000003ff
1168 #define HOSTCC_RXCOAL_MAXF_INT          0x00003c20
1169 #define  DEFAULT_RXCOAL_MAXF_INT         0x00000005
1170 #define  MAX_RXCOAL_MAXF_INT             0x000000ff
1171 #define HOSTCC_TXCOAL_MAXF_INT          0x00003c24
1172 #define  DEFAULT_TXCOAL_MAXF_INT         0x00000005
1173 #define  MAX_TXCOAL_MAXF_INT             0x000000ff
1174 #define HOSTCC_STAT_COAL_TICKS          0x00003c28
1175 #define  DEFAULT_STAT_COAL_TICKS         0x000f4240
1176 #define  MAX_STAT_COAL_TICKS             0xd693d400
1177 #define  MIN_STAT_COAL_TICKS             0x00000064
1178 /* 0x3c2c --> 0x3c30 unused */
1179 #define HOSTCC_STATS_BLK_HOST_ADDR      0x00003c30 /* 64-bit */
1180 #define HOSTCC_STATUS_BLK_HOST_ADDR     0x00003c38 /* 64-bit */
1181 #define HOSTCC_STATS_BLK_NIC_ADDR       0x00003c40
1182 #define HOSTCC_STATUS_BLK_NIC_ADDR      0x00003c44
1183 #define HOSTCC_FLOW_ATTN                0x00003c48
1184 /* 0x3c4c --> 0x3c50 unused */
1185 #define HOSTCC_JUMBO_CON_IDX            0x00003c50
1186 #define HOSTCC_STD_CON_IDX              0x00003c54
1187 #define HOSTCC_MINI_CON_IDX             0x00003c58
1188 /* 0x3c5c --> 0x3c80 unused */
1189 #define HOSTCC_RET_PROD_IDX_0           0x00003c80
1190 #define HOSTCC_RET_PROD_IDX_1           0x00003c84
1191 #define HOSTCC_RET_PROD_IDX_2           0x00003c88
1192 #define HOSTCC_RET_PROD_IDX_3           0x00003c8c
1193 #define HOSTCC_RET_PROD_IDX_4           0x00003c90
1194 #define HOSTCC_RET_PROD_IDX_5           0x00003c94
1195 #define HOSTCC_RET_PROD_IDX_6           0x00003c98
1196 #define HOSTCC_RET_PROD_IDX_7           0x00003c9c
1197 #define HOSTCC_RET_PROD_IDX_8           0x00003ca0
1198 #define HOSTCC_RET_PROD_IDX_9           0x00003ca4
1199 #define HOSTCC_RET_PROD_IDX_10          0x00003ca8
1200 #define HOSTCC_RET_PROD_IDX_11          0x00003cac
1201 #define HOSTCC_RET_PROD_IDX_12          0x00003cb0
1202 #define HOSTCC_RET_PROD_IDX_13          0x00003cb4
1203 #define HOSTCC_RET_PROD_IDX_14          0x00003cb8
1204 #define HOSTCC_RET_PROD_IDX_15          0x00003cbc
1205 #define HOSTCC_SND_CON_IDX_0            0x00003cc0
1206 #define HOSTCC_SND_CON_IDX_1            0x00003cc4
1207 #define HOSTCC_SND_CON_IDX_2            0x00003cc8
1208 #define HOSTCC_SND_CON_IDX_3            0x00003ccc
1209 #define HOSTCC_SND_CON_IDX_4            0x00003cd0
1210 #define HOSTCC_SND_CON_IDX_5            0x00003cd4
1211 #define HOSTCC_SND_CON_IDX_6            0x00003cd8
1212 #define HOSTCC_SND_CON_IDX_7            0x00003cdc
1213 #define HOSTCC_SND_CON_IDX_8            0x00003ce0
1214 #define HOSTCC_SND_CON_IDX_9            0x00003ce4
1215 #define HOSTCC_SND_CON_IDX_10           0x00003ce8
1216 #define HOSTCC_SND_CON_IDX_11           0x00003cec
1217 #define HOSTCC_SND_CON_IDX_12           0x00003cf0
1218 #define HOSTCC_SND_CON_IDX_13           0x00003cf4
1219 #define HOSTCC_SND_CON_IDX_14           0x00003cf8
1220 #define HOSTCC_SND_CON_IDX_15           0x00003cfc
1221 #define HOSTCC_STATBLCK_RING1           0x00003d00
1222 /* 0x3d00 --> 0x3d80 unused */
1223
1224 #define HOSTCC_RXCOL_TICKS_VEC1         0x00003d80
1225 #define HOSTCC_TXCOL_TICKS_VEC1         0x00003d84
1226 #define HOSTCC_RXMAX_FRAMES_VEC1        0x00003d88
1227 #define HOSTCC_TXMAX_FRAMES_VEC1        0x00003d8c
1228 #define HOSTCC_RXCOAL_MAXF_INT_VEC1     0x00003d90
1229 #define HOSTCC_TXCOAL_MAXF_INT_VEC1     0x00003d94
1230 /* 0x3d98 --> 0x4000 unused */
1231
1232 /* Memory arbiter control registers */
1233 #define MEMARB_MODE                     0x00004000
1234 #define  MEMARB_MODE_RESET               0x00000001
1235 #define  MEMARB_MODE_ENABLE              0x00000002
1236 #define MEMARB_STATUS                   0x00004004
1237 #define MEMARB_TRAP_ADDR_LOW            0x00004008
1238 #define MEMARB_TRAP_ADDR_HIGH           0x0000400c
1239 /* 0x4010 --> 0x4400 unused */
1240
1241 /* Buffer manager control registers */
1242 #define BUFMGR_MODE                     0x00004400
1243 #define  BUFMGR_MODE_RESET               0x00000001
1244 #define  BUFMGR_MODE_ENABLE              0x00000002
1245 #define  BUFMGR_MODE_ATTN_ENABLE         0x00000004
1246 #define  BUFMGR_MODE_BM_TEST             0x00000008
1247 #define  BUFMGR_MODE_MBLOW_ATTN_ENAB     0x00000010
1248 #define  BUFMGR_MODE_NO_TX_UNDERRUN      0x80000000
1249 #define BUFMGR_STATUS                   0x00004404
1250 #define  BUFMGR_STATUS_ERROR             0x00000004
1251 #define  BUFMGR_STATUS_MBLOW             0x00000010
1252 #define BUFMGR_MB_POOL_ADDR             0x00004408
1253 #define BUFMGR_MB_POOL_SIZE             0x0000440c
1254 #define BUFMGR_MB_RDMA_LOW_WATER        0x00004410
1255 #define  DEFAULT_MB_RDMA_LOW_WATER       0x00000050
1256 #define  DEFAULT_MB_RDMA_LOW_WATER_5705  0x00000000
1257 #define  DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130
1258 #define  DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780 0x00000000
1259 #define BUFMGR_MB_MACRX_LOW_WATER       0x00004414
1260 #define  DEFAULT_MB_MACRX_LOW_WATER       0x00000020
1261 #define  DEFAULT_MB_MACRX_LOW_WATER_5705  0x00000010
1262 #define  DEFAULT_MB_MACRX_LOW_WATER_5906  0x00000004
1263 #define  DEFAULT_MB_MACRX_LOW_WATER_57765 0x0000002a
1264 #define  DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
1265 #define  DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b
1266 #define  DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765 0x0000007e
1267 #define BUFMGR_MB_HIGH_WATER            0x00004418
1268 #define  DEFAULT_MB_HIGH_WATER           0x00000060
1269 #define  DEFAULT_MB_HIGH_WATER_5705      0x00000060
1270 #define  DEFAULT_MB_HIGH_WATER_5906      0x00000010
1271 #define  DEFAULT_MB_HIGH_WATER_57765     0x000000a0
1272 #define  DEFAULT_MB_HIGH_WATER_JUMBO     0x0000017c
1273 #define  DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096
1274 #define  DEFAULT_MB_HIGH_WATER_JUMBO_57765 0x000000ea
1275 #define BUFMGR_RX_MB_ALLOC_REQ          0x0000441c
1276 #define  BUFMGR_MB_ALLOC_BIT             0x10000000
1277 #define BUFMGR_RX_MB_ALLOC_RESP         0x00004420
1278 #define BUFMGR_TX_MB_ALLOC_REQ          0x00004424
1279 #define BUFMGR_TX_MB_ALLOC_RESP         0x00004428
1280 #define BUFMGR_DMA_DESC_POOL_ADDR       0x0000442c
1281 #define BUFMGR_DMA_DESC_POOL_SIZE       0x00004430
1282 #define BUFMGR_DMA_LOW_WATER            0x00004434
1283 #define  DEFAULT_DMA_LOW_WATER           0x00000005
1284 #define BUFMGR_DMA_HIGH_WATER           0x00004438
1285 #define  DEFAULT_DMA_HIGH_WATER          0x0000000a
1286 #define BUFMGR_RX_DMA_ALLOC_REQ         0x0000443c
1287 #define BUFMGR_RX_DMA_ALLOC_RESP        0x00004440
1288 #define BUFMGR_TX_DMA_ALLOC_REQ         0x00004444
1289 #define BUFMGR_TX_DMA_ALLOC_RESP        0x00004448
1290 #define BUFMGR_HWDIAG_0                 0x0000444c
1291 #define BUFMGR_HWDIAG_1                 0x00004450
1292 #define BUFMGR_HWDIAG_2                 0x00004454
1293 /* 0x4458 --> 0x4800 unused */
1294
1295 /* Read DMA control registers */
1296 #define RDMAC_MODE                      0x00004800
1297 #define  RDMAC_MODE_RESET                0x00000001
1298 #define  RDMAC_MODE_ENABLE               0x00000002
1299 #define  RDMAC_MODE_TGTABORT_ENAB        0x00000004
1300 #define  RDMAC_MODE_MSTABORT_ENAB        0x00000008
1301 #define  RDMAC_MODE_PARITYERR_ENAB       0x00000010
1302 #define  RDMAC_MODE_ADDROFLOW_ENAB       0x00000020
1303 #define  RDMAC_MODE_FIFOOFLOW_ENAB       0x00000040
1304 #define  RDMAC_MODE_FIFOURUN_ENAB        0x00000080
1305 #define  RDMAC_MODE_FIFOOREAD_ENAB       0x00000100
1306 #define  RDMAC_MODE_LNGREAD_ENAB         0x00000200
1307 #define  RDMAC_MODE_SPLIT_ENABLE         0x00000800
1308 #define  RDMAC_MODE_BD_SBD_CRPT_ENAB     0x00000800
1309 #define  RDMAC_MODE_SPLIT_RESET          0x00001000
1310 #define  RDMAC_MODE_MBUF_RBD_CRPT_ENAB   0x00001000
1311 #define  RDMAC_MODE_MBUF_SBD_CRPT_ENAB   0x00002000
1312 #define  RDMAC_MODE_FIFO_SIZE_128        0x00020000
1313 #define  RDMAC_MODE_FIFO_LONG_BURST      0x00030000
1314 #define  RDMAC_MODE_MULT_DMA_RD_DIS      0x01000000
1315 #define  RDMAC_MODE_IPV4_LSO_EN          0x08000000
1316 #define  RDMAC_MODE_IPV6_LSO_EN          0x10000000
1317 #define RDMAC_STATUS                    0x00004804
1318 #define  RDMAC_STATUS_TGTABORT           0x00000004
1319 #define  RDMAC_STATUS_MSTABORT           0x00000008
1320 #define  RDMAC_STATUS_PARITYERR          0x00000010
1321 #define  RDMAC_STATUS_ADDROFLOW          0x00000020
1322 #define  RDMAC_STATUS_FIFOOFLOW          0x00000040
1323 #define  RDMAC_STATUS_FIFOURUN           0x00000080
1324 #define  RDMAC_STATUS_FIFOOREAD          0x00000100
1325 #define  RDMAC_STATUS_LNGREAD            0x00000200
1326 /* 0x4808 --> 0x4900 unused */
1327
1328 #define TG3_RDMA_RSRVCTRL_REG           0x00004900
1329 #define TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX  0x00000004
1330 /* 0x4904 --> 0x4910 unused */
1331
1332 #define TG3_LSO_RD_DMA_CRPTEN_CTRL      0x00004910
1333 #define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K    0x00030000
1334 #define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K   0x000c0000
1335 /* 0x4914 --> 0x4c00 unused */
1336
1337 /* Write DMA control registers */
1338 #define WDMAC_MODE                      0x00004c00
1339 #define  WDMAC_MODE_RESET                0x00000001
1340 #define  WDMAC_MODE_ENABLE               0x00000002
1341 #define  WDMAC_MODE_TGTABORT_ENAB        0x00000004
1342 #define  WDMAC_MODE_MSTABORT_ENAB        0x00000008
1343 #define  WDMAC_MODE_PARITYERR_ENAB       0x00000010
1344 #define  WDMAC_MODE_ADDROFLOW_ENAB       0x00000020
1345 #define  WDMAC_MODE_FIFOOFLOW_ENAB       0x00000040
1346 #define  WDMAC_MODE_FIFOURUN_ENAB        0x00000080
1347 #define  WDMAC_MODE_FIFOOREAD_ENAB       0x00000100
1348 #define  WDMAC_MODE_LNGREAD_ENAB         0x00000200
1349 #define  WDMAC_MODE_RX_ACCEL             0x00000400
1350 #define  WDMAC_MODE_STATUS_TAG_FIX       0x20000000
1351 #define  WDMAC_MODE_BURST_ALL_DATA       0xc0000000
1352 #define WDMAC_STATUS                    0x00004c04
1353 #define  WDMAC_STATUS_TGTABORT           0x00000004
1354 #define  WDMAC_STATUS_MSTABORT           0x00000008
1355 #define  WDMAC_STATUS_PARITYERR          0x00000010
1356 #define  WDMAC_STATUS_ADDROFLOW          0x00000020
1357 #define  WDMAC_STATUS_FIFOOFLOW          0x00000040
1358 #define  WDMAC_STATUS_FIFOURUN           0x00000080
1359 #define  WDMAC_STATUS_FIFOOREAD          0x00000100
1360 #define  WDMAC_STATUS_LNGREAD            0x00000200
1361 /* 0x4c08 --> 0x5000 unused */
1362
1363 /* Per-cpu register offsets (arm9) */
1364 #define CPU_MODE                        0x00000000
1365 #define  CPU_MODE_RESET                  0x00000001
1366 #define  CPU_MODE_HALT                   0x00000400
1367 #define CPU_STATE                       0x00000004
1368 #define CPU_EVTMASK                     0x00000008
1369 /* 0xc --> 0x1c reserved */
1370 #define CPU_PC                          0x0000001c
1371 #define CPU_INSN                        0x00000020
1372 #define CPU_SPAD_UFLOW                  0x00000024
1373 #define CPU_WDOG_CLEAR                  0x00000028
1374 #define CPU_WDOG_VECTOR                 0x0000002c
1375 #define CPU_WDOG_PC                     0x00000030
1376 #define CPU_HW_BP                       0x00000034
1377 /* 0x38 --> 0x44 unused */
1378 #define CPU_WDOG_SAVED_STATE            0x00000044
1379 #define CPU_LAST_BRANCH_ADDR            0x00000048
1380 #define CPU_SPAD_UFLOW_SET              0x0000004c
1381 /* 0x50 --> 0x200 unused */
1382 #define CPU_R0                          0x00000200
1383 #define CPU_R1                          0x00000204
1384 #define CPU_R2                          0x00000208
1385 #define CPU_R3                          0x0000020c
1386 #define CPU_R4                          0x00000210
1387 #define CPU_R5                          0x00000214
1388 #define CPU_R6                          0x00000218
1389 #define CPU_R7                          0x0000021c
1390 #define CPU_R8                          0x00000220
1391 #define CPU_R9                          0x00000224
1392 #define CPU_R10                         0x00000228
1393 #define CPU_R11                         0x0000022c
1394 #define CPU_R12                         0x00000230
1395 #define CPU_R13                         0x00000234
1396 #define CPU_R14                         0x00000238
1397 #define CPU_R15                         0x0000023c
1398 #define CPU_R16                         0x00000240
1399 #define CPU_R17                         0x00000244
1400 #define CPU_R18                         0x00000248
1401 #define CPU_R19                         0x0000024c
1402 #define CPU_R20                         0x00000250
1403 #define CPU_R21                         0x00000254
1404 #define CPU_R22                         0x00000258
1405 #define CPU_R23                         0x0000025c
1406 #define CPU_R24                         0x00000260
1407 #define CPU_R25                         0x00000264
1408 #define CPU_R26                         0x00000268
1409 #define CPU_R27                         0x0000026c
1410 #define CPU_R28                         0x00000270
1411 #define CPU_R29                         0x00000274
1412 #define CPU_R30                         0x00000278
1413 #define CPU_R31                         0x0000027c
1414 /* 0x280 --> 0x400 unused */
1415
1416 #define RX_CPU_BASE                     0x00005000
1417 #define RX_CPU_MODE                     0x00005000
1418 #define RX_CPU_STATE                    0x00005004
1419 #define RX_CPU_PGMCTR                   0x0000501c
1420 #define RX_CPU_HWBKPT                   0x00005034
1421 #define TX_CPU_BASE                     0x00005400
1422 #define TX_CPU_MODE                     0x00005400
1423 #define TX_CPU_STATE                    0x00005404
1424 #define TX_CPU_PGMCTR                   0x0000541c
1425
1426 #define VCPU_STATUS                     0x00005100
1427 #define  VCPU_STATUS_INIT_DONE           0x04000000
1428 #define  VCPU_STATUS_DRV_RESET           0x08000000
1429
1430 #define VCPU_CFGSHDW                    0x00005104
1431 #define  VCPU_CFGSHDW_WOL_ENABLE         0x00000001
1432 #define  VCPU_CFGSHDW_WOL_MAGPKT         0x00000004
1433 #define  VCPU_CFGSHDW_ASPM_DBNC          0x00001000
1434
1435 /* Mailboxes */
1436 #define GRCMBOX_BASE                    0x00005600
1437 #define GRCMBOX_INTERRUPT_0             0x00005800 /* 64-bit */
1438 #define GRCMBOX_INTERRUPT_1             0x00005808 /* 64-bit */
1439 #define GRCMBOX_INTERRUPT_2             0x00005810 /* 64-bit */
1440 #define GRCMBOX_INTERRUPT_3             0x00005818 /* 64-bit */
1441 #define GRCMBOX_GENERAL_0               0x00005820 /* 64-bit */
1442 #define GRCMBOX_GENERAL_1               0x00005828 /* 64-bit */
1443 #define GRCMBOX_GENERAL_2               0x00005830 /* 64-bit */
1444 #define GRCMBOX_GENERAL_3               0x00005838 /* 64-bit */
1445 #define GRCMBOX_GENERAL_4               0x00005840 /* 64-bit */
1446 #define GRCMBOX_GENERAL_5               0x00005848 /* 64-bit */
1447 #define GRCMBOX_GENERAL_6               0x00005850 /* 64-bit */
1448 #define GRCMBOX_GENERAL_7               0x00005858 /* 64-bit */
1449 #define GRCMBOX_RELOAD_STAT             0x00005860 /* 64-bit */
1450 #define GRCMBOX_RCVSTD_PROD_IDX         0x00005868 /* 64-bit */
1451 #define GRCMBOX_RCVJUMBO_PROD_IDX       0x00005870 /* 64-bit */
1452 #define GRCMBOX_RCVMINI_PROD_IDX        0x00005878 /* 64-bit */
1453 #define GRCMBOX_RCVRET_CON_IDX_0        0x00005880 /* 64-bit */
1454 #define GRCMBOX_RCVRET_CON_IDX_1        0x00005888 /* 64-bit */
1455 #define GRCMBOX_RCVRET_CON_IDX_2        0x00005890 /* 64-bit */
1456 #define GRCMBOX_RCVRET_CON_IDX_3        0x00005898 /* 64-bit */
1457 #define GRCMBOX_RCVRET_CON_IDX_4        0x000058a0 /* 64-bit */
1458 #define GRCMBOX_RCVRET_CON_IDX_5        0x000058a8 /* 64-bit */
1459 #define GRCMBOX_RCVRET_CON_IDX_6        0x000058b0 /* 64-bit */
1460 #define GRCMBOX_RCVRET_CON_IDX_7        0x000058b8 /* 64-bit */
1461 #define GRCMBOX_RCVRET_CON_IDX_8        0x000058c0 /* 64-bit */
1462 #define GRCMBOX_RCVRET_CON_IDX_9        0x000058c8 /* 64-bit */
1463 #define GRCMBOX_RCVRET_CON_IDX_10       0x000058d0 /* 64-bit */
1464 #define GRCMBOX_RCVRET_CON_IDX_11       0x000058d8 /* 64-bit */
1465 #define GRCMBOX_RCVRET_CON_IDX_12       0x000058e0 /* 64-bit */
1466 #define GRCMBOX_RCVRET_CON_IDX_13       0x000058e8 /* 64-bit */
1467 #define GRCMBOX_RCVRET_CON_IDX_14       0x000058f0 /* 64-bit */
1468 #define GRCMBOX_RCVRET_CON_IDX_15       0x000058f8 /* 64-bit */
1469 #define GRCMBOX_SNDHOST_PROD_IDX_0      0x00005900 /* 64-bit */
1470 #define GRCMBOX_SNDHOST_PROD_IDX_1      0x00005908 /* 64-bit */
1471 #define GRCMBOX_SNDHOST_PROD_IDX_2      0x00005910 /* 64-bit */
1472 #define GRCMBOX_SNDHOST_PROD_IDX_3      0x00005918 /* 64-bit */
1473 #define GRCMBOX_SNDHOST_PROD_IDX_4      0x00005920 /* 64-bit */
1474 #define GRCMBOX_SNDHOST_PROD_IDX_5      0x00005928 /* 64-bit */
1475 #define GRCMBOX_SNDHOST_PROD_IDX_6      0x00005930 /* 64-bit */
1476 #define GRCMBOX_SNDHOST_PROD_IDX_7      0x00005938 /* 64-bit */
1477 #define GRCMBOX_SNDHOST_PROD_IDX_8      0x00005940 /* 64-bit */
1478 #define GRCMBOX_SNDHOST_PROD_IDX_9      0x00005948 /* 64-bit */
1479 #define GRCMBOX_SNDHOST_PROD_IDX_10     0x00005950 /* 64-bit */
1480 #define GRCMBOX_SNDHOST_PROD_IDX_11     0x00005958 /* 64-bit */
1481 #define GRCMBOX_SNDHOST_PROD_IDX_12     0x00005960 /* 64-bit */
1482 #define GRCMBOX_SNDHOST_PROD_IDX_13     0x00005968 /* 64-bit */
1483 #define GRCMBOX_SNDHOST_PROD_IDX_14     0x00005970 /* 64-bit */
1484 #define GRCMBOX_SNDHOST_PROD_IDX_15     0x00005978 /* 64-bit */
1485 #define GRCMBOX_SNDNIC_PROD_IDX_0       0x00005980 /* 64-bit */
1486 #define GRCMBOX_SNDNIC_PROD_IDX_1       0x00005988 /* 64-bit */
1487 #define GRCMBOX_SNDNIC_PROD_IDX_2       0x00005990 /* 64-bit */
1488 #define GRCMBOX_SNDNIC_PROD_IDX_3       0x00005998 /* 64-bit */
1489 #define GRCMBOX_SNDNIC_PROD_IDX_4       0x000059a0 /* 64-bit */
1490 #define GRCMBOX_SNDNIC_PROD_IDX_5       0x000059a8 /* 64-bit */
1491 #define GRCMBOX_SNDNIC_PROD_IDX_6       0x000059b0 /* 64-bit */
1492 #define GRCMBOX_SNDNIC_PROD_IDX_7       0x000059b8 /* 64-bit */
1493 #define GRCMBOX_SNDNIC_PROD_IDX_8       0x000059c0 /* 64-bit */
1494 #define GRCMBOX_SNDNIC_PROD_IDX_9       0x000059c8 /* 64-bit */
1495 #define GRCMBOX_SNDNIC_PROD_IDX_10      0x000059d0 /* 64-bit */
1496 #define GRCMBOX_SNDNIC_PROD_IDX_11      0x000059d8 /* 64-bit */
1497 #define GRCMBOX_SNDNIC_PROD_IDX_12      0x000059e0 /* 64-bit */
1498 #define GRCMBOX_SNDNIC_PROD_IDX_13      0x000059e8 /* 64-bit */
1499 #define GRCMBOX_SNDNIC_PROD_IDX_14      0x000059f0 /* 64-bit */
1500 #define GRCMBOX_SNDNIC_PROD_IDX_15      0x000059f8 /* 64-bit */
1501 #define GRCMBOX_HIGH_PRIO_EV_VECTOR     0x00005a00
1502 #define GRCMBOX_HIGH_PRIO_EV_MASK       0x00005a04
1503 #define GRCMBOX_LOW_PRIO_EV_VEC         0x00005a08
1504 #define GRCMBOX_LOW_PRIO_EV_MASK        0x00005a0c
1505 /* 0x5a10 --> 0x5c00 */
1506
1507 /* Flow Through queues */
1508 #define FTQ_RESET                       0x00005c00
1509 /* 0x5c04 --> 0x5c10 unused */
1510 #define FTQ_DMA_NORM_READ_CTL           0x00005c10
1511 #define FTQ_DMA_NORM_READ_FULL_CNT      0x00005c14
1512 #define FTQ_DMA_NORM_READ_FIFO_ENQDEQ   0x00005c18
1513 #define FTQ_DMA_NORM_READ_WRITE_PEEK    0x00005c1c
1514 #define FTQ_DMA_HIGH_READ_CTL           0x00005c20
1515 #define FTQ_DMA_HIGH_READ_FULL_CNT      0x00005c24
1516 #define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ   0x00005c28
1517 #define FTQ_DMA_HIGH_READ_WRITE_PEEK    0x00005c2c
1518 #define FTQ_DMA_COMP_DISC_CTL           0x00005c30
1519 #define FTQ_DMA_COMP_DISC_FULL_CNT      0x00005c34
1520 #define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ   0x00005c38
1521 #define FTQ_DMA_COMP_DISC_WRITE_PEEK    0x00005c3c
1522 #define FTQ_SEND_BD_COMP_CTL            0x00005c40
1523 #define FTQ_SEND_BD_COMP_FULL_CNT       0x00005c44
1524 #define FTQ_SEND_BD_COMP_FIFO_ENQDEQ    0x00005c48
1525 #define FTQ_SEND_BD_COMP_WRITE_PEEK     0x00005c4c
1526 #define FTQ_SEND_DATA_INIT_CTL          0x00005c50
1527 #define FTQ_SEND_DATA_INIT_FULL_CNT     0x00005c54
1528 #define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ  0x00005c58
1529 #define FTQ_SEND_DATA_INIT_WRITE_PEEK   0x00005c5c
1530 #define FTQ_DMA_NORM_WRITE_CTL          0x00005c60
1531 #define FTQ_DMA_NORM_WRITE_FULL_CNT     0x00005c64
1532 #define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ  0x00005c68
1533 #define FTQ_DMA_NORM_WRITE_WRITE_PEEK   0x00005c6c
1534 #define FTQ_DMA_HIGH_WRITE_CTL          0x00005c70
1535 #define FTQ_DMA_HIGH_WRITE_FULL_CNT     0x00005c74
1536 #define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ  0x00005c78
1537 #define FTQ_DMA_HIGH_WRITE_WRITE_PEEK   0x00005c7c
1538 #define FTQ_SWTYPE1_CTL                 0x00005c80
1539 #define FTQ_SWTYPE1_FULL_CNT            0x00005c84
1540 #define FTQ_SWTYPE1_FIFO_ENQDEQ         0x00005c88
1541 #define FTQ_SWTYPE1_WRITE_PEEK          0x00005c8c
1542 #define FTQ_SEND_DATA_COMP_CTL          0x00005c90
1543 #define FTQ_SEND_DATA_COMP_FULL_CNT     0x00005c94
1544 #define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ  0x00005c98
1545 #define FTQ_SEND_DATA_COMP_WRITE_PEEK   0x00005c9c
1546 #define FTQ_HOST_COAL_CTL               0x00005ca0
1547 #define FTQ_HOST_COAL_FULL_CNT          0x00005ca4
1548 #define FTQ_HOST_COAL_FIFO_ENQDEQ       0x00005ca8
1549 #define FTQ_HOST_COAL_WRITE_PEEK        0x00005cac
1550 #define FTQ_MAC_TX_CTL                  0x00005cb0
1551 #define FTQ_MAC_TX_FULL_CNT             0x00005cb4
1552 #define FTQ_MAC_TX_FIFO_ENQDEQ          0x00005cb8
1553 #define FTQ_MAC_TX_WRITE_PEEK           0x00005cbc
1554 #define FTQ_MB_FREE_CTL                 0x00005cc0
1555 #define FTQ_MB_FREE_FULL_CNT            0x00005cc4
1556 #define FTQ_MB_FREE_FIFO_ENQDEQ         0x00005cc8
1557 #define FTQ_MB_FREE_WRITE_PEEK          0x00005ccc
1558 #define FTQ_RCVBD_COMP_CTL              0x00005cd0
1559 #define FTQ_RCVBD_COMP_FULL_CNT         0x00005cd4
1560 #define FTQ_RCVBD_COMP_FIFO_ENQDEQ      0x00005cd8
1561 #define FTQ_RCVBD_COMP_WRITE_PEEK       0x00005cdc
1562 #define FTQ_RCVLST_PLMT_CTL             0x00005ce0
1563 #define FTQ_RCVLST_PLMT_FULL_CNT        0x00005ce4
1564 #define FTQ_RCVLST_PLMT_FIFO_ENQDEQ     0x00005ce8
1565 #define FTQ_RCVLST_PLMT_WRITE_PEEK      0x00005cec
1566 #define FTQ_RCVDATA_INI_CTL             0x00005cf0
1567 #define FTQ_RCVDATA_INI_FULL_CNT        0x00005cf4
1568 #define FTQ_RCVDATA_INI_FIFO_ENQDEQ     0x00005cf8
1569 #define FTQ_RCVDATA_INI_WRITE_PEEK      0x00005cfc
1570 #define FTQ_RCVDATA_COMP_CTL            0x00005d00
1571 #define FTQ_RCVDATA_COMP_FULL_CNT       0x00005d04
1572 #define FTQ_RCVDATA_COMP_FIFO_ENQDEQ    0x00005d08
1573 #define FTQ_RCVDATA_COMP_WRITE_PEEK     0x00005d0c
1574 #define FTQ_SWTYPE2_CTL                 0x00005d10
1575 #define FTQ_SWTYPE2_FULL_CNT            0x00005d14
1576 #define FTQ_SWTYPE2_FIFO_ENQDEQ         0x00005d18
1577 #define FTQ_SWTYPE2_WRITE_PEEK          0x00005d1c
1578 /* 0x5d20 --> 0x6000 unused */
1579
1580 /* Message signaled interrupt registers */
1581 #define MSGINT_MODE                     0x00006000
1582 #define  MSGINT_MODE_RESET               0x00000001
1583 #define  MSGINT_MODE_ENABLE              0x00000002
1584 #define  MSGINT_MODE_ONE_SHOT_DISABLE    0x00000020
1585 #define  MSGINT_MODE_MULTIVEC_EN         0x00000080
1586 #define MSGINT_STATUS                   0x00006004
1587 #define MSGINT_FIFO                     0x00006008
1588 /* 0x600c --> 0x6400 unused */
1589
1590 /* DMA completion registers */
1591 #define DMAC_MODE                       0x00006400
1592 #define  DMAC_MODE_RESET                 0x00000001
1593 #define  DMAC_MODE_ENABLE                0x00000002
1594 /* 0x6404 --> 0x6800 unused */
1595
1596 /* GRC registers */
1597 #define GRC_MODE                        0x00006800
1598 #define  GRC_MODE_UPD_ON_COAL           0x00000001
1599 #define  GRC_MODE_BSWAP_NONFRM_DATA     0x00000002
1600 #define  GRC_MODE_WSWAP_NONFRM_DATA     0x00000004
1601 #define  GRC_MODE_BSWAP_DATA            0x00000010
1602 #define  GRC_MODE_WSWAP_DATA            0x00000020
1603 #define  GRC_MODE_SPLITHDR              0x00000100
1604 #define  GRC_MODE_NOFRM_CRACKING        0x00000200
1605 #define  GRC_MODE_INCL_CRC              0x00000400
1606 #define  GRC_MODE_ALLOW_BAD_FRMS        0x00000800
1607 #define  GRC_MODE_NOIRQ_ON_SENDS        0x00002000
1608 #define  GRC_MODE_NOIRQ_ON_RCV          0x00004000
1609 #define  GRC_MODE_FORCE_PCI32BIT        0x00008000
1610 #define  GRC_MODE_HOST_STACKUP          0x00010000
1611 #define  GRC_MODE_HOST_SENDBDS          0x00020000
1612 #define  GRC_MODE_NO_TX_PHDR_CSUM       0x00100000
1613 #define  GRC_MODE_NVRAM_WR_ENABLE       0x00200000
1614 #define  GRC_MODE_PCIE_TL_SEL           0x00000000
1615 #define  GRC_MODE_PCIE_PL_SEL           0x00400000
1616 #define  GRC_MODE_NO_RX_PHDR_CSUM       0x00800000
1617 #define  GRC_MODE_IRQ_ON_TX_CPU_ATTN    0x01000000
1618 #define  GRC_MODE_IRQ_ON_RX_CPU_ATTN    0x02000000
1619 #define  GRC_MODE_IRQ_ON_MAC_ATTN       0x04000000
1620 #define  GRC_MODE_IRQ_ON_DMA_ATTN       0x08000000
1621 #define  GRC_MODE_IRQ_ON_FLOW_ATTN      0x10000000
1622 #define  GRC_MODE_4X_NIC_SEND_RINGS     0x20000000
1623 #define  GRC_MODE_PCIE_DL_SEL           0x20000000
1624 #define  GRC_MODE_MCAST_FRM_ENABLE      0x40000000
1625 #define  GRC_MODE_PCIE_HI_1K_EN         0x80000000
1626 #define  GRC_MODE_PCIE_PORT_MASK        (GRC_MODE_PCIE_TL_SEL | \
1627                                          GRC_MODE_PCIE_PL_SEL | \
1628                                          GRC_MODE_PCIE_DL_SEL | \
1629                                          GRC_MODE_PCIE_HI_1K_EN)
1630 #define GRC_MISC_CFG                    0x00006804
1631 #define  GRC_MISC_CFG_CORECLK_RESET     0x00000001
1632 #define  GRC_MISC_CFG_PRESCALAR_MASK    0x000000fe
1633 #define  GRC_MISC_CFG_PRESCALAR_SHIFT   1
1634 #define  GRC_MISC_CFG_BOARD_ID_MASK     0x0001e000
1635 #define  GRC_MISC_CFG_BOARD_ID_5700     0x0001e000
1636 #define  GRC_MISC_CFG_BOARD_ID_5701     0x00000000
1637 #define  GRC_MISC_CFG_BOARD_ID_5702FE   0x00004000
1638 #define  GRC_MISC_CFG_BOARD_ID_5703     0x00000000
1639 #define  GRC_MISC_CFG_BOARD_ID_5703S    0x00002000
1640 #define  GRC_MISC_CFG_BOARD_ID_5704     0x00000000
1641 #define  GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000
1642 #define  GRC_MISC_CFG_BOARD_ID_5704_A2  0x00008000
1643 #define  GRC_MISC_CFG_BOARD_ID_5788     0x00010000
1644 #define  GRC_MISC_CFG_BOARD_ID_5788M    0x00018000
1645 #define  GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000
1646 #define  GRC_MISC_CFG_EPHY_IDDQ         0x00200000
1647 #define  GRC_MISC_CFG_KEEP_GPHY_POWER   0x04000000
1648 #define GRC_LOCAL_CTRL                  0x00006808
1649 #define  GRC_LCLCTRL_INT_ACTIVE         0x00000001
1650 #define  GRC_LCLCTRL_CLEARINT           0x00000002
1651 #define  GRC_LCLCTRL_SETINT             0x00000004
1652 #define  GRC_LCLCTRL_INT_ON_ATTN        0x00000008
1653 #define  GRC_LCLCTRL_GPIO_UART_SEL      0x00000010      /* 5755 only */
1654 #define  GRC_LCLCTRL_USE_SIG_DETECT     0x00000010      /* 5714/5780 only */
1655 #define  GRC_LCLCTRL_USE_EXT_SIG_DETECT 0x00000020      /* 5714/5780 only */
1656 #define  GRC_LCLCTRL_GPIO_INPUT3        0x00000020
1657 #define  GRC_LCLCTRL_GPIO_OE3           0x00000040
1658 #define  GRC_LCLCTRL_GPIO_OUTPUT3       0x00000080
1659 #define  GRC_LCLCTRL_GPIO_INPUT0        0x00000100
1660 #define  GRC_LCLCTRL_GPIO_INPUT1        0x00000200
1661 #define  GRC_LCLCTRL_GPIO_INPUT2        0x00000400
1662 #define  GRC_LCLCTRL_GPIO_OE0           0x00000800
1663 #define  GRC_LCLCTRL_GPIO_OE1           0x00001000
1664 #define  GRC_LCLCTRL_GPIO_OE2           0x00002000
1665 #define  GRC_LCLCTRL_GPIO_OUTPUT0       0x00004000
1666 #define  GRC_LCLCTRL_GPIO_OUTPUT1       0x00008000
1667 #define  GRC_LCLCTRL_GPIO_OUTPUT2       0x00010000
1668 #define  GRC_LCLCTRL_EXTMEM_ENABLE      0x00020000
1669 #define  GRC_LCLCTRL_MEMSZ_MASK         0x001c0000
1670 #define  GRC_LCLCTRL_MEMSZ_256K         0x00000000
1671 #define  GRC_LCLCTRL_MEMSZ_512K         0x00040000
1672 #define  GRC_LCLCTRL_MEMSZ_1M           0x00080000
1673 #define  GRC_LCLCTRL_MEMSZ_2M           0x000c0000
1674 #define  GRC_LCLCTRL_MEMSZ_4M           0x00100000
1675 #define  GRC_LCLCTRL_MEMSZ_8M           0x00140000
1676 #define  GRC_LCLCTRL_MEMSZ_16M          0x00180000
1677 #define  GRC_LCLCTRL_BANK_SELECT        0x00200000
1678 #define  GRC_LCLCTRL_SSRAM_TYPE         0x00400000
1679 #define  GRC_LCLCTRL_AUTO_SEEPROM       0x01000000
1680 #define GRC_TIMER                       0x0000680c
1681 #define GRC_RX_CPU_EVENT                0x00006810
1682 #define  GRC_RX_CPU_DRIVER_EVENT        0x00004000
1683 #define GRC_RX_TIMER_REF                0x00006814
1684 #define GRC_RX_CPU_SEM                  0x00006818
1685 #define GRC_REMOTE_RX_CPU_ATTN          0x0000681c
1686 #define GRC_TX_CPU_EVENT                0x00006820
1687 #define GRC_TX_TIMER_REF                0x00006824
1688 #define GRC_TX_CPU_SEM                  0x00006828
1689 #define GRC_REMOTE_TX_CPU_ATTN          0x0000682c
1690 #define GRC_MEM_POWER_UP                0x00006830 /* 64-bit */
1691 #define GRC_EEPROM_ADDR                 0x00006838
1692 #define  EEPROM_ADDR_WRITE              0x00000000
1693 #define  EEPROM_ADDR_READ               0x80000000
1694 #define  EEPROM_ADDR_COMPLETE           0x40000000
1695 #define  EEPROM_ADDR_FSM_RESET          0x20000000
1696 #define  EEPROM_ADDR_DEVID_MASK         0x1c000000
1697 #define  EEPROM_ADDR_DEVID_SHIFT        26
1698 #define  EEPROM_ADDR_START              0x02000000
1699 #define  EEPROM_ADDR_CLKPERD_SHIFT      16
1700 #define  EEPROM_ADDR_ADDR_MASK          0x0000ffff
1701 #define  EEPROM_ADDR_ADDR_SHIFT         0
1702 #define  EEPROM_DEFAULT_CLOCK_PERIOD    0x60
1703 #define  EEPROM_CHIP_SIZE               (64 * 1024)
1704 #define GRC_EEPROM_DATA                 0x0000683c
1705 #define GRC_EEPROM_CTRL                 0x00006840
1706 #define GRC_MDI_CTRL                    0x00006844
1707 #define GRC_SEEPROM_DELAY               0x00006848
1708 /* 0x684c --> 0x6890 unused */
1709 #define GRC_VCPU_EXT_CTRL               0x00006890
1710 #define GRC_VCPU_EXT_CTRL_HALT_CPU       0x00400000
1711 #define GRC_VCPU_EXT_CTRL_DISABLE_WOL    0x20000000
1712 #define GRC_FASTBOOT_PC                 0x00006894      /* 5752, 5755, 5787 */
1713
1714 /* 0x6c00 --> 0x7000 unused */
1715
1716 /* NVRAM Control registers */
1717 #define NVRAM_CMD                       0x00007000
1718 #define  NVRAM_CMD_RESET                 0x00000001
1719 #define  NVRAM_CMD_DONE                  0x00000008
1720 #define  NVRAM_CMD_GO                    0x00000010
1721 #define  NVRAM_CMD_WR                    0x00000020
1722 #define  NVRAM_CMD_RD                    0x00000000
1723 #define  NVRAM_CMD_ERASE                 0x00000040
1724 #define  NVRAM_CMD_FIRST                 0x00000080
1725 #define  NVRAM_CMD_LAST                  0x00000100
1726 #define  NVRAM_CMD_WREN                  0x00010000
1727 #define  NVRAM_CMD_WRDI                  0x00020000
1728 #define NVRAM_STAT                      0x00007004
1729 #define NVRAM_WRDATA                    0x00007008
1730 #define NVRAM_ADDR                      0x0000700c
1731 #define  NVRAM_ADDR_MSK                 0x00ffffff
1732 #define NVRAM_RDDATA                    0x00007010
1733 #define NVRAM_CFG1                      0x00007014
1734 #define  NVRAM_CFG1_FLASHIF_ENAB         0x00000001
1735 #define  NVRAM_CFG1_BUFFERED_MODE        0x00000002
1736 #define  NVRAM_CFG1_PASS_THRU            0x00000004
1737 #define  NVRAM_CFG1_STATUS_BITS          0x00000070
1738 #define  NVRAM_CFG1_BIT_BANG             0x00000008
1739 #define  NVRAM_CFG1_FLASH_SIZE           0x02000000
1740 #define  NVRAM_CFG1_COMPAT_BYPASS        0x80000000
1741 #define  NVRAM_CFG1_VENDOR_MASK          0x03000003
1742 #define  FLASH_VENDOR_ATMEL_EEPROM       0x02000000
1743 #define  FLASH_VENDOR_ATMEL_FLASH_BUFFERED       0x02000003
1744 #define  FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED     0x00000003
1745 #define  FLASH_VENDOR_ST                         0x03000001
1746 #define  FLASH_VENDOR_SAIFUN             0x01000003
1747 #define  FLASH_VENDOR_SST_SMALL          0x00000001
1748 #define  FLASH_VENDOR_SST_LARGE          0x02000001
1749 #define  NVRAM_CFG1_5752VENDOR_MASK      0x03c00003
1750 #define  FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ     0x00000000
1751 #define  FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ    0x02000000
1752 #define  FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED   0x02000003
1753 #define  FLASH_5752VENDOR_ST_M45PE10     0x02400000
1754 #define  FLASH_5752VENDOR_ST_M45PE20     0x02400002
1755 #define  FLASH_5752VENDOR_ST_M45PE40     0x02400001
1756 #define  FLASH_5755VENDOR_ATMEL_FLASH_1  0x03400001
1757 #define  FLASH_5755VENDOR_ATMEL_FLASH_2  0x03400002
1758 #define  FLASH_5755VENDOR_ATMEL_FLASH_3  0x03400000
1759 #define  FLASH_5755VENDOR_ATMEL_FLASH_4  0x00000003
1760 #define  FLASH_5755VENDOR_ATMEL_FLASH_5  0x02000003
1761 #define  FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ     0x03c00003
1762 #define  FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ    0x03c00002
1763 #define  FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ     0x03000003
1764 #define  FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ    0x03000002
1765 #define  FLASH_5787VENDOR_MICRO_EEPROM_64KHZ     0x03000000
1766 #define  FLASH_5787VENDOR_MICRO_EEPROM_376KHZ    0x02000000
1767 #define  FLASH_5761VENDOR_ATMEL_MDB021D  0x00800003
1768 #define  FLASH_5761VENDOR_ATMEL_MDB041D  0x00800000
1769 #define  FLASH_5761VENDOR_ATMEL_MDB081D  0x00800002
1770 #define  FLASH_5761VENDOR_ATMEL_MDB161D  0x00800001
1771 #define  FLASH_5761VENDOR_ATMEL_ADB021D  0x00000003
1772 #define  FLASH_5761VENDOR_ATMEL_ADB041D  0x00000000
1773 #define  FLASH_5761VENDOR_ATMEL_ADB081D  0x00000002
1774 #define  FLASH_5761VENDOR_ATMEL_ADB161D  0x00000001
1775 #define  FLASH_5761VENDOR_ST_M_M45PE20   0x02800001
1776 #define  FLASH_5761VENDOR_ST_M_M45PE40   0x02800000
1777 #define  FLASH_5761VENDOR_ST_M_M45PE80   0x02800002
1778 #define  FLASH_5761VENDOR_ST_M_M45PE16   0x02800003
1779 #define  FLASH_5761VENDOR_ST_A_M45PE20   0x02000001
1780 #define  FLASH_5761VENDOR_ST_A_M45PE40   0x02000000
1781 #define  FLASH_5761VENDOR_ST_A_M45PE80   0x02000002
1782 #define  FLASH_5761VENDOR_ST_A_M45PE16   0x02000003
1783 #define  FLASH_57780VENDOR_ATMEL_AT45DB011D 0x00400000
1784 #define  FLASH_57780VENDOR_ATMEL_AT45DB011B 0x03400000
1785 #define  FLASH_57780VENDOR_ATMEL_AT45DB021D 0x00400002
1786 #define  FLASH_57780VENDOR_ATMEL_AT45DB021B 0x03400002
1787 #define  FLASH_57780VENDOR_ATMEL_AT45DB041D 0x00400001
1788 #define  FLASH_57780VENDOR_ATMEL_AT45DB041B 0x03400001
1789 #define  FLASH_5717VENDOR_ATMEL_EEPROM   0x02000001
1790 #define  FLASH_5717VENDOR_MICRO_EEPROM   0x02000003
1791 #define  FLASH_5717VENDOR_ATMEL_MDB011D  0x01000001
1792 #define  FLASH_5717VENDOR_ATMEL_MDB021D  0x01000003
1793 #define  FLASH_5717VENDOR_ST_M_M25PE10   0x02000000
1794 #define  FLASH_5717VENDOR_ST_M_M25PE20   0x02000002
1795 #define  FLASH_5717VENDOR_ST_M_M45PE10   0x00000001
1796 #define  FLASH_5717VENDOR_ST_M_M45PE20   0x00000003
1797 #define  FLASH_5717VENDOR_ATMEL_ADB011B  0x01400000
1798 #define  FLASH_5717VENDOR_ATMEL_ADB021B  0x01400002
1799 #define  FLASH_5717VENDOR_ATMEL_ADB011D  0x01400001
1800 #define  FLASH_5717VENDOR_ATMEL_ADB021D  0x01400003
1801 #define  FLASH_5717VENDOR_ST_A_M25PE10   0x02400000
1802 #define  FLASH_5717VENDOR_ST_A_M25PE20   0x02400002
1803 #define  FLASH_5717VENDOR_ST_A_M45PE10   0x02400001
1804 #define  FLASH_5717VENDOR_ST_A_M45PE20   0x02400003
1805 #define  FLASH_5717VENDOR_ATMEL_45USPT   0x03400000
1806 #define  FLASH_5717VENDOR_ST_25USPT      0x03400002
1807 #define  FLASH_5717VENDOR_ST_45USPT      0x03400001
1808 #define  NVRAM_CFG1_5752PAGE_SIZE_MASK   0x70000000
1809 #define  FLASH_5752PAGE_SIZE_256         0x00000000
1810 #define  FLASH_5752PAGE_SIZE_512         0x10000000
1811 #define  FLASH_5752PAGE_SIZE_1K          0x20000000
1812 #define  FLASH_5752PAGE_SIZE_2K          0x30000000
1813 #define  FLASH_5752PAGE_SIZE_4K          0x40000000
1814 #define  FLASH_5752PAGE_SIZE_264         0x50000000
1815 #define  FLASH_5752PAGE_SIZE_528         0x60000000
1816 #define NVRAM_CFG2                      0x00007018
1817 #define NVRAM_CFG3                      0x0000701c
1818 #define NVRAM_SWARB                     0x00007020
1819 #define  SWARB_REQ_SET0                  0x00000001
1820 #define  SWARB_REQ_SET1                  0x00000002
1821 #define  SWARB_REQ_SET2                  0x00000004
1822 #define  SWARB_REQ_SET3                  0x00000008
1823 #define  SWARB_REQ_CLR0                  0x00000010
1824 #define  SWARB_REQ_CLR1                  0x00000020
1825 #define  SWARB_REQ_CLR2                  0x00000040
1826 #define  SWARB_REQ_CLR3                  0x00000080
1827 #define  SWARB_GNT0                      0x00000100
1828 #define  SWARB_GNT1                      0x00000200
1829 #define  SWARB_GNT2                      0x00000400
1830 #define  SWARB_GNT3                      0x00000800
1831 #define  SWARB_REQ0                      0x00001000
1832 #define  SWARB_REQ1                      0x00002000
1833 #define  SWARB_REQ2                      0x00004000
1834 #define  SWARB_REQ3                      0x00008000
1835 #define NVRAM_ACCESS                    0x00007024
1836 #define  ACCESS_ENABLE                   0x00000001
1837 #define  ACCESS_WR_ENABLE                0x00000002
1838 #define NVRAM_WRITE1                    0x00007028
1839 /* 0x702c unused */
1840
1841 #define NVRAM_ADDR_LOCKOUT              0x00007030
1842 /* 0x7034 --> 0x7500 unused */
1843
1844 #define OTP_MODE                        0x00007500
1845 #define OTP_MODE_OTP_THRU_GRC            0x00000001
1846 #define OTP_CTRL                        0x00007504
1847 #define OTP_CTRL_OTP_PROG_ENABLE         0x00200000
1848 #define OTP_CTRL_OTP_CMD_READ            0x00000000
1849 #define OTP_CTRL_OTP_CMD_INIT            0x00000008
1850 #define OTP_CTRL_OTP_CMD_START           0x00000001
1851 #define OTP_STATUS                      0x00007508
1852 #define OTP_STATUS_CMD_DONE              0x00000001
1853 #define OTP_ADDRESS                     0x0000750c
1854 #define OTP_ADDRESS_MAGIC1               0x000000a0
1855 #define OTP_ADDRESS_MAGIC2               0x00000080
1856 /* 0x7510 unused */
1857
1858 #define OTP_READ_DATA                   0x00007514
1859 /* 0x7518 --> 0x7c04 unused */
1860
1861 #define PCIE_TRANSACTION_CFG            0x00007c04
1862 #define PCIE_TRANS_CFG_1SHOT_MSI         0x20000000
1863 #define PCIE_TRANS_CFG_LOM               0x00000020
1864 /* 0x7c08 --> 0x7d28 unused */
1865
1866 #define PCIE_PWR_MGMT_THRESH            0x00007d28
1867 #define PCIE_PWR_MGMT_L1_THRESH_MSK      0x0000ff00
1868 #define PCIE_PWR_MGMT_L1_THRESH_4MS      0x0000ff00
1869 #define PCIE_PWR_MGMT_EXT_ASPM_TMR_EN    0x01000000
1870 /* 0x7d2c --> 0x7d54 unused */
1871
1872 #define TG3_PCIE_LNKCTL                 0x00007d54
1873 #define  TG3_PCIE_LNKCTL_L1_PLL_PD_EN    0x00000008
1874 #define  TG3_PCIE_LNKCTL_L1_PLL_PD_DIS   0x00000080
1875 /* 0x7d58 --> 0x7e70 unused */
1876
1877 #define TG3_PCIE_PHY_TSTCTL             0x00007e2c
1878 #define  TG3_PCIE_PHY_TSTCTL_PCIE10      0x00000040
1879 #define  TG3_PCIE_PHY_TSTCTL_PSCRAM      0x00000020
1880
1881 #define TG3_PCIE_EIDLE_DELAY            0x00007e70
1882 #define  TG3_PCIE_EIDLE_DELAY_MASK       0x0000001f
1883 #define  TG3_PCIE_EIDLE_DELAY_13_CLKS    0x0000000c
1884 /* 0x7e74 --> 0x8000 unused */
1885
1886
1887 /* Alternate PCIE definitions */
1888 #define TG3_PCIE_TLDLPL_PORT            0x00007c00
1889 #define TG3_PCIE_PL_LO_PHYCTL1           0x00000004
1890 #define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN         0x00001000
1891 #define TG3_PCIE_PL_LO_PHYCTL5           0x00000014
1892 #define TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ       0x80000000
1893
1894 /* OTP bit definitions */
1895 #define TG3_OTP_AGCTGT_MASK             0x000000e0
1896 #define TG3_OTP_AGCTGT_SHIFT            1
1897 #define TG3_OTP_HPFFLTR_MASK            0x00000300
1898 #define TG3_OTP_HPFFLTR_SHIFT           1
1899 #define TG3_OTP_HPFOVER_MASK            0x00000400
1900 #define TG3_OTP_HPFOVER_SHIFT           1
1901 #define TG3_OTP_LPFDIS_MASK             0x00000800
1902 #define TG3_OTP_LPFDIS_SHIFT            11
1903 #define TG3_OTP_VDAC_MASK               0xff000000
1904 #define TG3_OTP_VDAC_SHIFT              24
1905 #define TG3_OTP_10BTAMP_MASK            0x0000f000
1906 #define TG3_OTP_10BTAMP_SHIFT           8
1907 #define TG3_OTP_ROFF_MASK               0x00e00000
1908 #define TG3_OTP_ROFF_SHIFT              11
1909 #define TG3_OTP_RCOFF_MASK              0x001c0000
1910 #define TG3_OTP_RCOFF_SHIFT             16
1911
1912 #define TG3_OTP_DEFAULT                 0x286c1640
1913
1914
1915 /* Hardware Legacy NVRAM layout */
1916 #define TG3_NVM_VPD_OFF                 0x100
1917 #define TG3_NVM_VPD_LEN                 256
1918
1919 /* Hardware Selfboot NVRAM layout */
1920 #define TG3_NVM_HWSB_CFG1               0x00000004
1921 #define  TG3_NVM_HWSB_CFG1_MAJMSK       0xf8000000
1922 #define  TG3_NVM_HWSB_CFG1_MAJSFT       27
1923 #define  TG3_NVM_HWSB_CFG1_MINMSK       0x07c00000
1924 #define  TG3_NVM_HWSB_CFG1_MINSFT       22
1925
1926 #define TG3_EEPROM_MAGIC                0x669955aa
1927 #define TG3_EEPROM_MAGIC_FW             0xa5000000
1928 #define TG3_EEPROM_MAGIC_FW_MSK         0xff000000
1929 #define TG3_EEPROM_SB_FORMAT_MASK       0x00e00000
1930 #define TG3_EEPROM_SB_FORMAT_1          0x00200000
1931 #define TG3_EEPROM_SB_REVISION_MASK     0x001f0000
1932 #define TG3_EEPROM_SB_REVISION_0        0x00000000
1933 #define TG3_EEPROM_SB_REVISION_2        0x00020000
1934 #define TG3_EEPROM_SB_REVISION_3        0x00030000
1935 #define TG3_EEPROM_SB_REVISION_4        0x00040000
1936 #define TG3_EEPROM_SB_REVISION_5        0x00050000
1937 #define TG3_EEPROM_SB_REVISION_6        0x00060000
1938 #define TG3_EEPROM_MAGIC_HW             0xabcd
1939 #define TG3_EEPROM_MAGIC_HW_MSK         0xffff
1940
1941 #define TG3_NVM_DIR_START               0x18
1942 #define TG3_NVM_DIR_END                 0x78
1943 #define TG3_NVM_DIRENT_SIZE             0xc
1944 #define TG3_NVM_DIRTYPE_SHIFT           24
1945 #define TG3_NVM_DIRTYPE_ASFINI          1
1946 #define TG3_NVM_PTREV_BCVER             0x94
1947 #define TG3_NVM_BCVER_MAJMSK            0x0000ff00
1948 #define TG3_NVM_BCVER_MAJSFT            8
1949 #define TG3_NVM_BCVER_MINMSK            0x000000ff
1950
1951 #define TG3_EEPROM_SB_F1R0_EDH_OFF      0x10
1952 #define TG3_EEPROM_SB_F1R2_EDH_OFF      0x14
1953 #define TG3_EEPROM_SB_F1R2_MBA_OFF      0x10
1954 #define TG3_EEPROM_SB_F1R3_EDH_OFF      0x18
1955 #define TG3_EEPROM_SB_F1R4_EDH_OFF      0x1c
1956 #define TG3_EEPROM_SB_F1R5_EDH_OFF      0x20
1957 #define TG3_EEPROM_SB_F1R6_EDH_OFF      0x4c
1958 #define TG3_EEPROM_SB_EDH_MAJ_MASK      0x00000700
1959 #define TG3_EEPROM_SB_EDH_MAJ_SHFT      8
1960 #define TG3_EEPROM_SB_EDH_MIN_MASK      0x000000ff
1961 #define TG3_EEPROM_SB_EDH_BLD_MASK      0x0000f800
1962 #define TG3_EEPROM_SB_EDH_BLD_SHFT      11
1963
1964
1965 /* 32K Window into NIC internal memory */
1966 #define NIC_SRAM_WIN_BASE               0x00008000
1967
1968 /* Offsets into first 32k of NIC internal memory. */
1969 #define NIC_SRAM_PAGE_ZERO              0x00000000
1970 #define NIC_SRAM_SEND_RCB               0x00000100 /* 16 * TG3_BDINFO_... */
1971 #define NIC_SRAM_RCV_RET_RCB            0x00000200 /* 16 * TG3_BDINFO_... */
1972 #define NIC_SRAM_STATS_BLK              0x00000300
1973 #define NIC_SRAM_STATUS_BLK             0x00000b00
1974
1975 #define NIC_SRAM_FIRMWARE_MBOX          0x00000b50
1976 #define  NIC_SRAM_FIRMWARE_MBOX_MAGIC1   0x4B657654
1977 #define  NIC_SRAM_FIRMWARE_MBOX_MAGIC2   0x4861764b /* !dma on linkchg */
1978
1979 #define NIC_SRAM_DATA_SIG               0x00000b54
1980 #define  NIC_SRAM_DATA_SIG_MAGIC         0x4b657654 /* ascii for 'KevT' */
1981
1982 #define NIC_SRAM_DATA_CFG                       0x00000b58
1983 #define  NIC_SRAM_DATA_CFG_LED_MODE_MASK         0x0000000c
1984 #define  NIC_SRAM_DATA_CFG_LED_MODE_MAC          0x00000000
1985 #define  NIC_SRAM_DATA_CFG_LED_MODE_PHY_1        0x00000004
1986 #define  NIC_SRAM_DATA_CFG_LED_MODE_PHY_2        0x00000008
1987 #define  NIC_SRAM_DATA_CFG_PHY_TYPE_MASK         0x00000030
1988 #define  NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN      0x00000000
1989 #define  NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER       0x00000010
1990 #define  NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER        0x00000020
1991 #define  NIC_SRAM_DATA_CFG_WOL_ENABLE            0x00000040
1992 #define  NIC_SRAM_DATA_CFG_ASF_ENABLE            0x00000080
1993 #define  NIC_SRAM_DATA_CFG_EEPROM_WP             0x00000100
1994 #define  NIC_SRAM_DATA_CFG_MINI_PCI              0x00001000
1995 #define  NIC_SRAM_DATA_CFG_FIBER_WOL             0x00004000
1996 #define  NIC_SRAM_DATA_CFG_NO_GPIO2              0x00100000
1997 #define  NIC_SRAM_DATA_CFG_APE_ENABLE            0x00200000
1998
1999 #define NIC_SRAM_DATA_VER                       0x00000b5c
2000 #define  NIC_SRAM_DATA_VER_SHIFT                 16
2001
2002 #define NIC_SRAM_DATA_PHY_ID            0x00000b74
2003 #define  NIC_SRAM_DATA_PHY_ID1_MASK      0xffff0000
2004 #define  NIC_SRAM_DATA_PHY_ID2_MASK      0x0000ffff
2005
2006 #define NIC_SRAM_FW_CMD_MBOX            0x00000b78
2007 #define  FWCMD_NICDRV_ALIVE              0x00000001
2008 #define  FWCMD_NICDRV_PAUSE_FW           0x00000002
2009 #define  FWCMD_NICDRV_IPV4ADDR_CHG       0x00000003
2010 #define  FWCMD_NICDRV_IPV6ADDR_CHG       0x00000004
2011 #define  FWCMD_NICDRV_FIX_DMAR           0x00000005
2012 #define  FWCMD_NICDRV_FIX_DMAW           0x00000006
2013 #define  FWCMD_NICDRV_LINK_UPDATE        0x0000000c
2014 #define  FWCMD_NICDRV_ALIVE2             0x0000000d
2015 #define  FWCMD_NICDRV_ALIVE3             0x0000000e
2016 #define NIC_SRAM_FW_CMD_LEN_MBOX        0x00000b7c
2017 #define NIC_SRAM_FW_CMD_DATA_MBOX       0x00000b80
2018 #define NIC_SRAM_FW_ASF_STATUS_MBOX     0x00000c00
2019 #define NIC_SRAM_FW_DRV_STATE_MBOX      0x00000c04
2020 #define  DRV_STATE_START                 0x00000001
2021 #define  DRV_STATE_START_DONE            0x80000001
2022 #define  DRV_STATE_UNLOAD                0x00000002
2023 #define  DRV_STATE_UNLOAD_DONE           0x80000002
2024 #define  DRV_STATE_WOL                   0x00000003
2025 #define  DRV_STATE_SUSPEND               0x00000004
2026
2027 #define NIC_SRAM_FW_RESET_TYPE_MBOX     0x00000c08
2028
2029 #define NIC_SRAM_MAC_ADDR_HIGH_MBOX     0x00000c14
2030 #define NIC_SRAM_MAC_ADDR_LOW_MBOX      0x00000c18
2031
2032 #define NIC_SRAM_WOL_MBOX               0x00000d30
2033 #define  WOL_SIGNATURE                   0x474c0000
2034 #define  WOL_DRV_STATE_SHUTDOWN          0x00000001
2035 #define  WOL_DRV_WOL                     0x00000002
2036 #define  WOL_SET_MAGIC_PKT               0x00000004
2037
2038 #define NIC_SRAM_DATA_CFG_2             0x00000d38
2039
2040 #define  NIC_SRAM_DATA_CFG_2_APD_EN      0x00000400
2041 #define  SHASTA_EXT_LED_MODE_MASK        0x00018000
2042 #define  SHASTA_EXT_LED_LEGACY           0x00000000
2043 #define  SHASTA_EXT_LED_SHARED           0x00008000
2044 #define  SHASTA_EXT_LED_MAC              0x00010000
2045 #define  SHASTA_EXT_LED_COMBO            0x00018000
2046
2047 #define NIC_SRAM_DATA_CFG_3             0x00000d3c
2048 #define  NIC_SRAM_ASPM_DEBOUNCE          0x00000002
2049
2050 #define NIC_SRAM_DATA_CFG_4             0x00000d60
2051 #define  NIC_SRAM_GMII_MODE              0x00000002
2052 #define  NIC_SRAM_RGMII_INBAND_DISABLE   0x00000004
2053 #define  NIC_SRAM_RGMII_EXT_IBND_RX_EN   0x00000008
2054 #define  NIC_SRAM_RGMII_EXT_IBND_TX_EN   0x00000010
2055
2056 #define NIC_SRAM_RX_MINI_BUFFER_DESC    0x00001000
2057
2058 #define NIC_SRAM_DMA_DESC_POOL_BASE     0x00002000
2059 #define  NIC_SRAM_DMA_DESC_POOL_SIZE     0x00002000
2060 #define NIC_SRAM_TX_BUFFER_DESC         0x00004000 /* 512 entries */
2061 #define NIC_SRAM_RX_BUFFER_DESC         0x00006000 /* 256 entries */
2062 #define NIC_SRAM_RX_JUMBO_BUFFER_DESC   0x00007000 /* 256 entries */
2063 #define NIC_SRAM_MBUF_POOL_BASE         0x00008000
2064 #define  NIC_SRAM_MBUF_POOL_SIZE96       0x00018000
2065 #define  NIC_SRAM_MBUF_POOL_SIZE64       0x00010000
2066 #define  NIC_SRAM_MBUF_POOL_BASE5705    0x00010000
2067 #define  NIC_SRAM_MBUF_POOL_SIZE5705    0x0000e000
2068
2069
2070 /* Currently this is fixed. */
2071 #define TG3_PHY_MII_ADDR                0x01
2072
2073
2074 /*** Tigon3 specific PHY MII registers. ***/
2075 #define  TG3_BMCR_SPEED1000             0x0040
2076
2077 #define MII_TG3_CTRL                    0x09 /* 1000-baseT control register */
2078 #define  MII_TG3_CTRL_ADV_1000_HALF     0x0100
2079 #define  MII_TG3_CTRL_ADV_1000_FULL     0x0200
2080 #define  MII_TG3_CTRL_AS_MASTER         0x0800
2081 #define  MII_TG3_CTRL_ENABLE_AS_MASTER  0x1000
2082
2083 #define MII_TG3_MMD_CTRL                0x0d /* MMD Access Control register */
2084 #define MII_TG3_MMD_CTRL_DATA_NOINC     0x4000
2085 #define MII_TG3_MMD_ADDRESS             0x0e /* MMD Address Data register */
2086
2087 #define MII_TG3_EXT_CTRL                0x10 /* Extended control register */
2088 #define  MII_TG3_EXT_CTRL_FIFO_ELASTIC  0x0001
2089 #define  MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002
2090 #define  MII_TG3_EXT_CTRL_FORCE_LED_OFF 0x0008
2091 #define  MII_TG3_EXT_CTRL_TBI           0x8000
2092
2093 #define MII_TG3_EXT_STAT                0x11 /* Extended status register */
2094 #define  MII_TG3_EXT_STAT_LPASS         0x0100
2095
2096 #define MII_TG3_RXR_COUNTERS            0x14 /* Local/Remote Receiver Counts */
2097 #define MII_TG3_DSP_RW_PORT             0x15 /* DSP coefficient read/write port */
2098 #define MII_TG3_DSP_CONTROL             0x16 /* DSP control register */
2099 #define MII_TG3_DSP_ADDRESS             0x17 /* DSP address register */
2100
2101 #define MII_TG3_DSP_TAP1                0x0001
2102 #define  MII_TG3_DSP_TAP1_AGCTGT_DFLT   0x0007
2103 #define MII_TG3_DSP_AADJ1CH0            0x001f
2104 #define MII_TG3_DSP_CH34TP2             0x4022
2105 #define MII_TG3_DSP_CH34TP2_HIBW01      0x0010
2106 #define MII_TG3_DSP_AADJ1CH3            0x601f
2107 #define  MII_TG3_DSP_AADJ1CH3_ADCCKADJ  0x0002
2108 #define MII_TG3_DSP_EXP1_INT_STAT       0x0f01
2109 #define MII_TG3_DSP_EXP8                0x0f08
2110 #define  MII_TG3_DSP_EXP8_REJ2MHz       0x0001
2111 #define  MII_TG3_DSP_EXP8_AEDW          0x0200
2112 #define MII_TG3_DSP_EXP75               0x0f75
2113 #define MII_TG3_DSP_EXP96               0x0f96
2114 #define MII_TG3_DSP_EXP97               0x0f97
2115
2116 #define MII_TG3_AUX_CTRL                0x18 /* auxilliary control register */
2117
2118 #define MII_TG3_AUXCTL_PCTL_100TX_LPWR  0x0010
2119 #define MII_TG3_AUXCTL_PCTL_SPR_ISOLATE 0x0020
2120 #define MII_TG3_AUXCTL_PCTL_VREG_11V    0x0180
2121 #define MII_TG3_AUXCTL_SHDWSEL_PWRCTL   0x0002
2122
2123 #define MII_TG3_AUXCTL_MISC_WREN        0x8000
2124 #define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200
2125 #define MII_TG3_AUXCTL_MISC_RDSEL_MISC  0x7000
2126 #define MII_TG3_AUXCTL_SHDWSEL_MISC     0x0007
2127
2128 #define MII_TG3_AUXCTL_ACTL_SMDSP_ENA   0x0800
2129 #define MII_TG3_AUXCTL_ACTL_TX_6DB      0x0400
2130 #define MII_TG3_AUXCTL_SHDWSEL_AUXCTL   0x0000
2131
2132 #define MII_TG3_AUX_STAT                0x19 /* auxilliary status register */
2133 #define MII_TG3_AUX_STAT_LPASS          0x0004
2134 #define MII_TG3_AUX_STAT_SPDMASK        0x0700
2135 #define MII_TG3_AUX_STAT_10HALF         0x0100
2136 #define MII_TG3_AUX_STAT_10FULL         0x0200
2137 #define MII_TG3_AUX_STAT_100HALF        0x0300
2138 #define MII_TG3_AUX_STAT_100_4          0x0400
2139 #define MII_TG3_AUX_STAT_100FULL        0x0500
2140 #define MII_TG3_AUX_STAT_1000HALF       0x0600
2141 #define MII_TG3_AUX_STAT_1000FULL       0x0700
2142 #define MII_TG3_AUX_STAT_100            0x0008
2143 #define MII_TG3_AUX_STAT_FULL           0x0001
2144
2145 #define MII_TG3_ISTAT                   0x1a /* IRQ status register */
2146 #define MII_TG3_IMASK                   0x1b /* IRQ mask register */
2147
2148 /* ISTAT/IMASK event bits */
2149 #define MII_TG3_INT_LINKCHG             0x0002
2150 #define MII_TG3_INT_SPEEDCHG            0x0004
2151 #define MII_TG3_INT_DUPLEXCHG           0x0008
2152 #define MII_TG3_INT_ANEG_PAGE_RX        0x0400
2153
2154 #define MII_TG3_MISC_SHDW               0x1c
2155 #define MII_TG3_MISC_SHDW_WREN          0x8000
2156
2157 #define MII_TG3_MISC_SHDW_APD_WKTM_84MS 0x0001
2158 #define MII_TG3_MISC_SHDW_APD_ENABLE    0x0020
2159 #define MII_TG3_MISC_SHDW_APD_SEL       0x2800
2160
2161 #define MII_TG3_MISC_SHDW_SCR5_C125OE   0x0001
2162 #define MII_TG3_MISC_SHDW_SCR5_DLLAPD   0x0002
2163 #define MII_TG3_MISC_SHDW_SCR5_SDTL     0x0004
2164 #define MII_TG3_MISC_SHDW_SCR5_DLPTLM   0x0008
2165 #define MII_TG3_MISC_SHDW_SCR5_LPED     0x0010
2166 #define MII_TG3_MISC_SHDW_SCR5_SEL      0x1400
2167
2168 #define MII_TG3_TEST1                   0x1e
2169 #define MII_TG3_TEST1_TRIM_EN           0x0010
2170 #define MII_TG3_TEST1_CRC_EN            0x8000
2171
2172 /* Clause 45 expansion registers */
2173 #define TG3_CL45_D7_EEEADV_CAP          0x003c
2174 #define TG3_CL45_D7_EEEADV_CAP_100TX    0x0002
2175 #define TG3_CL45_D7_EEEADV_CAP_1000T    0x0004
2176 #define TG3_CL45_D7_EEERES_STAT         0x803e
2177 #define TG3_CL45_D7_EEERES_STAT_LP_100TX        0x0002
2178 #define TG3_CL45_D7_EEERES_STAT_LP_1000T        0x0004
2179
2180
2181 /* Fast Ethernet Tranceiver definitions */
2182 #define MII_TG3_FET_PTEST               0x17
2183 #define  MII_TG3_FET_PTEST_FRC_TX_LINK  0x1000
2184 #define  MII_TG3_FET_PTEST_FRC_TX_LOCK  0x0800
2185
2186 #define MII_TG3_FET_TEST                0x1f
2187 #define  MII_TG3_FET_SHADOW_EN          0x0080
2188
2189 #define MII_TG3_FET_SHDW_MISCCTRL       0x10
2190 #define  MII_TG3_FET_SHDW_MISCCTRL_MDIX 0x4000
2191
2192 #define MII_TG3_FET_SHDW_AUXMODE4       0x1a
2193 #define MII_TG3_FET_SHDW_AUXMODE4_SBPD  0x0008
2194
2195 #define MII_TG3_FET_SHDW_AUXSTAT2       0x1b
2196 #define  MII_TG3_FET_SHDW_AUXSTAT2_APD  0x0020
2197
2198
2199 /* APE registers.  Accessible through BAR1 */
2200 #define TG3_APE_EVENT                   0x000c
2201 #define  APE_EVENT_1                     0x00000001
2202 #define TG3_APE_LOCK_REQ                0x002c
2203 #define  APE_LOCK_REQ_DRIVER             0x00001000
2204 #define TG3_APE_LOCK_GRANT              0x004c
2205 #define  APE_LOCK_GRANT_DRIVER           0x00001000
2206 #define TG3_APE_SEG_SIG                 0x4000
2207 #define  APE_SEG_SIG_MAGIC               0x41504521
2208
2209 /* APE shared memory.  Accessible through BAR1 */
2210 #define TG3_APE_FW_STATUS               0x400c
2211 #define  APE_FW_STATUS_READY             0x00000100
2212 #define TG3_APE_FW_FEATURES             0x4010
2213 #define  TG3_APE_FW_FEATURE_NCSI         0x00000002
2214 #define TG3_APE_FW_VERSION              0x4018
2215 #define  APE_FW_VERSION_MAJMSK           0xff000000
2216 #define  APE_FW_VERSION_MAJSFT           24
2217 #define  APE_FW_VERSION_MINMSK           0x00ff0000
2218 #define  APE_FW_VERSION_MINSFT           16
2219 #define  APE_FW_VERSION_REVMSK           0x0000ff00
2220 #define  APE_FW_VERSION_REVSFT           8
2221 #define  APE_FW_VERSION_BLDMSK           0x000000ff
2222 #define TG3_APE_HOST_SEG_SIG            0x4200
2223 #define  APE_HOST_SEG_SIG_MAGIC          0x484f5354
2224 #define TG3_APE_HOST_SEG_LEN            0x4204
2225 #define  APE_HOST_SEG_LEN_MAGIC          0x00000020
2226 #define TG3_APE_HOST_INIT_COUNT         0x4208
2227 #define TG3_APE_HOST_DRIVER_ID          0x420c
2228 #define  APE_HOST_DRIVER_ID_LINUX        0xf0000000
2229 #define  APE_HOST_DRIVER_ID_MAGIC(maj, min)     \
2230         (APE_HOST_DRIVER_ID_LINUX | (maj & 0xff) << 16 | (min & 0xff) << 8)
2231 #define TG3_APE_HOST_BEHAVIOR           0x4210
2232 #define  APE_HOST_BEHAV_NO_PHYLOCK       0x00000001
2233 #define TG3_APE_HOST_HEARTBEAT_INT_MS   0x4214
2234 #define  APE_HOST_HEARTBEAT_INT_DISABLE  0
2235 #define  APE_HOST_HEARTBEAT_INT_5SEC     5000
2236 #define TG3_APE_HOST_HEARTBEAT_COUNT    0x4218
2237 #define TG3_APE_HOST_DRVR_STATE         0x421c
2238 #define TG3_APE_HOST_DRVR_STATE_START    0x00000001
2239 #define TG3_APE_HOST_DRVR_STATE_UNLOAD   0x00000002
2240 #define TG3_APE_HOST_DRVR_STATE_WOL      0x00000003
2241 #define TG3_APE_HOST_WOL_SPEED          0x4224
2242 #define TG3_APE_HOST_WOL_SPEED_AUTO      0x00008000
2243
2244 #define TG3_APE_EVENT_STATUS            0x4300
2245
2246 #define  APE_EVENT_STATUS_DRIVER_EVNT    0x00000010
2247 #define  APE_EVENT_STATUS_STATE_CHNGE    0x00000500
2248 #define  APE_EVENT_STATUS_STATE_START    0x00010000
2249 #define  APE_EVENT_STATUS_STATE_UNLOAD   0x00020000
2250 #define  APE_EVENT_STATUS_STATE_WOL      0x00030000
2251 #define  APE_EVENT_STATUS_STATE_SUSPEND  0x00040000
2252 #define  APE_EVENT_STATUS_EVENT_PENDING  0x80000000
2253
2254 #define TG3_APE_PER_LOCK_REQ            0x8400
2255 #define  APE_LOCK_PER_REQ_DRIVER         0x00001000
2256 #define TG3_APE_PER_LOCK_GRANT          0x8420
2257 #define  APE_PER_LOCK_GRANT_DRIVER       0x00001000
2258
2259 /* APE convenience enumerations. */
2260 #define TG3_APE_LOCK_GRC                1
2261 #define TG3_APE_LOCK_MEM                4
2262
2263 #define TG3_EEPROM_SB_F1R2_MBA_OFF      0x10
2264
2265
2266 /* There are two ways to manage the TX descriptors on the tigon3.
2267  * Either the descriptors are in host DMA'able memory, or they
2268  * exist only in the cards on-chip SRAM.  All 16 send bds are under
2269  * the same mode, they may not be configured individually.
2270  *
2271  * This driver always uses host memory TX descriptors.
2272  *
2273  * To use host memory TX descriptors:
2274  *      1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register.
2275  *         Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear.
2276  *      2) Allocate DMA'able memory.
2277  *      3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
2278  *         a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory
2279  *            obtained in step 2
2280  *         b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC.
2281  *         c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number
2282  *            of TX descriptors.  Leave flags field clear.
2283  *      4) Access TX descriptors via host memory.  The chip
2284  *         will refetch into local SRAM as needed when producer
2285  *         index mailboxes are updated.
2286  *
2287  * To use on-chip TX descriptors:
2288  *      1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register.
2289  *         Make sure GRC_MODE_HOST_SENDBDS is clear.
2290  *      2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
2291  *         a) Set TG3_BDINFO_HOST_ADDR to zero.
2292  *         b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC
2293  *         c) TG3_BDINFO_MAXLEN_FLAGS is don't care.
2294  *      3) Access TX descriptors directly in on-chip SRAM
2295  *         using normal {read,write}l().  (and not using
2296  *         pointer dereferencing of ioremap()'d memory like
2297  *         the broken Broadcom driver does)
2298  *
2299  * Note that BDINFO_FLAGS_DISABLED should be set in the flags field of
2300  * TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices.
2301  */
2302 struct tg3_tx_buffer_desc {
2303         u32                             addr_hi;
2304         u32                             addr_lo;
2305
2306         u32                             len_flags;
2307 #define TXD_FLAG_TCPUDP_CSUM            0x0001
2308 #define TXD_FLAG_IP_CSUM                0x0002
2309 #define TXD_FLAG_END                    0x0004
2310 #define TXD_FLAG_IP_FRAG                0x0008
2311 #define TXD_FLAG_JMB_PKT                0x0008
2312 #define TXD_FLAG_IP_FRAG_END            0x0010
2313 #define TXD_FLAG_VLAN                   0x0040
2314 #define TXD_FLAG_COAL_NOW               0x0080
2315 #define TXD_FLAG_CPU_PRE_DMA            0x0100
2316 #define TXD_FLAG_CPU_POST_DMA           0x0200
2317 #define TXD_FLAG_ADD_SRC_ADDR           0x1000
2318 #define TXD_FLAG_CHOOSE_SRC_ADDR        0x6000
2319 #define TXD_FLAG_NO_CRC                 0x8000
2320 #define TXD_LEN_SHIFT                   16
2321
2322         u32                             vlan_tag;
2323 #define TXD_VLAN_TAG_SHIFT              0
2324 #define TXD_MSS_SHIFT                   16
2325 };
2326
2327 #define TXD_ADDR                        0x00UL /* 64-bit */
2328 #define TXD_LEN_FLAGS                   0x08UL /* 32-bit (upper 16-bits are len) */
2329 #define TXD_VLAN_TAG                    0x0cUL /* 32-bit (upper 16-bits are tag) */
2330 #define TXD_SIZE                        0x10UL
2331
2332 struct tg3_rx_buffer_desc {
2333         u32                             addr_hi;
2334         u32                             addr_lo;
2335
2336         u32                             idx_len;
2337 #define RXD_IDX_MASK    0xffff0000
2338 #define RXD_IDX_SHIFT   16
2339 #define RXD_LEN_MASK    0x0000ffff
2340 #define RXD_LEN_SHIFT   0
2341
2342         u32                             type_flags;
2343 #define RXD_TYPE_SHIFT  16
2344 #define RXD_FLAGS_SHIFT 0
2345
2346 #define RXD_FLAG_END                    0x0004
2347 #define RXD_FLAG_MINI                   0x0800
2348 #define RXD_FLAG_JUMBO                  0x0020
2349 #define RXD_FLAG_VLAN                   0x0040
2350 #define RXD_FLAG_ERROR                  0x0400
2351 #define RXD_FLAG_IP_CSUM                0x1000
2352 #define RXD_FLAG_TCPUDP_CSUM            0x2000
2353 #define RXD_FLAG_IS_TCP                 0x4000
2354
2355         u32                             ip_tcp_csum;
2356 #define RXD_IPCSUM_MASK         0xffff0000
2357 #define RXD_IPCSUM_SHIFT        16
2358 #define RXD_TCPCSUM_MASK        0x0000ffff
2359 #define RXD_TCPCSUM_SHIFT       0
2360
2361         u32                             err_vlan;
2362
2363 #define RXD_VLAN_MASK                   0x0000ffff
2364
2365 #define RXD_ERR_BAD_CRC                 0x00010000
2366 #define RXD_ERR_COLLISION               0x00020000
2367 #define RXD_ERR_LINK_LOST               0x00040000
2368 #define RXD_ERR_PHY_DECODE              0x00080000
2369 #define RXD_ERR_ODD_NIBBLE_RCVD_MII     0x00100000
2370 #define RXD_ERR_MAC_ABRT                0x00200000
2371 #define RXD_ERR_TOO_SMALL               0x00400000
2372 #define RXD_ERR_NO_RESOURCES            0x00800000
2373 #define RXD_ERR_HUGE_FRAME              0x01000000
2374 #define RXD_ERR_MASK                    0xffff0000
2375
2376         u32                             reserved;
2377         u32                             opaque;
2378 #define RXD_OPAQUE_INDEX_MASK           0x0000ffff
2379 #define RXD_OPAQUE_INDEX_SHIFT          0
2380 #define RXD_OPAQUE_RING_STD             0x00010000
2381 #define RXD_OPAQUE_RING_JUMBO           0x00020000
2382 #define RXD_OPAQUE_RING_MINI            0x00040000
2383 #define RXD_OPAQUE_RING_MASK            0x00070000
2384 };
2385
2386 struct tg3_ext_rx_buffer_desc {
2387         struct {
2388                 u32                     addr_hi;
2389                 u32                     addr_lo;
2390         }                               addrlist[3];
2391         u32                             len2_len1;
2392         u32                             resv_len3;
2393         struct tg3_rx_buffer_desc       std;
2394 };
2395
2396 /* We only use this when testing out the DMA engine
2397  * at probe time.  This is the internal format of buffer
2398  * descriptors used by the chip at NIC_SRAM_DMA_DESCS.
2399  */
2400 struct tg3_internal_buffer_desc {
2401         u32                             addr_hi;
2402         u32                             addr_lo;
2403         u32                             nic_mbuf;
2404         /* XXX FIX THIS */
2405 #ifdef __BIG_ENDIAN
2406         u16                             cqid_sqid;
2407         u16                             len;
2408 #else
2409         u16                             len;
2410         u16                             cqid_sqid;
2411 #endif
2412         u32                             flags;
2413         u32                             __cookie1;
2414         u32                             __cookie2;
2415         u32                             __cookie3;
2416 };
2417
2418 #define TG3_HW_STATUS_SIZE              0x50
2419 struct tg3_hw_status {
2420         u32                             status;
2421 #define SD_STATUS_UPDATED               0x00000001
2422 #define SD_STATUS_LINK_CHG              0x00000002
2423 #define SD_STATUS_ERROR                 0x00000004
2424
2425         u32                             status_tag;
2426
2427 #ifdef __BIG_ENDIAN
2428         u16                             rx_consumer;
2429         u16                             rx_jumbo_consumer;
2430 #else
2431         u16                             rx_jumbo_consumer;
2432         u16                             rx_consumer;
2433 #endif
2434
2435 #ifdef __BIG_ENDIAN
2436         u16                             reserved;
2437         u16                             rx_mini_consumer;
2438 #else
2439         u16                             rx_mini_consumer;
2440         u16                             reserved;
2441 #endif
2442         struct {
2443 #ifdef __BIG_ENDIAN
2444                 u16                     tx_consumer;
2445                 u16                     rx_producer;
2446 #else
2447                 u16                     rx_producer;
2448                 u16                     tx_consumer;
2449 #endif
2450         }                               idx[16];
2451 };
2452
2453 typedef struct {
2454         u32 high, low;
2455 } tg3_stat64_t;
2456
2457 struct tg3_hw_stats {
2458         u8                              __reserved0[0x400-0x300];
2459
2460         /* Statistics maintained by Receive MAC. */
2461         tg3_stat64_t                    rx_octets;
2462         u64                             __reserved1;
2463         tg3_stat64_t                    rx_fragments;
2464         tg3_stat64_t                    rx_ucast_packets;
2465         tg3_stat64_t                    rx_mcast_packets;
2466         tg3_stat64_t                    rx_bcast_packets;
2467         tg3_stat64_t                    rx_fcs_errors;
2468         tg3_stat64_t                    rx_align_errors;
2469         tg3_stat64_t                    rx_xon_pause_rcvd;
2470         tg3_stat64_t                    rx_xoff_pause_rcvd;
2471         tg3_stat64_t                    rx_mac_ctrl_rcvd;
2472         tg3_stat64_t                    rx_xoff_entered;
2473         tg3_stat64_t                    rx_frame_too_long_errors;
2474         tg3_stat64_t                    rx_jabbers;
2475         tg3_stat64_t                    rx_undersize_packets;
2476         tg3_stat64_t                    rx_in_length_errors;
2477         tg3_stat64_t                    rx_out_length_errors;
2478         tg3_stat64_t                    rx_64_or_less_octet_packets;
2479         tg3_stat64_t                    rx_65_to_127_octet_packets;
2480         tg3_stat64_t                    rx_128_to_255_octet_packets;
2481         tg3_stat64_t                    rx_256_to_511_octet_packets;
2482         tg3_stat64_t                    rx_512_to_1023_octet_packets;
2483         tg3_stat64_t                    rx_1024_to_1522_octet_packets;
2484         tg3_stat64_t                    rx_1523_to_2047_octet_packets;
2485         tg3_stat64_t                    rx_2048_to_4095_octet_packets;
2486         tg3_stat64_t                    rx_4096_to_8191_octet_packets;
2487         tg3_stat64_t                    rx_8192_to_9022_octet_packets;
2488
2489         u64                             __unused0[37];
2490
2491         /* Statistics maintained by Transmit MAC. */
2492         tg3_stat64_t                    tx_octets;
2493         u64                             __reserved2;
2494         tg3_stat64_t                    tx_collisions;
2495         tg3_stat64_t                    tx_xon_sent;
2496         tg3_stat64_t                    tx_xoff_sent;
2497         tg3_stat64_t                    tx_flow_control;
2498         tg3_stat64_t                    tx_mac_errors;
2499         tg3_stat64_t                    tx_single_collisions;
2500         tg3_stat64_t                    tx_mult_collisions;
2501         tg3_stat64_t                    tx_deferred;
2502         u64                             __reserved3;
2503         tg3_stat64_t                    tx_excessive_collisions;
2504         tg3_stat64_t                    tx_late_collisions;
2505         tg3_stat64_t                    tx_collide_2times;
2506         tg3_stat64_t                    tx_collide_3times;
2507         tg3_stat64_t                    tx_collide_4times;
2508         tg3_stat64_t                    tx_collide_5times;
2509         tg3_stat64_t                    tx_collide_6times;
2510         tg3_stat64_t                    tx_collide_7times;
2511         tg3_stat64_t                    tx_collide_8times;
2512         tg3_stat64_t                    tx_collide_9times;
2513         tg3_stat64_t                    tx_collide_10times;
2514         tg3_stat64_t                    tx_collide_11times;
2515         tg3_stat64_t                    tx_collide_12times;
2516         tg3_stat64_t                    tx_collide_13times;
2517         tg3_stat64_t                    tx_collide_14times;
2518         tg3_stat64_t                    tx_collide_15times;
2519         tg3_stat64_t                    tx_ucast_packets;
2520         tg3_stat64_t                    tx_mcast_packets;
2521         tg3_stat64_t                    tx_bcast_packets;
2522         tg3_stat64_t                    tx_carrier_sense_errors;
2523         tg3_stat64_t                    tx_discards;
2524         tg3_stat64_t                    tx_errors;
2525
2526         u64                             __unused1[31];
2527
2528         /* Statistics maintained by Receive List Placement. */
2529         tg3_stat64_t                    COS_rx_packets[16];
2530         tg3_stat64_t                    COS_rx_filter_dropped;
2531         tg3_stat64_t                    dma_writeq_full;
2532         tg3_stat64_t                    dma_write_prioq_full;
2533         tg3_stat64_t                    rxbds_empty;
2534         tg3_stat64_t                    rx_discards;
2535         tg3_stat64_t                    rx_errors;
2536         tg3_stat64_t                    rx_threshold_hit;
2537
2538         u64                             __unused2[9];
2539
2540         /* Statistics maintained by Send Data Initiator. */
2541         tg3_stat64_t                    COS_out_packets[16];
2542         tg3_stat64_t                    dma_readq_full;
2543         tg3_stat64_t                    dma_read_prioq_full;
2544         tg3_stat64_t                    tx_comp_queue_full;
2545
2546         /* Statistics maintained by Host Coalescing. */
2547         tg3_stat64_t                    ring_set_send_prod_index;
2548         tg3_stat64_t                    ring_status_update;
2549         tg3_stat64_t                    nic_irqs;
2550         tg3_stat64_t                    nic_avoided_irqs;
2551         tg3_stat64_t                    nic_tx_threshold_hit;
2552
2553         u8                              __reserved4[0xb00-0x9c0];
2554 };
2555
2556 /* 'mapping' is superfluous as the chip does not write into
2557  * the tx/rx post rings so we could just fetch it from there.
2558  * But the cache behavior is better how we are doing it now.
2559  */
2560 struct ring_info {
2561         struct sk_buff                  *skb;
2562         DEFINE_DMA_UNMAP_ADDR(mapping);
2563 };
2564
2565 struct tg3_config_info {
2566         u32                             flags;
2567 };
2568
2569 struct tg3_link_config {
2570         /* Describes what we're trying to get. */
2571         u32                             advertising;
2572         u16                             speed;
2573         u8                              duplex;
2574         u8                              autoneg;
2575         u8                              flowctrl;
2576
2577         /* Describes what we actually have. */
2578         u8                              active_flowctrl;
2579
2580         u8                              active_duplex;
2581 #define SPEED_INVALID           0xffff
2582 #define DUPLEX_INVALID          0xff
2583 #define AUTONEG_INVALID         0xff
2584         u16                             active_speed;
2585
2586         /* When we go in and out of low power mode we need
2587          * to swap with this state.
2588          */
2589         u16                             orig_speed;
2590         u8                              orig_duplex;
2591         u8                              orig_autoneg;
2592         u32                             orig_advertising;
2593 };
2594
2595 struct tg3_bufmgr_config {
2596         u32             mbuf_read_dma_low_water;
2597         u32             mbuf_mac_rx_low_water;
2598         u32             mbuf_high_water;
2599
2600         u32             mbuf_read_dma_low_water_jumbo;
2601         u32             mbuf_mac_rx_low_water_jumbo;
2602         u32             mbuf_high_water_jumbo;
2603
2604         u32             dma_low_water;
2605         u32             dma_high_water;
2606 };
2607
2608 struct tg3_ethtool_stats {
2609         /* Statistics maintained by Receive MAC. */
2610         u64             rx_octets;
2611         u64             rx_fragments;
2612         u64             rx_ucast_packets;
2613         u64             rx_mcast_packets;
2614         u64             rx_bcast_packets;
2615         u64             rx_fcs_errors;
2616         u64             rx_align_errors;
2617         u64             rx_xon_pause_rcvd;
2618         u64             rx_xoff_pause_rcvd;
2619         u64             rx_mac_ctrl_rcvd;
2620         u64             rx_xoff_entered;
2621         u64             rx_frame_too_long_errors;
2622         u64             rx_jabbers;
2623         u64             rx_undersize_packets;
2624         u64             rx_in_length_errors;
2625         u64             rx_out_length_errors;
2626         u64             rx_64_or_less_octet_packets;
2627         u64             rx_65_to_127_octet_packets;
2628         u64             rx_128_to_255_octet_packets;
2629         u64             rx_256_to_511_octet_packets;
2630         u64             rx_512_to_1023_octet_packets;
2631         u64             rx_1024_to_1522_octet_packets;
2632         u64             rx_1523_to_2047_octet_packets;
2633         u64             rx_2048_to_4095_octet_packets;
2634         u64             rx_4096_to_8191_octet_packets;
2635         u64             rx_8192_to_9022_octet_packets;
2636
2637         /* Statistics maintained by Transmit MAC. */
2638         u64             tx_octets;
2639         u64             tx_collisions;
2640         u64             tx_xon_sent;
2641         u64             tx_xoff_sent;
2642         u64             tx_flow_control;
2643         u64             tx_mac_errors;
2644         u64             tx_single_collisions;
2645         u64             tx_mult_collisions;
2646         u64             tx_deferred;
2647         u64             tx_excessive_collisions;
2648         u64             tx_late_collisions;
2649         u64             tx_collide_2times;
2650         u64             tx_collide_3times;
2651         u64             tx_collide_4times;
2652         u64             tx_collide_5times;
2653         u64             tx_collide_6times;
2654         u64             tx_collide_7times;
2655         u64             tx_collide_8times;
2656         u64             tx_collide_9times;
2657         u64             tx_collide_10times;
2658         u64             tx_collide_11times;
2659         u64             tx_collide_12times;
2660         u64             tx_collide_13times;
2661         u64             tx_collide_14times;
2662         u64             tx_collide_15times;
2663         u64             tx_ucast_packets;
2664         u64             tx_mcast_packets;
2665         u64             tx_bcast_packets;
2666         u64             tx_carrier_sense_errors;
2667         u64             tx_discards;
2668         u64             tx_errors;
2669
2670         /* Statistics maintained by Receive List Placement. */
2671         u64             dma_writeq_full;
2672         u64             dma_write_prioq_full;
2673         u64             rxbds_empty;
2674         u64             rx_discards;
2675         u64             rx_errors;
2676         u64             rx_threshold_hit;
2677
2678         /* Statistics maintained by Send Data Initiator. */
2679         u64             dma_readq_full;
2680         u64             dma_read_prioq_full;
2681         u64             tx_comp_queue_full;
2682
2683         /* Statistics maintained by Host Coalescing. */
2684         u64             ring_set_send_prod_index;
2685         u64             ring_status_update;
2686         u64             nic_irqs;
2687         u64             nic_avoided_irqs;
2688         u64             nic_tx_threshold_hit;
2689 };
2690
2691 struct tg3_rx_prodring_set {
2692         u32                             rx_std_prod_idx;
2693         u32                             rx_std_cons_idx;
2694         u32                             rx_jmb_prod_idx;
2695         u32                             rx_jmb_cons_idx;
2696         struct tg3_rx_buffer_desc       *rx_std;
2697         struct tg3_ext_rx_buffer_desc   *rx_jmb;
2698         struct ring_info                *rx_std_buffers;
2699         struct ring_info                *rx_jmb_buffers;
2700         dma_addr_t                      rx_std_mapping;
2701         dma_addr_t                      rx_jmb_mapping;
2702 };
2703
2704 #define TG3_IRQ_MAX_VECS_RSS            5
2705 #define TG3_IRQ_MAX_VECS                TG3_IRQ_MAX_VECS_RSS
2706
2707 struct tg3_napi {
2708         struct napi_struct              napi    ____cacheline_aligned;
2709         struct tg3                      *tp;
2710         struct tg3_hw_status            *hw_status;
2711
2712         u32                             last_tag;
2713         u32                             last_irq_tag;
2714         u32                             int_mbox;
2715         u32                             coal_now;
2716         u32                             tx_prod;
2717         u32                             tx_cons;
2718         u32                             tx_pending;
2719         u32                             prodmbox;
2720
2721         u32                             consmbox;
2722         u32                             rx_rcb_ptr;
2723         u16                             *rx_rcb_prod_idx;
2724         struct tg3_rx_prodring_set      prodring;
2725
2726         struct tg3_rx_buffer_desc       *rx_rcb;
2727         struct tg3_tx_buffer_desc       *tx_ring;
2728         struct ring_info                *tx_buffers;
2729
2730         dma_addr_t                      status_mapping;
2731         dma_addr_t                      rx_rcb_mapping;
2732         dma_addr_t                      tx_desc_mapping;
2733
2734         char                            irq_lbl[IFNAMSIZ];
2735         unsigned int                    irq_vec;
2736 };
2737
2738 struct tg3 {
2739         /* begin "general, frequently-used members" cacheline section */
2740
2741         /* If the IRQ handler (which runs lockless) needs to be
2742          * quiesced, the following bitmask state is used.  The
2743          * SYNC flag is set by non-IRQ context code to initiate
2744          * the quiescence.
2745          *
2746          * When the IRQ handler notices that SYNC is set, it
2747          * disables interrupts and returns.
2748          *
2749          * When all outstanding IRQ handlers have returned after
2750          * the SYNC flag has been set, the setter can be assured
2751          * that interrupts will no longer get run.
2752          *
2753          * In this way all SMP driver locks are never acquired
2754          * in hw IRQ context, only sw IRQ context or lower.
2755          */
2756         unsigned int                    irq_sync;
2757
2758         /* SMP locking strategy:
2759          *
2760          * lock: Held during reset, PHY access, timer, and when
2761          *       updating tg3_flags and tg3_flags2.
2762          *
2763          * netif_tx_lock: Held during tg3_start_xmit. tg3_tx holds
2764          *                netif_tx_lock when it needs to call
2765          *                netif_wake_queue.
2766          *
2767          * Both of these locks are to be held with BH safety.
2768          *
2769          * Because the IRQ handler, tg3_poll, and tg3_start_xmit
2770          * are running lockless, it is necessary to completely
2771          * quiesce the chip with tg3_netif_stop and tg3_full_lock
2772          * before reconfiguring the device.
2773          *
2774          * indirect_lock: Held when accessing registers indirectly
2775          *                with IRQ disabling.
2776          */
2777         spinlock_t                      lock;
2778         spinlock_t                      indirect_lock;
2779
2780         u32                             (*read32) (struct tg3 *, u32);
2781         void                            (*write32) (struct tg3 *, u32, u32);
2782         u32                             (*read32_mbox) (struct tg3 *, u32);
2783         void                            (*write32_mbox) (struct tg3 *, u32,
2784                                                          u32);
2785         void __iomem                    *regs;
2786         void __iomem                    *aperegs;
2787         struct net_device               *dev;
2788         struct pci_dev                  *pdev;
2789
2790         u32                             coal_now;
2791         u32                             msg_enable;
2792
2793         /* begin "tx thread" cacheline section */
2794         void                            (*write32_tx_mbox) (struct tg3 *, u32,
2795                                                             u32);
2796
2797         /* begin "rx thread" cacheline section */
2798         struct tg3_napi                 napi[TG3_IRQ_MAX_VECS];
2799         void                            (*write32_rx_mbox) (struct tg3 *, u32,
2800                                                             u32);
2801         u32                             rx_copy_thresh;
2802         u32                             rx_std_ring_mask;
2803         u32                             rx_jmb_ring_mask;
2804         u32                             rx_ret_ring_mask;
2805         u32                             rx_pending;
2806         u32                             rx_jumbo_pending;
2807         u32                             rx_std_max_post;
2808         u32                             rx_offset;
2809         u32                             rx_pkt_map_sz;
2810 #if TG3_VLAN_TAG_USED
2811         struct vlan_group               *vlgrp;
2812 #endif
2813
2814
2815         /* begin "everything else" cacheline(s) section */
2816         unsigned long                   rx_dropped;
2817         struct rtnl_link_stats64        net_stats_prev;
2818         struct tg3_ethtool_stats        estats;
2819         struct tg3_ethtool_stats        estats_prev;
2820
2821         union {
2822         unsigned long                   phy_crc_errors;
2823         unsigned long                   last_event_jiffies;
2824         };
2825
2826         u32                             tg3_flags;
2827 #define TG3_FLAG_TAGGED_STATUS          0x00000001
2828 #define TG3_FLAG_TXD_MBOX_HWBUG         0x00000002
2829 #define TG3_FLAG_RX_CHECKSUMS           0x00000004
2830 #define TG3_FLAG_USE_LINKCHG_REG        0x00000008
2831 #define TG3_FLAG_ENABLE_ASF             0x00000020
2832 #define TG3_FLAG_ASPM_WORKAROUND        0x00000040
2833 #define TG3_FLAG_POLL_SERDES            0x00000080
2834 #define TG3_FLAG_MBOX_WRITE_REORDER     0x00000100
2835 #define TG3_FLAG_PCIX_TARGET_HWBUG      0x00000200
2836 #define TG3_FLAG_WOL_SPEED_100MB        0x00000400
2837 #define TG3_FLAG_WOL_ENABLE             0x00000800
2838 #define TG3_FLAG_EEPROM_WRITE_PROT      0x00001000
2839 #define TG3_FLAG_NVRAM                  0x00002000
2840 #define TG3_FLAG_NVRAM_BUFFERED         0x00004000
2841 #define TG3_FLAG_SUPPORT_MSI            0x00008000
2842 #define TG3_FLAG_SUPPORT_MSIX           0x00010000
2843 #define TG3_FLAG_SUPPORT_MSI_OR_MSIX    (TG3_FLAG_SUPPORT_MSI | \
2844                                          TG3_FLAG_SUPPORT_MSIX)
2845 #define TG3_FLAG_PCIX_MODE              0x00020000
2846 #define TG3_FLAG_PCI_HIGH_SPEED         0x00040000
2847 #define TG3_FLAG_PCI_32BIT              0x00080000
2848 #define TG3_FLAG_SRAM_USE_CONFIG        0x00100000
2849 #define TG3_FLAG_TX_RECOVERY_PENDING    0x00200000
2850 #define TG3_FLAG_WOL_CAP                0x00400000
2851 #define TG3_FLAG_JUMBO_RING_ENABLE      0x00800000
2852 #define TG3_FLAG_PAUSE_AUTONEG          0x02000000
2853 #define TG3_FLAG_CPMU_PRESENT           0x04000000
2854 #define TG3_FLAG_40BIT_DMA_BUG          0x08000000
2855 #define TG3_FLAG_BROKEN_CHECKSUMS       0x10000000
2856 #define TG3_FLAG_JUMBO_CAPABLE          0x20000000
2857 #define TG3_FLAG_CHIP_RESETTING         0x40000000
2858 #define TG3_FLAG_INIT_COMPLETE          0x80000000
2859         u32                             tg3_flags2;
2860 #define TG3_FLG2_RESTART_TIMER          0x00000001
2861 #define TG3_FLG2_TSO_BUG                0x00000002
2862 #define TG3_FLG2_IS_5788                0x00000008
2863 #define TG3_FLG2_MAX_RXPEND_64          0x00000010
2864 #define TG3_FLG2_TSO_CAPABLE            0x00000020
2865 #define TG3_FLG2_PCI_EXPRESS            0x00000200
2866 #define TG3_FLG2_ASF_NEW_HANDSHAKE      0x00000400
2867 #define TG3_FLG2_HW_AUTONEG             0x00000800
2868 #define TG3_FLG2_IS_NIC                 0x00001000
2869 #define TG3_FLG2_FLASH                  0x00008000
2870 #define TG3_FLG2_HW_TSO_1               0x00010000
2871 #define TG3_FLG2_5705_PLUS              0x00040000
2872 #define TG3_FLG2_5750_PLUS              0x00080000
2873 #define TG3_FLG2_HW_TSO_3               0x00100000
2874 #define TG3_FLG2_USING_MSI              0x00200000
2875 #define TG3_FLG2_USING_MSIX             0x00400000
2876 #define TG3_FLG2_USING_MSI_OR_MSIX      (TG3_FLG2_USING_MSI | \
2877                                         TG3_FLG2_USING_MSIX)
2878 #define TG3_FLG2_ICH_WORKAROUND         0x02000000
2879 #define TG3_FLG2_5780_CLASS             0x04000000
2880 #define TG3_FLG2_HW_TSO_2               0x08000000
2881 #define TG3_FLG2_HW_TSO                 (TG3_FLG2_HW_TSO_1 | \
2882                                          TG3_FLG2_HW_TSO_2 | \
2883                                          TG3_FLG2_HW_TSO_3)
2884 #define TG3_FLG2_1SHOT_MSI              0x10000000
2885 #define TG3_FLG2_NO_FWARE_REPORTED      0x40000000
2886         u32                             tg3_flags3;
2887 #define TG3_FLG3_NO_NVRAM_ADDR_TRANS    0x00000001
2888 #define TG3_FLG3_ENABLE_APE             0x00000002
2889 #define TG3_FLG3_PROTECTED_NVRAM        0x00000004
2890 #define TG3_FLG3_5701_DMA_BUG           0x00000008
2891 #define TG3_FLG3_USE_PHYLIB             0x00000010
2892 #define TG3_FLG3_MDIOBUS_INITED         0x00000020
2893 #define TG3_FLG3_RGMII_INBAND_DISABLE   0x00000100
2894 #define TG3_FLG3_RGMII_EXT_IBND_RX_EN   0x00000200
2895 #define TG3_FLG3_RGMII_EXT_IBND_TX_EN   0x00000400
2896 #define TG3_FLG3_CLKREQ_BUG             0x00000800
2897 #define TG3_FLG3_5755_PLUS              0x00002000
2898 #define TG3_FLG3_NO_NVRAM               0x00004000
2899 #define TG3_FLG3_ENABLE_RSS             0x00020000
2900 #define TG3_FLG3_ENABLE_TSS             0x00040000
2901 #define TG3_FLG3_4G_DMA_BNDRY_BUG       0x00080000
2902 #define TG3_FLG3_40BIT_DMA_LIMIT_BUG    0x00100000
2903 #define TG3_FLG3_SHORT_DMA_BUG          0x00200000
2904 #define TG3_FLG3_USE_JUMBO_BDFLAG       0x00400000
2905 #define TG3_FLG3_L1PLLPD_EN             0x00800000
2906 #define TG3_FLG3_5717_PLUS              0x01000000
2907 #define TG3_FLG3_APE_HAS_NCSI           0x02000000
2908
2909         struct timer_list               timer;
2910         u16                             timer_counter;
2911         u16                             timer_multiplier;
2912         u32                             timer_offset;
2913         u16                             asf_counter;
2914         u16                             asf_multiplier;
2915
2916         /* 1 second counter for transient serdes link events */
2917         u32                             serdes_counter;
2918 #define SERDES_AN_TIMEOUT_5704S         2
2919 #define SERDES_PARALLEL_DET_TIMEOUT     1
2920 #define SERDES_AN_TIMEOUT_5714S         1
2921
2922         struct tg3_link_config          link_config;
2923         struct tg3_bufmgr_config        bufmgr_config;
2924
2925         /* cache h/w values, often passed straight to h/w */
2926         u32                             rx_mode;
2927         u32                             tx_mode;
2928         u32                             mac_mode;
2929         u32                             mi_mode;
2930         u32                             misc_host_ctrl;
2931         u32                             grc_mode;
2932         u32                             grc_local_ctrl;
2933         u32                             dma_rwctrl;
2934         u32                             coalesce_mode;
2935         u32                             pwrmgmt_thresh;
2936
2937         /* PCI block */
2938         u32                             pci_chip_rev_id;
2939         u16                             pci_cmd;
2940         u8                              pci_cacheline_sz;
2941         u8                              pci_lat_timer;
2942
2943         int                             pm_cap;
2944         int                             msi_cap;
2945         union {
2946         int                             pcix_cap;
2947         int                             pcie_cap;
2948         };
2949
2950         struct mii_bus                  *mdio_bus;
2951         int                             mdio_irq[PHY_MAX_ADDR];
2952
2953         u8                              phy_addr;
2954
2955         /* PHY info */
2956         u32                             phy_id;
2957 #define TG3_PHY_ID_MASK                 0xfffffff0
2958 #define TG3_PHY_ID_BCM5400              0x60008040
2959 #define TG3_PHY_ID_BCM5401              0x60008050
2960 #define TG3_PHY_ID_BCM5411              0x60008070
2961 #define TG3_PHY_ID_BCM5701              0x60008110
2962 #define TG3_PHY_ID_BCM5703              0x60008160
2963 #define TG3_PHY_ID_BCM5704              0x60008190
2964 #define TG3_PHY_ID_BCM5705              0x600081a0
2965 #define TG3_PHY_ID_BCM5750              0x60008180
2966 #define TG3_PHY_ID_BCM5752              0x60008100
2967 #define TG3_PHY_ID_BCM5714              0x60008340
2968 #define TG3_PHY_ID_BCM5780              0x60008350
2969 #define TG3_PHY_ID_BCM5755              0xbc050cc0
2970 #define TG3_PHY_ID_BCM5787              0xbc050ce0
2971 #define TG3_PHY_ID_BCM5756              0xbc050ed0
2972 #define TG3_PHY_ID_BCM5784              0xbc050fa0
2973 #define TG3_PHY_ID_BCM5761              0xbc050fd0
2974 #define TG3_PHY_ID_BCM5718C             0x5c0d8a00
2975 #define TG3_PHY_ID_BCM5718S             0xbc050ff0
2976 #define TG3_PHY_ID_BCM57765             0x5c0d8a40
2977 #define TG3_PHY_ID_BCM5719C             0x5c0d8a20
2978 #define TG3_PHY_ID_BCM5906              0xdc00ac40
2979 #define TG3_PHY_ID_BCM8002              0x60010140
2980 #define TG3_PHY_ID_INVALID              0xffffffff
2981
2982 #define PHY_ID_RTL8211C                 0x001cc910
2983 #define PHY_ID_RTL8201E                 0x00008200
2984
2985 #define TG3_PHY_ID_REV_MASK             0x0000000f
2986 #define TG3_PHY_REV_BCM5401_B0          0x1
2987
2988         /* This macro assumes the passed PHY ID is
2989          * already masked with TG3_PHY_ID_MASK.
2990          */
2991 #define TG3_KNOWN_PHY_ID(X)             \
2992         ((X) == TG3_PHY_ID_BCM5400 || (X) == TG3_PHY_ID_BCM5401 || \
2993          (X) == TG3_PHY_ID_BCM5411 || (X) == TG3_PHY_ID_BCM5701 || \
2994          (X) == TG3_PHY_ID_BCM5703 || (X) == TG3_PHY_ID_BCM5704 || \
2995          (X) == TG3_PHY_ID_BCM5705 || (X) == TG3_PHY_ID_BCM5750 || \
2996          (X) == TG3_PHY_ID_BCM5752 || (X) == TG3_PHY_ID_BCM5714 || \
2997          (X) == TG3_PHY_ID_BCM5780 || (X) == TG3_PHY_ID_BCM5787 || \
2998          (X) == TG3_PHY_ID_BCM5755 || (X) == TG3_PHY_ID_BCM5756 || \
2999          (X) == TG3_PHY_ID_BCM5906 || (X) == TG3_PHY_ID_BCM5761 || \
3000          (X) == TG3_PHY_ID_BCM5718C || (X) == TG3_PHY_ID_BCM5718S || \
3001          (X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM5719C || \
3002          (X) == TG3_PHY_ID_BCM8002)
3003
3004         u32                             phy_flags;
3005 #define TG3_PHYFLG_IS_LOW_POWER         0x00000001
3006 #define TG3_PHYFLG_IS_CONNECTED         0x00000002
3007 #define TG3_PHYFLG_USE_MI_INTERRUPT     0x00000004
3008 #define TG3_PHYFLG_PHY_SERDES           0x00000010
3009 #define TG3_PHYFLG_MII_SERDES           0x00000020
3010 #define TG3_PHYFLG_ANY_SERDES           (TG3_PHYFLG_PHY_SERDES |        \
3011                                         TG3_PHYFLG_MII_SERDES)
3012 #define TG3_PHYFLG_IS_FET               0x00000040
3013 #define TG3_PHYFLG_10_100_ONLY          0x00000080
3014 #define TG3_PHYFLG_ENABLE_APD           0x00000100
3015 #define TG3_PHYFLG_CAPACITIVE_COUPLING  0x00000200
3016 #define TG3_PHYFLG_NO_ETH_WIRE_SPEED    0x00000400
3017 #define TG3_PHYFLG_JITTER_BUG           0x00000800
3018 #define TG3_PHYFLG_ADJUST_TRIM          0x00001000
3019 #define TG3_PHYFLG_ADC_BUG              0x00002000
3020 #define TG3_PHYFLG_5704_A0_BUG          0x00004000
3021 #define TG3_PHYFLG_BER_BUG              0x00008000
3022 #define TG3_PHYFLG_SERDES_PREEMPHASIS   0x00010000
3023 #define TG3_PHYFLG_PARALLEL_DETECT      0x00020000
3024 #define TG3_PHYFLG_EEE_CAP              0x00040000
3025
3026         u32                             led_ctrl;
3027         u32                             phy_otp;
3028         u32                             setlpicnt;
3029
3030 #define TG3_BPN_SIZE                    24
3031         char                            board_part_number[TG3_BPN_SIZE];
3032 #define TG3_VER_SIZE                    ETHTOOL_FWVERS_LEN
3033         char                            fw_ver[TG3_VER_SIZE];
3034         u32                             nic_sram_data_cfg;
3035         u32                             pci_clock_ctrl;
3036         struct pci_dev                  *pdev_peer;
3037
3038         struct tg3_hw_stats             *hw_stats;
3039         dma_addr_t                      stats_mapping;
3040         struct work_struct              reset_task;
3041
3042         int                             nvram_lock_cnt;
3043         u32                             nvram_size;
3044 #define TG3_NVRAM_SIZE_64KB             0x00010000
3045 #define TG3_NVRAM_SIZE_128KB            0x00020000
3046 #define TG3_NVRAM_SIZE_256KB            0x00040000
3047 #define TG3_NVRAM_SIZE_512KB            0x00080000
3048 #define TG3_NVRAM_SIZE_1MB              0x00100000
3049 #define TG3_NVRAM_SIZE_2MB              0x00200000
3050
3051         u32                             nvram_pagesize;
3052         u32                             nvram_jedecnum;
3053
3054 #define JEDEC_ATMEL                     0x1f
3055 #define JEDEC_ST                        0x20
3056 #define JEDEC_SAIFUN                    0x4f
3057 #define JEDEC_SST                       0xbf
3058
3059 #define ATMEL_AT24C64_CHIP_SIZE         TG3_NVRAM_SIZE_64KB
3060 #define ATMEL_AT24C64_PAGE_SIZE         (32)
3061
3062 #define ATMEL_AT24C512_CHIP_SIZE        TG3_NVRAM_SIZE_512KB
3063 #define ATMEL_AT24C512_PAGE_SIZE        (128)
3064
3065 #define ATMEL_AT45DB0X1B_PAGE_POS       9
3066 #define ATMEL_AT45DB0X1B_PAGE_SIZE      264
3067
3068 #define ATMEL_AT25F512_PAGE_SIZE        256
3069
3070 #define ST_M45PEX0_PAGE_SIZE            256
3071
3072 #define SAIFUN_SA25F0XX_PAGE_SIZE       256
3073
3074 #define SST_25VF0X0_PAGE_SIZE           4098
3075
3076         unsigned int                    irq_max;
3077         unsigned int                    irq_cnt;
3078
3079         struct ethtool_coalesce         coal;
3080
3081         /* firmware info */
3082         const char                      *fw_needed;
3083         const struct firmware           *fw;
3084         u32                             fw_len; /* includes BSS */
3085 };
3086
3087 #endif /* !(_T3_H) */