[netdrvr] Trim trailing whitespace for several drivers
[linux-2.6.git] / drivers / net / tg3.h
1 /* $Id: tg3.h,v 1.37.2.32 2002/03/11 12:18:18 davem Exp $
2  * tg3.h: Definitions for Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  */
8
9 #ifndef _T3_H
10 #define _T3_H
11
12 #define TG3_64BIT_REG_HIGH              0x00UL
13 #define TG3_64BIT_REG_LOW               0x04UL
14
15 /* Descriptor block info. */
16 #define TG3_BDINFO_HOST_ADDR            0x0UL /* 64-bit */
17 #define TG3_BDINFO_MAXLEN_FLAGS         0x8UL /* 32-bit */
18 #define  BDINFO_FLAGS_USE_EXT_RECV       0x00000001 /* ext rx_buffer_desc */
19 #define  BDINFO_FLAGS_DISABLED           0x00000002
20 #define  BDINFO_FLAGS_MAXLEN_MASK        0xffff0000
21 #define  BDINFO_FLAGS_MAXLEN_SHIFT       16
22 #define TG3_BDINFO_NIC_ADDR             0xcUL /* 32-bit */
23 #define TG3_BDINFO_SIZE                 0x10UL
24
25 #define RX_COPY_THRESHOLD               256
26
27 #define TG3_RX_INTERNAL_RING_SZ_5906    32
28
29 #define RX_STD_MAX_SIZE                 1536
30 #define RX_STD_MAX_SIZE_5705            512
31 #define RX_JUMBO_MAX_SIZE               0xdeadbeef /* XXX */
32
33 /* First 256 bytes are a mirror of PCI config space. */
34 #define TG3PCI_VENDOR                   0x00000000
35 #define  TG3PCI_VENDOR_BROADCOM          0x14e4
36 #define TG3PCI_DEVICE                   0x00000002
37 #define  TG3PCI_DEVICE_TIGON3_1          0x1644 /* BCM5700 */
38 #define  TG3PCI_DEVICE_TIGON3_2          0x1645 /* BCM5701 */
39 #define  TG3PCI_DEVICE_TIGON3_3          0x1646 /* BCM5702 */
40 #define  TG3PCI_DEVICE_TIGON3_4          0x1647 /* BCM5703 */
41 #define TG3PCI_COMMAND                  0x00000004
42 #define TG3PCI_STATUS                   0x00000006
43 #define TG3PCI_CCREVID                  0x00000008
44 #define TG3PCI_CACHELINESZ              0x0000000c
45 #define TG3PCI_LATTIMER                 0x0000000d
46 #define TG3PCI_HEADERTYPE               0x0000000e
47 #define TG3PCI_BIST                     0x0000000f
48 #define TG3PCI_BASE0_LOW                0x00000010
49 #define TG3PCI_BASE0_HIGH               0x00000014
50 /* 0x18 --> 0x2c unused */
51 #define TG3PCI_SUBSYSVENID              0x0000002c
52 #define TG3PCI_SUBSYSID                 0x0000002e
53 #define TG3PCI_ROMADDR                  0x00000030
54 #define TG3PCI_CAPLIST                  0x00000034
55 /* 0x35 --> 0x3c unused */
56 #define TG3PCI_IRQ_LINE                 0x0000003c
57 #define TG3PCI_IRQ_PIN                  0x0000003d
58 #define TG3PCI_MIN_GNT                  0x0000003e
59 #define TG3PCI_MAX_LAT                  0x0000003f
60 /* 0x40 --> 0x64 unused */
61 #define TG3PCI_MSI_DATA                 0x00000064
62 /* 0x66 --> 0x68 unused */
63 #define TG3PCI_MISC_HOST_CTRL           0x00000068
64 #define  MISC_HOST_CTRL_CLEAR_INT        0x00000001
65 #define  MISC_HOST_CTRL_MASK_PCI_INT     0x00000002
66 #define  MISC_HOST_CTRL_BYTE_SWAP        0x00000004
67 #define  MISC_HOST_CTRL_WORD_SWAP        0x00000008
68 #define  MISC_HOST_CTRL_PCISTATE_RW      0x00000010
69 #define  MISC_HOST_CTRL_CLKREG_RW        0x00000020
70 #define  MISC_HOST_CTRL_REGWORD_SWAP     0x00000040
71 #define  MISC_HOST_CTRL_INDIR_ACCESS     0x00000080
72 #define  MISC_HOST_CTRL_IRQ_MASK_MODE    0x00000100
73 #define  MISC_HOST_CTRL_TAGGED_STATUS    0x00000200
74 #define  MISC_HOST_CTRL_CHIPREV          0xffff0000
75 #define  MISC_HOST_CTRL_CHIPREV_SHIFT    16
76 #define  GET_CHIP_REV_ID(MISC_HOST_CTRL) \
77          (((MISC_HOST_CTRL) & MISC_HOST_CTRL_CHIPREV) >> \
78           MISC_HOST_CTRL_CHIPREV_SHIFT)
79 #define  CHIPREV_ID_5700_A0              0x7000
80 #define  CHIPREV_ID_5700_A1              0x7001
81 #define  CHIPREV_ID_5700_B0              0x7100
82 #define  CHIPREV_ID_5700_B1              0x7101
83 #define  CHIPREV_ID_5700_B3              0x7102
84 #define  CHIPREV_ID_5700_ALTIMA          0x7104
85 #define  CHIPREV_ID_5700_C0              0x7200
86 #define  CHIPREV_ID_5701_A0              0x0000
87 #define  CHIPREV_ID_5701_B0              0x0100
88 #define  CHIPREV_ID_5701_B2              0x0102
89 #define  CHIPREV_ID_5701_B5              0x0105
90 #define  CHIPREV_ID_5703_A0              0x1000
91 #define  CHIPREV_ID_5703_A1              0x1001
92 #define  CHIPREV_ID_5703_A2              0x1002
93 #define  CHIPREV_ID_5703_A3              0x1003
94 #define  CHIPREV_ID_5704_A0              0x2000
95 #define  CHIPREV_ID_5704_A1              0x2001
96 #define  CHIPREV_ID_5704_A2              0x2002
97 #define  CHIPREV_ID_5704_A3              0x2003
98 #define  CHIPREV_ID_5705_A0              0x3000
99 #define  CHIPREV_ID_5705_A1              0x3001
100 #define  CHIPREV_ID_5705_A2              0x3002
101 #define  CHIPREV_ID_5705_A3              0x3003
102 #define  CHIPREV_ID_5750_A0              0x4000
103 #define  CHIPREV_ID_5750_A1              0x4001
104 #define  CHIPREV_ID_5750_A3              0x4003
105 #define  CHIPREV_ID_5750_C2              0x4202
106 #define  CHIPREV_ID_5752_A0_HW           0x5000
107 #define  CHIPREV_ID_5752_A0              0x6000
108 #define  CHIPREV_ID_5752_A1              0x6001
109 #define  CHIPREV_ID_5714_A2              0x9002
110 #define  CHIPREV_ID_5906_A1              0xc001
111 #define  CHIPREV_ID_5784_A0              0x5784000
112 #define  CHIPREV_ID_5784_A1              0x5784001
113 #define  CHIPREV_ID_5761_A0              0x5761000
114 #define  CHIPREV_ID_5761_A1              0x5761001
115 #define  GET_ASIC_REV(CHIP_REV_ID)      ((CHIP_REV_ID) >> 12)
116 #define   ASIC_REV_5700                  0x07
117 #define   ASIC_REV_5701                  0x00
118 #define   ASIC_REV_5703                  0x01
119 #define   ASIC_REV_5704                  0x02
120 #define   ASIC_REV_5705                  0x03
121 #define   ASIC_REV_5750                  0x04
122 #define   ASIC_REV_5752                  0x06
123 #define   ASIC_REV_5780                  0x08
124 #define   ASIC_REV_5714                  0x09
125 #define   ASIC_REV_5755                  0x0a
126 #define   ASIC_REV_5787                  0x0b
127 #define   ASIC_REV_5906                  0x0c
128 #define   ASIC_REV_USE_PROD_ID_REG       0x0f
129 #define   ASIC_REV_5784                  0x5784
130 #define   ASIC_REV_5761                  0x5761
131 #define  GET_CHIP_REV(CHIP_REV_ID)      ((CHIP_REV_ID) >> 8)
132 #define   CHIPREV_5700_AX                0x70
133 #define   CHIPREV_5700_BX                0x71
134 #define   CHIPREV_5700_CX                0x72
135 #define   CHIPREV_5701_AX                0x00
136 #define   CHIPREV_5703_AX                0x10
137 #define   CHIPREV_5704_AX                0x20
138 #define   CHIPREV_5704_BX                0x21
139 #define   CHIPREV_5750_AX                0x40
140 #define   CHIPREV_5750_BX                0x41
141 #define   CHIPREV_5784_AX                0x57840
142 #define   CHIPREV_5761_AX                0x57610
143 #define  GET_METAL_REV(CHIP_REV_ID)     ((CHIP_REV_ID) & 0xff)
144 #define   METAL_REV_A0                   0x00
145 #define   METAL_REV_A1                   0x01
146 #define   METAL_REV_B0                   0x00
147 #define   METAL_REV_B1                   0x01
148 #define   METAL_REV_B2                   0x02
149 #define TG3PCI_DMA_RW_CTRL              0x0000006c
150 #define  DMA_RWCTRL_MIN_DMA              0x000000ff
151 #define  DMA_RWCTRL_MIN_DMA_SHIFT        0
152 #define  DMA_RWCTRL_READ_BNDRY_MASK      0x00000700
153 #define  DMA_RWCTRL_READ_BNDRY_DISAB     0x00000000
154 #define  DMA_RWCTRL_READ_BNDRY_16        0x00000100
155 #define  DMA_RWCTRL_READ_BNDRY_128_PCIX  0x00000100
156 #define  DMA_RWCTRL_READ_BNDRY_32        0x00000200
157 #define  DMA_RWCTRL_READ_BNDRY_256_PCIX  0x00000200
158 #define  DMA_RWCTRL_READ_BNDRY_64        0x00000300
159 #define  DMA_RWCTRL_READ_BNDRY_384_PCIX  0x00000300
160 #define  DMA_RWCTRL_READ_BNDRY_128       0x00000400
161 #define  DMA_RWCTRL_READ_BNDRY_256       0x00000500
162 #define  DMA_RWCTRL_READ_BNDRY_512       0x00000600
163 #define  DMA_RWCTRL_READ_BNDRY_1024      0x00000700
164 #define  DMA_RWCTRL_WRITE_BNDRY_MASK     0x00003800
165 #define  DMA_RWCTRL_WRITE_BNDRY_DISAB    0x00000000
166 #define  DMA_RWCTRL_WRITE_BNDRY_16       0x00000800
167 #define  DMA_RWCTRL_WRITE_BNDRY_128_PCIX 0x00000800
168 #define  DMA_RWCTRL_WRITE_BNDRY_32       0x00001000
169 #define  DMA_RWCTRL_WRITE_BNDRY_256_PCIX 0x00001000
170 #define  DMA_RWCTRL_WRITE_BNDRY_64       0x00001800
171 #define  DMA_RWCTRL_WRITE_BNDRY_384_PCIX 0x00001800
172 #define  DMA_RWCTRL_WRITE_BNDRY_128      0x00002000
173 #define  DMA_RWCTRL_WRITE_BNDRY_256      0x00002800
174 #define  DMA_RWCTRL_WRITE_BNDRY_512      0x00003000
175 #define  DMA_RWCTRL_WRITE_BNDRY_1024     0x00003800
176 #define  DMA_RWCTRL_ONE_DMA              0x00004000
177 #define  DMA_RWCTRL_READ_WATER           0x00070000
178 #define  DMA_RWCTRL_READ_WATER_SHIFT     16
179 #define  DMA_RWCTRL_WRITE_WATER          0x00380000
180 #define  DMA_RWCTRL_WRITE_WATER_SHIFT    19
181 #define  DMA_RWCTRL_USE_MEM_READ_MULT    0x00400000
182 #define  DMA_RWCTRL_ASSERT_ALL_BE        0x00800000
183 #define  DMA_RWCTRL_PCI_READ_CMD         0x0f000000
184 #define  DMA_RWCTRL_PCI_READ_CMD_SHIFT   24
185 #define  DMA_RWCTRL_PCI_WRITE_CMD        0xf0000000
186 #define  DMA_RWCTRL_PCI_WRITE_CMD_SHIFT  28
187 #define  DMA_RWCTRL_WRITE_BNDRY_64_PCIE  0x10000000
188 #define  DMA_RWCTRL_WRITE_BNDRY_128_PCIE 0x30000000
189 #define  DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE 0x70000000
190 #define TG3PCI_PCISTATE                 0x00000070
191 #define  PCISTATE_FORCE_RESET            0x00000001
192 #define  PCISTATE_INT_NOT_ACTIVE         0x00000002
193 #define  PCISTATE_CONV_PCI_MODE          0x00000004
194 #define  PCISTATE_BUS_SPEED_HIGH         0x00000008
195 #define  PCISTATE_BUS_32BIT              0x00000010
196 #define  PCISTATE_ROM_ENABLE             0x00000020
197 #define  PCISTATE_ROM_RETRY_ENABLE       0x00000040
198 #define  PCISTATE_FLAT_VIEW              0x00000100
199 #define  PCISTATE_RETRY_SAME_DMA         0x00002000
200 #define  PCISTATE_ALLOW_APE_CTLSPC_WR    0x00010000
201 #define  PCISTATE_ALLOW_APE_SHMEM_WR     0x00020000
202 #define TG3PCI_CLOCK_CTRL               0x00000074
203 #define  CLOCK_CTRL_CORECLK_DISABLE      0x00000200
204 #define  CLOCK_CTRL_RXCLK_DISABLE        0x00000400
205 #define  CLOCK_CTRL_TXCLK_DISABLE        0x00000800
206 #define  CLOCK_CTRL_ALTCLK               0x00001000
207 #define  CLOCK_CTRL_PWRDOWN_PLL133       0x00008000
208 #define  CLOCK_CTRL_44MHZ_CORE           0x00040000
209 #define  CLOCK_CTRL_625_CORE             0x00100000
210 #define  CLOCK_CTRL_FORCE_CLKRUN         0x00200000
211 #define  CLOCK_CTRL_CLKRUN_OENABLE       0x00400000
212 #define  CLOCK_CTRL_DELAY_PCI_GRANT      0x80000000
213 #define TG3PCI_REG_BASE_ADDR            0x00000078
214 #define TG3PCI_MEM_WIN_BASE_ADDR        0x0000007c
215 #define TG3PCI_REG_DATA                 0x00000080
216 #define TG3PCI_MEM_WIN_DATA             0x00000084
217 #define TG3PCI_MODE_CTRL                0x00000088
218 #define TG3PCI_MISC_CFG                 0x0000008c
219 #define TG3PCI_MISC_LOCAL_CTRL          0x00000090
220 /* 0x94 --> 0x98 unused */
221 #define TG3PCI_STD_RING_PROD_IDX        0x00000098 /* 64-bit */
222 #define TG3PCI_RCV_RET_RING_CON_IDX     0x000000a0 /* 64-bit */
223 #define TG3PCI_SND_PROD_IDX             0x000000a8 /* 64-bit */
224 /* 0xb0 --> 0xb8 unused */
225 #define TG3PCI_DUAL_MAC_CTRL            0x000000b8
226 #define  DUAL_MAC_CTRL_CH_MASK           0x00000003
227 #define  DUAL_MAC_CTRL_ID                0x00000004
228 #define TG3PCI_PRODID_ASICREV           0x000000bc
229 #define  PROD_ID_ASIC_REV_MASK           0x0fffffff
230 /* 0xc0 --> 0x100 unused */
231
232 /* 0x100 --> 0x200 unused */
233
234 /* Mailbox registers */
235 #define MAILBOX_INTERRUPT_0             0x00000200 /* 64-bit */
236 #define MAILBOX_INTERRUPT_1             0x00000208 /* 64-bit */
237 #define MAILBOX_INTERRUPT_2             0x00000210 /* 64-bit */
238 #define MAILBOX_INTERRUPT_3             0x00000218 /* 64-bit */
239 #define MAILBOX_GENERAL_0               0x00000220 /* 64-bit */
240 #define MAILBOX_GENERAL_1               0x00000228 /* 64-bit */
241 #define MAILBOX_GENERAL_2               0x00000230 /* 64-bit */
242 #define MAILBOX_GENERAL_3               0x00000238 /* 64-bit */
243 #define MAILBOX_GENERAL_4               0x00000240 /* 64-bit */
244 #define MAILBOX_GENERAL_5               0x00000248 /* 64-bit */
245 #define MAILBOX_GENERAL_6               0x00000250 /* 64-bit */
246 #define MAILBOX_GENERAL_7               0x00000258 /* 64-bit */
247 #define MAILBOX_RELOAD_STAT             0x00000260 /* 64-bit */
248 #define MAILBOX_RCV_STD_PROD_IDX        0x00000268 /* 64-bit */
249 #define MAILBOX_RCV_JUMBO_PROD_IDX      0x00000270 /* 64-bit */
250 #define MAILBOX_RCV_MINI_PROD_IDX       0x00000278 /* 64-bit */
251 #define MAILBOX_RCVRET_CON_IDX_0        0x00000280 /* 64-bit */
252 #define MAILBOX_RCVRET_CON_IDX_1        0x00000288 /* 64-bit */
253 #define MAILBOX_RCVRET_CON_IDX_2        0x00000290 /* 64-bit */
254 #define MAILBOX_RCVRET_CON_IDX_3        0x00000298 /* 64-bit */
255 #define MAILBOX_RCVRET_CON_IDX_4        0x000002a0 /* 64-bit */
256 #define MAILBOX_RCVRET_CON_IDX_5        0x000002a8 /* 64-bit */
257 #define MAILBOX_RCVRET_CON_IDX_6        0x000002b0 /* 64-bit */
258 #define MAILBOX_RCVRET_CON_IDX_7        0x000002b8 /* 64-bit */
259 #define MAILBOX_RCVRET_CON_IDX_8        0x000002c0 /* 64-bit */
260 #define MAILBOX_RCVRET_CON_IDX_9        0x000002c8 /* 64-bit */
261 #define MAILBOX_RCVRET_CON_IDX_10       0x000002d0 /* 64-bit */
262 #define MAILBOX_RCVRET_CON_IDX_11       0x000002d8 /* 64-bit */
263 #define MAILBOX_RCVRET_CON_IDX_12       0x000002e0 /* 64-bit */
264 #define MAILBOX_RCVRET_CON_IDX_13       0x000002e8 /* 64-bit */
265 #define MAILBOX_RCVRET_CON_IDX_14       0x000002f0 /* 64-bit */
266 #define MAILBOX_RCVRET_CON_IDX_15       0x000002f8 /* 64-bit */
267 #define MAILBOX_SNDHOST_PROD_IDX_0      0x00000300 /* 64-bit */
268 #define MAILBOX_SNDHOST_PROD_IDX_1      0x00000308 /* 64-bit */
269 #define MAILBOX_SNDHOST_PROD_IDX_2      0x00000310 /* 64-bit */
270 #define MAILBOX_SNDHOST_PROD_IDX_3      0x00000318 /* 64-bit */
271 #define MAILBOX_SNDHOST_PROD_IDX_4      0x00000320 /* 64-bit */
272 #define MAILBOX_SNDHOST_PROD_IDX_5      0x00000328 /* 64-bit */
273 #define MAILBOX_SNDHOST_PROD_IDX_6      0x00000330 /* 64-bit */
274 #define MAILBOX_SNDHOST_PROD_IDX_7      0x00000338 /* 64-bit */
275 #define MAILBOX_SNDHOST_PROD_IDX_8      0x00000340 /* 64-bit */
276 #define MAILBOX_SNDHOST_PROD_IDX_9      0x00000348 /* 64-bit */
277 #define MAILBOX_SNDHOST_PROD_IDX_10     0x00000350 /* 64-bit */
278 #define MAILBOX_SNDHOST_PROD_IDX_11     0x00000358 /* 64-bit */
279 #define MAILBOX_SNDHOST_PROD_IDX_12     0x00000360 /* 64-bit */
280 #define MAILBOX_SNDHOST_PROD_IDX_13     0x00000368 /* 64-bit */
281 #define MAILBOX_SNDHOST_PROD_IDX_14     0x00000370 /* 64-bit */
282 #define MAILBOX_SNDHOST_PROD_IDX_15     0x00000378 /* 64-bit */
283 #define MAILBOX_SNDNIC_PROD_IDX_0       0x00000380 /* 64-bit */
284 #define MAILBOX_SNDNIC_PROD_IDX_1       0x00000388 /* 64-bit */
285 #define MAILBOX_SNDNIC_PROD_IDX_2       0x00000390 /* 64-bit */
286 #define MAILBOX_SNDNIC_PROD_IDX_3       0x00000398 /* 64-bit */
287 #define MAILBOX_SNDNIC_PROD_IDX_4       0x000003a0 /* 64-bit */
288 #define MAILBOX_SNDNIC_PROD_IDX_5       0x000003a8 /* 64-bit */
289 #define MAILBOX_SNDNIC_PROD_IDX_6       0x000003b0 /* 64-bit */
290 #define MAILBOX_SNDNIC_PROD_IDX_7       0x000003b8 /* 64-bit */
291 #define MAILBOX_SNDNIC_PROD_IDX_8       0x000003c0 /* 64-bit */
292 #define MAILBOX_SNDNIC_PROD_IDX_9       0x000003c8 /* 64-bit */
293 #define MAILBOX_SNDNIC_PROD_IDX_10      0x000003d0 /* 64-bit */
294 #define MAILBOX_SNDNIC_PROD_IDX_11      0x000003d8 /* 64-bit */
295 #define MAILBOX_SNDNIC_PROD_IDX_12      0x000003e0 /* 64-bit */
296 #define MAILBOX_SNDNIC_PROD_IDX_13      0x000003e8 /* 64-bit */
297 #define MAILBOX_SNDNIC_PROD_IDX_14      0x000003f0 /* 64-bit */
298 #define MAILBOX_SNDNIC_PROD_IDX_15      0x000003f8 /* 64-bit */
299
300 /* MAC control registers */
301 #define MAC_MODE                        0x00000400
302 #define  MAC_MODE_RESET                  0x00000001
303 #define  MAC_MODE_HALF_DUPLEX            0x00000002
304 #define  MAC_MODE_PORT_MODE_MASK         0x0000000c
305 #define  MAC_MODE_PORT_MODE_TBI          0x0000000c
306 #define  MAC_MODE_PORT_MODE_GMII         0x00000008
307 #define  MAC_MODE_PORT_MODE_MII          0x00000004
308 #define  MAC_MODE_PORT_MODE_NONE         0x00000000
309 #define  MAC_MODE_PORT_INT_LPBACK        0x00000010
310 #define  MAC_MODE_TAGGED_MAC_CTRL        0x00000080
311 #define  MAC_MODE_TX_BURSTING            0x00000100
312 #define  MAC_MODE_MAX_DEFER              0x00000200
313 #define  MAC_MODE_LINK_POLARITY          0x00000400
314 #define  MAC_MODE_RXSTAT_ENABLE          0x00000800
315 #define  MAC_MODE_RXSTAT_CLEAR           0x00001000
316 #define  MAC_MODE_RXSTAT_FLUSH           0x00002000
317 #define  MAC_MODE_TXSTAT_ENABLE          0x00004000
318 #define  MAC_MODE_TXSTAT_CLEAR           0x00008000
319 #define  MAC_MODE_TXSTAT_FLUSH           0x00010000
320 #define  MAC_MODE_SEND_CONFIGS           0x00020000
321 #define  MAC_MODE_MAGIC_PKT_ENABLE       0x00040000
322 #define  MAC_MODE_ACPI_ENABLE            0x00080000
323 #define  MAC_MODE_MIP_ENABLE             0x00100000
324 #define  MAC_MODE_TDE_ENABLE             0x00200000
325 #define  MAC_MODE_RDE_ENABLE             0x00400000
326 #define  MAC_MODE_FHDE_ENABLE            0x00800000
327 #define MAC_STATUS                      0x00000404
328 #define  MAC_STATUS_PCS_SYNCED           0x00000001
329 #define  MAC_STATUS_SIGNAL_DET           0x00000002
330 #define  MAC_STATUS_RCVD_CFG             0x00000004
331 #define  MAC_STATUS_CFG_CHANGED          0x00000008
332 #define  MAC_STATUS_SYNC_CHANGED         0x00000010
333 #define  MAC_STATUS_PORT_DEC_ERR         0x00000400
334 #define  MAC_STATUS_LNKSTATE_CHANGED     0x00001000
335 #define  MAC_STATUS_MI_COMPLETION        0x00400000
336 #define  MAC_STATUS_MI_INTERRUPT         0x00800000
337 #define  MAC_STATUS_AP_ERROR             0x01000000
338 #define  MAC_STATUS_ODI_ERROR            0x02000000
339 #define  MAC_STATUS_RXSTAT_OVERRUN       0x04000000
340 #define  MAC_STATUS_TXSTAT_OVERRUN       0x08000000
341 #define MAC_EVENT                       0x00000408
342 #define  MAC_EVENT_PORT_DECODE_ERR       0x00000400
343 #define  MAC_EVENT_LNKSTATE_CHANGED      0x00001000
344 #define  MAC_EVENT_MI_COMPLETION         0x00400000
345 #define  MAC_EVENT_MI_INTERRUPT          0x00800000
346 #define  MAC_EVENT_AP_ERROR              0x01000000
347 #define  MAC_EVENT_ODI_ERROR             0x02000000
348 #define  MAC_EVENT_RXSTAT_OVERRUN        0x04000000
349 #define  MAC_EVENT_TXSTAT_OVERRUN        0x08000000
350 #define MAC_LED_CTRL                    0x0000040c
351 #define  LED_CTRL_LNKLED_OVERRIDE        0x00000001
352 #define  LED_CTRL_1000MBPS_ON            0x00000002
353 #define  LED_CTRL_100MBPS_ON             0x00000004
354 #define  LED_CTRL_10MBPS_ON              0x00000008
355 #define  LED_CTRL_TRAFFIC_OVERRIDE       0x00000010
356 #define  LED_CTRL_TRAFFIC_BLINK          0x00000020
357 #define  LED_CTRL_TRAFFIC_LED            0x00000040
358 #define  LED_CTRL_1000MBPS_STATUS        0x00000080
359 #define  LED_CTRL_100MBPS_STATUS         0x00000100
360 #define  LED_CTRL_10MBPS_STATUS          0x00000200
361 #define  LED_CTRL_TRAFFIC_STATUS         0x00000400
362 #define  LED_CTRL_MODE_MAC               0x00000000
363 #define  LED_CTRL_MODE_PHY_1             0x00000800
364 #define  LED_CTRL_MODE_PHY_2             0x00001000
365 #define  LED_CTRL_MODE_SHASTA_MAC        0x00002000
366 #define  LED_CTRL_MODE_SHARED            0x00004000
367 #define  LED_CTRL_MODE_COMBO             0x00008000
368 #define  LED_CTRL_BLINK_RATE_MASK        0x7ff80000
369 #define  LED_CTRL_BLINK_RATE_SHIFT       19
370 #define  LED_CTRL_BLINK_PER_OVERRIDE     0x00080000
371 #define  LED_CTRL_BLINK_RATE_OVERRIDE    0x80000000
372 #define MAC_ADDR_0_HIGH                 0x00000410 /* upper 2 bytes */
373 #define MAC_ADDR_0_LOW                  0x00000414 /* lower 4 bytes */
374 #define MAC_ADDR_1_HIGH                 0x00000418 /* upper 2 bytes */
375 #define MAC_ADDR_1_LOW                  0x0000041c /* lower 4 bytes */
376 #define MAC_ADDR_2_HIGH                 0x00000420 /* upper 2 bytes */
377 #define MAC_ADDR_2_LOW                  0x00000424 /* lower 4 bytes */
378 #define MAC_ADDR_3_HIGH                 0x00000428 /* upper 2 bytes */
379 #define MAC_ADDR_3_LOW                  0x0000042c /* lower 4 bytes */
380 #define MAC_ACPI_MBUF_PTR               0x00000430
381 #define MAC_ACPI_LEN_OFFSET             0x00000434
382 #define  ACPI_LENOFF_LEN_MASK            0x0000ffff
383 #define  ACPI_LENOFF_LEN_SHIFT           0
384 #define  ACPI_LENOFF_OFF_MASK            0x0fff0000
385 #define  ACPI_LENOFF_OFF_SHIFT           16
386 #define MAC_TX_BACKOFF_SEED             0x00000438
387 #define  TX_BACKOFF_SEED_MASK            0x000003ff
388 #define MAC_RX_MTU_SIZE                 0x0000043c
389 #define  RX_MTU_SIZE_MASK                0x0000ffff
390 #define MAC_PCS_TEST                    0x00000440
391 #define  PCS_TEST_PATTERN_MASK           0x000fffff
392 #define  PCS_TEST_PATTERN_SHIFT          0
393 #define  PCS_TEST_ENABLE                 0x00100000
394 #define MAC_TX_AUTO_NEG                 0x00000444
395 #define  TX_AUTO_NEG_MASK                0x0000ffff
396 #define  TX_AUTO_NEG_SHIFT               0
397 #define MAC_RX_AUTO_NEG                 0x00000448
398 #define  RX_AUTO_NEG_MASK                0x0000ffff
399 #define  RX_AUTO_NEG_SHIFT               0
400 #define MAC_MI_COM                      0x0000044c
401 #define  MI_COM_CMD_MASK                 0x0c000000
402 #define  MI_COM_CMD_WRITE                0x04000000
403 #define  MI_COM_CMD_READ                 0x08000000
404 #define  MI_COM_READ_FAILED              0x10000000
405 #define  MI_COM_START                    0x20000000
406 #define  MI_COM_BUSY                     0x20000000
407 #define  MI_COM_PHY_ADDR_MASK            0x03e00000
408 #define  MI_COM_PHY_ADDR_SHIFT           21
409 #define  MI_COM_REG_ADDR_MASK            0x001f0000
410 #define  MI_COM_REG_ADDR_SHIFT           16
411 #define  MI_COM_DATA_MASK                0x0000ffff
412 #define MAC_MI_STAT                     0x00000450
413 #define  MAC_MI_STAT_LNKSTAT_ATTN_ENAB   0x00000001
414 #define MAC_MI_MODE                     0x00000454
415 #define  MAC_MI_MODE_CLK_10MHZ           0x00000001
416 #define  MAC_MI_MODE_SHORT_PREAMBLE      0x00000002
417 #define  MAC_MI_MODE_AUTO_POLL           0x00000010
418 #define  MAC_MI_MODE_500KHZ_CONST        0x00008000
419 #define  MAC_MI_MODE_BASE                0x000c0000 /* XXX magic values XXX */
420 #define MAC_AUTO_POLL_STATUS            0x00000458
421 #define  MAC_AUTO_POLL_ERROR             0x00000001
422 #define MAC_TX_MODE                     0x0000045c
423 #define  TX_MODE_RESET                   0x00000001
424 #define  TX_MODE_ENABLE                  0x00000002
425 #define  TX_MODE_FLOW_CTRL_ENABLE        0x00000010
426 #define  TX_MODE_BIG_BCKOFF_ENABLE       0x00000020
427 #define  TX_MODE_LONG_PAUSE_ENABLE       0x00000040
428 #define MAC_TX_STATUS                   0x00000460
429 #define  TX_STATUS_XOFFED                0x00000001
430 #define  TX_STATUS_SENT_XOFF             0x00000002
431 #define  TX_STATUS_SENT_XON              0x00000004
432 #define  TX_STATUS_LINK_UP               0x00000008
433 #define  TX_STATUS_ODI_UNDERRUN          0x00000010
434 #define  TX_STATUS_ODI_OVERRUN           0x00000020
435 #define MAC_TX_LENGTHS                  0x00000464
436 #define  TX_LENGTHS_SLOT_TIME_MASK       0x000000ff
437 #define  TX_LENGTHS_SLOT_TIME_SHIFT      0
438 #define  TX_LENGTHS_IPG_MASK             0x00000f00
439 #define  TX_LENGTHS_IPG_SHIFT            8
440 #define  TX_LENGTHS_IPG_CRS_MASK         0x00003000
441 #define  TX_LENGTHS_IPG_CRS_SHIFT        12
442 #define MAC_RX_MODE                     0x00000468
443 #define  RX_MODE_RESET                   0x00000001
444 #define  RX_MODE_ENABLE                  0x00000002
445 #define  RX_MODE_FLOW_CTRL_ENABLE        0x00000004
446 #define  RX_MODE_KEEP_MAC_CTRL           0x00000008
447 #define  RX_MODE_KEEP_PAUSE              0x00000010
448 #define  RX_MODE_ACCEPT_OVERSIZED        0x00000020
449 #define  RX_MODE_ACCEPT_RUNTS            0x00000040
450 #define  RX_MODE_LEN_CHECK               0x00000080
451 #define  RX_MODE_PROMISC                 0x00000100
452 #define  RX_MODE_NO_CRC_CHECK            0x00000200
453 #define  RX_MODE_KEEP_VLAN_TAG           0x00000400
454 #define  RX_MODE_IPV6_CSUM_ENABLE        0x01000000
455 #define MAC_RX_STATUS                   0x0000046c
456 #define  RX_STATUS_REMOTE_TX_XOFFED      0x00000001
457 #define  RX_STATUS_XOFF_RCVD             0x00000002
458 #define  RX_STATUS_XON_RCVD              0x00000004
459 #define MAC_HASH_REG_0                  0x00000470
460 #define MAC_HASH_REG_1                  0x00000474
461 #define MAC_HASH_REG_2                  0x00000478
462 #define MAC_HASH_REG_3                  0x0000047c
463 #define MAC_RCV_RULE_0                  0x00000480
464 #define MAC_RCV_VALUE_0                 0x00000484
465 #define MAC_RCV_RULE_1                  0x00000488
466 #define MAC_RCV_VALUE_1                 0x0000048c
467 #define MAC_RCV_RULE_2                  0x00000490
468 #define MAC_RCV_VALUE_2                 0x00000494
469 #define MAC_RCV_RULE_3                  0x00000498
470 #define MAC_RCV_VALUE_3                 0x0000049c
471 #define MAC_RCV_RULE_4                  0x000004a0
472 #define MAC_RCV_VALUE_4                 0x000004a4
473 #define MAC_RCV_RULE_5                  0x000004a8
474 #define MAC_RCV_VALUE_5                 0x000004ac
475 #define MAC_RCV_RULE_6                  0x000004b0
476 #define MAC_RCV_VALUE_6                 0x000004b4
477 #define MAC_RCV_RULE_7                  0x000004b8
478 #define MAC_RCV_VALUE_7                 0x000004bc
479 #define MAC_RCV_RULE_8                  0x000004c0
480 #define MAC_RCV_VALUE_8                 0x000004c4
481 #define MAC_RCV_RULE_9                  0x000004c8
482 #define MAC_RCV_VALUE_9                 0x000004cc
483 #define MAC_RCV_RULE_10                 0x000004d0
484 #define MAC_RCV_VALUE_10                0x000004d4
485 #define MAC_RCV_RULE_11                 0x000004d8
486 #define MAC_RCV_VALUE_11                0x000004dc
487 #define MAC_RCV_RULE_12                 0x000004e0
488 #define MAC_RCV_VALUE_12                0x000004e4
489 #define MAC_RCV_RULE_13                 0x000004e8
490 #define MAC_RCV_VALUE_13                0x000004ec
491 #define MAC_RCV_RULE_14                 0x000004f0
492 #define MAC_RCV_VALUE_14                0x000004f4
493 #define MAC_RCV_RULE_15                 0x000004f8
494 #define MAC_RCV_VALUE_15                0x000004fc
495 #define  RCV_RULE_DISABLE_MASK           0x7fffffff
496 #define MAC_RCV_RULE_CFG                0x00000500
497 #define  RCV_RULE_CFG_DEFAULT_CLASS     0x00000008
498 #define MAC_LOW_WMARK_MAX_RX_FRAME      0x00000504
499 /* 0x508 --> 0x520 unused */
500 #define MAC_HASHREGU_0                  0x00000520
501 #define MAC_HASHREGU_1                  0x00000524
502 #define MAC_HASHREGU_2                  0x00000528
503 #define MAC_HASHREGU_3                  0x0000052c
504 #define MAC_EXTADDR_0_HIGH              0x00000530
505 #define MAC_EXTADDR_0_LOW               0x00000534
506 #define MAC_EXTADDR_1_HIGH              0x00000538
507 #define MAC_EXTADDR_1_LOW               0x0000053c
508 #define MAC_EXTADDR_2_HIGH              0x00000540
509 #define MAC_EXTADDR_2_LOW               0x00000544
510 #define MAC_EXTADDR_3_HIGH              0x00000548
511 #define MAC_EXTADDR_3_LOW               0x0000054c
512 #define MAC_EXTADDR_4_HIGH              0x00000550
513 #define MAC_EXTADDR_4_LOW               0x00000554
514 #define MAC_EXTADDR_5_HIGH              0x00000558
515 #define MAC_EXTADDR_5_LOW               0x0000055c
516 #define MAC_EXTADDR_6_HIGH              0x00000560
517 #define MAC_EXTADDR_6_LOW               0x00000564
518 #define MAC_EXTADDR_7_HIGH              0x00000568
519 #define MAC_EXTADDR_7_LOW               0x0000056c
520 #define MAC_EXTADDR_8_HIGH              0x00000570
521 #define MAC_EXTADDR_8_LOW               0x00000574
522 #define MAC_EXTADDR_9_HIGH              0x00000578
523 #define MAC_EXTADDR_9_LOW               0x0000057c
524 #define MAC_EXTADDR_10_HIGH             0x00000580
525 #define MAC_EXTADDR_10_LOW              0x00000584
526 #define MAC_EXTADDR_11_HIGH             0x00000588
527 #define MAC_EXTADDR_11_LOW              0x0000058c
528 #define MAC_SERDES_CFG                  0x00000590
529 #define  MAC_SERDES_CFG_EDGE_SELECT      0x00001000
530 #define MAC_SERDES_STAT                 0x00000594
531 /* 0x598 --> 0x5b0 unused */
532 #define SERDES_RX_CTRL                  0x000005b0      /* 5780/5714 only */
533 #define  SERDES_RX_SIG_DETECT            0x00000400
534 #define SG_DIG_CTRL                     0x000005b0
535 #define  SG_DIG_USING_HW_AUTONEG         0x80000000
536 #define  SG_DIG_SOFT_RESET               0x40000000
537 #define  SG_DIG_DISABLE_LINKRDY          0x20000000
538 #define  SG_DIG_CRC16_CLEAR_N            0x01000000
539 #define  SG_DIG_EN10B                    0x00800000
540 #define  SG_DIG_CLEAR_STATUS             0x00400000
541 #define  SG_DIG_LOCAL_DUPLEX_STATUS      0x00200000
542 #define  SG_DIG_LOCAL_LINK_STATUS        0x00100000
543 #define  SG_DIG_SPEED_STATUS_MASK        0x000c0000
544 #define  SG_DIG_SPEED_STATUS_SHIFT       18
545 #define  SG_DIG_JUMBO_PACKET_DISABLE     0x00020000
546 #define  SG_DIG_RESTART_AUTONEG          0x00010000
547 #define  SG_DIG_FIBER_MODE               0x00008000
548 #define  SG_DIG_REMOTE_FAULT_MASK        0x00006000
549 #define  SG_DIG_PAUSE_MASK               0x00001800
550 #define  SG_DIG_PAUSE_CAP                0x00000800
551 #define  SG_DIG_ASYM_PAUSE               0x00001000
552 #define  SG_DIG_GBIC_ENABLE              0x00000400
553 #define  SG_DIG_CHECK_END_ENABLE         0x00000200
554 #define  SG_DIG_SGMII_AUTONEG_TIMER      0x00000100
555 #define  SG_DIG_CLOCK_PHASE_SELECT       0x00000080
556 #define  SG_DIG_GMII_INPUT_SELECT        0x00000040
557 #define  SG_DIG_MRADV_CRC16_SELECT       0x00000020
558 #define  SG_DIG_COMMA_DETECT_ENABLE      0x00000010
559 #define  SG_DIG_AUTONEG_TIMER_REDUCE     0x00000008
560 #define  SG_DIG_AUTONEG_LOW_ENABLE       0x00000004
561 #define  SG_DIG_REMOTE_LOOPBACK          0x00000002
562 #define  SG_DIG_LOOPBACK                 0x00000001
563 #define  SG_DIG_COMMON_SETUP (SG_DIG_CRC16_CLEAR_N | \
564                               SG_DIG_LOCAL_DUPLEX_STATUS | \
565                               SG_DIG_LOCAL_LINK_STATUS | \
566                               (0x2 << SG_DIG_SPEED_STATUS_SHIFT) | \
567                               SG_DIG_FIBER_MODE | SG_DIG_GBIC_ENABLE)
568 #define SG_DIG_STATUS                   0x000005b4
569 #define  SG_DIG_CRC16_BUS_MASK           0xffff0000
570 #define  SG_DIG_PARTNER_FAULT_MASK       0x00600000 /* If !MRADV_CRC16_SELECT */
571 #define  SG_DIG_PARTNER_ASYM_PAUSE       0x00100000 /* If !MRADV_CRC16_SELECT */
572 #define  SG_DIG_PARTNER_PAUSE_CAPABLE    0x00080000 /* If !MRADV_CRC16_SELECT */
573 #define  SG_DIG_PARTNER_HALF_DUPLEX      0x00040000 /* If !MRADV_CRC16_SELECT */
574 #define  SG_DIG_PARTNER_FULL_DUPLEX      0x00020000 /* If !MRADV_CRC16_SELECT */
575 #define  SG_DIG_PARTNER_NEXT_PAGE        0x00010000 /* If !MRADV_CRC16_SELECT */
576 #define  SG_DIG_AUTONEG_STATE_MASK       0x00000ff0
577 #define  SG_DIG_COMMA_DETECTOR           0x00000008
578 #define  SG_DIG_MAC_ACK_STATUS           0x00000004
579 #define  SG_DIG_AUTONEG_COMPLETE         0x00000002
580 #define  SG_DIG_AUTONEG_ERROR            0x00000001
581 /* 0x5b8 --> 0x600 unused */
582 #define MAC_TX_MAC_STATE_BASE           0x00000600 /* 16 bytes */
583 #define MAC_RX_MAC_STATE_BASE           0x00000610 /* 20 bytes */
584 /* 0x624 --> 0x800 unused */
585 #define MAC_TX_STATS_OCTETS             0x00000800
586 #define MAC_TX_STATS_RESV1              0x00000804
587 #define MAC_TX_STATS_COLLISIONS         0x00000808
588 #define MAC_TX_STATS_XON_SENT           0x0000080c
589 #define MAC_TX_STATS_XOFF_SENT          0x00000810
590 #define MAC_TX_STATS_RESV2              0x00000814
591 #define MAC_TX_STATS_MAC_ERRORS         0x00000818
592 #define MAC_TX_STATS_SINGLE_COLLISIONS  0x0000081c
593 #define MAC_TX_STATS_MULT_COLLISIONS    0x00000820
594 #define MAC_TX_STATS_DEFERRED           0x00000824
595 #define MAC_TX_STATS_RESV3              0x00000828
596 #define MAC_TX_STATS_EXCESSIVE_COL      0x0000082c
597 #define MAC_TX_STATS_LATE_COL           0x00000830
598 #define MAC_TX_STATS_RESV4_1            0x00000834
599 #define MAC_TX_STATS_RESV4_2            0x00000838
600 #define MAC_TX_STATS_RESV4_3            0x0000083c
601 #define MAC_TX_STATS_RESV4_4            0x00000840
602 #define MAC_TX_STATS_RESV4_5            0x00000844
603 #define MAC_TX_STATS_RESV4_6            0x00000848
604 #define MAC_TX_STATS_RESV4_7            0x0000084c
605 #define MAC_TX_STATS_RESV4_8            0x00000850
606 #define MAC_TX_STATS_RESV4_9            0x00000854
607 #define MAC_TX_STATS_RESV4_10           0x00000858
608 #define MAC_TX_STATS_RESV4_11           0x0000085c
609 #define MAC_TX_STATS_RESV4_12           0x00000860
610 #define MAC_TX_STATS_RESV4_13           0x00000864
611 #define MAC_TX_STATS_RESV4_14           0x00000868
612 #define MAC_TX_STATS_UCAST              0x0000086c
613 #define MAC_TX_STATS_MCAST              0x00000870
614 #define MAC_TX_STATS_BCAST              0x00000874
615 #define MAC_TX_STATS_RESV5_1            0x00000878
616 #define MAC_TX_STATS_RESV5_2            0x0000087c
617 #define MAC_RX_STATS_OCTETS             0x00000880
618 #define MAC_RX_STATS_RESV1              0x00000884
619 #define MAC_RX_STATS_FRAGMENTS          0x00000888
620 #define MAC_RX_STATS_UCAST              0x0000088c
621 #define MAC_RX_STATS_MCAST              0x00000890
622 #define MAC_RX_STATS_BCAST              0x00000894
623 #define MAC_RX_STATS_FCS_ERRORS         0x00000898
624 #define MAC_RX_STATS_ALIGN_ERRORS       0x0000089c
625 #define MAC_RX_STATS_XON_PAUSE_RECVD    0x000008a0
626 #define MAC_RX_STATS_XOFF_PAUSE_RECVD   0x000008a4
627 #define MAC_RX_STATS_MAC_CTRL_RECVD     0x000008a8
628 #define MAC_RX_STATS_XOFF_ENTERED       0x000008ac
629 #define MAC_RX_STATS_FRAME_TOO_LONG     0x000008b0
630 #define MAC_RX_STATS_JABBERS            0x000008b4
631 #define MAC_RX_STATS_UNDERSIZE          0x000008b8
632 /* 0x8bc --> 0xc00 unused */
633
634 /* Send data initiator control registers */
635 #define SNDDATAI_MODE                   0x00000c00
636 #define  SNDDATAI_MODE_RESET             0x00000001
637 #define  SNDDATAI_MODE_ENABLE            0x00000002
638 #define  SNDDATAI_MODE_STAT_OFLOW_ENAB   0x00000004
639 #define SNDDATAI_STATUS                 0x00000c04
640 #define  SNDDATAI_STATUS_STAT_OFLOW      0x00000004
641 #define SNDDATAI_STATSCTRL              0x00000c08
642 #define  SNDDATAI_SCTRL_ENABLE           0x00000001
643 #define  SNDDATAI_SCTRL_FASTUPD          0x00000002
644 #define  SNDDATAI_SCTRL_CLEAR            0x00000004
645 #define  SNDDATAI_SCTRL_FLUSH            0x00000008
646 #define  SNDDATAI_SCTRL_FORCE_ZERO       0x00000010
647 #define SNDDATAI_STATSENAB              0x00000c0c
648 #define SNDDATAI_STATSINCMASK           0x00000c10
649 #define ISO_PKT_TX                      0x00000c20
650 /* 0xc24 --> 0xc80 unused */
651 #define SNDDATAI_COS_CNT_0              0x00000c80
652 #define SNDDATAI_COS_CNT_1              0x00000c84
653 #define SNDDATAI_COS_CNT_2              0x00000c88
654 #define SNDDATAI_COS_CNT_3              0x00000c8c
655 #define SNDDATAI_COS_CNT_4              0x00000c90
656 #define SNDDATAI_COS_CNT_5              0x00000c94
657 #define SNDDATAI_COS_CNT_6              0x00000c98
658 #define SNDDATAI_COS_CNT_7              0x00000c9c
659 #define SNDDATAI_COS_CNT_8              0x00000ca0
660 #define SNDDATAI_COS_CNT_9              0x00000ca4
661 #define SNDDATAI_COS_CNT_10             0x00000ca8
662 #define SNDDATAI_COS_CNT_11             0x00000cac
663 #define SNDDATAI_COS_CNT_12             0x00000cb0
664 #define SNDDATAI_COS_CNT_13             0x00000cb4
665 #define SNDDATAI_COS_CNT_14             0x00000cb8
666 #define SNDDATAI_COS_CNT_15             0x00000cbc
667 #define SNDDATAI_DMA_RDQ_FULL_CNT       0x00000cc0
668 #define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT  0x00000cc4
669 #define SNDDATAI_SDCQ_FULL_CNT          0x00000cc8
670 #define SNDDATAI_NICRNG_SSND_PIDX_CNT   0x00000ccc
671 #define SNDDATAI_STATS_UPDATED_CNT      0x00000cd0
672 #define SNDDATAI_INTERRUPTS_CNT         0x00000cd4
673 #define SNDDATAI_AVOID_INTERRUPTS_CNT   0x00000cd8
674 #define SNDDATAI_SND_THRESH_HIT_CNT     0x00000cdc
675 /* 0xce0 --> 0x1000 unused */
676
677 /* Send data completion control registers */
678 #define SNDDATAC_MODE                   0x00001000
679 #define  SNDDATAC_MODE_RESET             0x00000001
680 #define  SNDDATAC_MODE_ENABLE            0x00000002
681 #define  SNDDATAC_MODE_CDELAY            0x00000010
682 /* 0x1004 --> 0x1400 unused */
683
684 /* Send BD ring selector */
685 #define SNDBDS_MODE                     0x00001400
686 #define  SNDBDS_MODE_RESET               0x00000001
687 #define  SNDBDS_MODE_ENABLE              0x00000002
688 #define  SNDBDS_MODE_ATTN_ENABLE         0x00000004
689 #define SNDBDS_STATUS                   0x00001404
690 #define  SNDBDS_STATUS_ERROR_ATTN        0x00000004
691 #define SNDBDS_HWDIAG                   0x00001408
692 /* 0x140c --> 0x1440 */
693 #define SNDBDS_SEL_CON_IDX_0            0x00001440
694 #define SNDBDS_SEL_CON_IDX_1            0x00001444
695 #define SNDBDS_SEL_CON_IDX_2            0x00001448
696 #define SNDBDS_SEL_CON_IDX_3            0x0000144c
697 #define SNDBDS_SEL_CON_IDX_4            0x00001450
698 #define SNDBDS_SEL_CON_IDX_5            0x00001454
699 #define SNDBDS_SEL_CON_IDX_6            0x00001458
700 #define SNDBDS_SEL_CON_IDX_7            0x0000145c
701 #define SNDBDS_SEL_CON_IDX_8            0x00001460
702 #define SNDBDS_SEL_CON_IDX_9            0x00001464
703 #define SNDBDS_SEL_CON_IDX_10           0x00001468
704 #define SNDBDS_SEL_CON_IDX_11           0x0000146c
705 #define SNDBDS_SEL_CON_IDX_12           0x00001470
706 #define SNDBDS_SEL_CON_IDX_13           0x00001474
707 #define SNDBDS_SEL_CON_IDX_14           0x00001478
708 #define SNDBDS_SEL_CON_IDX_15           0x0000147c
709 /* 0x1480 --> 0x1800 unused */
710
711 /* Send BD initiator control registers */
712 #define SNDBDI_MODE                     0x00001800
713 #define  SNDBDI_MODE_RESET               0x00000001
714 #define  SNDBDI_MODE_ENABLE              0x00000002
715 #define  SNDBDI_MODE_ATTN_ENABLE         0x00000004
716 #define SNDBDI_STATUS                   0x00001804
717 #define  SNDBDI_STATUS_ERROR_ATTN        0x00000004
718 #define SNDBDI_IN_PROD_IDX_0            0x00001808
719 #define SNDBDI_IN_PROD_IDX_1            0x0000180c
720 #define SNDBDI_IN_PROD_IDX_2            0x00001810
721 #define SNDBDI_IN_PROD_IDX_3            0x00001814
722 #define SNDBDI_IN_PROD_IDX_4            0x00001818
723 #define SNDBDI_IN_PROD_IDX_5            0x0000181c
724 #define SNDBDI_IN_PROD_IDX_6            0x00001820
725 #define SNDBDI_IN_PROD_IDX_7            0x00001824
726 #define SNDBDI_IN_PROD_IDX_8            0x00001828
727 #define SNDBDI_IN_PROD_IDX_9            0x0000182c
728 #define SNDBDI_IN_PROD_IDX_10           0x00001830
729 #define SNDBDI_IN_PROD_IDX_11           0x00001834
730 #define SNDBDI_IN_PROD_IDX_12           0x00001838
731 #define SNDBDI_IN_PROD_IDX_13           0x0000183c
732 #define SNDBDI_IN_PROD_IDX_14           0x00001840
733 #define SNDBDI_IN_PROD_IDX_15           0x00001844
734 /* 0x1848 --> 0x1c00 unused */
735
736 /* Send BD completion control registers */
737 #define SNDBDC_MODE                     0x00001c00
738 #define SNDBDC_MODE_RESET                0x00000001
739 #define SNDBDC_MODE_ENABLE               0x00000002
740 #define SNDBDC_MODE_ATTN_ENABLE          0x00000004
741 /* 0x1c04 --> 0x2000 unused */
742
743 /* Receive list placement control registers */
744 #define RCVLPC_MODE                     0x00002000
745 #define  RCVLPC_MODE_RESET               0x00000001
746 #define  RCVLPC_MODE_ENABLE              0x00000002
747 #define  RCVLPC_MODE_CLASS0_ATTN_ENAB    0x00000004
748 #define  RCVLPC_MODE_MAPOOR_AATTN_ENAB   0x00000008
749 #define  RCVLPC_MODE_STAT_OFLOW_ENAB     0x00000010
750 #define RCVLPC_STATUS                   0x00002004
751 #define  RCVLPC_STATUS_CLASS0            0x00000004
752 #define  RCVLPC_STATUS_MAPOOR            0x00000008
753 #define  RCVLPC_STATUS_STAT_OFLOW        0x00000010
754 #define RCVLPC_LOCK                     0x00002008
755 #define  RCVLPC_LOCK_REQ_MASK            0x0000ffff
756 #define  RCVLPC_LOCK_REQ_SHIFT           0
757 #define  RCVLPC_LOCK_GRANT_MASK          0xffff0000
758 #define  RCVLPC_LOCK_GRANT_SHIFT         16
759 #define RCVLPC_NON_EMPTY_BITS           0x0000200c
760 #define  RCVLPC_NON_EMPTY_BITS_MASK      0x0000ffff
761 #define RCVLPC_CONFIG                   0x00002010
762 #define RCVLPC_STATSCTRL                0x00002014
763 #define  RCVLPC_STATSCTRL_ENABLE         0x00000001
764 #define  RCVLPC_STATSCTRL_FASTUPD        0x00000002
765 #define RCVLPC_STATS_ENABLE             0x00002018
766 #define  RCVLPC_STATSENAB_DACK_FIX       0x00040000
767 #define  RCVLPC_STATSENAB_LNGBRST_RFIX   0x00400000
768 #define RCVLPC_STATS_INCMASK            0x0000201c
769 /* 0x2020 --> 0x2100 unused */
770 #define RCVLPC_SELLST_BASE              0x00002100 /* 16 16-byte entries */
771 #define  SELLST_TAIL                    0x00000004
772 #define  SELLST_CONT                    0x00000008
773 #define  SELLST_UNUSED                  0x0000000c
774 #define RCVLPC_COS_CNTL_BASE            0x00002200 /* 16 4-byte entries */
775 #define RCVLPC_DROP_FILTER_CNT          0x00002240
776 #define RCVLPC_DMA_WQ_FULL_CNT          0x00002244
777 #define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT   0x00002248
778 #define RCVLPC_NO_RCV_BD_CNT            0x0000224c
779 #define RCVLPC_IN_DISCARDS_CNT          0x00002250
780 #define RCVLPC_IN_ERRORS_CNT            0x00002254
781 #define RCVLPC_RCV_THRESH_HIT_CNT       0x00002258
782 /* 0x225c --> 0x2400 unused */
783
784 /* Receive Data and Receive BD Initiator Control */
785 #define RCVDBDI_MODE                    0x00002400
786 #define  RCVDBDI_MODE_RESET              0x00000001
787 #define  RCVDBDI_MODE_ENABLE             0x00000002
788 #define  RCVDBDI_MODE_JUMBOBD_NEEDED     0x00000004
789 #define  RCVDBDI_MODE_FRM_TOO_BIG        0x00000008
790 #define  RCVDBDI_MODE_INV_RING_SZ        0x00000010
791 #define RCVDBDI_STATUS                  0x00002404
792 #define  RCVDBDI_STATUS_JUMBOBD_NEEDED   0x00000004
793 #define  RCVDBDI_STATUS_FRM_TOO_BIG      0x00000008
794 #define  RCVDBDI_STATUS_INV_RING_SZ      0x00000010
795 #define RCVDBDI_SPLIT_FRAME_MINSZ       0x00002408
796 /* 0x240c --> 0x2440 unused */
797 #define RCVDBDI_JUMBO_BD                0x00002440 /* TG3_BDINFO_... */
798 #define RCVDBDI_STD_BD                  0x00002450 /* TG3_BDINFO_... */
799 #define RCVDBDI_MINI_BD                 0x00002460 /* TG3_BDINFO_... */
800 #define RCVDBDI_JUMBO_CON_IDX           0x00002470
801 #define RCVDBDI_STD_CON_IDX             0x00002474
802 #define RCVDBDI_MINI_CON_IDX            0x00002478
803 /* 0x247c --> 0x2480 unused */
804 #define RCVDBDI_BD_PROD_IDX_0           0x00002480
805 #define RCVDBDI_BD_PROD_IDX_1           0x00002484
806 #define RCVDBDI_BD_PROD_IDX_2           0x00002488
807 #define RCVDBDI_BD_PROD_IDX_3           0x0000248c
808 #define RCVDBDI_BD_PROD_IDX_4           0x00002490
809 #define RCVDBDI_BD_PROD_IDX_5           0x00002494
810 #define RCVDBDI_BD_PROD_IDX_6           0x00002498
811 #define RCVDBDI_BD_PROD_IDX_7           0x0000249c
812 #define RCVDBDI_BD_PROD_IDX_8           0x000024a0
813 #define RCVDBDI_BD_PROD_IDX_9           0x000024a4
814 #define RCVDBDI_BD_PROD_IDX_10          0x000024a8
815 #define RCVDBDI_BD_PROD_IDX_11          0x000024ac
816 #define RCVDBDI_BD_PROD_IDX_12          0x000024b0
817 #define RCVDBDI_BD_PROD_IDX_13          0x000024b4
818 #define RCVDBDI_BD_PROD_IDX_14          0x000024b8
819 #define RCVDBDI_BD_PROD_IDX_15          0x000024bc
820 #define RCVDBDI_HWDIAG                  0x000024c0
821 /* 0x24c4 --> 0x2800 unused */
822
823 /* Receive Data Completion Control */
824 #define RCVDCC_MODE                     0x00002800
825 #define  RCVDCC_MODE_RESET               0x00000001
826 #define  RCVDCC_MODE_ENABLE              0x00000002
827 #define  RCVDCC_MODE_ATTN_ENABLE         0x00000004
828 /* 0x2804 --> 0x2c00 unused */
829
830 /* Receive BD Initiator Control Registers */
831 #define RCVBDI_MODE                     0x00002c00
832 #define  RCVBDI_MODE_RESET               0x00000001
833 #define  RCVBDI_MODE_ENABLE              0x00000002
834 #define  RCVBDI_MODE_RCB_ATTN_ENAB       0x00000004
835 #define RCVBDI_STATUS                   0x00002c04
836 #define  RCVBDI_STATUS_RCB_ATTN          0x00000004
837 #define RCVBDI_JUMBO_PROD_IDX           0x00002c08
838 #define RCVBDI_STD_PROD_IDX             0x00002c0c
839 #define RCVBDI_MINI_PROD_IDX            0x00002c10
840 #define RCVBDI_MINI_THRESH              0x00002c14
841 #define RCVBDI_STD_THRESH               0x00002c18
842 #define RCVBDI_JUMBO_THRESH             0x00002c1c
843 /* 0x2c20 --> 0x3000 unused */
844
845 /* Receive BD Completion Control Registers */
846 #define RCVCC_MODE                      0x00003000
847 #define  RCVCC_MODE_RESET                0x00000001
848 #define  RCVCC_MODE_ENABLE               0x00000002
849 #define  RCVCC_MODE_ATTN_ENABLE          0x00000004
850 #define RCVCC_STATUS                    0x00003004
851 #define  RCVCC_STATUS_ERROR_ATTN         0x00000004
852 #define RCVCC_JUMP_PROD_IDX             0x00003008
853 #define RCVCC_STD_PROD_IDX              0x0000300c
854 #define RCVCC_MINI_PROD_IDX             0x00003010
855 /* 0x3014 --> 0x3400 unused */
856
857 /* Receive list selector control registers */
858 #define RCVLSC_MODE                     0x00003400
859 #define  RCVLSC_MODE_RESET               0x00000001
860 #define  RCVLSC_MODE_ENABLE              0x00000002
861 #define  RCVLSC_MODE_ATTN_ENABLE         0x00000004
862 #define RCVLSC_STATUS                   0x00003404
863 #define  RCVLSC_STATUS_ERROR_ATTN        0x00000004
864 /* 0x3408 --> 0x3600 unused */
865
866 /* CPMU registers */
867 #define TG3_CPMU_CTRL                   0x00003600
868 #define  CPMU_CTRL_LINK_IDLE_MODE        0x00000200
869 #define  CPMU_CTRL_LINK_AWARE_MODE       0x00000400
870 #define  CPMU_CTRL_LINK_SPEED_MODE       0x00004000
871 #define  CPMU_CTRL_GPHY_10MB_RXONLY      0x00010000
872 #define TG3_CPMU_LSPD_10MB_CLK          0x00003604
873 #define  CPMU_LSPD_10MB_MACCLK_MASK      0x001f0000
874 #define  CPMU_LSPD_10MB_MACCLK_6_25      0x00130000
875 /* 0x3608 --> 0x360c unused */
876
877 #define TG3_CPMU_LSPD_1000MB_CLK        0x0000360c
878 #define  CPMU_LSPD_1000MB_MACCLK_62_5    0x00000000
879 #define  CPMU_LSPD_1000MB_MACCLK_12_5    0x00110000
880 #define  CPMU_LSPD_1000MB_MACCLK_MASK    0x001f0000
881 #define TG3_CPMU_LNK_AWARE_PWRMD        0x00003610
882 #define  CPMU_LNK_AWARE_MACCLK_MASK      0x001f0000
883 #define  CPMU_LNK_AWARE_MACCLK_6_25      0x00130000
884 /* 0x3614 --> 0x361c unused */
885
886 #define TG3_CPMU_HST_ACC                0x0000361c
887 #define  CPMU_HST_ACC_MACCLK_MASK        0x001f0000
888 #define  CPMU_HST_ACC_MACCLK_6_25        0x00130000
889 /* 0x3620 --> 0x3630 unused */
890
891 #define TG3_CPMU_CLCK_STAT              0x00003630
892 #define  CPMU_CLCK_STAT_MAC_CLCK_MASK    0x001f0000
893 #define  CPMU_CLCK_STAT_MAC_CLCK_62_5    0x00000000
894 #define  CPMU_CLCK_STAT_MAC_CLCK_12_5    0x00110000
895 #define  CPMU_CLCK_STAT_MAC_CLCK_6_25    0x00130000
896 /* 0x3634 --> 0x365c unused */
897
898 #define TG3_CPMU_MUTEX_REQ              0x0000365c
899 #define  CPMU_MUTEX_REQ_DRIVER           0x00001000
900 #define TG3_CPMU_MUTEX_GNT              0x00003660
901 #define  CPMU_MUTEX_GNT_DRIVER           0x00001000
902 /* 0x3664 --> 0x3800 unused */
903
904 /* Mbuf cluster free registers */
905 #define MBFREE_MODE                     0x00003800
906 #define  MBFREE_MODE_RESET               0x00000001
907 #define  MBFREE_MODE_ENABLE              0x00000002
908 #define MBFREE_STATUS                   0x00003804
909 /* 0x3808 --> 0x3c00 unused */
910
911 /* Host coalescing control registers */
912 #define HOSTCC_MODE                     0x00003c00
913 #define  HOSTCC_MODE_RESET               0x00000001
914 #define  HOSTCC_MODE_ENABLE              0x00000002
915 #define  HOSTCC_MODE_ATTN                0x00000004
916 #define  HOSTCC_MODE_NOW                 0x00000008
917 #define  HOSTCC_MODE_FULL_STATUS         0x00000000
918 #define  HOSTCC_MODE_64BYTE              0x00000080
919 #define  HOSTCC_MODE_32BYTE              0x00000100
920 #define  HOSTCC_MODE_CLRTICK_RXBD        0x00000200
921 #define  HOSTCC_MODE_CLRTICK_TXBD        0x00000400
922 #define  HOSTCC_MODE_NOINT_ON_NOW        0x00000800
923 #define  HOSTCC_MODE_NOINT_ON_FORCE      0x00001000
924 #define HOSTCC_STATUS                   0x00003c04
925 #define  HOSTCC_STATUS_ERROR_ATTN        0x00000004
926 #define HOSTCC_RXCOL_TICKS              0x00003c08
927 #define  LOW_RXCOL_TICKS                 0x00000032
928 #define  LOW_RXCOL_TICKS_CLRTCKS         0x00000014
929 #define  DEFAULT_RXCOL_TICKS             0x00000048
930 #define  HIGH_RXCOL_TICKS                0x00000096
931 #define  MAX_RXCOL_TICKS                 0x000003ff
932 #define HOSTCC_TXCOL_TICKS              0x00003c0c
933 #define  LOW_TXCOL_TICKS                 0x00000096
934 #define  LOW_TXCOL_TICKS_CLRTCKS         0x00000048
935 #define  DEFAULT_TXCOL_TICKS             0x0000012c
936 #define  HIGH_TXCOL_TICKS                0x00000145
937 #define  MAX_TXCOL_TICKS                 0x000003ff
938 #define HOSTCC_RXMAX_FRAMES             0x00003c10
939 #define  LOW_RXMAX_FRAMES                0x00000005
940 #define  DEFAULT_RXMAX_FRAMES            0x00000008
941 #define  HIGH_RXMAX_FRAMES               0x00000012
942 #define  MAX_RXMAX_FRAMES                0x000000ff
943 #define HOSTCC_TXMAX_FRAMES             0x00003c14
944 #define  LOW_TXMAX_FRAMES                0x00000035
945 #define  DEFAULT_TXMAX_FRAMES            0x0000004b
946 #define  HIGH_TXMAX_FRAMES               0x00000052
947 #define  MAX_TXMAX_FRAMES                0x000000ff
948 #define HOSTCC_RXCOAL_TICK_INT          0x00003c18
949 #define  DEFAULT_RXCOAL_TICK_INT         0x00000019
950 #define  DEFAULT_RXCOAL_TICK_INT_CLRTCKS 0x00000014
951 #define  MAX_RXCOAL_TICK_INT             0x000003ff
952 #define HOSTCC_TXCOAL_TICK_INT          0x00003c1c
953 #define  DEFAULT_TXCOAL_TICK_INT         0x00000019
954 #define  DEFAULT_TXCOAL_TICK_INT_CLRTCKS 0x00000014
955 #define  MAX_TXCOAL_TICK_INT             0x000003ff
956 #define HOSTCC_RXCOAL_MAXF_INT          0x00003c20
957 #define  DEFAULT_RXCOAL_MAXF_INT         0x00000005
958 #define  MAX_RXCOAL_MAXF_INT             0x000000ff
959 #define HOSTCC_TXCOAL_MAXF_INT          0x00003c24
960 #define  DEFAULT_TXCOAL_MAXF_INT         0x00000005
961 #define  MAX_TXCOAL_MAXF_INT             0x000000ff
962 #define HOSTCC_STAT_COAL_TICKS          0x00003c28
963 #define  DEFAULT_STAT_COAL_TICKS         0x000f4240
964 #define  MAX_STAT_COAL_TICKS             0xd693d400
965 #define  MIN_STAT_COAL_TICKS             0x00000064
966 /* 0x3c2c --> 0x3c30 unused */
967 #define HOSTCC_STATS_BLK_HOST_ADDR      0x00003c30 /* 64-bit */
968 #define HOSTCC_STATUS_BLK_HOST_ADDR     0x00003c38 /* 64-bit */
969 #define HOSTCC_STATS_BLK_NIC_ADDR       0x00003c40
970 #define HOSTCC_STATUS_BLK_NIC_ADDR      0x00003c44
971 #define HOSTCC_FLOW_ATTN                0x00003c48
972 /* 0x3c4c --> 0x3c50 unused */
973 #define HOSTCC_JUMBO_CON_IDX            0x00003c50
974 #define HOSTCC_STD_CON_IDX              0x00003c54
975 #define HOSTCC_MINI_CON_IDX             0x00003c58
976 /* 0x3c5c --> 0x3c80 unused */
977 #define HOSTCC_RET_PROD_IDX_0           0x00003c80
978 #define HOSTCC_RET_PROD_IDX_1           0x00003c84
979 #define HOSTCC_RET_PROD_IDX_2           0x00003c88
980 #define HOSTCC_RET_PROD_IDX_3           0x00003c8c
981 #define HOSTCC_RET_PROD_IDX_4           0x00003c90
982 #define HOSTCC_RET_PROD_IDX_5           0x00003c94
983 #define HOSTCC_RET_PROD_IDX_6           0x00003c98
984 #define HOSTCC_RET_PROD_IDX_7           0x00003c9c
985 #define HOSTCC_RET_PROD_IDX_8           0x00003ca0
986 #define HOSTCC_RET_PROD_IDX_9           0x00003ca4
987 #define HOSTCC_RET_PROD_IDX_10          0x00003ca8
988 #define HOSTCC_RET_PROD_IDX_11          0x00003cac
989 #define HOSTCC_RET_PROD_IDX_12          0x00003cb0
990 #define HOSTCC_RET_PROD_IDX_13          0x00003cb4
991 #define HOSTCC_RET_PROD_IDX_14          0x00003cb8
992 #define HOSTCC_RET_PROD_IDX_15          0x00003cbc
993 #define HOSTCC_SND_CON_IDX_0            0x00003cc0
994 #define HOSTCC_SND_CON_IDX_1            0x00003cc4
995 #define HOSTCC_SND_CON_IDX_2            0x00003cc8
996 #define HOSTCC_SND_CON_IDX_3            0x00003ccc
997 #define HOSTCC_SND_CON_IDX_4            0x00003cd0
998 #define HOSTCC_SND_CON_IDX_5            0x00003cd4
999 #define HOSTCC_SND_CON_IDX_6            0x00003cd8
1000 #define HOSTCC_SND_CON_IDX_7            0x00003cdc
1001 #define HOSTCC_SND_CON_IDX_8            0x00003ce0
1002 #define HOSTCC_SND_CON_IDX_9            0x00003ce4
1003 #define HOSTCC_SND_CON_IDX_10           0x00003ce8
1004 #define HOSTCC_SND_CON_IDX_11           0x00003cec
1005 #define HOSTCC_SND_CON_IDX_12           0x00003cf0
1006 #define HOSTCC_SND_CON_IDX_13           0x00003cf4
1007 #define HOSTCC_SND_CON_IDX_14           0x00003cf8
1008 #define HOSTCC_SND_CON_IDX_15           0x00003cfc
1009 /* 0x3d00 --> 0x4000 unused */
1010
1011 /* Memory arbiter control registers */
1012 #define MEMARB_MODE                     0x00004000
1013 #define  MEMARB_MODE_RESET               0x00000001
1014 #define  MEMARB_MODE_ENABLE              0x00000002
1015 #define MEMARB_STATUS                   0x00004004
1016 #define MEMARB_TRAP_ADDR_LOW            0x00004008
1017 #define MEMARB_TRAP_ADDR_HIGH           0x0000400c
1018 /* 0x4010 --> 0x4400 unused */
1019
1020 /* Buffer manager control registers */
1021 #define BUFMGR_MODE                     0x00004400
1022 #define  BUFMGR_MODE_RESET               0x00000001
1023 #define  BUFMGR_MODE_ENABLE              0x00000002
1024 #define  BUFMGR_MODE_ATTN_ENABLE         0x00000004
1025 #define  BUFMGR_MODE_BM_TEST             0x00000008
1026 #define  BUFMGR_MODE_MBLOW_ATTN_ENAB     0x00000010
1027 #define BUFMGR_STATUS                   0x00004404
1028 #define  BUFMGR_STATUS_ERROR             0x00000004
1029 #define  BUFMGR_STATUS_MBLOW             0x00000010
1030 #define BUFMGR_MB_POOL_ADDR             0x00004408
1031 #define BUFMGR_MB_POOL_SIZE             0x0000440c
1032 #define BUFMGR_MB_RDMA_LOW_WATER        0x00004410
1033 #define  DEFAULT_MB_RDMA_LOW_WATER       0x00000050
1034 #define  DEFAULT_MB_RDMA_LOW_WATER_5705  0x00000000
1035 #define  DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130
1036 #define  DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780 0x00000000
1037 #define BUFMGR_MB_MACRX_LOW_WATER       0x00004414
1038 #define  DEFAULT_MB_MACRX_LOW_WATER       0x00000020
1039 #define  DEFAULT_MB_MACRX_LOW_WATER_5705  0x00000010
1040 #define  DEFAULT_MB_MACRX_LOW_WATER_5906  0x00000004
1041 #define  DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
1042 #define  DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b
1043 #define BUFMGR_MB_HIGH_WATER            0x00004418
1044 #define  DEFAULT_MB_HIGH_WATER           0x00000060
1045 #define  DEFAULT_MB_HIGH_WATER_5705      0x00000060
1046 #define  DEFAULT_MB_HIGH_WATER_5906      0x00000010
1047 #define  DEFAULT_MB_HIGH_WATER_JUMBO     0x0000017c
1048 #define  DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096
1049 #define BUFMGR_RX_MB_ALLOC_REQ          0x0000441c
1050 #define  BUFMGR_MB_ALLOC_BIT             0x10000000
1051 #define BUFMGR_RX_MB_ALLOC_RESP         0x00004420
1052 #define BUFMGR_TX_MB_ALLOC_REQ          0x00004424
1053 #define BUFMGR_TX_MB_ALLOC_RESP         0x00004428
1054 #define BUFMGR_DMA_DESC_POOL_ADDR       0x0000442c
1055 #define BUFMGR_DMA_DESC_POOL_SIZE       0x00004430
1056 #define BUFMGR_DMA_LOW_WATER            0x00004434
1057 #define  DEFAULT_DMA_LOW_WATER           0x00000005
1058 #define BUFMGR_DMA_HIGH_WATER           0x00004438
1059 #define  DEFAULT_DMA_HIGH_WATER          0x0000000a
1060 #define BUFMGR_RX_DMA_ALLOC_REQ         0x0000443c
1061 #define BUFMGR_RX_DMA_ALLOC_RESP        0x00004440
1062 #define BUFMGR_TX_DMA_ALLOC_REQ         0x00004444
1063 #define BUFMGR_TX_DMA_ALLOC_RESP        0x00004448
1064 #define BUFMGR_HWDIAG_0                 0x0000444c
1065 #define BUFMGR_HWDIAG_1                 0x00004450
1066 #define BUFMGR_HWDIAG_2                 0x00004454
1067 /* 0x4458 --> 0x4800 unused */
1068
1069 /* Read DMA control registers */
1070 #define RDMAC_MODE                      0x00004800
1071 #define  RDMAC_MODE_RESET                0x00000001
1072 #define  RDMAC_MODE_ENABLE               0x00000002
1073 #define  RDMAC_MODE_TGTABORT_ENAB        0x00000004
1074 #define  RDMAC_MODE_MSTABORT_ENAB        0x00000008
1075 #define  RDMAC_MODE_PARITYERR_ENAB       0x00000010
1076 #define  RDMAC_MODE_ADDROFLOW_ENAB       0x00000020
1077 #define  RDMAC_MODE_FIFOOFLOW_ENAB       0x00000040
1078 #define  RDMAC_MODE_FIFOURUN_ENAB        0x00000080
1079 #define  RDMAC_MODE_FIFOOREAD_ENAB       0x00000100
1080 #define  RDMAC_MODE_LNGREAD_ENAB         0x00000200
1081 #define  RDMAC_MODE_SPLIT_ENABLE         0x00000800
1082 #define  RDMAC_MODE_BD_SBD_CRPT_ENAB     0x00000800
1083 #define  RDMAC_MODE_SPLIT_RESET          0x00001000
1084 #define  RDMAC_MODE_MBUF_RBD_CRPT_ENAB   0x00001000
1085 #define  RDMAC_MODE_MBUF_SBD_CRPT_ENAB   0x00002000
1086 #define  RDMAC_MODE_FIFO_SIZE_128        0x00020000
1087 #define  RDMAC_MODE_FIFO_LONG_BURST      0x00030000
1088 #define RDMAC_STATUS                    0x00004804
1089 #define  RDMAC_STATUS_TGTABORT           0x00000004
1090 #define  RDMAC_STATUS_MSTABORT           0x00000008
1091 #define  RDMAC_STATUS_PARITYERR          0x00000010
1092 #define  RDMAC_STATUS_ADDROFLOW          0x00000020
1093 #define  RDMAC_STATUS_FIFOOFLOW          0x00000040
1094 #define  RDMAC_STATUS_FIFOURUN           0x00000080
1095 #define  RDMAC_STATUS_FIFOOREAD          0x00000100
1096 #define  RDMAC_STATUS_LNGREAD            0x00000200
1097 /* 0x4808 --> 0x4c00 unused */
1098
1099 /* Write DMA control registers */
1100 #define WDMAC_MODE                      0x00004c00
1101 #define  WDMAC_MODE_RESET                0x00000001
1102 #define  WDMAC_MODE_ENABLE               0x00000002
1103 #define  WDMAC_MODE_TGTABORT_ENAB        0x00000004
1104 #define  WDMAC_MODE_MSTABORT_ENAB        0x00000008
1105 #define  WDMAC_MODE_PARITYERR_ENAB       0x00000010
1106 #define  WDMAC_MODE_ADDROFLOW_ENAB       0x00000020
1107 #define  WDMAC_MODE_FIFOOFLOW_ENAB       0x00000040
1108 #define  WDMAC_MODE_FIFOURUN_ENAB        0x00000080
1109 #define  WDMAC_MODE_FIFOOREAD_ENAB       0x00000100
1110 #define  WDMAC_MODE_LNGREAD_ENAB         0x00000200
1111 #define  WDMAC_MODE_RX_ACCEL             0x00000400
1112 #define WDMAC_STATUS                    0x00004c04
1113 #define  WDMAC_STATUS_TGTABORT           0x00000004
1114 #define  WDMAC_STATUS_MSTABORT           0x00000008
1115 #define  WDMAC_STATUS_PARITYERR          0x00000010
1116 #define  WDMAC_STATUS_ADDROFLOW          0x00000020
1117 #define  WDMAC_STATUS_FIFOOFLOW          0x00000040
1118 #define  WDMAC_STATUS_FIFOURUN           0x00000080
1119 #define  WDMAC_STATUS_FIFOOREAD          0x00000100
1120 #define  WDMAC_STATUS_LNGREAD            0x00000200
1121 /* 0x4c08 --> 0x5000 unused */
1122
1123 /* Per-cpu register offsets (arm9) */
1124 #define CPU_MODE                        0x00000000
1125 #define  CPU_MODE_RESET                  0x00000001
1126 #define  CPU_MODE_HALT                   0x00000400
1127 #define CPU_STATE                       0x00000004
1128 #define CPU_EVTMASK                     0x00000008
1129 /* 0xc --> 0x1c reserved */
1130 #define CPU_PC                          0x0000001c
1131 #define CPU_INSN                        0x00000020
1132 #define CPU_SPAD_UFLOW                  0x00000024
1133 #define CPU_WDOG_CLEAR                  0x00000028
1134 #define CPU_WDOG_VECTOR                 0x0000002c
1135 #define CPU_WDOG_PC                     0x00000030
1136 #define CPU_HW_BP                       0x00000034
1137 /* 0x38 --> 0x44 unused */
1138 #define CPU_WDOG_SAVED_STATE            0x00000044
1139 #define CPU_LAST_BRANCH_ADDR            0x00000048
1140 #define CPU_SPAD_UFLOW_SET              0x0000004c
1141 /* 0x50 --> 0x200 unused */
1142 #define CPU_R0                          0x00000200
1143 #define CPU_R1                          0x00000204
1144 #define CPU_R2                          0x00000208
1145 #define CPU_R3                          0x0000020c
1146 #define CPU_R4                          0x00000210
1147 #define CPU_R5                          0x00000214
1148 #define CPU_R6                          0x00000218
1149 #define CPU_R7                          0x0000021c
1150 #define CPU_R8                          0x00000220
1151 #define CPU_R9                          0x00000224
1152 #define CPU_R10                         0x00000228
1153 #define CPU_R11                         0x0000022c
1154 #define CPU_R12                         0x00000230
1155 #define CPU_R13                         0x00000234
1156 #define CPU_R14                         0x00000238
1157 #define CPU_R15                         0x0000023c
1158 #define CPU_R16                         0x00000240
1159 #define CPU_R17                         0x00000244
1160 #define CPU_R18                         0x00000248
1161 #define CPU_R19                         0x0000024c
1162 #define CPU_R20                         0x00000250
1163 #define CPU_R21                         0x00000254
1164 #define CPU_R22                         0x00000258
1165 #define CPU_R23                         0x0000025c
1166 #define CPU_R24                         0x00000260
1167 #define CPU_R25                         0x00000264
1168 #define CPU_R26                         0x00000268
1169 #define CPU_R27                         0x0000026c
1170 #define CPU_R28                         0x00000270
1171 #define CPU_R29                         0x00000274
1172 #define CPU_R30                         0x00000278
1173 #define CPU_R31                         0x0000027c
1174 /* 0x280 --> 0x400 unused */
1175
1176 #define RX_CPU_BASE                     0x00005000
1177 #define RX_CPU_MODE                     0x00005000
1178 #define RX_CPU_STATE                    0x00005004
1179 #define RX_CPU_PGMCTR                   0x0000501c
1180 #define RX_CPU_HWBKPT                   0x00005034
1181 #define TX_CPU_BASE                     0x00005400
1182 #define TX_CPU_MODE                     0x00005400
1183 #define TX_CPU_STATE                    0x00005404
1184 #define TX_CPU_PGMCTR                   0x0000541c
1185
1186 #define VCPU_STATUS                     0x00005100
1187 #define  VCPU_STATUS_INIT_DONE           0x04000000
1188 #define  VCPU_STATUS_DRV_RESET           0x08000000
1189
1190 #define VCPU_CFGSHDW                    0x00005104
1191 #define  VCPU_CFGSHDW_WOL_ENABLE         0x00000001
1192 #define  VCPU_CFGSHDW_WOL_MAGPKT         0x00000004
1193 #define  VCPU_CFGSHDW_ASPM_DBNC          0x00001000
1194
1195 /* Mailboxes */
1196 #define GRCMBOX_BASE                    0x00005600
1197 #define GRCMBOX_INTERRUPT_0             0x00005800 /* 64-bit */
1198 #define GRCMBOX_INTERRUPT_1             0x00005808 /* 64-bit */
1199 #define GRCMBOX_INTERRUPT_2             0x00005810 /* 64-bit */
1200 #define GRCMBOX_INTERRUPT_3             0x00005818 /* 64-bit */
1201 #define GRCMBOX_GENERAL_0               0x00005820 /* 64-bit */
1202 #define GRCMBOX_GENERAL_1               0x00005828 /* 64-bit */
1203 #define GRCMBOX_GENERAL_2               0x00005830 /* 64-bit */
1204 #define GRCMBOX_GENERAL_3               0x00005838 /* 64-bit */
1205 #define GRCMBOX_GENERAL_4               0x00005840 /* 64-bit */
1206 #define GRCMBOX_GENERAL_5               0x00005848 /* 64-bit */
1207 #define GRCMBOX_GENERAL_6               0x00005850 /* 64-bit */
1208 #define GRCMBOX_GENERAL_7               0x00005858 /* 64-bit */
1209 #define GRCMBOX_RELOAD_STAT             0x00005860 /* 64-bit */
1210 #define GRCMBOX_RCVSTD_PROD_IDX         0x00005868 /* 64-bit */
1211 #define GRCMBOX_RCVJUMBO_PROD_IDX       0x00005870 /* 64-bit */
1212 #define GRCMBOX_RCVMINI_PROD_IDX        0x00005878 /* 64-bit */
1213 #define GRCMBOX_RCVRET_CON_IDX_0        0x00005880 /* 64-bit */
1214 #define GRCMBOX_RCVRET_CON_IDX_1        0x00005888 /* 64-bit */
1215 #define GRCMBOX_RCVRET_CON_IDX_2        0x00005890 /* 64-bit */
1216 #define GRCMBOX_RCVRET_CON_IDX_3        0x00005898 /* 64-bit */
1217 #define GRCMBOX_RCVRET_CON_IDX_4        0x000058a0 /* 64-bit */
1218 #define GRCMBOX_RCVRET_CON_IDX_5        0x000058a8 /* 64-bit */
1219 #define GRCMBOX_RCVRET_CON_IDX_6        0x000058b0 /* 64-bit */
1220 #define GRCMBOX_RCVRET_CON_IDX_7        0x000058b8 /* 64-bit */
1221 #define GRCMBOX_RCVRET_CON_IDX_8        0x000058c0 /* 64-bit */
1222 #define GRCMBOX_RCVRET_CON_IDX_9        0x000058c8 /* 64-bit */
1223 #define GRCMBOX_RCVRET_CON_IDX_10       0x000058d0 /* 64-bit */
1224 #define GRCMBOX_RCVRET_CON_IDX_11       0x000058d8 /* 64-bit */
1225 #define GRCMBOX_RCVRET_CON_IDX_12       0x000058e0 /* 64-bit */
1226 #define GRCMBOX_RCVRET_CON_IDX_13       0x000058e8 /* 64-bit */
1227 #define GRCMBOX_RCVRET_CON_IDX_14       0x000058f0 /* 64-bit */
1228 #define GRCMBOX_RCVRET_CON_IDX_15       0x000058f8 /* 64-bit */
1229 #define GRCMBOX_SNDHOST_PROD_IDX_0      0x00005900 /* 64-bit */
1230 #define GRCMBOX_SNDHOST_PROD_IDX_1      0x00005908 /* 64-bit */
1231 #define GRCMBOX_SNDHOST_PROD_IDX_2      0x00005910 /* 64-bit */
1232 #define GRCMBOX_SNDHOST_PROD_IDX_3      0x00005918 /* 64-bit */
1233 #define GRCMBOX_SNDHOST_PROD_IDX_4      0x00005920 /* 64-bit */
1234 #define GRCMBOX_SNDHOST_PROD_IDX_5      0x00005928 /* 64-bit */
1235 #define GRCMBOX_SNDHOST_PROD_IDX_6      0x00005930 /* 64-bit */
1236 #define GRCMBOX_SNDHOST_PROD_IDX_7      0x00005938 /* 64-bit */
1237 #define GRCMBOX_SNDHOST_PROD_IDX_8      0x00005940 /* 64-bit */
1238 #define GRCMBOX_SNDHOST_PROD_IDX_9      0x00005948 /* 64-bit */
1239 #define GRCMBOX_SNDHOST_PROD_IDX_10     0x00005950 /* 64-bit */
1240 #define GRCMBOX_SNDHOST_PROD_IDX_11     0x00005958 /* 64-bit */
1241 #define GRCMBOX_SNDHOST_PROD_IDX_12     0x00005960 /* 64-bit */
1242 #define GRCMBOX_SNDHOST_PROD_IDX_13     0x00005968 /* 64-bit */
1243 #define GRCMBOX_SNDHOST_PROD_IDX_14     0x00005970 /* 64-bit */
1244 #define GRCMBOX_SNDHOST_PROD_IDX_15     0x00005978 /* 64-bit */
1245 #define GRCMBOX_SNDNIC_PROD_IDX_0       0x00005980 /* 64-bit */
1246 #define GRCMBOX_SNDNIC_PROD_IDX_1       0x00005988 /* 64-bit */
1247 #define GRCMBOX_SNDNIC_PROD_IDX_2       0x00005990 /* 64-bit */
1248 #define GRCMBOX_SNDNIC_PROD_IDX_3       0x00005998 /* 64-bit */
1249 #define GRCMBOX_SNDNIC_PROD_IDX_4       0x000059a0 /* 64-bit */
1250 #define GRCMBOX_SNDNIC_PROD_IDX_5       0x000059a8 /* 64-bit */
1251 #define GRCMBOX_SNDNIC_PROD_IDX_6       0x000059b0 /* 64-bit */
1252 #define GRCMBOX_SNDNIC_PROD_IDX_7       0x000059b8 /* 64-bit */
1253 #define GRCMBOX_SNDNIC_PROD_IDX_8       0x000059c0 /* 64-bit */
1254 #define GRCMBOX_SNDNIC_PROD_IDX_9       0x000059c8 /* 64-bit */
1255 #define GRCMBOX_SNDNIC_PROD_IDX_10      0x000059d0 /* 64-bit */
1256 #define GRCMBOX_SNDNIC_PROD_IDX_11      0x000059d8 /* 64-bit */
1257 #define GRCMBOX_SNDNIC_PROD_IDX_12      0x000059e0 /* 64-bit */
1258 #define GRCMBOX_SNDNIC_PROD_IDX_13      0x000059e8 /* 64-bit */
1259 #define GRCMBOX_SNDNIC_PROD_IDX_14      0x000059f0 /* 64-bit */
1260 #define GRCMBOX_SNDNIC_PROD_IDX_15      0x000059f8 /* 64-bit */
1261 #define GRCMBOX_HIGH_PRIO_EV_VECTOR     0x00005a00
1262 #define GRCMBOX_HIGH_PRIO_EV_MASK       0x00005a04
1263 #define GRCMBOX_LOW_PRIO_EV_VEC         0x00005a08
1264 #define GRCMBOX_LOW_PRIO_EV_MASK        0x00005a0c
1265 /* 0x5a10 --> 0x5c00 */
1266
1267 /* Flow Through queues */
1268 #define FTQ_RESET                       0x00005c00
1269 /* 0x5c04 --> 0x5c10 unused */
1270 #define FTQ_DMA_NORM_READ_CTL           0x00005c10
1271 #define FTQ_DMA_NORM_READ_FULL_CNT      0x00005c14
1272 #define FTQ_DMA_NORM_READ_FIFO_ENQDEQ   0x00005c18
1273 #define FTQ_DMA_NORM_READ_WRITE_PEEK    0x00005c1c
1274 #define FTQ_DMA_HIGH_READ_CTL           0x00005c20
1275 #define FTQ_DMA_HIGH_READ_FULL_CNT      0x00005c24
1276 #define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ   0x00005c28
1277 #define FTQ_DMA_HIGH_READ_WRITE_PEEK    0x00005c2c
1278 #define FTQ_DMA_COMP_DISC_CTL           0x00005c30
1279 #define FTQ_DMA_COMP_DISC_FULL_CNT      0x00005c34
1280 #define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ   0x00005c38
1281 #define FTQ_DMA_COMP_DISC_WRITE_PEEK    0x00005c3c
1282 #define FTQ_SEND_BD_COMP_CTL            0x00005c40
1283 #define FTQ_SEND_BD_COMP_FULL_CNT       0x00005c44
1284 #define FTQ_SEND_BD_COMP_FIFO_ENQDEQ    0x00005c48
1285 #define FTQ_SEND_BD_COMP_WRITE_PEEK     0x00005c4c
1286 #define FTQ_SEND_DATA_INIT_CTL          0x00005c50
1287 #define FTQ_SEND_DATA_INIT_FULL_CNT     0x00005c54
1288 #define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ  0x00005c58
1289 #define FTQ_SEND_DATA_INIT_WRITE_PEEK   0x00005c5c
1290 #define FTQ_DMA_NORM_WRITE_CTL          0x00005c60
1291 #define FTQ_DMA_NORM_WRITE_FULL_CNT     0x00005c64
1292 #define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ  0x00005c68
1293 #define FTQ_DMA_NORM_WRITE_WRITE_PEEK   0x00005c6c
1294 #define FTQ_DMA_HIGH_WRITE_CTL          0x00005c70
1295 #define FTQ_DMA_HIGH_WRITE_FULL_CNT     0x00005c74
1296 #define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ  0x00005c78
1297 #define FTQ_DMA_HIGH_WRITE_WRITE_PEEK   0x00005c7c
1298 #define FTQ_SWTYPE1_CTL                 0x00005c80
1299 #define FTQ_SWTYPE1_FULL_CNT            0x00005c84
1300 #define FTQ_SWTYPE1_FIFO_ENQDEQ         0x00005c88
1301 #define FTQ_SWTYPE1_WRITE_PEEK          0x00005c8c
1302 #define FTQ_SEND_DATA_COMP_CTL          0x00005c90
1303 #define FTQ_SEND_DATA_COMP_FULL_CNT     0x00005c94
1304 #define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ  0x00005c98
1305 #define FTQ_SEND_DATA_COMP_WRITE_PEEK   0x00005c9c
1306 #define FTQ_HOST_COAL_CTL               0x00005ca0
1307 #define FTQ_HOST_COAL_FULL_CNT          0x00005ca4
1308 #define FTQ_HOST_COAL_FIFO_ENQDEQ       0x00005ca8
1309 #define FTQ_HOST_COAL_WRITE_PEEK        0x00005cac
1310 #define FTQ_MAC_TX_CTL                  0x00005cb0
1311 #define FTQ_MAC_TX_FULL_CNT             0x00005cb4
1312 #define FTQ_MAC_TX_FIFO_ENQDEQ          0x00005cb8
1313 #define FTQ_MAC_TX_WRITE_PEEK           0x00005cbc
1314 #define FTQ_MB_FREE_CTL                 0x00005cc0
1315 #define FTQ_MB_FREE_FULL_CNT            0x00005cc4
1316 #define FTQ_MB_FREE_FIFO_ENQDEQ         0x00005cc8
1317 #define FTQ_MB_FREE_WRITE_PEEK          0x00005ccc
1318 #define FTQ_RCVBD_COMP_CTL              0x00005cd0
1319 #define FTQ_RCVBD_COMP_FULL_CNT         0x00005cd4
1320 #define FTQ_RCVBD_COMP_FIFO_ENQDEQ      0x00005cd8
1321 #define FTQ_RCVBD_COMP_WRITE_PEEK       0x00005cdc
1322 #define FTQ_RCVLST_PLMT_CTL             0x00005ce0
1323 #define FTQ_RCVLST_PLMT_FULL_CNT        0x00005ce4
1324 #define FTQ_RCVLST_PLMT_FIFO_ENQDEQ     0x00005ce8
1325 #define FTQ_RCVLST_PLMT_WRITE_PEEK      0x00005cec
1326 #define FTQ_RCVDATA_INI_CTL             0x00005cf0
1327 #define FTQ_RCVDATA_INI_FULL_CNT        0x00005cf4
1328 #define FTQ_RCVDATA_INI_FIFO_ENQDEQ     0x00005cf8
1329 #define FTQ_RCVDATA_INI_WRITE_PEEK      0x00005cfc
1330 #define FTQ_RCVDATA_COMP_CTL            0x00005d00
1331 #define FTQ_RCVDATA_COMP_FULL_CNT       0x00005d04
1332 #define FTQ_RCVDATA_COMP_FIFO_ENQDEQ    0x00005d08
1333 #define FTQ_RCVDATA_COMP_WRITE_PEEK     0x00005d0c
1334 #define FTQ_SWTYPE2_CTL                 0x00005d10
1335 #define FTQ_SWTYPE2_FULL_CNT            0x00005d14
1336 #define FTQ_SWTYPE2_FIFO_ENQDEQ         0x00005d18
1337 #define FTQ_SWTYPE2_WRITE_PEEK          0x00005d1c
1338 /* 0x5d20 --> 0x6000 unused */
1339
1340 /* Message signaled interrupt registers */
1341 #define MSGINT_MODE                     0x00006000
1342 #define  MSGINT_MODE_RESET               0x00000001
1343 #define  MSGINT_MODE_ENABLE              0x00000002
1344 #define MSGINT_STATUS                   0x00006004
1345 #define MSGINT_FIFO                     0x00006008
1346 /* 0x600c --> 0x6400 unused */
1347
1348 /* DMA completion registers */
1349 #define DMAC_MODE                       0x00006400
1350 #define  DMAC_MODE_RESET                 0x00000001
1351 #define  DMAC_MODE_ENABLE                0x00000002
1352 /* 0x6404 --> 0x6800 unused */
1353
1354 /* GRC registers */
1355 #define GRC_MODE                        0x00006800
1356 #define  GRC_MODE_UPD_ON_COAL           0x00000001
1357 #define  GRC_MODE_BSWAP_NONFRM_DATA     0x00000002
1358 #define  GRC_MODE_WSWAP_NONFRM_DATA     0x00000004
1359 #define  GRC_MODE_BSWAP_DATA            0x00000010
1360 #define  GRC_MODE_WSWAP_DATA            0x00000020
1361 #define  GRC_MODE_SPLITHDR              0x00000100
1362 #define  GRC_MODE_NOFRM_CRACKING        0x00000200
1363 #define  GRC_MODE_INCL_CRC              0x00000400
1364 #define  GRC_MODE_ALLOW_BAD_FRMS        0x00000800
1365 #define  GRC_MODE_NOIRQ_ON_SENDS        0x00002000
1366 #define  GRC_MODE_NOIRQ_ON_RCV          0x00004000
1367 #define  GRC_MODE_FORCE_PCI32BIT        0x00008000
1368 #define  GRC_MODE_HOST_STACKUP          0x00010000
1369 #define  GRC_MODE_HOST_SENDBDS          0x00020000
1370 #define  GRC_MODE_NO_TX_PHDR_CSUM       0x00100000
1371 #define  GRC_MODE_NVRAM_WR_ENABLE       0x00200000
1372 #define  GRC_MODE_NO_RX_PHDR_CSUM       0x00800000
1373 #define  GRC_MODE_IRQ_ON_TX_CPU_ATTN    0x01000000
1374 #define  GRC_MODE_IRQ_ON_RX_CPU_ATTN    0x02000000
1375 #define  GRC_MODE_IRQ_ON_MAC_ATTN       0x04000000
1376 #define  GRC_MODE_IRQ_ON_DMA_ATTN       0x08000000
1377 #define  GRC_MODE_IRQ_ON_FLOW_ATTN      0x10000000
1378 #define  GRC_MODE_4X_NIC_SEND_RINGS     0x20000000
1379 #define  GRC_MODE_MCAST_FRM_ENABLE      0x40000000
1380 #define GRC_MISC_CFG                    0x00006804
1381 #define  GRC_MISC_CFG_CORECLK_RESET     0x00000001
1382 #define  GRC_MISC_CFG_PRESCALAR_MASK    0x000000fe
1383 #define  GRC_MISC_CFG_PRESCALAR_SHIFT   1
1384 #define  GRC_MISC_CFG_BOARD_ID_MASK     0x0001e000
1385 #define  GRC_MISC_CFG_BOARD_ID_5700     0x0001e000
1386 #define  GRC_MISC_CFG_BOARD_ID_5701     0x00000000
1387 #define  GRC_MISC_CFG_BOARD_ID_5702FE   0x00004000
1388 #define  GRC_MISC_CFG_BOARD_ID_5703     0x00000000
1389 #define  GRC_MISC_CFG_BOARD_ID_5703S    0x00002000
1390 #define  GRC_MISC_CFG_BOARD_ID_5704     0x00000000
1391 #define  GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000
1392 #define  GRC_MISC_CFG_BOARD_ID_5704_A2  0x00008000
1393 #define  GRC_MISC_CFG_BOARD_ID_5788     0x00010000
1394 #define  GRC_MISC_CFG_BOARD_ID_5788M    0x00018000
1395 #define  GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000
1396 #define  GRC_MISC_CFG_EPHY_IDDQ         0x00200000
1397 #define  GRC_MISC_CFG_KEEP_GPHY_POWER   0x04000000
1398 #define GRC_LOCAL_CTRL                  0x00006808
1399 #define  GRC_LCLCTRL_INT_ACTIVE         0x00000001
1400 #define  GRC_LCLCTRL_CLEARINT           0x00000002
1401 #define  GRC_LCLCTRL_SETINT             0x00000004
1402 #define  GRC_LCLCTRL_INT_ON_ATTN        0x00000008
1403 #define  GRC_LCLCTRL_GPIO_UART_SEL      0x00000010      /* 5755 only */
1404 #define  GRC_LCLCTRL_USE_SIG_DETECT     0x00000010      /* 5714/5780 only */
1405 #define  GRC_LCLCTRL_USE_EXT_SIG_DETECT 0x00000020      /* 5714/5780 only */
1406 #define  GRC_LCLCTRL_GPIO_INPUT3        0x00000020
1407 #define  GRC_LCLCTRL_GPIO_OE3           0x00000040
1408 #define  GRC_LCLCTRL_GPIO_OUTPUT3       0x00000080
1409 #define  GRC_LCLCTRL_GPIO_INPUT0        0x00000100
1410 #define  GRC_LCLCTRL_GPIO_INPUT1        0x00000200
1411 #define  GRC_LCLCTRL_GPIO_INPUT2        0x00000400
1412 #define  GRC_LCLCTRL_GPIO_OE0           0x00000800
1413 #define  GRC_LCLCTRL_GPIO_OE1           0x00001000
1414 #define  GRC_LCLCTRL_GPIO_OE2           0x00002000
1415 #define  GRC_LCLCTRL_GPIO_OUTPUT0       0x00004000
1416 #define  GRC_LCLCTRL_GPIO_OUTPUT1       0x00008000
1417 #define  GRC_LCLCTRL_GPIO_OUTPUT2       0x00010000
1418 #define  GRC_LCLCTRL_EXTMEM_ENABLE      0x00020000
1419 #define  GRC_LCLCTRL_MEMSZ_MASK         0x001c0000
1420 #define  GRC_LCLCTRL_MEMSZ_256K         0x00000000
1421 #define  GRC_LCLCTRL_MEMSZ_512K         0x00040000
1422 #define  GRC_LCLCTRL_MEMSZ_1M           0x00080000
1423 #define  GRC_LCLCTRL_MEMSZ_2M           0x000c0000
1424 #define  GRC_LCLCTRL_MEMSZ_4M           0x00100000
1425 #define  GRC_LCLCTRL_MEMSZ_8M           0x00140000
1426 #define  GRC_LCLCTRL_MEMSZ_16M          0x00180000
1427 #define  GRC_LCLCTRL_BANK_SELECT        0x00200000
1428 #define  GRC_LCLCTRL_SSRAM_TYPE         0x00400000
1429 #define  GRC_LCLCTRL_AUTO_SEEPROM       0x01000000
1430 #define GRC_TIMER                       0x0000680c
1431 #define GRC_RX_CPU_EVENT                0x00006810
1432 #define  GRC_RX_CPU_DRIVER_EVENT        0x00004000
1433 #define GRC_RX_TIMER_REF                0x00006814
1434 #define GRC_RX_CPU_SEM                  0x00006818
1435 #define GRC_REMOTE_RX_CPU_ATTN          0x0000681c
1436 #define GRC_TX_CPU_EVENT                0x00006820
1437 #define GRC_TX_TIMER_REF                0x00006824
1438 #define GRC_TX_CPU_SEM                  0x00006828
1439 #define GRC_REMOTE_TX_CPU_ATTN          0x0000682c
1440 #define GRC_MEM_POWER_UP                0x00006830 /* 64-bit */
1441 #define GRC_EEPROM_ADDR                 0x00006838
1442 #define  EEPROM_ADDR_WRITE              0x00000000
1443 #define  EEPROM_ADDR_READ               0x80000000
1444 #define  EEPROM_ADDR_COMPLETE           0x40000000
1445 #define  EEPROM_ADDR_FSM_RESET          0x20000000
1446 #define  EEPROM_ADDR_DEVID_MASK         0x1c000000
1447 #define  EEPROM_ADDR_DEVID_SHIFT        26
1448 #define  EEPROM_ADDR_START              0x02000000
1449 #define  EEPROM_ADDR_CLKPERD_SHIFT      16
1450 #define  EEPROM_ADDR_ADDR_MASK          0x0000ffff
1451 #define  EEPROM_ADDR_ADDR_SHIFT         0
1452 #define  EEPROM_DEFAULT_CLOCK_PERIOD    0x60
1453 #define  EEPROM_CHIP_SIZE               (64 * 1024)
1454 #define GRC_EEPROM_DATA                 0x0000683c
1455 #define GRC_EEPROM_CTRL                 0x00006840
1456 #define GRC_MDI_CTRL                    0x00006844
1457 #define GRC_SEEPROM_DELAY               0x00006848
1458 /* 0x684c --> 0x6890 unused */
1459 #define GRC_VCPU_EXT_CTRL               0x00006890
1460 #define GRC_VCPU_EXT_CTRL_HALT_CPU       0x00400000
1461 #define GRC_VCPU_EXT_CTRL_DISABLE_WOL    0x20000000
1462 #define GRC_FASTBOOT_PC                 0x00006894      /* 5752, 5755, 5787 */
1463
1464 /* 0x6c00 --> 0x7000 unused */
1465
1466 /* NVRAM Control registers */
1467 #define NVRAM_CMD                       0x00007000
1468 #define  NVRAM_CMD_RESET                 0x00000001
1469 #define  NVRAM_CMD_DONE                  0x00000008
1470 #define  NVRAM_CMD_GO                    0x00000010
1471 #define  NVRAM_CMD_WR                    0x00000020
1472 #define  NVRAM_CMD_RD                    0x00000000
1473 #define  NVRAM_CMD_ERASE                 0x00000040
1474 #define  NVRAM_CMD_FIRST                 0x00000080
1475 #define  NVRAM_CMD_LAST                  0x00000100
1476 #define  NVRAM_CMD_WREN                  0x00010000
1477 #define  NVRAM_CMD_WRDI                  0x00020000
1478 #define NVRAM_STAT                      0x00007004
1479 #define NVRAM_WRDATA                    0x00007008
1480 #define NVRAM_ADDR                      0x0000700c
1481 #define  NVRAM_ADDR_MSK                 0x00ffffff
1482 #define NVRAM_RDDATA                    0x00007010
1483 #define NVRAM_CFG1                      0x00007014
1484 #define  NVRAM_CFG1_FLASHIF_ENAB         0x00000001
1485 #define  NVRAM_CFG1_BUFFERED_MODE        0x00000002
1486 #define  NVRAM_CFG1_PASS_THRU            0x00000004
1487 #define  NVRAM_CFG1_STATUS_BITS          0x00000070
1488 #define  NVRAM_CFG1_BIT_BANG             0x00000008
1489 #define  NVRAM_CFG1_FLASH_SIZE           0x02000000
1490 #define  NVRAM_CFG1_COMPAT_BYPASS        0x80000000
1491 #define  NVRAM_CFG1_VENDOR_MASK          0x03000003
1492 #define  FLASH_VENDOR_ATMEL_EEPROM       0x02000000
1493 #define  FLASH_VENDOR_ATMEL_FLASH_BUFFERED       0x02000003
1494 #define  FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED     0x00000003
1495 #define  FLASH_VENDOR_ST                         0x03000001
1496 #define  FLASH_VENDOR_SAIFUN             0x01000003
1497 #define  FLASH_VENDOR_SST_SMALL          0x00000001
1498 #define  FLASH_VENDOR_SST_LARGE          0x02000001
1499 #define  NVRAM_CFG1_5752VENDOR_MASK      0x03c00003
1500 #define  FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ     0x00000000
1501 #define  FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ    0x02000000
1502 #define  FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED   0x02000003
1503 #define  FLASH_5752VENDOR_ST_M45PE10     0x02400000
1504 #define  FLASH_5752VENDOR_ST_M45PE20     0x02400002
1505 #define  FLASH_5752VENDOR_ST_M45PE40     0x02400001
1506 #define  FLASH_5755VENDOR_ATMEL_FLASH_1  0x03400001
1507 #define  FLASH_5755VENDOR_ATMEL_FLASH_2  0x03400002
1508 #define  FLASH_5755VENDOR_ATMEL_FLASH_3  0x03400000
1509 #define  FLASH_5755VENDOR_ATMEL_FLASH_4  0x00000003
1510 #define  FLASH_5755VENDOR_ATMEL_FLASH_5  0x02000003
1511 #define  FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ     0x03c00003
1512 #define  FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ    0x03c00002
1513 #define  FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ     0x03000003
1514 #define  FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ    0x03000002
1515 #define  FLASH_5787VENDOR_MICRO_EEPROM_64KHZ     0x03000000
1516 #define  FLASH_5787VENDOR_MICRO_EEPROM_376KHZ    0x02000000
1517 #define  FLASH_5761VENDOR_ATMEL_MDB021D  0x00800003
1518 #define  FLASH_5761VENDOR_ATMEL_MDB041D  0x00800000
1519 #define  FLASH_5761VENDOR_ATMEL_MDB081D  0x00800002
1520 #define  FLASH_5761VENDOR_ATMEL_MDB161D  0x00800001
1521 #define  FLASH_5761VENDOR_ATMEL_ADB021D  0x00000003
1522 #define  FLASH_5761VENDOR_ATMEL_ADB041D  0x00000000
1523 #define  FLASH_5761VENDOR_ATMEL_ADB081D  0x00000002
1524 #define  FLASH_5761VENDOR_ATMEL_ADB161D  0x00000001
1525 #define  FLASH_5761VENDOR_ST_M_M45PE20   0x02800001
1526 #define  FLASH_5761VENDOR_ST_M_M45PE40   0x02800000
1527 #define  FLASH_5761VENDOR_ST_M_M45PE80   0x02800002
1528 #define  FLASH_5761VENDOR_ST_M_M45PE16   0x02800003
1529 #define  FLASH_5761VENDOR_ST_A_M45PE20   0x02000001
1530 #define  FLASH_5761VENDOR_ST_A_M45PE40   0x02000000
1531 #define  FLASH_5761VENDOR_ST_A_M45PE80   0x02000002
1532 #define  FLASH_5761VENDOR_ST_A_M45PE16   0x02000003
1533 #define  NVRAM_CFG1_5752PAGE_SIZE_MASK   0x70000000
1534 #define  FLASH_5752PAGE_SIZE_256         0x00000000
1535 #define  FLASH_5752PAGE_SIZE_512         0x10000000
1536 #define  FLASH_5752PAGE_SIZE_1K          0x20000000
1537 #define  FLASH_5752PAGE_SIZE_2K          0x30000000
1538 #define  FLASH_5752PAGE_SIZE_4K          0x40000000
1539 #define  FLASH_5752PAGE_SIZE_264         0x50000000
1540 #define NVRAM_CFG2                      0x00007018
1541 #define NVRAM_CFG3                      0x0000701c
1542 #define NVRAM_SWARB                     0x00007020
1543 #define  SWARB_REQ_SET0                  0x00000001
1544 #define  SWARB_REQ_SET1                  0x00000002
1545 #define  SWARB_REQ_SET2                  0x00000004
1546 #define  SWARB_REQ_SET3                  0x00000008
1547 #define  SWARB_REQ_CLR0                  0x00000010
1548 #define  SWARB_REQ_CLR1                  0x00000020
1549 #define  SWARB_REQ_CLR2                  0x00000040
1550 #define  SWARB_REQ_CLR3                  0x00000080
1551 #define  SWARB_GNT0                      0x00000100
1552 #define  SWARB_GNT1                      0x00000200
1553 #define  SWARB_GNT2                      0x00000400
1554 #define  SWARB_GNT3                      0x00000800
1555 #define  SWARB_REQ0                      0x00001000
1556 #define  SWARB_REQ1                      0x00002000
1557 #define  SWARB_REQ2                      0x00004000
1558 #define  SWARB_REQ3                      0x00008000
1559 #define NVRAM_ACCESS                    0x00007024
1560 #define  ACCESS_ENABLE                   0x00000001
1561 #define  ACCESS_WR_ENABLE                0x00000002
1562 #define NVRAM_WRITE1                    0x00007028
1563 /* 0x702c unused */
1564
1565 #define NVRAM_ADDR_LOCKOUT              0x00007030
1566 /* 0x7034 --> 0x7500 unused */
1567
1568 #define OTP_MODE                        0x00007500
1569 #define OTP_MODE_OTP_THRU_GRC            0x00000001
1570 #define OTP_CTRL                        0x00007504
1571 #define OTP_CTRL_OTP_PROG_ENABLE         0x00200000
1572 #define OTP_CTRL_OTP_CMD_READ            0x00000000
1573 #define OTP_CTRL_OTP_CMD_INIT            0x00000008
1574 #define OTP_CTRL_OTP_CMD_START           0x00000001
1575 #define OTP_STATUS                      0x00007508
1576 #define OTP_STATUS_CMD_DONE              0x00000001
1577 #define OTP_ADDRESS                     0x0000750c
1578 #define OTP_ADDRESS_MAGIC1               0x000000a0
1579 #define OTP_ADDRESS_MAGIC2               0x00000080
1580 /* 0x7510 unused */
1581
1582 #define OTP_READ_DATA                   0x00007514
1583 /* 0x7518 --> 0x7c04 unused */
1584
1585 #define PCIE_TRANSACTION_CFG            0x00007c04
1586 #define PCIE_TRANS_CFG_1SHOT_MSI         0x20000000
1587 #define PCIE_TRANS_CFG_LOM               0x00000020
1588
1589 #define PCIE_PWR_MGMT_THRESH            0x00007d28
1590 #define PCIE_PWR_MGMT_L1_THRESH_MSK      0x0000ff00
1591
1592
1593 /* OTP bit definitions */
1594 #define TG3_OTP_AGCTGT_MASK             0x000000e0
1595 #define TG3_OTP_AGCTGT_SHIFT            1
1596 #define TG3_OTP_HPFFLTR_MASK            0x00000300
1597 #define TG3_OTP_HPFFLTR_SHIFT           1
1598 #define TG3_OTP_HPFOVER_MASK            0x00000400
1599 #define TG3_OTP_HPFOVER_SHIFT           1
1600 #define TG3_OTP_LPFDIS_MASK             0x00000800
1601 #define TG3_OTP_LPFDIS_SHIFT            11
1602 #define TG3_OTP_VDAC_MASK               0xff000000
1603 #define TG3_OTP_VDAC_SHIFT              24
1604 #define TG3_OTP_10BTAMP_MASK            0x0000f000
1605 #define TG3_OTP_10BTAMP_SHIFT           8
1606 #define TG3_OTP_ROFF_MASK               0x00e00000
1607 #define TG3_OTP_ROFF_SHIFT              11
1608 #define TG3_OTP_RCOFF_MASK              0x001c0000
1609 #define TG3_OTP_RCOFF_SHIFT             16
1610
1611 #define TG3_OTP_DEFAULT                 0x286c1640
1612
1613
1614 #define TG3_EEPROM_MAGIC                0x669955aa
1615 #define TG3_EEPROM_MAGIC_FW             0xa5000000
1616 #define TG3_EEPROM_MAGIC_FW_MSK         0xff000000
1617 #define TG3_EEPROM_SB_FORMAT_MASK       0x00e00000
1618 #define TG3_EEPROM_SB_FORMAT_1          0x00200000
1619 #define TG3_EEPROM_SB_REVISION_MASK     0x001f0000
1620 #define TG3_EEPROM_SB_REVISION_0        0x00000000
1621 #define TG3_EEPROM_SB_REVISION_2        0x00020000
1622 #define TG3_EEPROM_SB_REVISION_3        0x00030000
1623 #define TG3_EEPROM_MAGIC_HW             0xabcd
1624 #define TG3_EEPROM_MAGIC_HW_MSK         0xffff
1625
1626 #define TG3_NVM_DIR_START               0x18
1627 #define TG3_NVM_DIR_END                 0x78
1628 #define TG3_NVM_DIRENT_SIZE             0xc
1629 #define TG3_NVM_DIRTYPE_SHIFT           24
1630 #define TG3_NVM_DIRTYPE_ASFINI          1
1631
1632 /* 32K Window into NIC internal memory */
1633 #define NIC_SRAM_WIN_BASE               0x00008000
1634
1635 /* Offsets into first 32k of NIC internal memory. */
1636 #define NIC_SRAM_PAGE_ZERO              0x00000000
1637 #define NIC_SRAM_SEND_RCB               0x00000100 /* 16 * TG3_BDINFO_... */
1638 #define NIC_SRAM_RCV_RET_RCB            0x00000200 /* 16 * TG3_BDINFO_... */
1639 #define NIC_SRAM_STATS_BLK              0x00000300
1640 #define NIC_SRAM_STATUS_BLK             0x00000b00
1641
1642 #define NIC_SRAM_FIRMWARE_MBOX          0x00000b50
1643 #define  NIC_SRAM_FIRMWARE_MBOX_MAGIC1   0x4B657654
1644 #define  NIC_SRAM_FIRMWARE_MBOX_MAGIC2   0x4861764b /* !dma on linkchg */
1645
1646 #define NIC_SRAM_DATA_SIG               0x00000b54
1647 #define  NIC_SRAM_DATA_SIG_MAGIC         0x4b657654 /* ascii for 'KevT' */
1648
1649 #define NIC_SRAM_DATA_CFG                       0x00000b58
1650 #define  NIC_SRAM_DATA_CFG_LED_MODE_MASK         0x0000000c
1651 #define  NIC_SRAM_DATA_CFG_LED_MODE_MAC          0x00000000
1652 #define  NIC_SRAM_DATA_CFG_LED_MODE_PHY_1        0x00000004
1653 #define  NIC_SRAM_DATA_CFG_LED_MODE_PHY_2        0x00000008
1654 #define  NIC_SRAM_DATA_CFG_PHY_TYPE_MASK         0x00000030
1655 #define  NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN      0x00000000
1656 #define  NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER       0x00000010
1657 #define  NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER        0x00000020
1658 #define  NIC_SRAM_DATA_CFG_WOL_ENABLE            0x00000040
1659 #define  NIC_SRAM_DATA_CFG_ASF_ENABLE            0x00000080
1660 #define  NIC_SRAM_DATA_CFG_EEPROM_WP             0x00000100
1661 #define  NIC_SRAM_DATA_CFG_MINI_PCI              0x00001000
1662 #define  NIC_SRAM_DATA_CFG_FIBER_WOL             0x00004000
1663 #define  NIC_SRAM_DATA_CFG_NO_GPIO2              0x00100000
1664 #define  NIC_SRAM_DATA_CFG_APE_ENABLE            0x00200000
1665
1666 #define NIC_SRAM_DATA_VER                       0x00000b5c
1667 #define  NIC_SRAM_DATA_VER_SHIFT                 16
1668
1669 #define NIC_SRAM_DATA_PHY_ID            0x00000b74
1670 #define  NIC_SRAM_DATA_PHY_ID1_MASK      0xffff0000
1671 #define  NIC_SRAM_DATA_PHY_ID2_MASK      0x0000ffff
1672
1673 #define NIC_SRAM_FW_CMD_MBOX            0x00000b78
1674 #define  FWCMD_NICDRV_ALIVE              0x00000001
1675 #define  FWCMD_NICDRV_PAUSE_FW           0x00000002
1676 #define  FWCMD_NICDRV_IPV4ADDR_CHG       0x00000003
1677 #define  FWCMD_NICDRV_IPV6ADDR_CHG       0x00000004
1678 #define  FWCMD_NICDRV_FIX_DMAR           0x00000005
1679 #define  FWCMD_NICDRV_FIX_DMAW           0x00000006
1680 #define  FWCMD_NICDRV_LINK_UPDATE        0x0000000c
1681 #define  FWCMD_NICDRV_ALIVE2             0x0000000d
1682 #define  FWCMD_NICDRV_ALIVE3             0x0000000e
1683 #define NIC_SRAM_FW_CMD_LEN_MBOX        0x00000b7c
1684 #define NIC_SRAM_FW_CMD_DATA_MBOX       0x00000b80
1685 #define NIC_SRAM_FW_ASF_STATUS_MBOX     0x00000c00
1686 #define NIC_SRAM_FW_DRV_STATE_MBOX      0x00000c04
1687 #define  DRV_STATE_START                 0x00000001
1688 #define  DRV_STATE_START_DONE            0x80000001
1689 #define  DRV_STATE_UNLOAD                0x00000002
1690 #define  DRV_STATE_UNLOAD_DONE           0x80000002
1691 #define  DRV_STATE_WOL                   0x00000003
1692 #define  DRV_STATE_SUSPEND               0x00000004
1693
1694 #define NIC_SRAM_FW_RESET_TYPE_MBOX     0x00000c08
1695
1696 #define NIC_SRAM_MAC_ADDR_HIGH_MBOX     0x00000c14
1697 #define NIC_SRAM_MAC_ADDR_LOW_MBOX      0x00000c18
1698
1699 #define NIC_SRAM_WOL_MBOX               0x00000d30
1700 #define  WOL_SIGNATURE                   0x474c0000
1701 #define  WOL_DRV_STATE_SHUTDOWN          0x00000001
1702 #define  WOL_DRV_WOL                     0x00000002
1703 #define  WOL_SET_MAGIC_PKT               0x00000004
1704
1705 #define NIC_SRAM_DATA_CFG_2             0x00000d38
1706
1707 #define  SHASTA_EXT_LED_MODE_MASK        0x00018000
1708 #define  SHASTA_EXT_LED_LEGACY           0x00000000
1709 #define  SHASTA_EXT_LED_SHARED           0x00008000
1710 #define  SHASTA_EXT_LED_MAC              0x00010000
1711 #define  SHASTA_EXT_LED_COMBO            0x00018000
1712
1713 #define NIC_SRAM_DATA_CFG_3             0x00000d3c
1714 #define  NIC_SRAM_ASPM_DEBOUNCE          0x00000002
1715
1716 #define NIC_SRAM_RX_MINI_BUFFER_DESC    0x00001000
1717
1718 #define NIC_SRAM_DMA_DESC_POOL_BASE     0x00002000
1719 #define  NIC_SRAM_DMA_DESC_POOL_SIZE     0x00002000
1720 #define NIC_SRAM_TX_BUFFER_DESC         0x00004000 /* 512 entries */
1721 #define NIC_SRAM_RX_BUFFER_DESC         0x00006000 /* 256 entries */
1722 #define NIC_SRAM_RX_JUMBO_BUFFER_DESC   0x00007000 /* 256 entries */
1723 #define NIC_SRAM_MBUF_POOL_BASE         0x00008000
1724 #define  NIC_SRAM_MBUF_POOL_SIZE96       0x00018000
1725 #define  NIC_SRAM_MBUF_POOL_SIZE64       0x00010000
1726 #define  NIC_SRAM_MBUF_POOL_BASE5705    0x00010000
1727 #define  NIC_SRAM_MBUF_POOL_SIZE5705    0x0000e000
1728
1729 /* Currently this is fixed. */
1730 #define PHY_ADDR                0x01
1731
1732 /* Tigon3 specific PHY MII registers. */
1733 #define  TG3_BMCR_SPEED1000             0x0040
1734
1735 #define MII_TG3_CTRL                    0x09 /* 1000-baseT control register */
1736 #define  MII_TG3_CTRL_ADV_1000_HALF     0x0100
1737 #define  MII_TG3_CTRL_ADV_1000_FULL     0x0200
1738 #define  MII_TG3_CTRL_AS_MASTER         0x0800
1739 #define  MII_TG3_CTRL_ENABLE_AS_MASTER  0x1000
1740
1741 #define MII_TG3_EXT_CTRL                0x10 /* Extended control register */
1742 #define  MII_TG3_EXT_CTRL_FIFO_ELASTIC  0x0001
1743 #define  MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002
1744 #define  MII_TG3_EXT_CTRL_FORCE_LED_OFF 0x0008
1745 #define  MII_TG3_EXT_CTRL_TBI           0x8000
1746
1747 #define MII_TG3_EXT_STAT                0x11 /* Extended status register */
1748 #define  MII_TG3_EXT_STAT_LPASS         0x0100
1749
1750 #define MII_TG3_DSP_RW_PORT             0x15 /* DSP coefficient read/write port */
1751
1752 #define MII_TG3_EPHY_PTEST              0x17 /* 5906 PHY register */
1753 #define MII_TG3_DSP_ADDRESS             0x17 /* DSP address register */
1754
1755 #define MII_TG3_DSP_TAP1                0x0001
1756 #define  MII_TG3_DSP_TAP1_AGCTGT_DFLT   0x0007
1757 #define MII_TG3_DSP_AADJ1CH0            0x001f
1758 #define MII_TG3_DSP_AADJ1CH3            0x601f
1759 #define  MII_TG3_DSP_AADJ1CH3_ADCCKADJ  0x0002
1760 #define MII_TG3_DSP_EXP8                0x0708
1761 #define  MII_TG3_DSP_EXP8_REJ2MHz       0x0001
1762 #define  MII_TG3_DSP_EXP8_AEDW          0x0200
1763 #define MII_TG3_DSP_EXP75               0x0f75
1764 #define MII_TG3_DSP_EXP96               0x0f96
1765 #define MII_TG3_DSP_EXP97               0x0f97
1766
1767 #define MII_TG3_AUX_CTRL                0x18 /* auxilliary control register */
1768
1769 #define MII_TG3_AUXCTL_MISC_WREN        0x8000
1770 #define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200
1771 #define MII_TG3_AUXCTL_MISC_RDSEL_MISC  0x7000
1772 #define MII_TG3_AUXCTL_SHDWSEL_MISC     0x0007
1773
1774 #define MII_TG3_AUXCTL_ACTL_SMDSP_ENA   0x0800
1775 #define MII_TG3_AUXCTL_ACTL_TX_6DB      0x0400
1776 #define MII_TG3_AUXCTL_SHDWSEL_AUXCTL   0x0000
1777
1778 #define MII_TG3_AUX_STAT                0x19 /* auxilliary status register */
1779 #define MII_TG3_AUX_STAT_LPASS          0x0004
1780 #define MII_TG3_AUX_STAT_SPDMASK        0x0700
1781 #define MII_TG3_AUX_STAT_10HALF         0x0100
1782 #define MII_TG3_AUX_STAT_10FULL         0x0200
1783 #define MII_TG3_AUX_STAT_100HALF        0x0300
1784 #define MII_TG3_AUX_STAT_100_4          0x0400
1785 #define MII_TG3_AUX_STAT_100FULL        0x0500
1786 #define MII_TG3_AUX_STAT_1000HALF       0x0600
1787 #define MII_TG3_AUX_STAT_1000FULL       0x0700
1788 #define MII_TG3_AUX_STAT_100            0x0008
1789 #define MII_TG3_AUX_STAT_FULL           0x0001
1790
1791 #define MII_TG3_ISTAT                   0x1a /* IRQ status register */
1792 #define MII_TG3_IMASK                   0x1b /* IRQ mask register */
1793
1794 #define MII_TG3_MISC_SHDW               0x1c
1795 #define MII_TG3_MISC_SHDW_WREN          0x8000
1796 #define MII_TG3_MISC_SHDW_APD_SEL       0x2800
1797
1798 #define MII_TG3_MISC_SHDW_APD_WKTM_84MS 0x0001
1799
1800 /* ISTAT/IMASK event bits */
1801 #define MII_TG3_INT_LINKCHG             0x0002
1802 #define MII_TG3_INT_SPEEDCHG            0x0004
1803 #define MII_TG3_INT_DUPLEXCHG           0x0008
1804 #define MII_TG3_INT_ANEG_PAGE_RX        0x0400
1805
1806 #define MII_TG3_MISC_SHDW               0x1c
1807 #define MII_TG3_MISC_SHDW_WREN          0x8000
1808 #define MII_TG3_MISC_SHDW_SCR5_SEL      0x1400
1809 #define MII_TG3_MISC_SHDW_APD_SEL       0x2800
1810
1811 #define MII_TG3_MISC_SHDW_SCR5_C125OE   0x0001
1812 #define MII_TG3_MISC_SHDW_SCR5_DLLAPD   0x0002
1813 #define MII_TG3_MISC_SHDW_SCR5_SDTL     0x0004
1814 #define MII_TG3_MISC_SHDW_SCR5_DLPTLM   0x0008
1815 #define MII_TG3_MISC_SHDW_SCR5_LPED     0x0010
1816
1817 #define MII_TG3_MISC_SHDW_APD_WKTM_84MS 0x0001
1818 #define MII_TG3_MISC_SHDW_APD_ENABLE    0x0020
1819
1820 #define MII_TG3_EPHY_TEST               0x1f /* 5906 PHY register */
1821 #define MII_TG3_EPHY_SHADOW_EN          0x80
1822
1823 #define MII_TG3_EPHYTST_MISCCTRL        0x10 /* 5906 EPHY misc ctrl shadow register */
1824 #define MII_TG3_EPHYTST_MISCCTRL_MDIX   0x4000
1825
1826 #define MII_TG3_TEST1                   0x1e
1827 #define MII_TG3_TEST1_TRIM_EN           0x0010
1828 #define MII_TG3_TEST1_CRC_EN            0x8000
1829
1830 /* APE registers.  Accessible through BAR1 */
1831 #define TG3_APE_EVENT                   0x000c
1832 #define  APE_EVENT_1                     0x00000001
1833 #define TG3_APE_LOCK_REQ                0x002c
1834 #define  APE_LOCK_REQ_DRIVER             0x00001000
1835 #define TG3_APE_LOCK_GRANT              0x004c
1836 #define  APE_LOCK_GRANT_DRIVER           0x00001000
1837 #define TG3_APE_SEG_SIG                 0x4000
1838 #define  APE_SEG_SIG_MAGIC               0x41504521
1839
1840 /* APE shared memory.  Accessible through BAR1 */
1841 #define TG3_APE_FW_STATUS               0x400c
1842 #define  APE_FW_STATUS_READY             0x00000100
1843 #define TG3_APE_HOST_SEG_SIG            0x4200
1844 #define  APE_HOST_SEG_SIG_MAGIC          0x484f5354
1845 #define TG3_APE_HOST_SEG_LEN            0x4204
1846 #define  APE_HOST_SEG_LEN_MAGIC          0x0000001c
1847 #define TG3_APE_HOST_INIT_COUNT         0x4208
1848 #define TG3_APE_HOST_DRIVER_ID          0x420c
1849 #define  APE_HOST_DRIVER_ID_MAGIC        0xf0035100
1850 #define TG3_APE_HOST_BEHAVIOR           0x4210
1851 #define  APE_HOST_BEHAV_NO_PHYLOCK       0x00000001
1852 #define TG3_APE_HOST_HEARTBEAT_INT_MS   0x4214
1853 #define  APE_HOST_HEARTBEAT_INT_DISABLE  0
1854 #define  APE_HOST_HEARTBEAT_INT_5SEC     5000
1855 #define TG3_APE_HOST_HEARTBEAT_COUNT    0x4218
1856
1857 #define TG3_APE_EVENT_STATUS            0x4300
1858
1859 #define  APE_EVENT_STATUS_DRIVER_EVNT    0x00000010
1860 #define  APE_EVENT_STATUS_STATE_CHNGE    0x00000500
1861 #define  APE_EVENT_STATUS_STATE_START    0x00010000
1862 #define  APE_EVENT_STATUS_STATE_UNLOAD   0x00020000
1863 #define  APE_EVENT_STATUS_STATE_WOL      0x00030000
1864 #define  APE_EVENT_STATUS_STATE_SUSPEND  0x00040000
1865 #define  APE_EVENT_STATUS_EVENT_PENDING  0x80000000
1866
1867 /* APE convenience enumerations. */
1868 #define TG3_APE_LOCK_MEM                4
1869
1870 #define TG3_EEPROM_SB_F1R2_MBA_OFF      0x10
1871
1872
1873 /* There are two ways to manage the TX descriptors on the tigon3.
1874  * Either the descriptors are in host DMA'able memory, or they
1875  * exist only in the cards on-chip SRAM.  All 16 send bds are under
1876  * the same mode, they may not be configured individually.
1877  *
1878  * This driver always uses host memory TX descriptors.
1879  *
1880  * To use host memory TX descriptors:
1881  *      1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register.
1882  *         Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear.
1883  *      2) Allocate DMA'able memory.
1884  *      3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
1885  *         a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory
1886  *            obtained in step 2
1887  *         b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC.
1888  *         c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number
1889  *            of TX descriptors.  Leave flags field clear.
1890  *      4) Access TX descriptors via host memory.  The chip
1891  *         will refetch into local SRAM as needed when producer
1892  *         index mailboxes are updated.
1893  *
1894  * To use on-chip TX descriptors:
1895  *      1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register.
1896  *         Make sure GRC_MODE_HOST_SENDBDS is clear.
1897  *      2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
1898  *         a) Set TG3_BDINFO_HOST_ADDR to zero.
1899  *         b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC
1900  *         c) TG3_BDINFO_MAXLEN_FLAGS is don't care.
1901  *      3) Access TX descriptors directly in on-chip SRAM
1902  *         using normal {read,write}l().  (and not using
1903  *         pointer dereferencing of ioremap()'d memory like
1904  *         the broken Broadcom driver does)
1905  *
1906  * Note that BDINFO_FLAGS_DISABLED should be set in the flags field of
1907  * TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices.
1908  */
1909 struct tg3_tx_buffer_desc {
1910         u32                             addr_hi;
1911         u32                             addr_lo;
1912
1913         u32                             len_flags;
1914 #define TXD_FLAG_TCPUDP_CSUM            0x0001
1915 #define TXD_FLAG_IP_CSUM                0x0002
1916 #define TXD_FLAG_END                    0x0004
1917 #define TXD_FLAG_IP_FRAG                0x0008
1918 #define TXD_FLAG_IP_FRAG_END            0x0010
1919 #define TXD_FLAG_VLAN                   0x0040
1920 #define TXD_FLAG_COAL_NOW               0x0080
1921 #define TXD_FLAG_CPU_PRE_DMA            0x0100
1922 #define TXD_FLAG_CPU_POST_DMA           0x0200
1923 #define TXD_FLAG_ADD_SRC_ADDR           0x1000
1924 #define TXD_FLAG_CHOOSE_SRC_ADDR        0x6000
1925 #define TXD_FLAG_NO_CRC                 0x8000
1926 #define TXD_LEN_SHIFT                   16
1927
1928         u32                             vlan_tag;
1929 #define TXD_VLAN_TAG_SHIFT              0
1930 #define TXD_MSS_SHIFT                   16
1931 };
1932
1933 #define TXD_ADDR                        0x00UL /* 64-bit */
1934 #define TXD_LEN_FLAGS                   0x08UL /* 32-bit (upper 16-bits are len) */
1935 #define TXD_VLAN_TAG                    0x0cUL /* 32-bit (upper 16-bits are tag) */
1936 #define TXD_SIZE                        0x10UL
1937
1938 struct tg3_rx_buffer_desc {
1939         u32                             addr_hi;
1940         u32                             addr_lo;
1941
1942         u32                             idx_len;
1943 #define RXD_IDX_MASK    0xffff0000
1944 #define RXD_IDX_SHIFT   16
1945 #define RXD_LEN_MASK    0x0000ffff
1946 #define RXD_LEN_SHIFT   0
1947
1948         u32                             type_flags;
1949 #define RXD_TYPE_SHIFT  16
1950 #define RXD_FLAGS_SHIFT 0
1951
1952 #define RXD_FLAG_END                    0x0004
1953 #define RXD_FLAG_MINI                   0x0800
1954 #define RXD_FLAG_JUMBO                  0x0020
1955 #define RXD_FLAG_VLAN                   0x0040
1956 #define RXD_FLAG_ERROR                  0x0400
1957 #define RXD_FLAG_IP_CSUM                0x1000
1958 #define RXD_FLAG_TCPUDP_CSUM            0x2000
1959 #define RXD_FLAG_IS_TCP                 0x4000
1960
1961         u32                             ip_tcp_csum;
1962 #define RXD_IPCSUM_MASK         0xffff0000
1963 #define RXD_IPCSUM_SHIFT        16
1964 #define RXD_TCPCSUM_MASK        0x0000ffff
1965 #define RXD_TCPCSUM_SHIFT       0
1966
1967         u32                             err_vlan;
1968
1969 #define RXD_VLAN_MASK                   0x0000ffff
1970
1971 #define RXD_ERR_BAD_CRC                 0x00010000
1972 #define RXD_ERR_COLLISION               0x00020000
1973 #define RXD_ERR_LINK_LOST               0x00040000
1974 #define RXD_ERR_PHY_DECODE              0x00080000
1975 #define RXD_ERR_ODD_NIBBLE_RCVD_MII     0x00100000
1976 #define RXD_ERR_MAC_ABRT                0x00200000
1977 #define RXD_ERR_TOO_SMALL               0x00400000
1978 #define RXD_ERR_NO_RESOURCES            0x00800000
1979 #define RXD_ERR_HUGE_FRAME              0x01000000
1980 #define RXD_ERR_MASK                    0xffff0000
1981
1982         u32                             reserved;
1983         u32                             opaque;
1984 #define RXD_OPAQUE_INDEX_MASK           0x0000ffff
1985 #define RXD_OPAQUE_INDEX_SHIFT          0
1986 #define RXD_OPAQUE_RING_STD             0x00010000
1987 #define RXD_OPAQUE_RING_JUMBO           0x00020000
1988 #define RXD_OPAQUE_RING_MINI            0x00040000
1989 #define RXD_OPAQUE_RING_MASK            0x00070000
1990 };
1991
1992 struct tg3_ext_rx_buffer_desc {
1993         struct {
1994                 u32                     addr_hi;
1995                 u32                     addr_lo;
1996         }                               addrlist[3];
1997         u32                             len2_len1;
1998         u32                             resv_len3;
1999         struct tg3_rx_buffer_desc       std;
2000 };
2001
2002 /* We only use this when testing out the DMA engine
2003  * at probe time.  This is the internal format of buffer
2004  * descriptors used by the chip at NIC_SRAM_DMA_DESCS.
2005  */
2006 struct tg3_internal_buffer_desc {
2007         u32                             addr_hi;
2008         u32                             addr_lo;
2009         u32                             nic_mbuf;
2010         /* XXX FIX THIS */
2011 #ifdef __BIG_ENDIAN
2012         u16                             cqid_sqid;
2013         u16                             len;
2014 #else
2015         u16                             len;
2016         u16                             cqid_sqid;
2017 #endif
2018         u32                             flags;
2019         u32                             __cookie1;
2020         u32                             __cookie2;
2021         u32                             __cookie3;
2022 };
2023
2024 #define TG3_HW_STATUS_SIZE              0x50
2025 struct tg3_hw_status {
2026         u32                             status;
2027 #define SD_STATUS_UPDATED               0x00000001
2028 #define SD_STATUS_LINK_CHG              0x00000002
2029 #define SD_STATUS_ERROR                 0x00000004
2030
2031         u32                             status_tag;
2032
2033 #ifdef __BIG_ENDIAN
2034         u16                             rx_consumer;
2035         u16                             rx_jumbo_consumer;
2036 #else
2037         u16                             rx_jumbo_consumer;
2038         u16                             rx_consumer;
2039 #endif
2040
2041 #ifdef __BIG_ENDIAN
2042         u16                             reserved;
2043         u16                             rx_mini_consumer;
2044 #else
2045         u16                             rx_mini_consumer;
2046         u16                             reserved;
2047 #endif
2048         struct {
2049 #ifdef __BIG_ENDIAN
2050                 u16                     tx_consumer;
2051                 u16                     rx_producer;
2052 #else
2053                 u16                     rx_producer;
2054                 u16                     tx_consumer;
2055 #endif
2056         }                               idx[16];
2057 };
2058
2059 typedef struct {
2060         u32 high, low;
2061 } tg3_stat64_t;
2062
2063 struct tg3_hw_stats {
2064         u8                              __reserved0[0x400-0x300];
2065
2066         /* Statistics maintained by Receive MAC. */
2067         tg3_stat64_t                    rx_octets;
2068         u64                             __reserved1;
2069         tg3_stat64_t                    rx_fragments;
2070         tg3_stat64_t                    rx_ucast_packets;
2071         tg3_stat64_t                    rx_mcast_packets;
2072         tg3_stat64_t                    rx_bcast_packets;
2073         tg3_stat64_t                    rx_fcs_errors;
2074         tg3_stat64_t                    rx_align_errors;
2075         tg3_stat64_t                    rx_xon_pause_rcvd;
2076         tg3_stat64_t                    rx_xoff_pause_rcvd;
2077         tg3_stat64_t                    rx_mac_ctrl_rcvd;
2078         tg3_stat64_t                    rx_xoff_entered;
2079         tg3_stat64_t                    rx_frame_too_long_errors;
2080         tg3_stat64_t                    rx_jabbers;
2081         tg3_stat64_t                    rx_undersize_packets;
2082         tg3_stat64_t                    rx_in_length_errors;
2083         tg3_stat64_t                    rx_out_length_errors;
2084         tg3_stat64_t                    rx_64_or_less_octet_packets;
2085         tg3_stat64_t                    rx_65_to_127_octet_packets;
2086         tg3_stat64_t                    rx_128_to_255_octet_packets;
2087         tg3_stat64_t                    rx_256_to_511_octet_packets;
2088         tg3_stat64_t                    rx_512_to_1023_octet_packets;
2089         tg3_stat64_t                    rx_1024_to_1522_octet_packets;
2090         tg3_stat64_t                    rx_1523_to_2047_octet_packets;
2091         tg3_stat64_t                    rx_2048_to_4095_octet_packets;
2092         tg3_stat64_t                    rx_4096_to_8191_octet_packets;
2093         tg3_stat64_t                    rx_8192_to_9022_octet_packets;
2094
2095         u64                             __unused0[37];
2096
2097         /* Statistics maintained by Transmit MAC. */
2098         tg3_stat64_t                    tx_octets;
2099         u64                             __reserved2;
2100         tg3_stat64_t                    tx_collisions;
2101         tg3_stat64_t                    tx_xon_sent;
2102         tg3_stat64_t                    tx_xoff_sent;
2103         tg3_stat64_t                    tx_flow_control;
2104         tg3_stat64_t                    tx_mac_errors;
2105         tg3_stat64_t                    tx_single_collisions;
2106         tg3_stat64_t                    tx_mult_collisions;
2107         tg3_stat64_t                    tx_deferred;
2108         u64                             __reserved3;
2109         tg3_stat64_t                    tx_excessive_collisions;
2110         tg3_stat64_t                    tx_late_collisions;
2111         tg3_stat64_t                    tx_collide_2times;
2112         tg3_stat64_t                    tx_collide_3times;
2113         tg3_stat64_t                    tx_collide_4times;
2114         tg3_stat64_t                    tx_collide_5times;
2115         tg3_stat64_t                    tx_collide_6times;
2116         tg3_stat64_t                    tx_collide_7times;
2117         tg3_stat64_t                    tx_collide_8times;
2118         tg3_stat64_t                    tx_collide_9times;
2119         tg3_stat64_t                    tx_collide_10times;
2120         tg3_stat64_t                    tx_collide_11times;
2121         tg3_stat64_t                    tx_collide_12times;
2122         tg3_stat64_t                    tx_collide_13times;
2123         tg3_stat64_t                    tx_collide_14times;
2124         tg3_stat64_t                    tx_collide_15times;
2125         tg3_stat64_t                    tx_ucast_packets;
2126         tg3_stat64_t                    tx_mcast_packets;
2127         tg3_stat64_t                    tx_bcast_packets;
2128         tg3_stat64_t                    tx_carrier_sense_errors;
2129         tg3_stat64_t                    tx_discards;
2130         tg3_stat64_t                    tx_errors;
2131
2132         u64                             __unused1[31];
2133
2134         /* Statistics maintained by Receive List Placement. */
2135         tg3_stat64_t                    COS_rx_packets[16];
2136         tg3_stat64_t                    COS_rx_filter_dropped;
2137         tg3_stat64_t                    dma_writeq_full;
2138         tg3_stat64_t                    dma_write_prioq_full;
2139         tg3_stat64_t                    rxbds_empty;
2140         tg3_stat64_t                    rx_discards;
2141         tg3_stat64_t                    rx_errors;
2142         tg3_stat64_t                    rx_threshold_hit;
2143
2144         u64                             __unused2[9];
2145
2146         /* Statistics maintained by Send Data Initiator. */
2147         tg3_stat64_t                    COS_out_packets[16];
2148         tg3_stat64_t                    dma_readq_full;
2149         tg3_stat64_t                    dma_read_prioq_full;
2150         tg3_stat64_t                    tx_comp_queue_full;
2151
2152         /* Statistics maintained by Host Coalescing. */
2153         tg3_stat64_t                    ring_set_send_prod_index;
2154         tg3_stat64_t                    ring_status_update;
2155         tg3_stat64_t                    nic_irqs;
2156         tg3_stat64_t                    nic_avoided_irqs;
2157         tg3_stat64_t                    nic_tx_threshold_hit;
2158
2159         u8                              __reserved4[0xb00-0x9c0];
2160 };
2161
2162 /* 'mapping' is superfluous as the chip does not write into
2163  * the tx/rx post rings so we could just fetch it from there.
2164  * But the cache behavior is better how we are doing it now.
2165  */
2166 struct ring_info {
2167         struct sk_buff                  *skb;
2168         DECLARE_PCI_UNMAP_ADDR(mapping)
2169 };
2170
2171 struct tx_ring_info {
2172         struct sk_buff                  *skb;
2173         DECLARE_PCI_UNMAP_ADDR(mapping)
2174         u32                             prev_vlan_tag;
2175 };
2176
2177 struct tg3_config_info {
2178         u32                             flags;
2179 };
2180
2181 struct tg3_link_config {
2182         /* Describes what we're trying to get. */
2183         u32                             advertising;
2184         u16                             speed;
2185         u8                              duplex;
2186         u8                              autoneg;
2187         u8                              flowctrl;
2188 #define TG3_FLOW_CTRL_TX                0x01
2189 #define TG3_FLOW_CTRL_RX                0x02
2190
2191         /* Describes what we actually have. */
2192         u8                              active_flowctrl;
2193
2194         u8                              active_duplex;
2195 #define SPEED_INVALID           0xffff
2196 #define DUPLEX_INVALID          0xff
2197 #define AUTONEG_INVALID         0xff
2198         u16                             active_speed;
2199
2200         /* When we go in and out of low power mode we need
2201          * to swap with this state.
2202          */
2203         int                             phy_is_low_power;
2204         u16                             orig_speed;
2205         u8                              orig_duplex;
2206         u8                              orig_autoneg;
2207 };
2208
2209 struct tg3_bufmgr_config {
2210         u32             mbuf_read_dma_low_water;
2211         u32             mbuf_mac_rx_low_water;
2212         u32             mbuf_high_water;
2213
2214         u32             mbuf_read_dma_low_water_jumbo;
2215         u32             mbuf_mac_rx_low_water_jumbo;
2216         u32             mbuf_high_water_jumbo;
2217
2218         u32             dma_low_water;
2219         u32             dma_high_water;
2220 };
2221
2222 struct tg3_ethtool_stats {
2223         /* Statistics maintained by Receive MAC. */
2224         u64             rx_octets;
2225         u64             rx_fragments;
2226         u64             rx_ucast_packets;
2227         u64             rx_mcast_packets;
2228         u64             rx_bcast_packets;
2229         u64             rx_fcs_errors;
2230         u64             rx_align_errors;
2231         u64             rx_xon_pause_rcvd;
2232         u64             rx_xoff_pause_rcvd;
2233         u64             rx_mac_ctrl_rcvd;
2234         u64             rx_xoff_entered;
2235         u64             rx_frame_too_long_errors;
2236         u64             rx_jabbers;
2237         u64             rx_undersize_packets;
2238         u64             rx_in_length_errors;
2239         u64             rx_out_length_errors;
2240         u64             rx_64_or_less_octet_packets;
2241         u64             rx_65_to_127_octet_packets;
2242         u64             rx_128_to_255_octet_packets;
2243         u64             rx_256_to_511_octet_packets;
2244         u64             rx_512_to_1023_octet_packets;
2245         u64             rx_1024_to_1522_octet_packets;
2246         u64             rx_1523_to_2047_octet_packets;
2247         u64             rx_2048_to_4095_octet_packets;
2248         u64             rx_4096_to_8191_octet_packets;
2249         u64             rx_8192_to_9022_octet_packets;
2250
2251         /* Statistics maintained by Transmit MAC. */
2252         u64             tx_octets;
2253         u64             tx_collisions;
2254         u64             tx_xon_sent;
2255         u64             tx_xoff_sent;
2256         u64             tx_flow_control;
2257         u64             tx_mac_errors;
2258         u64             tx_single_collisions;
2259         u64             tx_mult_collisions;
2260         u64             tx_deferred;
2261         u64             tx_excessive_collisions;
2262         u64             tx_late_collisions;
2263         u64             tx_collide_2times;
2264         u64             tx_collide_3times;
2265         u64             tx_collide_4times;
2266         u64             tx_collide_5times;
2267         u64             tx_collide_6times;
2268         u64             tx_collide_7times;
2269         u64             tx_collide_8times;
2270         u64             tx_collide_9times;
2271         u64             tx_collide_10times;
2272         u64             tx_collide_11times;
2273         u64             tx_collide_12times;
2274         u64             tx_collide_13times;
2275         u64             tx_collide_14times;
2276         u64             tx_collide_15times;
2277         u64             tx_ucast_packets;
2278         u64             tx_mcast_packets;
2279         u64             tx_bcast_packets;
2280         u64             tx_carrier_sense_errors;
2281         u64             tx_discards;
2282         u64             tx_errors;
2283
2284         /* Statistics maintained by Receive List Placement. */
2285         u64             dma_writeq_full;
2286         u64             dma_write_prioq_full;
2287         u64             rxbds_empty;
2288         u64             rx_discards;
2289         u64             rx_errors;
2290         u64             rx_threshold_hit;
2291
2292         /* Statistics maintained by Send Data Initiator. */
2293         u64             dma_readq_full;
2294         u64             dma_read_prioq_full;
2295         u64             tx_comp_queue_full;
2296
2297         /* Statistics maintained by Host Coalescing. */
2298         u64             ring_set_send_prod_index;
2299         u64             ring_status_update;
2300         u64             nic_irqs;
2301         u64             nic_avoided_irqs;
2302         u64             nic_tx_threshold_hit;
2303 };
2304
2305 struct tg3 {
2306         /* begin "general, frequently-used members" cacheline section */
2307
2308         /* If the IRQ handler (which runs lockless) needs to be
2309          * quiesced, the following bitmask state is used.  The
2310          * SYNC flag is set by non-IRQ context code to initiate
2311          * the quiescence.
2312          *
2313          * When the IRQ handler notices that SYNC is set, it
2314          * disables interrupts and returns.
2315          *
2316          * When all outstanding IRQ handlers have returned after
2317          * the SYNC flag has been set, the setter can be assured
2318          * that interrupts will no longer get run.
2319          *
2320          * In this way all SMP driver locks are never acquired
2321          * in hw IRQ context, only sw IRQ context or lower.
2322          */
2323         unsigned int                    irq_sync;
2324
2325         /* SMP locking strategy:
2326          *
2327          * lock: Held during reset, PHY access, timer, and when
2328          *       updating tg3_flags and tg3_flags2.
2329          *
2330          * netif_tx_lock: Held during tg3_start_xmit. tg3_tx holds
2331          *                netif_tx_lock when it needs to call
2332          *                netif_wake_queue.
2333          *
2334          * Both of these locks are to be held with BH safety.
2335          *
2336          * Because the IRQ handler, tg3_poll, and tg3_start_xmit
2337          * are running lockless, it is necessary to completely
2338          * quiesce the chip with tg3_netif_stop and tg3_full_lock
2339          * before reconfiguring the device.
2340          *
2341          * indirect_lock: Held when accessing registers indirectly
2342          *                with IRQ disabling.
2343          */
2344         spinlock_t                      lock;
2345         spinlock_t                      indirect_lock;
2346
2347         u32                             (*read32) (struct tg3 *, u32);
2348         void                            (*write32) (struct tg3 *, u32, u32);
2349         u32                             (*read32_mbox) (struct tg3 *, u32);
2350         void                            (*write32_mbox) (struct tg3 *, u32,
2351                                                          u32);
2352         void __iomem                    *regs;
2353         void __iomem                    *aperegs;
2354         struct net_device               *dev;
2355         struct pci_dev                  *pdev;
2356
2357         struct tg3_hw_status            *hw_status;
2358         dma_addr_t                      status_mapping;
2359         u32                             last_tag;
2360
2361         u32                             msg_enable;
2362
2363         /* begin "tx thread" cacheline section */
2364         void                            (*write32_tx_mbox) (struct tg3 *, u32,
2365                                                             u32);
2366         u32                             tx_prod;
2367         u32                             tx_cons;
2368         u32                             tx_pending;
2369
2370         struct tg3_tx_buffer_desc       *tx_ring;
2371         struct tx_ring_info             *tx_buffers;
2372         dma_addr_t                      tx_desc_mapping;
2373
2374         /* begin "rx thread" cacheline section */
2375         struct napi_struct              napi;
2376         void                            (*write32_rx_mbox) (struct tg3 *, u32,
2377                                                             u32);
2378         u32                             rx_rcb_ptr;
2379         u32                             rx_std_ptr;
2380         u32                             rx_jumbo_ptr;
2381         u32                             rx_pending;
2382         u32                             rx_jumbo_pending;
2383 #if TG3_VLAN_TAG_USED
2384         struct vlan_group               *vlgrp;
2385 #endif
2386
2387         struct tg3_rx_buffer_desc       *rx_std;
2388         struct ring_info                *rx_std_buffers;
2389         dma_addr_t                      rx_std_mapping;
2390         u32                             rx_std_max_post;
2391
2392         struct tg3_rx_buffer_desc       *rx_jumbo;
2393         struct ring_info                *rx_jumbo_buffers;
2394         dma_addr_t                      rx_jumbo_mapping;
2395
2396         struct tg3_rx_buffer_desc       *rx_rcb;
2397         dma_addr_t                      rx_rcb_mapping;
2398
2399         u32                             rx_pkt_buf_sz;
2400
2401         /* begin "everything else" cacheline(s) section */
2402         struct net_device_stats         net_stats;
2403         struct net_device_stats         net_stats_prev;
2404         struct tg3_ethtool_stats        estats;
2405         struct tg3_ethtool_stats        estats_prev;
2406
2407         unsigned long                   phy_crc_errors;
2408
2409         u32                             rx_offset;
2410         u32                             tg3_flags;
2411 #define TG3_FLAG_TAGGED_STATUS          0x00000001
2412 #define TG3_FLAG_TXD_MBOX_HWBUG         0x00000002
2413 #define TG3_FLAG_RX_CHECKSUMS           0x00000004
2414 #define TG3_FLAG_USE_LINKCHG_REG        0x00000008
2415 #define TG3_FLAG_USE_MI_INTERRUPT       0x00000010
2416 #define TG3_FLAG_ENABLE_ASF             0x00000020
2417 #define TG3_FLAG_ASPM_WORKAROUND        0x00000040
2418 #define TG3_FLAG_POLL_SERDES            0x00000080
2419 #define TG3_FLAG_MBOX_WRITE_REORDER     0x00000100
2420 #define TG3_FLAG_PCIX_TARGET_HWBUG      0x00000200
2421 #define TG3_FLAG_WOL_SPEED_100MB        0x00000400
2422 #define TG3_FLAG_WOL_ENABLE             0x00000800
2423 #define TG3_FLAG_EEPROM_WRITE_PROT      0x00001000
2424 #define TG3_FLAG_NVRAM                  0x00002000
2425 #define TG3_FLAG_NVRAM_BUFFERED         0x00004000
2426 #define TG3_FLAG_PCIX_MODE              0x00020000
2427 #define TG3_FLAG_PCI_HIGH_SPEED         0x00040000
2428 #define TG3_FLAG_PCI_32BIT              0x00080000
2429 #define TG3_FLAG_SRAM_USE_CONFIG        0x00100000
2430 #define TG3_FLAG_TX_RECOVERY_PENDING    0x00200000
2431 #define TG3_FLAG_WOL_CAP                0x00400000
2432 #define TG3_FLAG_JUMBO_RING_ENABLE      0x00800000
2433 #define TG3_FLAG_10_100_ONLY            0x01000000
2434 #define TG3_FLAG_PAUSE_AUTONEG          0x02000000
2435 #define TG3_FLAG_CPMU_PRESENT           0x04000000
2436 #define TG3_FLAG_40BIT_DMA_BUG          0x08000000
2437 #define TG3_FLAG_BROKEN_CHECKSUMS       0x10000000
2438 #define TG3_FLAG_SUPPORT_MSI            0x20000000
2439 #define TG3_FLAG_CHIP_RESETTING         0x40000000
2440 #define TG3_FLAG_INIT_COMPLETE          0x80000000
2441         u32                             tg3_flags2;
2442 #define TG3_FLG2_RESTART_TIMER          0x00000001
2443 #define TG3_FLG2_TSO_BUG                0x00000002
2444 #define TG3_FLG2_NO_ETH_WIRE_SPEED      0x00000004
2445 #define TG3_FLG2_IS_5788                0x00000008
2446 #define TG3_FLG2_MAX_RXPEND_64          0x00000010
2447 #define TG3_FLG2_TSO_CAPABLE            0x00000020
2448 #define TG3_FLG2_PHY_ADC_BUG            0x00000040
2449 #define TG3_FLG2_PHY_5704_A0_BUG        0x00000080
2450 #define TG3_FLG2_PHY_BER_BUG            0x00000100
2451 #define TG3_FLG2_PCI_EXPRESS            0x00000200
2452 #define TG3_FLG2_ASF_NEW_HANDSHAKE      0x00000400
2453 #define TG3_FLG2_HW_AUTONEG             0x00000800
2454 #define TG3_FLG2_IS_NIC                 0x00001000
2455 #define TG3_FLG2_PHY_SERDES             0x00002000
2456 #define TG3_FLG2_CAPACITIVE_COUPLING    0x00004000
2457 #define TG3_FLG2_FLASH                  0x00008000
2458 #define TG3_FLG2_HW_TSO_1               0x00010000
2459 #define TG3_FLG2_SERDES_PREEMPHASIS     0x00020000
2460 #define TG3_FLG2_5705_PLUS              0x00040000
2461 #define TG3_FLG2_5750_PLUS              0x00080000
2462 #define TG3_FLG2_PROTECTED_NVRAM        0x00100000
2463 #define TG3_FLG2_USING_MSI              0x00200000
2464 #define TG3_FLG2_JUMBO_CAPABLE          0x00400000
2465 #define TG3_FLG2_MII_SERDES             0x00800000
2466 #define TG3_FLG2_ANY_SERDES             (TG3_FLG2_PHY_SERDES |  \
2467                                         TG3_FLG2_MII_SERDES)
2468 #define TG3_FLG2_PARALLEL_DETECT        0x01000000
2469 #define TG3_FLG2_ICH_WORKAROUND         0x02000000
2470 #define TG3_FLG2_5780_CLASS             0x04000000
2471 #define TG3_FLG2_HW_TSO_2               0x08000000
2472 #define TG3_FLG2_HW_TSO                 (TG3_FLG2_HW_TSO_1 | TG3_FLG2_HW_TSO_2)
2473 #define TG3_FLG2_1SHOT_MSI              0x10000000
2474 #define TG3_FLG2_PHY_JITTER_BUG         0x20000000
2475 #define TG3_FLG2_NO_FWARE_REPORTED      0x40000000
2476 #define TG3_FLG2_PHY_ADJUST_TRIM        0x80000000
2477         u32                             tg3_flags3;
2478 #define TG3_FLG3_NO_NVRAM_ADDR_TRANS    0x00000001
2479 #define TG3_FLG3_ENABLE_APE             0x00000002
2480 #define TG3_FLG3_5761_5784_AX_FIXES     0x00000004
2481 #define TG3_FLG3_5701_DMA_BUG           0x00000008
2482
2483         struct timer_list               timer;
2484         u16                             timer_counter;
2485         u16                             timer_multiplier;
2486         u32                             timer_offset;
2487         u16                             asf_counter;
2488         u16                             asf_multiplier;
2489
2490         /* 1 second counter for transient serdes link events */
2491         u32                             serdes_counter;
2492 #define SERDES_AN_TIMEOUT_5704S         2
2493 #define SERDES_PARALLEL_DET_TIMEOUT     1
2494 #define SERDES_AN_TIMEOUT_5714S         1
2495
2496         struct tg3_link_config          link_config;
2497         struct tg3_bufmgr_config        bufmgr_config;
2498
2499         /* cache h/w values, often passed straight to h/w */
2500         u32                             rx_mode;
2501         u32                             tx_mode;
2502         u32                             mac_mode;
2503         u32                             mi_mode;
2504         u32                             misc_host_ctrl;
2505         u32                             grc_mode;
2506         u32                             grc_local_ctrl;
2507         u32                             dma_rwctrl;
2508         u32                             coalesce_mode;
2509         u32                             pwrmgmt_thresh;
2510
2511         /* PCI block */
2512         u32                             pci_chip_rev_id;
2513         u8                              pci_cacheline_sz;
2514         u8                              pci_lat_timer;
2515         u8                              pci_hdr_type;
2516         u8                              pci_bist;
2517
2518         int                             pm_cap;
2519         int                             msi_cap;
2520         int                             pcix_cap;
2521
2522         /* PHY info */
2523         u32                             phy_id;
2524 #define PHY_ID_MASK                     0xfffffff0
2525 #define PHY_ID_BCM5400                  0x60008040
2526 #define PHY_ID_BCM5401                  0x60008050
2527 #define PHY_ID_BCM5411                  0x60008070
2528 #define PHY_ID_BCM5701                  0x60008110
2529 #define PHY_ID_BCM5703                  0x60008160
2530 #define PHY_ID_BCM5704                  0x60008190
2531 #define PHY_ID_BCM5705                  0x600081a0
2532 #define PHY_ID_BCM5750                  0x60008180
2533 #define PHY_ID_BCM5752                  0x60008100
2534 #define PHY_ID_BCM5714                  0x60008340
2535 #define PHY_ID_BCM5780                  0x60008350
2536 #define PHY_ID_BCM5755                  0xbc050cc0
2537 #define PHY_ID_BCM5787                  0xbc050ce0
2538 #define PHY_ID_BCM5756                  0xbc050ed0
2539 #define PHY_ID_BCM5784                  0xbc050fa0
2540 #define PHY_ID_BCM5761                  0xbc050fd0
2541 #define PHY_ID_BCM5906                  0xdc00ac40
2542 #define PHY_ID_BCM8002                  0x60010140
2543 #define PHY_ID_INVALID                  0xffffffff
2544 #define PHY_ID_REV_MASK                 0x0000000f
2545 #define PHY_REV_BCM5401_B0              0x1
2546 #define PHY_REV_BCM5401_B2              0x3
2547 #define PHY_REV_BCM5401_C0              0x6
2548 #define PHY_REV_BCM5411_X0              0x1 /* Found on Netgear GA302T */
2549
2550         u32                             led_ctrl;
2551         u32                             phy_otp;
2552         u16                             pci_cmd;
2553
2554         char                            board_part_number[24];
2555 #define TG3_VER_SIZE 32
2556         char                            fw_ver[TG3_VER_SIZE];
2557         u32                             nic_sram_data_cfg;
2558         u32                             pci_clock_ctrl;
2559         struct pci_dev                  *pdev_peer;
2560
2561         /* This macro assumes the passed PHY ID is already masked
2562          * with PHY_ID_MASK.
2563          */
2564 #define KNOWN_PHY_ID(X)         \
2565         ((X) == PHY_ID_BCM5400 || (X) == PHY_ID_BCM5401 || \
2566          (X) == PHY_ID_BCM5411 || (X) == PHY_ID_BCM5701 || \
2567          (X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \
2568          (X) == PHY_ID_BCM5705 || (X) == PHY_ID_BCM5750 || \
2569          (X) == PHY_ID_BCM5752 || (X) == PHY_ID_BCM5714 || \
2570          (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
2571          (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \
2572          (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM5761 || \
2573          (X) == PHY_ID_BCM8002)
2574
2575         struct tg3_hw_stats             *hw_stats;
2576         dma_addr_t                      stats_mapping;
2577         struct work_struct              reset_task;
2578
2579         int                             nvram_lock_cnt;
2580         u32                             nvram_size;
2581 #define TG3_NVRAM_SIZE_64KB             0x00010000
2582 #define TG3_NVRAM_SIZE_128KB            0x00020000
2583 #define TG3_NVRAM_SIZE_256KB            0x00040000
2584 #define TG3_NVRAM_SIZE_512KB            0x00080000
2585 #define TG3_NVRAM_SIZE_1MB              0x00100000
2586 #define TG3_NVRAM_SIZE_2MB              0x00200000
2587
2588         u32                             nvram_pagesize;
2589         u32                             nvram_jedecnum;
2590
2591 #define JEDEC_ATMEL                     0x1f
2592 #define JEDEC_ST                        0x20
2593 #define JEDEC_SAIFUN                    0x4f
2594 #define JEDEC_SST                       0xbf
2595
2596 #define ATMEL_AT24C64_CHIP_SIZE         TG3_NVRAM_SIZE_64KB
2597 #define ATMEL_AT24C64_PAGE_SIZE         (32)
2598
2599 #define ATMEL_AT24C512_CHIP_SIZE        TG3_NVRAM_SIZE_512KB
2600 #define ATMEL_AT24C512_PAGE_SIZE        (128)
2601
2602 #define ATMEL_AT45DB0X1B_PAGE_POS       9
2603 #define ATMEL_AT45DB0X1B_PAGE_SIZE      264
2604
2605 #define ATMEL_AT25F512_PAGE_SIZE        256
2606
2607 #define ST_M45PEX0_PAGE_SIZE            256
2608
2609 #define SAIFUN_SA25F0XX_PAGE_SIZE       256
2610
2611 #define SST_25VF0X0_PAGE_SIZE           4098
2612
2613         struct ethtool_coalesce         coal;
2614 };
2615
2616 #endif /* !(_T3_H) */