drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18 #include <linux/config.h>
  19
  20 #include <linux/module.h>
  21 #include <linux/moduleparam.h>
  22 #include <linux/kernel.h>
  23 #include <linux/types.h>
  24 #include <linux/compiler.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/if_vlan.h>
  36 #include <linux/ip.h>
  37 #include <linux/tcp.h>
  38 #include <linux/workqueue.h>
  39
  40 #include <net/checksum.h>
  41
  42 #include <asm/system.h>
  43 #include <asm/io.h>
  44 #include <asm/byteorder.h>
  45 #include <asm/uaccess.h>
  46
  47 #ifdef CONFIG_SPARC64
  48 #include <asm/idprom.h>
  49 #include <asm/oplib.h>
  50 #include <asm/pbm.h>
  51 #endif
  52
  53 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  54 #define TG3_VLAN_TAG_USED 1
  55 #else
  56 #define TG3_VLAN_TAG_USED 0
  57 #endif
  58
  59 #ifdef NETIF_F_TSO
  60 #define TG3_TSO_SUPPORT 1
  61 #else
  62 #define TG3_TSO_SUPPORT 0
  63 #endif
  64
  65 #include "tg3.h"
  66
  67 #define DRV_MODULE_NAME         "tg3"
  68 #define PFX DRV_MODULE_NAME     ": "
  69 #define DRV_MODULE_VERSION      "3.33"
  70 #define DRV_MODULE_RELDATE      "July 5, 2005"
  71
  72 #define TG3_DEF_MAC_MODE        0
  73 #define TG3_DEF_RX_MODE         0
  74 #define TG3_DEF_TX_MODE         0
  75 #define TG3_DEF_MSG_ENABLE        \
  76         (NETIF_MSG_DRV          | \
  77          NETIF_MSG_PROBE        | \
  78          NETIF_MSG_LINK         | \
  79          NETIF_MSG_TIMER        | \
  80          NETIF_MSG_IFDOWN       | \
  81          NETIF_MSG_IFUP         | \
  82          NETIF_MSG_RX_ERR       | \
  83          NETIF_MSG_TX_ERR)
  84
  85 /* length of time before we decide the hardware is borked,
  86  * and dev->tx_timeout() should be called to fix the problem
  87  */
  88 #define TG3_TX_TIMEOUT                  (5 * HZ)
  89
  90 /* hardware minimum and maximum for a single frame's data payload */
  91 #define TG3_MIN_MTU                     60
  92 #define TG3_MAX_MTU(tp) \
  93         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
  94
  95 /* These numbers seem to be hard coded in the NIC firmware somehow.
  96  * You can't change the ring sizes, but you can change where you place
  97  * them in the NIC onboard memory.
  98  */
  99 #define TG3_RX_RING_SIZE                512
 100 #define TG3_DEF_RX_RING_PENDING         200
 101 #define TG3_RX_JUMBO_RING_SIZE          256
 102 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 103
 104 /* Do not place this n-ring entries value into the tp struct itself,
 105  * we really want to expose these constants to GCC so that modulo et
 106  * al.  operations are done with shifts and masks instead of with
 107  * hw multiply/modulo instructions.  Another solution would be to
 108  * replace things like '% foo' with '& (foo - 1)'.
 109  */
 110 #define TG3_RX_RCB_RING_SIZE(tp)        \
 111         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
 112
 113 #define TG3_TX_RING_SIZE                512
 114 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 115
 116 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 117                                  TG3_RX_RING_SIZE)
 118 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
 119                                  TG3_RX_JUMBO_RING_SIZE)
 120 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 121                                    TG3_RX_RCB_RING_SIZE(tp))
 122 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 123                                  TG3_TX_RING_SIZE)
 124 #define TX_RING_GAP(TP) \
 125         (TG3_TX_RING_SIZE - (TP)->tx_pending)
 126 #define TX_BUFFS_AVAIL(TP)                                              \
 127         (((TP)->tx_cons <= (TP)->tx_prod) ?                             \
 128           (TP)->tx_cons + (TP)->tx_pending - (TP)->tx_prod :            \
 129           (TP)->tx_cons - (TP)->tx_prod - TX_RING_GAP(TP))
 130 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 131
 132 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
 133 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
 134
 135 /* minimum number of free TX descriptors required to wake up TX process */
 136 #define TG3_TX_WAKEUP_THRESH            (TG3_TX_RING_SIZE / 4)
 137
 138 /* number of ETHTOOL_GSTATS u64's */
 139 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 140
 141 #define TG3_NUM_TEST            6
 142
 143 static char version[] __devinitdata =
 144         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 145
 146 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 147 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 148 MODULE_LICENSE("GPL");
 149 MODULE_VERSION(DRV_MODULE_VERSION);
 150
 151 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 152 module_param(tg3_debug, int, 0);
 153 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 154
 155 static struct pci_device_id tg3_pci_tbl[] = {
 156         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700,
 157           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 158         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701,
 159           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 160         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702,
 161           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 162         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703,
 163           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 164         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704,
 165           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 166         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE,
 167           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 168         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705,
 169           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 170         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2,
 171           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 172         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M,
 173           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 174         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2,
 175           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 176         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X,
 177           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 178         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X,
 179           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 180         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S,
 181           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 182         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3,
 183           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 184         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3,
 185           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 186         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782,
 187           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 188         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788,
 189           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 190         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789,
 191           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 192         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901,
 193           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 194         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2,
 195           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 196         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2,
 197           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 198         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F,
 199           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 200         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720,
 201           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 202         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721,
 203           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 204         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750,
 205           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 206         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751,
 207           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 208         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M,
 209           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 210         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M,
 211           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 212         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F,
 213           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 214         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752,
 215           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 216         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M,
 217           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 218         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753,
 219           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 220         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M,
 221           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 222         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F,
 223           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 224         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780,
 225           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 226         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S,
 227           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 228         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781,
 229           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 230         { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX,
 231           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 232         { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX,
 233           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 234         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000,
 235           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 236         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001,
 237           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 238         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003,
 239           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 240         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100,
 241           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 242         { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3,
 243           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 244         { 0, }
 245 };
 246
 247 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 248
 249 static struct {
 250         const char string[ETH_GSTRING_LEN];
 251 } ethtool_stats_keys[TG3_NUM_STATS] = {
 252         { "rx_octets" },
 253         { "rx_fragments" },
 254         { "rx_ucast_packets" },
 255         { "rx_mcast_packets" },
 256         { "rx_bcast_packets" },
 257         { "rx_fcs_errors" },
 258         { "rx_align_errors" },
 259         { "rx_xon_pause_rcvd" },
 260         { "rx_xoff_pause_rcvd" },
 261         { "rx_mac_ctrl_rcvd" },
 262         { "rx_xoff_entered" },
 263         { "rx_frame_too_long_errors" },
 264         { "rx_jabbers" },
 265         { "rx_undersize_packets" },
 266         { "rx_in_length_errors" },
 267         { "rx_out_length_errors" },
 268         { "rx_64_or_less_octet_packets" },
 269         { "rx_65_to_127_octet_packets" },
 270         { "rx_128_to_255_octet_packets" },
 271         { "rx_256_to_511_octet_packets" },
 272         { "rx_512_to_1023_octet_packets" },
 273         { "rx_1024_to_1522_octet_packets" },
 274         { "rx_1523_to_2047_octet_packets" },
 275         { "rx_2048_to_4095_octet_packets" },
 276         { "rx_4096_to_8191_octet_packets" },
 277         { "rx_8192_to_9022_octet_packets" },
 278
 279         { "tx_octets" },
 280         { "tx_collisions" },
 281
 282         { "tx_xon_sent" },
 283         { "tx_xoff_sent" },
 284         { "tx_flow_control" },
 285         { "tx_mac_errors" },
 286         { "tx_single_collisions" },
 287         { "tx_mult_collisions" },
 288         { "tx_deferred" },
 289         { "tx_excessive_collisions" },
 290         { "tx_late_collisions" },
 291         { "tx_collide_2times" },
 292         { "tx_collide_3times" },
 293         { "tx_collide_4times" },
 294         { "tx_collide_5times" },
 295         { "tx_collide_6times" },
 296         { "tx_collide_7times" },
 297         { "tx_collide_8times" },
 298         { "tx_collide_9times" },
 299         { "tx_collide_10times" },
 300         { "tx_collide_11times" },
 301         { "tx_collide_12times" },
 302         { "tx_collide_13times" },
 303         { "tx_collide_14times" },
 304         { "tx_collide_15times" },
 305         { "tx_ucast_packets" },
 306         { "tx_mcast_packets" },
 307         { "tx_bcast_packets" },
 308         { "tx_carrier_sense_errors" },
 309         { "tx_discards" },
 310         { "tx_errors" },
 311
 312         { "dma_writeq_full" },
 313         { "dma_write_prioq_full" },
 314         { "rxbds_empty" },
 315         { "rx_discards" },
 316         { "rx_errors" },
 317         { "rx_threshold_hit" },
 318
 319         { "dma_readq_full" },
 320         { "dma_read_prioq_full" },
 321         { "tx_comp_queue_full" },
 322
 323         { "ring_set_send_prod_index" },
 324         { "ring_status_update" },
 325         { "nic_irqs" },
 326         { "nic_avoided_irqs" },
 327         { "nic_tx_threshold_hit" }
 328 };
 329
 330 static struct {
 331         const char string[ETH_GSTRING_LEN];
 332 } ethtool_test_keys[TG3_NUM_TEST] = {
 333         { "nvram test     (online) " },
 334         { "link test      (online) " },
 335         { "register test  (offline)" },
 336         { "memory test    (offline)" },
 337         { "loopback test  (offline)" },
 338         { "interrupt test (offline)" },
 339 };
 340
 341 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 342 {
 343         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) != 0) {
 344                 spin_lock_bh(&tp->indirect_lock);
 345                 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 346                 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 347                 spin_unlock_bh(&tp->indirect_lock);
 348         } else {
 349                 writel(val, tp->regs + off);
 350                 if ((tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG) != 0)
 351                         readl(tp->regs + off);
 352         }
 353 }
 354
 355 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val)
 356 {
 357         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) != 0) {
 358                 spin_lock_bh(&tp->indirect_lock);
 359                 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 360                 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 361                 spin_unlock_bh(&tp->indirect_lock);
 362         } else {
 363                 void __iomem *dest = tp->regs + off;
 364                 writel(val, dest);
 365                 readl(dest);    /* always flush PCI write */
 366         }
 367 }
 368
 369 static inline void _tw32_rx_mbox(struct tg3 *tp, u32 off, u32 val)
 370 {
 371         void __iomem *mbox = tp->regs + off;
 372         writel(val, mbox);
 373         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 374                 readl(mbox);
 375 }
 376
 377 static inline void _tw32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 378 {
 379         void __iomem *mbox = tp->regs + off;
 380         writel(val, mbox);
 381         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 382                 writel(val, mbox);
 383         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 384                 readl(mbox);
 385 }
 386
 387 #define tw32_mailbox(reg, val)  writel(((val) & 0xffffffff), tp->regs + (reg))
 388 #define tw32_rx_mbox(reg, val)  _tw32_rx_mbox(tp, reg, val)
 389 #define tw32_tx_mbox(reg, val)  _tw32_tx_mbox(tp, reg, val)
 390
 391 #define tw32(reg,val)           tg3_write_indirect_reg32(tp,(reg),(val))
 392 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val))
 393 #define tw16(reg,val)           writew(((val) & 0xffff), tp->regs + (reg))
 394 #define tw8(reg,val)            writeb(((val) & 0xff), tp->regs + (reg))
 395 #define tr32(reg)               readl(tp->regs + (reg))
 396 #define tr16(reg)               readw(tp->regs + (reg))
 397 #define tr8(reg)                readb(tp->regs + (reg))
 398
 399 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 400 {
 401         spin_lock_bh(&tp->indirect_lock);
 402         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 403         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 404
 405         /* Always leave this as zero. */
 406         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 407         spin_unlock_bh(&tp->indirect_lock);
 408 }
 409
 410 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 411 {
 412         spin_lock_bh(&tp->indirect_lock);
 413         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 414         pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 415
 416         /* Always leave this as zero. */
 417         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 418         spin_unlock_bh(&tp->indirect_lock);
 419 }
 420
 421 static void tg3_disable_ints(struct tg3 *tp)
 422 {
 423         tw32(TG3PCI_MISC_HOST_CTRL,
 424              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 425         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
 426         tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
 427 }
 428
 429 static inline void tg3_cond_int(struct tg3 *tp)
 430 {
 431         if (tp->hw_status->status & SD_STATUS_UPDATED)
 432                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 433 }
 434
 435 static void tg3_enable_ints(struct tg3 *tp)
 436 {
 437         tp->irq_sync = 0;
 438         wmb();
 439
 440         tw32(TG3PCI_MISC_HOST_CTRL,
 441              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 442         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 443                      (tp->last_tag << 24));
 444         tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
 445         tg3_cond_int(tp);
 446 }
 447
 448 static inline unsigned int tg3_has_work(struct tg3 *tp)
 449 {
 450         struct tg3_hw_status *sblk = tp->hw_status;
 451         unsigned int work_exists = 0;
 452
 453         /* check for phy events */
 454         if (!(tp->tg3_flags &
 455               (TG3_FLAG_USE_LINKCHG_REG |
 456                TG3_FLAG_POLL_SERDES))) {
 457                 if (sblk->status & SD_STATUS_LINK_CHG)
 458                         work_exists = 1;
 459         }
 460         /* check for RX/TX work to do */
 461         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
 462             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
 463                 work_exists = 1;
 464
 465         return work_exists;
 466 }
 467
 468 /* tg3_restart_ints
 469  *  similar to tg3_enable_ints, but it accurately determines whether there
 470  *  is new work pending and can return without flushing the PIO write
 471  *  which reenables interrupts
 472  */
 473 static void tg3_restart_ints(struct tg3 *tp)
 474 {
 475         tw32(TG3PCI_MISC_HOST_CTRL,
 476                 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 477         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 478                      tp->last_tag << 24);
 479         mmiowb();
 480
 481         /* When doing tagged status, this work check is unnecessary.
 482          * The last_tag we write above tells the chip which piece of
 483          * work we've completed.
 484          */
 485         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 486             tg3_has_work(tp))
 487                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 488                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 489 }
 490
 491 static inline void tg3_netif_stop(struct tg3 *tp)
 492 {
 493         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 494         netif_poll_disable(tp->dev);
 495         netif_tx_disable(tp->dev);
 496 }
 497
 498 static inline void tg3_netif_start(struct tg3 *tp)
 499 {
 500         netif_wake_queue(tp->dev);
 501         /* NOTE: unconditional netif_wake_queue is only appropriate
 502          * so long as all callers are assured to have free tx slots
 503          * (such as after tg3_init_hw)
 504          */
 505         netif_poll_enable(tp->dev);
 506         tp->hw_status->status |= SD_STATUS_UPDATED;
 507         tg3_enable_ints(tp);
 508 }
 509
 510 static void tg3_switch_clocks(struct tg3 *tp)
 511 {
 512         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 513         u32 orig_clock_ctrl;
 514
 515         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
 516                 return;
 517
 518         orig_clock_ctrl = clock_ctrl;
 519         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 520                        CLOCK_CTRL_CLKRUN_OENABLE |
 521                        0x1f);
 522         tp->pci_clock_ctrl = clock_ctrl;
 523
 524         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 525                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 526                         tw32_f(TG3PCI_CLOCK_CTRL,
 527                                clock_ctrl | CLOCK_CTRL_625_CORE);
 528                         udelay(40);
 529                 }
 530         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 531                 tw32_f(TG3PCI_CLOCK_CTRL,
 532                      clock_ctrl |
 533                      (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK));
 534                 udelay(40);
 535                 tw32_f(TG3PCI_CLOCK_CTRL,
 536                      clock_ctrl | (CLOCK_CTRL_ALTCLK));
 537                 udelay(40);
 538         }
 539         tw32_f(TG3PCI_CLOCK_CTRL, clock_ctrl);
 540         udelay(40);
 541 }
 542
 543 #define PHY_BUSY_LOOPS  5000
 544
 545 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 546 {
 547         u32 frame_val;
 548         unsigned int loops;
 549         int ret;
 550
 551         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 552                 tw32_f(MAC_MI_MODE,
 553                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 554                 udelay(80);
 555         }
 556
 557         *val = 0x0;
 558
 559         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 560                       MI_COM_PHY_ADDR_MASK);
 561         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 562                       MI_COM_REG_ADDR_MASK);
 563         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 564
 565         tw32_f(MAC_MI_COM, frame_val);
 566
 567         loops = PHY_BUSY_LOOPS;
 568         while (loops != 0) {
 569                 udelay(10);
 570                 frame_val = tr32(MAC_MI_COM);
 571
 572                 if ((frame_val & MI_COM_BUSY) == 0) {
 573                         udelay(5);
 574                         frame_val = tr32(MAC_MI_COM);
 575                         break;
 576                 }
 577                 loops -= 1;
 578         }
 579
 580         ret = -EBUSY;
 581         if (loops != 0) {
 582                 *val = frame_val & MI_COM_DATA_MASK;
 583                 ret = 0;
 584         }
 585
 586         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 587                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 588                 udelay(80);
 589         }
 590
 591         return ret;
 592 }
 593
 594 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 595 {
 596         u32 frame_val;
 597         unsigned int loops;
 598         int ret;
 599
 600         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 601                 tw32_f(MAC_MI_MODE,
 602                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 603                 udelay(80);
 604         }
 605
 606         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 607                       MI_COM_PHY_ADDR_MASK);
 608         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 609                       MI_COM_REG_ADDR_MASK);
 610         frame_val |= (val & MI_COM_DATA_MASK);
 611         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 612
 613         tw32_f(MAC_MI_COM, frame_val);
 614
 615         loops = PHY_BUSY_LOOPS;
 616         while (loops != 0) {
 617                 udelay(10);
 618                 frame_val = tr32(MAC_MI_COM);
 619                 if ((frame_val & MI_COM_BUSY) == 0) {
 620                         udelay(5);
 621                         frame_val = tr32(MAC_MI_COM);
 622                         break;
 623                 }
 624                 loops -= 1;
 625         }
 626
 627         ret = -EBUSY;
 628         if (loops != 0)
 629                 ret = 0;
 630
 631         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 632                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 633                 udelay(80);
 634         }
 635
 636         return ret;
 637 }
 638
 639 static void tg3_phy_set_wirespeed(struct tg3 *tp)
 640 {
 641         u32 val;
 642
 643         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
 644                 return;
 645
 646         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
 647             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
 648                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
 649                              (val | (1 << 15) | (1 << 4)));
 650 }
 651
 652 static int tg3_bmcr_reset(struct tg3 *tp)
 653 {
 654         u32 phy_control;
 655         int limit, err;
 656
 657         /* OK, reset it, and poll the BMCR_RESET bit until it
 658          * clears or we time out.
 659          */
 660         phy_control = BMCR_RESET;
 661         err = tg3_writephy(tp, MII_BMCR, phy_control);
 662         if (err != 0)
 663                 return -EBUSY;
 664
 665         limit = 5000;
 666         while (limit--) {
 667                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 668                 if (err != 0)
 669                         return -EBUSY;
 670
 671                 if ((phy_control & BMCR_RESET) == 0) {
 672                         udelay(40);
 673                         break;
 674                 }
 675                 udelay(10);
 676         }
 677         if (limit <= 0)
 678                 return -EBUSY;
 679
 680         return 0;
 681 }
 682
 683 static int tg3_wait_macro_done(struct tg3 *tp)
 684 {
 685         int limit = 100;
 686
 687         while (limit--) {
 688                 u32 tmp32;
 689
 690                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
 691                         if ((tmp32 & 0x1000) == 0)
 692                                 break;
 693                 }
 694         }
 695         if (limit <= 0)
 696                 return -EBUSY;
 697
 698         return 0;
 699 }
 700
 701 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
 702 {
 703         static const u32 test_pat[4][6] = {
 704         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
 705         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
 706         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
 707         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
 708         };
 709         int chan;
 710
 711         for (chan = 0; chan < 4; chan++) {
 712                 int i;
 713
 714                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 715                              (chan * 0x2000) | 0x0200);
 716                 tg3_writephy(tp, 0x16, 0x0002);
 717
 718                 for (i = 0; i < 6; i++)
 719                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
 720                                      test_pat[chan][i]);
 721
 722                 tg3_writephy(tp, 0x16, 0x0202);
 723                 if (tg3_wait_macro_done(tp)) {
 724                         *resetp = 1;
 725                         return -EBUSY;
 726                 }
 727
 728                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 729                              (chan * 0x2000) | 0x0200);
 730                 tg3_writephy(tp, 0x16, 0x0082);
 731                 if (tg3_wait_macro_done(tp)) {
 732                         *resetp = 1;
 733                         return -EBUSY;
 734                 }
 735
 736                 tg3_writephy(tp, 0x16, 0x0802);
 737                 if (tg3_wait_macro_done(tp)) {
 738                         *resetp = 1;
 739                         return -EBUSY;
 740                 }
 741
 742                 for (i = 0; i < 6; i += 2) {
 743                         u32 low, high;
 744
 745                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
 746                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
 747                             tg3_wait_macro_done(tp)) {
 748                                 *resetp = 1;
 749                                 return -EBUSY;
 750                         }
 751                         low &= 0x7fff;
 752                         high &= 0x000f;
 753                         if (low != test_pat[chan][i] ||
 754                             high != test_pat[chan][i+1]) {
 755                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
 756                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
 757                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
 758
 759                                 return -EBUSY;
 760                         }
 761                 }
 762         }
 763
 764         return 0;
 765 }
 766
 767 static int tg3_phy_reset_chanpat(struct tg3 *tp)
 768 {
 769         int chan;
 770
 771         for (chan = 0; chan < 4; chan++) {
 772                 int i;
 773
 774                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 775                              (chan * 0x2000) | 0x0200);
 776                 tg3_writephy(tp, 0x16, 0x0002);
 777                 for (i = 0; i < 6; i++)
 778                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
 779                 tg3_writephy(tp, 0x16, 0x0202);
 780                 if (tg3_wait_macro_done(tp))
 781                         return -EBUSY;
 782         }
 783
 784         return 0;
 785 }
 786
 787 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
 788 {
 789         u32 reg32, phy9_orig;
 790         int retries, do_phy_reset, err;
 791
 792         retries = 10;
 793         do_phy_reset = 1;
 794         do {
 795                 if (do_phy_reset) {
 796                         err = tg3_bmcr_reset(tp);
 797                         if (err)
 798                                 return err;
 799                         do_phy_reset = 0;
 800                 }
 801
 802                 /* Disable transmitter and interrupt.  */
 803                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
 804                         continue;
 805
 806                 reg32 |= 0x3000;
 807                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 808
 809                 /* Set full-duplex, 1000 mbps.  */
 810                 tg3_writephy(tp, MII_BMCR,
 811                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
 812
 813                 /* Set to master mode.  */
 814                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
 815                         continue;
 816
 817                 tg3_writephy(tp, MII_TG3_CTRL,
 818                              (MII_TG3_CTRL_AS_MASTER |
 819                               MII_TG3_CTRL_ENABLE_AS_MASTER));
 820
 821                 /* Enable SM_DSP_CLOCK and 6dB.  */
 822                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 823
 824                 /* Block the PHY control access.  */
 825                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 826                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
 827
 828                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
 829                 if (!err)
 830                         break;
 831         } while (--retries);
 832
 833         err = tg3_phy_reset_chanpat(tp);
 834         if (err)
 835                 return err;
 836
 837         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 838         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
 839
 840         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
 841         tg3_writephy(tp, 0x16, 0x0000);
 842
 843         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 844             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
 845                 /* Set Extended packet length bit for jumbo frames */
 846                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
 847         }
 848         else {
 849                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 850         }
 851
 852         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
 853
 854         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
 855                 reg32 &= ~0x3000;
 856                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 857         } else if (!err)
 858                 err = -EBUSY;
 859
 860         return err;
 861 }
 862
 863 /* This will reset the tigon3 PHY if there is no valid
 864  * link unless the FORCE argument is non-zero.
 865  */
 866 static int tg3_phy_reset(struct tg3 *tp)
 867 {
 868         u32 phy_status;
 869         int err;
 870
 871         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
 872         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
 873         if (err != 0)
 874                 return -EBUSY;
 875
 876         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 877             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
 878             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
 879                 err = tg3_phy_reset_5703_4_5(tp);
 880                 if (err)
 881                         return err;
 882                 goto out;
 883         }
 884
 885         err = tg3_bmcr_reset(tp);
 886         if (err)
 887                 return err;
 888
 889 out:
 890         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
 891                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 892                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
 893                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
 894                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
 895                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
 896                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 897         }
 898         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
 899                 tg3_writephy(tp, 0x1c, 0x8d68);
 900                 tg3_writephy(tp, 0x1c, 0x8d68);
 901         }
 902         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
 903                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 904                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
 905                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
 906                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
 907                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
 908                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
 909                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
 910                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 911         }
 912         /* Set Extended packet length bit (bit 14) on all chips that */
 913         /* support jumbo frames */
 914         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
 915                 /* Cannot do read-modify-write on 5401 */
 916                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
 917         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
 918                 u32 phy_reg;
 919
 920                 /* Set bit 14 with read-modify-write to preserve other bits */
 921                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
 922                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
 923                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
 924         }
 925
 926         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
 927          * jumbo frames transmission.
 928          */
 929         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
 930                 u32 phy_reg;
 931
 932                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
 933                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
 934                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
 935         }
 936
 937         tg3_phy_set_wirespeed(tp);
 938         return 0;
 939 }
 940
 941 static void tg3_frob_aux_power(struct tg3 *tp)
 942 {
 943         struct tg3 *tp_peer = tp;
 944
 945         if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0)
 946                 return;
 947
 948         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
 949                 tp_peer = pci_get_drvdata(tp->pdev_peer);
 950                 if (!tp_peer)
 951                         BUG();
 952         }
 953
 954
 955         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
 956             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0) {
 957                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
 958                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
 959                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
 960                              (GRC_LCLCTRL_GPIO_OE0 |
 961                               GRC_LCLCTRL_GPIO_OE1 |
 962                               GRC_LCLCTRL_GPIO_OE2 |
 963                               GRC_LCLCTRL_GPIO_OUTPUT0 |
 964                               GRC_LCLCTRL_GPIO_OUTPUT1));
 965                         udelay(100);
 966                 } else {
 967                         u32 no_gpio2;
 968                         u32 grc_local_ctrl;
 969
 970                         if (tp_peer != tp &&
 971                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
 972                                 return;
 973
 974                         /* On 5753 and variants, GPIO2 cannot be used. */
 975                         no_gpio2 = tp->nic_sram_data_cfg &
 976                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
 977
 978                         grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
 979                                          GRC_LCLCTRL_GPIO_OE1 |
 980                                          GRC_LCLCTRL_GPIO_OE2 |
 981                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
 982                                          GRC_LCLCTRL_GPIO_OUTPUT2;
 983                         if (no_gpio2) {
 984                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
 985                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
 986                         }
 987                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
 988                                                 grc_local_ctrl);
 989                         udelay(100);
 990
 991                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
 992
 993                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
 994                                                 grc_local_ctrl);
 995                         udelay(100);
 996
 997                         if (!no_gpio2) {
 998                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
 999                                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1000                                        grc_local_ctrl);
1001                                 udelay(100);
1002                         }
1003                 }
1004         } else {
1005                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1006                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1007                         if (tp_peer != tp &&
1008                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1009                                 return;
1010
1011                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1012                              (GRC_LCLCTRL_GPIO_OE1 |
1013                               GRC_LCLCTRL_GPIO_OUTPUT1));
1014                         udelay(100);
1015
1016                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1017                              (GRC_LCLCTRL_GPIO_OE1));
1018                         udelay(100);
1019
1020                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1021                              (GRC_LCLCTRL_GPIO_OE1 |
1022                               GRC_LCLCTRL_GPIO_OUTPUT1));
1023                         udelay(100);
1024                 }
1025         }
1026 }
1027
1028 static int tg3_setup_phy(struct tg3 *, int);
1029
1030 #define RESET_KIND_SHUTDOWN     0
1031 #define RESET_KIND_INIT         1
1032 #define RESET_KIND_SUSPEND      2
1033
1034 static void tg3_write_sig_post_reset(struct tg3 *, int);
1035 static int tg3_halt_cpu(struct tg3 *, u32);
1036
1037 static int tg3_set_power_state(struct tg3 *tp, int state)
1038 {
1039         u32 misc_host_ctrl;
1040         u16 power_control, power_caps;
1041         int pm = tp->pm_cap;
1042
1043         /* Make sure register accesses (indirect or otherwise)
1044          * will function correctly.
1045          */
1046         pci_write_config_dword(tp->pdev,
1047                                TG3PCI_MISC_HOST_CTRL,
1048                                tp->misc_host_ctrl);
1049
1050         pci_read_config_word(tp->pdev,
1051                              pm + PCI_PM_CTRL,
1052                              &power_control);
1053         power_control |= PCI_PM_CTRL_PME_STATUS;
1054         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1055         switch (state) {
1056         case 0:
1057                 power_control |= 0;
1058                 pci_write_config_word(tp->pdev,
1059                                       pm + PCI_PM_CTRL,
1060                                       power_control);
1061                 udelay(100);    /* Delay after power state change */
1062
1063                 /* Switch out of Vaux if it is not a LOM */
1064                 if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)) {
1065                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1066                         udelay(100);
1067                 }
1068
1069                 return 0;
1070
1071         case 1:
1072                 power_control |= 1;
1073                 break;
1074
1075         case 2:
1076                 power_control |= 2;
1077                 break;
1078
1079         case 3:
1080                 power_control |= 3;
1081                 break;
1082
1083         default:
1084                 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1085                        "requested.\n",
1086                        tp->dev->name, state);
1087                 return -EINVAL;
1088         };
1089
1090         power_control |= PCI_PM_CTRL_PME_ENABLE;
1091
1092         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1093         tw32(TG3PCI_MISC_HOST_CTRL,
1094              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1095
1096         if (tp->link_config.phy_is_low_power == 0) {
1097                 tp->link_config.phy_is_low_power = 1;
1098                 tp->link_config.orig_speed = tp->link_config.speed;
1099                 tp->link_config.orig_duplex = tp->link_config.duplex;
1100                 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1101         }
1102
1103         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1104                 tp->link_config.speed = SPEED_10;
1105                 tp->link_config.duplex = DUPLEX_HALF;
1106                 tp->link_config.autoneg = AUTONEG_ENABLE;
1107                 tg3_setup_phy(tp, 0);
1108         }
1109
1110         pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1111
1112         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1113                 u32 mac_mode;
1114
1115                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1116                         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1117                         udelay(40);
1118
1119                         mac_mode = MAC_MODE_PORT_MODE_MII;
1120
1121                         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1122                             !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1123                                 mac_mode |= MAC_MODE_LINK_POLARITY;
1124                 } else {
1125                         mac_mode = MAC_MODE_PORT_MODE_TBI;
1126                 }
1127
1128                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1129                         tw32(MAC_LED_CTRL, tp->led_ctrl);
1130
1131                 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1132                      (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1133                         mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1134
1135                 tw32_f(MAC_MODE, mac_mode);
1136                 udelay(100);
1137
1138                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1139                 udelay(10);
1140         }
1141
1142         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1143             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1144              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1145                 u32 base_val;
1146
1147                 base_val = tp->pci_clock_ctrl;
1148                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1149                              CLOCK_CTRL_TXCLK_DISABLE);
1150
1151                 tw32_f(TG3PCI_CLOCK_CTRL, base_val |
1152                      CLOCK_CTRL_ALTCLK |
1153                      CLOCK_CTRL_PWRDOWN_PLL133);
1154                 udelay(40);
1155         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
1156                 /* do nothing */
1157         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1158                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1159                 u32 newbits1, newbits2;
1160
1161                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1162                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1163                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1164                                     CLOCK_CTRL_TXCLK_DISABLE |
1165                                     CLOCK_CTRL_ALTCLK);
1166                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1167                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1168                         newbits1 = CLOCK_CTRL_625_CORE;
1169                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1170                 } else {
1171                         newbits1 = CLOCK_CTRL_ALTCLK;
1172                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1173                 }
1174
1175                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1);
1176                 udelay(40);
1177
1178                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2);
1179                 udelay(40);
1180
1181                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1182                         u32 newbits3;
1183
1184                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1185                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1186                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1187                                             CLOCK_CTRL_TXCLK_DISABLE |
1188                                             CLOCK_CTRL_44MHZ_CORE);
1189                         } else {
1190                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1191                         }
1192
1193                         tw32_f(TG3PCI_CLOCK_CTRL,
1194                                          tp->pci_clock_ctrl | newbits3);
1195                         udelay(40);
1196                 }
1197         }
1198
1199         tg3_frob_aux_power(tp);
1200
1201         /* Workaround for unstable PLL clock */
1202         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1203             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1204                 u32 val = tr32(0x7d00);
1205
1206                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1207                 tw32(0x7d00, val);
1208                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1209                         tg3_halt_cpu(tp, RX_CPU_BASE);
1210         }
1211
1212         /* Finally, set the new power state. */
1213         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1214         udelay(100);    /* Delay after power state change */
1215
1216         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1217
1218         return 0;
1219 }
1220
1221 static void tg3_link_report(struct tg3 *tp)
1222 {
1223         if (!netif_carrier_ok(tp->dev)) {
1224                 printk(KERN_INFO PFX "%s: Link is down.\n", tp->dev->name);
1225         } else {
1226                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1227                        tp->dev->name,
1228                        (tp->link_config.active_speed == SPEED_1000 ?
1229                         1000 :
1230                         (tp->link_config.active_speed == SPEED_100 ?
1231                          100 : 10)),
1232                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1233                         "full" : "half"));
1234
1235                 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1236                        "%s for RX.\n",
1237                        tp->dev->name,
1238                        (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1239                        (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1240         }
1241 }
1242
1243 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1244 {
1245         u32 new_tg3_flags = 0;
1246         u32 old_rx_mode = tp->rx_mode;
1247         u32 old_tx_mode = tp->tx_mode;
1248
1249         if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1250                 if (local_adv & ADVERTISE_PAUSE_CAP) {
1251                         if (local_adv & ADVERTISE_PAUSE_ASYM) {
1252                                 if (remote_adv & LPA_PAUSE_CAP)
1253                                         new_tg3_flags |=
1254                                                 (TG3_FLAG_RX_PAUSE |
1255                                                 TG3_FLAG_TX_PAUSE);
1256                                 else if (remote_adv & LPA_PAUSE_ASYM)
1257                                         new_tg3_flags |=
1258                                                 (TG3_FLAG_RX_PAUSE);
1259                         } else {
1260                                 if (remote_adv & LPA_PAUSE_CAP)
1261                                         new_tg3_flags |=
1262                                                 (TG3_FLAG_RX_PAUSE |
1263                                                 TG3_FLAG_TX_PAUSE);
1264                         }
1265                 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1266                         if ((remote_adv & LPA_PAUSE_CAP) &&
1267                         (remote_adv & LPA_PAUSE_ASYM))
1268                                 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1269                 }
1270
1271                 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1272                 tp->tg3_flags |= new_tg3_flags;
1273         } else {
1274                 new_tg3_flags = tp->tg3_flags;
1275         }
1276
1277         if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1278                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1279         else
1280                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1281
1282         if (old_rx_mode != tp->rx_mode) {
1283                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1284         }
1285
1286         if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1287                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1288         else
1289                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1290
1291         if (old_tx_mode != tp->tx_mode) {
1292                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1293         }
1294 }
1295
1296 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1297 {
1298         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1299         case MII_TG3_AUX_STAT_10HALF:
1300                 *speed = SPEED_10;
1301                 *duplex = DUPLEX_HALF;
1302                 break;
1303
1304         case MII_TG3_AUX_STAT_10FULL:
1305                 *speed = SPEED_10;
1306                 *duplex = DUPLEX_FULL;
1307                 break;
1308
1309         case MII_TG3_AUX_STAT_100HALF:
1310                 *speed = SPEED_100;
1311                 *duplex = DUPLEX_HALF;
1312                 break;
1313
1314         case MII_TG3_AUX_STAT_100FULL:
1315                 *speed = SPEED_100;
1316                 *duplex = DUPLEX_FULL;
1317                 break;
1318
1319         case MII_TG3_AUX_STAT_1000HALF:
1320                 *speed = SPEED_1000;
1321                 *duplex = DUPLEX_HALF;
1322                 break;
1323
1324         case MII_TG3_AUX_STAT_1000FULL:
1325                 *speed = SPEED_1000;
1326                 *duplex = DUPLEX_FULL;
1327                 break;
1328
1329         default:
1330                 *speed = SPEED_INVALID;
1331                 *duplex = DUPLEX_INVALID;
1332                 break;
1333         };
1334 }
1335
1336 static void tg3_phy_copper_begin(struct tg3 *tp)
1337 {
1338         u32 new_adv;
1339         int i;
1340
1341         if (tp->link_config.phy_is_low_power) {
1342                 /* Entering low power mode.  Disable gigabit and
1343                  * 100baseT advertisements.
1344                  */
1345                 tg3_writephy(tp, MII_TG3_CTRL, 0);
1346
1347                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1348                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1349                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1350                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1351
1352                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1353         } else if (tp->link_config.speed == SPEED_INVALID) {
1354                 tp->link_config.advertising =
1355                         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1356                          ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
1357                          ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
1358                          ADVERTISED_Autoneg | ADVERTISED_MII);
1359
1360                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1361                         tp->link_config.advertising &=
1362                                 ~(ADVERTISED_1000baseT_Half |
1363                                   ADVERTISED_1000baseT_Full);
1364
1365                 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1366                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1367                         new_adv |= ADVERTISE_10HALF;
1368                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1369                         new_adv |= ADVERTISE_10FULL;
1370                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1371                         new_adv |= ADVERTISE_100HALF;
1372                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1373                         new_adv |= ADVERTISE_100FULL;
1374                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1375
1376                 if (tp->link_config.advertising &
1377                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1378                         new_adv = 0;
1379                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1380                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1381                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1382                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1383                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1384                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1385                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1386                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1387                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1388                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1389                 } else {
1390                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1391                 }
1392         } else {
1393                 /* Asking for a specific link mode. */
1394                 if (tp->link_config.speed == SPEED_1000) {
1395                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1396                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1397
1398                         if (tp->link_config.duplex == DUPLEX_FULL)
1399                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1400                         else
1401                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1402                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1403                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1404                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1405                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1406                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1407                 } else {
1408                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1409
1410                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1411                         if (tp->link_config.speed == SPEED_100) {
1412                                 if (tp->link_config.duplex == DUPLEX_FULL)
1413                                         new_adv |= ADVERTISE_100FULL;
1414                                 else
1415                                         new_adv |= ADVERTISE_100HALF;
1416                         } else {
1417                                 if (tp->link_config.duplex == DUPLEX_FULL)
1418                                         new_adv |= ADVERTISE_10FULL;
1419                                 else
1420                                         new_adv |= ADVERTISE_10HALF;
1421                         }
1422                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1423                 }
1424         }
1425
1426         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1427             tp->link_config.speed != SPEED_INVALID) {
1428                 u32 bmcr, orig_bmcr;
1429
1430                 tp->link_config.active_speed = tp->link_config.speed;
1431                 tp->link_config.active_duplex = tp->link_config.duplex;
1432
1433                 bmcr = 0;
1434                 switch (tp->link_config.speed) {
1435                 default:
1436                 case SPEED_10:
1437                         break;
1438
1439                 case SPEED_100:
1440                         bmcr |= BMCR_SPEED100;
1441                         break;
1442
1443                 case SPEED_1000:
1444                         bmcr |= TG3_BMCR_SPEED1000;
1445                         break;
1446                 };
1447
1448                 if (tp->link_config.duplex == DUPLEX_FULL)
1449                         bmcr |= BMCR_FULLDPLX;
1450
1451                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1452                     (bmcr != orig_bmcr)) {
1453                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1454                         for (i = 0; i < 1500; i++) {
1455                                 u32 tmp;
1456
1457                                 udelay(10);
1458                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1459                                     tg3_readphy(tp, MII_BMSR, &tmp))
1460                                         continue;
1461                                 if (!(tmp & BMSR_LSTATUS)) {
1462                                         udelay(40);
1463                                         break;
1464                                 }
1465                         }
1466                         tg3_writephy(tp, MII_BMCR, bmcr);
1467                         udelay(40);
1468                 }
1469         } else {
1470                 tg3_writephy(tp, MII_BMCR,
1471                              BMCR_ANENABLE | BMCR_ANRESTART);
1472         }
1473 }
1474
1475 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1476 {
1477         int err;
1478
1479         /* Turn off tap power management. */
1480         /* Set Extended packet length bit */
1481         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1482
1483         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1484         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1485
1486         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1487         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1488
1489         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1490         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1491
1492         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1493         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1494
1495         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1496         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1497
1498         udelay(40);
1499
1500         return err;
1501 }
1502
1503 static int tg3_copper_is_advertising_all(struct tg3 *tp)
1504 {
1505         u32 adv_reg, all_mask;
1506
1507         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1508                 return 0;
1509
1510         all_mask = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1511                     ADVERTISE_100HALF | ADVERTISE_100FULL);
1512         if ((adv_reg & all_mask) != all_mask)
1513                 return 0;
1514         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1515                 u32 tg3_ctrl;
1516
1517                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1518                         return 0;
1519
1520                 all_mask = (MII_TG3_CTRL_ADV_1000_HALF |
1521                             MII_TG3_CTRL_ADV_1000_FULL);
1522                 if ((tg3_ctrl & all_mask) != all_mask)
1523                         return 0;
1524         }
1525         return 1;
1526 }
1527
1528 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1529 {
1530         int current_link_up;
1531         u32 bmsr, dummy;
1532         u16 current_speed;
1533         u8 current_duplex;
1534         int i, err;
1535
1536         tw32(MAC_EVENT, 0);
1537
1538         tw32_f(MAC_STATUS,
1539              (MAC_STATUS_SYNC_CHANGED |
1540               MAC_STATUS_CFG_CHANGED |
1541               MAC_STATUS_MI_COMPLETION |
1542               MAC_STATUS_LNKSTATE_CHANGED));
1543         udelay(40);
1544
1545         tp->mi_mode = MAC_MI_MODE_BASE;
1546         tw32_f(MAC_MI_MODE, tp->mi_mode);
1547         udelay(80);
1548
1549         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1550
1551         /* Some third-party PHYs need to be reset on link going
1552          * down.
1553          */
1554         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1555              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1556              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1557             netif_carrier_ok(tp->dev)) {
1558                 tg3_readphy(tp, MII_BMSR, &bmsr);
1559                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1560                     !(bmsr & BMSR_LSTATUS))
1561                         force_reset = 1;
1562         }
1563         if (force_reset)
1564                 tg3_phy_reset(tp);
1565
1566         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1567                 tg3_readphy(tp, MII_BMSR, &bmsr);
1568                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1569                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1570                         bmsr = 0;
1571
1572                 if (!(bmsr & BMSR_LSTATUS)) {
1573                         err = tg3_init_5401phy_dsp(tp);
1574                         if (err)
1575                                 return err;
1576
1577                         tg3_readphy(tp, MII_BMSR, &bmsr);
1578                         for (i = 0; i < 1000; i++) {
1579                                 udelay(10);
1580                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1581                                     (bmsr & BMSR_LSTATUS)) {
1582                                         udelay(40);
1583                                         break;
1584                                 }
1585                         }
1586
1587                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1588                             !(bmsr & BMSR_LSTATUS) &&
1589                             tp->link_config.active_speed == SPEED_1000) {
1590                                 err = tg3_phy_reset(tp);
1591                                 if (!err)
1592                                         err = tg3_init_5401phy_dsp(tp);
1593                                 if (err)
1594                                         return err;
1595                         }
1596                 }
1597         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1598                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1599                 /* 5701 {A0,B0} CRC bug workaround */
1600                 tg3_writephy(tp, 0x15, 0x0a75);
1601                 tg3_writephy(tp, 0x1c, 0x8c68);
1602                 tg3_writephy(tp, 0x1c, 0x8d68);
1603                 tg3_writephy(tp, 0x1c, 0x8c68);
1604         }
1605
1606         /* Clear pending interrupts... */
1607         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1608         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1609
1610         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1611                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1612         else
1613                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1614
1615         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1616             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1617                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1618                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
1619                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1620                 else
1621                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1622         }
1623
1624         current_link_up = 0;
1625         current_speed = SPEED_INVALID;
1626         current_duplex = DUPLEX_INVALID;
1627
1628         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1629                 u32 val;
1630
1631                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1632                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1633                 if (!(val & (1 << 10))) {
1634                         val |= (1 << 10);
1635                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1636                         goto relink;
1637                 }
1638         }
1639
1640         bmsr = 0;
1641         for (i = 0; i < 100; i++) {
1642                 tg3_readphy(tp, MII_BMSR, &bmsr);
1643                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1644                     (bmsr & BMSR_LSTATUS))
1645                         break;
1646                 udelay(40);
1647         }
1648
1649         if (bmsr & BMSR_LSTATUS) {
1650                 u32 aux_stat, bmcr;
1651
1652                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1653                 for (i = 0; i < 2000; i++) {
1654                         udelay(10);
1655                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1656                             aux_stat)
1657                                 break;
1658                 }
1659
1660                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1661                                              &current_speed,
1662                                              &current_duplex);
1663
1664                 bmcr = 0;
1665                 for (i = 0; i < 200; i++) {
1666                         tg3_readphy(tp, MII_BMCR, &bmcr);
1667                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
1668                                 continue;
1669                         if (bmcr && bmcr != 0x7fff)
1670                                 break;
1671                         udelay(10);
1672                 }
1673
1674                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1675                         if (bmcr & BMCR_ANENABLE) {
1676                                 current_link_up = 1;
1677
1678                                 /* Force autoneg restart if we are exiting
1679                                  * low power mode.
1680                                  */
1681                                 if (!tg3_copper_is_advertising_all(tp))
1682                                         current_link_up = 0;
1683                         } else {
1684                                 current_link_up = 0;
1685                         }
1686                 } else {
1687                         if (!(bmcr & BMCR_ANENABLE) &&
1688                             tp->link_config.speed == current_speed &&
1689                             tp->link_config.duplex == current_duplex) {
1690                                 current_link_up = 1;
1691                         } else {
1692                                 current_link_up = 0;
1693                         }
1694                 }
1695
1696                 tp->link_config.active_speed = current_speed;
1697                 tp->link_config.active_duplex = current_duplex;
1698         }
1699
1700         if (current_link_up == 1 &&
1701             (tp->link_config.active_duplex == DUPLEX_FULL) &&
1702             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1703                 u32 local_adv, remote_adv;
1704
1705                 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1706                         local_adv = 0;
1707                 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1708
1709                 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1710                         remote_adv = 0;
1711
1712                 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1713
1714                 /* If we are not advertising full pause capability,
1715                  * something is wrong.  Bring the link down and reconfigure.
1716                  */
1717                 if (local_adv != ADVERTISE_PAUSE_CAP) {
1718                         current_link_up = 0;
1719                 } else {
1720                         tg3_setup_flow_control(tp, local_adv, remote_adv);
1721                 }
1722         }
1723 relink:
1724         if (current_link_up == 0) {
1725                 u32 tmp;
1726
1727                 tg3_phy_copper_begin(tp);
1728
1729                 tg3_readphy(tp, MII_BMSR, &tmp);
1730                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1731                     (tmp & BMSR_LSTATUS))
1732                         current_link_up = 1;
1733         }
1734
1735         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1736         if (current_link_up == 1) {
1737                 if (tp->link_config.active_speed == SPEED_100 ||
1738                     tp->link_config.active_speed == SPEED_10)
1739                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1740                 else
1741                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1742         } else
1743                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1744
1745         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1746         if (tp->link_config.active_duplex == DUPLEX_HALF)
1747                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1748
1749         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1750         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1751                 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1752                     (current_link_up == 1 &&
1753                      tp->link_config.active_speed == SPEED_10))
1754                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1755         } else {
1756                 if (current_link_up == 1)
1757                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1758         }
1759
1760         /* ??? Without this setting Netgear GA302T PHY does not
1761          * ??? send/receive packets...
1762          */
1763         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
1764             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
1765                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
1766                 tw32_f(MAC_MI_MODE, tp->mi_mode);
1767                 udelay(80);
1768         }
1769
1770         tw32_f(MAC_MODE, tp->mac_mode);
1771         udelay(40);
1772
1773         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
1774                 /* Polled via timer. */
1775                 tw32_f(MAC_EVENT, 0);
1776         } else {
1777                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
1778         }
1779         udelay(40);
1780
1781         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
1782             current_link_up == 1 &&
1783             tp->link_config.active_speed == SPEED_1000 &&
1784             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
1785              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
1786                 udelay(120);
1787                 tw32_f(MAC_STATUS,
1788                      (MAC_STATUS_SYNC_CHANGED |
1789                       MAC_STATUS_CFG_CHANGED));
1790                 udelay(40);
1791                 tg3_write_mem(tp,
1792                               NIC_SRAM_FIRMWARE_MBOX,
1793                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
1794         }
1795
1796         if (current_link_up != netif_carrier_ok(tp->dev)) {
1797                 if (current_link_up)
1798                         netif_carrier_on(tp->dev);
1799                 else
1800                         netif_carrier_off(tp->dev);
1801                 tg3_link_report(tp);
1802         }
1803
1804         return 0;
1805 }
1806
1807 struct tg3_fiber_aneginfo {
1808         int state;
1809 #define ANEG_STATE_UNKNOWN              0
1810 #define ANEG_STATE_AN_ENABLE            1
1811 #define ANEG_STATE_RESTART_INIT         2
1812 #define ANEG_STATE_RESTART              3
1813 #define ANEG_STATE_DISABLE_LINK_OK      4
1814 #define ANEG_STATE_ABILITY_DETECT_INIT  5
1815 #define ANEG_STATE_ABILITY_DETECT       6
1816 #define ANEG_STATE_ACK_DETECT_INIT      7
1817 #define ANEG_STATE_ACK_DETECT           8
1818 #define ANEG_STATE_COMPLETE_ACK_INIT    9
1819 #define ANEG_STATE_COMPLETE_ACK         10
1820 #define ANEG_STATE_IDLE_DETECT_INIT     11
1821 #define ANEG_STATE_IDLE_DETECT          12
1822 #define ANEG_STATE_LINK_OK              13
1823 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
1824 #define ANEG_STATE_NEXT_PAGE_WAIT       15
1825
1826         u32 flags;
1827 #define MR_AN_ENABLE            0x00000001
1828 #define MR_RESTART_AN           0x00000002
1829 #define MR_AN_COMPLETE          0x00000004
1830 #define MR_PAGE_RX              0x00000008
1831 #define MR_NP_LOADED            0x00000010
1832 #define MR_TOGGLE_TX            0x00000020
1833 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
1834 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
1835 #define MR_LP_ADV_SYM_PAUSE     0x00000100
1836 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
1837 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
1838 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
1839 #define MR_LP_ADV_NEXT_PAGE     0x00001000
1840 #define MR_TOGGLE_RX            0x00002000
1841 #define MR_NP_RX                0x00004000
1842
1843 #define MR_LINK_OK              0x80000000
1844
1845         unsigned long link_time, cur_time;
1846
1847         u32 ability_match_cfg;
1848         int ability_match_count;
1849
1850         char ability_match, idle_match, ack_match;
1851
1852         u32 txconfig, rxconfig;
1853 #define ANEG_CFG_NP             0x00000080
1854 #define ANEG_CFG_ACK            0x00000040
1855 #define ANEG_CFG_RF2            0x00000020
1856 #define ANEG_CFG_RF1            0x00000010
1857 #define ANEG_CFG_PS2            0x00000001
1858 #define ANEG_CFG_PS1            0x00008000
1859 #define ANEG_CFG_HD             0x00004000
1860 #define ANEG_CFG_FD             0x00002000
1861 #define ANEG_CFG_INVAL          0x00001f06
1862
1863 };
1864 #define ANEG_OK         0
1865 #define ANEG_DONE       1
1866 #define ANEG_TIMER_ENAB 2
1867 #define ANEG_FAILED     -1
1868
1869 #define ANEG_STATE_SETTLE_TIME  10000
1870
1871 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
1872                                    struct tg3_fiber_aneginfo *ap)
1873 {
1874         unsigned long delta;
1875         u32 rx_cfg_reg;
1876         int ret;
1877
1878         if (ap->state == ANEG_STATE_UNKNOWN) {
1879                 ap->rxconfig = 0;
1880                 ap->link_time = 0;
1881                 ap->cur_time = 0;
1882                 ap->ability_match_cfg = 0;
1883                 ap->ability_match_count = 0;
1884                 ap->ability_match = 0;
1885                 ap->idle_match = 0;
1886                 ap->ack_match = 0;
1887         }
1888         ap->cur_time++;
1889
1890         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
1891                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
1892
1893                 if (rx_cfg_reg != ap->ability_match_cfg) {
1894                         ap->ability_match_cfg = rx_cfg_reg;
1895                         ap->ability_match = 0;
1896                         ap->ability_match_count = 0;
1897                 } else {
1898                         if (++ap->ability_match_count > 1) {
1899                                 ap->ability_match = 1;
1900                                 ap->ability_match_cfg = rx_cfg_reg;
1901                         }
1902                 }
1903                 if (rx_cfg_reg & ANEG_CFG_ACK)
1904                         ap->ack_match = 1;
1905                 else
1906                         ap->ack_match = 0;
1907
1908                 ap->idle_match = 0;
1909         } else {
1910                 ap->idle_match = 1;
1911                 ap->ability_match_cfg = 0;
1912                 ap->ability_match_count = 0;
1913                 ap->ability_match = 0;
1914                 ap->ack_match = 0;
1915
1916                 rx_cfg_reg = 0;
1917         }
1918
1919         ap->rxconfig = rx_cfg_reg;
1920         ret = ANEG_OK;
1921
1922         switch(ap->state) {
1923         case ANEG_STATE_UNKNOWN:
1924                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
1925                         ap->state = ANEG_STATE_AN_ENABLE;
1926
1927                 /* fallthru */
1928         case ANEG_STATE_AN_ENABLE:
1929                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
1930                 if (ap->flags & MR_AN_ENABLE) {
1931                         ap->link_time = 0;
1932                         ap->cur_time = 0;
1933                         ap->ability_match_cfg = 0;
1934                         ap->ability_match_count = 0;
1935                         ap->ability_match = 0;
1936                         ap->idle_match = 0;
1937                         ap->ack_match = 0;
1938
1939                         ap->state = ANEG_STATE_RESTART_INIT;
1940                 } else {
1941                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
1942                 }
1943                 break;
1944
1945         case ANEG_STATE_RESTART_INIT:
1946                 ap->link_time = ap->cur_time;
1947                 ap->flags &= ~(MR_NP_LOADED);
1948                 ap->txconfig = 0;
1949                 tw32(MAC_TX_AUTO_NEG, 0);
1950                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1951                 tw32_f(MAC_MODE, tp->mac_mode);
1952                 udelay(40);
1953
1954                 ret = ANEG_TIMER_ENAB;
1955                 ap->state = ANEG_STATE_RESTART;
1956
1957                 /* fallthru */
1958         case ANEG_STATE_RESTART:
1959                 delta = ap->cur_time - ap->link_time;
1960                 if (delta > ANEG_STATE_SETTLE_TIME) {
1961                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
1962                 } else {
1963                         ret = ANEG_TIMER_ENAB;
1964                 }
1965                 break;
1966
1967         case ANEG_STATE_DISABLE_LINK_OK:
1968                 ret = ANEG_DONE;
1969                 break;
1970
1971         case ANEG_STATE_ABILITY_DETECT_INIT:
1972                 ap->flags &= ~(MR_TOGGLE_TX);
1973                 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
1974                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1975                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1976                 tw32_f(MAC_MODE, tp->mac_mode);
1977                 udelay(40);
1978
1979                 ap->state = ANEG_STATE_ABILITY_DETECT;
1980                 break;
1981
1982         case ANEG_STATE_ABILITY_DETECT:
1983                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
1984                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
1985                 }
1986                 break;
1987
1988         case ANEG_STATE_ACK_DETECT_INIT:
1989                 ap->txconfig |= ANEG_CFG_ACK;
1990                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1991                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1992                 tw32_f(MAC_MODE, tp->mac_mode);
1993                 udelay(40);
1994
1995                 ap->state = ANEG_STATE_ACK_DETECT;
1996
1997                 /* fallthru */
1998         case ANEG_STATE_ACK_DETECT:
1999                 if (ap->ack_match != 0) {
2000                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2001                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2002                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2003                         } else {
2004                                 ap->state = ANEG_STATE_AN_ENABLE;
2005                         }
2006                 } else if (ap->ability_match != 0 &&
2007                            ap->rxconfig == 0) {
2008                         ap->state = ANEG_STATE_AN_ENABLE;
2009                 }
2010                 break;
2011
2012         case ANEG_STATE_COMPLETE_ACK_INIT:
2013                 if (ap->rxconfig & ANEG_CFG_INVAL) {
2014                         ret = ANEG_FAILED;
2015                         break;
2016                 }
2017                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2018                                MR_LP_ADV_HALF_DUPLEX |
2019                                MR_LP_ADV_SYM_PAUSE |
2020                                MR_LP_ADV_ASYM_PAUSE |
2021                                MR_LP_ADV_REMOTE_FAULT1 |
2022                                MR_LP_ADV_REMOTE_FAULT2 |
2023                                MR_LP_ADV_NEXT_PAGE |
2024                                MR_TOGGLE_RX |
2025                                MR_NP_RX);
2026                 if (ap->rxconfig & ANEG_CFG_FD)
2027                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2028                 if (ap->rxconfig & ANEG_CFG_HD)
2029                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2030                 if (ap->rxconfig & ANEG_CFG_PS1)
2031                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
2032                 if (ap->rxconfig & ANEG_CFG_PS2)
2033                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2034                 if (ap->rxconfig & ANEG_CFG_RF1)
2035                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2036                 if (ap->rxconfig & ANEG_CFG_RF2)
2037                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2038                 if (ap->rxconfig & ANEG_CFG_NP)
2039                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
2040
2041                 ap->link_time = ap->cur_time;
2042
2043                 ap->flags ^= (MR_TOGGLE_TX);
2044                 if (ap->rxconfig & 0x0008)
2045                         ap->flags |= MR_TOGGLE_RX;
2046                 if (ap->rxconfig & ANEG_CFG_NP)
2047                         ap->flags |= MR_NP_RX;
2048                 ap->flags |= MR_PAGE_RX;
2049
2050                 ap->state = ANEG_STATE_COMPLETE_ACK;
2051                 ret = ANEG_TIMER_ENAB;
2052                 break;
2053
2054         case ANEG_STATE_COMPLETE_ACK:
2055                 if (ap->ability_match != 0 &&
2056                     ap->rxconfig == 0) {
2057                         ap->state = ANEG_STATE_AN_ENABLE;
2058                         break;
2059                 }
2060                 delta = ap->cur_time - ap->link_time;
2061                 if (delta > ANEG_STATE_SETTLE_TIME) {
2062                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2063                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2064                         } else {
2065                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2066                                     !(ap->flags & MR_NP_RX)) {
2067                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2068                                 } else {
2069                                         ret = ANEG_FAILED;
2070                                 }
2071                         }
2072                 }
2073                 break;
2074
2075         case ANEG_STATE_IDLE_DETECT_INIT:
2076                 ap->link_time = ap->cur_time;
2077                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2078                 tw32_f(MAC_MODE, tp->mac_mode);
2079                 udelay(40);
2080
2081                 ap->state = ANEG_STATE_IDLE_DETECT;
2082                 ret = ANEG_TIMER_ENAB;
2083                 break;
2084
2085         case ANEG_STATE_IDLE_DETECT:
2086                 if (ap->ability_match != 0 &&
2087                     ap->rxconfig == 0) {
2088                         ap->state = ANEG_STATE_AN_ENABLE;
2089                         break;
2090                 }
2091                 delta = ap->cur_time - ap->link_time;
2092                 if (delta > ANEG_STATE_SETTLE_TIME) {
2093                         /* XXX another gem from the Broadcom driver :( */
2094                         ap->state = ANEG_STATE_LINK_OK;
2095                 }
2096                 break;
2097
2098         case ANEG_STATE_LINK_OK:
2099                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2100                 ret = ANEG_DONE;
2101                 break;
2102
2103         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2104                 /* ??? unimplemented */
2105                 break;
2106
2107         case ANEG_STATE_NEXT_PAGE_WAIT:
2108                 /* ??? unimplemented */
2109                 break;
2110
2111         default:
2112                 ret = ANEG_FAILED;
2113                 break;
2114         };
2115
2116         return ret;
2117 }
2118
2119 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2120 {
2121         int res = 0;
2122         struct tg3_fiber_aneginfo aninfo;
2123         int status = ANEG_FAILED;
2124         unsigned int tick;
2125         u32 tmp;
2126
2127         tw32_f(MAC_TX_AUTO_NEG, 0);
2128
2129         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2130         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2131         udelay(40);
2132
2133         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2134         udelay(40);
2135
2136         memset(&aninfo, 0, sizeof(aninfo));
2137         aninfo.flags |= MR_AN_ENABLE;
2138         aninfo.state = ANEG_STATE_UNKNOWN;
2139         aninfo.cur_time = 0;
2140         tick = 0;
2141         while (++tick < 195000) {
2142                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2143                 if (status == ANEG_DONE || status == ANEG_FAILED)
2144                         break;
2145
2146                 udelay(1);
2147         }
2148
2149         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2150         tw32_f(MAC_MODE, tp->mac_mode);
2151         udelay(40);
2152
2153         *flags = aninfo.flags;
2154
2155         if (status == ANEG_DONE &&
2156             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2157                              MR_LP_ADV_FULL_DUPLEX)))
2158                 res = 1;
2159
2160         return res;
2161 }
2162
2163 static void tg3_init_bcm8002(struct tg3 *tp)
2164 {
2165         u32 mac_status = tr32(MAC_STATUS);
2166         int i;
2167
2168         /* Reset when initting first time or we have a link. */
2169         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2170             !(mac_status & MAC_STATUS_PCS_SYNCED))
2171                 return;
2172
2173         /* Set PLL lock range. */
2174         tg3_writephy(tp, 0x16, 0x8007);
2175
2176         /* SW reset */
2177         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2178
2179         /* Wait for reset to complete. */
2180         /* XXX schedule_timeout() ... */
2181         for (i = 0; i < 500; i++)
2182                 udelay(10);
2183
2184         /* Config mode; select PMA/Ch 1 regs. */
2185         tg3_writephy(tp, 0x10, 0x8411);
2186
2187         /* Enable auto-lock and comdet, select txclk for tx. */
2188         tg3_writephy(tp, 0x11, 0x0a10);
2189
2190         tg3_writephy(tp, 0x18, 0x00a0);
2191         tg3_writephy(tp, 0x16, 0x41ff);
2192
2193         /* Assert and deassert POR. */
2194         tg3_writephy(tp, 0x13, 0x0400);
2195         udelay(40);
2196         tg3_writephy(tp, 0x13, 0x0000);
2197
2198         tg3_writephy(tp, 0x11, 0x0a50);
2199         udelay(40);
2200         tg3_writephy(tp, 0x11, 0x0a10);
2201
2202         /* Wait for signal to stabilize */
2203         /* XXX schedule_timeout() ... */
2204         for (i = 0; i < 15000; i++)
2205                 udelay(10);
2206
2207         /* Deselect the channel register so we can read the PHYID
2208          * later.
2209          */
2210         tg3_writephy(tp, 0x10, 0x8011);
2211 }
2212
2213 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2214 {
2215         u32 sg_dig_ctrl, sg_dig_status;
2216         u32 serdes_cfg, expected_sg_dig_ctrl;
2217         int workaround, port_a;
2218         int current_link_up;
2219
2220         serdes_cfg = 0;
2221         expected_sg_dig_ctrl = 0;
2222         workaround = 0;
2223         port_a = 1;
2224         current_link_up = 0;
2225
2226         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2227             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2228                 workaround = 1;
2229                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2230                         port_a = 0;
2231
2232                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2233                 /* preserve bits 20-23 for voltage regulator */
2234                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2235         }
2236
2237         sg_dig_ctrl = tr32(SG_DIG_CTRL);
2238
2239         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2240                 if (sg_dig_ctrl & (1 << 31)) {
2241                         if (workaround) {
2242                                 u32 val = serdes_cfg;
2243
2244                                 if (port_a)
2245                                         val |= 0xc010000;
2246                                 else
2247                                         val |= 0x4010000;
2248                                 tw32_f(MAC_SERDES_CFG, val);
2249                         }
2250                         tw32_f(SG_DIG_CTRL, 0x01388400);
2251                 }
2252                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2253                         tg3_setup_flow_control(tp, 0, 0);
2254                         current_link_up = 1;
2255                 }
2256                 goto out;
2257         }
2258
2259         /* Want auto-negotiation.  */
2260         expected_sg_dig_ctrl = 0x81388400;
2261
2262         /* Pause capability */
2263         expected_sg_dig_ctrl |= (1 << 11);
2264
2265         /* Asymettric pause */
2266         expected_sg_dig_ctrl |= (1 << 12);
2267
2268         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2269                 if (workaround)
2270                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2271                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2272                 udelay(5);
2273                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2274
2275                 tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2276         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2277                                  MAC_STATUS_SIGNAL_DET)) {
2278                 int i;
2279
2280                 /* Giver time to negotiate (~200ms) */
2281                 for (i = 0; i < 40000; i++) {
2282                         sg_dig_status = tr32(SG_DIG_STATUS);
2283                         if (sg_dig_status & (0x3))
2284                                 break;
2285                         udelay(5);
2286                 }
2287                 mac_status = tr32(MAC_STATUS);
2288
2289                 if ((sg_dig_status & (1 << 1)) &&
2290                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
2291                         u32 local_adv, remote_adv;
2292
2293                         local_adv = ADVERTISE_PAUSE_CAP;
2294                         remote_adv = 0;
2295                         if (sg_dig_status & (1 << 19))
2296                                 remote_adv |= LPA_PAUSE_CAP;
2297                         if (sg_dig_status & (1 << 20))
2298                                 remote_adv |= LPA_PAUSE_ASYM;
2299
2300                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2301                         current_link_up = 1;
2302                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2303                 } else if (!(sg_dig_status & (1 << 1))) {
2304                         if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED)
2305                                 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2306                         else {
2307                                 if (workaround) {
2308                                         u32 val = serdes_cfg;
2309
2310                                         if (port_a)
2311                                                 val |= 0xc010000;
2312                                         else
2313                                                 val |= 0x4010000;
2314
2315                                         tw32_f(MAC_SERDES_CFG, val);
2316                                 }
2317
2318                                 tw32_f(SG_DIG_CTRL, 0x01388400);
2319                                 udelay(40);
2320
2321                                 /* Link parallel detection - link is up */
2322                                 /* only if we have PCS_SYNC and not */
2323                                 /* receiving config code words */
2324                                 mac_status = tr32(MAC_STATUS);
2325                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2326                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
2327                                         tg3_setup_flow_control(tp, 0, 0);
2328                                         current_link_up = 1;
2329                                 }
2330                         }
2331                 }
2332         }
2333
2334 out:
2335         return current_link_up;
2336 }
2337
2338 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2339 {
2340         int current_link_up = 0;
2341
2342         if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2343                 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2344                 goto out;
2345         }
2346
2347         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2348                 u32 flags;
2349                 int i;
2350
2351                 if (fiber_autoneg(tp, &flags)) {
2352                         u32 local_adv, remote_adv;
2353
2354                         local_adv = ADVERTISE_PAUSE_CAP;
2355                         remote_adv = 0;
2356                         if (flags & MR_LP_ADV_SYM_PAUSE)
2357                                 remote_adv |= LPA_PAUSE_CAP;
2358                         if (flags & MR_LP_ADV_ASYM_PAUSE)
2359                                 remote_adv |= LPA_PAUSE_ASYM;
2360
2361                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2362
2363                         tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2364                         current_link_up = 1;
2365                 }
2366                 for (i = 0; i < 30; i++) {
2367                         udelay(20);
2368                         tw32_f(MAC_STATUS,
2369                                (MAC_STATUS_SYNC_CHANGED |
2370                                 MAC_STATUS_CFG_CHANGED));
2371                         udelay(40);
2372                         if ((tr32(MAC_STATUS) &
2373                              (MAC_STATUS_SYNC_CHANGED |
2374                               MAC_STATUS_CFG_CHANGED)) == 0)
2375                                 break;
2376                 }
2377
2378                 mac_status = tr32(MAC_STATUS);
2379                 if (current_link_up == 0 &&
2380                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
2381                     !(mac_status & MAC_STATUS_RCVD_CFG))
2382                         current_link_up = 1;
2383         } else {
2384                 /* Forcing 1000FD link up. */
2385                 current_link_up = 1;
2386                 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2387
2388                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2389                 udelay(40);
2390         }
2391
2392 out:
2393         return current_link_up;
2394 }
2395
2396 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2397 {
2398         u32 orig_pause_cfg;
2399         u16 orig_active_speed;
2400         u8 orig_active_duplex;
2401         u32 mac_status;
2402         int current_link_up;
2403         int i;
2404
2405         orig_pause_cfg =
2406                 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2407                                   TG3_FLAG_TX_PAUSE));
2408         orig_active_speed = tp->link_config.active_speed;
2409         orig_active_duplex = tp->link_config.active_duplex;
2410
2411         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2412             netif_carrier_ok(tp->dev) &&
2413             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2414                 mac_status = tr32(MAC_STATUS);
2415                 mac_status &= (MAC_STATUS_PCS_SYNCED |
2416                                MAC_STATUS_SIGNAL_DET |
2417                                MAC_STATUS_CFG_CHANGED |
2418                                MAC_STATUS_RCVD_CFG);
2419                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2420                                    MAC_STATUS_SIGNAL_DET)) {
2421                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2422                                             MAC_STATUS_CFG_CHANGED));
2423                         return 0;
2424                 }
2425         }
2426
2427         tw32_f(MAC_TX_AUTO_NEG, 0);
2428
2429         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2430         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2431         tw32_f(MAC_MODE, tp->mac_mode);
2432         udelay(40);
2433
2434         if (tp->phy_id == PHY_ID_BCM8002)
2435                 tg3_init_bcm8002(tp);
2436
2437         /* Enable link change event even when serdes polling.  */
2438         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2439         udelay(40);
2440
2441         current_link_up = 0;
2442         mac_status = tr32(MAC_STATUS);
2443
2444         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2445                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2446         else
2447                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2448
2449         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2450         tw32_f(MAC_MODE, tp->mac_mode);
2451         udelay(40);
2452
2453         tp->hw_status->status =
2454                 (SD_STATUS_UPDATED |
2455                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2456
2457         for (i = 0; i < 100; i++) {
2458                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2459                                     MAC_STATUS_CFG_CHANGED));
2460                 udelay(5);
2461                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2462                                          MAC_STATUS_CFG_CHANGED)) == 0)
2463                         break;
2464         }
2465
2466         mac_status = tr32(MAC_STATUS);
2467         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2468                 current_link_up = 0;
2469                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2470                         tw32_f(MAC_MODE, (tp->mac_mode |
2471                                           MAC_MODE_SEND_CONFIGS));
2472                         udelay(1);
2473                         tw32_f(MAC_MODE, tp->mac_mode);
2474                 }
2475         }
2476
2477         if (current_link_up == 1) {
2478                 tp->link_config.active_speed = SPEED_1000;
2479                 tp->link_config.active_duplex = DUPLEX_FULL;
2480                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2481                                     LED_CTRL_LNKLED_OVERRIDE |
2482                                     LED_CTRL_1000MBPS_ON));
2483         } else {
2484                 tp->link_config.active_speed = SPEED_INVALID;
2485                 tp->link_config.active_duplex = DUPLEX_INVALID;
2486                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2487                                     LED_CTRL_LNKLED_OVERRIDE |
2488                                     LED_CTRL_TRAFFIC_OVERRIDE));
2489         }
2490
2491         if (current_link_up != netif_carrier_ok(tp->dev)) {
2492                 if (current_link_up)
2493                         netif_carrier_on(tp->dev);
2494                 else
2495                         netif_carrier_off(tp->dev);
2496                 tg3_link_report(tp);
2497         } else {
2498                 u32 now_pause_cfg =
2499                         tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2500                                          TG3_FLAG_TX_PAUSE);
2501                 if (orig_pause_cfg != now_pause_cfg ||
2502                     orig_active_speed != tp->link_config.active_speed ||
2503                     orig_active_duplex != tp->link_config.active_duplex)
2504                         tg3_link_report(tp);
2505         }
2506
2507         return 0;
2508 }
2509
2510 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2511 {
2512         int err;
2513
2514         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2515                 err = tg3_setup_fiber_phy(tp, force_reset);
2516         } else {
2517                 err = tg3_setup_copper_phy(tp, force_reset);
2518         }
2519
2520         if (tp->link_config.active_speed == SPEED_1000 &&
2521             tp->link_config.active_duplex == DUPLEX_HALF)
2522                 tw32(MAC_TX_LENGTHS,
2523                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2524                       (6 << TX_LENGTHS_IPG_SHIFT) |
2525                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2526         else
2527                 tw32(MAC_TX_LENGTHS,
2528                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2529                       (6 << TX_LENGTHS_IPG_SHIFT) |
2530                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2531
2532         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2533                 if (netif_carrier_ok(tp->dev)) {
2534                         tw32(HOSTCC_STAT_COAL_TICKS,
2535                              tp->coal.stats_block_coalesce_usecs);
2536                 } else {
2537                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
2538                 }
2539         }
2540
2541         return err;
2542 }
2543
2544 /* Tigon3 never reports partial packet sends.  So we do not
2545  * need special logic to handle SKBs that have not had all
2546  * of their frags sent yet, like SunGEM does.
2547  */
2548 static void tg3_tx(struct tg3 *tp)
2549 {
2550         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
2551         u32 sw_idx = tp->tx_cons;
2552
2553         while (sw_idx != hw_idx) {
2554                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
2555                 struct sk_buff *skb = ri->skb;
2556                 int i;
2557
2558                 if (unlikely(skb == NULL))
2559                         BUG();
2560
2561                 pci_unmap_single(tp->pdev,
2562                                  pci_unmap_addr(ri, mapping),
2563                                  skb_headlen(skb),
2564                                  PCI_DMA_TODEVICE);
2565
2566                 ri->skb = NULL;
2567
2568                 sw_idx = NEXT_TX(sw_idx);
2569
2570                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2571                         if (unlikely(sw_idx == hw_idx))
2572                                 BUG();
2573
2574                         ri = &tp->tx_buffers[sw_idx];
2575                         if (unlikely(ri->skb != NULL))
2576                                 BUG();
2577
2578                         pci_unmap_page(tp->pdev,
2579                                        pci_unmap_addr(ri, mapping),
2580                                        skb_shinfo(skb)->frags[i].size,
2581                                        PCI_DMA_TODEVICE);
2582
2583                         sw_idx = NEXT_TX(sw_idx);
2584                 }
2585
2586                 dev_kfree_skb(skb);
2587         }
2588
2589         tp->tx_cons = sw_idx;
2590
2591         if (netif_queue_stopped(tp->dev) &&
2592             (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH))
2593                 netif_wake_queue(tp->dev);
2594 }
2595
2596 /* Returns size of skb allocated or < 0 on error.
2597  *
2598  * We only need to fill in the address because the other members
2599  * of the RX descriptor are invariant, see tg3_init_rings.
2600  *
2601  * Note the purposeful assymetry of cpu vs. chip accesses.  For
2602  * posting buffers we only dirty the first cache line of the RX
2603  * descriptor (containing the address).  Whereas for the RX status
2604  * buffers the cpu only reads the last cacheline of the RX descriptor
2605  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
2606  */
2607 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
2608                             int src_idx, u32 dest_idx_unmasked)
2609 {
2610         struct tg3_rx_buffer_desc *desc;
2611         struct ring_info *map, *src_map;
2612         struct sk_buff *skb;
2613         dma_addr_t mapping;
2614         int skb_size, dest_idx;
2615
2616         src_map = NULL;
2617         switch (opaque_key) {
2618         case RXD_OPAQUE_RING_STD:
2619                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
2620                 desc = &tp->rx_std[dest_idx];
2621                 map = &tp->rx_std_buffers[dest_idx];
2622                 if (src_idx >= 0)
2623                         src_map = &tp->rx_std_buffers[src_idx];
2624                 skb_size = tp->rx_pkt_buf_sz;
2625                 break;
2626
2627         case RXD_OPAQUE_RING_JUMBO:
2628                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
2629                 desc = &tp->rx_jumbo[dest_idx];
2630                 map = &tp->rx_jumbo_buffers[dest_idx];
2631                 if (src_idx >= 0)
2632                         src_map = &tp->rx_jumbo_buffers[src_idx];
2633                 skb_size = RX_JUMBO_PKT_BUF_SZ;
2634                 break;
2635
2636         default:
2637                 return -EINVAL;
2638         };
2639
2640         /* Do not overwrite any of the map or rp information
2641          * until we are sure we can commit to a new buffer.
2642          *
2643          * Callers depend upon this behavior and assume that
2644          * we leave everything unchanged if we fail.
2645          */
2646         skb = dev_alloc_skb(skb_size);
2647         if (skb == NULL)
2648                 return -ENOMEM;
2649
2650         skb->dev = tp->dev;
2651         skb_reserve(skb, tp->rx_offset);
2652
2653         mapping = pci_map_single(tp->pdev, skb->data,
2654                                  skb_size - tp->rx_offset,
2655                                  PCI_DMA_FROMDEVICE);
2656
2657         map->skb = skb;
2658         pci_unmap_addr_set(map, mapping, mapping);
2659
2660         if (src_map != NULL)
2661                 src_map->skb = NULL;
2662
2663         desc->addr_hi = ((u64)mapping >> 32);
2664         desc->addr_lo = ((u64)mapping & 0xffffffff);
2665
2666         return skb_size;
2667 }
2668
2669 /* We only need to move over in the address because the other
2670  * members of the RX descriptor are invariant.  See notes above
2671  * tg3_alloc_rx_skb for full details.
2672  */
2673 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
2674                            int src_idx, u32 dest_idx_unmasked)
2675 {
2676         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
2677         struct ring_info *src_map, *dest_map;
2678         int dest_idx;
2679
2680         switch (opaque_key) {
2681         case RXD_OPAQUE_RING_STD:
2682                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
2683                 dest_desc = &tp->rx_std[dest_idx];
2684                 dest_map = &tp->rx_std_buffers[dest_idx];
2685                 src_desc = &tp->rx_std[src_idx];
2686                 src_map = &tp->rx_std_buffers[src_idx];
2687                 break;
2688
2689         case RXD_OPAQUE_RING_JUMBO:
2690                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
2691                 dest_desc = &tp->rx_jumbo[dest_idx];
2692                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
2693                 src_desc = &tp->rx_jumbo[src_idx];
2694                 src_map = &tp->rx_jumbo_buffers[src_idx];
2695                 break;
2696
2697         default:
2698                 return;
2699         };
2700
2701         dest_map->skb = src_map->skb;
2702         pci_unmap_addr_set(dest_map, mapping,
2703                            pci_unmap_addr(src_map, mapping));
2704         dest_desc->addr_hi = src_desc->addr_hi;
2705         dest_desc->addr_lo = src_desc->addr_lo;
2706
2707         src_map->skb = NULL;
2708 }
2709
2710 #if TG3_VLAN_TAG_USED
2711 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
2712 {
2713         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
2714 }
2715 #endif
2716
2717 /* The RX ring scheme is composed of multiple rings which post fresh
2718  * buffers to the chip, and one special ring the chip uses to report
2719  * status back to the host.
2720  *
2721  * The special ring reports the status of received packets to the
2722  * host.  The chip does not write into the original descriptor the
2723  * RX buffer was obtained from.  The chip simply takes the original
2724  * descriptor as provided by the host, updates the status and length
2725  * field, then writes this into the next status ring entry.
2726  *
2727  * Each ring the host uses to post buffers to the chip is described
2728  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
2729  * it is first placed into the on-chip ram.  When the packet's length
2730  * is known, it walks down the TG3_BDINFO entries to select the ring.
2731  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
2732  * which is within the range of the new packet's length is chosen.
2733  *
2734  * The "separate ring for rx status" scheme may sound queer, but it makes
2735  * sense from a cache coherency perspective.  If only the host writes
2736  * to the buffer post rings, and only the chip writes to the rx status
2737  * rings, then cache lines never move beyond shared-modified state.
2738  * If both the host and chip were to write into the same ring, cache line
2739  * eviction could occur since both entities want it in an exclusive state.
2740  */
2741 static int tg3_rx(struct tg3 *tp, int budget)
2742 {
2743         u32 work_mask;
2744         u32 sw_idx = tp->rx_rcb_ptr;
2745         u16 hw_idx;
2746         int received;
2747
2748         hw_idx = tp->hw_status->idx[0].rx_producer;
2749         /*
2750          * We need to order the read of hw_idx and the read of
2751          * the opaque cookie.
2752          */
2753         rmb();
2754         work_mask = 0;
2755         received = 0;
2756         while (sw_idx != hw_idx && budget > 0) {
2757                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
2758                 unsigned int len;
2759                 struct sk_buff *skb;
2760                 dma_addr_t dma_addr;
2761                 u32 opaque_key, desc_idx, *post_ptr;
2762
2763                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
2764                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
2765                 if (opaque_key == RXD_OPAQUE_RING_STD) {
2766                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
2767                                                   mapping);
2768                         skb = tp->rx_std_buffers[desc_idx].skb;
2769                         post_ptr = &tp->rx_std_ptr;
2770                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
2771                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
2772                                                   mapping);
2773                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
2774                         post_ptr = &tp->rx_jumbo_ptr;
2775                 }
2776                 else {
2777                         goto next_pkt_nopost;
2778                 }
2779
2780                 work_mask |= opaque_key;
2781
2782                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
2783                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
2784                 drop_it:
2785                         tg3_recycle_rx(tp, opaque_key,
2786                                        desc_idx, *post_ptr);
2787                 drop_it_no_recycle:
2788                         /* Other statistics kept track of by card. */
2789                         tp->net_stats.rx_dropped++;
2790                         goto next_pkt;
2791                 }
2792
2793                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
2794
2795                 if (len > RX_COPY_THRESHOLD
2796                         && tp->rx_offset == 2
2797                         /* rx_offset != 2 iff this is a 5701 card running
2798                          * in PCI-X mode [see tg3_get_invariants()] */
2799                 ) {
2800                         int skb_size;
2801
2802                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
2803                                                     desc_idx, *post_ptr);
2804                         if (skb_size < 0)
2805                                 goto drop_it;
2806
2807                         pci_unmap_single(tp->pdev, dma_addr,
2808                                          skb_size - tp->rx_offset,
2809                                          PCI_DMA_FROMDEVICE);
2810
2811                         skb_put(skb, len);
2812                 } else {
2813                         struct sk_buff *copy_skb;
2814
2815                         tg3_recycle_rx(tp, opaque_key,
2816                                        desc_idx, *post_ptr);
2817
2818                         copy_skb = dev_alloc_skb(len + 2);
2819                         if (copy_skb == NULL)
2820                                 goto drop_it_no_recycle;
2821
2822                         copy_skb->dev = tp->dev;
2823                         skb_reserve(copy_skb, 2);
2824                         skb_put(copy_skb, len);
2825                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
2826                         memcpy(copy_skb->data, skb->data, len);
2827                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
2828
2829                         /* We'll reuse the original ring buffer. */
2830                         skb = copy_skb;
2831                 }
2832
2833                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
2834                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
2835                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
2836                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
2837                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2838                 else
2839                         skb->ip_summed = CHECKSUM_NONE;
2840
2841                 skb->protocol = eth_type_trans(skb, tp->dev);
2842 #if TG3_VLAN_TAG_USED
2843                 if (tp->vlgrp != NULL &&
2844                     desc->type_flags & RXD_FLAG_VLAN) {
2845                         tg3_vlan_rx(tp, skb,
2846                                     desc->err_vlan & RXD_VLAN_MASK);
2847                 } else
2848 #endif
2849                         netif_receive_skb(skb);
2850
2851                 tp->dev->last_rx = jiffies;
2852                 received++;
2853                 budget--;
2854
2855 next_pkt:
2856                 (*post_ptr)++;
2857 next_pkt_nopost:
2858                 sw_idx++;
2859                 sw_idx %= TG3_RX_RCB_RING_SIZE(tp);
2860
2861                 /* Refresh hw_idx to see if there is new work */
2862                 if (sw_idx == hw_idx) {
2863                         hw_idx = tp->hw_status->idx[0].rx_producer;
2864                         rmb();
2865                 }
2866         }
2867
2868         /* ACK the status ring. */
2869         tp->rx_rcb_ptr = sw_idx;
2870         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
2871
2872         /* Refill RX ring(s). */
2873         if (work_mask & RXD_OPAQUE_RING_STD) {
2874                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
2875                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
2876                              sw_idx);
2877         }
2878         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
2879                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
2880                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
2881                              sw_idx);
2882         }
2883         mmiowb();
2884
2885         return received;
2886 }
2887
2888 static int tg3_poll(struct net_device *netdev, int *budget)
2889 {
2890         struct tg3 *tp = netdev_priv(netdev);
2891         struct tg3_hw_status *sblk = tp->hw_status;
2892         int done;
2893
2894         /* handle link change and other phy events */
2895         if (!(tp->tg3_flags &
2896               (TG3_FLAG_USE_LINKCHG_REG |
2897                TG3_FLAG_POLL_SERDES))) {
2898                 if (sblk->status & SD_STATUS_LINK_CHG) {
2899                         sblk->status = SD_STATUS_UPDATED |
2900                                 (sblk->status & ~SD_STATUS_LINK_CHG);
2901                         spin_lock(&tp->lock);
2902                         tg3_setup_phy(tp, 0);
2903                         spin_unlock(&tp->lock);
2904                 }
2905         }
2906
2907         /* run TX completion thread */
2908         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
2909                 spin_lock(&tp->tx_lock);
2910                 tg3_tx(tp);
2911                 spin_unlock(&tp->tx_lock);
2912         }
2913
2914         /* run RX thread, within the bounds set by NAPI.
2915          * All RX "locking" is done by ensuring outside
2916          * code synchronizes with dev->poll()
2917          */
2918         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
2919                 int orig_budget = *budget;
2920                 int work_done;
2921
2922                 if (orig_budget > netdev->quota)
2923                         orig_budget = netdev->quota;
2924
2925                 work_done = tg3_rx(tp, orig_budget);
2926
2927                 *budget -= work_done;
2928                 netdev->quota -= work_done;
2929         }
2930
2931         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
2932                 tp->last_tag = sblk->status_tag;
2933         rmb();
2934         sblk->status &= ~SD_STATUS_UPDATED;
2935
2936         /* if no more work, tell net stack and NIC we're done */
2937         done = !tg3_has_work(tp);
2938         if (done) {
2939                 spin_lock(&tp->lock);
2940                 netif_rx_complete(netdev);
2941                 tg3_restart_ints(tp);
2942                 spin_unlock(&tp->lock);
2943         }
2944
2945         return (done ? 0 : 1);
2946 }
2947
2948 static void tg3_irq_quiesce(struct tg3 *tp)
2949 {
2950         BUG_ON(tp->irq_sync);
2951
2952         tp->irq_sync = 1;
2953         smp_mb();
2954
2955         synchronize_irq(tp->pdev->irq);
2956 }
2957
2958 static inline int tg3_irq_sync(struct tg3 *tp)
2959 {
2960         return tp->irq_sync;
2961 }
2962
2963 /* Fully shutdown all tg3 driver activity elsewhere in the system.
2964  * If irq_sync is non-zero, then the IRQ handler must be synchronized
2965  * with as well.  Most of the time, this is not necessary except when
2966  * shutting down the device.
2967  */
2968 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
2969 {
2970         if (irq_sync)
2971                 tg3_irq_quiesce(tp);
2972         spin_lock_bh(&tp->lock);
2973         spin_lock(&tp->tx_lock);
2974 }
2975
2976 static inline void tg3_full_unlock(struct tg3 *tp)
2977 {
2978         spin_unlock(&tp->tx_lock);
2979         spin_unlock_bh(&tp->lock);
2980 }
2981
2982 /* MSI ISR - No need to check for interrupt sharing and no need to
2983  * flush status block and interrupt mailbox. PCI ordering rules
2984  * guarantee that MSI will arrive after the status block.
2985  */
2986 static irqreturn_t tg3_msi(int irq, void *dev_id, struct pt_regs *regs)
2987 {
2988         struct net_device *dev = dev_id;
2989         struct tg3 *tp = netdev_priv(dev);
2990         struct tg3_hw_status *sblk = tp->hw_status;
2991
2992         /*
2993          * Writing any value to intr-mbox-0 clears PCI INTA# and
2994          * chip-internal interrupt pending events.
2995          * Writing non-zero to intr-mbox-0 additional tells the
2996          * NIC to stop sending us irqs, engaging "in-intr-handler"
2997          * event coalescing.
2998          */
2999         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3000         tp->last_tag = sblk->status_tag;
3001         rmb();
3002         if (tg3_irq_sync(tp))
3003                 goto out;
3004         sblk->status &= ~SD_STATUS_UPDATED;
3005         if (likely(tg3_has_work(tp)))
3006                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3007         else {
3008                 /* No work, re-enable interrupts.  */
3009                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3010                              tp->last_tag << 24);
3011         }
3012 out:
3013         return IRQ_RETVAL(1);
3014 }
3015
3016 static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
3017 {
3018         struct net_device *dev = dev_id;
3019         struct tg3 *tp = netdev_priv(dev);
3020         struct tg3_hw_status *sblk = tp->hw_status;
3021         unsigned int handled = 1;
3022
3023         /* In INTx mode, it is possible for the interrupt to arrive at
3024          * the CPU before the status block posted prior to the interrupt.
3025          * Reading the PCI State register will confirm whether the
3026          * interrupt is ours and will flush the status block.
3027          */
3028         if ((sblk->status & SD_STATUS_UPDATED) ||
3029             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3030                 /*
3031                  * Writing any value to intr-mbox-0 clears PCI INTA# and
3032                  * chip-internal interrupt pending events.
3033                  * Writing non-zero to intr-mbox-0 additional tells the
3034                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3035                  * event coalescing.
3036                  */
3037                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3038                              0x00000001);
3039                 if (tg3_irq_sync(tp))
3040                         goto out;
3041                 sblk->status &= ~SD_STATUS_UPDATED;
3042                 if (likely(tg3_has_work(tp)))
3043                         netif_rx_schedule(dev);         /* schedule NAPI poll */
3044                 else {
3045                         /* No work, shared interrupt perhaps?  re-enable
3046                          * interrupts, and flush that PCI write
3047                          */
3048                         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3049                                 0x00000000);
3050                         tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
3051                 }
3052         } else {        /* shared interrupt */
3053                 handled = 0;
3054         }
3055 out:
3056         return IRQ_RETVAL(handled);
3057 }
3058
3059 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id, struct pt_regs *regs)
3060 {
3061         struct net_device *dev = dev_id;
3062         struct tg3 *tp = netdev_priv(dev);
3063         struct tg3_hw_status *sblk = tp->hw_status;
3064         unsigned int handled = 1;
3065
3066         /* In INTx mode, it is possible for the interrupt to arrive at
3067          * the CPU before the status block posted prior to the interrupt.
3068          * Reading the PCI State register will confirm whether the
3069          * interrupt is ours and will flush the status block.
3070          */
3071         if ((sblk->status & SD_STATUS_UPDATED) ||
3072             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3073                 /*
3074                  * writing any value to intr-mbox-0 clears PCI INTA# and
3075                  * chip-internal interrupt pending events.
3076                  * writing non-zero to intr-mbox-0 additional tells the
3077                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3078                  * event coalescing.
3079                  */
3080                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3081                              0x00000001);
3082                 tp->last_tag = sblk->status_tag;
3083                 rmb();
3084                 if (tg3_irq_sync(tp))
3085                         goto out;
3086                 sblk->status &= ~SD_STATUS_UPDATED;
3087                 if (likely(tg3_has_work(tp)))
3088                         netif_rx_schedule(dev);         /* schedule NAPI poll */
3089                 else {
3090                         /* no work, shared interrupt perhaps?  re-enable
3091                          * interrupts, and flush that PCI write
3092                          */
3093                         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3094                                      tp->last_tag << 24);
3095                         tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
3096                 }
3097         } else {        /* shared interrupt */
3098                 handled = 0;
3099         }
3100 out:
3101         return IRQ_RETVAL(handled);
3102 }
3103
3104 /* ISR for interrupt test */
3105 static irqreturn_t tg3_test_isr(int irq, void *dev_id,
3106                 struct pt_regs *regs)
3107 {
3108         struct net_device *dev = dev_id;
3109         struct tg3 *tp = netdev_priv(dev);
3110         struct tg3_hw_status *sblk = tp->hw_status;
3111
3112         if (sblk->status & SD_STATUS_UPDATED) {
3113                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3114                              0x00000001);
3115                 return IRQ_RETVAL(1);
3116         }
3117         return IRQ_RETVAL(0);
3118 }
3119
3120 static int tg3_init_hw(struct tg3 *);
3121 static int tg3_halt(struct tg3 *, int, int);
3122
3123 #ifdef CONFIG_NET_POLL_CONTROLLER
3124 static void tg3_poll_controller(struct net_device *dev)
3125 {
3126         struct tg3 *tp = netdev_priv(dev);
3127
3128         tg3_interrupt(tp->pdev->irq, dev, NULL);
3129 }
3130 #endif
3131
3132 static void tg3_reset_task(void *_data)
3133 {
3134         struct tg3 *tp = _data;
3135         unsigned int restart_timer;
3136
3137         tg3_netif_stop(tp);
3138
3139         tg3_full_lock(tp, 1);
3140
3141         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3142         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3143
3144         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3145         tg3_init_hw(tp);
3146
3147         tg3_netif_start(tp);
3148
3149         tg3_full_unlock(tp);
3150
3151         if (restart_timer)
3152                 mod_timer(&tp->timer, jiffies + 1);
3153 }
3154
3155 static void tg3_tx_timeout(struct net_device *dev)
3156 {
3157         struct tg3 *tp = netdev_priv(dev);
3158
3159         printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3160                dev->name);
3161
3162         schedule_work(&tp->reset_task);
3163 }
3164
3165 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3166
3167 static int tigon3_4gb_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3168                                        u32 guilty_entry, int guilty_len,
3169                                        u32 last_plus_one, u32 *start, u32 mss)
3170 {
3171         struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3172         dma_addr_t new_addr;
3173         u32 entry = *start;
3174         int i;
3175
3176         if (!new_skb) {
3177                 dev_kfree_skb(skb);
3178                 return -1;
3179         }
3180
3181         /* New SKB is guaranteed to be linear. */
3182         entry = *start;
3183         new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3184                                   PCI_DMA_TODEVICE);
3185         tg3_set_txd(tp, entry, new_addr, new_skb->len,
3186                     (skb->ip_summed == CHECKSUM_HW) ?
3187                     TXD_FLAG_TCPUDP_CSUM : 0, 1 | (mss << 1));
3188         *start = NEXT_TX(entry);
3189
3190         /* Now clean up the sw ring entries. */
3191         i = 0;
3192         while (entry != last_plus_one) {
3193                 int len;
3194
3195                 if (i == 0)
3196                         len = skb_headlen(skb);
3197                 else
3198                         len = skb_shinfo(skb)->frags[i-1].size;
3199                 pci_unmap_single(tp->pdev,
3200                                  pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3201                                  len, PCI_DMA_TODEVICE);
3202                 if (i == 0) {
3203                         tp->tx_buffers[entry].skb = new_skb;
3204                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3205                 } else {
3206                         tp->tx_buffers[entry].skb = NULL;
3207                 }
3208                 entry = NEXT_TX(entry);
3209                 i++;
3210         }
3211
3212         dev_kfree_skb(skb);
3213
3214         return 0;
3215 }
3216
3217 static void tg3_set_txd(struct tg3 *tp, int entry,
3218                         dma_addr_t mapping, int len, u32 flags,
3219                         u32 mss_and_is_end)
3220 {
3221         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3222         int is_end = (mss_and_is_end & 0x1);
3223         u32 mss = (mss_and_is_end >> 1);
3224         u32 vlan_tag = 0;
3225
3226         if (is_end)
3227                 flags |= TXD_FLAG_END;
3228         if (flags & TXD_FLAG_VLAN) {
3229                 vlan_tag = flags >> 16;
3230                 flags &= 0xffff;
3231         }
3232         vlan_tag |= (mss << TXD_MSS_SHIFT);
3233
3234         txd->addr_hi = ((u64) mapping >> 32);
3235         txd->addr_lo = ((u64) mapping & 0xffffffff);
3236         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3237         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3238 }
3239
3240 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3241 {
3242         u32 base = (u32) mapping & 0xffffffff;
3243
3244         return ((base > 0xffffdcc0) &&
3245                 (base + len + 8 < base));
3246 }
3247
3248 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3249 {
3250         struct tg3 *tp = netdev_priv(dev);
3251         dma_addr_t mapping;
3252         unsigned int i;
3253         u32 len, entry, base_flags, mss;
3254         int would_hit_hwbug;
3255
3256         len = skb_headlen(skb);
3257
3258         /* No BH disabling for tx_lock here.  We are running in BH disabled
3259          * context and TX reclaim runs via tp->poll inside of a software
3260          * interrupt.  Furthermore, IRQ processing runs lockless so we have
3261          * no IRQ context deadlocks to worry about either.  Rejoice!
3262          */
3263         if (!spin_trylock(&tp->tx_lock))
3264                 return NETDEV_TX_LOCKED;
3265
3266         /* This is a hard error, log it. */
3267         if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3268                 netif_stop_queue(dev);
3269                 spin_unlock(&tp->tx_lock);
3270                 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
3271                        dev->name);
3272                 return NETDEV_TX_BUSY;
3273         }
3274
3275         entry = tp->tx_prod;
3276         base_flags = 0;
3277         if (skb->ip_summed == CHECKSUM_HW)
3278                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3279 #if TG3_TSO_SUPPORT != 0
3280         mss = 0;
3281         if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3282             (mss = skb_shinfo(skb)->tso_size) != 0) {
3283                 int tcp_opt_len, ip_tcp_len;
3284
3285                 if (skb_header_cloned(skb) &&
3286                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3287                         dev_kfree_skb(skb);
3288                         goto out_unlock;
3289                 }
3290
3291                 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3292                 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
3293
3294                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3295                                TXD_FLAG_CPU_POST_DMA);
3296
3297                 skb->nh.iph->check = 0;
3298                 skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len);
3299                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
3300                         skb->h.th->check = 0;
3301                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
3302                 }
3303                 else {
3304                         skb->h.th->check =
3305                                 ~csum_tcpudp_magic(skb->nh.iph->saddr,
3306                                                    skb->nh.iph->daddr,
3307                                                    0, IPPROTO_TCP, 0);
3308                 }
3309
3310                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
3311                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
3312                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3313                                 int tsflags;
3314
3315                                 tsflags = ((skb->nh.iph->ihl - 5) +
3316                                            (tcp_opt_len >> 2));
3317                                 mss |= (tsflags << 11);
3318                         }
3319                 } else {
3320                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3321                                 int tsflags;
3322
3323                                 tsflags = ((skb->nh.iph->ihl - 5) +
3324                                            (tcp_opt_len >> 2));
3325                                 base_flags |= tsflags << 12;
3326                         }
3327                 }
3328         }
3329 #else
3330         mss = 0;
3331 #endif
3332 #if TG3_VLAN_TAG_USED
3333         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3334                 base_flags |= (TXD_FLAG_VLAN |
3335                                (vlan_tx_tag_get(skb) << 16));
3336 #endif
3337
3338         /* Queue skb data, a.k.a. the main skb fragment. */
3339         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3340
3341         tp->tx_buffers[entry].skb = skb;
3342         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3343
3344         would_hit_hwbug = 0;
3345
3346         if (tg3_4g_overflow_test(mapping, len))
3347                 would_hit_hwbug = entry + 1;
3348
3349         tg3_set_txd(tp, entry, mapping, len, base_flags,
3350                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3351
3352         entry = NEXT_TX(entry);
3353
3354         /* Now loop through additional data fragments, and queue them. */
3355         if (skb_shinfo(skb)->nr_frags > 0) {
3356                 unsigned int i, last;
3357
3358                 last = skb_shinfo(skb)->nr_frags - 1;
3359                 for (i = 0; i <= last; i++) {
3360                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3361
3362                         len = frag->size;
3363                         mapping = pci_map_page(tp->pdev,
3364                                                frag->page,
3365                                                frag->page_offset,
3366                                                len, PCI_DMA_TODEVICE);
3367
3368                         tp->tx_buffers[entry].skb = NULL;
3369                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3370
3371                         if (tg3_4g_overflow_test(mapping, len)) {
3372                                 /* Only one should match. */
3373                                 if (would_hit_hwbug)
3374                                         BUG();
3375                                 would_hit_hwbug = entry + 1;
3376                         }
3377
3378                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
3379                                 tg3_set_txd(tp, entry, mapping, len,
3380                                             base_flags, (i == last)|(mss << 1));
3381                         else
3382                                 tg3_set_txd(tp, entry, mapping, len,
3383                                             base_flags, (i == last));
3384
3385                         entry = NEXT_TX(entry);
3386                 }
3387         }
3388
3389         if (would_hit_hwbug) {
3390                 u32 last_plus_one = entry;
3391                 u32 start;
3392                 unsigned int len = 0;
3393
3394                 would_hit_hwbug -= 1;
3395                 entry = entry - 1 - skb_shinfo(skb)->nr_frags;
3396                 entry &= (TG3_TX_RING_SIZE - 1);
3397                 start = entry;
3398                 i = 0;
3399                 while (entry != last_plus_one) {
3400                         if (i == 0)
3401                                 len = skb_headlen(skb);
3402                         else
3403                                 len = skb_shinfo(skb)->frags[i-1].size;
3404
3405                         if (entry == would_hit_hwbug)
3406                                 break;
3407
3408                         i++;
3409                         entry = NEXT_TX(entry);
3410
3411                 }
3412
3413                 /* If the workaround fails due to memory/mapping
3414                  * failure, silently drop this packet.
3415                  */
3416                 if (tigon3_4gb_hwbug_workaround(tp, skb,
3417                                                 entry, len,
3418                                                 last_plus_one,
3419                                                 &start, mss))
3420                         goto out_unlock;
3421
3422                 entry = start;
3423         }
3424
3425         /* Packets are ready, update Tx producer idx local and on card. */
3426         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3427
3428         tp->tx_prod = entry;
3429         if (TX_BUFFS_AVAIL(tp) <= (MAX_SKB_FRAGS + 1))
3430                 netif_stop_queue(dev);
3431
3432 out_unlock:
3433         mmiowb();
3434         spin_unlock(&tp->tx_lock);
3435
3436         dev->trans_start = jiffies;
3437
3438         return NETDEV_TX_OK;
3439 }
3440
3441 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
3442                                int new_mtu)
3443 {
3444         dev->mtu = new_mtu;
3445
3446         if (new_mtu > ETH_DATA_LEN) {
3447                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
3448                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
3449                         ethtool_op_set_tso(dev, 0);
3450                 }
3451                 else
3452                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
3453         } else {
3454                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
3455                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
3456                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
3457         }
3458 }
3459
3460 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
3461 {
3462         struct tg3 *tp = netdev_priv(dev);
3463
3464         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
3465                 return -EINVAL;
3466
3467         if (!netif_running(dev)) {
3468                 /* We'll just catch it later when the
3469                  * device is up'd.
3470                  */
3471                 tg3_set_mtu(dev, tp, new_mtu);
3472                 return 0;
3473         }
3474
3475         tg3_netif_stop(tp);
3476
3477         tg3_full_lock(tp, 1);
3478
3479         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3480
3481         tg3_set_mtu(dev, tp, new_mtu);
3482
3483         tg3_init_hw(tp);
3484
3485         tg3_netif_start(tp);
3486
3487         tg3_full_unlock(tp);
3488
3489         return 0;
3490 }
3491
3492 /* Free up pending packets in all rx/tx rings.
3493  *
3494  * The chip has been shut down and the driver detached from
3495  * the networking, so no interrupts or new tx packets will
3496  * end up in the driver.  tp->{tx,}lock is not held and we are not
3497  * in an interrupt context and thus may sleep.
3498  */
3499 static void tg3_free_rings(struct tg3 *tp)
3500 {
3501         struct ring_info *rxp;
3502         int i;
3503
3504         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
3505                 rxp = &tp->rx_std_buffers[i];
3506
3507                 if (rxp->skb == NULL)
3508                         continue;
3509                 pci_unmap_single(tp->pdev,
3510                                  pci_unmap_addr(rxp, mapping),
3511                                  tp->rx_pkt_buf_sz - tp->rx_offset,
3512                                  PCI_DMA_FROMDEVICE);
3513                 dev_kfree_skb_any(rxp->skb);
3514                 rxp->skb = NULL;
3515         }
3516
3517         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
3518                 rxp = &tp->rx_jumbo_buffers[i];
3519
3520                 if (rxp->skb == NULL)
3521                         continue;
3522                 pci_unmap_single(tp->pdev,
3523                                  pci_unmap_addr(rxp, mapping),
3524                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
3525                                  PCI_DMA_FROMDEVICE);
3526                 dev_kfree_skb_any(rxp->skb);
3527                 rxp->skb = NULL;
3528         }
3529
3530         for (i = 0; i < TG3_TX_RING_SIZE; ) {
3531                 struct tx_ring_info *txp;
3532                 struct sk_buff *skb;
3533                 int j;
3534
3535                 txp = &tp->tx_buffers[i];
3536                 skb = txp->skb;
3537
3538                 if (skb == NULL) {
3539                         i++;
3540                         continue;
3541                 }
3542
3543                 pci_unmap_single(tp->pdev,
3544                                  pci_unmap_addr(txp, mapping),
3545                                  skb_headlen(skb),
3546                                  PCI_DMA_TODEVICE);
3547                 txp->skb = NULL;
3548
3549                 i++;
3550
3551                 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
3552                         txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
3553                         pci_unmap_page(tp->pdev,
3554                                        pci_unmap_addr(txp, mapping),
3555                                        skb_shinfo(skb)->frags[j].size,
3556                                        PCI_DMA_TODEVICE);
3557                         i++;
3558                 }
3559
3560                 dev_kfree_skb_any(skb);
3561         }
3562 }
3563
3564 /* Initialize tx/rx rings for packet processing.
3565  *
3566  * The chip has been shut down and the driver detached from
3567  * the networking, so no interrupts or new tx packets will
3568  * end up in the driver.  tp->{tx,}lock are held and thus
3569  * we may not sleep.
3570  */
3571 static void tg3_init_rings(struct tg3 *tp)
3572 {
3573         u32 i;
3574
3575         /* Free up all the SKBs. */
3576         tg3_free_rings(tp);
3577
3578         /* Zero out all descriptors. */
3579         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
3580         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
3581         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
3582         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
3583
3584         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
3585         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) &&
3586             (tp->dev->mtu > ETH_DATA_LEN))
3587                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
3588
3589         /* Initialize invariants of the rings, we only set this
3590          * stuff once.  This works because the card does not
3591          * write into the rx buffer posting rings.
3592          */
3593         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
3594                 struct tg3_rx_buffer_desc *rxd;
3595
3596                 rxd = &tp->rx_std[i];
3597                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
3598                         << RXD_LEN_SHIFT;
3599                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
3600                 rxd->opaque = (RXD_OPAQUE_RING_STD |
3601                                (i << RXD_OPAQUE_INDEX_SHIFT));
3602         }
3603
3604         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
3605                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
3606                         struct tg3_rx_buffer_desc *rxd;
3607
3608                         rxd = &tp->rx_jumbo[i];
3609                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
3610                                 << RXD_LEN_SHIFT;
3611                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
3612                                 RXD_FLAG_JUMBO;
3613                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
3614                                (i << RXD_OPAQUE_INDEX_SHIFT));
3615                 }
3616         }
3617
3618         /* Now allocate fresh SKBs for each rx ring. */
3619         for (i = 0; i < tp->rx_pending; i++) {
3620                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD,
3621                                      -1, i) < 0)
3622                         break;
3623         }
3624
3625         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
3626                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
3627                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
3628                                              -1, i) < 0)
3629                                 break;
3630                 }
3631         }
3632 }
3633
3634 /*
3635  * Must not be invoked with interrupt sources disabled and
3636  * the hardware shutdown down.
3637  */
3638 static void tg3_free_consistent(struct tg3 *tp)
3639 {
3640         if (tp->rx_std_buffers) {
3641                 kfree(tp->rx_std_buffers);
3642                 tp->rx_std_buffers = NULL;
3643         }
3644         if (tp->rx_std) {
3645                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
3646                                     tp->rx_std, tp->rx_std_mapping);
3647                 tp->rx_std = NULL;
3648         }
3649         if (tp->rx_jumbo) {
3650                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
3651                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
3652                 tp->rx_jumbo = NULL;
3653         }
3654         if (tp->rx_rcb) {
3655                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
3656                                     tp->rx_rcb, tp->rx_rcb_mapping);
3657                 tp->rx_rcb = NULL;
3658         }
3659         if (tp->tx_ring) {
3660                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
3661                         tp->tx_ring, tp->tx_desc_mapping);
3662                 tp->tx_ring = NULL;
3663         }
3664         if (tp->hw_status) {
3665                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
3666                                     tp->hw_status, tp->status_mapping);
3667                 tp->hw_status = NULL;
3668         }
3669         if (tp->hw_stats) {
3670                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
3671                                     tp->hw_stats, tp->stats_mapping);
3672                 tp->hw_stats = NULL;
3673         }
3674 }
3675
3676 /*
3677  * Must not be invoked with interrupt sources disabled and
3678  * the hardware shutdown down.  Can sleep.
3679  */
3680 static int tg3_alloc_consistent(struct tg3 *tp)
3681 {
3682         tp->rx_std_buffers = kmalloc((sizeof(struct ring_info) *
3683                                       (TG3_RX_RING_SIZE +
3684                                        TG3_RX_JUMBO_RING_SIZE)) +
3685                                      (sizeof(struct tx_ring_info) *
3686                                       TG3_TX_RING_SIZE),
3687                                      GFP_KERNEL);
3688         if (!tp->rx_std_buffers)
3689                 return -ENOMEM;
3690
3691         memset(tp->rx_std_buffers, 0,
3692                (sizeof(struct ring_info) *
3693                 (TG3_RX_RING_SIZE +
3694                  TG3_RX_JUMBO_RING_SIZE)) +
3695                (sizeof(struct tx_ring_info) *
3696                 TG3_TX_RING_SIZE));
3697
3698         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
3699         tp->tx_buffers = (struct tx_ring_info *)
3700                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
3701
3702         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
3703                                           &tp->rx_std_mapping);
3704         if (!tp->rx_std)
3705                 goto err_out;
3706
3707         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
3708                                             &tp->rx_jumbo_mapping);
3709
3710         if (!tp->rx_jumbo)
3711                 goto err_out;
3712
3713         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
3714                                           &tp->rx_rcb_mapping);
3715         if (!tp->rx_rcb)
3716                 goto err_out;
3717
3718         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
3719                                            &tp->tx_desc_mapping);
3720         if (!tp->tx_ring)
3721                 goto err_out;
3722
3723         tp->hw_status = pci_alloc_consistent(tp->pdev,
3724                                              TG3_HW_STATUS_SIZE,
3725                                              &tp->status_mapping);
3726         if (!tp->hw_status)
3727                 goto err_out;
3728
3729         tp->hw_stats = pci_alloc_consistent(tp->pdev,
3730                                             sizeof(struct tg3_hw_stats),
3731                                             &tp->stats_mapping);
3732         if (!tp->hw_stats)
3733                 goto err_out;
3734
3735         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
3736         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
3737
3738         return 0;
3739
3740 err_out:
3741         tg3_free_consistent(tp);
3742         return -ENOMEM;
3743 }
3744
3745 #define MAX_WAIT_CNT 1000
3746
3747 /* To stop a block, clear the enable bit and poll till it
3748  * clears.  tp->lock is held.
3749  */
3750 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
3751 {
3752         unsigned int i;
3753         u32 val;
3754
3755         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
3756                 switch (ofs) {
3757                 case RCVLSC_MODE:
3758                 case DMAC_MODE:
3759                 case MBFREE_MODE:
3760                 case BUFMGR_MODE:
3761                 case MEMARB_MODE:
3762                         /* We can't enable/disable these bits of the
3763                          * 5705/5750, just say success.
3764                          */
3765                         return 0;
3766
3767                 default:
3768                         break;
3769                 };
3770         }
3771
3772         val = tr32(ofs);
3773         val &= ~enable_bit;
3774         tw32_f(ofs, val);
3775
3776         for (i = 0; i < MAX_WAIT_CNT; i++) {
3777                 udelay(100);
3778                 val = tr32(ofs);
3779                 if ((val & enable_bit) == 0)
3780                         break;
3781         }
3782
3783         if (i == MAX_WAIT_CNT && !silent) {
3784                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
3785                        "ofs=%lx enable_bit=%x\n",
3786                        ofs, enable_bit);
3787                 return -ENODEV;
3788         }
3789
3790         return 0;
3791 }
3792
3793 /* tp->lock is held. */
3794 static int tg3_abort_hw(struct tg3 *tp, int silent)
3795 {
3796         int i, err;
3797
3798         tg3_disable_ints(tp);
3799
3800         tp->rx_mode &= ~RX_MODE_ENABLE;
3801         tw32_f(MAC_RX_MODE, tp->rx_mode);
3802         udelay(10);
3803
3804         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
3805         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
3806         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
3807         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
3808         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
3809         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
3810
3811         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
3812         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
3813         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
3814         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
3815         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
3816         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
3817         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
3818
3819         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
3820         tw32_f(MAC_MODE, tp->mac_mode);
3821         udelay(40);
3822
3823         tp->tx_mode &= ~TX_MODE_ENABLE;
3824         tw32_f(MAC_TX_MODE, tp->tx_mode);
3825
3826         for (i = 0; i < MAX_WAIT_CNT; i++) {
3827                 udelay(100);
3828                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
3829                         break;
3830         }
3831         if (i >= MAX_WAIT_CNT) {
3832                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
3833                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
3834                        tp->dev->name, tr32(MAC_TX_MODE));
3835                 err |= -ENODEV;
3836         }
3837
3838         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
3839         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
3840         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
3841
3842         tw32(FTQ_RESET, 0xffffffff);
3843         tw32(FTQ_RESET, 0x00000000);
3844
3845         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
3846         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
3847
3848         if (tp->hw_status)
3849                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
3850         if (tp->hw_stats)
3851                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
3852
3853         return err;
3854 }
3855
3856 /* tp->lock is held. */
3857 static int tg3_nvram_lock(struct tg3 *tp)
3858 {
3859         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
3860                 int i;
3861
3862                 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3863                 for (i = 0; i < 8000; i++) {
3864                         if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3865                                 break;
3866                         udelay(20);
3867                 }
3868                 if (i == 8000)
3869                         return -ENODEV;
3870         }
3871         return 0;
3872 }
3873
3874 /* tp->lock is held. */
3875 static void tg3_nvram_unlock(struct tg3 *tp)
3876 {
3877         if (tp->tg3_flags & TG3_FLAG_NVRAM)
3878                 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3879 }
3880
3881 /* tp->lock is held. */
3882 static void tg3_enable_nvram_access(struct tg3 *tp)
3883 {
3884         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
3885             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
3886                 u32 nvaccess = tr32(NVRAM_ACCESS);
3887
3888                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3889         }
3890 }
3891
3892 /* tp->lock is held. */
3893 static void tg3_disable_nvram_access(struct tg3 *tp)
3894 {
3895         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
3896             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
3897                 u32 nvaccess = tr32(NVRAM_ACCESS);
3898
3899                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3900         }
3901 }
3902
3903 /* tp->lock is held. */
3904 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
3905 {
3906         if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
3907                 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
3908                               NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
3909
3910         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
3911                 switch (kind) {
3912                 case RESET_KIND_INIT:
3913                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3914                                       DRV_STATE_START);
3915                         break;
3916
3917                 case RESET_KIND_SHUTDOWN:
3918                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3919                                       DRV_STATE_UNLOAD);
3920                         break;
3921
3922                 case RESET_KIND_SUSPEND:
3923                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3924                                       DRV_STATE_SUSPEND);
3925                         break;
3926
3927                 default:
3928                         break;
3929                 };
3930         }
3931 }
3932
3933 /* tp->lock is held. */
3934 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
3935 {
3936         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
3937                 switch (kind) {
3938                 case RESET_KIND_INIT:
3939                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3940                                       DRV_STATE_START_DONE);
3941                         break;
3942
3943                 case RESET_KIND_SHUTDOWN:
3944                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3945                                       DRV_STATE_UNLOAD_DONE);
3946                         break;
3947
3948                 default:
3949                         break;
3950                 };
3951         }
3952 }
3953
3954 /* tp->lock is held. */
3955 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
3956 {
3957         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
3958                 switch (kind) {
3959                 case RESET_KIND_INIT:
3960                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3961                                       DRV_STATE_START);
3962                         break;
3963
3964                 case RESET_KIND_SHUTDOWN:
3965                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3966                                       DRV_STATE_UNLOAD);
3967                         break;
3968
3969                 case RESET_KIND_SUSPEND:
3970                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3971                                       DRV_STATE_SUSPEND);
3972                         break;
3973
3974                 default:
3975                         break;
3976                 };
3977         }
3978 }
3979
3980 static void tg3_stop_fw(struct tg3 *);
3981
3982 /* tp->lock is held. */
3983 static int tg3_chip_reset(struct tg3 *tp)
3984 {
3985         u32 val;
3986         u32 flags_save;
3987         int i;
3988
3989         if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
3990                 tg3_nvram_lock(tp);
3991
3992         /*
3993          * We must avoid the readl() that normally takes place.
3994          * It locks machines, causes machine checks, and other
3995          * fun things.  So, temporarily disable the 5701
3996          * hardware workaround, while we do the reset.
3997          */
3998         flags_save = tp->tg3_flags;
3999         tp->tg3_flags &= ~TG3_FLAG_5701_REG_WRITE_BUG;
4000
4001         /* do the reset */
4002         val = GRC_MISC_CFG_CORECLK_RESET;
4003
4004         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4005                 if (tr32(0x7e2c) == 0x60) {
4006                         tw32(0x7e2c, 0x20);
4007                 }
4008                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4009                         tw32(GRC_MISC_CFG, (1 << 29));
4010                         val |= (1 << 29);
4011                 }
4012         }
4013
4014         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4015                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4016         tw32(GRC_MISC_CFG, val);
4017
4018         /* restore 5701 hardware bug workaround flag */
4019         tp->tg3_flags = flags_save;
4020
4021         /* Unfortunately, we have to delay before the PCI read back.
4022          * Some 575X chips even will not respond to a PCI cfg access
4023          * when the reset command is given to the chip.
4024          *
4025          * How do these hardware designers expect things to work
4026          * properly if the PCI write is posted for a long period
4027          * of time?  It is always necessary to have some method by
4028          * which a register read back can occur to push the write
4029          * out which does the reset.
4030          *
4031          * For most tg3 variants the trick below was working.
4032          * Ho hum...
4033          */
4034         udelay(120);
4035
4036         /* Flush PCI posted writes.  The normal MMIO registers
4037          * are inaccessible at this time so this is the only
4038          * way to make this reliably (actually, this is no longer
4039          * the case, see above).  I tried to use indirect
4040          * register read/write but this upset some 5701 variants.
4041          */
4042         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4043
4044         udelay(120);
4045
4046         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4047                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4048                         int i;
4049                         u32 cfg_val;
4050
4051                         /* Wait for link training to complete.  */
4052                         for (i = 0; i < 5000; i++)
4053                                 udelay(100);
4054
4055                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4056                         pci_write_config_dword(tp->pdev, 0xc4,
4057                                                cfg_val | (1 << 15));
4058                 }
4059                 /* Set PCIE max payload size and clear error status.  */
4060                 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4061         }
4062
4063         /* Re-enable indirect register accesses. */
4064         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4065                                tp->misc_host_ctrl);
4066
4067         /* Set MAX PCI retry to zero. */
4068         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4069         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4070             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4071                 val |= PCISTATE_RETRY_SAME_DMA;
4072         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4073
4074         pci_restore_state(tp->pdev);
4075
4076         /* Make sure PCI-X relaxed ordering bit is clear. */
4077         pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4078         val &= ~PCIX_CAPS_RELAXED_ORDERING;
4079         pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4080
4081         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
4082                 u32 val;
4083
4084                 /* Chip reset on 5780 will reset MSI enable bit,
4085                  * so need to restore it.
4086                  */
4087                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4088                         u16 ctrl;
4089
4090                         pci_read_config_word(tp->pdev,
4091                                              tp->msi_cap + PCI_MSI_FLAGS,
4092                                              &ctrl);
4093                         pci_write_config_word(tp->pdev,
4094                                               tp->msi_cap + PCI_MSI_FLAGS,
4095                                               ctrl | PCI_MSI_FLAGS_ENABLE);
4096                         val = tr32(MSGINT_MODE);
4097                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4098                 }
4099
4100                 val = tr32(MEMARB_MODE);
4101                 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
4102
4103         } else
4104                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
4105
4106         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4107                 tg3_stop_fw(tp);
4108                 tw32(0x5000, 0x400);
4109         }
4110
4111         tw32(GRC_MODE, tp->grc_mode);
4112
4113         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4114                 u32 val = tr32(0xc4);
4115
4116                 tw32(0xc4, val | (1 << 15));
4117         }
4118
4119         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4120             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4121                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4122                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4123                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4124                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4125         }
4126
4127         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4128                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4129                 tw32_f(MAC_MODE, tp->mac_mode);
4130         } else
4131                 tw32_f(MAC_MODE, 0);
4132         udelay(40);
4133
4134         if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) {
4135                 /* Wait for firmware initialization to complete. */
4136                 for (i = 0; i < 100000; i++) {
4137                         tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4138                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4139                                 break;
4140                         udelay(10);
4141                 }
4142                 if (i >= 100000) {
4143                         printk(KERN_ERR PFX "tg3_reset_hw timed out for %s, "
4144                                "firmware will not restart magic=%08x\n",
4145                                tp->dev->name, val);
4146                         return -ENODEV;
4147                 }
4148         }
4149
4150         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4151             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4152                 u32 val = tr32(0x7c00);
4153
4154                 tw32(0x7c00, val | (1 << 25));
4155         }
4156
4157         /* Reprobe ASF enable state.  */
4158         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
4159         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
4160         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
4161         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
4162                 u32 nic_cfg;
4163
4164                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
4165                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
4166                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4167                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
4168                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
4169                 }
4170         }
4171
4172         return 0;
4173 }
4174
4175 /* tp->lock is held. */
4176 static void tg3_stop_fw(struct tg3 *tp)
4177 {
4178         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4179                 u32 val;
4180                 int i;
4181
4182                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4183                 val = tr32(GRC_RX_CPU_EVENT);
4184                 val |= (1 << 14);
4185                 tw32(GRC_RX_CPU_EVENT, val);
4186
4187                 /* Wait for RX cpu to ACK the event.  */
4188                 for (i = 0; i < 100; i++) {
4189                         if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
4190                                 break;
4191                         udelay(1);
4192                 }
4193         }
4194 }
4195
4196 /* tp->lock is held. */
4197 static int tg3_halt(struct tg3 *tp, int kind, int silent)
4198 {
4199         int err;
4200
4201         tg3_stop_fw(tp);
4202
4203         tg3_write_sig_pre_reset(tp, kind);
4204
4205         tg3_abort_hw(tp, silent);
4206         err = tg3_chip_reset(tp);
4207
4208         tg3_write_sig_legacy(tp, kind);
4209         tg3_write_sig_post_reset(tp, kind);
4210
4211         if (err)
4212                 return err;
4213
4214         return 0;
4215 }
4216
4217 #define TG3_FW_RELEASE_MAJOR    0x0
4218 #define TG3_FW_RELASE_MINOR     0x0
4219 #define TG3_FW_RELEASE_FIX      0x0
4220 #define TG3_FW_START_ADDR       0x08000000
4221 #define TG3_FW_TEXT_ADDR        0x08000000
4222 #define TG3_FW_TEXT_LEN         0x9c0
4223 #define TG3_FW_RODATA_ADDR      0x080009c0
4224 #define TG3_FW_RODATA_LEN       0x60
4225 #define TG3_FW_DATA_ADDR        0x08000a40
4226 #define TG3_FW_DATA_LEN         0x20
4227 #define TG3_FW_SBSS_ADDR        0x08000a60
4228 #define TG3_FW_SBSS_LEN         0xc
4229 #define TG3_FW_BSS_ADDR         0x08000a70
4230 #define TG3_FW_BSS_LEN          0x10
4231
4232 static u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
4233         0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
4234         0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
4235         0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
4236         0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
4237         0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
4238         0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
4239         0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
4240         0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
4241         0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
4242         0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
4243         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
4244         0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
4245         0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
4246         0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
4247         0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
4248         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
4249         0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
4250         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
4251         0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
4252         0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
4253         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
4254         0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
4255         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
4256         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4257         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4258         0, 0, 0, 0, 0, 0,
4259         0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
4260         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4261         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4262         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4263         0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
4264         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
4265         0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
4266         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
4267         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4268         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4269         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
4270         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4271         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4272         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4273         0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
4274         0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
4275         0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
4276         0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
4277         0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
4278         0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
4279         0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
4280         0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
4281         0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
4282         0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
4283         0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
4284         0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
4285         0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
4286         0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
4287         0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
4288         0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
4289         0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
4290         0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
4291         0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
4292         0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
4293         0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
4294         0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
4295         0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
4296         0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
4297         0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
4298         0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
4299         0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
4300         0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
4301         0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
4302         0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
4303         0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
4304         0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
4305         0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
4306         0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
4307         0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
4308         0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
4309         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
4310         0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
4311         0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
4312         0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
4313         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
4314         0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
4315         0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
4316         0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
4317         0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
4318         0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
4319         0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
4320         0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
4321         0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
4322         0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
4323         0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
4324 };
4325
4326 static u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
4327         0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
4328         0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
4329         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
4330         0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
4331         0x00000000
4332 };
4333
4334 #if 0 /* All zeros, don't eat up space with it. */
4335 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
4336         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4337         0x00000000, 0x00000000, 0x00000000, 0x00000000
4338 };
4339 #endif
4340
4341 #define RX_CPU_SCRATCH_BASE     0x30000
4342 #define RX_CPU_SCRATCH_SIZE     0x04000
4343 #define TX_CPU_SCRATCH_BASE     0x34000
4344 #define TX_CPU_SCRATCH_SIZE     0x04000
4345
4346 /* tp->lock is held. */
4347 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
4348 {
4349         int i;
4350
4351         if (offset == TX_CPU_BASE &&
4352             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
4353                 BUG();
4354
4355         if (offset == RX_CPU_BASE) {
4356                 for (i = 0; i < 10000; i++) {
4357                         tw32(offset + CPU_STATE, 0xffffffff);
4358                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
4359                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4360                                 break;
4361                 }
4362
4363                 tw32(offset + CPU_STATE, 0xffffffff);
4364                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
4365                 udelay(10);
4366         } else {
4367                 for (i = 0; i < 10000; i++) {
4368                         tw32(offset + CPU_STATE, 0xffffffff);
4369                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
4370                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4371                                 break;
4372                 }
4373         }
4374
4375         if (i >= 10000) {
4376                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
4377                        "and %s CPU\n",
4378                        tp->dev->name,
4379                        (offset == RX_CPU_BASE ? "RX" : "TX"));
4380                 return -ENODEV;
4381         }
4382         return 0;
4383 }
4384
4385 struct fw_info {
4386         unsigned int text_base;
4387         unsigned int text_len;
4388         u32 *text_data;
4389         unsigned int rodata_base;
4390         unsigned int rodata_len;
4391         u32 *rodata_data;
4392         unsigned int data_base;
4393         unsigned int data_len;
4394         u32 *data_data;
4395 };
4396
4397 /* tp->lock is held. */
4398 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
4399                                  int cpu_scratch_size, struct fw_info *info)
4400 {
4401         int err, i;
4402         u32 orig_tg3_flags = tp->tg3_flags;
4403         void (*write_op)(struct tg3 *, u32, u32);
4404
4405         if (cpu_base == TX_CPU_BASE &&
4406             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4407                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
4408                        "TX cpu firmware on %s which is 5705.\n",
4409                        tp->dev->name);
4410                 return -EINVAL;
4411         }
4412
4413         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4414                 write_op = tg3_write_mem;
4415         else
4416                 write_op = tg3_write_indirect_reg32;
4417
4418         /* Force use of PCI config space for indirect register
4419          * write calls.
4420          */
4421         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
4422
4423         /* It is possible that bootcode is still loading at this point.
4424          * Get the nvram lock first before halting the cpu.
4425          */
4426         tg3_nvram_lock(tp);
4427         err = tg3_halt_cpu(tp, cpu_base);
4428         tg3_nvram_unlock(tp);
4429         if (err)
4430                 goto out;
4431
4432         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
4433                 write_op(tp, cpu_scratch_base + i, 0);
4434         tw32(cpu_base + CPU_STATE, 0xffffffff);
4435         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
4436         for (i = 0; i < (info->text_len / sizeof(u32)); i++)
4437                 write_op(tp, (cpu_scratch_base +
4438                               (info->text_base & 0xffff) +
4439                               (i * sizeof(u32))),
4440                          (info->text_data ?
4441                           info->text_data[i] : 0));
4442         for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
4443                 write_op(tp, (cpu_scratch_base +
4444                               (info->rodata_base & 0xffff) +
4445                               (i * sizeof(u32))),
4446                          (info->rodata_data ?
4447                           info->rodata_data[i] : 0));
4448         for (i = 0; i < (info->data_len / sizeof(u32)); i++)
4449                 write_op(tp, (cpu_scratch_base +
4450                               (info->data_base & 0xffff) +
4451                               (i * sizeof(u32))),
4452                          (info->data_data ?
4453                           info->data_data[i] : 0));
4454
4455         err = 0;
4456
4457 out:
4458         tp->tg3_flags = orig_tg3_flags;
4459         return err;
4460 }
4461
4462 /* tp->lock is held. */
4463 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
4464 {
4465         struct fw_info info;
4466         int err, i;
4467
4468         info.text_base = TG3_FW_TEXT_ADDR;
4469         info.text_len = TG3_FW_TEXT_LEN;
4470         info.text_data = &tg3FwText[0];
4471         info.rodata_base = TG3_FW_RODATA_ADDR;
4472         info.rodata_len = TG3_FW_RODATA_LEN;
4473         info.rodata_data = &tg3FwRodata[0];
4474         info.data_base = TG3_FW_DATA_ADDR;
4475         info.data_len = TG3_FW_DATA_LEN;
4476         info.data_data = NULL;
4477
4478         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
4479                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
4480                                     &info);
4481         if (err)
4482                 return err;
4483
4484         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
4485                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
4486                                     &info);
4487         if (err)
4488                 return err;
4489
4490         /* Now startup only the RX cpu. */
4491         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4492         tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
4493
4494         for (i = 0; i < 5; i++) {
4495                 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
4496                         break;
4497                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4498                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
4499                 tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
4500                 udelay(1000);
4501         }
4502         if (i >= 5) {
4503                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
4504                        "to set RX CPU PC, is %08x should be %08x\n",
4505                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
4506                        TG3_FW_TEXT_ADDR);
4507                 return -ENODEV;
4508         }
4509         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4510         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
4511
4512         return 0;
4513 }
4514
4515 #if TG3_TSO_SUPPORT != 0
4516
4517 #define TG3_TSO_FW_RELEASE_MAJOR        0x1
4518 #define TG3_TSO_FW_RELASE_MINOR         0x6
4519 #define TG3_TSO_FW_RELEASE_FIX          0x0
4520 #define TG3_TSO_FW_START_ADDR           0x08000000
4521 #define TG3_TSO_FW_TEXT_ADDR            0x08000000
4522 #define TG3_TSO_FW_TEXT_LEN             0x1aa0
4523 #define TG3_TSO_FW_RODATA_ADDR          0x08001aa0
4524 #define TG3_TSO_FW_RODATA_LEN           0x60
4525 #define TG3_TSO_FW_DATA_ADDR            0x08001b20
4526 #define TG3_TSO_FW_DATA_LEN             0x30
4527 #define TG3_TSO_FW_SBSS_ADDR            0x08001b50
4528 #define TG3_TSO_FW_SBSS_LEN             0x2c
4529 #define TG3_TSO_FW_BSS_ADDR             0x08001b80
4530 #define TG3_TSO_FW_BSS_LEN              0x894
4531
4532 static u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
4533         0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
4534         0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
4535         0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
4536         0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
4537         0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
4538         0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
4539         0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
4540         0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
4541         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
4542         0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
4543         0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
4544         0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
4545         0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
4546         0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
4547         0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
4548         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
4549         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
4550         0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
4551         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4552         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
4553         0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
4554         0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
4555         0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
4556         0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
4557         0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
4558         0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
4559         0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
4560         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
4561         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
4562         0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4563         0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
4564         0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
4565         0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
4566         0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
4567         0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
4568         0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
4569         0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
4570         0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
4571         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4572         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
4573         0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
4574         0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
4575         0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
4576         0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
4577         0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
4578         0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
4579         0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
4580         0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4581         0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
4582         0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4583         0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
4584         0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
4585         0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
4586         0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
4587         0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
4588         0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
4589         0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
4590         0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
4591         0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
4592         0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
4593         0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
4594         0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
4595         0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
4596         0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
4597         0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
4598         0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
4599         0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
4600         0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
4601         0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
4602         0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
4603         0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
4604         0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
4605         0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
4606         0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
4607         0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
4608         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
4609         0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
4610         0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
4611         0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
4612         0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
4613         0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
4614         0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
4615         0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
4616         0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
4617         0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
4618         0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
4619         0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
4620         0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
4621         0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
4622         0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
4623         0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
4624         0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
4625         0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
4626         0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
4627         0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
4628         0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
4629         0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
4630         0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
4631         0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
4632         0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
4633         0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
4634         0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
4635         0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
4636         0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
4637         0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
4638         0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
4639         0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
4640         0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
4641         0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
4642         0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
4643         0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
4644         0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
4645         0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
4646         0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
4647         0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
4648         0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
4649         0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
4650         0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
4651         0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
4652         0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
4653         0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
4654         0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
4655         0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
4656         0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
4657         0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
4658         0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
4659         0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
4660         0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
4661         0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
4662         0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
4663         0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
4664         0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
4665         0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
4666         0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
4667         0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
4668         0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
4669         0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
4670         0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
4671         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
4672         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
4673         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
4674         0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
4675         0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
4676         0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
4677         0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
4678         0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
4679         0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
4680         0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
4681         0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
4682         0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
4683         0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
4684         0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
4685         0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
4686         0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
4687         0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
4688         0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
4689         0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
4690         0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
4691         0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
4692         0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
4693         0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
4694         0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
4695         0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
4696         0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
4697         0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
4698         0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
4699         0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
4700         0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
4701         0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
4702         0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
4703         0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
4704         0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
4705         0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
4706         0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
4707         0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
4708         0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
4709         0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
4710         0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
4711         0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
4712         0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
4713         0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
4714         0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
4715         0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
4716         0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
4717         0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
4718         0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
4719         0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
4720         0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
4721         0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
4722         0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
4723         0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
4724         0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
4725         0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
4726         0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
4727         0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
4728         0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
4729         0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
4730         0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
4731         0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
4732         0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
4733         0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
4734         0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
4735         0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
4736         0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
4737         0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
4738         0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
4739         0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
4740         0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
4741         0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
4742         0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
4743         0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
4744         0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
4745         0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
4746         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
4747         0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
4748         0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
4749         0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
4750         0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
4751         0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
4752         0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
4753         0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
4754         0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
4755         0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
4756         0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
4757         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
4758         0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
4759         0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
4760         0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
4761         0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
4762         0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
4763         0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
4764         0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
4765         0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
4766         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
4767         0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
4768         0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
4769         0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
4770         0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
4771         0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
4772         0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
4773         0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
4774         0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
4775         0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
4776         0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
4777         0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
4778         0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
4779         0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
4780         0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
4781         0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
4782         0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
4783         0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
4784         0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
4785         0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
4786         0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
4787         0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
4788         0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
4789         0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
4790         0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
4791         0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
4792         0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
4793         0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
4794         0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
4795         0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
4796         0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
4797         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
4798         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
4799         0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
4800         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
4801         0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
4802         0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
4803         0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
4804         0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
4805         0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
4806         0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
4807         0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
4808         0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
4809         0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
4810         0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
4811         0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
4812         0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
4813         0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
4814         0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
4815         0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
4816         0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
4817 };
4818
4819 static u32 tg3TsoFwRodata[] = {
4820         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
4821         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
4822         0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
4823         0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
4824         0x00000000,
4825 };
4826
4827 static u32 tg3TsoFwData[] = {
4828         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
4829         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4830         0x00000000,
4831 };
4832
4833 /* 5705 needs a special version of the TSO firmware.  */
4834 #define TG3_TSO5_FW_RELEASE_MAJOR       0x1
4835 #define TG3_TSO5_FW_RELASE_MINOR        0x2
4836 #define TG3_TSO5_FW_RELEASE_FIX         0x0
4837 #define TG3_TSO5_FW_START_ADDR          0x00010000
4838 #define TG3_TSO5_FW_TEXT_ADDR           0x00010000
4839 #define TG3_TSO5_FW_TEXT_LEN            0xe90
4840 #define TG3_TSO5_FW_RODATA_ADDR         0x00010e90
4841 #define TG3_TSO5_FW_RODATA_LEN          0x50
4842 #define TG3_TSO5_FW_DATA_ADDR           0x00010f00
4843 #define TG3_TSO5_FW_DATA_LEN            0x20
4844 #define TG3_TSO5_FW_SBSS_ADDR           0x00010f20
4845 #define TG3_TSO5_FW_SBSS_LEN            0x28
4846 #define TG3_TSO5_FW_BSS_ADDR            0x00010f50
4847 #define TG3_TSO5_FW_BSS_LEN             0x88
4848
4849 static u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
4850         0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
4851         0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
4852         0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
4853         0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
4854         0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
4855         0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
4856         0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4857         0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
4858         0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
4859         0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
4860         0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
4861         0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
4862         0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
4863         0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
4864         0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
4865         0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
4866         0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
4867         0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
4868         0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
4869         0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
4870         0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
4871         0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
4872         0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
4873         0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
4874         0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
4875         0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
4876         0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
4877         0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
4878         0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
4879         0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
4880         0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
4881         0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
4882         0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
4883         0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
4884         0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
4885         0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
4886         0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
4887         0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
4888         0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
4889         0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
4890         0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
4891         0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
4892         0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
4893         0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
4894         0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
4895         0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
4896         0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
4897         0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
4898         0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
4899         0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
4900         0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
4901         0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
4902         0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
4903         0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
4904         0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
4905         0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
4906         0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
4907         0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
4908         0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
4909         0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
4910         0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
4911         0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
4912         0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
4913         0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
4914         0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
4915         0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
4916         0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
4917         0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
4918         0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
4919         0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
4920         0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
4921         0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
4922         0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
4923         0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
4924         0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
4925         0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
4926         0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
4927         0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
4928         0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
4929         0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
4930         0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
4931         0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
4932         0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
4933         0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
4934         0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
4935         0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
4936         0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
4937         0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
4938         0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
4939         0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
4940         0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
4941         0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
4942         0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
4943         0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
4944         0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
4945         0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
4946         0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
4947         0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
4948         0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
4949         0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
4950         0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
4951         0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
4952         0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
4953         0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
4954         0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
4955         0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
4956         0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
4957         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
4958         0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
4959         0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
4960         0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
4961         0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
4962         0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
4963         0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
4964         0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
4965         0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
4966         0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
4967         0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
4968         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
4969         0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
4970         0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
4971         0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
4972         0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
4973         0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4974         0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
4975         0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
4976         0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
4977         0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
4978         0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
4979         0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
4980         0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
4981         0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
4982         0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
4983         0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
4984         0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
4985         0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
4986         0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
4987         0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
4988         0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
4989         0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
4990         0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
4991         0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
4992         0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
4993         0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
4994         0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
4995         0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
4996         0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
4997         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
4998         0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
4999         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
5000         0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
5001         0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5002         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
5003         0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
5004         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5005         0x00000000, 0x00000000, 0x00000000,
5006 };
5007
5008 static u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
5009         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5010         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5011         0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5012         0x00000000, 0x00000000, 0x00000000,
5013 };
5014
5015 static u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
5016         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5017         0x00000000, 0x00000000, 0x00000000,
5018 };
5019
5020 /* tp->lock is held. */
5021 static int tg3_load_tso_firmware(struct tg3 *tp)
5022 {
5023         struct fw_info info;
5024         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
5025         int err, i;
5026
5027         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5028                 return 0;
5029
5030         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5031                 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
5032                 info.text_len = TG3_TSO5_FW_TEXT_LEN;
5033                 info.text_data = &tg3Tso5FwText[0];
5034                 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
5035                 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
5036                 info.rodata_data = &tg3Tso5FwRodata[0];
5037                 info.data_base = TG3_TSO5_FW_DATA_ADDR;
5038                 info.data_len = TG3_TSO5_FW_DATA_LEN;
5039                 info.data_data = &tg3Tso5FwData[0];
5040                 cpu_base = RX_CPU_BASE;
5041                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
5042                 cpu_scratch_size = (info.text_len +
5043                                     info.rodata_len +
5044                                     info.data_len +
5045                                     TG3_TSO5_FW_SBSS_LEN +
5046                                     TG3_TSO5_FW_BSS_LEN);
5047         } else {
5048                 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5049                 info.text_len = TG3_TSO_FW_TEXT_LEN;
5050                 info.text_data = &tg3TsoFwText[0];
5051                 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5052                 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5053                 info.rodata_data = &tg3TsoFwRodata[0];
5054                 info.data_base = TG3_TSO_FW_DATA_ADDR;
5055                 info.data_len = TG3_TSO_FW_DATA_LEN;
5056                 info.data_data = &tg3TsoFwData[0];
5057                 cpu_base = TX_CPU_BASE;
5058                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5059                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5060         }
5061
5062         err = tg3_load_firmware_cpu(tp, cpu_base,
5063                                     cpu_scratch_base, cpu_scratch_size,
5064                                     &info);
5065         if (err)
5066                 return err;
5067
5068         /* Now startup the cpu. */
5069         tw32(cpu_base + CPU_STATE, 0xffffffff);
5070         tw32_f(cpu_base + CPU_PC,    info.text_base);
5071
5072         for (i = 0; i < 5; i++) {
5073                 if (tr32(cpu_base + CPU_PC) == info.text_base)
5074                         break;
5075                 tw32(cpu_base + CPU_STATE, 0xffffffff);
5076                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
5077                 tw32_f(cpu_base + CPU_PC,    info.text_base);
5078                 udelay(1000);
5079         }
5080         if (i >= 5) {
5081                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5082                        "to set CPU PC, is %08x should be %08x\n",
5083                        tp->dev->name, tr32(cpu_base + CPU_PC),
5084                        info.text_base);
5085                 return -ENODEV;
5086         }
5087         tw32(cpu_base + CPU_STATE, 0xffffffff);
5088         tw32_f(cpu_base + CPU_MODE,  0x00000000);
5089         return 0;
5090 }
5091
5092 #endif /* TG3_TSO_SUPPORT != 0 */
5093
5094 /* tp->lock is held. */
5095 static void __tg3_set_mac_addr(struct tg3 *tp)
5096 {
5097         u32 addr_high, addr_low;
5098         int i;
5099
5100         addr_high = ((tp->dev->dev_addr[0] << 8) |
5101                      tp->dev->dev_addr[1]);
5102         addr_low = ((tp->dev->dev_addr[2] << 24) |
5103                     (tp->dev->dev_addr[3] << 16) |
5104                     (tp->dev->dev_addr[4] <<  8) |
5105                     (tp->dev->dev_addr[5] <<  0));
5106         for (i = 0; i < 4; i++) {
5107                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
5108                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
5109         }
5110
5111         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
5112             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5113                 for (i = 0; i < 12; i++) {
5114                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
5115                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
5116                 }
5117         }
5118
5119         addr_high = (tp->dev->dev_addr[0] +
5120                      tp->dev->dev_addr[1] +
5121                      tp->dev->dev_addr[2] +
5122                      tp->dev->dev_addr[3] +
5123                      tp->dev->dev_addr[4] +
5124                      tp->dev->dev_addr[5]) &
5125                 TX_BACKOFF_SEED_MASK;
5126         tw32(MAC_TX_BACKOFF_SEED, addr_high);
5127 }
5128
5129 static int tg3_set_mac_addr(struct net_device *dev, void *p)
5130 {
5131         struct tg3 *tp = netdev_priv(dev);
5132         struct sockaddr *addr = p;
5133
5134         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5135
5136         spin_lock_bh(&tp->lock);
5137         __tg3_set_mac_addr(tp);
5138         spin_unlock_bh(&tp->lock);
5139
5140         return 0;
5141 }
5142
5143 /* tp->lock is held. */
5144 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
5145                            dma_addr_t mapping, u32 maxlen_flags,
5146                            u32 nic_addr)
5147 {
5148         tg3_write_mem(tp,
5149                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
5150                       ((u64) mapping >> 32));
5151         tg3_write_mem(tp,
5152                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
5153                       ((u64) mapping & 0xffffffff));
5154         tg3_write_mem(tp,
5155                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
5156                        maxlen_flags);
5157
5158         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5159                 tg3_write_mem(tp,
5160                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
5161                               nic_addr);
5162 }
5163
5164 static void __tg3_set_rx_mode(struct net_device *);
5165 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
5166 {
5167         tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
5168         tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
5169         tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
5170         tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
5171         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5172                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
5173                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
5174         }
5175         tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
5176         tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
5177         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5178                 u32 val = ec->stats_block_coalesce_usecs;
5179
5180                 if (!netif_carrier_ok(tp->dev))
5181                         val = 0;
5182
5183                 tw32(HOSTCC_STAT_COAL_TICKS, val);
5184         }
5185 }
5186
5187 /* tp->lock is held. */
5188 static int tg3_reset_hw(struct tg3 *tp)
5189 {
5190         u32 val, rdmac_mode;
5191         int i, err, limit;
5192
5193         tg3_disable_ints(tp);
5194
5195         tg3_stop_fw(tp);
5196
5197         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
5198
5199         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
5200                 tg3_abort_hw(tp, 1);
5201         }
5202
5203         err = tg3_chip_reset(tp);
5204         if (err)
5205                 return err;
5206
5207         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
5208
5209         /* This works around an issue with Athlon chipsets on
5210          * B3 tigon3 silicon.  This bit has no effect on any
5211          * other revision.  But do not set this on PCI Express
5212          * chips.
5213          */
5214         if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
5215                 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
5216         tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5217
5218         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5219             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
5220                 val = tr32(TG3PCI_PCISTATE);
5221                 val |= PCISTATE_RETRY_SAME_DMA;
5222                 tw32(TG3PCI_PCISTATE, val);
5223         }
5224
5225         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
5226                 /* Enable some hw fixes.  */
5227                 val = tr32(TG3PCI_MSI_DATA);
5228                 val |= (1 << 26) | (1 << 28) | (1 << 29);
5229                 tw32(TG3PCI_MSI_DATA, val);
5230         }
5231
5232         /* Descriptor ring init may make accesses to the
5233          * NIC SRAM area to setup the TX descriptors, so we
5234          * can only do this after the hardware has been
5235          * successfully reset.
5236          */
5237         tg3_init_rings(tp);
5238
5239         /* This value is determined during the probe time DMA
5240          * engine test, tg3_test_dma.
5241          */
5242         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
5243
5244         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
5245                           GRC_MODE_4X_NIC_SEND_RINGS |
5246                           GRC_MODE_NO_TX_PHDR_CSUM |
5247                           GRC_MODE_NO_RX_PHDR_CSUM);
5248         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
5249         if (tp->tg3_flags & TG3_FLAG_NO_TX_PSEUDO_CSUM)
5250                 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
5251         if (tp->tg3_flags & TG3_FLAG_NO_RX_PSEUDO_CSUM)
5252                 tp->grc_mode |= GRC_MODE_NO_RX_PHDR_CSUM;
5253
5254         tw32(GRC_MODE,
5255              tp->grc_mode |
5256              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
5257
5258         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
5259         val = tr32(GRC_MISC_CFG);
5260         val &= ~0xff;
5261         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
5262         tw32(GRC_MISC_CFG, val);
5263
5264         /* Initialize MBUF/DESC pool. */
5265         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
5266                 /* Do nothing.  */
5267         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
5268                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
5269                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
5270                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
5271                 else
5272                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
5273                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
5274                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
5275         }
5276 #if TG3_TSO_SUPPORT != 0
5277         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5278                 int fw_len;
5279
5280                 fw_len = (TG3_TSO5_FW_TEXT_LEN +
5281                           TG3_TSO5_FW_RODATA_LEN +
5282                           TG3_TSO5_FW_DATA_LEN +
5283                           TG3_TSO5_FW_SBSS_LEN +
5284                           TG3_TSO5_FW_BSS_LEN);
5285                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
5286                 tw32(BUFMGR_MB_POOL_ADDR,
5287                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
5288                 tw32(BUFMGR_MB_POOL_SIZE,
5289                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
5290         }
5291 #endif
5292
5293         if (tp->dev->mtu <= ETH_DATA_LEN) {
5294                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5295                      tp->bufmgr_config.mbuf_read_dma_low_water);
5296                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5297                      tp->bufmgr_config.mbuf_mac_rx_low_water);
5298                 tw32(BUFMGR_MB_HIGH_WATER,
5299                      tp->bufmgr_config.mbuf_high_water);
5300         } else {
5301                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5302                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
5303                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5304                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
5305                 tw32(BUFMGR_MB_HIGH_WATER,
5306                      tp->bufmgr_config.mbuf_high_water_jumbo);
5307         }
5308         tw32(BUFMGR_DMA_LOW_WATER,
5309              tp->bufmgr_config.dma_low_water);
5310         tw32(BUFMGR_DMA_HIGH_WATER,
5311              tp->bufmgr_config.dma_high_water);
5312
5313         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
5314         for (i = 0; i < 2000; i++) {
5315                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
5316                         break;
5317                 udelay(10);
5318         }
5319         if (i >= 2000) {
5320                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
5321                        tp->dev->name);
5322                 return -ENODEV;
5323         }
5324
5325         /* Setup replenish threshold. */
5326         tw32(RCVBDI_STD_THRESH, tp->rx_pending / 8);
5327
5328         /* Initialize TG3_BDINFO's at:
5329          *  RCVDBDI_STD_BD:     standard eth size rx ring
5330          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
5331          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
5332          *
5333          * like so:
5334          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
5335          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
5336          *                              ring attribute flags
5337          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
5338          *
5339          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
5340          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
5341          *
5342          * The size of each ring is fixed in the firmware, but the location is
5343          * configurable.
5344          */
5345         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5346              ((u64) tp->rx_std_mapping >> 32));
5347         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5348              ((u64) tp->rx_std_mapping & 0xffffffff));
5349         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
5350              NIC_SRAM_RX_BUFFER_DESC);
5351
5352         /* Don't even try to program the JUMBO/MINI buffer descriptor
5353          * configs on 5705.
5354          */
5355         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5356                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5357                      RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
5358         } else {
5359                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5360                      RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5361
5362                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
5363                      BDINFO_FLAGS_DISABLED);
5364
5365                 /* Setup replenish threshold. */
5366                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
5367
5368                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5369                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5370                              ((u64) tp->rx_jumbo_mapping >> 32));
5371                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5372                              ((u64) tp->rx_jumbo_mapping & 0xffffffff));
5373                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5374                              RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5375                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
5376                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
5377                 } else {
5378                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5379                              BDINFO_FLAGS_DISABLED);
5380                 }
5381
5382         }
5383
5384         /* There is only one send ring on 5705/5750, no need to explicitly
5385          * disable the others.
5386          */
5387         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5388                 /* Clear out send RCB ring in SRAM. */
5389                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
5390                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
5391                                       BDINFO_FLAGS_DISABLED);
5392         }
5393
5394         tp->tx_prod = 0;
5395         tp->tx_cons = 0;
5396         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
5397         tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
5398
5399         tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
5400                        tp->tx_desc_mapping,
5401                        (TG3_TX_RING_SIZE <<
5402                         BDINFO_FLAGS_MAXLEN_SHIFT),
5403                        NIC_SRAM_TX_BUFFER_DESC);
5404
5405         /* There is only one receive return ring on 5705/5750, no need
5406          * to explicitly disable the others.
5407          */
5408         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5409                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
5410                      i += TG3_BDINFO_SIZE) {
5411                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
5412                                       BDINFO_FLAGS_DISABLED);
5413                 }
5414         }
5415
5416         tp->rx_rcb_ptr = 0;
5417         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
5418
5419         tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
5420                        tp->rx_rcb_mapping,
5421                        (TG3_RX_RCB_RING_SIZE(tp) <<
5422                         BDINFO_FLAGS_MAXLEN_SHIFT),
5423                        0);
5424
5425         tp->rx_std_ptr = tp->rx_pending;
5426         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
5427                      tp->rx_std_ptr);
5428
5429         tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
5430                                                 tp->rx_jumbo_pending : 0;
5431         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
5432                      tp->rx_jumbo_ptr);
5433
5434         /* Initialize MAC address and backoff seed. */
5435         __tg3_set_mac_addr(tp);
5436
5437         /* MTU + ethernet header + FCS + optional VLAN tag */
5438         tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
5439
5440         /* The slot time is changed by tg3_setup_phy if we
5441          * run at gigabit with half duplex.
5442          */
5443         tw32(MAC_TX_LENGTHS,
5444              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
5445              (6 << TX_LENGTHS_IPG_SHIFT) |
5446              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
5447
5448         /* Receive rules. */
5449         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
5450         tw32(RCVLPC_CONFIG, 0x0181);
5451
5452         /* Calculate RDMAC_MODE setting early, we need it to determine
5453          * the RCVLPC_STATE_ENABLE mask.
5454          */
5455         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
5456                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
5457                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
5458                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
5459                       RDMAC_MODE_LNGREAD_ENAB);
5460         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
5461                 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
5462
5463         /* If statement applies to 5705 and 5750 PCI devices only */
5464         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
5465              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
5466             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
5467                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
5468                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
5469                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
5470                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
5471                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
5472                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
5473                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
5474                 }
5475         }
5476
5477         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
5478                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
5479
5480 #if TG3_TSO_SUPPORT != 0
5481         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5482                 rdmac_mode |= (1 << 27);
5483 #endif
5484
5485         /* Receive/send statistics. */
5486         if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
5487             (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
5488                 val = tr32(RCVLPC_STATS_ENABLE);
5489                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
5490                 tw32(RCVLPC_STATS_ENABLE, val);
5491         } else {
5492                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
5493         }
5494         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
5495         tw32(SNDDATAI_STATSENAB, 0xffffff);
5496         tw32(SNDDATAI_STATSCTRL,
5497              (SNDDATAI_SCTRL_ENABLE |
5498               SNDDATAI_SCTRL_FASTUPD));
5499
5500         /* Setup host coalescing engine. */
5501         tw32(HOSTCC_MODE, 0);
5502         for (i = 0; i < 2000; i++) {
5503                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
5504                         break;
5505                 udelay(10);
5506         }
5507
5508         __tg3_set_coalesce(tp, &tp->coal);
5509
5510         /* set status block DMA address */
5511         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
5512              ((u64) tp->status_mapping >> 32));
5513         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
5514              ((u64) tp->status_mapping & 0xffffffff));
5515
5516         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5517                 /* Status/statistics block address.  See tg3_timer,
5518                  * the tg3_periodic_fetch_stats call there, and
5519                  * tg3_get_stats to see how this works for 5705/5750 chips.
5520                  */
5521                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
5522                      ((u64) tp->stats_mapping >> 32));
5523                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
5524                      ((u64) tp->stats_mapping & 0xffffffff));
5525                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
5526                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
5527         }
5528
5529         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
5530
5531         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
5532         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
5533         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5534                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
5535
5536         /* Clear statistics/status block in chip, and status block in ram. */
5537         for (i = NIC_SRAM_STATS_BLK;
5538              i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
5539              i += sizeof(u32)) {
5540                 tg3_write_mem(tp, i, 0);
5541                 udelay(40);
5542         }
5543         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5544
5545         tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
5546                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
5547         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
5548         udelay(40);
5549
5550         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
5551          * If TG3_FLAG_EEPROM_WRITE_PROT is set, we should read the
5552          * register to preserve the GPIO settings for LOMs. The GPIOs,
5553          * whether used as inputs or outputs, are set by boot code after
5554          * reset.
5555          */
5556         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
5557                 u32 gpio_mask;
5558
5559                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE2 |
5560                             GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT2;
5561
5562                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
5563                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
5564                                      GRC_LCLCTRL_GPIO_OUTPUT3;
5565
5566                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
5567
5568                 /* GPIO1 must be driven high for eeprom write protect */
5569                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
5570                                        GRC_LCLCTRL_GPIO_OUTPUT1);
5571         }
5572         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
5573         udelay(100);
5574
5575         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
5576         tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
5577         tp->last_tag = 0;
5578
5579         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5580                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
5581                 udelay(40);
5582         }
5583
5584         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
5585                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
5586                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
5587                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
5588                WDMAC_MODE_LNGREAD_ENAB);
5589
5590         /* If statement applies to 5705 and 5750 PCI devices only */
5591         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
5592              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
5593             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
5594                 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
5595                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
5596                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
5597                         /* nothing */
5598                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
5599                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
5600                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
5601                         val |= WDMAC_MODE_RX_ACCEL;
5602                 }
5603         }
5604
5605         tw32_f(WDMAC_MODE, val);
5606         udelay(40);
5607
5608         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
5609                 val = tr32(TG3PCI_X_CAPS);
5610                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
5611                         val &= ~PCIX_CAPS_BURST_MASK;
5612                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
5613                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5614                         val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
5615                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
5616                         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
5617                                 val |= (tp->split_mode_max_reqs <<
5618                                         PCIX_CAPS_SPLIT_SHIFT);
5619                 }
5620                 tw32(TG3PCI_X_CAPS, val);
5621         }
5622
5623         tw32_f(RDMAC_MODE, rdmac_mode);
5624         udelay(40);
5625
5626         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
5627         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5628                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
5629         tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
5630         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
5631         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
5632         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
5633         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
5634 #if TG3_TSO_SUPPORT != 0
5635         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5636                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
5637 #endif
5638         tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
5639         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
5640
5641         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
5642                 err = tg3_load_5701_a0_firmware_fix(tp);
5643                 if (err)
5644                         return err;
5645         }
5646
5647 #if TG3_TSO_SUPPORT != 0
5648         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5649                 err = tg3_load_tso_firmware(tp);
5650                 if (err)
5651                         return err;
5652         }
5653 #endif
5654
5655         tp->tx_mode = TX_MODE_ENABLE;
5656         tw32_f(MAC_TX_MODE, tp->tx_mode);
5657         udelay(100);
5658
5659         tp->rx_mode = RX_MODE_ENABLE;
5660         tw32_f(MAC_RX_MODE, tp->rx_mode);
5661         udelay(10);
5662
5663         if (tp->link_config.phy_is_low_power) {
5664                 tp->link_config.phy_is_low_power = 0;
5665                 tp->link_config.speed = tp->link_config.orig_speed;
5666                 tp->link_config.duplex = tp->link_config.orig_duplex;
5667                 tp->link_config.autoneg = tp->link_config.orig_autoneg;
5668         }
5669
5670         tp->mi_mode = MAC_MI_MODE_BASE;
5671         tw32_f(MAC_MI_MODE, tp->mi_mode);
5672         udelay(80);
5673
5674         tw32(MAC_LED_CTRL, tp->led_ctrl);
5675
5676         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
5677         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5678                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
5679                 udelay(10);
5680         }
5681         tw32_f(MAC_RX_MODE, tp->rx_mode);
5682         udelay(10);
5683
5684         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5685                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
5686                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
5687                         /* Set drive transmission level to 1.2V  */
5688                         /* only if the signal pre-emphasis bit is not set  */
5689                         val = tr32(MAC_SERDES_CFG);
5690                         val &= 0xfffff000;
5691                         val |= 0x880;
5692                         tw32(MAC_SERDES_CFG, val);
5693                 }
5694                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
5695                         tw32(MAC_SERDES_CFG, 0x616000);
5696         }
5697
5698         /* Prevent chip from dropping frames when flow control
5699          * is enabled.
5700          */
5701         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
5702
5703         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
5704             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
5705                 /* Use hardware link auto-negotiation */
5706                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
5707         }
5708
5709         err = tg3_setup_phy(tp, 1);
5710         if (err)
5711                 return err;
5712
5713         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
5714                 u32 tmp;
5715
5716                 /* Clear CRC stats. */
5717                 if (!tg3_readphy(tp, 0x1e, &tmp)) {
5718                         tg3_writephy(tp, 0x1e, tmp | 0x8000);
5719                         tg3_readphy(tp, 0x14, &tmp);
5720                 }
5721         }
5722
5723         __tg3_set_rx_mode(tp->dev);
5724
5725         /* Initialize receive rules. */
5726         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
5727         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
5728         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
5729         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
5730
5731         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
5732             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780))
5733                 limit = 8;
5734         else
5735                 limit = 16;
5736         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
5737                 limit -= 4;
5738         switch (limit) {
5739         case 16:
5740                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
5741         case 15:
5742                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
5743         case 14:
5744                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
5745         case 13:
5746                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
5747         case 12:
5748                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
5749         case 11:
5750                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
5751         case 10:
5752                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
5753         case 9:
5754                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
5755         case 8:
5756                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
5757         case 7:
5758                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
5759         case 6:
5760                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
5761         case 5:
5762                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
5763         case 4:
5764                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
5765         case 3:
5766                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
5767         case 2:
5768         case 1:
5769
5770         default:
5771                 break;
5772         };
5773
5774         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
5775
5776         return 0;
5777 }
5778
5779 /* Called at device open time to get the chip ready for
5780  * packet processing.  Invoked with tp->lock held.
5781  */
5782 static int tg3_init_hw(struct tg3 *tp)
5783 {
5784         int err;
5785
5786         /* Force the chip into D0. */
5787         err = tg3_set_power_state(tp, 0);
5788         if (err)
5789                 goto out;
5790
5791         tg3_switch_clocks(tp);
5792
5793         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
5794
5795         err = tg3_reset_hw(tp);
5796
5797 out:
5798         return err;
5799 }
5800
5801 #define TG3_STAT_ADD32(PSTAT, REG) \
5802 do {    u32 __val = tr32(REG); \
5803         (PSTAT)->low += __val; \
5804         if ((PSTAT)->low < __val) \
5805                 (PSTAT)->high += 1; \
5806 } while (0)
5807
5808 static void tg3_periodic_fetch_stats(struct tg3 *tp)
5809 {
5810         struct tg3_hw_stats *sp = tp->hw_stats;
5811
5812         if (!netif_carrier_ok(tp->dev))
5813                 return;
5814
5815         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
5816         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
5817         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
5818         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
5819         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
5820         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
5821         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
5822         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
5823         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
5824         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
5825         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
5826         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
5827         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
5828
5829         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
5830         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
5831         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
5832         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
5833         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
5834         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
5835         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
5836         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
5837         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
5838         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
5839         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
5840         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
5841         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
5842         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
5843 }
5844
5845 static void tg3_timer(unsigned long __opaque)
5846 {
5847         struct tg3 *tp = (struct tg3 *) __opaque;
5848
5849         spin_lock(&tp->lock);
5850
5851         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
5852                 /* All of this garbage is because when using non-tagged
5853                  * IRQ status the mailbox/status_block protocol the chip
5854                  * uses with the cpu is race prone.
5855                  */
5856                 if (tp->hw_status->status & SD_STATUS_UPDATED) {
5857                         tw32(GRC_LOCAL_CTRL,
5858                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
5859                 } else {
5860                         tw32(HOSTCC_MODE, tp->coalesce_mode |
5861                              (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
5862                 }
5863
5864                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
5865                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
5866                         spin_unlock(&tp->lock);
5867                         schedule_work(&tp->reset_task);
5868                         return;
5869                 }
5870         }
5871
5872         /* This part only runs once per second. */
5873         if (!--tp->timer_counter) {
5874                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5875                         tg3_periodic_fetch_stats(tp);
5876
5877                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
5878                         u32 mac_stat;
5879                         int phy_event;
5880
5881                         mac_stat = tr32(MAC_STATUS);
5882
5883                         phy_event = 0;
5884                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
5885                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
5886                                         phy_event = 1;
5887                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
5888                                 phy_event = 1;
5889
5890                         if (phy_event)
5891                                 tg3_setup_phy(tp, 0);
5892                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
5893                         u32 mac_stat = tr32(MAC_STATUS);
5894                         int need_setup = 0;
5895
5896                         if (netif_carrier_ok(tp->dev) &&
5897                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
5898                                 need_setup = 1;
5899                         }
5900                         if (! netif_carrier_ok(tp->dev) &&
5901                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
5902                                          MAC_STATUS_SIGNAL_DET))) {
5903                                 need_setup = 1;
5904                         }
5905                         if (need_setup) {
5906                                 tw32_f(MAC_MODE,
5907                                      (tp->mac_mode &
5908                                       ~MAC_MODE_PORT_MODE_MASK));
5909                                 udelay(40);
5910                                 tw32_f(MAC_MODE, tp->mac_mode);
5911                                 udelay(40);
5912                                 tg3_setup_phy(tp, 0);
5913                         }
5914                 }
5915
5916                 tp->timer_counter = tp->timer_multiplier;
5917         }
5918
5919         /* Heartbeat is only sent once every 120 seconds.  */
5920         if (!--tp->asf_counter) {
5921                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5922                         u32 val;
5923
5924                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_ALIVE);
5925                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
5926                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 3);
5927                         val = tr32(GRC_RX_CPU_EVENT);
5928                         val |= (1 << 14);
5929                         tw32(GRC_RX_CPU_EVENT, val);
5930                 }
5931                 tp->asf_counter = tp->asf_multiplier;
5932         }
5933
5934         spin_unlock(&tp->lock);
5935
5936         tp->timer.expires = jiffies + tp->timer_offset;
5937         add_timer(&tp->timer);
5938 }
5939
5940 static int tg3_test_interrupt(struct tg3 *tp)
5941 {
5942         struct net_device *dev = tp->dev;
5943         int err, i;
5944         u32 int_mbox = 0;
5945
5946         if (!netif_running(dev))
5947                 return -ENODEV;
5948
5949         tg3_disable_ints(tp);
5950
5951         free_irq(tp->pdev->irq, dev);
5952
5953         err = request_irq(tp->pdev->irq, tg3_test_isr,
5954                           SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
5955         if (err)
5956                 return err;
5957
5958         tg3_enable_ints(tp);
5959
5960         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
5961                HOSTCC_MODE_NOW);
5962
5963         for (i = 0; i < 5; i++) {
5964                 int_mbox = tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
5965                 if (int_mbox != 0)
5966                         break;
5967                 msleep(10);
5968         }
5969
5970         tg3_disable_ints(tp);
5971
5972         free_irq(tp->pdev->irq, dev);
5973
5974         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
5975                 err = request_irq(tp->pdev->irq, tg3_msi,
5976                                   SA_SAMPLE_RANDOM, dev->name, dev);
5977         else {
5978                 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
5979                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
5980                         fn = tg3_interrupt_tagged;
5981                 err = request_irq(tp->pdev->irq, fn,
5982                                   SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
5983         }
5984
5985         if (err)
5986                 return err;
5987
5988         if (int_mbox != 0)
5989                 return 0;
5990
5991         return -EIO;
5992 }
5993
5994 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
5995  * successfully restored
5996  */
5997 static int tg3_test_msi(struct tg3 *tp)
5998 {
5999         struct net_device *dev = tp->dev;
6000         int err;
6001         u16 pci_cmd;
6002
6003         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
6004                 return 0;
6005
6006         /* Turn off SERR reporting in case MSI terminates with Master
6007          * Abort.
6008          */
6009         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
6010         pci_write_config_word(tp->pdev, PCI_COMMAND,
6011                               pci_cmd & ~PCI_COMMAND_SERR);
6012
6013         err = tg3_test_interrupt(tp);
6014
6015         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
6016
6017         if (!err)
6018                 return 0;
6019
6020         /* other failures */
6021         if (err != -EIO)
6022                 return err;
6023
6024         /* MSI test failed, go back to INTx mode */
6025         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
6026                "switching to INTx mode. Please report this failure to "
6027                "the PCI maintainer and include system chipset information.\n",
6028                        tp->dev->name);
6029
6030         free_irq(tp->pdev->irq, dev);
6031         pci_disable_msi(tp->pdev);
6032
6033         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6034
6035         {
6036                 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
6037                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6038                         fn = tg3_interrupt_tagged;
6039
6040                 err = request_irq(tp->pdev->irq, fn,
6041                                   SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
6042         }
6043         if (err)
6044                 return err;
6045
6046         /* Need to reset the chip because the MSI cycle may have terminated
6047          * with Master Abort.
6048          */
6049         tg3_full_lock(tp, 1);
6050
6051         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6052         err = tg3_init_hw(tp);
6053
6054         tg3_full_unlock(tp);
6055
6056         if (err)
6057                 free_irq(tp->pdev->irq, dev);
6058
6059         return err;
6060 }
6061
6062 static int tg3_open(struct net_device *dev)
6063 {
6064         struct tg3 *tp = netdev_priv(dev);
6065         int err;
6066
6067         tg3_full_lock(tp, 0);
6068
6069         tg3_disable_ints(tp);
6070         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
6071
6072         tg3_full_unlock(tp);
6073
6074         /* The placement of this call is tied
6075          * to the setup and use of Host TX descriptors.
6076          */
6077         err = tg3_alloc_consistent(tp);
6078         if (err)
6079                 return err;
6080
6081         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
6082             (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
6083             (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX)) {
6084                 /* All MSI supporting chips should support tagged
6085                  * status.  Assert that this is the case.
6086                  */
6087                 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6088                         printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
6089                                "Not using MSI.\n", tp->dev->name);
6090                 } else if (pci_enable_msi(tp->pdev) == 0) {
6091                         u32 msi_mode;
6092
6093                         msi_mode = tr32(MSGINT_MODE);
6094                         tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
6095                         tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
6096                 }
6097         }
6098         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
6099                 err = request_irq(tp->pdev->irq, tg3_msi,
6100                                   SA_SAMPLE_RANDOM, dev->name, dev);
6101         else {
6102                 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
6103                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6104                         fn = tg3_interrupt_tagged;
6105
6106                 err = request_irq(tp->pdev->irq, fn,
6107                                   SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
6108         }
6109
6110         if (err) {
6111                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6112                         pci_disable_msi(tp->pdev);
6113                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6114                 }
6115                 tg3_free_consistent(tp);
6116                 return err;
6117         }
6118
6119         tg3_full_lock(tp, 0);
6120
6121         err = tg3_init_hw(tp);
6122         if (err) {
6123                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6124                 tg3_free_rings(tp);
6125         } else {
6126                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6127                         tp->timer_offset = HZ;
6128                 else
6129                         tp->timer_offset = HZ / 10;
6130
6131                 BUG_ON(tp->timer_offset > HZ);
6132                 tp->timer_counter = tp->timer_multiplier =
6133                         (HZ / tp->timer_offset);
6134                 tp->asf_counter = tp->asf_multiplier =
6135                         ((HZ / tp->timer_offset) * 120);
6136
6137                 init_timer(&tp->timer);
6138                 tp->timer.expires = jiffies + tp->timer_offset;
6139                 tp->timer.data = (unsigned long) tp;
6140                 tp->timer.function = tg3_timer;
6141         }
6142
6143         tg3_full_unlock(tp);
6144
6145         if (err) {
6146                 free_irq(tp->pdev->irq, dev);
6147                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6148                         pci_disable_msi(tp->pdev);
6149                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6150                 }
6151                 tg3_free_consistent(tp);
6152                 return err;
6153         }
6154
6155         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6156                 err = tg3_test_msi(tp);
6157
6158                 if (err) {
6159                         tg3_full_lock(tp, 0);
6160
6161                         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6162                                 pci_disable_msi(tp->pdev);
6163                                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6164                         }
6165                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6166                         tg3_free_rings(tp);
6167                         tg3_free_consistent(tp);
6168
6169                         tg3_full_unlock(tp);
6170
6171                         return err;
6172                 }
6173         }
6174
6175         tg3_full_lock(tp, 0);
6176
6177         add_timer(&tp->timer);
6178         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
6179         tg3_enable_ints(tp);
6180
6181         tg3_full_unlock(tp);
6182
6183         netif_start_queue(dev);
6184
6185         return 0;
6186 }
6187
6188 #if 0
6189 /*static*/ void tg3_dump_state(struct tg3 *tp)
6190 {
6191         u32 val32, val32_2, val32_3, val32_4, val32_5;
6192         u16 val16;
6193         int i;
6194
6195         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
6196         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
6197         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
6198                val16, val32);
6199
6200         /* MAC block */
6201         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
6202                tr32(MAC_MODE), tr32(MAC_STATUS));
6203         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
6204                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
6205         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
6206                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
6207         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
6208                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
6209
6210         /* Send data initiator control block */
6211         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
6212                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
6213         printk("       SNDDATAI_STATSCTRL[%08x]\n",
6214                tr32(SNDDATAI_STATSCTRL));
6215
6216         /* Send data completion control block */
6217         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
6218
6219         /* Send BD ring selector block */
6220         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
6221                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
6222
6223         /* Send BD initiator control block */
6224         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
6225                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
6226
6227         /* Send BD completion control block */
6228         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
6229
6230         /* Receive list placement control block */
6231         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
6232                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
6233         printk("       RCVLPC_STATSCTRL[%08x]\n",
6234                tr32(RCVLPC_STATSCTRL));
6235
6236         /* Receive data and receive BD initiator control block */
6237         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
6238                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
6239
6240         /* Receive data completion control block */
6241         printk("DEBUG: RCVDCC_MODE[%08x]\n",
6242                tr32(RCVDCC_MODE));
6243
6244         /* Receive BD initiator control block */
6245         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
6246                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
6247
6248         /* Receive BD completion control block */
6249         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
6250                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
6251
6252         /* Receive list selector control block */
6253         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
6254                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
6255
6256         /* Mbuf cluster free block */
6257         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
6258                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
6259
6260         /* Host coalescing control block */
6261         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
6262                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
6263         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
6264                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6265                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6266         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
6267                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6268                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6269         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
6270                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
6271         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
6272                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
6273
6274         /* Memory arbiter control block */
6275         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
6276                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
6277
6278         /* Buffer manager control block */
6279         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
6280                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
6281         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
6282                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
6283         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
6284                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
6285                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
6286                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
6287
6288         /* Read DMA control block */
6289         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
6290                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
6291
6292         /* Write DMA control block */
6293         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
6294                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
6295
6296         /* DMA completion block */
6297         printk("DEBUG: DMAC_MODE[%08x]\n",
6298                tr32(DMAC_MODE));
6299
6300         /* GRC block */
6301         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
6302                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
6303         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
6304                tr32(GRC_LOCAL_CTRL));
6305
6306         /* TG3_BDINFOs */
6307         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
6308                tr32(RCVDBDI_JUMBO_BD + 0x0),
6309                tr32(RCVDBDI_JUMBO_BD + 0x4),
6310                tr32(RCVDBDI_JUMBO_BD + 0x8),
6311                tr32(RCVDBDI_JUMBO_BD + 0xc));
6312         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
6313                tr32(RCVDBDI_STD_BD + 0x0),
6314                tr32(RCVDBDI_STD_BD + 0x4),
6315                tr32(RCVDBDI_STD_BD + 0x8),
6316                tr32(RCVDBDI_STD_BD + 0xc));
6317         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
6318                tr32(RCVDBDI_MINI_BD + 0x0),
6319                tr32(RCVDBDI_MINI_BD + 0x4),
6320                tr32(RCVDBDI_MINI_BD + 0x8),
6321                tr32(RCVDBDI_MINI_BD + 0xc));
6322
6323         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
6324         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
6325         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
6326         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
6327         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
6328                val32, val32_2, val32_3, val32_4);
6329
6330         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
6331         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
6332         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
6333         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
6334         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
6335                val32, val32_2, val32_3, val32_4);
6336
6337         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
6338         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
6339         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
6340         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
6341         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
6342         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
6343                val32, val32_2, val32_3, val32_4, val32_5);
6344
6345         /* SW status block */
6346         printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6347                tp->hw_status->status,
6348                tp->hw_status->status_tag,
6349                tp->hw_status->rx_jumbo_consumer,
6350                tp->hw_status->rx_consumer,
6351                tp->hw_status->rx_mini_consumer,
6352                tp->hw_status->idx[0].rx_producer,
6353                tp->hw_status->idx[0].tx_consumer);
6354
6355         /* SW statistics block */
6356         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
6357                ((u32 *)tp->hw_stats)[0],
6358                ((u32 *)tp->hw_stats)[1],
6359                ((u32 *)tp->hw_stats)[2],
6360                ((u32 *)tp->hw_stats)[3]);
6361
6362         /* Mailboxes */
6363         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
6364                tr32(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
6365                tr32(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
6366                tr32(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
6367                tr32(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
6368
6369         /* NIC side send descriptors. */
6370         for (i = 0; i < 6; i++) {
6371                 unsigned long txd;
6372
6373                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
6374                         + (i * sizeof(struct tg3_tx_buffer_desc));
6375                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
6376                        i,
6377                        readl(txd + 0x0), readl(txd + 0x4),
6378                        readl(txd + 0x8), readl(txd + 0xc));
6379         }
6380
6381         /* NIC side RX descriptors. */
6382         for (i = 0; i < 6; i++) {
6383                 unsigned long rxd;
6384
6385                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
6386                         + (i * sizeof(struct tg3_rx_buffer_desc));
6387                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
6388                        i,
6389                        readl(rxd + 0x0), readl(rxd + 0x4),
6390                        readl(rxd + 0x8), readl(rxd + 0xc));
6391                 rxd += (4 * sizeof(u32));
6392                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
6393                        i,
6394                        readl(rxd + 0x0), readl(rxd + 0x4),
6395                        readl(rxd + 0x8), readl(rxd + 0xc));
6396         }
6397
6398         for (i = 0; i < 6; i++) {
6399                 unsigned long rxd;
6400
6401                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
6402                         + (i * sizeof(struct tg3_rx_buffer_desc));
6403                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
6404                        i,
6405                        readl(rxd + 0x0), readl(rxd + 0x4),
6406                        readl(rxd + 0x8), readl(rxd + 0xc));
6407                 rxd += (4 * sizeof(u32));
6408                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
6409                        i,
6410                        readl(rxd + 0x0), readl(rxd + 0x4),
6411                        readl(rxd + 0x8), readl(rxd + 0xc));
6412         }
6413 }
6414 #endif
6415
6416 static struct net_device_stats *tg3_get_stats(struct net_device *);
6417 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
6418
6419 static int tg3_close(struct net_device *dev)
6420 {
6421         struct tg3 *tp = netdev_priv(dev);
6422
6423         netif_stop_queue(dev);
6424
6425         del_timer_sync(&tp->timer);
6426
6427         tg3_full_lock(tp, 1);
6428 #if 0
6429         tg3_dump_state(tp);
6430 #endif
6431
6432         tg3_disable_ints(tp);
6433
6434         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6435         tg3_free_rings(tp);
6436         tp->tg3_flags &=
6437                 ~(TG3_FLAG_INIT_COMPLETE |
6438                   TG3_FLAG_GOT_SERDES_FLOWCTL);
6439         netif_carrier_off(tp->dev);
6440
6441         tg3_full_unlock(tp);
6442
6443         free_irq(tp->pdev->irq, dev);
6444         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6445                 pci_disable_msi(tp->pdev);
6446                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6447         }
6448
6449         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
6450                sizeof(tp->net_stats_prev));
6451         memcpy(&tp->estats_prev, tg3_get_estats(tp),
6452                sizeof(tp->estats_prev));
6453
6454         tg3_free_consistent(tp);
6455
6456         return 0;
6457 }
6458
6459 static inline unsigned long get_stat64(tg3_stat64_t *val)
6460 {
6461         unsigned long ret;
6462
6463 #if (BITS_PER_LONG == 32)
6464         ret = val->low;
6465 #else
6466         ret = ((u64)val->high << 32) | ((u64)val->low);
6467 #endif
6468         return ret;
6469 }
6470
6471 static unsigned long calc_crc_errors(struct tg3 *tp)
6472 {
6473         struct tg3_hw_stats *hw_stats = tp->hw_stats;
6474
6475         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6476             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
6477              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
6478                 u32 val;
6479
6480                 spin_lock_bh(&tp->lock);
6481                 if (!tg3_readphy(tp, 0x1e, &val)) {
6482                         tg3_writephy(tp, 0x1e, val | 0x8000);
6483                         tg3_readphy(tp, 0x14, &val);
6484                 } else
6485                         val = 0;
6486                 spin_unlock_bh(&tp->lock);
6487
6488                 tp->phy_crc_errors += val;
6489
6490                 return tp->phy_crc_errors;
6491         }
6492
6493         return get_stat64(&hw_stats->rx_fcs_errors);
6494 }
6495
6496 #define ESTAT_ADD(member) \
6497         estats->member =        old_estats->member + \
6498                                 get_stat64(&hw_stats->member)
6499
6500 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
6501 {
6502         struct tg3_ethtool_stats *estats = &tp->estats;
6503         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
6504         struct tg3_hw_stats *hw_stats = tp->hw_stats;
6505
6506         if (!hw_stats)
6507                 return old_estats;
6508
6509         ESTAT_ADD(rx_octets);
6510         ESTAT_ADD(rx_fragments);
6511         ESTAT_ADD(rx_ucast_packets);
6512         ESTAT_ADD(rx_mcast_packets);
6513         ESTAT_ADD(rx_bcast_packets);
6514         ESTAT_ADD(rx_fcs_errors);
6515         ESTAT_ADD(rx_align_errors);
6516         ESTAT_ADD(rx_xon_pause_rcvd);
6517         ESTAT_ADD(rx_xoff_pause_rcvd);
6518         ESTAT_ADD(rx_mac_ctrl_rcvd);
6519         ESTAT_ADD(rx_xoff_entered);
6520         ESTAT_ADD(rx_frame_too_long_errors);
6521         ESTAT_ADD(rx_jabbers);
6522         ESTAT_ADD(rx_undersize_packets);
6523         ESTAT_ADD(rx_in_length_errors);
6524         ESTAT_ADD(rx_out_length_errors);
6525         ESTAT_ADD(rx_64_or_less_octet_packets);
6526         ESTAT_ADD(rx_65_to_127_octet_packets);
6527         ESTAT_ADD(rx_128_to_255_octet_packets);
6528         ESTAT_ADD(rx_256_to_511_octet_packets);
6529         ESTAT_ADD(rx_512_to_1023_octet_packets);
6530         ESTAT_ADD(rx_1024_to_1522_octet_packets);
6531         ESTAT_ADD(rx_1523_to_2047_octet_packets);
6532         ESTAT_ADD(rx_2048_to_4095_octet_packets);
6533         ESTAT_ADD(rx_4096_to_8191_octet_packets);
6534         ESTAT_ADD(rx_8192_to_9022_octet_packets);
6535
6536         ESTAT_ADD(tx_octets);
6537         ESTAT_ADD(tx_collisions);
6538         ESTAT_ADD(tx_xon_sent);
6539         ESTAT_ADD(tx_xoff_sent);
6540         ESTAT_ADD(tx_flow_control);
6541         ESTAT_ADD(tx_mac_errors);
6542         ESTAT_ADD(tx_single_collisions);
6543         ESTAT_ADD(tx_mult_collisions);
6544         ESTAT_ADD(tx_deferred);
6545         ESTAT_ADD(tx_excessive_collisions);
6546         ESTAT_ADD(tx_late_collisions);
6547         ESTAT_ADD(tx_collide_2times);
6548         ESTAT_ADD(tx_collide_3times);
6549         ESTAT_ADD(tx_collide_4times);
6550         ESTAT_ADD(tx_collide_5times);
6551         ESTAT_ADD(tx_collide_6times);
6552         ESTAT_ADD(tx_collide_7times);
6553         ESTAT_ADD(tx_collide_8times);
6554         ESTAT_ADD(tx_collide_9times);
6555         ESTAT_ADD(tx_collide_10times);
6556         ESTAT_ADD(tx_collide_11times);
6557         ESTAT_ADD(tx_collide_12times);
6558         ESTAT_ADD(tx_collide_13times);
6559         ESTAT_ADD(tx_collide_14times);
6560         ESTAT_ADD(tx_collide_15times);
6561         ESTAT_ADD(tx_ucast_packets);
6562         ESTAT_ADD(tx_mcast_packets);
6563         ESTAT_ADD(tx_bcast_packets);
6564         ESTAT_ADD(tx_carrier_sense_errors);
6565         ESTAT_ADD(tx_discards);
6566         ESTAT_ADD(tx_errors);
6567
6568         ESTAT_ADD(dma_writeq_full);
6569         ESTAT_ADD(dma_write_prioq_full);
6570         ESTAT_ADD(rxbds_empty);
6571         ESTAT_ADD(rx_discards);
6572         ESTAT_ADD(rx_errors);
6573         ESTAT_ADD(rx_threshold_hit);
6574
6575         ESTAT_ADD(dma_readq_full);
6576         ESTAT_ADD(dma_read_prioq_full);
6577         ESTAT_ADD(tx_comp_queue_full);
6578
6579         ESTAT_ADD(ring_set_send_prod_index);
6580         ESTAT_ADD(ring_status_update);
6581         ESTAT_ADD(nic_irqs);
6582         ESTAT_ADD(nic_avoided_irqs);
6583         ESTAT_ADD(nic_tx_threshold_hit);
6584
6585         return estats;
6586 }
6587
6588 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
6589 {
6590         struct tg3 *tp = netdev_priv(dev);
6591         struct net_device_stats *stats = &tp->net_stats;
6592         struct net_device_stats *old_stats = &tp->net_stats_prev;
6593         struct tg3_hw_stats *hw_stats = tp->hw_stats;
6594
6595         if (!hw_stats)
6596                 return old_stats;
6597
6598         stats->rx_packets = old_stats->rx_packets +
6599                 get_stat64(&hw_stats->rx_ucast_packets) +
6600                 get_stat64(&hw_stats->rx_mcast_packets) +
6601                 get_stat64(&hw_stats->rx_bcast_packets);
6602
6603         stats->tx_packets = old_stats->tx_packets +
6604                 get_stat64(&hw_stats->tx_ucast_packets) +
6605                 get_stat64(&hw_stats->tx_mcast_packets) +
6606                 get_stat64(&hw_stats->tx_bcast_packets);
6607
6608         stats->rx_bytes = old_stats->rx_bytes +
6609                 get_stat64(&hw_stats->rx_octets);
6610         stats->tx_bytes = old_stats->tx_bytes +
6611                 get_stat64(&hw_stats->tx_octets);
6612
6613         stats->rx_errors = old_stats->rx_errors +
6614                 get_stat64(&hw_stats->rx_errors) +
6615                 get_stat64(&hw_stats->rx_discards);
6616         stats->tx_errors = old_stats->tx_errors +
6617                 get_stat64(&hw_stats->tx_errors) +
6618                 get_stat64(&hw_stats->tx_mac_errors) +
6619                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
6620                 get_stat64(&hw_stats->tx_discards);
6621
6622         stats->multicast = old_stats->multicast +
6623                 get_stat64(&hw_stats->rx_mcast_packets);
6624         stats->collisions = old_stats->collisions +
6625                 get_stat64(&hw_stats->tx_collisions);
6626
6627         stats->rx_length_errors = old_stats->rx_length_errors +
6628                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
6629                 get_stat64(&hw_stats->rx_undersize_packets);
6630
6631         stats->rx_over_errors = old_stats->rx_over_errors +
6632                 get_stat64(&hw_stats->rxbds_empty);
6633         stats->rx_frame_errors = old_stats->rx_frame_errors +
6634                 get_stat64(&hw_stats->rx_align_errors);
6635         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
6636                 get_stat64(&hw_stats->tx_discards);
6637         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
6638                 get_stat64(&hw_stats->tx_carrier_sense_errors);
6639
6640         stats->rx_crc_errors = old_stats->rx_crc_errors +
6641                 calc_crc_errors(tp);
6642
6643         return stats;
6644 }
6645
6646 static inline u32 calc_crc(unsigned char *buf, int len)
6647 {
6648         u32 reg;
6649         u32 tmp;
6650         int j, k;
6651
6652         reg = 0xffffffff;
6653
6654         for (j = 0; j < len; j++) {
6655                 reg ^= buf[j];
6656
6657                 for (k = 0; k < 8; k++) {
6658                         tmp = reg & 0x01;
6659
6660                         reg >>= 1;
6661
6662                         if (tmp) {
6663                                 reg ^= 0xedb88320;
6664                         }
6665                 }
6666         }
6667
6668         return ~reg;
6669 }
6670
6671 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
6672 {
6673         /* accept or reject all multicast frames */
6674         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
6675         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
6676         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
6677         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
6678 }
6679
6680 static void __tg3_set_rx_mode(struct net_device *dev)
6681 {
6682         struct tg3 *tp = netdev_priv(dev);
6683         u32 rx_mode;
6684
6685         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
6686                                   RX_MODE_KEEP_VLAN_TAG);
6687
6688         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
6689          * flag clear.
6690          */
6691 #if TG3_VLAN_TAG_USED
6692         if (!tp->vlgrp &&
6693             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
6694                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
6695 #else
6696         /* By definition, VLAN is disabled always in this
6697          * case.
6698          */
6699         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
6700                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
6701 #endif
6702
6703         if (dev->flags & IFF_PROMISC) {
6704                 /* Promiscuous mode. */
6705                 rx_mode |= RX_MODE_PROMISC;
6706         } else if (dev->flags & IFF_ALLMULTI) {
6707                 /* Accept all multicast. */
6708                 tg3_set_multi (tp, 1);
6709         } else if (dev->mc_count < 1) {
6710                 /* Reject all multicast. */
6711                 tg3_set_multi (tp, 0);
6712         } else {
6713                 /* Accept one or more multicast(s). */
6714                 struct dev_mc_list *mclist;
6715                 unsigned int i;
6716                 u32 mc_filter[4] = { 0, };
6717                 u32 regidx;
6718                 u32 bit;
6719                 u32 crc;
6720
6721                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
6722                      i++, mclist = mclist->next) {
6723
6724                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
6725                         bit = ~crc & 0x7f;
6726                         regidx = (bit & 0x60) >> 5;
6727                         bit &= 0x1f;
6728                         mc_filter[regidx] |= (1 << bit);
6729                 }
6730
6731                 tw32(MAC_HASH_REG_0, mc_filter[0]);
6732                 tw32(MAC_HASH_REG_1, mc_filter[1]);
6733                 tw32(MAC_HASH_REG_2, mc_filter[2]);
6734                 tw32(MAC_HASH_REG_3, mc_filter[3]);
6735         }
6736
6737         if (rx_mode != tp->rx_mode) {
6738                 tp->rx_mode = rx_mode;
6739                 tw32_f(MAC_RX_MODE, rx_mode);
6740                 udelay(10);
6741         }
6742 }
6743
6744 static void tg3_set_rx_mode(struct net_device *dev)
6745 {
6746         struct tg3 *tp = netdev_priv(dev);
6747
6748         tg3_full_lock(tp, 0);
6749         __tg3_set_rx_mode(dev);
6750         tg3_full_unlock(tp);
6751 }
6752
6753 #define TG3_REGDUMP_LEN         (32 * 1024)
6754
6755 static int tg3_get_regs_len(struct net_device *dev)
6756 {
6757         return TG3_REGDUMP_LEN;
6758 }
6759
6760 static void tg3_get_regs(struct net_device *dev,
6761                 struct ethtool_regs *regs, void *_p)
6762 {
6763         u32 *p = _p;
6764         struct tg3 *tp = netdev_priv(dev);
6765         u8 *orig_p = _p;
6766         int i;
6767
6768         regs->version = 0;
6769
6770         memset(p, 0, TG3_REGDUMP_LEN);
6771
6772         tg3_full_lock(tp, 0);
6773
6774 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
6775 #define GET_REG32_LOOP(base,len)                \
6776 do {    p = (u32 *)(orig_p + (base));           \
6777         for (i = 0; i < len; i += 4)            \
6778                 __GET_REG32((base) + i);        \
6779 } while (0)
6780 #define GET_REG32_1(reg)                        \
6781 do {    p = (u32 *)(orig_p + (reg));            \
6782         __GET_REG32((reg));                     \
6783 } while (0)
6784
6785         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
6786         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
6787         GET_REG32_LOOP(MAC_MODE, 0x4f0);
6788         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
6789         GET_REG32_1(SNDDATAC_MODE);
6790         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
6791         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
6792         GET_REG32_1(SNDBDC_MODE);
6793         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
6794         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
6795         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
6796         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
6797         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
6798         GET_REG32_1(RCVDCC_MODE);
6799         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
6800         GET_REG32_LOOP(RCVCC_MODE, 0x14);
6801         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
6802         GET_REG32_1(MBFREE_MODE);
6803         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
6804         GET_REG32_LOOP(MEMARB_MODE, 0x10);
6805         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
6806         GET_REG32_LOOP(RDMAC_MODE, 0x08);
6807         GET_REG32_LOOP(WDMAC_MODE, 0x08);
6808         GET_REG32_LOOP(RX_CPU_BASE, 0x280);
6809         GET_REG32_LOOP(TX_CPU_BASE, 0x280);
6810         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
6811         GET_REG32_LOOP(FTQ_RESET, 0x120);
6812         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
6813         GET_REG32_1(DMAC_MODE);
6814         GET_REG32_LOOP(GRC_MODE, 0x4c);
6815         if (tp->tg3_flags & TG3_FLAG_NVRAM)
6816                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
6817
6818 #undef __GET_REG32
6819 #undef GET_REG32_LOOP
6820 #undef GET_REG32_1
6821
6822         tg3_full_unlock(tp);
6823 }
6824
6825 static int tg3_get_eeprom_len(struct net_device *dev)
6826 {
6827         struct tg3 *tp = netdev_priv(dev);
6828
6829         return tp->nvram_size;
6830 }
6831
6832 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
6833
6834 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
6835 {
6836         struct tg3 *tp = netdev_priv(dev);
6837         int ret;
6838         u8  *pd;
6839         u32 i, offset, len, val, b_offset, b_count;
6840
6841         offset = eeprom->offset;
6842         len = eeprom->len;
6843         eeprom->len = 0;
6844
6845         eeprom->magic = TG3_EEPROM_MAGIC;
6846
6847         if (offset & 3) {
6848                 /* adjustments to start on required 4 byte boundary */
6849                 b_offset = offset & 3;
6850                 b_count = 4 - b_offset;
6851                 if (b_count > len) {
6852                         /* i.e. offset=1 len=2 */
6853                         b_count = len;
6854                 }
6855                 ret = tg3_nvram_read(tp, offset-b_offset, &val);
6856                 if (ret)
6857                         return ret;
6858                 val = cpu_to_le32(val);
6859                 memcpy(data, ((char*)&val) + b_offset, b_count);
6860                 len -= b_count;
6861                 offset += b_count;
6862                 eeprom->len += b_count;
6863         }
6864
6865         /* read bytes upto the last 4 byte boundary */
6866         pd = &data[eeprom->len];
6867         for (i = 0; i < (len - (len & 3)); i += 4) {
6868                 ret = tg3_nvram_read(tp, offset + i, &val);
6869                 if (ret) {
6870                         eeprom->len += i;
6871                         return ret;
6872                 }
6873                 val = cpu_to_le32(val);
6874                 memcpy(pd + i, &val, 4);
6875         }
6876         eeprom->len += i;
6877
6878         if (len & 3) {
6879                 /* read last bytes not ending on 4 byte boundary */
6880                 pd = &data[eeprom->len];
6881                 b_count = len & 3;
6882                 b_offset = offset + len - b_count;
6883                 ret = tg3_nvram_read(tp, b_offset, &val);
6884                 if (ret)
6885                         return ret;
6886                 val = cpu_to_le32(val);
6887                 memcpy(pd, ((char*)&val), b_count);
6888                 eeprom->len += b_count;
6889         }
6890         return 0;
6891 }
6892
6893 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
6894
6895 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
6896 {
6897         struct tg3 *tp = netdev_priv(dev);
6898         int ret;
6899         u32 offset, len, b_offset, odd_len, start, end;
6900         u8 *buf;
6901
6902         if (eeprom->magic != TG3_EEPROM_MAGIC)
6903                 return -EINVAL;
6904
6905         offset = eeprom->offset;
6906         len = eeprom->len;
6907
6908         if ((b_offset = (offset & 3))) {
6909                 /* adjustments to start on required 4 byte boundary */
6910                 ret = tg3_nvram_read(tp, offset-b_offset, &start);
6911                 if (ret)
6912                         return ret;
6913                 start = cpu_to_le32(start);
6914                 len += b_offset;
6915                 offset &= ~3;
6916                 if (len < 4)
6917                         len = 4;
6918         }
6919
6920         odd_len = 0;
6921         if (len & 3) {
6922                 /* adjustments to end on required 4 byte boundary */
6923                 odd_len = 1;
6924                 len = (len + 3) & ~3;
6925                 ret = tg3_nvram_read(tp, offset+len-4, &end);
6926                 if (ret)
6927                         return ret;
6928                 end = cpu_to_le32(end);
6929         }
6930
6931         buf = data;
6932         if (b_offset || odd_len) {
6933                 buf = kmalloc(len, GFP_KERNEL);
6934                 if (buf == 0)
6935                         return -ENOMEM;
6936                 if (b_offset)
6937                         memcpy(buf, &start, 4);
6938                 if (odd_len)
6939                         memcpy(buf+len-4, &end, 4);
6940                 memcpy(buf + b_offset, data, eeprom->len);
6941         }
6942
6943         ret = tg3_nvram_write_block(tp, offset, len, buf);
6944
6945         if (buf != data)
6946                 kfree(buf);
6947
6948         return ret;
6949 }
6950
6951 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6952 {
6953         struct tg3 *tp = netdev_priv(dev);
6954
6955         cmd->supported = (SUPPORTED_Autoneg);
6956
6957         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
6958                 cmd->supported |= (SUPPORTED_1000baseT_Half |
6959                                    SUPPORTED_1000baseT_Full);
6960
6961         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES))
6962                 cmd->supported |= (SUPPORTED_100baseT_Half |
6963                                   SUPPORTED_100baseT_Full |
6964                                   SUPPORTED_10baseT_Half |
6965                                   SUPPORTED_10baseT_Full |
6966                                   SUPPORTED_MII);
6967         else
6968                 cmd->supported |= SUPPORTED_FIBRE;
6969
6970         cmd->advertising = tp->link_config.advertising;
6971         if (netif_running(dev)) {
6972                 cmd->speed = tp->link_config.active_speed;
6973                 cmd->duplex = tp->link_config.active_duplex;
6974         }
6975         cmd->port = 0;
6976         cmd->phy_address = PHY_ADDR;
6977         cmd->transceiver = 0;
6978         cmd->autoneg = tp->link_config.autoneg;
6979         cmd->maxtxpkt = 0;
6980         cmd->maxrxpkt = 0;
6981         return 0;
6982 }
6983
6984 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6985 {
6986         struct tg3 *tp = netdev_priv(dev);
6987
6988         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6989                 /* These are the only valid advertisement bits allowed.  */
6990                 if (cmd->autoneg == AUTONEG_ENABLE &&
6991                     (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
6992                                           ADVERTISED_1000baseT_Full |
6993                                           ADVERTISED_Autoneg |
6994                                           ADVERTISED_FIBRE)))
6995                         return -EINVAL;
6996         }
6997
6998         tg3_full_lock(tp, 0);
6999
7000         tp->link_config.autoneg = cmd->autoneg;
7001         if (cmd->autoneg == AUTONEG_ENABLE) {
7002                 tp->link_config.advertising = cmd->advertising;
7003                 tp->link_config.speed = SPEED_INVALID;
7004                 tp->link_config.duplex = DUPLEX_INVALID;
7005         } else {
7006                 tp->link_config.advertising = 0;
7007                 tp->link_config.speed = cmd->speed;
7008                 tp->link_config.duplex = cmd->duplex;
7009         }
7010
7011         if (netif_running(dev))
7012                 tg3_setup_phy(tp, 1);
7013
7014         tg3_full_unlock(tp);
7015
7016         return 0;
7017 }
7018
7019 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
7020 {
7021         struct tg3 *tp = netdev_priv(dev);
7022
7023         strcpy(info->driver, DRV_MODULE_NAME);
7024         strcpy(info->version, DRV_MODULE_VERSION);
7025         strcpy(info->bus_info, pci_name(tp->pdev));
7026 }
7027
7028 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7029 {
7030         struct tg3 *tp = netdev_priv(dev);
7031
7032         wol->supported = WAKE_MAGIC;
7033         wol->wolopts = 0;
7034         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
7035                 wol->wolopts = WAKE_MAGIC;
7036         memset(&wol->sopass, 0, sizeof(wol->sopass));
7037 }
7038
7039 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7040 {
7041         struct tg3 *tp = netdev_priv(dev);
7042
7043         if (wol->wolopts & ~WAKE_MAGIC)
7044                 return -EINVAL;
7045         if ((wol->wolopts & WAKE_MAGIC) &&
7046             tp->tg3_flags2 & TG3_FLG2_PHY_SERDES &&
7047             !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
7048                 return -EINVAL;
7049
7050         spin_lock_bh(&tp->lock);
7051         if (wol->wolopts & WAKE_MAGIC)
7052                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
7053         else
7054                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
7055         spin_unlock_bh(&tp->lock);
7056
7057         return 0;
7058 }
7059
7060 static u32 tg3_get_msglevel(struct net_device *dev)
7061 {
7062         struct tg3 *tp = netdev_priv(dev);
7063         return tp->msg_enable;
7064 }
7065
7066 static void tg3_set_msglevel(struct net_device *dev, u32 value)
7067 {
7068         struct tg3 *tp = netdev_priv(dev);
7069         tp->msg_enable = value;
7070 }
7071
7072 #if TG3_TSO_SUPPORT != 0
7073 static int tg3_set_tso(struct net_device *dev, u32 value)
7074 {
7075         struct tg3 *tp = netdev_priv(dev);
7076
7077         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7078                 if (value)
7079                         return -EINVAL;
7080                 return 0;
7081         }
7082         return ethtool_op_set_tso(dev, value);
7083 }
7084 #endif
7085
7086 static int tg3_nway_reset(struct net_device *dev)
7087 {
7088         struct tg3 *tp = netdev_priv(dev);
7089         u32 bmcr;
7090         int r;
7091
7092         if (!netif_running(dev))
7093                 return -EAGAIN;
7094
7095         spin_lock_bh(&tp->lock);
7096         r = -EINVAL;
7097         tg3_readphy(tp, MII_BMCR, &bmcr);
7098         if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
7099             (bmcr & BMCR_ANENABLE)) {
7100                 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART);
7101                 r = 0;
7102         }
7103         spin_unlock_bh(&tp->lock);
7104
7105         return r;
7106 }
7107
7108 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7109 {
7110         struct tg3 *tp = netdev_priv(dev);
7111
7112         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
7113         ering->rx_mini_max_pending = 0;
7114         ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
7115
7116         ering->rx_pending = tp->rx_pending;
7117         ering->rx_mini_pending = 0;
7118         ering->rx_jumbo_pending = tp->rx_jumbo_pending;
7119         ering->tx_pending = tp->tx_pending;
7120 }
7121
7122 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7123 {
7124         struct tg3 *tp = netdev_priv(dev);
7125         int irq_sync = 0;
7126
7127         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
7128             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
7129             (ering->tx_pending > TG3_TX_RING_SIZE - 1))
7130                 return -EINVAL;
7131
7132         if (netif_running(dev)) {
7133                 tg3_netif_stop(tp);
7134                 irq_sync = 1;
7135         }
7136
7137         tg3_full_lock(tp, irq_sync);
7138
7139         tp->rx_pending = ering->rx_pending;
7140
7141         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
7142             tp->rx_pending > 63)
7143                 tp->rx_pending = 63;
7144         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
7145         tp->tx_pending = ering->tx_pending;
7146
7147         if (netif_running(dev)) {
7148                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7149                 tg3_init_hw(tp);
7150                 tg3_netif_start(tp);
7151         }
7152
7153         tg3_full_unlock(tp);
7154
7155         return 0;
7156 }
7157
7158 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7159 {
7160         struct tg3 *tp = netdev_priv(dev);
7161
7162         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
7163         epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
7164         epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
7165 }
7166
7167 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7168 {
7169         struct tg3 *tp = netdev_priv(dev);
7170         int irq_sync = 0;
7171
7172         if (netif_running(dev)) {
7173                 tg3_netif_stop(tp);
7174                 irq_sync = 1;
7175         }
7176
7177         tg3_full_lock(tp, irq_sync);
7178
7179         if (epause->autoneg)
7180                 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
7181         else
7182                 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
7183         if (epause->rx_pause)
7184                 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
7185         else
7186                 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
7187         if (epause->tx_pause)
7188                 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
7189         else
7190                 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
7191
7192         if (netif_running(dev)) {
7193                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7194                 tg3_init_hw(tp);
7195                 tg3_netif_start(tp);
7196         }
7197
7198         tg3_full_unlock(tp);
7199
7200         return 0;
7201 }
7202
7203 static u32 tg3_get_rx_csum(struct net_device *dev)
7204 {
7205         struct tg3 *tp = netdev_priv(dev);
7206         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
7207 }
7208
7209 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
7210 {
7211         struct tg3 *tp = netdev_priv(dev);
7212
7213         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7214                 if (data != 0)
7215                         return -EINVAL;
7216                 return 0;
7217         }
7218
7219         spin_lock_bh(&tp->lock);
7220         if (data)
7221                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
7222         else
7223                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
7224         spin_unlock_bh(&tp->lock);
7225
7226         return 0;
7227 }
7228
7229 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
7230 {
7231         struct tg3 *tp = netdev_priv(dev);
7232
7233         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7234                 if (data != 0)
7235                         return -EINVAL;
7236                 return 0;
7237         }
7238
7239         if (data)
7240                 dev->features |= NETIF_F_IP_CSUM;
7241         else
7242                 dev->features &= ~NETIF_F_IP_CSUM;
7243
7244         return 0;
7245 }
7246
7247 static int tg3_get_stats_count (struct net_device *dev)
7248 {
7249         return TG3_NUM_STATS;
7250 }
7251
7252 static int tg3_get_test_count (struct net_device *dev)
7253 {
7254         return TG3_NUM_TEST;
7255 }
7256
7257 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
7258 {
7259         switch (stringset) {
7260         case ETH_SS_STATS:
7261                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
7262                 break;
7263         case ETH_SS_TEST:
7264                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
7265                 break;
7266         default:
7267                 WARN_ON(1);     /* we need a WARN() */
7268                 break;
7269         }
7270 }
7271
7272 static void tg3_get_ethtool_stats (struct net_device *dev,
7273                                    struct ethtool_stats *estats, u64 *tmp_stats)
7274 {
7275         struct tg3 *tp = netdev_priv(dev);
7276         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
7277 }
7278
7279 #define NVRAM_TEST_SIZE 0x100
7280
7281 static int tg3_test_nvram(struct tg3 *tp)
7282 {
7283         u32 *buf, csum;
7284         int i, j, err = 0;
7285
7286         buf = kmalloc(NVRAM_TEST_SIZE, GFP_KERNEL);
7287         if (buf == NULL)
7288                 return -ENOMEM;
7289
7290         for (i = 0, j = 0; i < NVRAM_TEST_SIZE; i += 4, j++) {
7291                 u32 val;
7292
7293                 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
7294                         break;
7295                 buf[j] = cpu_to_le32(val);
7296         }
7297         if (i < NVRAM_TEST_SIZE)
7298                 goto out;
7299
7300         err = -EIO;
7301         if (cpu_to_be32(buf[0]) != TG3_EEPROM_MAGIC)
7302                 goto out;
7303
7304         /* Bootstrap checksum at offset 0x10 */
7305         csum = calc_crc((unsigned char *) buf, 0x10);
7306         if(csum != cpu_to_le32(buf[0x10/4]))
7307                 goto out;
7308
7309         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
7310         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
7311         if (csum != cpu_to_le32(buf[0xfc/4]))
7312                  goto out;
7313
7314         err = 0;
7315
7316 out:
7317         kfree(buf);
7318         return err;
7319 }
7320
7321 #define TG3_SERDES_TIMEOUT_SEC  2
7322 #define TG3_COPPER_TIMEOUT_SEC  6
7323
7324 static int tg3_test_link(struct tg3 *tp)
7325 {
7326         int i, max;
7327
7328         if (!netif_running(tp->dev))
7329                 return -ENODEV;
7330
7331         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7332                 max = TG3_SERDES_TIMEOUT_SEC;
7333         else
7334                 max = TG3_COPPER_TIMEOUT_SEC;
7335
7336         for (i = 0; i < max; i++) {
7337                 if (netif_carrier_ok(tp->dev))
7338                         return 0;
7339
7340                 if (msleep_interruptible(1000))
7341                         break;
7342         }
7343
7344         return -EIO;
7345 }
7346
7347 /* Only test the commonly used registers */
7348 static int tg3_test_registers(struct tg3 *tp)
7349 {
7350         int i, is_5705;
7351         u32 offset, read_mask, write_mask, val, save_val, read_val;
7352         static struct {
7353                 u16 offset;
7354                 u16 flags;
7355 #define TG3_FL_5705     0x1
7356 #define TG3_FL_NOT_5705 0x2
7357 #define TG3_FL_NOT_5788 0x4
7358                 u32 read_mask;
7359                 u32 write_mask;
7360         } reg_tbl[] = {
7361                 /* MAC Control Registers */
7362                 { MAC_MODE, TG3_FL_NOT_5705,
7363                         0x00000000, 0x00ef6f8c },
7364                 { MAC_MODE, TG3_FL_5705,
7365                         0x00000000, 0x01ef6b8c },
7366                 { MAC_STATUS, TG3_FL_NOT_5705,
7367                         0x03800107, 0x00000000 },
7368                 { MAC_STATUS, TG3_FL_5705,
7369                         0x03800100, 0x00000000 },
7370                 { MAC_ADDR_0_HIGH, 0x0000,
7371                         0x00000000, 0x0000ffff },
7372                 { MAC_ADDR_0_LOW, 0x0000,
7373                         0x00000000, 0xffffffff },
7374                 { MAC_RX_MTU_SIZE, 0x0000,
7375                         0x00000000, 0x0000ffff },
7376                 { MAC_TX_MODE, 0x0000,
7377                         0x00000000, 0x00000070 },
7378                 { MAC_TX_LENGTHS, 0x0000,
7379                         0x00000000, 0x00003fff },
7380                 { MAC_RX_MODE, TG3_FL_NOT_5705,
7381                         0x00000000, 0x000007fc },
7382                 { MAC_RX_MODE, TG3_FL_5705,
7383                         0x00000000, 0x000007dc },
7384                 { MAC_HASH_REG_0, 0x0000,
7385                         0x00000000, 0xffffffff },
7386                 { MAC_HASH_REG_1, 0x0000,
7387                         0x00000000, 0xffffffff },
7388                 { MAC_HASH_REG_2, 0x0000,
7389                         0x00000000, 0xffffffff },
7390                 { MAC_HASH_REG_3, 0x0000,
7391                         0x00000000, 0xffffffff },
7392
7393                 /* Receive Data and Receive BD Initiator Control Registers. */
7394                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
7395                         0x00000000, 0xffffffff },
7396                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
7397                         0x00000000, 0xffffffff },
7398                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
7399                         0x00000000, 0x00000003 },
7400                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
7401                         0x00000000, 0xffffffff },
7402                 { RCVDBDI_STD_BD+0, 0x0000,
7403                         0x00000000, 0xffffffff },
7404                 { RCVDBDI_STD_BD+4, 0x0000,
7405                         0x00000000, 0xffffffff },
7406                 { RCVDBDI_STD_BD+8, 0x0000,
7407                         0x00000000, 0xffff0002 },
7408                 { RCVDBDI_STD_BD+0xc, 0x0000,
7409                         0x00000000, 0xffffffff },
7410
7411                 /* Receive BD Initiator Control Registers. */
7412                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
7413                         0x00000000, 0xffffffff },
7414                 { RCVBDI_STD_THRESH, TG3_FL_5705,
7415                         0x00000000, 0x000003ff },
7416                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
7417                         0x00000000, 0xffffffff },
7418
7419                 /* Host Coalescing Control Registers. */
7420                 { HOSTCC_MODE, TG3_FL_NOT_5705,
7421                         0x00000000, 0x00000004 },
7422                 { HOSTCC_MODE, TG3_FL_5705,
7423                         0x00000000, 0x000000f6 },
7424                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
7425                         0x00000000, 0xffffffff },
7426                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
7427                         0x00000000, 0x000003ff },
7428                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
7429                         0x00000000, 0xffffffff },
7430                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
7431                         0x00000000, 0x000003ff },
7432                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
7433                         0x00000000, 0xffffffff },
7434                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
7435                         0x00000000, 0x000000ff },
7436                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
7437                         0x00000000, 0xffffffff },
7438                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
7439                         0x00000000, 0x000000ff },
7440                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
7441                         0x00000000, 0xffffffff },
7442                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
7443                         0x00000000, 0xffffffff },
7444                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
7445                         0x00000000, 0xffffffff },
7446                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
7447                         0x00000000, 0x000000ff },
7448                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
7449                         0x00000000, 0xffffffff },
7450                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
7451                         0x00000000, 0x000000ff },
7452                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
7453                         0x00000000, 0xffffffff },
7454                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
7455                         0x00000000, 0xffffffff },
7456                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
7457                         0x00000000, 0xffffffff },
7458                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
7459                         0x00000000, 0xffffffff },
7460                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
7461                         0x00000000, 0xffffffff },
7462                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
7463                         0xffffffff, 0x00000000 },
7464                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
7465                         0xffffffff, 0x00000000 },
7466
7467                 /* Buffer Manager Control Registers. */
7468                 { BUFMGR_MB_POOL_ADDR, 0x0000,
7469                         0x00000000, 0x007fff80 },
7470                 { BUFMGR_MB_POOL_SIZE, 0x0000,
7471                         0x00000000, 0x007fffff },
7472                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
7473                         0x00000000, 0x0000003f },
7474                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
7475                         0x00000000, 0x000001ff },
7476                 { BUFMGR_MB_HIGH_WATER, 0x0000,
7477                         0x00000000, 0x000001ff },
7478                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
7479                         0xffffffff, 0x00000000 },
7480                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
7481                         0xffffffff, 0x00000000 },
7482
7483                 /* Mailbox Registers */
7484                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
7485                         0x00000000, 0x000001ff },
7486                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
7487                         0x00000000, 0x000001ff },
7488                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
7489                         0x00000000, 0x000007ff },
7490                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
7491                         0x00000000, 0x000001ff },
7492
7493                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
7494         };
7495
7496         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7497                 is_5705 = 1;
7498         else
7499                 is_5705 = 0;
7500
7501         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
7502                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
7503                         continue;
7504
7505                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
7506                         continue;
7507
7508                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7509                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
7510                         continue;
7511
7512                 offset = (u32) reg_tbl[i].offset;
7513                 read_mask = reg_tbl[i].read_mask;
7514                 write_mask = reg_tbl[i].write_mask;
7515
7516                 /* Save the original register content */
7517                 save_val = tr32(offset);
7518
7519                 /* Determine the read-only value. */
7520                 read_val = save_val & read_mask;
7521
7522                 /* Write zero to the register, then make sure the read-only bits
7523                  * are not changed and the read/write bits are all zeros.
7524                  */
7525                 tw32(offset, 0);
7526
7527                 val = tr32(offset);
7528
7529                 /* Test the read-only and read/write bits. */
7530                 if (((val & read_mask) != read_val) || (val & write_mask))
7531                         goto out;
7532
7533                 /* Write ones to all the bits defined by RdMask and WrMask, then
7534                  * make sure the read-only bits are not changed and the
7535                  * read/write bits are all ones.
7536                  */
7537                 tw32(offset, read_mask | write_mask);
7538
7539                 val = tr32(offset);
7540
7541                 /* Test the read-only bits. */
7542                 if ((val & read_mask) != read_val)
7543                         goto out;
7544
7545                 /* Test the read/write bits. */
7546                 if ((val & write_mask) != write_mask)
7547                         goto out;
7548
7549                 tw32(offset, save_val);
7550         }
7551
7552         return 0;
7553
7554 out:
7555         printk(KERN_ERR PFX "Register test failed at offset %x\n", offset);
7556         tw32(offset, save_val);
7557         return -EIO;
7558 }
7559
7560 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
7561 {
7562         static u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7563         int i;
7564         u32 j;
7565
7566         for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
7567                 for (j = 0; j < len; j += 4) {
7568                         u32 val;
7569
7570                         tg3_write_mem(tp, offset + j, test_pattern[i]);
7571                         tg3_read_mem(tp, offset + j, &val);
7572                         if (val != test_pattern[i])
7573                                 return -EIO;
7574                 }
7575         }
7576         return 0;
7577 }
7578
7579 static int tg3_test_memory(struct tg3 *tp)
7580 {
7581         static struct mem_entry {
7582                 u32 offset;
7583                 u32 len;
7584         } mem_tbl_570x[] = {
7585                 { 0x00000000, 0x01000},
7586                 { 0x00002000, 0x1c000},
7587                 { 0xffffffff, 0x00000}
7588         }, mem_tbl_5705[] = {
7589                 { 0x00000100, 0x0000c},
7590                 { 0x00000200, 0x00008},
7591                 { 0x00000b50, 0x00400},
7592                 { 0x00004000, 0x00800},
7593                 { 0x00006000, 0x01000},
7594                 { 0x00008000, 0x02000},
7595                 { 0x00010000, 0x0e000},
7596                 { 0xffffffff, 0x00000}
7597         };
7598         struct mem_entry *mem_tbl;
7599         int err = 0;
7600         int i;
7601
7602         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7603                 mem_tbl = mem_tbl_5705;
7604         else
7605                 mem_tbl = mem_tbl_570x;
7606
7607         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
7608                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
7609                     mem_tbl[i].len)) != 0)
7610                         break;
7611         }
7612
7613         return err;
7614 }
7615
7616 static int tg3_test_loopback(struct tg3 *tp)
7617 {
7618         u32 mac_mode, send_idx, rx_start_idx, rx_idx, tx_idx, opaque_key;
7619         u32 desc_idx;
7620         struct sk_buff *skb, *rx_skb;
7621         u8 *tx_data;
7622         dma_addr_t map;
7623         int num_pkts, tx_len, rx_len, i, err;
7624         struct tg3_rx_buffer_desc *desc;
7625
7626         if (!netif_running(tp->dev))
7627                 return -ENODEV;
7628
7629         err = -EIO;
7630
7631         tg3_abort_hw(tp, 1);
7632
7633         tg3_reset_hw(tp);
7634
7635         mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
7636                    MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY |
7637                    MAC_MODE_PORT_MODE_GMII;
7638         tw32(MAC_MODE, mac_mode);
7639
7640         tx_len = 1514;
7641         skb = dev_alloc_skb(tx_len);
7642         tx_data = skb_put(skb, tx_len);
7643         memcpy(tx_data, tp->dev->dev_addr, 6);
7644         memset(tx_data + 6, 0x0, 8);
7645
7646         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
7647
7648         for (i = 14; i < tx_len; i++)
7649                 tx_data[i] = (u8) (i & 0xff);
7650
7651         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
7652
7653         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7654              HOSTCC_MODE_NOW);
7655
7656         udelay(10);
7657
7658         rx_start_idx = tp->hw_status->idx[0].rx_producer;
7659
7660         send_idx = 0;
7661         num_pkts = 0;
7662
7663         tg3_set_txd(tp, send_idx, map, tx_len, 0, 1);
7664
7665         send_idx++;
7666         num_pkts++;
7667
7668         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, send_idx);
7669         tr32(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
7670
7671         udelay(10);
7672
7673         for (i = 0; i < 10; i++) {
7674                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7675                        HOSTCC_MODE_NOW);
7676
7677                 udelay(10);
7678
7679                 tx_idx = tp->hw_status->idx[0].tx_consumer;
7680                 rx_idx = tp->hw_status->idx[0].rx_producer;
7681                 if ((tx_idx == send_idx) &&
7682                     (rx_idx == (rx_start_idx + num_pkts)))
7683                         break;
7684         }
7685
7686         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
7687         dev_kfree_skb(skb);
7688
7689         if (tx_idx != send_idx)
7690                 goto out;
7691
7692         if (rx_idx != rx_start_idx + num_pkts)
7693                 goto out;
7694
7695         desc = &tp->rx_rcb[rx_start_idx];
7696         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
7697         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
7698         if (opaque_key != RXD_OPAQUE_RING_STD)
7699                 goto out;
7700
7701         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
7702             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
7703                 goto out;
7704
7705         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
7706         if (rx_len != tx_len)
7707                 goto out;
7708
7709         rx_skb = tp->rx_std_buffers[desc_idx].skb;
7710
7711         map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
7712         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
7713
7714         for (i = 14; i < tx_len; i++) {
7715                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
7716                         goto out;
7717         }
7718         err = 0;
7719
7720         /* tg3_free_rings will unmap and free the rx_skb */
7721 out:
7722         return err;
7723 }
7724
7725 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
7726                           u64 *data)
7727 {
7728         struct tg3 *tp = netdev_priv(dev);
7729
7730         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
7731
7732         if (tg3_test_nvram(tp) != 0) {
7733                 etest->flags |= ETH_TEST_FL_FAILED;
7734                 data[0] = 1;
7735         }
7736         if (tg3_test_link(tp) != 0) {
7737                 etest->flags |= ETH_TEST_FL_FAILED;
7738                 data[1] = 1;
7739         }
7740         if (etest->flags & ETH_TEST_FL_OFFLINE) {
7741                 int irq_sync = 0;
7742
7743                 if (netif_running(dev)) {
7744                         tg3_netif_stop(tp);
7745                         irq_sync = 1;
7746                 }
7747
7748                 tg3_full_lock(tp, irq_sync);
7749
7750                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
7751                 tg3_nvram_lock(tp);
7752                 tg3_halt_cpu(tp, RX_CPU_BASE);
7753                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7754                         tg3_halt_cpu(tp, TX_CPU_BASE);
7755                 tg3_nvram_unlock(tp);
7756
7757                 if (tg3_test_registers(tp) != 0) {
7758                         etest->flags |= ETH_TEST_FL_FAILED;
7759                         data[2] = 1;
7760                 }
7761                 if (tg3_test_memory(tp) != 0) {
7762                         etest->flags |= ETH_TEST_FL_FAILED;
7763                         data[3] = 1;
7764                 }
7765                 if (tg3_test_loopback(tp) != 0) {
7766                         etest->flags |= ETH_TEST_FL_FAILED;
7767                         data[4] = 1;
7768                 }
7769
7770                 tg3_full_unlock(tp);
7771
7772                 if (tg3_test_interrupt(tp) != 0) {
7773                         etest->flags |= ETH_TEST_FL_FAILED;
7774                         data[5] = 1;
7775                 }
7776
7777                 tg3_full_lock(tp, 0);
7778
7779                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7780                 if (netif_running(dev)) {
7781                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7782                         tg3_init_hw(tp);
7783                         tg3_netif_start(tp);
7784                 }
7785
7786                 tg3_full_unlock(tp);
7787         }
7788 }
7789
7790 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7791 {
7792         struct mii_ioctl_data *data = if_mii(ifr);
7793         struct tg3 *tp = netdev_priv(dev);
7794         int err;
7795
7796         switch(cmd) {
7797         case SIOCGMIIPHY:
7798                 data->phy_id = PHY_ADDR;
7799
7800                 /* fallthru */
7801         case SIOCGMIIREG: {
7802                 u32 mii_regval;
7803
7804                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7805                         break;                  /* We have no PHY */
7806
7807                 spin_lock_bh(&tp->lock);
7808                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
7809                 spin_unlock_bh(&tp->lock);
7810
7811                 data->val_out = mii_regval;
7812
7813                 return err;
7814         }
7815
7816         case SIOCSMIIREG:
7817                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7818                         break;                  /* We have no PHY */
7819
7820                 if (!capable(CAP_NET_ADMIN))
7821                         return -EPERM;
7822
7823                 spin_lock_bh(&tp->lock);
7824                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
7825                 spin_unlock_bh(&tp->lock);
7826
7827                 return err;
7828
7829         default:
7830                 /* do nothing */
7831                 break;
7832         }
7833         return -EOPNOTSUPP;
7834 }
7835
7836 #if TG3_VLAN_TAG_USED
7837 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
7838 {
7839         struct tg3 *tp = netdev_priv(dev);
7840
7841         tg3_full_lock(tp, 0);
7842
7843         tp->vlgrp = grp;
7844
7845         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
7846         __tg3_set_rx_mode(dev);
7847
7848         tg3_full_unlock(tp);
7849 }
7850
7851 static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
7852 {
7853         struct tg3 *tp = netdev_priv(dev);
7854
7855         tg3_full_lock(tp, 0);
7856         if (tp->vlgrp)
7857                 tp->vlgrp->vlan_devices[vid] = NULL;
7858         tg3_full_unlock(tp);
7859 }
7860 #endif
7861
7862 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
7863 {
7864         struct tg3 *tp = netdev_priv(dev);
7865
7866         memcpy(ec, &tp->coal, sizeof(*ec));
7867         return 0;
7868 }
7869
7870 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
7871 {
7872         struct tg3 *tp = netdev_priv(dev);
7873         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
7874         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
7875
7876         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7877                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
7878                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
7879                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
7880                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
7881         }
7882
7883         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
7884             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
7885             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
7886             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
7887             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
7888             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
7889             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
7890             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
7891             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
7892             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
7893                 return -EINVAL;
7894
7895         /* No rx interrupts will be generated if both are zero */
7896         if ((ec->rx_coalesce_usecs == 0) &&
7897             (ec->rx_max_coalesced_frames == 0))
7898                 return -EINVAL;
7899
7900         /* No tx interrupts will be generated if both are zero */
7901         if ((ec->tx_coalesce_usecs == 0) &&
7902             (ec->tx_max_coalesced_frames == 0))
7903                 return -EINVAL;
7904
7905         /* Only copy relevant parameters, ignore all others. */
7906         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
7907         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
7908         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
7909         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
7910         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
7911         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
7912         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
7913         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
7914         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
7915
7916         if (netif_running(dev)) {
7917                 tg3_full_lock(tp, 0);
7918                 __tg3_set_coalesce(tp, &tp->coal);
7919                 tg3_full_unlock(tp);
7920         }
7921         return 0;
7922 }
7923
7924 static struct ethtool_ops tg3_ethtool_ops = {
7925         .get_settings           = tg3_get_settings,
7926         .set_settings           = tg3_set_settings,
7927         .get_drvinfo            = tg3_get_drvinfo,
7928         .get_regs_len           = tg3_get_regs_len,
7929         .get_regs               = tg3_get_regs,
7930         .get_wol                = tg3_get_wol,
7931         .set_wol                = tg3_set_wol,
7932         .get_msglevel           = tg3_get_msglevel,
7933         .set_msglevel           = tg3_set_msglevel,
7934         .nway_reset             = tg3_nway_reset,
7935         .get_link               = ethtool_op_get_link,
7936         .get_eeprom_len         = tg3_get_eeprom_len,
7937         .get_eeprom             = tg3_get_eeprom,
7938         .set_eeprom             = tg3_set_eeprom,
7939         .get_ringparam          = tg3_get_ringparam,
7940         .set_ringparam          = tg3_set_ringparam,
7941         .get_pauseparam         = tg3_get_pauseparam,
7942         .set_pauseparam         = tg3_set_pauseparam,
7943         .get_rx_csum            = tg3_get_rx_csum,
7944         .set_rx_csum            = tg3_set_rx_csum,
7945         .get_tx_csum            = ethtool_op_get_tx_csum,
7946         .set_tx_csum            = tg3_set_tx_csum,
7947         .get_sg                 = ethtool_op_get_sg,
7948         .set_sg                 = ethtool_op_set_sg,
7949 #if TG3_TSO_SUPPORT != 0
7950         .get_tso                = ethtool_op_get_tso,
7951         .set_tso                = tg3_set_tso,
7952 #endif
7953         .self_test_count        = tg3_get_test_count,
7954         .self_test              = tg3_self_test,
7955         .get_strings            = tg3_get_strings,
7956         .get_stats_count        = tg3_get_stats_count,
7957         .get_ethtool_stats      = tg3_get_ethtool_stats,
7958         .get_coalesce           = tg3_get_coalesce,
7959         .set_coalesce           = tg3_set_coalesce,
7960 };
7961
7962 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
7963 {
7964         u32 cursize, val;
7965
7966         tp->nvram_size = EEPROM_CHIP_SIZE;
7967
7968         if (tg3_nvram_read(tp, 0, &val) != 0)
7969                 return;
7970
7971         if (swab32(val) != TG3_EEPROM_MAGIC)
7972                 return;
7973
7974         /*
7975          * Size the chip by reading offsets at increasing powers of two.
7976          * When we encounter our validation signature, we know the addressing
7977          * has wrapped around, and thus have our chip size.
7978          */
7979         cursize = 0x800;
7980
7981         while (cursize < tp->nvram_size) {
7982                 if (tg3_nvram_read(tp, cursize, &val) != 0)
7983                         return;
7984
7985                 if (swab32(val) == TG3_EEPROM_MAGIC)
7986                         break;
7987
7988                 cursize <<= 1;
7989         }
7990
7991         tp->nvram_size = cursize;
7992 }
7993
7994 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
7995 {
7996         u32 val;
7997
7998         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
7999                 if (val != 0) {
8000                         tp->nvram_size = (val >> 16) * 1024;
8001                         return;
8002                 }
8003         }
8004         tp->nvram_size = 0x20000;
8005 }
8006
8007 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
8008 {
8009         u32 nvcfg1;
8010
8011         nvcfg1 = tr32(NVRAM_CFG1);
8012         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
8013                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8014         }
8015         else {
8016                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
8017                 tw32(NVRAM_CFG1, nvcfg1);
8018         }
8019
8020         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8021                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8022                         case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
8023                                 tp->nvram_jedecnum = JEDEC_ATMEL;
8024                                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
8025                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8026                                 break;
8027                         case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
8028                                 tp->nvram_jedecnum = JEDEC_ATMEL;
8029                                 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
8030                                 break;
8031                         case FLASH_VENDOR_ATMEL_EEPROM:
8032                                 tp->nvram_jedecnum = JEDEC_ATMEL;
8033                                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
8034                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8035                                 break;
8036                         case FLASH_VENDOR_ST:
8037                                 tp->nvram_jedecnum = JEDEC_ST;
8038                                 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
8039                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8040                                 break;
8041                         case FLASH_VENDOR_SAIFUN:
8042                                 tp->nvram_jedecnum = JEDEC_SAIFUN;
8043                                 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
8044                                 break;
8045                         case FLASH_VENDOR_SST_SMALL:
8046                         case FLASH_VENDOR_SST_LARGE:
8047                                 tp->nvram_jedecnum = JEDEC_SST;
8048                                 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
8049                                 break;
8050                 }
8051         }
8052         else {
8053                 tp->nvram_jedecnum = JEDEC_ATMEL;
8054                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
8055                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8056         }
8057 }
8058
8059 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
8060 {
8061         u32 nvcfg1;
8062
8063         nvcfg1 = tr32(NVRAM_CFG1);
8064
8065         /* NVRAM protection for TPM */
8066         if (nvcfg1 & (1 << 27))
8067                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
8068
8069         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8070                 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
8071                 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
8072                         tp->nvram_jedecnum = JEDEC_ATMEL;
8073                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8074                         break;
8075                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
8076                         tp->nvram_jedecnum = JEDEC_ATMEL;
8077                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8078                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
8079                         break;
8080                 case FLASH_5752VENDOR_ST_M45PE10:
8081                 case FLASH_5752VENDOR_ST_M45PE20:
8082                 case FLASH_5752VENDOR_ST_M45PE40:
8083                         tp->nvram_jedecnum = JEDEC_ST;
8084                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8085                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
8086                         break;
8087         }
8088
8089         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
8090                 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
8091                         case FLASH_5752PAGE_SIZE_256:
8092                                 tp->nvram_pagesize = 256;
8093                                 break;
8094                         case FLASH_5752PAGE_SIZE_512:
8095                                 tp->nvram_pagesize = 512;
8096                                 break;
8097                         case FLASH_5752PAGE_SIZE_1K:
8098                                 tp->nvram_pagesize = 1024;
8099                                 break;
8100                         case FLASH_5752PAGE_SIZE_2K:
8101                                 tp->nvram_pagesize = 2048;
8102                                 break;
8103                         case FLASH_5752PAGE_SIZE_4K:
8104                                 tp->nvram_pagesize = 4096;
8105                                 break;
8106                         case FLASH_5752PAGE_SIZE_264:
8107                                 tp->nvram_pagesize = 264;
8108                                 break;
8109                 }
8110         }
8111         else {
8112                 /* For eeprom, set pagesize to maximum eeprom size */
8113                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
8114
8115                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
8116                 tw32(NVRAM_CFG1, nvcfg1);
8117         }
8118 }
8119
8120 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
8121 static void __devinit tg3_nvram_init(struct tg3 *tp)
8122 {
8123         int j;
8124
8125         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X)
8126                 return;
8127
8128         tw32_f(GRC_EEPROM_ADDR,
8129              (EEPROM_ADDR_FSM_RESET |
8130               (EEPROM_DEFAULT_CLOCK_PERIOD <<
8131                EEPROM_ADDR_CLKPERD_SHIFT)));
8132
8133         /* XXX schedule_timeout() ... */
8134         for (j = 0; j < 100; j++)
8135                 udelay(10);
8136
8137         /* Enable seeprom accesses. */
8138         tw32_f(GRC_LOCAL_CTRL,
8139              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
8140         udelay(100);
8141
8142         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
8143             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
8144                 tp->tg3_flags |= TG3_FLAG_NVRAM;
8145
8146                 tg3_enable_nvram_access(tp);
8147
8148                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8149                         tg3_get_5752_nvram_info(tp);
8150                 else
8151                         tg3_get_nvram_info(tp);
8152
8153                 tg3_get_nvram_size(tp);
8154
8155                 tg3_disable_nvram_access(tp);
8156
8157         } else {
8158                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
8159
8160                 tg3_get_eeprom_size(tp);
8161         }
8162 }
8163
8164 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
8165                                         u32 offset, u32 *val)
8166 {
8167         u32 tmp;
8168         int i;
8169
8170         if (offset > EEPROM_ADDR_ADDR_MASK ||
8171             (offset % 4) != 0)
8172                 return -EINVAL;
8173
8174         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
8175                                         EEPROM_ADDR_DEVID_MASK |
8176                                         EEPROM_ADDR_READ);
8177         tw32(GRC_EEPROM_ADDR,
8178              tmp |
8179              (0 << EEPROM_ADDR_DEVID_SHIFT) |
8180              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
8181               EEPROM_ADDR_ADDR_MASK) |
8182              EEPROM_ADDR_READ | EEPROM_ADDR_START);
8183
8184         for (i = 0; i < 10000; i++) {
8185                 tmp = tr32(GRC_EEPROM_ADDR);
8186
8187                 if (tmp & EEPROM_ADDR_COMPLETE)
8188                         break;
8189                 udelay(100);
8190         }
8191         if (!(tmp & EEPROM_ADDR_COMPLETE))
8192                 return -EBUSY;
8193
8194         *val = tr32(GRC_EEPROM_DATA);
8195         return 0;
8196 }
8197
8198 #define NVRAM_CMD_TIMEOUT 10000
8199
8200 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
8201 {
8202         int i;
8203
8204         tw32(NVRAM_CMD, nvram_cmd);
8205         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
8206                 udelay(10);
8207                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
8208                         udelay(10);
8209                         break;
8210                 }
8211         }
8212         if (i == NVRAM_CMD_TIMEOUT) {
8213                 return -EBUSY;
8214         }
8215         return 0;
8216 }
8217
8218 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
8219 {
8220         int ret;
8221
8222         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
8223                 printk(KERN_ERR PFX "Attempt to do nvram_read on Sun 570X\n");
8224                 return -EINVAL;
8225         }
8226
8227         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
8228                 return tg3_nvram_read_using_eeprom(tp, offset, val);
8229
8230         if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
8231                 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
8232                 (tp->nvram_jedecnum == JEDEC_ATMEL)) {
8233
8234                 offset = ((offset / tp->nvram_pagesize) <<
8235                           ATMEL_AT45DB0X1B_PAGE_POS) +
8236                         (offset % tp->nvram_pagesize);
8237         }
8238
8239         if (offset > NVRAM_ADDR_MSK)
8240                 return -EINVAL;
8241
8242         tg3_nvram_lock(tp);
8243
8244         tg3_enable_nvram_access(tp);
8245
8246         tw32(NVRAM_ADDR, offset);
8247         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
8248                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
8249
8250         if (ret == 0)
8251                 *val = swab32(tr32(NVRAM_RDDATA));
8252
8253         tg3_nvram_unlock(tp);
8254
8255         tg3_disable_nvram_access(tp);
8256
8257         return ret;
8258 }
8259
8260 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
8261                                     u32 offset, u32 len, u8 *buf)
8262 {
8263         int i, j, rc = 0;
8264         u32 val;
8265
8266         for (i = 0; i < len; i += 4) {
8267                 u32 addr, data;
8268
8269                 addr = offset + i;
8270
8271                 memcpy(&data, buf + i, 4);
8272
8273                 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
8274
8275                 val = tr32(GRC_EEPROM_ADDR);
8276                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
8277
8278                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
8279                         EEPROM_ADDR_READ);
8280                 tw32(GRC_EEPROM_ADDR, val |
8281                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
8282                         (addr & EEPROM_ADDR_ADDR_MASK) |
8283                         EEPROM_ADDR_START |
8284                         EEPROM_ADDR_WRITE);
8285
8286                 for (j = 0; j < 10000; j++) {
8287                         val = tr32(GRC_EEPROM_ADDR);
8288
8289                         if (val & EEPROM_ADDR_COMPLETE)
8290                                 break;
8291                         udelay(100);
8292                 }
8293                 if (!(val & EEPROM_ADDR_COMPLETE)) {
8294                         rc = -EBUSY;
8295                         break;
8296                 }
8297         }
8298
8299         return rc;
8300 }
8301
8302 /* offset and length are dword aligned */
8303 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
8304                 u8 *buf)
8305 {
8306         int ret = 0;
8307         u32 pagesize = tp->nvram_pagesize;
8308         u32 pagemask = pagesize - 1;
8309         u32 nvram_cmd;
8310         u8 *tmp;
8311
8312         tmp = kmalloc(pagesize, GFP_KERNEL);
8313         if (tmp == NULL)
8314                 return -ENOMEM;
8315
8316         while (len) {
8317                 int j;
8318                 u32 phy_addr, page_off, size;
8319
8320                 phy_addr = offset & ~pagemask;
8321
8322                 for (j = 0; j < pagesize; j += 4) {
8323                         if ((ret = tg3_nvram_read(tp, phy_addr + j,
8324                                                 (u32 *) (tmp + j))))
8325                                 break;
8326                 }
8327                 if (ret)
8328                         break;
8329
8330                 page_off = offset & pagemask;
8331                 size = pagesize;
8332                 if (len < size)
8333                         size = len;
8334
8335                 len -= size;
8336
8337                 memcpy(tmp + page_off, buf, size);
8338
8339                 offset = offset + (pagesize - page_off);
8340
8341                 tg3_enable_nvram_access(tp);
8342
8343                 /*
8344                  * Before we can erase the flash page, we need
8345                  * to issue a special "write enable" command.
8346                  */
8347                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8348
8349                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8350                         break;
8351
8352                 /* Erase the target page */
8353                 tw32(NVRAM_ADDR, phy_addr);
8354
8355                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
8356                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
8357
8358                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8359                         break;
8360
8361                 /* Issue another write enable to start the write. */
8362                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8363
8364                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8365                         break;
8366
8367                 for (j = 0; j < pagesize; j += 4) {
8368                         u32 data;
8369
8370                         data = *((u32 *) (tmp + j));
8371                         tw32(NVRAM_WRDATA, cpu_to_be32(data));
8372
8373                         tw32(NVRAM_ADDR, phy_addr + j);
8374
8375                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
8376                                 NVRAM_CMD_WR;
8377
8378                         if (j == 0)
8379                                 nvram_cmd |= NVRAM_CMD_FIRST;
8380                         else if (j == (pagesize - 4))
8381                                 nvram_cmd |= NVRAM_CMD_LAST;
8382
8383                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
8384                                 break;
8385                 }
8386                 if (ret)
8387                         break;
8388         }
8389
8390         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8391         tg3_nvram_exec_cmd(tp, nvram_cmd);
8392
8393         kfree(tmp);
8394
8395         return ret;
8396 }
8397
8398 /* offset and length are dword aligned */
8399 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
8400                 u8 *buf)
8401 {
8402         int i, ret = 0;
8403
8404         for (i = 0; i < len; i += 4, offset += 4) {
8405                 u32 data, page_off, phy_addr, nvram_cmd;
8406
8407                 memcpy(&data, buf + i, 4);
8408                 tw32(NVRAM_WRDATA, cpu_to_be32(data));
8409
8410                 page_off = offset % tp->nvram_pagesize;
8411
8412                 if ((tp->tg3_flags2 & TG3_FLG2_FLASH) &&
8413                         (tp->nvram_jedecnum == JEDEC_ATMEL)) {
8414
8415                         phy_addr = ((offset / tp->nvram_pagesize) <<
8416                                     ATMEL_AT45DB0X1B_PAGE_POS) + page_off;
8417                 }
8418                 else {
8419                         phy_addr = offset;
8420                 }
8421
8422                 tw32(NVRAM_ADDR, phy_addr);
8423
8424                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
8425
8426                 if ((page_off == 0) || (i == 0))
8427                         nvram_cmd |= NVRAM_CMD_FIRST;
8428                 else if (page_off == (tp->nvram_pagesize - 4))
8429                         nvram_cmd |= NVRAM_CMD_LAST;
8430
8431                 if (i == (len - 4))
8432                         nvram_cmd |= NVRAM_CMD_LAST;
8433
8434                 if ((tp->nvram_jedecnum == JEDEC_ST) &&
8435                         (nvram_cmd & NVRAM_CMD_FIRST)) {
8436
8437                         if ((ret = tg3_nvram_exec_cmd(tp,
8438                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
8439                                 NVRAM_CMD_DONE)))
8440
8441                                 break;
8442                 }
8443                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
8444                         /* We always do complete word writes to eeprom. */
8445                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
8446                 }
8447
8448                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
8449                         break;
8450         }
8451         return ret;
8452 }
8453
8454 /* offset and length are dword aligned */
8455 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
8456 {
8457         int ret;
8458
8459         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
8460                 printk(KERN_ERR PFX "Attempt to do nvram_write on Sun 570X\n");
8461                 return -EINVAL;
8462         }
8463
8464         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
8465                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
8466                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
8467                 udelay(40);
8468         }
8469
8470         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
8471                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
8472         }
8473         else {
8474                 u32 grc_mode;
8475
8476                 tg3_nvram_lock(tp);
8477
8478                 tg3_enable_nvram_access(tp);
8479                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
8480                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
8481                         tw32(NVRAM_WRITE1, 0x406);
8482
8483                 grc_mode = tr32(GRC_MODE);
8484                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
8485
8486                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
8487                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
8488
8489                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
8490                                 buf);
8491                 }
8492                 else {
8493                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
8494                                 buf);
8495                 }
8496
8497                 grc_mode = tr32(GRC_MODE);
8498                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
8499
8500                 tg3_disable_nvram_access(tp);
8501                 tg3_nvram_unlock(tp);
8502         }
8503
8504         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
8505                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8506                 udelay(40);
8507         }
8508
8509         return ret;
8510 }
8511
8512 struct subsys_tbl_ent {
8513         u16 subsys_vendor, subsys_devid;
8514         u32 phy_id;
8515 };
8516
8517 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
8518         /* Broadcom boards. */
8519         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
8520         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
8521         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
8522         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
8523         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
8524         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
8525         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
8526         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
8527         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
8528         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
8529         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
8530
8531         /* 3com boards. */
8532         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
8533         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
8534         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
8535         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
8536         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
8537
8538         /* DELL boards. */
8539         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
8540         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
8541         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
8542         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
8543
8544         /* Compaq boards. */
8545         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
8546         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
8547         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
8548         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
8549         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
8550
8551         /* IBM boards. */
8552         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
8553 };
8554
8555 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
8556 {
8557         int i;
8558
8559         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
8560                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
8561                      tp->pdev->subsystem_vendor) &&
8562                     (subsys_id_to_phy_id[i].subsys_devid ==
8563                      tp->pdev->subsystem_device))
8564                         return &subsys_id_to_phy_id[i];
8565         }
8566         return NULL;
8567 }
8568
8569 /* Since this function may be called in D3-hot power state during
8570  * tg3_init_one(), only config cycles are allowed.
8571  */
8572 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
8573 {
8574         u32 val;
8575
8576         /* Make sure register accesses (indirect or otherwise)
8577          * will function correctly.
8578          */
8579         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8580                                tp->misc_host_ctrl);
8581
8582         tp->phy_id = PHY_ID_INVALID;
8583         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
8584
8585         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
8586         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
8587                 u32 nic_cfg, led_cfg;
8588                 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
8589                 int eeprom_phy_serdes = 0;
8590
8591                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
8592                 tp->nic_sram_data_cfg = nic_cfg;
8593
8594                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
8595                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
8596                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
8597                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
8598                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
8599                     (ver > 0) && (ver < 0x100))
8600                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
8601
8602                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
8603                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
8604                         eeprom_phy_serdes = 1;
8605
8606                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
8607                 if (nic_phy_id != 0) {
8608                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
8609                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
8610
8611                         eeprom_phy_id  = (id1 >> 16) << 10;
8612                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
8613                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
8614                 } else
8615                         eeprom_phy_id = 0;
8616
8617                 tp->phy_id = eeprom_phy_id;
8618                 if (eeprom_phy_serdes)
8619                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
8620
8621                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8622                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
8623                                     SHASTA_EXT_LED_MODE_MASK);
8624                 else
8625                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
8626
8627                 switch (led_cfg) {
8628                 default:
8629                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
8630                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
8631                         break;
8632
8633                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
8634                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
8635                         break;
8636
8637                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
8638                         tp->led_ctrl = LED_CTRL_MODE_MAC;
8639
8640                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
8641                          * read on some older 5700/5701 bootcode.
8642                          */
8643                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
8644                             ASIC_REV_5700 ||
8645                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
8646                             ASIC_REV_5701)
8647                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
8648
8649                         break;
8650
8651                 case SHASTA_EXT_LED_SHARED:
8652                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
8653                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
8654                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
8655                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
8656                                                  LED_CTRL_MODE_PHY_2);
8657                         break;
8658
8659                 case SHASTA_EXT_LED_MAC:
8660                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
8661                         break;
8662
8663                 case SHASTA_EXT_LED_COMBO:
8664                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
8665                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
8666                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
8667                                                  LED_CTRL_MODE_PHY_2);
8668                         break;
8669
8670                 };
8671
8672                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8673                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
8674                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
8675                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
8676
8677                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
8678                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
8679                     (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP))
8680                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
8681
8682                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
8683                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
8684                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8685                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
8686                 }
8687                 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
8688                         tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
8689
8690                 if (cfg2 & (1 << 17))
8691                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
8692
8693                 /* serdes signal pre-emphasis in register 0x590 set by */
8694                 /* bootcode if bit 18 is set */
8695                 if (cfg2 & (1 << 18))
8696                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8697         }
8698 }
8699
8700 static int __devinit tg3_phy_probe(struct tg3 *tp)
8701 {
8702         u32 hw_phy_id_1, hw_phy_id_2;
8703         u32 hw_phy_id, hw_phy_id_masked;
8704         int err;
8705
8706         /* Reading the PHY ID register can conflict with ASF
8707          * firwmare access to the PHY hardware.
8708          */
8709         err = 0;
8710         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
8711                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
8712         } else {
8713                 /* Now read the physical PHY_ID from the chip and verify
8714                  * that it is sane.  If it doesn't look good, we fall back
8715                  * to either the hard-coded table based PHY_ID and failing
8716                  * that the value found in the eeprom area.
8717                  */
8718                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
8719                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
8720
8721                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
8722                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
8723                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
8724
8725                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
8726         }
8727
8728         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
8729                 tp->phy_id = hw_phy_id;
8730                 if (hw_phy_id_masked == PHY_ID_BCM8002)
8731                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
8732         } else {
8733                 if (tp->phy_id != PHY_ID_INVALID) {
8734                         /* Do nothing, phy ID already set up in
8735                          * tg3_get_eeprom_hw_cfg().
8736                          */
8737                 } else {
8738                         struct subsys_tbl_ent *p;
8739
8740                         /* No eeprom signature?  Try the hardcoded
8741                          * subsys device table.
8742                          */
8743                         p = lookup_by_subsys(tp);
8744                         if (!p)
8745                                 return -ENODEV;
8746
8747                         tp->phy_id = p->phy_id;
8748                         if (!tp->phy_id ||
8749                             tp->phy_id == PHY_ID_BCM8002)
8750                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
8751                 }
8752         }
8753
8754         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8755             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
8756                 u32 bmsr, adv_reg, tg3_ctrl;
8757
8758                 tg3_readphy(tp, MII_BMSR, &bmsr);
8759                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
8760                     (bmsr & BMSR_LSTATUS))
8761                         goto skip_phy_reset;
8762
8763                 err = tg3_phy_reset(tp);
8764                 if (err)
8765                         return err;
8766
8767                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
8768                            ADVERTISE_100HALF | ADVERTISE_100FULL |
8769                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
8770                 tg3_ctrl = 0;
8771                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
8772                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
8773                                     MII_TG3_CTRL_ADV_1000_FULL);
8774                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
8775                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
8776                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
8777                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
8778                 }
8779
8780                 if (!tg3_copper_is_advertising_all(tp)) {
8781                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
8782
8783                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8784                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
8785
8786                         tg3_writephy(tp, MII_BMCR,
8787                                      BMCR_ANENABLE | BMCR_ANRESTART);
8788                 }
8789                 tg3_phy_set_wirespeed(tp);
8790
8791                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
8792                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8793                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
8794         }
8795
8796 skip_phy_reset:
8797         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
8798                 err = tg3_init_5401phy_dsp(tp);
8799                 if (err)
8800                         return err;
8801         }
8802
8803         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
8804                 err = tg3_init_5401phy_dsp(tp);
8805         }
8806
8807         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8808                 tp->link_config.advertising =
8809                         (ADVERTISED_1000baseT_Half |
8810                          ADVERTISED_1000baseT_Full |
8811                          ADVERTISED_Autoneg |
8812                          ADVERTISED_FIBRE);
8813         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8814                 tp->link_config.advertising &=
8815                         ~(ADVERTISED_1000baseT_Half |
8816                           ADVERTISED_1000baseT_Full);
8817
8818         return err;
8819 }
8820
8821 static void __devinit tg3_read_partno(struct tg3 *tp)
8822 {
8823         unsigned char vpd_data[256];
8824         int i;
8825
8826         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
8827                 /* Sun decided not to put the necessary bits in the
8828                  * NVRAM of their onboard tg3 parts :(
8829                  */
8830                 strcpy(tp->board_part_number, "Sun 570X");
8831                 return;
8832         }
8833
8834         for (i = 0; i < 256; i += 4) {
8835                 u32 tmp;
8836
8837                 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
8838                         goto out_not_found;
8839
8840                 vpd_data[i + 0] = ((tmp >>  0) & 0xff);
8841                 vpd_data[i + 1] = ((tmp >>  8) & 0xff);
8842                 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
8843                 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
8844         }
8845
8846         /* Now parse and find the part number. */
8847         for (i = 0; i < 256; ) {
8848                 unsigned char val = vpd_data[i];
8849                 int block_end;
8850
8851                 if (val == 0x82 || val == 0x91) {
8852                         i = (i + 3 +
8853                              (vpd_data[i + 1] +
8854                               (vpd_data[i + 2] << 8)));
8855                         continue;
8856                 }
8857
8858                 if (val != 0x90)
8859                         goto out_not_found;
8860
8861                 block_end = (i + 3 +
8862                              (vpd_data[i + 1] +
8863                               (vpd_data[i + 2] << 8)));
8864                 i += 3;
8865                 while (i < block_end) {
8866                         if (vpd_data[i + 0] == 'P' &&
8867                             vpd_data[i + 1] == 'N') {
8868                                 int partno_len = vpd_data[i + 2];
8869
8870                                 if (partno_len > 24)
8871                                         goto out_not_found;
8872
8873                                 memcpy(tp->board_part_number,
8874                                        &vpd_data[i + 3],
8875                                        partno_len);
8876
8877                                 /* Success. */
8878                                 return;
8879                         }
8880                 }
8881
8882                 /* Part number not found. */
8883                 goto out_not_found;
8884         }
8885
8886 out_not_found:
8887         strcpy(tp->board_part_number, "none");
8888 }
8889
8890 #ifdef CONFIG_SPARC64
8891 static int __devinit tg3_is_sun_570X(struct tg3 *tp)
8892 {
8893         struct pci_dev *pdev = tp->pdev;
8894         struct pcidev_cookie *pcp = pdev->sysdata;
8895
8896         if (pcp != NULL) {
8897                 int node = pcp->prom_node;
8898                 u32 venid;
8899                 int err;
8900
8901                 err = prom_getproperty(node, "subsystem-vendor-id",
8902                                        (char *) &venid, sizeof(venid));
8903                 if (err == 0 || err == -1)
8904                         return 0;
8905                 if (venid == PCI_VENDOR_ID_SUN)
8906                         return 1;
8907         }
8908         return 0;
8909 }
8910 #endif
8911
8912 static int __devinit tg3_get_invariants(struct tg3 *tp)
8913 {
8914         static struct pci_device_id write_reorder_chipsets[] = {
8915                 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
8916                              PCI_DEVICE_ID_INTEL_82801AA_8) },
8917                 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
8918                              PCI_DEVICE_ID_INTEL_82801AB_8) },
8919                 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
8920                              PCI_DEVICE_ID_INTEL_82801BA_11) },
8921                 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
8922                              PCI_DEVICE_ID_INTEL_82801BA_6) },
8923                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
8924                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
8925                 { },
8926         };
8927         u32 misc_ctrl_reg;
8928         u32 cacheline_sz_reg;
8929         u32 pci_state_reg, grc_misc_cfg;
8930         u32 val;
8931         u16 pci_cmd;
8932         int err;
8933
8934 #ifdef CONFIG_SPARC64
8935         if (tg3_is_sun_570X(tp))
8936                 tp->tg3_flags2 |= TG3_FLG2_SUN_570X;
8937 #endif
8938
8939         /* If we have an AMD 762 or Intel ICH/ICH0/ICH2 chipset, write
8940          * reordering to the mailbox registers done by the host
8941          * controller can cause major troubles.  We read back from
8942          * every mailbox register write to force the writes to be
8943          * posted to the chip in order.
8944          */
8945         if (pci_dev_present(write_reorder_chipsets))
8946                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
8947
8948         /* Force memory write invalidate off.  If we leave it on,
8949          * then on 5700_BX chips we have to enable a workaround.
8950          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
8951          * to match the cacheline size.  The Broadcom driver have this
8952          * workaround but turns MWI off all the times so never uses
8953          * it.  This seems to suggest that the workaround is insufficient.
8954          */
8955         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8956         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
8957         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8958
8959         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
8960          * has the register indirect write enable bit set before
8961          * we try to access any of the MMIO registers.  It is also
8962          * critical that the PCI-X hw workaround situation is decided
8963          * before that as well.
8964          */
8965         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8966                               &misc_ctrl_reg);
8967
8968         tp->pci_chip_rev_id = (misc_ctrl_reg >>
8969                                MISC_HOST_CTRL_CHIPREV_SHIFT);
8970
8971         /* Wrong chip ID in 5752 A0. This code can be removed later
8972          * as A0 is not in production.
8973          */
8974         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
8975                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
8976
8977         /* Find msi capability. */
8978         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8979                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
8980
8981         /* Initialize misc host control in PCI block. */
8982         tp->misc_host_ctrl |= (misc_ctrl_reg &
8983                                MISC_HOST_CTRL_CHIPREV);
8984         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8985                                tp->misc_host_ctrl);
8986
8987         pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
8988                               &cacheline_sz_reg);
8989
8990         tp->pci_cacheline_sz = (cacheline_sz_reg >>  0) & 0xff;
8991         tp->pci_lat_timer    = (cacheline_sz_reg >>  8) & 0xff;
8992         tp->pci_hdr_type     = (cacheline_sz_reg >> 16) & 0xff;
8993         tp->pci_bist         = (cacheline_sz_reg >> 24) & 0xff;
8994
8995         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
8996             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
8997             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8998                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
8999
9000         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
9001             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
9002                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
9003
9004         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9005                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO;
9006
9007         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
9008             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
9009             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752)
9010                 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
9011
9012         if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
9013                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
9014
9015         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
9016             tp->pci_lat_timer < 64) {
9017                 tp->pci_lat_timer = 64;
9018
9019                 cacheline_sz_reg  = ((tp->pci_cacheline_sz & 0xff) <<  0);
9020                 cacheline_sz_reg |= ((tp->pci_lat_timer    & 0xff) <<  8);
9021                 cacheline_sz_reg |= ((tp->pci_hdr_type     & 0xff) << 16);
9022                 cacheline_sz_reg |= ((tp->pci_bist         & 0xff) << 24);
9023
9024                 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
9025                                        cacheline_sz_reg);
9026         }
9027
9028         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
9029                               &pci_state_reg);
9030
9031         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
9032                 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
9033
9034                 /* If this is a 5700 BX chipset, and we are in PCI-X
9035                  * mode, enable register write workaround.
9036                  *
9037                  * The workaround is to use indirect register accesses
9038                  * for all chip writes not to mailbox registers.
9039                  */
9040                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
9041                         u32 pm_reg;
9042                         u16 pci_cmd;
9043
9044                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
9045
9046                         /* The chip can have it's power management PCI config
9047                          * space registers clobbered due to this bug.
9048                          * So explicitly force the chip into D0 here.
9049                          */
9050                         pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
9051                                               &pm_reg);
9052                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
9053                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9054                         pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
9055                                                pm_reg);
9056
9057                         /* Also, force SERR#/PERR# in PCI command. */
9058                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9059                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
9060                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9061                 }
9062         }
9063
9064         /* Back to back register writes can cause problems on this chip,
9065          * the workaround is to read back all reg writes except those to
9066          * mailbox regs.  See tg3_write_indirect_reg32().
9067          *
9068          * PCI Express 5750_A0 rev chips need this workaround too.
9069          */
9070         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
9071             ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
9072              tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
9073                 tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
9074
9075         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
9076                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
9077         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
9078                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
9079
9080         /* Chip-specific fixup from Broadcom driver */
9081         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
9082             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
9083                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
9084                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
9085         }
9086
9087         /* Get eeprom hw config before calling tg3_set_power_state().
9088          * In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be
9089          * determined before calling tg3_set_power_state() so that
9090          * we know whether or not to switch out of Vaux power.
9091          * When the flag is set, it means that GPIO1 is used for eeprom
9092          * write protect and also implies that it is a LOM where GPIOs
9093          * are not used to switch power.
9094          */
9095         tg3_get_eeprom_hw_cfg(tp);
9096
9097         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
9098          * GPIO1 driven high will bring 5700's external PHY out of reset.
9099          * It is also used as eeprom write protect on LOMs.
9100          */
9101         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
9102         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
9103             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
9104                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
9105                                        GRC_LCLCTRL_GPIO_OUTPUT1);
9106         /* Unused GPIO3 must be driven as output on 5752 because there
9107          * are no pull-up resistors on unused GPIO pins.
9108          */
9109         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9110                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
9111
9112         /* Force the chip into D0. */
9113         err = tg3_set_power_state(tp, 0);
9114         if (err) {
9115                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
9116                        pci_name(tp->pdev));
9117                 return err;
9118         }
9119
9120         /* 5700 B0 chips do not support checksumming correctly due
9121          * to hardware bugs.
9122          */
9123         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
9124                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
9125
9126         /* Pseudo-header checksum is done by hardware logic and not
9127          * the offload processers, so make the chip do the pseudo-
9128          * header checksums on receive.  For transmit it is more
9129          * convenient to do the pseudo-header checksum in software
9130          * as Linux does that on transmit for us in all cases.
9131          */
9132         tp->tg3_flags |= TG3_FLAG_NO_TX_PSEUDO_CSUM;
9133         tp->tg3_flags &= ~TG3_FLAG_NO_RX_PSEUDO_CSUM;
9134
9135         /* Derive initial jumbo mode from MTU assigned in
9136          * ether_setup() via the alloc_etherdev() call
9137          */
9138         if (tp->dev->mtu > ETH_DATA_LEN &&
9139             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780)
9140                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
9141
9142         /* Determine WakeOnLan speed to use. */
9143         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9144             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
9145             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
9146             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
9147                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
9148         } else {
9149                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
9150         }
9151
9152         /* A few boards don't want Ethernet@WireSpeed phy feature */
9153         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
9154             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
9155              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
9156              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)))
9157                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
9158
9159         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
9160             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
9161                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
9162         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
9163                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
9164
9165         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
9166                 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
9167
9168         tp->coalesce_mode = 0;
9169         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
9170             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
9171                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
9172
9173         /* Initialize MAC MI mode, polling disabled. */
9174         tw32_f(MAC_MI_MODE, tp->mi_mode);
9175         udelay(80);
9176
9177         /* Initialize data/descriptor byte/word swapping. */
9178         val = tr32(GRC_MODE);
9179         val &= GRC_MODE_HOST_STACKUP;
9180         tw32(GRC_MODE, val | tp->grc_mode);
9181
9182         tg3_switch_clocks(tp);
9183
9184         /* Clear this out for sanity. */
9185         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
9186
9187         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
9188                               &pci_state_reg);
9189         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
9190             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
9191                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
9192
9193                 if (chiprevid == CHIPREV_ID_5701_A0 ||
9194                     chiprevid == CHIPREV_ID_5701_B0 ||
9195                     chiprevid == CHIPREV_ID_5701_B2 ||
9196                     chiprevid == CHIPREV_ID_5701_B5) {
9197                         void __iomem *sram_base;
9198
9199                         /* Write some dummy words into the SRAM status block
9200                          * area, see if it reads back correctly.  If the return
9201                          * value is bad, force enable the PCIX workaround.
9202                          */
9203                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
9204
9205                         writel(0x00000000, sram_base);
9206                         writel(0x00000000, sram_base + 4);
9207                         writel(0xffffffff, sram_base + 4);
9208                         if (readl(sram_base) != 0x00000000)
9209                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
9210                 }
9211         }
9212
9213         udelay(50);
9214         tg3_nvram_init(tp);
9215
9216         grc_misc_cfg = tr32(GRC_MISC_CFG);
9217         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
9218
9219         /* Broadcom's driver says that CIOBE multisplit has a bug */
9220 #if 0
9221         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
9222             grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
9223                 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
9224                 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
9225         }
9226 #endif
9227         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
9228             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
9229              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
9230                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
9231
9232         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9233             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
9234                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
9235         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
9236                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
9237                                       HOSTCC_MODE_CLRTICK_TXBD);
9238
9239                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
9240                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9241                                        tp->misc_host_ctrl);
9242         }
9243
9244         /* these are limited to 10/100 only */
9245         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
9246              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
9247             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
9248              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
9249              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
9250               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
9251               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
9252             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
9253              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
9254               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F)))
9255                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
9256
9257         err = tg3_phy_probe(tp);
9258         if (err) {
9259                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
9260                        pci_name(tp->pdev), err);
9261                 /* ... but do not return immediately ... */
9262         }
9263
9264         tg3_read_partno(tp);
9265
9266         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
9267                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
9268         } else {
9269                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
9270                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
9271                 else
9272                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
9273         }
9274
9275         /* 5700 {AX,BX} chips have a broken status block link
9276          * change bit implementation, so we must use the
9277          * status register in those cases.
9278          */
9279         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
9280                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
9281         else
9282                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
9283
9284         /* The led_ctrl is set during tg3_phy_probe, here we might
9285          * have to force the link status polling mechanism based
9286          * upon subsystem IDs.
9287          */
9288         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
9289             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
9290                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
9291                                   TG3_FLAG_USE_LINKCHG_REG);
9292         }
9293
9294         /* For all SERDES we poll the MAC status register. */
9295         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9296                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
9297         else
9298                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
9299
9300         /* 5700 BX chips need to have their TX producer index mailboxes
9301          * written twice to workaround a bug.
9302          */
9303         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
9304                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
9305         else
9306                 tp->tg3_flags &= ~TG3_FLAG_TXD_MBOX_HWBUG;
9307
9308         /* It seems all chips can get confused if TX buffers
9309          * straddle the 4GB address boundary in some cases.
9310          */
9311         tp->dev->hard_start_xmit = tg3_start_xmit;
9312
9313         tp->rx_offset = 2;
9314         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
9315             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
9316                 tp->rx_offset = 0;
9317
9318         /* By default, disable wake-on-lan.  User can change this
9319          * using ETHTOOL_SWOL.
9320          */
9321         tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9322
9323         return err;
9324 }
9325
9326 #ifdef CONFIG_SPARC64
9327 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
9328 {
9329         struct net_device *dev = tp->dev;
9330         struct pci_dev *pdev = tp->pdev;
9331         struct pcidev_cookie *pcp = pdev->sysdata;
9332
9333         if (pcp != NULL) {
9334                 int node = pcp->prom_node;
9335
9336                 if (prom_getproplen(node, "local-mac-address") == 6) {
9337                         prom_getproperty(node, "local-mac-address",
9338                                          dev->dev_addr, 6);
9339                         return 0;
9340                 }
9341         }
9342         return -ENODEV;
9343 }
9344
9345 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
9346 {
9347         struct net_device *dev = tp->dev;
9348
9349         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
9350         return 0;
9351 }
9352 #endif
9353
9354 static int __devinit tg3_get_device_address(struct tg3 *tp)
9355 {
9356         struct net_device *dev = tp->dev;
9357         u32 hi, lo, mac_offset;
9358
9359 #ifdef CONFIG_SPARC64
9360         if (!tg3_get_macaddr_sparc(tp))
9361                 return 0;
9362 #endif
9363
9364         mac_offset = 0x7c;
9365         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
9366              !(tp->tg3_flags & TG3_FLG2_SUN_570X)) ||
9367             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
9368                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
9369                         mac_offset = 0xcc;
9370                 if (tg3_nvram_lock(tp))
9371                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
9372                 else
9373                         tg3_nvram_unlock(tp);
9374         }
9375
9376         /* First try to get it from MAC address mailbox. */
9377         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
9378         if ((hi >> 16) == 0x484b) {
9379                 dev->dev_addr[0] = (hi >>  8) & 0xff;
9380                 dev->dev_addr[1] = (hi >>  0) & 0xff;
9381
9382                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
9383                 dev->dev_addr[2] = (lo >> 24) & 0xff;
9384                 dev->dev_addr[3] = (lo >> 16) & 0xff;
9385                 dev->dev_addr[4] = (lo >>  8) & 0xff;
9386                 dev->dev_addr[5] = (lo >>  0) & 0xff;
9387         }
9388         /* Next, try NVRAM. */
9389         else if (!(tp->tg3_flags & TG3_FLG2_SUN_570X) &&
9390                  !tg3_nvram_read(tp, mac_offset + 0, &hi) &&
9391                  !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
9392                 dev->dev_addr[0] = ((hi >> 16) & 0xff);
9393                 dev->dev_addr[1] = ((hi >> 24) & 0xff);
9394                 dev->dev_addr[2] = ((lo >>  0) & 0xff);
9395                 dev->dev_addr[3] = ((lo >>  8) & 0xff);
9396                 dev->dev_addr[4] = ((lo >> 16) & 0xff);
9397                 dev->dev_addr[5] = ((lo >> 24) & 0xff);
9398         }
9399         /* Finally just fetch it out of the MAC control regs. */
9400         else {
9401                 hi = tr32(MAC_ADDR_0_HIGH);
9402                 lo = tr32(MAC_ADDR_0_LOW);
9403
9404                 dev->dev_addr[5] = lo & 0xff;
9405                 dev->dev_addr[4] = (lo >> 8) & 0xff;
9406                 dev->dev_addr[3] = (lo >> 16) & 0xff;
9407                 dev->dev_addr[2] = (lo >> 24) & 0xff;
9408                 dev->dev_addr[1] = hi & 0xff;
9409                 dev->dev_addr[0] = (hi >> 8) & 0xff;
9410         }
9411
9412         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
9413 #ifdef CONFIG_SPARC64
9414                 if (!tg3_get_default_macaddr_sparc(tp))
9415                         return 0;
9416 #endif
9417                 return -EINVAL;
9418         }
9419         return 0;
9420 }
9421
9422 #define BOUNDARY_SINGLE_CACHELINE       1
9423 #define BOUNDARY_MULTI_CACHELINE        2
9424
9425 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
9426 {
9427         int cacheline_size;
9428         u8 byte;
9429         int goal;
9430
9431         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
9432         if (byte == 0)
9433                 cacheline_size = 1024;
9434         else
9435                 cacheline_size = (int) byte * 4;
9436
9437         /* On 5703 and later chips, the boundary bits have no
9438          * effect.
9439          */
9440         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9441             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
9442             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
9443                 goto out;
9444
9445 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
9446         goal = BOUNDARY_MULTI_CACHELINE;
9447 #else
9448 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
9449         goal = BOUNDARY_SINGLE_CACHELINE;
9450 #else
9451         goal = 0;
9452 #endif
9453 #endif
9454
9455         if (!goal)
9456                 goto out;
9457
9458         /* PCI controllers on most RISC systems tend to disconnect
9459          * when a device tries to burst across a cache-line boundary.
9460          * Therefore, letting tg3 do so just wastes PCI bandwidth.
9461          *
9462          * Unfortunately, for PCI-E there are only limited
9463          * write-side controls for this, and thus for reads
9464          * we will still get the disconnects.  We'll also waste
9465          * these PCI cycles for both read and write for chips
9466          * other than 5700 and 5701 which do not implement the
9467          * boundary bits.
9468          */
9469         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
9470             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
9471                 switch (cacheline_size) {
9472                 case 16:
9473                 case 32:
9474                 case 64:
9475                 case 128:
9476                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
9477                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
9478                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
9479                         } else {
9480                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
9481                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
9482                         }
9483                         break;
9484
9485                 case 256:
9486                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
9487                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
9488                         break;
9489
9490                 default:
9491                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
9492                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
9493                         break;
9494                 };
9495         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
9496                 switch (cacheline_size) {
9497                 case 16:
9498                 case 32:
9499                 case 64:
9500                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
9501                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
9502                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
9503                                 break;
9504                         }
9505                         /* fallthrough */
9506                 case 128:
9507                 default:
9508                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
9509                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
9510                         break;
9511                 };
9512         } else {
9513                 switch (cacheline_size) {
9514                 case 16:
9515                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
9516                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
9517                                         DMA_RWCTRL_WRITE_BNDRY_16);
9518                                 break;
9519                         }
9520                         /* fallthrough */
9521                 case 32:
9522                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
9523                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
9524                                         DMA_RWCTRL_WRITE_BNDRY_32);
9525                                 break;
9526                         }
9527                         /* fallthrough */
9528                 case 64:
9529                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
9530                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
9531                                         DMA_RWCTRL_WRITE_BNDRY_64);
9532                                 break;
9533                         }
9534                         /* fallthrough */
9535                 case 128:
9536                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
9537                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
9538                                         DMA_RWCTRL_WRITE_BNDRY_128);
9539                                 break;
9540                         }
9541                         /* fallthrough */
9542                 case 256:
9543                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
9544                                 DMA_RWCTRL_WRITE_BNDRY_256);
9545                         break;
9546                 case 512:
9547                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
9548                                 DMA_RWCTRL_WRITE_BNDRY_512);
9549                         break;
9550                 case 1024:
9551                 default:
9552                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
9553                                 DMA_RWCTRL_WRITE_BNDRY_1024);
9554                         break;
9555                 };
9556         }
9557
9558 out:
9559         return val;
9560 }
9561
9562 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
9563 {
9564         struct tg3_internal_buffer_desc test_desc;
9565         u32 sram_dma_descs;
9566         int i, ret;
9567
9568         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
9569
9570         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
9571         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
9572         tw32(RDMAC_STATUS, 0);
9573         tw32(WDMAC_STATUS, 0);
9574
9575         tw32(BUFMGR_MODE, 0);
9576         tw32(FTQ_RESET, 0);
9577
9578         test_desc.addr_hi = ((u64) buf_dma) >> 32;
9579         test_desc.addr_lo = buf_dma & 0xffffffff;
9580         test_desc.nic_mbuf = 0x00002100;
9581         test_desc.len = size;
9582
9583         /*
9584          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
9585          * the *second* time the tg3 driver was getting loaded after an
9586          * initial scan.
9587          *
9588          * Broadcom tells me:
9589          *   ...the DMA engine is connected to the GRC block and a DMA
9590          *   reset may affect the GRC block in some unpredictable way...
9591          *   The behavior of resets to individual blocks has not been tested.
9592          *
9593          * Broadcom noted the GRC reset will also reset all sub-components.
9594          */
9595         if (to_device) {
9596                 test_desc.cqid_sqid = (13 << 8) | 2;
9597
9598                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
9599                 udelay(40);
9600         } else {
9601                 test_desc.cqid_sqid = (16 << 8) | 7;
9602
9603                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
9604                 udelay(40);
9605         }
9606         test_desc.flags = 0x00000005;
9607
9608         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
9609                 u32 val;
9610
9611                 val = *(((u32 *)&test_desc) + i);
9612                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
9613                                        sram_dma_descs + (i * sizeof(u32)));
9614                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
9615         }
9616         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
9617
9618         if (to_device) {
9619                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
9620         } else {
9621                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
9622         }
9623
9624         ret = -ENODEV;
9625         for (i = 0; i < 40; i++) {
9626                 u32 val;
9627
9628                 if (to_device)
9629                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
9630                 else
9631                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
9632                 if ((val & 0xffff) == sram_dma_descs) {
9633                         ret = 0;
9634                         break;
9635                 }
9636
9637                 udelay(100);
9638         }
9639
9640         return ret;
9641 }
9642
9643 #define TEST_BUFFER_SIZE        0x2000
9644
9645 static int __devinit tg3_test_dma(struct tg3 *tp)
9646 {
9647         dma_addr_t buf_dma;
9648         u32 *buf, saved_dma_rwctrl;
9649         int ret;
9650
9651         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
9652         if (!buf) {
9653                 ret = -ENOMEM;
9654                 goto out_nofree;
9655         }
9656
9657         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
9658                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
9659
9660         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
9661
9662         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
9663                 /* DMA read watermark not used on PCIE */
9664                 tp->dma_rwctrl |= 0x00180000;
9665         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
9666                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
9667                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
9668                         tp->dma_rwctrl |= 0x003f0000;
9669                 else
9670                         tp->dma_rwctrl |= 0x003f000f;
9671         } else {
9672                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
9673                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9674                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
9675
9676                         if (ccval == 0x6 || ccval == 0x7)
9677                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
9678
9679                         /* Set bit 23 to enable PCIX hw bug fix */
9680                         tp->dma_rwctrl |= 0x009f0000;
9681                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
9682                         /* 5780 always in PCIX mode */
9683                         tp->dma_rwctrl |= 0x00144000;
9684                 } else {
9685                         tp->dma_rwctrl |= 0x001b000f;
9686                 }
9687         }
9688
9689         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
9690             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
9691                 tp->dma_rwctrl &= 0xfffffff0;
9692
9693         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9694             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
9695                 /* Remove this if it causes problems for some boards. */
9696                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
9697
9698                 /* On 5700/5701 chips, we need to set this bit.
9699                  * Otherwise the chip will issue cacheline transactions
9700                  * to streamable DMA memory with not all the byte
9701                  * enables turned on.  This is an error on several
9702                  * RISC PCI controllers, in particular sparc64.
9703                  *
9704                  * On 5703/5704 chips, this bit has been reassigned
9705                  * a different meaning.  In particular, it is used
9706                  * on those chips to enable a PCI-X workaround.
9707                  */
9708                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
9709         }
9710
9711         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9712
9713 #if 0
9714         /* Unneeded, already done by tg3_get_invariants.  */
9715         tg3_switch_clocks(tp);
9716 #endif
9717
9718         ret = 0;
9719         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9720             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
9721                 goto out;
9722
9723         /* It is best to perform DMA test with maximum write burst size
9724          * to expose the 5700/5701 write DMA bug.
9725          */
9726         saved_dma_rwctrl = tp->dma_rwctrl;
9727         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
9728         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9729
9730         while (1) {
9731                 u32 *p = buf, i;
9732
9733                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
9734                         p[i] = i;
9735
9736                 /* Send the buffer to the chip. */
9737                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
9738                 if (ret) {
9739                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
9740                         break;
9741                 }
9742
9743 #if 0
9744                 /* validate data reached card RAM correctly. */
9745                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
9746                         u32 val;
9747                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
9748                         if (le32_to_cpu(val) != p[i]) {
9749                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
9750                                 /* ret = -ENODEV here? */
9751                         }
9752                         p[i] = 0;
9753                 }
9754 #endif
9755                 /* Now read it back. */
9756                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
9757                 if (ret) {
9758                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
9759
9760                         break;
9761                 }
9762
9763                 /* Verify it. */
9764                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
9765                         if (p[i] == i)
9766                                 continue;
9767
9768                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
9769                             DMA_RWCTRL_WRITE_BNDRY_16) {
9770                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
9771                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
9772                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9773                                 break;
9774                         } else {
9775                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
9776                                 ret = -ENODEV;
9777                                 goto out;
9778                         }
9779                 }
9780
9781                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
9782                         /* Success. */
9783                         ret = 0;
9784                         break;
9785                 }
9786         }
9787         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
9788             DMA_RWCTRL_WRITE_BNDRY_16) {
9789                 static struct pci_device_id dma_wait_state_chipsets[] = {
9790                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
9791                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
9792                         { },
9793                 };
9794
9795                 /* DMA test passed without adjusting DMA boundary,
9796                  * now look for chipsets that are known to expose the
9797                  * DMA bug without failing the test.
9798                  */
9799                 if (pci_dev_present(dma_wait_state_chipsets)) {
9800                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
9801                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
9802                 }
9803                 else
9804                         /* Safe to use the calculated DMA boundary. */
9805                         tp->dma_rwctrl = saved_dma_rwctrl;
9806
9807                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9808         }
9809
9810 out:
9811         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
9812 out_nofree:
9813         return ret;
9814 }
9815
9816 static void __devinit tg3_init_link_config(struct tg3 *tp)
9817 {
9818         tp->link_config.advertising =
9819                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
9820                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
9821                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
9822                  ADVERTISED_Autoneg | ADVERTISED_MII);
9823         tp->link_config.speed = SPEED_INVALID;
9824         tp->link_config.duplex = DUPLEX_INVALID;
9825         tp->link_config.autoneg = AUTONEG_ENABLE;
9826         netif_carrier_off(tp->dev);
9827         tp->link_config.active_speed = SPEED_INVALID;
9828         tp->link_config.active_duplex = DUPLEX_INVALID;
9829         tp->link_config.phy_is_low_power = 0;
9830         tp->link_config.orig_speed = SPEED_INVALID;
9831         tp->link_config.orig_duplex = DUPLEX_INVALID;
9832         tp->link_config.orig_autoneg = AUTONEG_INVALID;
9833 }
9834
9835 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
9836 {
9837         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9838                 tp->bufmgr_config.mbuf_read_dma_low_water =
9839                         DEFAULT_MB_RDMA_LOW_WATER_5705;
9840                 tp->bufmgr_config.mbuf_mac_rx_low_water =
9841                         DEFAULT_MB_MACRX_LOW_WATER_5705;
9842                 tp->bufmgr_config.mbuf_high_water =
9843                         DEFAULT_MB_HIGH_WATER_5705;
9844
9845                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
9846                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
9847                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
9848                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
9849                 tp->bufmgr_config.mbuf_high_water_jumbo =
9850                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
9851         } else {
9852                 tp->bufmgr_config.mbuf_read_dma_low_water =
9853                         DEFAULT_MB_RDMA_LOW_WATER;
9854                 tp->bufmgr_config.mbuf_mac_rx_low_water =
9855                         DEFAULT_MB_MACRX_LOW_WATER;
9856                 tp->bufmgr_config.mbuf_high_water =
9857                         DEFAULT_MB_HIGH_WATER;
9858
9859                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
9860                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
9861                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
9862                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
9863                 tp->bufmgr_config.mbuf_high_water_jumbo =
9864                         DEFAULT_MB_HIGH_WATER_JUMBO;
9865         }
9866
9867         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
9868         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
9869 }
9870
9871 static char * __devinit tg3_phy_string(struct tg3 *tp)
9872 {
9873         switch (tp->phy_id & PHY_ID_MASK) {
9874         case PHY_ID_BCM5400:    return "5400";
9875         case PHY_ID_BCM5401:    return "5401";
9876         case PHY_ID_BCM5411:    return "5411";
9877         case PHY_ID_BCM5701:    return "5701";
9878         case PHY_ID_BCM5703:    return "5703";
9879         case PHY_ID_BCM5704:    return "5704";
9880         case PHY_ID_BCM5705:    return "5705";
9881         case PHY_ID_BCM5750:    return "5750";
9882         case PHY_ID_BCM5752:    return "5752";
9883         case PHY_ID_BCM5780:    return "5780";
9884         case PHY_ID_BCM8002:    return "8002/serdes";
9885         case 0:                 return "serdes";
9886         default:                return "unknown";
9887         };
9888 }
9889
9890 static struct pci_dev * __devinit tg3_find_5704_peer(struct tg3 *tp)
9891 {
9892         struct pci_dev *peer;
9893         unsigned int func, devnr = tp->pdev->devfn & ~7;
9894
9895         for (func = 0; func < 8; func++) {
9896                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
9897                 if (peer && peer != tp->pdev)
9898                         break;
9899                 pci_dev_put(peer);
9900         }
9901         if (!peer || peer == tp->pdev)
9902                 BUG();
9903
9904         /*
9905          * We don't need to keep the refcount elevated; there's no way
9906          * to remove one half of this device without removing the other
9907          */
9908         pci_dev_put(peer);
9909
9910         return peer;
9911 }
9912
9913 static void __devinit tg3_init_coal(struct tg3 *tp)
9914 {
9915         struct ethtool_coalesce *ec = &tp->coal;
9916
9917         memset(ec, 0, sizeof(*ec));
9918         ec->cmd = ETHTOOL_GCOALESCE;
9919         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
9920         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
9921         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
9922         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
9923         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
9924         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
9925         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
9926         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
9927         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
9928
9929         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
9930                                  HOSTCC_MODE_CLRTICK_TXBD)) {
9931                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
9932                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
9933                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
9934                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
9935         }
9936
9937         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9938                 ec->rx_coalesce_usecs_irq = 0;
9939                 ec->tx_coalesce_usecs_irq = 0;
9940                 ec->stats_block_coalesce_usecs = 0;
9941         }
9942 }
9943
9944 static int __devinit tg3_init_one(struct pci_dev *pdev,
9945                                   const struct pci_device_id *ent)
9946 {
9947         static int tg3_version_printed = 0;
9948         unsigned long tg3reg_base, tg3reg_len;
9949         struct net_device *dev;
9950         struct tg3 *tp;
9951         int i, err, pci_using_dac, pm_cap;
9952
9953         if (tg3_version_printed++ == 0)
9954                 printk(KERN_INFO "%s", version);
9955
9956         err = pci_enable_device(pdev);
9957         if (err) {
9958                 printk(KERN_ERR PFX "Cannot enable PCI device, "
9959                        "aborting.\n");
9960                 return err;
9961         }
9962
9963         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9964                 printk(KERN_ERR PFX "Cannot find proper PCI device "
9965                        "base address, aborting.\n");
9966                 err = -ENODEV;
9967                 goto err_out_disable_pdev;
9968         }
9969
9970         err = pci_request_regions(pdev, DRV_MODULE_NAME);
9971         if (err) {
9972                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
9973                        "aborting.\n");
9974                 goto err_out_disable_pdev;
9975         }
9976
9977         pci_set_master(pdev);
9978
9979         /* Find power-management capability. */
9980         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
9981         if (pm_cap == 0) {
9982                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
9983                        "aborting.\n");
9984                 err = -EIO;
9985                 goto err_out_free_res;
9986         }
9987
9988         /* Configure DMA attributes. */
9989         err = pci_set_dma_mask(pdev, 0xffffffffffffffffULL);
9990         if (!err) {
9991                 pci_using_dac = 1;
9992                 err = pci_set_consistent_dma_mask(pdev, 0xffffffffffffffffULL);
9993                 if (err < 0) {
9994                         printk(KERN_ERR PFX "Unable to obtain 64 bit DMA "
9995                                "for consistent allocations\n");
9996                         goto err_out_free_res;
9997                 }
9998         } else {
9999                 err = pci_set_dma_mask(pdev, 0xffffffffULL);
10000                 if (err) {
10001                         printk(KERN_ERR PFX "No usable DMA configuration, "
10002                                "aborting.\n");
10003                         goto err_out_free_res;
10004                 }
10005                 pci_using_dac = 0;
10006         }
10007
10008         tg3reg_base = pci_resource_start(pdev, 0);
10009         tg3reg_len = pci_resource_len(pdev, 0);
10010
10011         dev = alloc_etherdev(sizeof(*tp));
10012         if (!dev) {
10013                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
10014                 err = -ENOMEM;
10015                 goto err_out_free_res;
10016         }
10017
10018         SET_MODULE_OWNER(dev);
10019         SET_NETDEV_DEV(dev, &pdev->dev);
10020
10021         if (pci_using_dac)
10022                 dev->features |= NETIF_F_HIGHDMA;
10023         dev->features |= NETIF_F_LLTX;
10024 #if TG3_VLAN_TAG_USED
10025         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
10026         dev->vlan_rx_register = tg3_vlan_rx_register;
10027         dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
10028 #endif
10029
10030         tp = netdev_priv(dev);
10031         tp->pdev = pdev;
10032         tp->dev = dev;
10033         tp->pm_cap = pm_cap;
10034         tp->mac_mode = TG3_DEF_MAC_MODE;
10035         tp->rx_mode = TG3_DEF_RX_MODE;
10036         tp->tx_mode = TG3_DEF_TX_MODE;
10037         tp->mi_mode = MAC_MI_MODE_BASE;
10038         if (tg3_debug > 0)
10039                 tp->msg_enable = tg3_debug;
10040         else
10041                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
10042
10043         /* The word/byte swap controls here control register access byte
10044          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
10045          * setting below.
10046          */
10047         tp->misc_host_ctrl =
10048                 MISC_HOST_CTRL_MASK_PCI_INT |
10049                 MISC_HOST_CTRL_WORD_SWAP |
10050                 MISC_HOST_CTRL_INDIR_ACCESS |
10051                 MISC_HOST_CTRL_PCISTATE_RW;
10052
10053         /* The NONFRM (non-frame) byte/word swap controls take effect
10054          * on descriptor entries, anything which isn't packet data.
10055          *
10056          * The StrongARM chips on the board (one for tx, one for rx)
10057          * are running in big-endian mode.
10058          */
10059         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
10060                         GRC_MODE_WSWAP_NONFRM_DATA);
10061 #ifdef __BIG_ENDIAN
10062         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
10063 #endif
10064         spin_lock_init(&tp->lock);
10065         spin_lock_init(&tp->tx_lock);
10066         spin_lock_init(&tp->indirect_lock);
10067         INIT_WORK(&tp->reset_task, tg3_reset_task, tp);
10068
10069         tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
10070         if (tp->regs == 0UL) {
10071                 printk(KERN_ERR PFX "Cannot map device registers, "
10072                        "aborting.\n");
10073                 err = -ENOMEM;
10074                 goto err_out_free_dev;
10075         }
10076
10077         tg3_init_link_config(tp);
10078
10079         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
10080         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
10081         tp->tx_pending = TG3_DEF_TX_RING_PENDING;
10082
10083         dev->open = tg3_open;
10084         dev->stop = tg3_close;
10085         dev->get_stats = tg3_get_stats;
10086         dev->set_multicast_list = tg3_set_rx_mode;
10087         dev->set_mac_address = tg3_set_mac_addr;
10088         dev->do_ioctl = tg3_ioctl;
10089         dev->tx_timeout = tg3_tx_timeout;
10090         dev->poll = tg3_poll;
10091         dev->ethtool_ops = &tg3_ethtool_ops;
10092         dev->weight = 64;
10093         dev->watchdog_timeo = TG3_TX_TIMEOUT;
10094         dev->change_mtu = tg3_change_mtu;
10095         dev->irq = pdev->irq;
10096 #ifdef CONFIG_NET_POLL_CONTROLLER
10097         dev->poll_controller = tg3_poll_controller;
10098 #endif
10099
10100         err = tg3_get_invariants(tp);
10101         if (err) {
10102                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
10103                        "aborting.\n");
10104                 goto err_out_iounmap;
10105         }
10106
10107         tg3_init_bufmgr_config(tp);
10108
10109 #if TG3_TSO_SUPPORT != 0
10110         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
10111                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
10112         }
10113         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10114             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
10115             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
10116             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
10117                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
10118         } else {
10119                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
10120         }
10121
10122         /* TSO is off by default, user can enable using ethtool.  */
10123 #if 0
10124         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)
10125                 dev->features |= NETIF_F_TSO;
10126 #endif
10127
10128 #endif
10129
10130         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
10131             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
10132             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
10133                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
10134                 tp->rx_pending = 63;
10135         }
10136
10137         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
10138                 tp->pdev_peer = tg3_find_5704_peer(tp);
10139
10140         err = tg3_get_device_address(tp);
10141         if (err) {
10142                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
10143                        "aborting.\n");
10144                 goto err_out_iounmap;
10145         }
10146
10147         /*
10148          * Reset chip in case UNDI or EFI driver did not shutdown
10149          * DMA self test will enable WDMAC and we'll see (spurious)
10150          * pending DMA on the PCI bus at that point.
10151          */
10152         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
10153             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
10154                 pci_save_state(tp->pdev);
10155                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
10156                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10157         }
10158
10159         err = tg3_test_dma(tp);
10160         if (err) {
10161                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
10162                 goto err_out_iounmap;
10163         }
10164
10165         /* Tigon3 can do ipv4 only... and some chips have buggy
10166          * checksumming.
10167          */
10168         if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
10169                 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
10170                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10171         } else
10172                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10173
10174         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
10175                 dev->features &= ~NETIF_F_HIGHDMA;
10176
10177         /* flow control autonegotiation is default behavior */
10178         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10179
10180         tg3_init_coal(tp);
10181
10182         err = register_netdev(dev);
10183         if (err) {
10184                 printk(KERN_ERR PFX "Cannot register net device, "
10185                        "aborting.\n");
10186                 goto err_out_iounmap;
10187         }
10188
10189         pci_set_drvdata(pdev, dev);
10190
10191         /* Now that we have fully setup the chip, save away a snapshot
10192          * of the PCI config space.  We need to restore this after
10193          * GRC_MISC_CFG core clock resets and some resume events.
10194          */
10195         pci_save_state(tp->pdev);
10196
10197         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (PCI%s:%s:%s) %sBaseT Ethernet ",
10198                dev->name,
10199                tp->board_part_number,
10200                tp->pci_chip_rev_id,
10201                tg3_phy_string(tp),
10202                ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "X" : ""),
10203                ((tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED) ?
10204                 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "133MHz" : "66MHz") :
10205                 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "100MHz" : "33MHz")),
10206                ((tp->tg3_flags & TG3_FLAG_PCI_32BIT) ? "32-bit" : "64-bit"),
10207                (tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100" : "10/100/1000");
10208
10209         for (i = 0; i < 6; i++)
10210                 printk("%2.2x%c", dev->dev_addr[i],
10211                        i == 5 ? '\n' : ':');
10212
10213         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
10214                "MIirq[%d] ASF[%d] Split[%d] WireSpeed[%d] "
10215                "TSOcap[%d] \n",
10216                dev->name,
10217                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
10218                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
10219                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
10220                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
10221                (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
10222                (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
10223                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
10224         printk(KERN_INFO "%s: dma_rwctrl[%08x]\n",
10225                dev->name, tp->dma_rwctrl);
10226
10227         return 0;
10228
10229 err_out_iounmap:
10230         iounmap(tp->regs);
10231
10232 err_out_free_dev:
10233         free_netdev(dev);
10234
10235 err_out_free_res:
10236         pci_release_regions(pdev);
10237
10238 err_out_disable_pdev:
10239         pci_disable_device(pdev);
10240         pci_set_drvdata(pdev, NULL);
10241         return err;
10242 }
10243
10244 static void __devexit tg3_remove_one(struct pci_dev *pdev)
10245 {
10246         struct net_device *dev = pci_get_drvdata(pdev);
10247
10248         if (dev) {
10249                 struct tg3 *tp = netdev_priv(dev);
10250
10251                 unregister_netdev(dev);
10252                 iounmap(tp->regs);
10253                 free_netdev(dev);
10254                 pci_release_regions(pdev);
10255                 pci_disable_device(pdev);
10256                 pci_set_drvdata(pdev, NULL);
10257         }
10258 }
10259
10260 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
10261 {
10262         struct net_device *dev = pci_get_drvdata(pdev);
10263         struct tg3 *tp = netdev_priv(dev);
10264         int err;
10265
10266         if (!netif_running(dev))
10267                 return 0;
10268
10269         tg3_netif_stop(tp);
10270
10271         del_timer_sync(&tp->timer);
10272
10273         tg3_full_lock(tp, 1);
10274         tg3_disable_ints(tp);
10275         tg3_full_unlock(tp);
10276
10277         netif_device_detach(dev);
10278
10279         tg3_full_lock(tp, 0);
10280         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10281         tg3_full_unlock(tp);
10282
10283         err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
10284         if (err) {
10285                 tg3_full_lock(tp, 0);
10286
10287                 tg3_init_hw(tp);
10288
10289                 tp->timer.expires = jiffies + tp->timer_offset;
10290                 add_timer(&tp->timer);
10291
10292                 netif_device_attach(dev);
10293                 tg3_netif_start(tp);
10294
10295                 tg3_full_unlock(tp);
10296         }
10297
10298         return err;
10299 }
10300
10301 static int tg3_resume(struct pci_dev *pdev)
10302 {
10303         struct net_device *dev = pci_get_drvdata(pdev);
10304         struct tg3 *tp = netdev_priv(dev);
10305         int err;
10306
10307         if (!netif_running(dev))
10308                 return 0;
10309
10310         pci_restore_state(tp->pdev);
10311
10312         err = tg3_set_power_state(tp, 0);
10313         if (err)
10314                 return err;
10315
10316         netif_device_attach(dev);
10317
10318         tg3_full_lock(tp, 0);
10319
10320         tg3_init_hw(tp);
10321
10322         tp->timer.expires = jiffies + tp->timer_offset;
10323         add_timer(&tp->timer);
10324
10325         tg3_netif_start(tp);
10326
10327         tg3_full_unlock(tp);
10328
10329         return 0;
10330 }
10331
10332 static struct pci_driver tg3_driver = {
10333         .name           = DRV_MODULE_NAME,
10334         .id_table       = tg3_pci_tbl,
10335         .probe          = tg3_init_one,
10336         .remove         = __devexit_p(tg3_remove_one),
10337         .suspend        = tg3_suspend,
10338         .resume         = tg3_resume
10339 };
10340
10341 static int __init tg3_init(void)
10342 {
10343         return pci_module_init(&tg3_driver);
10344 }
10345
10346 static void __exit tg3_cleanup(void)
10347 {
10348         pci_unregister_driver(&tg3_driver);
10349 }
10350
10351 module_init(tg3_init);
10352 module_exit(tg3_cleanup);