tg3: Add 5720 ASIC rev
[linux-2.6.git] / drivers / net / tg3.c
1 /*
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  * Copyright (C) 2005-2011 Broadcom Corporation.
8  *
9  * Firmware is:
10  *      Derived from proprietary unpublished source code,
11  *      Copyright (C) 2000-2003 Broadcom Corporation.
12  *
13  *      Permission is hereby granted for the distribution of this firmware
14  *      data in hexadecimal or equivalent format, provided this copyright
15  *      notice is accompanying it.
16  */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/in.h>
28 #include <linux/init.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mdio.h>
36 #include <linux/mii.h>
37 #include <linux/phy.h>
38 #include <linux/brcmphy.h>
39 #include <linux/if_vlan.h>
40 #include <linux/ip.h>
41 #include <linux/tcp.h>
42 #include <linux/workqueue.h>
43 #include <linux/prefetch.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/firmware.h>
46
47 #include <net/checksum.h>
48 #include <net/ip.h>
49
50 #include <asm/system.h>
51 #include <linux/io.h>
52 #include <asm/byteorder.h>
53 #include <linux/uaccess.h>
54
55 #ifdef CONFIG_SPARC
56 #include <asm/idprom.h>
57 #include <asm/prom.h>
58 #endif
59
60 #define BAR_0   0
61 #define BAR_2   2
62
63 #include "tg3.h"
64
65 #define DRV_MODULE_NAME         "tg3"
66 #define TG3_MAJ_NUM                     3
67 #define TG3_MIN_NUM                     117
68 #define DRV_MODULE_VERSION      \
69         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
70 #define DRV_MODULE_RELDATE      "January 25, 2011"
71
72 #define TG3_DEF_MAC_MODE        0
73 #define TG3_DEF_RX_MODE         0
74 #define TG3_DEF_TX_MODE         0
75 #define TG3_DEF_MSG_ENABLE        \
76         (NETIF_MSG_DRV          | \
77          NETIF_MSG_PROBE        | \
78          NETIF_MSG_LINK         | \
79          NETIF_MSG_TIMER        | \
80          NETIF_MSG_IFDOWN       | \
81          NETIF_MSG_IFUP         | \
82          NETIF_MSG_RX_ERR       | \
83          NETIF_MSG_TX_ERR)
84
85 /* length of time before we decide the hardware is borked,
86  * and dev->tx_timeout() should be called to fix the problem
87  */
88 #define TG3_TX_TIMEOUT                  (5 * HZ)
89
90 /* hardware minimum and maximum for a single frame's data payload */
91 #define TG3_MIN_MTU                     60
92 #define TG3_MAX_MTU(tp) \
93         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
94
95 /* These numbers seem to be hard coded in the NIC firmware somehow.
96  * You can't change the ring sizes, but you can change where you place
97  * them in the NIC onboard memory.
98  */
99 #define TG3_RX_STD_RING_SIZE(tp) \
100         ((tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) ? \
101          TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
102 #define TG3_DEF_RX_RING_PENDING         200
103 #define TG3_RX_JMB_RING_SIZE(tp) \
104         ((tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) ? \
105          TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
106 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
107 #define TG3_RSS_INDIR_TBL_SIZE          128
108
109 /* Do not place this n-ring entries value into the tp struct itself,
110  * we really want to expose these constants to GCC so that modulo et
111  * al.  operations are done with shifts and masks instead of with
112  * hw multiply/modulo instructions.  Another solution would be to
113  * replace things like '% foo' with '& (foo - 1)'.
114  */
115
116 #define TG3_TX_RING_SIZE                512
117 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
118
119 #define TG3_RX_STD_RING_BYTES(tp) \
120         (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
121 #define TG3_RX_JMB_RING_BYTES(tp) \
122         (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
123 #define TG3_RX_RCB_RING_BYTES(tp) \
124         (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
125 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
126                                  TG3_TX_RING_SIZE)
127 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
128
129 #define TG3_DMA_BYTE_ENAB               64
130
131 #define TG3_RX_STD_DMA_SZ               1536
132 #define TG3_RX_JMB_DMA_SZ               9046
133
134 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
135
136 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
137 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
138
139 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
140         (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
141
142 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
143         (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
144
145 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
146  * that are at least dword aligned when used in PCIX mode.  The driver
147  * works around this bug by double copying the packet.  This workaround
148  * is built into the normal double copy length check for efficiency.
149  *
150  * However, the double copy is only necessary on those architectures
151  * where unaligned memory accesses are inefficient.  For those architectures
152  * where unaligned memory accesses incur little penalty, we can reintegrate
153  * the 5701 in the normal rx path.  Doing so saves a device structure
154  * dereference by hardcoding the double copy threshold in place.
155  */
156 #define TG3_RX_COPY_THRESHOLD           256
157 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
158         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
159 #else
160         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
161 #endif
162
163 /* minimum number of free TX descriptors required to wake up TX process */
164 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
165
166 #define TG3_RAW_IP_ALIGN 2
167
168 /* number of ETHTOOL_GSTATS u64's */
169 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
170
171 #define TG3_NUM_TEST            6
172
173 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
174
175 #define FIRMWARE_TG3            "tigon/tg3.bin"
176 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
177 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
178
179 static char version[] __devinitdata =
180         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
181
182 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
183 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
184 MODULE_LICENSE("GPL");
185 MODULE_VERSION(DRV_MODULE_VERSION);
186 MODULE_FIRMWARE(FIRMWARE_TG3);
187 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
188 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
189
190 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
191 module_param(tg3_debug, int, 0);
192 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
193
194 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
267         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
268         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
269         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
270         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
271         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
272         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
273         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
274         {}
275 };
276
277 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
278
279 static const struct {
280         const char string[ETH_GSTRING_LEN];
281 } ethtool_stats_keys[TG3_NUM_STATS] = {
282         { "rx_octets" },
283         { "rx_fragments" },
284         { "rx_ucast_packets" },
285         { "rx_mcast_packets" },
286         { "rx_bcast_packets" },
287         { "rx_fcs_errors" },
288         { "rx_align_errors" },
289         { "rx_xon_pause_rcvd" },
290         { "rx_xoff_pause_rcvd" },
291         { "rx_mac_ctrl_rcvd" },
292         { "rx_xoff_entered" },
293         { "rx_frame_too_long_errors" },
294         { "rx_jabbers" },
295         { "rx_undersize_packets" },
296         { "rx_in_length_errors" },
297         { "rx_out_length_errors" },
298         { "rx_64_or_less_octet_packets" },
299         { "rx_65_to_127_octet_packets" },
300         { "rx_128_to_255_octet_packets" },
301         { "rx_256_to_511_octet_packets" },
302         { "rx_512_to_1023_octet_packets" },
303         { "rx_1024_to_1522_octet_packets" },
304         { "rx_1523_to_2047_octet_packets" },
305         { "rx_2048_to_4095_octet_packets" },
306         { "rx_4096_to_8191_octet_packets" },
307         { "rx_8192_to_9022_octet_packets" },
308
309         { "tx_octets" },
310         { "tx_collisions" },
311
312         { "tx_xon_sent" },
313         { "tx_xoff_sent" },
314         { "tx_flow_control" },
315         { "tx_mac_errors" },
316         { "tx_single_collisions" },
317         { "tx_mult_collisions" },
318         { "tx_deferred" },
319         { "tx_excessive_collisions" },
320         { "tx_late_collisions" },
321         { "tx_collide_2times" },
322         { "tx_collide_3times" },
323         { "tx_collide_4times" },
324         { "tx_collide_5times" },
325         { "tx_collide_6times" },
326         { "tx_collide_7times" },
327         { "tx_collide_8times" },
328         { "tx_collide_9times" },
329         { "tx_collide_10times" },
330         { "tx_collide_11times" },
331         { "tx_collide_12times" },
332         { "tx_collide_13times" },
333         { "tx_collide_14times" },
334         { "tx_collide_15times" },
335         { "tx_ucast_packets" },
336         { "tx_mcast_packets" },
337         { "tx_bcast_packets" },
338         { "tx_carrier_sense_errors" },
339         { "tx_discards" },
340         { "tx_errors" },
341
342         { "dma_writeq_full" },
343         { "dma_write_prioq_full" },
344         { "rxbds_empty" },
345         { "rx_discards" },
346         { "rx_errors" },
347         { "rx_threshold_hit" },
348
349         { "dma_readq_full" },
350         { "dma_read_prioq_full" },
351         { "tx_comp_queue_full" },
352
353         { "ring_set_send_prod_index" },
354         { "ring_status_update" },
355         { "nic_irqs" },
356         { "nic_avoided_irqs" },
357         { "nic_tx_threshold_hit" }
358 };
359
360 static const struct {
361         const char string[ETH_GSTRING_LEN];
362 } ethtool_test_keys[TG3_NUM_TEST] = {
363         { "nvram test     (online) " },
364         { "link test      (online) " },
365         { "register test  (offline)" },
366         { "memory test    (offline)" },
367         { "loopback test  (offline)" },
368         { "interrupt test (offline)" },
369 };
370
371 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
372 {
373         writel(val, tp->regs + off);
374 }
375
376 static u32 tg3_read32(struct tg3 *tp, u32 off)
377 {
378         return readl(tp->regs + off);
379 }
380
381 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
382 {
383         writel(val, tp->aperegs + off);
384 }
385
386 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
387 {
388         return readl(tp->aperegs + off);
389 }
390
391 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
392 {
393         unsigned long flags;
394
395         spin_lock_irqsave(&tp->indirect_lock, flags);
396         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
397         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
398         spin_unlock_irqrestore(&tp->indirect_lock, flags);
399 }
400
401 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
402 {
403         writel(val, tp->regs + off);
404         readl(tp->regs + off);
405 }
406
407 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
408 {
409         unsigned long flags;
410         u32 val;
411
412         spin_lock_irqsave(&tp->indirect_lock, flags);
413         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
414         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
415         spin_unlock_irqrestore(&tp->indirect_lock, flags);
416         return val;
417 }
418
419 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
420 {
421         unsigned long flags;
422
423         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
424                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
425                                        TG3_64BIT_REG_LOW, val);
426                 return;
427         }
428         if (off == TG3_RX_STD_PROD_IDX_REG) {
429                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
430                                        TG3_64BIT_REG_LOW, val);
431                 return;
432         }
433
434         spin_lock_irqsave(&tp->indirect_lock, flags);
435         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
436         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
437         spin_unlock_irqrestore(&tp->indirect_lock, flags);
438
439         /* In indirect mode when disabling interrupts, we also need
440          * to clear the interrupt bit in the GRC local ctrl register.
441          */
442         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
443             (val == 0x1)) {
444                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
445                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
446         }
447 }
448
449 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
450 {
451         unsigned long flags;
452         u32 val;
453
454         spin_lock_irqsave(&tp->indirect_lock, flags);
455         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
456         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
457         spin_unlock_irqrestore(&tp->indirect_lock, flags);
458         return val;
459 }
460
461 /* usec_wait specifies the wait time in usec when writing to certain registers
462  * where it is unsafe to read back the register without some delay.
463  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
464  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
465  */
466 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
467 {
468         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
469             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
470                 /* Non-posted methods */
471                 tp->write32(tp, off, val);
472         else {
473                 /* Posted method */
474                 tg3_write32(tp, off, val);
475                 if (usec_wait)
476                         udelay(usec_wait);
477                 tp->read32(tp, off);
478         }
479         /* Wait again after the read for the posted method to guarantee that
480          * the wait time is met.
481          */
482         if (usec_wait)
483                 udelay(usec_wait);
484 }
485
486 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
487 {
488         tp->write32_mbox(tp, off, val);
489         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
490             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
491                 tp->read32_mbox(tp, off);
492 }
493
494 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
495 {
496         void __iomem *mbox = tp->regs + off;
497         writel(val, mbox);
498         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
499                 writel(val, mbox);
500         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
501                 readl(mbox);
502 }
503
504 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
505 {
506         return readl(tp->regs + off + GRCMBOX_BASE);
507 }
508
509 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
510 {
511         writel(val, tp->regs + off + GRCMBOX_BASE);
512 }
513
514 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
515 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
516 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
517 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
518 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
519
520 #define tw32(reg, val)                  tp->write32(tp, reg, val)
521 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
522 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
523 #define tr32(reg)                       tp->read32(tp, reg)
524
525 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
526 {
527         unsigned long flags;
528
529         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
530             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
531                 return;
532
533         spin_lock_irqsave(&tp->indirect_lock, flags);
534         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
535                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
536                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
537
538                 /* Always leave this as zero. */
539                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
540         } else {
541                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
542                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
543
544                 /* Always leave this as zero. */
545                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
546         }
547         spin_unlock_irqrestore(&tp->indirect_lock, flags);
548 }
549
550 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
551 {
552         unsigned long flags;
553
554         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
555             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
556                 *val = 0;
557                 return;
558         }
559
560         spin_lock_irqsave(&tp->indirect_lock, flags);
561         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
562                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
563                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
564
565                 /* Always leave this as zero. */
566                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
567         } else {
568                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
569                 *val = tr32(TG3PCI_MEM_WIN_DATA);
570
571                 /* Always leave this as zero. */
572                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
573         }
574         spin_unlock_irqrestore(&tp->indirect_lock, flags);
575 }
576
577 static void tg3_ape_lock_init(struct tg3 *tp)
578 {
579         int i;
580         u32 regbase;
581
582         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
583                 regbase = TG3_APE_LOCK_GRANT;
584         else
585                 regbase = TG3_APE_PER_LOCK_GRANT;
586
587         /* Make sure the driver hasn't any stale locks. */
588         for (i = 0; i < 8; i++)
589                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
590 }
591
592 static int tg3_ape_lock(struct tg3 *tp, int locknum)
593 {
594         int i, off;
595         int ret = 0;
596         u32 status, req, gnt;
597
598         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
599                 return 0;
600
601         switch (locknum) {
602         case TG3_APE_LOCK_GRC:
603         case TG3_APE_LOCK_MEM:
604                 break;
605         default:
606                 return -EINVAL;
607         }
608
609         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
610                 req = TG3_APE_LOCK_REQ;
611                 gnt = TG3_APE_LOCK_GRANT;
612         } else {
613                 req = TG3_APE_PER_LOCK_REQ;
614                 gnt = TG3_APE_PER_LOCK_GRANT;
615         }
616
617         off = 4 * locknum;
618
619         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
620
621         /* Wait for up to 1 millisecond to acquire lock. */
622         for (i = 0; i < 100; i++) {
623                 status = tg3_ape_read32(tp, gnt + off);
624                 if (status == APE_LOCK_GRANT_DRIVER)
625                         break;
626                 udelay(10);
627         }
628
629         if (status != APE_LOCK_GRANT_DRIVER) {
630                 /* Revoke the lock request. */
631                 tg3_ape_write32(tp, gnt + off,
632                                 APE_LOCK_GRANT_DRIVER);
633
634                 ret = -EBUSY;
635         }
636
637         return ret;
638 }
639
640 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
641 {
642         u32 gnt;
643
644         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
645                 return;
646
647         switch (locknum) {
648         case TG3_APE_LOCK_GRC:
649         case TG3_APE_LOCK_MEM:
650                 break;
651         default:
652                 return;
653         }
654
655         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
656                 gnt = TG3_APE_LOCK_GRANT;
657         else
658                 gnt = TG3_APE_PER_LOCK_GRANT;
659
660         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
661 }
662
663 static void tg3_disable_ints(struct tg3 *tp)
664 {
665         int i;
666
667         tw32(TG3PCI_MISC_HOST_CTRL,
668              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
669         for (i = 0; i < tp->irq_max; i++)
670                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
671 }
672
673 static void tg3_enable_ints(struct tg3 *tp)
674 {
675         int i;
676
677         tp->irq_sync = 0;
678         wmb();
679
680         tw32(TG3PCI_MISC_HOST_CTRL,
681              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
682
683         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
684         for (i = 0; i < tp->irq_cnt; i++) {
685                 struct tg3_napi *tnapi = &tp->napi[i];
686
687                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
688                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
689                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
690
691                 tp->coal_now |= tnapi->coal_now;
692         }
693
694         /* Force an initial interrupt */
695         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
696             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
697                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
698         else
699                 tw32(HOSTCC_MODE, tp->coal_now);
700
701         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
702 }
703
704 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
705 {
706         struct tg3 *tp = tnapi->tp;
707         struct tg3_hw_status *sblk = tnapi->hw_status;
708         unsigned int work_exists = 0;
709
710         /* check for phy events */
711         if (!(tp->tg3_flags &
712               (TG3_FLAG_USE_LINKCHG_REG |
713                TG3_FLAG_POLL_SERDES))) {
714                 if (sblk->status & SD_STATUS_LINK_CHG)
715                         work_exists = 1;
716         }
717         /* check for RX/TX work to do */
718         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
719             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
720                 work_exists = 1;
721
722         return work_exists;
723 }
724
725 /* tg3_int_reenable
726  *  similar to tg3_enable_ints, but it accurately determines whether there
727  *  is new work pending and can return without flushing the PIO write
728  *  which reenables interrupts
729  */
730 static void tg3_int_reenable(struct tg3_napi *tnapi)
731 {
732         struct tg3 *tp = tnapi->tp;
733
734         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
735         mmiowb();
736
737         /* When doing tagged status, this work check is unnecessary.
738          * The last_tag we write above tells the chip which piece of
739          * work we've completed.
740          */
741         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
742             tg3_has_work(tnapi))
743                 tw32(HOSTCC_MODE, tp->coalesce_mode |
744                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
745 }
746
747 static void tg3_switch_clocks(struct tg3 *tp)
748 {
749         u32 clock_ctrl;
750         u32 orig_clock_ctrl;
751
752         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
753             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
754                 return;
755
756         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
757
758         orig_clock_ctrl = clock_ctrl;
759         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
760                        CLOCK_CTRL_CLKRUN_OENABLE |
761                        0x1f);
762         tp->pci_clock_ctrl = clock_ctrl;
763
764         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
765                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
766                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
767                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
768                 }
769         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
770                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
771                             clock_ctrl |
772                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
773                             40);
774                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
775                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
776                             40);
777         }
778         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
779 }
780
781 #define PHY_BUSY_LOOPS  5000
782
783 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
784 {
785         u32 frame_val;
786         unsigned int loops;
787         int ret;
788
789         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
790                 tw32_f(MAC_MI_MODE,
791                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
792                 udelay(80);
793         }
794
795         *val = 0x0;
796
797         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
798                       MI_COM_PHY_ADDR_MASK);
799         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
800                       MI_COM_REG_ADDR_MASK);
801         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
802
803         tw32_f(MAC_MI_COM, frame_val);
804
805         loops = PHY_BUSY_LOOPS;
806         while (loops != 0) {
807                 udelay(10);
808                 frame_val = tr32(MAC_MI_COM);
809
810                 if ((frame_val & MI_COM_BUSY) == 0) {
811                         udelay(5);
812                         frame_val = tr32(MAC_MI_COM);
813                         break;
814                 }
815                 loops -= 1;
816         }
817
818         ret = -EBUSY;
819         if (loops != 0) {
820                 *val = frame_val & MI_COM_DATA_MASK;
821                 ret = 0;
822         }
823
824         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
825                 tw32_f(MAC_MI_MODE, tp->mi_mode);
826                 udelay(80);
827         }
828
829         return ret;
830 }
831
832 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
833 {
834         u32 frame_val;
835         unsigned int loops;
836         int ret;
837
838         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
839             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
840                 return 0;
841
842         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
843                 tw32_f(MAC_MI_MODE,
844                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
845                 udelay(80);
846         }
847
848         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
849                       MI_COM_PHY_ADDR_MASK);
850         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
851                       MI_COM_REG_ADDR_MASK);
852         frame_val |= (val & MI_COM_DATA_MASK);
853         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
854
855         tw32_f(MAC_MI_COM, frame_val);
856
857         loops = PHY_BUSY_LOOPS;
858         while (loops != 0) {
859                 udelay(10);
860                 frame_val = tr32(MAC_MI_COM);
861                 if ((frame_val & MI_COM_BUSY) == 0) {
862                         udelay(5);
863                         frame_val = tr32(MAC_MI_COM);
864                         break;
865                 }
866                 loops -= 1;
867         }
868
869         ret = -EBUSY;
870         if (loops != 0)
871                 ret = 0;
872
873         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
874                 tw32_f(MAC_MI_MODE, tp->mi_mode);
875                 udelay(80);
876         }
877
878         return ret;
879 }
880
881 static int tg3_bmcr_reset(struct tg3 *tp)
882 {
883         u32 phy_control;
884         int limit, err;
885
886         /* OK, reset it, and poll the BMCR_RESET bit until it
887          * clears or we time out.
888          */
889         phy_control = BMCR_RESET;
890         err = tg3_writephy(tp, MII_BMCR, phy_control);
891         if (err != 0)
892                 return -EBUSY;
893
894         limit = 5000;
895         while (limit--) {
896                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
897                 if (err != 0)
898                         return -EBUSY;
899
900                 if ((phy_control & BMCR_RESET) == 0) {
901                         udelay(40);
902                         break;
903                 }
904                 udelay(10);
905         }
906         if (limit < 0)
907                 return -EBUSY;
908
909         return 0;
910 }
911
912 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
913 {
914         struct tg3 *tp = bp->priv;
915         u32 val;
916
917         spin_lock_bh(&tp->lock);
918
919         if (tg3_readphy(tp, reg, &val))
920                 val = -EIO;
921
922         spin_unlock_bh(&tp->lock);
923
924         return val;
925 }
926
927 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
928 {
929         struct tg3 *tp = bp->priv;
930         u32 ret = 0;
931
932         spin_lock_bh(&tp->lock);
933
934         if (tg3_writephy(tp, reg, val))
935                 ret = -EIO;
936
937         spin_unlock_bh(&tp->lock);
938
939         return ret;
940 }
941
942 static int tg3_mdio_reset(struct mii_bus *bp)
943 {
944         return 0;
945 }
946
947 static void tg3_mdio_config_5785(struct tg3 *tp)
948 {
949         u32 val;
950         struct phy_device *phydev;
951
952         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
953         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
954         case PHY_ID_BCM50610:
955         case PHY_ID_BCM50610M:
956                 val = MAC_PHYCFG2_50610_LED_MODES;
957                 break;
958         case PHY_ID_BCMAC131:
959                 val = MAC_PHYCFG2_AC131_LED_MODES;
960                 break;
961         case PHY_ID_RTL8211C:
962                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
963                 break;
964         case PHY_ID_RTL8201E:
965                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
966                 break;
967         default:
968                 return;
969         }
970
971         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
972                 tw32(MAC_PHYCFG2, val);
973
974                 val = tr32(MAC_PHYCFG1);
975                 val &= ~(MAC_PHYCFG1_RGMII_INT |
976                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
977                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
978                 tw32(MAC_PHYCFG1, val);
979
980                 return;
981         }
982
983         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
984                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
985                        MAC_PHYCFG2_FMODE_MASK_MASK |
986                        MAC_PHYCFG2_GMODE_MASK_MASK |
987                        MAC_PHYCFG2_ACT_MASK_MASK   |
988                        MAC_PHYCFG2_QUAL_MASK_MASK |
989                        MAC_PHYCFG2_INBAND_ENABLE;
990
991         tw32(MAC_PHYCFG2, val);
992
993         val = tr32(MAC_PHYCFG1);
994         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
995                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
996         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
997                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
998                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
999                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1000                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1001         }
1002         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1003                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1004         tw32(MAC_PHYCFG1, val);
1005
1006         val = tr32(MAC_EXT_RGMII_MODE);
1007         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1008                  MAC_RGMII_MODE_RX_QUALITY |
1009                  MAC_RGMII_MODE_RX_ACTIVITY |
1010                  MAC_RGMII_MODE_RX_ENG_DET |
1011                  MAC_RGMII_MODE_TX_ENABLE |
1012                  MAC_RGMII_MODE_TX_LOWPWR |
1013                  MAC_RGMII_MODE_TX_RESET);
1014         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1015                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1016                         val |= MAC_RGMII_MODE_RX_INT_B |
1017                                MAC_RGMII_MODE_RX_QUALITY |
1018                                MAC_RGMII_MODE_RX_ACTIVITY |
1019                                MAC_RGMII_MODE_RX_ENG_DET;
1020                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1021                         val |= MAC_RGMII_MODE_TX_ENABLE |
1022                                MAC_RGMII_MODE_TX_LOWPWR |
1023                                MAC_RGMII_MODE_TX_RESET;
1024         }
1025         tw32(MAC_EXT_RGMII_MODE, val);
1026 }
1027
1028 static void tg3_mdio_start(struct tg3 *tp)
1029 {
1030         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1031         tw32_f(MAC_MI_MODE, tp->mi_mode);
1032         udelay(80);
1033
1034         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1035             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1036                 tg3_mdio_config_5785(tp);
1037 }
1038
1039 static int tg3_mdio_init(struct tg3 *tp)
1040 {
1041         int i;
1042         u32 reg;
1043         struct phy_device *phydev;
1044
1045         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
1046                 u32 is_serdes;
1047
1048                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1049
1050                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1051                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1052                 else
1053                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1054                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1055                 if (is_serdes)
1056                         tp->phy_addr += 7;
1057         } else
1058                 tp->phy_addr = TG3_PHY_MII_ADDR;
1059
1060         tg3_mdio_start(tp);
1061
1062         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1063             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1064                 return 0;
1065
1066         tp->mdio_bus = mdiobus_alloc();
1067         if (tp->mdio_bus == NULL)
1068                 return -ENOMEM;
1069
1070         tp->mdio_bus->name     = "tg3 mdio bus";
1071         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1072                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1073         tp->mdio_bus->priv     = tp;
1074         tp->mdio_bus->parent   = &tp->pdev->dev;
1075         tp->mdio_bus->read     = &tg3_mdio_read;
1076         tp->mdio_bus->write    = &tg3_mdio_write;
1077         tp->mdio_bus->reset    = &tg3_mdio_reset;
1078         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1079         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1080
1081         for (i = 0; i < PHY_MAX_ADDR; i++)
1082                 tp->mdio_bus->irq[i] = PHY_POLL;
1083
1084         /* The bus registration will look for all the PHYs on the mdio bus.
1085          * Unfortunately, it does not ensure the PHY is powered up before
1086          * accessing the PHY ID registers.  A chip reset is the
1087          * quickest way to bring the device back to an operational state..
1088          */
1089         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1090                 tg3_bmcr_reset(tp);
1091
1092         i = mdiobus_register(tp->mdio_bus);
1093         if (i) {
1094                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1095                 mdiobus_free(tp->mdio_bus);
1096                 return i;
1097         }
1098
1099         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1100
1101         if (!phydev || !phydev->drv) {
1102                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1103                 mdiobus_unregister(tp->mdio_bus);
1104                 mdiobus_free(tp->mdio_bus);
1105                 return -ENODEV;
1106         }
1107
1108         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1109         case PHY_ID_BCM57780:
1110                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1111                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1112                 break;
1113         case PHY_ID_BCM50610:
1114         case PHY_ID_BCM50610M:
1115                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1116                                      PHY_BRCM_RX_REFCLK_UNUSED |
1117                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1118                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1119                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1120                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1121                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1122                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1123                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1124                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1125                 /* fallthru */
1126         case PHY_ID_RTL8211C:
1127                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1128                 break;
1129         case PHY_ID_RTL8201E:
1130         case PHY_ID_BCMAC131:
1131                 phydev->interface = PHY_INTERFACE_MODE_MII;
1132                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1133                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1134                 break;
1135         }
1136
1137         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1138
1139         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1140                 tg3_mdio_config_5785(tp);
1141
1142         return 0;
1143 }
1144
1145 static void tg3_mdio_fini(struct tg3 *tp)
1146 {
1147         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1148                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1149                 mdiobus_unregister(tp->mdio_bus);
1150                 mdiobus_free(tp->mdio_bus);
1151         }
1152 }
1153
1154 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1155 {
1156         int err;
1157
1158         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1159         if (err)
1160                 goto done;
1161
1162         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1163         if (err)
1164                 goto done;
1165
1166         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1167                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1168         if (err)
1169                 goto done;
1170
1171         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1172
1173 done:
1174         return err;
1175 }
1176
1177 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1178 {
1179         int err;
1180
1181         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1182         if (err)
1183                 goto done;
1184
1185         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1186         if (err)
1187                 goto done;
1188
1189         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1190                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1191         if (err)
1192                 goto done;
1193
1194         err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1195
1196 done:
1197         return err;
1198 }
1199
1200 /* tp->lock is held. */
1201 static inline void tg3_generate_fw_event(struct tg3 *tp)
1202 {
1203         u32 val;
1204
1205         val = tr32(GRC_RX_CPU_EVENT);
1206         val |= GRC_RX_CPU_DRIVER_EVENT;
1207         tw32_f(GRC_RX_CPU_EVENT, val);
1208
1209         tp->last_event_jiffies = jiffies;
1210 }
1211
1212 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1213
1214 /* tp->lock is held. */
1215 static void tg3_wait_for_event_ack(struct tg3 *tp)
1216 {
1217         int i;
1218         unsigned int delay_cnt;
1219         long time_remain;
1220
1221         /* If enough time has passed, no wait is necessary. */
1222         time_remain = (long)(tp->last_event_jiffies + 1 +
1223                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1224                       (long)jiffies;
1225         if (time_remain < 0)
1226                 return;
1227
1228         /* Check if we can shorten the wait time. */
1229         delay_cnt = jiffies_to_usecs(time_remain);
1230         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1231                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1232         delay_cnt = (delay_cnt >> 3) + 1;
1233
1234         for (i = 0; i < delay_cnt; i++) {
1235                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1236                         break;
1237                 udelay(8);
1238         }
1239 }
1240
1241 /* tp->lock is held. */
1242 static void tg3_ump_link_report(struct tg3 *tp)
1243 {
1244         u32 reg;
1245         u32 val;
1246
1247         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1248             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1249                 return;
1250
1251         tg3_wait_for_event_ack(tp);
1252
1253         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1254
1255         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1256
1257         val = 0;
1258         if (!tg3_readphy(tp, MII_BMCR, &reg))
1259                 val = reg << 16;
1260         if (!tg3_readphy(tp, MII_BMSR, &reg))
1261                 val |= (reg & 0xffff);
1262         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1263
1264         val = 0;
1265         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1266                 val = reg << 16;
1267         if (!tg3_readphy(tp, MII_LPA, &reg))
1268                 val |= (reg & 0xffff);
1269         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1270
1271         val = 0;
1272         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1273                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1274                         val = reg << 16;
1275                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1276                         val |= (reg & 0xffff);
1277         }
1278         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1279
1280         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1281                 val = reg << 16;
1282         else
1283                 val = 0;
1284         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1285
1286         tg3_generate_fw_event(tp);
1287 }
1288
1289 static void tg3_link_report(struct tg3 *tp)
1290 {
1291         if (!netif_carrier_ok(tp->dev)) {
1292                 netif_info(tp, link, tp->dev, "Link is down\n");
1293                 tg3_ump_link_report(tp);
1294         } else if (netif_msg_link(tp)) {
1295                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1296                             (tp->link_config.active_speed == SPEED_1000 ?
1297                              1000 :
1298                              (tp->link_config.active_speed == SPEED_100 ?
1299                               100 : 10)),
1300                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1301                              "full" : "half"));
1302
1303                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1304                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1305                             "on" : "off",
1306                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1307                             "on" : "off");
1308                 tg3_ump_link_report(tp);
1309         }
1310 }
1311
1312 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1313 {
1314         u16 miireg;
1315
1316         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1317                 miireg = ADVERTISE_PAUSE_CAP;
1318         else if (flow_ctrl & FLOW_CTRL_TX)
1319                 miireg = ADVERTISE_PAUSE_ASYM;
1320         else if (flow_ctrl & FLOW_CTRL_RX)
1321                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1322         else
1323                 miireg = 0;
1324
1325         return miireg;
1326 }
1327
1328 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1329 {
1330         u16 miireg;
1331
1332         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1333                 miireg = ADVERTISE_1000XPAUSE;
1334         else if (flow_ctrl & FLOW_CTRL_TX)
1335                 miireg = ADVERTISE_1000XPSE_ASYM;
1336         else if (flow_ctrl & FLOW_CTRL_RX)
1337                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1338         else
1339                 miireg = 0;
1340
1341         return miireg;
1342 }
1343
1344 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1345 {
1346         u8 cap = 0;
1347
1348         if (lcladv & ADVERTISE_1000XPAUSE) {
1349                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1350                         if (rmtadv & LPA_1000XPAUSE)
1351                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1352                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1353                                 cap = FLOW_CTRL_RX;
1354                 } else {
1355                         if (rmtadv & LPA_1000XPAUSE)
1356                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1357                 }
1358         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1359                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1360                         cap = FLOW_CTRL_TX;
1361         }
1362
1363         return cap;
1364 }
1365
1366 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1367 {
1368         u8 autoneg;
1369         u8 flowctrl = 0;
1370         u32 old_rx_mode = tp->rx_mode;
1371         u32 old_tx_mode = tp->tx_mode;
1372
1373         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1374                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1375         else
1376                 autoneg = tp->link_config.autoneg;
1377
1378         if (autoneg == AUTONEG_ENABLE &&
1379             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1380                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1381                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1382                 else
1383                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1384         } else
1385                 flowctrl = tp->link_config.flowctrl;
1386
1387         tp->link_config.active_flowctrl = flowctrl;
1388
1389         if (flowctrl & FLOW_CTRL_RX)
1390                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1391         else
1392                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1393
1394         if (old_rx_mode != tp->rx_mode)
1395                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1396
1397         if (flowctrl & FLOW_CTRL_TX)
1398                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1399         else
1400                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1401
1402         if (old_tx_mode != tp->tx_mode)
1403                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1404 }
1405
1406 static void tg3_adjust_link(struct net_device *dev)
1407 {
1408         u8 oldflowctrl, linkmesg = 0;
1409         u32 mac_mode, lcl_adv, rmt_adv;
1410         struct tg3 *tp = netdev_priv(dev);
1411         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1412
1413         spin_lock_bh(&tp->lock);
1414
1415         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1416                                     MAC_MODE_HALF_DUPLEX);
1417
1418         oldflowctrl = tp->link_config.active_flowctrl;
1419
1420         if (phydev->link) {
1421                 lcl_adv = 0;
1422                 rmt_adv = 0;
1423
1424                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1425                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1426                 else if (phydev->speed == SPEED_1000 ||
1427                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1428                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1429                 else
1430                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1431
1432                 if (phydev->duplex == DUPLEX_HALF)
1433                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1434                 else {
1435                         lcl_adv = tg3_advert_flowctrl_1000T(
1436                                   tp->link_config.flowctrl);
1437
1438                         if (phydev->pause)
1439                                 rmt_adv = LPA_PAUSE_CAP;
1440                         if (phydev->asym_pause)
1441                                 rmt_adv |= LPA_PAUSE_ASYM;
1442                 }
1443
1444                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1445         } else
1446                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1447
1448         if (mac_mode != tp->mac_mode) {
1449                 tp->mac_mode = mac_mode;
1450                 tw32_f(MAC_MODE, tp->mac_mode);
1451                 udelay(40);
1452         }
1453
1454         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1455                 if (phydev->speed == SPEED_10)
1456                         tw32(MAC_MI_STAT,
1457                              MAC_MI_STAT_10MBPS_MODE |
1458                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1459                 else
1460                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1461         }
1462
1463         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1464                 tw32(MAC_TX_LENGTHS,
1465                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1466                       (6 << TX_LENGTHS_IPG_SHIFT) |
1467                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1468         else
1469                 tw32(MAC_TX_LENGTHS,
1470                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1471                       (6 << TX_LENGTHS_IPG_SHIFT) |
1472                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1473
1474         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1475             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1476             phydev->speed != tp->link_config.active_speed ||
1477             phydev->duplex != tp->link_config.active_duplex ||
1478             oldflowctrl != tp->link_config.active_flowctrl)
1479                 linkmesg = 1;
1480
1481         tp->link_config.active_speed = phydev->speed;
1482         tp->link_config.active_duplex = phydev->duplex;
1483
1484         spin_unlock_bh(&tp->lock);
1485
1486         if (linkmesg)
1487                 tg3_link_report(tp);
1488 }
1489
1490 static int tg3_phy_init(struct tg3 *tp)
1491 {
1492         struct phy_device *phydev;
1493
1494         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1495                 return 0;
1496
1497         /* Bring the PHY back to a known state. */
1498         tg3_bmcr_reset(tp);
1499
1500         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1501
1502         /* Attach the MAC to the PHY. */
1503         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1504                              phydev->dev_flags, phydev->interface);
1505         if (IS_ERR(phydev)) {
1506                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1507                 return PTR_ERR(phydev);
1508         }
1509
1510         /* Mask with MAC supported features. */
1511         switch (phydev->interface) {
1512         case PHY_INTERFACE_MODE_GMII:
1513         case PHY_INTERFACE_MODE_RGMII:
1514                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1515                         phydev->supported &= (PHY_GBIT_FEATURES |
1516                                               SUPPORTED_Pause |
1517                                               SUPPORTED_Asym_Pause);
1518                         break;
1519                 }
1520                 /* fallthru */
1521         case PHY_INTERFACE_MODE_MII:
1522                 phydev->supported &= (PHY_BASIC_FEATURES |
1523                                       SUPPORTED_Pause |
1524                                       SUPPORTED_Asym_Pause);
1525                 break;
1526         default:
1527                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1528                 return -EINVAL;
1529         }
1530
1531         tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1532
1533         phydev->advertising = phydev->supported;
1534
1535         return 0;
1536 }
1537
1538 static void tg3_phy_start(struct tg3 *tp)
1539 {
1540         struct phy_device *phydev;
1541
1542         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1543                 return;
1544
1545         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1546
1547         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1548                 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1549                 phydev->speed = tp->link_config.orig_speed;
1550                 phydev->duplex = tp->link_config.orig_duplex;
1551                 phydev->autoneg = tp->link_config.orig_autoneg;
1552                 phydev->advertising = tp->link_config.orig_advertising;
1553         }
1554
1555         phy_start(phydev);
1556
1557         phy_start_aneg(phydev);
1558 }
1559
1560 static void tg3_phy_stop(struct tg3 *tp)
1561 {
1562         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1563                 return;
1564
1565         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1566 }
1567
1568 static void tg3_phy_fini(struct tg3 *tp)
1569 {
1570         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1571                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1572                 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1573         }
1574 }
1575
1576 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1577 {
1578         int err;
1579
1580         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1581         if (!err)
1582                 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1583
1584         return err;
1585 }
1586
1587 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1588 {
1589         int err;
1590
1591         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1592         if (!err)
1593                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1594
1595         return err;
1596 }
1597
1598 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1599 {
1600         u32 phytest;
1601
1602         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1603                 u32 phy;
1604
1605                 tg3_writephy(tp, MII_TG3_FET_TEST,
1606                              phytest | MII_TG3_FET_SHADOW_EN);
1607                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1608                         if (enable)
1609                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1610                         else
1611                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1612                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1613                 }
1614                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1615         }
1616 }
1617
1618 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1619 {
1620         u32 reg;
1621
1622         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1623             ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
1624              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1625                 return;
1626
1627         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1628                 tg3_phy_fet_toggle_apd(tp, enable);
1629                 return;
1630         }
1631
1632         reg = MII_TG3_MISC_SHDW_WREN |
1633               MII_TG3_MISC_SHDW_SCR5_SEL |
1634               MII_TG3_MISC_SHDW_SCR5_LPED |
1635               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1636               MII_TG3_MISC_SHDW_SCR5_SDTL |
1637               MII_TG3_MISC_SHDW_SCR5_C125OE;
1638         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1639                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1640
1641         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1642
1643
1644         reg = MII_TG3_MISC_SHDW_WREN |
1645               MII_TG3_MISC_SHDW_APD_SEL |
1646               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1647         if (enable)
1648                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1649
1650         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1651 }
1652
1653 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1654 {
1655         u32 phy;
1656
1657         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1658             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1659                 return;
1660
1661         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1662                 u32 ephy;
1663
1664                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1665                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1666
1667                         tg3_writephy(tp, MII_TG3_FET_TEST,
1668                                      ephy | MII_TG3_FET_SHADOW_EN);
1669                         if (!tg3_readphy(tp, reg, &phy)) {
1670                                 if (enable)
1671                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1672                                 else
1673                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1674                                 tg3_writephy(tp, reg, phy);
1675                         }
1676                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1677                 }
1678         } else {
1679                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1680                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1681                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1682                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1683                         if (enable)
1684                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1685                         else
1686                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1687                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1688                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1689                 }
1690         }
1691 }
1692
1693 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1694 {
1695         u32 val;
1696
1697         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1698                 return;
1699
1700         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1701             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1702                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1703                              (val | (1 << 15) | (1 << 4)));
1704 }
1705
1706 static void tg3_phy_apply_otp(struct tg3 *tp)
1707 {
1708         u32 otp, phy;
1709
1710         if (!tp->phy_otp)
1711                 return;
1712
1713         otp = tp->phy_otp;
1714
1715         /* Enable SM_DSP clock and tx 6dB coding. */
1716         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1717               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1718               MII_TG3_AUXCTL_ACTL_TX_6DB;
1719         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1720
1721         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1722         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1723         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1724
1725         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1726               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1727         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1728
1729         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1730         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1731         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1732
1733         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1734         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1735
1736         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1737         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1738
1739         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1740               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1741         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1742
1743         /* Turn off SM_DSP clock. */
1744         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1745               MII_TG3_AUXCTL_ACTL_TX_6DB;
1746         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1747 }
1748
1749 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
1750 {
1751         u32 val;
1752
1753         if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
1754                 return;
1755
1756         tp->setlpicnt = 0;
1757
1758         if (tp->link_config.autoneg == AUTONEG_ENABLE &&
1759             current_link_up == 1 &&
1760             tp->link_config.active_duplex == DUPLEX_FULL &&
1761             (tp->link_config.active_speed == SPEED_100 ||
1762              tp->link_config.active_speed == SPEED_1000)) {
1763                 u32 eeectl;
1764
1765                 if (tp->link_config.active_speed == SPEED_1000)
1766                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
1767                 else
1768                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
1769
1770                 tw32(TG3_CPMU_EEE_CTRL, eeectl);
1771
1772                 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
1773                                   TG3_CL45_D7_EEERES_STAT, &val);
1774
1775                 switch (val) {
1776                 case TG3_CL45_D7_EEERES_STAT_LP_1000T:
1777                         switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
1778                         case ASIC_REV_5717:
1779                         case ASIC_REV_5719:
1780                         case ASIC_REV_57765:
1781                                 /* Enable SM_DSP clock and tx 6dB coding. */
1782                                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1783                                       MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1784                                       MII_TG3_AUXCTL_ACTL_TX_6DB;
1785                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1786
1787                                 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
1788
1789                                 /* Turn off SM_DSP clock. */
1790                                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1791                                       MII_TG3_AUXCTL_ACTL_TX_6DB;
1792                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1793                         }
1794                         /* Fallthrough */
1795                 case TG3_CL45_D7_EEERES_STAT_LP_100TX:
1796                         tp->setlpicnt = 2;
1797                 }
1798         }
1799
1800         if (!tp->setlpicnt) {
1801                 val = tr32(TG3_CPMU_EEE_MODE);
1802                 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
1803         }
1804 }
1805
1806 static int tg3_wait_macro_done(struct tg3 *tp)
1807 {
1808         int limit = 100;
1809
1810         while (limit--) {
1811                 u32 tmp32;
1812
1813                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1814                         if ((tmp32 & 0x1000) == 0)
1815                                 break;
1816                 }
1817         }
1818         if (limit < 0)
1819                 return -EBUSY;
1820
1821         return 0;
1822 }
1823
1824 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1825 {
1826         static const u32 test_pat[4][6] = {
1827         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1828         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1829         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1830         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1831         };
1832         int chan;
1833
1834         for (chan = 0; chan < 4; chan++) {
1835                 int i;
1836
1837                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1838                              (chan * 0x2000) | 0x0200);
1839                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1840
1841                 for (i = 0; i < 6; i++)
1842                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1843                                      test_pat[chan][i]);
1844
1845                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1846                 if (tg3_wait_macro_done(tp)) {
1847                         *resetp = 1;
1848                         return -EBUSY;
1849                 }
1850
1851                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1852                              (chan * 0x2000) | 0x0200);
1853                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1854                 if (tg3_wait_macro_done(tp)) {
1855                         *resetp = 1;
1856                         return -EBUSY;
1857                 }
1858
1859                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1860                 if (tg3_wait_macro_done(tp)) {
1861                         *resetp = 1;
1862                         return -EBUSY;
1863                 }
1864
1865                 for (i = 0; i < 6; i += 2) {
1866                         u32 low, high;
1867
1868                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1869                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1870                             tg3_wait_macro_done(tp)) {
1871                                 *resetp = 1;
1872                                 return -EBUSY;
1873                         }
1874                         low &= 0x7fff;
1875                         high &= 0x000f;
1876                         if (low != test_pat[chan][i] ||
1877                             high != test_pat[chan][i+1]) {
1878                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1879                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1880                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1881
1882                                 return -EBUSY;
1883                         }
1884                 }
1885         }
1886
1887         return 0;
1888 }
1889
1890 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1891 {
1892         int chan;
1893
1894         for (chan = 0; chan < 4; chan++) {
1895                 int i;
1896
1897                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1898                              (chan * 0x2000) | 0x0200);
1899                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1900                 for (i = 0; i < 6; i++)
1901                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1902                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1903                 if (tg3_wait_macro_done(tp))
1904                         return -EBUSY;
1905         }
1906
1907         return 0;
1908 }
1909
1910 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1911 {
1912         u32 reg32, phy9_orig;
1913         int retries, do_phy_reset, err;
1914
1915         retries = 10;
1916         do_phy_reset = 1;
1917         do {
1918                 if (do_phy_reset) {
1919                         err = tg3_bmcr_reset(tp);
1920                         if (err)
1921                                 return err;
1922                         do_phy_reset = 0;
1923                 }
1924
1925                 /* Disable transmitter and interrupt.  */
1926                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1927                         continue;
1928
1929                 reg32 |= 0x3000;
1930                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1931
1932                 /* Set full-duplex, 1000 mbps.  */
1933                 tg3_writephy(tp, MII_BMCR,
1934                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1935
1936                 /* Set to master mode.  */
1937                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1938                         continue;
1939
1940                 tg3_writephy(tp, MII_TG3_CTRL,
1941                              (MII_TG3_CTRL_AS_MASTER |
1942                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1943
1944                 /* Enable SM_DSP_CLOCK and 6dB.  */
1945                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1946
1947                 /* Block the PHY control access.  */
1948                 tg3_phydsp_write(tp, 0x8005, 0x0800);
1949
1950                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1951                 if (!err)
1952                         break;
1953         } while (--retries);
1954
1955         err = tg3_phy_reset_chanpat(tp);
1956         if (err)
1957                 return err;
1958
1959         tg3_phydsp_write(tp, 0x8005, 0x0000);
1960
1961         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1962         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1963
1964         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1965             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1966                 /* Set Extended packet length bit for jumbo frames */
1967                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1968         } else {
1969                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1970         }
1971
1972         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1973
1974         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1975                 reg32 &= ~0x3000;
1976                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1977         } else if (!err)
1978                 err = -EBUSY;
1979
1980         return err;
1981 }
1982
1983 /* This will reset the tigon3 PHY if there is no valid
1984  * link unless the FORCE argument is non-zero.
1985  */
1986 static int tg3_phy_reset(struct tg3 *tp)
1987 {
1988         u32 val, cpmuctrl;
1989         int err;
1990
1991         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1992                 val = tr32(GRC_MISC_CFG);
1993                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1994                 udelay(40);
1995         }
1996         err  = tg3_readphy(tp, MII_BMSR, &val);
1997         err |= tg3_readphy(tp, MII_BMSR, &val);
1998         if (err != 0)
1999                 return -EBUSY;
2000
2001         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
2002                 netif_carrier_off(tp->dev);
2003                 tg3_link_report(tp);
2004         }
2005
2006         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2007             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2008             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2009                 err = tg3_phy_reset_5703_4_5(tp);
2010                 if (err)
2011                         return err;
2012                 goto out;
2013         }
2014
2015         cpmuctrl = 0;
2016         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2017             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2018                 cpmuctrl = tr32(TG3_CPMU_CTRL);
2019                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2020                         tw32(TG3_CPMU_CTRL,
2021                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2022         }
2023
2024         err = tg3_bmcr_reset(tp);
2025         if (err)
2026                 return err;
2027
2028         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2029                 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2030                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2031
2032                 tw32(TG3_CPMU_CTRL, cpmuctrl);
2033         }
2034
2035         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2036             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2037                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2038                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2039                     CPMU_LSPD_1000MB_MACCLK_12_5) {
2040                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2041                         udelay(40);
2042                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2043                 }
2044         }
2045
2046         if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
2047             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2048                 return 0;
2049
2050         tg3_phy_apply_otp(tp);
2051
2052         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2053                 tg3_phy_toggle_apd(tp, true);
2054         else
2055                 tg3_phy_toggle_apd(tp, false);
2056
2057 out:
2058         if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
2059                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2060                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2061                 tg3_phydsp_write(tp, 0x000a, 0x0323);
2062                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2063         }
2064         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2065                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2066                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2067         }
2068         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2069                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2070                 tg3_phydsp_write(tp, 0x000a, 0x310b);
2071                 tg3_phydsp_write(tp, 0x201f, 0x9506);
2072                 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2073                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2074         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2075                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2076                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2077                 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2078                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2079                         tg3_writephy(tp, MII_TG3_TEST1,
2080                                      MII_TG3_TEST1_TRIM_EN | 0x4);
2081                 } else
2082                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2083                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2084         }
2085         /* Set Extended packet length bit (bit 14) on all chips that */
2086         /* support jumbo frames */
2087         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2088                 /* Cannot do read-modify-write on 5401 */
2089                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2090         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2091                 /* Set bit 14 with read-modify-write to preserve other bits */
2092                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2093                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
2094                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000);
2095         }
2096
2097         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2098          * jumbo frames transmission.
2099          */
2100         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2101                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2102                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2103                                      val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2104         }
2105
2106         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2107                 /* adjust output voltage */
2108                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2109         }
2110
2111         tg3_phy_toggle_automdix(tp, 1);
2112         tg3_phy_set_wirespeed(tp);
2113         return 0;
2114 }
2115
2116 static void tg3_frob_aux_power(struct tg3 *tp)
2117 {
2118         bool need_vaux = false;
2119
2120         /* The GPIOs do something completely different on 57765. */
2121         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2122             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2123             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2124                 return;
2125
2126         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2127              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2128              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2129              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) &&
2130             tp->pdev_peer != tp->pdev) {
2131                 struct net_device *dev_peer;
2132
2133                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2134
2135                 /* remove_one() may have been run on the peer. */
2136                 if (dev_peer) {
2137                         struct tg3 *tp_peer = netdev_priv(dev_peer);
2138
2139                         if (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE)
2140                                 return;
2141
2142                         if ((tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) ||
2143                             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF))
2144                                 need_vaux = true;
2145                 }
2146         }
2147
2148         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) ||
2149             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2150                 need_vaux = true;
2151
2152         if (need_vaux) {
2153                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2154                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2155                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2156                                     (GRC_LCLCTRL_GPIO_OE0 |
2157                                      GRC_LCLCTRL_GPIO_OE1 |
2158                                      GRC_LCLCTRL_GPIO_OE2 |
2159                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2160                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2161                                     100);
2162                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2163                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2164                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2165                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2166                                              GRC_LCLCTRL_GPIO_OE1 |
2167                                              GRC_LCLCTRL_GPIO_OE2 |
2168                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2169                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2170                                              tp->grc_local_ctrl;
2171                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2172
2173                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2174                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2175
2176                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2177                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2178                 } else {
2179                         u32 no_gpio2;
2180                         u32 grc_local_ctrl = 0;
2181
2182                         /* Workaround to prevent overdrawing Amps. */
2183                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2184                             ASIC_REV_5714) {
2185                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2186                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2187                                             grc_local_ctrl, 100);
2188                         }
2189
2190                         /* On 5753 and variants, GPIO2 cannot be used. */
2191                         no_gpio2 = tp->nic_sram_data_cfg &
2192                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2193
2194                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2195                                          GRC_LCLCTRL_GPIO_OE1 |
2196                                          GRC_LCLCTRL_GPIO_OE2 |
2197                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2198                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2199                         if (no_gpio2) {
2200                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2201                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2202                         }
2203                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2204                                                     grc_local_ctrl, 100);
2205
2206                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2207
2208                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2209                                                     grc_local_ctrl, 100);
2210
2211                         if (!no_gpio2) {
2212                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2213                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2214                                             grc_local_ctrl, 100);
2215                         }
2216                 }
2217         } else {
2218                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2219                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2220                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2221                                     (GRC_LCLCTRL_GPIO_OE1 |
2222                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2223
2224                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2225                                     GRC_LCLCTRL_GPIO_OE1, 100);
2226
2227                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2228                                     (GRC_LCLCTRL_GPIO_OE1 |
2229                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2230                 }
2231         }
2232 }
2233
2234 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2235 {
2236         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2237                 return 1;
2238         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2239                 if (speed != SPEED_10)
2240                         return 1;
2241         } else if (speed == SPEED_10)
2242                 return 1;
2243
2244         return 0;
2245 }
2246
2247 static int tg3_setup_phy(struct tg3 *, int);
2248
2249 #define RESET_KIND_SHUTDOWN     0
2250 #define RESET_KIND_INIT         1
2251 #define RESET_KIND_SUSPEND      2
2252
2253 static void tg3_write_sig_post_reset(struct tg3 *, int);
2254 static int tg3_halt_cpu(struct tg3 *, u32);
2255
2256 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2257 {
2258         u32 val;
2259
2260         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2261                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2262                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2263                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2264
2265                         sg_dig_ctrl |=
2266                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2267                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2268                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2269                 }
2270                 return;
2271         }
2272
2273         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2274                 tg3_bmcr_reset(tp);
2275                 val = tr32(GRC_MISC_CFG);
2276                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2277                 udelay(40);
2278                 return;
2279         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2280                 u32 phytest;
2281                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2282                         u32 phy;
2283
2284                         tg3_writephy(tp, MII_ADVERTISE, 0);
2285                         tg3_writephy(tp, MII_BMCR,
2286                                      BMCR_ANENABLE | BMCR_ANRESTART);
2287
2288                         tg3_writephy(tp, MII_TG3_FET_TEST,
2289                                      phytest | MII_TG3_FET_SHADOW_EN);
2290                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2291                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2292                                 tg3_writephy(tp,
2293                                              MII_TG3_FET_SHDW_AUXMODE4,
2294                                              phy);
2295                         }
2296                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2297                 }
2298                 return;
2299         } else if (do_low_power) {
2300                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2301                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2302
2303                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2304                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2305                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2306                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2307                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2308         }
2309
2310         /* The PHY should not be powered down on some chips because
2311          * of bugs.
2312          */
2313         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2314             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2315             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2316              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2317                 return;
2318
2319         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2320             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2321                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2322                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2323                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2324                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2325         }
2326
2327         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2328 }
2329
2330 /* tp->lock is held. */
2331 static int tg3_nvram_lock(struct tg3 *tp)
2332 {
2333         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2334                 int i;
2335
2336                 if (tp->nvram_lock_cnt == 0) {
2337                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2338                         for (i = 0; i < 8000; i++) {
2339                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2340                                         break;
2341                                 udelay(20);
2342                         }
2343                         if (i == 8000) {
2344                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2345                                 return -ENODEV;
2346                         }
2347                 }
2348                 tp->nvram_lock_cnt++;
2349         }
2350         return 0;
2351 }
2352
2353 /* tp->lock is held. */
2354 static void tg3_nvram_unlock(struct tg3 *tp)
2355 {
2356         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2357                 if (tp->nvram_lock_cnt > 0)
2358                         tp->nvram_lock_cnt--;
2359                 if (tp->nvram_lock_cnt == 0)
2360                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2361         }
2362 }
2363
2364 /* tp->lock is held. */
2365 static void tg3_enable_nvram_access(struct tg3 *tp)
2366 {
2367         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2368             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2369                 u32 nvaccess = tr32(NVRAM_ACCESS);
2370
2371                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2372         }
2373 }
2374
2375 /* tp->lock is held. */
2376 static void tg3_disable_nvram_access(struct tg3 *tp)
2377 {
2378         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2379             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2380                 u32 nvaccess = tr32(NVRAM_ACCESS);
2381
2382                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2383         }
2384 }
2385
2386 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2387                                         u32 offset, u32 *val)
2388 {
2389         u32 tmp;
2390         int i;
2391
2392         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2393                 return -EINVAL;
2394
2395         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2396                                         EEPROM_ADDR_DEVID_MASK |
2397                                         EEPROM_ADDR_READ);
2398         tw32(GRC_EEPROM_ADDR,
2399              tmp |
2400              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2401              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2402               EEPROM_ADDR_ADDR_MASK) |
2403              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2404
2405         for (i = 0; i < 1000; i++) {
2406                 tmp = tr32(GRC_EEPROM_ADDR);
2407
2408                 if (tmp & EEPROM_ADDR_COMPLETE)
2409                         break;
2410                 msleep(1);
2411         }
2412         if (!(tmp & EEPROM_ADDR_COMPLETE))
2413                 return -EBUSY;
2414
2415         tmp = tr32(GRC_EEPROM_DATA);
2416
2417         /*
2418          * The data will always be opposite the native endian
2419          * format.  Perform a blind byteswap to compensate.
2420          */
2421         *val = swab32(tmp);
2422
2423         return 0;
2424 }
2425
2426 #define NVRAM_CMD_TIMEOUT 10000
2427
2428 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2429 {
2430         int i;
2431
2432         tw32(NVRAM_CMD, nvram_cmd);
2433         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2434                 udelay(10);
2435                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2436                         udelay(10);
2437                         break;
2438                 }
2439         }
2440
2441         if (i == NVRAM_CMD_TIMEOUT)
2442                 return -EBUSY;
2443
2444         return 0;
2445 }
2446
2447 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2448 {
2449         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2450             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2451             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2452            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2453             (tp->nvram_jedecnum == JEDEC_ATMEL))
2454
2455                 addr = ((addr / tp->nvram_pagesize) <<
2456                         ATMEL_AT45DB0X1B_PAGE_POS) +
2457                        (addr % tp->nvram_pagesize);
2458
2459         return addr;
2460 }
2461
2462 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2463 {
2464         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2465             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2466             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2467            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2468             (tp->nvram_jedecnum == JEDEC_ATMEL))
2469
2470                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2471                         tp->nvram_pagesize) +
2472                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2473
2474         return addr;
2475 }
2476
2477 /* NOTE: Data read in from NVRAM is byteswapped according to
2478  * the byteswapping settings for all other register accesses.
2479  * tg3 devices are BE devices, so on a BE machine, the data
2480  * returned will be exactly as it is seen in NVRAM.  On a LE
2481  * machine, the 32-bit value will be byteswapped.
2482  */
2483 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2484 {
2485         int ret;
2486
2487         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2488                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2489
2490         offset = tg3_nvram_phys_addr(tp, offset);
2491
2492         if (offset > NVRAM_ADDR_MSK)
2493                 return -EINVAL;
2494
2495         ret = tg3_nvram_lock(tp);
2496         if (ret)
2497                 return ret;
2498
2499         tg3_enable_nvram_access(tp);
2500
2501         tw32(NVRAM_ADDR, offset);
2502         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2503                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2504
2505         if (ret == 0)
2506                 *val = tr32(NVRAM_RDDATA);
2507
2508         tg3_disable_nvram_access(tp);
2509
2510         tg3_nvram_unlock(tp);
2511
2512         return ret;
2513 }
2514
2515 /* Ensures NVRAM data is in bytestream format. */
2516 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2517 {
2518         u32 v;
2519         int res = tg3_nvram_read(tp, offset, &v);
2520         if (!res)
2521                 *val = cpu_to_be32(v);
2522         return res;
2523 }
2524
2525 /* tp->lock is held. */
2526 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2527 {
2528         u32 addr_high, addr_low;
2529         int i;
2530
2531         addr_high = ((tp->dev->dev_addr[0] << 8) |
2532                      tp->dev->dev_addr[1]);
2533         addr_low = ((tp->dev->dev_addr[2] << 24) |
2534                     (tp->dev->dev_addr[3] << 16) |
2535                     (tp->dev->dev_addr[4] <<  8) |
2536                     (tp->dev->dev_addr[5] <<  0));
2537         for (i = 0; i < 4; i++) {
2538                 if (i == 1 && skip_mac_1)
2539                         continue;
2540                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2541                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2542         }
2543
2544         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2545             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2546                 for (i = 0; i < 12; i++) {
2547                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2548                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2549                 }
2550         }
2551
2552         addr_high = (tp->dev->dev_addr[0] +
2553                      tp->dev->dev_addr[1] +
2554                      tp->dev->dev_addr[2] +
2555                      tp->dev->dev_addr[3] +
2556                      tp->dev->dev_addr[4] +
2557                      tp->dev->dev_addr[5]) &
2558                 TX_BACKOFF_SEED_MASK;
2559         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2560 }
2561
2562 static void tg3_enable_register_access(struct tg3 *tp)
2563 {
2564         /*
2565          * Make sure register accesses (indirect or otherwise) will function
2566          * correctly.
2567          */
2568         pci_write_config_dword(tp->pdev,
2569                                TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
2570 }
2571
2572 static int tg3_power_up(struct tg3 *tp)
2573 {
2574         tg3_enable_register_access(tp);
2575
2576         pci_set_power_state(tp->pdev, PCI_D0);
2577
2578         /* Switch out of Vaux if it is a NIC */
2579         if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2580                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2581
2582         return 0;
2583 }
2584
2585 static int tg3_power_down_prepare(struct tg3 *tp)
2586 {
2587         u32 misc_host_ctrl;
2588         bool device_should_wake, do_low_power;
2589
2590         tg3_enable_register_access(tp);
2591
2592         /* Restore the CLKREQ setting. */
2593         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2594                 u16 lnkctl;
2595
2596                 pci_read_config_word(tp->pdev,
2597                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2598                                      &lnkctl);
2599                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2600                 pci_write_config_word(tp->pdev,
2601                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2602                                       lnkctl);
2603         }
2604
2605         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2606         tw32(TG3PCI_MISC_HOST_CTRL,
2607              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2608
2609         device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
2610                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2611
2612         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2613                 do_low_power = false;
2614                 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2615                     !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2616                         struct phy_device *phydev;
2617                         u32 phyid, advertising;
2618
2619                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2620
2621                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2622
2623                         tp->link_config.orig_speed = phydev->speed;
2624                         tp->link_config.orig_duplex = phydev->duplex;
2625                         tp->link_config.orig_autoneg = phydev->autoneg;
2626                         tp->link_config.orig_advertising = phydev->advertising;
2627
2628                         advertising = ADVERTISED_TP |
2629                                       ADVERTISED_Pause |
2630                                       ADVERTISED_Autoneg |
2631                                       ADVERTISED_10baseT_Half;
2632
2633                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2634                             device_should_wake) {
2635                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2636                                         advertising |=
2637                                                 ADVERTISED_100baseT_Half |
2638                                                 ADVERTISED_100baseT_Full |
2639                                                 ADVERTISED_10baseT_Full;
2640                                 else
2641                                         advertising |= ADVERTISED_10baseT_Full;
2642                         }
2643
2644                         phydev->advertising = advertising;
2645
2646                         phy_start_aneg(phydev);
2647
2648                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2649                         if (phyid != PHY_ID_BCMAC131) {
2650                                 phyid &= PHY_BCM_OUI_MASK;
2651                                 if (phyid == PHY_BCM_OUI_1 ||
2652                                     phyid == PHY_BCM_OUI_2 ||
2653                                     phyid == PHY_BCM_OUI_3)
2654                                         do_low_power = true;
2655                         }
2656                 }
2657         } else {
2658                 do_low_power = true;
2659
2660                 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2661                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2662                         tp->link_config.orig_speed = tp->link_config.speed;
2663                         tp->link_config.orig_duplex = tp->link_config.duplex;
2664                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2665                 }
2666
2667                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2668                         tp->link_config.speed = SPEED_10;
2669                         tp->link_config.duplex = DUPLEX_HALF;
2670                         tp->link_config.autoneg = AUTONEG_ENABLE;
2671                         tg3_setup_phy(tp, 0);
2672                 }
2673         }
2674
2675         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2676                 u32 val;
2677
2678                 val = tr32(GRC_VCPU_EXT_CTRL);
2679                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2680         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2681                 int i;
2682                 u32 val;
2683
2684                 for (i = 0; i < 200; i++) {
2685                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2686                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2687                                 break;
2688                         msleep(1);
2689                 }
2690         }
2691         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2692                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2693                                                      WOL_DRV_STATE_SHUTDOWN |
2694                                                      WOL_DRV_WOL |
2695                                                      WOL_SET_MAGIC_PKT);
2696
2697         if (device_should_wake) {
2698                 u32 mac_mode;
2699
2700                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2701                         if (do_low_power) {
2702                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2703                                 udelay(40);
2704                         }
2705
2706                         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2707                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2708                         else
2709                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2710
2711                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2712                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2713                             ASIC_REV_5700) {
2714                                 u32 speed = (tp->tg3_flags &
2715                                              TG3_FLAG_WOL_SPEED_100MB) ?
2716                                              SPEED_100 : SPEED_10;
2717                                 if (tg3_5700_link_polarity(tp, speed))
2718                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2719                                 else
2720                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2721                         }
2722                 } else {
2723                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2724                 }
2725
2726                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2727                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2728
2729                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2730                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2731                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2732                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2733                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2734                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2735
2736                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
2737                         mac_mode |= MAC_MODE_APE_TX_EN |
2738                                     MAC_MODE_APE_RX_EN |
2739                                     MAC_MODE_TDE_ENABLE;
2740
2741                 tw32_f(MAC_MODE, mac_mode);
2742                 udelay(100);
2743
2744                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2745                 udelay(10);
2746         }
2747
2748         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2749             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2750              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2751                 u32 base_val;
2752
2753                 base_val = tp->pci_clock_ctrl;
2754                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2755                              CLOCK_CTRL_TXCLK_DISABLE);
2756
2757                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2758                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2759         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2760                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2761                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2762                 /* do nothing */
2763         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2764                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2765                 u32 newbits1, newbits2;
2766
2767                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2768                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2769                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2770                                     CLOCK_CTRL_TXCLK_DISABLE |
2771                                     CLOCK_CTRL_ALTCLK);
2772                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2773                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2774                         newbits1 = CLOCK_CTRL_625_CORE;
2775                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2776                 } else {
2777                         newbits1 = CLOCK_CTRL_ALTCLK;
2778                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2779                 }
2780
2781                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2782                             40);
2783
2784                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2785                             40);
2786
2787                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2788                         u32 newbits3;
2789
2790                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2791                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2792                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2793                                             CLOCK_CTRL_TXCLK_DISABLE |
2794                                             CLOCK_CTRL_44MHZ_CORE);
2795                         } else {
2796                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2797                         }
2798
2799                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2800                                     tp->pci_clock_ctrl | newbits3, 40);
2801                 }
2802         }
2803
2804         if (!(device_should_wake) &&
2805             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2806                 tg3_power_down_phy(tp, do_low_power);
2807
2808         tg3_frob_aux_power(tp);
2809
2810         /* Workaround for unstable PLL clock */
2811         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2812             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2813                 u32 val = tr32(0x7d00);
2814
2815                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2816                 tw32(0x7d00, val);
2817                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2818                         int err;
2819
2820                         err = tg3_nvram_lock(tp);
2821                         tg3_halt_cpu(tp, RX_CPU_BASE);
2822                         if (!err)
2823                                 tg3_nvram_unlock(tp);
2824                 }
2825         }
2826
2827         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2828
2829         return 0;
2830 }
2831
2832 static void tg3_power_down(struct tg3 *tp)
2833 {
2834         tg3_power_down_prepare(tp);
2835
2836         pci_wake_from_d3(tp->pdev, tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2837         pci_set_power_state(tp->pdev, PCI_D3hot);
2838 }
2839
2840 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2841 {
2842         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2843         case MII_TG3_AUX_STAT_10HALF:
2844                 *speed = SPEED_10;
2845                 *duplex = DUPLEX_HALF;
2846                 break;
2847
2848         case MII_TG3_AUX_STAT_10FULL:
2849                 *speed = SPEED_10;
2850                 *duplex = DUPLEX_FULL;
2851                 break;
2852
2853         case MII_TG3_AUX_STAT_100HALF:
2854                 *speed = SPEED_100;
2855                 *duplex = DUPLEX_HALF;
2856                 break;
2857
2858         case MII_TG3_AUX_STAT_100FULL:
2859                 *speed = SPEED_100;
2860                 *duplex = DUPLEX_FULL;
2861                 break;
2862
2863         case MII_TG3_AUX_STAT_1000HALF:
2864                 *speed = SPEED_1000;
2865                 *duplex = DUPLEX_HALF;
2866                 break;
2867
2868         case MII_TG3_AUX_STAT_1000FULL:
2869                 *speed = SPEED_1000;
2870                 *duplex = DUPLEX_FULL;
2871                 break;
2872
2873         default:
2874                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2875                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2876                                  SPEED_10;
2877                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2878                                   DUPLEX_HALF;
2879                         break;
2880                 }
2881                 *speed = SPEED_INVALID;
2882                 *duplex = DUPLEX_INVALID;
2883                 break;
2884         }
2885 }
2886
2887 static void tg3_phy_copper_begin(struct tg3 *tp)
2888 {
2889         u32 new_adv;
2890         int i;
2891
2892         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2893                 /* Entering low power mode.  Disable gigabit and
2894                  * 100baseT advertisements.
2895                  */
2896                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2897
2898                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2899                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2900                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2901                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2902
2903                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2904         } else if (tp->link_config.speed == SPEED_INVALID) {
2905                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2906                         tp->link_config.advertising &=
2907                                 ~(ADVERTISED_1000baseT_Half |
2908                                   ADVERTISED_1000baseT_Full);
2909
2910                 new_adv = ADVERTISE_CSMA;
2911                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2912                         new_adv |= ADVERTISE_10HALF;
2913                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2914                         new_adv |= ADVERTISE_10FULL;
2915                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2916                         new_adv |= ADVERTISE_100HALF;
2917                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2918                         new_adv |= ADVERTISE_100FULL;
2919
2920                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2921
2922                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2923
2924                 if (tp->link_config.advertising &
2925                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2926                         new_adv = 0;
2927                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2928                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2929                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2930                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2931                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
2932                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2933                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2934                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2935                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2936                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2937                 } else {
2938                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2939                 }
2940         } else {
2941                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2942                 new_adv |= ADVERTISE_CSMA;
2943
2944                 /* Asking for a specific link mode. */
2945                 if (tp->link_config.speed == SPEED_1000) {
2946                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2947
2948                         if (tp->link_config.duplex == DUPLEX_FULL)
2949                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2950                         else
2951                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2952                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2953                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2954                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2955                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2956                 } else {
2957                         if (tp->link_config.speed == SPEED_100) {
2958                                 if (tp->link_config.duplex == DUPLEX_FULL)
2959                                         new_adv |= ADVERTISE_100FULL;
2960                                 else
2961                                         new_adv |= ADVERTISE_100HALF;
2962                         } else {
2963                                 if (tp->link_config.duplex == DUPLEX_FULL)
2964                                         new_adv |= ADVERTISE_10FULL;
2965                                 else
2966                                         new_adv |= ADVERTISE_10HALF;
2967                         }
2968                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2969
2970                         new_adv = 0;
2971                 }
2972
2973                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2974         }
2975
2976         if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
2977                 u32 val;
2978
2979                 tw32(TG3_CPMU_EEE_MODE,
2980                      tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2981
2982                 /* Enable SM_DSP clock and tx 6dB coding. */
2983                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
2984                       MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
2985                       MII_TG3_AUXCTL_ACTL_TX_6DB;
2986                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2987
2988                 switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
2989                 case ASIC_REV_5717:
2990                 case ASIC_REV_57765:
2991                         if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
2992                                 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
2993                                                  MII_TG3_DSP_CH34TP2_HIBW01);
2994                         /* Fall through */
2995                 case ASIC_REV_5719:
2996                         val = MII_TG3_DSP_TAP26_ALNOKO |
2997                               MII_TG3_DSP_TAP26_RMRXSTO |
2998                               MII_TG3_DSP_TAP26_OPCSINPT;
2999                         tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
3000                 }
3001
3002                 val = 0;
3003                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3004                         /* Advertise 100-BaseTX EEE ability */
3005                         if (tp->link_config.advertising &
3006                             ADVERTISED_100baseT_Full)
3007                                 val |= MDIO_AN_EEE_ADV_100TX;
3008                         /* Advertise 1000-BaseT EEE ability */
3009                         if (tp->link_config.advertising &
3010                             ADVERTISED_1000baseT_Full)
3011                                 val |= MDIO_AN_EEE_ADV_1000T;
3012                 }
3013                 tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3014
3015                 /* Turn off SM_DSP clock. */
3016                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
3017                       MII_TG3_AUXCTL_ACTL_TX_6DB;
3018                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3019         }
3020
3021         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
3022             tp->link_config.speed != SPEED_INVALID) {
3023                 u32 bmcr, orig_bmcr;
3024
3025                 tp->link_config.active_speed = tp->link_config.speed;
3026                 tp->link_config.active_duplex = tp->link_config.duplex;
3027
3028                 bmcr = 0;
3029                 switch (tp->link_config.speed) {
3030                 default:
3031                 case SPEED_10:
3032                         break;
3033
3034                 case SPEED_100:
3035                         bmcr |= BMCR_SPEED100;
3036                         break;
3037
3038                 case SPEED_1000:
3039                         bmcr |= TG3_BMCR_SPEED1000;
3040                         break;
3041                 }
3042
3043                 if (tp->link_config.duplex == DUPLEX_FULL)
3044                         bmcr |= BMCR_FULLDPLX;
3045
3046                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
3047                     (bmcr != orig_bmcr)) {
3048                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
3049                         for (i = 0; i < 1500; i++) {
3050                                 u32 tmp;
3051
3052                                 udelay(10);
3053                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
3054                                     tg3_readphy(tp, MII_BMSR, &tmp))
3055                                         continue;
3056                                 if (!(tmp & BMSR_LSTATUS)) {
3057                                         udelay(40);
3058                                         break;
3059                                 }
3060                         }
3061                         tg3_writephy(tp, MII_BMCR, bmcr);
3062                         udelay(40);
3063                 }
3064         } else {
3065                 tg3_writephy(tp, MII_BMCR,
3066                              BMCR_ANENABLE | BMCR_ANRESTART);
3067         }
3068 }
3069
3070 static int tg3_init_5401phy_dsp(struct tg3 *tp)
3071 {
3072         int err;
3073
3074         /* Turn off tap power management. */
3075         /* Set Extended packet length bit */
3076         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
3077
3078         err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
3079         err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
3080         err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
3081         err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
3082         err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
3083
3084         udelay(40);
3085
3086         return err;
3087 }
3088
3089 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3090 {
3091         u32 adv_reg, all_mask = 0;
3092
3093         if (mask & ADVERTISED_10baseT_Half)
3094                 all_mask |= ADVERTISE_10HALF;
3095         if (mask & ADVERTISED_10baseT_Full)
3096                 all_mask |= ADVERTISE_10FULL;
3097         if (mask & ADVERTISED_100baseT_Half)
3098                 all_mask |= ADVERTISE_100HALF;
3099         if (mask & ADVERTISED_100baseT_Full)
3100                 all_mask |= ADVERTISE_100FULL;
3101
3102         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3103                 return 0;
3104
3105         if ((adv_reg & all_mask) != all_mask)
3106                 return 0;
3107         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3108                 u32 tg3_ctrl;
3109
3110                 all_mask = 0;
3111                 if (mask & ADVERTISED_1000baseT_Half)
3112                         all_mask |= ADVERTISE_1000HALF;
3113                 if (mask & ADVERTISED_1000baseT_Full)
3114                         all_mask |= ADVERTISE_1000FULL;
3115
3116                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3117                         return 0;
3118
3119                 if ((tg3_ctrl & all_mask) != all_mask)
3120                         return 0;
3121         }
3122         return 1;
3123 }
3124
3125 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3126 {
3127         u32 curadv, reqadv;
3128
3129         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3130                 return 1;
3131
3132         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3133         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3134
3135         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3136                 if (curadv != reqadv)
3137                         return 0;
3138
3139                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3140                         tg3_readphy(tp, MII_LPA, rmtadv);
3141         } else {
3142                 /* Reprogram the advertisement register, even if it
3143                  * does not affect the current link.  If the link
3144                  * gets renegotiated in the future, we can save an
3145                  * additional renegotiation cycle by advertising
3146                  * it correctly in the first place.
3147                  */
3148                 if (curadv != reqadv) {
3149                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3150                                      ADVERTISE_PAUSE_ASYM);
3151                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3152                 }
3153         }
3154
3155         return 1;
3156 }
3157
3158 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3159 {
3160         int current_link_up;
3161         u32 bmsr, val;
3162         u32 lcl_adv, rmt_adv;
3163         u16 current_speed;
3164         u8 current_duplex;
3165         int i, err;
3166
3167         tw32(MAC_EVENT, 0);
3168
3169         tw32_f(MAC_STATUS,
3170              (MAC_STATUS_SYNC_CHANGED |
3171               MAC_STATUS_CFG_CHANGED |
3172               MAC_STATUS_MI_COMPLETION |
3173               MAC_STATUS_LNKSTATE_CHANGED));
3174         udelay(40);
3175
3176         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3177                 tw32_f(MAC_MI_MODE,
3178                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3179                 udelay(80);
3180         }
3181
3182         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3183
3184         /* Some third-party PHYs need to be reset on link going
3185          * down.
3186          */
3187         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3188              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3189              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3190             netif_carrier_ok(tp->dev)) {
3191                 tg3_readphy(tp, MII_BMSR, &bmsr);
3192                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3193                     !(bmsr & BMSR_LSTATUS))
3194                         force_reset = 1;
3195         }
3196         if (force_reset)
3197                 tg3_phy_reset(tp);
3198
3199         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3200                 tg3_readphy(tp, MII_BMSR, &bmsr);
3201                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3202                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3203                         bmsr = 0;
3204
3205                 if (!(bmsr & BMSR_LSTATUS)) {
3206                         err = tg3_init_5401phy_dsp(tp);
3207                         if (err)
3208                                 return err;
3209
3210                         tg3_readphy(tp, MII_BMSR, &bmsr);
3211                         for (i = 0; i < 1000; i++) {
3212                                 udelay(10);
3213                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3214                                     (bmsr & BMSR_LSTATUS)) {
3215                                         udelay(40);
3216                                         break;
3217                                 }
3218                         }
3219
3220                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3221                             TG3_PHY_REV_BCM5401_B0 &&
3222                             !(bmsr & BMSR_LSTATUS) &&
3223                             tp->link_config.active_speed == SPEED_1000) {
3224                                 err = tg3_phy_reset(tp);
3225                                 if (!err)
3226                                         err = tg3_init_5401phy_dsp(tp);
3227                                 if (err)
3228                                         return err;
3229                         }
3230                 }
3231         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3232                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3233                 /* 5701 {A0,B0} CRC bug workaround */
3234                 tg3_writephy(tp, 0x15, 0x0a75);
3235                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3236                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3237                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3238         }
3239
3240         /* Clear pending interrupts... */
3241         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3242         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3243
3244         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3245                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3246         else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3247                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3248
3249         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3250             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3251                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3252                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3253                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3254                 else
3255                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3256         }
3257
3258         current_link_up = 0;
3259         current_speed = SPEED_INVALID;
3260         current_duplex = DUPLEX_INVALID;
3261
3262         if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3263                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3264                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3265                 if (!(val & (1 << 10))) {
3266                         val |= (1 << 10);
3267                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3268                         goto relink;
3269                 }
3270         }
3271
3272         bmsr = 0;
3273         for (i = 0; i < 100; i++) {
3274                 tg3_readphy(tp, MII_BMSR, &bmsr);
3275                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3276                     (bmsr & BMSR_LSTATUS))
3277                         break;
3278                 udelay(40);
3279         }
3280
3281         if (bmsr & BMSR_LSTATUS) {
3282                 u32 aux_stat, bmcr;
3283
3284                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3285                 for (i = 0; i < 2000; i++) {
3286                         udelay(10);
3287                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3288                             aux_stat)
3289                                 break;
3290                 }
3291
3292                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3293                                              &current_speed,
3294                                              &current_duplex);
3295
3296                 bmcr = 0;
3297                 for (i = 0; i < 200; i++) {
3298                         tg3_readphy(tp, MII_BMCR, &bmcr);
3299                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3300                                 continue;
3301                         if (bmcr && bmcr != 0x7fff)
3302                                 break;
3303                         udelay(10);
3304                 }
3305
3306                 lcl_adv = 0;
3307                 rmt_adv = 0;
3308
3309                 tp->link_config.active_speed = current_speed;
3310                 tp->link_config.active_duplex = current_duplex;
3311
3312                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3313                         if ((bmcr & BMCR_ANENABLE) &&
3314                             tg3_copper_is_advertising_all(tp,
3315                                                 tp->link_config.advertising)) {
3316                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3317                                                                   &rmt_adv))
3318                                         current_link_up = 1;
3319                         }
3320                 } else {
3321                         if (!(bmcr & BMCR_ANENABLE) &&
3322                             tp->link_config.speed == current_speed &&
3323                             tp->link_config.duplex == current_duplex &&
3324                             tp->link_config.flowctrl ==
3325                             tp->link_config.active_flowctrl) {
3326                                 current_link_up = 1;
3327                         }
3328                 }
3329
3330                 if (current_link_up == 1 &&
3331                     tp->link_config.active_duplex == DUPLEX_FULL)
3332                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3333         }
3334
3335 relink:
3336         if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3337                 tg3_phy_copper_begin(tp);
3338
3339                 tg3_readphy(tp, MII_BMSR, &bmsr);
3340                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3341                     (bmsr & BMSR_LSTATUS))
3342                         current_link_up = 1;
3343         }
3344
3345         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3346         if (current_link_up == 1) {
3347                 if (tp->link_config.active_speed == SPEED_100 ||
3348                     tp->link_config.active_speed == SPEED_10)
3349                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3350                 else
3351                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3352         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3353                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3354         else
3355                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3356
3357         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3358         if (tp->link_config.active_duplex == DUPLEX_HALF)
3359                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3360
3361         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3362                 if (current_link_up == 1 &&
3363                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3364                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3365                 else
3366                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3367         }
3368
3369         /* ??? Without this setting Netgear GA302T PHY does not
3370          * ??? send/receive packets...
3371          */
3372         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3373             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3374                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3375                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3376                 udelay(80);
3377         }
3378
3379         tw32_f(MAC_MODE, tp->mac_mode);
3380         udelay(40);
3381
3382         tg3_phy_eee_adjust(tp, current_link_up);
3383
3384         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3385                 /* Polled via timer. */
3386                 tw32_f(MAC_EVENT, 0);
3387         } else {
3388                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3389         }
3390         udelay(40);
3391
3392         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3393             current_link_up == 1 &&
3394             tp->link_config.active_speed == SPEED_1000 &&
3395             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3396              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3397                 udelay(120);
3398                 tw32_f(MAC_STATUS,
3399                      (MAC_STATUS_SYNC_CHANGED |
3400                       MAC_STATUS_CFG_CHANGED));
3401                 udelay(40);
3402                 tg3_write_mem(tp,
3403                               NIC_SRAM_FIRMWARE_MBOX,
3404                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3405         }
3406
3407         /* Prevent send BD corruption. */
3408         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3409                 u16 oldlnkctl, newlnkctl;
3410
3411                 pci_read_config_word(tp->pdev,
3412                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3413                                      &oldlnkctl);
3414                 if (tp->link_config.active_speed == SPEED_100 ||
3415                     tp->link_config.active_speed == SPEED_10)
3416                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3417                 else
3418                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3419                 if (newlnkctl != oldlnkctl)
3420                         pci_write_config_word(tp->pdev,
3421                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3422                                               newlnkctl);
3423         }
3424
3425         if (current_link_up != netif_carrier_ok(tp->dev)) {
3426                 if (current_link_up)
3427                         netif_carrier_on(tp->dev);
3428                 else
3429                         netif_carrier_off(tp->dev);
3430                 tg3_link_report(tp);
3431         }
3432
3433         return 0;
3434 }
3435
3436 struct tg3_fiber_aneginfo {
3437         int state;
3438 #define ANEG_STATE_UNKNOWN              0
3439 #define ANEG_STATE_AN_ENABLE            1
3440 #define ANEG_STATE_RESTART_INIT         2
3441 #define ANEG_STATE_RESTART              3
3442 #define ANEG_STATE_DISABLE_LINK_OK      4
3443 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3444 #define ANEG_STATE_ABILITY_DETECT       6
3445 #define ANEG_STATE_ACK_DETECT_INIT      7
3446 #define ANEG_STATE_ACK_DETECT           8
3447 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3448 #define ANEG_STATE_COMPLETE_ACK         10
3449 #define ANEG_STATE_IDLE_DETECT_INIT     11
3450 #define ANEG_STATE_IDLE_DETECT          12
3451 #define ANEG_STATE_LINK_OK              13
3452 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3453 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3454
3455         u32 flags;
3456 #define MR_AN_ENABLE            0x00000001
3457 #define MR_RESTART_AN           0x00000002
3458 #define MR_AN_COMPLETE          0x00000004
3459 #define MR_PAGE_RX              0x00000008
3460 #define MR_NP_LOADED            0x00000010
3461 #define MR_TOGGLE_TX            0x00000020
3462 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3463 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3464 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3465 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3466 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3467 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3468 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3469 #define MR_TOGGLE_RX            0x00002000
3470 #define MR_NP_RX                0x00004000
3471
3472 #define MR_LINK_OK              0x80000000
3473
3474         unsigned long link_time, cur_time;
3475
3476         u32 ability_match_cfg;
3477         int ability_match_count;
3478
3479         char ability_match, idle_match, ack_match;
3480
3481         u32 txconfig, rxconfig;
3482 #define ANEG_CFG_NP             0x00000080
3483 #define ANEG_CFG_ACK            0x00000040
3484 #define ANEG_CFG_RF2            0x00000020
3485 #define ANEG_CFG_RF1            0x00000010
3486 #define ANEG_CFG_PS2            0x00000001
3487 #define ANEG_CFG_PS1            0x00008000
3488 #define ANEG_CFG_HD             0x00004000
3489 #define ANEG_CFG_FD             0x00002000
3490 #define ANEG_CFG_INVAL          0x00001f06
3491
3492 };
3493 #define ANEG_OK         0
3494 #define ANEG_DONE       1
3495 #define ANEG_TIMER_ENAB 2
3496 #define ANEG_FAILED     -1
3497
3498 #define ANEG_STATE_SETTLE_TIME  10000
3499
3500 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3501                                    struct tg3_fiber_aneginfo *ap)
3502 {
3503         u16 flowctrl;
3504         unsigned long delta;
3505         u32 rx_cfg_reg;
3506         int ret;
3507
3508         if (ap->state == ANEG_STATE_UNKNOWN) {
3509                 ap->rxconfig = 0;
3510                 ap->link_time = 0;
3511                 ap->cur_time = 0;
3512                 ap->ability_match_cfg = 0;
3513                 ap->ability_match_count = 0;
3514                 ap->ability_match = 0;
3515                 ap->idle_match = 0;
3516                 ap->ack_match = 0;
3517         }
3518         ap->cur_time++;
3519
3520         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3521                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3522
3523                 if (rx_cfg_reg != ap->ability_match_cfg) {
3524                         ap->ability_match_cfg = rx_cfg_reg;
3525                         ap->ability_match = 0;
3526                         ap->ability_match_count = 0;
3527                 } else {
3528                         if (++ap->ability_match_count > 1) {
3529                                 ap->ability_match = 1;
3530                                 ap->ability_match_cfg = rx_cfg_reg;
3531                         }
3532                 }
3533                 if (rx_cfg_reg & ANEG_CFG_ACK)
3534                         ap->ack_match = 1;
3535                 else
3536                         ap->ack_match = 0;
3537
3538                 ap->idle_match = 0;
3539         } else {
3540                 ap->idle_match = 1;
3541                 ap->ability_match_cfg = 0;
3542                 ap->ability_match_count = 0;
3543                 ap->ability_match = 0;
3544                 ap->ack_match = 0;
3545
3546                 rx_cfg_reg = 0;
3547         }
3548
3549         ap->rxconfig = rx_cfg_reg;
3550         ret = ANEG_OK;
3551
3552         switch (ap->state) {
3553         case ANEG_STATE_UNKNOWN:
3554                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3555                         ap->state = ANEG_STATE_AN_ENABLE;
3556
3557                 /* fallthru */
3558         case ANEG_STATE_AN_ENABLE:
3559                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3560                 if (ap->flags & MR_AN_ENABLE) {
3561                         ap->link_time = 0;
3562                         ap->cur_time = 0;
3563                         ap->ability_match_cfg = 0;
3564                         ap->ability_match_count = 0;
3565                         ap->ability_match = 0;
3566                         ap->idle_match = 0;
3567                         ap->ack_match = 0;
3568
3569                         ap->state = ANEG_STATE_RESTART_INIT;
3570                 } else {
3571                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3572                 }
3573                 break;
3574
3575         case ANEG_STATE_RESTART_INIT:
3576                 ap->link_time = ap->cur_time;
3577                 ap->flags &= ~(MR_NP_LOADED);
3578                 ap->txconfig = 0;
3579                 tw32(MAC_TX_AUTO_NEG, 0);
3580                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3581                 tw32_f(MAC_MODE, tp->mac_mode);
3582                 udelay(40);
3583
3584                 ret = ANEG_TIMER_ENAB;
3585                 ap->state = ANEG_STATE_RESTART;
3586
3587                 /* fallthru */
3588         case ANEG_STATE_RESTART:
3589                 delta = ap->cur_time - ap->link_time;
3590                 if (delta > ANEG_STATE_SETTLE_TIME)
3591                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3592                 else
3593                         ret = ANEG_TIMER_ENAB;
3594                 break;
3595
3596         case ANEG_STATE_DISABLE_LINK_OK:
3597                 ret = ANEG_DONE;
3598                 break;
3599
3600         case ANEG_STATE_ABILITY_DETECT_INIT:
3601                 ap->flags &= ~(MR_TOGGLE_TX);
3602                 ap->txconfig = ANEG_CFG_FD;
3603                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3604                 if (flowctrl & ADVERTISE_1000XPAUSE)
3605                         ap->txconfig |= ANEG_CFG_PS1;
3606                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3607                         ap->txconfig |= ANEG_CFG_PS2;
3608                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3609                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3610                 tw32_f(MAC_MODE, tp->mac_mode);
3611                 udelay(40);
3612
3613                 ap->state = ANEG_STATE_ABILITY_DETECT;
3614                 break;
3615
3616         case ANEG_STATE_ABILITY_DETECT:
3617                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3618                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3619                 break;
3620
3621         case ANEG_STATE_ACK_DETECT_INIT:
3622                 ap->txconfig |= ANEG_CFG_ACK;
3623                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3624                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3625                 tw32_f(MAC_MODE, tp->mac_mode);
3626                 udelay(40);
3627
3628                 ap->state = ANEG_STATE_ACK_DETECT;
3629
3630                 /* fallthru */
3631         case ANEG_STATE_ACK_DETECT:
3632                 if (ap->ack_match != 0) {
3633                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3634                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3635                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3636                         } else {
3637                                 ap->state = ANEG_STATE_AN_ENABLE;
3638                         }
3639                 } else if (ap->ability_match != 0 &&
3640                            ap->rxconfig == 0) {
3641                         ap->state = ANEG_STATE_AN_ENABLE;
3642                 }
3643                 break;
3644
3645         case ANEG_STATE_COMPLETE_ACK_INIT:
3646                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3647                         ret = ANEG_FAILED;
3648                         break;
3649                 }
3650                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3651                                MR_LP_ADV_HALF_DUPLEX |
3652                                MR_LP_ADV_SYM_PAUSE |
3653                                MR_LP_ADV_ASYM_PAUSE |
3654                                MR_LP_ADV_REMOTE_FAULT1 |
3655                                MR_LP_ADV_REMOTE_FAULT2 |
3656                                MR_LP_ADV_NEXT_PAGE |
3657                                MR_TOGGLE_RX |
3658                                MR_NP_RX);
3659                 if (ap->rxconfig & ANEG_CFG_FD)
3660                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3661                 if (ap->rxconfig & ANEG_CFG_HD)
3662                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3663                 if (ap->rxconfig & ANEG_CFG_PS1)
3664                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3665                 if (ap->rxconfig & ANEG_CFG_PS2)
3666                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3667                 if (ap->rxconfig & ANEG_CFG_RF1)
3668                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3669                 if (ap->rxconfig & ANEG_CFG_RF2)
3670                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3671                 if (ap->rxconfig & ANEG_CFG_NP)
3672                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3673
3674                 ap->link_time = ap->cur_time;
3675
3676                 ap->flags ^= (MR_TOGGLE_TX);
3677                 if (ap->rxconfig & 0x0008)
3678                         ap->flags |= MR_TOGGLE_RX;
3679                 if (ap->rxconfig & ANEG_CFG_NP)
3680                         ap->flags |= MR_NP_RX;
3681                 ap->flags |= MR_PAGE_RX;
3682
3683                 ap->state = ANEG_STATE_COMPLETE_ACK;
3684                 ret = ANEG_TIMER_ENAB;
3685                 break;
3686
3687         case ANEG_STATE_COMPLETE_ACK:
3688                 if (ap->ability_match != 0 &&
3689                     ap->rxconfig == 0) {
3690                         ap->state = ANEG_STATE_AN_ENABLE;
3691                         break;
3692                 }
3693                 delta = ap->cur_time - ap->link_time;
3694                 if (delta > ANEG_STATE_SETTLE_TIME) {
3695                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3696                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3697                         } else {
3698                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3699                                     !(ap->flags & MR_NP_RX)) {
3700                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3701                                 } else {
3702                                         ret = ANEG_FAILED;
3703                                 }
3704                         }
3705                 }
3706                 break;
3707
3708         case ANEG_STATE_IDLE_DETECT_INIT:
3709                 ap->link_time = ap->cur_time;
3710                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3711                 tw32_f(MAC_MODE, tp->mac_mode);
3712                 udelay(40);
3713
3714                 ap->state = ANEG_STATE_IDLE_DETECT;
3715                 ret = ANEG_TIMER_ENAB;
3716                 break;
3717
3718         case ANEG_STATE_IDLE_DETECT:
3719                 if (ap->ability_match != 0 &&
3720                     ap->rxconfig == 0) {
3721                         ap->state = ANEG_STATE_AN_ENABLE;
3722                         break;
3723                 }
3724                 delta = ap->cur_time - ap->link_time;
3725                 if (delta > ANEG_STATE_SETTLE_TIME) {
3726                         /* XXX another gem from the Broadcom driver :( */
3727                         ap->state = ANEG_STATE_LINK_OK;
3728                 }
3729                 break;
3730
3731         case ANEG_STATE_LINK_OK:
3732                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3733                 ret = ANEG_DONE;
3734                 break;
3735
3736         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3737                 /* ??? unimplemented */
3738                 break;
3739
3740         case ANEG_STATE_NEXT_PAGE_WAIT:
3741                 /* ??? unimplemented */
3742                 break;
3743
3744         default:
3745                 ret = ANEG_FAILED;
3746                 break;
3747         }
3748
3749         return ret;
3750 }
3751
3752 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3753 {
3754         int res = 0;
3755         struct tg3_fiber_aneginfo aninfo;
3756         int status = ANEG_FAILED;
3757         unsigned int tick;
3758         u32 tmp;
3759
3760         tw32_f(MAC_TX_AUTO_NEG, 0);
3761
3762         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3763         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3764         udelay(40);
3765
3766         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3767         udelay(40);
3768
3769         memset(&aninfo, 0, sizeof(aninfo));
3770         aninfo.flags |= MR_AN_ENABLE;
3771         aninfo.state = ANEG_STATE_UNKNOWN;
3772         aninfo.cur_time = 0;
3773         tick = 0;
3774         while (++tick < 195000) {
3775                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3776                 if (status == ANEG_DONE || status == ANEG_FAILED)
3777                         break;
3778
3779                 udelay(1);
3780         }
3781
3782         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3783         tw32_f(MAC_MODE, tp->mac_mode);
3784         udelay(40);
3785
3786         *txflags = aninfo.txconfig;
3787         *rxflags = aninfo.flags;
3788
3789         if (status == ANEG_DONE &&
3790             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3791                              MR_LP_ADV_FULL_DUPLEX)))
3792                 res = 1;
3793
3794         return res;
3795 }
3796
3797 static void tg3_init_bcm8002(struct tg3 *tp)
3798 {
3799         u32 mac_status = tr32(MAC_STATUS);
3800         int i;
3801
3802         /* Reset when initting first time or we have a link. */
3803         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3804             !(mac_status & MAC_STATUS_PCS_SYNCED))
3805                 return;
3806
3807         /* Set PLL lock range. */
3808         tg3_writephy(tp, 0x16, 0x8007);
3809
3810         /* SW reset */
3811         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3812
3813         /* Wait for reset to complete. */
3814         /* XXX schedule_timeout() ... */
3815         for (i = 0; i < 500; i++)
3816                 udelay(10);
3817
3818         /* Config mode; select PMA/Ch 1 regs. */
3819         tg3_writephy(tp, 0x10, 0x8411);
3820
3821         /* Enable auto-lock and comdet, select txclk for tx. */
3822         tg3_writephy(tp, 0x11, 0x0a10);
3823
3824         tg3_writephy(tp, 0x18, 0x00a0);
3825         tg3_writephy(tp, 0x16, 0x41ff);
3826
3827         /* Assert and deassert POR. */
3828         tg3_writephy(tp, 0x13, 0x0400);
3829         udelay(40);
3830         tg3_writephy(tp, 0x13, 0x0000);
3831
3832         tg3_writephy(tp, 0x11, 0x0a50);
3833         udelay(40);
3834         tg3_writephy(tp, 0x11, 0x0a10);
3835
3836         /* Wait for signal to stabilize */
3837         /* XXX schedule_timeout() ... */
3838         for (i = 0; i < 15000; i++)
3839                 udelay(10);
3840
3841         /* Deselect the channel register so we can read the PHYID
3842          * later.
3843          */
3844         tg3_writephy(tp, 0x10, 0x8011);
3845 }
3846
3847 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3848 {
3849         u16 flowctrl;
3850         u32 sg_dig_ctrl, sg_dig_status;
3851         u32 serdes_cfg, expected_sg_dig_ctrl;
3852         int workaround, port_a;
3853         int current_link_up;
3854
3855         serdes_cfg = 0;
3856         expected_sg_dig_ctrl = 0;
3857         workaround = 0;
3858         port_a = 1;
3859         current_link_up = 0;
3860
3861         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3862             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3863                 workaround = 1;
3864                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3865                         port_a = 0;
3866
3867                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3868                 /* preserve bits 20-23 for voltage regulator */
3869                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3870         }
3871
3872         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3873
3874         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3875                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3876                         if (workaround) {
3877                                 u32 val = serdes_cfg;
3878
3879                                 if (port_a)
3880                                         val |= 0xc010000;
3881                                 else
3882                                         val |= 0x4010000;
3883                                 tw32_f(MAC_SERDES_CFG, val);
3884                         }
3885
3886                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3887                 }
3888                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3889                         tg3_setup_flow_control(tp, 0, 0);
3890                         current_link_up = 1;
3891                 }
3892                 goto out;
3893         }
3894
3895         /* Want auto-negotiation.  */
3896         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3897
3898         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3899         if (flowctrl & ADVERTISE_1000XPAUSE)
3900                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3901         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3902                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3903
3904         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3905                 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3906                     tp->serdes_counter &&
3907                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3908                                     MAC_STATUS_RCVD_CFG)) ==
3909                      MAC_STATUS_PCS_SYNCED)) {
3910                         tp->serdes_counter--;
3911                         current_link_up = 1;
3912                         goto out;
3913                 }
3914 restart_autoneg:
3915                 if (workaround)
3916                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3917                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3918                 udelay(5);
3919                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3920
3921                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3922                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3923         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3924                                  MAC_STATUS_SIGNAL_DET)) {
3925                 sg_dig_status = tr32(SG_DIG_STATUS);
3926                 mac_status = tr32(MAC_STATUS);
3927
3928                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3929                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3930                         u32 local_adv = 0, remote_adv = 0;
3931
3932                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3933                                 local_adv |= ADVERTISE_1000XPAUSE;
3934                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3935                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3936
3937                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3938                                 remote_adv |= LPA_1000XPAUSE;
3939                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3940                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3941
3942                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3943                         current_link_up = 1;
3944                         tp->serdes_counter = 0;
3945                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3946                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3947                         if (tp->serdes_counter)
3948                                 tp->serdes_counter--;
3949                         else {
3950                                 if (workaround) {
3951                                         u32 val = serdes_cfg;
3952
3953                                         if (port_a)
3954                                                 val |= 0xc010000;
3955                                         else
3956                                                 val |= 0x4010000;
3957
3958                                         tw32_f(MAC_SERDES_CFG, val);
3959                                 }
3960
3961                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3962                                 udelay(40);
3963
3964                                 /* Link parallel detection - link is up */
3965                                 /* only if we have PCS_SYNC and not */
3966                                 /* receiving config code words */
3967                                 mac_status = tr32(MAC_STATUS);
3968                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3969                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3970                                         tg3_setup_flow_control(tp, 0, 0);
3971                                         current_link_up = 1;
3972                                         tp->phy_flags |=
3973                                                 TG3_PHYFLG_PARALLEL_DETECT;
3974                                         tp->serdes_counter =
3975                                                 SERDES_PARALLEL_DET_TIMEOUT;
3976                                 } else
3977                                         goto restart_autoneg;
3978                         }
3979                 }
3980         } else {
3981                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3982                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3983         }
3984
3985 out:
3986         return current_link_up;
3987 }
3988
3989 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3990 {
3991         int current_link_up = 0;
3992
3993         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3994                 goto out;
3995
3996         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3997                 u32 txflags, rxflags;
3998                 int i;
3999
4000                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
4001                         u32 local_adv = 0, remote_adv = 0;
4002
4003                         if (txflags & ANEG_CFG_PS1)
4004                                 local_adv |= ADVERTISE_1000XPAUSE;
4005                         if (txflags & ANEG_CFG_PS2)
4006                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
4007
4008                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
4009                                 remote_adv |= LPA_1000XPAUSE;
4010                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
4011                                 remote_adv |= LPA_1000XPAUSE_ASYM;
4012
4013                         tg3_setup_flow_control(tp, local_adv, remote_adv);
4014
4015                         current_link_up = 1;
4016                 }
4017                 for (i = 0; i < 30; i++) {
4018                         udelay(20);
4019                         tw32_f(MAC_STATUS,
4020                                (MAC_STATUS_SYNC_CHANGED |
4021                                 MAC_STATUS_CFG_CHANGED));
4022                         udelay(40);
4023                         if ((tr32(MAC_STATUS) &
4024                              (MAC_STATUS_SYNC_CHANGED |
4025                               MAC_STATUS_CFG_CHANGED)) == 0)
4026                                 break;
4027                 }
4028
4029                 mac_status = tr32(MAC_STATUS);
4030                 if (current_link_up == 0 &&
4031                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
4032                     !(mac_status & MAC_STATUS_RCVD_CFG))
4033                         current_link_up = 1;
4034         } else {
4035                 tg3_setup_flow_control(tp, 0, 0);
4036
4037                 /* Forcing 1000FD link up. */
4038                 current_link_up = 1;
4039
4040                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
4041                 udelay(40);
4042
4043                 tw32_f(MAC_MODE, tp->mac_mode);
4044                 udelay(40);
4045         }
4046
4047 out:
4048         return current_link_up;
4049 }
4050
4051 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4052 {
4053         u32 orig_pause_cfg;
4054         u16 orig_active_speed;
4055         u8 orig_active_duplex;
4056         u32 mac_status;
4057         int current_link_up;
4058         int i;
4059
4060         orig_pause_cfg = tp->link_config.active_flowctrl;
4061         orig_active_speed = tp->link_config.active_speed;
4062         orig_active_duplex = tp->link_config.active_duplex;
4063
4064         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
4065             netif_carrier_ok(tp->dev) &&
4066             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
4067                 mac_status = tr32(MAC_STATUS);
4068                 mac_status &= (MAC_STATUS_PCS_SYNCED |
4069                                MAC_STATUS_SIGNAL_DET |
4070                                MAC_STATUS_CFG_CHANGED |
4071                                MAC_STATUS_RCVD_CFG);
4072                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
4073                                    MAC_STATUS_SIGNAL_DET)) {
4074                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4075                                             MAC_STATUS_CFG_CHANGED));
4076                         return 0;
4077                 }
4078         }
4079
4080         tw32_f(MAC_TX_AUTO_NEG, 0);
4081
4082         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
4083         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
4084         tw32_f(MAC_MODE, tp->mac_mode);
4085         udelay(40);
4086
4087         if (tp->phy_id == TG3_PHY_ID_BCM8002)
4088                 tg3_init_bcm8002(tp);
4089
4090         /* Enable link change event even when serdes polling.  */
4091         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4092         udelay(40);
4093
4094         current_link_up = 0;
4095         mac_status = tr32(MAC_STATUS);
4096
4097         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
4098                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4099         else
4100                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4101
4102         tp->napi[0].hw_status->status =
4103                 (SD_STATUS_UPDATED |
4104                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4105
4106         for (i = 0; i < 100; i++) {
4107                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4108                                     MAC_STATUS_CFG_CHANGED));
4109                 udelay(5);
4110                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4111                                          MAC_STATUS_CFG_CHANGED |
4112                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4113                         break;
4114         }
4115
4116         mac_status = tr32(MAC_STATUS);
4117         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4118                 current_link_up = 0;
4119                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4120                     tp->serdes_counter == 0) {
4121                         tw32_f(MAC_MODE, (tp->mac_mode |
4122                                           MAC_MODE_SEND_CONFIGS));
4123                         udelay(1);
4124                         tw32_f(MAC_MODE, tp->mac_mode);
4125                 }
4126         }
4127
4128         if (current_link_up == 1) {
4129                 tp->link_config.active_speed = SPEED_1000;
4130                 tp->link_config.active_duplex = DUPLEX_FULL;
4131                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4132                                     LED_CTRL_LNKLED_OVERRIDE |
4133                                     LED_CTRL_1000MBPS_ON));
4134         } else {
4135                 tp->link_config.active_speed = SPEED_INVALID;
4136                 tp->link_config.active_duplex = DUPLEX_INVALID;
4137                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4138                                     LED_CTRL_LNKLED_OVERRIDE |
4139                                     LED_CTRL_TRAFFIC_OVERRIDE));
4140         }
4141
4142         if (current_link_up != netif_carrier_ok(tp->dev)) {
4143                 if (current_link_up)
4144                         netif_carrier_on(tp->dev);
4145                 else
4146                         netif_carrier_off(tp->dev);
4147                 tg3_link_report(tp);
4148         } else {
4149                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4150                 if (orig_pause_cfg != now_pause_cfg ||
4151                     orig_active_speed != tp->link_config.active_speed ||
4152                     orig_active_duplex != tp->link_config.active_duplex)
4153                         tg3_link_report(tp);
4154         }
4155
4156         return 0;
4157 }
4158
4159 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4160 {
4161         int current_link_up, err = 0;
4162         u32 bmsr, bmcr;
4163         u16 current_speed;
4164         u8 current_duplex;
4165         u32 local_adv, remote_adv;
4166
4167         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4168         tw32_f(MAC_MODE, tp->mac_mode);
4169         udelay(40);
4170
4171         tw32(MAC_EVENT, 0);
4172
4173         tw32_f(MAC_STATUS,
4174              (MAC_STATUS_SYNC_CHANGED |
4175               MAC_STATUS_CFG_CHANGED |
4176               MAC_STATUS_MI_COMPLETION |
4177               MAC_STATUS_LNKSTATE_CHANGED));
4178         udelay(40);
4179
4180         if (force_reset)
4181                 tg3_phy_reset(tp);
4182
4183         current_link_up = 0;
4184         current_speed = SPEED_INVALID;
4185         current_duplex = DUPLEX_INVALID;
4186
4187         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4188         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4189         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4190                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4191                         bmsr |= BMSR_LSTATUS;
4192                 else
4193                         bmsr &= ~BMSR_LSTATUS;
4194         }
4195
4196         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4197
4198         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4199             (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4200                 /* do nothing, just check for link up at the end */
4201         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4202                 u32 adv, new_adv;
4203
4204                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4205                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4206                                   ADVERTISE_1000XPAUSE |
4207                                   ADVERTISE_1000XPSE_ASYM |
4208                                   ADVERTISE_SLCT);
4209
4210                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4211
4212                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4213                         new_adv |= ADVERTISE_1000XHALF;
4214                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4215                         new_adv |= ADVERTISE_1000XFULL;
4216
4217                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4218                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4219                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4220                         tg3_writephy(tp, MII_BMCR, bmcr);
4221
4222                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4223                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4224                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4225
4226                         return err;
4227                 }
4228         } else {
4229                 u32 new_bmcr;
4230
4231                 bmcr &= ~BMCR_SPEED1000;
4232                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4233
4234                 if (tp->link_config.duplex == DUPLEX_FULL)
4235                         new_bmcr |= BMCR_FULLDPLX;
4236
4237                 if (new_bmcr != bmcr) {
4238                         /* BMCR_SPEED1000 is a reserved bit that needs
4239                          * to be set on write.
4240                          */
4241                         new_bmcr |= BMCR_SPEED1000;
4242
4243                         /* Force a linkdown */
4244                         if (netif_carrier_ok(tp->dev)) {
4245                                 u32 adv;
4246
4247                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4248                                 adv &= ~(ADVERTISE_1000XFULL |
4249                                          ADVERTISE_1000XHALF |
4250                                          ADVERTISE_SLCT);
4251                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4252                                 tg3_writephy(tp, MII_BMCR, bmcr |
4253                                                            BMCR_ANRESTART |
4254                                                            BMCR_ANENABLE);
4255                                 udelay(10);
4256                                 netif_carrier_off(tp->dev);
4257                         }
4258                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4259                         bmcr = new_bmcr;
4260                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4261                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4262                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4263                             ASIC_REV_5714) {
4264                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4265                                         bmsr |= BMSR_LSTATUS;
4266                                 else
4267                                         bmsr &= ~BMSR_LSTATUS;
4268                         }
4269                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4270                 }
4271         }
4272
4273         if (bmsr & BMSR_LSTATUS) {
4274                 current_speed = SPEED_1000;
4275                 current_link_up = 1;
4276                 if (bmcr & BMCR_FULLDPLX)
4277                         current_duplex = DUPLEX_FULL;
4278                 else
4279                         current_duplex = DUPLEX_HALF;
4280
4281                 local_adv = 0;
4282                 remote_adv = 0;
4283
4284                 if (bmcr & BMCR_ANENABLE) {
4285                         u32 common;
4286
4287                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4288                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4289                         common = local_adv & remote_adv;
4290                         if (common & (ADVERTISE_1000XHALF |
4291                                       ADVERTISE_1000XFULL)) {
4292                                 if (common & ADVERTISE_1000XFULL)
4293                                         current_duplex = DUPLEX_FULL;
4294                                 else
4295                                         current_duplex = DUPLEX_HALF;
4296                         } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4297                                 /* Link is up via parallel detect */
4298                         } else {
4299                                 current_link_up = 0;
4300                         }
4301                 }
4302         }
4303
4304         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4305                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4306
4307         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4308         if (tp->link_config.active_duplex == DUPLEX_HALF)
4309                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4310
4311         tw32_f(MAC_MODE, tp->mac_mode);
4312         udelay(40);
4313
4314         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4315
4316         tp->link_config.active_speed = current_speed;
4317         tp->link_config.active_duplex = current_duplex;
4318
4319         if (current_link_up != netif_carrier_ok(tp->dev)) {
4320                 if (current_link_up)
4321                         netif_carrier_on(tp->dev);
4322                 else {
4323                         netif_carrier_off(tp->dev);
4324                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4325                 }
4326                 tg3_link_report(tp);
4327         }
4328         return err;
4329 }
4330
4331 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4332 {
4333         if (tp->serdes_counter) {
4334                 /* Give autoneg time to complete. */
4335                 tp->serdes_counter--;
4336                 return;
4337         }
4338
4339         if (!netif_carrier_ok(tp->dev) &&
4340             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4341                 u32 bmcr;
4342
4343                 tg3_readphy(tp, MII_BMCR, &bmcr);
4344                 if (bmcr & BMCR_ANENABLE) {
4345                         u32 phy1, phy2;
4346
4347                         /* Select shadow register 0x1f */
4348                         tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4349                         tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4350
4351                         /* Select expansion interrupt status register */
4352                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4353                                          MII_TG3_DSP_EXP1_INT_STAT);
4354                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4355                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4356
4357                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4358                                 /* We have signal detect and not receiving
4359                                  * config code words, link is up by parallel
4360                                  * detection.
4361                                  */
4362
4363                                 bmcr &= ~BMCR_ANENABLE;
4364                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4365                                 tg3_writephy(tp, MII_BMCR, bmcr);
4366                                 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4367                         }
4368                 }
4369         } else if (netif_carrier_ok(tp->dev) &&
4370                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4371                    (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4372                 u32 phy2;
4373
4374                 /* Select expansion interrupt status register */
4375                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4376                                  MII_TG3_DSP_EXP1_INT_STAT);
4377                 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4378                 if (phy2 & 0x20) {
4379                         u32 bmcr;
4380
4381                         /* Config code words received, turn on autoneg. */
4382                         tg3_readphy(tp, MII_BMCR, &bmcr);
4383                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4384
4385                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4386
4387                 }
4388         }
4389 }
4390
4391 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4392 {
4393         int err;
4394
4395         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4396                 err = tg3_setup_fiber_phy(tp, force_reset);
4397         else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4398                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4399         else
4400                 err = tg3_setup_copper_phy(tp, force_reset);
4401
4402         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4403                 u32 val, scale;
4404
4405                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4406                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4407                         scale = 65;
4408                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4409                         scale = 6;
4410                 else
4411                         scale = 12;
4412
4413                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4414                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4415                 tw32(GRC_MISC_CFG, val);
4416         }
4417
4418         if (tp->link_config.active_speed == SPEED_1000 &&
4419             tp->link_config.active_duplex == DUPLEX_HALF)
4420                 tw32(MAC_TX_LENGTHS,
4421                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4422                       (6 << TX_LENGTHS_IPG_SHIFT) |
4423                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4424         else
4425                 tw32(MAC_TX_LENGTHS,
4426                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4427                       (6 << TX_LENGTHS_IPG_SHIFT) |
4428                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4429
4430         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4431                 if (netif_carrier_ok(tp->dev)) {
4432                         tw32(HOSTCC_STAT_COAL_TICKS,
4433                              tp->coal.stats_block_coalesce_usecs);
4434                 } else {
4435                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4436                 }
4437         }
4438
4439         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4440                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4441                 if (!netif_carrier_ok(tp->dev))
4442                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4443                               tp->pwrmgmt_thresh;
4444                 else
4445                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4446                 tw32(PCIE_PWR_MGMT_THRESH, val);
4447         }
4448
4449         return err;
4450 }
4451
4452 static inline int tg3_irq_sync(struct tg3 *tp)
4453 {
4454         return tp->irq_sync;
4455 }
4456
4457 /* This is called whenever we suspect that the system chipset is re-
4458  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4459  * is bogus tx completions. We try to recover by setting the
4460  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4461  * in the workqueue.
4462  */
4463 static void tg3_tx_recover(struct tg3 *tp)
4464 {
4465         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4466                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4467
4468         netdev_warn(tp->dev,
4469                     "The system may be re-ordering memory-mapped I/O "
4470                     "cycles to the network device, attempting to recover. "
4471                     "Please report the problem to the driver maintainer "
4472                     "and include system chipset information.\n");
4473
4474         spin_lock(&tp->lock);
4475         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4476         spin_unlock(&tp->lock);
4477 }
4478
4479 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4480 {
4481         /* Tell compiler to fetch tx indices from memory. */
4482         barrier();
4483         return tnapi->tx_pending -
4484                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4485 }
4486
4487 /* Tigon3 never reports partial packet sends.  So we do not
4488  * need special logic to handle SKBs that have not had all
4489  * of their frags sent yet, like SunGEM does.
4490  */
4491 static void tg3_tx(struct tg3_napi *tnapi)
4492 {
4493         struct tg3 *tp = tnapi->tp;
4494         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4495         u32 sw_idx = tnapi->tx_cons;
4496         struct netdev_queue *txq;
4497         int index = tnapi - tp->napi;
4498
4499         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4500                 index--;
4501
4502         txq = netdev_get_tx_queue(tp->dev, index);
4503
4504         while (sw_idx != hw_idx) {
4505                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4506                 struct sk_buff *skb = ri->skb;
4507                 int i, tx_bug = 0;
4508
4509                 if (unlikely(skb == NULL)) {
4510                         tg3_tx_recover(tp);
4511                         return;
4512                 }
4513
4514                 pci_unmap_single(tp->pdev,
4515                                  dma_unmap_addr(ri, mapping),
4516                                  skb_headlen(skb),
4517                                  PCI_DMA_TODEVICE);
4518
4519                 ri->skb = NULL;
4520
4521                 sw_idx = NEXT_TX(sw_idx);
4522
4523                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4524                         ri = &tnapi->tx_buffers[sw_idx];
4525                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4526                                 tx_bug = 1;
4527
4528                         pci_unmap_page(tp->pdev,
4529                                        dma_unmap_addr(ri, mapping),
4530                                        skb_shinfo(skb)->frags[i].size,
4531                                        PCI_DMA_TODEVICE);
4532                         sw_idx = NEXT_TX(sw_idx);
4533                 }
4534
4535                 dev_kfree_skb(skb);
4536
4537                 if (unlikely(tx_bug)) {
4538                         tg3_tx_recover(tp);
4539                         return;
4540                 }
4541         }
4542
4543         tnapi->tx_cons = sw_idx;
4544
4545         /* Need to make the tx_cons update visible to tg3_start_xmit()
4546          * before checking for netif_queue_stopped().  Without the
4547          * memory barrier, there is a small possibility that tg3_start_xmit()
4548          * will miss it and cause the queue to be stopped forever.
4549          */
4550         smp_mb();
4551
4552         if (unlikely(netif_tx_queue_stopped(txq) &&
4553                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4554                 __netif_tx_lock(txq, smp_processor_id());
4555                 if (netif_tx_queue_stopped(txq) &&
4556                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4557                         netif_tx_wake_queue(txq);
4558                 __netif_tx_unlock(txq);
4559         }
4560 }
4561
4562 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4563 {
4564         if (!ri->skb)
4565                 return;
4566
4567         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4568                          map_sz, PCI_DMA_FROMDEVICE);
4569         dev_kfree_skb_any(ri->skb);
4570         ri->skb = NULL;
4571 }
4572
4573 /* Returns size of skb allocated or < 0 on error.
4574  *
4575  * We only need to fill in the address because the other members
4576  * of the RX descriptor are invariant, see tg3_init_rings.
4577  *
4578  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4579  * posting buffers we only dirty the first cache line of the RX
4580  * descriptor (containing the address).  Whereas for the RX status
4581  * buffers the cpu only reads the last cacheline of the RX descriptor
4582  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4583  */
4584 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4585                             u32 opaque_key, u32 dest_idx_unmasked)
4586 {
4587         struct tg3_rx_buffer_desc *desc;
4588         struct ring_info *map;
4589         struct sk_buff *skb;
4590         dma_addr_t mapping;
4591         int skb_size, dest_idx;
4592
4593         switch (opaque_key) {
4594         case RXD_OPAQUE_RING_STD:
4595                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4596                 desc = &tpr->rx_std[dest_idx];
4597                 map = &tpr->rx_std_buffers[dest_idx];
4598                 skb_size = tp->rx_pkt_map_sz;
4599                 break;
4600
4601         case RXD_OPAQUE_RING_JUMBO:
4602                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4603                 desc = &tpr->rx_jmb[dest_idx].std;
4604                 map = &tpr->rx_jmb_buffers[dest_idx];
4605                 skb_size = TG3_RX_JMB_MAP_SZ;
4606                 break;
4607
4608         default:
4609                 return -EINVAL;
4610         }
4611
4612         /* Do not overwrite any of the map or rp information
4613          * until we are sure we can commit to a new buffer.
4614          *
4615          * Callers depend upon this behavior and assume that
4616          * we leave everything unchanged if we fail.
4617          */
4618         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4619         if (skb == NULL)
4620                 return -ENOMEM;
4621
4622         skb_reserve(skb, tp->rx_offset);
4623
4624         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4625                                  PCI_DMA_FROMDEVICE);
4626         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4627                 dev_kfree_skb(skb);
4628                 return -EIO;
4629         }
4630
4631         map->skb = skb;
4632         dma_unmap_addr_set(map, mapping, mapping);
4633
4634         desc->addr_hi = ((u64)mapping >> 32);
4635         desc->addr_lo = ((u64)mapping & 0xffffffff);
4636
4637         return skb_size;
4638 }
4639
4640 /* We only need to move over in the address because the other
4641  * members of the RX descriptor are invariant.  See notes above
4642  * tg3_alloc_rx_skb for full details.
4643  */
4644 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4645                            struct tg3_rx_prodring_set *dpr,
4646                            u32 opaque_key, int src_idx,
4647                            u32 dest_idx_unmasked)
4648 {
4649         struct tg3 *tp = tnapi->tp;
4650         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4651         struct ring_info *src_map, *dest_map;
4652         struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
4653         int dest_idx;
4654
4655         switch (opaque_key) {
4656         case RXD_OPAQUE_RING_STD:
4657                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4658                 dest_desc = &dpr->rx_std[dest_idx];
4659                 dest_map = &dpr->rx_std_buffers[dest_idx];
4660                 src_desc = &spr->rx_std[src_idx];
4661                 src_map = &spr->rx_std_buffers[src_idx];
4662                 break;
4663
4664         case RXD_OPAQUE_RING_JUMBO:
4665                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4666                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4667                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4668                 src_desc = &spr->rx_jmb[src_idx].std;
4669                 src_map = &spr->rx_jmb_buffers[src_idx];
4670                 break;
4671
4672         default:
4673                 return;
4674         }
4675
4676         dest_map->skb = src_map->skb;
4677         dma_unmap_addr_set(dest_map, mapping,
4678                            dma_unmap_addr(src_map, mapping));
4679         dest_desc->addr_hi = src_desc->addr_hi;
4680         dest_desc->addr_lo = src_desc->addr_lo;
4681
4682         /* Ensure that the update to the skb happens after the physical
4683          * addresses have been transferred to the new BD location.
4684          */
4685         smp_wmb();
4686
4687         src_map->skb = NULL;
4688 }
4689
4690 /* The RX ring scheme is composed of multiple rings which post fresh
4691  * buffers to the chip, and one special ring the chip uses to report
4692  * status back to the host.
4693  *
4694  * The special ring reports the status of received packets to the
4695  * host.  The chip does not write into the original descriptor the
4696  * RX buffer was obtained from.  The chip simply takes the original
4697  * descriptor as provided by the host, updates the status and length
4698  * field, then writes this into the next status ring entry.
4699  *
4700  * Each ring the host uses to post buffers to the chip is described
4701  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4702  * it is first placed into the on-chip ram.  When the packet's length
4703  * is known, it walks down the TG3_BDINFO entries to select the ring.
4704  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4705  * which is within the range of the new packet's length is chosen.
4706  *
4707  * The "separate ring for rx status" scheme may sound queer, but it makes
4708  * sense from a cache coherency perspective.  If only the host writes
4709  * to the buffer post rings, and only the chip writes to the rx status
4710  * rings, then cache lines never move beyond shared-modified state.
4711  * If both the host and chip were to write into the same ring, cache line
4712  * eviction could occur since both entities want it in an exclusive state.
4713  */
4714 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4715 {
4716         struct tg3 *tp = tnapi->tp;
4717         u32 work_mask, rx_std_posted = 0;
4718         u32 std_prod_idx, jmb_prod_idx;
4719         u32 sw_idx = tnapi->rx_rcb_ptr;
4720         u16 hw_idx;
4721         int received;
4722         struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
4723
4724         hw_idx = *(tnapi->rx_rcb_prod_idx);
4725         /*
4726          * We need to order the read of hw_idx and the read of
4727          * the opaque cookie.
4728          */
4729         rmb();
4730         work_mask = 0;
4731         received = 0;
4732         std_prod_idx = tpr->rx_std_prod_idx;
4733         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4734         while (sw_idx != hw_idx && budget > 0) {
4735                 struct ring_info *ri;
4736                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4737                 unsigned int len;
4738                 struct sk_buff *skb;
4739                 dma_addr_t dma_addr;
4740                 u32 opaque_key, desc_idx, *post_ptr;
4741
4742                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4743                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4744                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4745                         ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4746                         dma_addr = dma_unmap_addr(ri, mapping);
4747                         skb = ri->skb;
4748                         post_ptr = &std_prod_idx;
4749                         rx_std_posted++;
4750                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4751                         ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4752                         dma_addr = dma_unmap_addr(ri, mapping);
4753                         skb = ri->skb;
4754                         post_ptr = &jmb_prod_idx;
4755                 } else
4756                         goto next_pkt_nopost;
4757
4758                 work_mask |= opaque_key;
4759
4760                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4761                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4762                 drop_it:
4763                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4764                                        desc_idx, *post_ptr);
4765                 drop_it_no_recycle:
4766                         /* Other statistics kept track of by card. */
4767                         tp->rx_dropped++;
4768                         goto next_pkt;
4769                 }
4770
4771                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4772                       ETH_FCS_LEN;
4773
4774                 if (len > TG3_RX_COPY_THRESH(tp)) {
4775                         int skb_size;
4776
4777                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4778                                                     *post_ptr);
4779                         if (skb_size < 0)
4780                                 goto drop_it;
4781
4782                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4783                                          PCI_DMA_FROMDEVICE);
4784
4785                         /* Ensure that the update to the skb happens
4786                          * after the usage of the old DMA mapping.
4787                          */
4788                         smp_wmb();
4789
4790                         ri->skb = NULL;
4791
4792                         skb_put(skb, len);
4793                 } else {
4794                         struct sk_buff *copy_skb;
4795
4796                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4797                                        desc_idx, *post_ptr);
4798
4799                         copy_skb = netdev_alloc_skb(tp->dev, len +
4800                                                     TG3_RAW_IP_ALIGN);
4801                         if (copy_skb == NULL)
4802                                 goto drop_it_no_recycle;
4803
4804                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4805                         skb_put(copy_skb, len);
4806                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4807                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4808                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4809
4810                         /* We'll reuse the original ring buffer. */
4811                         skb = copy_skb;
4812                 }
4813
4814                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4815                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4816                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4817                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4818                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4819                 else
4820                         skb_checksum_none_assert(skb);
4821
4822                 skb->protocol = eth_type_trans(skb, tp->dev);
4823
4824                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4825                     skb->protocol != htons(ETH_P_8021Q)) {
4826                         dev_kfree_skb(skb);
4827                         goto drop_it_no_recycle;
4828                 }
4829
4830                 if (desc->type_flags & RXD_FLAG_VLAN &&
4831                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
4832                         __vlan_hwaccel_put_tag(skb,
4833                                                desc->err_vlan & RXD_VLAN_MASK);
4834
4835                 napi_gro_receive(&tnapi->napi, skb);
4836
4837                 received++;
4838                 budget--;
4839
4840 next_pkt:
4841                 (*post_ptr)++;
4842
4843                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4844                         tpr->rx_std_prod_idx = std_prod_idx &
4845                                                tp->rx_std_ring_mask;
4846                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4847                                      tpr->rx_std_prod_idx);
4848                         work_mask &= ~RXD_OPAQUE_RING_STD;
4849                         rx_std_posted = 0;
4850                 }
4851 next_pkt_nopost:
4852                 sw_idx++;
4853                 sw_idx &= tp->rx_ret_ring_mask;
4854
4855                 /* Refresh hw_idx to see if there is new work */
4856                 if (sw_idx == hw_idx) {
4857                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4858                         rmb();
4859                 }
4860         }
4861
4862         /* ACK the status ring. */
4863         tnapi->rx_rcb_ptr = sw_idx;
4864         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4865
4866         /* Refill RX ring(s). */
4867         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4868                 if (work_mask & RXD_OPAQUE_RING_STD) {
4869                         tpr->rx_std_prod_idx = std_prod_idx &
4870                                                tp->rx_std_ring_mask;
4871                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4872                                      tpr->rx_std_prod_idx);
4873                 }
4874                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4875                         tpr->rx_jmb_prod_idx = jmb_prod_idx &
4876                                                tp->rx_jmb_ring_mask;
4877                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4878                                      tpr->rx_jmb_prod_idx);
4879                 }
4880                 mmiowb();
4881         } else if (work_mask) {
4882                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4883                  * updated before the producer indices can be updated.
4884                  */
4885                 smp_wmb();
4886
4887                 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
4888                 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
4889
4890                 if (tnapi != &tp->napi[1])
4891                         napi_schedule(&tp->napi[1].napi);
4892         }
4893
4894         return received;
4895 }
4896
4897 static void tg3_poll_link(struct tg3 *tp)
4898 {
4899         /* handle link change and other phy events */
4900         if (!(tp->tg3_flags &
4901               (TG3_FLAG_USE_LINKCHG_REG |
4902                TG3_FLAG_POLL_SERDES))) {
4903                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4904
4905                 if (sblk->status & SD_STATUS_LINK_CHG) {
4906                         sblk->status = SD_STATUS_UPDATED |
4907                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4908                         spin_lock(&tp->lock);
4909                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4910                                 tw32_f(MAC_STATUS,
4911                                      (MAC_STATUS_SYNC_CHANGED |
4912                                       MAC_STATUS_CFG_CHANGED |
4913                                       MAC_STATUS_MI_COMPLETION |
4914                                       MAC_STATUS_LNKSTATE_CHANGED));
4915                                 udelay(40);
4916                         } else
4917                                 tg3_setup_phy(tp, 0);
4918                         spin_unlock(&tp->lock);
4919                 }
4920         }
4921 }
4922
4923 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4924                                 struct tg3_rx_prodring_set *dpr,
4925                                 struct tg3_rx_prodring_set *spr)
4926 {
4927         u32 si, di, cpycnt, src_prod_idx;
4928         int i, err = 0;
4929
4930         while (1) {
4931                 src_prod_idx = spr->rx_std_prod_idx;
4932
4933                 /* Make sure updates to the rx_std_buffers[] entries and the
4934                  * standard producer index are seen in the correct order.
4935                  */
4936                 smp_rmb();
4937
4938                 if (spr->rx_std_cons_idx == src_prod_idx)
4939                         break;
4940
4941                 if (spr->rx_std_cons_idx < src_prod_idx)
4942                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4943                 else
4944                         cpycnt = tp->rx_std_ring_mask + 1 -
4945                                  spr->rx_std_cons_idx;
4946
4947                 cpycnt = min(cpycnt,
4948                              tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
4949
4950                 si = spr->rx_std_cons_idx;
4951                 di = dpr->rx_std_prod_idx;
4952
4953                 for (i = di; i < di + cpycnt; i++) {
4954                         if (dpr->rx_std_buffers[i].skb) {
4955                                 cpycnt = i - di;
4956                                 err = -ENOSPC;
4957                                 break;
4958                         }
4959                 }
4960
4961                 if (!cpycnt)
4962                         break;
4963
4964                 /* Ensure that updates to the rx_std_buffers ring and the
4965                  * shadowed hardware producer ring from tg3_recycle_skb() are
4966                  * ordered correctly WRT the skb check above.
4967                  */
4968                 smp_rmb();
4969
4970                 memcpy(&dpr->rx_std_buffers[di],
4971                        &spr->rx_std_buffers[si],
4972                        cpycnt * sizeof(struct ring_info));
4973
4974                 for (i = 0; i < cpycnt; i++, di++, si++) {
4975                         struct tg3_rx_buffer_desc *sbd, *dbd;
4976                         sbd = &spr->rx_std[si];
4977                         dbd = &dpr->rx_std[di];
4978                         dbd->addr_hi = sbd->addr_hi;
4979                         dbd->addr_lo = sbd->addr_lo;
4980                 }
4981
4982                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
4983                                        tp->rx_std_ring_mask;
4984                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
4985                                        tp->rx_std_ring_mask;
4986         }
4987
4988         while (1) {
4989                 src_prod_idx = spr->rx_jmb_prod_idx;
4990
4991                 /* Make sure updates to the rx_jmb_buffers[] entries and
4992                  * the jumbo producer index are seen in the correct order.
4993                  */
4994                 smp_rmb();
4995
4996                 if (spr->rx_jmb_cons_idx == src_prod_idx)
4997                         break;
4998
4999                 if (spr->rx_jmb_cons_idx < src_prod_idx)
5000                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
5001                 else
5002                         cpycnt = tp->rx_jmb_ring_mask + 1 -
5003                                  spr->rx_jmb_cons_idx;
5004
5005                 cpycnt = min(cpycnt,
5006                              tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
5007
5008                 si = spr->rx_jmb_cons_idx;
5009                 di = dpr->rx_jmb_prod_idx;
5010
5011                 for (i = di; i < di + cpycnt; i++) {
5012                         if (dpr->rx_jmb_buffers[i].skb) {
5013                                 cpycnt = i - di;
5014                                 err = -ENOSPC;
5015                                 break;
5016                         }
5017                 }
5018
5019                 if (!cpycnt)
5020                         break;
5021
5022                 /* Ensure that updates to the rx_jmb_buffers ring and the
5023                  * shadowed hardware producer ring from tg3_recycle_skb() are
5024                  * ordered correctly WRT the skb check above.
5025                  */
5026                 smp_rmb();
5027
5028                 memcpy(&dpr->rx_jmb_buffers[di],
5029                        &spr->rx_jmb_buffers[si],
5030                        cpycnt * sizeof(struct ring_info));
5031
5032                 for (i = 0; i < cpycnt; i++, di++, si++) {
5033                         struct tg3_rx_buffer_desc *sbd, *dbd;
5034                         sbd = &spr->rx_jmb[si].std;
5035                         dbd = &dpr->rx_jmb[di].std;
5036                         dbd->addr_hi = sbd->addr_hi;
5037                         dbd->addr_lo = sbd->addr_lo;
5038                 }
5039
5040                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
5041                                        tp->rx_jmb_ring_mask;
5042                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
5043                                        tp->rx_jmb_ring_mask;
5044         }
5045
5046         return err;
5047 }
5048
5049 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
5050 {
5051         struct tg3 *tp = tnapi->tp;
5052
5053         /* run TX completion thread */
5054         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
5055                 tg3_tx(tnapi);
5056                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5057                         return work_done;
5058         }
5059
5060         /* run RX thread, within the bounds set by NAPI.
5061          * All RX "locking" is done by ensuring outside
5062          * code synchronizes with tg3->napi.poll()
5063          */
5064         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
5065                 work_done += tg3_rx(tnapi, budget - work_done);
5066
5067         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
5068                 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
5069                 int i, err = 0;
5070                 u32 std_prod_idx = dpr->rx_std_prod_idx;
5071                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
5072
5073                 for (i = 1; i < tp->irq_cnt; i++)
5074                         err |= tg3_rx_prodring_xfer(tp, dpr,
5075                                                     &tp->napi[i].prodring);
5076
5077                 wmb();
5078
5079                 if (std_prod_idx != dpr->rx_std_prod_idx)
5080                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5081                                      dpr->rx_std_prod_idx);
5082
5083                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5084                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5085                                      dpr->rx_jmb_prod_idx);
5086
5087                 mmiowb();
5088
5089                 if (err)
5090                         tw32_f(HOSTCC_MODE, tp->coal_now);
5091         }
5092
5093         return work_done;
5094 }
5095
5096 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5097 {
5098         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5099         struct tg3 *tp = tnapi->tp;
5100         int work_done = 0;
5101         struct tg3_hw_status *sblk = tnapi->hw_status;
5102
5103         while (1) {
5104                 work_done = tg3_poll_work(tnapi, work_done, budget);
5105
5106                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5107                         goto tx_recovery;
5108
5109                 if (unlikely(work_done >= budget))
5110                         break;
5111
5112                 /* tp->last_tag is used in tg3_int_reenable() below
5113                  * to tell the hw how much work has been processed,
5114                  * so we must read it before checking for more work.
5115                  */
5116                 tnapi->last_tag = sblk->status_tag;
5117                 tnapi->last_irq_tag = tnapi->last_tag;
5118                 rmb();
5119
5120                 /* check for RX/TX work to do */
5121                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5122                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5123                         napi_complete(napi);
5124                         /* Reenable interrupts. */
5125                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5126                         mmiowb();
5127                         break;
5128                 }
5129         }
5130
5131         return work_done;
5132
5133 tx_recovery:
5134         /* work_done is guaranteed to be less than budget. */
5135         napi_complete(napi);
5136         schedule_work(&tp->reset_task);
5137         return work_done;
5138 }
5139
5140 static int tg3_poll(struct napi_struct *napi, int budget)
5141 {
5142         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5143         struct tg3 *tp = tnapi->tp;
5144         int work_done = 0;
5145         struct tg3_hw_status *sblk = tnapi->hw_status;
5146
5147         while (1) {
5148                 tg3_poll_link(tp);
5149
5150                 work_done = tg3_poll_work(tnapi, work_done, budget);
5151
5152                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5153                         goto tx_recovery;
5154
5155                 if (unlikely(work_done >= budget))
5156                         break;
5157
5158                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5159                         /* tp->last_tag is used in tg3_int_reenable() below
5160                          * to tell the hw how much work has been processed,
5161                          * so we must read it before checking for more work.
5162                          */
5163                         tnapi->last_tag = sblk->status_tag;
5164                         tnapi->last_irq_tag = tnapi->last_tag;
5165                         rmb();
5166                 } else
5167                         sblk->status &= ~SD_STATUS_UPDATED;
5168
5169                 if (likely(!tg3_has_work(tnapi))) {
5170                         napi_complete(napi);
5171                         tg3_int_reenable(tnapi);
5172                         break;
5173                 }
5174         }
5175
5176         return work_done;
5177
5178 tx_recovery:
5179         /* work_done is guaranteed to be less than budget. */
5180         napi_complete(napi);
5181         schedule_work(&tp->reset_task);
5182         return work_done;
5183 }
5184
5185 static void tg3_napi_disable(struct tg3 *tp)
5186 {
5187         int i;
5188
5189         for (i = tp->irq_cnt - 1; i >= 0; i--)
5190                 napi_disable(&tp->napi[i].napi);
5191 }
5192
5193 static void tg3_napi_enable(struct tg3 *tp)
5194 {
5195         int i;
5196
5197         for (i = 0; i < tp->irq_cnt; i++)
5198                 napi_enable(&tp->napi[i].napi);
5199 }
5200
5201 static void tg3_napi_init(struct tg3 *tp)
5202 {
5203         int i;
5204
5205         netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
5206         for (i = 1; i < tp->irq_cnt; i++)
5207                 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
5208 }
5209
5210 static void tg3_napi_fini(struct tg3 *tp)
5211 {
5212         int i;
5213
5214         for (i = 0; i < tp->irq_cnt; i++)
5215                 netif_napi_del(&tp->napi[i].napi);
5216 }
5217
5218 static inline void tg3_netif_stop(struct tg3 *tp)
5219 {
5220         tp->dev->trans_start = jiffies; /* prevent tx timeout */
5221         tg3_napi_disable(tp);
5222         netif_tx_disable(tp->dev);
5223 }
5224
5225 static inline void tg3_netif_start(struct tg3 *tp)
5226 {
5227         /* NOTE: unconditional netif_tx_wake_all_queues is only
5228          * appropriate so long as all callers are assured to
5229          * have free tx slots (such as after tg3_init_hw)
5230          */
5231         netif_tx_wake_all_queues(tp->dev);
5232
5233         tg3_napi_enable(tp);
5234         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
5235         tg3_enable_ints(tp);
5236 }
5237
5238 static void tg3_irq_quiesce(struct tg3 *tp)
5239 {
5240         int i;
5241
5242         BUG_ON(tp->irq_sync);
5243
5244         tp->irq_sync = 1;
5245         smp_mb();
5246
5247         for (i = 0; i < tp->irq_cnt; i++)
5248                 synchronize_irq(tp->napi[i].irq_vec);
5249 }
5250
5251 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5252  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5253  * with as well.  Most of the time, this is not necessary except when
5254  * shutting down the device.
5255  */
5256 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5257 {
5258         spin_lock_bh(&tp->lock);
5259         if (irq_sync)
5260                 tg3_irq_quiesce(tp);
5261 }
5262
5263 static inline void tg3_full_unlock(struct tg3 *tp)
5264 {
5265         spin_unlock_bh(&tp->lock);
5266 }
5267
5268 /* One-shot MSI handler - Chip automatically disables interrupt
5269  * after sending MSI so driver doesn't have to do it.
5270  */
5271 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5272 {
5273         struct tg3_napi *tnapi = dev_id;
5274         struct tg3 *tp = tnapi->tp;
5275
5276         prefetch(tnapi->hw_status);
5277         if (tnapi->rx_rcb)
5278                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5279
5280         if (likely(!tg3_irq_sync(tp)))
5281                 napi_schedule(&tnapi->napi);
5282
5283         return IRQ_HANDLED;
5284 }
5285
5286 /* MSI ISR - No need to check for interrupt sharing and no need to
5287  * flush status block and interrupt mailbox. PCI ordering rules
5288  * guarantee that MSI will arrive after the status block.
5289  */
5290 static irqreturn_t tg3_msi(int irq, void *dev_id)
5291 {
5292         struct tg3_napi *tnapi = dev_id;
5293         struct tg3 *tp = tnapi->tp;
5294
5295         prefetch(tnapi->hw_status);
5296         if (tnapi->rx_rcb)
5297                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5298         /*
5299          * Writing any value to intr-mbox-0 clears PCI INTA# and
5300          * chip-internal interrupt pending events.
5301          * Writing non-zero to intr-mbox-0 additional tells the
5302          * NIC to stop sending us irqs, engaging "in-intr-handler"
5303          * event coalescing.
5304          */
5305         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5306         if (likely(!tg3_irq_sync(tp)))
5307                 napi_schedule(&tnapi->napi);
5308
5309         return IRQ_RETVAL(1);
5310 }
5311
5312 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5313 {
5314         struct tg3_napi *tnapi = dev_id;
5315         struct tg3 *tp = tnapi->tp;
5316         struct tg3_hw_status *sblk = tnapi->hw_status;
5317         unsigned int handled = 1;
5318
5319         /* In INTx mode, it is possible for the interrupt to arrive at
5320          * the CPU before the status block posted prior to the interrupt.
5321          * Reading the PCI State register will confirm whether the
5322          * interrupt is ours and will flush the status block.
5323          */
5324         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5325                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5326                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5327                         handled = 0;
5328                         goto out;
5329                 }
5330         }
5331
5332         /*
5333          * Writing any value to intr-mbox-0 clears PCI INTA# and
5334          * chip-internal interrupt pending events.
5335          * Writing non-zero to intr-mbox-0 additional tells the
5336          * NIC to stop sending us irqs, engaging "in-intr-handler"
5337          * event coalescing.
5338          *
5339          * Flush the mailbox to de-assert the IRQ immediately to prevent
5340          * spurious interrupts.  The flush impacts performance but
5341          * excessive spurious interrupts can be worse in some cases.
5342          */
5343         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5344         if (tg3_irq_sync(tp))
5345                 goto out;
5346         sblk->status &= ~SD_STATUS_UPDATED;
5347         if (likely(tg3_has_work(tnapi))) {
5348                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5349                 napi_schedule(&tnapi->napi);
5350         } else {
5351                 /* No work, shared interrupt perhaps?  re-enable
5352                  * interrupts, and flush that PCI write
5353                  */
5354                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5355                                0x00000000);
5356         }
5357 out:
5358         return IRQ_RETVAL(handled);
5359 }
5360
5361 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5362 {
5363         struct tg3_napi *tnapi = dev_id;
5364         struct tg3 *tp = tnapi->tp;
5365         struct tg3_hw_status *sblk = tnapi->hw_status;
5366         unsigned int handled = 1;
5367
5368         /* In INTx mode, it is possible for the interrupt to arrive at
5369          * the CPU before the status block posted prior to the interrupt.
5370          * Reading the PCI State register will confirm whether the
5371          * interrupt is ours and will flush the status block.
5372          */
5373         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5374                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5375                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5376                         handled = 0;
5377                         goto out;
5378                 }
5379         }
5380
5381         /*
5382          * writing any value to intr-mbox-0 clears PCI INTA# and
5383          * chip-internal interrupt pending events.
5384          * writing non-zero to intr-mbox-0 additional tells the
5385          * NIC to stop sending us irqs, engaging "in-intr-handler"
5386          * event coalescing.
5387          *
5388          * Flush the mailbox to de-assert the IRQ immediately to prevent
5389          * spurious interrupts.  The flush impacts performance but
5390          * excessive spurious interrupts can be worse in some cases.
5391          */
5392         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5393
5394         /*
5395          * In a shared interrupt configuration, sometimes other devices'
5396          * interrupts will scream.  We record the current status tag here
5397          * so that the above check can report that the screaming interrupts
5398          * are unhandled.  Eventually they will be silenced.
5399          */
5400         tnapi->last_irq_tag = sblk->status_tag;
5401
5402         if (tg3_irq_sync(tp))
5403                 goto out;
5404
5405         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5406
5407         napi_schedule(&tnapi->napi);
5408
5409 out:
5410         return IRQ_RETVAL(handled);
5411 }
5412
5413 /* ISR for interrupt test */
5414 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5415 {
5416         struct tg3_napi *tnapi = dev_id;
5417         struct tg3 *tp = tnapi->tp;
5418         struct tg3_hw_status *sblk = tnapi->hw_status;
5419
5420         if ((sblk->status & SD_STATUS_UPDATED) ||
5421             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5422                 tg3_disable_ints(tp);
5423                 return IRQ_RETVAL(1);
5424         }
5425         return IRQ_RETVAL(0);
5426 }
5427
5428 static int tg3_init_hw(struct tg3 *, int);
5429 static int tg3_halt(struct tg3 *, int, int);
5430
5431 /* Restart hardware after configuration changes, self-test, etc.
5432  * Invoked with tp->lock held.
5433  */
5434 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5435         __releases(tp->lock)
5436         __acquires(tp->lock)
5437 {
5438         int err;
5439
5440         err = tg3_init_hw(tp, reset_phy);
5441         if (err) {
5442                 netdev_err(tp->dev,
5443                            "Failed to re-initialize device, aborting\n");
5444                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5445                 tg3_full_unlock(tp);
5446                 del_timer_sync(&tp->timer);
5447                 tp->irq_sync = 0;
5448                 tg3_napi_enable(tp);
5449                 dev_close(tp->dev);
5450                 tg3_full_lock(tp, 0);
5451         }
5452         return err;
5453 }
5454
5455 #ifdef CONFIG_NET_POLL_CONTROLLER
5456 static void tg3_poll_controller(struct net_device *dev)
5457 {
5458         int i;
5459         struct tg3 *tp = netdev_priv(dev);
5460
5461         for (i = 0; i < tp->irq_cnt; i++)
5462                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5463 }
5464 #endif
5465
5466 static void tg3_reset_task(struct work_struct *work)
5467 {
5468         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5469         int err;
5470         unsigned int restart_timer;
5471
5472         tg3_full_lock(tp, 0);
5473
5474         if (!netif_running(tp->dev)) {
5475                 tg3_full_unlock(tp);
5476                 return;
5477         }
5478
5479         tg3_full_unlock(tp);
5480
5481         tg3_phy_stop(tp);
5482
5483         tg3_netif_stop(tp);
5484
5485         tg3_full_lock(tp, 1);
5486
5487         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5488         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5489
5490         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5491                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5492                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5493                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5494                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5495         }
5496
5497         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5498         err = tg3_init_hw(tp, 1);
5499         if (err)
5500                 goto out;
5501
5502         tg3_netif_start(tp);
5503
5504         if (restart_timer)
5505                 mod_timer(&tp->timer, jiffies + 1);
5506
5507 out:
5508         tg3_full_unlock(tp);
5509
5510         if (!err)
5511                 tg3_phy_start(tp);
5512 }
5513
5514 static void tg3_dump_short_state(struct tg3 *tp)
5515 {
5516         netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5517                    tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5518         netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5519                    tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5520 }
5521
5522 static void tg3_tx_timeout(struct net_device *dev)
5523 {
5524         struct tg3 *tp = netdev_priv(dev);
5525
5526         if (netif_msg_tx_err(tp)) {
5527                 netdev_err(dev, "transmit timed out, resetting\n");
5528                 tg3_dump_short_state(tp);
5529         }
5530
5531         schedule_work(&tp->reset_task);
5532 }
5533
5534 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5535 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5536 {
5537         u32 base = (u32) mapping & 0xffffffff;
5538
5539         return (base > 0xffffdcc0) && (base + len + 8 < base);
5540 }
5541
5542 /* Test for DMA addresses > 40-bit */
5543 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5544                                           int len)
5545 {
5546 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5547         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5548                 return ((u64) mapping + len) > DMA_BIT_MASK(40);
5549         return 0;
5550 #else
5551         return 0;
5552 #endif
5553 }
5554
5555 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5556
5557 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5558 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5559                                        struct sk_buff *skb, u32 last_plus_one,
5560                                        u32 *start, u32 base_flags, u32 mss)
5561 {
5562         struct tg3 *tp = tnapi->tp;
5563         struct sk_buff *new_skb;
5564         dma_addr_t new_addr = 0;
5565         u32 entry = *start;
5566         int i, ret = 0;
5567
5568         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5569                 new_skb = skb_copy(skb, GFP_ATOMIC);
5570         else {
5571                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5572
5573                 new_skb = skb_copy_expand(skb,
5574                                           skb_headroom(skb) + more_headroom,
5575                                           skb_tailroom(skb), GFP_ATOMIC);
5576         }
5577
5578         if (!new_skb) {
5579                 ret = -1;
5580         } else {
5581                 /* New SKB is guaranteed to be linear. */
5582                 entry = *start;
5583                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5584                                           PCI_DMA_TODEVICE);
5585                 /* Make sure the mapping succeeded */
5586                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5587                         ret = -1;
5588                         dev_kfree_skb(new_skb);
5589                         new_skb = NULL;
5590
5591                 /* Make sure new skb does not cross any 4G boundaries.
5592                  * Drop the packet if it does.
5593                  */
5594                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5595                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5596                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5597                                          PCI_DMA_TODEVICE);
5598                         ret = -1;
5599                         dev_kfree_skb(new_skb);
5600                         new_skb = NULL;
5601                 } else {
5602                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5603                                     base_flags, 1 | (mss << 1));
5604                         *start = NEXT_TX(entry);
5605                 }
5606         }
5607
5608         /* Now clean up the sw ring entries. */
5609         i = 0;
5610         while (entry != last_plus_one) {
5611                 int len;
5612
5613                 if (i == 0)
5614                         len = skb_headlen(skb);
5615                 else
5616                         len = skb_shinfo(skb)->frags[i-1].size;
5617
5618                 pci_unmap_single(tp->pdev,
5619                                  dma_unmap_addr(&tnapi->tx_buffers[entry],
5620                                                 mapping),
5621                                  len, PCI_DMA_TODEVICE);
5622                 if (i == 0) {
5623                         tnapi->tx_buffers[entry].skb = new_skb;
5624                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5625                                            new_addr);
5626                 } else {
5627                         tnapi->tx_buffers[entry].skb = NULL;
5628                 }
5629                 entry = NEXT_TX(entry);
5630                 i++;
5631         }
5632
5633         dev_kfree_skb(skb);
5634
5635         return ret;
5636 }
5637
5638 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5639                         dma_addr_t mapping, int len, u32 flags,
5640                         u32 mss_and_is_end)
5641 {
5642         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5643         int is_end = (mss_and_is_end & 0x1);
5644         u32 mss = (mss_and_is_end >> 1);
5645         u32 vlan_tag = 0;
5646
5647         if (is_end)
5648                 flags |= TXD_FLAG_END;
5649         if (flags & TXD_FLAG_VLAN) {
5650                 vlan_tag = flags >> 16;
5651                 flags &= 0xffff;
5652         }
5653         vlan_tag |= (mss << TXD_MSS_SHIFT);
5654
5655         txd->addr_hi = ((u64) mapping >> 32);
5656         txd->addr_lo = ((u64) mapping & 0xffffffff);
5657         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5658         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5659 }
5660
5661 /* hard_start_xmit for devices that don't have any bugs and
5662  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5663  */
5664 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5665                                   struct net_device *dev)
5666 {
5667         struct tg3 *tp = netdev_priv(dev);
5668         u32 len, entry, base_flags, mss;
5669         dma_addr_t mapping;
5670         struct tg3_napi *tnapi;
5671         struct netdev_queue *txq;
5672         unsigned int i, last;
5673
5674         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5675         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5676         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5677                 tnapi++;
5678
5679         /* We are running in BH disabled context with netif_tx_lock
5680          * and TX reclaim runs via tp->napi.poll inside of a software
5681          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5682          * no IRQ context deadlocks to worry about either.  Rejoice!
5683          */
5684         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5685                 if (!netif_tx_queue_stopped(txq)) {
5686                         netif_tx_stop_queue(txq);
5687
5688                         /* This is a hard error, log it. */
5689                         netdev_err(dev,
5690                                    "BUG! Tx Ring full when queue awake!\n");
5691                 }
5692                 return NETDEV_TX_BUSY;
5693         }
5694
5695         entry = tnapi->tx_prod;
5696         base_flags = 0;
5697         mss = skb_shinfo(skb)->gso_size;
5698         if (mss) {
5699                 int tcp_opt_len, ip_tcp_len;
5700                 u32 hdrlen;
5701
5702                 if (skb_header_cloned(skb) &&
5703                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5704                         dev_kfree_skb(skb);
5705                         goto out_unlock;
5706                 }
5707
5708                 if (skb_is_gso_v6(skb)) {
5709                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5710                 } else {
5711                         struct iphdr *iph = ip_hdr(skb);
5712
5713                         tcp_opt_len = tcp_optlen(skb);
5714                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5715
5716                         iph->check = 0;
5717                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5718                         hdrlen = ip_tcp_len + tcp_opt_len;
5719                 }
5720
5721                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5722                         mss |= (hdrlen & 0xc) << 12;
5723                         if (hdrlen & 0x10)
5724                                 base_flags |= 0x00000010;
5725                         base_flags |= (hdrlen & 0x3e0) << 5;
5726                 } else
5727                         mss |= hdrlen << 9;
5728
5729                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5730                                TXD_FLAG_CPU_POST_DMA);
5731
5732                 tcp_hdr(skb)->check = 0;
5733
5734         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5735                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5736         }
5737
5738         if (vlan_tx_tag_present(skb))
5739                 base_flags |= (TXD_FLAG_VLAN |
5740                                (vlan_tx_tag_get(skb) << 16));
5741
5742         len = skb_headlen(skb);
5743
5744         /* Queue skb data, a.k.a. the main skb fragment. */
5745         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5746         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5747                 dev_kfree_skb(skb);
5748                 goto out_unlock;
5749         }
5750
5751         tnapi->tx_buffers[entry].skb = skb;
5752         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5753
5754         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5755             !mss && skb->len > VLAN_ETH_FRAME_LEN)
5756                 base_flags |= TXD_FLAG_JMB_PKT;
5757
5758         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5759                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5760
5761         entry = NEXT_TX(entry);
5762
5763         /* Now loop through additional data fragments, and queue them. */
5764         if (skb_shinfo(s