tg3: Add TSO loopback test
[linux-2.6.git] / drivers / net / tg3.c
1 /*
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  * Copyright (C) 2005-2011 Broadcom Corporation.
8  *
9  * Firmware is:
10  *      Derived from proprietary unpublished source code,
11  *      Copyright (C) 2000-2003 Broadcom Corporation.
12  *
13  *      Permission is hereby granted for the distribution of this firmware
14  *      data in hexadecimal or equivalent format, provided this copyright
15  *      notice is accompanying it.
16  */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/in.h>
28 #include <linux/init.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mdio.h>
36 #include <linux/mii.h>
37 #include <linux/phy.h>
38 #include <linux/brcmphy.h>
39 #include <linux/if_vlan.h>
40 #include <linux/ip.h>
41 #include <linux/tcp.h>
42 #include <linux/workqueue.h>
43 #include <linux/prefetch.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/firmware.h>
46
47 #include <net/checksum.h>
48 #include <net/ip.h>
49
50 #include <asm/system.h>
51 #include <linux/io.h>
52 #include <asm/byteorder.h>
53 #include <linux/uaccess.h>
54
55 #ifdef CONFIG_SPARC
56 #include <asm/idprom.h>
57 #include <asm/prom.h>
58 #endif
59
60 #define BAR_0   0
61 #define BAR_2   2
62
63 #include "tg3.h"
64
65 #define DRV_MODULE_NAME         "tg3"
66 #define TG3_MAJ_NUM                     3
67 #define TG3_MIN_NUM                     117
68 #define DRV_MODULE_VERSION      \
69         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
70 #define DRV_MODULE_RELDATE      "January 25, 2011"
71
72 #define TG3_DEF_MAC_MODE        0
73 #define TG3_DEF_RX_MODE         0
74 #define TG3_DEF_TX_MODE         0
75 #define TG3_DEF_MSG_ENABLE        \
76         (NETIF_MSG_DRV          | \
77          NETIF_MSG_PROBE        | \
78          NETIF_MSG_LINK         | \
79          NETIF_MSG_TIMER        | \
80          NETIF_MSG_IFDOWN       | \
81          NETIF_MSG_IFUP         | \
82          NETIF_MSG_RX_ERR       | \
83          NETIF_MSG_TX_ERR)
84
85 /* length of time before we decide the hardware is borked,
86  * and dev->tx_timeout() should be called to fix the problem
87  */
88 #define TG3_TX_TIMEOUT                  (5 * HZ)
89
90 /* hardware minimum and maximum for a single frame's data payload */
91 #define TG3_MIN_MTU                     60
92 #define TG3_MAX_MTU(tp) \
93         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
94
95 /* These numbers seem to be hard coded in the NIC firmware somehow.
96  * You can't change the ring sizes, but you can change where you place
97  * them in the NIC onboard memory.
98  */
99 #define TG3_RX_STD_RING_SIZE(tp) \
100         ((tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) ? \
101          TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
102 #define TG3_DEF_RX_RING_PENDING         200
103 #define TG3_RX_JMB_RING_SIZE(tp) \
104         ((tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) ? \
105          TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
106 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
107 #define TG3_RSS_INDIR_TBL_SIZE          128
108
109 /* Do not place this n-ring entries value into the tp struct itself,
110  * we really want to expose these constants to GCC so that modulo et
111  * al.  operations are done with shifts and masks instead of with
112  * hw multiply/modulo instructions.  Another solution would be to
113  * replace things like '% foo' with '& (foo - 1)'.
114  */
115
116 #define TG3_TX_RING_SIZE                512
117 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
118
119 #define TG3_RX_STD_RING_BYTES(tp) \
120         (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
121 #define TG3_RX_JMB_RING_BYTES(tp) \
122         (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
123 #define TG3_RX_RCB_RING_BYTES(tp) \
124         (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
125 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
126                                  TG3_TX_RING_SIZE)
127 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
128
129 #define TG3_DMA_BYTE_ENAB               64
130
131 #define TG3_RX_STD_DMA_SZ               1536
132 #define TG3_RX_JMB_DMA_SZ               9046
133
134 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
135
136 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
137 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
138
139 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
140         (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
141
142 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
143         (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
144
145 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
146  * that are at least dword aligned when used in PCIX mode.  The driver
147  * works around this bug by double copying the packet.  This workaround
148  * is built into the normal double copy length check for efficiency.
149  *
150  * However, the double copy is only necessary on those architectures
151  * where unaligned memory accesses are inefficient.  For those architectures
152  * where unaligned memory accesses incur little penalty, we can reintegrate
153  * the 5701 in the normal rx path.  Doing so saves a device structure
154  * dereference by hardcoding the double copy threshold in place.
155  */
156 #define TG3_RX_COPY_THRESHOLD           256
157 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
158         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
159 #else
160         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
161 #endif
162
163 /* minimum number of free TX descriptors required to wake up TX process */
164 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
165
166 #define TG3_RAW_IP_ALIGN 2
167
168 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
169
170 #define FIRMWARE_TG3            "tigon/tg3.bin"
171 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
172 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
173
174 static char version[] __devinitdata =
175         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
176
177 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
178 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
179 MODULE_LICENSE("GPL");
180 MODULE_VERSION(DRV_MODULE_VERSION);
181 MODULE_FIRMWARE(FIRMWARE_TG3);
182 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
183 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
184
185 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
186 module_param(tg3_debug, int, 0);
187 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
188
189 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
263         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
264         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
265         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
266         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
267         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
268         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
269         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
270         {}
271 };
272
273 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
274
275 static const struct {
276         const char string[ETH_GSTRING_LEN];
277 } ethtool_stats_keys[] = {
278         { "rx_octets" },
279         { "rx_fragments" },
280         { "rx_ucast_packets" },
281         { "rx_mcast_packets" },
282         { "rx_bcast_packets" },
283         { "rx_fcs_errors" },
284         { "rx_align_errors" },
285         { "rx_xon_pause_rcvd" },
286         { "rx_xoff_pause_rcvd" },
287         { "rx_mac_ctrl_rcvd" },
288         { "rx_xoff_entered" },
289         { "rx_frame_too_long_errors" },
290         { "rx_jabbers" },
291         { "rx_undersize_packets" },
292         { "rx_in_length_errors" },
293         { "rx_out_length_errors" },
294         { "rx_64_or_less_octet_packets" },
295         { "rx_65_to_127_octet_packets" },
296         { "rx_128_to_255_octet_packets" },
297         { "rx_256_to_511_octet_packets" },
298         { "rx_512_to_1023_octet_packets" },
299         { "rx_1024_to_1522_octet_packets" },
300         { "rx_1523_to_2047_octet_packets" },
301         { "rx_2048_to_4095_octet_packets" },
302         { "rx_4096_to_8191_octet_packets" },
303         { "rx_8192_to_9022_octet_packets" },
304
305         { "tx_octets" },
306         { "tx_collisions" },
307
308         { "tx_xon_sent" },
309         { "tx_xoff_sent" },
310         { "tx_flow_control" },
311         { "tx_mac_errors" },
312         { "tx_single_collisions" },
313         { "tx_mult_collisions" },
314         { "tx_deferred" },
315         { "tx_excessive_collisions" },
316         { "tx_late_collisions" },
317         { "tx_collide_2times" },
318         { "tx_collide_3times" },
319         { "tx_collide_4times" },
320         { "tx_collide_5times" },
321         { "tx_collide_6times" },
322         { "tx_collide_7times" },
323         { "tx_collide_8times" },
324         { "tx_collide_9times" },
325         { "tx_collide_10times" },
326         { "tx_collide_11times" },
327         { "tx_collide_12times" },
328         { "tx_collide_13times" },
329         { "tx_collide_14times" },
330         { "tx_collide_15times" },
331         { "tx_ucast_packets" },
332         { "tx_mcast_packets" },
333         { "tx_bcast_packets" },
334         { "tx_carrier_sense_errors" },
335         { "tx_discards" },
336         { "tx_errors" },
337
338         { "dma_writeq_full" },
339         { "dma_write_prioq_full" },
340         { "rxbds_empty" },
341         { "rx_discards" },
342         { "mbuf_lwm_thresh_hit" },
343         { "rx_errors" },
344         { "rx_threshold_hit" },
345
346         { "dma_readq_full" },
347         { "dma_read_prioq_full" },
348         { "tx_comp_queue_full" },
349
350         { "ring_set_send_prod_index" },
351         { "ring_status_update" },
352         { "nic_irqs" },
353         { "nic_avoided_irqs" },
354         { "nic_tx_threshold_hit" }
355 };
356
357 #define TG3_NUM_STATS   ARRAY_SIZE(ethtool_stats_keys)
358
359
360 static const struct {
361         const char string[ETH_GSTRING_LEN];
362 } ethtool_test_keys[] = {
363         { "nvram test     (online) " },
364         { "link test      (online) " },
365         { "register test  (offline)" },
366         { "memory test    (offline)" },
367         { "loopback test  (offline)" },
368         { "interrupt test (offline)" },
369 };
370
371 #define TG3_NUM_TEST    ARRAY_SIZE(ethtool_test_keys)
372
373
374 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
375 {
376         writel(val, tp->regs + off);
377 }
378
379 static u32 tg3_read32(struct tg3 *tp, u32 off)
380 {
381         return readl(tp->regs + off);
382 }
383
384 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
385 {
386         writel(val, tp->aperegs + off);
387 }
388
389 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
390 {
391         return readl(tp->aperegs + off);
392 }
393
394 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
395 {
396         unsigned long flags;
397
398         spin_lock_irqsave(&tp->indirect_lock, flags);
399         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
400         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
401         spin_unlock_irqrestore(&tp->indirect_lock, flags);
402 }
403
404 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
405 {
406         writel(val, tp->regs + off);
407         readl(tp->regs + off);
408 }
409
410 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
411 {
412         unsigned long flags;
413         u32 val;
414
415         spin_lock_irqsave(&tp->indirect_lock, flags);
416         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
417         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
418         spin_unlock_irqrestore(&tp->indirect_lock, flags);
419         return val;
420 }
421
422 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
423 {
424         unsigned long flags;
425
426         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
427                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
428                                        TG3_64BIT_REG_LOW, val);
429                 return;
430         }
431         if (off == TG3_RX_STD_PROD_IDX_REG) {
432                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
433                                        TG3_64BIT_REG_LOW, val);
434                 return;
435         }
436
437         spin_lock_irqsave(&tp->indirect_lock, flags);
438         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
439         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
440         spin_unlock_irqrestore(&tp->indirect_lock, flags);
441
442         /* In indirect mode when disabling interrupts, we also need
443          * to clear the interrupt bit in the GRC local ctrl register.
444          */
445         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
446             (val == 0x1)) {
447                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
448                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
449         }
450 }
451
452 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
453 {
454         unsigned long flags;
455         u32 val;
456
457         spin_lock_irqsave(&tp->indirect_lock, flags);
458         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
459         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
460         spin_unlock_irqrestore(&tp->indirect_lock, flags);
461         return val;
462 }
463
464 /* usec_wait specifies the wait time in usec when writing to certain registers
465  * where it is unsafe to read back the register without some delay.
466  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
467  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
468  */
469 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
470 {
471         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
472             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
473                 /* Non-posted methods */
474                 tp->write32(tp, off, val);
475         else {
476                 /* Posted method */
477                 tg3_write32(tp, off, val);
478                 if (usec_wait)
479                         udelay(usec_wait);
480                 tp->read32(tp, off);
481         }
482         /* Wait again after the read for the posted method to guarantee that
483          * the wait time is met.
484          */
485         if (usec_wait)
486                 udelay(usec_wait);
487 }
488
489 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
490 {
491         tp->write32_mbox(tp, off, val);
492         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
493             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
494                 tp->read32_mbox(tp, off);
495 }
496
497 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
498 {
499         void __iomem *mbox = tp->regs + off;
500         writel(val, mbox);
501         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
502                 writel(val, mbox);
503         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
504                 readl(mbox);
505 }
506
507 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
508 {
509         return readl(tp->regs + off + GRCMBOX_BASE);
510 }
511
512 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
513 {
514         writel(val, tp->regs + off + GRCMBOX_BASE);
515 }
516
517 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
518 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
519 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
520 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
521 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
522
523 #define tw32(reg, val)                  tp->write32(tp, reg, val)
524 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
525 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
526 #define tr32(reg)                       tp->read32(tp, reg)
527
528 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
529 {
530         unsigned long flags;
531
532         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
533             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
534                 return;
535
536         spin_lock_irqsave(&tp->indirect_lock, flags);
537         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
538                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
539                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
540
541                 /* Always leave this as zero. */
542                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
543         } else {
544                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
545                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
546
547                 /* Always leave this as zero. */
548                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
549         }
550         spin_unlock_irqrestore(&tp->indirect_lock, flags);
551 }
552
553 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
554 {
555         unsigned long flags;
556
557         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
558             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
559                 *val = 0;
560                 return;
561         }
562
563         spin_lock_irqsave(&tp->indirect_lock, flags);
564         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
565                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
566                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
567
568                 /* Always leave this as zero. */
569                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
570         } else {
571                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
572                 *val = tr32(TG3PCI_MEM_WIN_DATA);
573
574                 /* Always leave this as zero. */
575                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
576         }
577         spin_unlock_irqrestore(&tp->indirect_lock, flags);
578 }
579
580 static void tg3_ape_lock_init(struct tg3 *tp)
581 {
582         int i;
583         u32 regbase;
584
585         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
586                 regbase = TG3_APE_LOCK_GRANT;
587         else
588                 regbase = TG3_APE_PER_LOCK_GRANT;
589
590         /* Make sure the driver hasn't any stale locks. */
591         for (i = 0; i < 8; i++)
592                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
593 }
594
595 static int tg3_ape_lock(struct tg3 *tp, int locknum)
596 {
597         int i, off;
598         int ret = 0;
599         u32 status, req, gnt;
600
601         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
602                 return 0;
603
604         switch (locknum) {
605         case TG3_APE_LOCK_GRC:
606         case TG3_APE_LOCK_MEM:
607                 break;
608         default:
609                 return -EINVAL;
610         }
611
612         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
613                 req = TG3_APE_LOCK_REQ;
614                 gnt = TG3_APE_LOCK_GRANT;
615         } else {
616                 req = TG3_APE_PER_LOCK_REQ;
617                 gnt = TG3_APE_PER_LOCK_GRANT;
618         }
619
620         off = 4 * locknum;
621
622         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
623
624         /* Wait for up to 1 millisecond to acquire lock. */
625         for (i = 0; i < 100; i++) {
626                 status = tg3_ape_read32(tp, gnt + off);
627                 if (status == APE_LOCK_GRANT_DRIVER)
628                         break;
629                 udelay(10);
630         }
631
632         if (status != APE_LOCK_GRANT_DRIVER) {
633                 /* Revoke the lock request. */
634                 tg3_ape_write32(tp, gnt + off,
635                                 APE_LOCK_GRANT_DRIVER);
636
637                 ret = -EBUSY;
638         }
639
640         return ret;
641 }
642
643 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
644 {
645         u32 gnt;
646
647         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
648                 return;
649
650         switch (locknum) {
651         case TG3_APE_LOCK_GRC:
652         case TG3_APE_LOCK_MEM:
653                 break;
654         default:
655                 return;
656         }
657
658         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
659                 gnt = TG3_APE_LOCK_GRANT;
660         else
661                 gnt = TG3_APE_PER_LOCK_GRANT;
662
663         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
664 }
665
666 static void tg3_disable_ints(struct tg3 *tp)
667 {
668         int i;
669
670         tw32(TG3PCI_MISC_HOST_CTRL,
671              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
672         for (i = 0; i < tp->irq_max; i++)
673                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
674 }
675
676 static void tg3_enable_ints(struct tg3 *tp)
677 {
678         int i;
679
680         tp->irq_sync = 0;
681         wmb();
682
683         tw32(TG3PCI_MISC_HOST_CTRL,
684              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
685
686         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
687         for (i = 0; i < tp->irq_cnt; i++) {
688                 struct tg3_napi *tnapi = &tp->napi[i];
689
690                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
691                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
692                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
693
694                 tp->coal_now |= tnapi->coal_now;
695         }
696
697         /* Force an initial interrupt */
698         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
699             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
700                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
701         else
702                 tw32(HOSTCC_MODE, tp->coal_now);
703
704         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
705 }
706
707 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
708 {
709         struct tg3 *tp = tnapi->tp;
710         struct tg3_hw_status *sblk = tnapi->hw_status;
711         unsigned int work_exists = 0;
712
713         /* check for phy events */
714         if (!(tp->tg3_flags &
715               (TG3_FLAG_USE_LINKCHG_REG |
716                TG3_FLAG_POLL_SERDES))) {
717                 if (sblk->status & SD_STATUS_LINK_CHG)
718                         work_exists = 1;
719         }
720         /* check for RX/TX work to do */
721         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
722             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
723                 work_exists = 1;
724
725         return work_exists;
726 }
727
728 /* tg3_int_reenable
729  *  similar to tg3_enable_ints, but it accurately determines whether there
730  *  is new work pending and can return without flushing the PIO write
731  *  which reenables interrupts
732  */
733 static void tg3_int_reenable(struct tg3_napi *tnapi)
734 {
735         struct tg3 *tp = tnapi->tp;
736
737         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
738         mmiowb();
739
740         /* When doing tagged status, this work check is unnecessary.
741          * The last_tag we write above tells the chip which piece of
742          * work we've completed.
743          */
744         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
745             tg3_has_work(tnapi))
746                 tw32(HOSTCC_MODE, tp->coalesce_mode |
747                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
748 }
749
750 static void tg3_switch_clocks(struct tg3 *tp)
751 {
752         u32 clock_ctrl;
753         u32 orig_clock_ctrl;
754
755         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
756             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
757                 return;
758
759         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
760
761         orig_clock_ctrl = clock_ctrl;
762         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
763                        CLOCK_CTRL_CLKRUN_OENABLE |
764                        0x1f);
765         tp->pci_clock_ctrl = clock_ctrl;
766
767         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
768                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
769                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
770                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
771                 }
772         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
773                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
774                             clock_ctrl |
775                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
776                             40);
777                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
778                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
779                             40);
780         }
781         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
782 }
783
784 #define PHY_BUSY_LOOPS  5000
785
786 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
787 {
788         u32 frame_val;
789         unsigned int loops;
790         int ret;
791
792         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
793                 tw32_f(MAC_MI_MODE,
794                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
795                 udelay(80);
796         }
797
798         *val = 0x0;
799
800         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
801                       MI_COM_PHY_ADDR_MASK);
802         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
803                       MI_COM_REG_ADDR_MASK);
804         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
805
806         tw32_f(MAC_MI_COM, frame_val);
807
808         loops = PHY_BUSY_LOOPS;
809         while (loops != 0) {
810                 udelay(10);
811                 frame_val = tr32(MAC_MI_COM);
812
813                 if ((frame_val & MI_COM_BUSY) == 0) {
814                         udelay(5);
815                         frame_val = tr32(MAC_MI_COM);
816                         break;
817                 }
818                 loops -= 1;
819         }
820
821         ret = -EBUSY;
822         if (loops != 0) {
823                 *val = frame_val & MI_COM_DATA_MASK;
824                 ret = 0;
825         }
826
827         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
828                 tw32_f(MAC_MI_MODE, tp->mi_mode);
829                 udelay(80);
830         }
831
832         return ret;
833 }
834
835 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
836 {
837         u32 frame_val;
838         unsigned int loops;
839         int ret;
840
841         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
842             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
843                 return 0;
844
845         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
846                 tw32_f(MAC_MI_MODE,
847                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
848                 udelay(80);
849         }
850
851         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
852                       MI_COM_PHY_ADDR_MASK);
853         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
854                       MI_COM_REG_ADDR_MASK);
855         frame_val |= (val & MI_COM_DATA_MASK);
856         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
857
858         tw32_f(MAC_MI_COM, frame_val);
859
860         loops = PHY_BUSY_LOOPS;
861         while (loops != 0) {
862                 udelay(10);
863                 frame_val = tr32(MAC_MI_COM);
864                 if ((frame_val & MI_COM_BUSY) == 0) {
865                         udelay(5);
866                         frame_val = tr32(MAC_MI_COM);
867                         break;
868                 }
869                 loops -= 1;
870         }
871
872         ret = -EBUSY;
873         if (loops != 0)
874                 ret = 0;
875
876         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
877                 tw32_f(MAC_MI_MODE, tp->mi_mode);
878                 udelay(80);
879         }
880
881         return ret;
882 }
883
884 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
885 {
886         int err;
887
888         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
889         if (err)
890                 goto done;
891
892         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
893         if (err)
894                 goto done;
895
896         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
897                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
898         if (err)
899                 goto done;
900
901         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
902
903 done:
904         return err;
905 }
906
907 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
908 {
909         int err;
910
911         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
912         if (err)
913                 goto done;
914
915         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
916         if (err)
917                 goto done;
918
919         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
920                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
921         if (err)
922                 goto done;
923
924         err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
925
926 done:
927         return err;
928 }
929
930 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
931 {
932         int err;
933
934         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
935         if (!err)
936                 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
937
938         return err;
939 }
940
941 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
942 {
943         int err;
944
945         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
946         if (!err)
947                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
948
949         return err;
950 }
951
952 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
953 {
954         int err;
955
956         err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
957                            (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
958                            MII_TG3_AUXCTL_SHDWSEL_MISC);
959         if (!err)
960                 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
961
962         return err;
963 }
964
965 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
966 {
967         if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
968                 set |= MII_TG3_AUXCTL_MISC_WREN;
969
970         return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
971 }
972
973 #define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \
974         tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
975                              MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \
976                              MII_TG3_AUXCTL_ACTL_TX_6DB)
977
978 #define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \
979         tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
980                              MII_TG3_AUXCTL_ACTL_TX_6DB);
981
982 static int tg3_bmcr_reset(struct tg3 *tp)
983 {
984         u32 phy_control;
985         int limit, err;
986
987         /* OK, reset it, and poll the BMCR_RESET bit until it
988          * clears or we time out.
989          */
990         phy_control = BMCR_RESET;
991         err = tg3_writephy(tp, MII_BMCR, phy_control);
992         if (err != 0)
993                 return -EBUSY;
994
995         limit = 5000;
996         while (limit--) {
997                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
998                 if (err != 0)
999                         return -EBUSY;
1000
1001                 if ((phy_control & BMCR_RESET) == 0) {
1002                         udelay(40);
1003                         break;
1004                 }
1005                 udelay(10);
1006         }
1007         if (limit < 0)
1008                 return -EBUSY;
1009
1010         return 0;
1011 }
1012
1013 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1014 {
1015         struct tg3 *tp = bp->priv;
1016         u32 val;
1017
1018         spin_lock_bh(&tp->lock);
1019
1020         if (tg3_readphy(tp, reg, &val))
1021                 val = -EIO;
1022
1023         spin_unlock_bh(&tp->lock);
1024
1025         return val;
1026 }
1027
1028 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1029 {
1030         struct tg3 *tp = bp->priv;
1031         u32 ret = 0;
1032
1033         spin_lock_bh(&tp->lock);
1034
1035         if (tg3_writephy(tp, reg, val))
1036                 ret = -EIO;
1037
1038         spin_unlock_bh(&tp->lock);
1039
1040         return ret;
1041 }
1042
1043 static int tg3_mdio_reset(struct mii_bus *bp)
1044 {
1045         return 0;
1046 }
1047
1048 static void tg3_mdio_config_5785(struct tg3 *tp)
1049 {
1050         u32 val;
1051         struct phy_device *phydev;
1052
1053         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1054         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1055         case PHY_ID_BCM50610:
1056         case PHY_ID_BCM50610M:
1057                 val = MAC_PHYCFG2_50610_LED_MODES;
1058                 break;
1059         case PHY_ID_BCMAC131:
1060                 val = MAC_PHYCFG2_AC131_LED_MODES;
1061                 break;
1062         case PHY_ID_RTL8211C:
1063                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1064                 break;
1065         case PHY_ID_RTL8201E:
1066                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1067                 break;
1068         default:
1069                 return;
1070         }
1071
1072         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1073                 tw32(MAC_PHYCFG2, val);
1074
1075                 val = tr32(MAC_PHYCFG1);
1076                 val &= ~(MAC_PHYCFG1_RGMII_INT |
1077                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1078                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1079                 tw32(MAC_PHYCFG1, val);
1080
1081                 return;
1082         }
1083
1084         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
1085                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1086                        MAC_PHYCFG2_FMODE_MASK_MASK |
1087                        MAC_PHYCFG2_GMODE_MASK_MASK |
1088                        MAC_PHYCFG2_ACT_MASK_MASK   |
1089                        MAC_PHYCFG2_QUAL_MASK_MASK |
1090                        MAC_PHYCFG2_INBAND_ENABLE;
1091
1092         tw32(MAC_PHYCFG2, val);
1093
1094         val = tr32(MAC_PHYCFG1);
1095         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1096                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1097         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1098                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1099                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1100                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1101                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1102         }
1103         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1104                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1105         tw32(MAC_PHYCFG1, val);
1106
1107         val = tr32(MAC_EXT_RGMII_MODE);
1108         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1109                  MAC_RGMII_MODE_RX_QUALITY |
1110                  MAC_RGMII_MODE_RX_ACTIVITY |
1111                  MAC_RGMII_MODE_RX_ENG_DET |
1112                  MAC_RGMII_MODE_TX_ENABLE |
1113                  MAC_RGMII_MODE_TX_LOWPWR |
1114                  MAC_RGMII_MODE_TX_RESET);
1115         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1116                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1117                         val |= MAC_RGMII_MODE_RX_INT_B |
1118                                MAC_RGMII_MODE_RX_QUALITY |
1119                                MAC_RGMII_MODE_RX_ACTIVITY |
1120                                MAC_RGMII_MODE_RX_ENG_DET;
1121                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1122                         val |= MAC_RGMII_MODE_TX_ENABLE |
1123                                MAC_RGMII_MODE_TX_LOWPWR |
1124                                MAC_RGMII_MODE_TX_RESET;
1125         }
1126         tw32(MAC_EXT_RGMII_MODE, val);
1127 }
1128
1129 static void tg3_mdio_start(struct tg3 *tp)
1130 {
1131         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1132         tw32_f(MAC_MI_MODE, tp->mi_mode);
1133         udelay(80);
1134
1135         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1136             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1137                 tg3_mdio_config_5785(tp);
1138 }
1139
1140 static int tg3_mdio_init(struct tg3 *tp)
1141 {
1142         int i;
1143         u32 reg;
1144         struct phy_device *phydev;
1145
1146         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
1147                 u32 is_serdes;
1148
1149                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1150
1151                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1152                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1153                 else
1154                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1155                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1156                 if (is_serdes)
1157                         tp->phy_addr += 7;
1158         } else
1159                 tp->phy_addr = TG3_PHY_MII_ADDR;
1160
1161         tg3_mdio_start(tp);
1162
1163         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1164             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1165                 return 0;
1166
1167         tp->mdio_bus = mdiobus_alloc();
1168         if (tp->mdio_bus == NULL)
1169                 return -ENOMEM;
1170
1171         tp->mdio_bus->name     = "tg3 mdio bus";
1172         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1173                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1174         tp->mdio_bus->priv     = tp;
1175         tp->mdio_bus->parent   = &tp->pdev->dev;
1176         tp->mdio_bus->read     = &tg3_mdio_read;
1177         tp->mdio_bus->write    = &tg3_mdio_write;
1178         tp->mdio_bus->reset    = &tg3_mdio_reset;
1179         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1180         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1181
1182         for (i = 0; i < PHY_MAX_ADDR; i++)
1183                 tp->mdio_bus->irq[i] = PHY_POLL;
1184
1185         /* The bus registration will look for all the PHYs on the mdio bus.
1186          * Unfortunately, it does not ensure the PHY is powered up before
1187          * accessing the PHY ID registers.  A chip reset is the
1188          * quickest way to bring the device back to an operational state..
1189          */
1190         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1191                 tg3_bmcr_reset(tp);
1192
1193         i = mdiobus_register(tp->mdio_bus);
1194         if (i) {
1195                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1196                 mdiobus_free(tp->mdio_bus);
1197                 return i;
1198         }
1199
1200         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1201
1202         if (!phydev || !phydev->drv) {
1203                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1204                 mdiobus_unregister(tp->mdio_bus);
1205                 mdiobus_free(tp->mdio_bus);
1206                 return -ENODEV;
1207         }
1208
1209         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1210         case PHY_ID_BCM57780:
1211                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1212                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1213                 break;
1214         case PHY_ID_BCM50610:
1215         case PHY_ID_BCM50610M:
1216                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1217                                      PHY_BRCM_RX_REFCLK_UNUSED |
1218                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1219                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1220                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1221                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1222                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1223                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1224                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1225                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1226                 /* fallthru */
1227         case PHY_ID_RTL8211C:
1228                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1229                 break;
1230         case PHY_ID_RTL8201E:
1231         case PHY_ID_BCMAC131:
1232                 phydev->interface = PHY_INTERFACE_MODE_MII;
1233                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1234                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1235                 break;
1236         }
1237
1238         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1239
1240         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1241                 tg3_mdio_config_5785(tp);
1242
1243         return 0;
1244 }
1245
1246 static void tg3_mdio_fini(struct tg3 *tp)
1247 {
1248         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1249                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1250                 mdiobus_unregister(tp->mdio_bus);
1251                 mdiobus_free(tp->mdio_bus);
1252         }
1253 }
1254
1255 /* tp->lock is held. */
1256 static inline void tg3_generate_fw_event(struct tg3 *tp)
1257 {
1258         u32 val;
1259
1260         val = tr32(GRC_RX_CPU_EVENT);
1261         val |= GRC_RX_CPU_DRIVER_EVENT;
1262         tw32_f(GRC_RX_CPU_EVENT, val);
1263
1264         tp->last_event_jiffies = jiffies;
1265 }
1266
1267 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1268
1269 /* tp->lock is held. */
1270 static void tg3_wait_for_event_ack(struct tg3 *tp)
1271 {
1272         int i;
1273         unsigned int delay_cnt;
1274         long time_remain;
1275
1276         /* If enough time has passed, no wait is necessary. */
1277         time_remain = (long)(tp->last_event_jiffies + 1 +
1278                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1279                       (long)jiffies;
1280         if (time_remain < 0)
1281                 return;
1282
1283         /* Check if we can shorten the wait time. */
1284         delay_cnt = jiffies_to_usecs(time_remain);
1285         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1286                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1287         delay_cnt = (delay_cnt >> 3) + 1;
1288
1289         for (i = 0; i < delay_cnt; i++) {
1290                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1291                         break;
1292                 udelay(8);
1293         }
1294 }
1295
1296 /* tp->lock is held. */
1297 static void tg3_ump_link_report(struct tg3 *tp)
1298 {
1299         u32 reg;
1300         u32 val;
1301
1302         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1303             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1304                 return;
1305
1306         tg3_wait_for_event_ack(tp);
1307
1308         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1309
1310         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1311
1312         val = 0;
1313         if (!tg3_readphy(tp, MII_BMCR, &reg))
1314                 val = reg << 16;
1315         if (!tg3_readphy(tp, MII_BMSR, &reg))
1316                 val |= (reg & 0xffff);
1317         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1318
1319         val = 0;
1320         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1321                 val = reg << 16;
1322         if (!tg3_readphy(tp, MII_LPA, &reg))
1323                 val |= (reg & 0xffff);
1324         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1325
1326         val = 0;
1327         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1328                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1329                         val = reg << 16;
1330                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1331                         val |= (reg & 0xffff);
1332         }
1333         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1334
1335         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1336                 val = reg << 16;
1337         else
1338                 val = 0;
1339         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1340
1341         tg3_generate_fw_event(tp);
1342 }
1343
1344 static void tg3_link_report(struct tg3 *tp)
1345 {
1346         if (!netif_carrier_ok(tp->dev)) {
1347                 netif_info(tp, link, tp->dev, "Link is down\n");
1348                 tg3_ump_link_report(tp);
1349         } else if (netif_msg_link(tp)) {
1350                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1351                             (tp->link_config.active_speed == SPEED_1000 ?
1352                              1000 :
1353                              (tp->link_config.active_speed == SPEED_100 ?
1354                               100 : 10)),
1355                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1356                              "full" : "half"));
1357
1358                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1359                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1360                             "on" : "off",
1361                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1362                             "on" : "off");
1363
1364                 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1365                         netdev_info(tp->dev, "EEE is %s\n",
1366                                     tp->setlpicnt ? "enabled" : "disabled");
1367
1368                 tg3_ump_link_report(tp);
1369         }
1370 }
1371
1372 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1373 {
1374         u16 miireg;
1375
1376         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1377                 miireg = ADVERTISE_PAUSE_CAP;
1378         else if (flow_ctrl & FLOW_CTRL_TX)
1379                 miireg = ADVERTISE_PAUSE_ASYM;
1380         else if (flow_ctrl & FLOW_CTRL_RX)
1381                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1382         else
1383                 miireg = 0;
1384
1385         return miireg;
1386 }
1387
1388 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1389 {
1390         u16 miireg;
1391
1392         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1393                 miireg = ADVERTISE_1000XPAUSE;
1394         else if (flow_ctrl & FLOW_CTRL_TX)
1395                 miireg = ADVERTISE_1000XPSE_ASYM;
1396         else if (flow_ctrl & FLOW_CTRL_RX)
1397                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1398         else
1399                 miireg = 0;
1400
1401         return miireg;
1402 }
1403
1404 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1405 {
1406         u8 cap = 0;
1407
1408         if (lcladv & ADVERTISE_1000XPAUSE) {
1409                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1410                         if (rmtadv & LPA_1000XPAUSE)
1411                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1412                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1413                                 cap = FLOW_CTRL_RX;
1414                 } else {
1415                         if (rmtadv & LPA_1000XPAUSE)
1416                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1417                 }
1418         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1419                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1420                         cap = FLOW_CTRL_TX;
1421         }
1422
1423         return cap;
1424 }
1425
1426 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1427 {
1428         u8 autoneg;
1429         u8 flowctrl = 0;
1430         u32 old_rx_mode = tp->rx_mode;
1431         u32 old_tx_mode = tp->tx_mode;
1432
1433         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1434                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1435         else
1436                 autoneg = tp->link_config.autoneg;
1437
1438         if (autoneg == AUTONEG_ENABLE &&
1439             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1440                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1441                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1442                 else
1443                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1444         } else
1445                 flowctrl = tp->link_config.flowctrl;
1446
1447         tp->link_config.active_flowctrl = flowctrl;
1448
1449         if (flowctrl & FLOW_CTRL_RX)
1450                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1451         else
1452                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1453
1454         if (old_rx_mode != tp->rx_mode)
1455                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1456
1457         if (flowctrl & FLOW_CTRL_TX)
1458                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1459         else
1460                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1461
1462         if (old_tx_mode != tp->tx_mode)
1463                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1464 }
1465
1466 static void tg3_adjust_link(struct net_device *dev)
1467 {
1468         u8 oldflowctrl, linkmesg = 0;
1469         u32 mac_mode, lcl_adv, rmt_adv;
1470         struct tg3 *tp = netdev_priv(dev);
1471         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1472
1473         spin_lock_bh(&tp->lock);
1474
1475         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1476                                     MAC_MODE_HALF_DUPLEX);
1477
1478         oldflowctrl = tp->link_config.active_flowctrl;
1479
1480         if (phydev->link) {
1481                 lcl_adv = 0;
1482                 rmt_adv = 0;
1483
1484                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1485                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1486                 else if (phydev->speed == SPEED_1000 ||
1487                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1488                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1489                 else
1490                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1491
1492                 if (phydev->duplex == DUPLEX_HALF)
1493                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1494                 else {
1495                         lcl_adv = tg3_advert_flowctrl_1000T(
1496                                   tp->link_config.flowctrl);
1497
1498                         if (phydev->pause)
1499                                 rmt_adv = LPA_PAUSE_CAP;
1500                         if (phydev->asym_pause)
1501                                 rmt_adv |= LPA_PAUSE_ASYM;
1502                 }
1503
1504                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1505         } else
1506                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1507
1508         if (mac_mode != tp->mac_mode) {
1509                 tp->mac_mode = mac_mode;
1510                 tw32_f(MAC_MODE, tp->mac_mode);
1511                 udelay(40);
1512         }
1513
1514         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1515                 if (phydev->speed == SPEED_10)
1516                         tw32(MAC_MI_STAT,
1517                              MAC_MI_STAT_10MBPS_MODE |
1518                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1519                 else
1520                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1521         }
1522
1523         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1524                 tw32(MAC_TX_LENGTHS,
1525                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1526                       (6 << TX_LENGTHS_IPG_SHIFT) |
1527                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1528         else
1529                 tw32(MAC_TX_LENGTHS,
1530                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1531                       (6 << TX_LENGTHS_IPG_SHIFT) |
1532                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1533
1534         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1535             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1536             phydev->speed != tp->link_config.active_speed ||
1537             phydev->duplex != tp->link_config.active_duplex ||
1538             oldflowctrl != tp->link_config.active_flowctrl)
1539                 linkmesg = 1;
1540
1541         tp->link_config.active_speed = phydev->speed;
1542         tp->link_config.active_duplex = phydev->duplex;
1543
1544         spin_unlock_bh(&tp->lock);
1545
1546         if (linkmesg)
1547                 tg3_link_report(tp);
1548 }
1549
1550 static int tg3_phy_init(struct tg3 *tp)
1551 {
1552         struct phy_device *phydev;
1553
1554         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1555                 return 0;
1556
1557         /* Bring the PHY back to a known state. */
1558         tg3_bmcr_reset(tp);
1559
1560         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1561
1562         /* Attach the MAC to the PHY. */
1563         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1564                              phydev->dev_flags, phydev->interface);
1565         if (IS_ERR(phydev)) {
1566                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1567                 return PTR_ERR(phydev);
1568         }
1569
1570         /* Mask with MAC supported features. */
1571         switch (phydev->interface) {
1572         case PHY_INTERFACE_MODE_GMII:
1573         case PHY_INTERFACE_MODE_RGMII:
1574                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1575                         phydev->supported &= (PHY_GBIT_FEATURES |
1576                                               SUPPORTED_Pause |
1577                                               SUPPORTED_Asym_Pause);
1578                         break;
1579                 }
1580                 /* fallthru */
1581         case PHY_INTERFACE_MODE_MII:
1582                 phydev->supported &= (PHY_BASIC_FEATURES |
1583                                       SUPPORTED_Pause |
1584                                       SUPPORTED_Asym_Pause);
1585                 break;
1586         default:
1587                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1588                 return -EINVAL;
1589         }
1590
1591         tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1592
1593         phydev->advertising = phydev->supported;
1594
1595         return 0;
1596 }
1597
1598 static void tg3_phy_start(struct tg3 *tp)
1599 {
1600         struct phy_device *phydev;
1601
1602         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1603                 return;
1604
1605         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1606
1607         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1608                 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1609                 phydev->speed = tp->link_config.orig_speed;
1610                 phydev->duplex = tp->link_config.orig_duplex;
1611                 phydev->autoneg = tp->link_config.orig_autoneg;
1612                 phydev->advertising = tp->link_config.orig_advertising;
1613         }
1614
1615         phy_start(phydev);
1616
1617         phy_start_aneg(phydev);
1618 }
1619
1620 static void tg3_phy_stop(struct tg3 *tp)
1621 {
1622         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1623                 return;
1624
1625         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1626 }
1627
1628 static void tg3_phy_fini(struct tg3 *tp)
1629 {
1630         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1631                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1632                 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1633         }
1634 }
1635
1636 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1637 {
1638         u32 phytest;
1639
1640         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1641                 u32 phy;
1642
1643                 tg3_writephy(tp, MII_TG3_FET_TEST,
1644                              phytest | MII_TG3_FET_SHADOW_EN);
1645                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1646                         if (enable)
1647                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1648                         else
1649                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1650                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1651                 }
1652                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1653         }
1654 }
1655
1656 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1657 {
1658         u32 reg;
1659
1660         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1661             ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
1662              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1663                 return;
1664
1665         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1666                 tg3_phy_fet_toggle_apd(tp, enable);
1667                 return;
1668         }
1669
1670         reg = MII_TG3_MISC_SHDW_WREN |
1671               MII_TG3_MISC_SHDW_SCR5_SEL |
1672               MII_TG3_MISC_SHDW_SCR5_LPED |
1673               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1674               MII_TG3_MISC_SHDW_SCR5_SDTL |
1675               MII_TG3_MISC_SHDW_SCR5_C125OE;
1676         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1677                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1678
1679         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1680
1681
1682         reg = MII_TG3_MISC_SHDW_WREN |
1683               MII_TG3_MISC_SHDW_APD_SEL |
1684               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1685         if (enable)
1686                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1687
1688         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1689 }
1690
1691 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1692 {
1693         u32 phy;
1694
1695         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1696             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1697                 return;
1698
1699         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1700                 u32 ephy;
1701
1702                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1703                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1704
1705                         tg3_writephy(tp, MII_TG3_FET_TEST,
1706                                      ephy | MII_TG3_FET_SHADOW_EN);
1707                         if (!tg3_readphy(tp, reg, &phy)) {
1708                                 if (enable)
1709                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1710                                 else
1711                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1712                                 tg3_writephy(tp, reg, phy);
1713                         }
1714                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1715                 }
1716         } else {
1717                 int ret;
1718
1719                 ret = tg3_phy_auxctl_read(tp,
1720                                           MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
1721                 if (!ret) {
1722                         if (enable)
1723                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1724                         else
1725                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1726                         tg3_phy_auxctl_write(tp,
1727                                              MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
1728                 }
1729         }
1730 }
1731
1732 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1733 {
1734         int ret;
1735         u32 val;
1736
1737         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1738                 return;
1739
1740         ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
1741         if (!ret)
1742                 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
1743                                      val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
1744 }
1745
1746 static void tg3_phy_apply_otp(struct tg3 *tp)
1747 {
1748         u32 otp, phy;
1749
1750         if (!tp->phy_otp)
1751                 return;
1752
1753         otp = tp->phy_otp;
1754
1755         if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp))
1756                 return;
1757
1758         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1759         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1760         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1761
1762         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1763               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1764         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1765
1766         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1767         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1768         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1769
1770         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1771         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1772
1773         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1774         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1775
1776         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1777               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1778         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1779
1780         TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
1781 }
1782
1783 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
1784 {
1785         u32 val;
1786
1787         if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
1788                 return;
1789
1790         tp->setlpicnt = 0;
1791
1792         if (tp->link_config.autoneg == AUTONEG_ENABLE &&
1793             current_link_up == 1 &&
1794             tp->link_config.active_duplex == DUPLEX_FULL &&
1795             (tp->link_config.active_speed == SPEED_100 ||
1796              tp->link_config.active_speed == SPEED_1000)) {
1797                 u32 eeectl;
1798
1799                 if (tp->link_config.active_speed == SPEED_1000)
1800                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
1801                 else
1802                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
1803
1804                 tw32(TG3_CPMU_EEE_CTRL, eeectl);
1805
1806                 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
1807                                   TG3_CL45_D7_EEERES_STAT, &val);
1808
1809                 switch (val) {
1810                 case TG3_CL45_D7_EEERES_STAT_LP_1000T:
1811                         switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
1812                         case ASIC_REV_5717:
1813                         case ASIC_REV_5719:
1814                         case ASIC_REV_57765:
1815                                 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
1816                                         tg3_phydsp_write(tp, MII_TG3_DSP_TAP26,
1817                                                          0x0000);
1818                                         TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
1819                                 }
1820                         }
1821                         /* Fallthrough */
1822                 case TG3_CL45_D7_EEERES_STAT_LP_100TX:
1823                         tp->setlpicnt = 2;
1824                 }
1825         }
1826
1827         if (!tp->setlpicnt) {
1828                 val = tr32(TG3_CPMU_EEE_MODE);
1829                 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
1830         }
1831 }
1832
1833 static int tg3_wait_macro_done(struct tg3 *tp)
1834 {
1835         int limit = 100;
1836
1837         while (limit--) {
1838                 u32 tmp32;
1839
1840                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1841                         if ((tmp32 & 0x1000) == 0)
1842                                 break;
1843                 }
1844         }
1845         if (limit < 0)
1846                 return -EBUSY;
1847
1848         return 0;
1849 }
1850
1851 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1852 {
1853         static const u32 test_pat[4][6] = {
1854         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1855         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1856         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1857         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1858         };
1859         int chan;
1860
1861         for (chan = 0; chan < 4; chan++) {
1862                 int i;
1863
1864                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1865                              (chan * 0x2000) | 0x0200);
1866                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1867
1868                 for (i = 0; i < 6; i++)
1869                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1870                                      test_pat[chan][i]);
1871
1872                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1873                 if (tg3_wait_macro_done(tp)) {
1874                         *resetp = 1;
1875                         return -EBUSY;
1876                 }
1877
1878                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1879                              (chan * 0x2000) | 0x0200);
1880                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1881                 if (tg3_wait_macro_done(tp)) {
1882                         *resetp = 1;
1883                         return -EBUSY;
1884                 }
1885
1886                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1887                 if (tg3_wait_macro_done(tp)) {
1888                         *resetp = 1;
1889                         return -EBUSY;
1890                 }
1891
1892                 for (i = 0; i < 6; i += 2) {
1893                         u32 low, high;
1894
1895                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1896                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1897                             tg3_wait_macro_done(tp)) {
1898                                 *resetp = 1;
1899                                 return -EBUSY;
1900                         }
1901                         low &= 0x7fff;
1902                         high &= 0x000f;
1903                         if (low != test_pat[chan][i] ||
1904                             high != test_pat[chan][i+1]) {
1905                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1906                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1907                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1908
1909                                 return -EBUSY;
1910                         }
1911                 }
1912         }
1913
1914         return 0;
1915 }
1916
1917 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1918 {
1919         int chan;
1920
1921         for (chan = 0; chan < 4; chan++) {
1922                 int i;
1923
1924                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1925                              (chan * 0x2000) | 0x0200);
1926                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1927                 for (i = 0; i < 6; i++)
1928                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1929                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1930                 if (tg3_wait_macro_done(tp))
1931                         return -EBUSY;
1932         }
1933
1934         return 0;
1935 }
1936
1937 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1938 {
1939         u32 reg32, phy9_orig;
1940         int retries, do_phy_reset, err;
1941
1942         retries = 10;
1943         do_phy_reset = 1;
1944         do {
1945                 if (do_phy_reset) {
1946                         err = tg3_bmcr_reset(tp);
1947                         if (err)
1948                                 return err;
1949                         do_phy_reset = 0;
1950                 }
1951
1952                 /* Disable transmitter and interrupt.  */
1953                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1954                         continue;
1955
1956                 reg32 |= 0x3000;
1957                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1958
1959                 /* Set full-duplex, 1000 mbps.  */
1960                 tg3_writephy(tp, MII_BMCR,
1961                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1962
1963                 /* Set to master mode.  */
1964                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1965                         continue;
1966
1967                 tg3_writephy(tp, MII_TG3_CTRL,
1968                              (MII_TG3_CTRL_AS_MASTER |
1969                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1970
1971                 err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
1972                 if (err)
1973                         return err;
1974
1975                 /* Block the PHY control access.  */
1976                 tg3_phydsp_write(tp, 0x8005, 0x0800);
1977
1978                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1979                 if (!err)
1980                         break;
1981         } while (--retries);
1982
1983         err = tg3_phy_reset_chanpat(tp);
1984         if (err)
1985                 return err;
1986
1987         tg3_phydsp_write(tp, 0x8005, 0x0000);
1988
1989         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1990         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1991
1992         TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
1993
1994         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1995
1996         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1997                 reg32 &= ~0x3000;
1998                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1999         } else if (!err)
2000                 err = -EBUSY;
2001
2002         return err;
2003 }
2004
2005 /* This will reset the tigon3 PHY if there is no valid
2006  * link unless the FORCE argument is non-zero.
2007  */
2008 static int tg3_phy_reset(struct tg3 *tp)
2009 {
2010         u32 val, cpmuctrl;
2011         int err;
2012
2013         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2014                 val = tr32(GRC_MISC_CFG);
2015                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2016                 udelay(40);
2017         }
2018         err  = tg3_readphy(tp, MII_BMSR, &val);
2019         err |= tg3_readphy(tp, MII_BMSR, &val);
2020         if (err != 0)
2021                 return -EBUSY;
2022
2023         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
2024                 netif_carrier_off(tp->dev);
2025                 tg3_link_report(tp);
2026         }
2027
2028         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2029             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2030             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2031                 err = tg3_phy_reset_5703_4_5(tp);
2032                 if (err)
2033                         return err;
2034                 goto out;
2035         }
2036
2037         cpmuctrl = 0;
2038         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2039             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2040                 cpmuctrl = tr32(TG3_CPMU_CTRL);
2041                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2042                         tw32(TG3_CPMU_CTRL,
2043                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2044         }
2045
2046         err = tg3_bmcr_reset(tp);
2047         if (err)
2048                 return err;
2049
2050         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2051                 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2052                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2053
2054                 tw32(TG3_CPMU_CTRL, cpmuctrl);
2055         }
2056
2057         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2058             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2059                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2060                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2061                     CPMU_LSPD_1000MB_MACCLK_12_5) {
2062                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2063                         udelay(40);
2064                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2065                 }
2066         }
2067
2068         if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
2069             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2070                 return 0;
2071
2072         tg3_phy_apply_otp(tp);
2073
2074         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2075                 tg3_phy_toggle_apd(tp, true);
2076         else
2077                 tg3_phy_toggle_apd(tp, false);
2078
2079 out:
2080         if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2081             !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2082                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2083                 tg3_phydsp_write(tp, 0x000a, 0x0323);
2084                 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2085         }
2086
2087         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2088                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2089                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2090         }
2091
2092         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2093                 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2094                         tg3_phydsp_write(tp, 0x000a, 0x310b);
2095                         tg3_phydsp_write(tp, 0x201f, 0x9506);
2096                         tg3_phydsp_write(tp, 0x401f, 0x14e2);
2097                         TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2098                 }
2099         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2100                 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2101                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2102                         if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2103                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2104                                 tg3_writephy(tp, MII_TG3_TEST1,
2105                                              MII_TG3_TEST1_TRIM_EN | 0x4);
2106                         } else
2107                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2108
2109                         TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2110                 }
2111         }
2112
2113         /* Set Extended packet length bit (bit 14) on all chips that */
2114         /* support jumbo frames */
2115         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2116                 /* Cannot do read-modify-write on 5401 */
2117                 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2118         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2119                 /* Set bit 14 with read-modify-write to preserve other bits */
2120                 err = tg3_phy_auxctl_read(tp,
2121                                           MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2122                 if (!err)
2123                         tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2124                                            val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
2125         }
2126
2127         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2128          * jumbo frames transmission.
2129          */
2130         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2131                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2132                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2133                                      val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2134         }
2135
2136         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2137                 /* adjust output voltage */
2138                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2139         }
2140
2141         tg3_phy_toggle_automdix(tp, 1);
2142         tg3_phy_set_wirespeed(tp);
2143         return 0;
2144 }
2145
2146 static void tg3_frob_aux_power(struct tg3 *tp)
2147 {
2148         bool need_vaux = false;
2149
2150         /* The GPIOs do something completely different on 57765. */
2151         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2152             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2153             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2154                 return;
2155
2156         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2157              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2158              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2159              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) &&
2160             tp->pdev_peer != tp->pdev) {
2161                 struct net_device *dev_peer;
2162
2163                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2164
2165                 /* remove_one() may have been run on the peer. */
2166                 if (dev_peer) {
2167                         struct tg3 *tp_peer = netdev_priv(dev_peer);
2168
2169                         if (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE)
2170                                 return;
2171
2172                         if ((tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) ||
2173                             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF))
2174                                 need_vaux = true;
2175                 }
2176         }
2177
2178         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) ||
2179             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2180                 need_vaux = true;
2181
2182         if (need_vaux) {
2183                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2184                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2185                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2186                                     (GRC_LCLCTRL_GPIO_OE0 |
2187                                      GRC_LCLCTRL_GPIO_OE1 |
2188                                      GRC_LCLCTRL_GPIO_OE2 |
2189                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2190                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2191                                     100);
2192                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2193                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2194                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2195                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2196                                              GRC_LCLCTRL_GPIO_OE1 |
2197                                              GRC_LCLCTRL_GPIO_OE2 |
2198                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2199                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2200                                              tp->grc_local_ctrl;
2201                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2202
2203                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2204                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2205
2206                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2207                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2208                 } else {
2209                         u32 no_gpio2;
2210                         u32 grc_local_ctrl = 0;
2211
2212                         /* Workaround to prevent overdrawing Amps. */
2213                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2214                             ASIC_REV_5714) {
2215                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2216                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2217                                             grc_local_ctrl, 100);
2218                         }
2219
2220                         /* On 5753 and variants, GPIO2 cannot be used. */
2221                         no_gpio2 = tp->nic_sram_data_cfg &
2222                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2223
2224                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2225                                          GRC_LCLCTRL_GPIO_OE1 |
2226                                          GRC_LCLCTRL_GPIO_OE2 |
2227                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2228                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2229                         if (no_gpio2) {
2230                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2231                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2232                         }
2233                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2234                                                     grc_local_ctrl, 100);
2235
2236                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2237
2238                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2239                                                     grc_local_ctrl, 100);
2240
2241                         if (!no_gpio2) {
2242                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2243                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2244                                             grc_local_ctrl, 100);
2245                         }
2246                 }
2247         } else {
2248                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2249                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2250                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2251                                     (GRC_LCLCTRL_GPIO_OE1 |
2252                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2253
2254                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2255                                     GRC_LCLCTRL_GPIO_OE1, 100);
2256
2257                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2258                                     (GRC_LCLCTRL_GPIO_OE1 |
2259                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2260                 }
2261         }
2262 }
2263
2264 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2265 {
2266         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2267                 return 1;
2268         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2269                 if (speed != SPEED_10)
2270                         return 1;
2271         } else if (speed == SPEED_10)
2272                 return 1;
2273
2274         return 0;
2275 }
2276
2277 static int tg3_setup_phy(struct tg3 *, int);
2278
2279 #define RESET_KIND_SHUTDOWN     0
2280 #define RESET_KIND_INIT         1
2281 #define RESET_KIND_SUSPEND      2
2282
2283 static void tg3_write_sig_post_reset(struct tg3 *, int);
2284 static int tg3_halt_cpu(struct tg3 *, u32);
2285
2286 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2287 {
2288         u32 val;
2289
2290         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2291                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2292                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2293                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2294
2295                         sg_dig_ctrl |=
2296                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2297                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2298                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2299                 }
2300                 return;
2301         }
2302
2303         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2304                 tg3_bmcr_reset(tp);
2305                 val = tr32(GRC_MISC_CFG);
2306                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2307                 udelay(40);
2308                 return;
2309         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2310                 u32 phytest;
2311                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2312                         u32 phy;
2313
2314                         tg3_writephy(tp, MII_ADVERTISE, 0);
2315                         tg3_writephy(tp, MII_BMCR,
2316                                      BMCR_ANENABLE | BMCR_ANRESTART);
2317
2318                         tg3_writephy(tp, MII_TG3_FET_TEST,
2319                                      phytest | MII_TG3_FET_SHADOW_EN);
2320                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2321                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2322                                 tg3_writephy(tp,
2323                                              MII_TG3_FET_SHDW_AUXMODE4,
2324                                              phy);
2325                         }
2326                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2327                 }
2328                 return;
2329         } else if (do_low_power) {
2330                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2331                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2332
2333                 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2334                       MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2335                       MII_TG3_AUXCTL_PCTL_VREG_11V;
2336                 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
2337         }
2338
2339         /* The PHY should not be powered down on some chips because
2340          * of bugs.
2341          */
2342         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2343             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2344             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2345              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2346                 return;
2347
2348         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2349             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2350                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2351                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2352                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2353                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2354         }
2355
2356         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2357 }
2358
2359 /* tp->lock is held. */
2360 static int tg3_nvram_lock(struct tg3 *tp)
2361 {
2362         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2363                 int i;
2364
2365                 if (tp->nvram_lock_cnt == 0) {
2366                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2367                         for (i = 0; i < 8000; i++) {
2368                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2369                                         break;
2370                                 udelay(20);
2371                         }
2372                         if (i == 8000) {
2373                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2374                                 return -ENODEV;
2375                         }
2376                 }
2377                 tp->nvram_lock_cnt++;
2378         }
2379         return 0;
2380 }
2381
2382 /* tp->lock is held. */
2383 static void tg3_nvram_unlock(struct tg3 *tp)
2384 {
2385         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2386                 if (tp->nvram_lock_cnt > 0)
2387                         tp->nvram_lock_cnt--;
2388                 if (tp->nvram_lock_cnt == 0)
2389                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2390         }
2391 }
2392
2393 /* tp->lock is held. */
2394 static void tg3_enable_nvram_access(struct tg3 *tp)
2395 {
2396         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2397             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2398                 u32 nvaccess = tr32(NVRAM_ACCESS);
2399
2400                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2401         }
2402 }
2403
2404 /* tp->lock is held. */
2405 static void tg3_disable_nvram_access(struct tg3 *tp)
2406 {
2407         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2408             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2409                 u32 nvaccess = tr32(NVRAM_ACCESS);
2410
2411                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2412         }
2413 }
2414
2415 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2416                                         u32 offset, u32 *val)
2417 {
2418         u32 tmp;
2419         int i;
2420
2421         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2422                 return -EINVAL;
2423
2424         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2425                                         EEPROM_ADDR_DEVID_MASK |
2426                                         EEPROM_ADDR_READ);
2427         tw32(GRC_EEPROM_ADDR,
2428              tmp |
2429              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2430              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2431               EEPROM_ADDR_ADDR_MASK) |
2432              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2433
2434         for (i = 0; i < 1000; i++) {
2435                 tmp = tr32(GRC_EEPROM_ADDR);
2436
2437                 if (tmp & EEPROM_ADDR_COMPLETE)
2438                         break;
2439                 msleep(1);
2440         }
2441         if (!(tmp & EEPROM_ADDR_COMPLETE))
2442                 return -EBUSY;
2443
2444         tmp = tr32(GRC_EEPROM_DATA);
2445
2446         /*
2447          * The data will always be opposite the native endian
2448          * format.  Perform a blind byteswap to compensate.
2449          */
2450         *val = swab32(tmp);
2451
2452         return 0;
2453 }
2454
2455 #define NVRAM_CMD_TIMEOUT 10000
2456
2457 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2458 {
2459         int i;
2460
2461         tw32(NVRAM_CMD, nvram_cmd);
2462         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2463                 udelay(10);
2464                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2465                         udelay(10);
2466                         break;
2467                 }
2468         }
2469
2470         if (i == NVRAM_CMD_TIMEOUT)
2471                 return -EBUSY;
2472
2473         return 0;
2474 }
2475
2476 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2477 {
2478         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2479             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2480             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2481            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2482             (tp->nvram_jedecnum == JEDEC_ATMEL))
2483
2484                 addr = ((addr / tp->nvram_pagesize) <<
2485                         ATMEL_AT45DB0X1B_PAGE_POS) +
2486                        (addr % tp->nvram_pagesize);
2487
2488         return addr;
2489 }
2490
2491 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2492 {
2493         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2494             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2495             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2496            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2497             (tp->nvram_jedecnum == JEDEC_ATMEL))
2498
2499                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2500                         tp->nvram_pagesize) +
2501                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2502
2503         return addr;
2504 }
2505
2506 /* NOTE: Data read in from NVRAM is byteswapped according to
2507  * the byteswapping settings for all other register accesses.
2508  * tg3 devices are BE devices, so on a BE machine, the data
2509  * returned will be exactly as it is seen in NVRAM.  On a LE
2510  * machine, the 32-bit value will be byteswapped.
2511  */
2512 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2513 {
2514         int ret;
2515
2516         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2517                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2518
2519         offset = tg3_nvram_phys_addr(tp, offset);
2520
2521         if (offset > NVRAM_ADDR_MSK)
2522                 return -EINVAL;
2523
2524         ret = tg3_nvram_lock(tp);
2525         if (ret)
2526                 return ret;
2527
2528         tg3_enable_nvram_access(tp);
2529
2530         tw32(NVRAM_ADDR, offset);
2531         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2532                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2533
2534         if (ret == 0)
2535                 *val = tr32(NVRAM_RDDATA);
2536
2537         tg3_disable_nvram_access(tp);
2538
2539         tg3_nvram_unlock(tp);
2540
2541         return ret;
2542 }
2543
2544 /* Ensures NVRAM data is in bytestream format. */
2545 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2546 {
2547         u32 v;
2548         int res = tg3_nvram_read(tp, offset, &v);
2549         if (!res)
2550                 *val = cpu_to_be32(v);
2551         return res;
2552 }
2553
2554 /* tp->lock is held. */
2555 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2556 {
2557         u32 addr_high, addr_low;
2558         int i;
2559
2560         addr_high = ((tp->dev->dev_addr[0] << 8) |
2561                      tp->dev->dev_addr[1]);
2562         addr_low = ((tp->dev->dev_addr[2] << 24) |
2563                     (tp->dev->dev_addr[3] << 16) |
2564                     (tp->dev->dev_addr[4] <<  8) |
2565                     (tp->dev->dev_addr[5] <<  0));
2566         for (i = 0; i < 4; i++) {
2567                 if (i == 1 && skip_mac_1)
2568                         continue;
2569                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2570                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2571         }
2572
2573         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2574             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2575                 for (i = 0; i < 12; i++) {
2576                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2577                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2578                 }
2579         }
2580
2581         addr_high = (tp->dev->dev_addr[0] +
2582                      tp->dev->dev_addr[1] +
2583                      tp->dev->dev_addr[2] +
2584                      tp->dev->dev_addr[3] +
2585                      tp->dev->dev_addr[4] +
2586                      tp->dev->dev_addr[5]) &
2587                 TX_BACKOFF_SEED_MASK;
2588         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2589 }
2590
2591 static void tg3_enable_register_access(struct tg3 *tp)
2592 {
2593         /*
2594          * Make sure register accesses (indirect or otherwise) will function
2595          * correctly.
2596          */
2597         pci_write_config_dword(tp->pdev,
2598                                TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
2599 }
2600
2601 static int tg3_power_up(struct tg3 *tp)
2602 {
2603         tg3_enable_register_access(tp);
2604
2605         pci_set_power_state(tp->pdev, PCI_D0);
2606
2607         /* Switch out of Vaux if it is a NIC */
2608         if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2609                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2610
2611         return 0;
2612 }
2613
2614 static int tg3_power_down_prepare(struct tg3 *tp)
2615 {
2616         u32 misc_host_ctrl;
2617         bool device_should_wake, do_low_power;
2618
2619         tg3_enable_register_access(tp);
2620
2621         /* Restore the CLKREQ setting. */
2622         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2623                 u16 lnkctl;
2624
2625                 pci_read_config_word(tp->pdev,
2626                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2627                                      &lnkctl);
2628                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2629                 pci_write_config_word(tp->pdev,
2630                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2631                                       lnkctl);
2632         }
2633
2634         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2635         tw32(TG3PCI_MISC_HOST_CTRL,
2636              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2637
2638         device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
2639                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2640
2641         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2642                 do_low_power = false;
2643                 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2644                     !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2645                         struct phy_device *phydev;
2646                         u32 phyid, advertising;
2647
2648                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2649
2650                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2651
2652                         tp->link_config.orig_speed = phydev->speed;
2653                         tp->link_config.orig_duplex = phydev->duplex;
2654                         tp->link_config.orig_autoneg = phydev->autoneg;
2655                         tp->link_config.orig_advertising = phydev->advertising;
2656
2657                         advertising = ADVERTISED_TP |
2658                                       ADVERTISED_Pause |
2659                                       ADVERTISED_Autoneg |
2660                                       ADVERTISED_10baseT_Half;
2661
2662                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2663                             device_should_wake) {
2664                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2665                                         advertising |=
2666                                                 ADVERTISED_100baseT_Half |
2667                                                 ADVERTISED_100baseT_Full |
2668                                                 ADVERTISED_10baseT_Full;
2669                                 else
2670                                         advertising |= ADVERTISED_10baseT_Full;
2671                         }
2672
2673                         phydev->advertising = advertising;
2674
2675                         phy_start_aneg(phydev);
2676
2677                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2678                         if (phyid != PHY_ID_BCMAC131) {
2679                                 phyid &= PHY_BCM_OUI_MASK;
2680                                 if (phyid == PHY_BCM_OUI_1 ||
2681                                     phyid == PHY_BCM_OUI_2 ||
2682                                     phyid == PHY_BCM_OUI_3)
2683                                         do_low_power = true;
2684                         }
2685                 }
2686         } else {
2687                 do_low_power = true;
2688
2689                 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2690                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2691                         tp->link_config.orig_speed = tp->link_config.speed;
2692                         tp->link_config.orig_duplex = tp->link_config.duplex;
2693                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2694                 }
2695
2696                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2697                         tp->link_config.speed = SPEED_10;
2698                         tp->link_config.duplex = DUPLEX_HALF;
2699                         tp->link_config.autoneg = AUTONEG_ENABLE;
2700                         tg3_setup_phy(tp, 0);
2701                 }
2702         }
2703
2704         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2705                 u32 val;
2706
2707                 val = tr32(GRC_VCPU_EXT_CTRL);
2708                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2709         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2710                 int i;
2711                 u32 val;
2712
2713                 for (i = 0; i < 200; i++) {
2714                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2715                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2716                                 break;
2717                         msleep(1);
2718                 }
2719         }
2720         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2721                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2722                                                      WOL_DRV_STATE_SHUTDOWN |
2723                                                      WOL_DRV_WOL |
2724                                                      WOL_SET_MAGIC_PKT);
2725
2726         if (device_should_wake) {
2727                 u32 mac_mode;
2728
2729                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2730                         if (do_low_power &&
2731                             !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
2732                                 tg3_phy_auxctl_write(tp,
2733                                                MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
2734                                                MII_TG3_AUXCTL_PCTL_WOL_EN |
2735                                                MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2736                                                MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
2737                                 udelay(40);
2738                         }
2739
2740                         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2741                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2742                         else
2743                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2744
2745                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2746                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2747                             ASIC_REV_5700) {
2748                                 u32 speed = (tp->tg3_flags &
2749                                              TG3_FLAG_WOL_SPEED_100MB) ?
2750                                              SPEED_100 : SPEED_10;
2751                                 if (tg3_5700_link_polarity(tp, speed))
2752                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2753                                 else
2754                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2755                         }
2756                 } else {
2757                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2758                 }
2759
2760                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2761                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2762
2763                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2764                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2765                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2766                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2767                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2768                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2769
2770                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
2771                         mac_mode |= MAC_MODE_APE_TX_EN |
2772                                     MAC_MODE_APE_RX_EN |
2773                                     MAC_MODE_TDE_ENABLE;
2774
2775                 tw32_f(MAC_MODE, mac_mode);
2776                 udelay(100);
2777
2778                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2779                 udelay(10);
2780         }
2781
2782         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2783             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2784              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2785                 u32 base_val;
2786
2787                 base_val = tp->pci_clock_ctrl;
2788                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2789                              CLOCK_CTRL_TXCLK_DISABLE);
2790
2791                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2792                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2793         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2794                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2795                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2796                 /* do nothing */
2797         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2798                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2799                 u32 newbits1, newbits2;
2800
2801                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2802                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2803                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2804                                     CLOCK_CTRL_TXCLK_DISABLE |
2805                                     CLOCK_CTRL_ALTCLK);
2806                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2807                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2808                         newbits1 = CLOCK_CTRL_625_CORE;
2809                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2810                 } else {
2811                         newbits1 = CLOCK_CTRL_ALTCLK;
2812                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2813                 }
2814
2815                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2816                             40);
2817
2818                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2819                             40);
2820
2821                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2822                         u32 newbits3;
2823
2824                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2825                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2826                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2827                                             CLOCK_CTRL_TXCLK_DISABLE |
2828                                             CLOCK_CTRL_44MHZ_CORE);
2829                         } else {
2830                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2831                         }
2832
2833                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2834                                     tp->pci_clock_ctrl | newbits3, 40);
2835                 }
2836         }
2837
2838         if (!(device_should_wake) &&
2839             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2840                 tg3_power_down_phy(tp, do_low_power);
2841
2842         tg3_frob_aux_power(tp);
2843
2844         /* Workaround for unstable PLL clock */
2845         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2846             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2847                 u32 val = tr32(0x7d00);
2848
2849                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2850                 tw32(0x7d00, val);
2851                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2852                         int err;
2853
2854                         err = tg3_nvram_lock(tp);
2855                         tg3_halt_cpu(tp, RX_CPU_BASE);
2856                         if (!err)
2857                                 tg3_nvram_unlock(tp);
2858                 }
2859         }
2860
2861         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2862
2863         return 0;
2864 }
2865
2866 static void tg3_power_down(struct tg3 *tp)
2867 {
2868         tg3_power_down_prepare(tp);
2869
2870         pci_wake_from_d3(tp->pdev, tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2871         pci_set_power_state(tp->pdev, PCI_D3hot);
2872 }
2873
2874 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2875 {
2876         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2877         case MII_TG3_AUX_STAT_10HALF:
2878                 *speed = SPEED_10;
2879                 *duplex = DUPLEX_HALF;
2880                 break;
2881
2882         case MII_TG3_AUX_STAT_10FULL:
2883                 *speed = SPEED_10;
2884                 *duplex = DUPLEX_FULL;
2885                 break;
2886
2887         case MII_TG3_AUX_STAT_100HALF:
2888                 *speed = SPEED_100;
2889                 *duplex = DUPLEX_HALF;
2890                 break;
2891
2892         case MII_TG3_AUX_STAT_100FULL:
2893                 *speed = SPEED_100;
2894                 *duplex = DUPLEX_FULL;
2895                 break;
2896
2897         case MII_TG3_AUX_STAT_1000HALF:
2898                 *speed = SPEED_1000;
2899                 *duplex = DUPLEX_HALF;
2900                 break;
2901
2902         case MII_TG3_AUX_STAT_1000FULL:
2903                 *speed = SPEED_1000;
2904                 *duplex = DUPLEX_FULL;
2905                 break;
2906
2907         default:
2908                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2909                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2910                                  SPEED_10;
2911                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2912                                   DUPLEX_HALF;
2913                         break;
2914                 }
2915                 *speed = SPEED_INVALID;
2916                 *duplex = DUPLEX_INVALID;
2917                 break;
2918         }
2919 }
2920
2921 static void tg3_phy_copper_begin(struct tg3 *tp)
2922 {
2923         u32 new_adv;
2924         int i;
2925
2926         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2927                 /* Entering low power mode.  Disable gigabit and
2928                  * 100baseT advertisements.
2929                  */
2930                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2931
2932                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2933                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2934                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2935                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2936
2937                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2938         } else if (tp->link_config.speed == SPEED_INVALID) {
2939                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2940                         tp->link_config.advertising &=
2941                                 ~(ADVERTISED_1000baseT_Half |
2942                                   ADVERTISED_1000baseT_Full);
2943
2944                 new_adv = ADVERTISE_CSMA;
2945                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2946                         new_adv |= ADVERTISE_10HALF;
2947                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2948                         new_adv |= ADVERTISE_10FULL;
2949                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2950                         new_adv |= ADVERTISE_100HALF;
2951                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2952                         new_adv |= ADVERTISE_100FULL;
2953
2954                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2955
2956                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2957
2958                 if (tp->link_config.advertising &
2959                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2960                         new_adv = 0;
2961                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2962                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2963                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2964                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2965                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
2966                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2967                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2968                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2969                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2970                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2971                 } else {
2972                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2973                 }
2974         } else {
2975                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2976                 new_adv |= ADVERTISE_CSMA;
2977
2978                 /* Asking for a specific link mode. */
2979                 if (tp->link_config.speed == SPEED_1000) {
2980                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2981
2982                         if (tp->link_config.duplex == DUPLEX_FULL)
2983                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2984                         else
2985                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2986                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2987                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2988                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2989                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2990                 } else {
2991                         if (tp->link_config.speed == SPEED_100) {
2992                                 if (tp->link_config.duplex == DUPLEX_FULL)
2993                                         new_adv |= ADVERTISE_100FULL;
2994                                 else
2995                                         new_adv |= ADVERTISE_100HALF;
2996                         } else {
2997                                 if (tp->link_config.duplex == DUPLEX_FULL)
2998                                         new_adv |= ADVERTISE_10FULL;
2999                                 else
3000                                         new_adv |= ADVERTISE_10HALF;
3001                         }
3002                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
3003
3004                         new_adv = 0;
3005                 }
3006
3007                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
3008         }
3009
3010         if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
3011                 u32 val;
3012
3013                 tw32(TG3_CPMU_EEE_MODE,
3014                      tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
3015
3016                 TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
3017
3018                 switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
3019                 case ASIC_REV_5717:
3020                 case ASIC_REV_57765:
3021                         if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
3022                                 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
3023                                                  MII_TG3_DSP_CH34TP2_HIBW01);
3024                         /* Fall through */
3025                 case ASIC_REV_5719:
3026                         val = MII_TG3_DSP_TAP26_ALNOKO |
3027                               MII_TG3_DSP_TAP26_RMRXSTO |
3028                               MII_TG3_DSP_TAP26_OPCSINPT;
3029                         tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
3030                 }
3031
3032                 val = 0;
3033                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3034                         /* Advertise 100-BaseTX EEE ability */
3035                         if (tp->link_config.advertising &
3036                             ADVERTISED_100baseT_Full)
3037                                 val |= MDIO_AN_EEE_ADV_100TX;
3038                         /* Advertise 1000-BaseT EEE ability */
3039                         if (tp->link_config.advertising &
3040                             ADVERTISED_1000baseT_Full)
3041                                 val |= MDIO_AN_EEE_ADV_1000T;
3042                 }
3043                 tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3044
3045                 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
3046         }
3047
3048         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
3049             tp->link_config.speed != SPEED_INVALID) {
3050                 u32 bmcr, orig_bmcr;
3051
3052                 tp->link_config.active_speed = tp->link_config.speed;
3053                 tp->link_config.active_duplex = tp->link_config.duplex;
3054
3055                 bmcr = 0;
3056                 switch (tp->link_config.speed) {
3057                 default:
3058                 case SPEED_10:
3059                         break;
3060
3061                 case SPEED_100:
3062                         bmcr |= BMCR_SPEED100;
3063                         break;
3064
3065                 case SPEED_1000:
3066                         bmcr |= TG3_BMCR_SPEED1000;
3067                         break;
3068                 }
3069
3070                 if (tp->link_config.duplex == DUPLEX_FULL)
3071                         bmcr |= BMCR_FULLDPLX;
3072
3073                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
3074                     (bmcr != orig_bmcr)) {
3075                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
3076                         for (i = 0; i < 1500; i++) {
3077                                 u32 tmp;
3078
3079                                 udelay(10);
3080                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
3081                                     tg3_readphy(tp, MII_BMSR, &tmp))
3082                                         continue;
3083                                 if (!(tmp & BMSR_LSTATUS)) {
3084                                         udelay(40);
3085                                         break;
3086                                 }
3087                         }
3088                         tg3_writephy(tp, MII_BMCR, bmcr);
3089                         udelay(40);
3090                 }
3091         } else {
3092                 tg3_writephy(tp, MII_BMCR,
3093                              BMCR_ANENABLE | BMCR_ANRESTART);
3094         }
3095 }
3096
3097 static int tg3_init_5401phy_dsp(struct tg3 *tp)
3098 {
3099         int err;
3100
3101         /* Turn off tap power management. */
3102         /* Set Extended packet length bit */
3103         err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
3104
3105         err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
3106         err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
3107         err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
3108         err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
3109         err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
3110
3111         udelay(40);
3112
3113         return err;
3114 }
3115
3116 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3117 {
3118         u32 adv_reg, all_mask = 0;
3119
3120         if (mask & ADVERTISED_10baseT_Half)
3121                 all_mask |= ADVERTISE_10HALF;
3122         if (mask & ADVERTISED_10baseT_Full)
3123                 all_mask |= ADVERTISE_10FULL;
3124         if (mask & ADVERTISED_100baseT_Half)
3125                 all_mask |= ADVERTISE_100HALF;
3126         if (mask & ADVERTISED_100baseT_Full)
3127                 all_mask |= ADVERTISE_100FULL;
3128
3129         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3130                 return 0;
3131
3132         if ((adv_reg & all_mask) != all_mask)
3133                 return 0;
3134         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3135                 u32 tg3_ctrl;
3136
3137                 all_mask = 0;
3138                 if (mask & ADVERTISED_1000baseT_Half)
3139                         all_mask |= ADVERTISE_1000HALF;
3140                 if (mask & ADVERTISED_1000baseT_Full)
3141                         all_mask |= ADVERTISE_1000FULL;
3142
3143                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3144                         return 0;
3145
3146                 if ((tg3_ctrl & all_mask) != all_mask)
3147                         return 0;
3148         }
3149         return 1;
3150 }
3151
3152 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3153 {
3154         u32 curadv, reqadv;
3155
3156         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3157                 return 1;
3158
3159         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3160         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3161
3162         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3163                 if (curadv != reqadv)
3164                         return 0;
3165
3166                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3167                         tg3_readphy(tp, MII_LPA, rmtadv);
3168         } else {
3169                 /* Reprogram the advertisement register, even if it
3170                  * does not affect the current link.  If the link
3171                  * gets renegotiated in the future, we can save an
3172                  * additional renegotiation cycle by advertising
3173                  * it correctly in the first place.
3174                  */
3175                 if (curadv != reqadv) {
3176                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3177                                      ADVERTISE_PAUSE_ASYM);
3178                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3179                 }
3180         }
3181
3182         return 1;
3183 }
3184
3185 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3186 {
3187         int current_link_up;
3188         u32 bmsr, val;
3189         u32 lcl_adv, rmt_adv;
3190         u16 current_speed;
3191         u8 current_duplex;
3192         int i, err;
3193
3194         tw32(MAC_EVENT, 0);
3195
3196         tw32_f(MAC_STATUS,
3197              (MAC_STATUS_SYNC_CHANGED |
3198               MAC_STATUS_CFG_CHANGED |
3199               MAC_STATUS_MI_COMPLETION |
3200               MAC_STATUS_LNKSTATE_CHANGED));
3201         udelay(40);
3202
3203         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3204                 tw32_f(MAC_MI_MODE,
3205                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3206                 udelay(80);
3207         }
3208
3209         tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
3210
3211         /* Some third-party PHYs need to be reset on link going
3212          * down.
3213          */
3214         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3215              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3216              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3217             netif_carrier_ok(tp->dev)) {
3218                 tg3_readphy(tp, MII_BMSR, &bmsr);
3219                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3220                     !(bmsr & BMSR_LSTATUS))
3221                         force_reset = 1;
3222         }
3223         if (force_reset)
3224                 tg3_phy_reset(tp);
3225
3226         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3227                 tg3_readphy(tp, MII_BMSR, &bmsr);
3228                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3229                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3230                         bmsr = 0;
3231
3232                 if (!(bmsr & BMSR_LSTATUS)) {
3233                         err = tg3_init_5401phy_dsp(tp);
3234                         if (err)
3235                                 return err;
3236
3237                         tg3_readphy(tp, MII_BMSR, &bmsr);
3238                         for (i = 0; i < 1000; i++) {
3239                                 udelay(10);
3240                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3241                                     (bmsr & BMSR_LSTATUS)) {
3242                                         udelay(40);
3243                                         break;
3244                                 }
3245                         }
3246
3247                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3248                             TG3_PHY_REV_BCM5401_B0 &&
3249                             !(bmsr & BMSR_LSTATUS) &&
3250                             tp->link_config.active_speed == SPEED_1000) {
3251                                 err = tg3_phy_reset(tp);
3252                                 if (!err)
3253                                         err = tg3_init_5401phy_dsp(tp);
3254                                 if (err)
3255                                         return err;
3256                         }
3257                 }
3258         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3259                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3260                 /* 5701 {A0,B0} CRC bug workaround */
3261                 tg3_writephy(tp, 0x15, 0x0a75);
3262                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3263                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3264                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3265         }
3266
3267         /* Clear pending interrupts... */
3268         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3269         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3270
3271         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3272                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3273         else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3274                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3275
3276         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3277             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3278                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3279                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3280                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3281                 else
3282                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3283         }
3284
3285         current_link_up = 0;
3286         current_speed = SPEED_INVALID;
3287         current_duplex = DUPLEX_INVALID;
3288
3289         if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3290                 err = tg3_phy_auxctl_read(tp,
3291                                           MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
3292                                           &val);
3293                 if (!err && !(val & (1 << 10))) {
3294                         tg3_phy_auxctl_write(tp,
3295                                              MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
3296                                              val | (1 << 10));
3297                         goto relink;
3298                 }
3299         }
3300
3301         bmsr = 0;
3302         for (i = 0; i < 100; i++) {
3303                 tg3_readphy(tp, MII_BMSR, &bmsr);
3304                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3305                     (bmsr & BMSR_LSTATUS))
3306                         break;
3307                 udelay(40);
3308         }
3309
3310         if (bmsr & BMSR_LSTATUS) {
3311                 u32 aux_stat, bmcr;
3312
3313                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3314                 for (i = 0; i < 2000; i++) {
3315                         udelay(10);
3316                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3317                             aux_stat)
3318                                 break;
3319                 }
3320
3321                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3322                                              &current_speed,
3323                                              &current_duplex);
3324
3325                 bmcr = 0;
3326                 for (i = 0; i < 200; i++) {
3327                         tg3_readphy(tp, MII_BMCR, &bmcr);
3328                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3329                                 continue;
3330                         if (bmcr && bmcr != 0x7fff)
3331                                 break;
3332                         udelay(10);
3333                 }
3334
3335                 lcl_adv = 0;
3336                 rmt_adv = 0;
3337
3338                 tp->link_config.active_speed = current_speed;
3339                 tp->link_config.active_duplex = current_duplex;
3340
3341                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3342                         if ((bmcr & BMCR_ANENABLE) &&
3343                             tg3_copper_is_advertising_all(tp,
3344                                                 tp->link_config.advertising)) {
3345                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3346                                                                   &rmt_adv))
3347                                         current_link_up = 1;
3348                         }
3349                 } else {
3350                         if (!(bmcr & BMCR_ANENABLE) &&
3351                             tp->link_config.speed == current_speed &&
3352                             tp->link_config.duplex == current_duplex &&
3353                             tp->link_config.flowctrl ==
3354                             tp->link_config.active_flowctrl) {
3355                                 current_link_up = 1;
3356                         }
3357                 }
3358
3359                 if (current_link_up == 1 &&
3360                     tp->link_config.active_duplex == DUPLEX_FULL)
3361                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3362         }
3363
3364 relink:
3365         if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3366                 tg3_phy_copper_begin(tp);
3367
3368                 tg3_readphy(tp, MII_BMSR, &bmsr);
3369                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3370                     (bmsr & BMSR_LSTATUS))
3371                         current_link_up = 1;
3372         }
3373
3374         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3375         if (current_link_up == 1) {
3376                 if (tp->link_config.active_speed == SPEED_100 ||
3377                     tp->link_config.active_speed == SPEED_10)
3378                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3379                 else
3380                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3381         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3382                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3383         else
3384                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3385
3386         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3387         if (tp->link_config.active_duplex == DUPLEX_HALF)
3388                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3389
3390         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3391                 if (current_link_up == 1 &&
3392                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3393                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3394                 else
3395                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3396         }
3397
3398         /* ??? Without this setting Netgear GA302T PHY does not
3399          * ??? send/receive packets...
3400          */
3401         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3402             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3403                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3404                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3405                 udelay(80);
3406         }
3407
3408         tw32_f(MAC_MODE, tp->mac_mode);
3409         udelay(40);
3410
3411         tg3_phy_eee_adjust(tp, current_link_up);
3412
3413         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3414                 /* Polled via timer. */
3415                 tw32_f(MAC_EVENT, 0);
3416         } else {
3417                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3418         }
3419         udelay(40);
3420
3421         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3422             current_link_up == 1 &&
3423             tp->link_config.active_speed == SPEED_1000 &&
3424             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3425              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3426                 udelay(120);
3427                 tw32_f(MAC_STATUS,
3428                      (MAC_STATUS_SYNC_CHANGED |
3429                       MAC_STATUS_CFG_CHANGED));
3430                 udelay(40);
3431                 tg3_write_mem(tp,
3432                               NIC_SRAM_FIRMWARE_MBOX,
3433                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3434         }
3435
3436         /* Prevent send BD corruption. */
3437         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3438                 u16 oldlnkctl, newlnkctl;
3439
3440                 pci_read_config_word(tp->pdev,
3441                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3442                                      &oldlnkctl);
3443                 if (tp->link_config.active_speed == SPEED_100 ||
3444                     tp->link_config.active_speed == SPEED_10)
3445                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3446                 else
3447                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3448                 if (newlnkctl != oldlnkctl)
3449                         pci_write_config_word(tp->pdev,
3450                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3451                                               newlnkctl);
3452         }
3453
3454         if (current_link_up != netif_carrier_ok(tp->dev)) {
3455                 if (current_link_up)
3456                         netif_carrier_on(tp->dev);
3457                 else
3458                         netif_carrier_off(tp->dev);
3459                 tg3_link_report(tp);
3460         }
3461
3462         return 0;
3463 }
3464
3465 struct tg3_fiber_aneginfo {
3466         int state;
3467 #define ANEG_STATE_UNKNOWN              0
3468 #define ANEG_STATE_AN_ENABLE            1
3469 #define ANEG_STATE_RESTART_INIT         2
3470 #define ANEG_STATE_RESTART              3
3471 #define ANEG_STATE_DISABLE_LINK_OK      4
3472 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3473 #define ANEG_STATE_ABILITY_DETECT       6
3474 #define ANEG_STATE_ACK_DETECT_INIT      7
3475 #define ANEG_STATE_ACK_DETECT           8
3476 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3477 #define ANEG_STATE_COMPLETE_ACK         10
3478 #define ANEG_STATE_IDLE_DETECT_INIT     11
3479 #define ANEG_STATE_IDLE_DETECT          12
3480 #define ANEG_STATE_LINK_OK              13
3481 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3482 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3483
3484         u32 flags;
3485 #define MR_AN_ENABLE            0x00000001
3486 #define MR_RESTART_AN           0x00000002
3487 #define MR_AN_COMPLETE          0x00000004
3488 #define MR_PAGE_RX              0x00000008
3489 #define MR_NP_LOADED            0x00000010
3490 #define MR_TOGGLE_TX            0x00000020
3491 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3492 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3493 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3494 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3495 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3496 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3497 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3498 #define MR_TOGGLE_RX            0x00002000
3499 #define MR_NP_RX                0x00004000
3500
3501 #define MR_LINK_OK              0x80000000
3502
3503         unsigned long link_time, cur_time;
3504
3505         u32 ability_match_cfg;
3506         int ability_match_count;
3507
3508         char ability_match, idle_match, ack_match;
3509
3510         u32 txconfig, rxconfig;
3511 #define ANEG_CFG_NP             0x00000080
3512 #define ANEG_CFG_ACK            0x00000040
3513 #define ANEG_CFG_RF2            0x00000020
3514 #define ANEG_CFG_RF1            0x00000010
3515 #define ANEG_CFG_PS2            0x00000001
3516 #define ANEG_CFG_PS1            0x00008000
3517 #define ANEG_CFG_HD             0x00004000
3518 #define ANEG_CFG_FD             0x00002000
3519 #define ANEG_CFG_INVAL          0x00001f06
3520
3521 };
3522 #define ANEG_OK         0
3523 #define ANEG_DONE       1
3524 #define ANEG_TIMER_ENAB 2
3525 #define ANEG_FAILED     -1
3526
3527 #define ANEG_STATE_SETTLE_TIME  10000
3528
3529 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3530                                    struct tg3_fiber_aneginfo *ap)
3531 {
3532         u16 flowctrl;
3533         unsigned long delta;
3534         u32 rx_cfg_reg;
3535         int ret;
3536
3537         if (ap->state == ANEG_STATE_UNKNOWN) {
3538                 ap->rxconfig = 0;
3539                 ap->link_time = 0;
3540                 ap->cur_time = 0;
3541                 ap->ability_match_cfg = 0;
3542                 ap->ability_match_count = 0;
3543                 ap->ability_match = 0;
3544                 ap->idle_match = 0;
3545                 ap->ack_match = 0;
3546         }
3547         ap->cur_time++;
3548
3549         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3550                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3551
3552                 if (rx_cfg_reg != ap->ability_match_cfg) {
3553                         ap->ability_match_cfg = rx_cfg_reg;
3554                         ap->ability_match = 0;
3555                         ap->ability_match_count = 0;
3556                 } else {
3557                         if (++ap->ability_match_count > 1) {
3558                                 ap->ability_match = 1;
3559                                 ap->ability_match_cfg = rx_cfg_reg;
3560                         }
3561                 }
3562                 if (rx_cfg_reg & ANEG_CFG_ACK)
3563                         ap->ack_match = 1;
3564                 else
3565                         ap->ack_match = 0;
3566
3567                 ap->idle_match = 0;
3568         } else {
3569                 ap->idle_match = 1;
3570                 ap->ability_match_cfg = 0;
3571                 ap->ability_match_count = 0;
3572                 ap->ability_match = 0;
3573                 ap->ack_match = 0;
3574
3575                 rx_cfg_reg = 0;
3576         }
3577
3578         ap->rxconfig = rx_cfg_reg;
3579         ret = ANEG_OK;
3580
3581         switch (ap->state) {
3582         case ANEG_STATE_UNKNOWN:
3583                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3584                         ap->state = ANEG_STATE_AN_ENABLE;
3585
3586                 /* fallthru */
3587         case ANEG_STATE_AN_ENABLE:
3588                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3589                 if (ap->flags & MR_AN_ENABLE) {
3590                         ap->link_time = 0;
3591                         ap->cur_time = 0;
3592                         ap->ability_match_cfg = 0;
3593                         ap->ability_match_count = 0;
3594                         ap->ability_match = 0;
3595                         ap->idle_match = 0;
3596                         ap->ack_match = 0;
3597
3598                         ap->state = ANEG_STATE_RESTART_INIT;
3599                 } else {
3600                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3601                 }
3602                 break;
3603
3604         case ANEG_STATE_RESTART_INIT:
3605                 ap->link_time = ap->cur_time;
3606                 ap->flags &= ~(MR_NP_LOADED);
3607                 ap->txconfig = 0;
3608                 tw32(MAC_TX_AUTO_NEG, 0);
3609                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3610                 tw32_f(MAC_MODE, tp->mac_mode);
3611                 udelay(40);
3612
3613                 ret = ANEG_TIMER_ENAB;
3614                 ap->state = ANEG_STATE_RESTART;
3615
3616                 /* fallthru */
3617         case ANEG_STATE_RESTART:
3618                 delta = ap->cur_time - ap->link_time;
3619                 if (delta > ANEG_STATE_SETTLE_TIME)
3620                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3621                 else
3622                         ret = ANEG_TIMER_ENAB;
3623                 break;
3624
3625         case ANEG_STATE_DISABLE_LINK_OK:
3626                 ret = ANEG_DONE;
3627                 break;
3628
3629         case ANEG_STATE_ABILITY_DETECT_INIT:
3630                 ap->flags &= ~(MR_TOGGLE_TX);
3631                 ap->txconfig = ANEG_CFG_FD;
3632                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3633                 if (flowctrl & ADVERTISE_1000XPAUSE)
3634                         ap->txconfig |= ANEG_CFG_PS1;
3635                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3636                         ap->txconfig |= ANEG_CFG_PS2;
3637                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3638                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3639                 tw32_f(MAC_MODE, tp->mac_mode);
3640                 udelay(40);
3641
3642                 ap->state = ANEG_STATE_ABILITY_DETECT;
3643                 break;
3644
3645         case ANEG_STATE_ABILITY_DETECT:
3646                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3647                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3648                 break;
3649
3650         case ANEG_STATE_ACK_DETECT_INIT:
3651                 ap->txconfig |= ANEG_CFG_ACK;
3652                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3653                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3654                 tw32_f(MAC_MODE, tp->mac_mode);
3655                 udelay(40);
3656
3657                 ap->state = ANEG_STATE_ACK_DETECT;
3658
3659                 /* fallthru */
3660         case ANEG_STATE_ACK_DETECT:
3661                 if (ap->ack_match != 0) {
3662                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3663                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3664                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3665                         } else {
3666                                 ap->state = ANEG_STATE_AN_ENABLE;
3667                         }
3668                 } else if (ap->ability_match != 0 &&
3669                            ap->rxconfig == 0) {
3670                         ap->state = ANEG_STATE_AN_ENABLE;
3671                 }
3672                 break;
3673
3674         case ANEG_STATE_COMPLETE_ACK_INIT:
3675                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3676                         ret = ANEG_FAILED;
3677                         break;
3678                 }
3679                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3680                                MR_LP_ADV_HALF_DUPLEX |
3681                                MR_LP_ADV_SYM_PAUSE |
3682                                MR_LP_ADV_ASYM_PAUSE |
3683                                MR_LP_ADV_REMOTE_FAULT1 |
3684                                MR_LP_ADV_REMOTE_FAULT2 |
3685                                MR_LP_ADV_NEXT_PAGE |
3686                                MR_TOGGLE_RX |
3687                                MR_NP_RX);
3688                 if (ap->rxconfig & ANEG_CFG_FD)
3689                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3690                 if (ap->rxconfig & ANEG_CFG_HD)
3691                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3692                 if (ap->rxconfig & ANEG_CFG_PS1)
3693                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3694                 if (ap->rxconfig & ANEG_CFG_PS2)
3695                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3696                 if (ap->rxconfig & ANEG_CFG_RF1)
3697                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3698                 if (ap->rxconfig & ANEG_CFG_RF2)
3699                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3700                 if (ap->rxconfig & ANEG_CFG_NP)
3701                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3702
3703                 ap->link_time = ap->cur_time;
3704
3705                 ap->flags ^= (MR_TOGGLE_TX);
3706                 if (ap->rxconfig & 0x0008)
3707                         ap->flags |= MR_TOGGLE_RX;
3708                 if (ap->rxconfig & ANEG_CFG_NP)
3709                         ap->flags |= MR_NP_RX;
3710                 ap->flags |= MR_PAGE_RX;
3711
3712                 ap->state = ANEG_STATE_COMPLETE_ACK;
3713                 ret = ANEG_TIMER_ENAB;
3714                 break;
3715
3716         case ANEG_STATE_COMPLETE_ACK:
3717                 if (ap->ability_match != 0 &&
3718                     ap->rxconfig == 0) {
3719                         ap->state = ANEG_STATE_AN_ENABLE;
3720                         break;
3721                 }
3722                 delta = ap->cur_time - ap->link_time;
3723                 if (delta > ANEG_STATE_SETTLE_TIME) {
3724                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3725                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3726                         } else {
3727                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3728                                     !(ap->flags & MR_NP_RX)) {
3729                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3730                                 } else {
3731                                         ret = ANEG_FAILED;
3732                                 }
3733                         }
3734                 }
3735                 break;
3736
3737         case ANEG_STATE_IDLE_DETECT_INIT:
3738                 ap->link_time = ap->cur_time;
3739                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3740                 tw32_f(MAC_MODE, tp->mac_mode);
3741                 udelay(40);
3742
3743                 ap->state = ANEG_STATE_IDLE_DETECT;
3744                 ret = ANEG_TIMER_ENAB;
3745                 break;
3746
3747         case ANEG_STATE_IDLE_DETECT:
3748                 if (ap->ability_match != 0 &&
3749                     ap->rxconfig == 0) {
3750                         ap->state = ANEG_STATE_AN_ENABLE;
3751                         break;
3752                 }
3753                 delta = ap->cur_time - ap->link_time;
3754                 if (delta > ANEG_STATE_SETTLE_TIME) {
3755                         /* XXX another gem from the Broadcom driver :( */
3756                         ap->state = ANEG_STATE_LINK_OK;
3757                 }
3758                 break;
3759
3760         case ANEG_STATE_LINK_OK:
3761                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3762                 ret = ANEG_DONE;
3763                 break;
3764
3765         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3766                 /* ??? unimplemented */
3767                 break;
3768
3769         case ANEG_STATE_NEXT_PAGE_WAIT:
3770                 /* ??? unimplemented */
3771                 break;
3772
3773         default:
3774                 ret = ANEG_FAILED;
3775                 break;
3776         }
3777
3778         return ret;
3779 }
3780
3781 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3782 {
3783         int res = 0;
3784         struct tg3_fiber_aneginfo aninfo;
3785         int status = ANEG_FAILED;
3786         unsigned int tick;
3787         u32 tmp;
3788
3789         tw32_f(MAC_TX_AUTO_NEG, 0);
3790
3791         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3792         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3793         udelay(40);
3794
3795         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3796         udelay(40);
3797
3798         memset(&aninfo, 0, sizeof(aninfo));
3799         aninfo.flags |= MR_AN_ENABLE;
3800         aninfo.state = ANEG_STATE_UNKNOWN;
3801         aninfo.cur_time = 0;
3802         tick = 0;
3803         while (++tick < 195000) {
3804                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3805                 if (status == ANEG_DONE || status == ANEG_FAILED)
3806                         break;
3807
3808                 udelay(1);
3809         }
3810
3811         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3812         tw32_f(MAC_MODE, tp->mac_mode);
3813         udelay(40);
3814
3815         *txflags = aninfo.txconfig;
3816         *rxflags = aninfo.flags;
3817
3818         if (status == ANEG_DONE &&
3819             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3820                              MR_LP_ADV_FULL_DUPLEX)))
3821                 res = 1;
3822
3823         return res;
3824 }
3825
3826 static void tg3_init_bcm8002(struct tg3 *tp)
3827 {
3828         u32 mac_status = tr32(MAC_STATUS);
3829         int i;
3830
3831         /* Reset when initting first time or we have a link. */
3832         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3833             !(mac_status & MAC_STATUS_PCS_SYNCED))
3834                 return;
3835
3836         /* Set PLL lock range. */
3837         tg3_writephy(tp, 0x16, 0x8007);
3838
3839         /* SW reset */
3840         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3841
3842         /* Wait for reset to complete. */
3843         /* XXX schedule_timeout() ... */
3844         for (i = 0; i < 500; i++)
3845                 udelay(10);
3846
3847         /* Config mode; select PMA/Ch 1 regs. */
3848         tg3_writephy(tp, 0x10, 0x8411);
3849
3850         /* Enable auto-lock and comdet, select txclk for tx. */
3851         tg3_writephy(tp, 0x11, 0x0a10);
3852
3853         tg3_writephy(tp, 0x18, 0x00a0);
3854         tg3_writephy(tp, 0x16, 0x41ff);
3855
3856         /* Assert and deassert POR. */
3857         tg3_writephy(tp, 0x13, 0x0400);
3858         udelay(40);
3859         tg3_writephy(tp, 0x13, 0x0000);
3860
3861         tg3_writephy(tp, 0x11, 0x0a50);
3862         udelay(40);
3863         tg3_writephy(tp, 0x11, 0x0a10);
3864
3865         /* Wait for signal to stabilize */
3866         /* XXX schedule_timeout() ... */
3867         for (i = 0; i < 15000; i++)
3868                 udelay(10);
3869
3870         /* Deselect the channel register so we can read the PHYID
3871          * later.
3872          */
3873         tg3_writephy(tp, 0x10, 0x8011);
3874 }
3875
3876 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3877 {
3878         u16 flowctrl;
3879         u32 sg_dig_ctrl, sg_dig_status;
3880         u32 serdes_cfg, expected_sg_dig_ctrl;
3881         int workaround, port_a;
3882         int current_link_up;
3883
3884         serdes_cfg = 0;
3885         expected_sg_dig_ctrl = 0;
3886         workaround = 0;
3887         port_a = 1;
3888         current_link_up = 0;
3889
3890         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3891             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3892                 workaround = 1;
3893                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3894                         port_a = 0;
3895
3896                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3897                 /* preserve bits 20-23 for voltage regulator */
3898                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3899         }
3900
3901         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3902
3903         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3904                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3905                         if (workaround) {
3906                                 u32 val = serdes_cfg;
3907
3908                                 if (port_a)
3909                                         val |= 0xc010000;
3910                                 else
3911                                         val |= 0x4010000;
3912                                 tw32_f(MAC_SERDES_CFG, val);
3913                         }
3914
3915                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3916                 }
3917                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3918                         tg3_setup_flow_control(tp, 0, 0);
3919                         current_link_up = 1;
3920                 }
3921                 goto out;
3922         }
3923
3924         /* Want auto-negotiation.  */
3925         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3926
3927         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3928         if (flowctrl & ADVERTISE_1000XPAUSE)
3929                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3930         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3931                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3932
3933         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3934                 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3935                     tp->serdes_counter &&
3936                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3937                                     MAC_STATUS_RCVD_CFG)) ==
3938                      MAC_STATUS_PCS_SYNCED)) {
3939                         tp->serdes_counter--;
3940                         current_link_up = 1;
3941                         goto out;
3942                 }
3943 restart_autoneg:
3944                 if (workaround)
3945                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3946                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3947                 udelay(5);
3948                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3949
3950                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3951                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3952         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3953                                  MAC_STATUS_SIGNAL_DET)) {
3954                 sg_dig_status = tr32(SG_DIG_STATUS);
3955                 mac_status = tr32(MAC_STATUS);
3956
3957                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3958                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3959                         u32 local_adv = 0, remote_adv = 0;
3960
3961                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3962                                 local_adv |= ADVERTISE_1000XPAUSE;
3963                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3964                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3965
3966                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3967                                 remote_adv |= LPA_1000XPAUSE;
3968                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3969                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3970
3971                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3972                         current_link_up = 1;
3973                         tp->serdes_counter = 0;
3974                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3975                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3976                         if (tp->serdes_counter)
3977                                 tp->serdes_counter--;
3978                         else {
3979                                 if (workaround) {
3980                                         u32 val = serdes_cfg;
3981
3982                                         if (port_a)
3983                                                 val |= 0xc010000;
3984                                         else
3985                                                 val |= 0x4010000;
3986
3987                                         tw32_f(MAC_SERDES_CFG, val);
3988                                 }
3989
3990                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3991                                 udelay(40);
3992
3993                                 /* Link parallel detection - link is up */
3994                                 /* only if we have PCS_SYNC and not */
3995                                 /* receiving config code words */
3996                                 mac_status = tr32(MAC_STATUS);
3997                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3998                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3999                                         tg3_setup_flow_control(tp, 0, 0);
4000                                         current_link_up = 1;
4001                                         tp->phy_flags |=
4002                                                 TG3_PHYFLG_PARALLEL_DETECT;
4003                                         tp->serdes_counter =
4004                                                 SERDES_PARALLEL_DET_TIMEOUT;
4005                                 } else
4006                                         goto restart_autoneg;
4007                         }
4008                 }
4009         } else {
4010                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
4011                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4012         }
4013
4014 out:
4015         return current_link_up;
4016 }
4017
4018 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
4019 {
4020         int current_link_up = 0;
4021
4022         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
4023                 goto out;
4024
4025         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4026                 u32 txflags, rxflags;
4027                 int i;
4028
4029                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
4030                         u32 local_adv = 0, remote_adv = 0;
4031
4032                         if (txflags & ANEG_CFG_PS1)
4033                                 local_adv |= ADVERTISE_1000XPAUSE;
4034                         if (txflags & ANEG_CFG_PS2)
4035                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
4036
4037                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
4038                                 remote_adv |= LPA_1000XPAUSE;
4039                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
4040                                 remote_adv |= LPA_1000XPAUSE_ASYM;
4041
4042                         tg3_setup_flow_control(tp, local_adv, remote_adv);
4043
4044                         current_link_up = 1;
4045                 }
4046                 for (i = 0; i < 30; i++) {
4047                         udelay(20);
4048                         tw32_f(MAC_STATUS,
4049                                (MAC_STATUS_SYNC_CHANGED |
4050                                 MAC_STATUS_CFG_CHANGED));
4051                         udelay(40);
4052                         if ((tr32(MAC_STATUS) &
4053                              (MAC_STATUS_SYNC_CHANGED |
4054                               MAC_STATUS_CFG_CHANGED)) == 0)
4055                                 break;
4056                 }
4057
4058                 mac_status = tr32(MAC_STATUS);
4059                 if (current_link_up == 0 &&
4060                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
4061                     !(mac_status & MAC_STATUS_RCVD_CFG))
4062                         current_link_up = 1;
4063         } else {
4064                 tg3_setup_flow_control(tp, 0, 0);
4065
4066                 /* Forcing 1000FD link up. */
4067                 current_link_up = 1;
4068
4069                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
4070                 udelay(40);
4071
4072                 tw32_f(MAC_MODE, tp->mac_mode);
4073                 udelay(40);
4074         }
4075
4076 out:
4077         return current_link_up;
4078 }
4079
4080 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4081 {
4082         u32 orig_pause_cfg;
4083         u16 orig_active_speed;
4084         u8 orig_active_duplex;
4085         u32 mac_status;
4086         int current_link_up;
4087         int i;
4088
4089         orig_pause_cfg = tp->link_config.active_flowctrl;
4090         orig_active_speed = tp->link_config.active_speed;
4091         orig_active_duplex = tp->link_config.active_duplex;
4092
4093         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
4094             netif_carrier_ok(tp->dev) &&
4095             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
4096                 mac_status = tr32(MAC_STATUS);
4097                 mac_status &= (MAC_STATUS_PCS_SYNCED |
4098                                MAC_STATUS_SIGNAL_DET |
4099                                MAC_STATUS_CFG_CHANGED |
4100                                MAC_STATUS_RCVD_CFG);
4101                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
4102                                    MAC_STATUS_SIGNAL_DET)) {
4103                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4104                                             MAC_STATUS_CFG_CHANGED));
4105                         return 0;
4106                 }
4107         }
4108
4109         tw32_f(MAC_TX_AUTO_NEG, 0);
4110
4111         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
4112         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
4113         tw32_f(MAC_MODE, tp->mac_mode);
4114         udelay(40);
4115
4116         if (tp->phy_id == TG3_PHY_ID_BCM8002)
4117                 tg3_init_bcm8002(tp);
4118
4119         /* Enable link change event even when serdes polling.  */
4120         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4121         udelay(40);
4122
4123         current_link_up = 0;
4124         mac_status = tr32(MAC_STATUS);
4125
4126         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
4127                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4128         else
4129                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4130
4131         tp->napi[0].hw_status->status =
4132                 (SD_STATUS_UPDATED |
4133                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4134
4135         for (i = 0; i < 100; i++) {
4136                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4137                                     MAC_STATUS_CFG_CHANGED));
4138                 udelay(5);
4139                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4140                                          MAC_STATUS_CFG_CHANGED |
4141                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4142                         break;
4143         }
4144
4145         mac_status = tr32(MAC_STATUS);
4146         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4147                 current_link_up = 0;
4148                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4149                     tp->serdes_counter == 0) {
4150                         tw32_f(MAC_MODE, (tp->mac_mode |
4151                                           MAC_MODE_SEND_CONFIGS));
4152                         udelay(1);
4153                         tw32_f(MAC_MODE, tp->mac_mode);
4154                 }
4155         }
4156
4157         if (current_link_up == 1) {
4158                 tp->link_config.active_speed = SPEED_1000;
4159                 tp->link_config.active_duplex = DUPLEX_FULL;
4160                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4161                                     LED_CTRL_LNKLED_OVERRIDE |
4162                                     LED_CTRL_1000MBPS_ON));
4163         } else {
4164                 tp->link_config.active_speed = SPEED_INVALID;
4165                 tp->link_config.active_duplex = DUPLEX_INVALID;
4166                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4167                                     LED_CTRL_LNKLED_OVERRIDE |
4168                                     LED_CTRL_TRAFFIC_OVERRIDE));
4169         }
4170
4171         if (current_link_up != netif_carrier_ok(tp->dev)) {
4172                 if (current_link_up)
4173                         netif_carrier_on(tp->dev);
4174                 else
4175                         netif_carrier_off(tp->dev);
4176                 tg3_link_report(tp);
4177         } else {
4178                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4179                 if (orig_pause_cfg != now_pause_cfg ||
4180                     orig_active_speed != tp->link_config.active_speed ||
4181                     orig_active_duplex != tp->link_config.active_duplex)
4182                         tg3_link_report(tp);
4183         }
4184
4185         return 0;
4186 }
4187
4188 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4189 {
4190         int current_link_up, err = 0;
4191         u32 bmsr, bmcr;
4192         u16 current_speed;
4193         u8 current_duplex;
4194         u32 local_adv, remote_adv;
4195
4196         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4197         tw32_f(MAC_MODE, tp->mac_mode);
4198         udelay(40);
4199
4200         tw32(MAC_EVENT, 0);
4201
4202         tw32_f(MAC_STATUS,
4203              (MAC_STATUS_SYNC_CHANGED |
4204               MAC_STATUS_CFG_CHANGED |
4205               MAC_STATUS_MI_COMPLETION |
4206               MAC_STATUS_LNKSTATE_CHANGED));
4207         udelay(40);
4208
4209         if (force_reset)
4210                 tg3_phy_reset(tp);
4211
4212         current_link_up = 0;
4213         current_speed = SPEED_INVALID;
4214         current_duplex = DUPLEX_INVALID;
4215
4216         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4217         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4218         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4219                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4220                         bmsr |= BMSR_LSTATUS;
4221                 else
4222                         bmsr &= ~BMSR_LSTATUS;
4223         }
4224
4225         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4226
4227         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4228             (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4229                 /* do nothing, just check for link up at the end */
4230         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4231                 u32 adv, new_adv;
4232
4233                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4234                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4235                                   ADVERTISE_1000XPAUSE |
4236                                   ADVERTISE_1000XPSE_ASYM |
4237                                   ADVERTISE_SLCT);
4238
4239                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4240
4241                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4242                         new_adv |= ADVERTISE_1000XHALF;
4243                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4244                         new_adv |= ADVERTISE_1000XFULL;
4245
4246                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4247                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4248                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4249                         tg3_writephy(tp, MII_BMCR, bmcr);
4250
4251                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4252                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4253                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4254
4255                         return err;
4256                 }
4257         } else {
4258                 u32 new_bmcr;
4259
4260                 bmcr &= ~BMCR_SPEED1000;
4261                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4262
4263                 if (tp->link_config.duplex == DUPLEX_FULL)
4264                         new_bmcr |= BMCR_FULLDPLX;
4265
4266                 if (new_bmcr != bmcr) {
4267                         /* BMCR_SPEED1000 is a reserved bit that needs
4268                          * to be set on write.
4269                          */
4270                         new_bmcr |= BMCR_SPEED1000;
4271
4272                         /* Force a linkdown */
4273                         if (netif_carrier_ok(tp->dev)) {
4274                                 u32 adv;
4275
4276                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4277                                 adv &= ~(ADVERTISE_1000XFULL |
4278                                          ADVERTISE_1000XHALF |
4279                                          ADVERTISE_SLCT);
4280                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4281                                 tg3_writephy(tp, MII_BMCR, bmcr |
4282                                                            BMCR_ANRESTART |
4283                                                            BMCR_ANENABLE);
4284                                 udelay(10);
4285                                 netif_carrier_off(tp->dev);
4286                         }
4287                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4288                         bmcr = new_bmcr;
4289                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4290                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4291                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4292                             ASIC_REV_5714) {
4293                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4294                                         bmsr |= BMSR_LSTATUS;
4295                                 else
4296                                         bmsr &= ~BMSR_LSTATUS;
4297                         }
4298                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4299                 }
4300         }
4301
4302         if (bmsr & BMSR_LSTATUS) {
4303                 current_speed = SPEED_1000;
4304                 current_link_up = 1;
4305                 if (bmcr & BMCR_FULLDPLX)
4306                         current_duplex = DUPLEX_FULL;
4307                 else
4308                         current_duplex = DUPLEX_HALF;
4309
4310                 local_adv = 0;
4311                 remote_adv = 0;
4312
4313                 if (bmcr & BMCR_ANENABLE) {
4314                         u32 common;
4315
4316                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4317                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4318                         common = local_adv & remote_adv;
4319                         if (common & (ADVERTISE_1000XHALF |
4320                                       ADVERTISE_1000XFULL)) {
4321                                 if (common & ADVERTISE_1000XFULL)
4322                                         current_duplex = DUPLEX_FULL;
4323                                 else
4324                                         current_duplex = DUPLEX_HALF;
4325                         } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4326                                 /* Link is up via parallel detect */
4327                         } else {
4328                                 current_link_up = 0;
4329                         }
4330                 }
4331         }
4332
4333         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4334                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4335
4336         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4337         if (tp->link_config.active_duplex == DUPLEX_HALF)
4338                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4339
4340         tw32_f(MAC_MODE, tp->mac_mode);
4341         udelay(40);
4342
4343         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4344
4345         tp->link_config.active_speed = current_speed;
4346         tp->link_config.active_duplex = current_duplex;
4347
4348         if (current_link_up != netif_carrier_ok(tp->dev)) {
4349                 if (current_link_up)
4350                         netif_carrier_on(tp->dev);
4351                 else {
4352                         netif_carrier_off(tp->dev);
4353                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4354                 }
4355                 tg3_link_report(tp);
4356         }
4357         return err;
4358 }
4359
4360 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4361 {
4362         if (tp->serdes_counter) {
4363                 /* Give autoneg time to complete. */
4364                 tp->serdes_counter--;
4365                 return;
4366         }
4367
4368         if (!netif_carrier_ok(tp->dev) &&
4369             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4370                 u32 bmcr;
4371
4372                 tg3_readphy(tp, MII_BMCR, &bmcr);
4373                 if (bmcr & BMCR_ANENABLE) {
4374                         u32 phy1, phy2;
4375
4376                         /* Select shadow register 0x1f */
4377                         tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4378                         tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4379
4380                         /* Select expansion interrupt status register */
4381                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4382                                          MII_TG3_DSP_EXP1_INT_STAT);
4383                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4384                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4385
4386                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4387                                 /* We have signal detect and not receiving
4388                                  * config code words, link is up by parallel
4389                                  * detection.
4390                                  */
4391
4392                                 bmcr &= ~BMCR_ANENABLE;
4393                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4394                                 tg3_writephy(tp, MII_BMCR, bmcr);
4395                                 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4396                         }
4397                 }
4398         } else if (netif_carrier_ok(tp->dev) &&
4399                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4400                    (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4401                 u32 phy2;
4402
4403                 /* Select expansion interrupt status register */
4404                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4405                                  MII_TG3_DSP_EXP1_INT_STAT);
4406                 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4407                 if (phy2 & 0x20) {
4408                         u32 bmcr;
4409
4410                         /* Config code words received, turn on autoneg. */
4411                         tg3_readphy(tp, MII_BMCR, &bmcr);
4412                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4413
4414                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4415
4416                 }
4417         }
4418 }
4419
4420 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4421 {
4422         u32 val;
4423         int err;
4424
4425         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4426                 err = tg3_setup_fiber_phy(tp, force_reset);
4427         else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4428                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4429         else
4430                 err = tg3_setup_copper_phy(tp, force_reset);
4431
4432         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4433                 u32 scale;
4434
4435                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4436                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4437                         scale = 65;
4438                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4439                         scale = 6;
4440                 else
4441                         scale = 12;
4442
4443                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4444                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4445                 tw32(GRC_MISC_CFG, val);
4446         }
4447
4448         val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4449               (6 << TX_LENGTHS_IPG_SHIFT);
4450         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
4451                 val |= tr32(MAC_TX_LENGTHS) &
4452                        (TX_LENGTHS_JMB_FRM_LEN_MSK |
4453                         TX_LENGTHS_CNT_DWN_VAL_MSK);
4454
4455         if (tp->link_config.active_speed == SPEED_1000 &&
4456             tp->link_config.active_duplex == DUPLEX_HALF)
4457                 tw32(MAC_TX_LENGTHS, val |
4458                      (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
4459         else
4460                 tw32(MAC_TX_LENGTHS, val |
4461                      (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
4462
4463         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4464                 if (netif_carrier_ok(tp->dev)) {
4465                         tw32(HOSTCC_STAT_COAL_TICKS,
4466                              tp->coal.stats_block_coalesce_usecs);
4467                 } else {
4468                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4469                 }
4470         }
4471
4472         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4473                 val = tr32(PCIE_PWR_MGMT_THRESH);
4474                 if (!netif_carrier_ok(tp->dev))
4475                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4476                               tp->pwrmgmt_thresh;
4477                 else
4478                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4479                 tw32(PCIE_PWR_MGMT_THRESH, val);
4480         }
4481
4482         return err;
4483 }
4484
4485 static inline int tg3_irq_sync(struct tg3 *tp)
4486 {
4487         return tp->irq_sync;
4488 }
4489
4490 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
4491 {
4492         int i;
4493
4494         dst = (u32 *)((u8 *)dst + off);
4495         for (i = 0; i < len; i += sizeof(u32))
4496                 *dst++ = tr32(off + i);
4497 }
4498
4499 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
4500 {
4501         tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
4502         tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
4503         tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
4504         tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
4505         tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
4506         tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
4507         tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
4508         tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
4509         tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
4510         tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
4511         tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
4512         tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
4513         tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
4514         tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
4515         tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
4516         tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
4517         tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
4518         tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
4519         tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
4520
4521         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX)
4522                 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
4523
4524         tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
4525         tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
4526         tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
4527         tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
4528         tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
4529         tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
4530         tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
4531         tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
4532
4533         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4534                 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
4535                 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
4536                 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
4537         }
4538
4539         tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
4540         tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
4541         tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
4542         tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
4543         tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
4544
4545         if (tp->tg3_flags & TG3_FLAG_NVRAM)
4546                 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
4547 }
4548
4549 static void tg3_dump_state(struct tg3 *tp)
4550 {
4551         int i;
4552         u32 *regs;
4553
4554         regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
4555         if (!regs) {
4556                 netdev_err(tp->dev, "Failed allocating register dump buffer\n");
4557                 return;
4558         }
4559
4560         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4561                 /* Read up to but not including private PCI registers */
4562                 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
4563                         regs[i / sizeof(u32)] = tr32(i);
4564         } else
4565                 tg3_dump_legacy_regs(tp, regs);
4566
4567         for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
4568                 if (!regs[i + 0] && !regs[i + 1] &&
4569                     !regs[i + 2] && !regs[i + 3])
4570                         continue;
4571
4572                 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
4573                            i * 4,
4574                            regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
4575         }
4576
4577         kfree(regs);
4578
4579         for (i = 0; i < tp->irq_cnt; i++) {
4580                 struct tg3_napi *tnapi = &tp->napi[i];
4581
4582                 /* SW status block */
4583                 netdev_err(tp->dev,
4584                          "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
4585                            i,
4586                            tnapi->hw_status->status,
4587                            tnapi->hw_status->status_tag,
4588                            tnapi->hw_status->rx_jumbo_consumer,
4589                            tnapi->hw_status->rx_consumer,
4590                            tnapi->hw_status->rx_mini_consumer,
4591                            tnapi->hw_status->idx[0].rx_producer,
4592                            tnapi->hw_status->idx[0].tx_consumer);
4593
4594                 netdev_err(tp->dev,
4595                 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
4596                            i,
4597                            tnapi->last_tag, tnapi->last_irq_tag,
4598                            tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
4599                            tnapi->rx_rcb_ptr,
4600                            tnapi->prodring.rx_std_prod_idx,
4601                            tnapi->prodring.rx_std_cons_idx,
4602                            tnapi->prodring.rx_jmb_prod_idx,
4603                            tnapi->prodring.rx_jmb_cons_idx);
4604         }
4605 }
4606
4607 /* This is called whenever we suspect that the system chipset is re-
4608  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4609  * is bogus tx completions. We try to recover by setting the
4610  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4611  * in the workqueue.
4612  */
4613 static void tg3_tx_recover(struct tg3 *tp)
4614 {
4615         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4616                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4617
4618         netdev_warn(tp->dev,
4619                     "The system may be re-ordering memory-mapped I/O "
4620                     "cycles to the network device, attempting to recover. "
4621                     "Please report the problem to the driver maintainer "
4622                     "and include system chipset information.\n");
4623
4624         spin_lock(&tp->lock);
4625         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4626         spin_unlock(&tp->lock);
4627 }
4628
4629 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4630 {
4631         /* Tell compiler to fetch tx indices from memory. */
4632         barrier();
4633         return tnapi->tx_pending -
4634                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4635 }
4636
4637 /* Tigon3 never reports partial packet sends.  So we do not
4638  * need special logic to handle SKBs that have not had all
4639  * of their frags sent yet, like SunGEM does.
4640  */
4641 static void tg3_tx(struct tg3_napi *tnapi)
4642 {
4643         struct tg3 *tp = tnapi->tp;
4644         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4645         u32 sw_idx = tnapi->tx_cons;
4646         struct netdev_queue *txq;
4647         int index = tnapi - tp->napi;
4648
4649         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4650                 index--;
4651
4652         txq = netdev_get_tx_queue(tp->dev, index);
4653
4654         while (sw_idx != hw_idx) {
4655                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4656                 struct sk_buff *skb = ri->skb;
4657                 int i, tx_bug = 0;
4658
4659                 if (unlikely(skb == NULL)) {
4660                         tg3_tx_recover(tp);
4661                         return;
4662                 }
4663
4664                 pci_unmap_single(tp->pdev,
4665                                  dma_unmap_addr(ri, mapping),
4666                                  skb_headlen(skb),
4667                                  PCI_DMA_TODEVICE);
4668
4669                 ri->skb = NULL;
4670
4671                 sw_idx = NEXT_TX(sw_idx);
4672
4673                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4674                         ri = &tnapi->tx_buffers[sw_idx];
4675                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4676                                 tx_bug = 1;
4677
4678                         pci_unmap_page(tp->pdev,
4679                                        dma_unmap_addr(ri, mapping),
4680                                        skb_shinfo(skb)->frags[i].size,
4681                                        PCI_DMA_TODEVICE);
4682                         sw_idx = NEXT_TX(sw_idx);
4683                 }
4684
4685                 dev_kfree_skb(skb);
4686
4687                 if (unlikely(tx_bug)) {
4688                         tg3_tx_recover(tp);
4689                         return;
4690                 }
4691         }
4692
4693         tnapi->tx_cons = sw_idx;
4694
4695         /* Need to make the tx_cons update visible to tg3_start_xmit()
4696          * before checking for netif_queue_stopped().  Without the
4697          * memory barrier, there is a small possibility that tg3_start_xmit()
4698          * will miss it and cause the queue to be stopped forever.
4699          */
4700         smp_mb();
4701
4702         if (unlikely(netif_tx_queue_stopped(txq) &&
4703                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4704                 __netif_tx_lock(txq, smp_processor_id());
4705                 if (netif_tx_queue_stopped(txq) &&
4706                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4707                         netif_tx_wake_queue(txq);
4708                 __netif_tx_unlock(txq);
4709         }
4710 }
4711
4712 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4713 {
4714         if (!ri->skb)
4715                 return;
4716
4717         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4718                          map_sz, PCI_DMA_FROMDEVICE);
4719         dev_kfree_skb_any(ri->skb);
4720         ri->skb = NULL;
4721 }
4722
4723 /* Returns size of skb allocated or < 0 on error.
4724  *
4725  * We only need to fill in the address because the other members
4726  * of the RX descriptor are invariant, see tg3_init_rings.
4727  *
4728  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4729  * posting buffers we only dirty the first cache line of the RX
4730  * descriptor (containing the address).  Whereas for the RX status
4731  * buffers the cpu only reads the last cacheline of the RX descriptor
4732  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4733  */
4734 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4735                             u32 opaque_key, u32 dest_idx_unmasked)
4736 {
4737         struct tg3_rx_buffer_desc *desc;
4738         struct ring_info *map;
4739         struct sk_buff *skb;
4740         dma_addr_t mapping;
4741         int skb_size, dest_idx;
4742
4743         switch (opaque_key) {
4744         case RXD_OPAQUE_RING_STD:
4745                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4746                 desc = &tpr->rx_std[dest_idx];
4747                 map = &tpr->rx_std_buffers[dest_idx];
4748                 skb_size = tp->rx_pkt_map_sz;
4749                 break;
4750
4751         case RXD_OPAQUE_RING_JUMBO:
4752                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4753                 desc = &tpr->rx_jmb[dest_idx].std;
4754                 map = &tpr->rx_jmb_buffers[dest_idx];
4755                 skb_size = TG3_RX_JMB_MAP_SZ;
4756                 break;
4757
4758         default:
4759                 return -EINVAL;
4760         }
4761
4762         /* Do not overwrite any of the map or rp information
4763          * until we are sure we can commit to a new buffer.
4764          *
4765          * Callers depend upon this behavior and assume that
4766          * we leave everything unchanged if we fail.
4767          */
4768         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4769         if (skb == NULL)
4770                 return -ENOMEM;
4771
4772         skb_reserve(skb, tp->rx_offset);
4773
4774         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4775                                  PCI_DMA_FROMDEVICE);
4776         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4777                 dev_kfree_skb(skb);
4778                 return -EIO;
4779         }
4780
4781         map->skb = skb;
4782         dma_unmap_addr_set(map, mapping, mapping);
4783
4784         desc->addr_hi = ((u64)mapping >> 32);
4785         desc->addr_lo = ((u64)mapping & 0xffffffff);
4786
4787         return skb_size;
4788 }
4789
4790 /* We only need to move over in the address because the other
4791  * members of the RX descriptor are invariant.  See notes above
4792  * tg3_alloc_rx_skb for full details.
4793  */
4794 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4795                            struct tg3_rx_prodring_set *dpr,
4796                            u32 opaque_key, int src_idx,
4797                            u32 dest_idx_unmasked)
4798 {
4799         struct tg3 *tp = tnapi->tp;
4800         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4801         struct ring_info *src_map, *dest_map;
4802         struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
4803         int dest_idx;
4804
4805         switch (opaque_key) {
4806         case RXD_OPAQUE_RING_STD:
4807                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4808                 dest_desc = &dpr->rx_std[dest_idx];
4809                 dest_map = &dpr->rx_std_buffers[dest_idx];
4810                 src_desc = &spr->rx_std[src_idx];
4811                 src_map = &spr->rx_std_buffers[src_idx];
4812                 break;
4813
4814         case RXD_OPAQUE_RING_JUMBO:
4815                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4816                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4817                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4818                 src_desc = &spr->rx_jmb[src_idx].std;
4819                 src_map = &spr->rx_jmb_buffers[src_idx];
4820                 break;
4821
4822         default:
4823                 return;
4824         }
4825
4826         dest_map->skb = src_map->skb;
4827         dma_unmap_addr_set(dest_map, mapping,
4828                            dma_unmap_addr(src_map, mapping));
4829         dest_desc->addr_hi = src_desc->addr_hi;
4830         dest_desc->addr_lo = src_desc->addr_lo;
4831
4832         /* Ensure that the update to the skb happens after the physical
4833          * addresses have been transferred to the new BD location.
4834          */
4835         smp_wmb();
4836
4837         src_map->skb = NULL;
4838 }
4839
4840 /* The RX ring scheme is composed of multiple rings which post fresh
4841  * buffers to the chip, and one special ring the chip uses to report
4842  * status back to the host.
4843  *
4844  * The special ring reports the status of received packets to the
4845  * host.  The chip does not write into the original descriptor the
4846  * RX buffer was obtained from.  The chip simply takes the original
4847  * descriptor as provided by the host, updates the status and length
4848  * field, then writes this into the next status ring entry.
4849  *
4850  * Each ring the host uses to post buffers to the chip is described
4851  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4852  * it is first placed into the on-chip ram.  When the packet's length
4853  * is known, it walks down the TG3_BDINFO entries to select the ring.
4854  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4855  * which is within the range of the new packet's length is chosen.
4856  *
4857  * The "separate ring for rx status" scheme may sound queer, but it makes
4858  * sense from a cache coherency perspective.  If only the host writes
4859  * to the buffer post rings, and only the chip writes to the rx status
4860  * rings, then cache lines never move beyond shared-modified state.
4861  * If both the host and chip were to write into the same ring, cache line
4862  * eviction could occur since both entities want it in an exclusive state.
4863  */
4864 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4865 {
4866         struct tg3 *tp = tnapi->tp;
4867         u32 work_mask, rx_std_posted = 0;
4868         u32 std_prod_idx, jmb_prod_idx;
4869         u32 sw_idx = tnapi->rx_rcb_ptr;
4870         u16 hw_idx;
4871         int received;
4872         struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
4873
4874         hw_idx = *(tnapi->rx_rcb_prod_idx);
4875         /*
4876          * We need to order the read of hw_idx and the read of
4877          * the opaque cookie.
4878          */
4879         rmb();
4880         work_mask = 0;
4881         received = 0;
4882         std_prod_idx = tpr->rx_std_prod_idx;
4883         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4884         while (sw_idx != hw_idx && budget > 0) {
4885                 struct ring_info *ri;
4886                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4887                 unsigned int len;
4888                 struct sk_buff *skb;
4889                 dma_addr_t dma_addr;
4890                 u32 opaque_key, desc_idx, *post_ptr;
4891
4892                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4893                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4894                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4895                         ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4896                         dma_addr = dma_unmap_addr(ri, mapping);
4897                         skb = ri->skb;
4898                         post_ptr = &std_prod_idx;
4899                         rx_std_posted++;
4900                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4901                         ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4902                         dma_addr = dma_unmap_addr(ri, mapping);
4903                         skb = ri->skb;
4904                         post_ptr = &jmb_prod_idx;
4905                 } else
4906                         goto next_pkt_nopost;
4907
4908                 work_mask |= opaque_key;
4909
4910                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4911                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4912                 drop_it:
4913                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4914                                        desc_idx, *post_ptr);
4915                 drop_it_no_recycle:
4916                         /* Other statistics kept track of by card. */
4917                         tp->rx_dropped++;
4918                         goto next_pkt;
4919                 }
4920
4921                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4922                       ETH_FCS_LEN;
4923
4924                 if (len > TG3_RX_COPY_THRESH(tp)) {
4925                         int skb_size;
4926
4927                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4928                                                     *post_ptr);
4929                         if (skb_size < 0)
4930                                 goto drop_it;
4931
4932                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4933                                          PCI_DMA_FROMDEVICE);
4934
4935                         /* Ensure that the update to the skb happens
4936                          * after the usage of the old DMA mapping.
4937                          */
4938                         smp_wmb();
4939
4940                         ri->skb = NULL;
4941
4942                         skb_put(skb, len);
4943                 } else {
4944                         struct sk_buff *copy_skb;
4945
4946                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4947                                        desc_idx, *post_ptr);
4948
4949                         copy_skb = netdev_alloc_skb(tp->dev, len +
4950                                                     TG3_RAW_IP_ALIGN);
4951                         if (copy_skb == NULL)
4952                                 goto drop_it_no_recycle;
4953
4954                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4955                         skb_put(copy_skb, len);
4956                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4957                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4958                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4959
4960                         /* We'll reuse the original ring buffer. */
4961                         skb = copy_skb;
4962                 }
4963
4964                 if ((tp->dev->features & NETIF_F_RXCSUM) &&
4965                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4966                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4967                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4968                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4969                 else
4970                         skb_checksum_none_assert(skb);
4971
4972                 skb->protocol = eth_type_trans(skb, tp->dev);
4973
4974                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4975                     skb->protocol != htons(ETH_P_8021Q)) {
4976                         dev_kfree_skb(skb);
4977                         goto drop_it_no_recycle;
4978                 }
4979
4980                 if (desc->type_flags & RXD_FLAG_VLAN &&
4981                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
4982                         __vlan_hwaccel_put_tag(skb,
4983                                                desc->err_vlan & RXD_VLAN_MASK);
4984
4985                 napi_gro_receive(&tnapi->napi, skb);
4986
4987                 received++;
4988                 budget--;
4989
4990 next_pkt:
4991                 (*post_ptr)++;
4992
4993                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4994                         tpr->rx_std_prod_idx = std_prod_idx &
4995                                                tp->rx_std_ring_mask;
4996                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4997                                      tpr->rx_std_prod_idx);
4998                         work_mask &= ~RXD_OPAQUE_RING_STD;
4999                         rx_std_posted = 0;
5000                 }
5001 next_pkt_nopost:
5002                 sw_idx++;
5003                 sw_idx &= tp->rx_ret_ring_mask;
5004
5005                 /* Refresh hw_idx to see if there is new work */
5006                 if (sw_idx == hw_idx) {
5007                         hw_idx = *(tnapi->rx_rcb_prod_idx);
5008                         rmb();
5009                 }
5010         }
5011
5012         /* ACK the status ring. */
5013         tnapi->rx_rcb_ptr = sw_idx;
5014         tw32_rx_mbox(tnapi->consmbox, sw_idx);
5015
5016         /* Refill RX ring(s). */
5017         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
5018                 if (work_mask & RXD_OPAQUE_RING_STD) {
5019                         tpr->rx_std_prod_idx = std_prod_idx &
5020                                                tp->rx_std_ring_mask;
5021                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5022                                      tpr->rx_std_prod_idx);
5023                 }
5024                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
5025                         tpr->rx_jmb_prod_idx = jmb_prod_idx &
5026                                                tp->rx_jmb_ring_mask;
5027                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5028                                      tpr->rx_jmb_prod_idx);
5029                 }
5030                 mmiowb();
5031         } else if (work_mask) {
5032                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
5033                  * updated before the producer indices can be updated.
5034                  */
5035                 smp_wmb();
5036
5037                 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
5038                 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
5039
5040                 if (tnapi != &tp->napi[1])
5041                         napi_schedule(&tp->napi[1].napi);
5042         }
5043
5044         return received;
5045 }
5046
5047 static void tg3_poll_link(struct tg3 *tp)
5048 {
5049         /* handle link change and other phy events */
5050         if (!(tp->tg3_flags &
5051               (TG3_FLAG_USE_LINKCHG_REG |
5052                TG3_FLAG_POLL_SERDES))) {
5053                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
5054
5055                 if (sblk->status & SD_STATUS_LINK_CHG) {
5056                         sblk->status = SD_STATUS_UPDATED |
5057                                        (sblk->status & ~SD_STATUS_LINK_CHG);
5058                         spin_lock(&tp->lock);
5059                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
5060                                 tw32_f(MAC_STATUS,
5061                                      (MAC_STATUS_SYNC_CHANGED |
5062                                       MAC_STATUS_CFG_CHANGED |
5063                                       MAC_STATUS_MI_COMPLETION |
5064                                       MAC_STATUS_LNKSTATE_CHANGED));
5065                                 udelay(40);
5066                         } else
5067                                 tg3_setup_phy(tp, 0);
5068                         spin_unlock(&tp->lock);
5069                 }
5070         }
5071 }
5072
5073 static int tg3_rx_prodring_xfer(struct tg3 *tp,
5074                                 struct tg3_rx_prodring_set *dpr,
5075                                 struct tg3_rx_prodring_set *spr)
5076 {
5077         u32 si, di, cpycnt, src_prod_idx;
5078         int i, err = 0;
5079
5080         while (1) {
5081                 src_prod_idx = spr->rx_std_prod_idx;
5082
5083                 /* Make sure updates to the rx_std_buffers[] entries and the
5084                  * standard producer index are seen in the correct order.
5085                  */
5086                 smp_rmb();
5087
5088                 if (spr->rx_std_cons_idx == src_prod_idx)
5089                         break;
5090
5091                 if (spr->rx_std_cons_idx < src_prod_idx)
5092                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
5093                 else
5094                         cpycnt = tp->rx_std_ring_mask + 1 -
5095                                  spr->rx_std_cons_idx;
5096
5097                 cpycnt = min(cpycnt,
5098                              tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
5099
5100                 si = spr->rx_std_cons_idx;
5101                 di = dpr->rx_std_prod_idx;
5102
5103                 for (i = di; i < di + cpycnt; i++) {
5104                         if (dpr->rx_std_buffers[i].skb) {
5105                                 cpycnt = i - di;
5106                                 err = -ENOSPC;
5107                                 break;
5108                         }
5109                 }
5110
5111                 if (!cpycnt)
5112                         break;
5113
5114                 /* Ensure that updates to the rx_std_buffers ring and the
5115                  * shadowed hardware producer ring from tg3_recycle_skb() are
5116                  * ordered correctly WRT the skb check above.
5117                  */
5118                 smp_rmb();
5119
5120                 memcpy(&dpr->rx_std_buffers[di],
5121                        &spr->rx_std_buffers[si],
5122                        cpycnt * sizeof(struct ring_info));
5123
5124                 for (i = 0; i < cpycnt; i++, di++, si++) {
5125                         struct tg3_rx_buffer_desc *sbd, *dbd;
5126                         sbd = &spr->rx_std[si];
5127                         dbd = &dpr->rx_std[di];
5128                         dbd->addr_hi = sbd->addr_hi;
5129                         dbd->addr_lo = sbd->addr_lo;
5130                 }
5131
5132                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
5133                                        tp->rx_std_ring_mask;
5134                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
5135                                        tp->rx_std_ring_mask;
5136         }
5137
5138         while (1) {
5139                 src_prod_idx = spr->rx_jmb_prod_idx;
5140
5141                 /* Make sure updates to the rx_jmb_buffers[] entries and
5142                  * the jumbo producer index are seen in the correct order.
5143                  */
5144                 smp_rmb();
5145
5146                 if (spr->rx_jmb_cons_idx == src_prod_idx)
5147                         break;
5148
5149                 if (spr->rx_jmb_cons_idx < src_prod_idx)
5150                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
5151                 else
5152                         cpycnt = tp->rx_jmb_ring_mask + 1 -
5153                                  spr->rx_jmb_cons_idx;
5154
5155                 cpycnt = min(cpycnt,
5156                              tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
5157
5158                 si = spr->rx_jmb_cons_idx;
5159                 di = dpr->rx_jmb_prod_idx;
5160
5161                 for (i = di; i < di + cpycnt; i++) {
5162                         if (dpr->rx_jmb_buffers[i].skb) {
5163                                 cpycnt = i - di;
5164                                 err = -ENOSPC;
5165                                 break;
5166                         }
5167                 }
5168
5169                 if (!cpycnt)
5170                         break;
5171
5172                 /* Ensure that updates to the rx_jmb_buffers ring and the
5173                  * shadowed hardware producer ring from tg3_recycle_skb() are
5174                  * ordered correctly WRT the skb check above.
5175                  */
5176                 smp_rmb();
5177
5178                 memcpy(&dpr->rx_jmb_buffers[di],
5179                        &spr->rx_jmb_buffers[si],
5180                        cpycnt * sizeof(struct ring_info));
5181
5182                 for (i = 0; i < cpycnt; i++, di++, si++) {
5183                         struct tg3_rx_buffer_desc *sbd, *dbd;
5184                         sbd = &spr->rx_jmb[si].std;
5185                         dbd = &dpr->rx_jmb[di].std;
5186                         dbd->addr_hi = sbd->addr_hi;
5187                         dbd->addr_lo = sbd->addr_lo;
5188                 }
5189
5190                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
5191                                        tp->rx_jmb_ring_mask;
5192                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
5193                                        tp->rx_jmb_ring_mask;
5194         }
5195
5196         return err;
5197 }
5198
5199 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
5200 {
5201         struct tg3 *tp = tnapi->tp;
5202
5203         /* run TX completion thread */
5204         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
5205                 tg3_tx(tnapi);
5206                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5207                         return work_done;
5208         }
5209
5210         /* run RX thread, within the bounds set by NAPI.
5211          * All RX "locking" is done by ensuring outside
5212          * code synchronizes with tg3->napi.poll()
5213          */
5214         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
5215                 work_done += tg3_rx(tnapi, budget - work_done);
5216
5217         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
5218                 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
5219                 int i, err = 0;
5220                 u32 std_prod_idx = dpr->rx_std_prod_idx;
5221                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
5222
5223                 for (i = 1; i < tp->irq_cnt; i++)
5224                         err |= tg3_rx_prodring_xfer(tp, dpr,
5225                                                     &tp->napi[i].prodring);
5226
5227                 wmb();
5228
5229                 if (std_prod_idx != dpr->rx_std_prod_idx)
5230                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5231                                      dpr->rx_std_prod_idx);
5232
5233                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5234                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5235                                      dpr->rx_jmb_prod_idx);
5236
5237                 mmiowb();
5238
5239                 if (err)
5240                         tw32_f(HOSTCC_MODE, tp->coal_now);
5241         }
5242
5243         return work_done;
5244 }
5245
5246 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5247 {
5248         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5249         struct tg3 *tp = tnapi->tp;
5250         int work_done = 0;
5251         struct tg3_hw_status *sblk = tnapi->hw_status;
5252
5253         while (1) {
5254                 work_done = tg3_poll_work(tnapi, work_done, budget);
5255
5256                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5257                         goto tx_recovery;
5258
5259                 if (unlikely(work_done >= budget))
5260                         break;
5261
5262                 /* tp->last_tag is used in tg3_int_reenable() below
5263                  * to tell the hw how much work has been processed,
5264                  * so we must read it before checking for more work.
5265                  */
5266                 tnapi->last_tag = sblk->status_tag;
5267                 tnapi->last_irq_tag = tnapi->last_tag;
5268                 rmb();
5269
5270                 /* check for RX/TX work to do */
5271                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5272                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5273                         napi_complete(napi);
5274                         /* Reenable interrupts. */
5275                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5276                         mmiowb();
5277                         break;
5278                 }
5279         }
5280
5281         return work_done;
5282
5283 tx_recovery:
5284         /* work_done is guaranteed to be less than budget. */
5285         napi_complete(napi);
5286         schedule_work(&tp->reset_task);
5287         return work_done;
5288 }
5289
5290 static void tg3_process_error(struct tg3 *tp)
5291 {
5292         u32 val;
5293         bool real_error = false;
5294
5295         if (tp->tg3_flags & TG3_FLAG_ERROR_PROCESSED)
5296                 return;
5297
5298         /* Check Flow Attention register */
5299         val = tr32(HOSTCC_FLOW_ATTN);
5300         if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
5301                 netdev_err(tp->dev, "FLOW Attention error.  Resetting chip.\n");
5302                 real_error = true;
5303         }
5304
5305         if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
5306                 netdev_err(tp->dev, "MSI Status error.  Resetting chip.\n");
5307                 real_error = true;
5308         }
5309
5310         if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
5311                 netdev_err(tp->dev, "DMA Status error.  Resetting chip.\n");
5312                 real_error = true;
5313         }
5314
5315         if (!real_error)
5316                 return;
5317
5318         tg3_dump_state(tp);
5319
5320         tp->tg3_flags |= TG3_FLAG_ERROR_PROCESSED;
5321         schedule_work(&tp->reset_task);
5322 }
5323
5324 static int tg3_poll(struct napi_struct *napi, int budget)
5325 {
5326         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5327         struct tg3 *tp = tnapi->tp;
5328         int work_done = 0;
5329         struct tg3_hw_status *sblk = tnapi->hw_status;
5330
5331         while (1) {
5332                 if (sblk->status & SD_STATUS_ERROR)
5333                         tg3_process_error(tp);
5334
5335                 tg3_poll_link(tp);
5336
5337                 work_done = tg3_poll_work(tnapi, work_done, budget);
5338
5339                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5340                         goto tx_recovery;
5341
5342                 if (unlikely(work_done >= budget))
5343                         break;
5344
5345                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5346                         /* tp->last_tag is used in tg3_int_reenable() below
5347                          * to tell the hw how much work has been processed,
5348                          * so we must read it before checking for more work.
5349                          */
5350                         tnapi->last_tag = sblk->status_tag;
5351                         tnapi->last_irq_tag = tnapi->last_tag;
5352                         rmb();
5353                 } else
5354                         sblk->status &= ~SD_STATUS_UPDATED;
5355
5356                 if (likely(!tg3_has_work(tnapi))) {
5357                         napi_complete(napi);
5358                         tg3_int_reenable(tnapi);
5359                         break;
5360                 }
5361         }
5362
5363         return work_done;
5364
5365 tx_recovery:
5366         /* work_done is guaranteed to be less than budget. */
5367         napi_complete(napi);
5368         schedule_work(&tp->reset_task);
5369         return work_done;
5370 }
5371
5372 static void tg3_napi_disable(struct tg3 *tp)
5373 {
5374         int i;
5375
5376         for (i = tp->irq_cnt - 1; i >= 0; i--)
5377                 napi_disable(&tp->napi[i].napi);
5378 }
5379
5380 static void tg3_napi_enable(struct tg3 *tp)
5381 {
5382         int i;
5383
5384         for (i = 0; i < tp->irq_cnt; i++)
5385                 napi_enable(&tp->napi[i].napi);
5386 }
5387
5388 static void tg3_napi_init(struct tg3 *tp)
5389 {
5390         int i;
5391
5392         netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
5393         for (i = 1; i < tp->irq_cnt; i++)
5394                 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
5395 }
5396
5397 static void tg3_napi_fini(struct tg3 *tp)
5398 {
5399         int i;
5400
5401         for (i = 0; i < tp->irq_cnt; i++)
5402                 netif_napi_del(&tp->napi[i].napi);
5403 }
5404
5405 static inline void tg3_netif_stop(struct tg3 *tp)
5406 {
5407         tp->dev->trans_start = jiffies; /* prevent tx timeout */
5408         tg3_napi_disable(tp);
5409         netif_tx_disable(tp->dev);
5410 }
5411
5412 static inline void tg3_netif_start(struct tg3 *tp)
5413 {
5414         /* NOTE: unconditional netif_tx_wake_all_queues is only
5415          * appropriate so long as all callers are assured to
5416          * have free tx slots (such as after tg3_init_hw)
5417          */
5418         netif_tx_wake_all_queues(tp->dev);
5419
5420         tg3_napi_enable(tp);
5421         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
5422         tg3_enable_ints(tp);
5423 }
5424
5425 static void tg3_irq_quiesce(struct tg3 *tp)
5426 {
5427         int i;
5428
5429         BUG_ON(tp->irq_sync);
5430
5431         tp->irq_sync = 1;
5432         smp_mb();
5433
5434         for (i = 0; i < tp->irq_cnt; i++)
5435                 synchronize_irq(tp->napi[i].irq_vec);
5436 }
5437
5438 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5439  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5440  * with as well.  Most of the time, this is not necessary except when
5441  * shutting down the device.
5442  */
5443 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5444 {
5445         spin_lock_bh(&tp->lock);
5446         if (irq_sync)
5447                 tg3_irq_quiesce(tp);
5448 }
5449
5450 static inline void tg3_full_unlock(struct tg3 *tp)
5451 {
5452         spin_unlock_bh(&tp->lock);
5453 }
5454
5455 /* One-shot MSI handler - Chip automatically disables interrupt
5456  * after sending MSI so driver doesn't have to do it.
5457  */
5458 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5459 {
5460         struct tg3_napi *tnapi = dev_id;
5461         struct tg3 *tp = tnapi->tp;
5462
5463         prefetch(tnapi->hw_status);
5464         if (tnapi->rx_rcb)
5465                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5466
5467         if (likely(!tg3_irq_sync(tp)))
5468                 napi_schedule(&tnapi->napi);
5469
5470         return IRQ_HANDLED;
5471 }
5472
5473 /* MSI ISR - No need to check for interrupt sharing and no need to
5474  * flush status block and interrupt mailbox. PCI ordering rules
5475  * guarantee that MSI will arrive after the status block.
5476  */
5477 static irqreturn_t tg3_msi(int irq, void *dev_id)
5478 {
5479         struct tg3_napi *tnapi = dev_id;
5480         struct tg3 *tp = tnapi->tp;
5481
5482         prefetch(tnapi->hw_status);
5483         if (tnapi->rx_rcb)
5484                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5485         /*
5486          * Writing any value to intr-mbox-0 clears PCI INTA# and
5487          * chip-internal interrupt pending events.
5488          * Writing non-zero to intr-mbox-0 additional tells the
5489          * NIC to stop sending us irqs, engaging "in-intr-handler"
5490          * event coalescing.
5491          */
5492         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5493         if (likely(!tg3_irq_sync(tp)))
5494                 napi_schedule(&tnapi->napi);
5495
5496         return IRQ_RETVAL(1);
5497 }
5498
5499 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5500 {
5501         struct tg3_napi *tnapi = dev_id;
5502         struct tg3 *tp = tnapi->tp;
5503         struct tg3_hw_status *sblk = tnapi->hw_status;
5504         unsigned int handled = 1;
5505
5506         /* In INTx mode, it is possible for the interrupt to arrive at
5507          * the CPU before the status block posted prior to the interrupt.
5508          * Reading the PCI State register will confirm whether the
5509          * interrupt is ours and will flush the status block.
5510          */
5511         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5512                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5513                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5514                         handled = 0;
5515                         goto out;
5516                 }
5517         }
5518
5519         /*
5520          * Writing any value to intr-mbox-0 clears PCI INTA# and
5521          * chip-internal interrupt pending events.
5522          * Writing non-zero to intr-mbox-0 additional tells the
5523          * NIC to stop sending us irqs, engaging "in-intr-handler"
5524          * event coalescing.
5525          *
5526          * Flush the mailbox to de-assert the IRQ immediately to prevent
5527          * spurious interrupts.  The flush impacts performance but
5528          * excessive spurious interrupts can be worse in some cases.
5529          */
5530         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5531         if (tg3_irq_sync(tp))
5532                 goto out;
5533         sblk->status &= ~SD_STATUS_UPDATED;
5534         if (likely(tg3_has_work(tnapi))) {
5535                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5536                 napi_schedule(&tnapi->napi);
5537         } else {
5538                 /* No work, shared interrupt perhaps?  re-enable
5539                  * interrupts, and flush that PCI write
5540                  */
5541                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5542                                0x00000000);
5543         }
5544 out:
5545         return IRQ_RETVAL(handled);
5546 }
5547
5548 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5549 {
5550         struct tg3_napi *tnapi = dev_id;
5551         struct tg3 *tp = tnapi->tp;
5552         struct tg3_hw_status *sblk = tnapi->hw_status;
5553         unsigned int handled = 1;
5554
5555         /* In INTx mode, it is possible for the interrupt to arrive at
5556          * the CPU before the status block posted prior to the interrupt.
5557          * Reading the PCI State register will confirm whether the
5558          * interrupt is ours and will flush the status block.
5559          */
5560         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5561                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5562                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5563                         handled = 0;
5564                         goto out;
5565                 }
5566         }
5567
5568         /*
5569          * writing any value to intr-mbox-0 clears PCI INTA# and
5570          * chip-internal interrupt pending events.
5571          * writing non-zero to intr-mbox-0 additional tells the
5572          * NIC to stop sending us irqs, engaging "in-intr-handler"
5573          * event coalescing.
5574          *
5575          * Flush the mailbox to de-assert the IRQ immediately to prevent
5576          * spurious interrupts.  The flush impacts performance but
5577          * excessive spurious interrupts can be worse in some cases.
5578          */
5579         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5580
5581         /*
5582          * In a shared interrupt configuration, sometimes other devices'
5583          * interrupts will scream.  We record the current status tag here
5584          * so that the above check can report that the screaming interrupts
5585          * are unhandled.  Eventually they will be silenced.
5586          */
5587         tnapi->last_irq_tag = sblk->status_tag;
5588
5589         if (tg3_irq_sync(tp))
5590                 goto out;
5591
5592         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5593
5594         napi_schedule(&tnapi->napi);
5595
5596 out:
5597         return IRQ_RETVAL(handled);
5598 }
5599
5600 /* ISR for interrupt test */
5601 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5602 {
5603         struct tg3_napi *tnapi = dev_id;
5604         struct tg3 *tp = tnapi->tp;
5605         struct tg3_hw_status *sblk = tnapi->hw_status;
5606
5607         if ((sblk->status & SD_STATUS_UPDATED) ||
5608             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5609                 tg3_disable_ints(tp);
5610                 return IRQ_RETVAL(1);
5611         }
5612         return IRQ_RETVAL(0);
5613 }
5614
5615 static int tg3_init_hw(struct tg3 *, int);
5616 static int tg3_halt(struct tg3 *, int, int);
5617
5618 /* Restart hardware after configuration changes, self-test, etc.
5619  * Invoked with tp->lock held.
5620  */
5621 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5622         __releases(tp->lock)
5623         __acquires(tp->lock)
5624 {
5625         int err;
5626
5627         err = tg3_init_hw(tp, reset_phy);
5628         if (err) {
5629                 netdev_err(tp->dev,
5630                            "Failed to re-initialize device, aborting\n");
5631                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5632                 tg3_full_unlock(tp);
5633                 del_timer_sync(&tp->timer);
5634                 tp->irq_sync = 0;
5635                 tg3_napi_enable(tp);
5636                 dev_close(tp->dev);
5637                 tg3_full_lock(tp, 0);
5638         }
5639         return err;
5640 }
5641
5642 #ifdef CONFIG_NET_POLL_CONTROLLER
5643 static void tg3_poll_controller(struct net_device *dev)
5644 {
5645         int i;
5646         struct tg3 *tp = netdev_priv(dev);
5647
5648         for (i = 0; i < tp->irq_cnt; i++)
5649                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5650 }
5651 #endif
5652
5653 static void tg3_reset_task(struct work_struct *work)
5654 {
5655         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5656         int err;
5657         unsigned int restart_timer;
5658
5659         tg3_full_lock(tp, 0);
5660
5661         if (!netif_running(tp->dev)) {
5662                 tg3_full_unlock(tp);
5663                 return;
5664         }
5665
5666         tg3_full_unlock(tp);
5667
5668         tg3_phy_stop(tp);
5669
5670         tg3_netif_stop(tp);
5671
5672         tg3_full_lock(tp, 1);
5673
5674         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5675         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5676
5677         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5678                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5679                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5680                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5681                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5682         }
5683
5684         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5685         err = tg3_init_hw(tp, 1);
5686         if (err)
5687                 goto out;
5688
5689         tg3_netif_start(tp);
5690
5691         if (restart_timer)
5692                 mod_timer(&tp->timer, jiffies + 1);
5693
5694 out:
5695         tg3_full_unlock(tp);
5696
5697         if (!err)
5698                 tg3_phy_start(tp);
5699 }
5700
5701 static void tg3_tx_timeout(struct net_device *dev)
5702 {
5703         struct tg3 *tp = netdev_priv(dev);
5704
5705         if (netif_msg_tx_err(tp)) {
5706                 netdev_err(dev, "transmit timed out, resetting\n");
5707                 tg3_dump_state(tp);
5708         }
5709
5710         schedule_work(&tp->reset_task);
5711 }
5712
5713 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5714 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5715 {
5716         u32 base = (u32) mapping & 0xffffffff;
5717
5718         return (base > 0xffffdcc0) && (base + len + 8 < base);
5719 }
5720
5721 /* Test for DMA addresses > 40-bit */
5722 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5723                                           int len)
5724 {
5725 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5726         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5727                 return ((u64) mapping + len) > DMA_BIT_MASK(40);
5728         return 0;
5729 #else
5730         return 0;
5731 #endif
5732 }
5733
5734 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5735
5736 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5737 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5738                                        struct sk_buff *skb, u32 last_plus_one,
5739                                        u32 *start, u32 base_flags, u32 mss)
5740 {
5741         struct tg3 *tp = tnapi->tp;
5742         struct sk_buff *new_skb;
5743         dma_addr_t new_addr = 0;
5744         u32 entry = *start;
5745         int i, ret = 0;
5746
5747         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5748                 new_skb = skb_copy(skb, GFP_ATOMIC);
5749         else {
5750                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5751
5752                 new_skb = skb_copy_expand(skb,
5753                                           skb_headroom(skb) + more_headroom,
5754                                           skb_tailroom(skb), GFP_ATOMIC);
5755         }
5756
5757         if (!new_skb) {
5758                 ret = -1;
5759         } else {
5760                 /* New SKB is guaranteed to be linear. */
5761                 entry = *start;
5762                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5763                                           PCI_DMA_TODEVICE);
5764                 /* Make sure the mapping succeeded */
5765                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5766                         ret = -1;
5767                         dev_kfree_skb(new_skb);
5768                         new_skb = NULL;
5769
5770                 /* Make sure new skb does not cross any 4G boundaries.
5771                  * Drop the packet if it does.
5772                  */
5773                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5774                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5775                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,