tg3: Add write accessor for AUX CTRL phy reg
[linux-2.6.git] / drivers / net / tg3.c
1 /*
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  * Copyright (C) 2005-2011 Broadcom Corporation.
8  *
9  * Firmware is:
10  *      Derived from proprietary unpublished source code,
11  *      Copyright (C) 2000-2003 Broadcom Corporation.
12  *
13  *      Permission is hereby granted for the distribution of this firmware
14  *      data in hexadecimal or equivalent format, provided this copyright
15  *      notice is accompanying it.
16  */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/in.h>
28 #include <linux/init.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mdio.h>
36 #include <linux/mii.h>
37 #include <linux/phy.h>
38 #include <linux/brcmphy.h>
39 #include <linux/if_vlan.h>
40 #include <linux/ip.h>
41 #include <linux/tcp.h>
42 #include <linux/workqueue.h>
43 #include <linux/prefetch.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/firmware.h>
46
47 #include <net/checksum.h>
48 #include <net/ip.h>
49
50 #include <asm/system.h>
51 #include <linux/io.h>
52 #include <asm/byteorder.h>
53 #include <linux/uaccess.h>
54
55 #ifdef CONFIG_SPARC
56 #include <asm/idprom.h>
57 #include <asm/prom.h>
58 #endif
59
60 #define BAR_0   0
61 #define BAR_2   2
62
63 #include "tg3.h"
64
65 #define DRV_MODULE_NAME         "tg3"
66 #define TG3_MAJ_NUM                     3
67 #define TG3_MIN_NUM                     117
68 #define DRV_MODULE_VERSION      \
69         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
70 #define DRV_MODULE_RELDATE      "January 25, 2011"
71
72 #define TG3_DEF_MAC_MODE        0
73 #define TG3_DEF_RX_MODE         0
74 #define TG3_DEF_TX_MODE         0
75 #define TG3_DEF_MSG_ENABLE        \
76         (NETIF_MSG_DRV          | \
77          NETIF_MSG_PROBE        | \
78          NETIF_MSG_LINK         | \
79          NETIF_MSG_TIMER        | \
80          NETIF_MSG_IFDOWN       | \
81          NETIF_MSG_IFUP         | \
82          NETIF_MSG_RX_ERR       | \
83          NETIF_MSG_TX_ERR)
84
85 /* length of time before we decide the hardware is borked,
86  * and dev->tx_timeout() should be called to fix the problem
87  */
88 #define TG3_TX_TIMEOUT                  (5 * HZ)
89
90 /* hardware minimum and maximum for a single frame's data payload */
91 #define TG3_MIN_MTU                     60
92 #define TG3_MAX_MTU(tp) \
93         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
94
95 /* These numbers seem to be hard coded in the NIC firmware somehow.
96  * You can't change the ring sizes, but you can change where you place
97  * them in the NIC onboard memory.
98  */
99 #define TG3_RX_STD_RING_SIZE(tp) \
100         ((tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) ? \
101          TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
102 #define TG3_DEF_RX_RING_PENDING         200
103 #define TG3_RX_JMB_RING_SIZE(tp) \
104         ((tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) ? \
105          TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
106 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
107 #define TG3_RSS_INDIR_TBL_SIZE          128
108
109 /* Do not place this n-ring entries value into the tp struct itself,
110  * we really want to expose these constants to GCC so that modulo et
111  * al.  operations are done with shifts and masks instead of with
112  * hw multiply/modulo instructions.  Another solution would be to
113  * replace things like '% foo' with '& (foo - 1)'.
114  */
115
116 #define TG3_TX_RING_SIZE                512
117 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
118
119 #define TG3_RX_STD_RING_BYTES(tp) \
120         (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
121 #define TG3_RX_JMB_RING_BYTES(tp) \
122         (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
123 #define TG3_RX_RCB_RING_BYTES(tp) \
124         (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
125 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
126                                  TG3_TX_RING_SIZE)
127 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
128
129 #define TG3_DMA_BYTE_ENAB               64
130
131 #define TG3_RX_STD_DMA_SZ               1536
132 #define TG3_RX_JMB_DMA_SZ               9046
133
134 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
135
136 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
137 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
138
139 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
140         (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
141
142 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
143         (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
144
145 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
146  * that are at least dword aligned when used in PCIX mode.  The driver
147  * works around this bug by double copying the packet.  This workaround
148  * is built into the normal double copy length check for efficiency.
149  *
150  * However, the double copy is only necessary on those architectures
151  * where unaligned memory accesses are inefficient.  For those architectures
152  * where unaligned memory accesses incur little penalty, we can reintegrate
153  * the 5701 in the normal rx path.  Doing so saves a device structure
154  * dereference by hardcoding the double copy threshold in place.
155  */
156 #define TG3_RX_COPY_THRESHOLD           256
157 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
158         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
159 #else
160         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
161 #endif
162
163 /* minimum number of free TX descriptors required to wake up TX process */
164 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
165
166 #define TG3_RAW_IP_ALIGN 2
167
168 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
169
170 #define FIRMWARE_TG3            "tigon/tg3.bin"
171 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
172 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
173
174 static char version[] __devinitdata =
175         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
176
177 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
178 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
179 MODULE_LICENSE("GPL");
180 MODULE_VERSION(DRV_MODULE_VERSION);
181 MODULE_FIRMWARE(FIRMWARE_TG3);
182 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
183 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
184
185 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
186 module_param(tg3_debug, int, 0);
187 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
188
189 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
263         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
264         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
265         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
266         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
267         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
268         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
269         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
270         {}
271 };
272
273 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
274
275 static const struct {
276         const char string[ETH_GSTRING_LEN];
277 } ethtool_stats_keys[] = {
278         { "rx_octets" },
279         { "rx_fragments" },
280         { "rx_ucast_packets" },
281         { "rx_mcast_packets" },
282         { "rx_bcast_packets" },
283         { "rx_fcs_errors" },
284         { "rx_align_errors" },
285         { "rx_xon_pause_rcvd" },
286         { "rx_xoff_pause_rcvd" },
287         { "rx_mac_ctrl_rcvd" },
288         { "rx_xoff_entered" },
289         { "rx_frame_too_long_errors" },
290         { "rx_jabbers" },
291         { "rx_undersize_packets" },
292         { "rx_in_length_errors" },
293         { "rx_out_length_errors" },
294         { "rx_64_or_less_octet_packets" },
295         { "rx_65_to_127_octet_packets" },
296         { "rx_128_to_255_octet_packets" },
297         { "rx_256_to_511_octet_packets" },
298         { "rx_512_to_1023_octet_packets" },
299         { "rx_1024_to_1522_octet_packets" },
300         { "rx_1523_to_2047_octet_packets" },
301         { "rx_2048_to_4095_octet_packets" },
302         { "rx_4096_to_8191_octet_packets" },
303         { "rx_8192_to_9022_octet_packets" },
304
305         { "tx_octets" },
306         { "tx_collisions" },
307
308         { "tx_xon_sent" },
309         { "tx_xoff_sent" },
310         { "tx_flow_control" },
311         { "tx_mac_errors" },
312         { "tx_single_collisions" },
313         { "tx_mult_collisions" },
314         { "tx_deferred" },
315         { "tx_excessive_collisions" },
316         { "tx_late_collisions" },
317         { "tx_collide_2times" },
318         { "tx_collide_3times" },
319         { "tx_collide_4times" },
320         { "tx_collide_5times" },
321         { "tx_collide_6times" },
322         { "tx_collide_7times" },
323         { "tx_collide_8times" },
324         { "tx_collide_9times" },
325         { "tx_collide_10times" },
326         { "tx_collide_11times" },
327         { "tx_collide_12times" },
328         { "tx_collide_13times" },
329         { "tx_collide_14times" },
330         { "tx_collide_15times" },
331         { "tx_ucast_packets" },
332         { "tx_mcast_packets" },
333         { "tx_bcast_packets" },
334         { "tx_carrier_sense_errors" },
335         { "tx_discards" },
336         { "tx_errors" },
337
338         { "dma_writeq_full" },
339         { "dma_write_prioq_full" },
340         { "rxbds_empty" },
341         { "rx_discards" },
342         { "mbuf_lwm_thresh_hit" },
343         { "rx_errors" },
344         { "rx_threshold_hit" },
345
346         { "dma_readq_full" },
347         { "dma_read_prioq_full" },
348         { "tx_comp_queue_full" },
349
350         { "ring_set_send_prod_index" },
351         { "ring_status_update" },
352         { "nic_irqs" },
353         { "nic_avoided_irqs" },
354         { "nic_tx_threshold_hit" }
355 };
356
357 #define TG3_NUM_STATS   ARRAY_SIZE(ethtool_stats_keys)
358
359
360 static const struct {
361         const char string[ETH_GSTRING_LEN];
362 } ethtool_test_keys[] = {
363         { "nvram test     (online) " },
364         { "link test      (online) " },
365         { "register test  (offline)" },
366         { "memory test    (offline)" },
367         { "loopback test  (offline)" },
368         { "interrupt test (offline)" },
369 };
370
371 #define TG3_NUM_TEST    ARRAY_SIZE(ethtool_test_keys)
372
373
374 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
375 {
376         writel(val, tp->regs + off);
377 }
378
379 static u32 tg3_read32(struct tg3 *tp, u32 off)
380 {
381         return readl(tp->regs + off);
382 }
383
384 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
385 {
386         writel(val, tp->aperegs + off);
387 }
388
389 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
390 {
391         return readl(tp->aperegs + off);
392 }
393
394 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
395 {
396         unsigned long flags;
397
398         spin_lock_irqsave(&tp->indirect_lock, flags);
399         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
400         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
401         spin_unlock_irqrestore(&tp->indirect_lock, flags);
402 }
403
404 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
405 {
406         writel(val, tp->regs + off);
407         readl(tp->regs + off);
408 }
409
410 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
411 {
412         unsigned long flags;
413         u32 val;
414
415         spin_lock_irqsave(&tp->indirect_lock, flags);
416         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
417         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
418         spin_unlock_irqrestore(&tp->indirect_lock, flags);
419         return val;
420 }
421
422 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
423 {
424         unsigned long flags;
425
426         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
427                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
428                                        TG3_64BIT_REG_LOW, val);
429                 return;
430         }
431         if (off == TG3_RX_STD_PROD_IDX_REG) {
432                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
433                                        TG3_64BIT_REG_LOW, val);
434                 return;
435         }
436
437         spin_lock_irqsave(&tp->indirect_lock, flags);
438         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
439         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
440         spin_unlock_irqrestore(&tp->indirect_lock, flags);
441
442         /* In indirect mode when disabling interrupts, we also need
443          * to clear the interrupt bit in the GRC local ctrl register.
444          */
445         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
446             (val == 0x1)) {
447                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
448                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
449         }
450 }
451
452 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
453 {
454         unsigned long flags;
455         u32 val;
456
457         spin_lock_irqsave(&tp->indirect_lock, flags);
458         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
459         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
460         spin_unlock_irqrestore(&tp->indirect_lock, flags);
461         return val;
462 }
463
464 /* usec_wait specifies the wait time in usec when writing to certain registers
465  * where it is unsafe to read back the register without some delay.
466  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
467  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
468  */
469 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
470 {
471         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
472             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
473                 /* Non-posted methods */
474                 tp->write32(tp, off, val);
475         else {
476                 /* Posted method */
477                 tg3_write32(tp, off, val);
478                 if (usec_wait)
479                         udelay(usec_wait);
480                 tp->read32(tp, off);
481         }
482         /* Wait again after the read for the posted method to guarantee that
483          * the wait time is met.
484          */
485         if (usec_wait)
486                 udelay(usec_wait);
487 }
488
489 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
490 {
491         tp->write32_mbox(tp, off, val);
492         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
493             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
494                 tp->read32_mbox(tp, off);
495 }
496
497 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
498 {
499         void __iomem *mbox = tp->regs + off;
500         writel(val, mbox);
501         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
502                 writel(val, mbox);
503         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
504                 readl(mbox);
505 }
506
507 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
508 {
509         return readl(tp->regs + off + GRCMBOX_BASE);
510 }
511
512 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
513 {
514         writel(val, tp->regs + off + GRCMBOX_BASE);
515 }
516
517 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
518 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
519 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
520 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
521 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
522
523 #define tw32(reg, val)                  tp->write32(tp, reg, val)
524 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
525 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
526 #define tr32(reg)                       tp->read32(tp, reg)
527
528 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
529 {
530         unsigned long flags;
531
532         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
533             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
534                 return;
535
536         spin_lock_irqsave(&tp->indirect_lock, flags);
537         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
538                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
539                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
540
541                 /* Always leave this as zero. */
542                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
543         } else {
544                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
545                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
546
547                 /* Always leave this as zero. */
548                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
549         }
550         spin_unlock_irqrestore(&tp->indirect_lock, flags);
551 }
552
553 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
554 {
555         unsigned long flags;
556
557         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
558             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
559                 *val = 0;
560                 return;
561         }
562
563         spin_lock_irqsave(&tp->indirect_lock, flags);
564         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
565                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
566                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
567
568                 /* Always leave this as zero. */
569                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
570         } else {
571                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
572                 *val = tr32(TG3PCI_MEM_WIN_DATA);
573
574                 /* Always leave this as zero. */
575                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
576         }
577         spin_unlock_irqrestore(&tp->indirect_lock, flags);
578 }
579
580 static void tg3_ape_lock_init(struct tg3 *tp)
581 {
582         int i;
583         u32 regbase;
584
585         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
586                 regbase = TG3_APE_LOCK_GRANT;
587         else
588                 regbase = TG3_APE_PER_LOCK_GRANT;
589
590         /* Make sure the driver hasn't any stale locks. */
591         for (i = 0; i < 8; i++)
592                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
593 }
594
595 static int tg3_ape_lock(struct tg3 *tp, int locknum)
596 {
597         int i, off;
598         int ret = 0;
599         u32 status, req, gnt;
600
601         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
602                 return 0;
603
604         switch (locknum) {
605         case TG3_APE_LOCK_GRC:
606         case TG3_APE_LOCK_MEM:
607                 break;
608         default:
609                 return -EINVAL;
610         }
611
612         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
613                 req = TG3_APE_LOCK_REQ;
614                 gnt = TG3_APE_LOCK_GRANT;
615         } else {
616                 req = TG3_APE_PER_LOCK_REQ;
617                 gnt = TG3_APE_PER_LOCK_GRANT;
618         }
619
620         off = 4 * locknum;
621
622         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
623
624         /* Wait for up to 1 millisecond to acquire lock. */
625         for (i = 0; i < 100; i++) {
626                 status = tg3_ape_read32(tp, gnt + off);
627                 if (status == APE_LOCK_GRANT_DRIVER)
628                         break;
629                 udelay(10);
630         }
631
632         if (status != APE_LOCK_GRANT_DRIVER) {
633                 /* Revoke the lock request. */
634                 tg3_ape_write32(tp, gnt + off,
635                                 APE_LOCK_GRANT_DRIVER);
636
637                 ret = -EBUSY;
638         }
639
640         return ret;
641 }
642
643 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
644 {
645         u32 gnt;
646
647         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
648                 return;
649
650         switch (locknum) {
651         case TG3_APE_LOCK_GRC:
652         case TG3_APE_LOCK_MEM:
653                 break;
654         default:
655                 return;
656         }
657
658         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
659                 gnt = TG3_APE_LOCK_GRANT;
660         else
661                 gnt = TG3_APE_PER_LOCK_GRANT;
662
663         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
664 }
665
666 static void tg3_disable_ints(struct tg3 *tp)
667 {
668         int i;
669
670         tw32(TG3PCI_MISC_HOST_CTRL,
671              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
672         for (i = 0; i < tp->irq_max; i++)
673                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
674 }
675
676 static void tg3_enable_ints(struct tg3 *tp)
677 {
678         int i;
679
680         tp->irq_sync = 0;
681         wmb();
682
683         tw32(TG3PCI_MISC_HOST_CTRL,
684              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
685
686         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
687         for (i = 0; i < tp->irq_cnt; i++) {
688                 struct tg3_napi *tnapi = &tp->napi[i];
689
690                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
691                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
692                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
693
694                 tp->coal_now |= tnapi->coal_now;
695         }
696
697         /* Force an initial interrupt */
698         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
699             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
700                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
701         else
702                 tw32(HOSTCC_MODE, tp->coal_now);
703
704         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
705 }
706
707 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
708 {
709         struct tg3 *tp = tnapi->tp;
710         struct tg3_hw_status *sblk = tnapi->hw_status;
711         unsigned int work_exists = 0;
712
713         /* check for phy events */
714         if (!(tp->tg3_flags &
715               (TG3_FLAG_USE_LINKCHG_REG |
716                TG3_FLAG_POLL_SERDES))) {
717                 if (sblk->status & SD_STATUS_LINK_CHG)
718                         work_exists = 1;
719         }
720         /* check for RX/TX work to do */
721         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
722             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
723                 work_exists = 1;
724
725         return work_exists;
726 }
727
728 /* tg3_int_reenable
729  *  similar to tg3_enable_ints, but it accurately determines whether there
730  *  is new work pending and can return without flushing the PIO write
731  *  which reenables interrupts
732  */
733 static void tg3_int_reenable(struct tg3_napi *tnapi)
734 {
735         struct tg3 *tp = tnapi->tp;
736
737         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
738         mmiowb();
739
740         /* When doing tagged status, this work check is unnecessary.
741          * The last_tag we write above tells the chip which piece of
742          * work we've completed.
743          */
744         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
745             tg3_has_work(tnapi))
746                 tw32(HOSTCC_MODE, tp->coalesce_mode |
747                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
748 }
749
750 static void tg3_switch_clocks(struct tg3 *tp)
751 {
752         u32 clock_ctrl;
753         u32 orig_clock_ctrl;
754
755         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
756             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
757                 return;
758
759         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
760
761         orig_clock_ctrl = clock_ctrl;
762         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
763                        CLOCK_CTRL_CLKRUN_OENABLE |
764                        0x1f);
765         tp->pci_clock_ctrl = clock_ctrl;
766
767         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
768                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
769                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
770                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
771                 }
772         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
773                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
774                             clock_ctrl |
775                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
776                             40);
777                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
778                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
779                             40);
780         }
781         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
782 }
783
784 #define PHY_BUSY_LOOPS  5000
785
786 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
787 {
788         u32 frame_val;
789         unsigned int loops;
790         int ret;
791
792         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
793                 tw32_f(MAC_MI_MODE,
794                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
795                 udelay(80);
796         }
797
798         *val = 0x0;
799
800         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
801                       MI_COM_PHY_ADDR_MASK);
802         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
803                       MI_COM_REG_ADDR_MASK);
804         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
805
806         tw32_f(MAC_MI_COM, frame_val);
807
808         loops = PHY_BUSY_LOOPS;
809         while (loops != 0) {
810                 udelay(10);
811                 frame_val = tr32(MAC_MI_COM);
812
813                 if ((frame_val & MI_COM_BUSY) == 0) {
814                         udelay(5);
815                         frame_val = tr32(MAC_MI_COM);
816                         break;
817                 }
818                 loops -= 1;
819         }
820
821         ret = -EBUSY;
822         if (loops != 0) {
823                 *val = frame_val & MI_COM_DATA_MASK;
824                 ret = 0;
825         }
826
827         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
828                 tw32_f(MAC_MI_MODE, tp->mi_mode);
829                 udelay(80);
830         }
831
832         return ret;
833 }
834
835 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
836 {
837         u32 frame_val;
838         unsigned int loops;
839         int ret;
840
841         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
842             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
843                 return 0;
844
845         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
846                 tw32_f(MAC_MI_MODE,
847                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
848                 udelay(80);
849         }
850
851         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
852                       MI_COM_PHY_ADDR_MASK);
853         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
854                       MI_COM_REG_ADDR_MASK);
855         frame_val |= (val & MI_COM_DATA_MASK);
856         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
857
858         tw32_f(MAC_MI_COM, frame_val);
859
860         loops = PHY_BUSY_LOOPS;
861         while (loops != 0) {
862                 udelay(10);
863                 frame_val = tr32(MAC_MI_COM);
864                 if ((frame_val & MI_COM_BUSY) == 0) {
865                         udelay(5);
866                         frame_val = tr32(MAC_MI_COM);
867                         break;
868                 }
869                 loops -= 1;
870         }
871
872         ret = -EBUSY;
873         if (loops != 0)
874                 ret = 0;
875
876         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
877                 tw32_f(MAC_MI_MODE, tp->mi_mode);
878                 udelay(80);
879         }
880
881         return ret;
882 }
883
884 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
885 {
886         int err;
887
888         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
889         if (err)
890                 goto done;
891
892         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
893         if (err)
894                 goto done;
895
896         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
897                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
898         if (err)
899                 goto done;
900
901         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
902
903 done:
904         return err;
905 }
906
907 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
908 {
909         int err;
910
911         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
912         if (err)
913                 goto done;
914
915         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
916         if (err)
917                 goto done;
918
919         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
920                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
921         if (err)
922                 goto done;
923
924         err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
925
926 done:
927         return err;
928 }
929
930 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
931 {
932         int err;
933
934         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
935         if (!err)
936                 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
937
938         return err;
939 }
940
941 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
942 {
943         int err;
944
945         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
946         if (!err)
947                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
948
949         return err;
950 }
951
952 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
953 {
954         int err;
955
956         err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
957                            (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
958                            MII_TG3_AUXCTL_SHDWSEL_MISC);
959         if (!err)
960                 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
961
962         return err;
963 }
964
965 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
966 {
967         if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
968                 set |= MII_TG3_AUXCTL_MISC_WREN;
969
970         return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
971 }
972
973 static int tg3_bmcr_reset(struct tg3 *tp)
974 {
975         u32 phy_control;
976         int limit, err;
977
978         /* OK, reset it, and poll the BMCR_RESET bit until it
979          * clears or we time out.
980          */
981         phy_control = BMCR_RESET;
982         err = tg3_writephy(tp, MII_BMCR, phy_control);
983         if (err != 0)
984                 return -EBUSY;
985
986         limit = 5000;
987         while (limit--) {
988                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
989                 if (err != 0)
990                         return -EBUSY;
991
992                 if ((phy_control & BMCR_RESET) == 0) {
993                         udelay(40);
994                         break;
995                 }
996                 udelay(10);
997         }
998         if (limit < 0)
999                 return -EBUSY;
1000
1001         return 0;
1002 }
1003
1004 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1005 {
1006         struct tg3 *tp = bp->priv;
1007         u32 val;
1008
1009         spin_lock_bh(&tp->lock);
1010
1011         if (tg3_readphy(tp, reg, &val))
1012                 val = -EIO;
1013
1014         spin_unlock_bh(&tp->lock);
1015
1016         return val;
1017 }
1018
1019 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1020 {
1021         struct tg3 *tp = bp->priv;
1022         u32 ret = 0;
1023
1024         spin_lock_bh(&tp->lock);
1025
1026         if (tg3_writephy(tp, reg, val))
1027                 ret = -EIO;
1028
1029         spin_unlock_bh(&tp->lock);
1030
1031         return ret;
1032 }
1033
1034 static int tg3_mdio_reset(struct mii_bus *bp)
1035 {
1036         return 0;
1037 }
1038
1039 static void tg3_mdio_config_5785(struct tg3 *tp)
1040 {
1041         u32 val;
1042         struct phy_device *phydev;
1043
1044         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1045         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1046         case PHY_ID_BCM50610:
1047         case PHY_ID_BCM50610M:
1048                 val = MAC_PHYCFG2_50610_LED_MODES;
1049                 break;
1050         case PHY_ID_BCMAC131:
1051                 val = MAC_PHYCFG2_AC131_LED_MODES;
1052                 break;
1053         case PHY_ID_RTL8211C:
1054                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1055                 break;
1056         case PHY_ID_RTL8201E:
1057                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1058                 break;
1059         default:
1060                 return;
1061         }
1062
1063         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1064                 tw32(MAC_PHYCFG2, val);
1065
1066                 val = tr32(MAC_PHYCFG1);
1067                 val &= ~(MAC_PHYCFG1_RGMII_INT |
1068                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1069                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1070                 tw32(MAC_PHYCFG1, val);
1071
1072                 return;
1073         }
1074
1075         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
1076                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1077                        MAC_PHYCFG2_FMODE_MASK_MASK |
1078                        MAC_PHYCFG2_GMODE_MASK_MASK |
1079                        MAC_PHYCFG2_ACT_MASK_MASK   |
1080                        MAC_PHYCFG2_QUAL_MASK_MASK |
1081                        MAC_PHYCFG2_INBAND_ENABLE;
1082
1083         tw32(MAC_PHYCFG2, val);
1084
1085         val = tr32(MAC_PHYCFG1);
1086         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1087                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1088         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1089                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1090                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1091                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1092                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1093         }
1094         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1095                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1096         tw32(MAC_PHYCFG1, val);
1097
1098         val = tr32(MAC_EXT_RGMII_MODE);
1099         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1100                  MAC_RGMII_MODE_RX_QUALITY |
1101                  MAC_RGMII_MODE_RX_ACTIVITY |
1102                  MAC_RGMII_MODE_RX_ENG_DET |
1103                  MAC_RGMII_MODE_TX_ENABLE |
1104                  MAC_RGMII_MODE_TX_LOWPWR |
1105                  MAC_RGMII_MODE_TX_RESET);
1106         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1107                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1108                         val |= MAC_RGMII_MODE_RX_INT_B |
1109                                MAC_RGMII_MODE_RX_QUALITY |
1110                                MAC_RGMII_MODE_RX_ACTIVITY |
1111                                MAC_RGMII_MODE_RX_ENG_DET;
1112                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1113                         val |= MAC_RGMII_MODE_TX_ENABLE |
1114                                MAC_RGMII_MODE_TX_LOWPWR |
1115                                MAC_RGMII_MODE_TX_RESET;
1116         }
1117         tw32(MAC_EXT_RGMII_MODE, val);
1118 }
1119
1120 static void tg3_mdio_start(struct tg3 *tp)
1121 {
1122         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1123         tw32_f(MAC_MI_MODE, tp->mi_mode);
1124         udelay(80);
1125
1126         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1127             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1128                 tg3_mdio_config_5785(tp);
1129 }
1130
1131 static int tg3_mdio_init(struct tg3 *tp)
1132 {
1133         int i;
1134         u32 reg;
1135         struct phy_device *phydev;
1136
1137         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
1138                 u32 is_serdes;
1139
1140                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1141
1142                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1143                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1144                 else
1145                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1146                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1147                 if (is_serdes)
1148                         tp->phy_addr += 7;
1149         } else
1150                 tp->phy_addr = TG3_PHY_MII_ADDR;
1151
1152         tg3_mdio_start(tp);
1153
1154         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1155             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1156                 return 0;
1157
1158         tp->mdio_bus = mdiobus_alloc();
1159         if (tp->mdio_bus == NULL)
1160                 return -ENOMEM;
1161
1162         tp->mdio_bus->name     = "tg3 mdio bus";
1163         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1164                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1165         tp->mdio_bus->priv     = tp;
1166         tp->mdio_bus->parent   = &tp->pdev->dev;
1167         tp->mdio_bus->read     = &tg3_mdio_read;
1168         tp->mdio_bus->write    = &tg3_mdio_write;
1169         tp->mdio_bus->reset    = &tg3_mdio_reset;
1170         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1171         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1172
1173         for (i = 0; i < PHY_MAX_ADDR; i++)
1174                 tp->mdio_bus->irq[i] = PHY_POLL;
1175
1176         /* The bus registration will look for all the PHYs on the mdio bus.
1177          * Unfortunately, it does not ensure the PHY is powered up before
1178          * accessing the PHY ID registers.  A chip reset is the
1179          * quickest way to bring the device back to an operational state..
1180          */
1181         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1182                 tg3_bmcr_reset(tp);
1183
1184         i = mdiobus_register(tp->mdio_bus);
1185         if (i) {
1186                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1187                 mdiobus_free(tp->mdio_bus);
1188                 return i;
1189         }
1190
1191         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1192
1193         if (!phydev || !phydev->drv) {
1194                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1195                 mdiobus_unregister(tp->mdio_bus);
1196                 mdiobus_free(tp->mdio_bus);
1197                 return -ENODEV;
1198         }
1199
1200         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1201         case PHY_ID_BCM57780:
1202                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1203                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1204                 break;
1205         case PHY_ID_BCM50610:
1206         case PHY_ID_BCM50610M:
1207                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1208                                      PHY_BRCM_RX_REFCLK_UNUSED |
1209                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1210                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1211                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1212                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1213                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1214                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1215                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1216                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1217                 /* fallthru */
1218         case PHY_ID_RTL8211C:
1219                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1220                 break;
1221         case PHY_ID_RTL8201E:
1222         case PHY_ID_BCMAC131:
1223                 phydev->interface = PHY_INTERFACE_MODE_MII;
1224                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1225                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1226                 break;
1227         }
1228
1229         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1230
1231         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1232                 tg3_mdio_config_5785(tp);
1233
1234         return 0;
1235 }
1236
1237 static void tg3_mdio_fini(struct tg3 *tp)
1238 {
1239         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1240                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1241                 mdiobus_unregister(tp->mdio_bus);
1242                 mdiobus_free(tp->mdio_bus);
1243         }
1244 }
1245
1246 /* tp->lock is held. */
1247 static inline void tg3_generate_fw_event(struct tg3 *tp)
1248 {
1249         u32 val;
1250
1251         val = tr32(GRC_RX_CPU_EVENT);
1252         val |= GRC_RX_CPU_DRIVER_EVENT;
1253         tw32_f(GRC_RX_CPU_EVENT, val);
1254
1255         tp->last_event_jiffies = jiffies;
1256 }
1257
1258 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1259
1260 /* tp->lock is held. */
1261 static void tg3_wait_for_event_ack(struct tg3 *tp)
1262 {
1263         int i;
1264         unsigned int delay_cnt;
1265         long time_remain;
1266
1267         /* If enough time has passed, no wait is necessary. */
1268         time_remain = (long)(tp->last_event_jiffies + 1 +
1269                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1270                       (long)jiffies;
1271         if (time_remain < 0)
1272                 return;
1273
1274         /* Check if we can shorten the wait time. */
1275         delay_cnt = jiffies_to_usecs(time_remain);
1276         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1277                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1278         delay_cnt = (delay_cnt >> 3) + 1;
1279
1280         for (i = 0; i < delay_cnt; i++) {
1281                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1282                         break;
1283                 udelay(8);
1284         }
1285 }
1286
1287 /* tp->lock is held. */
1288 static void tg3_ump_link_report(struct tg3 *tp)
1289 {
1290         u32 reg;
1291         u32 val;
1292
1293         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1294             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1295                 return;
1296
1297         tg3_wait_for_event_ack(tp);
1298
1299         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1300
1301         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1302
1303         val = 0;
1304         if (!tg3_readphy(tp, MII_BMCR, &reg))
1305                 val = reg << 16;
1306         if (!tg3_readphy(tp, MII_BMSR, &reg))
1307                 val |= (reg & 0xffff);
1308         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1309
1310         val = 0;
1311         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1312                 val = reg << 16;
1313         if (!tg3_readphy(tp, MII_LPA, &reg))
1314                 val |= (reg & 0xffff);
1315         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1316
1317         val = 0;
1318         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1319                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1320                         val = reg << 16;
1321                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1322                         val |= (reg & 0xffff);
1323         }
1324         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1325
1326         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1327                 val = reg << 16;
1328         else
1329                 val = 0;
1330         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1331
1332         tg3_generate_fw_event(tp);
1333 }
1334
1335 static void tg3_link_report(struct tg3 *tp)
1336 {
1337         if (!netif_carrier_ok(tp->dev)) {
1338                 netif_info(tp, link, tp->dev, "Link is down\n");
1339                 tg3_ump_link_report(tp);
1340         } else if (netif_msg_link(tp)) {
1341                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1342                             (tp->link_config.active_speed == SPEED_1000 ?
1343                              1000 :
1344                              (tp->link_config.active_speed == SPEED_100 ?
1345                               100 : 10)),
1346                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1347                              "full" : "half"));
1348
1349                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1350                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1351                             "on" : "off",
1352                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1353                             "on" : "off");
1354                 tg3_ump_link_report(tp);
1355         }
1356 }
1357
1358 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1359 {
1360         u16 miireg;
1361
1362         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1363                 miireg = ADVERTISE_PAUSE_CAP;
1364         else if (flow_ctrl & FLOW_CTRL_TX)
1365                 miireg = ADVERTISE_PAUSE_ASYM;
1366         else if (flow_ctrl & FLOW_CTRL_RX)
1367                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1368         else
1369                 miireg = 0;
1370
1371         return miireg;
1372 }
1373
1374 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1375 {
1376         u16 miireg;
1377
1378         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1379                 miireg = ADVERTISE_1000XPAUSE;
1380         else if (flow_ctrl & FLOW_CTRL_TX)
1381                 miireg = ADVERTISE_1000XPSE_ASYM;
1382         else if (flow_ctrl & FLOW_CTRL_RX)
1383                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1384         else
1385                 miireg = 0;
1386
1387         return miireg;
1388 }
1389
1390 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1391 {
1392         u8 cap = 0;
1393
1394         if (lcladv & ADVERTISE_1000XPAUSE) {
1395                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1396                         if (rmtadv & LPA_1000XPAUSE)
1397                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1398                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1399                                 cap = FLOW_CTRL_RX;
1400                 } else {
1401                         if (rmtadv & LPA_1000XPAUSE)
1402                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1403                 }
1404         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1405                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1406                         cap = FLOW_CTRL_TX;
1407         }
1408
1409         return cap;
1410 }
1411
1412 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1413 {
1414         u8 autoneg;
1415         u8 flowctrl = 0;
1416         u32 old_rx_mode = tp->rx_mode;
1417         u32 old_tx_mode = tp->tx_mode;
1418
1419         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1420                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1421         else
1422                 autoneg = tp->link_config.autoneg;
1423
1424         if (autoneg == AUTONEG_ENABLE &&
1425             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1426                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1427                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1428                 else
1429                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1430         } else
1431                 flowctrl = tp->link_config.flowctrl;
1432
1433         tp->link_config.active_flowctrl = flowctrl;
1434
1435         if (flowctrl & FLOW_CTRL_RX)
1436                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1437         else
1438                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1439
1440         if (old_rx_mode != tp->rx_mode)
1441                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1442
1443         if (flowctrl & FLOW_CTRL_TX)
1444                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1445         else
1446                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1447
1448         if (old_tx_mode != tp->tx_mode)
1449                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1450 }
1451
1452 static void tg3_adjust_link(struct net_device *dev)
1453 {
1454         u8 oldflowctrl, linkmesg = 0;
1455         u32 mac_mode, lcl_adv, rmt_adv;
1456         struct tg3 *tp = netdev_priv(dev);
1457         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1458
1459         spin_lock_bh(&tp->lock);
1460
1461         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1462                                     MAC_MODE_HALF_DUPLEX);
1463
1464         oldflowctrl = tp->link_config.active_flowctrl;
1465
1466         if (phydev->link) {
1467                 lcl_adv = 0;
1468                 rmt_adv = 0;
1469
1470                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1471                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1472                 else if (phydev->speed == SPEED_1000 ||
1473                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1474                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1475                 else
1476                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1477
1478                 if (phydev->duplex == DUPLEX_HALF)
1479                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1480                 else {
1481                         lcl_adv = tg3_advert_flowctrl_1000T(
1482                                   tp->link_config.flowctrl);
1483
1484                         if (phydev->pause)
1485                                 rmt_adv = LPA_PAUSE_CAP;
1486                         if (phydev->asym_pause)
1487                                 rmt_adv |= LPA_PAUSE_ASYM;
1488                 }
1489
1490                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1491         } else
1492                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1493
1494         if (mac_mode != tp->mac_mode) {
1495                 tp->mac_mode = mac_mode;
1496                 tw32_f(MAC_MODE, tp->mac_mode);
1497                 udelay(40);
1498         }
1499
1500         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1501                 if (phydev->speed == SPEED_10)
1502                         tw32(MAC_MI_STAT,
1503                              MAC_MI_STAT_10MBPS_MODE |
1504                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1505                 else
1506                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1507         }
1508
1509         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1510                 tw32(MAC_TX_LENGTHS,
1511                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1512                       (6 << TX_LENGTHS_IPG_SHIFT) |
1513                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1514         else
1515                 tw32(MAC_TX_LENGTHS,
1516                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1517                       (6 << TX_LENGTHS_IPG_SHIFT) |
1518                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1519
1520         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1521             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1522             phydev->speed != tp->link_config.active_speed ||
1523             phydev->duplex != tp->link_config.active_duplex ||
1524             oldflowctrl != tp->link_config.active_flowctrl)
1525                 linkmesg = 1;
1526
1527         tp->link_config.active_speed = phydev->speed;
1528         tp->link_config.active_duplex = phydev->duplex;
1529
1530         spin_unlock_bh(&tp->lock);
1531
1532         if (linkmesg)
1533                 tg3_link_report(tp);
1534 }
1535
1536 static int tg3_phy_init(struct tg3 *tp)
1537 {
1538         struct phy_device *phydev;
1539
1540         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1541                 return 0;
1542
1543         /* Bring the PHY back to a known state. */
1544         tg3_bmcr_reset(tp);
1545
1546         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1547
1548         /* Attach the MAC to the PHY. */
1549         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1550                              phydev->dev_flags, phydev->interface);
1551         if (IS_ERR(phydev)) {
1552                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1553                 return PTR_ERR(phydev);
1554         }
1555
1556         /* Mask with MAC supported features. */
1557         switch (phydev->interface) {
1558         case PHY_INTERFACE_MODE_GMII:
1559         case PHY_INTERFACE_MODE_RGMII:
1560                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1561                         phydev->supported &= (PHY_GBIT_FEATURES |
1562                                               SUPPORTED_Pause |
1563                                               SUPPORTED_Asym_Pause);
1564                         break;
1565                 }
1566                 /* fallthru */
1567         case PHY_INTERFACE_MODE_MII:
1568                 phydev->supported &= (PHY_BASIC_FEATURES |
1569                                       SUPPORTED_Pause |
1570                                       SUPPORTED_Asym_Pause);
1571                 break;
1572         default:
1573                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1574                 return -EINVAL;
1575         }
1576
1577         tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1578
1579         phydev->advertising = phydev->supported;
1580
1581         return 0;
1582 }
1583
1584 static void tg3_phy_start(struct tg3 *tp)
1585 {
1586         struct phy_device *phydev;
1587
1588         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1589                 return;
1590
1591         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1592
1593         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1594                 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1595                 phydev->speed = tp->link_config.orig_speed;
1596                 phydev->duplex = tp->link_config.orig_duplex;
1597                 phydev->autoneg = tp->link_config.orig_autoneg;
1598                 phydev->advertising = tp->link_config.orig_advertising;
1599         }
1600
1601         phy_start(phydev);
1602
1603         phy_start_aneg(phydev);
1604 }
1605
1606 static void tg3_phy_stop(struct tg3 *tp)
1607 {
1608         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1609                 return;
1610
1611         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1612 }
1613
1614 static void tg3_phy_fini(struct tg3 *tp)
1615 {
1616         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1617                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1618                 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1619         }
1620 }
1621
1622 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1623 {
1624         u32 phytest;
1625
1626         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1627                 u32 phy;
1628
1629                 tg3_writephy(tp, MII_TG3_FET_TEST,
1630                              phytest | MII_TG3_FET_SHADOW_EN);
1631                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1632                         if (enable)
1633                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1634                         else
1635                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1636                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1637                 }
1638                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1639         }
1640 }
1641
1642 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1643 {
1644         u32 reg;
1645
1646         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1647             ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
1648              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1649                 return;
1650
1651         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1652                 tg3_phy_fet_toggle_apd(tp, enable);
1653                 return;
1654         }
1655
1656         reg = MII_TG3_MISC_SHDW_WREN |
1657               MII_TG3_MISC_SHDW_SCR5_SEL |
1658               MII_TG3_MISC_SHDW_SCR5_LPED |
1659               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1660               MII_TG3_MISC_SHDW_SCR5_SDTL |
1661               MII_TG3_MISC_SHDW_SCR5_C125OE;
1662         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1663                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1664
1665         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1666
1667
1668         reg = MII_TG3_MISC_SHDW_WREN |
1669               MII_TG3_MISC_SHDW_APD_SEL |
1670               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1671         if (enable)
1672                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1673
1674         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1675 }
1676
1677 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1678 {
1679         u32 phy;
1680
1681         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1682             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1683                 return;
1684
1685         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1686                 u32 ephy;
1687
1688                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1689                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1690
1691                         tg3_writephy(tp, MII_TG3_FET_TEST,
1692                                      ephy | MII_TG3_FET_SHADOW_EN);
1693                         if (!tg3_readphy(tp, reg, &phy)) {
1694                                 if (enable)
1695                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1696                                 else
1697                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1698                                 tg3_writephy(tp, reg, phy);
1699                         }
1700                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1701                 }
1702         } else {
1703                 int ret;
1704
1705                 ret = tg3_phy_auxctl_read(tp,
1706                                           MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
1707                 if (!ret) {
1708                         if (enable)
1709                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1710                         else
1711                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1712                         tg3_phy_auxctl_write(tp,
1713                                              MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
1714                 }
1715         }
1716 }
1717
1718 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1719 {
1720         int ret;
1721         u32 val;
1722
1723         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1724                 return;
1725
1726         ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
1727         if (!ret)
1728                 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
1729                                      val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
1730 }
1731
1732 static void tg3_phy_apply_otp(struct tg3 *tp)
1733 {
1734         u32 otp, phy;
1735
1736         if (!tp->phy_otp)
1737                 return;
1738
1739         otp = tp->phy_otp;
1740
1741         /* Enable SM_DSP clock and tx 6dB coding. */
1742         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1743               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1744               MII_TG3_AUXCTL_ACTL_TX_6DB;
1745         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1746
1747         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1748         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1749         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1750
1751         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1752               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1753         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1754
1755         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1756         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1757         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1758
1759         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1760         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1761
1762         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1763         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1764
1765         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1766               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1767         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1768
1769         /* Turn off SM_DSP clock. */
1770         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1771               MII_TG3_AUXCTL_ACTL_TX_6DB;
1772         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1773 }
1774
1775 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
1776 {
1777         u32 val;
1778
1779         if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
1780                 return;
1781
1782         tp->setlpicnt = 0;
1783
1784         if (tp->link_config.autoneg == AUTONEG_ENABLE &&
1785             current_link_up == 1 &&
1786             tp->link_config.active_duplex == DUPLEX_FULL &&
1787             (tp->link_config.active_speed == SPEED_100 ||
1788              tp->link_config.active_speed == SPEED_1000)) {
1789                 u32 eeectl;
1790
1791                 if (tp->link_config.active_speed == SPEED_1000)
1792                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
1793                 else
1794                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
1795
1796                 tw32(TG3_CPMU_EEE_CTRL, eeectl);
1797
1798                 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
1799                                   TG3_CL45_D7_EEERES_STAT, &val);
1800
1801                 switch (val) {
1802                 case TG3_CL45_D7_EEERES_STAT_LP_1000T:
1803                         switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
1804                         case ASIC_REV_5717:
1805                         case ASIC_REV_5719:
1806                         case ASIC_REV_57765:
1807                                 /* Enable SM_DSP clock and tx 6dB coding. */
1808                                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1809                                       MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1810                                       MII_TG3_AUXCTL_ACTL_TX_6DB;
1811                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1812
1813                                 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
1814
1815                                 /* Turn off SM_DSP clock. */
1816                                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1817                                       MII_TG3_AUXCTL_ACTL_TX_6DB;
1818                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1819                         }
1820                         /* Fallthrough */
1821                 case TG3_CL45_D7_EEERES_STAT_LP_100TX:
1822                         tp->setlpicnt = 2;
1823                 }
1824         }
1825
1826         if (!tp->setlpicnt) {
1827                 val = tr32(TG3_CPMU_EEE_MODE);
1828                 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
1829         }
1830 }
1831
1832 static int tg3_wait_macro_done(struct tg3 *tp)
1833 {
1834         int limit = 100;
1835
1836         while (limit--) {
1837                 u32 tmp32;
1838
1839                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1840                         if ((tmp32 & 0x1000) == 0)
1841                                 break;
1842                 }
1843         }
1844         if (limit < 0)
1845                 return -EBUSY;
1846
1847         return 0;
1848 }
1849
1850 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1851 {
1852         static const u32 test_pat[4][6] = {
1853         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1854         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1855         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1856         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1857         };
1858         int chan;
1859
1860         for (chan = 0; chan < 4; chan++) {
1861                 int i;
1862
1863                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1864                              (chan * 0x2000) | 0x0200);
1865                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1866
1867                 for (i = 0; i < 6; i++)
1868                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1869                                      test_pat[chan][i]);
1870
1871                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1872                 if (tg3_wait_macro_done(tp)) {
1873                         *resetp = 1;
1874                         return -EBUSY;
1875                 }
1876
1877                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1878                              (chan * 0x2000) | 0x0200);
1879                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1880                 if (tg3_wait_macro_done(tp)) {
1881                         *resetp = 1;
1882                         return -EBUSY;
1883                 }
1884
1885                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1886                 if (tg3_wait_macro_done(tp)) {
1887                         *resetp = 1;
1888                         return -EBUSY;
1889                 }
1890
1891                 for (i = 0; i < 6; i += 2) {
1892                         u32 low, high;
1893
1894                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1895                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1896                             tg3_wait_macro_done(tp)) {
1897                                 *resetp = 1;
1898                                 return -EBUSY;
1899                         }
1900                         low &= 0x7fff;
1901                         high &= 0x000f;
1902                         if (low != test_pat[chan][i] ||
1903                             high != test_pat[chan][i+1]) {
1904                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1905                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1906                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1907
1908                                 return -EBUSY;
1909                         }
1910                 }
1911         }
1912
1913         return 0;
1914 }
1915
1916 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1917 {
1918         int chan;
1919
1920         for (chan = 0; chan < 4; chan++) {
1921                 int i;
1922
1923                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1924                              (chan * 0x2000) | 0x0200);
1925                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1926                 for (i = 0; i < 6; i++)
1927                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1928                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1929                 if (tg3_wait_macro_done(tp))
1930                         return -EBUSY;
1931         }
1932
1933         return 0;
1934 }
1935
1936 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1937 {
1938         u32 reg32, phy9_orig;
1939         int retries, do_phy_reset, err;
1940
1941         retries = 10;
1942         do_phy_reset = 1;
1943         do {
1944                 if (do_phy_reset) {
1945                         err = tg3_bmcr_reset(tp);
1946                         if (err)
1947                                 return err;
1948                         do_phy_reset = 0;
1949                 }
1950
1951                 /* Disable transmitter and interrupt.  */
1952                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1953                         continue;
1954
1955                 reg32 |= 0x3000;
1956                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1957
1958                 /* Set full-duplex, 1000 mbps.  */
1959                 tg3_writephy(tp, MII_BMCR,
1960                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1961
1962                 /* Set to master mode.  */
1963                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1964                         continue;
1965
1966                 tg3_writephy(tp, MII_TG3_CTRL,
1967                              (MII_TG3_CTRL_AS_MASTER |
1968                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1969
1970                 /* Enable SM_DSP_CLOCK and 6dB.  */
1971                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1972
1973                 /* Block the PHY control access.  */
1974                 tg3_phydsp_write(tp, 0x8005, 0x0800);
1975
1976                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1977                 if (!err)
1978                         break;
1979         } while (--retries);
1980
1981         err = tg3_phy_reset_chanpat(tp);
1982         if (err)
1983                 return err;
1984
1985         tg3_phydsp_write(tp, 0x8005, 0x0000);
1986
1987         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1988         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1989
1990         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1991             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1992                 /* Set Extended packet length bit for jumbo frames */
1993                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1994         } else {
1995                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1996         }
1997
1998         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1999
2000         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
2001                 reg32 &= ~0x3000;
2002                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2003         } else if (!err)
2004                 err = -EBUSY;
2005
2006         return err;
2007 }
2008
2009 /* This will reset the tigon3 PHY if there is no valid
2010  * link unless the FORCE argument is non-zero.
2011  */
2012 static int tg3_phy_reset(struct tg3 *tp)
2013 {
2014         u32 val, cpmuctrl;
2015         int err;
2016
2017         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2018                 val = tr32(GRC_MISC_CFG);
2019                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2020                 udelay(40);
2021         }
2022         err  = tg3_readphy(tp, MII_BMSR, &val);
2023         err |= tg3_readphy(tp, MII_BMSR, &val);
2024         if (err != 0)
2025                 return -EBUSY;
2026
2027         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
2028                 netif_carrier_off(tp->dev);
2029                 tg3_link_report(tp);
2030         }
2031
2032         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2033             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2034             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2035                 err = tg3_phy_reset_5703_4_5(tp);
2036                 if (err)
2037                         return err;
2038                 goto out;
2039         }
2040
2041         cpmuctrl = 0;
2042         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2043             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2044                 cpmuctrl = tr32(TG3_CPMU_CTRL);
2045                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2046                         tw32(TG3_CPMU_CTRL,
2047                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2048         }
2049
2050         err = tg3_bmcr_reset(tp);
2051         if (err)
2052                 return err;
2053
2054         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2055                 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2056                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2057
2058                 tw32(TG3_CPMU_CTRL, cpmuctrl);
2059         }
2060
2061         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2062             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2063                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2064                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2065                     CPMU_LSPD_1000MB_MACCLK_12_5) {
2066                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2067                         udelay(40);
2068                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2069                 }
2070         }
2071
2072         if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
2073             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2074                 return 0;
2075
2076         tg3_phy_apply_otp(tp);
2077
2078         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2079                 tg3_phy_toggle_apd(tp, true);
2080         else
2081                 tg3_phy_toggle_apd(tp, false);
2082
2083 out:
2084         if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
2085                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2086                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2087                 tg3_phydsp_write(tp, 0x000a, 0x0323);
2088                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2089         }
2090         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2091                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2092                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2093         }
2094         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2095                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2096                 tg3_phydsp_write(tp, 0x000a, 0x310b);
2097                 tg3_phydsp_write(tp, 0x201f, 0x9506);
2098                 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2099                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2100         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2101                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2102                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2103                 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2104                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2105                         tg3_writephy(tp, MII_TG3_TEST1,
2106                                      MII_TG3_TEST1_TRIM_EN | 0x4);
2107                 } else
2108                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2109                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2110         }
2111         /* Set Extended packet length bit (bit 14) on all chips that */
2112         /* support jumbo frames */
2113         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2114                 /* Cannot do read-modify-write on 5401 */
2115                 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2116         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2117                 /* Set bit 14 with read-modify-write to preserve other bits */
2118                 err = tg3_phy_auxctl_read(tp,
2119                                           MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2120                 if (!err)
2121                         tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2122                                            val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
2123         }
2124
2125         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2126          * jumbo frames transmission.
2127          */
2128         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2129                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2130                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2131                                      val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2132         }
2133
2134         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2135                 /* adjust output voltage */
2136                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2137         }
2138
2139         tg3_phy_toggle_automdix(tp, 1);
2140         tg3_phy_set_wirespeed(tp);
2141         return 0;
2142 }
2143
2144 static void tg3_frob_aux_power(struct tg3 *tp)
2145 {
2146         bool need_vaux = false;
2147
2148         /* The GPIOs do something completely different on 57765. */
2149         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2150             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2151             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2152                 return;
2153
2154         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2155              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2156              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2157              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) &&
2158             tp->pdev_peer != tp->pdev) {
2159                 struct net_device *dev_peer;
2160
2161                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2162
2163                 /* remove_one() may have been run on the peer. */
2164                 if (dev_peer) {
2165                         struct tg3 *tp_peer = netdev_priv(dev_peer);
2166
2167                         if (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE)
2168                                 return;
2169
2170                         if ((tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) ||
2171                             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF))
2172                                 need_vaux = true;
2173                 }
2174         }
2175
2176         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) ||
2177             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2178                 need_vaux = true;
2179
2180         if (need_vaux) {
2181                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2182                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2183                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2184                                     (GRC_LCLCTRL_GPIO_OE0 |
2185                                      GRC_LCLCTRL_GPIO_OE1 |
2186                                      GRC_LCLCTRL_GPIO_OE2 |
2187                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2188                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2189                                     100);
2190                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2191                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2192                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2193                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2194                                              GRC_LCLCTRL_GPIO_OE1 |
2195                                              GRC_LCLCTRL_GPIO_OE2 |
2196                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2197                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2198                                              tp->grc_local_ctrl;
2199                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2200
2201                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2202                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2203
2204                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2205                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2206                 } else {
2207                         u32 no_gpio2;
2208                         u32 grc_local_ctrl = 0;
2209
2210                         /* Workaround to prevent overdrawing Amps. */
2211                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2212                             ASIC_REV_5714) {
2213                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2214                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2215                                             grc_local_ctrl, 100);
2216                         }
2217
2218                         /* On 5753 and variants, GPIO2 cannot be used. */
2219                         no_gpio2 = tp->nic_sram_data_cfg &
2220                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2221
2222                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2223                                          GRC_LCLCTRL_GPIO_OE1 |
2224                                          GRC_LCLCTRL_GPIO_OE2 |
2225                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2226                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2227                         if (no_gpio2) {
2228                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2229                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2230                         }
2231                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2232                                                     grc_local_ctrl, 100);
2233
2234                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2235
2236                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2237                                                     grc_local_ctrl, 100);
2238
2239                         if (!no_gpio2) {
2240                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2241                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2242                                             grc_local_ctrl, 100);
2243                         }
2244                 }
2245         } else {
2246                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2247                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2248                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2249                                     (GRC_LCLCTRL_GPIO_OE1 |
2250                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2251
2252                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2253                                     GRC_LCLCTRL_GPIO_OE1, 100);
2254
2255                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2256                                     (GRC_LCLCTRL_GPIO_OE1 |
2257                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2258                 }
2259         }
2260 }
2261
2262 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2263 {
2264         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2265                 return 1;
2266         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2267                 if (speed != SPEED_10)
2268                         return 1;
2269         } else if (speed == SPEED_10)
2270                 return 1;
2271
2272         return 0;
2273 }
2274
2275 static int tg3_setup_phy(struct tg3 *, int);
2276
2277 #define RESET_KIND_SHUTDOWN     0
2278 #define RESET_KIND_INIT         1
2279 #define RESET_KIND_SUSPEND      2
2280
2281 static void tg3_write_sig_post_reset(struct tg3 *, int);
2282 static int tg3_halt_cpu(struct tg3 *, u32);
2283
2284 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2285 {
2286         u32 val;
2287
2288         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2289                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2290                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2291                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2292
2293                         sg_dig_ctrl |=
2294                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2295                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2296                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2297                 }
2298                 return;
2299         }
2300
2301         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2302                 tg3_bmcr_reset(tp);
2303                 val = tr32(GRC_MISC_CFG);
2304                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2305                 udelay(40);
2306                 return;
2307         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2308                 u32 phytest;
2309                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2310                         u32 phy;
2311
2312                         tg3_writephy(tp, MII_ADVERTISE, 0);
2313                         tg3_writephy(tp, MII_BMCR,
2314                                      BMCR_ANENABLE | BMCR_ANRESTART);
2315
2316                         tg3_writephy(tp, MII_TG3_FET_TEST,
2317                                      phytest | MII_TG3_FET_SHADOW_EN);
2318                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2319                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2320                                 tg3_writephy(tp,
2321                                              MII_TG3_FET_SHDW_AUXMODE4,
2322                                              phy);
2323                         }
2324                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2325                 }
2326                 return;
2327         } else if (do_low_power) {
2328                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2329                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2330
2331                 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2332                       MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2333                       MII_TG3_AUXCTL_PCTL_VREG_11V;
2334                 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
2335         }
2336
2337         /* The PHY should not be powered down on some chips because
2338          * of bugs.
2339          */
2340         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2341             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2342             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2343              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2344                 return;
2345
2346         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2347             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2348                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2349                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2350                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2351                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2352         }
2353
2354         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2355 }
2356
2357 /* tp->lock is held. */
2358 static int tg3_nvram_lock(struct tg3 *tp)
2359 {
2360         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2361                 int i;
2362
2363                 if (tp->nvram_lock_cnt == 0) {
2364                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2365                         for (i = 0; i < 8000; i++) {
2366                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2367                                         break;
2368                                 udelay(20);
2369                         }
2370                         if (i == 8000) {
2371                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2372                                 return -ENODEV;
2373                         }
2374                 }
2375                 tp->nvram_lock_cnt++;
2376         }
2377         return 0;
2378 }
2379
2380 /* tp->lock is held. */
2381 static void tg3_nvram_unlock(struct tg3 *tp)
2382 {
2383         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2384                 if (tp->nvram_lock_cnt > 0)
2385                         tp->nvram_lock_cnt--;
2386                 if (tp->nvram_lock_cnt == 0)
2387                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2388         }
2389 }
2390
2391 /* tp->lock is held. */
2392 static void tg3_enable_nvram_access(struct tg3 *tp)
2393 {
2394         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2395             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2396                 u32 nvaccess = tr32(NVRAM_ACCESS);
2397
2398                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2399         }
2400 }
2401
2402 /* tp->lock is held. */
2403 static void tg3_disable_nvram_access(struct tg3 *tp)
2404 {
2405         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2406             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2407                 u32 nvaccess = tr32(NVRAM_ACCESS);
2408
2409                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2410         }
2411 }
2412
2413 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2414                                         u32 offset, u32 *val)
2415 {
2416         u32 tmp;
2417         int i;
2418
2419         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2420                 return -EINVAL;
2421
2422         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2423                                         EEPROM_ADDR_DEVID_MASK |
2424                                         EEPROM_ADDR_READ);
2425         tw32(GRC_EEPROM_ADDR,
2426              tmp |
2427              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2428              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2429               EEPROM_ADDR_ADDR_MASK) |
2430              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2431
2432         for (i = 0; i < 1000; i++) {
2433                 tmp = tr32(GRC_EEPROM_ADDR);
2434
2435                 if (tmp & EEPROM_ADDR_COMPLETE)
2436                         break;
2437                 msleep(1);
2438         }
2439         if (!(tmp & EEPROM_ADDR_COMPLETE))
2440                 return -EBUSY;
2441
2442         tmp = tr32(GRC_EEPROM_DATA);
2443
2444         /*
2445          * The data will always be opposite the native endian
2446          * format.  Perform a blind byteswap to compensate.
2447          */
2448         *val = swab32(tmp);
2449
2450         return 0;
2451 }
2452
2453 #define NVRAM_CMD_TIMEOUT 10000
2454
2455 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2456 {
2457         int i;
2458
2459         tw32(NVRAM_CMD, nvram_cmd);
2460         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2461                 udelay(10);
2462                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2463                         udelay(10);
2464                         break;
2465                 }
2466         }
2467
2468         if (i == NVRAM_CMD_TIMEOUT)
2469                 return -EBUSY;
2470
2471         return 0;
2472 }
2473
2474 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2475 {
2476         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2477             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2478             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2479            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2480             (tp->nvram_jedecnum == JEDEC_ATMEL))
2481
2482                 addr = ((addr / tp->nvram_pagesize) <<
2483                         ATMEL_AT45DB0X1B_PAGE_POS) +
2484                        (addr % tp->nvram_pagesize);
2485
2486         return addr;
2487 }
2488
2489 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2490 {
2491         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2492             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2493             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2494            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2495             (tp->nvram_jedecnum == JEDEC_ATMEL))
2496
2497                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2498                         tp->nvram_pagesize) +
2499                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2500
2501         return addr;
2502 }
2503
2504 /* NOTE: Data read in from NVRAM is byteswapped according to
2505  * the byteswapping settings for all other register accesses.
2506  * tg3 devices are BE devices, so on a BE machine, the data
2507  * returned will be exactly as it is seen in NVRAM.  On a LE
2508  * machine, the 32-bit value will be byteswapped.
2509  */
2510 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2511 {
2512         int ret;
2513
2514         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2515                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2516
2517         offset = tg3_nvram_phys_addr(tp, offset);
2518
2519         if (offset > NVRAM_ADDR_MSK)
2520                 return -EINVAL;
2521
2522         ret = tg3_nvram_lock(tp);
2523         if (ret)
2524                 return ret;
2525
2526         tg3_enable_nvram_access(tp);
2527
2528         tw32(NVRAM_ADDR, offset);
2529         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2530                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2531
2532         if (ret == 0)
2533                 *val = tr32(NVRAM_RDDATA);
2534
2535         tg3_disable_nvram_access(tp);
2536
2537         tg3_nvram_unlock(tp);
2538
2539         return ret;
2540 }
2541
2542 /* Ensures NVRAM data is in bytestream format. */
2543 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2544 {
2545         u32 v;
2546         int res = tg3_nvram_read(tp, offset, &v);
2547         if (!res)
2548                 *val = cpu_to_be32(v);
2549         return res;
2550 }
2551
2552 /* tp->lock is held. */
2553 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2554 {
2555         u32 addr_high, addr_low;
2556         int i;
2557
2558         addr_high = ((tp->dev->dev_addr[0] << 8) |
2559                      tp->dev->dev_addr[1]);
2560         addr_low = ((tp->dev->dev_addr[2] << 24) |
2561                     (tp->dev->dev_addr[3] << 16) |
2562                     (tp->dev->dev_addr[4] <<  8) |
2563                     (tp->dev->dev_addr[5] <<  0));
2564         for (i = 0; i < 4; i++) {
2565                 if (i == 1 && skip_mac_1)
2566                         continue;
2567                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2568                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2569         }
2570
2571         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2572             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2573                 for (i = 0; i < 12; i++) {
2574                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2575                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2576                 }
2577         }
2578
2579         addr_high = (tp->dev->dev_addr[0] +
2580                      tp->dev->dev_addr[1] +
2581                      tp->dev->dev_addr[2] +
2582                      tp->dev->dev_addr[3] +
2583                      tp->dev->dev_addr[4] +
2584                      tp->dev->dev_addr[5]) &
2585                 TX_BACKOFF_SEED_MASK;
2586         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2587 }
2588
2589 static void tg3_enable_register_access(struct tg3 *tp)
2590 {
2591         /*
2592          * Make sure register accesses (indirect or otherwise) will function
2593          * correctly.
2594          */
2595         pci_write_config_dword(tp->pdev,
2596                                TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
2597 }
2598
2599 static int tg3_power_up(struct tg3 *tp)
2600 {
2601         tg3_enable_register_access(tp);
2602
2603         pci_set_power_state(tp->pdev, PCI_D0);
2604
2605         /* Switch out of Vaux if it is a NIC */
2606         if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2607                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2608
2609         return 0;
2610 }
2611
2612 static int tg3_power_down_prepare(struct tg3 *tp)
2613 {
2614         u32 misc_host_ctrl;
2615         bool device_should_wake, do_low_power;
2616
2617         tg3_enable_register_access(tp);
2618
2619         /* Restore the CLKREQ setting. */
2620         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2621                 u16 lnkctl;
2622
2623                 pci_read_config_word(tp->pdev,
2624                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2625                                      &lnkctl);
2626                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2627                 pci_write_config_word(tp->pdev,
2628                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2629                                       lnkctl);
2630         }
2631
2632         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2633         tw32(TG3PCI_MISC_HOST_CTRL,
2634              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2635
2636         device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
2637                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2638
2639         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2640                 do_low_power = false;
2641                 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2642                     !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2643                         struct phy_device *phydev;
2644                         u32 phyid, advertising;
2645
2646                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2647
2648                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2649
2650                         tp->link_config.orig_speed = phydev->speed;
2651                         tp->link_config.orig_duplex = phydev->duplex;
2652                         tp->link_config.orig_autoneg = phydev->autoneg;
2653                         tp->link_config.orig_advertising = phydev->advertising;
2654
2655                         advertising = ADVERTISED_TP |
2656                                       ADVERTISED_Pause |
2657                                       ADVERTISED_Autoneg |
2658                                       ADVERTISED_10baseT_Half;
2659
2660                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2661                             device_should_wake) {
2662                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2663                                         advertising |=
2664                                                 ADVERTISED_100baseT_Half |
2665                                                 ADVERTISED_100baseT_Full |
2666                                                 ADVERTISED_10baseT_Full;
2667                                 else
2668                                         advertising |= ADVERTISED_10baseT_Full;
2669                         }
2670
2671                         phydev->advertising = advertising;
2672
2673                         phy_start_aneg(phydev);
2674
2675                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2676                         if (phyid != PHY_ID_BCMAC131) {
2677                                 phyid &= PHY_BCM_OUI_MASK;
2678                                 if (phyid == PHY_BCM_OUI_1 ||
2679                                     phyid == PHY_BCM_OUI_2 ||
2680                                     phyid == PHY_BCM_OUI_3)
2681                                         do_low_power = true;
2682                         }
2683                 }
2684         } else {
2685                 do_low_power = true;
2686
2687                 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2688                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2689                         tp->link_config.orig_speed = tp->link_config.speed;
2690                         tp->link_config.orig_duplex = tp->link_config.duplex;
2691                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2692                 }
2693
2694                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2695                         tp->link_config.speed = SPEED_10;
2696                         tp->link_config.duplex = DUPLEX_HALF;
2697                         tp->link_config.autoneg = AUTONEG_ENABLE;
2698                         tg3_setup_phy(tp, 0);
2699                 }
2700         }
2701
2702         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2703                 u32 val;
2704
2705                 val = tr32(GRC_VCPU_EXT_CTRL);
2706                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2707         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2708                 int i;
2709                 u32 val;
2710
2711                 for (i = 0; i < 200; i++) {
2712                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2713                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2714                                 break;
2715                         msleep(1);
2716                 }
2717         }
2718         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2719                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2720                                                      WOL_DRV_STATE_SHUTDOWN |
2721                                                      WOL_DRV_WOL |
2722                                                      WOL_SET_MAGIC_PKT);
2723
2724         if (device_should_wake) {
2725                 u32 mac_mode;
2726
2727                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2728                         if (do_low_power &&
2729                             !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
2730                                 tg3_phy_auxctl_write(tp,
2731                                                MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
2732                                                MII_TG3_AUXCTL_PCTL_WOL_EN |
2733                                                MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2734                                                MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
2735                                 udelay(40);
2736                         }
2737
2738                         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2739                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2740                         else
2741                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2742
2743                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2744                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2745                             ASIC_REV_5700) {
2746                                 u32 speed = (tp->tg3_flags &
2747                                              TG3_FLAG_WOL_SPEED_100MB) ?
2748                                              SPEED_100 : SPEED_10;
2749                                 if (tg3_5700_link_polarity(tp, speed))
2750                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2751                                 else
2752                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2753                         }
2754                 } else {
2755                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2756                 }
2757
2758                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2759                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2760
2761                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2762                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2763                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2764                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2765                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2766                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2767
2768                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
2769                         mac_mode |= MAC_MODE_APE_TX_EN |
2770                                     MAC_MODE_APE_RX_EN |
2771                                     MAC_MODE_TDE_ENABLE;
2772
2773                 tw32_f(MAC_MODE, mac_mode);
2774                 udelay(100);
2775
2776                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2777                 udelay(10);
2778         }
2779
2780         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2781             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2782              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2783                 u32 base_val;
2784
2785                 base_val = tp->pci_clock_ctrl;
2786                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2787                              CLOCK_CTRL_TXCLK_DISABLE);
2788
2789                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2790                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2791         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2792                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2793                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2794                 /* do nothing */
2795         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2796                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2797                 u32 newbits1, newbits2;
2798
2799                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2800                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2801                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2802                                     CLOCK_CTRL_TXCLK_DISABLE |
2803                                     CLOCK_CTRL_ALTCLK);
2804                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2805                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2806                         newbits1 = CLOCK_CTRL_625_CORE;
2807                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2808                 } else {
2809                         newbits1 = CLOCK_CTRL_ALTCLK;
2810                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2811                 }
2812
2813                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2814                             40);
2815
2816                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2817                             40);
2818
2819                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2820                         u32 newbits3;
2821
2822                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2823                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2824                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2825                                             CLOCK_CTRL_TXCLK_DISABLE |
2826                                             CLOCK_CTRL_44MHZ_CORE);
2827                         } else {
2828                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2829                         }
2830
2831                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2832                                     tp->pci_clock_ctrl | newbits3, 40);
2833                 }
2834         }
2835
2836         if (!(device_should_wake) &&
2837             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2838                 tg3_power_down_phy(tp, do_low_power);
2839
2840         tg3_frob_aux_power(tp);
2841
2842         /* Workaround for unstable PLL clock */
2843         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2844             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2845                 u32 val = tr32(0x7d00);
2846
2847                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2848                 tw32(0x7d00, val);
2849                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2850                         int err;
2851
2852                         err = tg3_nvram_lock(tp);
2853                         tg3_halt_cpu(tp, RX_CPU_BASE);
2854                         if (!err)
2855                                 tg3_nvram_unlock(tp);
2856                 }
2857         }
2858
2859         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2860
2861         return 0;
2862 }
2863
2864 static void tg3_power_down(struct tg3 *tp)
2865 {
2866         tg3_power_down_prepare(tp);
2867
2868         pci_wake_from_d3(tp->pdev, tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2869         pci_set_power_state(tp->pdev, PCI_D3hot);
2870 }
2871
2872 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2873 {
2874         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2875         case MII_TG3_AUX_STAT_10HALF:
2876                 *speed = SPEED_10;
2877                 *duplex = DUPLEX_HALF;
2878                 break;
2879
2880         case MII_TG3_AUX_STAT_10FULL:
2881                 *speed = SPEED_10;
2882                 *duplex = DUPLEX_FULL;
2883                 break;
2884
2885         case MII_TG3_AUX_STAT_100HALF:
2886                 *speed = SPEED_100;
2887                 *duplex = DUPLEX_HALF;
2888                 break;
2889
2890         case MII_TG3_AUX_STAT_100FULL:
2891                 *speed = SPEED_100;
2892                 *duplex = DUPLEX_FULL;
2893                 break;
2894
2895         case MII_TG3_AUX_STAT_1000HALF:
2896                 *speed = SPEED_1000;
2897                 *duplex = DUPLEX_HALF;
2898                 break;
2899
2900         case MII_TG3_AUX_STAT_1000FULL:
2901                 *speed = SPEED_1000;
2902                 *duplex = DUPLEX_FULL;
2903                 break;
2904
2905         default:
2906                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2907                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2908                                  SPEED_10;
2909                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2910                                   DUPLEX_HALF;
2911                         break;
2912                 }
2913                 *speed = SPEED_INVALID;
2914                 *duplex = DUPLEX_INVALID;
2915                 break;
2916         }
2917 }
2918
2919 static void tg3_phy_copper_begin(struct tg3 *tp)
2920 {
2921         u32 new_adv;
2922         int i;
2923
2924         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2925                 /* Entering low power mode.  Disable gigabit and
2926                  * 100baseT advertisements.
2927                  */
2928                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2929
2930                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2931                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2932                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2933                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2934
2935                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2936         } else if (tp->link_config.speed == SPEED_INVALID) {
2937                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2938                         tp->link_config.advertising &=
2939                                 ~(ADVERTISED_1000baseT_Half |
2940                                   ADVERTISED_1000baseT_Full);
2941
2942                 new_adv = ADVERTISE_CSMA;
2943                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2944                         new_adv |= ADVERTISE_10HALF;
2945                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2946                         new_adv |= ADVERTISE_10FULL;
2947                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2948                         new_adv |= ADVERTISE_100HALF;
2949                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2950                         new_adv |= ADVERTISE_100FULL;
2951
2952                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2953
2954                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2955
2956                 if (tp->link_config.advertising &
2957                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2958                         new_adv = 0;
2959                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2960                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2961                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2962                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2963                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
2964                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2965                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2966                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2967                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2968                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2969                 } else {
2970                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2971                 }
2972         } else {
2973                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2974                 new_adv |= ADVERTISE_CSMA;
2975
2976                 /* Asking for a specific link mode. */
2977                 if (tp->link_config.speed == SPEED_1000) {
2978                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2979
2980                         if (tp->link_config.duplex == DUPLEX_FULL)
2981                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2982                         else
2983                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2984                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2985                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2986                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2987                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2988                 } else {
2989                         if (tp->link_config.speed == SPEED_100) {
2990                                 if (tp->link_config.duplex == DUPLEX_FULL)
2991                                         new_adv |= ADVERTISE_100FULL;
2992                                 else
2993                                         new_adv |= ADVERTISE_100HALF;
2994                         } else {
2995                                 if (tp->link_config.duplex == DUPLEX_FULL)
2996                                         new_adv |= ADVERTISE_10FULL;
2997                                 else
2998                                         new_adv |= ADVERTISE_10HALF;
2999                         }
3000                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
3001
3002                         new_adv = 0;
3003                 }
3004
3005                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
3006         }
3007
3008         if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
3009                 u32 val;
3010
3011                 tw32(TG3_CPMU_EEE_MODE,
3012                      tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
3013
3014                 /* Enable SM_DSP clock and tx 6dB coding. */
3015                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
3016                       MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
3017                       MII_TG3_AUXCTL_ACTL_TX_6DB;
3018                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3019
3020                 switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
3021                 case ASIC_REV_5717:
3022                 case ASIC_REV_57765:
3023                         if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
3024                                 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
3025                                                  MII_TG3_DSP_CH34TP2_HIBW01);
3026                         /* Fall through */
3027                 case ASIC_REV_5719:
3028                         val = MII_TG3_DSP_TAP26_ALNOKO |
3029                               MII_TG3_DSP_TAP26_RMRXSTO |
3030                               MII_TG3_DSP_TAP26_OPCSINPT;
3031                         tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
3032                 }
3033
3034                 val = 0;
3035                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3036                         /* Advertise 100-BaseTX EEE ability */
3037                         if (tp->link_config.advertising &
3038                             ADVERTISED_100baseT_Full)
3039                                 val |= MDIO_AN_EEE_ADV_100TX;
3040                         /* Advertise 1000-BaseT EEE ability */
3041                         if (tp->link_config.advertising &
3042                             ADVERTISED_1000baseT_Full)
3043                                 val |= MDIO_AN_EEE_ADV_1000T;
3044                 }
3045                 tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3046
3047                 /* Turn off SM_DSP clock. */
3048                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
3049                       MII_TG3_AUXCTL_ACTL_TX_6DB;
3050                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3051         }
3052
3053         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
3054             tp->link_config.speed != SPEED_INVALID) {
3055                 u32 bmcr, orig_bmcr;
3056
3057                 tp->link_config.active_speed = tp->link_config.speed;
3058                 tp->link_config.active_duplex = tp->link_config.duplex;
3059
3060                 bmcr = 0;
3061                 switch (tp->link_config.speed) {
3062                 default:
3063                 case SPEED_10:
3064                         break;
3065
3066                 case SPEED_100:
3067                         bmcr |= BMCR_SPEED100;
3068                         break;
3069
3070                 case SPEED_1000:
3071                         bmcr |= TG3_BMCR_SPEED1000;
3072                         break;
3073                 }
3074
3075                 if (tp->link_config.duplex == DUPLEX_FULL)
3076                         bmcr |= BMCR_FULLDPLX;
3077
3078                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
3079                     (bmcr != orig_bmcr)) {
3080                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
3081                         for (i = 0; i < 1500; i++) {
3082                                 u32 tmp;
3083
3084                                 udelay(10);
3085                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
3086                                     tg3_readphy(tp, MII_BMSR, &tmp))
3087                                         continue;
3088                                 if (!(tmp & BMSR_LSTATUS)) {
3089                                         udelay(40);
3090                                         break;
3091                                 }
3092                         }
3093                         tg3_writephy(tp, MII_BMCR, bmcr);
3094                         udelay(40);
3095                 }
3096         } else {
3097                 tg3_writephy(tp, MII_BMCR,
3098                              BMCR_ANENABLE | BMCR_ANRESTART);
3099         }
3100 }
3101
3102 static int tg3_init_5401phy_dsp(struct tg3 *tp)
3103 {
3104         int err;
3105
3106         /* Turn off tap power management. */
3107         /* Set Extended packet length bit */
3108         err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
3109
3110         err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
3111         err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
3112         err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
3113         err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
3114         err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
3115
3116         udelay(40);
3117
3118         return err;
3119 }
3120
3121 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3122 {
3123         u32 adv_reg, all_mask = 0;
3124
3125         if (mask & ADVERTISED_10baseT_Half)
3126                 all_mask |= ADVERTISE_10HALF;
3127         if (mask & ADVERTISED_10baseT_Full)
3128                 all_mask |= ADVERTISE_10FULL;
3129         if (mask & ADVERTISED_100baseT_Half)
3130                 all_mask |= ADVERTISE_100HALF;
3131         if (mask & ADVERTISED_100baseT_Full)
3132                 all_mask |= ADVERTISE_100FULL;
3133
3134         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3135                 return 0;
3136
3137         if ((adv_reg & all_mask) != all_mask)
3138                 return 0;
3139         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3140                 u32 tg3_ctrl;
3141
3142                 all_mask = 0;
3143                 if (mask & ADVERTISED_1000baseT_Half)
3144                         all_mask |= ADVERTISE_1000HALF;
3145                 if (mask & ADVERTISED_1000baseT_Full)
3146                         all_mask |= ADVERTISE_1000FULL;
3147
3148                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3149                         return 0;
3150
3151                 if ((tg3_ctrl & all_mask) != all_mask)
3152                         return 0;
3153         }
3154         return 1;
3155 }
3156
3157 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3158 {
3159         u32 curadv, reqadv;
3160
3161         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3162                 return 1;
3163
3164         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3165         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3166
3167         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3168                 if (curadv != reqadv)
3169                         return 0;
3170
3171                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3172                         tg3_readphy(tp, MII_LPA, rmtadv);
3173         } else {
3174                 /* Reprogram the advertisement register, even if it
3175                  * does not affect the current link.  If the link
3176                  * gets renegotiated in the future, we can save an
3177                  * additional renegotiation cycle by advertising
3178                  * it correctly in the first place.
3179                  */
3180                 if (curadv != reqadv) {
3181                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3182                                      ADVERTISE_PAUSE_ASYM);
3183                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3184                 }
3185         }
3186
3187         return 1;
3188 }
3189
3190 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3191 {
3192         int current_link_up;
3193         u32 bmsr, val;
3194         u32 lcl_adv, rmt_adv;
3195         u16 current_speed;
3196         u8 current_duplex;
3197         int i, err;
3198
3199         tw32(MAC_EVENT, 0);
3200
3201         tw32_f(MAC_STATUS,
3202              (MAC_STATUS_SYNC_CHANGED |
3203               MAC_STATUS_CFG_CHANGED |
3204               MAC_STATUS_MI_COMPLETION |
3205               MAC_STATUS_LNKSTATE_CHANGED));
3206         udelay(40);
3207
3208         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3209                 tw32_f(MAC_MI_MODE,
3210                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3211                 udelay(80);
3212         }
3213
3214         tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
3215
3216         /* Some third-party PHYs need to be reset on link going
3217          * down.
3218          */
3219         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3220              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3221              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3222             netif_carrier_ok(tp->dev)) {
3223                 tg3_readphy(tp, MII_BMSR, &bmsr);
3224                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3225                     !(bmsr & BMSR_LSTATUS))
3226                         force_reset = 1;
3227         }
3228         if (force_reset)
3229                 tg3_phy_reset(tp);
3230
3231         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3232                 tg3_readphy(tp, MII_BMSR, &bmsr);
3233                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3234                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3235                         bmsr = 0;
3236
3237                 if (!(bmsr & BMSR_LSTATUS)) {
3238                         err = tg3_init_5401phy_dsp(tp);
3239                         if (err)
3240                                 return err;
3241
3242                         tg3_readphy(tp, MII_BMSR, &bmsr);
3243                         for (i = 0; i < 1000; i++) {
3244                                 udelay(10);
3245                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3246                                     (bmsr & BMSR_LSTATUS)) {
3247                                         udelay(40);
3248                                         break;
3249                                 }
3250                         }
3251
3252                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3253                             TG3_PHY_REV_BCM5401_B0 &&
3254                             !(bmsr & BMSR_LSTATUS) &&
3255                             tp->link_config.active_speed == SPEED_1000) {
3256                                 err = tg3_phy_reset(tp);
3257                                 if (!err)
3258                                         err = tg3_init_5401phy_dsp(tp);
3259                                 if (err)
3260                                         return err;
3261                         }
3262                 }
3263         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3264                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3265                 /* 5701 {A0,B0} CRC bug workaround */
3266                 tg3_writephy(tp, 0x15, 0x0a75);
3267                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3268                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3269                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3270         }
3271
3272         /* Clear pending interrupts... */
3273         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3274         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3275
3276         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3277                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3278         else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3279                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3280
3281         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3282             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3283                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3284                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3285                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3286                 else
3287                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3288         }
3289
3290         current_link_up = 0;
3291         current_speed = SPEED_INVALID;
3292         current_duplex = DUPLEX_INVALID;
3293
3294         if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3295                 err = tg3_phy_auxctl_read(tp,
3296                                           MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
3297                                           &val);
3298                 if (!err && !(val & (1 << 10))) {
3299                         tg3_phy_auxctl_write(tp,
3300                                              MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
3301                                              val | (1 << 10));
3302                         goto relink;
3303                 }
3304         }
3305
3306         bmsr = 0;
3307         for (i = 0; i < 100; i++) {
3308                 tg3_readphy(tp, MII_BMSR, &bmsr);
3309                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3310                     (bmsr & BMSR_LSTATUS))
3311                         break;
3312                 udelay(40);
3313         }
3314
3315         if (bmsr & BMSR_LSTATUS) {
3316                 u32 aux_stat, bmcr;
3317
3318                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3319                 for (i = 0; i < 2000; i++) {
3320                         udelay(10);
3321                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3322                             aux_stat)
3323                                 break;
3324                 }
3325
3326                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3327                                              &current_speed,
3328                                              &current_duplex);
3329
3330                 bmcr = 0;
3331                 for (i = 0; i < 200; i++) {
3332                         tg3_readphy(tp, MII_BMCR, &bmcr);
3333                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3334                                 continue;
3335                         if (bmcr && bmcr != 0x7fff)
3336                                 break;
3337                         udelay(10);
3338                 }
3339
3340                 lcl_adv = 0;
3341                 rmt_adv = 0;
3342
3343                 tp->link_config.active_speed = current_speed;
3344                 tp->link_config.active_duplex = current_duplex;
3345
3346                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3347                         if ((bmcr & BMCR_ANENABLE) &&
3348                             tg3_copper_is_advertising_all(tp,
3349                                                 tp->link_config.advertising)) {
3350                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3351                                                                   &rmt_adv))
3352                                         current_link_up = 1;
3353                         }
3354                 } else {
3355                         if (!(bmcr & BMCR_ANENABLE) &&
3356                             tp->link_config.speed == current_speed &&
3357                             tp->link_config.duplex == current_duplex &&
3358                             tp->link_config.flowctrl ==
3359                             tp->link_config.active_flowctrl) {
3360                                 current_link_up = 1;
3361                         }
3362                 }
3363
3364                 if (current_link_up == 1 &&
3365                     tp->link_config.active_duplex == DUPLEX_FULL)
3366                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3367         }
3368
3369 relink:
3370         if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3371                 tg3_phy_copper_begin(tp);
3372
3373                 tg3_readphy(tp, MII_BMSR, &bmsr);
3374                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3375                     (bmsr & BMSR_LSTATUS))
3376                         current_link_up = 1;
3377         }
3378
3379         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3380         if (current_link_up == 1) {
3381                 if (tp->link_config.active_speed == SPEED_100 ||
3382                     tp->link_config.active_speed == SPEED_10)
3383                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3384                 else
3385                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3386         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3387                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3388         else
3389                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3390
3391         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3392         if (tp->link_config.active_duplex == DUPLEX_HALF)
3393                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3394
3395         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3396                 if (current_link_up == 1 &&
3397                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3398                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3399                 else
3400                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3401         }
3402
3403         /* ??? Without this setting Netgear GA302T PHY does not
3404          * ??? send/receive packets...
3405          */
3406         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3407             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3408                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3409                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3410                 udelay(80);
3411         }
3412
3413         tw32_f(MAC_MODE, tp->mac_mode);
3414         udelay(40);
3415
3416         tg3_phy_eee_adjust(tp, current_link_up);
3417
3418         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3419                 /* Polled via timer. */
3420                 tw32_f(MAC_EVENT, 0);
3421         } else {
3422                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3423         }
3424         udelay(40);
3425
3426         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3427             current_link_up == 1 &&
3428             tp->link_config.active_speed == SPEED_1000 &&
3429             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3430              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3431                 udelay(120);
3432                 tw32_f(MAC_STATUS,
3433                      (MAC_STATUS_SYNC_CHANGED |
3434                       MAC_STATUS_CFG_CHANGED));
3435                 udelay(40);
3436                 tg3_write_mem(tp,
3437                               NIC_SRAM_FIRMWARE_MBOX,
3438                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3439         }
3440
3441         /* Prevent send BD corruption. */
3442         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3443                 u16 oldlnkctl, newlnkctl;
3444
3445                 pci_read_config_word(tp->pdev,
3446                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3447                                      &oldlnkctl);
3448                 if (tp->link_config.active_speed == SPEED_100 ||
3449                     tp->link_config.active_speed == SPEED_10)
3450                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3451                 else
3452                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3453                 if (newlnkctl != oldlnkctl)
3454                         pci_write_config_word(tp->pdev,
3455                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3456                                               newlnkctl);
3457         }
3458
3459         if (current_link_up != netif_carrier_ok(tp->dev)) {
3460                 if (current_link_up)
3461                         netif_carrier_on(tp->dev);
3462                 else
3463                         netif_carrier_off(tp->dev);
3464                 tg3_link_report(tp);
3465         }
3466
3467         return 0;
3468 }
3469
3470 struct tg3_fiber_aneginfo {
3471         int state;
3472 #define ANEG_STATE_UNKNOWN              0
3473 #define ANEG_STATE_AN_ENABLE            1
3474 #define ANEG_STATE_RESTART_INIT         2
3475 #define ANEG_STATE_RESTART              3
3476 #define ANEG_STATE_DISABLE_LINK_OK      4
3477 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3478 #define ANEG_STATE_ABILITY_DETECT       6
3479 #define ANEG_STATE_ACK_DETECT_INIT      7
3480 #define ANEG_STATE_ACK_DETECT           8
3481 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3482 #define ANEG_STATE_COMPLETE_ACK         10
3483 #define ANEG_STATE_IDLE_DETECT_INIT     11
3484 #define ANEG_STATE_IDLE_DETECT          12
3485 #define ANEG_STATE_LINK_OK              13
3486 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3487 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3488
3489         u32 flags;
3490 #define MR_AN_ENABLE            0x00000001
3491 #define MR_RESTART_AN           0x00000002
3492 #define MR_AN_COMPLETE          0x00000004
3493 #define MR_PAGE_RX              0x00000008
3494 #define MR_NP_LOADED            0x00000010
3495 #define MR_TOGGLE_TX            0x00000020
3496 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3497 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3498 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3499 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3500 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3501 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3502 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3503 #define MR_TOGGLE_RX            0x00002000
3504 #define MR_NP_RX                0x00004000
3505
3506 #define MR_LINK_OK              0x80000000
3507
3508         unsigned long link_time, cur_time;
3509
3510         u32 ability_match_cfg;
3511         int ability_match_count;
3512
3513         char ability_match, idle_match, ack_match;
3514
3515         u32 txconfig, rxconfig;
3516 #define ANEG_CFG_NP             0x00000080
3517 #define ANEG_CFG_ACK            0x00000040
3518 #define ANEG_CFG_RF2            0x00000020
3519 #define ANEG_CFG_RF1            0x00000010
3520 #define ANEG_CFG_PS2            0x00000001
3521 #define ANEG_CFG_PS1            0x00008000
3522 #define ANEG_CFG_HD             0x00004000
3523 #define ANEG_CFG_FD             0x00002000
3524 #define ANEG_CFG_INVAL          0x00001f06
3525
3526 };
3527 #define ANEG_OK         0
3528 #define ANEG_DONE       1
3529 #define ANEG_TIMER_ENAB 2
3530 #define ANEG_FAILED     -1
3531
3532 #define ANEG_STATE_SETTLE_TIME  10000
3533
3534 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3535                                    struct tg3_fiber_aneginfo *ap)
3536 {
3537         u16 flowctrl;
3538         unsigned long delta;
3539         u32 rx_cfg_reg;
3540         int ret;
3541
3542         if (ap->state == ANEG_STATE_UNKNOWN) {
3543                 ap->rxconfig = 0;
3544                 ap->link_time = 0;
3545                 ap->cur_time = 0;
3546                 ap->ability_match_cfg = 0;
3547                 ap->ability_match_count = 0;
3548                 ap->ability_match = 0;
3549                 ap->idle_match = 0;
3550                 ap->ack_match = 0;
3551         }
3552         ap->cur_time++;
3553
3554         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3555                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3556
3557                 if (rx_cfg_reg != ap->ability_match_cfg) {
3558                         ap->ability_match_cfg = rx_cfg_reg;
3559                         ap->ability_match = 0;
3560                         ap->ability_match_count = 0;
3561                 } else {
3562                         if (++ap->ability_match_count > 1) {
3563                                 ap->ability_match = 1;
3564                                 ap->ability_match_cfg = rx_cfg_reg;
3565                         }
3566                 }
3567                 if (rx_cfg_reg & ANEG_CFG_ACK)
3568                         ap->ack_match = 1;
3569                 else
3570                         ap->ack_match = 0;
3571
3572                 ap->idle_match = 0;
3573         } else {
3574                 ap->idle_match = 1;
3575                 ap->ability_match_cfg = 0;
3576                 ap->ability_match_count = 0;
3577                 ap->ability_match = 0;
3578                 ap->ack_match = 0;
3579
3580                 rx_cfg_reg = 0;
3581         }
3582
3583         ap->rxconfig = rx_cfg_reg;
3584         ret = ANEG_OK;
3585
3586         switch (ap->state) {
3587         case ANEG_STATE_UNKNOWN:
3588                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3589                         ap->state = ANEG_STATE_AN_ENABLE;
3590
3591                 /* fallthru */
3592         case ANEG_STATE_AN_ENABLE:
3593                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3594                 if (ap->flags & MR_AN_ENABLE) {
3595                         ap->link_time = 0;
3596                         ap->cur_time = 0;
3597                         ap->ability_match_cfg = 0;
3598                         ap->ability_match_count = 0;
3599                         ap->ability_match = 0;
3600                         ap->idle_match = 0;
3601                         ap->ack_match = 0;
3602
3603                         ap->state = ANEG_STATE_RESTART_INIT;
3604                 } else {
3605                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3606                 }
3607                 break;
3608
3609         case ANEG_STATE_RESTART_INIT:
3610                 ap->link_time = ap->cur_time;
3611                 ap->flags &= ~(MR_NP_LOADED);
3612                 ap->txconfig = 0;
3613                 tw32(MAC_TX_AUTO_NEG, 0);
3614                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3615                 tw32_f(MAC_MODE, tp->mac_mode);
3616                 udelay(40);
3617
3618                 ret = ANEG_TIMER_ENAB;
3619                 ap->state = ANEG_STATE_RESTART;
3620
3621                 /* fallthru */
3622         case ANEG_STATE_RESTART:
3623                 delta = ap->cur_time - ap->link_time;
3624                 if (delta > ANEG_STATE_SETTLE_TIME)
3625                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3626                 else
3627                         ret = ANEG_TIMER_ENAB;
3628                 break;
3629
3630         case ANEG_STATE_DISABLE_LINK_OK:
3631                 ret = ANEG_DONE;
3632                 break;
3633
3634         case ANEG_STATE_ABILITY_DETECT_INIT:
3635                 ap->flags &= ~(MR_TOGGLE_TX);
3636                 ap->txconfig = ANEG_CFG_FD;
3637                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3638                 if (flowctrl & ADVERTISE_1000XPAUSE)
3639                         ap->txconfig |= ANEG_CFG_PS1;
3640                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3641                         ap->txconfig |= ANEG_CFG_PS2;
3642                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3643                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3644                 tw32_f(MAC_MODE, tp->mac_mode);
3645                 udelay(40);
3646
3647                 ap->state = ANEG_STATE_ABILITY_DETECT;
3648                 break;
3649
3650         case ANEG_STATE_ABILITY_DETECT:
3651                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3652                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3653                 break;
3654
3655         case ANEG_STATE_ACK_DETECT_INIT:
3656                 ap->txconfig |= ANEG_CFG_ACK;
3657                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3658                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3659                 tw32_f(MAC_MODE, tp->mac_mode);
3660                 udelay(40);
3661
3662                 ap->state = ANEG_STATE_ACK_DETECT;
3663
3664                 /* fallthru */
3665         case ANEG_STATE_ACK_DETECT:
3666                 if (ap->ack_match != 0) {
3667                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3668                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3669                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3670                         } else {
3671                                 ap->state = ANEG_STATE_AN_ENABLE;
3672                         }
3673                 } else if (ap->ability_match != 0 &&
3674                            ap->rxconfig == 0) {
3675                         ap->state = ANEG_STATE_AN_ENABLE;
3676                 }
3677                 break;
3678
3679         case ANEG_STATE_COMPLETE_ACK_INIT:
3680                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3681                         ret = ANEG_FAILED;
3682                         break;
3683                 }
3684                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3685                                MR_LP_ADV_HALF_DUPLEX |
3686                                MR_LP_ADV_SYM_PAUSE |
3687                                MR_LP_ADV_ASYM_PAUSE |
3688                                MR_LP_ADV_REMOTE_FAULT1 |
3689                                MR_LP_ADV_REMOTE_FAULT2 |
3690                                MR_LP_ADV_NEXT_PAGE |
3691                                MR_TOGGLE_RX |
3692                                MR_NP_RX);
3693                 if (ap->rxconfig & ANEG_CFG_FD)
3694                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3695                 if (ap->rxconfig & ANEG_CFG_HD)
3696                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3697                 if (ap->rxconfig & ANEG_CFG_PS1)
3698                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3699                 if (ap->rxconfig & ANEG_CFG_PS2)
3700                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3701                 if (ap->rxconfig & ANEG_CFG_RF1)
3702                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3703                 if (ap->rxconfig & ANEG_CFG_RF2)
3704                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3705                 if (ap->rxconfig & ANEG_CFG_NP)
3706                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3707
3708                 ap->link_time = ap->cur_time;
3709
3710                 ap->flags ^= (MR_TOGGLE_TX);
3711                 if (ap->rxconfig & 0x0008)
3712                         ap->flags |= MR_TOGGLE_RX;
3713                 if (ap->rxconfig & ANEG_CFG_NP)
3714                         ap->flags |= MR_NP_RX;
3715                 ap->flags |= MR_PAGE_RX;
3716
3717                 ap->state = ANEG_STATE_COMPLETE_ACK;
3718                 ret = ANEG_TIMER_ENAB;
3719                 break;
3720
3721         case ANEG_STATE_COMPLETE_ACK:
3722                 if (ap->ability_match != 0 &&
3723                     ap->rxconfig == 0) {
3724                         ap->state = ANEG_STATE_AN_ENABLE;
3725                         break;
3726                 }
3727                 delta = ap->cur_time - ap->link_time;
3728                 if (delta > ANEG_STATE_SETTLE_TIME) {
3729                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3730                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3731                         } else {
3732                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3733                                     !(ap->flags & MR_NP_RX)) {
3734                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3735                                 } else {
3736                                         ret = ANEG_FAILED;
3737                                 }
3738                         }
3739                 }
3740                 break;
3741
3742         case ANEG_STATE_IDLE_DETECT_INIT:
3743                 ap->link_time = ap->cur_time;
3744                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3745                 tw32_f(MAC_MODE, tp->mac_mode);
3746                 udelay(40);
3747
3748                 ap->state = ANEG_STATE_IDLE_DETECT;
3749                 ret = ANEG_TIMER_ENAB;
3750                 break;
3751
3752         case ANEG_STATE_IDLE_DETECT:
3753                 if (ap->ability_match != 0 &&
3754                     ap->rxconfig == 0) {
3755                         ap->state = ANEG_STATE_AN_ENABLE;
3756                         break;
3757                 }
3758                 delta = ap->cur_time - ap->link_time;
3759                 if (delta > ANEG_STATE_SETTLE_TIME) {
3760                         /* XXX another gem from the Broadcom driver :( */
3761                         ap->state = ANEG_STATE_LINK_OK;
3762                 }
3763                 break;
3764
3765         case ANEG_STATE_LINK_OK:
3766                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3767                 ret = ANEG_DONE;
3768                 break;
3769
3770         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3771                 /* ??? unimplemented */
3772                 break;
3773
3774         case ANEG_STATE_NEXT_PAGE_WAIT:
3775                 /* ??? unimplemented */
3776                 break;
3777
3778         default:
3779                 ret = ANEG_FAILED;
3780                 break;
3781         }
3782
3783         return ret;
3784 }
3785
3786 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3787 {
3788         int res = 0;
3789         struct tg3_fiber_aneginfo aninfo;
3790         int status = ANEG_FAILED;
3791         unsigned int tick;
3792         u32 tmp;
3793
3794         tw32_f(MAC_TX_AUTO_NEG, 0);
3795
3796         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3797         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3798         udelay(40);
3799
3800         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3801         udelay(40);
3802
3803         memset(&aninfo, 0, sizeof(aninfo));
3804         aninfo.flags |= MR_AN_ENABLE;
3805         aninfo.state = ANEG_STATE_UNKNOWN;
3806         aninfo.cur_time = 0;
3807         tick = 0;
3808         while (++tick < 195000) {
3809                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3810                 if (status == ANEG_DONE || status == ANEG_FAILED)
3811                         break;
3812
3813                 udelay(1);
3814         }
3815
3816         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3817         tw32_f(MAC_MODE, tp->mac_mode);
3818         udelay(40);
3819
3820         *txflags = aninfo.txconfig;
3821         *rxflags = aninfo.flags;
3822
3823         if (status == ANEG_DONE &&
3824             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3825                              MR_LP_ADV_FULL_DUPLEX)))
3826                 res = 1;
3827
3828         return res;
3829 }
3830
3831 static void tg3_init_bcm8002(struct tg3 *tp)
3832 {
3833         u32 mac_status = tr32(MAC_STATUS);
3834         int i;
3835
3836         /* Reset when initting first time or we have a link. */
3837         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3838             !(mac_status & MAC_STATUS_PCS_SYNCED))
3839                 return;
3840
3841         /* Set PLL lock range. */
3842         tg3_writephy(tp, 0x16, 0x8007);
3843
3844         /* SW reset */
3845         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3846
3847         /* Wait for reset to complete. */
3848         /* XXX schedule_timeout() ... */
3849         for (i = 0; i < 500; i++)
3850                 udelay(10);
3851
3852         /* Config mode; select PMA/Ch 1 regs. */
3853         tg3_writephy(tp, 0x10, 0x8411);
3854
3855         /* Enable auto-lock and comdet, select txclk for tx. */
3856         tg3_writephy(tp, 0x11, 0x0a10);
3857
3858         tg3_writephy(tp, 0x18, 0x00a0);
3859         tg3_writephy(tp, 0x16, 0x41ff);
3860
3861         /* Assert and deassert POR. */
3862         tg3_writephy(tp, 0x13, 0x0400);
3863         udelay(40);
3864         tg3_writephy(tp, 0x13, 0x0000);
3865
3866         tg3_writephy(tp, 0x11, 0x0a50);
3867         udelay(40);
3868         tg3_writephy(tp, 0x11, 0x0a10);
3869
3870         /* Wait for signal to stabilize */
3871         /* XXX schedule_timeout() ... */
3872         for (i = 0; i < 15000; i++)
3873                 udelay(10);
3874
3875         /* Deselect the channel register so we can read the PHYID
3876          * later.
3877          */
3878         tg3_writephy(tp, 0x10, 0x8011);
3879 }
3880
3881 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3882 {
3883         u16 flowctrl;
3884         u32 sg_dig_ctrl, sg_dig_status;
3885         u32 serdes_cfg, expected_sg_dig_ctrl;
3886         int workaround, port_a;
3887         int current_link_up;
3888
3889         serdes_cfg = 0;
3890         expected_sg_dig_ctrl = 0;
3891         workaround = 0;
3892         port_a = 1;
3893         current_link_up = 0;
3894
3895         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3896             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3897                 workaround = 1;
3898                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3899                         port_a = 0;
3900
3901                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3902                 /* preserve bits 20-23 for voltage regulator */
3903                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3904         }
3905
3906         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3907
3908         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3909                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3910                         if (workaround) {
3911                                 u32 val = serdes_cfg;
3912
3913                                 if (port_a)
3914                                         val |= 0xc010000;
3915                                 else
3916                                         val |= 0x4010000;
3917                                 tw32_f(MAC_SERDES_CFG, val);
3918                         }
3919
3920                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3921                 }
3922                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3923                         tg3_setup_flow_control(tp, 0, 0);
3924                         current_link_up = 1;
3925                 }
3926                 goto out;
3927         }
3928
3929         /* Want auto-negotiation.  */
3930         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3931
3932         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3933         if (flowctrl & ADVERTISE_1000XPAUSE)
3934                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3935         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3936                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3937
3938         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3939                 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3940                     tp->serdes_counter &&
3941                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3942                                     MAC_STATUS_RCVD_CFG)) ==
3943                      MAC_STATUS_PCS_SYNCED)) {
3944                         tp->serdes_counter--;
3945                         current_link_up = 1;
3946                         goto out;
3947                 }
3948 restart_autoneg:
3949                 if (workaround)
3950                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3951                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3952                 udelay(5);
3953                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3954
3955                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3956                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3957         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3958                                  MAC_STATUS_SIGNAL_DET)) {
3959                 sg_dig_status = tr32(SG_DIG_STATUS);
3960                 mac_status = tr32(MAC_STATUS);
3961
3962                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3963                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3964                         u32 local_adv = 0, remote_adv = 0;
3965
3966                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3967                                 local_adv |= ADVERTISE_1000XPAUSE;
3968                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3969                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3970
3971                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3972                                 remote_adv |= LPA_1000XPAUSE;
3973                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3974                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3975
3976                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3977                         current_link_up = 1;
3978                         tp->serdes_counter = 0;
3979                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3980                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3981                         if (tp->serdes_counter)
3982                                 tp->serdes_counter--;
3983                         else {
3984                                 if (workaround) {
3985                                         u32 val = serdes_cfg;
3986
3987                                         if (port_a)
3988                                                 val |= 0xc010000;
3989                                         else
3990                                                 val |= 0x4010000;
3991
3992                                         tw32_f(MAC_SERDES_CFG, val);
3993                                 }
3994
3995                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3996                                 udelay(40);
3997
3998                                 /* Link parallel detection - link is up */
3999                                 /* only if we have PCS_SYNC and not */
4000                                 /* receiving config code words */
4001                                 mac_status = tr32(MAC_STATUS);
4002                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
4003                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
4004                                         tg3_setup_flow_control(tp, 0, 0);
4005                                         current_link_up = 1;
4006                                         tp->phy_flags |=
4007                                                 TG3_PHYFLG_PARALLEL_DETECT;
4008                                         tp->serdes_counter =
4009                                                 SERDES_PARALLEL_DET_TIMEOUT;
4010                                 } else
4011                                         goto restart_autoneg;
4012                         }
4013                 }
4014         } else {
4015                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
4016                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4017         }
4018
4019 out:
4020         return current_link_up;
4021 }
4022
4023 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
4024 {
4025         int current_link_up = 0;
4026
4027         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
4028                 goto out;
4029
4030         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4031                 u32 txflags, rxflags;
4032                 int i;
4033
4034                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
4035                         u32 local_adv = 0, remote_adv = 0;
4036
4037                         if (txflags & ANEG_CFG_PS1)
4038                                 local_adv |= ADVERTISE_1000XPAUSE;
4039                         if (txflags & ANEG_CFG_PS2)
4040                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
4041
4042                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
4043                                 remote_adv |= LPA_1000XPAUSE;
4044                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
4045                                 remote_adv |= LPA_1000XPAUSE_ASYM;
4046
4047                         tg3_setup_flow_control(tp, local_adv, remote_adv);
4048
4049                         current_link_up = 1;
4050                 }
4051                 for (i = 0; i < 30; i++) {
4052                         udelay(20);
4053                         tw32_f(MAC_STATUS,
4054                                (MAC_STATUS_SYNC_CHANGED |
4055                                 MAC_STATUS_CFG_CHANGED));
4056                         udelay(40);
4057                         if ((tr32(MAC_STATUS) &
4058                              (MAC_STATUS_SYNC_CHANGED |
4059                               MAC_STATUS_CFG_CHANGED)) == 0)
4060                                 break;
4061                 }
4062
4063                 mac_status = tr32(MAC_STATUS);
4064                 if (current_link_up == 0 &&
4065                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
4066                     !(mac_status & MAC_STATUS_RCVD_CFG))
4067                         current_link_up = 1;
4068         } else {
4069                 tg3_setup_flow_control(tp, 0, 0);
4070
4071                 /* Forcing 1000FD link up. */
4072                 current_link_up = 1;
4073
4074                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
4075                 udelay(40);
4076
4077                 tw32_f(MAC_MODE, tp->mac_mode);
4078                 udelay(40);
4079         }
4080
4081 out:
4082         return current_link_up;
4083 }
4084
4085 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4086 {
4087         u32 orig_pause_cfg;
4088         u16 orig_active_speed;
4089         u8 orig_active_duplex;
4090         u32 mac_status;
4091         int current_link_up;
4092         int i;
4093
4094         orig_pause_cfg = tp->link_config.active_flowctrl;
4095         orig_active_speed = tp->link_config.active_speed;
4096         orig_active_duplex = tp->link_config.active_duplex;
4097
4098         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
4099             netif_carrier_ok(tp->dev) &&
4100             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
4101                 mac_status = tr32(MAC_STATUS);
4102                 mac_status &= (MAC_STATUS_PCS_SYNCED |
4103                                MAC_STATUS_SIGNAL_DET |
4104                                MAC_STATUS_CFG_CHANGED |
4105                                MAC_STATUS_RCVD_CFG);
4106                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
4107                                    MAC_STATUS_SIGNAL_DET)) {
4108                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4109                                             MAC_STATUS_CFG_CHANGED));
4110                         return 0;
4111                 }
4112         }
4113
4114         tw32_f(MAC_TX_AUTO_NEG, 0);
4115
4116         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
4117         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
4118         tw32_f(MAC_MODE, tp->mac_mode);
4119         udelay(40);
4120
4121         if (tp->phy_id == TG3_PHY_ID_BCM8002)
4122                 tg3_init_bcm8002(tp);
4123
4124         /* Enable link change event even when serdes polling.  */
4125         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4126         udelay(40);
4127
4128         current_link_up = 0;
4129         mac_status = tr32(MAC_STATUS);
4130
4131         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
4132                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4133         else
4134                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4135
4136         tp->napi[0].hw_status->status =
4137                 (SD_STATUS_UPDATED |
4138                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4139
4140         for (i = 0; i < 100; i++) {
4141                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4142                                     MAC_STATUS_CFG_CHANGED));
4143                 udelay(5);
4144                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4145                                          MAC_STATUS_CFG_CHANGED |
4146                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4147                         break;
4148         }
4149
4150         mac_status = tr32(MAC_STATUS);
4151         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4152                 current_link_up = 0;
4153                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4154                     tp->serdes_counter == 0) {
4155                         tw32_f(MAC_MODE, (tp->mac_mode |
4156                                           MAC_MODE_SEND_CONFIGS));
4157                         udelay(1);
4158                         tw32_f(MAC_MODE, tp->mac_mode);
4159                 }
4160         }
4161
4162         if (current_link_up == 1) {
4163                 tp->link_config.active_speed = SPEED_1000;
4164                 tp->link_config.active_duplex = DUPLEX_FULL;
4165                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4166                                     LED_CTRL_LNKLED_OVERRIDE |
4167                                     LED_CTRL_1000MBPS_ON));
4168         } else {
4169                 tp->link_config.active_speed = SPEED_INVALID;
4170                 tp->link_config.active_duplex = DUPLEX_INVALID;
4171                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4172                                     LED_CTRL_LNKLED_OVERRIDE |
4173                                     LED_CTRL_TRAFFIC_OVERRIDE));
4174         }
4175
4176         if (current_link_up != netif_carrier_ok(tp->dev)) {
4177                 if (current_link_up)
4178                         netif_carrier_on(tp->dev);
4179                 else
4180                         netif_carrier_off(tp->dev);
4181                 tg3_link_report(tp);
4182         } else {
4183                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4184                 if (orig_pause_cfg != now_pause_cfg ||
4185                     orig_active_speed != tp->link_config.active_speed ||
4186                     orig_active_duplex != tp->link_config.active_duplex)
4187                         tg3_link_report(tp);
4188         }
4189
4190         return 0;
4191 }
4192
4193 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4194 {
4195         int current_link_up, err = 0;
4196         u32 bmsr, bmcr;
4197         u16 current_speed;
4198         u8 current_duplex;
4199         u32 local_adv, remote_adv;
4200
4201         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4202         tw32_f(MAC_MODE, tp->mac_mode);
4203         udelay(40);
4204
4205         tw32(MAC_EVENT, 0);
4206
4207         tw32_f(MAC_STATUS,
4208              (MAC_STATUS_SYNC_CHANGED |
4209               MAC_STATUS_CFG_CHANGED |
4210               MAC_STATUS_MI_COMPLETION |
4211               MAC_STATUS_LNKSTATE_CHANGED));
4212         udelay(40);
4213
4214         if (force_reset)
4215                 tg3_phy_reset(tp);
4216
4217         current_link_up = 0;
4218         current_speed = SPEED_INVALID;
4219         current_duplex = DUPLEX_INVALID;
4220
4221         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4222         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4223         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4224                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4225                         bmsr |= BMSR_LSTATUS;
4226                 else
4227                         bmsr &= ~BMSR_LSTATUS;
4228         }
4229
4230         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4231
4232         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4233             (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4234                 /* do nothing, just check for link up at the end */
4235         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4236                 u32 adv, new_adv;
4237
4238                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4239                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4240                                   ADVERTISE_1000XPAUSE |
4241                                   ADVERTISE_1000XPSE_ASYM |
4242                                   ADVERTISE_SLCT);
4243
4244                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4245
4246                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4247                         new_adv |= ADVERTISE_1000XHALF;
4248                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4249                         new_adv |= ADVERTISE_1000XFULL;
4250
4251                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4252                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4253                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4254                         tg3_writephy(tp, MII_BMCR, bmcr);
4255
4256                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4257                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4258                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4259
4260                         return err;
4261                 }
4262         } else {
4263                 u32 new_bmcr;
4264
4265                 bmcr &= ~BMCR_SPEED1000;
4266                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4267
4268                 if (tp->link_config.duplex == DUPLEX_FULL)
4269                         new_bmcr |= BMCR_FULLDPLX;
4270
4271                 if (new_bmcr != bmcr) {
4272                         /* BMCR_SPEED1000 is a reserved bit that needs
4273                          * to be set on write.
4274                          */
4275                         new_bmcr |= BMCR_SPEED1000;
4276
4277                         /* Force a linkdown */
4278                         if (netif_carrier_ok(tp->dev)) {
4279                                 u32 adv;
4280
4281                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4282                                 adv &= ~(ADVERTISE_1000XFULL |
4283                                          ADVERTISE_1000XHALF |
4284                                          ADVERTISE_SLCT);
4285                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4286                                 tg3_writephy(tp, MII_BMCR, bmcr |
4287                                                            BMCR_ANRESTART |
4288                                                            BMCR_ANENABLE);
4289                                 udelay(10);
4290                                 netif_carrier_off(tp->dev);
4291                         }
4292                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4293                         bmcr = new_bmcr;
4294                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4295                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4296                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4297                             ASIC_REV_5714) {
4298                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4299                                         bmsr |= BMSR_LSTATUS;
4300                                 else
4301                                         bmsr &= ~BMSR_LSTATUS;
4302                         }
4303                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4304                 }
4305         }
4306
4307         if (bmsr & BMSR_LSTATUS) {
4308                 current_speed = SPEED_1000;
4309                 current_link_up = 1;
4310                 if (bmcr & BMCR_FULLDPLX)
4311                         current_duplex = DUPLEX_FULL;
4312                 else
4313                         current_duplex = DUPLEX_HALF;
4314
4315                 local_adv = 0;
4316                 remote_adv = 0;
4317
4318                 if (bmcr & BMCR_ANENABLE) {
4319                         u32 common;
4320
4321                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4322                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4323                         common = local_adv & remote_adv;
4324                         if (common & (ADVERTISE_1000XHALF |
4325                                       ADVERTISE_1000XFULL)) {
4326                                 if (common & ADVERTISE_1000XFULL)
4327                                         current_duplex = DUPLEX_FULL;
4328                                 else
4329                                         current_duplex = DUPLEX_HALF;
4330                         } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4331                                 /* Link is up via parallel detect */
4332                         } else {
4333                                 current_link_up = 0;
4334                         }
4335                 }
4336         }
4337
4338         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4339                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4340
4341         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4342         if (tp->link_config.active_duplex == DUPLEX_HALF)
4343                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4344
4345         tw32_f(MAC_MODE, tp->mac_mode);
4346         udelay(40);
4347
4348         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4349
4350         tp->link_config.active_speed = current_speed;
4351         tp->link_config.active_duplex = current_duplex;
4352
4353         if (current_link_up != netif_carrier_ok(tp->dev)) {
4354                 if (current_link_up)
4355                         netif_carrier_on(tp->dev);
4356                 else {
4357                         netif_carrier_off(tp->dev);
4358                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4359                 }
4360                 tg3_link_report(tp);
4361         }
4362         return err;
4363 }
4364
4365 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4366 {
4367         if (tp->serdes_counter) {
4368                 /* Give autoneg time to complete. */
4369                 tp->serdes_counter--;
4370                 return;
4371         }
4372
4373         if (!netif_carrier_ok(tp->dev) &&
4374             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4375                 u32 bmcr;
4376
4377                 tg3_readphy(tp, MII_BMCR, &bmcr);
4378                 if (bmcr & BMCR_ANENABLE) {
4379                         u32 phy1, phy2;
4380
4381                         /* Select shadow register 0x1f */
4382                         tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4383                         tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4384
4385                         /* Select expansion interrupt status register */
4386                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4387                                          MII_TG3_DSP_EXP1_INT_STAT);
4388                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4389                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4390
4391                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4392                                 /* We have signal detect and not receiving
4393                                  * config code words, link is up by parallel
4394                                  * detection.
4395                                  */
4396
4397                                 bmcr &= ~BMCR_ANENABLE;
4398                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4399                                 tg3_writephy(tp, MII_BMCR, bmcr);
4400                                 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4401                         }
4402                 }
4403         } else if (netif_carrier_ok(tp->dev) &&
4404                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4405                    (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4406                 u32 phy2;
4407
4408                 /* Select expansion interrupt status register */
4409                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4410                                  MII_TG3_DSP_EXP1_INT_STAT);
4411                 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4412                 if (phy2 & 0x20) {
4413                         u32 bmcr;
4414
4415                         /* Config code words received, turn on autoneg. */
4416                         tg3_readphy(tp, MII_BMCR, &bmcr);
4417                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4418
4419                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4420
4421                 }
4422         }
4423 }
4424
4425 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4426 {
4427         u32 val;
4428         int err;
4429
4430         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4431                 err = tg3_setup_fiber_phy(tp, force_reset);
4432         else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4433                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4434         else
4435                 err = tg3_setup_copper_phy(tp, force_reset);
4436
4437         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4438                 u32 scale;
4439
4440                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4441                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4442                         scale = 65;
4443                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4444                         scale = 6;
4445                 else
4446                         scale = 12;
4447
4448                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4449                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4450                 tw32(GRC_MISC_CFG, val);
4451         }
4452
4453         val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4454               (6 << TX_LENGTHS_IPG_SHIFT);
4455         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
4456                 val |= tr32(MAC_TX_LENGTHS) &
4457                        (TX_LENGTHS_JMB_FRM_LEN_MSK |
4458                         TX_LENGTHS_CNT_DWN_VAL_MSK);
4459
4460         if (tp->link_config.active_speed == SPEED_1000 &&
4461             tp->link_config.active_duplex == DUPLEX_HALF)
4462                 tw32(MAC_TX_LENGTHS, val |
4463                      (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
4464         else
4465                 tw32(MAC_TX_LENGTHS, val |
4466                      (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
4467
4468         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4469                 if (netif_carrier_ok(tp->dev)) {
4470                         tw32(HOSTCC_STAT_COAL_TICKS,
4471                              tp->coal.stats_block_coalesce_usecs);
4472                 } else {
4473                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4474                 }
4475         }
4476
4477         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4478                 val = tr32(PCIE_PWR_MGMT_THRESH);
4479                 if (!netif_carrier_ok(tp->dev))
4480                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4481                               tp->pwrmgmt_thresh;
4482                 else
4483                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4484                 tw32(PCIE_PWR_MGMT_THRESH, val);
4485         }
4486
4487         return err;
4488 }
4489
4490 static inline int tg3_irq_sync(struct tg3 *tp)
4491 {
4492         return tp->irq_sync;
4493 }
4494
4495 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
4496 {
4497         int i;
4498
4499         dst = (u32 *)((u8 *)dst + off);
4500         for (i = 0; i < len; i += sizeof(u32))
4501                 *dst++ = tr32(off + i);
4502 }
4503
4504 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
4505 {
4506         tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
4507         tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
4508         tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
4509         tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
4510         tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
4511         tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
4512         tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
4513         tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
4514         tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
4515         tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
4516         tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
4517         tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
4518         tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
4519         tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
4520         tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
4521         tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
4522         tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
4523         tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
4524         tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
4525
4526         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX)
4527                 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
4528
4529         tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
4530         tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
4531         tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
4532         tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
4533         tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
4534         tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
4535         tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
4536         tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
4537
4538         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4539                 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
4540                 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
4541                 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
4542         }
4543
4544         tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
4545         tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
4546         tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
4547         tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
4548         tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
4549
4550         if (tp->tg3_flags & TG3_FLAG_NVRAM)
4551                 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
4552 }
4553
4554 static void tg3_dump_state(struct tg3 *tp)
4555 {
4556         int i;
4557         u32 *regs;
4558
4559         regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
4560         if (!regs) {
4561                 netdev_err(tp->dev, "Failed allocating register dump buffer\n");
4562                 return;
4563         }
4564
4565         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4566                 /* Read up to but not including private PCI registers */
4567                 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
4568                         regs[i / sizeof(u32)] = tr32(i);
4569         } else
4570                 tg3_dump_legacy_regs(tp, regs);
4571
4572         for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
4573                 if (!regs[i + 0] && !regs[i + 1] &&
4574                     !regs[i + 2] && !regs[i + 3])
4575                         continue;
4576
4577                 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
4578                            i * 4,
4579                            regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
4580         }
4581
4582         kfree(regs);
4583
4584         for (i = 0; i < tp->irq_cnt; i++) {
4585                 struct tg3_napi *tnapi = &tp->napi[i];
4586
4587                 /* SW status block */
4588                 netdev_err(tp->dev,
4589                          "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
4590                            i,
4591                            tnapi->hw_status->status,
4592                            tnapi->hw_status->status_tag,
4593                            tnapi->hw_status->rx_jumbo_consumer,
4594                            tnapi->hw_status->rx_consumer,
4595                            tnapi->hw_status->rx_mini_consumer,
4596                            tnapi->hw_status->idx[0].rx_producer,
4597                            tnapi->hw_status->idx[0].tx_consumer);
4598
4599                 netdev_err(tp->dev,
4600                 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
4601                            i,
4602                            tnapi->last_tag, tnapi->last_irq_tag,
4603                            tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
4604                            tnapi->rx_rcb_ptr,
4605                            tnapi->prodring.rx_std_prod_idx,
4606                            tnapi->prodring.rx_std_cons_idx,
4607                            tnapi->prodring.rx_jmb_prod_idx,
4608                            tnapi->prodring.rx_jmb_cons_idx);
4609         }
4610 }
4611
4612 /* This is called whenever we suspect that the system chipset is re-
4613  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4614  * is bogus tx completions. We try to recover by setting the
4615  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4616  * in the workqueue.
4617  */
4618 static void tg3_tx_recover(struct tg3 *tp)
4619 {
4620         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4621                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4622
4623         netdev_warn(tp->dev,
4624                     "The system may be re-ordering memory-mapped I/O "
4625                     "cycles to the network device, attempting to recover. "
4626                     "Please report the problem to the driver maintainer "
4627                     "and include system chipset information.\n");
4628
4629         spin_lock(&tp->lock);
4630         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4631         spin_unlock(&tp->lock);
4632 }
4633
4634 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4635 {
4636         /* Tell compiler to fetch tx indices from memory. */
4637         barrier();
4638         return tnapi->tx_pending -
4639                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4640 }
4641
4642 /* Tigon3 never reports partial packet sends.  So we do not
4643  * need special logic to handle SKBs that have not had all
4644  * of their frags sent yet, like SunGEM does.
4645  */
4646 static void tg3_tx(struct tg3_napi *tnapi)
4647 {
4648         struct tg3 *tp = tnapi->tp;
4649         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4650         u32 sw_idx = tnapi->tx_cons;
4651         struct netdev_queue *txq;
4652         int index = tnapi - tp->napi;
4653
4654         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4655                 index--;
4656
4657         txq = netdev_get_tx_queue(tp->dev, index);
4658
4659         while (sw_idx != hw_idx) {
4660                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4661                 struct sk_buff *skb = ri->skb;
4662                 int i, tx_bug = 0;
4663
4664                 if (unlikely(skb == NULL)) {
4665                         tg3_tx_recover(tp);
4666                         return;
4667                 }
4668
4669                 pci_unmap_single(tp->pdev,
4670                                  dma_unmap_addr(ri, mapping),
4671                                  skb_headlen(skb),
4672                                  PCI_DMA_TODEVICE);
4673
4674                 ri->skb = NULL;
4675
4676                 sw_idx = NEXT_TX(sw_idx);
4677
4678                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4679                         ri = &tnapi->tx_buffers[sw_idx];
4680                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4681                                 tx_bug = 1;
4682
4683                         pci_unmap_page(tp->pdev,
4684                                        dma_unmap_addr(ri, mapping),
4685                                        skb_shinfo(skb)->frags[i].size,
4686                                        PCI_DMA_TODEVICE);
4687                         sw_idx = NEXT_TX(sw_idx);
4688                 }
4689
4690                 dev_kfree_skb(skb);
4691
4692                 if (unlikely(tx_bug)) {
4693                         tg3_tx_recover(tp);
4694                         return;
4695                 }
4696         }
4697
4698         tnapi->tx_cons = sw_idx;
4699
4700         /* Need to make the tx_cons update visible to tg3_start_xmit()
4701          * before checking for netif_queue_stopped().  Without the
4702          * memory barrier, there is a small possibility that tg3_start_xmit()
4703          * will miss it and cause the queue to be stopped forever.
4704          */
4705         smp_mb();
4706
4707         if (unlikely(netif_tx_queue_stopped(txq) &&
4708                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4709                 __netif_tx_lock(txq, smp_processor_id());
4710                 if (netif_tx_queue_stopped(txq) &&
4711                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4712                         netif_tx_wake_queue(txq);
4713                 __netif_tx_unlock(txq);
4714         }
4715 }
4716
4717 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4718 {
4719         if (!ri->skb)
4720                 return;
4721
4722         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4723                          map_sz, PCI_DMA_FROMDEVICE);
4724         dev_kfree_skb_any(ri->skb);
4725         ri->skb = NULL;
4726 }
4727
4728 /* Returns size of skb allocated or < 0 on error.
4729  *
4730  * We only need to fill in the address because the other members
4731  * of the RX descriptor are invariant, see tg3_init_rings.
4732  *
4733  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4734  * posting buffers we only dirty the first cache line of the RX
4735  * descriptor (containing the address).  Whereas for the RX status
4736  * buffers the cpu only reads the last cacheline of the RX descriptor
4737  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4738  */
4739 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4740                             u32 opaque_key, u32 dest_idx_unmasked)
4741 {
4742         struct tg3_rx_buffer_desc *desc;
4743         struct ring_info *map;
4744         struct sk_buff *skb;
4745         dma_addr_t mapping;
4746         int skb_size, dest_idx;
4747
4748         switch (opaque_key) {
4749         case RXD_OPAQUE_RING_STD:
4750                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4751                 desc = &tpr->rx_std[dest_idx];
4752                 map = &tpr->rx_std_buffers[dest_idx];
4753                 skb_size = tp->rx_pkt_map_sz;
4754                 break;
4755
4756         case RXD_OPAQUE_RING_JUMBO:
4757                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4758                 desc = &tpr->rx_jmb[dest_idx].std;
4759                 map = &tpr->rx_jmb_buffers[dest_idx];
4760                 skb_size = TG3_RX_JMB_MAP_SZ;
4761                 break;
4762
4763         default:
4764                 return -EINVAL;
4765         }
4766
4767         /* Do not overwrite any of the map or rp information
4768          * until we are sure we can commit to a new buffer.
4769          *
4770          * Callers depend upon this behavior and assume that
4771          * we leave everything unchanged if we fail.
4772          */
4773         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4774         if (skb == NULL)
4775                 return -ENOMEM;
4776
4777         skb_reserve(skb, tp->rx_offset);
4778
4779         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4780                                  PCI_DMA_FROMDEVICE);
4781         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4782                 dev_kfree_skb(skb);
4783                 return -EIO;
4784         }
4785
4786         map->skb = skb;
4787         dma_unmap_addr_set(map, mapping, mapping);
4788
4789         desc->addr_hi = ((u64)mapping >> 32);
4790         desc->addr_lo = ((u64)mapping & 0xffffffff);
4791
4792         return skb_size;
4793 }
4794
4795 /* We only need to move over in the address because the other
4796  * members of the RX descriptor are invariant.  See notes above
4797  * tg3_alloc_rx_skb for full details.
4798  */
4799 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4800                            struct tg3_rx_prodring_set *dpr,
4801                            u32 opaque_key, int src_idx,
4802                            u32 dest_idx_unmasked)
4803 {
4804         struct tg3 *tp = tnapi->tp;
4805         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4806         struct ring_info *src_map, *dest_map;
4807         struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
4808         int dest_idx;
4809
4810         switch (opaque_key) {
4811         case RXD_OPAQUE_RING_STD:
4812                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4813                 dest_desc = &dpr->rx_std[dest_idx];
4814                 dest_map = &dpr->rx_std_buffers[dest_idx];
4815                 src_desc = &spr->rx_std[src_idx];
4816                 src_map = &spr->rx_std_buffers[src_idx];
4817                 break;
4818
4819         case RXD_OPAQUE_RING_JUMBO:
4820                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4821                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4822                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4823                 src_desc = &spr->rx_jmb[src_idx].std;
4824                 src_map = &spr->rx_jmb_buffers[src_idx];
4825                 break;
4826
4827         default:
4828                 return;
4829         }
4830
4831         dest_map->skb = src_map->skb;
4832         dma_unmap_addr_set(dest_map, mapping,
4833                            dma_unmap_addr(src_map, mapping));
4834         dest_desc->addr_hi = src_desc->addr_hi;
4835         dest_desc->addr_lo = src_desc->addr_lo;
4836
4837         /* Ensure that the update to the skb happens after the physical
4838          * addresses have been transferred to the new BD location.
4839          */
4840         smp_wmb();
4841
4842         src_map->skb = NULL;
4843 }
4844
4845 /* The RX ring scheme is composed of multiple rings which post fresh
4846  * buffers to the chip, and one special ring the chip uses to report
4847  * status back to the host.
4848  *
4849  * The special ring reports the status of received packets to the
4850  * host.  The chip does not write into the original descriptor the
4851  * RX buffer was obtained from.  The chip simply takes the original
4852  * descriptor as provided by the host, updates the status and length
4853  * field, then writes this into the next status ring entry.
4854  *
4855  * Each ring the host uses to post buffers to the chip is described
4856  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4857  * it is first placed into the on-chip ram.  When the packet's length
4858  * is known, it walks down the TG3_BDINFO entries to select the ring.
4859  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4860  * which is within the range of the new packet's length is chosen.
4861  *
4862  * The "separate ring for rx status" scheme may sound queer, but it makes
4863  * sense from a cache coherency perspective.  If only the host writes
4864  * to the buffer post rings, and only the chip writes to the rx status
4865  * rings, then cache lines never move beyond shared-modified state.
4866  * If both the host and chip were to write into the same ring, cache line
4867  * eviction could occur since both entities want it in an exclusive state.
4868  */
4869 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4870 {
4871         struct tg3 *tp = tnapi->tp;
4872         u32 work_mask, rx_std_posted = 0;
4873         u32 std_prod_idx, jmb_prod_idx;
4874         u32 sw_idx = tnapi->rx_rcb_ptr;
4875         u16 hw_idx;
4876         int received;
4877         struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
4878
4879         hw_idx = *(tnapi->rx_rcb_prod_idx);
4880         /*
4881          * We need to order the read of hw_idx and the read of
4882          * the opaque cookie.
4883          */
4884         rmb();
4885         work_mask = 0;
4886         received = 0;
4887         std_prod_idx = tpr->rx_std_prod_idx;
4888         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4889         while (sw_idx != hw_idx && budget > 0) {
4890                 struct ring_info *ri;
4891                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4892                 unsigned int len;
4893                 struct sk_buff *skb;
4894                 dma_addr_t dma_addr;
4895                 u32 opaque_key, desc_idx, *post_ptr;
4896
4897                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4898                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4899                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4900                         ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4901                         dma_addr = dma_unmap_addr(ri, mapping);
4902                         skb = ri->skb;
4903                         post_ptr = &std_prod_idx;
4904                         rx_std_posted++;
4905                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4906                         ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4907                         dma_addr = dma_unmap_addr(ri, mapping);
4908                         skb = ri->skb;
4909                         post_ptr = &jmb_prod_idx;
4910                 } else
4911                         goto next_pkt_nopost;
4912
4913                 work_mask |= opaque_key;
4914
4915                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4916                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4917                 drop_it:
4918                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4919                                        desc_idx, *post_ptr);
4920                 drop_it_no_recycle:
4921                         /* Other statistics kept track of by card. */
4922                         tp->rx_dropped++;
4923                         goto next_pkt;
4924                 }
4925
4926                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4927                       ETH_FCS_LEN;
4928
4929                 if (len > TG3_RX_COPY_THRESH(tp)) {
4930                         int skb_size;
4931
4932                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4933                                                     *post_ptr);
4934                         if (skb_size < 0)
4935                                 goto drop_it;
4936
4937                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4938                                          PCI_DMA_FROMDEVICE);
4939
4940                         /* Ensure that the update to the skb happens
4941                          * after the usage of the old DMA mapping.
4942                          */
4943                         smp_wmb();
4944
4945                         ri->skb = NULL;
4946
4947                         skb_put(skb, len);
4948                 } else {
4949                         struct sk_buff *copy_skb;
4950
4951                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4952                                        desc_idx, *post_ptr);
4953
4954                         copy_skb = netdev_alloc_skb(tp->dev, len +
4955                                                     TG3_RAW_IP_ALIGN);
4956                         if (copy_skb == NULL)
4957                                 goto drop_it_no_recycle;
4958
4959                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4960                         skb_put(copy_skb, len);
4961                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4962                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4963                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4964
4965                         /* We'll reuse the original ring buffer. */
4966                         skb = copy_skb;
4967                 }
4968
4969                 if ((tp->dev->features & NETIF_F_RXCSUM) &&
4970                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4971                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4972                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4973                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4974                 else
4975                         skb_checksum_none_assert(skb);
4976
4977                 skb->protocol = eth_type_trans(skb, tp->dev);
4978
4979                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4980                     skb->protocol != htons(ETH_P_8021Q)) {
4981                         dev_kfree_skb(skb);
4982                         goto drop_it_no_recycle;
4983                 }
4984
4985                 if (desc->type_flags & RXD_FLAG_VLAN &&
4986                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
4987                         __vlan_hwaccel_put_tag(skb,
4988                                                desc->err_vlan & RXD_VLAN_MASK);
4989
4990                 napi_gro_receive(&tnapi->napi, skb);
4991
4992                 received++;
4993                 budget--;
4994
4995 next_pkt:
4996                 (*post_ptr)++;
4997
4998                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4999                         tpr->rx_std_prod_idx = std_prod_idx &
5000                                                tp->rx_std_ring_mask;
5001                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5002                                      tpr->rx_std_prod_idx);
5003                         work_mask &= ~RXD_OPAQUE_RING_STD;
5004                         rx_std_posted = 0;
5005                 }
5006 next_pkt_nopost:
5007                 sw_idx++;
5008                 sw_idx &= tp->rx_ret_ring_mask;
5009
5010                 /* Refresh hw_idx to see if there is new work */
5011                 if (sw_idx == hw_idx) {
5012                         hw_idx = *(tnapi->rx_rcb_prod_idx);
5013                         rmb();
5014                 }
5015         }
5016
5017         /* ACK the status ring. */
5018         tnapi->rx_rcb_ptr = sw_idx;
5019         tw32_rx_mbox(tnapi->consmbox, sw_idx);
5020
5021         /* Refill RX ring(s). */
5022         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
5023                 if (work_mask & RXD_OPAQUE_RING_STD) {
5024                         tpr->rx_std_prod_idx = std_prod_idx &
5025                                                tp->rx_std_ring_mask;
5026                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5027                                      tpr->rx_std_prod_idx);
5028                 }
5029                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
5030                         tpr->rx_jmb_prod_idx = jmb_prod_idx &
5031                                                tp->rx_jmb_ring_mask;
5032                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5033                                      tpr->rx_jmb_prod_idx);
5034                 }
5035                 mmiowb();
5036         } else if (work_mask) {
5037                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
5038                  * updated before the producer indices can be updated.
5039                  */
5040                 smp_wmb();
5041
5042                 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
5043                 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
5044
5045                 if (tnapi != &tp->napi[1])
5046                         napi_schedule(&tp->napi[1].napi);
5047         }
5048
5049         return received;
5050 }
5051
5052 static void tg3_poll_link(struct tg3 *tp)
5053 {
5054         /* handle link change and other phy events */
5055         if (!(tp->tg3_flags &
5056               (TG3_FLAG_USE_LINKCHG_REG |
5057                TG3_FLAG_POLL_SERDES))) {
5058                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
5059
5060                 if (sblk->status & SD_STATUS_LINK_CHG) {
5061                         sblk->status = SD_STATUS_UPDATED |
5062                                        (sblk->status & ~SD_STATUS_LINK_CHG);
5063                         spin_lock(&tp->lock);
5064                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
5065                                 tw32_f(MAC_STATUS,
5066                                      (MAC_STATUS_SYNC_CHANGED |
5067                                       MAC_STATUS_CFG_CHANGED |
5068                                       MAC_STATUS_MI_COMPLETION |
5069                                       MAC_STATUS_LNKSTATE_CHANGED));
5070                                 udelay(40);
5071                         } else
5072                                 tg3_setup_phy(tp, 0);
5073                         spin_unlock(&tp->lock);
5074                 }
5075         }
5076 }
5077
5078 static int tg3_rx_prodring_xfer(struct tg3 *tp,
5079                                 struct tg3_rx_prodring_set *dpr,
5080                                 struct tg3_rx_prodring_set *spr)
5081 {
5082         u32 si, di, cpycnt, src_prod_idx;
5083         int i, err = 0;
5084
5085         while (1) {
5086                 src_prod_idx = spr->rx_std_prod_idx;
5087
5088                 /* Make sure updates to the rx_std_buffers[] entries and the
5089                  * standard producer index are seen in the correct order.
5090                  */
5091                 smp_rmb();
5092
5093                 if (spr->rx_std_cons_idx == src_prod_idx)
5094                         break;
5095
5096                 if (spr->rx_std_cons_idx < src_prod_idx)
5097                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
5098                 else
5099                         cpycnt = tp->rx_std_ring_mask + 1 -
5100                                  spr->rx_std_cons_idx;
5101
5102                 cpycnt = min(cpycnt,
5103                              tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
5104
5105                 si = spr->rx_std_cons_idx;
5106                 di = dpr->rx_std_prod_idx;
5107
5108                 for (i = di; i < di + cpycnt; i++) {
5109                         if (dpr->rx_std_buffers[i].skb) {
5110                                 cpycnt = i - di;
5111                                 err = -ENOSPC;
5112                                 break;
5113                         }
5114                 }
5115
5116                 if (!cpycnt)
5117                         break;
5118
5119                 /* Ensure that updates to the rx_std_buffers ring and the
5120                  * shadowed hardware producer ring from tg3_recycle_skb() are
5121                  * ordered correctly WRT the skb check above.
5122                  */
5123                 smp_rmb();
5124
5125                 memcpy(&dpr->rx_std_buffers[di],
5126                        &spr->rx_std_buffers[si],
5127                        cpycnt * sizeof(struct ring_info));
5128
5129                 for (i = 0; i < cpycnt; i++, di++, si++) {
5130                         struct tg3_rx_buffer_desc *sbd, *dbd;
5131                         sbd = &spr->rx_std[si];
5132                         dbd = &dpr->rx_std[di];
5133                         dbd->addr_hi = sbd->addr_hi;
5134                         dbd->addr_lo = sbd->addr_lo;
5135                 }
5136
5137                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
5138                                        tp->rx_std_ring_mask;
5139                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
5140                                        tp->rx_std_ring_mask;
5141         }
5142
5143         while (1) {
5144                 src_prod_idx = spr->rx_jmb_prod_idx;
5145
5146                 /* Make sure updates to the rx_jmb_buffers[] entries and
5147                  * the jumbo producer index are seen in the correct order.
5148                  */
5149                 smp_rmb();
5150
5151                 if (spr->rx_jmb_cons_idx == src_prod_idx)
5152                         break;
5153
5154                 if (spr->rx_jmb_cons_idx < src_prod_idx)
5155                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
5156                 else
5157                         cpycnt = tp->rx_jmb_ring_mask + 1 -
5158                                  spr->rx_jmb_cons_idx;
5159
5160                 cpycnt = min(cpycnt,
5161                              tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
5162
5163                 si = spr->rx_jmb_cons_idx;
5164                 di = dpr->rx_jmb_prod_idx;
5165
5166                 for (i = di; i < di + cpycnt; i++) {
5167                         if (dpr->rx_jmb_buffers[i].skb) {
5168                                 cpycnt = i - di;
5169                                 err = -ENOSPC;
5170                                 break;
5171                         }
5172                 }
5173
5174                 if (!cpycnt)
5175                         break;
5176
5177                 /* Ensure that updates to the rx_jmb_buffers ring and the
5178                  * shadowed hardware producer ring from tg3_recycle_skb() are
5179                  * ordered correctly WRT the skb check above.
5180                  */
5181                 smp_rmb();
5182
5183                 memcpy(&dpr->rx_jmb_buffers[di],
5184                        &spr->rx_jmb_buffers[si],
5185                        cpycnt * sizeof(struct ring_info));
5186
5187                 for (i = 0; i < cpycnt; i++, di++, si++) {
5188                         struct tg3_rx_buffer_desc *sbd, *dbd;
5189                         sbd = &spr->rx_jmb[si].std;
5190                         dbd = &dpr->rx_jmb[di].std;
5191                         dbd->addr_hi = sbd->addr_hi;
5192                         dbd->addr_lo = sbd->addr_lo;
5193                 }
5194
5195                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
5196                                        tp->rx_jmb_ring_mask;
5197                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
5198                                        tp->rx_jmb_ring_mask;
5199         }
5200
5201         return err;
5202 }
5203
5204 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
5205 {
5206         struct tg3 *tp = tnapi->tp;
5207
5208         /* run TX completion thread */
5209         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
5210                 tg3_tx(tnapi);
5211                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5212                         return work_done;
5213         }
5214
5215         /* run RX thread, within the bounds set by NAPI.
5216          * All RX "locking" is done by ensuring outside
5217          * code synchronizes with tg3->napi.poll()
5218          */
5219         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
5220                 work_done += tg3_rx(tnapi, budget - work_done);
5221
5222         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
5223                 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
5224                 int i, err = 0;
5225                 u32 std_prod_idx = dpr->rx_std_prod_idx;
5226                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
5227
5228                 for (i = 1; i < tp->irq_cnt; i++)
5229                         err |= tg3_rx_prodring_xfer(tp, dpr,
5230                                                     &tp->napi[i].prodring);
5231
5232                 wmb();
5233
5234                 if (std_prod_idx != dpr->rx_std_prod_idx)
5235                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5236                                      dpr->rx_std_prod_idx);
5237
5238                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5239                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5240                                      dpr->rx_jmb_prod_idx);
5241
5242                 mmiowb();
5243
5244                 if (err)
5245                         tw32_f(HOSTCC_MODE, tp->coal_now);
5246         }
5247
5248         return work_done;
5249 }
5250
5251 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5252 {
5253         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5254         struct tg3 *tp = tnapi->tp;
5255         int work_done = 0;
5256         struct tg3_hw_status *sblk = tnapi->hw_status;
5257
5258         while (1) {
5259                 work_done = tg3_poll_work(tnapi, work_done, budget);
5260
5261                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5262                         goto tx_recovery;
5263
5264                 if (unlikely(work_done >= budget))
5265                         break;
5266
5267                 /* tp->last_tag is used in tg3_int_reenable() below
5268                  * to tell the hw how much work has been processed,
5269                  * so we must read it before checking for more work.
5270                  */
5271                 tnapi->last_tag = sblk->status_tag;
5272                 tnapi->last_irq_tag = tnapi->last_tag;
5273                 rmb();
5274
5275                 /* check for RX/TX work to do */
5276                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5277                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5278                         napi_complete(napi);
5279                         /* Reenable interrupts. */
5280                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5281                         mmiowb();
5282                         break;
5283                 }
5284         }
5285
5286         return work_done;
5287
5288 tx_recovery:
5289         /* work_done is guaranteed to be less than budget. */
5290         napi_complete(napi);
5291         schedule_work(&tp->reset_task);
5292         return work_done;
5293 }
5294
5295 static void tg3_process_error(struct tg3 *tp)
5296 {
5297         u32 val;
5298         bool real_error = false;
5299
5300         if (tp->tg3_flags & TG3_FLAG_ERROR_PROCESSED)
5301                 return;
5302
5303         /* Check Flow Attention register */
5304         val = tr32(HOSTCC_FLOW_ATTN);
5305         if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
5306                 netdev_err(tp->dev, "FLOW Attention error.  Resetting chip.\n");
5307                 real_error = true;
5308         }
5309
5310         if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
5311                 netdev_err(tp->dev, "MSI Status error.  Resetting chip.\n");
5312                 real_error = true;
5313         }
5314
5315         if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
5316                 netdev_err(tp->dev, "DMA Status error.  Resetting chip.\n");
5317                 real_error = true;
5318         }
5319
5320         if (!real_error)
5321                 return;
5322
5323         tg3_dump_state(tp);
5324
5325         tp->tg3_flags |= TG3_FLAG_ERROR_PROCESSED;
5326         schedule_work(&tp->reset_task);
5327 }
5328
5329 static int tg3_poll(struct napi_struct *napi, int budget)
5330 {
5331         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5332         struct tg3 *tp = tnapi->tp;
5333         int work_done = 0;
5334         struct tg3_hw_status *sblk = tnapi->hw_status;
5335
5336         while (1) {
5337                 if (sblk->status & SD_STATUS_ERROR)
5338                         tg3_process_error(tp);
5339
5340                 tg3_poll_link(tp);
5341
5342                 work_done = tg3_poll_work(tnapi, work_done, budget);
5343
5344                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5345                         goto tx_recovery;
5346
5347                 if (unlikely(work_done >= budget))
5348                         break;
5349
5350                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5351                         /* tp->last_tag is used in tg3_int_reenable() below
5352                          * to tell the hw how much work has been processed,
5353                          * so we must read it before checking for more work.
5354                          */
5355                         tnapi->last_tag = sblk->status_tag;
5356                         tnapi->last_irq_tag = tnapi->last_tag;
5357                         rmb();
5358                 } else
5359                         sblk->status &= ~SD_STATUS_UPDATED;
5360
5361                 if (likely(!tg3_has_work(tnapi))) {
5362                         napi_complete(napi);
5363                         tg3_int_reenable(tnapi);
5364                         break;
5365                 }
5366         }
5367
5368         return work_done;
5369
5370 tx_recovery:
5371         /* work_done is guaranteed to be less than budget. */
5372         napi_complete(napi);
5373         schedule_work(&tp->reset_task);
5374         return work_done;
5375 }
5376
5377 static void tg3_napi_disable(struct tg3 *tp)
5378 {
5379         int i;
5380
5381         for (i = tp->irq_cnt - 1; i >= 0; i--)
5382                 napi_disable(&tp->napi[i].napi);
5383 }
5384
5385 static void tg3_napi_enable(struct tg3 *tp)
5386 {
5387         int i;
5388
5389         for (i = 0; i < tp->irq_cnt; i++)
5390                 napi_enable(&tp->napi[i].napi);
5391 }
5392
5393 static void tg3_napi_init(struct tg3 *tp)
5394 {
5395         int i;
5396
5397         netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
5398         for (i = 1; i < tp->irq_cnt; i++)
5399                 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
5400 }
5401
5402 static void tg3_napi_fini(struct tg3 *tp)
5403 {
5404         int i;
5405
5406         for (i = 0; i < tp->irq_cnt; i++)
5407                 netif_napi_del(&tp->napi[i].napi);
5408 }
5409
5410 static inline void tg3_netif_stop(struct tg3 *tp)
5411 {
5412         tp->dev->trans_start = jiffies; /* prevent tx timeout */
5413         tg3_napi_disable(tp);
5414         netif_tx_disable(tp->dev);
5415 }
5416
5417 static inline void tg3_netif_start(struct tg3 *tp)
5418 {
5419         /* NOTE: unconditional netif_tx_wake_all_queues is only
5420          * appropriate so long as all callers are assured to
5421          * have free tx slots (such as after tg3_init_hw)
5422          */
5423         netif_tx_wake_all_queues(tp->dev);
5424
5425         tg3_napi_enable(tp);
5426         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
5427         tg3_enable_ints(tp);
5428 }
5429
5430 static void tg3_irq_quiesce(struct tg3 *tp)
5431 {
5432         int i;
5433
5434         BUG_ON(tp->irq_sync);
5435
5436         tp->irq_sync = 1;
5437         smp_mb();
5438
5439         for (i = 0; i < tp->irq_cnt; i++)
5440                 synchronize_irq(tp->napi[i].irq_vec);
5441 }
5442
5443 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5444  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5445  * with as well.  Most of the time, this is not necessary except when
5446  * shutting down the device.
5447  */
5448 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5449 {
5450         spin_lock_bh(&tp->lock);
5451         if (irq_sync)
5452                 tg3_irq_quiesce(tp);
5453 }
5454
5455 static inline void tg3_full_unlock(struct tg3 *tp)
5456 {
5457         spin_unlock_bh(&tp->lock);
5458 }
5459
5460 /* One-shot MSI handler - Chip automatically disables interrupt
5461  * after sending MSI so driver doesn't have to do it.
5462  */
5463 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5464 {
5465         struct tg3_napi *tnapi = dev_id;
5466         struct tg3 *tp = tnapi->tp;
5467
5468         prefetch(tnapi->hw_status);
5469         if (tnapi->rx_rcb)
5470                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5471
5472         if (likely(!tg3_irq_sync(tp)))
5473                 napi_schedule(&tnapi->napi);
5474
5475         return IRQ_HANDLED;
5476 }
5477
5478 /* MSI ISR - No need to check for interrupt sharing and no need to
5479  * flush status block and interrupt mailbox. PCI ordering rules
5480  * guarantee that MSI will arrive after the status block.
5481  */
5482 static irqreturn_t tg3_msi(int irq, void *dev_id)
5483 {
5484         struct tg3_napi *tnapi = dev_id;
5485         struct tg3 *tp = tnapi->tp;
5486
5487         prefetch(tnapi->hw_status);
5488         if (tnapi->rx_rcb)
5489                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5490         /*
5491          * Writing any value to intr-mbox-0 clears PCI INTA# and
5492          * chip-internal interrupt pending events.
5493          * Writing non-zero to intr-mbox-0 additional tells the
5494          * NIC to stop sending us irqs, engaging "in-intr-handler"
5495          * event coalescing.
5496          */
5497         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5498         if (likely(!tg3_irq_sync(tp)))
5499                 napi_schedule(&tnapi->napi);
5500
5501         return IRQ_RETVAL(1);
5502 }
5503
5504 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5505 {
5506         struct tg3_napi *tnapi = dev_id;
5507         struct tg3 *tp = tnapi->tp;
5508         struct tg3_hw_status *sblk = tnapi->hw_status;
5509         unsigned int handled = 1;
5510
5511         /* In INTx mode, it is possible for the interrupt to arrive at
5512          * the CPU before the status block posted prior to the interrupt.
5513          * Reading the PCI State register will confirm whether the
5514          * interrupt is ours and will flush the status block.
5515          */
5516         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5517                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5518                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5519                         handled = 0;
5520                         goto out;
5521                 }
5522         }
5523
5524         /*
5525          * Writing any value to intr-mbox-0 clears PCI INTA# and
5526          * chip-internal interrupt pending events.
5527          * Writing non-zero to intr-mbox-0 additional tells the
5528          * NIC to stop sending us irqs, engaging "in-intr-handler"
5529          * event coalescing.
5530          *
5531          * Flush the mailbox to de-assert the IRQ immediately to prevent
5532          * spurious interrupts.  The flush impacts performance but
5533          * excessive spurious interrupts can be worse in some cases.
5534          */
5535         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5536         if (tg3_irq_sync(tp))
5537                 goto out;
5538         sblk->status &= ~SD_STATUS_UPDATED;
5539         if (likely(tg3_has_work(tnapi))) {
5540                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5541                 napi_schedule(&tnapi->napi);
5542         } else {
5543                 /* No work, shared interrupt perhaps?  re-enable
5544                  * interrupts, and flush that PCI write
5545                  */
5546                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5547                                0x00000000);
5548         }
5549 out:
5550         return IRQ_RETVAL(handled);
5551 }
5552
5553 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5554 {
5555         struct tg3_napi *tnapi = dev_id;
5556         struct tg3 *tp = tnapi->tp;
5557         struct tg3_hw_status *sblk = tnapi->hw_status;
5558         unsigned int handled = 1;
5559
5560         /* In INTx mode, it is possible for the interrupt to arrive at
5561          * the CPU before the status block posted prior to the interrupt.
5562          * Reading the PCI State register will confirm whether the
5563          * interrupt is ours and will flush the status block.
5564          */
5565         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5566                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5567                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5568                         handled = 0;
5569                         goto out;
5570                 }
5571         }
5572
5573         /*
5574          * writing any value to intr-mbox-0 clears PCI INTA# and
5575          * chip-internal interrupt pending events.
5576          * writing non-zero to intr-mbox-0 additional tells the
5577          * NIC to stop sending us irqs, engaging "in-intr-handler"
5578          * event coalescing.
5579          *
5580          * Flush the mailbox to de-assert the IRQ immediately to prevent
5581          * spurious interrupts.  The flush impacts performance but
5582          * excessive spurious interrupts can be worse in some cases.
5583          */
5584         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5585
5586         /*
5587          * In a shared interrupt configuration, sometimes other devices'
5588          * interrupts will scream.  We record the current status tag here
5589          * so that the above check can report that the screaming interrupts
5590          * are unhandled.  Eventually they will be silenced.
5591          */
5592         tnapi->last_irq_tag = sblk->status_tag;
5593
5594         if (tg3_irq_sync(tp))
5595                 goto out;
5596
5597         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5598
5599         napi_schedule(&tnapi->napi);
5600
5601 out:
5602         return IRQ_RETVAL(handled);
5603 }
5604
5605 /* ISR for interrupt test */
5606 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5607 {
5608         struct tg3_napi *tnapi = dev_id;
5609         struct tg3 *tp = tnapi->tp;
5610         struct tg3_hw_status *sblk = tnapi->hw_status;
5611
5612         if ((sblk->status & SD_STATUS_UPDATED) ||
5613             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5614                 tg3_disable_ints(tp);
5615                 return IRQ_RETVAL(1);
5616         }
5617         return IRQ_RETVAL(0);
5618 }
5619
5620 static int tg3_init_hw(struct tg3 *, int);
5621 static int tg3_halt(struct tg3 *, int, int);
5622
5623 /* Restart hardware after configuration changes, self-test, etc.
5624  * Invoked with tp->lock held.
5625  */
5626 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5627         __releases(tp->lock)
5628         __acquires(tp->lock)
5629 {
5630         int err;
5631
5632         err = tg3_init_hw(tp, reset_phy);
5633         if (err) {
5634                 netdev_err(tp->dev,
5635                            "Failed to re-initialize device, aborting\n");
5636                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5637                 tg3_full_unlock(tp);
5638                 del_timer_sync(&tp->timer);
5639                 tp->irq_sync = 0;
5640                 tg3_napi_enable(tp);
5641                 dev_close(tp->dev);
5642                 tg3_full_lock(tp, 0);
5643         }
5644         return err;
5645 }
5646
5647 #ifdef CONFIG_NET_POLL_CONTROLLER
5648 static void tg3_poll_controller(struct net_device *dev)
5649 {
5650         int i;
5651         struct tg3 *tp = netdev_priv(dev);
5652
5653         for (i = 0; i < tp->irq_cnt; i++)
5654                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5655 }
5656 #endif
5657
5658 static void tg3_reset_task(struct work_struct *work)
5659 {
5660         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5661         int err;
5662         unsigned int restart_timer;
5663
5664         tg3_full_lock(tp, 0);
5665
5666         if (!netif_running(tp->dev)) {
5667                 tg3_full_unlock(tp);
5668                 return;
5669         }
5670
5671         tg3_full_unlock(tp);
5672
5673         tg3_phy_stop(tp);
5674
5675         tg3_netif_stop(tp);
5676
5677         tg3_full_lock(tp, 1);
5678
5679         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5680         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5681
5682         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5683                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5684                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5685                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5686                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5687         }
5688
5689         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5690         err = tg3_init_hw(tp, 1);
5691         if (err)
5692                 goto out;
5693
5694         tg3_netif_start(tp);
5695
5696         if (restart_timer)
5697                 mod_timer(&tp->timer, jiffies + 1);
5698
5699 out:
5700         tg3_full_unlock(tp);
5701
5702         if (!err)
5703                 tg3_phy_start(tp);
5704 }
5705
5706 static void tg3_tx_timeout(struct net_device *dev)
5707 {
5708         struct tg3 *tp = netdev_priv(dev);
5709
5710         if (netif_msg_tx_err(tp)) {
5711                 netdev_err(dev, "transmit timed out, resetting\n");
5712                 tg3_dump_state(tp);
5713         }
5714
5715         schedule_work(&tp->reset_task);
5716 }
5717
5718 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5719 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5720 {
5721         u32 base = (u32) mapping & 0xffffffff;
5722
5723         return (base > 0xffffdcc0) && (base + len + 8 < base);
5724 }
5725
5726 /* Test for DMA addresses > 40-bit */
5727 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5728                                           int len)
5729 {
5730 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5731         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5732                 return ((u64) mapping + len) > DMA_BIT_MASK(40);
5733         return 0;
5734 #else
5735         return 0;
5736 #endif
5737 }
5738
5739 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5740
5741 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5742 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5743                                        struct sk_buff *skb, u32 last_plus_one,
5744                                        u32 *start, u32 base_flags, u32 mss)
5745 {
5746         struct tg3 *tp = tnapi->tp;
5747         struct sk_buff *new_skb;
5748         dma_addr_t new_addr = 0;
5749         u32 entry = *start;
5750         int i, ret = 0;
5751
5752         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5753                 new_skb = skb_copy(skb, GFP_ATOMIC);
5754         else {
5755                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5756
5757                 new_skb = skb_copy_expand(skb,
5758                                           skb_headroom(skb) + more_headroom,
5759                                           skb_tailroom(skb), GFP_ATOMIC);
5760         }
5761
5762         if (!new_skb) {
5763                 ret = -1;
5764         } else {
5765                 /* New SKB is guaranteed to be linear. */
5766                 entry = *start;
5767                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5768                                           PCI_DMA_TODEVICE);
5769                 /* Make sure the mapping succeeded */
5770                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5771                         ret = -1;
5772                         dev_kfree_skb(new_skb);
5773       &nbs