tg3: Fix io failures after chip reset
[linux-2.6.git] / drivers / net / tg3.c
1 /*
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  * Copyright (C) 2005-2011 Broadcom Corporation.
8  *
9  * Firmware is:
10  *      Derived from proprietary unpublished source code,
11  *      Copyright (C) 2000-2003 Broadcom Corporation.
12  *
13  *      Permission is hereby granted for the distribution of this firmware
14  *      data in hexadecimal or equivalent format, provided this copyright
15  *      notice is accompanying it.
16  */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/in.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioport.h>
31 #include <linux/pci.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/skbuff.h>
35 #include <linux/ethtool.h>
36 #include <linux/mdio.h>
37 #include <linux/mii.h>
38 #include <linux/phy.h>
39 #include <linux/brcmphy.h>
40 #include <linux/if_vlan.h>
41 #include <linux/ip.h>
42 #include <linux/tcp.h>
43 #include <linux/workqueue.h>
44 #include <linux/prefetch.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/firmware.h>
47
48 #include <net/checksum.h>
49 #include <net/ip.h>
50
51 #include <asm/system.h>
52 #include <linux/io.h>
53 #include <asm/byteorder.h>
54 #include <linux/uaccess.h>
55
56 #ifdef CONFIG_SPARC
57 #include <asm/idprom.h>
58 #include <asm/prom.h>
59 #endif
60
61 #define BAR_0   0
62 #define BAR_2   2
63
64 #include "tg3.h"
65
66 /* Functions & macros to verify TG3_FLAGS types */
67
68 static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
69 {
70         return test_bit(flag, bits);
71 }
72
73 static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
74 {
75         set_bit(flag, bits);
76 }
77
78 static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
79 {
80         clear_bit(flag, bits);
81 }
82
83 #define tg3_flag(tp, flag)                              \
84         _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
85 #define tg3_flag_set(tp, flag)                          \
86         _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
87 #define tg3_flag_clear(tp, flag)                        \
88         _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
89
90 #define DRV_MODULE_NAME         "tg3"
91 #define TG3_MAJ_NUM                     3
92 #define TG3_MIN_NUM                     119
93 #define DRV_MODULE_VERSION      \
94         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
95 #define DRV_MODULE_RELDATE      "May 18, 2011"
96
97 #define TG3_DEF_MAC_MODE        0
98 #define TG3_DEF_RX_MODE         0
99 #define TG3_DEF_TX_MODE         0
100 #define TG3_DEF_MSG_ENABLE        \
101         (NETIF_MSG_DRV          | \
102          NETIF_MSG_PROBE        | \
103          NETIF_MSG_LINK         | \
104          NETIF_MSG_TIMER        | \
105          NETIF_MSG_IFDOWN       | \
106          NETIF_MSG_IFUP         | \
107          NETIF_MSG_RX_ERR       | \
108          NETIF_MSG_TX_ERR)
109
110 #define TG3_GRC_LCLCTL_PWRSW_DELAY      100
111
112 /* length of time before we decide the hardware is borked,
113  * and dev->tx_timeout() should be called to fix the problem
114  */
115
116 #define TG3_TX_TIMEOUT                  (5 * HZ)
117
118 /* hardware minimum and maximum for a single frame's data payload */
119 #define TG3_MIN_MTU                     60
120 #define TG3_MAX_MTU(tp) \
121         (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
122
123 /* These numbers seem to be hard coded in the NIC firmware somehow.
124  * You can't change the ring sizes, but you can change where you place
125  * them in the NIC onboard memory.
126  */
127 #define TG3_RX_STD_RING_SIZE(tp) \
128         (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
129          TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
130 #define TG3_DEF_RX_RING_PENDING         200
131 #define TG3_RX_JMB_RING_SIZE(tp) \
132         (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
133          TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
134 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
135 #define TG3_RSS_INDIR_TBL_SIZE          128
136
137 /* Do not place this n-ring entries value into the tp struct itself,
138  * we really want to expose these constants to GCC so that modulo et
139  * al.  operations are done with shifts and masks instead of with
140  * hw multiply/modulo instructions.  Another solution would be to
141  * replace things like '% foo' with '& (foo - 1)'.
142  */
143
144 #define TG3_TX_RING_SIZE                512
145 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
146
147 #define TG3_RX_STD_RING_BYTES(tp) \
148         (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
149 #define TG3_RX_JMB_RING_BYTES(tp) \
150         (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
151 #define TG3_RX_RCB_RING_BYTES(tp) \
152         (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
153 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
154                                  TG3_TX_RING_SIZE)
155 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
156
157 #define TG3_DMA_BYTE_ENAB               64
158
159 #define TG3_RX_STD_DMA_SZ               1536
160 #define TG3_RX_JMB_DMA_SZ               9046
161
162 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
163
164 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
165 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
166
167 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
168         (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
169
170 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
171         (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
172
173 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
174  * that are at least dword aligned when used in PCIX mode.  The driver
175  * works around this bug by double copying the packet.  This workaround
176  * is built into the normal double copy length check for efficiency.
177  *
178  * However, the double copy is only necessary on those architectures
179  * where unaligned memory accesses are inefficient.  For those architectures
180  * where unaligned memory accesses incur little penalty, we can reintegrate
181  * the 5701 in the normal rx path.  Doing so saves a device structure
182  * dereference by hardcoding the double copy threshold in place.
183  */
184 #define TG3_RX_COPY_THRESHOLD           256
185 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
186         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
187 #else
188         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
189 #endif
190
191 /* minimum number of free TX descriptors required to wake up TX process */
192 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
193
194 #define TG3_RAW_IP_ALIGN 2
195
196 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
197
198 #define FIRMWARE_TG3            "tigon/tg3.bin"
199 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
200 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
201
202 static char version[] __devinitdata =
203         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
204
205 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
206 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
207 MODULE_LICENSE("GPL");
208 MODULE_VERSION(DRV_MODULE_VERSION);
209 MODULE_FIRMWARE(FIRMWARE_TG3);
210 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
211 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
212
213 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
214 module_param(tg3_debug, int, 0);
215 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
216
217 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
268         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
269         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
270         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
271         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
272         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
273         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
274         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
275         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
276         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
277         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
278         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
279         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
280         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
281         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
282         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
283         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
284         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
285         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
286         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
287         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
288         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
289         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
290         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
291         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
292         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
293         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
294         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
295         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
296         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
297         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
298         {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
299         {}
300 };
301
302 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
303
304 static const struct {
305         const char string[ETH_GSTRING_LEN];
306 } ethtool_stats_keys[] = {
307         { "rx_octets" },
308         { "rx_fragments" },
309         { "rx_ucast_packets" },
310         { "rx_mcast_packets" },
311         { "rx_bcast_packets" },
312         { "rx_fcs_errors" },
313         { "rx_align_errors" },
314         { "rx_xon_pause_rcvd" },
315         { "rx_xoff_pause_rcvd" },
316         { "rx_mac_ctrl_rcvd" },
317         { "rx_xoff_entered" },
318         { "rx_frame_too_long_errors" },
319         { "rx_jabbers" },
320         { "rx_undersize_packets" },
321         { "rx_in_length_errors" },
322         { "rx_out_length_errors" },
323         { "rx_64_or_less_octet_packets" },
324         { "rx_65_to_127_octet_packets" },
325         { "rx_128_to_255_octet_packets" },
326         { "rx_256_to_511_octet_packets" },
327         { "rx_512_to_1023_octet_packets" },
328         { "rx_1024_to_1522_octet_packets" },
329         { "rx_1523_to_2047_octet_packets" },
330         { "rx_2048_to_4095_octet_packets" },
331         { "rx_4096_to_8191_octet_packets" },
332         { "rx_8192_to_9022_octet_packets" },
333
334         { "tx_octets" },
335         { "tx_collisions" },
336
337         { "tx_xon_sent" },
338         { "tx_xoff_sent" },
339         { "tx_flow_control" },
340         { "tx_mac_errors" },
341         { "tx_single_collisions" },
342         { "tx_mult_collisions" },
343         { "tx_deferred" },
344         { "tx_excessive_collisions" },
345         { "tx_late_collisions" },
346         { "tx_collide_2times" },
347         { "tx_collide_3times" },
348         { "tx_collide_4times" },
349         { "tx_collide_5times" },
350         { "tx_collide_6times" },
351         { "tx_collide_7times" },
352         { "tx_collide_8times" },
353         { "tx_collide_9times" },
354         { "tx_collide_10times" },
355         { "tx_collide_11times" },
356         { "tx_collide_12times" },
357         { "tx_collide_13times" },
358         { "tx_collide_14times" },
359         { "tx_collide_15times" },
360         { "tx_ucast_packets" },
361         { "tx_mcast_packets" },
362         { "tx_bcast_packets" },
363         { "tx_carrier_sense_errors" },
364         { "tx_discards" },
365         { "tx_errors" },
366
367         { "dma_writeq_full" },
368         { "dma_write_prioq_full" },
369         { "rxbds_empty" },
370         { "rx_discards" },
371         { "rx_errors" },
372         { "rx_threshold_hit" },
373
374         { "dma_readq_full" },
375         { "dma_read_prioq_full" },
376         { "tx_comp_queue_full" },
377
378         { "ring_set_send_prod_index" },
379         { "ring_status_update" },
380         { "nic_irqs" },
381         { "nic_avoided_irqs" },
382         { "nic_tx_threshold_hit" },
383
384         { "mbuf_lwm_thresh_hit" },
385 };
386
387 #define TG3_NUM_STATS   ARRAY_SIZE(ethtool_stats_keys)
388
389
390 static const struct {
391         const char string[ETH_GSTRING_LEN];
392 } ethtool_test_keys[] = {
393         { "nvram test     (online) " },
394         { "link test      (online) " },
395         { "register test  (offline)" },
396         { "memory test    (offline)" },
397         { "loopback test  (offline)" },
398         { "interrupt test (offline)" },
399 };
400
401 #define TG3_NUM_TEST    ARRAY_SIZE(ethtool_test_keys)
402
403
404 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
405 {
406         writel(val, tp->regs + off);
407 }
408
409 static u32 tg3_read32(struct tg3 *tp, u32 off)
410 {
411         return readl(tp->regs + off);
412 }
413
414 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
415 {
416         writel(val, tp->aperegs + off);
417 }
418
419 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
420 {
421         return readl(tp->aperegs + off);
422 }
423
424 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
425 {
426         unsigned long flags;
427
428         spin_lock_irqsave(&tp->indirect_lock, flags);
429         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
430         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
431         spin_unlock_irqrestore(&tp->indirect_lock, flags);
432 }
433
434 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
435 {
436         writel(val, tp->regs + off);
437         readl(tp->regs + off);
438 }
439
440 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
441 {
442         unsigned long flags;
443         u32 val;
444
445         spin_lock_irqsave(&tp->indirect_lock, flags);
446         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
447         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
448         spin_unlock_irqrestore(&tp->indirect_lock, flags);
449         return val;
450 }
451
452 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
453 {
454         unsigned long flags;
455
456         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
457                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
458                                        TG3_64BIT_REG_LOW, val);
459                 return;
460         }
461         if (off == TG3_RX_STD_PROD_IDX_REG) {
462                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
463                                        TG3_64BIT_REG_LOW, val);
464                 return;
465         }
466
467         spin_lock_irqsave(&tp->indirect_lock, flags);
468         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
469         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
470         spin_unlock_irqrestore(&tp->indirect_lock, flags);
471
472         /* In indirect mode when disabling interrupts, we also need
473          * to clear the interrupt bit in the GRC local ctrl register.
474          */
475         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
476             (val == 0x1)) {
477                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
478                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
479         }
480 }
481
482 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
483 {
484         unsigned long flags;
485         u32 val;
486
487         spin_lock_irqsave(&tp->indirect_lock, flags);
488         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
489         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
490         spin_unlock_irqrestore(&tp->indirect_lock, flags);
491         return val;
492 }
493
494 /* usec_wait specifies the wait time in usec when writing to certain registers
495  * where it is unsafe to read back the register without some delay.
496  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
497  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
498  */
499 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
500 {
501         if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
502                 /* Non-posted methods */
503                 tp->write32(tp, off, val);
504         else {
505                 /* Posted method */
506                 tg3_write32(tp, off, val);
507                 if (usec_wait)
508                         udelay(usec_wait);
509                 tp->read32(tp, off);
510         }
511         /* Wait again after the read for the posted method to guarantee that
512          * the wait time is met.
513          */
514         if (usec_wait)
515                 udelay(usec_wait);
516 }
517
518 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
519 {
520         tp->write32_mbox(tp, off, val);
521         if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
522                 tp->read32_mbox(tp, off);
523 }
524
525 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
526 {
527         void __iomem *mbox = tp->regs + off;
528         writel(val, mbox);
529         if (tg3_flag(tp, TXD_MBOX_HWBUG))
530                 writel(val, mbox);
531         if (tg3_flag(tp, MBOX_WRITE_REORDER))
532                 readl(mbox);
533 }
534
535 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
536 {
537         return readl(tp->regs + off + GRCMBOX_BASE);
538 }
539
540 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
541 {
542         writel(val, tp->regs + off + GRCMBOX_BASE);
543 }
544
545 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
546 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
547 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
548 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
549 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
550
551 #define tw32(reg, val)                  tp->write32(tp, reg, val)
552 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
553 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
554 #define tr32(reg)                       tp->read32(tp, reg)
555
556 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
557 {
558         unsigned long flags;
559
560         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
561             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
562                 return;
563
564         spin_lock_irqsave(&tp->indirect_lock, flags);
565         if (tg3_flag(tp, SRAM_USE_CONFIG)) {
566                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
567                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
568
569                 /* Always leave this as zero. */
570                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
571         } else {
572                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
573                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
574
575                 /* Always leave this as zero. */
576                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
577         }
578         spin_unlock_irqrestore(&tp->indirect_lock, flags);
579 }
580
581 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
582 {
583         unsigned long flags;
584
585         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
586             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
587                 *val = 0;
588                 return;
589         }
590
591         spin_lock_irqsave(&tp->indirect_lock, flags);
592         if (tg3_flag(tp, SRAM_USE_CONFIG)) {
593                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
594                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
595
596                 /* Always leave this as zero. */
597                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
598         } else {
599                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
600                 *val = tr32(TG3PCI_MEM_WIN_DATA);
601
602                 /* Always leave this as zero. */
603                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
604         }
605         spin_unlock_irqrestore(&tp->indirect_lock, flags);
606 }
607
608 static void tg3_ape_lock_init(struct tg3 *tp)
609 {
610         int i;
611         u32 regbase, bit;
612
613         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
614                 regbase = TG3_APE_LOCK_GRANT;
615         else
616                 regbase = TG3_APE_PER_LOCK_GRANT;
617
618         /* Make sure the driver hasn't any stale locks. */
619         for (i = 0; i < 8; i++) {
620                 if (i == TG3_APE_LOCK_GPIO)
621                         continue;
622                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
623         }
624
625         /* Clear the correct bit of the GPIO lock too. */
626         if (!tp->pci_fn)
627                 bit = APE_LOCK_GRANT_DRIVER;
628         else
629                 bit = 1 << tp->pci_fn;
630
631         tg3_ape_write32(tp, regbase + 4 * TG3_APE_LOCK_GPIO, bit);
632 }
633
634 static int tg3_ape_lock(struct tg3 *tp, int locknum)
635 {
636         int i, off;
637         int ret = 0;
638         u32 status, req, gnt, bit;
639
640         if (!tg3_flag(tp, ENABLE_APE))
641                 return 0;
642
643         switch (locknum) {
644         case TG3_APE_LOCK_GPIO:
645                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
646                         return 0;
647         case TG3_APE_LOCK_GRC:
648         case TG3_APE_LOCK_MEM:
649                 break;
650         default:
651                 return -EINVAL;
652         }
653
654         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
655                 req = TG3_APE_LOCK_REQ;
656                 gnt = TG3_APE_LOCK_GRANT;
657         } else {
658                 req = TG3_APE_PER_LOCK_REQ;
659                 gnt = TG3_APE_PER_LOCK_GRANT;
660         }
661
662         off = 4 * locknum;
663
664         if (locknum != TG3_APE_LOCK_GPIO || !tp->pci_fn)
665                 bit = APE_LOCK_REQ_DRIVER;
666         else
667                 bit = 1 << tp->pci_fn;
668
669         tg3_ape_write32(tp, req + off, bit);
670
671         /* Wait for up to 1 millisecond to acquire lock. */
672         for (i = 0; i < 100; i++) {
673                 status = tg3_ape_read32(tp, gnt + off);
674                 if (status == bit)
675                         break;
676                 udelay(10);
677         }
678
679         if (status != bit) {
680                 /* Revoke the lock request. */
681                 tg3_ape_write32(tp, gnt + off, bit);
682                 ret = -EBUSY;
683         }
684
685         return ret;
686 }
687
688 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
689 {
690         u32 gnt, bit;
691
692         if (!tg3_flag(tp, ENABLE_APE))
693                 return;
694
695         switch (locknum) {
696         case TG3_APE_LOCK_GPIO:
697                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
698                         return;
699         case TG3_APE_LOCK_GRC:
700         case TG3_APE_LOCK_MEM:
701                 break;
702         default:
703                 return;
704         }
705
706         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
707                 gnt = TG3_APE_LOCK_GRANT;
708         else
709                 gnt = TG3_APE_PER_LOCK_GRANT;
710
711         if (locknum != TG3_APE_LOCK_GPIO || !tp->pci_fn)
712                 bit = APE_LOCK_GRANT_DRIVER;
713         else
714                 bit = 1 << tp->pci_fn;
715
716         tg3_ape_write32(tp, gnt + 4 * locknum, bit);
717 }
718
719 static void tg3_disable_ints(struct tg3 *tp)
720 {
721         int i;
722
723         tw32(TG3PCI_MISC_HOST_CTRL,
724              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
725         for (i = 0; i < tp->irq_max; i++)
726                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
727 }
728
729 static void tg3_enable_ints(struct tg3 *tp)
730 {
731         int i;
732
733         tp->irq_sync = 0;
734         wmb();
735
736         tw32(TG3PCI_MISC_HOST_CTRL,
737              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
738
739         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
740         for (i = 0; i < tp->irq_cnt; i++) {
741                 struct tg3_napi *tnapi = &tp->napi[i];
742
743                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
744                 if (tg3_flag(tp, 1SHOT_MSI))
745                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
746
747                 tp->coal_now |= tnapi->coal_now;
748         }
749
750         /* Force an initial interrupt */
751         if (!tg3_flag(tp, TAGGED_STATUS) &&
752             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
753                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
754         else
755                 tw32(HOSTCC_MODE, tp->coal_now);
756
757         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
758 }
759
760 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
761 {
762         struct tg3 *tp = tnapi->tp;
763         struct tg3_hw_status *sblk = tnapi->hw_status;
764         unsigned int work_exists = 0;
765
766         /* check for phy events */
767         if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
768                 if (sblk->status & SD_STATUS_LINK_CHG)
769                         work_exists = 1;
770         }
771         /* check for RX/TX work to do */
772         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
773             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
774                 work_exists = 1;
775
776         return work_exists;
777 }
778
779 /* tg3_int_reenable
780  *  similar to tg3_enable_ints, but it accurately determines whether there
781  *  is new work pending and can return without flushing the PIO write
782  *  which reenables interrupts
783  */
784 static void tg3_int_reenable(struct tg3_napi *tnapi)
785 {
786         struct tg3 *tp = tnapi->tp;
787
788         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
789         mmiowb();
790
791         /* When doing tagged status, this work check is unnecessary.
792          * The last_tag we write above tells the chip which piece of
793          * work we've completed.
794          */
795         if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
796                 tw32(HOSTCC_MODE, tp->coalesce_mode |
797                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
798 }
799
800 static void tg3_switch_clocks(struct tg3 *tp)
801 {
802         u32 clock_ctrl;
803         u32 orig_clock_ctrl;
804
805         if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
806                 return;
807
808         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
809
810         orig_clock_ctrl = clock_ctrl;
811         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
812                        CLOCK_CTRL_CLKRUN_OENABLE |
813                        0x1f);
814         tp->pci_clock_ctrl = clock_ctrl;
815
816         if (tg3_flag(tp, 5705_PLUS)) {
817                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
818                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
819                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
820                 }
821         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
822                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
823                             clock_ctrl |
824                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
825                             40);
826                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
827                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
828                             40);
829         }
830         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
831 }
832
833 #define PHY_BUSY_LOOPS  5000
834
835 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
836 {
837         u32 frame_val;
838         unsigned int loops;
839         int ret;
840
841         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
842                 tw32_f(MAC_MI_MODE,
843                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
844                 udelay(80);
845         }
846
847         *val = 0x0;
848
849         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
850                       MI_COM_PHY_ADDR_MASK);
851         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
852                       MI_COM_REG_ADDR_MASK);
853         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
854
855         tw32_f(MAC_MI_COM, frame_val);
856
857         loops = PHY_BUSY_LOOPS;
858         while (loops != 0) {
859                 udelay(10);
860                 frame_val = tr32(MAC_MI_COM);
861
862                 if ((frame_val & MI_COM_BUSY) == 0) {
863                         udelay(5);
864                         frame_val = tr32(MAC_MI_COM);
865                         break;
866                 }
867                 loops -= 1;
868         }
869
870         ret = -EBUSY;
871         if (loops != 0) {
872                 *val = frame_val & MI_COM_DATA_MASK;
873                 ret = 0;
874         }
875
876         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
877                 tw32_f(MAC_MI_MODE, tp->mi_mode);
878                 udelay(80);
879         }
880
881         return ret;
882 }
883
884 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
885 {
886         u32 frame_val;
887         unsigned int loops;
888         int ret;
889
890         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
891             (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
892                 return 0;
893
894         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
895                 tw32_f(MAC_MI_MODE,
896                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
897                 udelay(80);
898         }
899
900         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
901                       MI_COM_PHY_ADDR_MASK);
902         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
903                       MI_COM_REG_ADDR_MASK);
904         frame_val |= (val & MI_COM_DATA_MASK);
905         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
906
907         tw32_f(MAC_MI_COM, frame_val);
908
909         loops = PHY_BUSY_LOOPS;
910         while (loops != 0) {
911                 udelay(10);
912                 frame_val = tr32(MAC_MI_COM);
913                 if ((frame_val & MI_COM_BUSY) == 0) {
914                         udelay(5);
915                         frame_val = tr32(MAC_MI_COM);
916                         break;
917                 }
918                 loops -= 1;
919         }
920
921         ret = -EBUSY;
922         if (loops != 0)
923                 ret = 0;
924
925         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
926                 tw32_f(MAC_MI_MODE, tp->mi_mode);
927                 udelay(80);
928         }
929
930         return ret;
931 }
932
933 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
934 {
935         int err;
936
937         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
938         if (err)
939                 goto done;
940
941         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
942         if (err)
943                 goto done;
944
945         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
946                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
947         if (err)
948                 goto done;
949
950         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
951
952 done:
953         return err;
954 }
955
956 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
957 {
958         int err;
959
960         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
961         if (err)
962                 goto done;
963
964         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
965         if (err)
966                 goto done;
967
968         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
969                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
970         if (err)
971                 goto done;
972
973         err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
974
975 done:
976         return err;
977 }
978
979 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
980 {
981         int err;
982
983         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
984         if (!err)
985                 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
986
987         return err;
988 }
989
990 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
991 {
992         int err;
993
994         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
995         if (!err)
996                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
997
998         return err;
999 }
1000
1001 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1002 {
1003         int err;
1004
1005         err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1006                            (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1007                            MII_TG3_AUXCTL_SHDWSEL_MISC);
1008         if (!err)
1009                 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1010
1011         return err;
1012 }
1013
1014 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1015 {
1016         if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1017                 set |= MII_TG3_AUXCTL_MISC_WREN;
1018
1019         return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1020 }
1021
1022 #define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \
1023         tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
1024                              MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \
1025                              MII_TG3_AUXCTL_ACTL_TX_6DB)
1026
1027 #define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \
1028         tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
1029                              MII_TG3_AUXCTL_ACTL_TX_6DB);
1030
1031 static int tg3_bmcr_reset(struct tg3 *tp)
1032 {
1033         u32 phy_control;
1034         int limit, err;
1035
1036         /* OK, reset it, and poll the BMCR_RESET bit until it
1037          * clears or we time out.
1038          */
1039         phy_control = BMCR_RESET;
1040         err = tg3_writephy(tp, MII_BMCR, phy_control);
1041         if (err != 0)
1042                 return -EBUSY;
1043
1044         limit = 5000;
1045         while (limit--) {
1046                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1047                 if (err != 0)
1048                         return -EBUSY;
1049
1050                 if ((phy_control & BMCR_RESET) == 0) {
1051                         udelay(40);
1052                         break;
1053                 }
1054                 udelay(10);
1055         }
1056         if (limit < 0)
1057                 return -EBUSY;
1058
1059         return 0;
1060 }
1061
1062 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1063 {
1064         struct tg3 *tp = bp->priv;
1065         u32 val;
1066
1067         spin_lock_bh(&tp->lock);
1068
1069         if (tg3_readphy(tp, reg, &val))
1070                 val = -EIO;
1071
1072         spin_unlock_bh(&tp->lock);
1073
1074         return val;
1075 }
1076
1077 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1078 {
1079         struct tg3 *tp = bp->priv;
1080         u32 ret = 0;
1081
1082         spin_lock_bh(&tp->lock);
1083
1084         if (tg3_writephy(tp, reg, val))
1085                 ret = -EIO;
1086
1087         spin_unlock_bh(&tp->lock);
1088
1089         return ret;
1090 }
1091
1092 static int tg3_mdio_reset(struct mii_bus *bp)
1093 {
1094         return 0;
1095 }
1096
1097 static void tg3_mdio_config_5785(struct tg3 *tp)
1098 {
1099         u32 val;
1100         struct phy_device *phydev;
1101
1102         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1103         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1104         case PHY_ID_BCM50610:
1105         case PHY_ID_BCM50610M:
1106                 val = MAC_PHYCFG2_50610_LED_MODES;
1107                 break;
1108         case PHY_ID_BCMAC131:
1109                 val = MAC_PHYCFG2_AC131_LED_MODES;
1110                 break;
1111         case PHY_ID_RTL8211C:
1112                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1113                 break;
1114         case PHY_ID_RTL8201E:
1115                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1116                 break;
1117         default:
1118                 return;
1119         }
1120
1121         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1122                 tw32(MAC_PHYCFG2, val);
1123
1124                 val = tr32(MAC_PHYCFG1);
1125                 val &= ~(MAC_PHYCFG1_RGMII_INT |
1126                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1127                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1128                 tw32(MAC_PHYCFG1, val);
1129
1130                 return;
1131         }
1132
1133         if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
1134                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1135                        MAC_PHYCFG2_FMODE_MASK_MASK |
1136                        MAC_PHYCFG2_GMODE_MASK_MASK |
1137                        MAC_PHYCFG2_ACT_MASK_MASK   |
1138                        MAC_PHYCFG2_QUAL_MASK_MASK |
1139                        MAC_PHYCFG2_INBAND_ENABLE;
1140
1141         tw32(MAC_PHYCFG2, val);
1142
1143         val = tr32(MAC_PHYCFG1);
1144         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1145                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1146         if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1147                 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1148                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1149                 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1150                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1151         }
1152         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1153                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1154         tw32(MAC_PHYCFG1, val);
1155
1156         val = tr32(MAC_EXT_RGMII_MODE);
1157         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1158                  MAC_RGMII_MODE_RX_QUALITY |
1159                  MAC_RGMII_MODE_RX_ACTIVITY |
1160                  MAC_RGMII_MODE_RX_ENG_DET |
1161                  MAC_RGMII_MODE_TX_ENABLE |
1162                  MAC_RGMII_MODE_TX_LOWPWR |
1163                  MAC_RGMII_MODE_TX_RESET);
1164         if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1165                 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1166                         val |= MAC_RGMII_MODE_RX_INT_B |
1167                                MAC_RGMII_MODE_RX_QUALITY |
1168                                MAC_RGMII_MODE_RX_ACTIVITY |
1169                                MAC_RGMII_MODE_RX_ENG_DET;
1170                 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1171                         val |= MAC_RGMII_MODE_TX_ENABLE |
1172                                MAC_RGMII_MODE_TX_LOWPWR |
1173                                MAC_RGMII_MODE_TX_RESET;
1174         }
1175         tw32(MAC_EXT_RGMII_MODE, val);
1176 }
1177
1178 static void tg3_mdio_start(struct tg3 *tp)
1179 {
1180         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1181         tw32_f(MAC_MI_MODE, tp->mi_mode);
1182         udelay(80);
1183
1184         if (tg3_flag(tp, MDIOBUS_INITED) &&
1185             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1186                 tg3_mdio_config_5785(tp);
1187 }
1188
1189 static int tg3_mdio_init(struct tg3 *tp)
1190 {
1191         int i;
1192         u32 reg;
1193         struct phy_device *phydev;
1194
1195         if (tg3_flag(tp, 5717_PLUS)) {
1196                 u32 is_serdes;
1197
1198                 tp->phy_addr = tp->pci_fn + 1;
1199
1200                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1201                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1202                 else
1203                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1204                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1205                 if (is_serdes)
1206                         tp->phy_addr += 7;
1207         } else
1208                 tp->phy_addr = TG3_PHY_MII_ADDR;
1209
1210         tg3_mdio_start(tp);
1211
1212         if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
1213                 return 0;
1214
1215         tp->mdio_bus = mdiobus_alloc();
1216         if (tp->mdio_bus == NULL)
1217                 return -ENOMEM;
1218
1219         tp->mdio_bus->name     = "tg3 mdio bus";
1220         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1221                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1222         tp->mdio_bus->priv     = tp;
1223         tp->mdio_bus->parent   = &tp->pdev->dev;
1224         tp->mdio_bus->read     = &tg3_mdio_read;
1225         tp->mdio_bus->write    = &tg3_mdio_write;
1226         tp->mdio_bus->reset    = &tg3_mdio_reset;
1227         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1228         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1229
1230         for (i = 0; i < PHY_MAX_ADDR; i++)
1231                 tp->mdio_bus->irq[i] = PHY_POLL;
1232
1233         /* The bus registration will look for all the PHYs on the mdio bus.
1234          * Unfortunately, it does not ensure the PHY is powered up before
1235          * accessing the PHY ID registers.  A chip reset is the
1236          * quickest way to bring the device back to an operational state..
1237          */
1238         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1239                 tg3_bmcr_reset(tp);
1240
1241         i = mdiobus_register(tp->mdio_bus);
1242         if (i) {
1243                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1244                 mdiobus_free(tp->mdio_bus);
1245                 return i;
1246         }
1247
1248         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1249
1250         if (!phydev || !phydev->drv) {
1251                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1252                 mdiobus_unregister(tp->mdio_bus);
1253                 mdiobus_free(tp->mdio_bus);
1254                 return -ENODEV;
1255         }
1256
1257         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1258         case PHY_ID_BCM57780:
1259                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1260                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1261                 break;
1262         case PHY_ID_BCM50610:
1263         case PHY_ID_BCM50610M:
1264                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1265                                      PHY_BRCM_RX_REFCLK_UNUSED |
1266                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1267                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1268                 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
1269                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1270                 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1271                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1272                 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1273                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1274                 /* fallthru */
1275         case PHY_ID_RTL8211C:
1276                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1277                 break;
1278         case PHY_ID_RTL8201E:
1279         case PHY_ID_BCMAC131:
1280                 phydev->interface = PHY_INTERFACE_MODE_MII;
1281                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1282                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1283                 break;
1284         }
1285
1286         tg3_flag_set(tp, MDIOBUS_INITED);
1287
1288         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1289                 tg3_mdio_config_5785(tp);
1290
1291         return 0;
1292 }
1293
1294 static void tg3_mdio_fini(struct tg3 *tp)
1295 {
1296         if (tg3_flag(tp, MDIOBUS_INITED)) {
1297                 tg3_flag_clear(tp, MDIOBUS_INITED);
1298                 mdiobus_unregister(tp->mdio_bus);
1299                 mdiobus_free(tp->mdio_bus);
1300         }
1301 }
1302
1303 /* tp->lock is held. */
1304 static inline void tg3_generate_fw_event(struct tg3 *tp)
1305 {
1306         u32 val;
1307
1308         val = tr32(GRC_RX_CPU_EVENT);
1309         val |= GRC_RX_CPU_DRIVER_EVENT;
1310         tw32_f(GRC_RX_CPU_EVENT, val);
1311
1312         tp->last_event_jiffies = jiffies;
1313 }
1314
1315 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1316
1317 /* tp->lock is held. */
1318 static void tg3_wait_for_event_ack(struct tg3 *tp)
1319 {
1320         int i;
1321         unsigned int delay_cnt;
1322         long time_remain;
1323
1324         /* If enough time has passed, no wait is necessary. */
1325         time_remain = (long)(tp->last_event_jiffies + 1 +
1326                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1327                       (long)jiffies;
1328         if (time_remain < 0)
1329                 return;
1330
1331         /* Check if we can shorten the wait time. */
1332         delay_cnt = jiffies_to_usecs(time_remain);
1333         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1334                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1335         delay_cnt = (delay_cnt >> 3) + 1;
1336
1337         for (i = 0; i < delay_cnt; i++) {
1338                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1339                         break;
1340                 udelay(8);
1341         }
1342 }
1343
1344 /* tp->lock is held. */
1345 static void tg3_ump_link_report(struct tg3 *tp)
1346 {
1347         u32 reg;
1348         u32 val;
1349
1350         if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1351                 return;
1352
1353         tg3_wait_for_event_ack(tp);
1354
1355         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1356
1357         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1358
1359         val = 0;
1360         if (!tg3_readphy(tp, MII_BMCR, &reg))
1361                 val = reg << 16;
1362         if (!tg3_readphy(tp, MII_BMSR, &reg))
1363                 val |= (reg & 0xffff);
1364         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1365
1366         val = 0;
1367         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1368                 val = reg << 16;
1369         if (!tg3_readphy(tp, MII_LPA, &reg))
1370                 val |= (reg & 0xffff);
1371         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1372
1373         val = 0;
1374         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1375                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1376                         val = reg << 16;
1377                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1378                         val |= (reg & 0xffff);
1379         }
1380         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1381
1382         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1383                 val = reg << 16;
1384         else
1385                 val = 0;
1386         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1387
1388         tg3_generate_fw_event(tp);
1389 }
1390
1391 static void tg3_link_report(struct tg3 *tp)
1392 {
1393         if (!netif_carrier_ok(tp->dev)) {
1394                 netif_info(tp, link, tp->dev, "Link is down\n");
1395                 tg3_ump_link_report(tp);
1396         } else if (netif_msg_link(tp)) {
1397                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1398                             (tp->link_config.active_speed == SPEED_1000 ?
1399                              1000 :
1400                              (tp->link_config.active_speed == SPEED_100 ?
1401                               100 : 10)),
1402                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1403                              "full" : "half"));
1404
1405                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1406                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1407                             "on" : "off",
1408                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1409                             "on" : "off");
1410
1411                 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1412                         netdev_info(tp->dev, "EEE is %s\n",
1413                                     tp->setlpicnt ? "enabled" : "disabled");
1414
1415                 tg3_ump_link_report(tp);
1416         }
1417 }
1418
1419 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1420 {
1421         u16 miireg;
1422
1423         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1424                 miireg = ADVERTISE_PAUSE_CAP;
1425         else if (flow_ctrl & FLOW_CTRL_TX)
1426                 miireg = ADVERTISE_PAUSE_ASYM;
1427         else if (flow_ctrl & FLOW_CTRL_RX)
1428                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1429         else
1430                 miireg = 0;
1431
1432         return miireg;
1433 }
1434
1435 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1436 {
1437         u16 miireg;
1438
1439         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1440                 miireg = ADVERTISE_1000XPAUSE;
1441         else if (flow_ctrl & FLOW_CTRL_TX)
1442                 miireg = ADVERTISE_1000XPSE_ASYM;
1443         else if (flow_ctrl & FLOW_CTRL_RX)
1444                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1445         else
1446                 miireg = 0;
1447
1448         return miireg;
1449 }
1450
1451 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1452 {
1453         u8 cap = 0;
1454
1455         if (lcladv & ADVERTISE_1000XPAUSE) {
1456                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1457                         if (rmtadv & LPA_1000XPAUSE)
1458                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1459                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1460                                 cap = FLOW_CTRL_RX;
1461                 } else {
1462                         if (rmtadv & LPA_1000XPAUSE)
1463                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1464                 }
1465         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1466                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1467                         cap = FLOW_CTRL_TX;
1468         }
1469
1470         return cap;
1471 }
1472
1473 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1474 {
1475         u8 autoneg;
1476         u8 flowctrl = 0;
1477         u32 old_rx_mode = tp->rx_mode;
1478         u32 old_tx_mode = tp->tx_mode;
1479
1480         if (tg3_flag(tp, USE_PHYLIB))
1481                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1482         else
1483                 autoneg = tp->link_config.autoneg;
1484
1485         if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
1486                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1487                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1488                 else
1489                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1490         } else
1491                 flowctrl = tp->link_config.flowctrl;
1492
1493         tp->link_config.active_flowctrl = flowctrl;
1494
1495         if (flowctrl & FLOW_CTRL_RX)
1496                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1497         else
1498                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1499
1500         if (old_rx_mode != tp->rx_mode)
1501                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1502
1503         if (flowctrl & FLOW_CTRL_TX)
1504                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1505         else
1506                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1507
1508         if (old_tx_mode != tp->tx_mode)
1509                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1510 }
1511
1512 static void tg3_adjust_link(struct net_device *dev)
1513 {
1514         u8 oldflowctrl, linkmesg = 0;
1515         u32 mac_mode, lcl_adv, rmt_adv;
1516         struct tg3 *tp = netdev_priv(dev);
1517         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1518
1519         spin_lock_bh(&tp->lock);
1520
1521         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1522                                     MAC_MODE_HALF_DUPLEX);
1523
1524         oldflowctrl = tp->link_config.active_flowctrl;
1525
1526         if (phydev->link) {
1527                 lcl_adv = 0;
1528                 rmt_adv = 0;
1529
1530                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1531                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1532                 else if (phydev->speed == SPEED_1000 ||
1533                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1534                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1535                 else
1536                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1537
1538                 if (phydev->duplex == DUPLEX_HALF)
1539                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1540                 else {
1541                         lcl_adv = tg3_advert_flowctrl_1000T(
1542                                   tp->link_config.flowctrl);
1543
1544                         if (phydev->pause)
1545                                 rmt_adv = LPA_PAUSE_CAP;
1546                         if (phydev->asym_pause)
1547                                 rmt_adv |= LPA_PAUSE_ASYM;
1548                 }
1549
1550                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1551         } else
1552                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1553
1554         if (mac_mode != tp->mac_mode) {
1555                 tp->mac_mode = mac_mode;
1556                 tw32_f(MAC_MODE, tp->mac_mode);
1557                 udelay(40);
1558         }
1559
1560         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1561                 if (phydev->speed == SPEED_10)
1562                         tw32(MAC_MI_STAT,
1563                              MAC_MI_STAT_10MBPS_MODE |
1564                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1565                 else
1566                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1567         }
1568
1569         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1570                 tw32(MAC_TX_LENGTHS,
1571                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1572                       (6 << TX_LENGTHS_IPG_SHIFT) |
1573                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1574         else
1575                 tw32(MAC_TX_LENGTHS,
1576                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1577                       (6 << TX_LENGTHS_IPG_SHIFT) |
1578                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1579
1580         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1581             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1582             phydev->speed != tp->link_config.active_speed ||
1583             phydev->duplex != tp->link_config.active_duplex ||
1584             oldflowctrl != tp->link_config.active_flowctrl)
1585                 linkmesg = 1;
1586
1587         tp->link_config.active_speed = phydev->speed;
1588         tp->link_config.active_duplex = phydev->duplex;
1589
1590         spin_unlock_bh(&tp->lock);
1591
1592         if (linkmesg)
1593                 tg3_link_report(tp);
1594 }
1595
1596 static int tg3_phy_init(struct tg3 *tp)
1597 {
1598         struct phy_device *phydev;
1599
1600         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1601                 return 0;
1602
1603         /* Bring the PHY back to a known state. */
1604         tg3_bmcr_reset(tp);
1605
1606         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1607
1608         /* Attach the MAC to the PHY. */
1609         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1610                              phydev->dev_flags, phydev->interface);
1611         if (IS_ERR(phydev)) {
1612                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1613                 return PTR_ERR(phydev);
1614         }
1615
1616         /* Mask with MAC supported features. */
1617         switch (phydev->interface) {
1618         case PHY_INTERFACE_MODE_GMII:
1619         case PHY_INTERFACE_MODE_RGMII:
1620                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1621                         phydev->supported &= (PHY_GBIT_FEATURES |
1622                                               SUPPORTED_Pause |
1623                                               SUPPORTED_Asym_Pause);
1624                         break;
1625                 }
1626                 /* fallthru */
1627         case PHY_INTERFACE_MODE_MII:
1628                 phydev->supported &= (PHY_BASIC_FEATURES |
1629                                       SUPPORTED_Pause |
1630                                       SUPPORTED_Asym_Pause);
1631                 break;
1632         default:
1633                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1634                 return -EINVAL;
1635         }
1636
1637         tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1638
1639         phydev->advertising = phydev->supported;
1640
1641         return 0;
1642 }
1643
1644 static void tg3_phy_start(struct tg3 *tp)
1645 {
1646         struct phy_device *phydev;
1647
1648         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1649                 return;
1650
1651         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1652
1653         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1654                 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1655                 phydev->speed = tp->link_config.orig_speed;
1656                 phydev->duplex = tp->link_config.orig_duplex;
1657                 phydev->autoneg = tp->link_config.orig_autoneg;
1658                 phydev->advertising = tp->link_config.orig_advertising;
1659         }
1660
1661         phy_start(phydev);
1662
1663         phy_start_aneg(phydev);
1664 }
1665
1666 static void tg3_phy_stop(struct tg3 *tp)
1667 {
1668         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1669                 return;
1670
1671         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1672 }
1673
1674 static void tg3_phy_fini(struct tg3 *tp)
1675 {
1676         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1677                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1678                 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1679         }
1680 }
1681
1682 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1683 {
1684         u32 phytest;
1685
1686         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1687                 u32 phy;
1688
1689                 tg3_writephy(tp, MII_TG3_FET_TEST,
1690                              phytest | MII_TG3_FET_SHADOW_EN);
1691                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1692                         if (enable)
1693                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1694                         else
1695                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1696                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1697                 }
1698                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1699         }
1700 }
1701
1702 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1703 {
1704         u32 reg;
1705
1706         if (!tg3_flag(tp, 5705_PLUS) ||
1707             (tg3_flag(tp, 5717_PLUS) &&
1708              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1709                 return;
1710
1711         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1712                 tg3_phy_fet_toggle_apd(tp, enable);
1713                 return;
1714         }
1715
1716         reg = MII_TG3_MISC_SHDW_WREN |
1717               MII_TG3_MISC_SHDW_SCR5_SEL |
1718               MII_TG3_MISC_SHDW_SCR5_LPED |
1719               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1720               MII_TG3_MISC_SHDW_SCR5_SDTL |
1721               MII_TG3_MISC_SHDW_SCR5_C125OE;
1722         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1723                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1724
1725         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1726
1727
1728         reg = MII_TG3_MISC_SHDW_WREN |
1729               MII_TG3_MISC_SHDW_APD_SEL |
1730               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1731         if (enable)
1732                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1733
1734         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1735 }
1736
1737 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1738 {
1739         u32 phy;
1740
1741         if (!tg3_flag(tp, 5705_PLUS) ||
1742             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1743                 return;
1744
1745         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1746                 u32 ephy;
1747
1748                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1749                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1750
1751                         tg3_writephy(tp, MII_TG3_FET_TEST,
1752                                      ephy | MII_TG3_FET_SHADOW_EN);
1753                         if (!tg3_readphy(tp, reg, &phy)) {
1754                                 if (enable)
1755                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1756                                 else
1757                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1758                                 tg3_writephy(tp, reg, phy);
1759                         }
1760                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1761                 }
1762         } else {
1763                 int ret;
1764
1765                 ret = tg3_phy_auxctl_read(tp,
1766                                           MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
1767                 if (!ret) {
1768                         if (enable)
1769                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1770                         else
1771                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1772                         tg3_phy_auxctl_write(tp,
1773                                              MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
1774                 }
1775         }
1776 }
1777
1778 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1779 {
1780         int ret;
1781         u32 val;
1782
1783         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1784                 return;
1785
1786         ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
1787         if (!ret)
1788                 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
1789                                      val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
1790 }
1791
1792 static void tg3_phy_apply_otp(struct tg3 *tp)
1793 {
1794         u32 otp, phy;
1795
1796         if (!tp->phy_otp)
1797                 return;
1798
1799         otp = tp->phy_otp;
1800
1801         if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp))
1802                 return;
1803
1804         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1805         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1806         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1807
1808         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1809               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1810         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1811
1812         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1813         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1814         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1815
1816         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1817         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1818
1819         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1820         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1821
1822         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1823               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1824         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1825
1826         TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
1827 }
1828
1829 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
1830 {
1831         u32 val;
1832
1833         if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
1834                 return;
1835
1836         tp->setlpicnt = 0;
1837
1838         if (tp->link_config.autoneg == AUTONEG_ENABLE &&
1839             current_link_up == 1 &&
1840             tp->link_config.active_duplex == DUPLEX_FULL &&
1841             (tp->link_config.active_speed == SPEED_100 ||
1842              tp->link_config.active_speed == SPEED_1000)) {
1843                 u32 eeectl;
1844
1845                 if (tp->link_config.active_speed == SPEED_1000)
1846                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
1847                 else
1848                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
1849
1850                 tw32(TG3_CPMU_EEE_CTRL, eeectl);
1851
1852                 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
1853                                   TG3_CL45_D7_EEERES_STAT, &val);
1854
1855                 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
1856                     val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
1857                         tp->setlpicnt = 2;
1858         }
1859
1860         if (!tp->setlpicnt) {
1861                 val = tr32(TG3_CPMU_EEE_MODE);
1862                 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
1863         }
1864 }
1865
1866 static void tg3_phy_eee_enable(struct tg3 *tp)
1867 {
1868         u32 val;
1869
1870         if (tp->link_config.active_speed == SPEED_1000 &&
1871             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1872              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
1873              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
1874             !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
1875                 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0003);
1876                 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
1877         }
1878
1879         val = tr32(TG3_CPMU_EEE_MODE);
1880         tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
1881 }
1882
1883 static int tg3_wait_macro_done(struct tg3 *tp)
1884 {
1885         int limit = 100;
1886
1887         while (limit--) {
1888                 u32 tmp32;
1889
1890                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1891                         if ((tmp32 & 0x1000) == 0)
1892                                 break;
1893                 }
1894         }
1895         if (limit < 0)
1896                 return -EBUSY;
1897
1898         return 0;
1899 }
1900
1901 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1902 {
1903         static const u32 test_pat[4][6] = {
1904         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1905         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1906         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1907         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1908         };
1909         int chan;
1910
1911         for (chan = 0; chan < 4; chan++) {
1912                 int i;
1913
1914                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1915                              (chan * 0x2000) | 0x0200);
1916                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1917
1918                 for (i = 0; i < 6; i++)
1919                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1920                                      test_pat[chan][i]);
1921
1922                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1923                 if (tg3_wait_macro_done(tp)) {
1924                         *resetp = 1;
1925                         return -EBUSY;
1926                 }
1927
1928                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1929                              (chan * 0x2000) | 0x0200);
1930                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1931                 if (tg3_wait_macro_done(tp)) {
1932                         *resetp = 1;
1933                         return -EBUSY;
1934                 }
1935
1936                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1937                 if (tg3_wait_macro_done(tp)) {
1938                         *resetp = 1;
1939                         return -EBUSY;
1940                 }
1941
1942                 for (i = 0; i < 6; i += 2) {
1943                         u32 low, high;
1944
1945                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1946                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1947                             tg3_wait_macro_done(tp)) {
1948                                 *resetp = 1;
1949                                 return -EBUSY;
1950                         }
1951                         low &= 0x7fff;
1952                         high &= 0x000f;
1953                         if (low != test_pat[chan][i] ||
1954                             high != test_pat[chan][i+1]) {
1955                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1956                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1957                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1958
1959                                 return -EBUSY;
1960                         }
1961                 }
1962         }
1963
1964         return 0;
1965 }
1966
1967 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1968 {
1969         int chan;
1970
1971         for (chan = 0; chan < 4; chan++) {
1972                 int i;
1973
1974                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1975                              (chan * 0x2000) | 0x0200);
1976                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1977                 for (i = 0; i < 6; i++)
1978                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1979                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1980                 if (tg3_wait_macro_done(tp))
1981                         return -EBUSY;
1982         }
1983
1984         return 0;
1985 }
1986
1987 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1988 {
1989         u32 reg32, phy9_orig;
1990         int retries, do_phy_reset, err;
1991
1992         retries = 10;
1993         do_phy_reset = 1;
1994         do {
1995                 if (do_phy_reset) {
1996                         err = tg3_bmcr_reset(tp);
1997                         if (err)
1998                                 return err;
1999                         do_phy_reset = 0;
2000                 }
2001
2002                 /* Disable transmitter and interrupt.  */
2003                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
2004                         continue;
2005
2006                 reg32 |= 0x3000;
2007                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2008
2009                 /* Set full-duplex, 1000 mbps.  */
2010                 tg3_writephy(tp, MII_BMCR,
2011                              BMCR_FULLDPLX | BMCR_SPEED1000);
2012
2013                 /* Set to master mode.  */
2014                 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
2015                         continue;
2016
2017                 tg3_writephy(tp, MII_CTRL1000,
2018                              CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
2019
2020                 err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
2021                 if (err)
2022                         return err;
2023
2024                 /* Block the PHY control access.  */
2025                 tg3_phydsp_write(tp, 0x8005, 0x0800);
2026
2027                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2028                 if (!err)
2029                         break;
2030         } while (--retries);
2031
2032         err = tg3_phy_reset_chanpat(tp);
2033         if (err)
2034                 return err;
2035
2036         tg3_phydsp_write(tp, 0x8005, 0x0000);
2037
2038         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2039         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2040
2041         TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2042
2043         tg3_writephy(tp, MII_CTRL1000, phy9_orig);
2044
2045         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
2046                 reg32 &= ~0x3000;
2047                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2048         } else if (!err)
2049                 err = -EBUSY;
2050
2051         return err;
2052 }
2053
2054 /* This will reset the tigon3 PHY if there is no valid
2055  * link unless the FORCE argument is non-zero.
2056  */
2057 static int tg3_phy_reset(struct tg3 *tp)
2058 {
2059         u32 val, cpmuctrl;
2060         int err;
2061
2062         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2063                 val = tr32(GRC_MISC_CFG);
2064                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2065                 udelay(40);
2066         }
2067         err  = tg3_readphy(tp, MII_BMSR, &val);
2068         err |= tg3_readphy(tp, MII_BMSR, &val);
2069         if (err != 0)
2070                 return -EBUSY;
2071
2072         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
2073                 netif_carrier_off(tp->dev);
2074                 tg3_link_report(tp);
2075         }
2076
2077         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2078             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2079             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2080                 err = tg3_phy_reset_5703_4_5(tp);
2081                 if (err)
2082                         return err;
2083                 goto out;
2084         }
2085
2086         cpmuctrl = 0;
2087         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2088             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2089                 cpmuctrl = tr32(TG3_CPMU_CTRL);
2090                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2091                         tw32(TG3_CPMU_CTRL,
2092                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2093         }
2094
2095         err = tg3_bmcr_reset(tp);
2096         if (err)
2097                 return err;
2098
2099         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2100                 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2101                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2102
2103                 tw32(TG3_CPMU_CTRL, cpmuctrl);
2104         }
2105
2106         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2107             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2108                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2109                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2110                     CPMU_LSPD_1000MB_MACCLK_12_5) {
2111                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2112                         udelay(40);
2113                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2114                 }
2115         }
2116
2117         if (tg3_flag(tp, 5717_PLUS) &&
2118             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2119                 return 0;
2120
2121         tg3_phy_apply_otp(tp);
2122
2123         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2124                 tg3_phy_toggle_apd(tp, true);
2125         else
2126                 tg3_phy_toggle_apd(tp, false);
2127
2128 out:
2129         if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2130             !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2131                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2132                 tg3_phydsp_write(tp, 0x000a, 0x0323);
2133                 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2134         }
2135
2136         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2137                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2138                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2139         }
2140
2141         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2142                 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2143                         tg3_phydsp_write(tp, 0x000a, 0x310b);
2144                         tg3_phydsp_write(tp, 0x201f, 0x9506);
2145                         tg3_phydsp_write(tp, 0x401f, 0x14e2);
2146                         TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2147                 }
2148         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2149                 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2150                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2151                         if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2152                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2153                                 tg3_writephy(tp, MII_TG3_TEST1,
2154                                              MII_TG3_TEST1_TRIM_EN | 0x4);
2155                         } else
2156                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2157
2158                         TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2159                 }
2160         }
2161
2162         /* Set Extended packet length bit (bit 14) on all chips that */
2163         /* support jumbo frames */
2164         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2165                 /* Cannot do read-modify-write on 5401 */
2166                 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2167         } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
2168                 /* Set bit 14 with read-modify-write to preserve other bits */
2169                 err = tg3_phy_auxctl_read(tp,
2170                                           MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2171                 if (!err)
2172                         tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2173                                            val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
2174         }
2175
2176         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2177          * jumbo frames transmission.
2178          */
2179         if (tg3_flag(tp, JUMBO_CAPABLE)) {
2180                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2181                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2182                                      val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2183         }
2184
2185         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2186                 /* adjust output voltage */
2187                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2188         }
2189
2190         tg3_phy_toggle_automdix(tp, 1);
2191         tg3_phy_set_wirespeed(tp);
2192         return 0;
2193 }
2194
2195 #define TG3_GPIO_MSG_DRVR_PRES           0x00000001
2196 #define TG3_GPIO_MSG_NEED_VAUX           0x00000002
2197 #define TG3_GPIO_MSG_MASK                (TG3_GPIO_MSG_DRVR_PRES | \
2198                                           TG3_GPIO_MSG_NEED_VAUX)
2199 #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2200         ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2201          (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2202          (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2203          (TG3_GPIO_MSG_DRVR_PRES << 12))
2204
2205 #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2206         ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2207          (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2208          (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2209          (TG3_GPIO_MSG_NEED_VAUX << 12))
2210
2211 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2212 {
2213         u32 status, shift;
2214
2215         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2216             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
2217                 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2218         else
2219                 status = tr32(TG3_CPMU_DRV_STATUS);
2220
2221         shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2222         status &= ~(TG3_GPIO_MSG_MASK << shift);
2223         status |= (newstat << shift);
2224
2225         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2226             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
2227                 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2228         else
2229                 tw32(TG3_CPMU_DRV_STATUS, status);
2230
2231         return status >> TG3_APE_GPIO_MSG_SHIFT;
2232 }
2233
2234 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2235 {
2236         if (!tg3_flag(tp, IS_NIC))
2237                 return 0;
2238
2239         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2240             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2241             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
2242                 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2243                         return -EIO;
2244
2245                 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2246
2247                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2248                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2249
2250                 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2251         } else {
2252                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2253                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2254         }
2255
2256         return 0;
2257 }
2258
2259 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2260 {
2261         u32 grc_local_ctrl;
2262
2263         if (!tg3_flag(tp, IS_NIC) ||
2264             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2265             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)
2266                 return;
2267
2268         grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2269
2270         tw32_wait_f(GRC_LOCAL_CTRL,
2271                     grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2272                     TG3_GRC_LCLCTL_PWRSW_DELAY);
2273
2274         tw32_wait_f(GRC_LOCAL_CTRL,
2275                     grc_local_ctrl,
2276                     TG3_GRC_LCLCTL_PWRSW_DELAY);
2277
2278         tw32_wait_f(GRC_LOCAL_CTRL,
2279                     grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2280                     TG3_GRC_LCLCTL_PWRSW_DELAY);
2281 }
2282
2283 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2284 {
2285         if (!tg3_flag(tp, IS_NIC))
2286                 return;
2287
2288         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2289             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2290                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2291                             (GRC_LCLCTRL_GPIO_OE0 |
2292                              GRC_LCLCTRL_GPIO_OE1 |
2293                              GRC_LCLCTRL_GPIO_OE2 |
2294                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2295                              GRC_LCLCTRL_GPIO_OUTPUT1),
2296                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2297         } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2298                    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2299                 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2300                 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2301                                      GRC_LCLCTRL_GPIO_OE1 |
2302                                      GRC_LCLCTRL_GPIO_OE2 |
2303                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2304                                      GRC_LCLCTRL_GPIO_OUTPUT1 |
2305                                      tp->grc_local_ctrl;
2306                 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2307                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2308
2309                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2310                 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2311                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2312
2313                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2314                 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2315                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2316         } else {
2317                 u32 no_gpio2;
2318                 u32 grc_local_ctrl = 0;
2319
2320                 /* Workaround to prevent overdrawing Amps. */
2321                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2322                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2323                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2324                                     grc_local_ctrl,
2325                                     TG3_GRC_LCLCTL_PWRSW_DELAY);
2326                 }
2327
2328                 /* On 5753 and variants, GPIO2 cannot be used. */
2329                 no_gpio2 = tp->nic_sram_data_cfg &
2330                            NIC_SRAM_DATA_CFG_NO_GPIO2;
2331
2332                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2333                                   GRC_LCLCTRL_GPIO_OE1 |
2334                                   GRC_LCLCTRL_GPIO_OE2 |
2335                                   GRC_LCLCTRL_GPIO_OUTPUT1 |
2336                                   GRC_LCLCTRL_GPIO_OUTPUT2;
2337                 if (no_gpio2) {
2338                         grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2339                                             GRC_LCLCTRL_GPIO_OUTPUT2);
2340                 }
2341                 tw32_wait_f(GRC_LOCAL_CTRL,
2342                             tp->grc_local_ctrl | grc_local_ctrl,
2343                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2344
2345                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2346
2347                 tw32_wait_f(GRC_LOCAL_CTRL,
2348                             tp->grc_local_ctrl | grc_local_ctrl,
2349                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2350
2351                 if (!no_gpio2) {
2352                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2353                         tw32_wait_f(GRC_LOCAL_CTRL,
2354                                     tp->grc_local_ctrl | grc_local_ctrl,
2355                                     TG3_GRC_LCLCTL_PWRSW_DELAY);
2356                 }
2357         }
2358 }
2359
2360 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
2361 {
2362         u32 msg = 0;
2363
2364         /* Serialize power state transitions */
2365         if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2366                 return;
2367
2368         if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
2369                 msg = TG3_GPIO_MSG_NEED_VAUX;
2370
2371         msg = tg3_set_function_status(tp, msg);
2372
2373         if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2374                 goto done;
2375
2376         if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2377                 tg3_pwrsrc_switch_to_vaux(tp);
2378         else
2379                 tg3_pwrsrc_die_with_vmain(tp);
2380
2381 done:
2382         tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2383 }
2384
2385 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
2386 {
2387         bool need_vaux = false;
2388
2389         /* The GPIOs do something completely different on 57765. */
2390         if (!tg3_flag(tp, IS_NIC) ||
2391             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2392                 return;
2393
2394         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2395             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2396             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
2397                 tg3_frob_aux_power_5717(tp, include_wol ?
2398                                         tg3_flag(tp, WOL_ENABLE) != 0 : 0);
2399                 return;
2400         }
2401
2402         if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
2403                 struct net_device *dev_peer;
2404
2405                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2406
2407                 /* remove_one() may have been run on the peer. */
2408                 if (dev_peer) {
2409                         struct tg3 *tp_peer = netdev_priv(dev_peer);
2410
2411                         if (tg3_flag(tp_peer, INIT_COMPLETE))
2412                                 return;
2413
2414                         if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
2415                             tg3_flag(tp_peer, ENABLE_ASF))
2416                                 need_vaux = true;
2417                 }
2418         }
2419
2420         if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2421             tg3_flag(tp, ENABLE_ASF))
2422                 need_vaux = true;
2423
2424         if (need_vaux)
2425                 tg3_pwrsrc_switch_to_vaux(tp);
2426         else
2427                 tg3_pwrsrc_die_with_vmain(tp);
2428 }
2429
2430 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2431 {
2432         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2433                 return 1;
2434         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2435                 if (speed != SPEED_10)
2436                         return 1;
2437         } else if (speed == SPEED_10)
2438                 return 1;
2439
2440         return 0;
2441 }
2442
2443 static int tg3_setup_phy(struct tg3 *, int);
2444
2445 #define RESET_KIND_SHUTDOWN     0
2446 #define RESET_KIND_INIT         1
2447 #define RESET_KIND_SUSPEND      2
2448
2449 static void tg3_write_sig_post_reset(struct tg3 *, int);
2450 static int tg3_halt_cpu(struct tg3 *, u32);
2451
2452 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2453 {
2454         u32 val;
2455
2456         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2457                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2458                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2459                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2460
2461                         sg_dig_ctrl |=
2462                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2463                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2464                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2465                 }
2466                 return;
2467         }
2468
2469         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2470                 tg3_bmcr_reset(tp);
2471                 val = tr32(GRC_MISC_CFG);
2472                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2473                 udelay(40);
2474                 return;
2475         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2476                 u32 phytest;
2477                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2478                         u32 phy;
2479
2480                         tg3_writephy(tp, MII_ADVERTISE, 0);
2481                         tg3_writephy(tp, MII_BMCR,
2482                                      BMCR_ANENABLE | BMCR_ANRESTART);
2483
2484                         tg3_writephy(tp, MII_TG3_FET_TEST,
2485                                      phytest | MII_TG3_FET_SHADOW_EN);
2486                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2487                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2488                                 tg3_writephy(tp,
2489                                              MII_TG3_FET_SHDW_AUXMODE4,
2490                                              phy);
2491                         }
2492                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2493                 }
2494                 return;
2495         } else if (do_low_power) {
2496                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2497                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2498
2499                 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2500                       MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2501                       MII_TG3_AUXCTL_PCTL_VREG_11V;
2502                 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
2503         }
2504
2505         /* The PHY should not be powered down on some chips because
2506          * of bugs.
2507          */
2508         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2509             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2510             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2511              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2512                 return;
2513
2514         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2515             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2516                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2517                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2518                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2519                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2520         }
2521
2522         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2523 }
2524
2525 /* tp->lock is held. */
2526 static int tg3_nvram_lock(struct tg3 *tp)
2527 {
2528         if (tg3_flag(tp, NVRAM)) {
2529                 int i;
2530
2531                 if (tp->nvram_lock_cnt == 0) {
2532                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2533                         for (i = 0; i < 8000; i++) {
2534                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2535                                         break;
2536                                 udelay(20);
2537                         }
2538                         if (i == 8000) {
2539                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2540                                 return -ENODEV;
2541                         }
2542                 }
2543                 tp->nvram_lock_cnt++;
2544         }
2545         return 0;
2546 }
2547
2548 /* tp->lock is held. */
2549 static void tg3_nvram_unlock(struct tg3 *tp)
2550 {
2551         if (tg3_flag(tp, NVRAM)) {
2552                 if (tp->nvram_lock_cnt > 0)
2553                         tp->nvram_lock_cnt--;
2554                 if (tp->nvram_lock_cnt == 0)
2555                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2556         }
2557 }
2558
2559 /* tp->lock is held. */
2560 static void tg3_enable_nvram_access(struct tg3 *tp)
2561 {
2562         if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
2563                 u32 nvaccess = tr32(NVRAM_ACCESS);
2564
2565                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2566         }
2567 }
2568
2569 /* tp->lock is held. */
2570 static void tg3_disable_nvram_access(struct tg3 *tp)
2571 {
2572         if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
2573                 u32 nvaccess = tr32(NVRAM_ACCESS);
2574
2575                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2576         }
2577 }
2578
2579 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2580                                         u32 offset, u32 *val)
2581 {
2582         u32 tmp;
2583         int i;
2584
2585         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2586                 return -EINVAL;
2587
2588         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2589                                         EEPROM_ADDR_DEVID_MASK |
2590                                         EEPROM_ADDR_READ);
2591         tw32(GRC_EEPROM_ADDR,
2592              tmp |
2593              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2594              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2595               EEPROM_ADDR_ADDR_MASK) |
2596              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2597
2598         for (i = 0; i < 1000; i++) {
2599                 tmp = tr32(GRC_EEPROM_ADDR);
2600
2601                 if (tmp & EEPROM_ADDR_COMPLETE)
2602                         break;
2603                 msleep(1);
2604         }
2605         if (!(tmp & EEPROM_ADDR_COMPLETE))
2606                 return -EBUSY;
2607
2608         tmp = tr32(GRC_EEPROM_DATA);
2609
2610         /*
2611          * The data will always be opposite the native endian
2612          * format.  Perform a blind byteswap to compensate.
2613          */
2614         *val = swab32(tmp);
2615
2616         return 0;
2617 }
2618
2619 #define NVRAM_CMD_TIMEOUT 10000
2620
2621 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2622 {
2623         int i;
2624
2625         tw32(NVRAM_CMD, nvram_cmd);
2626         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2627                 udelay(10);
2628                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2629                         udelay(10);
2630                         break;
2631                 }
2632         }
2633
2634         if (i == NVRAM_CMD_TIMEOUT)
2635                 return -EBUSY;
2636
2637         return 0;
2638 }
2639
2640 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2641 {
2642         if (tg3_flag(tp, NVRAM) &&
2643             tg3_flag(tp, NVRAM_BUFFERED) &&
2644             tg3_flag(tp, FLASH) &&
2645             !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
2646             (tp->nvram_jedecnum == JEDEC_ATMEL))
2647
2648                 addr = ((addr / tp->nvram_pagesize) <<
2649                         ATMEL_AT45DB0X1B_PAGE_POS) +
2650                        (addr % tp->nvram_pagesize);
2651
2652         return addr;
2653 }
2654
2655 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2656 {
2657         if (tg3_flag(tp, NVRAM) &&
2658             tg3_flag(tp, NVRAM_BUFFERED) &&
2659             tg3_flag(tp, FLASH) &&
2660             !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
2661             (tp->nvram_jedecnum == JEDEC_ATMEL))
2662
2663                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2664                         tp->nvram_pagesize) +
2665                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2666
2667         return addr;
2668 }
2669
2670 /* NOTE: Data read in from NVRAM is byteswapped according to
2671  * the byteswapping settings for all other register accesses.
2672  * tg3 devices are BE devices, so on a BE machine, the data
2673  * returned will be exactly as it is seen in NVRAM.  On a LE
2674  * machine, the 32-bit value will be byteswapped.
2675  */
2676 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2677 {
2678         int ret;
2679
2680         if (!tg3_flag(tp, NVRAM))
2681                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2682
2683         offset = tg3_nvram_phys_addr(tp, offset);
2684
2685         if (offset > NVRAM_ADDR_MSK)
2686                 return -EINVAL;
2687
2688         ret = tg3_nvram_lock(tp);
2689         if (ret)
2690                 return ret;
2691
2692         tg3_enable_nvram_access(tp);
2693
2694         tw32(NVRAM_ADDR, offset);
2695         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2696                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2697
2698         if (ret == 0)
2699                 *val = tr32(NVRAM_RDDATA);
2700
2701         tg3_disable_nvram_access(tp);
2702
2703         tg3_nvram_unlock(tp);
2704
2705         return ret;
2706 }
2707
2708 /* Ensures NVRAM data is in bytestream format. */
2709 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2710 {
2711         u32 v;
2712         int res = tg3_nvram_read(tp, offset, &v);
2713         if (!res)
2714                 *val = cpu_to_be32(v);
2715         return res;
2716 }
2717
2718 /* tp->lock is held. */
2719 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2720 {
2721         u32 addr_high, addr_low;
2722         int i;
2723
2724         addr_high = ((tp->dev->dev_addr[0] << 8) |
2725                      tp->dev->dev_addr[1]);
2726         addr_low = ((tp->dev->dev_addr[2] << 24) |
2727                     (tp->dev->dev_addr[3] << 16) |
2728                     (tp->dev->dev_addr[4] <<  8) |
2729                     (tp->dev->dev_addr[5] <<  0));
2730         for (i = 0; i < 4; i++) {
2731                 if (i == 1 && skip_mac_1)
2732                         continue;
2733                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2734                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2735         }
2736
2737         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2738             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2739                 for (i = 0; i < 12; i++) {
2740                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2741                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2742                 }
2743         }
2744
2745         addr_high = (tp->dev->dev_addr[0] +
2746                      tp->dev->dev_addr[1] +
2747                      tp->dev->dev_addr[2] +
2748                      tp->dev->dev_addr[3] +
2749                      tp->dev->dev_addr[4] +
2750                      tp->dev->dev_addr[5]) &
2751                 TX_BACKOFF_SEED_MASK;
2752         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2753 }
2754
2755 static void tg3_enable_register_access(struct tg3 *tp)
2756 {
2757         /*
2758          * Make sure register accesses (indirect or otherwise) will function
2759          * correctly.
2760          */
2761         pci_write_config_dword(tp->pdev,
2762                                TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
2763 }
2764
2765 static int tg3_power_up(struct tg3 *tp)
2766 {
2767         int err;
2768
2769         tg3_enable_register_access(tp);
2770
2771         err = pci_set_power_state(tp->pdev, PCI_D0);
2772         if (!err) {
2773                 /* Switch out of Vaux if it is a NIC */
2774                 tg3_pwrsrc_switch_to_vmain(tp);
2775         } else {
2776                 netdev_err(tp->dev, "Transition to D0 failed\n");
2777         }
2778
2779         return err;
2780 }
2781
2782 static int tg3_power_down_prepare(struct tg3 *tp)
2783 {
2784         u32 misc_host_ctrl;
2785         bool device_should_wake, do_low_power;
2786
2787         tg3_enable_register_access(tp);
2788
2789         /* Restore the CLKREQ setting. */
2790         if (tg3_flag(tp, CLKREQ_BUG)) {
2791                 u16 lnkctl;
2792
2793                 pci_read_config_word(tp->pdev,
2794                                      pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
2795                                      &lnkctl);
2796                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2797                 pci_write_config_word(tp->pdev,
2798                                       pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
2799                                       lnkctl);
2800         }
2801
2802         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2803         tw32(TG3PCI_MISC_HOST_CTRL,
2804              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2805
2806         device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
2807                              tg3_flag(tp, WOL_ENABLE);
2808
2809         if (tg3_flag(tp, USE_PHYLIB)) {
2810                 do_low_power = false;
2811                 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2812                     !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2813                         struct phy_device *phydev;
2814                         u32 phyid, advertising;
2815
2816                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2817
2818                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2819
2820                         tp->link_config.orig_speed = phydev->speed;
2821                         tp->link_config.orig_duplex = phydev->duplex;
2822                         tp->link_config.orig_autoneg = phydev->autoneg;
2823                         tp->link_config.orig_advertising = phydev->advertising;
2824
2825                         advertising = ADVERTISED_TP |
2826                                       ADVERTISED_Pause |
2827                                       ADVERTISED_Autoneg |
2828                                       ADVERTISED_10baseT_Half;
2829
2830                         if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
2831                                 if (tg3_flag(tp, WOL_SPEED_100MB))
2832                                         advertising |=
2833                                                 ADVERTISED_100baseT_Half |
2834                                                 ADVERTISED_100baseT_Full |
2835                                                 ADVERTISED_10baseT_Full;
2836                                 else
2837                                         advertising |= ADVERTISED_10baseT_Full;
2838                         }
2839
2840                         phydev->advertising = advertising;
2841
2842                         phy_start_aneg(phydev);
2843
2844                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2845                         if (phyid != PHY_ID_BCMAC131) {
2846                                 phyid &= PHY_BCM_OUI_MASK;
2847                                 if (phyid == PHY_BCM_OUI_1 ||
2848                                     phyid == PHY_BCM_OUI_2 ||
2849                                     phyid == PHY_BCM_OUI_3)
2850                                         do_low_power = true;
2851                         }
2852                 }
2853         } else {
2854                 do_low_power = true;
2855
2856                 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2857                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2858                         tp->link_config.orig_speed = tp->link_config.speed;
2859                         tp->link_config.orig_duplex = tp->link_config.duplex;
2860                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2861                 }
2862
2863                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2864                         tp->link_config.speed = SPEED_10;
2865                         tp->link_config.duplex = DUPLEX_HALF;
2866                         tp->link_config.autoneg = AUTONEG_ENABLE;
2867                         tg3_setup_phy(tp, 0);
2868                 }
2869         }
2870
2871         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2872                 u32 val;
2873
2874                 val = tr32(GRC_VCPU_EXT_CTRL);
2875                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2876         } else if (!tg3_flag(tp, ENABLE_ASF)) {
2877                 int i;
2878                 u32 val;
2879
2880                 for (i = 0; i < 200; i++) {
2881                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2882                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2883                                 break;
2884                         msleep(1);
2885                 }
2886         }
2887         if (tg3_flag(tp, WOL_CAP))
2888                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2889                                                      WOL_DRV_STATE_SHUTDOWN |
2890                                                      WOL_DRV_WOL |
2891                                                      WOL_SET_MAGIC_PKT);
2892
2893         if (device_should_wake) {
2894                 u32 mac_mode;
2895
2896                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2897                         if (do_low_power &&
2898                             !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
2899                                 tg3_phy_auxctl_write(tp,
2900                                                MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
2901                                                MII_TG3_AUXCTL_PCTL_WOL_EN |
2902                                                MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2903                                                MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
2904                                 udelay(40);
2905                         }
2906
2907                         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2908                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2909                         else
2910                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2911
2912                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2913                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2914                             ASIC_REV_5700) {
2915                                 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
2916                                              SPEED_100 : SPEED_10;
2917                                 if (tg3_5700_link_polarity(tp, speed))
2918                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2919                                 else
2920                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2921                         }
2922                 } else {
2923                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2924                 }
2925
2926                 if (!tg3_flag(tp, 5750_PLUS))
2927                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2928
2929                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2930                 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
2931                     (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
2932                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2933
2934                 if (tg3_flag(tp, ENABLE_APE))
2935                         mac_mode |= MAC_MODE_APE_TX_EN |
2936                                     MAC_MODE_APE_RX_EN |
2937                                     MAC_MODE_TDE_ENABLE;
2938
2939                 tw32_f(MAC_MODE, mac_mode);
2940                 udelay(100);
2941
2942                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2943                 udelay(10);
2944         }
2945
2946         if (!tg3_flag(tp, WOL_SPEED_100MB) &&
2947             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2948              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2949                 u32 base_val;
2950
2951                 base_val = tp->pci_clock_ctrl;
2952                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2953                              CLOCK_CTRL_TXCLK_DISABLE);
2954
2955                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2956                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2957         } else if (tg3_flag(tp, 5780_CLASS) ||
2958                    tg3_flag(tp, CPMU_PRESENT) ||
2959                    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2960                 /* do nothing */
2961         } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
2962                 u32 newbits1, newbits2;
2963
2964                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2965                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2966                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2967                                     CLOCK_CTRL_TXCLK_DISABLE |
2968                                     CLOCK_CTRL_ALTCLK);
2969                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2970                 } else if (tg3_flag(tp, 5705_PLUS)) {
2971                         newbits1 = CLOCK_CTRL_625_CORE;
2972                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2973                 } else {
2974                         newbits1 = CLOCK_CTRL_ALTCLK;
2975                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2976                 }
2977
2978                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2979                             40);
2980
2981                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2982                             40);
2983
2984                 if (!tg3_flag(tp, 5705_PLUS)) {
2985                         u32 newbits3;
2986
2987                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2988                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2989                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2990                                             CLOCK_CTRL_TXCLK_DISABLE |
2991                                             CLOCK_CTRL_44MHZ_CORE);
2992                         } else {
2993                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2994                         }
2995
2996                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2997                                     tp->pci_clock_ctrl | newbits3, 40);
2998                 }
2999         }
3000
3001         if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
3002                 tg3_power_down_phy(tp, do_low_power);
3003
3004         tg3_frob_aux_power(tp, true);
3005
3006         /* Workaround for unstable PLL clock */
3007         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
3008             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
3009                 u32 val = tr32(0x7d00);
3010
3011                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
3012                 tw32(0x7d00, val);
3013                 if (!tg3_flag(tp, ENABLE_ASF)) {
3014                         int err;
3015
3016                         err = tg3_nvram_lock(tp);
3017                         tg3_halt_cpu(tp, RX_CPU_BASE);
3018                         if (!err)
3019                                 tg3_nvram_unlock(tp);
3020                 }
3021         }
3022
3023         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
3024
3025         return 0;
3026 }
3027
3028 static void tg3_power_down(struct tg3 *tp)
3029 {
3030         tg3_power_down_prepare(tp);
3031
3032         pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
3033         pci_set_power_state(tp->pdev, PCI_D3hot);
3034 }
3035
3036 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
3037 {
3038         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
3039         case MII_TG3_AUX_STAT_10HALF:
3040                 *speed = SPEED_10;
3041                 *duplex = DUPLEX_HALF;
3042                 break;
3043
3044         case MII_TG3_AUX_STAT_10FULL:
3045                 *speed = SPEED_10;
3046                 *duplex = DUPLEX_FULL;
3047                 break;
3048
3049         case MII_TG3_AUX_STAT_100HALF:
3050                 *speed = SPEED_100;
3051                 *duplex = DUPLEX_HALF;
3052                 break;
3053
3054         case MII_TG3_AUX_STAT_100FULL:
3055                 *speed = SPEED_100;
3056                 *duplex = DUPLEX_FULL;
3057                 break;
3058
3059         case MII_TG3_AUX_STAT_1000HALF:
3060                 *speed = SPEED_1000;
3061                 *duplex = DUPLEX_HALF;
3062                 break;
3063
3064         case MII_TG3_AUX_STAT_1000FULL:
3065                 *speed = SPEED_1000;
3066                 *duplex = DUPLEX_FULL;
3067                 break;
3068
3069         default:
3070                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
3071                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
3072                                  SPEED_10;
3073                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
3074                                   DUPLEX_HALF;
3075                         break;
3076                 }
3077                 *speed = SPEED_INVALID;
3078                 *duplex = DUPLEX_INVALID;
3079                 break;
3080         }
3081 }
3082
3083 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
3084 {
3085         int err = 0;
3086         u32 val, new_adv;
3087
3088         new_adv = ADVERTISE_CSMA;
3089         if (advertise & ADVERTISED_10baseT_Half)
3090                 new_adv |= ADVERTISE_10HALF;
3091         if (advertise & ADVERTISED_10baseT_Full)
3092                 new_adv |= ADVERTISE_10FULL;
3093         if (advertise & ADVERTISED_100baseT_Half)
3094                 new_adv |= ADVERTISE_100HALF;
3095         if (advertise & ADVERTISED_100baseT_Full)
3096                 new_adv |= ADVERTISE_100FULL;
3097
3098         new_adv |= tg3_advert_flowctrl_1000T(flowctrl);
3099
3100         err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
3101         if (err)
3102                 goto done;
3103
3104         if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
3105                 goto done;
3106
3107         new_adv = 0;
3108         if (advertise & ADVERTISED_1000baseT_Half)
3109                 new_adv |= ADVERTISE_1000HALF;
3110         if (advertise & ADVERTISED_1000baseT_Full)
3111                 new_adv |= ADVERTISE_1000FULL;
3112
3113         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3114             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
3115                 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
3116
3117         err = tg3_writephy(tp, MII_CTRL1000, new_adv);
3118         if (err)
3119                 goto done;
3120
3121         if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
3122                 goto done;
3123
3124         tw32(TG3_CPMU_EEE_MODE,
3125              tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
3126
3127         err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
3128         if (!err) {
3129                 u32 err2;
3130
3131                 switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
3132                 case ASIC_REV_5717:
3133                 case ASIC_REV_57765:
3134                         if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
3135                                 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
3136                                                  MII_TG3_DSP_CH34TP2_HIBW01);
3137                         /* Fall through */
3138                 case ASIC_REV_5719:
3139                         val = MII_TG3_DSP_TAP26_ALNOKO |
3140                               MII_TG3_DSP_TAP26_RMRXSTO |
3141                               MII_TG3_DSP_TAP26_OPCSINPT;
3142                         tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
3143                 }
3144
3145                 val = 0;
3146                 /* Advertise 100-BaseTX EEE ability */
3147                 if (advertise & ADVERTISED_100baseT_Full)
3148                         val |= MDIO_AN_EEE_ADV_100TX;
3149                 /* Advertise 1000-BaseT EEE ability */
3150                 if (advertise & ADVERTISED_1000baseT_Full)
3151                         val |= MDIO_AN_EEE_ADV_1000T;
3152                 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3153
3154                 err2 = TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
3155                 if (!err)
3156                         err = err2;
3157         }
3158
3159 done:
3160         return err;
3161 }
3162
3163 static void tg3_phy_copper_begin(struct tg3 *tp)
3164 {
3165         u32 new_adv;
3166         int i;
3167
3168         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
3169                 new_adv = ADVERTISED_10baseT_Half |
3170                           ADVERTISED_10baseT_Full;
3171                 if (tg3_flag(tp, WOL_SPEED_100MB))
3172                         new_adv |= ADVERTISED_100baseT_Half |
3173                                    ADVERTISED_100baseT_Full;
3174
3175                 tg3_phy_autoneg_cfg(tp, new_adv,
3176                                     FLOW_CTRL_TX | FLOW_CTRL_RX);
3177         } else if (tp->link_config.speed == SPEED_INVALID) {
3178                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
3179                         tp->link_config.advertising &=
3180                                 ~(ADVERTISED_1000baseT_Half |
3181                                   ADVERTISED_1000baseT_Full);
3182
3183                 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
3184                                     tp->link_config.flowctrl);
3185         } else {
3186                 /* Asking for a specific link mode. */
3187                 if (tp->link_config.speed == SPEED_1000) {
3188                         if (tp->link_config.duplex == DUPLEX_FULL)
3189                                 new_adv = ADVERTISED_1000baseT_Full;
3190                         else
3191                                 new_adv = ADVERTISED_1000baseT_Half;
3192                 } else if (tp->link_config.speed == SPEED_100) {
3193                         if (tp->link_config.duplex == DUPLEX_FULL)
3194                                 new_adv = ADVERTISED_100baseT_Full;
3195                         else
3196                                 new_adv = ADVERTISED_100baseT_Half;
3197                 } else {
3198                         if (tp->link_config.duplex == DUPLEX_FULL)
3199                                 new_adv = ADVERTISED_10baseT_Full;
3200                         else
3201                                 new_adv = ADVERTISED_10baseT_Half;
3202                 }
3203
3204                 tg3_phy_autoneg_cfg(tp, new_adv,
3205                                     tp->link_config.flowctrl);
3206         }
3207
3208         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
3209             tp->link_config.speed != SPEED_INVALID) {
3210                 u32 bmcr, orig_bmcr;
3211
3212                 tp->link_config.active_speed = tp->link_config.speed;
3213                 tp->link_config.active_duplex = tp->link_config.duplex;
3214
3215                 bmcr = 0;
3216                 switch (tp->link_config.speed) {
3217                 default:
3218                 case SPEED_10:
3219                         break;
3220
3221                 case SPEED_100:
3222                         bmcr |= BMCR_SPEED100;
3223                         break;
3224
3225                 case SPEED_1000:
3226                         bmcr |= BMCR_SPEED1000;
3227                         break;
3228                 }
3229
3230                 if (tp->link_config.duplex == DUPLEX_FULL)
3231                         bmcr |= BMCR_FULLDPLX;
3232
3233                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
3234                     (bmcr != orig_bmcr)) {
3235                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
3236                         for (i = 0; i < 1500; i++) {
3237                                 u32 tmp;
3238
3239                                 udelay(10);
3240                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
3241                                     tg3_readphy(tp, MII_BMSR, &tmp))
3242                                         continue;
3243                                 if (!(tmp & BMSR_LSTATUS)) {
3244                                         udelay(40);
3245                                         break;
3246                                 }
3247                         }
3248                         tg3_writephy(tp, MII_BMCR, bmcr);
3249                         udelay(40);
3250                 }
3251         } else {
3252                 tg3_writephy(tp, MII_BMCR,
3253                              BMCR_ANENABLE | BMCR_ANRESTART);
3254         }
3255 }
3256
3257 static int tg3_init_5401phy_dsp(struct tg3 *tp)
3258 {
3259         int err;
3260
3261         /* Turn off tap power management. */
3262         /* Set Extended packet length bit */
3263         err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
3264
3265         err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
3266         err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
3267         err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
3268         err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
3269         err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
3270
3271         udelay(40);
3272
3273         return err;
3274 }
3275
3276 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3277 {
3278         u32 adv_reg, all_mask = 0;
3279
3280         if (mask & ADVERTISED_10baseT_Half)
3281                 all_mask |= ADVERTISE_10HALF;
3282         if (mask & ADVERTISED_10baseT_Full)
3283                 all_mask |= ADVERTISE_10FULL;
3284         if (mask & ADVERTISED_100baseT_Half)
3285                 all_mask |= ADVERTISE_100HALF;
3286         if (mask & ADVERTISED_100baseT_Full)
3287                 all_mask |= ADVERTISE_100FULL;
3288
3289         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3290                 return 0;
3291
3292         if ((adv_reg & all_mask) != all_mask)
3293                 return 0;
3294         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3295                 u32 tg3_ctrl;
3296
3297                 all_mask = 0;
3298                 if (mask & ADVERTISED_1000baseT_Half)
3299                         all_mask |= ADVERTISE_1000HALF;
3300                 if (mask & ADVERTISED_1000baseT_Full)
3301                         all_mask |= ADVERTISE_1000FULL;
3302
3303                 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
3304                         return 0;
3305
3306                 if ((tg3_ctrl & all_mask) != all_mask)
3307                         return 0;
3308         }
3309         return 1;
3310 }
3311
3312 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3313 {
3314         u32 curadv, reqadv;
3315
3316         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3317                 return 1;
3318
3319         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3320         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3321
3322         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3323                 if (curadv != reqadv)
3324                         return 0;
3325
3326                 if (tg3_flag(tp, PAUSE_AUTONEG))
3327                         tg3_readphy(tp, MII_LPA, rmtadv);
3328         } else {
3329                 /* Reprogram the advertisement register, even if it
3330                  * does not affect the current link.  If the link
3331                  * gets renegotiated in the future, we can save an
3332                  * additional renegotiation cycle by advertising
3333                  * it correctly in the first place.
3334                  */
3335                 if (curadv != reqadv) {
3336                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3337                                      ADVERTISE_PAUSE_ASYM);
3338                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3339                 }
3340         }
3341
3342         return 1;
3343 }
3344
3345 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3346 {
3347         int current_link_up;
3348         u32 bmsr, val;
3349         u32 lcl_adv, rmt_adv;
3350         u16 current_speed;
3351         u8 current_duplex;
3352         int i, err;
3353
3354         tw32(MAC_EVENT, 0);
3355
3356         tw32_f(MAC_STATUS,
3357              (MAC_STATUS_SYNC_CHANGED |
3358               MAC_STATUS_CFG_CHANGED |
3359               MAC_STATUS_MI_COMPLETION |
3360               MAC_STATUS_LNKSTATE_CHANGED));
3361         udelay(40);
3362
3363         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3364                 tw32_f(MAC_MI_MODE,
3365                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3366                 udelay(80);
3367         }
3368
3369         tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
3370
3371         /* Some third-party PHYs need to be reset on link going
3372          * down.
3373          */
3374         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3375              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3376              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3377             netif_carrier_ok(tp->dev)) {
3378                 tg3_readphy(tp, MII_BMSR, &bmsr);
3379                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3380                     !(bmsr & BMSR_LSTATUS))
3381                         force_reset = 1;
3382         }
3383         if (force_reset)
3384                 tg3_phy_reset(tp);
3385
3386         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3387                 tg3_readphy(tp, MII_BMSR, &bmsr);
3388                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3389                     !tg3_flag(tp, INIT_COMPLETE))
3390                         bmsr = 0;
3391
3392                 if (!(bmsr & BMSR_LSTATUS)) {
3393                         err = tg3_init_5401phy_dsp(tp);
3394                         if (err)
3395                                 return err;
3396
3397                         tg3_readphy(tp, MII_BMSR, &bmsr);
3398                         for (i = 0; i < 1000; i++) {
3399                                 udelay(10);
3400                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3401                                     (bmsr & BMSR_LSTATUS)) {
3402                                         udelay(40);
3403                                         break;
3404                                 }
3405                         }
3406
3407                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3408                             TG3_PHY_REV_BCM5401_B0 &&
3409                             !(bmsr & BMSR_LSTATUS) &&
3410                             tp->link_config.active_speed == SPEED_1000) {
3411                                 err = tg3_phy_reset(tp);
3412                                 if (!err)
3413                                         err = tg3_init_5401phy_dsp(tp);
3414                                 if (err)
3415                                         return err;
3416                         }
3417                 }
3418         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3419                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3420                 /* 5701 {A0,B0} CRC bug workaround */
3421                 tg3_writephy(tp, 0x15, 0x0a75);
3422                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3423                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3424                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3425         }
3426
3427         /* Clear pending interrupts... */
3428         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3429         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3430
3431         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3432                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3433         else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3434                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3435
3436         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3437             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3438                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3439                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3440                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3441                 else
3442                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3443         }
3444
3445         current_link_up = 0;
3446         current_speed = SPEED_INVALID;
3447         current_duplex = DUPLEX_INVALID;
3448
3449         if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3450                 err = tg3_phy_auxctl_read(tp,
3451                                           MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
3452                                           &val);
3453                 if (!err && !(val & (1 << 10))) {
3454                         tg3_phy_auxctl_write(tp,
3455                                              MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
3456                                              val | (1 << 10));
3457                         goto relink;
3458                 }
3459         }
3460
3461         bmsr = 0;
3462         for (i = 0; i < 100; i++) {
3463                 tg3_readphy(tp, MII_BMSR, &bmsr);
3464                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3465                     (bmsr & BMSR_LSTATUS))
3466                         break;
3467                 udelay(40);
3468         }
3469
3470         if (bmsr & BMSR_LSTATUS) {
3471                 u32 aux_stat, bmcr;
3472
3473                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3474                 for (i = 0; i < 2000; i++) {
3475                         udelay(10);
3476                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3477                             aux_stat)
3478                                 break;
3479                 }
3480
3481                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3482                                              &current_speed,
3483                                              &current_duplex);
3484
3485                 bmcr = 0;
3486                 for (i = 0; i < 200; i++) {
3487                         tg3_readphy(tp, MII_BMCR, &bmcr);
3488                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3489                                 continue;
3490                         if (bmcr && bmcr != 0x7fff)
3491                                 break;
3492                         udelay(10);
3493                 }
3494
3495                 lcl_adv = 0;
3496                 rmt_adv = 0;
3497
3498                 tp->link_config.active_speed = current_speed;
3499                 tp->link_config.active_duplex = current_duplex;
3500
3501                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3502                         if ((bmcr & BMCR_ANENABLE) &&
3503                             tg3_copper_is_advertising_all(tp,
3504                                                 tp->link_config.advertising)) {
3505                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3506                                                                   &rmt_adv))
3507                                         current_link_up = 1;
3508                         }
3509                 } else {
3510                         if (!(bmcr & BMCR_ANENABLE) &&
3511                             tp->link_config.speed == current_speed &&
3512                             tp->link_config.duplex == current_duplex &&
3513                             tp->link_config.flowctrl ==
3514                             tp->link_config.active_flowctrl) {
3515                                 current_link_up = 1;
3516                         }
3517                 }
3518
3519                 if (current_link_up == 1 &&
3520                     tp->link_config.active_duplex == DUPLEX_FULL)
3521                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3522         }
3523
3524 relink:
3525         if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3526                 tg3_phy_copper_begin(tp);
3527
3528                 tg3_readphy(tp, MII_BMSR, &bmsr);
3529                 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
3530                     (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
3531                         current_link_up = 1;
3532         }
3533
3534         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3535         if (current_link_up == 1) {
3536                 if (tp->link_config.active_speed == SPEED_100 ||
3537                     tp->link_config.active_speed == SPEED_10)
3538                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3539                 else
3540                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3541         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3542                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3543         else
3544                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3545
3546         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3547         if (tp->link_config.active_duplex == DUPLEX_HALF)
3548                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3549
3550         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3551                 if (current_link_up == 1 &&
3552                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3553                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3554                 else
3555                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3556         }
3557
3558         /* ??? Without this setting Netgear GA302T PHY does not
3559          * ??? send/receive packets...
3560          */
3561         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3562             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3563                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3564                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3565                 udelay(80);
3566         }
3567
3568         tw32_f(MAC_MODE, tp->mac_mode);
3569         udelay(40);
3570
3571         tg3_phy_eee_adjust(tp, current_link_up);
3572
3573         if (tg3_flag(tp, USE_LINKCHG_REG)) {
3574                 /* Polled via timer. */
3575                 tw32_f(MAC_EVENT, 0);
3576         } else {
3577                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3578         }
3579         udelay(40);
3580
3581         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3582             current_link_up == 1 &&
3583             tp->link_config.active_speed == SPEED_1000 &&
3584             (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
3585                 udelay(120);
3586                 tw32_f(MAC_STATUS,
3587                      (MAC_STATUS_SYNC_CHANGED |
3588                       MAC_STATUS_CFG_CHANGED));
3589                 udelay(40);
3590                 tg3_write_mem(tp,
3591                               NIC_SRAM_FIRMWARE_MBOX,
3592                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3593         }
3594
3595         /* Prevent send BD corruption. */
3596         if (tg3_flag(tp, CLKREQ_BUG)) {
3597                 u16 oldlnkctl, newlnkctl;
3598
3599                 pci_read_config_word(tp->pdev,
3600                                      pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
3601                                      &oldlnkctl);
3602                 if (tp->link_config.active_speed == SPEED_100 ||
3603                     tp->link_config.active_speed == SPEED_10)
3604                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3605                 else
3606                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3607                 if (newlnkctl != oldlnkctl)
3608                         pci_write_config_word(tp->pdev,
3609                                               pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
3610                                               newlnkctl);
3611         }
3612
3613         if (current_link_up != netif_carrier_ok(tp->dev)) {
3614                 if (current_link_up)
3615                         netif_carrier_on(tp->dev);
3616                 else
3617                         netif_carrier_off(tp->dev);
3618                 tg3_link_report(tp);
3619         }
3620
3621         return 0;
3622 }
3623
3624 struct tg3_fiber_aneginfo {
3625         int state;
3626 #define ANEG_STATE_UNKNOWN              0
3627 #define ANEG_STATE_AN_ENABLE            1
3628 #define ANEG_STATE_RESTART_INIT         2
3629 #define ANEG_STATE_RESTART              3
3630 #define ANEG_STATE_DISABLE_LINK_OK      4
3631 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3632 #define ANEG_STATE_ABILITY_DETECT       6
3633 #define ANEG_STATE_ACK_DETECT_INIT      7
3634 #define ANEG_STATE_ACK_DETECT           8
3635 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3636 #define ANEG_STATE_COMPLETE_ACK         10
3637 #define ANEG_STATE_IDLE_DETECT_INIT     11
3638 #define ANEG_STATE_IDLE_DETECT          12
3639 #define ANEG_STATE_LINK_OK              13
3640 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3641 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3642
3643         u32 flags;
3644 #define MR_AN_ENABLE            0x00000001
3645 #define MR_RESTART_AN           0x00000002
3646 #define MR_AN_COMPLETE          0x00000004
3647 #define MR_PAGE_RX              0x00000008
3648 #define MR_NP_LOADED            0x00000010
3649 #define MR_TOGGLE_TX            0x00000020
3650 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3651 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3652 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3653 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3654 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3655 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3656 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3657 #define MR_TOGGLE_RX            0x00002000
3658 #define MR_NP_RX                0x00004000
3659
3660 #define MR_LINK_OK              0x80000000
3661
3662         unsigned long link_time, cur_time;
3663
3664         u32 ability_match_cfg;
3665         int ability_match_count;
3666
3667         char ability_match, idle_match, ack_match;
3668
3669         u32 txconfig, rxconfig;
3670 #define ANEG_CFG_NP             0x00000080
3671 #define ANEG_CFG_ACK            0x00000040
3672 #define ANEG_CFG_RF2            0x00000020
3673 #define ANEG_CFG_RF1            0x00000010
3674 #define ANEG_CFG_PS2            0x00000001
3675 #define ANEG_CFG_PS1            0x00008000
3676 #define ANEG_CFG_HD             0x00004000
3677 #define ANEG_CFG_FD             0x00002000
3678 #define ANEG_CFG_INVAL          0x00001f06
3679
3680 };
3681 #define ANEG_OK         0
3682 #define ANEG_DONE       1
3683 #define ANEG_TIMER_ENAB 2
3684 #define ANEG_FAILED     -1
3685
3686 #define ANEG_STATE_SETTLE_TIME  10000
3687
3688 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3689                                    struct tg3_fiber_aneginfo *ap)
3690 {
3691         u16 flowctrl;
3692         unsigned long delta;
3693         u32 rx_cfg_reg;
3694         int ret;
3695
3696         if (ap->state == ANEG_STATE_UNKNOWN) {
3697                 ap->rxconfig = 0;
3698                 ap->link_time = 0;
3699                 ap->cur_time = 0;
3700                 ap->ability_match_cfg = 0;
3701                 ap->ability_match_count = 0;
3702                 ap->ability_match = 0;
3703                 ap->idle_match = 0;
3704                 ap->ack_match = 0;
3705         }
3706         ap->cur_time++;
3707
3708         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3709                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3710
3711                 if (rx_cfg_reg != ap->ability_match_cfg) {
3712                         ap->ability_match_cfg = rx_cfg_reg;
3713                         ap->ability_match = 0;
3714                         ap->ability_match_count = 0;
3715                 } else {
3716                         if (++ap->ability_match_count > 1) {
3717                                 ap->ability_match = 1;
3718                                 ap->ability_match_cfg = rx_cfg_reg;
3719                         }
3720                 }
3721                 if (rx_cfg_reg & ANEG_CFG_ACK)
3722                         ap->ack_match = 1;
3723                 else
3724                         ap->ack_match = 0;
3725
3726                 ap->idle_match = 0;
3727         } else {
3728                 ap->idle_match = 1;
3729                 ap->ability_match_cfg = 0;
3730                 ap->ability_match_count = 0;
3731                 ap->ability_match = 0;
3732                 ap->ack_match = 0;
3733
3734                 rx_cfg_reg = 0;
3735         }
3736
3737         ap->rxconfig = rx_cfg_reg;
3738         ret = ANEG_OK;
3739
3740         switch (ap->state) {
3741         case ANEG_STATE_UNKNOWN:
3742                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3743                         ap->state = ANEG_STATE_AN_ENABLE;
3744
3745                 /* fallthru */
3746         case ANEG_STATE_AN_ENABLE:
3747                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3748                 if (ap->flags & MR_AN_ENABLE) {
3749                         ap->link_time = 0;
3750                         ap->cur_time = 0;
3751                         ap->ability_match_cfg = 0;
3752                         ap->ability_match_count = 0;
3753                         ap->ability_match = 0;
3754                         ap->idle_match = 0;
3755                         ap->ack_match = 0;
3756
3757                         ap->state = ANEG_STATE_RESTART_INIT;
3758                 } else {
3759                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3760                 }
3761                 break;
3762
3763         case ANEG_STATE_RESTART_INIT:
3764                 ap->link_time = ap->cur_time;
3765                 ap->flags &= ~(MR_NP_LOADED);
3766                 ap->txconfig = 0;
3767                 tw32(MAC_TX_AUTO_NEG, 0);
3768                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3769                 tw32_f(MAC_MODE, tp->mac_mode);
3770                 udelay(40);
3771
3772                 ret = ANEG_TIMER_ENAB;
3773                 ap->state = ANEG_STATE_RESTART;
3774
3775                 /* fallthru */
3776         case ANEG_STATE_RESTART:
3777                 delta = ap->cur_time - ap->link_time;
3778                 if (delta > ANEG_STATE_SETTLE_TIME)
3779                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3780                 else
3781                         ret = ANEG_TIMER_ENAB;
3782                 break;
3783
3784         case ANEG_STATE_DISABLE_LINK_OK:
3785                 ret = ANEG_DONE;
3786                 break;
3787
3788         case ANEG_STATE_ABILITY_DETECT_INIT:
3789                 ap->flags &= ~(MR_TOGGLE_TX);
3790                 ap->txconfig = ANEG_CFG_FD;
3791                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3792                 if (flowctrl & ADVERTISE_1000XPAUSE)
3793                         ap->txconfig |= ANEG_CFG_PS1;
3794                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3795                         ap->txconfig |= ANEG_CFG_PS2;
3796                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3797                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3798                 tw32_f(MAC_MODE, tp->mac_mode);
3799                 udelay(40);
3800
3801                 ap->state = ANEG_STATE_ABILITY_DETECT;
3802                 break;
3803
3804         case ANEG_STATE_ABILITY_DETECT:
3805                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3806                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3807                 break;
3808
3809         case ANEG_STATE_ACK_DETECT_INIT:
3810                 ap->txconfig |= ANEG_CFG_ACK;
3811                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3812                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3813                 tw32_f(MAC_MODE, tp->mac_mode);
3814                 udelay(40);
3815
3816                 ap->state = ANEG_STATE_ACK_DETECT;
3817
3818                 /* fallthru */
3819         case ANEG_STATE_ACK_DETECT:
3820                 if (ap->ack_match != 0) {
3821                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3822                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3823                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3824                         } else {
3825                                 ap->state = ANEG_STATE_AN_ENABLE;
3826                         }
3827                 } else if (ap->ability_match != 0 &&
3828                            ap->rxconfig == 0) {
3829                         ap->state = ANEG_STATE_AN_ENABLE;
3830                 }
3831                 break;
3832
3833         case ANEG_STATE_COMPLETE_ACK_INIT:
3834                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3835                         ret = ANEG_FAILED;
3836                         break;
3837                 }
3838                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3839                                MR_LP_ADV_HALF_DUPLEX |
3840                                MR_LP_ADV_SYM_PAUSE |
3841                                MR_LP_ADV_ASYM_PAUSE |
3842                                MR_LP_ADV_REMOTE_FAULT1 |
3843                                MR_LP_ADV_REMOTE_FAULT2 |
3844                                MR_LP_ADV_NEXT_PAGE |
3845                                MR_TOGGLE_RX |
3846                                MR_NP_RX);
3847                 if (ap->rxconfig & ANEG_CFG_FD)
3848                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3849                 if (ap->rxconfig & ANEG_CFG_HD)
3850                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3851                 if (ap->rxconfig & ANEG_CFG_PS1)
3852                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3853                 if (ap->rxconfig & ANEG_CFG_PS2)
3854                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3855                 if (ap->rxconfig & ANEG_CFG_RF1)
3856                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3857                 if (ap->rxconfig & ANEG_CFG_RF2)
3858                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3859                 if (ap->rxconfig & ANEG_CFG_NP)
3860                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3861
3862                 ap->link_time = ap->cur_time;
3863
3864                 ap->flags ^= (MR_TOGGLE_TX);
3865                 if (ap->rxconfig & 0x0008)
3866                         ap->flags |= MR_TOGGLE_RX;
3867                 if (ap->rxconfig & ANEG_CFG_NP)
3868                         ap->flags |= MR_NP_RX;
3869                 ap->flags |= MR_PAGE_RX;
3870
3871                 ap->state = ANEG_STATE_COMPLETE_ACK;
3872                 ret = ANEG_TIMER_ENAB;
3873                 break;
3874
3875         case ANEG_STATE_COMPLETE_ACK:
3876                 if (ap->ability_match != 0 &&
3877                     ap->rxconfig == 0) {
3878                         ap->state = ANEG_STATE_AN_ENABLE;
3879                         break;
3880                 }
3881                 delta = ap->cur_time - ap->link_time;
3882                 if (delta > ANEG_STATE_SETTLE_TIME) {
3883                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3884                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3885                         } else {
3886                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3887                                     !(ap->flags & MR_NP_RX)) {
3888                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3889                                 } else {
3890                                         ret = ANEG_FAILED;
3891                                 }
3892                         }
3893                 }
3894                 break;
3895
3896         case ANEG_STATE_IDLE_DETECT_INIT:
3897                 ap->link_time = ap->cur_time;
3898                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3899                 tw32_f(MAC_MODE, tp->mac_mode);
3900                 udelay(40);
3901
3902                 ap->state = ANEG_STATE_IDLE_DETECT;
3903                 ret = ANEG_TIMER_ENAB;
3904                 break;
3905
3906         case ANEG_STATE_IDLE_DETECT:
3907                 if (ap->ability_match != 0 &&
3908                     ap->rxconfig == 0) {
3909                         ap->state = ANEG_STATE_AN_ENABLE;
3910                         break;
3911                 }
3912                 delta = ap->cur_time - ap->link_time;
3913                 if (delta > ANEG_STATE_SETTLE_TIME) {
3914                         /* XXX another gem from the Broadcom driver :( */
3915                         ap->state = ANEG_STATE_LINK_OK;
3916                 }
3917                 break;
3918
3919         case ANEG_STATE_LINK_OK:
3920                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3921                 ret = ANEG_DONE;
3922                 break;
3923
3924         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3925                 /* ??? unimplemented */
3926                 break;
3927
3928         case ANEG_STATE_NEXT_PAGE_WAIT:
3929                 /* ??? unimplemented */
3930                 break;
3931
3932         default:
3933                 ret = ANEG_FAILED;
3934                 break;
3935         }
3936
3937         return ret;
3938 }
3939
3940 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3941 {
3942         int res = 0;
3943         struct tg3_fiber_aneginfo aninfo;
3944         int status = ANEG_FAILED;
3945         unsigned int tick;
3946         u32 tmp;
3947
3948         tw32_f(MAC_TX_AUTO_NEG, 0);
3949
3950         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3951         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3952         udelay(40);
3953
3954         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3955         udelay(40);
3956
3957         memset(&aninfo, 0, sizeof(aninfo));
3958         aninfo.flags |= MR_AN_ENABLE;
3959         aninfo.state = ANEG_STATE_UNKNOWN;
3960         aninfo.cur_time = 0;
3961         tick = 0;
3962         while (++tick < 195000) {
3963                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3964                 if (status == ANEG_DONE || status == ANEG_FAILED)
3965                         break;
3966
3967                 udelay(1);
3968         }
3969
3970         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3971         tw32_f(MAC_MODE, tp->mac_mode);
3972         udelay(40);
3973
3974         *txflags = aninfo.txconfig;
3975         *rxflags = aninfo.flags;
3976
3977         if (status == ANEG_DONE &&
3978             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3979                              MR_LP_ADV_FULL_DUPLEX)))
3980                 res = 1;
3981
3982         return res;
3983 }
3984
3985 static void tg3_init_bcm8002(struct tg3 *tp)
3986 {
3987         u32 mac_status = tr32(MAC_STATUS);
3988         int i;
3989
3990         /* Reset when initting first time or we have a link. */
3991         if (tg3_flag(tp, INIT_COMPLETE) &&
3992             !(mac_status & MAC_STATUS_PCS_SYNCED))
3993                 return;
3994
3995         /* Set PLL lock range. */
3996         tg3_writephy(tp, 0x16, 0x8007);
3997
3998         /* SW reset */
3999         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
4000
4001         /* Wait for reset to complete. */
4002         /* XXX schedule_timeout() ... */
4003         for (i = 0; i < 500; i++)
4004                 udelay(10);
4005
4006         /* Config mode; select PMA/Ch 1 regs. */
4007         tg3_writephy(tp, 0x10, 0x8411);
4008
4009         /* Enable auto-lock and comdet, select txclk for tx. */
4010         tg3_writephy(tp, 0x11, 0x0a10);
4011
4012         tg3_writephy(tp, 0x18, 0x00a0);
4013         tg3_writephy(tp, 0x16, 0x41ff);
4014
4015         /* Assert and deassert POR. */
4016         tg3_writephy(tp, 0x13, 0x0400);
4017         udelay(40);
4018         tg3_writephy(tp, 0x13, 0x0000);
4019
4020         tg3_writephy(tp, 0x11, 0x0a50);
4021         udelay(40);
4022         tg3_writephy(tp, 0x11, 0x0a10);
4023
4024         /* Wait for signal to stabilize */
4025         /* XXX schedule_timeout() ... */
4026         for (i = 0; i < 15000; i++)
4027                 udelay(10);
4028
4029         /* Deselect the channel register so we can read the PHYID
4030          * later.
4031          */
4032         tg3_writephy(tp, 0x10, 0x8011);
4033 }
4034
4035 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
4036 {
4037         u16 flowctrl;
4038         u32 sg_dig_ctrl, sg_dig_status;
4039         u32 serdes_cfg, expected_sg_dig_ctrl;
4040         int workaround, port_a;
4041         int current_link_up;
4042
4043         serdes_cfg = 0;
4044         expected_sg_dig_ctrl = 0;
4045         workaround = 0;
4046         port_a = 1;
4047         current_link_up = 0;
4048
4049         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
4050             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
4051                 workaround = 1;
4052                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
4053                         port_a = 0;
4054
4055                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
4056                 /* preserve bits 20-23 for voltage regulator */
4057                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
4058         }
4059
4060         sg_dig_ctrl = tr32(SG_DIG_CTRL);
4061
4062         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
4063                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
4064                         if (workaround) {
4065                                 u32 val = serdes_cfg;
4066
4067                                 if (port_a)
4068                                         val |= 0xc010000;
4069                                 else
4070                                         val |= 0x4010000;
4071                                 tw32_f(MAC_SERDES_CFG, val);
4072                         }
4073
4074                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
4075                 }
4076                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
4077                         tg3_setup_flow_control(tp, 0, 0);
4078                         current_link_up = 1;
4079                 }
4080                 goto out;
4081         }
4082
4083         /* Want auto-negotiation.  */
4084         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
4085
4086         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4087         if (flowctrl & ADVERTISE_1000XPAUSE)
4088                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
4089         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
4090                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
4091
4092         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
4093                 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
4094                     tp->serdes_counter &&
4095                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
4096                                     MAC_STATUS_RCVD_CFG)) ==
4097                      MAC_STATUS_PCS_SYNCED)) {
4098                         tp->serdes_counter--;
4099                         current_link_up = 1;
4100                         goto out;
4101                 }
4102 restart_autoneg:
4103                 if (workaround)
4104                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
4105                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
4106                 udelay(5);
4107                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
4108
4109                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
4110                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4111         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
4112                                  MAC_STATUS_SIGNAL_DET)) {
4113                 sg_dig_status = tr32(SG_DIG_STATUS);
4114                 mac_status = tr32(MAC_STATUS);
4115
4116                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
4117                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
4118                         u32 local_adv = 0, remote_adv = 0;
4119
4120                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
4121                                 local_adv |= ADVERTISE_1000XPAUSE;
4122                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
4123                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
4124
4125                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
4126                                 remote_adv |= LPA_1000XPAUSE;
4127                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
4128                                 remote_adv |= LPA_1000XPAUSE_ASYM;
4129
4130                         tg3_setup_flow_control(tp, local_adv, remote_adv);
4131                         current_link_up = 1;
4132                         tp->serdes_counter = 0;
4133                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4134                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
4135                         if (tp->serdes_counter)
4136                                 tp->serdes_counter--;
4137                         else {
4138                                 if (workaround) {
4139                                         u32 val = serdes_cfg;
4140
4141                                         if (port_a)
4142                                                 val |= 0xc010000;
4143                                         else
4144                                                 val |= 0x4010000;
4145
4146                                         tw32_f(MAC_SERDES_CFG, val);
4147                                 }
4148
4149                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
4150                                 udelay(40);
4151
4152                                 /* Link parallel detection - link is up */
4153                                 /* only if we have PCS_SYNC and not */
4154                                 /* receiving config code words */
4155                                 mac_status = tr32(MAC_STATUS);
4156                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
4157                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
4158                                         tg3_setup_flow_control(tp, 0, 0);
4159                                         current_link_up = 1;
4160                                         tp->phy_flags |=
4161                                                 TG3_PHYFLG_PARALLEL_DETECT;
4162                                         tp->serdes_counter =
4163                                                 SERDES_PARALLEL_DET_TIMEOUT;
4164                                 } else
4165                                         goto restart_autoneg;
4166                         }
4167                 }
4168         } else {
4169                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
4170                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4171         }
4172
4173 out:
4174         return current_link_up;
4175 }
4176
4177 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
4178 {
4179         int current_link_up = 0;
4180
4181         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
4182                 goto out;
4183
4184         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4185                 u32 txflags, rxflags;
4186                 int i;
4187
4188                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
4189                         u32 local_adv = 0, remote_adv = 0;
4190
4191                         if (txflags & ANEG_CFG_PS1)
4192                                 local_adv |= ADVERTISE_1000XPAUSE;
4193                         if (txflags & ANEG_CFG_PS2)
4194                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
4195
4196                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
4197                                 remote_adv |= LPA_1000XPAUSE;
4198                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
4199                                 remote_adv |= LPA_1000XPAUSE_ASYM;
4200
4201                         tg3_setup_flow_control(tp, local_adv, remote_adv);
4202
4203                         current_link_up = 1;
4204                 }
4205                 for (i = 0; i < 30; i++) {
4206                         udelay(20);
4207                         tw32_f(MAC_STATUS,
4208                                (MAC_STATUS_SYNC_CHANGED |
4209                                 MAC_STATUS_CFG_CHANGED));
4210                         udelay(40);
4211                         if ((tr32(MAC_STATUS) &
4212                              (MAC_STATUS_SYNC_CHANGED |
4213                               MAC_STATUS_CFG_CHANGED)) == 0)
4214                                 break;
4215                 }
4216
4217                 mac_status = tr32(MAC_STATUS);
4218                 if (current_link_up == 0 &&
4219                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
4220                     !(mac_status & MAC_STATUS_RCVD_CFG))
4221                         current_link_up = 1;
4222         } else {
4223                 tg3_setup_flow_control(tp, 0, 0);
4224
4225                 /* Forcing 1000FD link up. */
4226                 current_link_up = 1;
4227
4228                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
4229                 udelay(40);
4230
4231                 tw32_f(MAC_MODE, tp->mac_mode);
4232                 udelay(40);
4233         }
4234
4235 out:
4236         return current_link_up;
4237 }
4238
4239 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4240 {
4241         u32 orig_pause_cfg;
4242         u16 orig_active_speed;
4243         u8 orig_active_duplex;
4244         u32 mac_status;
4245         int current_link_up;
4246         int i;
4247
4248         orig_pause_cfg = tp->link_config.active_flowctrl;
4249         orig_active_speed = tp->link_config.active_speed;
4250         orig_active_duplex = tp->link_config.active_duplex;
4251
4252         if (!tg3_flag(tp, HW_AUTONEG) &&
4253             netif_carrier_ok(tp->dev) &&
4254             tg3_flag(tp, INIT_COMPLETE)) {
4255                 mac_status = tr32(MAC_STATUS);
4256                 mac_status &= (MAC_STATUS_PCS_SYNCED |
4257                                MAC_STATUS_SIGNAL_DET |
4258                                MAC_STATUS_CFG_CHANGED |
4259                                MAC_STATUS_RCVD_CFG);
4260                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
4261                                    MAC_STATUS_SIGNAL_DET)) {
4262                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4263                                             MAC_STATUS_CFG_CHANGED));
4264                         return 0;
4265                 }
4266         }
4267
4268         tw32_f(MAC_TX_AUTO_NEG, 0);
4269
4270         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
4271         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
4272         tw32_f(MAC_MODE, tp->mac_mode);
4273         udelay(40);
4274
4275         if (tp->phy_id == TG3_PHY_ID_BCM8002)
4276                 tg3_init_bcm8002(tp);
4277
4278         /* Enable link change event even when serdes polling.  */
4279         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4280         udelay(40);
4281
4282         current_link_up = 0;
4283         mac_status = tr32(MAC_STATUS);
4284
4285         if (tg3_flag(tp, HW_AUTONEG))
4286                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4287         else
4288                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4289
4290         tp->napi[0].hw_status->status =
4291                 (SD_STATUS_UPDATED |
4292                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4293
4294         for (i = 0; i < 100; i++) {
4295                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4296                                     MAC_STATUS_CFG_CHANGED));
4297                 udelay(5);
4298                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4299                                          MAC_STATUS_CFG_CHANGED |
4300                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4301                         break;
4302         }
4303
4304         mac_status = tr32(MAC_STATUS);
4305         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4306                 current_link_up = 0;
4307                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4308                     tp->serdes_counter == 0) {
4309                         tw32_f(MAC_MODE, (tp->mac_mode |
4310                                           MAC_MODE_SEND_CONFIGS));
4311                         udelay(1);
4312                         tw32_f(MAC_MODE, tp->mac_mode);
4313                 }
4314         }
4315
4316         if (current_link_up == 1) {
4317                 tp->link_config.active_speed = SPEED_1000;
4318                 tp->link_config.active_duplex = DUPLEX_FULL;
4319                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4320                                     LED_CTRL_LNKLED_OVERRIDE |
4321                                     LED_CTRL_1000MBPS_ON));
4322         } else {
4323                 tp->link_config.active_speed = SPEED_INVALID;
4324                 tp->link_config.active_duplex = DUPLEX_INVALID;
4325                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4326                                     LED_CTRL_LNKLED_OVERRIDE |
4327                                     LED_CTRL_TRAFFIC_OVERRIDE));
4328         }
4329
4330         if (current_link_up != netif_carrier_ok(tp->dev)) {
4331                 if (current_link_up)
4332                         netif_carrier_on(tp->dev);
4333                 else
4334                         netif_carrier_off(tp->dev);
4335                 tg3_link_report(tp);
4336         } else {
4337                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4338                 if (orig_pause_cfg != now_pause_cfg ||
4339                     orig_active_speed != tp->link_config.active_speed ||
4340                     orig_active_duplex != tp->link_config.active_duplex)
4341                         tg3_link_report(tp);
4342         }
4343
4344         return 0;
4345 }
4346
4347 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4348 {
4349         int current_link_up, err = 0;
4350         u32 bmsr, bmcr;
4351         u16 current_speed;
4352         u8 current_duplex;
4353         u32 local_adv, remote_adv;
4354
4355         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4356         tw32_f(MAC_MODE, tp->mac_mode);
4357         udelay(40);
4358
4359         tw32(MAC_EVENT, 0);
4360
4361         tw32_f(MAC_STATUS,
4362              (MAC_STATUS_SYNC_CHANGED |
4363               MAC_STATUS_CFG_CHANGED |
4364               MAC_STATUS_MI_COMPLETION |
4365               MAC_STATUS_LNKSTATE_CHANGED));
4366         udelay(40);
4367
4368         if (force_reset)
4369                 tg3_phy_reset(tp);
4370
4371         current_link_up = 0;
4372         current_speed = SPEED_INVALID;
4373         current_duplex = DUPLEX_INVALID;
4374
4375         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4376         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4377         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4378                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4379                         bmsr |= BMSR_LSTATUS;
4380                 else
4381                         bmsr &= ~BMSR_LSTATUS;
4382         }
4383
4384         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4385
4386         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4387             (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4388                 /* do nothing, just check for link up at the end */
4389         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4390                 u32 adv, new_adv;
4391
4392                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4393                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4394                                   ADVERTISE_1000XPAUSE |
4395                                   ADVERTISE_1000XPSE_ASYM |
4396                                   ADVERTISE_SLCT);
4397
4398                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4399
4400                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4401                         new_adv |= ADVERTISE_1000XHALF;
4402                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4403                         new_adv |= ADVERTISE_1000XFULL;
4404
4405                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4406                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4407                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4408                         tg3_writephy(tp, MII_BMCR, bmcr);
4409
4410                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4411                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4412                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4413
4414                         return err;
4415                 }
4416         } else {
4417                 u32 new_bmcr;
4418
4419                 bmcr &= ~BMCR_SPEED1000;
4420                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4421
4422                 if (tp->link_config.duplex == DUPLEX_FULL)
4423                         new_bmcr |= BMCR_FULLDPLX;
4424
4425                 if (new_bmcr != bmcr) {
4426                         /* BMCR_SPEED1000 is a reserved bit that needs
4427                          * to be set on write.
4428                          */
4429                         new_bmcr |= BMCR_SPEED1000;
4430
4431                         /* Force a linkdown */
4432                         if (netif_carrier_ok(tp->dev)) {
4433                                 u32 adv;
4434
4435                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4436                                 adv &= ~(ADVERTISE_1000XFULL |
4437                                          ADVERTISE_1000XHALF |
4438                                          ADVERTISE_SLCT);
4439                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4440                                 tg3_writephy(tp, MII_BMCR, bmcr |
4441                                                            BMCR_ANRESTART |
4442                                                            BMCR_ANENABLE);
4443                                 udelay(10);
4444                                 netif_carrier_off(tp->dev);
4445                         }
4446                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4447                         bmcr = new_bmcr;
4448                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4449                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4450                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4451                             ASIC_REV_5714) {
4452                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4453                                         bmsr |= BMSR_LSTATUS;
4454                                 else
4455                                         bmsr &= ~BMSR_LSTATUS;
4456                         }
4457                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4458                 }
4459         }
4460
4461         if (bmsr & BMSR_LSTATUS) {
4462                 current_speed = SPEED_1000;
4463                 current_link_up = 1;
4464                 if (bmcr & BMCR_FULLDPLX)
4465                         current_duplex = DUPLEX_FULL;
4466                 else
4467                         current_duplex = DUPLEX_HALF;
4468
4469                 local_adv = 0;
4470                 remote_adv = 0;
4471
4472                 if (bmcr & BMCR_ANENABLE) {
4473                         u32 common;
4474
4475                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4476                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4477                         common = local_adv & remote_adv;
4478                         if (common & (ADVERTISE_1000XHALF |
4479                                       ADVERTISE_1000XFULL)) {
4480                                 if (common & ADVERTISE_1000XFULL)
4481                                         current_duplex = DUPLEX_FULL;
4482                                 else
4483                                         current_duplex = DUPLEX_HALF;
4484                         } else if (!tg3_flag(tp, 5780_CLASS)) {
4485                                 /* Link is up via parallel detect */
4486                         } else {
4487                                 current_link_up = 0;
4488                         }
4489                 }
4490         }
4491
4492         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4493                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4494
4495         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4496         if (tp->link_config.active_duplex == DUPLEX_HALF)
4497                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4498
4499         tw32_f(MAC_MODE, tp->mac_mode);
4500         udelay(40);
4501
4502         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4503
4504         tp->link_config.active_speed = current_speed;
4505         tp->link_config.active_duplex = current_duplex;
4506
4507         if (current_link_up != netif_carrier_ok(tp->dev)) {
4508                 if (current_link_up)
4509                         netif_carrier_on(tp->dev);
4510                 else {
4511                         netif_carrier_off(tp->dev);
4512                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4513                 }
4514                 tg3_link_report(tp);
4515         }
4516         return err;
4517 }
4518
4519 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4520 {
4521         if (tp->serdes_counter) {
4522                 /* Give autoneg time to complete. */
4523                 tp->serdes_counter--;
4524                 return;
4525         }
4526
4527         if (!netif_carrier_ok(tp->dev) &&
4528             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4529                 u32 bmcr;
4530
4531                 tg3_readphy(tp, MII_BMCR, &bmcr);
4532                 if (bmcr & BMCR_ANENABLE) {
4533                         u32 phy1, phy2;
4534
4535                         /* Select shadow register 0x1f */
4536                         tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4537                         tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4538
4539                         /* Select expansion interrupt status register */
4540                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4541                                          MII_TG3_DSP_EXP1_INT_STAT);
4542                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4543                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4544
4545                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4546                                 /* We have signal detect and not receiving
4547                                  * config code words, link is up by parallel
4548                                  * detection.
4549                                  */
4550
4551                                 bmcr &= ~BMCR_ANENABLE;
4552                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4553                                 tg3_writephy(tp, MII_BMCR, bmcr);
4554                                 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4555                         }
4556                 }
4557         } else if (netif_carrier_ok(tp->dev) &&
4558                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4559                    (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4560                 u32 phy2;
4561
4562                 /* Select expansion interrupt status register */
4563                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4564                                  MII_TG3_DSP_EXP1_INT_STAT);
4565                 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4566                 if (phy2 & 0x20) {
4567                         u32 bmcr;
4568
4569                         /* Config code words received, turn on autoneg. */
4570                         tg3_readphy(tp, MII_BMCR, &bmcr);
4571                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4572
4573                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4574
4575                 }
4576         }
4577 }
4578
4579 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4580 {
4581         u32 val;
4582         int err;
4583
4584         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4585                 err = tg3_setup_fiber_phy(tp, force_reset);
4586         else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4587                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4588         else
4589                 err = tg3_setup_copper_phy(tp, force_reset);
4590
4591         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4592                 u32 scale;
4593
4594                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4595                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4596                         scale = 65;
4597                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4598                         scale = 6;
4599                 else
4600                         scale = 12;
4601
4602                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4603                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4604                 tw32(GRC_MISC_CFG, val);
4605         }
4606
4607         val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4608               (6 << TX_LENGTHS_IPG_SHIFT);
4609         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
4610                 val |= tr32(MAC_TX_LENGTHS) &
4611                        (TX_LENGTHS_JMB_FRM_LEN_MSK |
4612                         TX_LENGTHS_CNT_DWN_VAL_MSK);
4613
4614         if (tp->link_config.active_speed == SPEED_1000 &&
4615             tp->link_config.active_duplex == DUPLEX_HALF)
4616                 tw32(MAC_TX_LENGTHS, val |
4617                      (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
4618         else
4619                 tw32(MAC_TX_LENGTHS, val |
4620                      (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
4621
4622         if (!tg3_flag(tp, 5705_PLUS)) {
4623                 if (netif_carrier_ok(tp->dev)) {
4624                         tw32(HOSTCC_STAT_COAL_TICKS,
4625                              tp->coal.stats_block_coalesce_usecs);
4626                 } else {
4627                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4628                 }
4629         }
4630
4631         if (tg3_flag(tp, ASPM_WORKAROUND)) {
4632                 val = tr32(PCIE_PWR_MGMT_THRESH);
4633                 if (!netif_carrier_ok(tp->dev))
4634                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4635                               tp->pwrmgmt_thresh;
4636                 else
4637                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4638                 tw32(PCIE_PWR_MGMT_THRESH, val);
4639         }
4640
4641         return err;
4642 }
4643
4644 static inline int tg3_irq_sync(struct tg3 *tp)
4645 {
4646         return tp->irq_sync;
4647 }
4648
4649 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
4650 {
4651         int i;
4652
4653         dst = (u32 *)((u8 *)dst + off);
4654         for (i = 0; i < len; i += sizeof(u32))
4655                 *dst++ = tr32(off + i);
4656 }
4657
4658 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
4659 {
4660         tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
4661         tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
4662         tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
4663         tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
4664         tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
4665         tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
4666         tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
4667         tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
4668         tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
4669         tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
4670         tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
4671         tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
4672         tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
4673         tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
4674         tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
4675         tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
4676         tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
4677         tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
4678         tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
4679
4680         if (tg3_flag(tp, SUPPORT_MSIX))
4681                 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
4682
4683         tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
4684         tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
4685         tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
4686         tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
4687         tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
4688         tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
4689         tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
4690         tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
4691
4692         if (!tg3_flag(tp, 5705_PLUS)) {
4693                 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
4694                 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
4695                 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
4696         }
4697
4698         tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
4699         tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
4700         tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
4701         tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
4702         tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
4703
4704         if (tg3_flag(tp, NVRAM))
4705                 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
4706 }
4707
4708 static void tg3_dump_state(struct tg3 *tp)
4709 {
4710         int i;
4711         u32 *regs;
4712
4713         regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
4714         if (!regs) {
4715                 netdev_err(tp->dev, "Failed allocating register dump buffer\n");
4716                 return;
4717         }
4718
4719         if (tg3_flag(tp, PCI_EXPRESS)) {
4720                 /* Read up to but not including private PCI registers */
4721                 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
4722                         regs[i / sizeof(u32)] = tr32(i);
4723         } else
4724                 tg3_dump_legacy_regs(tp, regs);
4725
4726         for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
4727                 if (!regs[i + 0] && !regs[i + 1] &&
4728                     !regs[i + 2] && !regs[i + 3])
4729                         continue;
4730
4731                 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
4732                            i * 4,
4733                            regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
4734         }
4735
4736         kfree(regs);
4737
4738         for (i = 0; i < tp->irq_cnt; i++) {
4739                 struct tg3_napi *tnapi = &tp->napi[i];
4740
4741                 /* SW status block */
4742                 netdev_err(tp->dev,
4743                          "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
4744                            i,
4745                            tnapi->hw_status->status,
4746                            tnapi->hw_status->status_tag,
4747                            tnapi->hw_status->rx_jumbo_consumer,
4748                            tnapi->hw_status->rx_consumer,
4749                            tnapi->hw_status->rx_mini_consumer,
4750                            tnapi->hw_status->idx[0].rx_producer,
4751                            tnapi->hw_status->idx[0].tx_consumer);
4752
4753                 netdev_err(tp->dev,
4754                 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
4755                            i,
4756                            tnapi->last_tag, tnapi->last_irq_tag,
4757                            tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
4758                            tnapi->rx_rcb_ptr,
4759                            tnapi->prodring.rx_std_prod_idx,
4760                            tnapi->prodring.rx_std_cons_idx,
4761                            tnapi->prodring.rx_jmb_prod_idx,
4762                            tnapi->prodring.rx_jmb_cons_idx);
4763         }
4764 }
4765
4766 /* This is called whenever we suspect that the system chipset is re-
4767  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4768  * is bogus tx completions. We try to recover by setting the
4769  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4770  * in the workqueue.
4771  */
4772 static void tg3_tx_recover(struct tg3 *tp)
4773 {
4774         BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
4775                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4776
4777         netdev_warn(tp->dev,
4778                     "The system may be re-ordering memory-mapped I/O "
4779                     "cycles to the network device, attempting to recover. "
4780                     "Please report the problem to the driver maintainer "
4781                     "and include system chipset information.\n");
4782
4783         spin_lock(&tp->lock);
4784         tg3_flag_set(tp, TX_RECOVERY_PENDING);
4785         spin_unlock(&tp->lock);
4786 }
4787
4788 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4789 {
4790         /* Tell compiler to fetch tx indices from memory. */
4791         barrier();
4792         return tnapi->tx_pending -
4793                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4794 }
4795
4796 /* Tigon3 never reports partial packet sends.  So we do not
4797  * need special logic to handle SKBs that have not had all
4798  * of their frags sent yet, like SunGEM does.
4799  */
4800 static void tg3_tx(struct tg3_napi *tnapi)
4801 {
4802         struct tg3 *tp = tnapi->tp;
4803         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4804         u32 sw_idx = tnapi->tx_cons;
4805         struct netdev_queue *txq;
4806         int index = tnapi - tp->napi;
4807
4808         if (tg3_flag(tp, ENABLE_TSS))
4809                 index--;
4810
4811         txq = netdev_get_tx_queue(tp->dev, index);
4812
4813         while (sw_idx != hw_idx) {
4814                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4815                 struct sk_buff *skb = ri->skb;
4816                 int i, tx_bug = 0;
4817
4818                 if (unlikely(skb == NULL)) {
4819                         tg3_tx_recover(tp);
4820                         return;
4821                 }
4822
4823                 pci_unmap_single(tp->pdev,
4824                                  dma_unmap_addr(ri, mapping),
4825                                  skb_headlen(skb),
4826                                  PCI_DMA_TODEVICE);
4827
4828                 ri->skb = NULL;
4829
4830                 sw_idx = NEXT_TX(sw_idx);
4831
4832                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4833                         ri = &tnapi->tx_buffers[sw_idx];
4834                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4835                                 tx_bug = 1;
4836
4837                         pci_unmap_page(tp->pdev,
4838                                        dma_unmap_addr(ri, mapping),
4839                                        skb_shinfo(skb)->frags[i].size,
4840                                        PCI_DMA_TODEVICE);
4841                         sw_idx = NEXT_TX(sw_idx);
4842                 }
4843
4844                 dev_kfree_skb(skb);
4845
4846                 if (unlikely(tx_bug)) {
4847                         tg3_tx_recover(tp);
4848                         return;
4849                 }
4850         }
4851
4852         tnapi->tx_cons = sw_idx;
4853
4854         /* Need to make the tx_cons update visible to tg3_start_xmit()
4855          * before checking for netif_queue_stopped().  Without the
4856          * memory barrier, there is a small possibility that tg3_start_xmit()
4857          * will miss it and cause the queue to be stopped forever.
4858          */
4859         smp_mb();
4860
4861         if (unlikely(netif_tx_queue_stopped(txq) &&
4862                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4863                 __netif_tx_lock(txq, smp_processor_id());
4864                 if (netif_tx_queue_stopped(txq) &&
4865                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4866                         netif_tx_wake_queue(txq);
4867                 __netif_tx_unlock(txq);
4868         }
4869 }
4870
4871 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4872 {
4873         if (!ri->skb)
4874                 return;
4875
4876         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4877                          map_sz, PCI_DMA_FROMDEVICE);
4878         dev_kfree_skb_any(ri->skb);
4879         ri->skb = NULL;
4880 }
4881
4882 /* Returns size of skb allocated or < 0 on error.
4883  *
4884  * We only need to fill in the address because the other members
4885  * of the RX descriptor are invariant, see tg3_init_rings.
4886  *
4887  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4888  * posting buffers we only dirty the first cache line of the RX
4889  * descriptor (containing the address).  Whereas for the RX status
4890  * buffers the cpu only reads the last cacheline of the RX descriptor
4891  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4892  */
4893 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4894                             u32 opaque_key, u32 dest_idx_unmasked)
4895 {
4896         struct tg3_rx_buffer_desc *desc;
4897         struct ring_info *map;
4898         struct sk_buff *skb;
4899         dma_addr_t mapping;
4900         int skb_size, dest_idx;
4901
4902         switch (opaque_key) {
4903         case RXD_OPAQUE_RING_STD:
4904                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4905                 desc = &tpr->rx_std[dest_idx];
4906                 map = &tpr->rx_std_buffers[dest_idx];
4907                 skb_size = tp->rx_pkt_map_sz;
4908                 break;
4909
4910         case RXD_OPAQUE_RING_JUMBO:
4911                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4912                 desc = &tpr->rx_jmb[dest_idx].std;
4913                 map = &tpr->rx_jmb_buffers[dest_idx];
4914                 skb_size = TG3_RX_JMB_MAP_SZ;
4915                 break;
4916
4917         default:
4918                 return -EINVAL;
4919         }
4920
4921         /* Do not overwrite any of the map or rp information
4922          * until we are sure we can commit to a new buffer.
4923          *
4924          * Callers depend upon this behavior and assume that
4925          * we leave everything unchanged if we fail.
4926          */
4927         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4928         if (skb == NULL)
4929                 return -ENOMEM;
4930
4931         skb_reserve(skb, tp->rx_offset);
4932
4933         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4934                                  PCI_DMA_FROMDEVICE);
4935         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4936                 dev_kfree_skb(skb);
4937                 return -EIO;
4938         }
4939
4940         map->skb = skb;
4941         dma_unmap_addr_set(map, mapping, mapping);
4942
4943         desc->addr_hi = ((u64)mapping >> 32);
4944         desc->addr_lo = ((u64)mapping & 0xffffffff);
4945
4946         return skb_size;
4947 }
4948
4949 /* We only need to move over in the address because the other
4950  * members of the RX descriptor are invariant.  See notes above
4951  * tg3_alloc_rx_skb for full details.
4952  */
4953 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4954                            struct tg3_rx_prodring_set *dpr,
4955                            u32 opaque_key, int src_idx,
4956                            u32 dest_idx_unmasked)
4957 {
4958         struct tg3 *tp = tnapi->tp;
4959         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4960         struct ring_info *src_map, *dest_map;
4961         struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
4962         int dest_idx;
4963
4964         switch (opaque_key) {
4965         case RXD_OPAQUE_RING_STD:
4966                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4967                 dest_desc = &dpr->rx_std[dest_idx];
4968                 dest_map = &dpr->rx_std_buffers[dest_idx];
4969                 src_desc = &spr->rx_std[src_idx];
4970                 src_map = &spr->rx_std_buffers[src_idx];
4971                 break;
4972
4973         case RXD_OPAQUE_RING_JUMBO:
4974                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4975                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4976                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4977                 src_desc = &spr->rx_jmb[src_idx].std;
4978                 src_map = &spr->rx_jmb_buffers[src_idx];
4979                 break;
4980
4981         default:
4982                 return;
4983         }
4984
4985         dest_map->skb = src_map->skb;
4986         dma_unmap_addr_set(dest_map, mapping,
4987                            dma_unmap_addr(src_map, mapping));
4988         dest_desc->addr_hi = src_desc->addr_hi;
4989         dest_desc->addr_lo = src_desc->addr_lo;
4990
4991         /* Ensure that the update to the skb happens after the physical
4992          * addresses have been transferred to the new BD location.
4993          */
4994         smp_wmb();
4995
4996         src_map->skb = NULL;
4997 }
4998
4999 /* The RX ring scheme is composed of multiple rings which post fresh
5000  * buffers to the chip, and one special ring the chip uses to report
5001  * status back to the host.
5002  *
5003  * The special ring reports the status of received packets to the
5004  * host.  The chip does not write into the original descriptor the
5005  * RX buffer was obtained from.  The chip simply takes the original
5006  * descriptor as provided by the host, updates the status and length
5007  * field, then writes this into the next status ring entry.
5008  *
5009  * Each ring the host uses to post buffers to the chip is described
5010  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
5011  * it is first placed into the on-chip ram.  When the packet's length
5012  * is known, it walks down the TG3_BDINFO entries to select the ring.
5013  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
5014  * which is within the range of the new packet's length is chosen.
5015  *
5016  * The "separate ring for rx status" scheme may sound queer, but it makes
5017  * sense from a cache coherency perspective.  If only the host writes
5018  * to the buffer post rings, and only the chip writes to the rx status
5019  * rings, then cache lines never move beyond shared-modified state.
5020  * If both the host and chip were to write into the same ring, cache line
5021  * eviction could occur since both entities want it in an exclusive state.
5022  */
5023 static int tg3_rx(struct tg3_napi *tnapi, int budget)
5024 {
5025         struct tg3 *tp = tnapi->tp;
5026         u32 work_mask, rx_std_posted = 0;
5027         u32 std_prod_idx, jmb_prod_idx;
5028         u32 sw_idx = tnapi->rx_rcb_ptr;
5029         u16 hw_idx;
5030         int received;
5031         struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
5032
5033         hw_idx = *(tnapi->rx_rcb_prod_idx);
5034         /*
5035          * We need to order the read of hw_idx and the read of
5036          * the opaque cookie.
5037          */
5038         rmb();
5039         work_mask = 0;
5040         received = 0;
5041         std_prod_idx = tpr->rx_std_prod_idx;
5042         jmb_prod_idx = tpr->rx_jmb_prod_idx;
5043         while (sw_idx != hw_idx && budget > 0) {
5044                 struct ring_info *ri;
5045                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
5046                 unsigned int len;
5047                 struct sk_buff *skb;
5048                 dma_addr_t dma_addr;
5049                 u32 opaque_key, desc_idx, *post_ptr;
5050
5051                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
5052                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
5053                 if (opaque_key == RXD_OPAQUE_RING_STD) {
5054                         ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
5055                         dma_addr = dma_unmap_addr(ri, mapping);
5056                         skb = ri->skb;
5057                         post_ptr = &std_prod_idx;
5058                         rx_std_posted++;
5059                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
5060                         ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
5061                         dma_addr = dma_unmap_addr(ri, mapping);
5062                         skb = ri->skb;
5063                         post_ptr = &jmb_prod_idx;
5064                 } else
5065                         goto next_pkt_nopost;
5066
5067                 work_mask |= opaque_key;
5068
5069                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
5070                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
5071                 drop_it:
5072                         tg3_recycle_rx(tnapi, tpr, opaque_key,
5073                                        desc_idx, *post_ptr);
5074                 drop_it_no_recycle:
5075                         /* Other statistics kept track of by card. */
5076                         tp->rx_dropped++;
5077                         goto next_pkt;
5078                 }
5079
5080                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
5081                       ETH_FCS_LEN;
5082
5083                 if (len > TG3_RX_COPY_THRESH(tp)) {
5084                         int skb_size;
5085
5086                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
5087                                                     *post_ptr);
5088                         if (skb_size < 0)
5089                                 goto drop_it;
5090
5091                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
5092                                          PCI_DMA_FROMDEVICE);
5093
5094                         /* Ensure that the update to the skb happens
5095                          * after the usage of the old DMA mapping.
5096                          */
5097                         smp_wmb();
5098
5099                         ri->skb = NULL;
5100
5101                         skb_put(skb, len);
5102                 } else {
5103                         struct sk_buff *copy_skb;
5104
5105                         tg3_recycle_rx(tnapi, tpr, opaque_key,
5106                                        desc_idx, *post_ptr);
5107
5108                         copy_skb = netdev_alloc_skb(tp->dev, len +
5109                                                     TG3_RAW_IP_ALIGN);
5110                         if (copy_skb == NULL)
5111                                 goto drop_it_no_recycle;
5112
5113                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
5114                         skb_put(copy_skb, len);
5115                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
5116                         skb_copy_from_linear_data(skb, copy_skb->data, len);
5117                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
5118
5119                         /* We'll reuse the original ring buffer. */
5120                         skb = copy_skb;
5121                 }
5122
5123                 if ((tp->dev->features & NETIF_F_RXCSUM) &&
5124                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
5125                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
5126                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
5127                         skb->ip_summed = CHECKSUM_UNNECESSARY;
5128                 else
5129                         skb_checksum_none_assert(skb);
5130
5131                 skb->protocol = eth_type_trans(skb, tp->dev);
5132
5133                 if (len > (tp->dev->mtu + ETH_HLEN) &&
5134                     skb->protocol != htons(ETH_P_8021Q)) {
5135                         dev_kfree_skb(skb);
5136                         goto drop_it_no_recycle;
5137                 }
5138
5139                 if (desc->type_flags & RXD_FLAG_VLAN &&
5140                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
5141                         __vlan_hwaccel_put_tag(skb,
5142                                                desc->err_vlan & RXD_VLAN_MASK);
5143
5144                 napi_gro_receive(&tnapi->napi, skb);
5145
5146                 received++;
5147                 budget--;
5148
5149 next_pkt:
5150                 (*post_ptr)++;
5151
5152                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
5153                         tpr->rx_std_prod_idx = std_prod_idx &
5154                                                tp->rx_std_ring_mask;
5155                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5156                                      tpr->rx_std_prod_idx);
5157                         work_mask &= ~RXD_OPAQUE_RING_STD;
5158                         rx_std_posted = 0;
5159                 }
5160 next_pkt_nopost:
5161                 sw_idx++;
5162                 sw_idx &= tp->rx_ret_ring_mask;
5163
5164                 /* Refresh hw_idx to see if there is new work */
5165                 if (sw_idx == hw_idx) {
5166                         hw_idx = *(tnapi->rx_rcb_prod_idx);
5167                         rmb();
5168                 }
5169         }
5170
5171         /* ACK the status ring. */
5172         tnapi->rx_rcb_ptr = sw_idx;
5173         tw32_rx_mbox(tnapi->consmbox, sw_idx);
5174
5175         /* Refill RX ring(s). */
5176         if (!tg3_flag(tp, ENABLE_RSS)) {
5177                 if (work_mask & RXD_OPAQUE_RING_STD) {
5178                         tpr->rx_std_prod_idx = std_prod_idx &
5179                                                tp->rx_std_ring_mask;
5180                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5181                                      tpr->rx_std_prod_idx);
5182                 }
5183                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
5184                         tpr->rx_jmb_prod_idx = jmb_prod_idx &
5185                                                tp->rx_jmb_ring_mask;
5186                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5187                                      tpr->rx_jmb_prod_idx);
5188                 }
5189                 mmiowb();
5190         } else if (work_mask) {
5191                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
5192                  * updated before the producer indices can be updated.
5193                  */
5194                 smp_wmb();
5195
5196                 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
5197                 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
5198
5199                 if (tnapi != &tp->napi[1])
5200                         napi_schedule(&tp->napi[1].napi);
5201         }
5202
5203         return received;
5204 }
5205
5206 static void tg3_poll_link(struct tg3 *tp)
5207 {
5208         /* handle link change and other phy events */
5209         if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
5210                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
5211
5212                 if (sblk->status & SD_STATUS_LINK_CHG) {
5213                         sblk->status = SD_STATUS_UPDATED |
5214                                        (sblk->status & ~SD_STATUS_LINK_CHG);
5215                         spin_lock(&tp->lock);
5216                         if (tg3_flag(tp, USE_PHYLIB)) {
5217                                 tw32_f(MAC_STATUS,
5218                                      (MAC_STATUS_SYNC_CHANGED |
5219                                       MAC_STATUS_CFG_CHANGED |
5220                                       MAC_STATUS_MI_COMPLETION |
5221                                       MAC_STATUS_LNKSTATE_CHANGED));
5222                                 udelay(40);
5223                         } else
5224                                 tg3_setup_phy(tp, 0);
5225                         spin_unlock(&tp->lock);
5226                 }
5227         }
5228 }
5229
5230 static int tg3_rx_prodring_xfer(struct tg3 *tp,
5231                                 struct tg3_rx_prodring_set *dpr,
5232                                 struct tg3_rx_prodring_set *spr)
5233 {
5234         u32 si, di, cpycnt, src_prod_idx;
5235         int i, err = 0;
5236
5237         while (1) {
5238                 src_prod_idx = spr->rx_std_prod_idx;
5239
5240                 /* Make sure updates to the rx_std_buffers[] entries and the
5241                  * standard producer index are seen in the correct order.
5242                  */
5243                 smp_rmb();
5244
5245                 if (spr->rx_std_cons_idx == src_prod_idx)
5246                         break;
5247
5248                 if (spr->rx_std_cons_idx < src_prod_idx)
5249                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
5250                 else
5251                         cpycnt = tp->rx_std_ring_mask + 1 -
5252                                  spr->rx_std_cons_idx;
5253
5254                 cpycnt = min(cpycnt,
5255                              tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
5256
5257                 si = spr->rx_std_cons_idx;
5258                 di = dpr->rx_std_prod_idx;
5259
5260                 for (i = di; i < di + cpycnt; i++) {
5261                         if (dpr->rx_std_buffers[i].skb) {
5262                                 cpycnt = i - di;
5263                                 err = -ENOSPC;
5264                                 break;
5265                         }
5266                 }
5267
5268                 if (!cpycnt)
5269                         break;
5270
5271                 /* Ensure that updates to the rx_std_buffers ring and the
5272                  * shadowed hardware producer ring from tg3_recycle_skb() are
5273                  * ordered correctly WRT the skb check above.
5274                  */
5275                 smp_rmb();
5276
5277                 memcpy(&dpr->rx_std_buffers[di],
5278                        &spr->rx_std_buffers[si],
5279                        cpycnt * sizeof(struct ring_info));
5280
5281                 for (i = 0; i < cpycnt; i++, di++, si++) {
5282                         struct tg3_rx_buffer_desc *sbd, *dbd;
5283                         sbd = &spr->rx_std[si];
5284                         dbd = &dpr->rx_std[di];
5285                         dbd->addr_hi = sbd->addr_hi;
5286                         dbd->addr_lo = sbd->addr_lo;
5287                 }
5288
5289                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
5290                                        tp->rx_std_ring_mask;
5291                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
5292                                        tp->rx_std_ring_mask;
5293         }
5294
5295         while (1) {
5296                 src_prod_idx = spr->rx_jmb_prod_idx;
5297
5298                 /* Make sure updates to the rx_jmb_buffers[] entries and
5299                  * the jumbo producer index are seen in the correct order.
5300                  */
5301                 smp_rmb();
5302
5303                 if (spr->rx_jmb_cons_idx == src_prod_idx)
5304                         break;
5305
5306                 if (spr->rx_jmb_cons_idx < src_prod_idx)
5307                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
5308                 else
5309                         cpycnt = tp->rx_jmb_ring_mask + 1 -
5310                                  spr->rx_jmb_cons_idx;
5311
5312                 cpycnt = min(cpycnt,
5313                              tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
5314
5315                 si = spr->rx_jmb_cons_idx;
5316                 di = dpr->rx_jmb_prod_idx;
5317
5318                 for (i = di; i < di + cpycnt; i++) {
5319                         if (dpr->rx_jmb_buffers[i].skb) {
5320                                 cpycnt = i - di;
5321                                 err = -ENOSPC;
5322                                 break;
5323                         }
5324                 }
5325
5326                 if (!cpycnt)
5327                         break;
5328
5329                 /* Ensure that updates to the rx_jmb_buffers ring and the
5330                  * shadowed hardware producer ring from tg3_recycle_skb() are
5331                  * ordered correctly WRT the skb check above.
5332                  */
5333                 smp_rmb();
5334
5335                 memcpy(&dpr->rx_jmb_buffers[di],
5336                        &spr->rx_jmb_buffers[si],
5337                        cpycnt * sizeof(struct ring_info));
5338
5339                 for (i = 0; i < cpycnt; i++, di++, si++) {
5340                         struct tg3_rx_buffer_desc *sbd, *dbd;
5341                         sbd = &spr->rx_jmb[si].std;
5342                         dbd = &dpr->rx_jmb[di].std;
5343                         dbd->addr_hi = sbd->addr_hi;
5344                         dbd->addr_lo = sbd->addr_lo;
5345                 }
5346
5347                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
5348                                        tp->rx_jmb_ring_mask;
5349                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
5350                                        tp->rx_jmb_ring_mask;
5351         }
5352
5353         return err;
5354 }
5355
5356 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
5357 {
5358         struct tg3 *tp = tnapi->tp;
5359
5360         /* run TX completion thread */
5361         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
5362                 tg3_tx(tnapi);
5363                 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
5364                         return work_done;
5365         }
5366
5367         /* run RX thread, within the bounds set by NAPI.
5368          * All RX "locking" is done by ensuring outside
5369          * code synchronizes with tg3->napi.poll()
5370          */
5371         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
5372                 work_done += tg3_rx(tnapi, budget - work_done);
5373
5374         if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
5375                 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
5376                 int i, err = 0;
5377                 u32 std_prod_idx = dpr->rx_std_prod_idx;
5378                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
5379
5380                 for (i = 1; i < tp->irq_cnt; i++)
5381                         err |= tg3_rx_prodring_xfer(tp, dpr,
5382                                                     &tp->napi[i].prodring);
5383
5384                 wmb();
5385
5386                 if (std_prod_idx != dpr->rx_std_prod_idx)
5387                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5388                                      dpr->rx_std_prod_idx);
5389
5390                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5391                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5392                                      dpr->rx_jmb_prod_idx);
5393
5394                 mmiowb();
5395
5396                 if (err)
5397                         tw32_f(HOSTCC_MODE, tp->coal_now);
5398         }
5399
5400         return work_done;
5401 }
5402
5403 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5404 {
5405         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5406         struct tg3 *tp = tnapi->tp;
5407         int work_done = 0;
5408         struct tg3_hw_status *sblk = tnapi->hw_status;
5409
5410         while (1) {
5411                 work_done = tg3_poll_work(tnapi, work_done, budget);
5412
5413                 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
5414                         goto tx_recovery;
5415
5416                 if (unlikely(work_done >= budget))
5417                         break;
5418
5419                 /* tp->last_tag is used in tg3_int_reenable() below
5420                  * to tell the hw how much work has been processed,
5421                  * so we must read it before checking for more work.
5422                  */
5423                 tnapi->last_tag = sblk->status_tag;
5424                 tnapi->last_irq_tag = tnapi->last_tag;
5425                 rmb();
5426
5427                 /* check for RX/TX work to do */
5428                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5429                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5430                         napi_complete(napi);
5431                         /* Reenable interrupts. */
5432                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5433                         mmiowb();
5434                         break;
5435                 }
5436         }
5437
5438         return work_done;
5439
5440 tx_recovery:
5441         /* work_done is guaranteed to be less than budget. */
5442         napi_complete(napi);
5443         schedule_work(&tp->reset_task);
5444         return work_done;
5445 }
5446
5447 static void tg3_process_error(struct tg3 *tp)
5448 {
5449         u32 val;
5450         bool real_error = false;
5451
5452         if (tg3_flag(tp, ERROR_PROCESSED))
5453                 return;
5454
5455         /* Check Flow Attention register */
5456         val = tr32(HOSTCC_FLOW_ATTN);
5457         if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
5458                 netdev_err(tp->dev, "FLOW Attention error.  Resetting chip.\n");
5459                 real_error = true;
5460         }
5461
5462         if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
5463                 netdev_err(tp->dev, "MSI Status error.  Resetting chip.\n");
5464                 real_error = true;
5465         }
5466
5467         if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
5468                 netdev_err(tp->dev, "DMA Status error.  Resetting chip.\n");
5469                 real_error = true;
5470         }
5471
5472         if (!real_error)
5473                 return;
5474
5475         tg3_dump_state(tp);
5476
5477         tg3_flag_set(tp, ERROR_PROCESSED);
5478         schedule_work(&tp->reset_task);
5479 }
5480
5481 static int tg3_poll(struct napi_struct *napi, int budget)
5482 {
5483         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5484         struct tg3 *tp = tnapi->tp;
5485         int work_done = 0;
5486         struct tg3_hw_status *sblk = tnapi->hw_status;
5487
5488         while (1) {
5489                 if (sblk->status & SD_STATUS_ERROR)
5490                         tg3_process_error(tp);
5491
5492                 tg3_poll_link(tp);
5493
5494                 work_done = tg3_poll_work(tnapi, work_done, budget);
5495
5496                 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
5497                         goto tx_recovery;
5498
5499                 if (unlikely(work_done >= budget))
5500                         break;
5501
5502                 if (tg3_flag(tp, TAGGED_STATUS)) {
5503                         /* tp->last_tag is used in tg3_int_reenable() below
5504                          * to tell the hw how much work has been processed,
5505                          * so we must read it before checking for more work.
5506                          */
5507                         tnapi->last_tag = sblk->status_tag;
5508                         tnapi->last_irq_tag = tnapi->last_tag;
5509                         rmb();
5510                 } else
5511                         sblk->status &= ~SD_STATUS_UPDATED;
5512
5513                 if (likely(!tg3_has_work(tnapi))) {
5514                         napi_complete(napi);
5515                         tg3_int_reenable(tnapi);
5516                         break;
5517                 }
5518         }
5519
5520         return work_done;
5521
5522 tx_recovery:
5523         /* work_done is guaranteed to be less than budget. */
5524         napi_complete(napi);
5525         schedule_work(&tp->reset_task);
5526         return work_done;
5527 }
5528
5529 static void tg3_napi_disable(struct tg3 *tp)
5530 {
5531         int i;
5532
5533         for (i = tp->irq_cnt - 1; i >= 0; i--)
5534                 napi_disable(&tp->napi[i].napi);
5535 }
5536
5537 static void tg3_napi_enable(struct tg3 *tp)
5538 {
5539         int i;
5540
5541         for (i = 0; i < tp->irq_cnt; i++)
5542                 napi_enable(&tp->napi[i].napi);
5543 }
5544
5545 static void tg3_napi_init(struct tg3 *tp)
5546 {
5547         int i;
5548
5549         netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
5550         for (i = 1; i < tp->irq_cnt; i++)
5551                 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
5552 }
5553
5554 static void tg3_napi_fini(struct tg3 *tp)
5555 {
5556         int i;
5557
5558         for (i = 0; i < tp->irq_cnt; i++)
5559                 netif_napi_del(&tp->napi[i].napi);
5560 }
5561
5562 static inline void tg3_netif_stop(struct tg3 *tp)
5563 {
5564         tp->dev->trans_start = jiffies; /* prevent tx timeout */
5565         tg3_napi_disable(tp);
5566         netif_tx_disable(tp->dev);
5567 }
5568
5569 static inline void tg3_netif_start(struct tg3 *tp)
5570 {
5571         /* NOTE: unconditional netif_tx_wake_all_queues is only
5572          * appropriate so long as all callers are assured to
5573          * have free tx slots (such as after tg3_init_hw)
5574          */
5575         netif_tx_wake_all_queues(tp->dev);
5576
5577         tg3_napi_enable(tp);
5578         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
5579         tg3_enable_ints(tp);
5580 }
5581
5582 static void tg3_irq_quiesce(struct tg3 *tp)
5583 {
5584         int i;
5585
5586         BUG_ON(tp->irq_sync);
5587
5588         tp->irq_sync = 1;
5589         smp_mb();
5590
5591         for (i = 0; i < tp->irq_cnt; i++)
5592                 synchronize_irq(tp->napi[i].irq_vec);
5593 }
5594
5595 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5596  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5597  * with as well.  Most of the time, this is not necessary except when
5598  * shutting down the device.
5599  */
5600 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5601 {
5602         spin_lock_bh(&tp->lock);
5603         if (irq_sync)
5604                 tg3_irq_quiesce(tp);
5605 }
5606
5607 static inline void tg3_full_unlock(struct tg3 *tp)
5608 {
5609         spin_unlock_bh(&tp->lock);
5610 }
5611
5612 /* One-shot MSI handler - Chip automatically disables interrupt
5613  * after sending MSI so driver doesn't have to do it.
5614  */
5615 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5616 {
5617         struct tg3_napi *tnapi = dev_id;
5618         struct tg3 *tp = tnapi->tp;
5619
5620         prefetch(tnapi->hw_status);
5621         if (tnapi->rx_rcb)
5622                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5623
5624         if (likely(!tg3_irq_sync(tp)))
5625                 napi_schedule(&tnapi->napi);
5626
5627         return IRQ_HANDLED;
5628 }
5629
5630 /* MSI ISR - No need to check for interrupt sharing and no need to
5631  * flush status block and interrupt mailbox. PCI ordering rules
5632  * guarantee that MSI will arrive after the status block.
5633  */
5634 static irqreturn_t tg3_msi(int irq, void *dev_id)
5635 {
5636         struct tg3_napi *tnapi = dev_id;
5637         struct tg3 *tp = tnapi->tp;
5638
5639         prefetch(tnapi->hw_status);
5640         if (tnapi->rx_rcb)
5641                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5642         /*
5643          * Writing any value to intr-mbox-0 clears PCI INTA# and
5644          * chip-internal interrupt pending events.
5645          * Writing non-zero to intr-mbox-0 additional tells the
5646          * NIC to stop sending us irqs, engaging "in-intr-handler"
5647          * event coalescing.
5648          */
5649         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5650         if (likely(!tg3_irq_sync(tp)))
5651                 napi_schedule(&tnapi->napi);
5652
5653         return IRQ_RETVAL(1);
5654 }
5655
5656 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5657 {
5658         struct tg3_napi *tnapi = dev_id;
5659         struct tg3 *tp = tnapi->tp;
5660         struct tg3_hw_status *sblk = tnapi->hw_status;
5661         unsigned int handled = 1;
5662
5663         /* In INTx mode, it is possible for the interrupt to arrive at
5664          * the CPU before the status block posted prior to the interrupt.
5665          * Reading the PCI State register will confirm whether the
5666          * interrupt is ours and will flush the status block.
5667          */
5668         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5669                 if (tg3_flag(tp, CHIP_RESETTING) ||
5670                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5671                         handled = 0;
5672                         goto out;
5673                 }
5674         }
5675
5676         /*
5677          * Writing any value to intr-mbox-0 clears PCI INTA# and
5678          * chip-internal interrupt pending events.
5679          * Writing non-zero to intr-mbox-0 additional tells the
5680          * NIC to stop sending us irqs, engaging "in-intr-handler"
5681          * event coalescing.
5682          *
5683          * Flush the mailbox to de-assert the IRQ immediately to prevent
5684          * spurious interrupts.  The flush impacts performance but
5685          * excessive spurious interrupts can be worse in some cases.
5686          */
5687         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5688         if (tg3_irq_sync(tp))
5689                 goto out;
5690         sblk->status &= ~SD_STATUS_UPDATED;
5691         if (likely(tg3_has_work(tnapi))) {
5692                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5693                 napi_schedule(&tnapi->napi);
5694         } else {
5695                 /* No work, shared interrupt perhaps?  re-enable
5696                  * interrupts, and flush that PCI write
5697                  */
5698                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5699                                0x00000000);
5700         }
5701 out:
5702         return IRQ_RETVAL(handled);
5703 }
5704
5705 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5706 {
5707         struct tg3_napi *tnapi = dev_id;
5708         struct tg3 *tp = tnapi->tp;
5709         struct tg3_hw_status *sblk = tnapi->hw_status;
5710         unsigned int handled = 1;
5711
5712         /* In INTx mode, it is possible for the interrupt to arrive at
5713          * the CPU before the status block posted prior to the interrupt.
5714          * Reading the PCI State register will confirm whether the
5715          * interrupt is ours and will flush the status block.
5716          */
5717         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5718                 if (tg3_flag(tp, CHIP_RESETTING) ||
5719                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5720                         handled = 0;
5721                         goto out;
5722                 }
5723         }
5724
5725         /*
5726          * writing any value to intr-mbox-0 clears PCI INTA# and
5727          * chip-internal interrupt pending events.
5728          * writing non-zero to intr-mbox-0 additional tells the
5729          * NIC to stop sending us irqs, engaging "in-intr-handler"
5730          * event coalescing.
5731          *
5732          * Flush the mailbox to de-assert the IRQ immediately to prevent
5733          * spurious interrupts.  The flush impacts performance but
5734          * excessive spurious interrupts can be worse in some cases.
5735          */
5736         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5737
5738         /*
5739          * In a shared interrupt configuration, sometimes other devices'
5740          * interrupts will scream.  We record the current status tag here
5741          * so that the above check can report that the screaming interrupts
5742          * are unhandled.  Eventually they will be silenced.
5743          */
5744         tnapi->last_irq_tag = sblk->status_tag;
5745
5746         if (tg3_irq_sync(tp))
5747                 goto out;
5748
5749         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5750
5751         napi_schedule(&tnapi->napi);
5752
5753 out:
5754         return IRQ_RETVAL(handled);
5755 }
5756
5757 /* ISR for interrupt test */
5758 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5759 {
5760         struct tg3_napi *tnapi = dev_id;
5761         struct tg3 *tp = tnapi->tp;
5762         struct tg3_hw_status *sblk = tnapi->hw_status;
5763
5764         if ((sblk->status & SD_STATUS_UPDATED) ||
5765             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5766                 tg3_disable_ints(tp);
5767                 return IRQ_RETVAL(1);
5768         }
5769         return IRQ_RETVAL(0);
5770 }
5771
5772 static int tg3_init_hw(struct tg3 *, int);
5773 static int tg3_halt(struct tg3 *, int, int);
5774
5775 /* Restart hardware after configuration changes, self-test, etc.
5776  * Invoked with tp->lock held.
5777  */
5778 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5779         __releases(tp->lock)
5780         __acquires(tp->lock)
5781 {
5782         int err;
5783
5784         err = tg3_init_hw(tp, reset_phy);
5785         if (err) {
5786                 netdev_err(tp->dev,
5787                            "Failed to re-initialize device, aborting\n");
5788                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5789                 tg3_full_unlock(tp);
5790                 del_timer_sync(&tp->timer);
5791                 tp->irq_sync = 0;
5792                 tg3_napi_enable(tp);
5793                 dev_close(tp->dev);
5794                 tg3_full_lock(tp, 0);
5795         }
5796         return err;
5797 }
5798
5799 #ifdef CONFIG_NET_POLL_CONTROLLER
5800 static void tg3_poll_controller(struct net_device *dev)
5801 {
5802         int i;
5803         struct tg3 *tp = netdev_priv(dev);
5804
5805         for (i = 0; i < tp->irq_cnt; i++)
5806                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5807 }
5808 #endif
5809
5810 static void tg3_reset_task(struct work_struct *work)
5811 {
5812         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5813         int err;
5814         unsigned int restart_timer;
5815
5816         tg3_full_lock(tp, 0);
5817
5818         if (!netif_running(tp->dev)) {
5819                 tg3_full_unlock(tp);
5820                 return;
5821         }
5822
5823         tg3_full_unlock(tp);
5824
5825         tg3_phy_stop(tp);
5826
5827         tg3_netif_stop(tp);
5828
5829         tg3_full_lock(tp, 1);
5830
5831         restart_timer = tg3_flag(tp, RESTART_TIMER);
5832         tg3_flag_clear(tp, RESTART_TIMER);
5833
5834         if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
5835                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5836                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5837                 tg3_flag_set(tp, MBOX_WRITE_REORDER);
5838                 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
5839         }
5840
5841         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5842         err = tg3_init_hw(tp, 1);
5843         if (err)
5844                 goto out;
5845
5846         tg3_netif_start(tp);
5847
5848         if (restart_timer)
5849                 mod_timer(&tp->timer, jiffies + 1);
5850
5851 out:
5852         tg3_full_unlock(tp);
5853
5854         if (!err)
5855                 tg3_phy_start(tp);
5856 }
5857
5858 static void tg3_tx_timeout(struct net_device *dev)
5859 {
5860         struct tg3 *tp = netdev_priv(dev);
5861
5862         if (netif_msg_tx_err(tp)) {
5863                 netdev_err(dev, "transmit timed out, resetting\n");
5864                 tg3_dump_state(tp);
5865         }
5866
5867         schedule_work(&tp->reset_task);