2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2011 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioport.h>
31 #include <linux/pci.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/skbuff.h>
35 #include <linux/ethtool.h>
36 #include <linux/mdio.h>
37 #include <linux/mii.h>
38 #include <linux/phy.h>
39 #include <linux/brcmphy.h>
40 #include <linux/if_vlan.h>
42 #include <linux/tcp.h>
43 #include <linux/workqueue.h>
44 #include <linux/prefetch.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/firmware.h>
48 #include <net/checksum.h>
51 #include <asm/system.h>
53 #include <asm/byteorder.h>
54 #include <linux/uaccess.h>
57 #include <asm/idprom.h>
66 /* Functions & macros to verify TG3_FLAGS types */
68 static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
70 return test_bit(flag, bits);
73 static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
78 static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
80 clear_bit(flag, bits);
83 #define tg3_flag(tp, flag) \
84 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
85 #define tg3_flag_set(tp, flag) \
86 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
87 #define tg3_flag_clear(tp, flag) \
88 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
90 #define DRV_MODULE_NAME "tg3"
92 #define TG3_MIN_NUM 119
93 #define DRV_MODULE_VERSION \
94 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
95 #define DRV_MODULE_RELDATE "May 18, 2011"
97 #define TG3_DEF_MAC_MODE 0
98 #define TG3_DEF_RX_MODE 0
99 #define TG3_DEF_TX_MODE 0
100 #define TG3_DEF_MSG_ENABLE \
110 #define TG3_GRC_LCLCTL_PWRSW_DELAY 100
112 /* length of time before we decide the hardware is borked,
113 * and dev->tx_timeout() should be called to fix the problem
116 #define TG3_TX_TIMEOUT (5 * HZ)
118 /* hardware minimum and maximum for a single frame's data payload */
119 #define TG3_MIN_MTU 60
120 #define TG3_MAX_MTU(tp) \
121 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
123 /* These numbers seem to be hard coded in the NIC firmware somehow.
124 * You can't change the ring sizes, but you can change where you place
125 * them in the NIC onboard memory.
127 #define TG3_RX_STD_RING_SIZE(tp) \
128 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
129 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
130 #define TG3_DEF_RX_RING_PENDING 200
131 #define TG3_RX_JMB_RING_SIZE(tp) \
132 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
133 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
134 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
135 #define TG3_RSS_INDIR_TBL_SIZE 128
137 /* Do not place this n-ring entries value into the tp struct itself,
138 * we really want to expose these constants to GCC so that modulo et
139 * al. operations are done with shifts and masks instead of with
140 * hw multiply/modulo instructions. Another solution would be to
141 * replace things like '% foo' with '& (foo - 1)'.
144 #define TG3_TX_RING_SIZE 512
145 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
147 #define TG3_RX_STD_RING_BYTES(tp) \
148 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
149 #define TG3_RX_JMB_RING_BYTES(tp) \
150 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
151 #define TG3_RX_RCB_RING_BYTES(tp) \
152 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
153 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
155 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
157 #define TG3_DMA_BYTE_ENAB 64
159 #define TG3_RX_STD_DMA_SZ 1536
160 #define TG3_RX_JMB_DMA_SZ 9046
162 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
164 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
165 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
167 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
168 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
170 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
171 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
173 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
174 * that are at least dword aligned when used in PCIX mode. The driver
175 * works around this bug by double copying the packet. This workaround
176 * is built into the normal double copy length check for efficiency.
178 * However, the double copy is only necessary on those architectures
179 * where unaligned memory accesses are inefficient. For those architectures
180 * where unaligned memory accesses incur little penalty, we can reintegrate
181 * the 5701 in the normal rx path. Doing so saves a device structure
182 * dereference by hardcoding the double copy threshold in place.
184 #define TG3_RX_COPY_THRESHOLD 256
185 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
186 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
188 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
191 /* minimum number of free TX descriptors required to wake up TX process */
192 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
194 #define TG3_RAW_IP_ALIGN 2
196 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
198 #define FIRMWARE_TG3 "tigon/tg3.bin"
199 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
200 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
202 static char version[] __devinitdata =
203 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
205 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
206 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
207 MODULE_LICENSE("GPL");
208 MODULE_VERSION(DRV_MODULE_VERSION);
209 MODULE_FIRMWARE(FIRMWARE_TG3);
210 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
211 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
213 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
214 module_param(tg3_debug, int, 0);
215 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
217 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
260 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
261 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
264 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
275 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
278 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
281 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
286 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
287 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
288 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
289 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
290 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
291 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
292 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
293 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
294 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
295 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
296 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
297 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
298 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
302 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
304 static const struct {
305 const char string[ETH_GSTRING_LEN];
306 } ethtool_stats_keys[] = {
309 { "rx_ucast_packets" },
310 { "rx_mcast_packets" },
311 { "rx_bcast_packets" },
313 { "rx_align_errors" },
314 { "rx_xon_pause_rcvd" },
315 { "rx_xoff_pause_rcvd" },
316 { "rx_mac_ctrl_rcvd" },
317 { "rx_xoff_entered" },
318 { "rx_frame_too_long_errors" },
320 { "rx_undersize_packets" },
321 { "rx_in_length_errors" },
322 { "rx_out_length_errors" },
323 { "rx_64_or_less_octet_packets" },
324 { "rx_65_to_127_octet_packets" },
325 { "rx_128_to_255_octet_packets" },
326 { "rx_256_to_511_octet_packets" },
327 { "rx_512_to_1023_octet_packets" },
328 { "rx_1024_to_1522_octet_packets" },
329 { "rx_1523_to_2047_octet_packets" },
330 { "rx_2048_to_4095_octet_packets" },
331 { "rx_4096_to_8191_octet_packets" },
332 { "rx_8192_to_9022_octet_packets" },
339 { "tx_flow_control" },
341 { "tx_single_collisions" },
342 { "tx_mult_collisions" },
344 { "tx_excessive_collisions" },
345 { "tx_late_collisions" },
346 { "tx_collide_2times" },
347 { "tx_collide_3times" },
348 { "tx_collide_4times" },
349 { "tx_collide_5times" },
350 { "tx_collide_6times" },
351 { "tx_collide_7times" },
352 { "tx_collide_8times" },
353 { "tx_collide_9times" },
354 { "tx_collide_10times" },
355 { "tx_collide_11times" },
356 { "tx_collide_12times" },
357 { "tx_collide_13times" },
358 { "tx_collide_14times" },
359 { "tx_collide_15times" },
360 { "tx_ucast_packets" },
361 { "tx_mcast_packets" },
362 { "tx_bcast_packets" },
363 { "tx_carrier_sense_errors" },
367 { "dma_writeq_full" },
368 { "dma_write_prioq_full" },
372 { "rx_threshold_hit" },
374 { "dma_readq_full" },
375 { "dma_read_prioq_full" },
376 { "tx_comp_queue_full" },
378 { "ring_set_send_prod_index" },
379 { "ring_status_update" },
381 { "nic_avoided_irqs" },
382 { "nic_tx_threshold_hit" },
384 { "mbuf_lwm_thresh_hit" },
387 #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
390 static const struct {
391 const char string[ETH_GSTRING_LEN];
392 } ethtool_test_keys[] = {
393 { "nvram test (online) " },
394 { "link test (online) " },
395 { "register test (offline)" },
396 { "memory test (offline)" },
397 { "loopback test (offline)" },
398 { "interrupt test (offline)" },
401 #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
404 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
406 writel(val, tp->regs + off);
409 static u32 tg3_read32(struct tg3 *tp, u32 off)
411 return readl(tp->regs + off);
414 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
416 writel(val, tp->aperegs + off);
419 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
421 return readl(tp->aperegs + off);
424 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
428 spin_lock_irqsave(&tp->indirect_lock, flags);
429 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
430 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
431 spin_unlock_irqrestore(&tp->indirect_lock, flags);
434 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
436 writel(val, tp->regs + off);
437 readl(tp->regs + off);
440 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
445 spin_lock_irqsave(&tp->indirect_lock, flags);
446 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
447 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
448 spin_unlock_irqrestore(&tp->indirect_lock, flags);
452 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
456 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
457 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
458 TG3_64BIT_REG_LOW, val);
461 if (off == TG3_RX_STD_PROD_IDX_REG) {
462 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
463 TG3_64BIT_REG_LOW, val);
467 spin_lock_irqsave(&tp->indirect_lock, flags);
468 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
469 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
470 spin_unlock_irqrestore(&tp->indirect_lock, flags);
472 /* In indirect mode when disabling interrupts, we also need
473 * to clear the interrupt bit in the GRC local ctrl register.
475 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
477 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
478 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
482 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
487 spin_lock_irqsave(&tp->indirect_lock, flags);
488 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
489 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
490 spin_unlock_irqrestore(&tp->indirect_lock, flags);
494 /* usec_wait specifies the wait time in usec when writing to certain registers
495 * where it is unsafe to read back the register without some delay.
496 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
497 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
499 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
501 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
502 /* Non-posted methods */
503 tp->write32(tp, off, val);
506 tg3_write32(tp, off, val);
511 /* Wait again after the read for the posted method to guarantee that
512 * the wait time is met.
518 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
520 tp->write32_mbox(tp, off, val);
521 if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
522 tp->read32_mbox(tp, off);
525 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
527 void __iomem *mbox = tp->regs + off;
529 if (tg3_flag(tp, TXD_MBOX_HWBUG))
531 if (tg3_flag(tp, MBOX_WRITE_REORDER))
535 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
537 return readl(tp->regs + off + GRCMBOX_BASE);
540 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
542 writel(val, tp->regs + off + GRCMBOX_BASE);
545 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
546 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
547 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
548 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
549 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
551 #define tw32(reg, val) tp->write32(tp, reg, val)
552 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
553 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
554 #define tr32(reg) tp->read32(tp, reg)
556 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
560 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
561 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
564 spin_lock_irqsave(&tp->indirect_lock, flags);
565 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
566 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
567 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
569 /* Always leave this as zero. */
570 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
572 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
573 tw32_f(TG3PCI_MEM_WIN_DATA, val);
575 /* Always leave this as zero. */
576 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
578 spin_unlock_irqrestore(&tp->indirect_lock, flags);
581 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
585 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
586 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
591 spin_lock_irqsave(&tp->indirect_lock, flags);
592 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
593 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
594 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
596 /* Always leave this as zero. */
597 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
599 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
600 *val = tr32(TG3PCI_MEM_WIN_DATA);
602 /* Always leave this as zero. */
603 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
605 spin_unlock_irqrestore(&tp->indirect_lock, flags);
608 static void tg3_ape_lock_init(struct tg3 *tp)
613 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
614 regbase = TG3_APE_LOCK_GRANT;
616 regbase = TG3_APE_PER_LOCK_GRANT;
618 /* Make sure the driver hasn't any stale locks. */
619 for (i = 0; i < 8; i++) {
620 if (i == TG3_APE_LOCK_GPIO)
622 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
625 /* Clear the correct bit of the GPIO lock too. */
627 bit = APE_LOCK_GRANT_DRIVER;
629 bit = 1 << tp->pci_fn;
631 tg3_ape_write32(tp, regbase + 4 * TG3_APE_LOCK_GPIO, bit);
634 static int tg3_ape_lock(struct tg3 *tp, int locknum)
638 u32 status, req, gnt, bit;
640 if (!tg3_flag(tp, ENABLE_APE))
644 case TG3_APE_LOCK_GPIO:
645 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
647 case TG3_APE_LOCK_GRC:
648 case TG3_APE_LOCK_MEM:
654 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
655 req = TG3_APE_LOCK_REQ;
656 gnt = TG3_APE_LOCK_GRANT;
658 req = TG3_APE_PER_LOCK_REQ;
659 gnt = TG3_APE_PER_LOCK_GRANT;
664 if (locknum != TG3_APE_LOCK_GPIO || !tp->pci_fn)
665 bit = APE_LOCK_REQ_DRIVER;
667 bit = 1 << tp->pci_fn;
669 tg3_ape_write32(tp, req + off, bit);
671 /* Wait for up to 1 millisecond to acquire lock. */
672 for (i = 0; i < 100; i++) {
673 status = tg3_ape_read32(tp, gnt + off);
680 /* Revoke the lock request. */
681 tg3_ape_write32(tp, gnt + off, bit);
688 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
692 if (!tg3_flag(tp, ENABLE_APE))
696 case TG3_APE_LOCK_GPIO:
697 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
699 case TG3_APE_LOCK_GRC:
700 case TG3_APE_LOCK_MEM:
706 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
707 gnt = TG3_APE_LOCK_GRANT;
709 gnt = TG3_APE_PER_LOCK_GRANT;
711 if (locknum != TG3_APE_LOCK_GPIO || !tp->pci_fn)
712 bit = APE_LOCK_GRANT_DRIVER;
714 bit = 1 << tp->pci_fn;
716 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
719 static void tg3_disable_ints(struct tg3 *tp)
723 tw32(TG3PCI_MISC_HOST_CTRL,
724 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
725 for (i = 0; i < tp->irq_max; i++)
726 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
729 static void tg3_enable_ints(struct tg3 *tp)
736 tw32(TG3PCI_MISC_HOST_CTRL,
737 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
739 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
740 for (i = 0; i < tp->irq_cnt; i++) {
741 struct tg3_napi *tnapi = &tp->napi[i];
743 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
744 if (tg3_flag(tp, 1SHOT_MSI))
745 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
747 tp->coal_now |= tnapi->coal_now;
750 /* Force an initial interrupt */
751 if (!tg3_flag(tp, TAGGED_STATUS) &&
752 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
753 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
755 tw32(HOSTCC_MODE, tp->coal_now);
757 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
760 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
762 struct tg3 *tp = tnapi->tp;
763 struct tg3_hw_status *sblk = tnapi->hw_status;
764 unsigned int work_exists = 0;
766 /* check for phy events */
767 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
768 if (sblk->status & SD_STATUS_LINK_CHG)
771 /* check for RX/TX work to do */
772 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
773 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
780 * similar to tg3_enable_ints, but it accurately determines whether there
781 * is new work pending and can return without flushing the PIO write
782 * which reenables interrupts
784 static void tg3_int_reenable(struct tg3_napi *tnapi)
786 struct tg3 *tp = tnapi->tp;
788 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
791 /* When doing tagged status, this work check is unnecessary.
792 * The last_tag we write above tells the chip which piece of
793 * work we've completed.
795 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
796 tw32(HOSTCC_MODE, tp->coalesce_mode |
797 HOSTCC_MODE_ENABLE | tnapi->coal_now);
800 static void tg3_switch_clocks(struct tg3 *tp)
805 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
808 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
810 orig_clock_ctrl = clock_ctrl;
811 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
812 CLOCK_CTRL_CLKRUN_OENABLE |
814 tp->pci_clock_ctrl = clock_ctrl;
816 if (tg3_flag(tp, 5705_PLUS)) {
817 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
818 tw32_wait_f(TG3PCI_CLOCK_CTRL,
819 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
821 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
822 tw32_wait_f(TG3PCI_CLOCK_CTRL,
824 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
826 tw32_wait_f(TG3PCI_CLOCK_CTRL,
827 clock_ctrl | (CLOCK_CTRL_ALTCLK),
830 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
833 #define PHY_BUSY_LOOPS 5000
835 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
841 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
843 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
849 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
850 MI_COM_PHY_ADDR_MASK);
851 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
852 MI_COM_REG_ADDR_MASK);
853 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
855 tw32_f(MAC_MI_COM, frame_val);
857 loops = PHY_BUSY_LOOPS;
860 frame_val = tr32(MAC_MI_COM);
862 if ((frame_val & MI_COM_BUSY) == 0) {
864 frame_val = tr32(MAC_MI_COM);
872 *val = frame_val & MI_COM_DATA_MASK;
876 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
877 tw32_f(MAC_MI_MODE, tp->mi_mode);
884 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
890 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
891 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
894 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
896 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
900 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
901 MI_COM_PHY_ADDR_MASK);
902 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
903 MI_COM_REG_ADDR_MASK);
904 frame_val |= (val & MI_COM_DATA_MASK);
905 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
907 tw32_f(MAC_MI_COM, frame_val);
909 loops = PHY_BUSY_LOOPS;
912 frame_val = tr32(MAC_MI_COM);
913 if ((frame_val & MI_COM_BUSY) == 0) {
915 frame_val = tr32(MAC_MI_COM);
925 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
926 tw32_f(MAC_MI_MODE, tp->mi_mode);
933 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
937 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
941 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
945 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
946 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
950 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
956 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
960 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
964 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
968 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
969 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
973 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
979 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
983 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
985 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
990 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
994 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
996 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1001 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1005 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1006 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1007 MII_TG3_AUXCTL_SHDWSEL_MISC);
1009 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1014 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1016 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1017 set |= MII_TG3_AUXCTL_MISC_WREN;
1019 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1022 #define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \
1023 tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
1024 MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \
1025 MII_TG3_AUXCTL_ACTL_TX_6DB)
1027 #define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \
1028 tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
1029 MII_TG3_AUXCTL_ACTL_TX_6DB);
1031 static int tg3_bmcr_reset(struct tg3 *tp)
1036 /* OK, reset it, and poll the BMCR_RESET bit until it
1037 * clears or we time out.
1039 phy_control = BMCR_RESET;
1040 err = tg3_writephy(tp, MII_BMCR, phy_control);
1046 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1050 if ((phy_control & BMCR_RESET) == 0) {
1062 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1064 struct tg3 *tp = bp->priv;
1067 spin_lock_bh(&tp->lock);
1069 if (tg3_readphy(tp, reg, &val))
1072 spin_unlock_bh(&tp->lock);
1077 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1079 struct tg3 *tp = bp->priv;
1082 spin_lock_bh(&tp->lock);
1084 if (tg3_writephy(tp, reg, val))
1087 spin_unlock_bh(&tp->lock);
1092 static int tg3_mdio_reset(struct mii_bus *bp)
1097 static void tg3_mdio_config_5785(struct tg3 *tp)
1100 struct phy_device *phydev;
1102 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1103 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1104 case PHY_ID_BCM50610:
1105 case PHY_ID_BCM50610M:
1106 val = MAC_PHYCFG2_50610_LED_MODES;
1108 case PHY_ID_BCMAC131:
1109 val = MAC_PHYCFG2_AC131_LED_MODES;
1111 case PHY_ID_RTL8211C:
1112 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1114 case PHY_ID_RTL8201E:
1115 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1121 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1122 tw32(MAC_PHYCFG2, val);
1124 val = tr32(MAC_PHYCFG1);
1125 val &= ~(MAC_PHYCFG1_RGMII_INT |
1126 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1127 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1128 tw32(MAC_PHYCFG1, val);
1133 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
1134 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1135 MAC_PHYCFG2_FMODE_MASK_MASK |
1136 MAC_PHYCFG2_GMODE_MASK_MASK |
1137 MAC_PHYCFG2_ACT_MASK_MASK |
1138 MAC_PHYCFG2_QUAL_MASK_MASK |
1139 MAC_PHYCFG2_INBAND_ENABLE;
1141 tw32(MAC_PHYCFG2, val);
1143 val = tr32(MAC_PHYCFG1);
1144 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1145 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1146 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1147 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1148 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1149 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1150 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1152 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1153 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1154 tw32(MAC_PHYCFG1, val);
1156 val = tr32(MAC_EXT_RGMII_MODE);
1157 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1158 MAC_RGMII_MODE_RX_QUALITY |
1159 MAC_RGMII_MODE_RX_ACTIVITY |
1160 MAC_RGMII_MODE_RX_ENG_DET |
1161 MAC_RGMII_MODE_TX_ENABLE |
1162 MAC_RGMII_MODE_TX_LOWPWR |
1163 MAC_RGMII_MODE_TX_RESET);
1164 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1165 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1166 val |= MAC_RGMII_MODE_RX_INT_B |
1167 MAC_RGMII_MODE_RX_QUALITY |
1168 MAC_RGMII_MODE_RX_ACTIVITY |
1169 MAC_RGMII_MODE_RX_ENG_DET;
1170 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1171 val |= MAC_RGMII_MODE_TX_ENABLE |
1172 MAC_RGMII_MODE_TX_LOWPWR |
1173 MAC_RGMII_MODE_TX_RESET;
1175 tw32(MAC_EXT_RGMII_MODE, val);
1178 static void tg3_mdio_start(struct tg3 *tp)
1180 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1181 tw32_f(MAC_MI_MODE, tp->mi_mode);
1184 if (tg3_flag(tp, MDIOBUS_INITED) &&
1185 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1186 tg3_mdio_config_5785(tp);
1189 static int tg3_mdio_init(struct tg3 *tp)
1193 struct phy_device *phydev;
1195 if (tg3_flag(tp, 5717_PLUS)) {
1198 tp->phy_addr = tp->pci_fn + 1;
1200 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1201 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1203 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1204 TG3_CPMU_PHY_STRAP_IS_SERDES;
1208 tp->phy_addr = TG3_PHY_MII_ADDR;
1212 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
1215 tp->mdio_bus = mdiobus_alloc();
1216 if (tp->mdio_bus == NULL)
1219 tp->mdio_bus->name = "tg3 mdio bus";
1220 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1221 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1222 tp->mdio_bus->priv = tp;
1223 tp->mdio_bus->parent = &tp->pdev->dev;
1224 tp->mdio_bus->read = &tg3_mdio_read;
1225 tp->mdio_bus->write = &tg3_mdio_write;
1226 tp->mdio_bus->reset = &tg3_mdio_reset;
1227 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1228 tp->mdio_bus->irq = &tp->mdio_irq[0];
1230 for (i = 0; i < PHY_MAX_ADDR; i++)
1231 tp->mdio_bus->irq[i] = PHY_POLL;
1233 /* The bus registration will look for all the PHYs on the mdio bus.
1234 * Unfortunately, it does not ensure the PHY is powered up before
1235 * accessing the PHY ID registers. A chip reset is the
1236 * quickest way to bring the device back to an operational state..
1238 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1241 i = mdiobus_register(tp->mdio_bus);
1243 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1244 mdiobus_free(tp->mdio_bus);
1248 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1250 if (!phydev || !phydev->drv) {
1251 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1252 mdiobus_unregister(tp->mdio_bus);
1253 mdiobus_free(tp->mdio_bus);
1257 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1258 case PHY_ID_BCM57780:
1259 phydev->interface = PHY_INTERFACE_MODE_GMII;
1260 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1262 case PHY_ID_BCM50610:
1263 case PHY_ID_BCM50610M:
1264 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1265 PHY_BRCM_RX_REFCLK_UNUSED |
1266 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1267 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1268 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
1269 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1270 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1271 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1272 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1273 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1275 case PHY_ID_RTL8211C:
1276 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1278 case PHY_ID_RTL8201E:
1279 case PHY_ID_BCMAC131:
1280 phydev->interface = PHY_INTERFACE_MODE_MII;
1281 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1282 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1286 tg3_flag_set(tp, MDIOBUS_INITED);
1288 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1289 tg3_mdio_config_5785(tp);
1294 static void tg3_mdio_fini(struct tg3 *tp)
1296 if (tg3_flag(tp, MDIOBUS_INITED)) {
1297 tg3_flag_clear(tp, MDIOBUS_INITED);
1298 mdiobus_unregister(tp->mdio_bus);
1299 mdiobus_free(tp->mdio_bus);
1303 /* tp->lock is held. */
1304 static inline void tg3_generate_fw_event(struct tg3 *tp)
1308 val = tr32(GRC_RX_CPU_EVENT);
1309 val |= GRC_RX_CPU_DRIVER_EVENT;
1310 tw32_f(GRC_RX_CPU_EVENT, val);
1312 tp->last_event_jiffies = jiffies;
1315 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1317 /* tp->lock is held. */
1318 static void tg3_wait_for_event_ack(struct tg3 *tp)
1321 unsigned int delay_cnt;
1324 /* If enough time has passed, no wait is necessary. */
1325 time_remain = (long)(tp->last_event_jiffies + 1 +
1326 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1328 if (time_remain < 0)
1331 /* Check if we can shorten the wait time. */
1332 delay_cnt = jiffies_to_usecs(time_remain);
1333 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1334 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1335 delay_cnt = (delay_cnt >> 3) + 1;
1337 for (i = 0; i < delay_cnt; i++) {
1338 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1344 /* tp->lock is held. */
1345 static void tg3_ump_link_report(struct tg3 *tp)
1350 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1353 tg3_wait_for_event_ack(tp);
1355 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1357 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1360 if (!tg3_readphy(tp, MII_BMCR, ®))
1362 if (!tg3_readphy(tp, MII_BMSR, ®))
1363 val |= (reg & 0xffff);
1364 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1367 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1369 if (!tg3_readphy(tp, MII_LPA, ®))
1370 val |= (reg & 0xffff);
1371 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1374 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1375 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1377 if (!tg3_readphy(tp, MII_STAT1000, ®))
1378 val |= (reg & 0xffff);
1380 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1382 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1386 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1388 tg3_generate_fw_event(tp);
1391 static void tg3_link_report(struct tg3 *tp)
1393 if (!netif_carrier_ok(tp->dev)) {
1394 netif_info(tp, link, tp->dev, "Link is down\n");
1395 tg3_ump_link_report(tp);
1396 } else if (netif_msg_link(tp)) {
1397 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1398 (tp->link_config.active_speed == SPEED_1000 ?
1400 (tp->link_config.active_speed == SPEED_100 ?
1402 (tp->link_config.active_duplex == DUPLEX_FULL ?
1405 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1406 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1408 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1411 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1412 netdev_info(tp->dev, "EEE is %s\n",
1413 tp->setlpicnt ? "enabled" : "disabled");
1415 tg3_ump_link_report(tp);
1419 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1423 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1424 miireg = ADVERTISE_PAUSE_CAP;
1425 else if (flow_ctrl & FLOW_CTRL_TX)
1426 miireg = ADVERTISE_PAUSE_ASYM;
1427 else if (flow_ctrl & FLOW_CTRL_RX)
1428 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1435 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1439 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1440 miireg = ADVERTISE_1000XPAUSE;
1441 else if (flow_ctrl & FLOW_CTRL_TX)
1442 miireg = ADVERTISE_1000XPSE_ASYM;
1443 else if (flow_ctrl & FLOW_CTRL_RX)
1444 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1451 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1455 if (lcladv & ADVERTISE_1000XPAUSE) {
1456 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1457 if (rmtadv & LPA_1000XPAUSE)
1458 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1459 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1462 if (rmtadv & LPA_1000XPAUSE)
1463 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1465 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1466 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1473 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1477 u32 old_rx_mode = tp->rx_mode;
1478 u32 old_tx_mode = tp->tx_mode;
1480 if (tg3_flag(tp, USE_PHYLIB))
1481 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1483 autoneg = tp->link_config.autoneg;
1485 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
1486 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1487 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1489 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1491 flowctrl = tp->link_config.flowctrl;
1493 tp->link_config.active_flowctrl = flowctrl;
1495 if (flowctrl & FLOW_CTRL_RX)
1496 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1498 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1500 if (old_rx_mode != tp->rx_mode)
1501 tw32_f(MAC_RX_MODE, tp->rx_mode);
1503 if (flowctrl & FLOW_CTRL_TX)
1504 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1506 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1508 if (old_tx_mode != tp->tx_mode)
1509 tw32_f(MAC_TX_MODE, tp->tx_mode);
1512 static void tg3_adjust_link(struct net_device *dev)
1514 u8 oldflowctrl, linkmesg = 0;
1515 u32 mac_mode, lcl_adv, rmt_adv;
1516 struct tg3 *tp = netdev_priv(dev);
1517 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1519 spin_lock_bh(&tp->lock);
1521 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1522 MAC_MODE_HALF_DUPLEX);
1524 oldflowctrl = tp->link_config.active_flowctrl;
1530 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1531 mac_mode |= MAC_MODE_PORT_MODE_MII;
1532 else if (phydev->speed == SPEED_1000 ||
1533 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1534 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1536 mac_mode |= MAC_MODE_PORT_MODE_MII;
1538 if (phydev->duplex == DUPLEX_HALF)
1539 mac_mode |= MAC_MODE_HALF_DUPLEX;
1541 lcl_adv = tg3_advert_flowctrl_1000T(
1542 tp->link_config.flowctrl);
1545 rmt_adv = LPA_PAUSE_CAP;
1546 if (phydev->asym_pause)
1547 rmt_adv |= LPA_PAUSE_ASYM;
1550 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1552 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1554 if (mac_mode != tp->mac_mode) {
1555 tp->mac_mode = mac_mode;
1556 tw32_f(MAC_MODE, tp->mac_mode);
1560 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1561 if (phydev->speed == SPEED_10)
1563 MAC_MI_STAT_10MBPS_MODE |
1564 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1566 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1569 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1570 tw32(MAC_TX_LENGTHS,
1571 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1572 (6 << TX_LENGTHS_IPG_SHIFT) |
1573 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1575 tw32(MAC_TX_LENGTHS,
1576 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1577 (6 << TX_LENGTHS_IPG_SHIFT) |
1578 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1580 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1581 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1582 phydev->speed != tp->link_config.active_speed ||
1583 phydev->duplex != tp->link_config.active_duplex ||
1584 oldflowctrl != tp->link_config.active_flowctrl)
1587 tp->link_config.active_speed = phydev->speed;
1588 tp->link_config.active_duplex = phydev->duplex;
1590 spin_unlock_bh(&tp->lock);
1593 tg3_link_report(tp);
1596 static int tg3_phy_init(struct tg3 *tp)
1598 struct phy_device *phydev;
1600 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1603 /* Bring the PHY back to a known state. */
1606 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1608 /* Attach the MAC to the PHY. */
1609 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1610 phydev->dev_flags, phydev->interface);
1611 if (IS_ERR(phydev)) {
1612 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1613 return PTR_ERR(phydev);
1616 /* Mask with MAC supported features. */
1617 switch (phydev->interface) {
1618 case PHY_INTERFACE_MODE_GMII:
1619 case PHY_INTERFACE_MODE_RGMII:
1620 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1621 phydev->supported &= (PHY_GBIT_FEATURES |
1623 SUPPORTED_Asym_Pause);
1627 case PHY_INTERFACE_MODE_MII:
1628 phydev->supported &= (PHY_BASIC_FEATURES |
1630 SUPPORTED_Asym_Pause);
1633 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1637 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1639 phydev->advertising = phydev->supported;
1644 static void tg3_phy_start(struct tg3 *tp)
1646 struct phy_device *phydev;
1648 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1651 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1653 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1654 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1655 phydev->speed = tp->link_config.orig_speed;
1656 phydev->duplex = tp->link_config.orig_duplex;
1657 phydev->autoneg = tp->link_config.orig_autoneg;
1658 phydev->advertising = tp->link_config.orig_advertising;
1663 phy_start_aneg(phydev);
1666 static void tg3_phy_stop(struct tg3 *tp)
1668 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1671 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1674 static void tg3_phy_fini(struct tg3 *tp)
1676 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1677 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1678 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1682 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1686 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1689 tg3_writephy(tp, MII_TG3_FET_TEST,
1690 phytest | MII_TG3_FET_SHADOW_EN);
1691 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1693 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1695 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1696 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1698 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1702 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1706 if (!tg3_flag(tp, 5705_PLUS) ||
1707 (tg3_flag(tp, 5717_PLUS) &&
1708 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1711 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1712 tg3_phy_fet_toggle_apd(tp, enable);
1716 reg = MII_TG3_MISC_SHDW_WREN |
1717 MII_TG3_MISC_SHDW_SCR5_SEL |
1718 MII_TG3_MISC_SHDW_SCR5_LPED |
1719 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1720 MII_TG3_MISC_SHDW_SCR5_SDTL |
1721 MII_TG3_MISC_SHDW_SCR5_C125OE;
1722 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1723 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1725 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1728 reg = MII_TG3_MISC_SHDW_WREN |
1729 MII_TG3_MISC_SHDW_APD_SEL |
1730 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1732 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1734 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1737 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1741 if (!tg3_flag(tp, 5705_PLUS) ||
1742 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1745 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1748 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1749 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1751 tg3_writephy(tp, MII_TG3_FET_TEST,
1752 ephy | MII_TG3_FET_SHADOW_EN);
1753 if (!tg3_readphy(tp, reg, &phy)) {
1755 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1757 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1758 tg3_writephy(tp, reg, phy);
1760 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1765 ret = tg3_phy_auxctl_read(tp,
1766 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
1769 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1771 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1772 tg3_phy_auxctl_write(tp,
1773 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
1778 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1783 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1786 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
1788 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
1789 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
1792 static void tg3_phy_apply_otp(struct tg3 *tp)
1801 if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp))
1804 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1805 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1806 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1808 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1809 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1810 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1812 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1813 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1814 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1816 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1817 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1819 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1820 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1822 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1823 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1824 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1826 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
1829 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
1833 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
1838 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
1839 current_link_up == 1 &&
1840 tp->link_config.active_duplex == DUPLEX_FULL &&
1841 (tp->link_config.active_speed == SPEED_100 ||
1842 tp->link_config.active_speed == SPEED_1000)) {
1845 if (tp->link_config.active_speed == SPEED_1000)
1846 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
1848 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
1850 tw32(TG3_CPMU_EEE_CTRL, eeectl);
1852 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
1853 TG3_CL45_D7_EEERES_STAT, &val);
1855 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
1856 val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
1860 if (!tp->setlpicnt) {
1861 val = tr32(TG3_CPMU_EEE_MODE);
1862 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
1866 static void tg3_phy_eee_enable(struct tg3 *tp)
1870 if (tp->link_config.active_speed == SPEED_1000 &&
1871 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1872 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
1873 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
1874 !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
1875 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0003);
1876 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
1879 val = tr32(TG3_CPMU_EEE_MODE);
1880 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
1883 static int tg3_wait_macro_done(struct tg3 *tp)
1890 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1891 if ((tmp32 & 0x1000) == 0)
1901 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1903 static const u32 test_pat[4][6] = {
1904 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1905 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1906 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1907 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1911 for (chan = 0; chan < 4; chan++) {
1914 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1915 (chan * 0x2000) | 0x0200);
1916 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1918 for (i = 0; i < 6; i++)
1919 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1922 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1923 if (tg3_wait_macro_done(tp)) {
1928 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1929 (chan * 0x2000) | 0x0200);
1930 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1931 if (tg3_wait_macro_done(tp)) {
1936 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1937 if (tg3_wait_macro_done(tp)) {
1942 for (i = 0; i < 6; i += 2) {
1945 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1946 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1947 tg3_wait_macro_done(tp)) {
1953 if (low != test_pat[chan][i] ||
1954 high != test_pat[chan][i+1]) {
1955 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1956 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1957 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1967 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1971 for (chan = 0; chan < 4; chan++) {
1974 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1975 (chan * 0x2000) | 0x0200);
1976 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1977 for (i = 0; i < 6; i++)
1978 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1979 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1980 if (tg3_wait_macro_done(tp))
1987 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1989 u32 reg32, phy9_orig;
1990 int retries, do_phy_reset, err;
1996 err = tg3_bmcr_reset(tp);
2002 /* Disable transmitter and interrupt. */
2003 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
2007 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2009 /* Set full-duplex, 1000 mbps. */
2010 tg3_writephy(tp, MII_BMCR,
2011 BMCR_FULLDPLX | BMCR_SPEED1000);
2013 /* Set to master mode. */
2014 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
2017 tg3_writephy(tp, MII_CTRL1000,
2018 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
2020 err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
2024 /* Block the PHY control access. */
2025 tg3_phydsp_write(tp, 0x8005, 0x0800);
2027 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2030 } while (--retries);
2032 err = tg3_phy_reset_chanpat(tp);
2036 tg3_phydsp_write(tp, 0x8005, 0x0000);
2038 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2039 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2041 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2043 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
2045 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) {
2047 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2054 /* This will reset the tigon3 PHY if there is no valid
2055 * link unless the FORCE argument is non-zero.
2057 static int tg3_phy_reset(struct tg3 *tp)
2062 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2063 val = tr32(GRC_MISC_CFG);
2064 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2067 err = tg3_readphy(tp, MII_BMSR, &val);
2068 err |= tg3_readphy(tp, MII_BMSR, &val);
2072 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
2073 netif_carrier_off(tp->dev);
2074 tg3_link_report(tp);
2077 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2078 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2079 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2080 err = tg3_phy_reset_5703_4_5(tp);
2087 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2088 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2089 cpmuctrl = tr32(TG3_CPMU_CTRL);
2090 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2092 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2095 err = tg3_bmcr_reset(tp);
2099 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2100 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2101 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2103 tw32(TG3_CPMU_CTRL, cpmuctrl);
2106 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2107 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2108 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2109 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2110 CPMU_LSPD_1000MB_MACCLK_12_5) {
2111 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2113 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2117 if (tg3_flag(tp, 5717_PLUS) &&
2118 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2121 tg3_phy_apply_otp(tp);
2123 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2124 tg3_phy_toggle_apd(tp, true);
2126 tg3_phy_toggle_apd(tp, false);
2129 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2130 !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2131 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2132 tg3_phydsp_write(tp, 0x000a, 0x0323);
2133 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2136 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2137 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2138 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2141 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2142 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2143 tg3_phydsp_write(tp, 0x000a, 0x310b);
2144 tg3_phydsp_write(tp, 0x201f, 0x9506);
2145 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2146 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2148 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2149 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2150 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2151 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2152 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2153 tg3_writephy(tp, MII_TG3_TEST1,
2154 MII_TG3_TEST1_TRIM_EN | 0x4);
2156 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2158 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2162 /* Set Extended packet length bit (bit 14) on all chips that */
2163 /* support jumbo frames */
2164 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2165 /* Cannot do read-modify-write on 5401 */
2166 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2167 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
2168 /* Set bit 14 with read-modify-write to preserve other bits */
2169 err = tg3_phy_auxctl_read(tp,
2170 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2172 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2173 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
2176 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2177 * jumbo frames transmission.
2179 if (tg3_flag(tp, JUMBO_CAPABLE)) {
2180 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2181 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2182 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2185 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2186 /* adjust output voltage */
2187 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2190 tg3_phy_toggle_automdix(tp, 1);
2191 tg3_phy_set_wirespeed(tp);
2195 #define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2196 #define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2197 #define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2198 TG3_GPIO_MSG_NEED_VAUX)
2199 #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2200 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2201 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2202 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2203 (TG3_GPIO_MSG_DRVR_PRES << 12))
2205 #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2206 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2207 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2208 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2209 (TG3_GPIO_MSG_NEED_VAUX << 12))
2211 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2215 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2216 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
2217 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2219 status = tr32(TG3_CPMU_DRV_STATUS);
2221 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2222 status &= ~(TG3_GPIO_MSG_MASK << shift);
2223 status |= (newstat << shift);
2225 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2226 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
2227 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2229 tw32(TG3_CPMU_DRV_STATUS, status);
2231 return status >> TG3_APE_GPIO_MSG_SHIFT;
2234 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2236 if (!tg3_flag(tp, IS_NIC))
2239 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2240 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2241 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
2242 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2245 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2247 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2248 TG3_GRC_LCLCTL_PWRSW_DELAY);
2250 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2252 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2253 TG3_GRC_LCLCTL_PWRSW_DELAY);
2259 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2263 if (!tg3_flag(tp, IS_NIC) ||
2264 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2265 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)
2268 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2270 tw32_wait_f(GRC_LOCAL_CTRL,
2271 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2272 TG3_GRC_LCLCTL_PWRSW_DELAY);
2274 tw32_wait_f(GRC_LOCAL_CTRL,
2276 TG3_GRC_LCLCTL_PWRSW_DELAY);
2278 tw32_wait_f(GRC_LOCAL_CTRL,
2279 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2280 TG3_GRC_LCLCTL_PWRSW_DELAY);
2283 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2285 if (!tg3_flag(tp, IS_NIC))
2288 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2289 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2290 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2291 (GRC_LCLCTRL_GPIO_OE0 |
2292 GRC_LCLCTRL_GPIO_OE1 |
2293 GRC_LCLCTRL_GPIO_OE2 |
2294 GRC_LCLCTRL_GPIO_OUTPUT0 |
2295 GRC_LCLCTRL_GPIO_OUTPUT1),
2296 TG3_GRC_LCLCTL_PWRSW_DELAY);
2297 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2298 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2299 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2300 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2301 GRC_LCLCTRL_GPIO_OE1 |
2302 GRC_LCLCTRL_GPIO_OE2 |
2303 GRC_LCLCTRL_GPIO_OUTPUT0 |
2304 GRC_LCLCTRL_GPIO_OUTPUT1 |
2306 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2307 TG3_GRC_LCLCTL_PWRSW_DELAY);
2309 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2310 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2311 TG3_GRC_LCLCTL_PWRSW_DELAY);
2313 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2314 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2315 TG3_GRC_LCLCTL_PWRSW_DELAY);
2318 u32 grc_local_ctrl = 0;
2320 /* Workaround to prevent overdrawing Amps. */
2321 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2322 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2323 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2325 TG3_GRC_LCLCTL_PWRSW_DELAY);
2328 /* On 5753 and variants, GPIO2 cannot be used. */
2329 no_gpio2 = tp->nic_sram_data_cfg &
2330 NIC_SRAM_DATA_CFG_NO_GPIO2;
2332 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2333 GRC_LCLCTRL_GPIO_OE1 |
2334 GRC_LCLCTRL_GPIO_OE2 |
2335 GRC_LCLCTRL_GPIO_OUTPUT1 |
2336 GRC_LCLCTRL_GPIO_OUTPUT2;
2338 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2339 GRC_LCLCTRL_GPIO_OUTPUT2);
2341 tw32_wait_f(GRC_LOCAL_CTRL,
2342 tp->grc_local_ctrl | grc_local_ctrl,
2343 TG3_GRC_LCLCTL_PWRSW_DELAY);
2345 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2347 tw32_wait_f(GRC_LOCAL_CTRL,
2348 tp->grc_local_ctrl | grc_local_ctrl,
2349 TG3_GRC_LCLCTL_PWRSW_DELAY);
2352 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2353 tw32_wait_f(GRC_LOCAL_CTRL,
2354 tp->grc_local_ctrl | grc_local_ctrl,
2355 TG3_GRC_LCLCTL_PWRSW_DELAY);
2360 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
2364 /* Serialize power state transitions */
2365 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2368 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
2369 msg = TG3_GPIO_MSG_NEED_VAUX;
2371 msg = tg3_set_function_status(tp, msg);
2373 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2376 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2377 tg3_pwrsrc_switch_to_vaux(tp);
2379 tg3_pwrsrc_die_with_vmain(tp);
2382 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2385 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
2387 bool need_vaux = false;
2389 /* The GPIOs do something completely different on 57765. */
2390 if (!tg3_flag(tp, IS_NIC) ||
2391 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2394 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2395 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2396 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
2397 tg3_frob_aux_power_5717(tp, include_wol ?
2398 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
2402 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
2403 struct net_device *dev_peer;
2405 dev_peer = pci_get_drvdata(tp->pdev_peer);
2407 /* remove_one() may have been run on the peer. */
2409 struct tg3 *tp_peer = netdev_priv(dev_peer);
2411 if (tg3_flag(tp_peer, INIT_COMPLETE))
2414 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
2415 tg3_flag(tp_peer, ENABLE_ASF))
2420 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2421 tg3_flag(tp, ENABLE_ASF))
2425 tg3_pwrsrc_switch_to_vaux(tp);
2427 tg3_pwrsrc_die_with_vmain(tp);
2430 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2432 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2434 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2435 if (speed != SPEED_10)
2437 } else if (speed == SPEED_10)
2443 static int tg3_setup_phy(struct tg3 *, int);
2445 #define RESET_KIND_SHUTDOWN 0
2446 #define RESET_KIND_INIT 1
2447 #define RESET_KIND_SUSPEND 2
2449 static void tg3_write_sig_post_reset(struct tg3 *, int);
2450 static int tg3_halt_cpu(struct tg3 *, u32);
2452 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2456 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2457 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2458 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2459 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2462 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2463 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2464 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2469 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2471 val = tr32(GRC_MISC_CFG);
2472 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2475 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2477 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2480 tg3_writephy(tp, MII_ADVERTISE, 0);
2481 tg3_writephy(tp, MII_BMCR,
2482 BMCR_ANENABLE | BMCR_ANRESTART);
2484 tg3_writephy(tp, MII_TG3_FET_TEST,
2485 phytest | MII_TG3_FET_SHADOW_EN);
2486 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2487 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2489 MII_TG3_FET_SHDW_AUXMODE4,
2492 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2495 } else if (do_low_power) {
2496 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2497 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2499 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2500 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2501 MII_TG3_AUXCTL_PCTL_VREG_11V;
2502 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
2505 /* The PHY should not be powered down on some chips because
2508 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2509 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2510 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2511 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2514 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2515 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2516 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2517 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2518 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2519 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2522 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2525 /* tp->lock is held. */
2526 static int tg3_nvram_lock(struct tg3 *tp)
2528 if (tg3_flag(tp, NVRAM)) {
2531 if (tp->nvram_lock_cnt == 0) {
2532 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2533 for (i = 0; i < 8000; i++) {
2534 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2539 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2543 tp->nvram_lock_cnt++;
2548 /* tp->lock is held. */
2549 static void tg3_nvram_unlock(struct tg3 *tp)
2551 if (tg3_flag(tp, NVRAM)) {
2552 if (tp->nvram_lock_cnt > 0)
2553 tp->nvram_lock_cnt--;
2554 if (tp->nvram_lock_cnt == 0)
2555 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2559 /* tp->lock is held. */
2560 static void tg3_enable_nvram_access(struct tg3 *tp)
2562 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
2563 u32 nvaccess = tr32(NVRAM_ACCESS);
2565 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2569 /* tp->lock is held. */
2570 static void tg3_disable_nvram_access(struct tg3 *tp)
2572 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
2573 u32 nvaccess = tr32(NVRAM_ACCESS);
2575 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2579 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2580 u32 offset, u32 *val)
2585 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2588 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2589 EEPROM_ADDR_DEVID_MASK |
2591 tw32(GRC_EEPROM_ADDR,
2593 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2594 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2595 EEPROM_ADDR_ADDR_MASK) |
2596 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2598 for (i = 0; i < 1000; i++) {
2599 tmp = tr32(GRC_EEPROM_ADDR);
2601 if (tmp & EEPROM_ADDR_COMPLETE)
2605 if (!(tmp & EEPROM_ADDR_COMPLETE))
2608 tmp = tr32(GRC_EEPROM_DATA);
2611 * The data will always be opposite the native endian
2612 * format. Perform a blind byteswap to compensate.
2619 #define NVRAM_CMD_TIMEOUT 10000
2621 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2625 tw32(NVRAM_CMD, nvram_cmd);
2626 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2628 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2634 if (i == NVRAM_CMD_TIMEOUT)
2640 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2642 if (tg3_flag(tp, NVRAM) &&
2643 tg3_flag(tp, NVRAM_BUFFERED) &&
2644 tg3_flag(tp, FLASH) &&
2645 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
2646 (tp->nvram_jedecnum == JEDEC_ATMEL))
2648 addr = ((addr / tp->nvram_pagesize) <<
2649 ATMEL_AT45DB0X1B_PAGE_POS) +
2650 (addr % tp->nvram_pagesize);
2655 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2657 if (tg3_flag(tp, NVRAM) &&
2658 tg3_flag(tp, NVRAM_BUFFERED) &&
2659 tg3_flag(tp, FLASH) &&
2660 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
2661 (tp->nvram_jedecnum == JEDEC_ATMEL))
2663 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2664 tp->nvram_pagesize) +
2665 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2670 /* NOTE: Data read in from NVRAM is byteswapped according to
2671 * the byteswapping settings for all other register accesses.
2672 * tg3 devices are BE devices, so on a BE machine, the data
2673 * returned will be exactly as it is seen in NVRAM. On a LE
2674 * machine, the 32-bit value will be byteswapped.
2676 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2680 if (!tg3_flag(tp, NVRAM))
2681 return tg3_nvram_read_using_eeprom(tp, offset, val);
2683 offset = tg3_nvram_phys_addr(tp, offset);
2685 if (offset > NVRAM_ADDR_MSK)
2688 ret = tg3_nvram_lock(tp);
2692 tg3_enable_nvram_access(tp);
2694 tw32(NVRAM_ADDR, offset);
2695 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2696 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2699 *val = tr32(NVRAM_RDDATA);
2701 tg3_disable_nvram_access(tp);
2703 tg3_nvram_unlock(tp);
2708 /* Ensures NVRAM data is in bytestream format. */
2709 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2712 int res = tg3_nvram_read(tp, offset, &v);
2714 *val = cpu_to_be32(v);
2718 /* tp->lock is held. */
2719 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2721 u32 addr_high, addr_low;
2724 addr_high = ((tp->dev->dev_addr[0] << 8) |
2725 tp->dev->dev_addr[1]);
2726 addr_low = ((tp->dev->dev_addr[2] << 24) |
2727 (tp->dev->dev_addr[3] << 16) |
2728 (tp->dev->dev_addr[4] << 8) |
2729 (tp->dev->dev_addr[5] << 0));
2730 for (i = 0; i < 4; i++) {
2731 if (i == 1 && skip_mac_1)
2733 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2734 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2737 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2738 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2739 for (i = 0; i < 12; i++) {
2740 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2741 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2745 addr_high = (tp->dev->dev_addr[0] +
2746 tp->dev->dev_addr[1] +
2747 tp->dev->dev_addr[2] +
2748 tp->dev->dev_addr[3] +
2749 tp->dev->dev_addr[4] +
2750 tp->dev->dev_addr[5]) &
2751 TX_BACKOFF_SEED_MASK;
2752 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2755 static void tg3_enable_register_access(struct tg3 *tp)
2758 * Make sure register accesses (indirect or otherwise) will function
2761 pci_write_config_dword(tp->pdev,
2762 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
2765 static int tg3_power_up(struct tg3 *tp)
2769 tg3_enable_register_access(tp);
2771 err = pci_set_power_state(tp->pdev, PCI_D0);
2773 /* Switch out of Vaux if it is a NIC */
2774 tg3_pwrsrc_switch_to_vmain(tp);
2776 netdev_err(tp->dev, "Transition to D0 failed\n");
2782 static int tg3_power_down_prepare(struct tg3 *tp)
2785 bool device_should_wake, do_low_power;
2787 tg3_enable_register_access(tp);
2789 /* Restore the CLKREQ setting. */
2790 if (tg3_flag(tp, CLKREQ_BUG)) {
2793 pci_read_config_word(tp->pdev,
2794 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
2796 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2797 pci_write_config_word(tp->pdev,
2798 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
2802 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2803 tw32(TG3PCI_MISC_HOST_CTRL,
2804 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2806 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
2807 tg3_flag(tp, WOL_ENABLE);
2809 if (tg3_flag(tp, USE_PHYLIB)) {
2810 do_low_power = false;
2811 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2812 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2813 struct phy_device *phydev;
2814 u32 phyid, advertising;
2816 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2818 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2820 tp->link_config.orig_speed = phydev->speed;
2821 tp->link_config.orig_duplex = phydev->duplex;
2822 tp->link_config.orig_autoneg = phydev->autoneg;
2823 tp->link_config.orig_advertising = phydev->advertising;
2825 advertising = ADVERTISED_TP |
2827 ADVERTISED_Autoneg |
2828 ADVERTISED_10baseT_Half;
2830 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
2831 if (tg3_flag(tp, WOL_SPEED_100MB))
2833 ADVERTISED_100baseT_Half |
2834 ADVERTISED_100baseT_Full |
2835 ADVERTISED_10baseT_Full;
2837 advertising |= ADVERTISED_10baseT_Full;
2840 phydev->advertising = advertising;
2842 phy_start_aneg(phydev);
2844 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2845 if (phyid != PHY_ID_BCMAC131) {
2846 phyid &= PHY_BCM_OUI_MASK;
2847 if (phyid == PHY_BCM_OUI_1 ||
2848 phyid == PHY_BCM_OUI_2 ||
2849 phyid == PHY_BCM_OUI_3)
2850 do_low_power = true;
2854 do_low_power = true;
2856 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2857 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2858 tp->link_config.orig_speed = tp->link_config.speed;
2859 tp->link_config.orig_duplex = tp->link_config.duplex;
2860 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2863 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2864 tp->link_config.speed = SPEED_10;
2865 tp->link_config.duplex = DUPLEX_HALF;
2866 tp->link_config.autoneg = AUTONEG_ENABLE;
2867 tg3_setup_phy(tp, 0);
2871 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2874 val = tr32(GRC_VCPU_EXT_CTRL);
2875 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2876 } else if (!tg3_flag(tp, ENABLE_ASF)) {
2880 for (i = 0; i < 200; i++) {
2881 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2882 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2887 if (tg3_flag(tp, WOL_CAP))
2888 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2889 WOL_DRV_STATE_SHUTDOWN |
2893 if (device_should_wake) {
2896 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2898 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
2899 tg3_phy_auxctl_write(tp,
2900 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
2901 MII_TG3_AUXCTL_PCTL_WOL_EN |
2902 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2903 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
2907 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2908 mac_mode = MAC_MODE_PORT_MODE_GMII;
2910 mac_mode = MAC_MODE_PORT_MODE_MII;
2912 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2913 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2915 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
2916 SPEED_100 : SPEED_10;
2917 if (tg3_5700_link_polarity(tp, speed))
2918 mac_mode |= MAC_MODE_LINK_POLARITY;
2920 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2923 mac_mode = MAC_MODE_PORT_MODE_TBI;
2926 if (!tg3_flag(tp, 5750_PLUS))
2927 tw32(MAC_LED_CTRL, tp->led_ctrl);
2929 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2930 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
2931 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
2932 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2934 if (tg3_flag(tp, ENABLE_APE))
2935 mac_mode |= MAC_MODE_APE_TX_EN |
2936 MAC_MODE_APE_RX_EN |
2937 MAC_MODE_TDE_ENABLE;
2939 tw32_f(MAC_MODE, mac_mode);
2942 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2946 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
2947 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2948 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2951 base_val = tp->pci_clock_ctrl;
2952 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2953 CLOCK_CTRL_TXCLK_DISABLE);
2955 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2956 CLOCK_CTRL_PWRDOWN_PLL133, 40);
2957 } else if (tg3_flag(tp, 5780_CLASS) ||
2958 tg3_flag(tp, CPMU_PRESENT) ||
2959 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2961 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
2962 u32 newbits1, newbits2;
2964 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2965 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2966 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2967 CLOCK_CTRL_TXCLK_DISABLE |
2969 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2970 } else if (tg3_flag(tp, 5705_PLUS)) {
2971 newbits1 = CLOCK_CTRL_625_CORE;
2972 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2974 newbits1 = CLOCK_CTRL_ALTCLK;
2975 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2978 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2981 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2984 if (!tg3_flag(tp, 5705_PLUS)) {
2987 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2988 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2989 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2990 CLOCK_CTRL_TXCLK_DISABLE |
2991 CLOCK_CTRL_44MHZ_CORE);
2993 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2996 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2997 tp->pci_clock_ctrl | newbits3, 40);
3001 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
3002 tg3_power_down_phy(tp, do_low_power);
3004 tg3_frob_aux_power(tp, true);
3006 /* Workaround for unstable PLL clock */
3007 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
3008 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
3009 u32 val = tr32(0x7d00);
3011 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
3013 if (!tg3_flag(tp, ENABLE_ASF)) {
3016 err = tg3_nvram_lock(tp);
3017 tg3_halt_cpu(tp, RX_CPU_BASE);
3019 tg3_nvram_unlock(tp);
3023 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
3028 static void tg3_power_down(struct tg3 *tp)
3030 tg3_power_down_prepare(tp);
3032 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
3033 pci_set_power_state(tp->pdev, PCI_D3hot);
3036 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
3038 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
3039 case MII_TG3_AUX_STAT_10HALF:
3041 *duplex = DUPLEX_HALF;
3044 case MII_TG3_AUX_STAT_10FULL:
3046 *duplex = DUPLEX_FULL;
3049 case MII_TG3_AUX_STAT_100HALF:
3051 *duplex = DUPLEX_HALF;
3054 case MII_TG3_AUX_STAT_100FULL:
3056 *duplex = DUPLEX_FULL;
3059 case MII_TG3_AUX_STAT_1000HALF:
3060 *speed = SPEED_1000;
3061 *duplex = DUPLEX_HALF;
3064 case MII_TG3_AUX_STAT_1000FULL:
3065 *speed = SPEED_1000;
3066 *duplex = DUPLEX_FULL;
3070 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
3071 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
3073 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
3077 *speed = SPEED_INVALID;
3078 *duplex = DUPLEX_INVALID;
3083 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
3088 new_adv = ADVERTISE_CSMA;
3089 if (advertise & ADVERTISED_10baseT_Half)
3090 new_adv |= ADVERTISE_10HALF;
3091 if (advertise & ADVERTISED_10baseT_Full)
3092 new_adv |= ADVERTISE_10FULL;
3093 if (advertise & ADVERTISED_100baseT_Half)
3094 new_adv |= ADVERTISE_100HALF;
3095 if (advertise & ADVERTISED_100baseT_Full)
3096 new_adv |= ADVERTISE_100FULL;
3098 new_adv |= tg3_advert_flowctrl_1000T(flowctrl);
3100 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
3104 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
3108 if (advertise & ADVERTISED_1000baseT_Half)
3109 new_adv |= ADVERTISE_1000HALF;
3110 if (advertise & ADVERTISED_1000baseT_Full)
3111 new_adv |= ADVERTISE_1000FULL;
3113 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3114 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
3115 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
3117 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
3121 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
3124 tw32(TG3_CPMU_EEE_MODE,
3125 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
3127 err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
3131 switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
3133 case ASIC_REV_57765:
3134 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
3135 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
3136 MII_TG3_DSP_CH34TP2_HIBW01);
3139 val = MII_TG3_DSP_TAP26_ALNOKO |
3140 MII_TG3_DSP_TAP26_RMRXSTO |
3141 MII_TG3_DSP_TAP26_OPCSINPT;
3142 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
3146 /* Advertise 100-BaseTX EEE ability */
3147 if (advertise & ADVERTISED_100baseT_Full)
3148 val |= MDIO_AN_EEE_ADV_100TX;
3149 /* Advertise 1000-BaseT EEE ability */
3150 if (advertise & ADVERTISED_1000baseT_Full)
3151 val |= MDIO_AN_EEE_ADV_1000T;
3152 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3154 err2 = TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
3163 static void tg3_phy_copper_begin(struct tg3 *tp)
3168 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
3169 new_adv = ADVERTISED_10baseT_Half |
3170 ADVERTISED_10baseT_Full;
3171 if (tg3_flag(tp, WOL_SPEED_100MB))
3172 new_adv |= ADVERTISED_100baseT_Half |
3173 ADVERTISED_100baseT_Full;
3175 tg3_phy_autoneg_cfg(tp, new_adv,
3176 FLOW_CTRL_TX | FLOW_CTRL_RX);
3177 } else if (tp->link_config.speed == SPEED_INVALID) {
3178 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
3179 tp->link_config.advertising &=
3180 ~(ADVERTISED_1000baseT_Half |
3181 ADVERTISED_1000baseT_Full);
3183 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
3184 tp->link_config.flowctrl);
3186 /* Asking for a specific link mode. */
3187 if (tp->link_config.speed == SPEED_1000) {
3188 if (tp->link_config.duplex == DUPLEX_FULL)
3189 new_adv = ADVERTISED_1000baseT_Full;
3191 new_adv = ADVERTISED_1000baseT_Half;
3192 } else if (tp->link_config.speed == SPEED_100) {
3193 if (tp->link_config.duplex == DUPLEX_FULL)
3194 new_adv = ADVERTISED_100baseT_Full;
3196 new_adv = ADVERTISED_100baseT_Half;
3198 if (tp->link_config.duplex == DUPLEX_FULL)
3199 new_adv = ADVERTISED_10baseT_Full;
3201 new_adv = ADVERTISED_10baseT_Half;
3204 tg3_phy_autoneg_cfg(tp, new_adv,
3205 tp->link_config.flowctrl);
3208 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
3209 tp->link_config.speed != SPEED_INVALID) {
3210 u32 bmcr, orig_bmcr;
3212 tp->link_config.active_speed = tp->link_config.speed;
3213 tp->link_config.active_duplex = tp->link_config.duplex;
3216 switch (tp->link_config.speed) {
3222 bmcr |= BMCR_SPEED100;
3226 bmcr |= BMCR_SPEED1000;
3230 if (tp->link_config.duplex == DUPLEX_FULL)
3231 bmcr |= BMCR_FULLDPLX;
3233 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
3234 (bmcr != orig_bmcr)) {
3235 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
3236 for (i = 0; i < 1500; i++) {
3240 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
3241 tg3_readphy(tp, MII_BMSR, &tmp))
3243 if (!(tmp & BMSR_LSTATUS)) {
3248 tg3_writephy(tp, MII_BMCR, bmcr);
3252 tg3_writephy(tp, MII_BMCR,
3253 BMCR_ANENABLE | BMCR_ANRESTART);
3257 static int tg3_init_5401phy_dsp(struct tg3 *tp)
3261 /* Turn off tap power management. */
3262 /* Set Extended packet length bit */
3263 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
3265 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
3266 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
3267 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
3268 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
3269 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
3276 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3278 u32 adv_reg, all_mask = 0;
3280 if (mask & ADVERTISED_10baseT_Half)
3281 all_mask |= ADVERTISE_10HALF;
3282 if (mask & ADVERTISED_10baseT_Full)
3283 all_mask |= ADVERTISE_10FULL;
3284 if (mask & ADVERTISED_100baseT_Half)
3285 all_mask |= ADVERTISE_100HALF;
3286 if (mask & ADVERTISED_100baseT_Full)
3287 all_mask |= ADVERTISE_100FULL;
3289 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3292 if ((adv_reg & all_mask) != all_mask)
3294 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3298 if (mask & ADVERTISED_1000baseT_Half)
3299 all_mask |= ADVERTISE_1000HALF;
3300 if (mask & ADVERTISED_1000baseT_Full)
3301 all_mask |= ADVERTISE_1000FULL;
3303 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
3306 if ((tg3_ctrl & all_mask) != all_mask)
3312 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3316 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3319 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3320 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3322 if (tp->link_config.active_duplex == DUPLEX_FULL) {
3323 if (curadv != reqadv)
3326 if (tg3_flag(tp, PAUSE_AUTONEG))
3327 tg3_readphy(tp, MII_LPA, rmtadv);
3329 /* Reprogram the advertisement register, even if it
3330 * does not affect the current link. If the link
3331 * gets renegotiated in the future, we can save an
3332 * additional renegotiation cycle by advertising
3333 * it correctly in the first place.
3335 if (curadv != reqadv) {
3336 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3337 ADVERTISE_PAUSE_ASYM);
3338 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3345 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3347 int current_link_up;
3349 u32 lcl_adv, rmt_adv;
3357 (MAC_STATUS_SYNC_CHANGED |
3358 MAC_STATUS_CFG_CHANGED |
3359 MAC_STATUS_MI_COMPLETION |
3360 MAC_STATUS_LNKSTATE_CHANGED));
3363 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3365 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3369 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
3371 /* Some third-party PHYs need to be reset on link going
3374 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3375 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3376 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3377 netif_carrier_ok(tp->dev)) {
3378 tg3_readphy(tp, MII_BMSR, &bmsr);
3379 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3380 !(bmsr & BMSR_LSTATUS))
3386 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3387 tg3_readphy(tp, MII_BMSR, &bmsr);
3388 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3389 !tg3_flag(tp, INIT_COMPLETE))
3392 if (!(bmsr & BMSR_LSTATUS)) {
3393 err = tg3_init_5401phy_dsp(tp);
3397 tg3_readphy(tp, MII_BMSR, &bmsr);
3398 for (i = 0; i < 1000; i++) {
3400 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3401 (bmsr & BMSR_LSTATUS)) {
3407 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3408 TG3_PHY_REV_BCM5401_B0 &&
3409 !(bmsr & BMSR_LSTATUS) &&
3410 tp->link_config.active_speed == SPEED_1000) {
3411 err = tg3_phy_reset(tp);
3413 err = tg3_init_5401phy_dsp(tp);
3418 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3419 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3420 /* 5701 {A0,B0} CRC bug workaround */
3421 tg3_writephy(tp, 0x15, 0x0a75);
3422 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3423 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3424 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3427 /* Clear pending interrupts... */
3428 tg3_readphy(tp, MII_TG3_ISTAT, &val);
3429 tg3_readphy(tp, MII_TG3_ISTAT, &val);
3431 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3432 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3433 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3434 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3436 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3437 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3438 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3439 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3440 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3442 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3445 current_link_up = 0;
3446 current_speed = SPEED_INVALID;
3447 current_duplex = DUPLEX_INVALID;
3449 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3450 err = tg3_phy_auxctl_read(tp,
3451 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
3453 if (!err && !(val & (1 << 10))) {
3454 tg3_phy_auxctl_write(tp,
3455 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
3462 for (i = 0; i < 100; i++) {
3463 tg3_readphy(tp, MII_BMSR, &bmsr);
3464 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3465 (bmsr & BMSR_LSTATUS))
3470 if (bmsr & BMSR_LSTATUS) {
3473 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3474 for (i = 0; i < 2000; i++) {
3476 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3481 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3486 for (i = 0; i < 200; i++) {
3487 tg3_readphy(tp, MII_BMCR, &bmcr);
3488 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3490 if (bmcr && bmcr != 0x7fff)
3498 tp->link_config.active_speed = current_speed;
3499 tp->link_config.active_duplex = current_duplex;
3501 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3502 if ((bmcr & BMCR_ANENABLE) &&
3503 tg3_copper_is_advertising_all(tp,
3504 tp->link_config.advertising)) {
3505 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3507 current_link_up = 1;
3510 if (!(bmcr & BMCR_ANENABLE) &&
3511 tp->link_config.speed == current_speed &&
3512 tp->link_config.duplex == current_duplex &&
3513 tp->link_config.flowctrl ==
3514 tp->link_config.active_flowctrl) {
3515 current_link_up = 1;
3519 if (current_link_up == 1 &&
3520 tp->link_config.active_duplex == DUPLEX_FULL)
3521 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3525 if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3526 tg3_phy_copper_begin(tp);
3528 tg3_readphy(tp, MII_BMSR, &bmsr);
3529 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
3530 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
3531 current_link_up = 1;
3534 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3535 if (current_link_up == 1) {
3536 if (tp->link_config.active_speed == SPEED_100 ||
3537 tp->link_config.active_speed == SPEED_10)
3538 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3540 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3541 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3542 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3544 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3546 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3547 if (tp->link_config.active_duplex == DUPLEX_HALF)
3548 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3550 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3551 if (current_link_up == 1 &&
3552 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3553 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3555 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3558 /* ??? Without this setting Netgear GA302T PHY does not
3559 * ??? send/receive packets...
3561 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3562 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3563 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3564 tw32_f(MAC_MI_MODE, tp->mi_mode);
3568 tw32_f(MAC_MODE, tp->mac_mode);
3571 tg3_phy_eee_adjust(tp, current_link_up);
3573 if (tg3_flag(tp, USE_LINKCHG_REG)) {
3574 /* Polled via timer. */
3575 tw32_f(MAC_EVENT, 0);
3577 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3581 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3582 current_link_up == 1 &&
3583 tp->link_config.active_speed == SPEED_1000 &&
3584 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
3587 (MAC_STATUS_SYNC_CHANGED |
3588 MAC_STATUS_CFG_CHANGED));
3591 NIC_SRAM_FIRMWARE_MBOX,
3592 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3595 /* Prevent send BD corruption. */
3596 if (tg3_flag(tp, CLKREQ_BUG)) {
3597 u16 oldlnkctl, newlnkctl;
3599 pci_read_config_word(tp->pdev,
3600 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
3602 if (tp->link_config.active_speed == SPEED_100 ||
3603 tp->link_config.active_speed == SPEED_10)
3604 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3606 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3607 if (newlnkctl != oldlnkctl)
3608 pci_write_config_word(tp->pdev,
3609 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
3613 if (current_link_up != netif_carrier_ok(tp->dev)) {
3614 if (current_link_up)
3615 netif_carrier_on(tp->dev);
3617 netif_carrier_off(tp->dev);
3618 tg3_link_report(tp);
3624 struct tg3_fiber_aneginfo {
3626 #define ANEG_STATE_UNKNOWN 0
3627 #define ANEG_STATE_AN_ENABLE 1
3628 #define ANEG_STATE_RESTART_INIT 2
3629 #define ANEG_STATE_RESTART 3
3630 #define ANEG_STATE_DISABLE_LINK_OK 4
3631 #define ANEG_STATE_ABILITY_DETECT_INIT 5
3632 #define ANEG_STATE_ABILITY_DETECT 6
3633 #define ANEG_STATE_ACK_DETECT_INIT 7
3634 #define ANEG_STATE_ACK_DETECT 8
3635 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3636 #define ANEG_STATE_COMPLETE_ACK 10
3637 #define ANEG_STATE_IDLE_DETECT_INIT 11
3638 #define ANEG_STATE_IDLE_DETECT 12
3639 #define ANEG_STATE_LINK_OK 13
3640 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3641 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3644 #define MR_AN_ENABLE 0x00000001
3645 #define MR_RESTART_AN 0x00000002
3646 #define MR_AN_COMPLETE 0x00000004
3647 #define MR_PAGE_RX 0x00000008
3648 #define MR_NP_LOADED 0x00000010
3649 #define MR_TOGGLE_TX 0x00000020
3650 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3651 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3652 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3653 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3654 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3655 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3656 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3657 #define MR_TOGGLE_RX 0x00002000
3658 #define MR_NP_RX 0x00004000
3660 #define MR_LINK_OK 0x80000000
3662 unsigned long link_time, cur_time;
3664 u32 ability_match_cfg;
3665 int ability_match_count;
3667 char ability_match, idle_match, ack_match;
3669 u32 txconfig, rxconfig;
3670 #define ANEG_CFG_NP 0x00000080
3671 #define ANEG_CFG_ACK 0x00000040
3672 #define ANEG_CFG_RF2 0x00000020
3673 #define ANEG_CFG_RF1 0x00000010
3674 #define ANEG_CFG_PS2 0x00000001
3675 #define ANEG_CFG_PS1 0x00008000
3676 #define ANEG_CFG_HD 0x00004000
3677 #define ANEG_CFG_FD 0x00002000
3678 #define ANEG_CFG_INVAL 0x00001f06
3683 #define ANEG_TIMER_ENAB 2
3684 #define ANEG_FAILED -1
3686 #define ANEG_STATE_SETTLE_TIME 10000
3688 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3689 struct tg3_fiber_aneginfo *ap)
3692 unsigned long delta;
3696 if (ap->state == ANEG_STATE_UNKNOWN) {
3700 ap->ability_match_cfg = 0;
3701 ap->ability_match_count = 0;
3702 ap->ability_match = 0;
3708 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3709 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3711 if (rx_cfg_reg != ap->ability_match_cfg) {
3712 ap->ability_match_cfg = rx_cfg_reg;
3713 ap->ability_match = 0;
3714 ap->ability_match_count = 0;
3716 if (++ap->ability_match_count > 1) {
3717 ap->ability_match = 1;
3718 ap->ability_match_cfg = rx_cfg_reg;
3721 if (rx_cfg_reg & ANEG_CFG_ACK)
3729 ap->ability_match_cfg = 0;
3730 ap->ability_match_count = 0;
3731 ap->ability_match = 0;
3737 ap->rxconfig = rx_cfg_reg;
3740 switch (ap->state) {
3741 case ANEG_STATE_UNKNOWN:
3742 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3743 ap->state = ANEG_STATE_AN_ENABLE;
3746 case ANEG_STATE_AN_ENABLE:
3747 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3748 if (ap->flags & MR_AN_ENABLE) {
3751 ap->ability_match_cfg = 0;
3752 ap->ability_match_count = 0;
3753 ap->ability_match = 0;
3757 ap->state = ANEG_STATE_RESTART_INIT;
3759 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3763 case ANEG_STATE_RESTART_INIT:
3764 ap->link_time = ap->cur_time;
3765 ap->flags &= ~(MR_NP_LOADED);
3767 tw32(MAC_TX_AUTO_NEG, 0);
3768 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3769 tw32_f(MAC_MODE, tp->mac_mode);
3772 ret = ANEG_TIMER_ENAB;
3773 ap->state = ANEG_STATE_RESTART;
3776 case ANEG_STATE_RESTART:
3777 delta = ap->cur_time - ap->link_time;
3778 if (delta > ANEG_STATE_SETTLE_TIME)
3779 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3781 ret = ANEG_TIMER_ENAB;
3784 case ANEG_STATE_DISABLE_LINK_OK:
3788 case ANEG_STATE_ABILITY_DETECT_INIT:
3789 ap->flags &= ~(MR_TOGGLE_TX);
3790 ap->txconfig = ANEG_CFG_FD;
3791 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3792 if (flowctrl & ADVERTISE_1000XPAUSE)
3793 ap->txconfig |= ANEG_CFG_PS1;
3794 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3795 ap->txconfig |= ANEG_CFG_PS2;
3796 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3797 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3798 tw32_f(MAC_MODE, tp->mac_mode);
3801 ap->state = ANEG_STATE_ABILITY_DETECT;
3804 case ANEG_STATE_ABILITY_DETECT:
3805 if (ap->ability_match != 0 && ap->rxconfig != 0)
3806 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3809 case ANEG_STATE_ACK_DETECT_INIT:
3810 ap->txconfig |= ANEG_CFG_ACK;
3811 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3812 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3813 tw32_f(MAC_MODE, tp->mac_mode);
3816 ap->state = ANEG_STATE_ACK_DETECT;
3819 case ANEG_STATE_ACK_DETECT:
3820 if (ap->ack_match != 0) {
3821 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3822 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3823 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3825 ap->state = ANEG_STATE_AN_ENABLE;
3827 } else if (ap->ability_match != 0 &&
3828 ap->rxconfig == 0) {
3829 ap->state = ANEG_STATE_AN_ENABLE;
3833 case ANEG_STATE_COMPLETE_ACK_INIT:
3834 if (ap->rxconfig & ANEG_CFG_INVAL) {
3838 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3839 MR_LP_ADV_HALF_DUPLEX |
3840 MR_LP_ADV_SYM_PAUSE |
3841 MR_LP_ADV_ASYM_PAUSE |
3842 MR_LP_ADV_REMOTE_FAULT1 |
3843 MR_LP_ADV_REMOTE_FAULT2 |
3844 MR_LP_ADV_NEXT_PAGE |
3847 if (ap->rxconfig & ANEG_CFG_FD)
3848 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3849 if (ap->rxconfig & ANEG_CFG_HD)
3850 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3851 if (ap->rxconfig & ANEG_CFG_PS1)
3852 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3853 if (ap->rxconfig & ANEG_CFG_PS2)
3854 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3855 if (ap->rxconfig & ANEG_CFG_RF1)
3856 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3857 if (ap->rxconfig & ANEG_CFG_RF2)
3858 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3859 if (ap->rxconfig & ANEG_CFG_NP)
3860 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3862 ap->link_time = ap->cur_time;
3864 ap->flags ^= (MR_TOGGLE_TX);
3865 if (ap->rxconfig & 0x0008)
3866 ap->flags |= MR_TOGGLE_RX;
3867 if (ap->rxconfig & ANEG_CFG_NP)
3868 ap->flags |= MR_NP_RX;
3869 ap->flags |= MR_PAGE_RX;
3871 ap->state = ANEG_STATE_COMPLETE_ACK;
3872 ret = ANEG_TIMER_ENAB;
3875 case ANEG_STATE_COMPLETE_ACK:
3876 if (ap->ability_match != 0 &&
3877 ap->rxconfig == 0) {
3878 ap->state = ANEG_STATE_AN_ENABLE;
3881 delta = ap->cur_time - ap->link_time;
3882 if (delta > ANEG_STATE_SETTLE_TIME) {
3883 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3884 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3886 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3887 !(ap->flags & MR_NP_RX)) {
3888 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3896 case ANEG_STATE_IDLE_DETECT_INIT:
3897 ap->link_time = ap->cur_time;
3898 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3899 tw32_f(MAC_MODE, tp->mac_mode);
3902 ap->state = ANEG_STATE_IDLE_DETECT;
3903 ret = ANEG_TIMER_ENAB;
3906 case ANEG_STATE_IDLE_DETECT:
3907 if (ap->ability_match != 0 &&
3908 ap->rxconfig == 0) {
3909 ap->state = ANEG_STATE_AN_ENABLE;
3912 delta = ap->cur_time - ap->link_time;
3913 if (delta > ANEG_STATE_SETTLE_TIME) {
3914 /* XXX another gem from the Broadcom driver :( */
3915 ap->state = ANEG_STATE_LINK_OK;
3919 case ANEG_STATE_LINK_OK:
3920 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3924 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3925 /* ??? unimplemented */
3928 case ANEG_STATE_NEXT_PAGE_WAIT:
3929 /* ??? unimplemented */
3940 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3943 struct tg3_fiber_aneginfo aninfo;
3944 int status = ANEG_FAILED;
3948 tw32_f(MAC_TX_AUTO_NEG, 0);
3950 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3951 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3954 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3957 memset(&aninfo, 0, sizeof(aninfo));
3958 aninfo.flags |= MR_AN_ENABLE;
3959 aninfo.state = ANEG_STATE_UNKNOWN;
3960 aninfo.cur_time = 0;
3962 while (++tick < 195000) {
3963 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3964 if (status == ANEG_DONE || status == ANEG_FAILED)
3970 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3971 tw32_f(MAC_MODE, tp->mac_mode);
3974 *txflags = aninfo.txconfig;
3975 *rxflags = aninfo.flags;
3977 if (status == ANEG_DONE &&
3978 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3979 MR_LP_ADV_FULL_DUPLEX)))
3985 static void tg3_init_bcm8002(struct tg3 *tp)
3987 u32 mac_status = tr32(MAC_STATUS);
3990 /* Reset when initting first time or we have a link. */
3991 if (tg3_flag(tp, INIT_COMPLETE) &&
3992 !(mac_status & MAC_STATUS_PCS_SYNCED))
3995 /* Set PLL lock range. */
3996 tg3_writephy(tp, 0x16, 0x8007);
3999 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
4001 /* Wait for reset to complete. */
4002 /* XXX schedule_timeout() ... */
4003 for (i = 0; i < 500; i++)
4006 /* Config mode; select PMA/Ch 1 regs. */
4007 tg3_writephy(tp, 0x10, 0x8411);
4009 /* Enable auto-lock and comdet, select txclk for tx. */
4010 tg3_writephy(tp, 0x11, 0x0a10);
4012 tg3_writephy(tp, 0x18, 0x00a0);
4013 tg3_writephy(tp, 0x16, 0x41ff);
4015 /* Assert and deassert POR. */
4016 tg3_writephy(tp, 0x13, 0x0400);
4018 tg3_writephy(tp, 0x13, 0x0000);
4020 tg3_writephy(tp, 0x11, 0x0a50);
4022 tg3_writephy(tp, 0x11, 0x0a10);
4024 /* Wait for signal to stabilize */
4025 /* XXX schedule_timeout() ... */
4026 for (i = 0; i < 15000; i++)
4029 /* Deselect the channel register so we can read the PHYID
4032 tg3_writephy(tp, 0x10, 0x8011);
4035 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
4038 u32 sg_dig_ctrl, sg_dig_status;
4039 u32 serdes_cfg, expected_sg_dig_ctrl;
4040 int workaround, port_a;
4041 int current_link_up;
4044 expected_sg_dig_ctrl = 0;
4047 current_link_up = 0;
4049 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
4050 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
4052 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
4055 /* preserve bits 0-11,13,14 for signal pre-emphasis */
4056 /* preserve bits 20-23 for voltage regulator */
4057 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
4060 sg_dig_ctrl = tr32(SG_DIG_CTRL);
4062 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
4063 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
4065 u32 val = serdes_cfg;
4071 tw32_f(MAC_SERDES_CFG, val);
4074 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
4076 if (mac_status & MAC_STATUS_PCS_SYNCED) {
4077 tg3_setup_flow_control(tp, 0, 0);
4078 current_link_up = 1;
4083 /* Want auto-negotiation. */
4084 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
4086 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4087 if (flowctrl & ADVERTISE_1000XPAUSE)
4088 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
4089 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
4090 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
4092 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
4093 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
4094 tp->serdes_counter &&
4095 ((mac_status & (MAC_STATUS_PCS_SYNCED |
4096 MAC_STATUS_RCVD_CFG)) ==
4097 MAC_STATUS_PCS_SYNCED)) {
4098 tp->serdes_counter--;
4099 current_link_up = 1;
4104 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
4105 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
4107 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
4109 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
4110 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4111 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
4112 MAC_STATUS_SIGNAL_DET)) {
4113 sg_dig_status = tr32(SG_DIG_STATUS);
4114 mac_status = tr32(MAC_STATUS);
4116 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
4117 (mac_status & MAC_STATUS_PCS_SYNCED)) {
4118 u32 local_adv = 0, remote_adv = 0;
4120 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
4121 local_adv |= ADVERTISE_1000XPAUSE;
4122 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
4123 local_adv |= ADVERTISE_1000XPSE_ASYM;
4125 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
4126 remote_adv |= LPA_1000XPAUSE;
4127 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
4128 remote_adv |= LPA_1000XPAUSE_ASYM;
4130 tg3_setup_flow_control(tp, local_adv, remote_adv);
4131 current_link_up = 1;
4132 tp->serdes_counter = 0;
4133 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4134 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
4135 if (tp->serdes_counter)
4136 tp->serdes_counter--;
4139 u32 val = serdes_cfg;
4146 tw32_f(MAC_SERDES_CFG, val);
4149 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
4152 /* Link parallel detection - link is up */
4153 /* only if we have PCS_SYNC and not */
4154 /* receiving config code words */
4155 mac_status = tr32(MAC_STATUS);
4156 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
4157 !(mac_status & MAC_STATUS_RCVD_CFG)) {
4158 tg3_setup_flow_control(tp, 0, 0);
4159 current_link_up = 1;
4161 TG3_PHYFLG_PARALLEL_DETECT;
4162 tp->serdes_counter =
4163 SERDES_PARALLEL_DET_TIMEOUT;
4165 goto restart_autoneg;
4169 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
4170 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4174 return current_link_up;
4177 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
4179 int current_link_up = 0;
4181 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
4184 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4185 u32 txflags, rxflags;
4188 if (fiber_autoneg(tp, &txflags, &rxflags)) {
4189 u32 local_adv = 0, remote_adv = 0;
4191 if (txflags & ANEG_CFG_PS1)
4192 local_adv |= ADVERTISE_1000XPAUSE;
4193 if (txflags & ANEG_CFG_PS2)
4194 local_adv |= ADVERTISE_1000XPSE_ASYM;
4196 if (rxflags & MR_LP_ADV_SYM_PAUSE)
4197 remote_adv |= LPA_1000XPAUSE;
4198 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
4199 remote_adv |= LPA_1000XPAUSE_ASYM;
4201 tg3_setup_flow_control(tp, local_adv, remote_adv);
4203 current_link_up = 1;
4205 for (i = 0; i < 30; i++) {
4208 (MAC_STATUS_SYNC_CHANGED |
4209 MAC_STATUS_CFG_CHANGED));
4211 if ((tr32(MAC_STATUS) &
4212 (MAC_STATUS_SYNC_CHANGED |
4213 MAC_STATUS_CFG_CHANGED)) == 0)
4217 mac_status = tr32(MAC_STATUS);
4218 if (current_link_up == 0 &&
4219 (mac_status & MAC_STATUS_PCS_SYNCED) &&
4220 !(mac_status & MAC_STATUS_RCVD_CFG))
4221 current_link_up = 1;
4223 tg3_setup_flow_control(tp, 0, 0);
4225 /* Forcing 1000FD link up. */
4226 current_link_up = 1;
4228 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
4231 tw32_f(MAC_MODE, tp->mac_mode);
4236 return current_link_up;
4239 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4242 u16 orig_active_speed;
4243 u8 orig_active_duplex;
4245 int current_link_up;
4248 orig_pause_cfg = tp->link_config.active_flowctrl;
4249 orig_active_speed = tp->link_config.active_speed;
4250 orig_active_duplex = tp->link_config.active_duplex;
4252 if (!tg3_flag(tp, HW_AUTONEG) &&
4253 netif_carrier_ok(tp->dev) &&
4254 tg3_flag(tp, INIT_COMPLETE)) {
4255 mac_status = tr32(MAC_STATUS);
4256 mac_status &= (MAC_STATUS_PCS_SYNCED |
4257 MAC_STATUS_SIGNAL_DET |
4258 MAC_STATUS_CFG_CHANGED |
4259 MAC_STATUS_RCVD_CFG);
4260 if (mac_status == (MAC_STATUS_PCS_SYNCED |
4261 MAC_STATUS_SIGNAL_DET)) {
4262 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4263 MAC_STATUS_CFG_CHANGED));
4268 tw32_f(MAC_TX_AUTO_NEG, 0);
4270 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
4271 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
4272 tw32_f(MAC_MODE, tp->mac_mode);
4275 if (tp->phy_id == TG3_PHY_ID_BCM8002)
4276 tg3_init_bcm8002(tp);
4278 /* Enable link change event even when serdes polling. */
4279 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4282 current_link_up = 0;
4283 mac_status = tr32(MAC_STATUS);
4285 if (tg3_flag(tp, HW_AUTONEG))
4286 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4288 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4290 tp->napi[0].hw_status->status =
4291 (SD_STATUS_UPDATED |
4292 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4294 for (i = 0; i < 100; i++) {
4295 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4296 MAC_STATUS_CFG_CHANGED));
4298 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4299 MAC_STATUS_CFG_CHANGED |
4300 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4304 mac_status = tr32(MAC_STATUS);
4305 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4306 current_link_up = 0;
4307 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4308 tp->serdes_counter == 0) {
4309 tw32_f(MAC_MODE, (tp->mac_mode |
4310 MAC_MODE_SEND_CONFIGS));
4312 tw32_f(MAC_MODE, tp->mac_mode);
4316 if (current_link_up == 1) {
4317 tp->link_config.active_speed = SPEED_1000;
4318 tp->link_config.active_duplex = DUPLEX_FULL;
4319 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4320 LED_CTRL_LNKLED_OVERRIDE |
4321 LED_CTRL_1000MBPS_ON));
4323 tp->link_config.active_speed = SPEED_INVALID;
4324 tp->link_config.active_duplex = DUPLEX_INVALID;
4325 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4326 LED_CTRL_LNKLED_OVERRIDE |
4327 LED_CTRL_TRAFFIC_OVERRIDE));
4330 if (current_link_up != netif_carrier_ok(tp->dev)) {
4331 if (current_link_up)
4332 netif_carrier_on(tp->dev);
4334 netif_carrier_off(tp->dev);
4335 tg3_link_report(tp);
4337 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4338 if (orig_pause_cfg != now_pause_cfg ||
4339 orig_active_speed != tp->link_config.active_speed ||
4340 orig_active_duplex != tp->link_config.active_duplex)
4341 tg3_link_report(tp);
4347 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4349 int current_link_up, err = 0;
4353 u32 local_adv, remote_adv;
4355 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4356 tw32_f(MAC_MODE, tp->mac_mode);
4362 (MAC_STATUS_SYNC_CHANGED |
4363 MAC_STATUS_CFG_CHANGED |
4364 MAC_STATUS_MI_COMPLETION |
4365 MAC_STATUS_LNKSTATE_CHANGED));
4371 current_link_up = 0;
4372 current_speed = SPEED_INVALID;
4373 current_duplex = DUPLEX_INVALID;
4375 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4376 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4377 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4378 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4379 bmsr |= BMSR_LSTATUS;
4381 bmsr &= ~BMSR_LSTATUS;
4384 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4386 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4387 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4388 /* do nothing, just check for link up at the end */
4389 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4392 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4393 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4394 ADVERTISE_1000XPAUSE |
4395 ADVERTISE_1000XPSE_ASYM |
4398 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4400 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4401 new_adv |= ADVERTISE_1000XHALF;
4402 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4403 new_adv |= ADVERTISE_1000XFULL;
4405 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4406 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4407 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4408 tg3_writephy(tp, MII_BMCR, bmcr);
4410 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4411 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4412 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4419 bmcr &= ~BMCR_SPEED1000;
4420 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4422 if (tp->link_config.duplex == DUPLEX_FULL)
4423 new_bmcr |= BMCR_FULLDPLX;
4425 if (new_bmcr != bmcr) {
4426 /* BMCR_SPEED1000 is a reserved bit that needs
4427 * to be set on write.
4429 new_bmcr |= BMCR_SPEED1000;
4431 /* Force a linkdown */
4432 if (netif_carrier_ok(tp->dev)) {
4435 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4436 adv &= ~(ADVERTISE_1000XFULL |
4437 ADVERTISE_1000XHALF |
4439 tg3_writephy(tp, MII_ADVERTISE, adv);
4440 tg3_writephy(tp, MII_BMCR, bmcr |
4444 netif_carrier_off(tp->dev);
4446 tg3_writephy(tp, MII_BMCR, new_bmcr);
4448 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4449 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4450 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4452 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4453 bmsr |= BMSR_LSTATUS;
4455 bmsr &= ~BMSR_LSTATUS;
4457 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4461 if (bmsr & BMSR_LSTATUS) {
4462 current_speed = SPEED_1000;
4463 current_link_up = 1;
4464 if (bmcr & BMCR_FULLDPLX)
4465 current_duplex = DUPLEX_FULL;
4467 current_duplex = DUPLEX_HALF;
4472 if (bmcr & BMCR_ANENABLE) {
4475 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4476 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4477 common = local_adv & remote_adv;
4478 if (common & (ADVERTISE_1000XHALF |
4479 ADVERTISE_1000XFULL)) {
4480 if (common & ADVERTISE_1000XFULL)
4481 current_duplex = DUPLEX_FULL;
4483 current_duplex = DUPLEX_HALF;
4484 } else if (!tg3_flag(tp, 5780_CLASS)) {
4485 /* Link is up via parallel detect */
4487 current_link_up = 0;
4492 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4493 tg3_setup_flow_control(tp, local_adv, remote_adv);
4495 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4496 if (tp->link_config.active_duplex == DUPLEX_HALF)
4497 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4499 tw32_f(MAC_MODE, tp->mac_mode);
4502 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4504 tp->link_config.active_speed = current_speed;
4505 tp->link_config.active_duplex = current_duplex;
4507 if (current_link_up != netif_carrier_ok(tp->dev)) {
4508 if (current_link_up)
4509 netif_carrier_on(tp->dev);
4511 netif_carrier_off(tp->dev);
4512 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4514 tg3_link_report(tp);
4519 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4521 if (tp->serdes_counter) {
4522 /* Give autoneg time to complete. */
4523 tp->serdes_counter--;
4527 if (!netif_carrier_ok(tp->dev) &&
4528 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4531 tg3_readphy(tp, MII_BMCR, &bmcr);
4532 if (bmcr & BMCR_ANENABLE) {
4535 /* Select shadow register 0x1f */
4536 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4537 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4539 /* Select expansion interrupt status register */
4540 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4541 MII_TG3_DSP_EXP1_INT_STAT);
4542 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4543 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4545 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4546 /* We have signal detect and not receiving
4547 * config code words, link is up by parallel
4551 bmcr &= ~BMCR_ANENABLE;
4552 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4553 tg3_writephy(tp, MII_BMCR, bmcr);
4554 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4557 } else if (netif_carrier_ok(tp->dev) &&
4558 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4559 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4562 /* Select expansion interrupt status register */
4563 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4564 MII_TG3_DSP_EXP1_INT_STAT);
4565 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4569 /* Config code words received, turn on autoneg. */
4570 tg3_readphy(tp, MII_BMCR, &bmcr);
4571 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4573 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4579 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4584 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4585 err = tg3_setup_fiber_phy(tp, force_reset);
4586 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4587 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4589 err = tg3_setup_copper_phy(tp, force_reset);
4591 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4594 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4595 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4597 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4602 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4603 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4604 tw32(GRC_MISC_CFG, val);
4607 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4608 (6 << TX_LENGTHS_IPG_SHIFT);
4609 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
4610 val |= tr32(MAC_TX_LENGTHS) &
4611 (TX_LENGTHS_JMB_FRM_LEN_MSK |
4612 TX_LENGTHS_CNT_DWN_VAL_MSK);
4614 if (tp->link_config.active_speed == SPEED_1000 &&
4615 tp->link_config.active_duplex == DUPLEX_HALF)
4616 tw32(MAC_TX_LENGTHS, val |
4617 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
4619 tw32(MAC_TX_LENGTHS, val |
4620 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
4622 if (!tg3_flag(tp, 5705_PLUS)) {
4623 if (netif_carrier_ok(tp->dev)) {
4624 tw32(HOSTCC_STAT_COAL_TICKS,
4625 tp->coal.stats_block_coalesce_usecs);
4627 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4631 if (tg3_flag(tp, ASPM_WORKAROUND)) {
4632 val = tr32(PCIE_PWR_MGMT_THRESH);
4633 if (!netif_carrier_ok(tp->dev))
4634 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4637 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4638 tw32(PCIE_PWR_MGMT_THRESH, val);
4644 static inline int tg3_irq_sync(struct tg3 *tp)
4646 return tp->irq_sync;
4649 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
4653 dst = (u32 *)((u8 *)dst + off);
4654 for (i = 0; i < len; i += sizeof(u32))
4655 *dst++ = tr32(off + i);
4658 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
4660 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
4661 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
4662 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
4663 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
4664 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
4665 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
4666 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
4667 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
4668 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
4669 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
4670 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
4671 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
4672 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
4673 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
4674 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
4675 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
4676 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
4677 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
4678 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
4680 if (tg3_flag(tp, SUPPORT_MSIX))
4681 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
4683 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
4684 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
4685 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
4686 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
4687 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
4688 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
4689 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
4690 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
4692 if (!tg3_flag(tp, 5705_PLUS)) {
4693 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
4694 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
4695 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
4698 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
4699 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
4700 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
4701 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
4702 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
4704 if (tg3_flag(tp, NVRAM))
4705 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
4708 static void tg3_dump_state(struct tg3 *tp)
4713 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
4715 netdev_err(tp->dev, "Failed allocating register dump buffer\n");
4719 if (tg3_flag(tp, PCI_EXPRESS)) {
4720 /* Read up to but not including private PCI registers */
4721 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
4722 regs[i / sizeof(u32)] = tr32(i);
4724 tg3_dump_legacy_regs(tp, regs);
4726 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
4727 if (!regs[i + 0] && !regs[i + 1] &&
4728 !regs[i + 2] && !regs[i + 3])
4731 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
4733 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
4738 for (i = 0; i < tp->irq_cnt; i++) {
4739 struct tg3_napi *tnapi = &tp->napi[i];
4741 /* SW status block */
4743 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
4745 tnapi->hw_status->status,
4746 tnapi->hw_status->status_tag,
4747 tnapi->hw_status->rx_jumbo_consumer,
4748 tnapi->hw_status->rx_consumer,
4749 tnapi->hw_status->rx_mini_consumer,
4750 tnapi->hw_status->idx[0].rx_producer,
4751 tnapi->hw_status->idx[0].tx_consumer);
4754 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
4756 tnapi->last_tag, tnapi->last_irq_tag,
4757 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
4759 tnapi->prodring.rx_std_prod_idx,
4760 tnapi->prodring.rx_std_cons_idx,
4761 tnapi->prodring.rx_jmb_prod_idx,
4762 tnapi->prodring.rx_jmb_cons_idx);
4766 /* This is called whenever we suspect that the system chipset is re-
4767 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4768 * is bogus tx completions. We try to recover by setting the
4769 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4772 static void tg3_tx_recover(struct tg3 *tp)
4774 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
4775 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4777 netdev_warn(tp->dev,
4778 "The system may be re-ordering memory-mapped I/O "
4779 "cycles to the network device, attempting to recover. "
4780 "Please report the problem to the driver maintainer "
4781 "and include system chipset information.\n");
4783 spin_lock(&tp->lock);
4784 tg3_flag_set(tp, TX_RECOVERY_PENDING);
4785 spin_unlock(&tp->lock);
4788 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4790 /* Tell compiler to fetch tx indices from memory. */
4792 return tnapi->tx_pending -
4793 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4796 /* Tigon3 never reports partial packet sends. So we do not
4797 * need special logic to handle SKBs that have not had all
4798 * of their frags sent yet, like SunGEM does.
4800 static void tg3_tx(struct tg3_napi *tnapi)
4802 struct tg3 *tp = tnapi->tp;
4803 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4804 u32 sw_idx = tnapi->tx_cons;
4805 struct netdev_queue *txq;
4806 int index = tnapi - tp->napi;
4808 if (tg3_flag(tp, ENABLE_TSS))
4811 txq = netdev_get_tx_queue(tp->dev, index);
4813 while (sw_idx != hw_idx) {
4814 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4815 struct sk_buff *skb = ri->skb;
4818 if (unlikely(skb == NULL)) {
4823 pci_unmap_single(tp->pdev,
4824 dma_unmap_addr(ri, mapping),
4830 sw_idx = NEXT_TX(sw_idx);
4832 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4833 ri = &tnapi->tx_buffers[sw_idx];
4834 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4837 pci_unmap_page(tp->pdev,
4838 dma_unmap_addr(ri, mapping),
4839 skb_shinfo(skb)->frags[i].size,
4841 sw_idx = NEXT_TX(sw_idx);
4846 if (unlikely(tx_bug)) {
4852 tnapi->tx_cons = sw_idx;
4854 /* Need to make the tx_cons update visible to tg3_start_xmit()
4855 * before checking for netif_queue_stopped(). Without the
4856 * memory barrier, there is a small possibility that tg3_start_xmit()
4857 * will miss it and cause the queue to be stopped forever.
4861 if (unlikely(netif_tx_queue_stopped(txq) &&
4862 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4863 __netif_tx_lock(txq, smp_processor_id());
4864 if (netif_tx_queue_stopped(txq) &&
4865 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4866 netif_tx_wake_queue(txq);
4867 __netif_tx_unlock(txq);
4871 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4876 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4877 map_sz, PCI_DMA_FROMDEVICE);
4878 dev_kfree_skb_any(ri->skb);
4882 /* Returns size of skb allocated or < 0 on error.
4884 * We only need to fill in the address because the other members
4885 * of the RX descriptor are invariant, see tg3_init_rings.
4887 * Note the purposeful assymetry of cpu vs. chip accesses. For
4888 * posting buffers we only dirty the first cache line of the RX
4889 * descriptor (containing the address). Whereas for the RX status
4890 * buffers the cpu only reads the last cacheline of the RX descriptor
4891 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4893 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4894 u32 opaque_key, u32 dest_idx_unmasked)
4896 struct tg3_rx_buffer_desc *desc;
4897 struct ring_info *map;
4898 struct sk_buff *skb;
4900 int skb_size, dest_idx;
4902 switch (opaque_key) {
4903 case RXD_OPAQUE_RING_STD:
4904 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4905 desc = &tpr->rx_std[dest_idx];
4906 map = &tpr->rx_std_buffers[dest_idx];
4907 skb_size = tp->rx_pkt_map_sz;
4910 case RXD_OPAQUE_RING_JUMBO:
4911 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4912 desc = &tpr->rx_jmb[dest_idx].std;
4913 map = &tpr->rx_jmb_buffers[dest_idx];
4914 skb_size = TG3_RX_JMB_MAP_SZ;
4921 /* Do not overwrite any of the map or rp information
4922 * until we are sure we can commit to a new buffer.
4924 * Callers depend upon this behavior and assume that
4925 * we leave everything unchanged if we fail.
4927 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4931 skb_reserve(skb, tp->rx_offset);
4933 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4934 PCI_DMA_FROMDEVICE);
4935 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4941 dma_unmap_addr_set(map, mapping, mapping);
4943 desc->addr_hi = ((u64)mapping >> 32);
4944 desc->addr_lo = ((u64)mapping & 0xffffffff);
4949 /* We only need to move over in the address because the other
4950 * members of the RX descriptor are invariant. See notes above
4951 * tg3_alloc_rx_skb for full details.
4953 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4954 struct tg3_rx_prodring_set *dpr,
4955 u32 opaque_key, int src_idx,
4956 u32 dest_idx_unmasked)
4958 struct tg3 *tp = tnapi->tp;
4959 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4960 struct ring_info *src_map, *dest_map;
4961 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
4964 switch (opaque_key) {
4965 case RXD_OPAQUE_RING_STD:
4966 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4967 dest_desc = &dpr->rx_std[dest_idx];
4968 dest_map = &dpr->rx_std_buffers[dest_idx];
4969 src_desc = &spr->rx_std[src_idx];
4970 src_map = &spr->rx_std_buffers[src_idx];
4973 case RXD_OPAQUE_RING_JUMBO:
4974 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4975 dest_desc = &dpr->rx_jmb[dest_idx].std;
4976 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4977 src_desc = &spr->rx_jmb[src_idx].std;
4978 src_map = &spr->rx_jmb_buffers[src_idx];
4985 dest_map->skb = src_map->skb;
4986 dma_unmap_addr_set(dest_map, mapping,
4987 dma_unmap_addr(src_map, mapping));
4988 dest_desc->addr_hi = src_desc->addr_hi;
4989 dest_desc->addr_lo = src_desc->addr_lo;
4991 /* Ensure that the update to the skb happens after the physical
4992 * addresses have been transferred to the new BD location.
4996 src_map->skb = NULL;
4999 /* The RX ring scheme is composed of multiple rings which post fresh
5000 * buffers to the chip, and one special ring the chip uses to report
5001 * status back to the host.
5003 * The special ring reports the status of received packets to the
5004 * host. The chip does not write into the original descriptor the
5005 * RX buffer was obtained from. The chip simply takes the original
5006 * descriptor as provided by the host, updates the status and length
5007 * field, then writes this into the next status ring entry.
5009 * Each ring the host uses to post buffers to the chip is described
5010 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
5011 * it is first placed into the on-chip ram. When the packet's length
5012 * is known, it walks down the TG3_BDINFO entries to select the ring.
5013 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
5014 * which is within the range of the new packet's length is chosen.
5016 * The "separate ring for rx status" scheme may sound queer, but it makes
5017 * sense from a cache coherency perspective. If only the host writes
5018 * to the buffer post rings, and only the chip writes to the rx status
5019 * rings, then cache lines never move beyond shared-modified state.
5020 * If both the host and chip were to write into the same ring, cache line
5021 * eviction could occur since both entities want it in an exclusive state.
5023 static int tg3_rx(struct tg3_napi *tnapi, int budget)
5025 struct tg3 *tp = tnapi->tp;
5026 u32 work_mask, rx_std_posted = 0;
5027 u32 std_prod_idx, jmb_prod_idx;
5028 u32 sw_idx = tnapi->rx_rcb_ptr;
5031 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
5033 hw_idx = *(tnapi->rx_rcb_prod_idx);
5035 * We need to order the read of hw_idx and the read of
5036 * the opaque cookie.
5041 std_prod_idx = tpr->rx_std_prod_idx;
5042 jmb_prod_idx = tpr->rx_jmb_prod_idx;
5043 while (sw_idx != hw_idx && budget > 0) {
5044 struct ring_info *ri;
5045 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
5047 struct sk_buff *skb;
5048 dma_addr_t dma_addr;
5049 u32 opaque_key, desc_idx, *post_ptr;
5051 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
5052 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
5053 if (opaque_key == RXD_OPAQUE_RING_STD) {
5054 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
5055 dma_addr = dma_unmap_addr(ri, mapping);
5057 post_ptr = &std_prod_idx;
5059 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
5060 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
5061 dma_addr = dma_unmap_addr(ri, mapping);
5063 post_ptr = &jmb_prod_idx;
5065 goto next_pkt_nopost;
5067 work_mask |= opaque_key;
5069 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
5070 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
5072 tg3_recycle_rx(tnapi, tpr, opaque_key,
5073 desc_idx, *post_ptr);
5075 /* Other statistics kept track of by card. */
5080 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
5083 if (len > TG3_RX_COPY_THRESH(tp)) {
5086 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
5091 pci_unmap_single(tp->pdev, dma_addr, skb_size,
5092 PCI_DMA_FROMDEVICE);
5094 /* Ensure that the update to the skb happens
5095 * after the usage of the old DMA mapping.
5103 struct sk_buff *copy_skb;
5105 tg3_recycle_rx(tnapi, tpr, opaque_key,
5106 desc_idx, *post_ptr);
5108 copy_skb = netdev_alloc_skb(tp->dev, len +
5110 if (copy_skb == NULL)
5111 goto drop_it_no_recycle;
5113 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
5114 skb_put(copy_skb, len);
5115 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
5116 skb_copy_from_linear_data(skb, copy_skb->data, len);
5117 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
5119 /* We'll reuse the original ring buffer. */
5123 if ((tp->dev->features & NETIF_F_RXCSUM) &&
5124 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
5125 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
5126 >> RXD_TCPCSUM_SHIFT) == 0xffff))
5127 skb->ip_summed = CHECKSUM_UNNECESSARY;
5129 skb_checksum_none_assert(skb);
5131 skb->protocol = eth_type_trans(skb, tp->dev);
5133 if (len > (tp->dev->mtu + ETH_HLEN) &&
5134 skb->protocol != htons(ETH_P_8021Q)) {
5136 goto drop_it_no_recycle;
5139 if (desc->type_flags & RXD_FLAG_VLAN &&
5140 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
5141 __vlan_hwaccel_put_tag(skb,
5142 desc->err_vlan & RXD_VLAN_MASK);
5144 napi_gro_receive(&tnapi->napi, skb);
5152 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
5153 tpr->rx_std_prod_idx = std_prod_idx &
5154 tp->rx_std_ring_mask;
5155 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5156 tpr->rx_std_prod_idx);
5157 work_mask &= ~RXD_OPAQUE_RING_STD;
5162 sw_idx &= tp->rx_ret_ring_mask;
5164 /* Refresh hw_idx to see if there is new work */
5165 if (sw_idx == hw_idx) {
5166 hw_idx = *(tnapi->rx_rcb_prod_idx);
5171 /* ACK the status ring. */
5172 tnapi->rx_rcb_ptr = sw_idx;
5173 tw32_rx_mbox(tnapi->consmbox, sw_idx);
5175 /* Refill RX ring(s). */
5176 if (!tg3_flag(tp, ENABLE_RSS)) {
5177 if (work_mask & RXD_OPAQUE_RING_STD) {
5178 tpr->rx_std_prod_idx = std_prod_idx &
5179 tp->rx_std_ring_mask;
5180 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5181 tpr->rx_std_prod_idx);
5183 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
5184 tpr->rx_jmb_prod_idx = jmb_prod_idx &
5185 tp->rx_jmb_ring_mask;
5186 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5187 tpr->rx_jmb_prod_idx);
5190 } else if (work_mask) {
5191 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
5192 * updated before the producer indices can be updated.
5196 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
5197 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
5199 if (tnapi != &tp->napi[1])
5200 napi_schedule(&tp->napi[1].napi);
5206 static void tg3_poll_link(struct tg3 *tp)
5208 /* handle link change and other phy events */
5209 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
5210 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
5212 if (sblk->status & SD_STATUS_LINK_CHG) {
5213 sblk->status = SD_STATUS_UPDATED |
5214 (sblk->status & ~SD_STATUS_LINK_CHG);
5215 spin_lock(&tp->lock);
5216 if (tg3_flag(tp, USE_PHYLIB)) {
5218 (MAC_STATUS_SYNC_CHANGED |
5219 MAC_STATUS_CFG_CHANGED |
5220 MAC_STATUS_MI_COMPLETION |
5221 MAC_STATUS_LNKSTATE_CHANGED));
5224 tg3_setup_phy(tp, 0);
5225 spin_unlock(&tp->lock);
5230 static int tg3_rx_prodring_xfer(struct tg3 *tp,
5231 struct tg3_rx_prodring_set *dpr,
5232 struct tg3_rx_prodring_set *spr)
5234 u32 si, di, cpycnt, src_prod_idx;
5238 src_prod_idx = spr->rx_std_prod_idx;
5240 /* Make sure updates to the rx_std_buffers[] entries and the
5241 * standard producer index are seen in the correct order.
5245 if (spr->rx_std_cons_idx == src_prod_idx)
5248 if (spr->rx_std_cons_idx < src_prod_idx)
5249 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
5251 cpycnt = tp->rx_std_ring_mask + 1 -
5252 spr->rx_std_cons_idx;
5254 cpycnt = min(cpycnt,
5255 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
5257 si = spr->rx_std_cons_idx;
5258 di = dpr->rx_std_prod_idx;
5260 for (i = di; i < di + cpycnt; i++) {
5261 if (dpr->rx_std_buffers[i].skb) {
5271 /* Ensure that updates to the rx_std_buffers ring and the
5272 * shadowed hardware producer ring from tg3_recycle_skb() are
5273 * ordered correctly WRT the skb check above.
5277 memcpy(&dpr->rx_std_buffers[di],
5278 &spr->rx_std_buffers[si],
5279 cpycnt * sizeof(struct ring_info));
5281 for (i = 0; i < cpycnt; i++, di++, si++) {
5282 struct tg3_rx_buffer_desc *sbd, *dbd;
5283 sbd = &spr->rx_std[si];
5284 dbd = &dpr->rx_std[di];
5285 dbd->addr_hi = sbd->addr_hi;
5286 dbd->addr_lo = sbd->addr_lo;
5289 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
5290 tp->rx_std_ring_mask;
5291 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
5292 tp->rx_std_ring_mask;
5296 src_prod_idx = spr->rx_jmb_prod_idx;
5298 /* Make sure updates to the rx_jmb_buffers[] entries and
5299 * the jumbo producer index are seen in the correct order.
5303 if (spr->rx_jmb_cons_idx == src_prod_idx)
5306 if (spr->rx_jmb_cons_idx < src_prod_idx)
5307 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
5309 cpycnt = tp->rx_jmb_ring_mask + 1 -
5310 spr->rx_jmb_cons_idx;
5312 cpycnt = min(cpycnt,
5313 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
5315 si = spr->rx_jmb_cons_idx;
5316 di = dpr->rx_jmb_prod_idx;
5318 for (i = di; i < di + cpycnt; i++) {
5319 if (dpr->rx_jmb_buffers[i].skb) {
5329 /* Ensure that updates to the rx_jmb_buffers ring and the
5330 * shadowed hardware producer ring from tg3_recycle_skb() are
5331 * ordered correctly WRT the skb check above.
5335 memcpy(&dpr->rx_jmb_buffers[di],
5336 &spr->rx_jmb_buffers[si],
5337 cpycnt * sizeof(struct ring_info));
5339 for (i = 0; i < cpycnt; i++, di++, si++) {
5340 struct tg3_rx_buffer_desc *sbd, *dbd;
5341 sbd = &spr->rx_jmb[si].std;
5342 dbd = &dpr->rx_jmb[di].std;
5343 dbd->addr_hi = sbd->addr_hi;
5344 dbd->addr_lo = sbd->addr_lo;
5347 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
5348 tp->rx_jmb_ring_mask;
5349 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
5350 tp->rx_jmb_ring_mask;
5356 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
5358 struct tg3 *tp = tnapi->tp;
5360 /* run TX completion thread */
5361 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
5363 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
5367 /* run RX thread, within the bounds set by NAPI.
5368 * All RX "locking" is done by ensuring outside
5369 * code synchronizes with tg3->napi.poll()
5371 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
5372 work_done += tg3_rx(tnapi, budget - work_done);
5374 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
5375 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
5377 u32 std_prod_idx = dpr->rx_std_prod_idx;
5378 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
5380 for (i = 1; i < tp->irq_cnt; i++)
5381 err |= tg3_rx_prodring_xfer(tp, dpr,
5382 &tp->napi[i].prodring);
5386 if (std_prod_idx != dpr->rx_std_prod_idx)
5387 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5388 dpr->rx_std_prod_idx);
5390 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5391 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5392 dpr->rx_jmb_prod_idx);
5397 tw32_f(HOSTCC_MODE, tp->coal_now);
5403 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5405 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5406 struct tg3 *tp = tnapi->tp;
5408 struct tg3_hw_status *sblk = tnapi->hw_status;
5411 work_done = tg3_poll_work(tnapi, work_done, budget);
5413 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
5416 if (unlikely(work_done >= budget))
5419 /* tp->last_tag is used in tg3_int_reenable() below
5420 * to tell the hw how much work has been processed,
5421 * so we must read it before checking for more work.
5423 tnapi->last_tag = sblk->status_tag;
5424 tnapi->last_irq_tag = tnapi->last_tag;
5427 /* check for RX/TX work to do */
5428 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5429 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5430 napi_complete(napi);
5431 /* Reenable interrupts. */
5432 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5441 /* work_done is guaranteed to be less than budget. */
5442 napi_complete(napi);
5443 schedule_work(&tp->reset_task);
5447 static void tg3_process_error(struct tg3 *tp)
5450 bool real_error = false;
5452 if (tg3_flag(tp, ERROR_PROCESSED))
5455 /* Check Flow Attention register */
5456 val = tr32(HOSTCC_FLOW_ATTN);
5457 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
5458 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
5462 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
5463 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
5467 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
5468 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
5477 tg3_flag_set(tp, ERROR_PROCESSED);
5478 schedule_work(&tp->reset_task);
5481 static int tg3_poll(struct napi_struct *napi, int budget)
5483 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5484 struct tg3 *tp = tnapi->tp;
5486 struct tg3_hw_status *sblk = tnapi->hw_status;
5489 if (sblk->status & SD_STATUS_ERROR)
5490 tg3_process_error(tp);
5494 work_done = tg3_poll_work(tnapi, work_done, budget);
5496 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
5499 if (unlikely(work_done >= budget))
5502 if (tg3_flag(tp, TAGGED_STATUS)) {
5503 /* tp->last_tag is used in tg3_int_reenable() below
5504 * to tell the hw how much work has been processed,
5505 * so we must read it before checking for more work.
5507 tnapi->last_tag = sblk->status_tag;
5508 tnapi->last_irq_tag = tnapi->last_tag;
5511 sblk->status &= ~SD_STATUS_UPDATED;
5513 if (likely(!tg3_has_work(tnapi))) {
5514 napi_complete(napi);
5515 tg3_int_reenable(tnapi);
5523 /* work_done is guaranteed to be less than budget. */
5524 napi_complete(napi);
5525 schedule_work(&tp->reset_task);
5529 static void tg3_napi_disable(struct tg3 *tp)
5533 for (i = tp->irq_cnt - 1; i >= 0; i--)
5534 napi_disable(&tp->napi[i].napi);
5537 static void tg3_napi_enable(struct tg3 *tp)
5541 for (i = 0; i < tp->irq_cnt; i++)
5542 napi_enable(&tp->napi[i].napi);
5545 static void tg3_napi_init(struct tg3 *tp)
5549 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
5550 for (i = 1; i < tp->irq_cnt; i++)
5551 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
5554 static void tg3_napi_fini(struct tg3 *tp)
5558 for (i = 0; i < tp->irq_cnt; i++)
5559 netif_napi_del(&tp->napi[i].napi);
5562 static inline void tg3_netif_stop(struct tg3 *tp)
5564 tp->dev->trans_start = jiffies; /* prevent tx timeout */
5565 tg3_napi_disable(tp);
5566 netif_tx_disable(tp->dev);
5569 static inline void tg3_netif_start(struct tg3 *tp)
5571 /* NOTE: unconditional netif_tx_wake_all_queues is only
5572 * appropriate so long as all callers are assured to
5573 * have free tx slots (such as after tg3_init_hw)
5575 netif_tx_wake_all_queues(tp->dev);
5577 tg3_napi_enable(tp);
5578 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
5579 tg3_enable_ints(tp);
5582 static void tg3_irq_quiesce(struct tg3 *tp)
5586 BUG_ON(tp->irq_sync);
5591 for (i = 0; i < tp->irq_cnt; i++)
5592 synchronize_irq(tp->napi[i].irq_vec);
5595 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5596 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5597 * with as well. Most of the time, this is not necessary except when
5598 * shutting down the device.
5600 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5602 spin_lock_bh(&tp->lock);
5604 tg3_irq_quiesce(tp);
5607 static inline void tg3_full_unlock(struct tg3 *tp)
5609 spin_unlock_bh(&tp->lock);
5612 /* One-shot MSI handler - Chip automatically disables interrupt
5613 * after sending MSI so driver doesn't have to do it.
5615 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5617 struct tg3_napi *tnapi = dev_id;
5618 struct tg3 *tp = tnapi->tp;
5620 prefetch(tnapi->hw_status);
5622 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5624 if (likely(!tg3_irq_sync(tp)))
5625 napi_schedule(&tnapi->napi);
5630 /* MSI ISR - No need to check for interrupt sharing and no need to
5631 * flush status block and interrupt mailbox. PCI ordering rules
5632 * guarantee that MSI will arrive after the status block.
5634 static irqreturn_t tg3_msi(int irq, void *dev_id)
5636 struct tg3_napi *tnapi = dev_id;
5637 struct tg3 *tp = tnapi->tp;
5639 prefetch(tnapi->hw_status);
5641 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5643 * Writing any value to intr-mbox-0 clears PCI INTA# and
5644 * chip-internal interrupt pending events.
5645 * Writing non-zero to intr-mbox-0 additional tells the
5646 * NIC to stop sending us irqs, engaging "in-intr-handler"
5649 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5650 if (likely(!tg3_irq_sync(tp)))
5651 napi_schedule(&tnapi->napi);
5653 return IRQ_RETVAL(1);
5656 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5658 struct tg3_napi *tnapi = dev_id;
5659 struct tg3 *tp = tnapi->tp;
5660 struct tg3_hw_status *sblk = tnapi->hw_status;
5661 unsigned int handled = 1;
5663 /* In INTx mode, it is possible for the interrupt to arrive at
5664 * the CPU before the status block posted prior to the interrupt.
5665 * Reading the PCI State register will confirm whether the
5666 * interrupt is ours and will flush the status block.
5668 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5669 if (tg3_flag(tp, CHIP_RESETTING) ||
5670 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5677 * Writing any value to intr-mbox-0 clears PCI INTA# and
5678 * chip-internal interrupt pending events.
5679 * Writing non-zero to intr-mbox-0 additional tells the
5680 * NIC to stop sending us irqs, engaging "in-intr-handler"
5683 * Flush the mailbox to de-assert the IRQ immediately to prevent
5684 * spurious interrupts. The flush impacts performance but
5685 * excessive spurious interrupts can be worse in some cases.
5687 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5688 if (tg3_irq_sync(tp))
5690 sblk->status &= ~SD_STATUS_UPDATED;
5691 if (likely(tg3_has_work(tnapi))) {
5692 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5693 napi_schedule(&tnapi->napi);
5695 /* No work, shared interrupt perhaps? re-enable
5696 * interrupts, and flush that PCI write
5698 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5702 return IRQ_RETVAL(handled);
5705 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5707 struct tg3_napi *tnapi = dev_id;
5708 struct tg3 *tp = tnapi->tp;
5709 struct tg3_hw_status *sblk = tnapi->hw_status;
5710 unsigned int handled = 1;
5712 /* In INTx mode, it is possible for the interrupt to arrive at
5713 * the CPU before the status block posted prior to the interrupt.
5714 * Reading the PCI State register will confirm whether the
5715 * interrupt is ours and will flush the status block.
5717 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5718 if (tg3_flag(tp, CHIP_RESETTING) ||
5719 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5726 * writing any value to intr-mbox-0 clears PCI INTA# and
5727 * chip-internal interrupt pending events.
5728 * writing non-zero to intr-mbox-0 additional tells the
5729 * NIC to stop sending us irqs, engaging "in-intr-handler"
5732 * Flush the mailbox to de-assert the IRQ immediately to prevent
5733 * spurious interrupts. The flush impacts performance but
5734 * excessive spurious interrupts can be worse in some cases.
5736 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5739 * In a shared interrupt configuration, sometimes other devices'
5740 * interrupts will scream. We record the current status tag here
5741 * so that the above check can report that the screaming interrupts
5742 * are unhandled. Eventually they will be silenced.
5744 tnapi->last_irq_tag = sblk->status_tag;
5746 if (tg3_irq_sync(tp))
5749 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5751 napi_schedule(&tnapi->napi);
5754 return IRQ_RETVAL(handled);
5757 /* ISR for interrupt test */
5758 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5760 struct tg3_napi *tnapi = dev_id;
5761 struct tg3 *tp = tnapi->tp;
5762 struct tg3_hw_status *sblk = tnapi->hw_status;
5764 if ((sblk->status & SD_STATUS_UPDATED) ||
5765 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5766 tg3_disable_ints(tp);
5767 return IRQ_RETVAL(1);
5769 return IRQ_RETVAL(0);
5772 static int tg3_init_hw(struct tg3 *, int);
5773 static int tg3_halt(struct tg3 *, int, int);
5775 /* Restart hardware after configuration changes, self-test, etc.
5776 * Invoked with tp->lock held.
5778 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5779 __releases(tp->lock)
5780 __acquires(tp->lock)
5784 err = tg3_init_hw(tp, reset_phy);
5787 "Failed to re-initialize device, aborting\n");
5788 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5789 tg3_full_unlock(tp);
5790 del_timer_sync(&tp->timer);
5792 tg3_napi_enable(tp);
5794 tg3_full_lock(tp, 0);
5799 #ifdef CONFIG_NET_POLL_CONTROLLER
5800 static void tg3_poll_controller(struct net_device *dev)
5803 struct tg3 *tp = netdev_priv(dev);
5805 for (i = 0; i < tp->irq_cnt; i++)
5806 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5810 static void tg3_reset_task(struct work_struct *work)
5812 struct tg3 *tp = container_of(work, struct tg3, reset_task);
5814 unsigned int restart_timer;
5816 tg3_full_lock(tp, 0);
5818 if (!netif_running(tp->dev)) {
5819 tg3_full_unlock(tp);
5823 tg3_full_unlock(tp);
5829 tg3_full_lock(tp, 1);
5831 restart_timer = tg3_flag(tp, RESTART_TIMER);
5832 tg3_flag_clear(tp, RESTART_TIMER);
5834 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
5835 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5836 tp->write32_rx_mbox = tg3_write_flush_reg32;
5837 tg3_flag_set(tp, MBOX_WRITE_REORDER);
5838 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
5841 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5842 err = tg3_init_hw(tp, 1);
5846 tg3_netif_start(tp);
5849 mod_timer(&tp->timer, jiffies + 1);
5852 tg3_full_unlock(tp);
5858 static void tg3_tx_timeout(struct net_device *dev)
5860 struct tg3 *tp = netdev_priv(dev);
5862 if (netif_msg_tx_err(tp)) {
5863 netdev_err(dev, "transmit timed out, resetting\n");
5867 schedule_work(&tp->reset_task);
5870 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5871 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5873 u32 base = (u32) mapping & 0xffffffff;
5875 return (base > 0xffffdcc0) && (base + len + 8 < base);
5878 /* Test for DMA addresses > 40-bit */
5879 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5882 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5883 if (tg3_flag(tp, 40BIT_DMA_BUG))
5884 return ((u64) mapping + len) > DMA_BIT_MASK(40);
5891 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5892 dma_addr_t mapping, int len, u32 flags,
5895 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5896 int is_end = (mss_and_is_end & 0x1);
5897 u32 mss = (mss_and_is_end >> 1);
5901 flags |= TXD_FLAG_END;
5902 if (flags & TXD_FLAG_VLAN) {
5903 vlan_tag = flags >> 16;
5906 vlan_tag |= (mss << TXD_MSS_SHIFT);
5908 txd->addr_hi = ((u64) mapping >> 32);
5909 txd->addr_lo = ((u64) mapping & 0xffffffff);
5910 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5911 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5914 static void tg3_skb_error_unmap(struct tg3_napi *tnapi,
5915 struct sk_buff *skb, int last)
5918 u32 entry = tnapi->tx_prod;
5919 struct ring_info *txb = &tnapi->tx_buffers[entry];
5921 pci_unmap_single(tnapi->tp->pdev,
5922 dma_unmap_addr(txb, mapping),
5925 for (i = 0; i < last; i++) {
5926 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5928 entry = NEXT_TX(entry);
5929 txb = &tnapi->tx_buffers[entry];
5931 pci_unmap_page(tnapi->tp->pdev,
5932 dma_unmap_addr(txb, mapping),
5933 frag->size, PCI_DMA_TODEVICE);
5937 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5938 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5939 struct sk_buff *skb,
5940 u32 base_flags, u32 mss)
5942 struct tg3 *tp = tnapi->tp;
5943 struct sk_buff *new_skb;
5944 dma_addr_t new_addr = 0;
5945 u32 entry = tnapi->tx_prod;
5948 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5949 new_skb = skb_copy(skb, GFP_ATOMIC);
5951 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5953 new_skb = skb_copy_expand(skb,
5954 skb_headroom(skb) + more_headroom,
5955 skb_tailroom(skb), GFP_ATOMIC);
5961 /* New SKB is guaranteed to be linear. */
5962 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5964 /* Make sure the mapping succeeded */
5965 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5967 dev_kfree_skb(new_skb);
5969 /* Make sure new skb does not cross any 4G boundaries.
5970 * Drop the packet if it does.
5972 } else if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
5973 pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5976 dev_kfree_skb(new_skb);
5978 tnapi->tx_buffers[entry].skb = new_skb;
5979 dma_unmap_addr_set(&tnapi->tx_buffers[entry],
5982 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5983 base_flags, 1 | (mss << 1));
5992 static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
5994 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5995 * TSO header is greater than 80 bytes.
5997 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5999 struct sk_buff *segs, *nskb;
6000 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
6002 /* Estimate the number of fragments in the worst case */
6003 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
6004 netif_stop_queue(tp->dev);
6006 /* netif_tx_stop_queue() must be done before checking
6007 * checking tx index in tg3_tx_avail() below, because in
6008 * tg3_tx(), we update tx index before checking for
6009 * netif_tx_queue_stopped().
6012 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
6013 return NETDEV_TX_BUSY;
6015 netif_wake_queue(tp->dev);
6018 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
6020 goto tg3_tso_bug_end;
6026 tg3_start_xmit(nskb, tp->dev);
6032 return NETDEV_TX_OK;
6035 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
6036 * support TG3_FLAG_HW_TSO_1 or firmware TSO only.
6038 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
6040 struct tg3 *tp = netdev_priv(dev);
6041 u32 len, entry, base_flags, mss;
6042 int i = -1, would_hit_hwbug;
6044 struct tg3_napi *tnapi;
6045 struct netdev_queue *txq;
6048 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
6049 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
6050 if (tg3_flag(tp, ENABLE_TSS))
6053 /* We are running in BH disabled context with netif_tx_lock
6054 * and TX reclaim runs via tp->napi.poll inside of a software
6055 * interrupt. Furthermore, IRQ processing runs lockless so we have
6056 * no IRQ context deadlocks to worry about either. Rejoice!
6058 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
6059 if (!netif_tx_queue_stopped(txq)) {
6060 netif_tx_stop_queue(txq);
6062 /* This is a hard error, log it. */
6064 "BUG! Tx Ring full when queue awake!\n");
6066 return NETDEV_TX_BUSY;
6069 entry = tnapi->tx_prod;
6071 if (skb->ip_summed == CHECKSUM_PARTIAL)
6072 base_flags |= TXD_FLAG_TCPUDP_CSUM;
6074 mss = skb_shinfo(skb)->gso_size;
6077 u32 tcp_opt_len, hdr_len;
6079 if (skb_header_cloned(skb) &&
6080 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
6086 tcp_opt_len = tcp_optlen(skb);
6088 if (skb_is_gso_v6(skb)) {
6089 hdr_len = skb_headlen(skb) - ETH_HLEN;
6093 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
6094 hdr_len = ip_tcp_len + tcp_opt_len;
6097 iph->tot_len = htons(mss + hdr_len);
6100 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
6101 tg3_flag(tp, TSO_BUG))
6102 return tg3_tso_bug(tp, skb);
6104 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
6105 TXD_FLAG_CPU_POST_DMA);
6107 if (tg3_flag(tp, HW_TSO_1) ||
6108 tg3_flag(tp, HW_TSO_2) ||
6109 tg3_flag(tp, HW_TSO_3)) {
6110 tcp_hdr(skb)->check = 0;
6111 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
6113 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6118 if (tg3_flag(tp, HW_TSO_3)) {
6119 mss |= (hdr_len & 0xc) << 12;
6121 base_flags |= 0x00000010;
6122 base_flags |= (hdr_len & 0x3e0) << 5;
6123 } else if (tg3_flag(tp, HW_TSO_2))
6124 mss |= hdr_len << 9;
6125 else if (tg3_flag(tp, HW_TSO_1) ||
6126 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6127 if (tcp_opt_len || iph->ihl > 5) {
6130 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
6131 mss |= (tsflags << 11);
6134 if (tcp_opt_len || iph->ihl > 5) {
6137 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
6138 base_flags |= tsflags << 12;
6143 if (vlan_tx_tag_present(skb))
6144 base_flags |= (TXD_FLAG_VLAN |
6145 (vlan_tx_tag_get(skb) << 16));
6147 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
6148 !mss && skb->len > VLAN_ETH_FRAME_LEN)
6149 base_flags |= TXD_FLAG_JMB_PKT;
6151 len = skb_headlen(skb);
6153 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6154 if (pci_dma_mapping_error(tp->pdev, mapping)) {
6159 tnapi->tx_buffers[entry].skb = skb;
6160 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
6162 would_hit_hwbug = 0;
6164 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
6165 would_hit_hwbug = 1;
6167 if (tg3_4g_overflow_test(mapping, len))
6168 would_hit_hwbug = 1;
6170 if (tg3_40bit_overflow_test(tp, mapping, len))
6171 would_hit_hwbug = 1;
6173 if (tg3_flag(tp, 5701_DMA_BUG))
6174 would_hit_hwbug = 1;
6176 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
6177 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
6179 entry = NEXT_TX(entry);
6181 /* Now loop through additional data fragments, and queue them. */
6182 if (skb_shinfo(skb)->nr_frags > 0) {
6183 last = skb_shinfo(skb)->nr_frags - 1;
6184 for (i = 0; i <= last; i++) {
6185 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6188 mapping = pci_map_page(tp->pdev,
6191 len, PCI_DMA_TODEVICE);
6193 tnapi->tx_buffers[entry].skb = NULL;
6194 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
6196 if (pci_dma_mapping_error(tp->pdev, mapping))
6199 if (tg3_flag(tp, SHORT_DMA_BUG) &&
6201 would_hit_hwbug = 1;
6203 if (tg3_4g_overflow_test(mapping, len))
6204 would_hit_hwbug = 1;
6206 if (tg3_40bit_overflow_test(tp, mapping, len))
6207 would_hit_hwbug = 1;
6209 if (tg3_flag(tp, HW_TSO_1) ||
6210 tg3_flag(tp, HW_TSO_2) ||
6211 tg3_flag(tp, HW_TSO_3))
6212 tg3_set_txd(tnapi, entry, mapping, len,
6213 base_flags, (i == last)|(mss << 1));
6215 tg3_set_txd(tnapi, entry, mapping, len,
6216 base_flags, (i == last));
6218 entry = NEXT_TX(entry);
6222 if (would_hit_hwbug) {
6223 tg3_skb_error_unmap(tnapi, skb, i);
6225 /* If the workaround fails due to memory/mapping
6226 * failure, silently drop this packet.
6228 if (tigon3_dma_hwbug_workaround(tnapi, skb, base_flags, mss))
6231 entry = NEXT_TX(tnapi->tx_prod);
6234 skb_tx_timestamp(skb);
6236 /* Packets are ready, update Tx producer idx local and on card. */
6237 tw32_tx_mbox(tnapi->prodmbox, entry);
6239 tnapi->tx_prod = entry;
6240 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
6241 netif_tx_stop_queue(txq);
6243 /* netif_tx_stop_queue() must be done before checking
6244 * checking tx index in tg3_tx_avail() below, because in
6245 * tg3_tx(), we update tx index before checking for
6246 * netif_tx_queue_stopped().
6249 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
6250 netif_tx_wake_queue(txq);
6256 return NETDEV_TX_OK;
6259 tg3_skb_error_unmap(tnapi, skb, i);
6261 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
6262 return NETDEV_TX_OK;
6265 static void tg3_set_loopback(struct net_device *dev, u32 features)
6267 struct tg3 *tp = netdev_priv(dev);
6269 if (features & NETIF_F_LOOPBACK) {
6270 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
6274 * Clear MAC_MODE_HALF_DUPLEX or you won't get packets back in
6275 * loopback mode if Half-Duplex mode was negotiated earlier.
6277 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
6279 /* Enable internal MAC loopback mode */
6280 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
6281 spin_lock_bh(&tp->lock);
6282 tw32(MAC_MODE, tp->mac_mode);
6283 netif_carrier_on(tp->dev);
6284 spin_unlock_bh(&tp->lock);
6285 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
6287 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
6290 /* Disable internal MAC loopback mode */
6291 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
6292 spin_lock_bh(&tp->lock);
6293 tw32(MAC_MODE, tp->mac_mode);
6294 /* Force link status check */
6295 tg3_setup_phy(tp, 1);
6296 spin_unlock_bh(&tp->lock);
6297 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
6301 static u32 tg3_fix_features(struct net_device *dev, u32 features)
6303 struct tg3 *tp = netdev_priv(dev);
6305 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
6306 features &= ~NETIF_F_ALL_TSO;
6311 static int tg3_set_features(struct net_device *dev, u32 features)
6313 u32 changed = dev->features ^ features;
6315 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
6316 tg3_set_loopback(dev, features);
6321 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
6326 if (new_mtu > ETH_DATA_LEN) {
6327 if (tg3_flag(tp, 5780_CLASS)) {
6328 netdev_update_features(dev);
6329 tg3_flag_clear(tp, TSO_CAPABLE);
6331 tg3_flag_set(tp, JUMBO_RING_ENABLE);
6334 if (tg3_flag(tp, 5780_CLASS)) {
6335 tg3_flag_set(tp, TSO_CAPABLE);
6336 netdev_update_features(dev);
6338 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
6342 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
6344 struct tg3 *tp = netdev_priv(dev);
6347 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
6350 if (!netif_running(dev)) {
6351 /* We'll just catch it later when the
6354 tg3_set_mtu(dev, tp, new_mtu);
6362 tg3_full_lock(tp, 1);
6364 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6366 tg3_set_mtu(dev, tp, new_mtu);
6368 err = tg3_restart_hw(tp, 0);
6371 tg3_netif_start(tp);
6373 tg3_full_unlock(tp);
6381 static void tg3_rx_prodring_free(struct tg3 *tp,
6382 struct tg3_rx_prodring_set *tpr)
6386 if (tpr != &tp->napi[0].prodring) {
6387 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
6388 i = (i + 1) & tp->rx_std_ring_mask)
6389 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6392 if (tg3_flag(tp, JUMBO_CAPABLE)) {
6393 for (i = tpr->rx_jmb_cons_idx;
6394 i != tpr->rx_jmb_prod_idx;
6395 i = (i + 1) & tp->rx_jmb_ring_mask) {
6396 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6404 for (i = 0; i <= tp->rx_std_ring_mask; i++)
6405 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6408 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
6409 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
6410 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6415 /* Initialize rx rings for packet processing.
6417 * The chip has been shut down and the driver detached from
6418 * the networking, so no interrupts or new tx packets will
6419 * end up in the driver. tp->{tx,}lock are held and thus
6422 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6423 struct tg3_rx_prodring_set *tpr)
6425 u32 i, rx_pkt_dma_sz;
6427 tpr->rx_std_cons_idx = 0;
6428 tpr->rx_std_prod_idx = 0;
6429 tpr->rx_jmb_cons_idx = 0;
6430 tpr->rx_jmb_prod_idx = 0;
6432 if (tpr != &tp->napi[0].prodring) {
6433 memset(&tpr->rx_std_buffers[0], 0,
6434 TG3_RX_STD_BUFF_RING_SIZE(tp));
6435 if (tpr->rx_jmb_buffers)
6436 memset(&tpr->rx_jmb_buffers[0], 0,
6437 TG3_RX_JMB_BUFF_RING_SIZE(tp));
6441 /* Zero out all descriptors. */
6442 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
6444 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6445 if (tg3_flag(tp, 5780_CLASS) &&
6446 tp->dev->mtu > ETH_DATA_LEN)
6447 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6448 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6450 /* Initialize invariants of the rings, we only set this
6451 * stuff once. This works because the card does not
6452 * write into the rx buffer posting rings.
6454 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
6455 struct tg3_rx_buffer_desc *rxd;
6457 rxd = &tpr->rx_std[i];
6458 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6459 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6460 rxd->opaque = (RXD_OPAQUE_RING_STD |
6461 (i << RXD_OPAQUE_INDEX_SHIFT));
6464 /* Now allocate fresh SKBs for each rx ring. */
6465 for (i = 0; i < tp->rx_pending; i++) {
6466 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6467 netdev_warn(tp->dev,
6468 "Using a smaller RX standard ring. Only "
6469 "%d out of %d buffers were allocated "
6470 "successfully\n", i, tp->rx_pending);
6478 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
6481 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
6483 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
6486 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
6487 struct tg3_rx_buffer_desc *rxd;
6489 rxd = &tpr->rx_jmb[i].std;
6490 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6491 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6493 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6494 (i << RXD_OPAQUE_INDEX_SHIFT));
6497 for (i = 0; i < tp->rx_jumbo_pending; i++) {
6498 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6499 netdev_warn(tp->dev,
6500 "Using a smaller RX jumbo ring. Only %d "
6501 "out of %d buffers were allocated "
6502 "successfully\n", i, tp->rx_jumbo_pending);
6505 tp->rx_jumbo_pending = i;
6514 tg3_rx_prodring_free(tp, tpr);
6518 static void tg3_rx_prodring_fini(struct tg3 *tp,
6519 struct tg3_rx_prodring_set *tpr)
6521 kfree(tpr->rx_std_buffers);
6522 tpr->rx_std_buffers = NULL;
6523 kfree(tpr->rx_jmb_buffers);
6524 tpr->rx_jmb_buffers = NULL;
6526 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
6527 tpr->rx_std, tpr->rx_std_mapping);
6531 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
6532 tpr->rx_jmb, tpr->rx_jmb_mapping);
6537 static int tg3_rx_prodring_init(struct tg3 *tp,
6538 struct tg3_rx_prodring_set *tpr)
6540 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
6542 if (!tpr->rx_std_buffers)
6545 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
6546 TG3_RX_STD_RING_BYTES(tp),
6547 &tpr->rx_std_mapping,
6552 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
6553 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
6555 if (!tpr->rx_jmb_buffers)
6558 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
6559 TG3_RX_JMB_RING_BYTES(tp),
6560 &tpr->rx_jmb_mapping,
6569 tg3_rx_prodring_fini(tp, tpr);
6573 /* Free up pending packets in all rx/tx rings.
6575 * The chip has been shut down and the driver detached from
6576 * the networking, so no interrupts or new tx packets will
6577 * end up in the driver. tp->{tx,}lock is not held and we are not
6578 * in an interrupt context and thus may sleep.
6580 static void tg3_free_rings(struct tg3 *tp)
6584 for (j = 0; j < tp->irq_cnt; j++) {
6585 struct tg3_napi *tnapi = &tp->napi[j];
6587 tg3_rx_prodring_free(tp, &tnapi->prodring);
6589 if (!tnapi->tx_buffers)
6592 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6593 struct ring_info *txp;
6594 struct sk_buff *skb;
6597 txp = &tnapi->tx_buffers[i];
6605 pci_unmap_single(tp->pdev,
6606 dma_unmap_addr(txp, mapping),
6613 for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6614 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6615 pci_unmap_page(tp->pdev,
6616 dma_unmap_addr(txp, mapping),
6617 skb_shinfo(skb)->frags[k].size,
6622 dev_kfree_skb_any(skb);
6627 /* Initialize tx/rx rings for packet processing.
6629 * The chip has been shut down and the driver detached from
6630 * the networking, so no interrupts or new tx packets will
6631 * end up in the driver. tp->{tx,}lock are held and thus
6634 static int tg3_init_rings(struct tg3 *tp)
6638 /* Free up all the SKBs. */
6641 for (i = 0; i < tp->irq_cnt; i++) {
6642 struct tg3_napi *tnapi = &tp->napi[i];
6644 tnapi->last_tag = 0;
6645 tnapi->last_irq_tag = 0;
6646 tnapi->hw_status->status = 0;
6647 tnapi->hw_status->status_tag = 0;
6648 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6653 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6655 tnapi->rx_rcb_ptr = 0;
6657 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6659 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
6669 * Must not be invoked with interrupt sources disabled and
6670 * the hardware shutdown down.
6672 static void tg3_free_consistent(struct tg3 *tp)
6676 for (i = 0; i < tp->irq_cnt; i++) {
6677 struct tg3_napi *tnapi = &tp->napi[i];
6679 if (tnapi->tx_ring) {
6680 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
6681 tnapi->tx_ring, tnapi->tx_desc_mapping);
6682 tnapi->tx_ring = NULL;
6685 kfree(tnapi->tx_buffers);
6686 tnapi->tx_buffers = NULL;
6688 if (tnapi->rx_rcb) {
6689 dma_free_coherent(&tp->pdev->dev,
6690 TG3_RX_RCB_RING_BYTES(tp),
6692 tnapi->rx_rcb_mapping);
6693 tnapi->rx_rcb = NULL;
6696 tg3_rx_prodring_fini(tp, &tnapi->prodring);
6698 if (tnapi->hw_status) {
6699 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
6701 tnapi->status_mapping);
6702 tnapi->hw_status = NULL;
6707 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
6708 tp->hw_stats, tp->stats_mapping);
6709 tp->hw_stats = NULL;
6714 * Must not be invoked with interrupt sources disabled and
6715 * the hardware shutdown down. Can sleep.
6717 static int tg3_alloc_consistent(struct tg3 *tp)
6721 tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
6722 sizeof(struct tg3_hw_stats),
6728 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6730 for (i = 0; i < tp->irq_cnt; i++) {
6731 struct tg3_napi *tnapi = &tp->napi[i];
6732 struct tg3_hw_status *sblk;
6734 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
6736 &tnapi->status_mapping,
6738 if (!tnapi->hw_status)
6741 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6742 sblk = tnapi->hw_status;
6744 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
6747 /* If multivector TSS is enabled, vector 0 does not handle
6748 * tx interrupts. Don't allocate any resources for it.
6750 if ((!i && !tg3_flag(tp, ENABLE_TSS)) ||
6751 (i && tg3_flag(tp, ENABLE_TSS))) {
6752 tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6755 if (!tnapi->tx_buffers)
6758 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
6760 &tnapi->tx_desc_mapping,
6762 if (!tnapi->tx_ring)
6767 * When RSS is enabled, the status block format changes
6768 * slightly. The "rx_jumbo_consumer", "reserved",
6769 * and "rx_mini_consumer" members get mapped to the
6770 * other three rx return ring producer indexes.
6774 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6777 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6780 tnapi->rx_rcb_prod_idx = &sblk->reserved;
6783 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6788 * If multivector RSS is enabled, vector 0 does not handle
6789 * rx or tx interrupts. Don't allocate any resources for it.
6791 if (!i && tg3_flag(tp, ENABLE_RSS))
6794 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
6795 TG3_RX_RCB_RING_BYTES(tp),
6796 &tnapi->rx_rcb_mapping,
6801 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6807 tg3_free_consistent(tp);
6811 #define MAX_WAIT_CNT 1000
6813 /* To stop a block, clear the enable bit and poll till it
6814 * clears. tp->lock is held.
6816 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6821 if (tg3_flag(tp, 5705_PLUS)) {
6828 /* We can't enable/disable these bits of the
6829 * 5705/5750, just say success.
6842 for (i = 0; i < MAX_WAIT_CNT; i++) {
6845 if ((val & enable_bit) == 0)
6849 if (i == MAX_WAIT_CNT && !silent) {
6850 dev_err(&tp->pdev->dev,
6851 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6859 /* tp->lock is held. */
6860 static int tg3_abort_hw(struct tg3 *tp, int silent)
6864 tg3_disable_ints(tp);
6866 tp->rx_mode &= ~RX_MODE_ENABLE;
6867 tw32_f(MAC_RX_MODE, tp->rx_mode);
6870 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6871 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6872 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6873 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6874 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6875 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6877 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6878 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6879 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6880 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6881 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6882 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6883 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6885 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6886 tw32_f(MAC_MODE, tp->mac_mode);
6889 tp->tx_mode &= ~TX_MODE_ENABLE;
6890 tw32_f(MAC_TX_MODE, tp->tx_mode);
6892 for (i = 0; i < MAX_WAIT_CNT; i++) {
6894 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6897 if (i >= MAX_WAIT_CNT) {
6898 dev_err(&tp->pdev->dev,
6899 "%s timed out, TX_MODE_ENABLE will not clear "
6900 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6904 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6905 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6906 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6908 tw32(FTQ_RESET, 0xffffffff);
6909 tw32(FTQ_RESET, 0x00000000);
6911 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6912 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6914 for (i = 0; i < tp->irq_cnt; i++) {
6915 struct tg3_napi *tnapi = &tp->napi[i];
6916 if (tnapi->hw_status)
6917 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6920 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6925 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6930 /* NCSI does not support APE events */
6931 if (tg3_flag(tp, APE_HAS_NCSI))
6934 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6935 if (apedata != APE_SEG_SIG_MAGIC)
6938 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6939 if (!(apedata & APE_FW_STATUS_READY))
6942 /* Wait for up to 1 millisecond for APE to service previous event. */
6943 for (i = 0; i < 10; i++) {
6944 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6947 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6949 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6950 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6951 event | APE_EVENT_STATUS_EVENT_PENDING);
6953 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6955 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6961 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6962 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6965 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6970 if (!tg3_flag(tp, ENABLE_APE))
6974 case RESET_KIND_INIT:
6975 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6976 APE_HOST_SEG_SIG_MAGIC);
6977 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6978 APE_HOST_SEG_LEN_MAGIC);
6979 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6980 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6981 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6982 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
6983 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6984 APE_HOST_BEHAV_NO_PHYLOCK);
6985 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
6986 TG3_APE_HOST_DRVR_STATE_START);
6988 event = APE_EVENT_STATUS_STATE_START;
6990 case RESET_KIND_SHUTDOWN:
6991 /* With the interface we are currently using,
6992 * APE does not track driver state. Wiping
6993 * out the HOST SEGMENT SIGNATURE forces
6994 * the APE to assume OS absent status.
6996 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6998 if (device_may_wakeup(&tp->pdev->dev) &&
6999 tg3_flag(tp, WOL_ENABLE)) {
7000 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
7001 TG3_APE_HOST_WOL_SPEED_AUTO);
7002 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
7004 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
7006 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
7008 event = APE_EVENT_STATUS_STATE_UNLOAD;
7010 case RESET_KIND_SUSPEND:
7011 event = APE_EVENT_STATUS_STATE_SUSPEND;
7017 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
7019 tg3_ape_send_event(tp, event);
7022 /* tp->lock is held. */
7023 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
7025 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
7026 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
7028 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
7030 case RESET_KIND_INIT:
7031 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
7035 case RESET_KIND_SHUTDOWN:
7036 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
7040 case RESET_KIND_SUSPEND:
7041 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
7050 if (kind == RESET_KIND_INIT ||
7051 kind == RESET_KIND_SUSPEND)
7052 tg3_ape_driver_state_change(tp, kind);
7055 /* tp->lock is held. */
7056 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
7058 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
7060 case RESET_KIND_INIT:
7061 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
7062 DRV_STATE_START_DONE);
7065 case RESET_KIND_SHUTDOWN:
7066 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
7067 DRV_STATE_UNLOAD_DONE);
7075 if (kind == RESET_KIND_SHUTDOWN)
7076 tg3_ape_driver_state_change(tp, kind);
7079 /* tp->lock is held. */
7080 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
7082 if (tg3_flag(tp, ENABLE_ASF)) {
7084 case RESET_KIND_INIT:
7085 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
7089 case RESET_KIND_SHUTDOWN:
7090 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
7094 case RESET_KIND_SUSPEND:
7095 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
7105 static int tg3_poll_fw(struct tg3 *tp)
7110 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7111 /* Wait up to 20ms for init done. */
7112 for (i = 0; i < 200; i++) {
7113 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
7120 /* Wait for firmware initialization to complete. */
7121 for (i = 0; i < 100000; i++) {
7122 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
7123 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
7128 /* Chip might not be fitted with firmware. Some Sun onboard
7129 * parts are configured like that. So don't signal the timeout
7130 * of the above loop as an error, but do report the lack of
7131 * running firmware once.
7133 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
7134 tg3_flag_set(tp, NO_FWARE_REPORTED);
7136 netdev_info(tp->dev, "No firmware running\n");
7139 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7140 /* The 57765 A0 needs a little more
7141 * time to do some important work.
7149 /* Save PCI command register before chip reset */
7150 static void tg3_save_pci_state(struct tg3 *tp)
7152 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
7155 /* Restore PCI state after chip reset */
7156 static void tg3_restore_pci_state(struct tg3 *tp)
7160 /* Re-enable indirect register accesses. */
7161 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
7162 tp->misc_host_ctrl);
7164 /* Set MAX PCI retry to zero. */
7165 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
7166 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7167 tg3_flag(tp, PCIX_MODE))
7168 val |= PCISTATE_RETRY_SAME_DMA;
7169 /* Allow reads and writes to the APE register and memory space. */
7170 if (tg3_flag(tp, ENABLE_APE))
7171 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7172 PCISTATE_ALLOW_APE_SHMEM_WR |
7173 PCISTATE_ALLOW_APE_PSPACE_WR;
7174 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
7176 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
7178 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
7179 if (tg3_flag(tp, PCI_EXPRESS))
7180 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
7182 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
7183 tp->pci_cacheline_sz);
7184 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
7189 /* Make sure PCI-X relaxed ordering bit is clear. */
7190 if (tg3_flag(tp, PCIX_MODE)) {
7193 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7195 pcix_cmd &= ~PCI_X_CMD_ERO;
7196 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7200 if (tg3_flag(tp, 5780_CLASS)) {
7202 /* Chip reset on 5780 will reset MSI enable bit,
7203 * so need to restore it.
7205 if (tg3_flag(tp, USING_MSI)) {
7208 pci_read_config_word(tp->pdev,
7209 tp->msi_cap + PCI_MSI_FLAGS,
7211 pci_write_config_word(tp->pdev,
7212 tp->msi_cap + PCI_MSI_FLAGS,
7213 ctrl | PCI_MSI_FLAGS_ENABLE);
7214 val = tr32(MSGINT_MODE);
7215 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
7220 static void tg3_stop_fw(struct tg3 *);
7222 /* tp->lock is held. */
7223 static int tg3_chip_reset(struct tg3 *tp)
7226 void (*write_op)(struct tg3 *, u32, u32);
7231 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
7233 /* No matching tg3_nvram_unlock() after this because
7234 * chip reset below will undo the nvram lock.
7236 tp->nvram_lock_cnt = 0;
7238 /* GRC_MISC_CFG core clock reset will clear the memory
7239 * enable bit in PCI register 4 and the MSI enable bit
7240 * on some chips, so we save relevant registers here.
7242 tg3_save_pci_state(tp);
7244 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
7245 tg3_flag(tp, 5755_PLUS))
7246 tw32(GRC_FASTBOOT_PC, 0);
7249 * We must avoid the readl() that normally takes place.
7250 * It locks machines, causes machine checks, and other
7251 * fun things. So, temporarily disable the 5701
7252 * hardware workaround, while we do the reset.
7254 write_op = tp->write32;
7255 if (write_op == tg3_write_flush_reg32)
7256 tp->write32 = tg3_write32;
7258 /* Prevent the irq handler from reading or writing PCI registers
7259 * during chip reset when the memory enable bit in the PCI command
7260 * register may be cleared. The chip does not generate interrupt
7261 * at this time, but the irq handler may still be called due to irq
7262 * sharing or irqpoll.
7264 tg3_flag_set(tp, CHIP_RESETTING);
7265 for (i = 0; i < tp->irq_cnt; i++) {
7266 struct tg3_napi *tnapi = &tp->napi[i];
7267 if (tnapi->hw_status) {
7268 tnapi->hw_status->status = 0;
7269 tnapi->hw_status->status_tag = 0;
7271 tnapi->last_tag = 0;
7272 tnapi->last_irq_tag = 0;
7276 for (i = 0; i < tp->irq_cnt; i++)
7277 synchronize_irq(tp->napi[i].irq_vec);
7279 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7280 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7281 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7285 val = GRC_MISC_CFG_CORECLK_RESET;
7287 if (tg3_flag(tp, PCI_EXPRESS)) {
7288 /* Force PCIe 1.0a mode */
7289 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7290 !tg3_flag(tp, 57765_PLUS) &&
7291 tr32(TG3_PCIE_PHY_TSTCTL) ==
7292 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
7293 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
7295 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
7296 tw32(GRC_MISC_CFG, (1 << 29));
7301 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7302 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
7303 tw32(GRC_VCPU_EXT_CTRL,
7304 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
7307 /* Manage gphy power for all CPMU absent PCIe devices. */
7308 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
7309 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
7311 tw32(GRC_MISC_CFG, val);
7313 /* restore 5701 hardware bug workaround write method */
7314 tp->write32 = write_op;
7316 /* Unfortunately, we have to delay before the PCI read back.
7317 * Some 575X chips even will not respond to a PCI cfg access
7318 * when the reset command is given to the chip.
7320 * How do these hardware designers expect things to work
7321 * properly if the PCI write is posted for a long period
7322 * of time? It is always necessary to have some method by
7323 * which a register read back can occur to push the write
7324 * out which does the reset.
7326 * For most tg3 variants the trick below was working.
7331 /* Flush PCI posted writes. The normal MMIO registers
7332 * are inaccessible at this time so this is the only
7333 * way to make this reliably (actually, this is no longer
7334 * the case, see above). I tried to use indirect
7335 * register read/write but this upset some 5701 variants.
7337 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
7341 if (tg3_flag(tp, PCI_EXPRESS) && pci_pcie_cap(tp->pdev)) {
7344 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
7348 /* Wait for link training to complete. */
7349 for (i = 0; i < 5000; i++)
7352 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7353 pci_write_config_dword(tp->pdev, 0xc4,
7354 cfg_val | (1 << 15));
7357 /* Clear the "no snoop" and "relaxed ordering" bits. */
7358 pci_read_config_word(tp->pdev,
7359 pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL,
7361 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7362 PCI_EXP_DEVCTL_NOSNOOP_EN);
7364 * Older PCIe devices only support the 128 byte
7365 * MPS setting. Enforce the restriction.
7367 if (!tg3_flag(tp, CPMU_PRESENT))
7368 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7369 pci_write_config_word(tp->pdev,
7370 pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL,
7373 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
7375 /* Clear error status */
7376 pci_write_config_word(tp->pdev,
7377 pci_pcie_cap(tp->pdev) + PCI_EXP_DEVSTA,
7378 PCI_EXP_DEVSTA_CED |
7379 PCI_EXP_DEVSTA_NFED |
7380 PCI_EXP_DEVSTA_FED |
7381 PCI_EXP_DEVSTA_URD);
7384 tg3_restore_pci_state(tp);
7386 tg3_flag_clear(tp, CHIP_RESETTING);
7387 tg3_flag_clear(tp, ERROR_PROCESSED);
7390 if (tg3_flag(tp, 5780_CLASS))
7391 val = tr32(MEMARB_MODE);
7392 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7394 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7396 tw32(0x5000, 0x400);
7399 tw32(GRC_MODE, tp->grc_mode);
7401 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7404 tw32(0xc4, val | (1 << 15));
7407 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7408 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7409 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7410 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7411 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7412 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7415 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
7416 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
7418 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
7419 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
7424 tw32_f(MAC_MODE, val);
7427 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7429 err = tg3_poll_fw(tp);
7435 if (tg3_flag(tp, PCI_EXPRESS) &&
7436 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7437 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7438 !tg3_flag(tp, 57765_PLUS)) {
7441 tw32(0x7c00, val | (1 << 25));
7444 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
7445 val = tr32(TG3_CPMU_CLCK_ORIDE);
7446 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
7449 /* Reprobe ASF enable state. */
7450 tg3_flag_clear(tp, ENABLE_ASF);
7451 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
7452 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7453 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7456 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7457 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7458 tg3_flag_set(tp, ENABLE_ASF);
7459 tp->last_event_jiffies = jiffies;
7460 if (tg3_flag(tp, 5750_PLUS))
7461 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
7468 /* tp->lock is held. */
7469 static void tg3_stop_fw(struct tg3 *tp)
7471 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
7472 /* Wait for RX cpu to ACK the previous event. */
7473 tg3_wait_for_event_ack(tp);
7475 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7477 tg3_generate_fw_event(tp);
7479 /* Wait for RX cpu to ACK this event. */
7480 tg3_wait_for_event_ack(tp);
7484 /* tp->lock is held. */
7485 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7491 tg3_write_sig_pre_reset(tp, kind);
7493 tg3_abort_hw(tp, silent);
7494 err = tg3_chip_reset(tp);
7496 __tg3_set_mac_addr(tp, 0);
7498 tg3_write_sig_legacy(tp, kind);
7499 tg3_write_sig_post_reset(tp, kind);
7507 #define RX_CPU_SCRATCH_BASE 0x30000
7508 #define RX_CPU_SCRATCH_SIZE 0x04000
7509 #define TX_CPU_SCRATCH_BASE 0x34000
7510 #define TX_CPU_SCRATCH_SIZE 0x04000
7512 /* tp->lock is held. */
7513 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7517 BUG_ON(offset == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
7519 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7520 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7522 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7525 if (offset == RX_CPU_BASE) {
7526 for (i = 0; i < 10000; i++) {
7527 tw32(offset + CPU_STATE, 0xffffffff);
7528 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7529 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7533 tw32(offset + CPU_STATE, 0xffffffff);
7534 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
7537 for (i = 0; i < 10000; i++) {
7538 tw32(offset + CPU_STATE, 0xffffffff);
7539 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7540 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7546 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7547 __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7551 /* Clear firmware's nvram arbitration. */
7552 if (tg3_flag(tp, NVRAM))
7553 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7558 unsigned int fw_base;
7559 unsigned int fw_len;
7560 const __be32 *fw_data;
7563 /* tp->lock is held. */
7564 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7565 int cpu_scratch_size, struct fw_info *info)
7567 int err, lock_err, i;
7568 void (*write_op)(struct tg3 *, u32, u32);
7570 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
7572 "%s: Trying to load TX cpu firmware which is 5705\n",
7577 if (tg3_flag(tp, 5705_PLUS))
7578 write_op = tg3_write_mem;
7580 write_op = tg3_write_indirect_reg32;
7582 /* It is possible that bootcode is still loading at this point.
7583 * Get the nvram lock first before halting the cpu.
7585 lock_err = tg3_nvram_lock(tp);
7586 err = tg3_halt_cpu(tp, cpu_base);
7588 tg3_nvram_unlock(tp);
7592 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7593 write_op(tp, cpu_scratch_base + i, 0);
7594 tw32(cpu_base + CPU_STATE, 0xffffffff);
7595 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7596 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7597 write_op(tp, (cpu_scratch_base +
7598 (info->fw_base & 0xffff) +
7600 be32_to_cpu(info->fw_data[i]));
7608 /* tp->lock is held. */
7609 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7611 struct fw_info info;
7612 const __be32 *fw_data;
7615 fw_data = (void *)tp->fw->data;
7617 /* Firmware blob starts with version numbers, followed by
7618 start address and length. We are setting complete length.
7619 length = end_address_of_bss - start_address_of_text.
7620 Remainder is the blob to be loaded contiguously
7621 from start address. */
7623 info.fw_base = be32_to_cpu(fw_data[1]);
7624 info.fw_len = tp->fw->size - 12;
7625 info.fw_data = &fw_data[3];
7627 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7628 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7633 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7634 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7639 /* Now startup only the RX cpu. */
7640 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7641 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7643 for (i = 0; i < 5; i++) {
7644 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7646 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7647 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
7648 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7652 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7653 "should be %08x\n", __func__,
7654 tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7657 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7658 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
7663 /* tp->lock is held. */
7664 static int tg3_load_tso_firmware(struct tg3 *tp)
7666 struct fw_info info;
7667 const __be32 *fw_data;
7668 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7671 if (tg3_flag(tp, HW_TSO_1) ||
7672 tg3_flag(tp, HW_TSO_2) ||
7673 tg3_flag(tp, HW_TSO_3))
7676 fw_data = (void *)tp->fw->data;
7678 /* Firmware blob starts with version numbers, followed by
7679 start address and length. We are setting complete length.
7680 length = end_address_of_bss - start_address_of_text.
7681 Remainder is the blob to be loaded contiguously
7682 from start address. */
7684 info.fw_base = be32_to_cpu(fw_data[1]);
7685 cpu_scratch_size = tp->fw_len;
7686 info.fw_len = tp->fw->size - 12;
7687 info.fw_data = &fw_data[3];
7689 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7690 cpu_base = RX_CPU_BASE;
7691 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7693 cpu_base = TX_CPU_BASE;
7694 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7695 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7698 err = tg3_load_firmware_cpu(tp, cpu_base,
7699 cpu_scratch_base, cpu_scratch_size,
7704 /* Now startup the cpu. */
7705 tw32(cpu_base + CPU_STATE, 0xffffffff);
7706 tw32_f(cpu_base + CPU_PC, info.fw_base);
7708 for (i = 0; i < 5; i++) {
7709 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7711 tw32(cpu_base + CPU_STATE, 0xffffffff);
7712 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
7713 tw32_f(cpu_base + CPU_PC, info.fw_base);
7718 "%s fails to set CPU PC, is %08x should be %08x\n",
7719 __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7722 tw32(cpu_base + CPU_STATE, 0xffffffff);
7723 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7728 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7730 struct tg3 *tp = netdev_priv(dev);
7731 struct sockaddr *addr = p;
7732 int err = 0, skip_mac_1 = 0;
7734 if (!is_valid_ether_addr(addr->sa_data))
7737 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7739 if (!netif_running(dev))
7742 if (tg3_flag(tp, ENABLE_ASF)) {
7743 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7745 addr0_high = tr32(MAC_ADDR_0_HIGH);
7746 addr0_low = tr32(MAC_ADDR_0_LOW);
7747 addr1_high = tr32(MAC_ADDR_1_HIGH);
7748 addr1_low = tr32(MAC_ADDR_1_LOW);
7750 /* Skip MAC addr 1 if ASF is using it. */
7751 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7752 !(addr1_high == 0 && addr1_low == 0))
7755 spin_lock_bh(&tp->lock);
7756 __tg3_set_mac_addr(tp, skip_mac_1);
7757 spin_unlock_bh(&tp->lock);
7762 /* tp->lock is held. */
7763 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7764 dma_addr_t mapping, u32 maxlen_flags,
7768 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7769 ((u64) mapping >> 32));
7771 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7772 ((u64) mapping & 0xffffffff));
7774 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7777 if (!tg3_flag(tp, 5705_PLUS))
7779 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7783 static void __tg3_set_rx_mode(struct net_device *);
7784 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7788 if (!tg3_flag(tp, ENABLE_TSS)) {
7789 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7790 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7791 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7793 tw32(HOSTCC_TXCOL_TICKS, 0);
7794 tw32(HOSTCC_TXMAX_FRAMES, 0);
7795 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7798 if (!tg3_flag(tp, ENABLE_RSS)) {
7799 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7800 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7801 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7803 tw32(HOSTCC_RXCOL_TICKS, 0);
7804 tw32(HOSTCC_RXMAX_FRAMES, 0);
7805 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7808 if (!tg3_flag(tp, 5705_PLUS)) {
7809 u32 val = ec->stats_block_coalesce_usecs;
7811 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7812 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7814 if (!netif_carrier_ok(tp->dev))
7817 tw32(HOSTCC_STAT_COAL_TICKS, val);
7820 for (i = 0; i < tp->irq_cnt - 1; i++) {
7823 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7824 tw32(reg, ec->rx_coalesce_usecs);
7825 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7826 tw32(reg, ec->rx_max_coalesced_frames);
7827 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7828 tw32(reg, ec->rx_max_coalesced_frames_irq);
7830 if (tg3_flag(tp, ENABLE_TSS)) {
7831 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7832 tw32(reg, ec->tx_coalesce_usecs);
7833 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7834 tw32(reg, ec->tx_max_coalesced_frames);
7835 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7836 tw32(reg, ec->tx_max_coalesced_frames_irq);
7840 for (; i < tp->irq_max - 1; i++) {
7841 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7842 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7843 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7845 if (tg3_flag(tp, ENABLE_TSS)) {
7846 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7847 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7848 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7853 /* tp->lock is held. */
7854 static void tg3_rings_reset(struct tg3 *tp)
7857 u32 stblk, txrcb, rxrcb, limit;
7858 struct tg3_napi *tnapi = &tp->napi[0];
7860 /* Disable all transmit rings but the first. */
7861 if (!tg3_flag(tp, 5705_PLUS))
7862 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7863 else if (tg3_flag(tp, 5717_PLUS))
7864 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
7865 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7866 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7868 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7870 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7871 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7872 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7873 BDINFO_FLAGS_DISABLED);
7876 /* Disable all receive return rings but the first. */
7877 if (tg3_flag(tp, 5717_PLUS))
7878 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7879 else if (!tg3_flag(tp, 5705_PLUS))
7880 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7881 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7882 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7883 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7885 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7887 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7888 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7889 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7890 BDINFO_FLAGS_DISABLED);
7892 /* Disable interrupts */
7893 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7894 tp->napi[0].chk_msi_cnt = 0;
7895 tp->napi[0].last_rx_cons = 0;
7896 tp->napi[0].last_tx_cons = 0;
7898 /* Zero mailbox registers. */
7899 if (tg3_flag(tp, SUPPORT_MSIX)) {
7900 for (i = 1; i < tp->irq_max; i++) {
7901 tp->napi[i].tx_prod = 0;
7902 tp->napi[i].tx_cons = 0;
7903 if (tg3_flag(tp, ENABLE_TSS))
7904 tw32_mailbox(tp->napi[i].prodmbox, 0);
7905 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7906 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7907 tp->napi[0].chk_msi_cnt = 0;
7908 tp->napi[i].last_rx_cons = 0;
7909 tp->napi[i].last_tx_cons = 0;
7911 if (!tg3_flag(tp, ENABLE_TSS))
7912 tw32_mailbox(tp->napi[0].prodmbox, 0);
7914 tp->napi[0].tx_prod = 0;
7915 tp->napi[0].tx_cons = 0;
7916 tw32_mailbox(tp->napi[0].prodmbox, 0);
7917 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7920 /* Make sure the NIC-based send BD rings are disabled. */
7921 if (!tg3_flag(tp, 5705_PLUS)) {
7922 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7923 for (i = 0; i < 16; i++)
7924 tw32_tx_mbox(mbox + i * 8, 0);
7927 txrcb = NIC_SRAM_SEND_RCB;
7928 rxrcb = NIC_SRAM_RCV_RET_RCB;
7930 /* Clear status block in ram. */
7931 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7933 /* Set status block DMA address */
7934 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7935 ((u64) tnapi->status_mapping >> 32));
7936 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7937 ((u64) tnapi->status_mapping & 0xffffffff));
7939 if (tnapi->tx_ring) {
7940 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7941 (TG3_TX_RING_SIZE <<
7942 BDINFO_FLAGS_MAXLEN_SHIFT),
7943 NIC_SRAM_TX_BUFFER_DESC);
7944 txrcb += TG3_BDINFO_SIZE;
7947 if (tnapi->rx_rcb) {
7948 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7949 (tp->rx_ret_ring_mask + 1) <<
7950 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
7951 rxrcb += TG3_BDINFO_SIZE;
7954 stblk = HOSTCC_STATBLCK_RING1;
7956 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7957 u64 mapping = (u64)tnapi->status_mapping;
7958 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7959 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7961 /* Clear status block in ram. */
7962 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7964 if (tnapi->tx_ring) {
7965 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7966 (TG3_TX_RING_SIZE <<
7967 BDINFO_FLAGS_MAXLEN_SHIFT),
7968 NIC_SRAM_TX_BUFFER_DESC);
7969 txrcb += TG3_BDINFO_SIZE;
7972 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7973 ((tp->rx_ret_ring_mask + 1) <<
7974 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7977 rxrcb += TG3_BDINFO_SIZE;
7981 static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
7983 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
7985 if (!tg3_flag(tp, 5750_PLUS) ||
7986 tg3_flag(tp, 5780_CLASS) ||
7987 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
7988 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7989 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
7990 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7991 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
7992 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
7994 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
7996 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
7997 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
7999 val = min(nic_rep_thresh, host_rep_thresh);
8000 tw32(RCVBDI_STD_THRESH, val);
8002 if (tg3_flag(tp, 57765_PLUS))
8003 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
8005 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
8008 if (!tg3_flag(tp, 5705_PLUS))
8009 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
8011 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717;
8013 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
8015 val = min(bdcache_maxcnt / 2, host_rep_thresh);
8016 tw32(RCVBDI_JUMBO_THRESH, val);
8018 if (tg3_flag(tp, 57765_PLUS))
8019 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
8022 /* tp->lock is held. */
8023 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8025 u32 val, rdmac_mode;
8027 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
8029 tg3_disable_ints(tp);
8033 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
8035 if (tg3_flag(tp, INIT_COMPLETE))
8036 tg3_abort_hw(tp, 1);
8038 /* Enable MAC control of LPI */
8039 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
8040 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
8041 TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
8042 TG3_CPMU_EEE_LNKIDL_UART_IDL);
8044 tw32_f(TG3_CPMU_EEE_CTRL,
8045 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
8047 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
8048 TG3_CPMU_EEEMD_LPI_IN_TX |
8049 TG3_CPMU_EEEMD_LPI_IN_RX |
8050 TG3_CPMU_EEEMD_EEE_ENABLE;
8052 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
8053 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
8055 if (tg3_flag(tp, ENABLE_APE))
8056 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
8058 tw32_f(TG3_CPMU_EEE_MODE, val);
8060 tw32_f(TG3_CPMU_EEE_DBTMR1,
8061 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
8062 TG3_CPMU_DBTMR1_LNKIDLE_2047US);
8064 tw32_f(TG3_CPMU_EEE_DBTMR2,
8065 TG3_CPMU_DBTMR2_APE_TX_2047US |
8066 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
8072 err = tg3_chip_reset(tp);
8076 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
8078 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
8079 val = tr32(TG3_CPMU_CTRL);
8080 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
8081 tw32(TG3_CPMU_CTRL, val);
8083 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
8084 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
8085 val |= CPMU_LSPD_10MB_MACCLK_6_25;
8086 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
8088 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
8089 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
8090 val |= CPMU_LNK_AWARE_MACCLK_6_25;
8091 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
8093 val = tr32(TG3_CPMU_HST_ACC);
8094 val &= ~CPMU_HST_ACC_MACCLK_MASK;
8095 val |= CPMU_HST_ACC_MACCLK_6_25;
8096 tw32(TG3_CPMU_HST_ACC, val);
8099 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
8100 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
8101 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
8102 PCIE_PWR_MGMT_L1_THRESH_4MS;
8103 tw32(PCIE_PWR_MGMT_THRESH, val);
8105 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
8106 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
8108 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
8110 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
8111 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
8114 if (tg3_flag(tp, L1PLLPD_EN)) {
8115 u32 grc_mode = tr32(GRC_MODE);
8117 /* Access the lower 1K of PL PCIE block registers. */
8118 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8119 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
8121 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
8122 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
8123 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
8125 tw32(GRC_MODE, grc_mode);
8128 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
8129 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
8130 u32 grc_mode = tr32(GRC_MODE);
8132 /* Access the lower 1K of PL PCIE block registers. */
8133 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8134 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
8136 val = tr32(TG3_PCIE_TLDLPL_PORT +
8137 TG3_PCIE_PL_LO_PHYCTL5);
8138 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
8139 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
8141 tw32(GRC_MODE, grc_mode);
8144 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) {
8145 u32 grc_mode = tr32(GRC_MODE);
8147 /* Access the lower 1K of DL PCIE block registers. */
8148 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8149 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
8151 val = tr32(TG3_PCIE_TLDLPL_PORT +
8152 TG3_PCIE_DL_LO_FTSMAX);
8153 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
8154 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
8155 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
8157 tw32(GRC_MODE, grc_mode);
8160 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
8161 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
8162 val |= CPMU_LSPD_10MB_MACCLK_6_25;
8163 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
8166 /* This works around an issue with Athlon chipsets on
8167 * B3 tigon3 silicon. This bit has no effect on any
8168 * other revision. But do not set this on PCI Express
8169 * chips and don't even touch the clocks if the CPMU is present.
8171 if (!tg3_flag(tp, CPMU_PRESENT)) {
8172 if (!tg3_flag(tp, PCI_EXPRESS))
8173 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
8174 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
8177 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
8178 tg3_flag(tp, PCIX_MODE)) {
8179 val = tr32(TG3PCI_PCISTATE);
8180 val |= PCISTATE_RETRY_SAME_DMA;
8181 tw32(TG3PCI_PCISTATE, val);
8184 if (tg3_flag(tp, ENABLE_APE)) {
8185 /* Allow reads and writes to the
8186 * APE register and memory space.
8188 val = tr32(TG3PCI_PCISTATE);
8189 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
8190 PCISTATE_ALLOW_APE_SHMEM_WR |
8191 PCISTATE_ALLOW_APE_PSPACE_WR;
8192 tw32(TG3PCI_PCISTATE, val);
8195 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
8196 /* Enable some hw fixes. */
8197 val = tr32(TG3PCI_MSI_DATA);
8198 val |= (1 << 26) | (1 << 28) | (1 << 29);
8199 tw32(TG3PCI_MSI_DATA, val);
8202 /* Descriptor ring init may make accesses to the
8203 * NIC SRAM area to setup the TX descriptors, so we
8204 * can only do this after the hardware has been
8205 * successfully reset.
8207 err = tg3_init_rings(tp);
8211 if (tg3_flag(tp, 57765_PLUS)) {
8212 val = tr32(TG3PCI_DMA_RW_CTRL) &
8213 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
8214 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
8215 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
8216 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
8217 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
8218 val |= DMA_RWCTRL_TAGGED_STAT_WA;
8219 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
8220 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
8221 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
8222 /* This value is determined during the probe time DMA
8223 * engine test, tg3_test_dma.
8225 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
8228 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
8229 GRC_MODE_4X_NIC_SEND_RINGS |
8230 GRC_MODE_NO_TX_PHDR_CSUM |
8231 GRC_MODE_NO_RX_PHDR_CSUM);
8232 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
8234 /* Pseudo-header checksum is done by hardware logic and not
8235 * the offload processers, so make the chip do the pseudo-
8236 * header checksums on receive. For transmit it is more
8237 * convenient to do the pseudo-header checksum in software
8238 * as Linux does that on transmit for us in all cases.
8240 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
8244 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
8246 /* Setup the timer prescalar register. Clock is always 66Mhz. */
8247 val = tr32(GRC_MISC_CFG);
8249 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
8250 tw32(GRC_MISC_CFG, val);
8252 /* Initialize MBUF/DESC pool. */
8253 if (tg3_flag(tp, 5750_PLUS)) {
8255 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
8256 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
8257 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
8258 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
8260 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
8261 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
8262 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
8263 } else if (tg3_flag(tp, TSO_CAPABLE)) {
8266 fw_len = tp->fw_len;
8267 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
8268 tw32(BUFMGR_MB_POOL_ADDR,
8269 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
8270 tw32(BUFMGR_MB_POOL_SIZE,
8271 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
8274 if (tp->dev->mtu <= ETH_DATA_LEN) {
8275 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8276 tp->bufmgr_config.mbuf_read_dma_low_water);
8277 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8278 tp->bufmgr_config.mbuf_mac_rx_low_water);
8279 tw32(BUFMGR_MB_HIGH_WATER,
8280 tp->bufmgr_config.mbuf_high_water);
8282 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8283 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
8284 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8285 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
8286 tw32(BUFMGR_MB_HIGH_WATER,
8287 tp->bufmgr_config.mbuf_high_water_jumbo);
8289 tw32(BUFMGR_DMA_LOW_WATER,
8290 tp->bufmgr_config.dma_low_water);
8291 tw32(BUFMGR_DMA_HIGH_WATER,
8292 tp->bufmgr_config.dma_high_water);
8294 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
8295 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8296 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
8297 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8298 tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
8299 tp->pci_chip_rev_id == CHIPREV_ID_5720_A0)
8300 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
8301 tw32(BUFMGR_MODE, val);
8302 for (i = 0; i < 2000; i++) {
8303 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
8308 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
8312 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
8313 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
8315 tg3_setup_rxbd_thresholds(tp);
8317 /* Initialize TG3_BDINFO's at:
8318 * RCVDBDI_STD_BD: standard eth size rx ring
8319 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
8320 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
8323 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
8324 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
8325 * ring attribute flags
8326 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
8328 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
8329 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
8331 * The size of each ring is fixed in the firmware, but the location is
8334 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8335 ((u64) tpr->rx_std_mapping >> 32));
8336 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8337 ((u64) tpr->rx_std_mapping & 0xffffffff));
8338 if (!tg3_flag(tp, 5717_PLUS))
8339 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
8340 NIC_SRAM_RX_BUFFER_DESC);
8342 /* Disable the mini ring */
8343 if (!tg3_flag(tp, 5705_PLUS))
8344 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
8345 BDINFO_FLAGS_DISABLED);
8347 /* Program the jumbo buffer descriptor ring control
8348 * blocks on those devices that have them.
8350 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8351 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
8353 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
8354 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8355 ((u64) tpr->rx_jmb_mapping >> 32));
8356 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8357 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
8358 val = TG3_RX_JMB_RING_SIZE(tp) <<
8359 BDINFO_FLAGS_MAXLEN_SHIFT;
8360 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8361 val | BDINFO_FLAGS_USE_EXT_RECV);
8362 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
8363 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8364 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
8365 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
8367 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8368 BDINFO_FLAGS_DISABLED);
8371 if (tg3_flag(tp, 57765_PLUS)) {
8372 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8373 val = TG3_RX_STD_MAX_SIZE_5700;
8375 val = TG3_RX_STD_MAX_SIZE_5717;
8376 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
8377 val |= (TG3_RX_STD_DMA_SZ << 2);
8379 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
8381 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
8383 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
8385 tpr->rx_std_prod_idx = tp->rx_pending;
8386 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
8388 tpr->rx_jmb_prod_idx =
8389 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
8390 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
8392 tg3_rings_reset(tp);
8394 /* Initialize MAC address and backoff seed. */
8395 __tg3_set_mac_addr(tp, 0);
8397 /* MTU + ethernet header + FCS + optional VLAN tag */
8398 tw32(MAC_RX_MTU_SIZE,
8399 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
8401 /* The slot time is changed by tg3_setup_phy if we
8402 * run at gigabit with half duplex.
8404 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
8405 (6 << TX_LENGTHS_IPG_SHIFT) |
8406 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
8408 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
8409 val |= tr32(MAC_TX_LENGTHS) &
8410 (TX_LENGTHS_JMB_FRM_LEN_MSK |
8411 TX_LENGTHS_CNT_DWN_VAL_MSK);
8413 tw32(MAC_TX_LENGTHS, val);
8415 /* Receive rules. */
8416 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
8417 tw32(RCVLPC_CONFIG, 0x0181);
8419 /* Calculate RDMAC_MODE setting early, we need it to determine
8420 * the RCVLPC_STATE_ENABLE mask.
8422 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
8423 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
8424 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
8425 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
8426 RDMAC_MODE_LNGREAD_ENAB);
8428 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
8429 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
8431 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8432 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8433 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8434 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
8435 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
8436 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
8438 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8439 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
8440 if (tg3_flag(tp, TSO_CAPABLE) &&
8441 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8442 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8443 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8444 !tg3_flag(tp, IS_5788)) {
8445 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8449 if (tg3_flag(tp, PCI_EXPRESS))
8450 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8452 if (tg3_flag(tp, HW_TSO_1) ||
8453 tg3_flag(tp, HW_TSO_2) ||
8454 tg3_flag(tp, HW_TSO_3))
8455 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8457 if (tg3_flag(tp, 57765_PLUS) ||
8458 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8459 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8460 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8462 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
8463 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
8465 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8466 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8467 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8468 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
8469 tg3_flag(tp, 57765_PLUS)) {
8470 val = tr32(TG3_RDMA_RSRVCTRL_REG);
8471 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8472 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8473 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
8474 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
8475 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
8476 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
8477 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
8478 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
8480 tw32(TG3_RDMA_RSRVCTRL_REG,
8481 val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
8484 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8485 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8486 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
8487 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
8488 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
8489 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
8492 /* Receive/send statistics. */
8493 if (tg3_flag(tp, 5750_PLUS)) {
8494 val = tr32(RCVLPC_STATS_ENABLE);
8495 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8496 tw32(RCVLPC_STATS_ENABLE, val);
8497 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8498 tg3_flag(tp, TSO_CAPABLE)) {
8499 val = tr32(RCVLPC_STATS_ENABLE);
8500 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8501 tw32(RCVLPC_STATS_ENABLE, val);
8503 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8505 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8506 tw32(SNDDATAI_STATSENAB, 0xffffff);
8507 tw32(SNDDATAI_STATSCTRL,
8508 (SNDDATAI_SCTRL_ENABLE |
8509 SNDDATAI_SCTRL_FASTUPD));
8511 /* Setup host coalescing engine. */
8512 tw32(HOSTCC_MODE, 0);
8513 for (i = 0; i < 2000; i++) {
8514 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8519 __tg3_set_coalesce(tp, &tp->coal);
8521 if (!tg3_flag(tp, 5705_PLUS)) {
8522 /* Status/statistics block address. See tg3_timer,
8523 * the tg3_periodic_fetch_stats call there, and
8524 * tg3_get_stats to see how this works for 5705/5750 chips.
8526 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8527 ((u64) tp->stats_mapping >> 32));
8528 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8529 ((u64) tp->stats_mapping & 0xffffffff));
8530 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8532 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8534 /* Clear statistics and status block memory areas */
8535 for (i = NIC_SRAM_STATS_BLK;
8536 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8538 tg3_write_mem(tp, i, 0);
8543 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8545 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8546 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8547 if (!tg3_flag(tp, 5705_PLUS))
8548 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8550 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8551 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
8552 /* reset to prevent losing 1st rx packet intermittently */
8553 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8557 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8558 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
8559 MAC_MODE_FHDE_ENABLE;
8560 if (tg3_flag(tp, ENABLE_APE))
8561 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8562 if (!tg3_flag(tp, 5705_PLUS) &&
8563 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8564 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8565 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8566 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8569 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8570 * If TG3_FLAG_IS_NIC is zero, we should read the
8571 * register to preserve the GPIO settings for LOMs. The GPIOs,
8572 * whether used as inputs or outputs, are set by boot code after
8575 if (!tg3_flag(tp, IS_NIC)) {
8578 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8579 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8580 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8582 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8583 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8584 GRC_LCLCTRL_GPIO_OUTPUT3;
8586 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8587 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8589 tp->grc_local_ctrl &= ~gpio_mask;
8590 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8592 /* GPIO1 must be driven high for eeprom write protect */
8593 if (tg3_flag(tp, EEPROM_WRITE_PROT))
8594 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8595 GRC_LCLCTRL_GPIO_OUTPUT1);
8597 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8600 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) {
8601 val = tr32(MSGINT_MODE);
8602 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8603 tw32(MSGINT_MODE, val);
8606 if (!tg3_flag(tp, 5705_PLUS)) {
8607 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8611 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8612 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8613 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8614 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8615 WDMAC_MODE_LNGREAD_ENAB);
8617 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8618 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
8619 if (tg3_flag(tp, TSO_CAPABLE) &&
8620 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8621 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8623 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8624 !tg3_flag(tp, IS_5788)) {
8625 val |= WDMAC_MODE_RX_ACCEL;
8629 /* Enable host coalescing bug fix */
8630 if (tg3_flag(tp, 5755_PLUS))
8631 val |= WDMAC_MODE_STATUS_TAG_FIX;
8633 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8634 val |= WDMAC_MODE_BURST_ALL_DATA;
8636 tw32_f(WDMAC_MODE, val);
8639 if (tg3_flag(tp, PCIX_MODE)) {
8642 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8644 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8645 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8646 pcix_cmd |= PCI_X_CMD_READ_2K;
8647 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8648 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8649 pcix_cmd |= PCI_X_CMD_READ_2K;
8651 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8655 tw32_f(RDMAC_MODE, rdmac_mode);
8658 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8659 if (!tg3_flag(tp, 5705_PLUS))
8660 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8662 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8664 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8666 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8668 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8669 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8670 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
8671 if (tg3_flag(tp, LRG_PROD_RING_CAP))
8672 val |= RCVDBDI_MODE_LRG_RING_SZ;
8673 tw32(RCVDBDI_MODE, val);
8674 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8675 if (tg3_flag(tp, HW_TSO_1) ||
8676 tg3_flag(tp, HW_TSO_2) ||
8677 tg3_flag(tp, HW_TSO_3))
8678 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8679 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8680 if (tg3_flag(tp, ENABLE_TSS))
8681 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8682 tw32(SNDBDI_MODE, val);
8683 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8685 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8686 err = tg3_load_5701_a0_firmware_fix(tp);
8691 if (tg3_flag(tp, TSO_CAPABLE)) {
8692 err = tg3_load_tso_firmware(tp);
8697 tp->tx_mode = TX_MODE_ENABLE;
8699 if (tg3_flag(tp, 5755_PLUS) ||
8700 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8701 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8703 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8704 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
8705 tp->tx_mode &= ~val;
8706 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
8709 tw32_f(MAC_TX_MODE, tp->tx_mode);
8712 if (tg3_flag(tp, ENABLE_RSS)) {
8713 u32 reg = MAC_RSS_INDIR_TBL_0;
8714 u8 *ent = (u8 *)&val;
8716 /* Setup the indirection table */
8717 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8718 int idx = i % sizeof(val);
8720 ent[idx] = i % (tp->irq_cnt - 1);
8721 if (idx == sizeof(val) - 1) {
8727 /* Setup the "secret" hash key. */
8728 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8729 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8730 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8731 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8732 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8733 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8734 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8735 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8736 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8737 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8740 tp->rx_mode = RX_MODE_ENABLE;
8741 if (tg3_flag(tp, 5755_PLUS))
8742 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8744 if (tg3_flag(tp, ENABLE_RSS))
8745 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8746 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8747 RX_MODE_RSS_IPV6_HASH_EN |
8748 RX_MODE_RSS_TCP_IPV6_HASH_EN |
8749 RX_MODE_RSS_IPV4_HASH_EN |
8750 RX_MODE_RSS_TCP_IPV4_HASH_EN;
8752 tw32_f(MAC_RX_MODE, tp->rx_mode);
8755 tw32(MAC_LED_CTRL, tp->led_ctrl);
8757 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8758 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8759 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8762 tw32_f(MAC_RX_MODE, tp->rx_mode);
8765 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8766 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8767 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
8768 /* Set drive transmission level to 1.2V */
8769 /* only if the signal pre-emphasis bit is not set */
8770 val = tr32(MAC_SERDES_CFG);
8773 tw32(MAC_SERDES_CFG, val);
8775 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8776 tw32(MAC_SERDES_CFG, 0x616000);
8779 /* Prevent chip from dropping frames when flow control
8782 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8786 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8788 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8789 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
8790 /* Use hardware link auto-negotiation */
8791 tg3_flag_set(tp, HW_AUTONEG);
8794 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8795 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
8798 tmp = tr32(SERDES_RX_CTRL);
8799 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8800 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8801 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8802 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8805 if (!tg3_flag(tp, USE_PHYLIB)) {
8806 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
8807 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
8808 tp->link_config.speed = tp->link_config.orig_speed;
8809 tp->link_config.duplex = tp->link_config.orig_duplex;
8810 tp->link_config.autoneg = tp->link_config.orig_autoneg;
8813 err = tg3_setup_phy(tp, 0);
8817 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8818 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8821 /* Clear CRC stats. */
8822 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8823 tg3_writephy(tp, MII_TG3_TEST1,
8824 tmp | MII_TG3_TEST1_CRC_EN);
8825 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
8830 __tg3_set_rx_mode(tp->dev);
8832 /* Initialize receive rules. */
8833 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
8834 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8835 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
8836 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8838 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
8842 if (tg3_flag(tp, ENABLE_ASF))
8846 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
8848 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
8850 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
8852 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
8854 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
8856 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
8858 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
8860 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
8862 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
8864 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
8866 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
8868 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
8870 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8872 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8880 if (tg3_flag(tp, ENABLE_APE))
8881 /* Write our heartbeat update interval to APE. */
8882 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8883 APE_HOST_HEARTBEAT_INT_DISABLE);
8885 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8890 /* Called at device open time to get the chip ready for
8891 * packet processing. Invoked with tp->lock held.
8893 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8895 tg3_switch_clocks(tp);
8897 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8899 return tg3_reset_hw(tp, reset_phy);
8902 #define TG3_STAT_ADD32(PSTAT, REG) \
8903 do { u32 __val = tr32(REG); \
8904 (PSTAT)->low += __val; \
8905 if ((PSTAT)->low < __val) \
8906 (PSTAT)->high += 1; \
8909 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8911 struct tg3_hw_stats *sp = tp->hw_stats;
8913 if (!netif_carrier_ok(tp->dev))
8916 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8917 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8918 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8919 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8920 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8921 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8922 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8923 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8924 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8925 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8926 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8927 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8928 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8930 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8931 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8932 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8933 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8934 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8935 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8936 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8937 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8938 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8939 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8940 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8941 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8942 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8943 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8945 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8946 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8947 tp->pci_chip_rev_id != CHIPREV_ID_5719_A0 &&
8948 tp->pci_chip_rev_id != CHIPREV_ID_5720_A0) {
8949 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8951 u32 val = tr32(HOSTCC_FLOW_ATTN);
8952 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
8954 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
8955 sp->rx_discards.low += val;
8956 if (sp->rx_discards.low < val)
8957 sp->rx_discards.high += 1;
8959 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
8961 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8964 static void tg3_chk_missed_msi(struct tg3 *tp)
8968 for (i = 0; i < tp->irq_cnt; i++) {
8969 struct tg3_napi *tnapi = &tp->napi[i];
8971 if (tg3_has_work(tnapi)) {
8972 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
8973 tnapi->last_tx_cons == tnapi->tx_cons) {
8974 if (tnapi->chk_msi_cnt < 1) {
8975 tnapi->chk_msi_cnt++;
8978 tw32_mailbox(tnapi->int_mbox,
8979 tnapi->last_tag << 24);
8982 tnapi->chk_msi_cnt = 0;
8983 tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
8984 tnapi->last_tx_cons = tnapi->tx_cons;
8988 static void tg3_timer(unsigned long __opaque)
8990 struct tg3 *tp = (struct tg3 *) __opaque;
8995 spin_lock(&tp->lock);
8997 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8998 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8999 tg3_chk_missed_msi(tp);
9001 if (!tg3_flag(tp, TAGGED_STATUS)) {
9002 /* All of this garbage is because when using non-tagged
9003 * IRQ status the mailbox/status_block protocol the chip
9004 * uses with the cpu is race prone.
9006 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
9007 tw32(GRC_LOCAL_CTRL,
9008 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
9010 tw32(HOSTCC_MODE, tp->coalesce_mode |
9011 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
9014 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
9015 tg3_flag_set(tp, RESTART_TIMER);
9016 spin_unlock(&tp->lock);
9017 schedule_work(&tp->reset_task);
9022 /* This part only runs once per second. */
9023 if (!--tp->timer_counter) {
9024 if (tg3_flag(tp, 5705_PLUS))
9025 tg3_periodic_fetch_stats(tp);
9027 if (tp->setlpicnt && !--tp->setlpicnt)
9028 tg3_phy_eee_enable(tp);
9030 if (tg3_flag(tp, USE_LINKCHG_REG)) {
9034 mac_stat = tr32(MAC_STATUS);
9037 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
9038 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
9040 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
9044 tg3_setup_phy(tp, 0);
9045 } else if (tg3_flag(tp, POLL_SERDES)) {
9046 u32 mac_stat = tr32(MAC_STATUS);
9049 if (netif_carrier_ok(tp->dev) &&
9050 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
9053 if (!netif_carrier_ok(tp->dev) &&
9054 (mac_stat & (MAC_STATUS_PCS_SYNCED |
9055 MAC_STATUS_SIGNAL_DET))) {
9059 if (!tp->serdes_counter) {
9062 ~MAC_MODE_PORT_MODE_MASK));
9064 tw32_f(MAC_MODE, tp->mac_mode);
9067 tg3_setup_phy(tp, 0);
9069 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
9070 tg3_flag(tp, 5780_CLASS)) {
9071 tg3_serdes_parallel_detect(tp);
9074 tp->timer_counter = tp->timer_multiplier;
9077 /* Heartbeat is only sent once every 2 seconds.
9079 * The heartbeat is to tell the ASF firmware that the host
9080 * driver is still alive. In the event that the OS crashes,
9081 * ASF needs to reset the hardware to free up the FIFO space
9082 * that may be filled with rx packets destined for the host.
9083 * If the FIFO is full, ASF will no longer function properly.
9085 * Unintended resets have been reported on real time kernels
9086 * where the timer doesn't run on time. Netpoll will also have
9089 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
9090 * to check the ring condition when the heartbeat is expiring
9091 * before doing the reset. This will prevent most unintended
9094 if (!--tp->asf_counter) {
9095 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
9096 tg3_wait_for_event_ack(tp);
9098 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
9099 FWCMD_NICDRV_ALIVE3);
9100 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
9101 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
9102 TG3_FW_UPDATE_TIMEOUT_SEC);
9104 tg3_generate_fw_event(tp);
9106 tp->asf_counter = tp->asf_multiplier;
9109 spin_unlock(&tp->lock);
9112 tp->timer.expires = jiffies + tp->timer_offset;
9113 add_timer(&tp->timer);
9116 static int tg3_request_irq(struct tg3 *tp, int irq_num)
9119 unsigned long flags;
9121 struct tg3_napi *tnapi = &tp->napi[irq_num];
9123 if (tp->irq_cnt == 1)
9124 name = tp->dev->name;
9126 name = &tnapi->irq_lbl[0];
9127 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
9128 name[IFNAMSIZ-1] = 0;
9131 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
9133 if (tg3_flag(tp, 1SHOT_MSI))
9138 if (tg3_flag(tp, TAGGED_STATUS))
9139 fn = tg3_interrupt_tagged;
9140 flags = IRQF_SHARED;
9143 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
9146 static int tg3_test_interrupt(struct tg3 *tp)
9148 struct tg3_napi *tnapi = &tp->napi[0];
9149 struct net_device *dev = tp->dev;
9150 int err, i, intr_ok = 0;
9153 if (!netif_running(dev))
9156 tg3_disable_ints(tp);
9158 free_irq(tnapi->irq_vec, tnapi);
9161 * Turn off MSI one shot mode. Otherwise this test has no
9162 * observable way to know whether the interrupt was delivered.
9164 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
9165 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
9166 tw32(MSGINT_MODE, val);
9169 err = request_irq(tnapi->irq_vec, tg3_test_isr,
9170 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
9174 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
9175 tg3_enable_ints(tp);
9177 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9180 for (i = 0; i < 5; i++) {
9181 u32 int_mbox, misc_host_ctrl;
9183 int_mbox = tr32_mailbox(tnapi->int_mbox);
9184 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
9186 if ((int_mbox != 0) ||
9187 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
9195 tg3_disable_ints(tp);
9197 free_irq(tnapi->irq_vec, tnapi);
9199 err = tg3_request_irq(tp, 0);
9205 /* Reenable MSI one shot mode. */
9206 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
9207 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
9208 tw32(MSGINT_MODE, val);
9216 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
9217 * successfully restored
9219 static int tg3_test_msi(struct tg3 *tp)
9224 if (!tg3_flag(tp, USING_MSI))
9227 /* Turn off SERR reporting in case MSI terminates with Master
9230 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9231 pci_write_config_word(tp->pdev, PCI_COMMAND,
9232 pci_cmd & ~PCI_COMMAND_SERR);
9234 err = tg3_test_interrupt(tp);
9236 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9241 /* other failures */
9245 /* MSI test failed, go back to INTx mode */
9246 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
9247 "to INTx mode. Please report this failure to the PCI "
9248 "maintainer and include system chipset information\n");
9250 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
9252 pci_disable_msi(tp->pdev);
9254 tg3_flag_clear(tp, USING_MSI);
9255 tp->napi[0].irq_vec = tp->pdev->irq;
9257 err = tg3_request_irq(tp, 0);
9261 /* Need to reset the chip because the MSI cycle may have terminated
9262 * with Master Abort.
9264 tg3_full_lock(tp, 1);
9266 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9267 err = tg3_init_hw(tp, 1);
9269 tg3_full_unlock(tp);
9272 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
9277 static int tg3_request_firmware(struct tg3 *tp)
9279 const __be32 *fw_data;
9281 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
9282 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
9287 fw_data = (void *)tp->fw->data;
9289 /* Firmware blob starts with version numbers, followed by
9290 * start address and _full_ length including BSS sections
9291 * (which must be longer than the actual data, of course
9294 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
9295 if (tp->fw_len < (tp->fw->size - 12)) {
9296 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
9297 tp->fw_len, tp->fw_needed);
9298 release_firmware(tp->fw);
9303 /* We no longer need firmware; we have it. */
9304 tp->fw_needed = NULL;
9308 static bool tg3_enable_msix(struct tg3 *tp)
9310 int i, rc, cpus = num_online_cpus();
9311 struct msix_entry msix_ent[tp->irq_max];
9314 /* Just fallback to the simpler MSI mode. */
9318 * We want as many rx rings enabled as there are cpus.
9319 * The first MSIX vector only deals with link interrupts, etc,
9320 * so we add one to the number of vectors we are requesting.
9322 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
9324 for (i = 0; i < tp->irq_max; i++) {
9325 msix_ent[i].entry = i;
9326 msix_ent[i].vector = 0;
9329 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
9332 } else if (rc != 0) {
9333 if (pci_enable_msix(tp->pdev, msix_ent, rc))
9335 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
9340 for (i = 0; i < tp->irq_max; i++)
9341 tp->napi[i].irq_vec = msix_ent[i].vector;
9343 netif_set_real_num_tx_queues(tp->dev, 1);
9344 rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1;
9345 if (netif_set_real_num_rx_queues(tp->dev, rc)) {
9346 pci_disable_msix(tp->pdev);
9350 if (tp->irq_cnt > 1) {
9351 tg3_flag_set(tp, ENABLE_RSS);
9353 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
9354 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
9355 tg3_flag_set(tp, ENABLE_TSS);
9356 netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1);
9363 static void tg3_ints_init(struct tg3 *tp)
9365 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
9366 !tg3_flag(tp, TAGGED_STATUS)) {
9367 /* All MSI supporting chips should support tagged
9368 * status. Assert that this is the case.
9370 netdev_warn(tp->dev,
9371 "MSI without TAGGED_STATUS? Not using MSI\n");
9375 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
9376 tg3_flag_set(tp, USING_MSIX);
9377 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
9378 tg3_flag_set(tp, USING_MSI);
9380 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
9381 u32 msi_mode = tr32(MSGINT_MODE);
9382 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
9383 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
9384 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
9387 if (!tg3_flag(tp, USING_MSIX)) {
9389 tp->napi[0].irq_vec = tp->pdev->irq;
9390 netif_set_real_num_tx_queues(tp->dev, 1);
9391 netif_set_real_num_rx_queues(tp->dev, 1);
9395 static void tg3_ints_fini(struct tg3 *tp)
9397 if (tg3_flag(tp, USING_MSIX))
9398 pci_disable_msix(tp->pdev);
9399 else if (tg3_flag(tp, USING_MSI))
9400 pci_disable_msi(tp->pdev);
9401 tg3_flag_clear(tp, USING_MSI);
9402 tg3_flag_clear(tp, USING_MSIX);
9403 tg3_flag_clear(tp, ENABLE_RSS);
9404 tg3_flag_clear(tp, ENABLE_TSS);
9407 static int tg3_open(struct net_device *dev)
9409 struct tg3 *tp = netdev_priv(dev);
9412 if (tp->fw_needed) {
9413 err = tg3_request_firmware(tp);
9414 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
9418 netdev_warn(tp->dev, "TSO capability disabled\n");
9419 tg3_flag_clear(tp, TSO_CAPABLE);
9420 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
9421 netdev_notice(tp->dev, "TSO capability restored\n");
9422 tg3_flag_set(tp, TSO_CAPABLE);
9426 netif_carrier_off(tp->dev);
9428 err = tg3_power_up(tp);
9432 tg3_full_lock(tp, 0);
9434 tg3_disable_ints(tp);
9435 tg3_flag_clear(tp, INIT_COMPLETE);
9437 tg3_full_unlock(tp);
9440 * Setup interrupts first so we know how
9441 * many NAPI resources to allocate
9445 /* The placement of this call is tied
9446 * to the setup and use of Host TX descriptors.
9448 err = tg3_alloc_consistent(tp);
9454 tg3_napi_enable(tp);
9456 for (i = 0; i < tp->irq_cnt; i++) {
9457 struct tg3_napi *tnapi = &tp->napi[i];
9458 err = tg3_request_irq(tp, i);
9460 for (i--; i >= 0; i--)
9461 free_irq(tnapi->irq_vec, tnapi);
9469 tg3_full_lock(tp, 0);
9471 err = tg3_init_hw(tp, 1);
9473 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9476 if (tg3_flag(tp, TAGGED_STATUS) &&
9477 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
9478 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765)
9479 tp->timer_offset = HZ;
9481 tp->timer_offset = HZ / 10;
9483 BUG_ON(tp->timer_offset > HZ);
9484 tp->timer_counter = tp->timer_multiplier =
9485 (HZ / tp->timer_offset);
9486 tp->asf_counter = tp->asf_multiplier =
9487 ((HZ / tp->timer_offset) * 2);
9489 init_timer(&tp->timer);
9490 tp->timer.expires = jiffies + tp->timer_offset;
9491 tp->timer.data = (unsigned long) tp;
9492 tp->timer.function = tg3_timer;
9495 tg3_full_unlock(tp);
9500 if (tg3_flag(tp, USING_MSI)) {
9501 err = tg3_test_msi(tp);
9504 tg3_full_lock(tp, 0);
9505 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9507 tg3_full_unlock(tp);
9512 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
9513 u32 val = tr32(PCIE_TRANSACTION_CFG);
9515 tw32(PCIE_TRANSACTION_CFG,
9516 val | PCIE_TRANS_CFG_1SHOT_MSI);
9522 tg3_full_lock(tp, 0);
9524 add_timer(&tp->timer);
9525 tg3_flag_set(tp, INIT_COMPLETE);
9526 tg3_enable_ints(tp);
9528 tg3_full_unlock(tp);
9530 netif_tx_start_all_queues(dev);
9533 * Reset loopback feature if it was turned on while the device was down
9534 * make sure that it's installed properly now.
9536 if (dev->features & NETIF_F_LOOPBACK)
9537 tg3_set_loopback(dev, dev->features);
9542 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9543 struct tg3_napi *tnapi = &tp->napi[i];
9544 free_irq(tnapi->irq_vec, tnapi);
9548 tg3_napi_disable(tp);
9550 tg3_free_consistent(tp);
9554 tg3_frob_aux_power(tp, false);
9555 pci_set_power_state(tp->pdev, PCI_D3hot);
9559 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9560 struct rtnl_link_stats64 *);
9561 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9563 static int tg3_close(struct net_device *dev)
9566 struct tg3 *tp = netdev_priv(dev);
9568 tg3_napi_disable(tp);
9569 cancel_work_sync(&tp->reset_task);
9571 netif_tx_stop_all_queues(dev);
9573 del_timer_sync(&tp->timer);
9577 tg3_full_lock(tp, 1);
9579 tg3_disable_ints(tp);
9581 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9583 tg3_flag_clear(tp, INIT_COMPLETE);
9585 tg3_full_unlock(tp);
9587 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9588 struct tg3_napi *tnapi = &tp->napi[i];
9589 free_irq(tnapi->irq_vec, tnapi);
9594 tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9596 memcpy(&tp->estats_prev, tg3_get_estats(tp),
9597 sizeof(tp->estats_prev));
9601 tg3_free_consistent(tp);
9605 netif_carrier_off(tp->dev);
9610 static inline u64 get_stat64(tg3_stat64_t *val)
9612 return ((u64)val->high << 32) | ((u64)val->low);
9615 static u64 calc_crc_errors(struct tg3 *tp)
9617 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9619 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9620 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9621 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9624 spin_lock_bh(&tp->lock);
9625 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9626 tg3_writephy(tp, MII_TG3_TEST1,
9627 val | MII_TG3_TEST1_CRC_EN);
9628 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
9631 spin_unlock_bh(&tp->lock);
9633 tp->phy_crc_errors += val;
9635 return tp->phy_crc_errors;
9638 return get_stat64(&hw_stats->rx_fcs_errors);
9641 #define ESTAT_ADD(member) \
9642 estats->member = old_estats->member + \
9643 get_stat64(&hw_stats->member)
9645 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9647 struct tg3_ethtool_stats *estats = &tp->estats;
9648 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9649 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9654 ESTAT_ADD(rx_octets);
9655 ESTAT_ADD(rx_fragments);
9656 ESTAT_ADD(rx_ucast_packets);
9657 ESTAT_ADD(rx_mcast_packets);
9658 ESTAT_ADD(rx_bcast_packets);
9659 ESTAT_ADD(rx_fcs_errors);
9660 ESTAT_ADD(rx_align_errors);
9661 ESTAT_ADD(rx_xon_pause_rcvd);
9662 ESTAT_ADD(rx_xoff_pause_rcvd);
9663 ESTAT_ADD(rx_mac_ctrl_rcvd);
9664 ESTAT_ADD(rx_xoff_entered);
9665 ESTAT_ADD(rx_frame_too_long_errors);
9666 ESTAT_ADD(rx_jabbers);
9667 ESTAT_ADD(rx_undersize_packets);
9668 ESTAT_ADD(rx_in_length_errors);
9669 ESTAT_ADD(rx_out_length_errors);
9670 ESTAT_ADD(rx_64_or_less_octet_packets);
9671 ESTAT_ADD(rx_65_to_127_octet_packets);
9672 ESTAT_ADD(rx_128_to_255_octet_packets);
9673 ESTAT_ADD(rx_256_to_511_octet_packets);
9674 ESTAT_ADD(rx_512_to_1023_octet_packets);
9675 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9676 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9677 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9678 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9679 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9681 ESTAT_ADD(tx_octets);
9682 ESTAT_ADD(tx_collisions);
9683 ESTAT_ADD(tx_xon_sent);
9684 ESTAT_ADD(tx_xoff_sent);
9685 ESTAT_ADD(tx_flow_control);
9686 ESTAT_ADD(tx_mac_errors);
9687 ESTAT_ADD(tx_single_collisions);
9688 ESTAT_ADD(tx_mult_collisions);
9689 ESTAT_ADD(tx_deferred);
9690 ESTAT_ADD(tx_excessive_collisions);
9691 ESTAT_ADD(tx_late_collisions);
9692 ESTAT_ADD(tx_collide_2times);
9693 ESTAT_ADD(tx_collide_3times);
9694 ESTAT_ADD(tx_collide_4times);
9695 ESTAT_ADD(tx_collide_5times);
9696 ESTAT_ADD(tx_collide_6times);
9697 ESTAT_ADD(tx_collide_7times);
9698 ESTAT_ADD(tx_collide_8times);
9699 ESTAT_ADD(tx_collide_9times);
9700 ESTAT_ADD(tx_collide_10times);
9701 ESTAT_ADD(tx_collide_11times);
9702 ESTAT_ADD(tx_collide_12times);
9703 ESTAT_ADD(tx_collide_13times);
9704 ESTAT_ADD(tx_collide_14times);
9705 ESTAT_ADD(tx_collide_15times);
9706 ESTAT_ADD(tx_ucast_packets);
9707 ESTAT_ADD(tx_mcast_packets);
9708 ESTAT_ADD(tx_bcast_packets);
9709 ESTAT_ADD(tx_carrier_sense_errors);
9710 ESTAT_ADD(tx_discards);
9711 ESTAT_ADD(tx_errors);
9713 ESTAT_ADD(dma_writeq_full);
9714 ESTAT_ADD(dma_write_prioq_full);
9715 ESTAT_ADD(rxbds_empty);
9716 ESTAT_ADD(rx_discards);
9717 ESTAT_ADD(rx_errors);
9718 ESTAT_ADD(rx_threshold_hit);
9720 ESTAT_ADD(dma_readq_full);
9721 ESTAT_ADD(dma_read_prioq_full);
9722 ESTAT_ADD(tx_comp_queue_full);
9724 ESTAT_ADD(ring_set_send_prod_index);
9725 ESTAT_ADD(ring_status_update);
9726 ESTAT_ADD(nic_irqs);
9727 ESTAT_ADD(nic_avoided_irqs);
9728 ESTAT_ADD(nic_tx_threshold_hit);
9730 ESTAT_ADD(mbuf_lwm_thresh_hit);
9735 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9736 struct rtnl_link_stats64 *stats)
9738 struct tg3 *tp = netdev_priv(dev);
9739 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
9740 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9745 stats->rx_packets = old_stats->rx_packets +
9746 get_stat64(&hw_stats->rx_ucast_packets) +
9747 get_stat64(&hw_stats->rx_mcast_packets) +
9748 get_stat64(&hw_stats->rx_bcast_packets);
9750 stats->tx_packets = old_stats->tx_packets +
9751 get_stat64(&hw_stats->tx_ucast_packets) +
9752 get_stat64(&hw_stats->tx_mcast_packets) +
9753 get_stat64(&hw_stats->tx_bcast_packets);
9755 stats->rx_bytes = old_stats->rx_bytes +
9756 get_stat64(&hw_stats->rx_octets);
9757 stats->tx_bytes = old_stats->tx_bytes +
9758 get_stat64(&hw_stats->tx_octets);
9760 stats->rx_errors = old_stats->rx_errors +
9761 get_stat64(&hw_stats->rx_errors);
9762 stats->tx_errors = old_stats->tx_errors +
9763 get_stat64(&hw_stats->tx_errors) +
9764 get_stat64(&hw_stats->tx_mac_errors) +
9765 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9766 get_stat64(&hw_stats->tx_discards);
9768 stats->multicast = old_stats->multicast +
9769 get_stat64(&hw_stats->rx_mcast_packets);
9770 stats->collisions = old_stats->collisions +
9771 get_stat64(&hw_stats->tx_collisions);
9773 stats->rx_length_errors = old_stats->rx_length_errors +
9774 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9775 get_stat64(&hw_stats->rx_undersize_packets);
9777 stats->rx_over_errors = old_stats->rx_over_errors +
9778 get_stat64(&hw_stats->rxbds_empty);
9779 stats->rx_frame_errors = old_stats->rx_frame_errors +
9780 get_stat64(&hw_stats->rx_align_errors);
9781 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9782 get_stat64(&hw_stats->tx_discards);
9783 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9784 get_stat64(&hw_stats->tx_carrier_sense_errors);
9786 stats->rx_crc_errors = old_stats->rx_crc_errors +
9787 calc_crc_errors(tp);
9789 stats->rx_missed_errors = old_stats->rx_missed_errors +
9790 get_stat64(&hw_stats->rx_discards);
9792 stats->rx_dropped = tp->rx_dropped;
9797 static inline u32 calc_crc(unsigned char *buf, int len)
9805 for (j = 0; j < len; j++) {
9808 for (k = 0; k < 8; k++) {
9821 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9823 /* accept or reject all multicast frames */
9824 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9825 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9826 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9827 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9830 static void __tg3_set_rx_mode(struct net_device *dev)
9832 struct tg3 *tp = netdev_priv(dev);
9835 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9836 RX_MODE_KEEP_VLAN_TAG);
9838 #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9839 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9842 if (!tg3_flag(tp, ENABLE_ASF))
9843 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9846 if (dev->flags & IFF_PROMISC) {
9847 /* Promiscuous mode. */
9848 rx_mode |= RX_MODE_PROMISC;
9849 } else if (dev->flags & IFF_ALLMULTI) {
9850 /* Accept all multicast. */
9851 tg3_set_multi(tp, 1);
9852 } else if (netdev_mc_empty(dev)) {
9853 /* Reject all multicast. */
9854 tg3_set_multi(tp, 0);
9856 /* Accept one or more multicast(s). */
9857 struct netdev_hw_addr *ha;
9858 u32 mc_filter[4] = { 0, };
9863 netdev_for_each_mc_addr(ha, dev) {
9864 crc = calc_crc(ha->addr, ETH_ALEN);
9866 regidx = (bit & 0x60) >> 5;
9868 mc_filter[regidx] |= (1 << bit);
9871 tw32(MAC_HASH_REG_0, mc_filter[0]);
9872 tw32(MAC_HASH_REG_1, mc_filter[1]);
9873 tw32(MAC_HASH_REG_2, mc_filter[2]);
9874 tw32(MAC_HASH_REG_3, mc_filter[3]);
9877 if (rx_mode != tp->rx_mode) {
9878 tp->rx_mode = rx_mode;
9879 tw32_f(MAC_RX_MODE, rx_mode);
9884 static void tg3_set_rx_mode(struct net_device *dev)
9886 struct tg3 *tp = netdev_priv(dev);
9888 if (!netif_running(dev))
9891 tg3_full_lock(tp, 0);
9892 __tg3_set_rx_mode(dev);
9893 tg3_full_unlock(tp);
9896 static int tg3_get_regs_len(struct net_device *dev)
9898 return TG3_REG_BLK_SIZE;
9901 static void tg3_get_regs(struct net_device *dev,
9902 struct ethtool_regs *regs, void *_p)
9904 struct tg3 *tp = netdev_priv(dev);
9908 memset(_p, 0, TG3_REG_BLK_SIZE);
9910 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9913 tg3_full_lock(tp, 0);
9915 tg3_dump_legacy_regs(tp, (u32 *)_p);
9917 tg3_full_unlock(tp);
9920 static int tg3_get_eeprom_len(struct net_device *dev)
9922 struct tg3 *tp = netdev_priv(dev);
9924 return tp->nvram_size;
9927 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9929 struct tg3 *tp = netdev_priv(dev);
9932 u32 i, offset, len, b_offset, b_count;
9935 if (tg3_flag(tp, NO_NVRAM))
9938 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9941 offset = eeprom->offset;
9945 eeprom->magic = TG3_EEPROM_MAGIC;
9948 /* adjustments to start on required 4 byte boundary */
9949 b_offset = offset & 3;
9950 b_count = 4 - b_offset;
9951 if (b_count > len) {
9952 /* i.e. offset=1 len=2 */
9955 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9958 memcpy(data, ((char *)&val) + b_offset, b_count);
9961 eeprom->len += b_count;
9964 /* read bytes up to the last 4 byte boundary */
9965 pd = &data[eeprom->len];
9966 for (i = 0; i < (len - (len & 3)); i += 4) {
9967 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9972 memcpy(pd + i, &val, 4);
9977 /* read last bytes not ending on 4 byte boundary */
9978 pd = &data[eeprom->len];
9980 b_offset = offset + len - b_count;
9981 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9984 memcpy(pd, &val, b_count);
9985 eeprom->len += b_count;
9990 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9992 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9994 struct tg3 *tp = netdev_priv(dev);
9996 u32 offset, len, b_offset, odd_len;
10000 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10003 if (tg3_flag(tp, NO_NVRAM) ||
10004 eeprom->magic != TG3_EEPROM_MAGIC)
10007 offset = eeprom->offset;
10010 if ((b_offset = (offset & 3))) {
10011 /* adjustments to start on required 4 byte boundary */
10012 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
10023 /* adjustments to end on required 4 byte boundary */
10025 len = (len + 3) & ~3;
10026 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
10032 if (b_offset || odd_len) {
10033 buf = kmalloc(len, GFP_KERNEL);
10037 memcpy(buf, &start, 4);
10039 memcpy(buf+len-4, &end, 4);
10040 memcpy(buf + b_offset, data, eeprom->len);
10043 ret = tg3_nvram_write_block(tp, offset, len, buf);
10051 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
10053 struct tg3 *tp = netdev_priv(dev);
10055 if (tg3_flag(tp, USE_PHYLIB)) {
10056 struct phy_device *phydev;
10057 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10059 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10060 return phy_ethtool_gset(phydev, cmd);
10063 cmd->supported = (SUPPORTED_Autoneg);
10065 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
10066 cmd->supported |= (SUPPORTED_1000baseT_Half |
10067 SUPPORTED_1000baseT_Full);
10069 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
10070 cmd->supported |= (SUPPORTED_100baseT_Half |
10071 SUPPORTED_100baseT_Full |
10072 SUPPORTED_10baseT_Half |
10073 SUPPORTED_10baseT_Full |
10075 cmd->port = PORT_TP;
10077 cmd->supported |= SUPPORTED_FIBRE;
10078 cmd->port = PORT_FIBRE;
10081 cmd->advertising = tp->link_config.advertising;
10082 if (tg3_flag(tp, PAUSE_AUTONEG)) {
10083 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
10084 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
10085 cmd->advertising |= ADVERTISED_Pause;
10087 cmd->advertising |= ADVERTISED_Pause |
10088 ADVERTISED_Asym_Pause;
10090 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
10091 cmd->advertising |= ADVERTISED_Asym_Pause;
10094 if (netif_running(dev)) {
10095 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
10096 cmd->duplex = tp->link_config.active_duplex;
10098 ethtool_cmd_speed_set(cmd, SPEED_INVALID);
10099 cmd->duplex = DUPLEX_INVALID;
10101 cmd->phy_address = tp->phy_addr;
10102 cmd->transceiver = XCVR_INTERNAL;
10103 cmd->autoneg = tp->link_config.autoneg;
10109 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
10111 struct tg3 *tp = netdev_priv(dev);
10112 u32 speed = ethtool_cmd_speed(cmd);
10114 if (tg3_flag(tp, USE_PHYLIB)) {
10115 struct phy_device *phydev;
10116 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10118 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10119 return phy_ethtool_sset(phydev, cmd);
10122 if (cmd->autoneg != AUTONEG_ENABLE &&
10123 cmd->autoneg != AUTONEG_DISABLE)
10126 if (cmd->autoneg == AUTONEG_DISABLE &&
10127 cmd->duplex != DUPLEX_FULL &&
10128 cmd->duplex != DUPLEX_HALF)
10131 if (cmd->autoneg == AUTONEG_ENABLE) {
10132 u32 mask = ADVERTISED_Autoneg |
10134 ADVERTISED_Asym_Pause;
10136 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
10137 mask |= ADVERTISED_1000baseT_Half |
10138 ADVERTISED_1000baseT_Full;
10140 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
10141 mask |= ADVERTISED_100baseT_Half |
10142 ADVERTISED_100baseT_Full |
10143 ADVERTISED_10baseT_Half |
10144 ADVERTISED_10baseT_Full |
10147 mask |= ADVERTISED_FIBRE;
10149 if (cmd->advertising & ~mask)
10152 mask &= (ADVERTISED_1000baseT_Half |
10153 ADVERTISED_1000baseT_Full |
10154 ADVERTISED_100baseT_Half |
10155 ADVERTISED_100baseT_Full |
10156 ADVERTISED_10baseT_Half |
10157 ADVERTISED_10baseT_Full);
10159 cmd->advertising &= mask;
10161 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
10162 if (speed != SPEED_1000)
10165 if (cmd->duplex != DUPLEX_FULL)
10168 if (speed != SPEED_100 &&
10174 tg3_full_lock(tp, 0);
10176 tp->link_config.autoneg = cmd->autoneg;
10177 if (cmd->autoneg == AUTONEG_ENABLE) {
10178 tp->link_config.advertising = (cmd->advertising |
10179 ADVERTISED_Autoneg);
10180 tp->link_config.speed = SPEED_INVALID;
10181 tp->link_config.duplex = DUPLEX_INVALID;
10183 tp->link_config.advertising = 0;
10184 tp->link_config.speed = speed;
10185 tp->link_config.duplex = cmd->duplex;
10188 tp->link_config.orig_speed = tp->link_config.speed;
10189 tp->link_config.orig_duplex = tp->link_config.duplex;
10190 tp->link_config.orig_autoneg = tp->link_config.autoneg;
10192 if (netif_running(dev))
10193 tg3_setup_phy(tp, 1);
10195 tg3_full_unlock(tp);
10200 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
10202 struct tg3 *tp = netdev_priv(dev);
10204 strcpy(info->driver, DRV_MODULE_NAME);
10205 strcpy(info->version, DRV_MODULE_VERSION);
10206 strcpy(info->fw_version, tp->fw_ver);
10207 strcpy(info->bus_info, pci_name(tp->pdev));
10210 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
10212 struct tg3 *tp = netdev_priv(dev);
10214 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
10215 wol->supported = WAKE_MAGIC;
10217 wol->supported = 0;
10219 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
10220 wol->wolopts = WAKE_MAGIC;
10221 memset(&wol->sopass, 0, sizeof(wol->sopass));
10224 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
10226 struct tg3 *tp = netdev_priv(dev);
10227 struct device *dp = &tp->pdev->dev;
10229 if (wol->wolopts & ~WAKE_MAGIC)
10231 if ((wol->wolopts & WAKE_MAGIC) &&
10232 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
10235 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
10237 spin_lock_bh(&tp->lock);
10238 if (device_may_wakeup(dp))
10239 tg3_flag_set(tp, WOL_ENABLE);
10241 tg3_flag_clear(tp, WOL_ENABLE);
10242 spin_unlock_bh(&tp->lock);
10247 static u32 tg3_get_msglevel(struct net_device *dev)
10249 struct tg3 *tp = netdev_priv(dev);
10250 return tp->msg_enable;
10253 static void tg3_set_msglevel(struct net_device *dev, u32 value)
10255 struct tg3 *tp = netdev_priv(dev);
10256 tp->msg_enable = value;
10259 static int tg3_nway_reset(struct net_device *dev)
10261 struct tg3 *tp = netdev_priv(dev);
10264 if (!netif_running(dev))
10267 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10270 if (tg3_flag(tp, USE_PHYLIB)) {
10271 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10273 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
10277 spin_lock_bh(&tp->lock);
10279 tg3_readphy(tp, MII_BMCR, &bmcr);
10280 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
10281 ((bmcr & BMCR_ANENABLE) ||
10282 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
10283 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
10287 spin_unlock_bh(&tp->lock);
10293 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10295 struct tg3 *tp = netdev_priv(dev);
10297 ering->rx_max_pending = tp->rx_std_ring_mask;
10298 ering->rx_mini_max_pending = 0;
10299 if (tg3_flag(tp, JUMBO_RING_ENABLE))
10300 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
10302 ering->rx_jumbo_max_pending = 0;
10304 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
10306 ering->rx_pending = tp->rx_pending;
10307 ering->rx_mini_pending = 0;
10308 if (tg3_flag(tp, JUMBO_RING_ENABLE))
10309 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
10311 ering->rx_jumbo_pending = 0;
10313 ering->tx_pending = tp->napi[0].tx_pending;
10316 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10318 struct tg3 *tp = netdev_priv(dev);
10319 int i, irq_sync = 0, err = 0;
10321 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
10322 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
10323 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
10324 (ering->tx_pending <= MAX_SKB_FRAGS) ||
10325 (tg3_flag(tp, TSO_BUG) &&
10326 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
10329 if (netif_running(dev)) {
10331 tg3_netif_stop(tp);
10335 tg3_full_lock(tp, irq_sync);
10337 tp->rx_pending = ering->rx_pending;
10339 if (tg3_flag(tp, MAX_RXPEND_64) &&
10340 tp->rx_pending > 63)
10341 tp->rx_pending = 63;
10342 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
10344 for (i = 0; i < tp->irq_max; i++)
10345 tp->napi[i].tx_pending = ering->tx_pending;
10347 if (netif_running(dev)) {
10348 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10349 err = tg3_restart_hw(tp, 1);
10351 tg3_netif_start(tp);
10354 tg3_full_unlock(tp);
10356 if (irq_sync && !err)
10362 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10364 struct tg3 *tp = netdev_priv(dev);
10366 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
10368 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
10369 epause->rx_pause = 1;
10371 epause->rx_pause = 0;
10373 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
10374 epause->tx_pause = 1;
10376 epause->tx_pause = 0;
10379 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10381 struct tg3 *tp = netdev_priv(dev);
10384 if (tg3_flag(tp, USE_PHYLIB)) {
10386 struct phy_device *phydev;
10388 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10390 if (!(phydev->supported & SUPPORTED_Pause) ||
10391 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
10392 (epause->rx_pause != epause->tx_pause)))
10395 tp->link_config.flowctrl = 0;
10396 if (epause->rx_pause) {
10397 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10399 if (epause->tx_pause) {
10400 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10401 newadv = ADVERTISED_Pause;
10403 newadv = ADVERTISED_Pause |
10404 ADVERTISED_Asym_Pause;
10405 } else if (epause->tx_pause) {
10406 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10407 newadv = ADVERTISED_Asym_Pause;
10411 if (epause->autoneg)
10412 tg3_flag_set(tp, PAUSE_AUTONEG);
10414 tg3_flag_clear(tp, PAUSE_AUTONEG);
10416 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
10417 u32 oldadv = phydev->advertising &
10418 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
10419 if (oldadv != newadv) {
10420 phydev->advertising &=
10421 ~(ADVERTISED_Pause |
10422 ADVERTISED_Asym_Pause);
10423 phydev->advertising |= newadv;
10424 if (phydev->autoneg) {
10426 * Always renegotiate the link to
10427 * inform our link partner of our
10428 * flow control settings, even if the
10429 * flow control is forced. Let
10430 * tg3_adjust_link() do the final
10431 * flow control setup.
10433 return phy_start_aneg(phydev);
10437 if (!epause->autoneg)
10438 tg3_setup_flow_control(tp, 0, 0);
10440 tp->link_config.orig_advertising &=
10441 ~(ADVERTISED_Pause |
10442 ADVERTISED_Asym_Pause);
10443 tp->link_config.orig_advertising |= newadv;
10448 if (netif_running(dev)) {
10449 tg3_netif_stop(tp);
10453 tg3_full_lock(tp, irq_sync);
10455 if (epause->autoneg)
10456 tg3_flag_set(tp, PAUSE_AUTONEG);
10458 tg3_flag_clear(tp, PAUSE_AUTONEG);
10459 if (epause->rx_pause)
10460 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10462 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10463 if (epause->tx_pause)
10464 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10466 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10468 if (netif_running(dev)) {
10469 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10470 err = tg3_restart_hw(tp, 1);
10472 tg3_netif_start(tp);
10475 tg3_full_unlock(tp);
10481 static int tg3_get_sset_count(struct net_device *dev, int sset)
10485 return TG3_NUM_TEST;
10487 return TG3_NUM_STATS;
10489 return -EOPNOTSUPP;
10493 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10495 switch (stringset) {
10497 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
10500 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
10503 WARN_ON(1); /* we need a WARN() */
10508 static int tg3_set_phys_id(struct net_device *dev,
10509 enum ethtool_phys_id_state state)
10511 struct tg3 *tp = netdev_priv(dev);
10513 if (!netif_running(tp->dev))
10517 case ETHTOOL_ID_ACTIVE:
10518 return 1; /* cycle on/off once per second */
10520 case ETHTOOL_ID_ON:
10521 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10522 LED_CTRL_1000MBPS_ON |
10523 LED_CTRL_100MBPS_ON |
10524 LED_CTRL_10MBPS_ON |
10525 LED_CTRL_TRAFFIC_OVERRIDE |
10526 LED_CTRL_TRAFFIC_BLINK |
10527 LED_CTRL_TRAFFIC_LED);
10530 case ETHTOOL_ID_OFF:
10531 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10532 LED_CTRL_TRAFFIC_OVERRIDE);
10535 case ETHTOOL_ID_INACTIVE:
10536 tw32(MAC_LED_CTRL, tp->led_ctrl);
10543 static void tg3_get_ethtool_stats(struct net_device *dev,
10544 struct ethtool_stats *estats, u64 *tmp_stats)
10546 struct tg3 *tp = netdev_priv(dev);
10547 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10550 static __be32 * tg3_vpd_readblock(struct tg3 *tp)
10554 u32 offset = 0, len = 0;
10557 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
10560 if (magic == TG3_EEPROM_MAGIC) {
10561 for (offset = TG3_NVM_DIR_START;
10562 offset < TG3_NVM_DIR_END;
10563 offset += TG3_NVM_DIRENT_SIZE) {
10564 if (tg3_nvram_read(tp, offset, &val))
10567 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
10568 TG3_NVM_DIRTYPE_EXTVPD)
10572 if (offset != TG3_NVM_DIR_END) {
10573 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
10574 if (tg3_nvram_read(tp, offset + 4, &offset))
10577 offset = tg3_nvram_logical_addr(tp, offset);
10581 if (!offset || !len) {
10582 offset = TG3_NVM_VPD_OFF;
10583 len = TG3_NVM_VPD_LEN;
10586 buf = kmalloc(len, GFP_KERNEL);
10590 if (magic == TG3_EEPROM_MAGIC) {
10591 for (i = 0; i < len; i += 4) {
10592 /* The data is in little-endian format in NVRAM.
10593 * Use the big-endian read routines to preserve
10594 * the byte order as it exists in NVRAM.
10596 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
10602 unsigned int pos = 0;
10604 ptr = (u8 *)&buf[0];
10605 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
10606 cnt = pci_read_vpd(tp->pdev, pos,
10608 if (cnt == -ETIMEDOUT || cnt == -EINTR)
10624 #define NVRAM_TEST_SIZE 0x100
10625 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10626 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10627 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
10628 #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
10629 #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
10630 #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x4c
10631 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10632 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10634 static int tg3_test_nvram(struct tg3 *tp)
10638 int i, j, k, err = 0, size;
10640 if (tg3_flag(tp, NO_NVRAM))
10643 if (tg3_nvram_read(tp, 0, &magic) != 0)
10646 if (magic == TG3_EEPROM_MAGIC)
10647 size = NVRAM_TEST_SIZE;
10648 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10649 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10650 TG3_EEPROM_SB_FORMAT_1) {
10651 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10652 case TG3_EEPROM_SB_REVISION_0:
10653 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10655 case TG3_EEPROM_SB_REVISION_2:
10656 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10658 case TG3_EEPROM_SB_REVISION_3:
10659 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10661 case TG3_EEPROM_SB_REVISION_4:
10662 size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
10664 case TG3_EEPROM_SB_REVISION_5:
10665 size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
10667 case TG3_EEPROM_SB_REVISION_6:
10668 size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
10675 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10676 size = NVRAM_SELFBOOT_HW_SIZE;
10680 buf = kmalloc(size, GFP_KERNEL);
10685 for (i = 0, j = 0; i < size; i += 4, j++) {
10686 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10693 /* Selfboot format */
10694 magic = be32_to_cpu(buf[0]);
10695 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10696 TG3_EEPROM_MAGIC_FW) {
10697 u8 *buf8 = (u8 *) buf, csum8 = 0;
10699 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10700 TG3_EEPROM_SB_REVISION_2) {
10701 /* For rev 2, the csum doesn't include the MBA. */
10702 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10704 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10707 for (i = 0; i < size; i++)
10720 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10721 TG3_EEPROM_MAGIC_HW) {
10722 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10723 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10724 u8 *buf8 = (u8 *) buf;
10726 /* Separate the parity bits and the data bytes. */
10727 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10728 if ((i == 0) || (i == 8)) {
10732 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10733 parity[k++] = buf8[i] & msk;
10735 } else if (i == 16) {
10739 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10740 parity[k++] = buf8[i] & msk;
10743 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10744 parity[k++] = buf8[i] & msk;
10747 data[j++] = buf8[i];
10751 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10752 u8 hw8 = hweight8(data[i]);
10754 if ((hw8 & 0x1) && parity[i])
10756 else if (!(hw8 & 0x1) && !parity[i])
10765 /* Bootstrap checksum at offset 0x10 */
10766 csum = calc_crc((unsigned char *) buf, 0x10);
10767 if (csum != le32_to_cpu(buf[0x10/4]))
10770 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10771 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10772 if (csum != le32_to_cpu(buf[0xfc/4]))
10777 buf = tg3_vpd_readblock(tp);
10781 i = pci_vpd_find_tag((u8 *)buf, 0, TG3_NVM_VPD_LEN,
10782 PCI_VPD_LRDT_RO_DATA);
10784 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
10788 if (i + PCI_VPD_LRDT_TAG_SIZE + j > TG3_NVM_VPD_LEN)
10791 i += PCI_VPD_LRDT_TAG_SIZE;
10792 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
10793 PCI_VPD_RO_KEYWORD_CHKSUM);
10797 j += PCI_VPD_INFO_FLD_HDR_SIZE;
10799 for (i = 0; i <= j; i++)
10800 csum8 += ((u8 *)buf)[i];
10814 #define TG3_SERDES_TIMEOUT_SEC 2
10815 #define TG3_COPPER_TIMEOUT_SEC 6
10817 static int tg3_test_link(struct tg3 *tp)
10821 if (!netif_running(tp->dev))
10824 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
10825 max = TG3_SERDES_TIMEOUT_SEC;
10827 max = TG3_COPPER_TIMEOUT_SEC;
10829 for (i = 0; i < max; i++) {
10830 if (netif_carrier_ok(tp->dev))
10833 if (msleep_interruptible(1000))
10840 /* Only test the commonly used registers */
10841 static int tg3_test_registers(struct tg3 *tp)
10843 int i, is_5705, is_5750;
10844 u32 offset, read_mask, write_mask, val, save_val, read_val;
10848 #define TG3_FL_5705 0x1
10849 #define TG3_FL_NOT_5705 0x2
10850 #define TG3_FL_NOT_5788 0x4
10851 #define TG3_FL_NOT_5750 0x8
10855 /* MAC Control Registers */
10856 { MAC_MODE, TG3_FL_NOT_5705,
10857 0x00000000, 0x00ef6f8c },
10858 { MAC_MODE, TG3_FL_5705,
10859 0x00000000, 0x01ef6b8c },
10860 { MAC_STATUS, TG3_FL_NOT_5705,
10861 0x03800107, 0x00000000 },
10862 { MAC_STATUS, TG3_FL_5705,
10863 0x03800100, 0x00000000 },
10864 { MAC_ADDR_0_HIGH, 0x0000,
10865 0x00000000, 0x0000ffff },
10866 { MAC_ADDR_0_LOW, 0x0000,
10867 0x00000000, 0xffffffff },
10868 { MAC_RX_MTU_SIZE, 0x0000,
10869 0x00000000, 0x0000ffff },
10870 { MAC_TX_MODE, 0x0000,
10871 0x00000000, 0x00000070 },
10872 { MAC_TX_LENGTHS, 0x0000,
10873 0x00000000, 0x00003fff },
10874 { MAC_RX_MODE, TG3_FL_NOT_5705,
10875 0x00000000, 0x000007fc },
10876 { MAC_RX_MODE, TG3_FL_5705,
10877 0x00000000, 0x000007dc },
10878 { MAC_HASH_REG_0, 0x0000,
10879 0x00000000, 0xffffffff },
10880 { MAC_HASH_REG_1, 0x0000,
10881 0x00000000, 0xffffffff },
10882 { MAC_HASH_REG_2, 0x0000,
10883 0x00000000, 0xffffffff },
10884 { MAC_HASH_REG_3, 0x0000,
10885 0x00000000, 0xffffffff },
10887 /* Receive Data and Receive BD Initiator Control Registers. */
10888 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10889 0x00000000, 0xffffffff },
10890 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10891 0x00000000, 0xffffffff },
10892 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10893 0x00000000, 0x00000003 },
10894 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10895 0x00000000, 0xffffffff },
10896 { RCVDBDI_STD_BD+0, 0x0000,
10897 0x00000000, 0xffffffff },
10898 { RCVDBDI_STD_BD+4, 0x0000,
10899 0x00000000, 0xffffffff },
10900 { RCVDBDI_STD_BD+8, 0x0000,
10901 0x00000000, 0xffff0002 },
10902 { RCVDBDI_STD_BD+0xc, 0x0000,
10903 0x00000000, 0xffffffff },
10905 /* Receive BD Initiator Control Registers. */
10906 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10907 0x00000000, 0xffffffff },
10908 { RCVBDI_STD_THRESH, TG3_FL_5705,
10909 0x00000000, 0x000003ff },
10910 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10911 0x00000000, 0xffffffff },
10913 /* Host Coalescing Control Registers. */
10914 { HOSTCC_MODE, TG3_FL_NOT_5705,
10915 0x00000000, 0x00000004 },
10916 { HOSTCC_MODE, TG3_FL_5705,
10917 0x00000000, 0x000000f6 },
10918 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10919 0x00000000, 0xffffffff },
10920 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10921 0x00000000, 0x000003ff },
10922 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10923 0x00000000, 0xffffffff },
10924 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10925 0x00000000, 0x000003ff },
10926 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10927 0x00000000, 0xffffffff },
10928 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10929 0x00000000, 0x000000ff },
10930 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10931 0x00000000, 0xffffffff },
10932 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10933 0x00000000, 0x000000ff },
10934 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10935 0x00000000, 0xffffffff },
10936 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10937 0x00000000, 0xffffffff },
10938 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10939 0x00000000, 0xffffffff },
10940 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10941 0x00000000, 0x000000ff },
10942 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10943 0x00000000, 0xffffffff },
10944 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10945 0x00000000, 0x000000ff },
10946 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10947 0x00000000, 0xffffffff },
10948 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10949 0x00000000, 0xffffffff },
10950 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10951 0x00000000, 0xffffffff },
10952 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10953 0x00000000, 0xffffffff },
10954 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10955 0x00000000, 0xffffffff },
10956 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10957 0xffffffff, 0x00000000 },
10958 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10959 0xffffffff, 0x00000000 },
10961 /* Buffer Manager Control Registers. */
10962 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10963 0x00000000, 0x007fff80 },
10964 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10965 0x00000000, 0x007fffff },
10966 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10967 0x00000000, 0x0000003f },
10968 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10969 0x00000000, 0x000001ff },
10970 { BUFMGR_MB_HIGH_WATER, 0x0000,
10971 0x00000000, 0x000001ff },
10972 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10973 0xffffffff, 0x00000000 },
10974 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10975 0xffffffff, 0x00000000 },
10977 /* Mailbox Registers */
10978 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10979 0x00000000, 0x000001ff },
10980 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10981 0x00000000, 0x000001ff },
10982 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10983 0x00000000, 0x000007ff },
10984 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10985 0x00000000, 0x000001ff },
10987 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10990 is_5705 = is_5750 = 0;
10991 if (tg3_flag(tp, 5705_PLUS)) {
10993 if (tg3_flag(tp, 5750_PLUS))
10997 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10998 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
11001 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
11004 if (tg3_flag(tp, IS_5788) &&
11005 (reg_tbl[i].flags & TG3_FL_NOT_5788))
11008 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
11011 offset = (u32) reg_tbl[i].offset;
11012 read_mask = reg_tbl[i].read_mask;
11013 write_mask = reg_tbl[i].write_mask;
11015 /* Save the original register content */
11016 save_val = tr32(offset);
11018 /* Determine the read-only value. */
11019 read_val = save_val & read_mask;
11021 /* Write zero to the register, then make sure the read-only bits
11022 * are not changed and the read/write bits are all zeros.
11026 val = tr32(offset);
11028 /* Test the read-only and read/write bits. */
11029 if (((val & read_mask) != read_val) || (val & write_mask))
11032 /* Write ones to all the bits defined by RdMask and WrMask, then
11033 * make sure the read-only bits are not changed and the
11034 * read/write bits are all ones.
11036 tw32(offset, read_mask | write_mask);
11038 val = tr32(offset);
11040 /* Test the read-only bits. */
11041 if ((val & read_mask) != read_val)
11044 /* Test the read/write bits. */
11045 if ((val & write_mask) != write_mask)
11048 tw32(offset, save_val);
11054 if (netif_msg_hw(tp))
11055 netdev_err(tp->dev,
11056 "Register test failed at offset %x\n", offset);
11057 tw32(offset, save_val);
11061 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
11063 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
11067 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
11068 for (j = 0; j < len; j += 4) {
11071 tg3_write_mem(tp, offset + j, test_pattern[i]);
11072 tg3_read_mem(tp, offset + j, &val);
11073 if (val != test_pattern[i])
11080 static int tg3_test_memory(struct tg3 *tp)
11082 static struct mem_entry {
11085 } mem_tbl_570x[] = {
11086 { 0x00000000, 0x00b50},
11087 { 0x00002000, 0x1c000},
11088 { 0xffffffff, 0x00000}
11089 }, mem_tbl_5705[] = {
11090 { 0x00000100, 0x0000c},
11091 { 0x00000200, 0x00008},
11092 { 0x00004000, 0x00800},
11093 { 0x00006000, 0x01000},
11094 { 0x00008000, 0x02000},
11095 { 0x00010000, 0x0e000},
11096 { 0xffffffff, 0x00000}
11097 }, mem_tbl_5755[] = {
11098 { 0x00000200, 0x00008},
11099 { 0x00004000, 0x00800},
11100 { 0x00006000, 0x00800},
11101 { 0x00008000, 0x02000},
11102 { 0x00010000, 0x0c000},
11103 { 0xffffffff, 0x00000}
11104 }, mem_tbl_5906[] = {
11105 { 0x00000200, 0x00008},
11106 { 0x00004000, 0x00400},
11107 { 0x00006000, 0x00400},
11108 { 0x00008000, 0x01000},
11109 { 0x00010000, 0x01000},
11110 { 0xffffffff, 0x00000}
11111 }, mem_tbl_5717[] = {
11112 { 0x00000200, 0x00008},
11113 { 0x00010000, 0x0a000},
11114 { 0x00020000, 0x13c00},
11115 { 0xffffffff, 0x00000}
11116 }, mem_tbl_57765[] = {
11117 { 0x00000200, 0x00008},
11118 { 0x00004000, 0x00800},
11119 { 0x00006000, 0x09800},
11120 { 0x00010000, 0x0a000},
11121 { 0xffffffff, 0x00000}
11123 struct mem_entry *mem_tbl;
11127 if (tg3_flag(tp, 5717_PLUS))
11128 mem_tbl = mem_tbl_5717;
11129 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11130 mem_tbl = mem_tbl_57765;
11131 else if (tg3_flag(tp, 5755_PLUS))
11132 mem_tbl = mem_tbl_5755;
11133 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11134 mem_tbl = mem_tbl_5906;
11135 else if (tg3_flag(tp, 5705_PLUS))
11136 mem_tbl = mem_tbl_5705;
11138 mem_tbl = mem_tbl_570x;
11140 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
11141 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
11149 #define TG3_MAC_LOOPBACK 0
11150 #define TG3_PHY_LOOPBACK 1
11151 #define TG3_TSO_LOOPBACK 2
11153 #define TG3_TSO_MSS 500
11155 #define TG3_TSO_IP_HDR_LEN 20
11156 #define TG3_TSO_TCP_HDR_LEN 20
11157 #define TG3_TSO_TCP_OPT_LEN 12
11159 static const u8 tg3_tso_header[] = {
11161 0x45, 0x00, 0x00, 0x00,
11162 0x00, 0x00, 0x40, 0x00,
11163 0x40, 0x06, 0x00, 0x00,
11164 0x0a, 0x00, 0x00, 0x01,
11165 0x0a, 0x00, 0x00, 0x02,
11166 0x0d, 0x00, 0xe0, 0x00,
11167 0x00, 0x00, 0x01, 0x00,
11168 0x00, 0x00, 0x02, 0x00,
11169 0x80, 0x10, 0x10, 0x00,
11170 0x14, 0x09, 0x00, 0x00,
11171 0x01, 0x01, 0x08, 0x0a,
11172 0x11, 0x11, 0x11, 0x11,
11173 0x11, 0x11, 0x11, 0x11,
11176 static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, int loopback_mode)
11178 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
11179 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
11180 struct sk_buff *skb, *rx_skb;
11183 int num_pkts, tx_len, rx_len, i, err;
11184 struct tg3_rx_buffer_desc *desc;
11185 struct tg3_napi *tnapi, *rnapi;
11186 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
11188 tnapi = &tp->napi[0];
11189 rnapi = &tp->napi[0];
11190 if (tp->irq_cnt > 1) {
11191 if (tg3_flag(tp, ENABLE_RSS))
11192 rnapi = &tp->napi[1];
11193 if (tg3_flag(tp, ENABLE_TSS))
11194 tnapi = &tp->napi[1];
11196 coal_now = tnapi->coal_now | rnapi->coal_now;
11198 if (loopback_mode == TG3_MAC_LOOPBACK) {
11199 /* HW errata - mac loopback fails in some cases on 5780.
11200 * Normal traffic and PHY loopback are not affected by
11201 * errata. Also, the MAC loopback test is deprecated for
11202 * all newer ASIC revisions.
11204 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
11205 tg3_flag(tp, CPMU_PRESENT))
11208 mac_mode = tp->mac_mode &
11209 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
11210 mac_mode |= MAC_MODE_PORT_INT_LPBACK;
11211 if (!tg3_flag(tp, 5705_PLUS))
11212 mac_mode |= MAC_MODE_LINK_POLARITY;
11213 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
11214 mac_mode |= MAC_MODE_PORT_MODE_MII;
11216 mac_mode |= MAC_MODE_PORT_MODE_GMII;
11217 tw32(MAC_MODE, mac_mode);
11219 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
11220 tg3_phy_fet_toggle_apd(tp, false);
11221 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
11223 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
11225 tg3_phy_toggle_automdix(tp, 0);
11227 tg3_writephy(tp, MII_BMCR, val);
11230 mac_mode = tp->mac_mode &
11231 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
11232 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
11233 tg3_writephy(tp, MII_TG3_FET_PTEST,
11234 MII_TG3_FET_PTEST_FRC_TX_LINK |
11235 MII_TG3_FET_PTEST_FRC_TX_LOCK);
11236 /* The write needs to be flushed for the AC131 */
11237 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11238 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
11239 mac_mode |= MAC_MODE_PORT_MODE_MII;
11241 mac_mode |= MAC_MODE_PORT_MODE_GMII;
11243 /* reset to prevent losing 1st rx packet intermittently */
11244 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
11245 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
11247 tw32_f(MAC_RX_MODE, tp->rx_mode);
11249 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
11250 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
11251 if (masked_phy_id == TG3_PHY_ID_BCM5401)
11252 mac_mode &= ~MAC_MODE_LINK_POLARITY;
11253 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
11254 mac_mode |= MAC_MODE_LINK_POLARITY;
11255 tg3_writephy(tp, MII_TG3_EXT_CTRL,
11256 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
11258 tw32(MAC_MODE, mac_mode);
11260 /* Wait for link */
11261 for (i = 0; i < 100; i++) {
11262 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
11271 skb = netdev_alloc_skb(tp->dev, tx_len);
11275 tx_data = skb_put(skb, tx_len);
11276 memcpy(tx_data, tp->dev->dev_addr, 6);
11277 memset(tx_data + 6, 0x0, 8);
11279 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
11281 if (loopback_mode == TG3_TSO_LOOPBACK) {
11282 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
11284 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
11285 TG3_TSO_TCP_OPT_LEN;
11287 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
11288 sizeof(tg3_tso_header));
11291 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
11292 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
11294 /* Set the total length field in the IP header */
11295 iph->tot_len = htons((u16)(mss + hdr_len));
11297 base_flags = (TXD_FLAG_CPU_PRE_DMA |
11298 TXD_FLAG_CPU_POST_DMA);
11300 if (tg3_flag(tp, HW_TSO_1) ||
11301 tg3_flag(tp, HW_TSO_2) ||
11302 tg3_flag(tp, HW_TSO_3)) {
11304 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
11305 th = (struct tcphdr *)&tx_data[val];
11308 base_flags |= TXD_FLAG_TCPUDP_CSUM;
11310 if (tg3_flag(tp, HW_TSO_3)) {
11311 mss |= (hdr_len & 0xc) << 12;
11312 if (hdr_len & 0x10)
11313 base_flags |= 0x00000010;
11314 base_flags |= (hdr_len & 0x3e0) << 5;
11315 } else if (tg3_flag(tp, HW_TSO_2))
11316 mss |= hdr_len << 9;
11317 else if (tg3_flag(tp, HW_TSO_1) ||
11318 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
11319 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
11321 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
11324 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
11327 data_off = ETH_HLEN;
11330 for (i = data_off; i < tx_len; i++)
11331 tx_data[i] = (u8) (i & 0xff);
11333 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
11334 if (pci_dma_mapping_error(tp->pdev, map)) {
11335 dev_kfree_skb(skb);
11339 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11344 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
11346 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len,
11347 base_flags, (mss << 1) | 1);
11351 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
11352 tr32_mailbox(tnapi->prodmbox);
11356 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
11357 for (i = 0; i < 35; i++) {
11358 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11363 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
11364 rx_idx = rnapi->hw_status->idx[0].rx_producer;
11365 if ((tx_idx == tnapi->tx_prod) &&
11366 (rx_idx == (rx_start_idx + num_pkts)))
11370 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
11371 dev_kfree_skb(skb);
11373 if (tx_idx != tnapi->tx_prod)
11376 if (rx_idx != rx_start_idx + num_pkts)
11380 while (rx_idx != rx_start_idx) {
11381 desc = &rnapi->rx_rcb[rx_start_idx++];
11382 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
11383 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
11385 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
11386 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
11389 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
11392 if (loopback_mode != TG3_TSO_LOOPBACK) {
11393 if (rx_len != tx_len)
11396 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
11397 if (opaque_key != RXD_OPAQUE_RING_STD)
11400 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
11403 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
11404 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
11405 >> RXD_TCPCSUM_SHIFT != 0xffff) {
11409 if (opaque_key == RXD_OPAQUE_RING_STD) {
11410 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
11411 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
11413 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
11414 rx_skb = tpr->rx_jmb_buffers[desc_idx].skb;
11415 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
11420 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
11421 PCI_DMA_FROMDEVICE);
11423 for (i = data_off; i < rx_len; i++, val++) {
11424 if (*(rx_skb->data + i) != (u8) (val & 0xff))
11431 /* tg3_free_rings will unmap and free the rx_skb */
11436 #define TG3_STD_LOOPBACK_FAILED 1
11437 #define TG3_JMB_LOOPBACK_FAILED 2
11438 #define TG3_TSO_LOOPBACK_FAILED 4
11440 #define TG3_MAC_LOOPBACK_SHIFT 0
11441 #define TG3_PHY_LOOPBACK_SHIFT 4
11442 #define TG3_LOOPBACK_FAILED 0x00000077
11444 static int tg3_test_loopback(struct tg3 *tp)
11447 u32 eee_cap, cpmuctrl = 0;
11449 if (!netif_running(tp->dev))
11450 return TG3_LOOPBACK_FAILED;
11452 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
11453 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11455 err = tg3_reset_hw(tp, 1);
11457 err = TG3_LOOPBACK_FAILED;
11461 if (tg3_flag(tp, ENABLE_RSS)) {
11464 /* Reroute all rx packets to the 1st queue */
11465 for (i = MAC_RSS_INDIR_TBL_0;
11466 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
11470 /* Turn off gphy autopowerdown. */
11471 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11472 tg3_phy_toggle_apd(tp, false);
11474 if (tg3_flag(tp, CPMU_PRESENT)) {
11478 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
11480 /* Wait for up to 40 microseconds to acquire lock. */
11481 for (i = 0; i < 4; i++) {
11482 status = tr32(TG3_CPMU_MUTEX_GNT);
11483 if (status == CPMU_MUTEX_GNT_DRIVER)
11488 if (status != CPMU_MUTEX_GNT_DRIVER) {
11489 err = TG3_LOOPBACK_FAILED;
11493 /* Turn off link-based power management. */
11494 cpmuctrl = tr32(TG3_CPMU_CTRL);
11495 tw32(TG3_CPMU_CTRL,
11496 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
11497 CPMU_CTRL_LINK_AWARE_MODE));
11500 if (tg3_run_loopback(tp, ETH_FRAME_LEN, TG3_MAC_LOOPBACK))
11501 err |= TG3_STD_LOOPBACK_FAILED << TG3_MAC_LOOPBACK_SHIFT;
11503 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
11504 tg3_run_loopback(tp, 9000 + ETH_HLEN, TG3_MAC_LOOPBACK))
11505 err |= TG3_JMB_LOOPBACK_FAILED << TG3_MAC_LOOPBACK_SHIFT;
11507 if (tg3_flag(tp, CPMU_PRESENT)) {
11508 tw32(TG3_CPMU_CTRL, cpmuctrl);
11510 /* Release the mutex */
11511 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
11514 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11515 !tg3_flag(tp, USE_PHYLIB)) {
11516 if (tg3_run_loopback(tp, ETH_FRAME_LEN, TG3_PHY_LOOPBACK))
11517 err |= TG3_STD_LOOPBACK_FAILED <<
11518 TG3_PHY_LOOPBACK_SHIFT;
11519 if (tg3_flag(tp, TSO_CAPABLE) &&
11520 tg3_run_loopback(tp, ETH_FRAME_LEN, TG3_TSO_LOOPBACK))
11521 err |= TG3_TSO_LOOPBACK_FAILED <<
11522 TG3_PHY_LOOPBACK_SHIFT;
11523 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
11524 tg3_run_loopback(tp, 9000 + ETH_HLEN, TG3_PHY_LOOPBACK))
11525 err |= TG3_JMB_LOOPBACK_FAILED <<
11526 TG3_PHY_LOOPBACK_SHIFT;
11529 /* Re-enable gphy autopowerdown. */
11530 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11531 tg3_phy_toggle_apd(tp, true);
11534 tp->phy_flags |= eee_cap;
11539 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
11542 struct tg3 *tp = netdev_priv(dev);
11544 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
11545 tg3_power_up(tp)) {
11546 etest->flags |= ETH_TEST_FL_FAILED;
11547 memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
11551 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
11553 if (tg3_test_nvram(tp) != 0) {
11554 etest->flags |= ETH_TEST_FL_FAILED;
11557 if (tg3_test_link(tp) != 0) {
11558 etest->flags |= ETH_TEST_FL_FAILED;
11561 if (etest->flags & ETH_TEST_FL_OFFLINE) {
11562 int err, err2 = 0, irq_sync = 0;
11564 if (netif_running(dev)) {
11566 tg3_netif_stop(tp);
11570 tg3_full_lock(tp, irq_sync);
11572 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
11573 err = tg3_nvram_lock(tp);
11574 tg3_halt_cpu(tp, RX_CPU_BASE);
11575 if (!tg3_flag(tp, 5705_PLUS))
11576 tg3_halt_cpu(tp, TX_CPU_BASE);
11578 tg3_nvram_unlock(tp);
11580 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
11583 if (tg3_test_registers(tp) != 0) {
11584 etest->flags |= ETH_TEST_FL_FAILED;
11587 if (tg3_test_memory(tp) != 0) {
11588 etest->flags |= ETH_TEST_FL_FAILED;
11591 if ((data[4] = tg3_test_loopback(tp)) != 0)
11592 etest->flags |= ETH_TEST_FL_FAILED;
11594 tg3_full_unlock(tp);
11596 if (tg3_test_interrupt(tp) != 0) {
11597 etest->flags |= ETH_TEST_FL_FAILED;
11601 tg3_full_lock(tp, 0);
11603 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11604 if (netif_running(dev)) {
11605 tg3_flag_set(tp, INIT_COMPLETE);
11606 err2 = tg3_restart_hw(tp, 1);
11608 tg3_netif_start(tp);
11611 tg3_full_unlock(tp);
11613 if (irq_sync && !err2)
11616 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11617 tg3_power_down(tp);
11621 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11623 struct mii_ioctl_data *data = if_mii(ifr);
11624 struct tg3 *tp = netdev_priv(dev);
11627 if (tg3_flag(tp, USE_PHYLIB)) {
11628 struct phy_device *phydev;
11629 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
11631 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11632 return phy_mii_ioctl(phydev, ifr, cmd);
11637 data->phy_id = tp->phy_addr;
11640 case SIOCGMIIREG: {
11643 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11644 break; /* We have no PHY */
11646 if (!netif_running(dev))
11649 spin_lock_bh(&tp->lock);
11650 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
11651 spin_unlock_bh(&tp->lock);
11653 data->val_out = mii_regval;
11659 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11660 break; /* We have no PHY */
11662 if (!netif_running(dev))
11665 spin_lock_bh(&tp->lock);
11666 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11667 spin_unlock_bh(&tp->lock);
11675 return -EOPNOTSUPP;
11678 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11680 struct tg3 *tp = netdev_priv(dev);
11682 memcpy(ec, &tp->coal, sizeof(*ec));
11686 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11688 struct tg3 *tp = netdev_priv(dev);
11689 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11690 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11692 if (!tg3_flag(tp, 5705_PLUS)) {
11693 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11694 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11695 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11696 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11699 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11700 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11701 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11702 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11703 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11704 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11705 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11706 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11707 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11708 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11711 /* No rx interrupts will be generated if both are zero */
11712 if ((ec->rx_coalesce_usecs == 0) &&
11713 (ec->rx_max_coalesced_frames == 0))
11716 /* No tx interrupts will be generated if both are zero */
11717 if ((ec->tx_coalesce_usecs == 0) &&
11718 (ec->tx_max_coalesced_frames == 0))
11721 /* Only copy relevant parameters, ignore all others. */
11722 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11723 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11724 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11725 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11726 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11727 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11728 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11729 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11730 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11732 if (netif_running(dev)) {
11733 tg3_full_lock(tp, 0);
11734 __tg3_set_coalesce(tp, &tp->coal);
11735 tg3_full_unlock(tp);
11740 static const struct ethtool_ops tg3_ethtool_ops = {
11741 .get_settings = tg3_get_settings,
11742 .set_settings = tg3_set_settings,
11743 .get_drvinfo = tg3_get_drvinfo,
11744 .get_regs_len = tg3_get_regs_len,
11745 .get_regs = tg3_get_regs,
11746 .get_wol = tg3_get_wol,
11747 .set_wol = tg3_set_wol,
11748 .get_msglevel = tg3_get_msglevel,
11749 .set_msglevel = tg3_set_msglevel,
11750 .nway_reset = tg3_nway_reset,
11751 .get_link = ethtool_op_get_link,
11752 .get_eeprom_len = tg3_get_eeprom_len,
11753 .get_eeprom = tg3_get_eeprom,
11754 .set_eeprom = tg3_set_eeprom,
11755 .get_ringparam = tg3_get_ringparam,
11756 .set_ringparam = tg3_set_ringparam,
11757 .get_pauseparam = tg3_get_pauseparam,
11758 .set_pauseparam = tg3_set_pauseparam,
11759 .self_test = tg3_self_test,
11760 .get_strings = tg3_get_strings,
11761 .set_phys_id = tg3_set_phys_id,
11762 .get_ethtool_stats = tg3_get_ethtool_stats,
11763 .get_coalesce = tg3_get_coalesce,
11764 .set_coalesce = tg3_set_coalesce,
11765 .get_sset_count = tg3_get_sset_count,
11768 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11770 u32 cursize, val, magic;
11772 tp->nvram_size = EEPROM_CHIP_SIZE;
11774 if (tg3_nvram_read(tp, 0, &magic) != 0)
11777 if ((magic != TG3_EEPROM_MAGIC) &&
11778 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11779 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11783 * Size the chip by reading offsets at increasing powers of two.
11784 * When we encounter our validation signature, we know the addressing
11785 * has wrapped around, and thus have our chip size.
11789 while (cursize < tp->nvram_size) {
11790 if (tg3_nvram_read(tp, cursize, &val) != 0)
11799 tp->nvram_size = cursize;
11802 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11806 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
11809 /* Selfboot format */
11810 if (val != TG3_EEPROM_MAGIC) {
11811 tg3_get_eeprom_size(tp);
11815 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11817 /* This is confusing. We want to operate on the
11818 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11819 * call will read from NVRAM and byteswap the data
11820 * according to the byteswapping settings for all
11821 * other register accesses. This ensures the data we
11822 * want will always reside in the lower 16-bits.
11823 * However, the data in NVRAM is in LE format, which
11824 * means the data from the NVRAM read will always be
11825 * opposite the endianness of the CPU. The 16-bit
11826 * byteswap then brings the data to CPU endianness.
11828 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11832 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11835 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11839 nvcfg1 = tr32(NVRAM_CFG1);
11840 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11841 tg3_flag_set(tp, FLASH);
11843 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11844 tw32(NVRAM_CFG1, nvcfg1);
11847 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
11848 tg3_flag(tp, 5780_CLASS)) {
11849 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11850 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11851 tp->nvram_jedecnum = JEDEC_ATMEL;
11852 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11853 tg3_flag_set(tp, NVRAM_BUFFERED);
11855 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11856 tp->nvram_jedecnum = JEDEC_ATMEL;
11857 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11859 case FLASH_VENDOR_ATMEL_EEPROM:
11860 tp->nvram_jedecnum = JEDEC_ATMEL;
11861 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11862 tg3_flag_set(tp, NVRAM_BUFFERED);
11864 case FLASH_VENDOR_ST:
11865 tp->nvram_jedecnum = JEDEC_ST;
11866 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11867 tg3_flag_set(tp, NVRAM_BUFFERED);
11869 case FLASH_VENDOR_SAIFUN:
11870 tp->nvram_jedecnum = JEDEC_SAIFUN;
11871 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11873 case FLASH_VENDOR_SST_SMALL:
11874 case FLASH_VENDOR_SST_LARGE:
11875 tp->nvram_jedecnum = JEDEC_SST;
11876 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11880 tp->nvram_jedecnum = JEDEC_ATMEL;
11881 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11882 tg3_flag_set(tp, NVRAM_BUFFERED);
11886 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11888 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11889 case FLASH_5752PAGE_SIZE_256:
11890 tp->nvram_pagesize = 256;
11892 case FLASH_5752PAGE_SIZE_512:
11893 tp->nvram_pagesize = 512;
11895 case FLASH_5752PAGE_SIZE_1K:
11896 tp->nvram_pagesize = 1024;
11898 case FLASH_5752PAGE_SIZE_2K:
11899 tp->nvram_pagesize = 2048;
11901 case FLASH_5752PAGE_SIZE_4K:
11902 tp->nvram_pagesize = 4096;
11904 case FLASH_5752PAGE_SIZE_264:
11905 tp->nvram_pagesize = 264;
11907 case FLASH_5752PAGE_SIZE_528:
11908 tp->nvram_pagesize = 528;
11913 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11917 nvcfg1 = tr32(NVRAM_CFG1);
11919 /* NVRAM protection for TPM */
11920 if (nvcfg1 & (1 << 27))
11921 tg3_flag_set(tp, PROTECTED_NVRAM);
11923 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11924 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11925 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11926 tp->nvram_jedecnum = JEDEC_ATMEL;
11927 tg3_flag_set(tp, NVRAM_BUFFERED);
11929 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11930 tp->nvram_jedecnum = JEDEC_ATMEL;
11931 tg3_flag_set(tp, NVRAM_BUFFERED);
11932 tg3_flag_set(tp, FLASH);
11934 case FLASH_5752VENDOR_ST_M45PE10:
11935 case FLASH_5752VENDOR_ST_M45PE20:
11936 case FLASH_5752VENDOR_ST_M45PE40:
11937 tp->nvram_jedecnum = JEDEC_ST;
11938 tg3_flag_set(tp, NVRAM_BUFFERED);
11939 tg3_flag_set(tp, FLASH);
11943 if (tg3_flag(tp, FLASH)) {
11944 tg3_nvram_get_pagesize(tp, nvcfg1);
11946 /* For eeprom, set pagesize to maximum eeprom size */
11947 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11949 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11950 tw32(NVRAM_CFG1, nvcfg1);
11954 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11956 u32 nvcfg1, protect = 0;
11958 nvcfg1 = tr32(NVRAM_CFG1);
11960 /* NVRAM protection for TPM */
11961 if (nvcfg1 & (1 << 27)) {
11962 tg3_flag_set(tp, PROTECTED_NVRAM);
11966 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11968 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11969 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11970 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11971 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11972 tp->nvram_jedecnum = JEDEC_ATMEL;
11973 tg3_flag_set(tp, NVRAM_BUFFERED);
11974 tg3_flag_set(tp, FLASH);
11975 tp->nvram_pagesize = 264;
11976 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11977 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11978 tp->nvram_size = (protect ? 0x3e200 :
11979 TG3_NVRAM_SIZE_512KB);
11980 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11981 tp->nvram_size = (protect ? 0x1f200 :
11982 TG3_NVRAM_SIZE_256KB);
11984 tp->nvram_size = (protect ? 0x1f200 :
11985 TG3_NVRAM_SIZE_128KB);
11987 case FLASH_5752VENDOR_ST_M45PE10:
11988 case FLASH_5752VENDOR_ST_M45PE20:
11989 case FLASH_5752VENDOR_ST_M45PE40:
11990 tp->nvram_jedecnum = JEDEC_ST;
11991 tg3_flag_set(tp, NVRAM_BUFFERED);
11992 tg3_flag_set(tp, FLASH);
11993 tp->nvram_pagesize = 256;
11994 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11995 tp->nvram_size = (protect ?
11996 TG3_NVRAM_SIZE_64KB :
11997 TG3_NVRAM_SIZE_128KB);
11998 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11999 tp->nvram_size = (protect ?
12000 TG3_NVRAM_SIZE_64KB :
12001 TG3_NVRAM_SIZE_256KB);
12003 tp->nvram_size = (protect ?
12004 TG3_NVRAM_SIZE_128KB :
12005 TG3_NVRAM_SIZE_512KB);
12010 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
12014 nvcfg1 = tr32(NVRAM_CFG1);
12016 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12017 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
12018 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
12019 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
12020 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
12021 tp->nvram_jedecnum = JEDEC_ATMEL;
12022 tg3_flag_set(tp, NVRAM_BUFFERED);
12023 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12025 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12026 tw32(NVRAM_CFG1, nvcfg1);
12028 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12029 case FLASH_5755VENDOR_ATMEL_FLASH_1:
12030 case FLASH_5755VENDOR_ATMEL_FLASH_2:
12031 case FLASH_5755VENDOR_ATMEL_FLASH_3:
12032 tp->nvram_jedecnum = JEDEC_ATMEL;
12033 tg3_flag_set(tp, NVRAM_BUFFERED);
12034 tg3_flag_set(tp, FLASH);
12035 tp->nvram_pagesize = 264;
12037 case FLASH_5752VENDOR_ST_M45PE10:
12038 case FLASH_5752VENDOR_ST_M45PE20:
12039 case FLASH_5752VENDOR_ST_M45PE40:
12040 tp->nvram_jedecnum = JEDEC_ST;
12041 tg3_flag_set(tp, NVRAM_BUFFERED);
12042 tg3_flag_set(tp, FLASH);
12043 tp->nvram_pagesize = 256;
12048 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
12050 u32 nvcfg1, protect = 0;
12052 nvcfg1 = tr32(NVRAM_CFG1);
12054 /* NVRAM protection for TPM */
12055 if (nvcfg1 & (1 << 27)) {
12056 tg3_flag_set(tp, PROTECTED_NVRAM);
12060 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
12062 case FLASH_5761VENDOR_ATMEL_ADB021D:
12063 case FLASH_5761VENDOR_ATMEL_ADB041D:
12064 case FLASH_5761VENDOR_ATMEL_ADB081D:
12065 case FLASH_5761VENDOR_ATMEL_ADB161D:
12066 case FLASH_5761VENDOR_ATMEL_MDB021D:
12067 case FLASH_5761VENDOR_ATMEL_MDB041D:
12068 case FLASH_5761VENDOR_ATMEL_MDB081D:
12069 case FLASH_5761VENDOR_ATMEL_MDB161D:
12070 tp->nvram_jedecnum = JEDEC_ATMEL;
12071 tg3_flag_set(tp, NVRAM_BUFFERED);
12072 tg3_flag_set(tp, FLASH);
12073 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12074 tp->nvram_pagesize = 256;
12076 case FLASH_5761VENDOR_ST_A_M45PE20:
12077 case FLASH_5761VENDOR_ST_A_M45PE40:
12078 case FLASH_5761VENDOR_ST_A_M45PE80:
12079 case FLASH_5761VENDOR_ST_A_M45PE16:
12080 case FLASH_5761VENDOR_ST_M_M45PE20:
12081 case FLASH_5761VENDOR_ST_M_M45PE40:
12082 case FLASH_5761VENDOR_ST_M_M45PE80:
12083 case FLASH_5761VENDOR_ST_M_M45PE16:
12084 tp->nvram_jedecnum = JEDEC_ST;
12085 tg3_flag_set(tp, NVRAM_BUFFERED);
12086 tg3_flag_set(tp, FLASH);
12087 tp->nvram_pagesize = 256;
12092 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
12095 case FLASH_5761VENDOR_ATMEL_ADB161D:
12096 case FLASH_5761VENDOR_ATMEL_MDB161D:
12097 case FLASH_5761VENDOR_ST_A_M45PE16:
12098 case FLASH_5761VENDOR_ST_M_M45PE16:
12099 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
12101 case FLASH_5761VENDOR_ATMEL_ADB081D:
12102 case FLASH_5761VENDOR_ATMEL_MDB081D:
12103 case FLASH_5761VENDOR_ST_A_M45PE80:
12104 case FLASH_5761VENDOR_ST_M_M45PE80:
12105 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12107 case FLASH_5761VENDOR_ATMEL_ADB041D:
12108 case FLASH_5761VENDOR_ATMEL_MDB041D:
12109 case FLASH_5761VENDOR_ST_A_M45PE40:
12110 case FLASH_5761VENDOR_ST_M_M45PE40:
12111 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12113 case FLASH_5761VENDOR_ATMEL_ADB021D:
12114 case FLASH_5761VENDOR_ATMEL_MDB021D:
12115 case FLASH_5761VENDOR_ST_A_M45PE20:
12116 case FLASH_5761VENDOR_ST_M_M45PE20:
12117 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12123 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
12125 tp->nvram_jedecnum = JEDEC_ATMEL;
12126 tg3_flag_set(tp, NVRAM_BUFFERED);
12127 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12130 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
12134 nvcfg1 = tr32(NVRAM_CFG1);
12136 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12137 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
12138 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
12139 tp->nvram_jedecnum = JEDEC_ATMEL;
12140 tg3_flag_set(tp, NVRAM_BUFFERED);
12141 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12143 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12144 tw32(NVRAM_CFG1, nvcfg1);
12146 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12147 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
12148 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
12149 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
12150 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
12151 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
12152 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
12153 tp->nvram_jedecnum = JEDEC_ATMEL;
12154 tg3_flag_set(tp, NVRAM_BUFFERED);
12155 tg3_flag_set(tp, FLASH);
12157 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12158 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12159 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
12160 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
12161 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12163 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
12164 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
12165 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12167 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
12168 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
12169 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12173 case FLASH_5752VENDOR_ST_M45PE10:
12174 case FLASH_5752VENDOR_ST_M45PE20:
12175 case FLASH_5752VENDOR_ST_M45PE40:
12176 tp->nvram_jedecnum = JEDEC_ST;
12177 tg3_flag_set(tp, NVRAM_BUFFERED);
12178 tg3_flag_set(tp, FLASH);
12180 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12181 case FLASH_5752VENDOR_ST_M45PE10:
12182 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12184 case FLASH_5752VENDOR_ST_M45PE20:
12185 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12187 case FLASH_5752VENDOR_ST_M45PE40:
12188 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12193 tg3_flag_set(tp, NO_NVRAM);
12197 tg3_nvram_get_pagesize(tp, nvcfg1);
12198 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12199 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12203 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
12207 nvcfg1 = tr32(NVRAM_CFG1);
12209 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12210 case FLASH_5717VENDOR_ATMEL_EEPROM:
12211 case FLASH_5717VENDOR_MICRO_EEPROM:
12212 tp->nvram_jedecnum = JEDEC_ATMEL;
12213 tg3_flag_set(tp, NVRAM_BUFFERED);
12214 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12216 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12217 tw32(NVRAM_CFG1, nvcfg1);
12219 case FLASH_5717VENDOR_ATMEL_MDB011D:
12220 case FLASH_5717VENDOR_ATMEL_ADB011B:
12221 case FLASH_5717VENDOR_ATMEL_ADB011D:
12222 case FLASH_5717VENDOR_ATMEL_MDB021D:
12223 case FLASH_5717VENDOR_ATMEL_ADB021B:
12224 case FLASH_5717VENDOR_ATMEL_ADB021D:
12225 case FLASH_5717VENDOR_ATMEL_45USPT:
12226 tp->nvram_jedecnum = JEDEC_ATMEL;
12227 tg3_flag_set(tp, NVRAM_BUFFERED);
12228 tg3_flag_set(tp, FLASH);
12230 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12231 case FLASH_5717VENDOR_ATMEL_MDB021D:
12232 /* Detect size with tg3_nvram_get_size() */
12234 case FLASH_5717VENDOR_ATMEL_ADB021B:
12235 case FLASH_5717VENDOR_ATMEL_ADB021D:
12236 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12239 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12243 case FLASH_5717VENDOR_ST_M_M25PE10:
12244 case FLASH_5717VENDOR_ST_A_M25PE10:
12245 case FLASH_5717VENDOR_ST_M_M45PE10:
12246 case FLASH_5717VENDOR_ST_A_M45PE10:
12247 case FLASH_5717VENDOR_ST_M_M25PE20:
12248 case FLASH_5717VENDOR_ST_A_M25PE20:
12249 case FLASH_5717VENDOR_ST_M_M45PE20:
12250 case FLASH_5717VENDOR_ST_A_M45PE20:
12251 case FLASH_5717VENDOR_ST_25USPT:
12252 case FLASH_5717VENDOR_ST_45USPT:
12253 tp->nvram_jedecnum = JEDEC_ST;
12254 tg3_flag_set(tp, NVRAM_BUFFERED);
12255 tg3_flag_set(tp, FLASH);
12257 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12258 case FLASH_5717VENDOR_ST_M_M25PE20:
12259 case FLASH_5717VENDOR_ST_M_M45PE20:
12260 /* Detect size with tg3_nvram_get_size() */
12262 case FLASH_5717VENDOR_ST_A_M25PE20:
12263 case FLASH_5717VENDOR_ST_A_M45PE20:
12264 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12267 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12272 tg3_flag_set(tp, NO_NVRAM);
12276 tg3_nvram_get_pagesize(tp, nvcfg1);
12277 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12278 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12281 static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp)
12283 u32 nvcfg1, nvmpinstrp;
12285 nvcfg1 = tr32(NVRAM_CFG1);
12286 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
12288 switch (nvmpinstrp) {
12289 case FLASH_5720_EEPROM_HD:
12290 case FLASH_5720_EEPROM_LD:
12291 tp->nvram_jedecnum = JEDEC_ATMEL;
12292 tg3_flag_set(tp, NVRAM_BUFFERED);
12294 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12295 tw32(NVRAM_CFG1, nvcfg1);
12296 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
12297 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12299 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
12301 case FLASH_5720VENDOR_M_ATMEL_DB011D:
12302 case FLASH_5720VENDOR_A_ATMEL_DB011B:
12303 case FLASH_5720VENDOR_A_ATMEL_DB011D:
12304 case FLASH_5720VENDOR_M_ATMEL_DB021D:
12305 case FLASH_5720VENDOR_A_ATMEL_DB021B:
12306 case FLASH_5720VENDOR_A_ATMEL_DB021D:
12307 case FLASH_5720VENDOR_M_ATMEL_DB041D:
12308 case FLASH_5720VENDOR_A_ATMEL_DB041B:
12309 case FLASH_5720VENDOR_A_ATMEL_DB041D:
12310 case FLASH_5720VENDOR_M_ATMEL_DB081D:
12311 case FLASH_5720VENDOR_A_ATMEL_DB081D:
12312 case FLASH_5720VENDOR_ATMEL_45USPT:
12313 tp->nvram_jedecnum = JEDEC_ATMEL;
12314 tg3_flag_set(tp, NVRAM_BUFFERED);
12315 tg3_flag_set(tp, FLASH);
12317 switch (nvmpinstrp) {
12318 case FLASH_5720VENDOR_M_ATMEL_DB021D:
12319 case FLASH_5720VENDOR_A_ATMEL_DB021B:
12320 case FLASH_5720VENDOR_A_ATMEL_DB021D:
12321 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12323 case FLASH_5720VENDOR_M_ATMEL_DB041D:
12324 case FLASH_5720VENDOR_A_ATMEL_DB041B:
12325 case FLASH_5720VENDOR_A_ATMEL_DB041D:
12326 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12328 case FLASH_5720VENDOR_M_ATMEL_DB081D:
12329 case FLASH_5720VENDOR_A_ATMEL_DB081D:
12330 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12333 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12337 case FLASH_5720VENDOR_M_ST_M25PE10:
12338 case FLASH_5720VENDOR_M_ST_M45PE10:
12339 case FLASH_5720VENDOR_A_ST_M25PE10:
12340 case FLASH_5720VENDOR_A_ST_M45PE10:
12341 case FLASH_5720VENDOR_M_ST_M25PE20:
12342 case FLASH_5720VENDOR_M_ST_M45PE20:
12343 case FLASH_5720VENDOR_A_ST_M25PE20:
12344 case FLASH_5720VENDOR_A_ST_M45PE20:
12345 case FLASH_5720VENDOR_M_ST_M25PE40:
12346 case FLASH_5720VENDOR_M_ST_M45PE40:
12347 case FLASH_5720VENDOR_A_ST_M25PE40:
12348 case FLASH_5720VENDOR_A_ST_M45PE40:
12349 case FLASH_5720VENDOR_M_ST_M25PE80:
12350 case FLASH_5720VENDOR_M_ST_M45PE80:
12351 case FLASH_5720VENDOR_A_ST_M25PE80:
12352 case FLASH_5720VENDOR_A_ST_M45PE80:
12353 case FLASH_5720VENDOR_ST_25USPT:
12354 case FLASH_5720VENDOR_ST_45USPT:
12355 tp->nvram_jedecnum = JEDEC_ST;
12356 tg3_flag_set(tp, NVRAM_BUFFERED);
12357 tg3_flag_set(tp, FLASH);
12359 switch (nvmpinstrp) {
12360 case FLASH_5720VENDOR_M_ST_M25PE20:
12361 case FLASH_5720VENDOR_M_ST_M45PE20:
12362 case FLASH_5720VENDOR_A_ST_M25PE20:
12363 case FLASH_5720VENDOR_A_ST_M45PE20:
12364 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12366 case FLASH_5720VENDOR_M_ST_M25PE40:
12367 case FLASH_5720VENDOR_M_ST_M45PE40:
12368 case FLASH_5720VENDOR_A_ST_M25PE40:
12369 case FLASH_5720VENDOR_A_ST_M45PE40:
12370 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12372 case FLASH_5720VENDOR_M_ST_M25PE80:
12373 case FLASH_5720VENDOR_M_ST_M45PE80:
12374 case FLASH_5720VENDOR_A_ST_M25PE80:
12375 case FLASH_5720VENDOR_A_ST_M45PE80:
12376 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12379 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12384 tg3_flag_set(tp, NO_NVRAM);
12388 tg3_nvram_get_pagesize(tp, nvcfg1);
12389 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12390 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12393 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
12394 static void __devinit tg3_nvram_init(struct tg3 *tp)
12396 tw32_f(GRC_EEPROM_ADDR,
12397 (EEPROM_ADDR_FSM_RESET |
12398 (EEPROM_DEFAULT_CLOCK_PERIOD <<
12399 EEPROM_ADDR_CLKPERD_SHIFT)));
12403 /* Enable seeprom accesses. */
12404 tw32_f(GRC_LOCAL_CTRL,
12405 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
12408 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12409 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
12410 tg3_flag_set(tp, NVRAM);
12412 if (tg3_nvram_lock(tp)) {
12413 netdev_warn(tp->dev,
12414 "Cannot get nvram lock, %s failed\n",
12418 tg3_enable_nvram_access(tp);
12420 tp->nvram_size = 0;
12422 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12423 tg3_get_5752_nvram_info(tp);
12424 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12425 tg3_get_5755_nvram_info(tp);
12426 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12427 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12428 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12429 tg3_get_5787_nvram_info(tp);
12430 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
12431 tg3_get_5761_nvram_info(tp);
12432 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12433 tg3_get_5906_nvram_info(tp);
12434 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12435 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
12436 tg3_get_57780_nvram_info(tp);
12437 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
12438 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
12439 tg3_get_5717_nvram_info(tp);
12440 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
12441 tg3_get_5720_nvram_info(tp);
12443 tg3_get_nvram_info(tp);
12445 if (tp->nvram_size == 0)
12446 tg3_get_nvram_size(tp);
12448 tg3_disable_nvram_access(tp);
12449 tg3_nvram_unlock(tp);
12452 tg3_flag_clear(tp, NVRAM);
12453 tg3_flag_clear(tp, NVRAM_BUFFERED);
12455 tg3_get_eeprom_size(tp);
12459 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
12460 u32 offset, u32 len, u8 *buf)
12465 for (i = 0; i < len; i += 4) {
12471 memcpy(&data, buf + i, 4);
12474 * The SEEPROM interface expects the data to always be opposite
12475 * the native endian format. We accomplish this by reversing
12476 * all the operations that would have been performed on the
12477 * data from a call to tg3_nvram_read_be32().
12479 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
12481 val = tr32(GRC_EEPROM_ADDR);
12482 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
12484 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
12486 tw32(GRC_EEPROM_ADDR, val |
12487 (0 << EEPROM_ADDR_DEVID_SHIFT) |
12488 (addr & EEPROM_ADDR_ADDR_MASK) |
12489 EEPROM_ADDR_START |
12490 EEPROM_ADDR_WRITE);
12492 for (j = 0; j < 1000; j++) {
12493 val = tr32(GRC_EEPROM_ADDR);
12495 if (val & EEPROM_ADDR_COMPLETE)
12499 if (!(val & EEPROM_ADDR_COMPLETE)) {
12508 /* offset and length are dword aligned */
12509 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
12513 u32 pagesize = tp->nvram_pagesize;
12514 u32 pagemask = pagesize - 1;
12518 tmp = kmalloc(pagesize, GFP_KERNEL);
12524 u32 phy_addr, page_off, size;
12526 phy_addr = offset & ~pagemask;
12528 for (j = 0; j < pagesize; j += 4) {
12529 ret = tg3_nvram_read_be32(tp, phy_addr + j,
12530 (__be32 *) (tmp + j));
12537 page_off = offset & pagemask;
12544 memcpy(tmp + page_off, buf, size);
12546 offset = offset + (pagesize - page_off);
12548 tg3_enable_nvram_access(tp);
12551 * Before we can erase the flash page, we need
12552 * to issue a special "write enable" command.
12554 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12556 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12559 /* Erase the target page */
12560 tw32(NVRAM_ADDR, phy_addr);
12562 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
12563 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
12565 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12568 /* Issue another write enable to start the write. */
12569 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12571 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12574 for (j = 0; j < pagesize; j += 4) {
12577 data = *((__be32 *) (tmp + j));
12579 tw32(NVRAM_WRDATA, be32_to_cpu(data));
12581 tw32(NVRAM_ADDR, phy_addr + j);
12583 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
12587 nvram_cmd |= NVRAM_CMD_FIRST;
12588 else if (j == (pagesize - 4))
12589 nvram_cmd |= NVRAM_CMD_LAST;
12591 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12598 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12599 tg3_nvram_exec_cmd(tp, nvram_cmd);
12606 /* offset and length are dword aligned */
12607 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
12612 for (i = 0; i < len; i += 4, offset += 4) {
12613 u32 page_off, phy_addr, nvram_cmd;
12616 memcpy(&data, buf + i, 4);
12617 tw32(NVRAM_WRDATA, be32_to_cpu(data));
12619 page_off = offset % tp->nvram_pagesize;
12621 phy_addr = tg3_nvram_phys_addr(tp, offset);
12623 tw32(NVRAM_ADDR, phy_addr);
12625 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
12627 if (page_off == 0 || i == 0)
12628 nvram_cmd |= NVRAM_CMD_FIRST;
12629 if (page_off == (tp->nvram_pagesize - 4))
12630 nvram_cmd |= NVRAM_CMD_LAST;
12632 if (i == (len - 4))
12633 nvram_cmd |= NVRAM_CMD_LAST;
12635 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
12636 !tg3_flag(tp, 5755_PLUS) &&
12637 (tp->nvram_jedecnum == JEDEC_ST) &&
12638 (nvram_cmd & NVRAM_CMD_FIRST)) {
12640 if ((ret = tg3_nvram_exec_cmd(tp,
12641 NVRAM_CMD_WREN | NVRAM_CMD_GO |
12646 if (!tg3_flag(tp, FLASH)) {
12647 /* We always do complete word writes to eeprom. */
12648 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
12651 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12657 /* offset and length are dword aligned */
12658 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12662 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
12663 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
12664 ~GRC_LCLCTRL_GPIO_OUTPUT1);
12668 if (!tg3_flag(tp, NVRAM)) {
12669 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
12673 ret = tg3_nvram_lock(tp);
12677 tg3_enable_nvram_access(tp);
12678 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
12679 tw32(NVRAM_WRITE1, 0x406);
12681 grc_mode = tr32(GRC_MODE);
12682 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12684 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
12685 ret = tg3_nvram_write_block_buffered(tp, offset, len,
12688 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12692 grc_mode = tr32(GRC_MODE);
12693 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12695 tg3_disable_nvram_access(tp);
12696 tg3_nvram_unlock(tp);
12699 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
12700 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
12707 struct subsys_tbl_ent {
12708 u16 subsys_vendor, subsys_devid;
12712 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
12713 /* Broadcom boards. */
12714 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12715 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
12716 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12717 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
12718 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12719 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
12720 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12721 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
12722 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12723 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
12724 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12725 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
12726 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12727 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
12728 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12729 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
12730 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12731 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
12732 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12733 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
12734 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12735 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
12738 { TG3PCI_SUBVENDOR_ID_3COM,
12739 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
12740 { TG3PCI_SUBVENDOR_ID_3COM,
12741 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
12742 { TG3PCI_SUBVENDOR_ID_3COM,
12743 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
12744 { TG3PCI_SUBVENDOR_ID_3COM,
12745 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
12746 { TG3PCI_SUBVENDOR_ID_3COM,
12747 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
12750 { TG3PCI_SUBVENDOR_ID_DELL,
12751 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
12752 { TG3PCI_SUBVENDOR_ID_DELL,
12753 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
12754 { TG3PCI_SUBVENDOR_ID_DELL,
12755 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
12756 { TG3PCI_SUBVENDOR_ID_DELL,
12757 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
12759 /* Compaq boards. */
12760 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12761 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
12762 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12763 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
12764 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12765 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
12766 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12767 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
12768 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12769 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
12772 { TG3PCI_SUBVENDOR_ID_IBM,
12773 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
12776 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
12780 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12781 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12782 tp->pdev->subsystem_vendor) &&
12783 (subsys_id_to_phy_id[i].subsys_devid ==
12784 tp->pdev->subsystem_device))
12785 return &subsys_id_to_phy_id[i];
12790 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12794 tp->phy_id = TG3_PHY_ID_INVALID;
12795 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12797 /* Assume an onboard device and WOL capable by default. */
12798 tg3_flag_set(tp, EEPROM_WRITE_PROT);
12799 tg3_flag_set(tp, WOL_CAP);
12801 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12802 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12803 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
12804 tg3_flag_set(tp, IS_NIC);
12806 val = tr32(VCPU_CFGSHDW);
12807 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12808 tg3_flag_set(tp, ASPM_WORKAROUND);
12809 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12810 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
12811 tg3_flag_set(tp, WOL_ENABLE);
12812 device_set_wakeup_enable(&tp->pdev->dev, true);
12817 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12818 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12819 u32 nic_cfg, led_cfg;
12820 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12821 int eeprom_phy_serdes = 0;
12823 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12824 tp->nic_sram_data_cfg = nic_cfg;
12826 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12827 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12828 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12829 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12830 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703 &&
12831 (ver > 0) && (ver < 0x100))
12832 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12834 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12835 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12837 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12838 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12839 eeprom_phy_serdes = 1;
12841 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12842 if (nic_phy_id != 0) {
12843 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12844 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12846 eeprom_phy_id = (id1 >> 16) << 10;
12847 eeprom_phy_id |= (id2 & 0xfc00) << 16;
12848 eeprom_phy_id |= (id2 & 0x03ff) << 0;
12852 tp->phy_id = eeprom_phy_id;
12853 if (eeprom_phy_serdes) {
12854 if (!tg3_flag(tp, 5705_PLUS))
12855 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12857 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
12860 if (tg3_flag(tp, 5750_PLUS))
12861 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12862 SHASTA_EXT_LED_MODE_MASK);
12864 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12868 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12869 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12872 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12873 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12876 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12877 tp->led_ctrl = LED_CTRL_MODE_MAC;
12879 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12880 * read on some older 5700/5701 bootcode.
12882 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12884 GET_ASIC_REV(tp->pci_chip_rev_id) ==
12886 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12890 case SHASTA_EXT_LED_SHARED:
12891 tp->led_ctrl = LED_CTRL_MODE_SHARED;
12892 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12893 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12894 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12895 LED_CTRL_MODE_PHY_2);
12898 case SHASTA_EXT_LED_MAC:
12899 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12902 case SHASTA_EXT_LED_COMBO:
12903 tp->led_ctrl = LED_CTRL_MODE_COMBO;
12904 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12905 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12906 LED_CTRL_MODE_PHY_2);
12911 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12912 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12913 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12914 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12916 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12917 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12919 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12920 tg3_flag_set(tp, EEPROM_WRITE_PROT);
12921 if ((tp->pdev->subsystem_vendor ==
12922 PCI_VENDOR_ID_ARIMA) &&
12923 (tp->pdev->subsystem_device == 0x205a ||
12924 tp->pdev->subsystem_device == 0x2063))
12925 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
12927 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
12928 tg3_flag_set(tp, IS_NIC);
12931 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12932 tg3_flag_set(tp, ENABLE_ASF);
12933 if (tg3_flag(tp, 5750_PLUS))
12934 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
12937 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12938 tg3_flag(tp, 5750_PLUS))
12939 tg3_flag_set(tp, ENABLE_APE);
12941 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
12942 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12943 tg3_flag_clear(tp, WOL_CAP);
12945 if (tg3_flag(tp, WOL_CAP) &&
12946 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
12947 tg3_flag_set(tp, WOL_ENABLE);
12948 device_set_wakeup_enable(&tp->pdev->dev, true);
12951 if (cfg2 & (1 << 17))
12952 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
12954 /* serdes signal pre-emphasis in register 0x590 set by */
12955 /* bootcode if bit 18 is set */
12956 if (cfg2 & (1 << 18))
12957 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
12959 if ((tg3_flag(tp, 57765_PLUS) ||
12960 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12961 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12962 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12963 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
12965 if (tg3_flag(tp, PCI_EXPRESS) &&
12966 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12967 !tg3_flag(tp, 57765_PLUS)) {
12970 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12971 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12972 tg3_flag_set(tp, ASPM_WORKAROUND);
12975 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12976 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
12977 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12978 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
12979 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12980 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
12983 if (tg3_flag(tp, WOL_CAP))
12984 device_set_wakeup_enable(&tp->pdev->dev,
12985 tg3_flag(tp, WOL_ENABLE));
12987 device_set_wakeup_capable(&tp->pdev->dev, false);
12990 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12995 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12996 tw32(OTP_CTRL, cmd);
12998 /* Wait for up to 1 ms for command to execute. */
12999 for (i = 0; i < 100; i++) {
13000 val = tr32(OTP_STATUS);
13001 if (val & OTP_STATUS_CMD_DONE)
13006 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
13009 /* Read the gphy configuration from the OTP region of the chip. The gphy
13010 * configuration is a 32-bit value that straddles the alignment boundary.
13011 * We do two 32-bit reads and then shift and merge the results.
13013 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
13015 u32 bhalf_otp, thalf_otp;
13017 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
13019 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
13022 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
13024 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
13027 thalf_otp = tr32(OTP_READ_DATA);
13029 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
13031 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
13034 bhalf_otp = tr32(OTP_READ_DATA);
13036 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
13039 static void __devinit tg3_phy_init_link_config(struct tg3 *tp)
13041 u32 adv = ADVERTISED_Autoneg |
13044 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
13045 adv |= ADVERTISED_1000baseT_Half |
13046 ADVERTISED_1000baseT_Full;
13048 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13049 adv |= ADVERTISED_100baseT_Half |
13050 ADVERTISED_100baseT_Full |
13051 ADVERTISED_10baseT_Half |
13052 ADVERTISED_10baseT_Full |
13055 adv |= ADVERTISED_FIBRE;
13057 tp->link_config.advertising = adv;
13058 tp->link_config.speed = SPEED_INVALID;
13059 tp->link_config.duplex = DUPLEX_INVALID;
13060 tp->link_config.autoneg = AUTONEG_ENABLE;
13061 tp->link_config.active_speed = SPEED_INVALID;
13062 tp->link_config.active_duplex = DUPLEX_INVALID;
13063 tp->link_config.orig_speed = SPEED_INVALID;
13064 tp->link_config.orig_duplex = DUPLEX_INVALID;
13065 tp->link_config.orig_autoneg = AUTONEG_INVALID;
13068 static int __devinit tg3_phy_probe(struct tg3 *tp)
13070 u32 hw_phy_id_1, hw_phy_id_2;
13071 u32 hw_phy_id, hw_phy_id_masked;
13074 /* flow control autonegotiation is default behavior */
13075 tg3_flag_set(tp, PAUSE_AUTONEG);
13076 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
13078 if (tg3_flag(tp, USE_PHYLIB))
13079 return tg3_phy_init(tp);
13081 /* Reading the PHY ID register can conflict with ASF
13082 * firmware access to the PHY hardware.
13085 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
13086 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
13088 /* Now read the physical PHY_ID from the chip and verify
13089 * that it is sane. If it doesn't look good, we fall back
13090 * to either the hard-coded table based PHY_ID and failing
13091 * that the value found in the eeprom area.
13093 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
13094 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
13096 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
13097 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
13098 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
13100 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
13103 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
13104 tp->phy_id = hw_phy_id;
13105 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
13106 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
13108 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
13110 if (tp->phy_id != TG3_PHY_ID_INVALID) {
13111 /* Do nothing, phy ID already set up in
13112 * tg3_get_eeprom_hw_cfg().
13115 struct subsys_tbl_ent *p;
13117 /* No eeprom signature? Try the hardcoded
13118 * subsys device table.
13120 p = tg3_lookup_by_subsys(tp);
13124 tp->phy_id = p->phy_id;
13126 tp->phy_id == TG3_PHY_ID_BCM8002)
13127 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
13131 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
13132 ((tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 &&
13133 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) ||
13134 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
13135 tp->pci_chip_rev_id != CHIPREV_ID_57765_A0)))
13136 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
13138 tg3_phy_init_link_config(tp);
13140 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
13141 !tg3_flag(tp, ENABLE_APE) &&
13142 !tg3_flag(tp, ENABLE_ASF)) {
13145 tg3_readphy(tp, MII_BMSR, &bmsr);
13146 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
13147 (bmsr & BMSR_LSTATUS))
13148 goto skip_phy_reset;
13150 err = tg3_phy_reset(tp);
13154 tg3_phy_set_wirespeed(tp);
13156 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13157 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13158 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
13159 if (!tg3_copper_is_advertising_all(tp, mask)) {
13160 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
13161 tp->link_config.flowctrl);
13163 tg3_writephy(tp, MII_BMCR,
13164 BMCR_ANENABLE | BMCR_ANRESTART);
13169 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
13170 err = tg3_init_5401phy_dsp(tp);
13174 err = tg3_init_5401phy_dsp(tp);
13180 static void __devinit tg3_read_vpd(struct tg3 *tp)
13183 unsigned int block_end, rosize, len;
13186 vpd_data = (u8 *)tg3_vpd_readblock(tp);
13190 i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
13191 PCI_VPD_LRDT_RO_DATA);
13193 goto out_not_found;
13195 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
13196 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
13197 i += PCI_VPD_LRDT_TAG_SIZE;
13199 if (block_end > TG3_NVM_VPD_LEN)
13200 goto out_not_found;
13202 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13203 PCI_VPD_RO_KEYWORD_MFR_ID);
13205 len = pci_vpd_info_field_size(&vpd_data[j]);
13207 j += PCI_VPD_INFO_FLD_HDR_SIZE;
13208 if (j + len > block_end || len != 4 ||
13209 memcmp(&vpd_data[j], "1028", 4))
13212 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13213 PCI_VPD_RO_KEYWORD_VENDOR0);
13217 len = pci_vpd_info_field_size(&vpd_data[j]);
13219 j += PCI_VPD_INFO_FLD_HDR_SIZE;
13220 if (j + len > block_end)
13223 memcpy(tp->fw_ver, &vpd_data[j], len);
13224 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
13228 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13229 PCI_VPD_RO_KEYWORD_PARTNO);
13231 goto out_not_found;
13233 len = pci_vpd_info_field_size(&vpd_data[i]);
13235 i += PCI_VPD_INFO_FLD_HDR_SIZE;
13236 if (len > TG3_BPN_SIZE ||
13237 (len + i) > TG3_NVM_VPD_LEN)
13238 goto out_not_found;
13240 memcpy(tp->board_part_number, &vpd_data[i], len);
13244 if (tp->board_part_number[0])
13248 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13249 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717)
13250 strcpy(tp->board_part_number, "BCM5717");
13251 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
13252 strcpy(tp->board_part_number, "BCM5718");
13255 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
13256 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
13257 strcpy(tp->board_part_number, "BCM57780");
13258 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
13259 strcpy(tp->board_part_number, "BCM57760");
13260 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
13261 strcpy(tp->board_part_number, "BCM57790");
13262 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
13263 strcpy(tp->board_part_number, "BCM57788");
13266 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13267 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
13268 strcpy(tp->board_part_number, "BCM57761");
13269 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
13270 strcpy(tp->board_part_number, "BCM57765");
13271 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
13272 strcpy(tp->board_part_number, "BCM57781");
13273 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
13274 strcpy(tp->board_part_number, "BCM57785");
13275 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
13276 strcpy(tp->board_part_number, "BCM57791");
13277 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13278 strcpy(tp->board_part_number, "BCM57795");
13281 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13282 strcpy(tp->board_part_number, "BCM95906");
13285 strcpy(tp->board_part_number, "none");
13289 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
13293 if (tg3_nvram_read(tp, offset, &val) ||
13294 (val & 0xfc000000) != 0x0c000000 ||
13295 tg3_nvram_read(tp, offset + 4, &val) ||
13302 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
13304 u32 val, offset, start, ver_offset;
13306 bool newver = false;
13308 if (tg3_nvram_read(tp, 0xc, &offset) ||
13309 tg3_nvram_read(tp, 0x4, &start))
13312 offset = tg3_nvram_logical_addr(tp, offset);
13314 if (tg3_nvram_read(tp, offset, &val))
13317 if ((val & 0xfc000000) == 0x0c000000) {
13318 if (tg3_nvram_read(tp, offset + 4, &val))
13325 dst_off = strlen(tp->fw_ver);
13328 if (TG3_VER_SIZE - dst_off < 16 ||
13329 tg3_nvram_read(tp, offset + 8, &ver_offset))
13332 offset = offset + ver_offset - start;
13333 for (i = 0; i < 16; i += 4) {
13335 if (tg3_nvram_read_be32(tp, offset + i, &v))
13338 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
13343 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
13346 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
13347 TG3_NVM_BCVER_MAJSFT;
13348 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
13349 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
13350 "v%d.%02d", major, minor);
13354 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
13356 u32 val, major, minor;
13358 /* Use native endian representation */
13359 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
13362 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
13363 TG3_NVM_HWSB_CFG1_MAJSFT;
13364 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
13365 TG3_NVM_HWSB_CFG1_MINSFT;
13367 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
13370 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
13372 u32 offset, major, minor, build;
13374 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
13376 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
13379 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
13380 case TG3_EEPROM_SB_REVISION_0:
13381 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
13383 case TG3_EEPROM_SB_REVISION_2:
13384 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
13386 case TG3_EEPROM_SB_REVISION_3:
13387 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
13389 case TG3_EEPROM_SB_REVISION_4:
13390 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
13392 case TG3_EEPROM_SB_REVISION_5:
13393 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
13395 case TG3_EEPROM_SB_REVISION_6:
13396 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
13402 if (tg3_nvram_read(tp, offset, &val))
13405 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
13406 TG3_EEPROM_SB_EDH_BLD_SHFT;
13407 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
13408 TG3_EEPROM_SB_EDH_MAJ_SHFT;
13409 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
13411 if (minor > 99 || build > 26)
13414 offset = strlen(tp->fw_ver);
13415 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
13416 " v%d.%02d", major, minor);
13419 offset = strlen(tp->fw_ver);
13420 if (offset < TG3_VER_SIZE - 1)
13421 tp->fw_ver[offset] = 'a' + build - 1;
13425 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
13427 u32 val, offset, start;
13430 for (offset = TG3_NVM_DIR_START;
13431 offset < TG3_NVM_DIR_END;
13432 offset += TG3_NVM_DIRENT_SIZE) {
13433 if (tg3_nvram_read(tp, offset, &val))
13436 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
13440 if (offset == TG3_NVM_DIR_END)
13443 if (!tg3_flag(tp, 5705_PLUS))
13444 start = 0x08000000;
13445 else if (tg3_nvram_read(tp, offset - 4, &start))
13448 if (tg3_nvram_read(tp, offset + 4, &offset) ||
13449 !tg3_fw_img_is_valid(tp, offset) ||
13450 tg3_nvram_read(tp, offset + 8, &val))
13453 offset += val - start;
13455 vlen = strlen(tp->fw_ver);
13457 tp->fw_ver[vlen++] = ',';
13458 tp->fw_ver[vlen++] = ' ';
13460 for (i = 0; i < 4; i++) {
13462 if (tg3_nvram_read_be32(tp, offset, &v))
13465 offset += sizeof(v);
13467 if (vlen > TG3_VER_SIZE - sizeof(v)) {
13468 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
13472 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
13477 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
13483 if (!tg3_flag(tp, ENABLE_APE) || !tg3_flag(tp, ENABLE_ASF))
13486 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
13487 if (apedata != APE_SEG_SIG_MAGIC)
13490 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
13491 if (!(apedata & APE_FW_STATUS_READY))
13494 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
13496 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
13497 tg3_flag_set(tp, APE_HAS_NCSI);
13503 vlen = strlen(tp->fw_ver);
13505 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
13507 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
13508 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
13509 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
13510 (apedata & APE_FW_VERSION_BLDMSK));
13513 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
13516 bool vpd_vers = false;
13518 if (tp->fw_ver[0] != 0)
13521 if (tg3_flag(tp, NO_NVRAM)) {
13522 strcat(tp->fw_ver, "sb");
13526 if (tg3_nvram_read(tp, 0, &val))
13529 if (val == TG3_EEPROM_MAGIC)
13530 tg3_read_bc_ver(tp);
13531 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
13532 tg3_read_sb_ver(tp, val);
13533 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
13534 tg3_read_hwsb_ver(tp);
13541 if (tg3_flag(tp, ENABLE_APE)) {
13542 if (tg3_flag(tp, ENABLE_ASF))
13543 tg3_read_dash_ver(tp);
13544 } else if (tg3_flag(tp, ENABLE_ASF)) {
13545 tg3_read_mgmtfw_ver(tp);
13549 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
13552 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
13554 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
13556 if (tg3_flag(tp, LRG_PROD_RING_CAP))
13557 return TG3_RX_RET_MAX_SIZE_5717;
13558 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
13559 return TG3_RX_RET_MAX_SIZE_5700;
13561 return TG3_RX_RET_MAX_SIZE_5705;
13564 static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
13565 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
13566 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
13567 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
13571 static int __devinit tg3_get_invariants(struct tg3 *tp)
13574 u32 pci_state_reg, grc_misc_cfg;
13579 /* Force memory write invalidate off. If we leave it on,
13580 * then on 5700_BX chips we have to enable a workaround.
13581 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
13582 * to match the cacheline size. The Broadcom driver have this
13583 * workaround but turns MWI off all the times so never uses
13584 * it. This seems to suggest that the workaround is insufficient.
13586 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13587 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
13588 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13590 /* Important! -- Make sure register accesses are byteswapped
13591 * correctly. Also, for those chips that require it, make
13592 * sure that indirect register accesses are enabled before
13593 * the first operation.
13595 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13597 tp->misc_host_ctrl |= (misc_ctrl_reg &
13598 MISC_HOST_CTRL_CHIPREV);
13599 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13600 tp->misc_host_ctrl);
13602 tp->pci_chip_rev_id = (misc_ctrl_reg >>
13603 MISC_HOST_CTRL_CHIPREV_SHIFT);
13604 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
13605 u32 prod_id_asic_rev;
13607 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
13608 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
13609 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
13610 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720)
13611 pci_read_config_dword(tp->pdev,
13612 TG3PCI_GEN2_PRODID_ASICREV,
13613 &prod_id_asic_rev);
13614 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
13615 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
13616 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
13617 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
13618 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13619 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13620 pci_read_config_dword(tp->pdev,
13621 TG3PCI_GEN15_PRODID_ASICREV,
13622 &prod_id_asic_rev);
13624 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
13625 &prod_id_asic_rev);
13627 tp->pci_chip_rev_id = prod_id_asic_rev;
13630 /* Wrong chip ID in 5752 A0. This code can be removed later
13631 * as A0 is not in production.
13633 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
13634 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
13636 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
13637 * we need to disable memory and use config. cycles
13638 * only to access all registers. The 5702/03 chips
13639 * can mistakenly decode the special cycles from the
13640 * ICH chipsets as memory write cycles, causing corruption
13641 * of register and memory space. Only certain ICH bridges
13642 * will drive special cycles with non-zero data during the
13643 * address phase which can fall within the 5703's address
13644 * range. This is not an ICH bug as the PCI spec allows
13645 * non-zero address during special cycles. However, only
13646 * these ICH bridges are known to drive non-zero addresses
13647 * during special cycles.
13649 * Since special cycles do not cross PCI bridges, we only
13650 * enable this workaround if the 5703 is on the secondary
13651 * bus of these ICH bridges.
13653 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
13654 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
13655 static struct tg3_dev_id {
13659 } ich_chipsets[] = {
13660 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
13662 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
13664 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
13666 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
13670 struct tg3_dev_id *pci_id = &ich_chipsets[0];
13671 struct pci_dev *bridge = NULL;
13673 while (pci_id->vendor != 0) {
13674 bridge = pci_get_device(pci_id->vendor, pci_id->device,
13680 if (pci_id->rev != PCI_ANY_ID) {
13681 if (bridge->revision > pci_id->rev)
13684 if (bridge->subordinate &&
13685 (bridge->subordinate->number ==
13686 tp->pdev->bus->number)) {
13687 tg3_flag_set(tp, ICH_WORKAROUND);
13688 pci_dev_put(bridge);
13694 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13695 static struct tg3_dev_id {
13698 } bridge_chipsets[] = {
13699 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
13700 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
13703 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
13704 struct pci_dev *bridge = NULL;
13706 while (pci_id->vendor != 0) {
13707 bridge = pci_get_device(pci_id->vendor,
13714 if (bridge->subordinate &&
13715 (bridge->subordinate->number <=
13716 tp->pdev->bus->number) &&
13717 (bridge->subordinate->subordinate >=
13718 tp->pdev->bus->number)) {
13719 tg3_flag_set(tp, 5701_DMA_BUG);
13720 pci_dev_put(bridge);
13726 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13727 * DMA addresses > 40-bit. This bridge may have other additional
13728 * 57xx devices behind it in some 4-port NIC designs for example.
13729 * Any tg3 device found behind the bridge will also need the 40-bit
13732 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13733 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13734 tg3_flag_set(tp, 5780_CLASS);
13735 tg3_flag_set(tp, 40BIT_DMA_BUG);
13736 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13738 struct pci_dev *bridge = NULL;
13741 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13742 PCI_DEVICE_ID_SERVERWORKS_EPB,
13744 if (bridge && bridge->subordinate &&
13745 (bridge->subordinate->number <=
13746 tp->pdev->bus->number) &&
13747 (bridge->subordinate->subordinate >=
13748 tp->pdev->bus->number)) {
13749 tg3_flag_set(tp, 40BIT_DMA_BUG);
13750 pci_dev_put(bridge);
13756 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13757 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)
13758 tp->pdev_peer = tg3_find_peer(tp);
13760 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13761 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13762 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
13763 tg3_flag_set(tp, 5717_PLUS);
13765 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 ||
13766 tg3_flag(tp, 5717_PLUS))
13767 tg3_flag_set(tp, 57765_PLUS);
13769 /* Intentionally exclude ASIC_REV_5906 */
13770 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13771 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13772 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13773 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13774 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13775 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13776 tg3_flag(tp, 57765_PLUS))
13777 tg3_flag_set(tp, 5755_PLUS);
13779 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13780 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13781 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13782 tg3_flag(tp, 5755_PLUS) ||
13783 tg3_flag(tp, 5780_CLASS))
13784 tg3_flag_set(tp, 5750_PLUS);
13786 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13787 tg3_flag(tp, 5750_PLUS))
13788 tg3_flag_set(tp, 5705_PLUS);
13790 /* Determine TSO capabilities */
13791 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
13792 ; /* Do nothing. HW bug. */
13793 else if (tg3_flag(tp, 57765_PLUS))
13794 tg3_flag_set(tp, HW_TSO_3);
13795 else if (tg3_flag(tp, 5755_PLUS) ||
13796 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13797 tg3_flag_set(tp, HW_TSO_2);
13798 else if (tg3_flag(tp, 5750_PLUS)) {
13799 tg3_flag_set(tp, HW_TSO_1);
13800 tg3_flag_set(tp, TSO_BUG);
13801 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13802 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13803 tg3_flag_clear(tp, TSO_BUG);
13804 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13805 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13806 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13807 tg3_flag_set(tp, TSO_BUG);
13808 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13809 tp->fw_needed = FIRMWARE_TG3TSO5;
13811 tp->fw_needed = FIRMWARE_TG3TSO;
13814 /* Selectively allow TSO based on operating conditions */
13815 if (tg3_flag(tp, HW_TSO_1) ||
13816 tg3_flag(tp, HW_TSO_2) ||
13817 tg3_flag(tp, HW_TSO_3) ||
13818 (tp->fw_needed && !tg3_flag(tp, ENABLE_ASF)))
13819 tg3_flag_set(tp, TSO_CAPABLE);
13821 tg3_flag_clear(tp, TSO_CAPABLE);
13822 tg3_flag_clear(tp, TSO_BUG);
13823 tp->fw_needed = NULL;
13826 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
13827 tp->fw_needed = FIRMWARE_TG3;
13831 if (tg3_flag(tp, 5750_PLUS)) {
13832 tg3_flag_set(tp, SUPPORT_MSI);
13833 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13834 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13835 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13836 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13837 tp->pdev_peer == tp->pdev))
13838 tg3_flag_clear(tp, SUPPORT_MSI);
13840 if (tg3_flag(tp, 5755_PLUS) ||
13841 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13842 tg3_flag_set(tp, 1SHOT_MSI);
13845 if (tg3_flag(tp, 57765_PLUS)) {
13846 tg3_flag_set(tp, SUPPORT_MSIX);
13847 tp->irq_max = TG3_IRQ_MAX_VECS;
13851 if (tg3_flag(tp, 5755_PLUS))
13852 tg3_flag_set(tp, SHORT_DMA_BUG);
13854 if (tg3_flag(tp, 5717_PLUS))
13855 tg3_flag_set(tp, LRG_PROD_RING_CAP);
13857 if (tg3_flag(tp, 57765_PLUS) &&
13858 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
13859 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
13861 if (!tg3_flag(tp, 5705_PLUS) ||
13862 tg3_flag(tp, 5780_CLASS) ||
13863 tg3_flag(tp, USE_JUMBO_BDFLAG))
13864 tg3_flag_set(tp, JUMBO_CAPABLE);
13866 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13869 if (pci_is_pcie(tp->pdev)) {
13872 tg3_flag_set(tp, PCI_EXPRESS);
13874 tp->pcie_readrq = 4096;
13875 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13876 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
13877 tp->pcie_readrq = 2048;
13879 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
13881 pci_read_config_word(tp->pdev,
13882 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
13884 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13885 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
13887 tg3_flag_clear(tp, HW_TSO_2);
13888 tg3_flag_clear(tp, TSO_CAPABLE);
13890 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13891 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13892 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13893 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13894 tg3_flag_set(tp, CLKREQ_BUG);
13895 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13896 tg3_flag_set(tp, L1PLLPD_EN);
13898 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13899 /* BCM5785 devices are effectively PCIe devices, and should
13900 * follow PCIe codepaths, but do not have a PCIe capabilities
13903 tg3_flag_set(tp, PCI_EXPRESS);
13904 } else if (!tg3_flag(tp, 5705_PLUS) ||
13905 tg3_flag(tp, 5780_CLASS)) {
13906 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13907 if (!tp->pcix_cap) {
13908 dev_err(&tp->pdev->dev,
13909 "Cannot find PCI-X capability, aborting\n");
13913 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13914 tg3_flag_set(tp, PCIX_MODE);
13917 /* If we have an AMD 762 or VIA K8T800 chipset, write
13918 * reordering to the mailbox registers done by the host
13919 * controller can cause major troubles. We read back from
13920 * every mailbox register write to force the writes to be
13921 * posted to the chip in order.
13923 if (pci_dev_present(tg3_write_reorder_chipsets) &&
13924 !tg3_flag(tp, PCI_EXPRESS))
13925 tg3_flag_set(tp, MBOX_WRITE_REORDER);
13927 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13928 &tp->pci_cacheline_sz);
13929 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13930 &tp->pci_lat_timer);
13931 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13932 tp->pci_lat_timer < 64) {
13933 tp->pci_lat_timer = 64;
13934 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13935 tp->pci_lat_timer);
13938 /* Important! -- It is critical that the PCI-X hw workaround
13939 * situation is decided before the first MMIO register access.
13941 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13942 /* 5700 BX chips need to have their TX producer index
13943 * mailboxes written twice to workaround a bug.
13945 tg3_flag_set(tp, TXD_MBOX_HWBUG);
13947 /* If we are in PCI-X mode, enable register write workaround.
13949 * The workaround is to use indirect register accesses
13950 * for all chip writes not to mailbox registers.
13952 if (tg3_flag(tp, PCIX_MODE)) {
13955 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
13957 /* The chip can have it's power management PCI config
13958 * space registers clobbered due to this bug.
13959 * So explicitly force the chip into D0 here.
13961 pci_read_config_dword(tp->pdev,
13962 tp->pm_cap + PCI_PM_CTRL,
13964 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13965 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13966 pci_write_config_dword(tp->pdev,
13967 tp->pm_cap + PCI_PM_CTRL,
13970 /* Also, force SERR#/PERR# in PCI command. */
13971 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13972 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13973 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13977 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13978 tg3_flag_set(tp, PCI_HIGH_SPEED);
13979 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13980 tg3_flag_set(tp, PCI_32BIT);
13982 /* Chip-specific fixup from Broadcom driver */
13983 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13984 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13985 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13986 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13989 /* Default fast path register access methods */
13990 tp->read32 = tg3_read32;
13991 tp->write32 = tg3_write32;
13992 tp->read32_mbox = tg3_read32;
13993 tp->write32_mbox = tg3_write32;
13994 tp->write32_tx_mbox = tg3_write32;
13995 tp->write32_rx_mbox = tg3_write32;
13997 /* Various workaround register access methods */
13998 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
13999 tp->write32 = tg3_write_indirect_reg32;
14000 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
14001 (tg3_flag(tp, PCI_EXPRESS) &&
14002 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
14004 * Back to back register writes can cause problems on these
14005 * chips, the workaround is to read back all reg writes
14006 * except those to mailbox regs.
14008 * See tg3_write_indirect_reg32().
14010 tp->write32 = tg3_write_flush_reg32;
14013 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
14014 tp->write32_tx_mbox = tg3_write32_tx_mbox;
14015 if (tg3_flag(tp, MBOX_WRITE_REORDER))
14016 tp->write32_rx_mbox = tg3_write_flush_reg32;
14019 if (tg3_flag(tp, ICH_WORKAROUND)) {
14020 tp->read32 = tg3_read_indirect_reg32;
14021 tp->write32 = tg3_write_indirect_reg32;
14022 tp->read32_mbox = tg3_read_indirect_mbox;
14023 tp->write32_mbox = tg3_write_indirect_mbox;
14024 tp->write32_tx_mbox = tg3_write_indirect_mbox;
14025 tp->write32_rx_mbox = tg3_write_indirect_mbox;
14030 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
14031 pci_cmd &= ~PCI_COMMAND_MEMORY;
14032 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
14034 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14035 tp->read32_mbox = tg3_read32_mbox_5906;
14036 tp->write32_mbox = tg3_write32_mbox_5906;
14037 tp->write32_tx_mbox = tg3_write32_mbox_5906;
14038 tp->write32_rx_mbox = tg3_write32_mbox_5906;
14041 if (tp->write32 == tg3_write_indirect_reg32 ||
14042 (tg3_flag(tp, PCIX_MODE) &&
14043 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14044 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
14045 tg3_flag_set(tp, SRAM_USE_CONFIG);
14047 /* The memory arbiter has to be enabled in order for SRAM accesses
14048 * to succeed. Normally on powerup the tg3 chip firmware will make
14049 * sure it is enabled, but other entities such as system netboot
14050 * code might disable it.
14052 val = tr32(MEMARB_MODE);
14053 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
14055 if (tg3_flag(tp, PCIX_MODE)) {
14056 pci_read_config_dword(tp->pdev,
14057 tp->pcix_cap + PCI_X_STATUS, &val);
14058 tp->pci_fn = val & 0x7;
14060 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
14063 /* Get eeprom hw config before calling tg3_set_power_state().
14064 * In particular, the TG3_FLAG_IS_NIC flag must be
14065 * determined before calling tg3_set_power_state() so that
14066 * we know whether or not to switch out of Vaux power.
14067 * When the flag is set, it means that GPIO1 is used for eeprom
14068 * write protect and also implies that it is a LOM where GPIOs
14069 * are not used to switch power.
14071 tg3_get_eeprom_hw_cfg(tp);
14073 if (tg3_flag(tp, ENABLE_APE)) {
14074 /* Allow reads and writes to the
14075 * APE register and memory space.
14077 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
14078 PCISTATE_ALLOW_APE_SHMEM_WR |
14079 PCISTATE_ALLOW_APE_PSPACE_WR;
14080 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
14083 tg3_ape_lock_init(tp);
14086 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
14087 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14088 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14089 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14090 tg3_flag(tp, 57765_PLUS))
14091 tg3_flag_set(tp, CPMU_PRESENT);
14093 /* Set up tp->grc_local_ctrl before calling
14094 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
14095 * will bring 5700's external PHY out of reset.
14096 * It is also used as eeprom write protect on LOMs.
14098 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
14099 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14100 tg3_flag(tp, EEPROM_WRITE_PROT))
14101 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
14102 GRC_LCLCTRL_GPIO_OUTPUT1);
14103 /* Unused GPIO3 must be driven as output on 5752 because there
14104 * are no pull-up resistors on unused GPIO pins.
14106 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
14107 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
14109 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
14110 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14111 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
14112 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
14114 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
14115 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
14116 /* Turn off the debug UART. */
14117 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
14118 if (tg3_flag(tp, IS_NIC))
14119 /* Keep VMain power. */
14120 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
14121 GRC_LCLCTRL_GPIO_OUTPUT0;
14124 /* Switch out of Vaux if it is a NIC */
14125 tg3_pwrsrc_switch_to_vmain(tp);
14127 /* Derive initial jumbo mode from MTU assigned in
14128 * ether_setup() via the alloc_etherdev() call
14130 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
14131 tg3_flag_set(tp, JUMBO_RING_ENABLE);
14133 /* Determine WakeOnLan speed to use. */
14134 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14135 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
14136 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
14137 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
14138 tg3_flag_clear(tp, WOL_SPEED_100MB);
14140 tg3_flag_set(tp, WOL_SPEED_100MB);
14143 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
14144 tp->phy_flags |= TG3_PHYFLG_IS_FET;
14146 /* A few boards don't want Ethernet@WireSpeed phy feature */
14147 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14148 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14149 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
14150 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
14151 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
14152 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
14153 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
14155 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
14156 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
14157 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
14158 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
14159 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
14161 if (tg3_flag(tp, 5705_PLUS) &&
14162 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
14163 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
14164 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
14165 !tg3_flag(tp, 57765_PLUS)) {
14166 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
14167 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
14168 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
14169 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
14170 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
14171 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
14172 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
14173 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
14174 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
14176 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
14179 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14180 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
14181 tp->phy_otp = tg3_read_otp_phycfg(tp);
14182 if (tp->phy_otp == 0)
14183 tp->phy_otp = TG3_OTP_DEFAULT;
14186 if (tg3_flag(tp, CPMU_PRESENT))
14187 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
14189 tp->mi_mode = MAC_MI_MODE_BASE;
14191 tp->coalesce_mode = 0;
14192 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
14193 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
14194 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
14196 /* Set these bits to enable statistics workaround. */
14197 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14198 tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
14199 tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) {
14200 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
14201 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
14204 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14205 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
14206 tg3_flag_set(tp, USE_PHYLIB);
14208 err = tg3_mdio_init(tp);
14212 /* Initialize data/descriptor byte/word swapping. */
14213 val = tr32(GRC_MODE);
14214 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
14215 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
14216 GRC_MODE_WORD_SWAP_B2HRX_DATA |
14217 GRC_MODE_B2HRX_ENABLE |
14218 GRC_MODE_HTX2B_ENABLE |
14219 GRC_MODE_HOST_STACKUP);
14221 val &= GRC_MODE_HOST_STACKUP;
14223 tw32(GRC_MODE, val | tp->grc_mode);
14225 tg3_switch_clocks(tp);
14227 /* Clear this out for sanity. */
14228 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
14230 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
14232 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
14233 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
14234 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
14236 if (chiprevid == CHIPREV_ID_5701_A0 ||
14237 chiprevid == CHIPREV_ID_5701_B0 ||
14238 chiprevid == CHIPREV_ID_5701_B2 ||
14239 chiprevid == CHIPREV_ID_5701_B5) {
14240 void __iomem *sram_base;
14242 /* Write some dummy words into the SRAM status block
14243 * area, see if it reads back correctly. If the return
14244 * value is bad, force enable the PCIX workaround.
14246 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
14248 writel(0x00000000, sram_base);
14249 writel(0x00000000, sram_base + 4);
14250 writel(0xffffffff, sram_base + 4);
14251 if (readl(sram_base) != 0x00000000)
14252 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
14257 tg3_nvram_init(tp);
14259 grc_misc_cfg = tr32(GRC_MISC_CFG);
14260 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
14262 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14263 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
14264 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
14265 tg3_flag_set(tp, IS_5788);
14267 if (!tg3_flag(tp, IS_5788) &&
14268 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
14269 tg3_flag_set(tp, TAGGED_STATUS);
14270 if (tg3_flag(tp, TAGGED_STATUS)) {
14271 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
14272 HOSTCC_MODE_CLRTICK_TXBD);
14274 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
14275 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
14276 tp->misc_host_ctrl);
14279 /* Preserve the APE MAC_MODE bits */
14280 if (tg3_flag(tp, ENABLE_APE))
14281 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
14283 tp->mac_mode = TG3_DEF_MAC_MODE;
14285 /* these are limited to 10/100 only */
14286 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
14287 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
14288 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14289 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
14290 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
14291 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
14292 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
14293 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
14294 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
14295 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
14296 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
14297 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
14298 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
14299 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
14300 (tp->phy_flags & TG3_PHYFLG_IS_FET))
14301 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
14303 err = tg3_phy_probe(tp);
14305 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
14306 /* ... but do not return immediately ... */
14311 tg3_read_fw_ver(tp);
14313 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
14314 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
14316 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
14317 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
14319 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
14322 /* 5700 {AX,BX} chips have a broken status block link
14323 * change bit implementation, so we must use the
14324 * status register in those cases.
14326 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
14327 tg3_flag_set(tp, USE_LINKCHG_REG);
14329 tg3_flag_clear(tp, USE_LINKCHG_REG);
14331 /* The led_ctrl is set during tg3_phy_probe, here we might
14332 * have to force the link status polling mechanism based
14333 * upon subsystem IDs.
14335 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
14336 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
14337 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
14338 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
14339 tg3_flag_set(tp, USE_LINKCHG_REG);
14342 /* For all SERDES we poll the MAC status register. */
14343 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
14344 tg3_flag_set(tp, POLL_SERDES);
14346 tg3_flag_clear(tp, POLL_SERDES);
14348 tp->rx_offset = NET_IP_ALIGN;
14349 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
14350 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
14351 tg3_flag(tp, PCIX_MODE)) {
14353 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
14354 tp->rx_copy_thresh = ~(u16)0;
14358 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
14359 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
14360 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
14362 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
14364 /* Increment the rx prod index on the rx std ring by at most
14365 * 8 for these chips to workaround hw errata.
14367 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
14368 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
14369 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
14370 tp->rx_std_max_post = 8;
14372 if (tg3_flag(tp, ASPM_WORKAROUND))
14373 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
14374 PCIE_PWR_MGMT_L1_THRESH_MSK;
14379 #ifdef CONFIG_SPARC
14380 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
14382 struct net_device *dev = tp->dev;
14383 struct pci_dev *pdev = tp->pdev;
14384 struct device_node *dp = pci_device_to_OF_node(pdev);
14385 const unsigned char *addr;
14388 addr = of_get_property(dp, "local-mac-address", &len);
14389 if (addr && len == 6) {
14390 memcpy(dev->dev_addr, addr, 6);
14391 memcpy(dev->perm_addr, dev->dev_addr, 6);
14397 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
14399 struct net_device *dev = tp->dev;
14401 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
14402 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
14407 static int __devinit tg3_get_device_address(struct tg3 *tp)
14409 struct net_device *dev = tp->dev;
14410 u32 hi, lo, mac_offset;
14413 #ifdef CONFIG_SPARC
14414 if (!tg3_get_macaddr_sparc(tp))
14419 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
14420 tg3_flag(tp, 5780_CLASS)) {
14421 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
14423 if (tg3_nvram_lock(tp))
14424 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
14426 tg3_nvram_unlock(tp);
14427 } else if (tg3_flag(tp, 5717_PLUS)) {
14428 if (tp->pci_fn & 1)
14430 if (tp->pci_fn > 1)
14431 mac_offset += 0x18c;
14432 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
14435 /* First try to get it from MAC address mailbox. */
14436 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
14437 if ((hi >> 16) == 0x484b) {
14438 dev->dev_addr[0] = (hi >> 8) & 0xff;
14439 dev->dev_addr[1] = (hi >> 0) & 0xff;
14441 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
14442 dev->dev_addr[2] = (lo >> 24) & 0xff;
14443 dev->dev_addr[3] = (lo >> 16) & 0xff;
14444 dev->dev_addr[4] = (lo >> 8) & 0xff;
14445 dev->dev_addr[5] = (lo >> 0) & 0xff;
14447 /* Some old bootcode may report a 0 MAC address in SRAM */
14448 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
14451 /* Next, try NVRAM. */
14452 if (!tg3_flag(tp, NO_NVRAM) &&
14453 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
14454 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
14455 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
14456 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
14458 /* Finally just fetch it out of the MAC control regs. */
14460 hi = tr32(MAC_ADDR_0_HIGH);
14461 lo = tr32(MAC_ADDR_0_LOW);
14463 dev->dev_addr[5] = lo & 0xff;
14464 dev->dev_addr[4] = (lo >> 8) & 0xff;
14465 dev->dev_addr[3] = (lo >> 16) & 0xff;
14466 dev->dev_addr[2] = (lo >> 24) & 0xff;
14467 dev->dev_addr[1] = hi & 0xff;
14468 dev->dev_addr[0] = (hi >> 8) & 0xff;
14472 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
14473 #ifdef CONFIG_SPARC
14474 if (!tg3_get_default_macaddr_sparc(tp))
14479 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
14483 #define BOUNDARY_SINGLE_CACHELINE 1
14484 #define BOUNDARY_MULTI_CACHELINE 2
14486 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
14488 int cacheline_size;
14492 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
14494 cacheline_size = 1024;
14496 cacheline_size = (int) byte * 4;
14498 /* On 5703 and later chips, the boundary bits have no
14501 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14502 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
14503 !tg3_flag(tp, PCI_EXPRESS))
14506 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
14507 goal = BOUNDARY_MULTI_CACHELINE;
14509 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
14510 goal = BOUNDARY_SINGLE_CACHELINE;
14516 if (tg3_flag(tp, 57765_PLUS)) {
14517 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
14524 /* PCI controllers on most RISC systems tend to disconnect
14525 * when a device tries to burst across a cache-line boundary.
14526 * Therefore, letting tg3 do so just wastes PCI bandwidth.
14528 * Unfortunately, for PCI-E there are only limited
14529 * write-side controls for this, and thus for reads
14530 * we will still get the disconnects. We'll also waste
14531 * these PCI cycles for both read and write for chips
14532 * other than 5700 and 5701 which do not implement the
14535 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
14536 switch (cacheline_size) {
14541 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14542 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
14543 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
14545 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14546 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14551 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
14552 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
14556 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14557 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14560 } else if (tg3_flag(tp, PCI_EXPRESS)) {
14561 switch (cacheline_size) {
14565 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14566 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14567 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
14573 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14574 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
14578 switch (cacheline_size) {
14580 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14581 val |= (DMA_RWCTRL_READ_BNDRY_16 |
14582 DMA_RWCTRL_WRITE_BNDRY_16);
14587 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14588 val |= (DMA_RWCTRL_READ_BNDRY_32 |
14589 DMA_RWCTRL_WRITE_BNDRY_32);
14594 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14595 val |= (DMA_RWCTRL_READ_BNDRY_64 |
14596 DMA_RWCTRL_WRITE_BNDRY_64);
14601 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14602 val |= (DMA_RWCTRL_READ_BNDRY_128 |
14603 DMA_RWCTRL_WRITE_BNDRY_128);
14608 val |= (DMA_RWCTRL_READ_BNDRY_256 |
14609 DMA_RWCTRL_WRITE_BNDRY_256);
14612 val |= (DMA_RWCTRL_READ_BNDRY_512 |
14613 DMA_RWCTRL_WRITE_BNDRY_512);
14617 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
14618 DMA_RWCTRL_WRITE_BNDRY_1024);
14627 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
14629 struct tg3_internal_buffer_desc test_desc;
14630 u32 sram_dma_descs;
14633 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
14635 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
14636 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
14637 tw32(RDMAC_STATUS, 0);
14638 tw32(WDMAC_STATUS, 0);
14640 tw32(BUFMGR_MODE, 0);
14641 tw32(FTQ_RESET, 0);
14643 test_desc.addr_hi = ((u64) buf_dma) >> 32;
14644 test_desc.addr_lo = buf_dma & 0xffffffff;
14645 test_desc.nic_mbuf = 0x00002100;
14646 test_desc.len = size;
14649 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
14650 * the *second* time the tg3 driver was getting loaded after an
14653 * Broadcom tells me:
14654 * ...the DMA engine is connected to the GRC block and a DMA
14655 * reset may affect the GRC block in some unpredictable way...
14656 * The behavior of resets to individual blocks has not been tested.
14658 * Broadcom noted the GRC reset will also reset all sub-components.
14661 test_desc.cqid_sqid = (13 << 8) | 2;
14663 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
14666 test_desc.cqid_sqid = (16 << 8) | 7;
14668 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
14671 test_desc.flags = 0x00000005;
14673 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
14676 val = *(((u32 *)&test_desc) + i);
14677 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
14678 sram_dma_descs + (i * sizeof(u32)));
14679 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
14681 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
14684 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
14686 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
14689 for (i = 0; i < 40; i++) {
14693 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
14695 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
14696 if ((val & 0xffff) == sram_dma_descs) {
14707 #define TEST_BUFFER_SIZE 0x2000
14709 static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
14710 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14714 static int __devinit tg3_test_dma(struct tg3 *tp)
14716 dma_addr_t buf_dma;
14717 u32 *buf, saved_dma_rwctrl;
14720 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
14721 &buf_dma, GFP_KERNEL);
14727 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
14728 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
14730 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
14732 if (tg3_flag(tp, 57765_PLUS))
14735 if (tg3_flag(tp, PCI_EXPRESS)) {
14736 /* DMA read watermark not used on PCIE */
14737 tp->dma_rwctrl |= 0x00180000;
14738 } else if (!tg3_flag(tp, PCIX_MODE)) {
14739 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14740 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
14741 tp->dma_rwctrl |= 0x003f0000;
14743 tp->dma_rwctrl |= 0x003f000f;
14745 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14746 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
14747 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
14748 u32 read_water = 0x7;
14750 /* If the 5704 is behind the EPB bridge, we can
14751 * do the less restrictive ONE_DMA workaround for
14752 * better performance.
14754 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
14755 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14756 tp->dma_rwctrl |= 0x8000;
14757 else if (ccval == 0x6 || ccval == 0x7)
14758 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
14760 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
14762 /* Set bit 23 to enable PCIX hw bug fix */
14764 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
14765 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
14767 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
14768 /* 5780 always in PCIX mode */
14769 tp->dma_rwctrl |= 0x00144000;
14770 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14771 /* 5714 always in PCIX mode */
14772 tp->dma_rwctrl |= 0x00148000;
14774 tp->dma_rwctrl |= 0x001b000f;
14778 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14779 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14780 tp->dma_rwctrl &= 0xfffffff0;
14782 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14783 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14784 /* Remove this if it causes problems for some boards. */
14785 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14787 /* On 5700/5701 chips, we need to set this bit.
14788 * Otherwise the chip will issue cacheline transactions
14789 * to streamable DMA memory with not all the byte
14790 * enables turned on. This is an error on several
14791 * RISC PCI controllers, in particular sparc64.
14793 * On 5703/5704 chips, this bit has been reassigned
14794 * a different meaning. In particular, it is used
14795 * on those chips to enable a PCI-X workaround.
14797 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14800 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14803 /* Unneeded, already done by tg3_get_invariants. */
14804 tg3_switch_clocks(tp);
14807 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14808 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14811 /* It is best to perform DMA test with maximum write burst size
14812 * to expose the 5700/5701 write DMA bug.
14814 saved_dma_rwctrl = tp->dma_rwctrl;
14815 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14816 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14821 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14824 /* Send the buffer to the chip. */
14825 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14827 dev_err(&tp->pdev->dev,
14828 "%s: Buffer write failed. err = %d\n",
14834 /* validate data reached card RAM correctly. */
14835 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14837 tg3_read_mem(tp, 0x2100 + (i*4), &val);
14838 if (le32_to_cpu(val) != p[i]) {
14839 dev_err(&tp->pdev->dev,
14840 "%s: Buffer corrupted on device! "
14841 "(%d != %d)\n", __func__, val, i);
14842 /* ret = -ENODEV here? */
14847 /* Now read it back. */
14848 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14850 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14851 "err = %d\n", __func__, ret);
14856 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14860 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14861 DMA_RWCTRL_WRITE_BNDRY_16) {
14862 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14863 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14864 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14867 dev_err(&tp->pdev->dev,
14868 "%s: Buffer corrupted on read back! "
14869 "(%d != %d)\n", __func__, p[i], i);
14875 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14881 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14882 DMA_RWCTRL_WRITE_BNDRY_16) {
14883 /* DMA test passed without adjusting DMA boundary,
14884 * now look for chipsets that are known to expose the
14885 * DMA bug without failing the test.
14887 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
14888 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14889 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14891 /* Safe to use the calculated DMA boundary. */
14892 tp->dma_rwctrl = saved_dma_rwctrl;
14895 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14899 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
14904 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14906 if (tg3_flag(tp, 57765_PLUS)) {
14907 tp->bufmgr_config.mbuf_read_dma_low_water =
14908 DEFAULT_MB_RDMA_LOW_WATER_5705;
14909 tp->bufmgr_config.mbuf_mac_rx_low_water =
14910 DEFAULT_MB_MACRX_LOW_WATER_57765;
14911 tp->bufmgr_config.mbuf_high_water =
14912 DEFAULT_MB_HIGH_WATER_57765;
14914 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14915 DEFAULT_MB_RDMA_LOW_WATER_5705;
14916 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14917 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14918 tp->bufmgr_config.mbuf_high_water_jumbo =
14919 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14920 } else if (tg3_flag(tp, 5705_PLUS)) {
14921 tp->bufmgr_config.mbuf_read_dma_low_water =
14922 DEFAULT_MB_RDMA_LOW_WATER_5705;
14923 tp->bufmgr_config.mbuf_mac_rx_low_water =
14924 DEFAULT_MB_MACRX_LOW_WATER_5705;
14925 tp->bufmgr_config.mbuf_high_water =
14926 DEFAULT_MB_HIGH_WATER_5705;
14927 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14928 tp->bufmgr_config.mbuf_mac_rx_low_water =
14929 DEFAULT_MB_MACRX_LOW_WATER_5906;
14930 tp->bufmgr_config.mbuf_high_water =
14931 DEFAULT_MB_HIGH_WATER_5906;
14934 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14935 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14936 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14937 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14938 tp->bufmgr_config.mbuf_high_water_jumbo =
14939 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14941 tp->bufmgr_config.mbuf_read_dma_low_water =
14942 DEFAULT_MB_RDMA_LOW_WATER;
14943 tp->bufmgr_config.mbuf_mac_rx_low_water =
14944 DEFAULT_MB_MACRX_LOW_WATER;
14945 tp->bufmgr_config.mbuf_high_water =
14946 DEFAULT_MB_HIGH_WATER;
14948 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14949 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14950 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14951 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14952 tp->bufmgr_config.mbuf_high_water_jumbo =
14953 DEFAULT_MB_HIGH_WATER_JUMBO;
14956 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14957 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14960 static char * __devinit tg3_phy_string(struct tg3 *tp)
14962 switch (tp->phy_id & TG3_PHY_ID_MASK) {
14963 case TG3_PHY_ID_BCM5400: return "5400";
14964 case TG3_PHY_ID_BCM5401: return "5401";
14965 case TG3_PHY_ID_BCM5411: return "5411";
14966 case TG3_PHY_ID_BCM5701: return "5701";
14967 case TG3_PHY_ID_BCM5703: return "5703";
14968 case TG3_PHY_ID_BCM5704: return "5704";
14969 case TG3_PHY_ID_BCM5705: return "5705";
14970 case TG3_PHY_ID_BCM5750: return "5750";
14971 case TG3_PHY_ID_BCM5752: return "5752";
14972 case TG3_PHY_ID_BCM5714: return "5714";
14973 case TG3_PHY_ID_BCM5780: return "5780";
14974 case TG3_PHY_ID_BCM5755: return "5755";
14975 case TG3_PHY_ID_BCM5787: return "5787";
14976 case TG3_PHY_ID_BCM5784: return "5784";
14977 case TG3_PHY_ID_BCM5756: return "5722/5756";
14978 case TG3_PHY_ID_BCM5906: return "5906";
14979 case TG3_PHY_ID_BCM5761: return "5761";
14980 case TG3_PHY_ID_BCM5718C: return "5718C";
14981 case TG3_PHY_ID_BCM5718S: return "5718S";
14982 case TG3_PHY_ID_BCM57765: return "57765";
14983 case TG3_PHY_ID_BCM5719C: return "5719C";
14984 case TG3_PHY_ID_BCM5720C: return "5720C";
14985 case TG3_PHY_ID_BCM8002: return "8002/serdes";
14986 case 0: return "serdes";
14987 default: return "unknown";
14991 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14993 if (tg3_flag(tp, PCI_EXPRESS)) {
14994 strcpy(str, "PCI Express");
14996 } else if (tg3_flag(tp, PCIX_MODE)) {
14997 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14999 strcpy(str, "PCIX:");
15001 if ((clock_ctrl == 7) ||
15002 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
15003 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
15004 strcat(str, "133MHz");
15005 else if (clock_ctrl == 0)
15006 strcat(str, "33MHz");
15007 else if (clock_ctrl == 2)
15008 strcat(str, "50MHz");
15009 else if (clock_ctrl == 4)
15010 strcat(str, "66MHz");
15011 else if (clock_ctrl == 6)
15012 strcat(str, "100MHz");
15014 strcpy(str, "PCI:");
15015 if (tg3_flag(tp, PCI_HIGH_SPEED))
15016 strcat(str, "66MHz");
15018 strcat(str, "33MHz");
15020 if (tg3_flag(tp, PCI_32BIT))
15021 strcat(str, ":32-bit");
15023 strcat(str, ":64-bit");
15027 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
15029 struct pci_dev *peer;
15030 unsigned int func, devnr = tp->pdev->devfn & ~7;
15032 for (func = 0; func < 8; func++) {
15033 peer = pci_get_slot(tp->pdev->bus, devnr | func);
15034 if (peer && peer != tp->pdev)
15038 /* 5704 can be configured in single-port mode, set peer to
15039 * tp->pdev in that case.
15047 * We don't need to keep the refcount elevated; there's no way
15048 * to remove one half of this device without removing the other
15055 static void __devinit tg3_init_coal(struct tg3 *tp)
15057 struct ethtool_coalesce *ec = &tp->coal;
15059 memset(ec, 0, sizeof(*ec));
15060 ec->cmd = ETHTOOL_GCOALESCE;
15061 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
15062 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
15063 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
15064 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
15065 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
15066 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
15067 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
15068 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
15069 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
15071 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
15072 HOSTCC_MODE_CLRTICK_TXBD)) {
15073 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
15074 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
15075 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
15076 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
15079 if (tg3_flag(tp, 5705_PLUS)) {
15080 ec->rx_coalesce_usecs_irq = 0;
15081 ec->tx_coalesce_usecs_irq = 0;
15082 ec->stats_block_coalesce_usecs = 0;
15086 static const struct net_device_ops tg3_netdev_ops = {
15087 .ndo_open = tg3_open,
15088 .ndo_stop = tg3_close,
15089 .ndo_start_xmit = tg3_start_xmit,
15090 .ndo_get_stats64 = tg3_get_stats64,
15091 .ndo_validate_addr = eth_validate_addr,
15092 .ndo_set_multicast_list = tg3_set_rx_mode,
15093 .ndo_set_mac_address = tg3_set_mac_addr,
15094 .ndo_do_ioctl = tg3_ioctl,
15095 .ndo_tx_timeout = tg3_tx_timeout,
15096 .ndo_change_mtu = tg3_change_mtu,
15097 .ndo_fix_features = tg3_fix_features,
15098 .ndo_set_features = tg3_set_features,
15099 #ifdef CONFIG_NET_POLL_CONTROLLER
15100 .ndo_poll_controller = tg3_poll_controller,
15104 static int __devinit tg3_init_one(struct pci_dev *pdev,
15105 const struct pci_device_id *ent)
15107 struct net_device *dev;
15109 int i, err, pm_cap;
15110 u32 sndmbx, rcvmbx, intmbx;
15112 u64 dma_mask, persist_dma_mask;
15115 printk_once(KERN_INFO "%s\n", version);
15117 err = pci_enable_device(pdev);
15119 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
15123 err = pci_request_regions(pdev, DRV_MODULE_NAME);
15125 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
15126 goto err_out_disable_pdev;
15129 pci_set_master(pdev);
15131 /* Find power-management capability. */
15132 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
15134 dev_err(&pdev->dev,
15135 "Cannot find Power Management capability, aborting\n");
15137 goto err_out_free_res;
15140 err = pci_set_power_state(pdev, PCI_D0);
15142 dev_err(&pdev->dev, "Transition to D0 failed, aborting\n");
15143 goto err_out_free_res;
15146 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
15148 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
15150 goto err_out_power_down;
15153 SET_NETDEV_DEV(dev, &pdev->dev);
15155 tp = netdev_priv(dev);
15158 tp->pm_cap = pm_cap;
15159 tp->rx_mode = TG3_DEF_RX_MODE;
15160 tp->tx_mode = TG3_DEF_TX_MODE;
15163 tp->msg_enable = tg3_debug;
15165 tp->msg_enable = TG3_DEF_MSG_ENABLE;
15167 /* The word/byte swap controls here control register access byte
15168 * swapping. DMA data byte swapping is controlled in the GRC_MODE
15171 tp->misc_host_ctrl =
15172 MISC_HOST_CTRL_MASK_PCI_INT |
15173 MISC_HOST_CTRL_WORD_SWAP |
15174 MISC_HOST_CTRL_INDIR_ACCESS |
15175 MISC_HOST_CTRL_PCISTATE_RW;
15177 /* The NONFRM (non-frame) byte/word swap controls take effect
15178 * on descriptor entries, anything which isn't packet data.
15180 * The StrongARM chips on the board (one for tx, one for rx)
15181 * are running in big-endian mode.
15183 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
15184 GRC_MODE_WSWAP_NONFRM_DATA);
15185 #ifdef __BIG_ENDIAN
15186 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
15188 spin_lock_init(&tp->lock);
15189 spin_lock_init(&tp->indirect_lock);
15190 INIT_WORK(&tp->reset_task, tg3_reset_task);
15192 tp->regs = pci_ioremap_bar(pdev, BAR_0);
15194 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
15196 goto err_out_free_dev;
15199 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
15200 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
15201 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
15202 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
15203 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15204 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
15205 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
15206 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720) {
15207 tg3_flag_set(tp, ENABLE_APE);
15208 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
15209 if (!tp->aperegs) {
15210 dev_err(&pdev->dev,
15211 "Cannot map APE registers, aborting\n");
15213 goto err_out_iounmap;
15217 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
15218 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
15220 dev->ethtool_ops = &tg3_ethtool_ops;
15221 dev->watchdog_timeo = TG3_TX_TIMEOUT;
15222 dev->netdev_ops = &tg3_netdev_ops;
15223 dev->irq = pdev->irq;
15225 err = tg3_get_invariants(tp);
15227 dev_err(&pdev->dev,
15228 "Problem fetching invariants of chip, aborting\n");
15229 goto err_out_apeunmap;
15232 /* The EPB bridge inside 5714, 5715, and 5780 and any
15233 * device behind the EPB cannot support DMA addresses > 40-bit.
15234 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
15235 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
15236 * do DMA address check in tg3_start_xmit().
15238 if (tg3_flag(tp, IS_5788))
15239 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
15240 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
15241 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
15242 #ifdef CONFIG_HIGHMEM
15243 dma_mask = DMA_BIT_MASK(64);
15246 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
15248 /* Configure DMA attributes. */
15249 if (dma_mask > DMA_BIT_MASK(32)) {
15250 err = pci_set_dma_mask(pdev, dma_mask);
15252 features |= NETIF_F_HIGHDMA;
15253 err = pci_set_consistent_dma_mask(pdev,
15256 dev_err(&pdev->dev, "Unable to obtain 64 bit "
15257 "DMA for consistent allocations\n");
15258 goto err_out_apeunmap;
15262 if (err || dma_mask == DMA_BIT_MASK(32)) {
15263 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
15265 dev_err(&pdev->dev,
15266 "No usable DMA configuration, aborting\n");
15267 goto err_out_apeunmap;
15271 tg3_init_bufmgr_config(tp);
15273 features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
15275 /* 5700 B0 chips do not support checksumming correctly due
15276 * to hardware bugs.
15278 if (tp->pci_chip_rev_id != CHIPREV_ID_5700_B0) {
15279 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
15281 if (tg3_flag(tp, 5755_PLUS))
15282 features |= NETIF_F_IPV6_CSUM;
15285 /* TSO is on by default on chips that support hardware TSO.
15286 * Firmware TSO on older chips gives lower performance, so it
15287 * is off by default, but can be enabled using ethtool.
15289 if ((tg3_flag(tp, HW_TSO_1) ||
15290 tg3_flag(tp, HW_TSO_2) ||
15291 tg3_flag(tp, HW_TSO_3)) &&
15292 (features & NETIF_F_IP_CSUM))
15293 features |= NETIF_F_TSO;
15294 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
15295 if (features & NETIF_F_IPV6_CSUM)
15296 features |= NETIF_F_TSO6;
15297 if (tg3_flag(tp, HW_TSO_3) ||
15298 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
15299 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
15300 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
15301 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
15302 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
15303 features |= NETIF_F_TSO_ECN;
15306 dev->features |= features;
15307 dev->vlan_features |= features;
15310 * Add loopback capability only for a subset of devices that support
15311 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
15312 * loopback for the remaining devices.
15314 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 &&
15315 !tg3_flag(tp, CPMU_PRESENT))
15316 /* Add the loopback capability */
15317 features |= NETIF_F_LOOPBACK;
15319 dev->hw_features |= features;
15321 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
15322 !tg3_flag(tp, TSO_CAPABLE) &&
15323 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
15324 tg3_flag_set(tp, MAX_RXPEND_64);
15325 tp->rx_pending = 63;
15328 err = tg3_get_device_address(tp);
15330 dev_err(&pdev->dev,
15331 "Could not obtain valid ethernet address, aborting\n");
15332 goto err_out_apeunmap;
15336 * Reset chip in case UNDI or EFI driver did not shutdown
15337 * DMA self test will enable WDMAC and we'll see (spurious)
15338 * pending DMA on the PCI bus at that point.
15340 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
15341 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
15342 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
15343 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15346 err = tg3_test_dma(tp);
15348 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
15349 goto err_out_apeunmap;
15352 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
15353 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
15354 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
15355 for (i = 0; i < tp->irq_max; i++) {
15356 struct tg3_napi *tnapi = &tp->napi[i];
15359 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
15361 tnapi->int_mbox = intmbx;
15367 tnapi->consmbox = rcvmbx;
15368 tnapi->prodmbox = sndmbx;
15371 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
15373 tnapi->coal_now = HOSTCC_MODE_NOW;
15375 if (!tg3_flag(tp, SUPPORT_MSIX))
15379 * If we support MSIX, we'll be using RSS. If we're using
15380 * RSS, the first vector only handles link interrupts and the
15381 * remaining vectors handle rx and tx interrupts. Reuse the
15382 * mailbox values for the next iteration. The values we setup
15383 * above are still useful for the single vectored mode.
15398 pci_set_drvdata(pdev, dev);
15400 if (tg3_flag(tp, 5717_PLUS)) {
15401 /* Resume a low-power mode */
15402 tg3_frob_aux_power(tp, false);
15405 err = register_netdev(dev);
15407 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
15408 goto err_out_apeunmap;
15411 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
15412 tp->board_part_number,
15413 tp->pci_chip_rev_id,
15414 tg3_bus_string(tp, str),
15417 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
15418 struct phy_device *phydev;
15419 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
15421 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
15422 phydev->drv->name, dev_name(&phydev->dev));
15426 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
15427 ethtype = "10/100Base-TX";
15428 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
15429 ethtype = "1000Base-SX";
15431 ethtype = "10/100/1000Base-T";
15433 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
15434 "(WireSpeed[%d], EEE[%d])\n",
15435 tg3_phy_string(tp), ethtype,
15436 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
15437 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
15440 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
15441 (dev->features & NETIF_F_RXCSUM) != 0,
15442 tg3_flag(tp, USE_LINKCHG_REG) != 0,
15443 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
15444 tg3_flag(tp, ENABLE_ASF) != 0,
15445 tg3_flag(tp, TSO_CAPABLE) != 0);
15446 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
15448 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
15449 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
15451 pci_save_state(pdev);
15457 iounmap(tp->aperegs);
15458 tp->aperegs = NULL;
15470 err_out_power_down:
15471 pci_set_power_state(pdev, PCI_D3hot);
15474 pci_release_regions(pdev);
15476 err_out_disable_pdev:
15477 pci_disable_device(pdev);
15478 pci_set_drvdata(pdev, NULL);
15482 static void __devexit tg3_remove_one(struct pci_dev *pdev)
15484 struct net_device *dev = pci_get_drvdata(pdev);
15487 struct tg3 *tp = netdev_priv(dev);
15490 release_firmware(tp->fw);
15492 cancel_work_sync(&tp->reset_task);
15494 if (!tg3_flag(tp, USE_PHYLIB)) {
15499 unregister_netdev(dev);
15501 iounmap(tp->aperegs);
15502 tp->aperegs = NULL;
15509 pci_release_regions(pdev);
15510 pci_disable_device(pdev);
15511 pci_set_drvdata(pdev, NULL);
15515 #ifdef CONFIG_PM_SLEEP
15516 static int tg3_suspend(struct device *device)
15518 struct pci_dev *pdev = to_pci_dev(device);
15519 struct net_device *dev = pci_get_drvdata(pdev);
15520 struct tg3 *tp = netdev_priv(dev);
15523 if (!netif_running(dev))
15526 flush_work_sync(&tp->reset_task);
15528 tg3_netif_stop(tp);
15530 del_timer_sync(&tp->timer);
15532 tg3_full_lock(tp, 1);
15533 tg3_disable_ints(tp);
15534 tg3_full_unlock(tp);
15536 netif_device_detach(dev);
15538 tg3_full_lock(tp, 0);
15539 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15540 tg3_flag_clear(tp, INIT_COMPLETE);
15541 tg3_full_unlock(tp);
15543 err = tg3_power_down_prepare(tp);
15547 tg3_full_lock(tp, 0);
15549 tg3_flag_set(tp, INIT_COMPLETE);
15550 err2 = tg3_restart_hw(tp, 1);
15554 tp->timer.expires = jiffies + tp->timer_offset;
15555 add_timer(&tp->timer);
15557 netif_device_attach(dev);
15558 tg3_netif_start(tp);
15561 tg3_full_unlock(tp);
15570 static int tg3_resume(struct device *device)
15572 struct pci_dev *pdev = to_pci_dev(device);
15573 struct net_device *dev = pci_get_drvdata(pdev);
15574 struct tg3 *tp = netdev_priv(dev);
15577 if (!netif_running(dev))
15580 netif_device_attach(dev);
15582 tg3_full_lock(tp, 0);
15584 tg3_flag_set(tp, INIT_COMPLETE);
15585 err = tg3_restart_hw(tp, 1);
15589 tp->timer.expires = jiffies + tp->timer_offset;
15590 add_timer(&tp->timer);
15592 tg3_netif_start(tp);
15595 tg3_full_unlock(tp);
15603 static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
15604 #define TG3_PM_OPS (&tg3_pm_ops)
15608 #define TG3_PM_OPS NULL
15610 #endif /* CONFIG_PM_SLEEP */
15613 * tg3_io_error_detected - called when PCI error is detected
15614 * @pdev: Pointer to PCI device
15615 * @state: The current pci connection state
15617 * This function is called after a PCI bus error affecting
15618 * this device has been detected.
15620 static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
15621 pci_channel_state_t state)
15623 struct net_device *netdev = pci_get_drvdata(pdev);
15624 struct tg3 *tp = netdev_priv(netdev);
15625 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
15627 netdev_info(netdev, "PCI I/O error detected\n");
15631 if (!netif_running(netdev))
15636 tg3_netif_stop(tp);
15638 del_timer_sync(&tp->timer);
15639 tg3_flag_clear(tp, RESTART_TIMER);
15641 /* Want to make sure that the reset task doesn't run */
15642 cancel_work_sync(&tp->reset_task);
15643 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
15644 tg3_flag_clear(tp, RESTART_TIMER);
15646 netif_device_detach(netdev);
15648 /* Clean up software state, even if MMIO is blocked */
15649 tg3_full_lock(tp, 0);
15650 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
15651 tg3_full_unlock(tp);
15654 if (state == pci_channel_io_perm_failure)
15655 err = PCI_ERS_RESULT_DISCONNECT;
15657 pci_disable_device(pdev);
15665 * tg3_io_slot_reset - called after the pci bus has been reset.
15666 * @pdev: Pointer to PCI device
15668 * Restart the card from scratch, as if from a cold-boot.
15669 * At this point, the card has exprienced a hard reset,
15670 * followed by fixups by BIOS, and has its config space
15671 * set up identically to what it was at cold boot.
15673 static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
15675 struct net_device *netdev = pci_get_drvdata(pdev);
15676 struct tg3 *tp = netdev_priv(netdev);
15677 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
15682 if (pci_enable_device(pdev)) {
15683 netdev_err(netdev, "Cannot re-enable PCI device after reset.\n");
15687 pci_set_master(pdev);
15688 pci_restore_state(pdev);
15689 pci_save_state(pdev);
15691 if (!netif_running(netdev)) {
15692 rc = PCI_ERS_RESULT_RECOVERED;
15696 err = tg3_power_up(tp);
15700 rc = PCI_ERS_RESULT_RECOVERED;
15709 * tg3_io_resume - called when traffic can start flowing again.
15710 * @pdev: Pointer to PCI device
15712 * This callback is called when the error recovery driver tells
15713 * us that its OK to resume normal operation.
15715 static void tg3_io_resume(struct pci_dev *pdev)
15717 struct net_device *netdev = pci_get_drvdata(pdev);
15718 struct tg3 *tp = netdev_priv(netdev);
15723 if (!netif_running(netdev))
15726 tg3_full_lock(tp, 0);
15727 tg3_flag_set(tp, INIT_COMPLETE);
15728 err = tg3_restart_hw(tp, 1);
15729 tg3_full_unlock(tp);
15731 netdev_err(netdev, "Cannot restart hardware after reset.\n");
15735 netif_device_attach(netdev);
15737 tp->timer.expires = jiffies + tp->timer_offset;
15738 add_timer(&tp->timer);
15740 tg3_netif_start(tp);
15748 static struct pci_error_handlers tg3_err_handler = {
15749 .error_detected = tg3_io_error_detected,
15750 .slot_reset = tg3_io_slot_reset,
15751 .resume = tg3_io_resume
15754 static struct pci_driver tg3_driver = {
15755 .name = DRV_MODULE_NAME,
15756 .id_table = tg3_pci_tbl,
15757 .probe = tg3_init_one,
15758 .remove = __devexit_p(tg3_remove_one),
15759 .err_handler = &tg3_err_handler,
15760 .driver.pm = TG3_PM_OPS,
15763 static int __init tg3_init(void)
15765 return pci_register_driver(&tg3_driver);
15768 static void __exit tg3_cleanup(void)
15770 pci_unregister_driver(&tg3_driver);
15773 module_init(tg3_init);
15774 module_exit(tg3_cleanup);