tg3: Fix 57765 EEE support
[linux-2.6.git] / drivers / net / tg3.c
1 /*
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  * Copyright (C) 2005-2010 Broadcom Corporation.
8  *
9  * Firmware is:
10  *      Derived from proprietary unpublished source code,
11  *      Copyright (C) 2000-2003 Broadcom Corporation.
12  *
13  *      Permission is hereby granted for the distribution of this firmware
14  *      data in hexadecimal or equivalent format, provided this copyright
15  *      notice is accompanying it.
16  */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/in.h>
28 #include <linux/init.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mdio.h>
36 #include <linux/mii.h>
37 #include <linux/phy.h>
38 #include <linux/brcmphy.h>
39 #include <linux/if_vlan.h>
40 #include <linux/ip.h>
41 #include <linux/tcp.h>
42 #include <linux/workqueue.h>
43 #include <linux/prefetch.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/firmware.h>
46
47 #include <net/checksum.h>
48 #include <net/ip.h>
49
50 #include <asm/system.h>
51 #include <asm/io.h>
52 #include <asm/byteorder.h>
53 #include <asm/uaccess.h>
54
55 #ifdef CONFIG_SPARC
56 #include <asm/idprom.h>
57 #include <asm/prom.h>
58 #endif
59
60 #define BAR_0   0
61 #define BAR_2   2
62
63 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
64 #define TG3_VLAN_TAG_USED 1
65 #else
66 #define TG3_VLAN_TAG_USED 0
67 #endif
68
69 #include "tg3.h"
70
71 #define DRV_MODULE_NAME         "tg3"
72 #define TG3_MAJ_NUM                     3
73 #define TG3_MIN_NUM                     115
74 #define DRV_MODULE_VERSION      \
75         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
76 #define DRV_MODULE_RELDATE      "October 14, 2010"
77
78 #define TG3_DEF_MAC_MODE        0
79 #define TG3_DEF_RX_MODE         0
80 #define TG3_DEF_TX_MODE         0
81 #define TG3_DEF_MSG_ENABLE        \
82         (NETIF_MSG_DRV          | \
83          NETIF_MSG_PROBE        | \
84          NETIF_MSG_LINK         | \
85          NETIF_MSG_TIMER        | \
86          NETIF_MSG_IFDOWN       | \
87          NETIF_MSG_IFUP         | \
88          NETIF_MSG_RX_ERR       | \
89          NETIF_MSG_TX_ERR)
90
91 /* length of time before we decide the hardware is borked,
92  * and dev->tx_timeout() should be called to fix the problem
93  */
94 #define TG3_TX_TIMEOUT                  (5 * HZ)
95
96 /* hardware minimum and maximum for a single frame's data payload */
97 #define TG3_MIN_MTU                     60
98 #define TG3_MAX_MTU(tp) \
99         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
100
101 /* These numbers seem to be hard coded in the NIC firmware somehow.
102  * You can't change the ring sizes, but you can change where you place
103  * them in the NIC onboard memory.
104  */
105 #define TG3_RX_STD_RING_SIZE(tp) \
106         ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
107           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
108          RX_STD_MAX_SIZE_5717 : 512)
109 #define TG3_DEF_RX_RING_PENDING         200
110 #define TG3_RX_JMB_RING_SIZE(tp) \
111         ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
112           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
113          1024 : 256)
114 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
115 #define TG3_RSS_INDIR_TBL_SIZE          128
116
117 /* Do not place this n-ring entries value into the tp struct itself,
118  * we really want to expose these constants to GCC so that modulo et
119  * al.  operations are done with shifts and masks instead of with
120  * hw multiply/modulo instructions.  Another solution would be to
121  * replace things like '% foo' with '& (foo - 1)'.
122  */
123
124 #define TG3_TX_RING_SIZE                512
125 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
126
127 #define TG3_RX_STD_RING_BYTES(tp) \
128         (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
129 #define TG3_RX_JMB_RING_BYTES(tp) \
130         (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
131 #define TG3_RX_RCB_RING_BYTES(tp) \
132         (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
133 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
134                                  TG3_TX_RING_SIZE)
135 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
136
137 #define TG3_RX_DMA_ALIGN                16
138 #define TG3_RX_HEADROOM                 ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
139
140 #define TG3_DMA_BYTE_ENAB               64
141
142 #define TG3_RX_STD_DMA_SZ               1536
143 #define TG3_RX_JMB_DMA_SZ               9046
144
145 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
146
147 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
148 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
149
150 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
151         (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
152
153 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
154         (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
155
156 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
157  * that are at least dword aligned when used in PCIX mode.  The driver
158  * works around this bug by double copying the packet.  This workaround
159  * is built into the normal double copy length check for efficiency.
160  *
161  * However, the double copy is only necessary on those architectures
162  * where unaligned memory accesses are inefficient.  For those architectures
163  * where unaligned memory accesses incur little penalty, we can reintegrate
164  * the 5701 in the normal rx path.  Doing so saves a device structure
165  * dereference by hardcoding the double copy threshold in place.
166  */
167 #define TG3_RX_COPY_THRESHOLD           256
168 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
169         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
170 #else
171         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
172 #endif
173
174 /* minimum number of free TX descriptors required to wake up TX process */
175 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
176
177 #define TG3_RAW_IP_ALIGN 2
178
179 /* number of ETHTOOL_GSTATS u64's */
180 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
181
182 #define TG3_NUM_TEST            6
183
184 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
185
186 #define FIRMWARE_TG3            "tigon/tg3.bin"
187 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
188 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
189
190 static char version[] __devinitdata =
191         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
192
193 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
194 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
195 MODULE_LICENSE("GPL");
196 MODULE_VERSION(DRV_MODULE_VERSION);
197 MODULE_FIRMWARE(FIRMWARE_TG3);
198 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
199 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
200
201 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
202 module_param(tg3_debug, int, 0);
203 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
204
205 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
268         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
269         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
270         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
271         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
272         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
273         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
274         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
275         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
276         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
277         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
278         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
279         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
280         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
281         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
282         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
283         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
284         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
285         {}
286 };
287
288 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
289
290 static const struct {
291         const char string[ETH_GSTRING_LEN];
292 } ethtool_stats_keys[TG3_NUM_STATS] = {
293         { "rx_octets" },
294         { "rx_fragments" },
295         { "rx_ucast_packets" },
296         { "rx_mcast_packets" },
297         { "rx_bcast_packets" },
298         { "rx_fcs_errors" },
299         { "rx_align_errors" },
300         { "rx_xon_pause_rcvd" },
301         { "rx_xoff_pause_rcvd" },
302         { "rx_mac_ctrl_rcvd" },
303         { "rx_xoff_entered" },
304         { "rx_frame_too_long_errors" },
305         { "rx_jabbers" },
306         { "rx_undersize_packets" },
307         { "rx_in_length_errors" },
308         { "rx_out_length_errors" },
309         { "rx_64_or_less_octet_packets" },
310         { "rx_65_to_127_octet_packets" },
311         { "rx_128_to_255_octet_packets" },
312         { "rx_256_to_511_octet_packets" },
313         { "rx_512_to_1023_octet_packets" },
314         { "rx_1024_to_1522_octet_packets" },
315         { "rx_1523_to_2047_octet_packets" },
316         { "rx_2048_to_4095_octet_packets" },
317         { "rx_4096_to_8191_octet_packets" },
318         { "rx_8192_to_9022_octet_packets" },
319
320         { "tx_octets" },
321         { "tx_collisions" },
322
323         { "tx_xon_sent" },
324         { "tx_xoff_sent" },
325         { "tx_flow_control" },
326         { "tx_mac_errors" },
327         { "tx_single_collisions" },
328         { "tx_mult_collisions" },
329         { "tx_deferred" },
330         { "tx_excessive_collisions" },
331         { "tx_late_collisions" },
332         { "tx_collide_2times" },
333         { "tx_collide_3times" },
334         { "tx_collide_4times" },
335         { "tx_collide_5times" },
336         { "tx_collide_6times" },
337         { "tx_collide_7times" },
338         { "tx_collide_8times" },
339         { "tx_collide_9times" },
340         { "tx_collide_10times" },
341         { "tx_collide_11times" },
342         { "tx_collide_12times" },
343         { "tx_collide_13times" },
344         { "tx_collide_14times" },
345         { "tx_collide_15times" },
346         { "tx_ucast_packets" },
347         { "tx_mcast_packets" },
348         { "tx_bcast_packets" },
349         { "tx_carrier_sense_errors" },
350         { "tx_discards" },
351         { "tx_errors" },
352
353         { "dma_writeq_full" },
354         { "dma_write_prioq_full" },
355         { "rxbds_empty" },
356         { "rx_discards" },
357         { "rx_errors" },
358         { "rx_threshold_hit" },
359
360         { "dma_readq_full" },
361         { "dma_read_prioq_full" },
362         { "tx_comp_queue_full" },
363
364         { "ring_set_send_prod_index" },
365         { "ring_status_update" },
366         { "nic_irqs" },
367         { "nic_avoided_irqs" },
368         { "nic_tx_threshold_hit" }
369 };
370
371 static const struct {
372         const char string[ETH_GSTRING_LEN];
373 } ethtool_test_keys[TG3_NUM_TEST] = {
374         { "nvram test     (online) " },
375         { "link test      (online) " },
376         { "register test  (offline)" },
377         { "memory test    (offline)" },
378         { "loopback test  (offline)" },
379         { "interrupt test (offline)" },
380 };
381
382 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
383 {
384         writel(val, tp->regs + off);
385 }
386
387 static u32 tg3_read32(struct tg3 *tp, u32 off)
388 {
389         return readl(tp->regs + off);
390 }
391
392 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
393 {
394         writel(val, tp->aperegs + off);
395 }
396
397 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
398 {
399         return readl(tp->aperegs + off);
400 }
401
402 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
403 {
404         unsigned long flags;
405
406         spin_lock_irqsave(&tp->indirect_lock, flags);
407         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
408         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
409         spin_unlock_irqrestore(&tp->indirect_lock, flags);
410 }
411
412 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
413 {
414         writel(val, tp->regs + off);
415         readl(tp->regs + off);
416 }
417
418 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
419 {
420         unsigned long flags;
421         u32 val;
422
423         spin_lock_irqsave(&tp->indirect_lock, flags);
424         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
425         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
426         spin_unlock_irqrestore(&tp->indirect_lock, flags);
427         return val;
428 }
429
430 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
431 {
432         unsigned long flags;
433
434         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
435                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
436                                        TG3_64BIT_REG_LOW, val);
437                 return;
438         }
439         if (off == TG3_RX_STD_PROD_IDX_REG) {
440                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
441                                        TG3_64BIT_REG_LOW, val);
442                 return;
443         }
444
445         spin_lock_irqsave(&tp->indirect_lock, flags);
446         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
447         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
448         spin_unlock_irqrestore(&tp->indirect_lock, flags);
449
450         /* In indirect mode when disabling interrupts, we also need
451          * to clear the interrupt bit in the GRC local ctrl register.
452          */
453         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
454             (val == 0x1)) {
455                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
456                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
457         }
458 }
459
460 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
461 {
462         unsigned long flags;
463         u32 val;
464
465         spin_lock_irqsave(&tp->indirect_lock, flags);
466         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
467         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
468         spin_unlock_irqrestore(&tp->indirect_lock, flags);
469         return val;
470 }
471
472 /* usec_wait specifies the wait time in usec when writing to certain registers
473  * where it is unsafe to read back the register without some delay.
474  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
475  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
476  */
477 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
478 {
479         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
480             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
481                 /* Non-posted methods */
482                 tp->write32(tp, off, val);
483         else {
484                 /* Posted method */
485                 tg3_write32(tp, off, val);
486                 if (usec_wait)
487                         udelay(usec_wait);
488                 tp->read32(tp, off);
489         }
490         /* Wait again after the read for the posted method to guarantee that
491          * the wait time is met.
492          */
493         if (usec_wait)
494                 udelay(usec_wait);
495 }
496
497 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
498 {
499         tp->write32_mbox(tp, off, val);
500         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
501             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
502                 tp->read32_mbox(tp, off);
503 }
504
505 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
506 {
507         void __iomem *mbox = tp->regs + off;
508         writel(val, mbox);
509         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
510                 writel(val, mbox);
511         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
512                 readl(mbox);
513 }
514
515 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
516 {
517         return readl(tp->regs + off + GRCMBOX_BASE);
518 }
519
520 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
521 {
522         writel(val, tp->regs + off + GRCMBOX_BASE);
523 }
524
525 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
526 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
527 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
528 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
529 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
530
531 #define tw32(reg, val)                  tp->write32(tp, reg, val)
532 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
533 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
534 #define tr32(reg)                       tp->read32(tp, reg)
535
536 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
537 {
538         unsigned long flags;
539
540         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
541             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
542                 return;
543
544         spin_lock_irqsave(&tp->indirect_lock, flags);
545         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
546                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
547                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
548
549                 /* Always leave this as zero. */
550                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
551         } else {
552                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
553                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
554
555                 /* Always leave this as zero. */
556                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
557         }
558         spin_unlock_irqrestore(&tp->indirect_lock, flags);
559 }
560
561 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
562 {
563         unsigned long flags;
564
565         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
566             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
567                 *val = 0;
568                 return;
569         }
570
571         spin_lock_irqsave(&tp->indirect_lock, flags);
572         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
573                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
574                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
575
576                 /* Always leave this as zero. */
577                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
578         } else {
579                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
580                 *val = tr32(TG3PCI_MEM_WIN_DATA);
581
582                 /* Always leave this as zero. */
583                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
584         }
585         spin_unlock_irqrestore(&tp->indirect_lock, flags);
586 }
587
588 static void tg3_ape_lock_init(struct tg3 *tp)
589 {
590         int i;
591         u32 regbase;
592
593         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
594                 regbase = TG3_APE_LOCK_GRANT;
595         else
596                 regbase = TG3_APE_PER_LOCK_GRANT;
597
598         /* Make sure the driver hasn't any stale locks. */
599         for (i = 0; i < 8; i++)
600                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
601 }
602
603 static int tg3_ape_lock(struct tg3 *tp, int locknum)
604 {
605         int i, off;
606         int ret = 0;
607         u32 status, req, gnt;
608
609         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
610                 return 0;
611
612         switch (locknum) {
613         case TG3_APE_LOCK_GRC:
614         case TG3_APE_LOCK_MEM:
615                 break;
616         default:
617                 return -EINVAL;
618         }
619
620         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
621                 req = TG3_APE_LOCK_REQ;
622                 gnt = TG3_APE_LOCK_GRANT;
623         } else {
624                 req = TG3_APE_PER_LOCK_REQ;
625                 gnt = TG3_APE_PER_LOCK_GRANT;
626         }
627
628         off = 4 * locknum;
629
630         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
631
632         /* Wait for up to 1 millisecond to acquire lock. */
633         for (i = 0; i < 100; i++) {
634                 status = tg3_ape_read32(tp, gnt + off);
635                 if (status == APE_LOCK_GRANT_DRIVER)
636                         break;
637                 udelay(10);
638         }
639
640         if (status != APE_LOCK_GRANT_DRIVER) {
641                 /* Revoke the lock request. */
642                 tg3_ape_write32(tp, gnt + off,
643                                 APE_LOCK_GRANT_DRIVER);
644
645                 ret = -EBUSY;
646         }
647
648         return ret;
649 }
650
651 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
652 {
653         u32 gnt;
654
655         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
656                 return;
657
658         switch (locknum) {
659         case TG3_APE_LOCK_GRC:
660         case TG3_APE_LOCK_MEM:
661                 break;
662         default:
663                 return;
664         }
665
666         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
667                 gnt = TG3_APE_LOCK_GRANT;
668         else
669                 gnt = TG3_APE_PER_LOCK_GRANT;
670
671         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
672 }
673
674 static void tg3_disable_ints(struct tg3 *tp)
675 {
676         int i;
677
678         tw32(TG3PCI_MISC_HOST_CTRL,
679              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
680         for (i = 0; i < tp->irq_max; i++)
681                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
682 }
683
684 static void tg3_enable_ints(struct tg3 *tp)
685 {
686         int i;
687
688         tp->irq_sync = 0;
689         wmb();
690
691         tw32(TG3PCI_MISC_HOST_CTRL,
692              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
693
694         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
695         for (i = 0; i < tp->irq_cnt; i++) {
696                 struct tg3_napi *tnapi = &tp->napi[i];
697
698                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
699                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
700                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
701
702                 tp->coal_now |= tnapi->coal_now;
703         }
704
705         /* Force an initial interrupt */
706         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
707             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
708                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
709         else
710                 tw32(HOSTCC_MODE, tp->coal_now);
711
712         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
713 }
714
715 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
716 {
717         struct tg3 *tp = tnapi->tp;
718         struct tg3_hw_status *sblk = tnapi->hw_status;
719         unsigned int work_exists = 0;
720
721         /* check for phy events */
722         if (!(tp->tg3_flags &
723               (TG3_FLAG_USE_LINKCHG_REG |
724                TG3_FLAG_POLL_SERDES))) {
725                 if (sblk->status & SD_STATUS_LINK_CHG)
726                         work_exists = 1;
727         }
728         /* check for RX/TX work to do */
729         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
730             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
731                 work_exists = 1;
732
733         return work_exists;
734 }
735
736 /* tg3_int_reenable
737  *  similar to tg3_enable_ints, but it accurately determines whether there
738  *  is new work pending and can return without flushing the PIO write
739  *  which reenables interrupts
740  */
741 static void tg3_int_reenable(struct tg3_napi *tnapi)
742 {
743         struct tg3 *tp = tnapi->tp;
744
745         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
746         mmiowb();
747
748         /* When doing tagged status, this work check is unnecessary.
749          * The last_tag we write above tells the chip which piece of
750          * work we've completed.
751          */
752         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
753             tg3_has_work(tnapi))
754                 tw32(HOSTCC_MODE, tp->coalesce_mode |
755                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
756 }
757
758 static void tg3_switch_clocks(struct tg3 *tp)
759 {
760         u32 clock_ctrl;
761         u32 orig_clock_ctrl;
762
763         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
764             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
765                 return;
766
767         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
768
769         orig_clock_ctrl = clock_ctrl;
770         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
771                        CLOCK_CTRL_CLKRUN_OENABLE |
772                        0x1f);
773         tp->pci_clock_ctrl = clock_ctrl;
774
775         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
776                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
777                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
778                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
779                 }
780         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
781                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
782                             clock_ctrl |
783                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
784                             40);
785                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
786                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
787                             40);
788         }
789         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
790 }
791
792 #define PHY_BUSY_LOOPS  5000
793
794 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
795 {
796         u32 frame_val;
797         unsigned int loops;
798         int ret;
799
800         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
801                 tw32_f(MAC_MI_MODE,
802                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
803                 udelay(80);
804         }
805
806         *val = 0x0;
807
808         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
809                       MI_COM_PHY_ADDR_MASK);
810         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
811                       MI_COM_REG_ADDR_MASK);
812         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
813
814         tw32_f(MAC_MI_COM, frame_val);
815
816         loops = PHY_BUSY_LOOPS;
817         while (loops != 0) {
818                 udelay(10);
819                 frame_val = tr32(MAC_MI_COM);
820
821                 if ((frame_val & MI_COM_BUSY) == 0) {
822                         udelay(5);
823                         frame_val = tr32(MAC_MI_COM);
824                         break;
825                 }
826                 loops -= 1;
827         }
828
829         ret = -EBUSY;
830         if (loops != 0) {
831                 *val = frame_val & MI_COM_DATA_MASK;
832                 ret = 0;
833         }
834
835         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
836                 tw32_f(MAC_MI_MODE, tp->mi_mode);
837                 udelay(80);
838         }
839
840         return ret;
841 }
842
843 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
844 {
845         u32 frame_val;
846         unsigned int loops;
847         int ret;
848
849         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
850             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
851                 return 0;
852
853         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
854                 tw32_f(MAC_MI_MODE,
855                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
856                 udelay(80);
857         }
858
859         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
860                       MI_COM_PHY_ADDR_MASK);
861         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
862                       MI_COM_REG_ADDR_MASK);
863         frame_val |= (val & MI_COM_DATA_MASK);
864         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
865
866         tw32_f(MAC_MI_COM, frame_val);
867
868         loops = PHY_BUSY_LOOPS;
869         while (loops != 0) {
870                 udelay(10);
871                 frame_val = tr32(MAC_MI_COM);
872                 if ((frame_val & MI_COM_BUSY) == 0) {
873                         udelay(5);
874                         frame_val = tr32(MAC_MI_COM);
875                         break;
876                 }
877                 loops -= 1;
878         }
879
880         ret = -EBUSY;
881         if (loops != 0)
882                 ret = 0;
883
884         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
885                 tw32_f(MAC_MI_MODE, tp->mi_mode);
886                 udelay(80);
887         }
888
889         return ret;
890 }
891
892 static int tg3_bmcr_reset(struct tg3 *tp)
893 {
894         u32 phy_control;
895         int limit, err;
896
897         /* OK, reset it, and poll the BMCR_RESET bit until it
898          * clears or we time out.
899          */
900         phy_control = BMCR_RESET;
901         err = tg3_writephy(tp, MII_BMCR, phy_control);
902         if (err != 0)
903                 return -EBUSY;
904
905         limit = 5000;
906         while (limit--) {
907                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
908                 if (err != 0)
909                         return -EBUSY;
910
911                 if ((phy_control & BMCR_RESET) == 0) {
912                         udelay(40);
913                         break;
914                 }
915                 udelay(10);
916         }
917         if (limit < 0)
918                 return -EBUSY;
919
920         return 0;
921 }
922
923 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
924 {
925         struct tg3 *tp = bp->priv;
926         u32 val;
927
928         spin_lock_bh(&tp->lock);
929
930         if (tg3_readphy(tp, reg, &val))
931                 val = -EIO;
932
933         spin_unlock_bh(&tp->lock);
934
935         return val;
936 }
937
938 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
939 {
940         struct tg3 *tp = bp->priv;
941         u32 ret = 0;
942
943         spin_lock_bh(&tp->lock);
944
945         if (tg3_writephy(tp, reg, val))
946                 ret = -EIO;
947
948         spin_unlock_bh(&tp->lock);
949
950         return ret;
951 }
952
953 static int tg3_mdio_reset(struct mii_bus *bp)
954 {
955         return 0;
956 }
957
958 static void tg3_mdio_config_5785(struct tg3 *tp)
959 {
960         u32 val;
961         struct phy_device *phydev;
962
963         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
964         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
965         case PHY_ID_BCM50610:
966         case PHY_ID_BCM50610M:
967                 val = MAC_PHYCFG2_50610_LED_MODES;
968                 break;
969         case PHY_ID_BCMAC131:
970                 val = MAC_PHYCFG2_AC131_LED_MODES;
971                 break;
972         case PHY_ID_RTL8211C:
973                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
974                 break;
975         case PHY_ID_RTL8201E:
976                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
977                 break;
978         default:
979                 return;
980         }
981
982         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
983                 tw32(MAC_PHYCFG2, val);
984
985                 val = tr32(MAC_PHYCFG1);
986                 val &= ~(MAC_PHYCFG1_RGMII_INT |
987                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
988                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
989                 tw32(MAC_PHYCFG1, val);
990
991                 return;
992         }
993
994         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
995                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
996                        MAC_PHYCFG2_FMODE_MASK_MASK |
997                        MAC_PHYCFG2_GMODE_MASK_MASK |
998                        MAC_PHYCFG2_ACT_MASK_MASK   |
999                        MAC_PHYCFG2_QUAL_MASK_MASK |
1000                        MAC_PHYCFG2_INBAND_ENABLE;
1001
1002         tw32(MAC_PHYCFG2, val);
1003
1004         val = tr32(MAC_PHYCFG1);
1005         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1006                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1007         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1008                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1009                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1010                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1011                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1012         }
1013         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1014                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1015         tw32(MAC_PHYCFG1, val);
1016
1017         val = tr32(MAC_EXT_RGMII_MODE);
1018         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1019                  MAC_RGMII_MODE_RX_QUALITY |
1020                  MAC_RGMII_MODE_RX_ACTIVITY |
1021                  MAC_RGMII_MODE_RX_ENG_DET |
1022                  MAC_RGMII_MODE_TX_ENABLE |
1023                  MAC_RGMII_MODE_TX_LOWPWR |
1024                  MAC_RGMII_MODE_TX_RESET);
1025         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1026                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1027                         val |= MAC_RGMII_MODE_RX_INT_B |
1028                                MAC_RGMII_MODE_RX_QUALITY |
1029                                MAC_RGMII_MODE_RX_ACTIVITY |
1030                                MAC_RGMII_MODE_RX_ENG_DET;
1031                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1032                         val |= MAC_RGMII_MODE_TX_ENABLE |
1033                                MAC_RGMII_MODE_TX_LOWPWR |
1034                                MAC_RGMII_MODE_TX_RESET;
1035         }
1036         tw32(MAC_EXT_RGMII_MODE, val);
1037 }
1038
1039 static void tg3_mdio_start(struct tg3 *tp)
1040 {
1041         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1042         tw32_f(MAC_MI_MODE, tp->mi_mode);
1043         udelay(80);
1044
1045         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1046             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1047                 tg3_mdio_config_5785(tp);
1048 }
1049
1050 static int tg3_mdio_init(struct tg3 *tp)
1051 {
1052         int i;
1053         u32 reg;
1054         struct phy_device *phydev;
1055
1056         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1057             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
1058                 u32 is_serdes;
1059
1060                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1061
1062                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1063                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1064                 else
1065                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1066                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1067                 if (is_serdes)
1068                         tp->phy_addr += 7;
1069         } else
1070                 tp->phy_addr = TG3_PHY_MII_ADDR;
1071
1072         tg3_mdio_start(tp);
1073
1074         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1075             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1076                 return 0;
1077
1078         tp->mdio_bus = mdiobus_alloc();
1079         if (tp->mdio_bus == NULL)
1080                 return -ENOMEM;
1081
1082         tp->mdio_bus->name     = "tg3 mdio bus";
1083         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1084                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1085         tp->mdio_bus->priv     = tp;
1086         tp->mdio_bus->parent   = &tp->pdev->dev;
1087         tp->mdio_bus->read     = &tg3_mdio_read;
1088         tp->mdio_bus->write    = &tg3_mdio_write;
1089         tp->mdio_bus->reset    = &tg3_mdio_reset;
1090         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1091         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1092
1093         for (i = 0; i < PHY_MAX_ADDR; i++)
1094                 tp->mdio_bus->irq[i] = PHY_POLL;
1095
1096         /* The bus registration will look for all the PHYs on the mdio bus.
1097          * Unfortunately, it does not ensure the PHY is powered up before
1098          * accessing the PHY ID registers.  A chip reset is the
1099          * quickest way to bring the device back to an operational state..
1100          */
1101         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1102                 tg3_bmcr_reset(tp);
1103
1104         i = mdiobus_register(tp->mdio_bus);
1105         if (i) {
1106                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1107                 mdiobus_free(tp->mdio_bus);
1108                 return i;
1109         }
1110
1111         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1112
1113         if (!phydev || !phydev->drv) {
1114                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1115                 mdiobus_unregister(tp->mdio_bus);
1116                 mdiobus_free(tp->mdio_bus);
1117                 return -ENODEV;
1118         }
1119
1120         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1121         case PHY_ID_BCM57780:
1122                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1123                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1124                 break;
1125         case PHY_ID_BCM50610:
1126         case PHY_ID_BCM50610M:
1127                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1128                                      PHY_BRCM_RX_REFCLK_UNUSED |
1129                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1130                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1131                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1132                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1133                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1134                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1135                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1136                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1137                 /* fallthru */
1138         case PHY_ID_RTL8211C:
1139                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1140                 break;
1141         case PHY_ID_RTL8201E:
1142         case PHY_ID_BCMAC131:
1143                 phydev->interface = PHY_INTERFACE_MODE_MII;
1144                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1145                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1146                 break;
1147         }
1148
1149         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1150
1151         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1152                 tg3_mdio_config_5785(tp);
1153
1154         return 0;
1155 }
1156
1157 static void tg3_mdio_fini(struct tg3 *tp)
1158 {
1159         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1160                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1161                 mdiobus_unregister(tp->mdio_bus);
1162                 mdiobus_free(tp->mdio_bus);
1163         }
1164 }
1165
1166 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1167 {
1168         int err;
1169
1170         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1171         if (err)
1172                 goto done;
1173
1174         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1175         if (err)
1176                 goto done;
1177
1178         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1179                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1180         if (err)
1181                 goto done;
1182
1183         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1184
1185 done:
1186         return err;
1187 }
1188
1189 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1190 {
1191         int err;
1192
1193         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1194         if (err)
1195                 goto done;
1196
1197         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1198         if (err)
1199                 goto done;
1200
1201         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1202                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1203         if (err)
1204                 goto done;
1205
1206         err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1207
1208 done:
1209         return err;
1210 }
1211
1212 /* tp->lock is held. */
1213 static inline void tg3_generate_fw_event(struct tg3 *tp)
1214 {
1215         u32 val;
1216
1217         val = tr32(GRC_RX_CPU_EVENT);
1218         val |= GRC_RX_CPU_DRIVER_EVENT;
1219         tw32_f(GRC_RX_CPU_EVENT, val);
1220
1221         tp->last_event_jiffies = jiffies;
1222 }
1223
1224 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1225
1226 /* tp->lock is held. */
1227 static void tg3_wait_for_event_ack(struct tg3 *tp)
1228 {
1229         int i;
1230         unsigned int delay_cnt;
1231         long time_remain;
1232
1233         /* If enough time has passed, no wait is necessary. */
1234         time_remain = (long)(tp->last_event_jiffies + 1 +
1235                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1236                       (long)jiffies;
1237         if (time_remain < 0)
1238                 return;
1239
1240         /* Check if we can shorten the wait time. */
1241         delay_cnt = jiffies_to_usecs(time_remain);
1242         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1243                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1244         delay_cnt = (delay_cnt >> 3) + 1;
1245
1246         for (i = 0; i < delay_cnt; i++) {
1247                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1248                         break;
1249                 udelay(8);
1250         }
1251 }
1252
1253 /* tp->lock is held. */
1254 static void tg3_ump_link_report(struct tg3 *tp)
1255 {
1256         u32 reg;
1257         u32 val;
1258
1259         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1260             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1261                 return;
1262
1263         tg3_wait_for_event_ack(tp);
1264
1265         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1266
1267         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1268
1269         val = 0;
1270         if (!tg3_readphy(tp, MII_BMCR, &reg))
1271                 val = reg << 16;
1272         if (!tg3_readphy(tp, MII_BMSR, &reg))
1273                 val |= (reg & 0xffff);
1274         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1275
1276         val = 0;
1277         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1278                 val = reg << 16;
1279         if (!tg3_readphy(tp, MII_LPA, &reg))
1280                 val |= (reg & 0xffff);
1281         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1282
1283         val = 0;
1284         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1285                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1286                         val = reg << 16;
1287                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1288                         val |= (reg & 0xffff);
1289         }
1290         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1291
1292         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1293                 val = reg << 16;
1294         else
1295                 val = 0;
1296         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1297
1298         tg3_generate_fw_event(tp);
1299 }
1300
1301 static void tg3_link_report(struct tg3 *tp)
1302 {
1303         if (!netif_carrier_ok(tp->dev)) {
1304                 netif_info(tp, link, tp->dev, "Link is down\n");
1305                 tg3_ump_link_report(tp);
1306         } else if (netif_msg_link(tp)) {
1307                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1308                             (tp->link_config.active_speed == SPEED_1000 ?
1309                              1000 :
1310                              (tp->link_config.active_speed == SPEED_100 ?
1311                               100 : 10)),
1312                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1313                              "full" : "half"));
1314
1315                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1316                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1317                             "on" : "off",
1318                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1319                             "on" : "off");
1320                 tg3_ump_link_report(tp);
1321         }
1322 }
1323
1324 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1325 {
1326         u16 miireg;
1327
1328         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1329                 miireg = ADVERTISE_PAUSE_CAP;
1330         else if (flow_ctrl & FLOW_CTRL_TX)
1331                 miireg = ADVERTISE_PAUSE_ASYM;
1332         else if (flow_ctrl & FLOW_CTRL_RX)
1333                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1334         else
1335                 miireg = 0;
1336
1337         return miireg;
1338 }
1339
1340 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1341 {
1342         u16 miireg;
1343
1344         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1345                 miireg = ADVERTISE_1000XPAUSE;
1346         else if (flow_ctrl & FLOW_CTRL_TX)
1347                 miireg = ADVERTISE_1000XPSE_ASYM;
1348         else if (flow_ctrl & FLOW_CTRL_RX)
1349                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1350         else
1351                 miireg = 0;
1352
1353         return miireg;
1354 }
1355
1356 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1357 {
1358         u8 cap = 0;
1359
1360         if (lcladv & ADVERTISE_1000XPAUSE) {
1361                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1362                         if (rmtadv & LPA_1000XPAUSE)
1363                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1364                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1365                                 cap = FLOW_CTRL_RX;
1366                 } else {
1367                         if (rmtadv & LPA_1000XPAUSE)
1368                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1369                 }
1370         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1371                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1372                         cap = FLOW_CTRL_TX;
1373         }
1374
1375         return cap;
1376 }
1377
1378 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1379 {
1380         u8 autoneg;
1381         u8 flowctrl = 0;
1382         u32 old_rx_mode = tp->rx_mode;
1383         u32 old_tx_mode = tp->tx_mode;
1384
1385         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1386                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1387         else
1388                 autoneg = tp->link_config.autoneg;
1389
1390         if (autoneg == AUTONEG_ENABLE &&
1391             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1392                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1393                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1394                 else
1395                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1396         } else
1397                 flowctrl = tp->link_config.flowctrl;
1398
1399         tp->link_config.active_flowctrl = flowctrl;
1400
1401         if (flowctrl & FLOW_CTRL_RX)
1402                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1403         else
1404                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1405
1406         if (old_rx_mode != tp->rx_mode)
1407                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1408
1409         if (flowctrl & FLOW_CTRL_TX)
1410                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1411         else
1412                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1413
1414         if (old_tx_mode != tp->tx_mode)
1415                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1416 }
1417
1418 static void tg3_adjust_link(struct net_device *dev)
1419 {
1420         u8 oldflowctrl, linkmesg = 0;
1421         u32 mac_mode, lcl_adv, rmt_adv;
1422         struct tg3 *tp = netdev_priv(dev);
1423         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1424
1425         spin_lock_bh(&tp->lock);
1426
1427         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1428                                     MAC_MODE_HALF_DUPLEX);
1429
1430         oldflowctrl = tp->link_config.active_flowctrl;
1431
1432         if (phydev->link) {
1433                 lcl_adv = 0;
1434                 rmt_adv = 0;
1435
1436                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1437                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1438                 else if (phydev->speed == SPEED_1000 ||
1439                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1440                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1441                 else
1442                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1443
1444                 if (phydev->duplex == DUPLEX_HALF)
1445                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1446                 else {
1447                         lcl_adv = tg3_advert_flowctrl_1000T(
1448                                   tp->link_config.flowctrl);
1449
1450                         if (phydev->pause)
1451                                 rmt_adv = LPA_PAUSE_CAP;
1452                         if (phydev->asym_pause)
1453                                 rmt_adv |= LPA_PAUSE_ASYM;
1454                 }
1455
1456                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1457         } else
1458                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1459
1460         if (mac_mode != tp->mac_mode) {
1461                 tp->mac_mode = mac_mode;
1462                 tw32_f(MAC_MODE, tp->mac_mode);
1463                 udelay(40);
1464         }
1465
1466         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1467                 if (phydev->speed == SPEED_10)
1468                         tw32(MAC_MI_STAT,
1469                              MAC_MI_STAT_10MBPS_MODE |
1470                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1471                 else
1472                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1473         }
1474
1475         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1476                 tw32(MAC_TX_LENGTHS,
1477                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1478                       (6 << TX_LENGTHS_IPG_SHIFT) |
1479                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1480         else
1481                 tw32(MAC_TX_LENGTHS,
1482                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1483                       (6 << TX_LENGTHS_IPG_SHIFT) |
1484                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1485
1486         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1487             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1488             phydev->speed != tp->link_config.active_speed ||
1489             phydev->duplex != tp->link_config.active_duplex ||
1490             oldflowctrl != tp->link_config.active_flowctrl)
1491                 linkmesg = 1;
1492
1493         tp->link_config.active_speed = phydev->speed;
1494         tp->link_config.active_duplex = phydev->duplex;
1495
1496         spin_unlock_bh(&tp->lock);
1497
1498         if (linkmesg)
1499                 tg3_link_report(tp);
1500 }
1501
1502 static int tg3_phy_init(struct tg3 *tp)
1503 {
1504         struct phy_device *phydev;
1505
1506         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1507                 return 0;
1508
1509         /* Bring the PHY back to a known state. */
1510         tg3_bmcr_reset(tp);
1511
1512         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1513
1514         /* Attach the MAC to the PHY. */
1515         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1516                              phydev->dev_flags, phydev->interface);
1517         if (IS_ERR(phydev)) {
1518                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1519                 return PTR_ERR(phydev);
1520         }
1521
1522         /* Mask with MAC supported features. */
1523         switch (phydev->interface) {
1524         case PHY_INTERFACE_MODE_GMII:
1525         case PHY_INTERFACE_MODE_RGMII:
1526                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1527                         phydev->supported &= (PHY_GBIT_FEATURES |
1528                                               SUPPORTED_Pause |
1529                                               SUPPORTED_Asym_Pause);
1530                         break;
1531                 }
1532                 /* fallthru */
1533         case PHY_INTERFACE_MODE_MII:
1534                 phydev->supported &= (PHY_BASIC_FEATURES |
1535                                       SUPPORTED_Pause |
1536                                       SUPPORTED_Asym_Pause);
1537                 break;
1538         default:
1539                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1540                 return -EINVAL;
1541         }
1542
1543         tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1544
1545         phydev->advertising = phydev->supported;
1546
1547         return 0;
1548 }
1549
1550 static void tg3_phy_start(struct tg3 *tp)
1551 {
1552         struct phy_device *phydev;
1553
1554         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1555                 return;
1556
1557         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1558
1559         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1560                 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1561                 phydev->speed = tp->link_config.orig_speed;
1562                 phydev->duplex = tp->link_config.orig_duplex;
1563                 phydev->autoneg = tp->link_config.orig_autoneg;
1564                 phydev->advertising = tp->link_config.orig_advertising;
1565         }
1566
1567         phy_start(phydev);
1568
1569         phy_start_aneg(phydev);
1570 }
1571
1572 static void tg3_phy_stop(struct tg3 *tp)
1573 {
1574         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1575                 return;
1576
1577         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1578 }
1579
1580 static void tg3_phy_fini(struct tg3 *tp)
1581 {
1582         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1583                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1584                 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1585         }
1586 }
1587
1588 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1589 {
1590         int err;
1591
1592         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1593         if (!err)
1594                 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1595
1596         return err;
1597 }
1598
1599 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1600 {
1601         int err;
1602
1603         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1604         if (!err)
1605                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1606
1607         return err;
1608 }
1609
1610 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1611 {
1612         u32 phytest;
1613
1614         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1615                 u32 phy;
1616
1617                 tg3_writephy(tp, MII_TG3_FET_TEST,
1618                              phytest | MII_TG3_FET_SHADOW_EN);
1619                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1620                         if (enable)
1621                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1622                         else
1623                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1624                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1625                 }
1626                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1627         }
1628 }
1629
1630 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1631 {
1632         u32 reg;
1633
1634         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1635             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1636               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1637              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1638                 return;
1639
1640         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1641                 tg3_phy_fet_toggle_apd(tp, enable);
1642                 return;
1643         }
1644
1645         reg = MII_TG3_MISC_SHDW_WREN |
1646               MII_TG3_MISC_SHDW_SCR5_SEL |
1647               MII_TG3_MISC_SHDW_SCR5_LPED |
1648               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1649               MII_TG3_MISC_SHDW_SCR5_SDTL |
1650               MII_TG3_MISC_SHDW_SCR5_C125OE;
1651         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1652                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1653
1654         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1655
1656
1657         reg = MII_TG3_MISC_SHDW_WREN |
1658               MII_TG3_MISC_SHDW_APD_SEL |
1659               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1660         if (enable)
1661                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1662
1663         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1664 }
1665
1666 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1667 {
1668         u32 phy;
1669
1670         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1671             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1672                 return;
1673
1674         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1675                 u32 ephy;
1676
1677                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1678                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1679
1680                         tg3_writephy(tp, MII_TG3_FET_TEST,
1681                                      ephy | MII_TG3_FET_SHADOW_EN);
1682                         if (!tg3_readphy(tp, reg, &phy)) {
1683                                 if (enable)
1684                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1685                                 else
1686                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1687                                 tg3_writephy(tp, reg, phy);
1688                         }
1689                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1690                 }
1691         } else {
1692                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1693                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1694                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1695                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1696                         if (enable)
1697                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1698                         else
1699                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1700                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1701                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1702                 }
1703         }
1704 }
1705
1706 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1707 {
1708         u32 val;
1709
1710         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1711                 return;
1712
1713         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1714             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1715                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1716                              (val | (1 << 15) | (1 << 4)));
1717 }
1718
1719 static void tg3_phy_apply_otp(struct tg3 *tp)
1720 {
1721         u32 otp, phy;
1722
1723         if (!tp->phy_otp)
1724                 return;
1725
1726         otp = tp->phy_otp;
1727
1728         /* Enable SM_DSP clock and tx 6dB coding. */
1729         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1730               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1731               MII_TG3_AUXCTL_ACTL_TX_6DB;
1732         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1733
1734         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1735         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1736         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1737
1738         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1739               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1740         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1741
1742         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1743         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1744         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1745
1746         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1747         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1748
1749         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1750         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1751
1752         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1753               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1754         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1755
1756         /* Turn off SM_DSP clock. */
1757         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1758               MII_TG3_AUXCTL_ACTL_TX_6DB;
1759         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1760 }
1761
1762 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
1763 {
1764         u32 val;
1765
1766         if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
1767                 return;
1768
1769         tp->setlpicnt = 0;
1770
1771         if (tp->link_config.autoneg == AUTONEG_ENABLE &&
1772             current_link_up == 1 &&
1773             (tp->link_config.active_speed == SPEED_1000 ||
1774              (tp->link_config.active_speed == SPEED_100 &&
1775               tp->link_config.active_duplex == DUPLEX_FULL))) {
1776                 u32 eeectl;
1777
1778                 if (tp->link_config.active_speed == SPEED_1000)
1779                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
1780                 else
1781                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
1782
1783                 tw32(TG3_CPMU_EEE_CTRL, eeectl);
1784
1785                 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
1786                                   TG3_CL45_D7_EEERES_STAT, &val);
1787
1788                 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
1789                     val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
1790                         tp->setlpicnt = 2;
1791         }
1792
1793         if (!tp->setlpicnt) {
1794                 val = tr32(TG3_CPMU_EEE_MODE);
1795                 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
1796         }
1797 }
1798
1799 static int tg3_wait_macro_done(struct tg3 *tp)
1800 {
1801         int limit = 100;
1802
1803         while (limit--) {
1804                 u32 tmp32;
1805
1806                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1807                         if ((tmp32 & 0x1000) == 0)
1808                                 break;
1809                 }
1810         }
1811         if (limit < 0)
1812                 return -EBUSY;
1813
1814         return 0;
1815 }
1816
1817 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1818 {
1819         static const u32 test_pat[4][6] = {
1820         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1821         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1822         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1823         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1824         };
1825         int chan;
1826
1827         for (chan = 0; chan < 4; chan++) {
1828                 int i;
1829
1830                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1831                              (chan * 0x2000) | 0x0200);
1832                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1833
1834                 for (i = 0; i < 6; i++)
1835                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1836                                      test_pat[chan][i]);
1837
1838                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1839                 if (tg3_wait_macro_done(tp)) {
1840                         *resetp = 1;
1841                         return -EBUSY;
1842                 }
1843
1844                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1845                              (chan * 0x2000) | 0x0200);
1846                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1847                 if (tg3_wait_macro_done(tp)) {
1848                         *resetp = 1;
1849                         return -EBUSY;
1850                 }
1851
1852                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1853                 if (tg3_wait_macro_done(tp)) {
1854                         *resetp = 1;
1855                         return -EBUSY;
1856                 }
1857
1858                 for (i = 0; i < 6; i += 2) {
1859                         u32 low, high;
1860
1861                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1862                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1863                             tg3_wait_macro_done(tp)) {
1864                                 *resetp = 1;
1865                                 return -EBUSY;
1866                         }
1867                         low &= 0x7fff;
1868                         high &= 0x000f;
1869                         if (low != test_pat[chan][i] ||
1870                             high != test_pat[chan][i+1]) {
1871                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1872                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1873                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1874
1875                                 return -EBUSY;
1876                         }
1877                 }
1878         }
1879
1880         return 0;
1881 }
1882
1883 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1884 {
1885         int chan;
1886
1887         for (chan = 0; chan < 4; chan++) {
1888                 int i;
1889
1890                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1891                              (chan * 0x2000) | 0x0200);
1892                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1893                 for (i = 0; i < 6; i++)
1894                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1895                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1896                 if (tg3_wait_macro_done(tp))
1897                         return -EBUSY;
1898         }
1899
1900         return 0;
1901 }
1902
1903 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1904 {
1905         u32 reg32, phy9_orig;
1906         int retries, do_phy_reset, err;
1907
1908         retries = 10;
1909         do_phy_reset = 1;
1910         do {
1911                 if (do_phy_reset) {
1912                         err = tg3_bmcr_reset(tp);
1913                         if (err)
1914                                 return err;
1915                         do_phy_reset = 0;
1916                 }
1917
1918                 /* Disable transmitter and interrupt.  */
1919                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1920                         continue;
1921
1922                 reg32 |= 0x3000;
1923                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1924
1925                 /* Set full-duplex, 1000 mbps.  */
1926                 tg3_writephy(tp, MII_BMCR,
1927                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1928
1929                 /* Set to master mode.  */
1930                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1931                         continue;
1932
1933                 tg3_writephy(tp, MII_TG3_CTRL,
1934                              (MII_TG3_CTRL_AS_MASTER |
1935                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1936
1937                 /* Enable SM_DSP_CLOCK and 6dB.  */
1938                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1939
1940                 /* Block the PHY control access.  */
1941                 tg3_phydsp_write(tp, 0x8005, 0x0800);
1942
1943                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1944                 if (!err)
1945                         break;
1946         } while (--retries);
1947
1948         err = tg3_phy_reset_chanpat(tp);
1949         if (err)
1950                 return err;
1951
1952         tg3_phydsp_write(tp, 0x8005, 0x0000);
1953
1954         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1955         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1956
1957         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1958             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1959                 /* Set Extended packet length bit for jumbo frames */
1960                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1961         } else {
1962                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1963         }
1964
1965         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1966
1967         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1968                 reg32 &= ~0x3000;
1969                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1970         } else if (!err)
1971                 err = -EBUSY;
1972
1973         return err;
1974 }
1975
1976 /* This will reset the tigon3 PHY if there is no valid
1977  * link unless the FORCE argument is non-zero.
1978  */
1979 static int tg3_phy_reset(struct tg3 *tp)
1980 {
1981         u32 val, cpmuctrl;
1982         int err;
1983
1984         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1985                 val = tr32(GRC_MISC_CFG);
1986                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1987                 udelay(40);
1988         }
1989         err  = tg3_readphy(tp, MII_BMSR, &val);
1990         err |= tg3_readphy(tp, MII_BMSR, &val);
1991         if (err != 0)
1992                 return -EBUSY;
1993
1994         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1995                 netif_carrier_off(tp->dev);
1996                 tg3_link_report(tp);
1997         }
1998
1999         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2000             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2001             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2002                 err = tg3_phy_reset_5703_4_5(tp);
2003                 if (err)
2004                         return err;
2005                 goto out;
2006         }
2007
2008         cpmuctrl = 0;
2009         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2010             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2011                 cpmuctrl = tr32(TG3_CPMU_CTRL);
2012                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2013                         tw32(TG3_CPMU_CTRL,
2014                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2015         }
2016
2017         err = tg3_bmcr_reset(tp);
2018         if (err)
2019                 return err;
2020
2021         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2022                 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2023                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2024
2025                 tw32(TG3_CPMU_CTRL, cpmuctrl);
2026         }
2027
2028         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2029             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2030                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2031                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2032                     CPMU_LSPD_1000MB_MACCLK_12_5) {
2033                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2034                         udelay(40);
2035                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2036                 }
2037         }
2038
2039         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2040              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
2041             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2042                 return 0;
2043
2044         tg3_phy_apply_otp(tp);
2045
2046         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2047                 tg3_phy_toggle_apd(tp, true);
2048         else
2049                 tg3_phy_toggle_apd(tp, false);
2050
2051 out:
2052         if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
2053                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2054                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2055                 tg3_phydsp_write(tp, 0x000a, 0x0323);
2056                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2057         }
2058         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2059                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2060                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2061         }
2062         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2063                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2064                 tg3_phydsp_write(tp, 0x000a, 0x310b);
2065                 tg3_phydsp_write(tp, 0x201f, 0x9506);
2066                 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2067                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2068         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2069                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2070                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2071                 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2072                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2073                         tg3_writephy(tp, MII_TG3_TEST1,
2074                                      MII_TG3_TEST1_TRIM_EN | 0x4);
2075                 } else
2076                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2077                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2078         }
2079         /* Set Extended packet length bit (bit 14) on all chips that */
2080         /* support jumbo frames */
2081         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2082                 /* Cannot do read-modify-write on 5401 */
2083                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2084         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2085                 /* Set bit 14 with read-modify-write to preserve other bits */
2086                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2087                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
2088                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000);
2089         }
2090
2091         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2092          * jumbo frames transmission.
2093          */
2094         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2095                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2096                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2097                                      val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2098         }
2099
2100         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2101                 /* adjust output voltage */
2102                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2103         }
2104
2105         tg3_phy_toggle_automdix(tp, 1);
2106         tg3_phy_set_wirespeed(tp);
2107         return 0;
2108 }
2109
2110 static void tg3_frob_aux_power(struct tg3 *tp)
2111 {
2112         struct tg3 *tp_peer = tp;
2113
2114         /* The GPIOs do something completely different on 57765. */
2115         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2116             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2117             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2118                 return;
2119
2120         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2121             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2122             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2123                 struct net_device *dev_peer;
2124
2125                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2126                 /* remove_one() may have been run on the peer. */
2127                 if (!dev_peer)
2128                         tp_peer = tp;
2129                 else
2130                         tp_peer = netdev_priv(dev_peer);
2131         }
2132
2133         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2134             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2135             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2136             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2137                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2138                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2139                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2140                                     (GRC_LCLCTRL_GPIO_OE0 |
2141                                      GRC_LCLCTRL_GPIO_OE1 |
2142                                      GRC_LCLCTRL_GPIO_OE2 |
2143                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2144                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2145                                     100);
2146                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2147                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2148                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2149                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2150                                              GRC_LCLCTRL_GPIO_OE1 |
2151                                              GRC_LCLCTRL_GPIO_OE2 |
2152                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2153                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2154                                              tp->grc_local_ctrl;
2155                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2156
2157                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2158                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2159
2160                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2161                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2162                 } else {
2163                         u32 no_gpio2;
2164                         u32 grc_local_ctrl = 0;
2165
2166                         if (tp_peer != tp &&
2167                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2168                                 return;
2169
2170                         /* Workaround to prevent overdrawing Amps. */
2171                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2172                             ASIC_REV_5714) {
2173                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2174                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2175                                             grc_local_ctrl, 100);
2176                         }
2177
2178                         /* On 5753 and variants, GPIO2 cannot be used. */
2179                         no_gpio2 = tp->nic_sram_data_cfg &
2180                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2181
2182                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2183                                          GRC_LCLCTRL_GPIO_OE1 |
2184                                          GRC_LCLCTRL_GPIO_OE2 |
2185                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2186                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2187                         if (no_gpio2) {
2188                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2189                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2190                         }
2191                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2192                                                     grc_local_ctrl, 100);
2193
2194                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2195
2196                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2197                                                     grc_local_ctrl, 100);
2198
2199                         if (!no_gpio2) {
2200                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2201                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2202                                             grc_local_ctrl, 100);
2203                         }
2204                 }
2205         } else {
2206                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2207                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2208                         if (tp_peer != tp &&
2209                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2210                                 return;
2211
2212                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2213                                     (GRC_LCLCTRL_GPIO_OE1 |
2214                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2215
2216                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2217                                     GRC_LCLCTRL_GPIO_OE1, 100);
2218
2219                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2220                                     (GRC_LCLCTRL_GPIO_OE1 |
2221                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2222                 }
2223         }
2224 }
2225
2226 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2227 {
2228         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2229                 return 1;
2230         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2231                 if (speed != SPEED_10)
2232                         return 1;
2233         } else if (speed == SPEED_10)
2234                 return 1;
2235
2236         return 0;
2237 }
2238
2239 static int tg3_setup_phy(struct tg3 *, int);
2240
2241 #define RESET_KIND_SHUTDOWN     0
2242 #define RESET_KIND_INIT         1
2243 #define RESET_KIND_SUSPEND      2
2244
2245 static void tg3_write_sig_post_reset(struct tg3 *, int);
2246 static int tg3_halt_cpu(struct tg3 *, u32);
2247
2248 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2249 {
2250         u32 val;
2251
2252         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2253                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2254                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2255                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2256
2257                         sg_dig_ctrl |=
2258                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2259                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2260                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2261                 }
2262                 return;
2263         }
2264
2265         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2266                 tg3_bmcr_reset(tp);
2267                 val = tr32(GRC_MISC_CFG);
2268                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2269                 udelay(40);
2270                 return;
2271         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2272                 u32 phytest;
2273                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2274                         u32 phy;
2275
2276                         tg3_writephy(tp, MII_ADVERTISE, 0);
2277                         tg3_writephy(tp, MII_BMCR,
2278                                      BMCR_ANENABLE | BMCR_ANRESTART);
2279
2280                         tg3_writephy(tp, MII_TG3_FET_TEST,
2281                                      phytest | MII_TG3_FET_SHADOW_EN);
2282                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2283                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2284                                 tg3_writephy(tp,
2285                                              MII_TG3_FET_SHDW_AUXMODE4,
2286                                              phy);
2287                         }
2288                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2289                 }
2290                 return;
2291         } else if (do_low_power) {
2292                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2293                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2294
2295                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2296                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2297                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2298                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2299                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2300         }
2301
2302         /* The PHY should not be powered down on some chips because
2303          * of bugs.
2304          */
2305         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2306             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2307             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2308              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2309                 return;
2310
2311         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2312             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2313                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2314                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2315                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2316                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2317         }
2318
2319         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2320 }
2321
2322 /* tp->lock is held. */
2323 static int tg3_nvram_lock(struct tg3 *tp)
2324 {
2325         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2326                 int i;
2327
2328                 if (tp->nvram_lock_cnt == 0) {
2329                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2330                         for (i = 0; i < 8000; i++) {
2331                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2332                                         break;
2333                                 udelay(20);
2334                         }
2335                         if (i == 8000) {
2336                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2337                                 return -ENODEV;
2338                         }
2339                 }
2340                 tp->nvram_lock_cnt++;
2341         }
2342         return 0;
2343 }
2344
2345 /* tp->lock is held. */
2346 static void tg3_nvram_unlock(struct tg3 *tp)
2347 {
2348         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2349                 if (tp->nvram_lock_cnt > 0)
2350                         tp->nvram_lock_cnt--;
2351                 if (tp->nvram_lock_cnt == 0)
2352                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2353         }
2354 }
2355
2356 /* tp->lock is held. */
2357 static void tg3_enable_nvram_access(struct tg3 *tp)
2358 {
2359         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2360             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2361                 u32 nvaccess = tr32(NVRAM_ACCESS);
2362
2363                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2364         }
2365 }
2366
2367 /* tp->lock is held. */
2368 static void tg3_disable_nvram_access(struct tg3 *tp)
2369 {
2370         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2371             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2372                 u32 nvaccess = tr32(NVRAM_ACCESS);
2373
2374                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2375         }
2376 }
2377
2378 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2379                                         u32 offset, u32 *val)
2380 {
2381         u32 tmp;
2382         int i;
2383
2384         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2385                 return -EINVAL;
2386
2387         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2388                                         EEPROM_ADDR_DEVID_MASK |
2389                                         EEPROM_ADDR_READ);
2390         tw32(GRC_EEPROM_ADDR,
2391              tmp |
2392              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2393              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2394               EEPROM_ADDR_ADDR_MASK) |
2395              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2396
2397         for (i = 0; i < 1000; i++) {
2398                 tmp = tr32(GRC_EEPROM_ADDR);
2399
2400                 if (tmp & EEPROM_ADDR_COMPLETE)
2401                         break;
2402                 msleep(1);
2403         }
2404         if (!(tmp & EEPROM_ADDR_COMPLETE))
2405                 return -EBUSY;
2406
2407         tmp = tr32(GRC_EEPROM_DATA);
2408
2409         /*
2410          * The data will always be opposite the native endian
2411          * format.  Perform a blind byteswap to compensate.
2412          */
2413         *val = swab32(tmp);
2414
2415         return 0;
2416 }
2417
2418 #define NVRAM_CMD_TIMEOUT 10000
2419
2420 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2421 {
2422         int i;
2423
2424         tw32(NVRAM_CMD, nvram_cmd);
2425         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2426                 udelay(10);
2427                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2428                         udelay(10);
2429                         break;
2430                 }
2431         }
2432
2433         if (i == NVRAM_CMD_TIMEOUT)
2434                 return -EBUSY;
2435
2436         return 0;
2437 }
2438
2439 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2440 {
2441         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2442             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2443             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2444            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2445             (tp->nvram_jedecnum == JEDEC_ATMEL))
2446
2447                 addr = ((addr / tp->nvram_pagesize) <<
2448                         ATMEL_AT45DB0X1B_PAGE_POS) +
2449                        (addr % tp->nvram_pagesize);
2450
2451         return addr;
2452 }
2453
2454 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2455 {
2456         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2457             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2458             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2459            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2460             (tp->nvram_jedecnum == JEDEC_ATMEL))
2461
2462                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2463                         tp->nvram_pagesize) +
2464                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2465
2466         return addr;
2467 }
2468
2469 /* NOTE: Data read in from NVRAM is byteswapped according to
2470  * the byteswapping settings for all other register accesses.
2471  * tg3 devices are BE devices, so on a BE machine, the data
2472  * returned will be exactly as it is seen in NVRAM.  On a LE
2473  * machine, the 32-bit value will be byteswapped.
2474  */
2475 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2476 {
2477         int ret;
2478
2479         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2480                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2481
2482         offset = tg3_nvram_phys_addr(tp, offset);
2483
2484         if (offset > NVRAM_ADDR_MSK)
2485                 return -EINVAL;
2486
2487         ret = tg3_nvram_lock(tp);
2488         if (ret)
2489                 return ret;
2490
2491         tg3_enable_nvram_access(tp);
2492
2493         tw32(NVRAM_ADDR, offset);
2494         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2495                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2496
2497         if (ret == 0)
2498                 *val = tr32(NVRAM_RDDATA);
2499
2500         tg3_disable_nvram_access(tp);
2501
2502         tg3_nvram_unlock(tp);
2503
2504         return ret;
2505 }
2506
2507 /* Ensures NVRAM data is in bytestream format. */
2508 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2509 {
2510         u32 v;
2511         int res = tg3_nvram_read(tp, offset, &v);
2512         if (!res)
2513                 *val = cpu_to_be32(v);
2514         return res;
2515 }
2516
2517 /* tp->lock is held. */
2518 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2519 {
2520         u32 addr_high, addr_low;
2521         int i;
2522
2523         addr_high = ((tp->dev->dev_addr[0] << 8) |
2524                      tp->dev->dev_addr[1]);
2525         addr_low = ((tp->dev->dev_addr[2] << 24) |
2526                     (tp->dev->dev_addr[3] << 16) |
2527                     (tp->dev->dev_addr[4] <<  8) |
2528                     (tp->dev->dev_addr[5] <<  0));
2529         for (i = 0; i < 4; i++) {
2530                 if (i == 1 && skip_mac_1)
2531                         continue;
2532                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2533                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2534         }
2535
2536         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2537             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2538                 for (i = 0; i < 12; i++) {
2539                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2540                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2541                 }
2542         }
2543
2544         addr_high = (tp->dev->dev_addr[0] +
2545                      tp->dev->dev_addr[1] +
2546                      tp->dev->dev_addr[2] +
2547                      tp->dev->dev_addr[3] +
2548                      tp->dev->dev_addr[4] +
2549                      tp->dev->dev_addr[5]) &
2550                 TX_BACKOFF_SEED_MASK;
2551         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2552 }
2553
2554 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2555 {
2556         u32 misc_host_ctrl;
2557         bool device_should_wake, do_low_power;
2558
2559         /* Make sure register accesses (indirect or otherwise)
2560          * will function correctly.
2561          */
2562         pci_write_config_dword(tp->pdev,
2563                                TG3PCI_MISC_HOST_CTRL,
2564                                tp->misc_host_ctrl);
2565
2566         switch (state) {
2567         case PCI_D0:
2568                 pci_enable_wake(tp->pdev, state, false);
2569                 pci_set_power_state(tp->pdev, PCI_D0);
2570
2571                 /* Switch out of Vaux if it is a NIC */
2572                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2573                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2574
2575                 return 0;
2576
2577         case PCI_D1:
2578         case PCI_D2:
2579         case PCI_D3hot:
2580                 break;
2581
2582         default:
2583                 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2584                            state);
2585                 return -EINVAL;
2586         }
2587
2588         /* Restore the CLKREQ setting. */
2589         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2590                 u16 lnkctl;
2591
2592                 pci_read_config_word(tp->pdev,
2593                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2594                                      &lnkctl);
2595                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2596                 pci_write_config_word(tp->pdev,
2597                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2598                                       lnkctl);
2599         }
2600
2601         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2602         tw32(TG3PCI_MISC_HOST_CTRL,
2603              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2604
2605         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2606                              device_may_wakeup(&tp->pdev->dev) &&
2607                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2608
2609         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2610                 do_low_power = false;
2611                 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2612                     !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2613                         struct phy_device *phydev;
2614                         u32 phyid, advertising;
2615
2616                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2617
2618                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2619
2620                         tp->link_config.orig_speed = phydev->speed;
2621                         tp->link_config.orig_duplex = phydev->duplex;
2622                         tp->link_config.orig_autoneg = phydev->autoneg;
2623                         tp->link_config.orig_advertising = phydev->advertising;
2624
2625                         advertising = ADVERTISED_TP |
2626                                       ADVERTISED_Pause |
2627                                       ADVERTISED_Autoneg |
2628                                       ADVERTISED_10baseT_Half;
2629
2630                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2631                             device_should_wake) {
2632                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2633                                         advertising |=
2634                                                 ADVERTISED_100baseT_Half |
2635                                                 ADVERTISED_100baseT_Full |
2636                                                 ADVERTISED_10baseT_Full;
2637                                 else
2638                                         advertising |= ADVERTISED_10baseT_Full;
2639                         }
2640
2641                         phydev->advertising = advertising;
2642
2643                         phy_start_aneg(phydev);
2644
2645                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2646                         if (phyid != PHY_ID_BCMAC131) {
2647                                 phyid &= PHY_BCM_OUI_MASK;
2648                                 if (phyid == PHY_BCM_OUI_1 ||
2649                                     phyid == PHY_BCM_OUI_2 ||
2650                                     phyid == PHY_BCM_OUI_3)
2651                                         do_low_power = true;
2652                         }
2653                 }
2654         } else {
2655                 do_low_power = true;
2656
2657                 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2658                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2659                         tp->link_config.orig_speed = tp->link_config.speed;
2660                         tp->link_config.orig_duplex = tp->link_config.duplex;
2661                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2662                 }
2663
2664                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2665                         tp->link_config.speed = SPEED_10;
2666                         tp->link_config.duplex = DUPLEX_HALF;
2667                         tp->link_config.autoneg = AUTONEG_ENABLE;
2668                         tg3_setup_phy(tp, 0);
2669                 }
2670         }
2671
2672         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2673                 u32 val;
2674
2675                 val = tr32(GRC_VCPU_EXT_CTRL);
2676                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2677         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2678                 int i;
2679                 u32 val;
2680
2681                 for (i = 0; i < 200; i++) {
2682                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2683                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2684                                 break;
2685                         msleep(1);
2686                 }
2687         }
2688         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2689                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2690                                                      WOL_DRV_STATE_SHUTDOWN |
2691                                                      WOL_DRV_WOL |
2692                                                      WOL_SET_MAGIC_PKT);
2693
2694         if (device_should_wake) {
2695                 u32 mac_mode;
2696
2697                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2698                         if (do_low_power) {
2699                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2700                                 udelay(40);
2701                         }
2702
2703                         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2704                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2705                         else
2706                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2707
2708                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2709                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2710                             ASIC_REV_5700) {
2711                                 u32 speed = (tp->tg3_flags &
2712                                              TG3_FLAG_WOL_SPEED_100MB) ?
2713                                              SPEED_100 : SPEED_10;
2714                                 if (tg3_5700_link_polarity(tp, speed))
2715                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2716                                 else
2717                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2718                         }
2719                 } else {
2720                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2721                 }
2722
2723                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2724                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2725
2726                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2727                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2728                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2729                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2730                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2731                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2732
2733                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
2734                         mac_mode |= MAC_MODE_APE_TX_EN |
2735                                     MAC_MODE_APE_RX_EN |
2736                                     MAC_MODE_TDE_ENABLE;
2737
2738                 tw32_f(MAC_MODE, mac_mode);
2739                 udelay(100);
2740
2741                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2742                 udelay(10);
2743         }
2744
2745         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2746             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2747              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2748                 u32 base_val;
2749
2750                 base_val = tp->pci_clock_ctrl;
2751                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2752                              CLOCK_CTRL_TXCLK_DISABLE);
2753
2754                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2755                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2756         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2757                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2758                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2759                 /* do nothing */
2760         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2761                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2762                 u32 newbits1, newbits2;
2763
2764                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2765                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2766                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2767                                     CLOCK_CTRL_TXCLK_DISABLE |
2768                                     CLOCK_CTRL_ALTCLK);
2769                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2770                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2771                         newbits1 = CLOCK_CTRL_625_CORE;
2772                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2773                 } else {
2774                         newbits1 = CLOCK_CTRL_ALTCLK;
2775                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2776                 }
2777
2778                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2779                             40);
2780
2781                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2782                             40);
2783
2784                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2785                         u32 newbits3;
2786
2787                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2788                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2789                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2790                                             CLOCK_CTRL_TXCLK_DISABLE |
2791                                             CLOCK_CTRL_44MHZ_CORE);
2792                         } else {
2793                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2794                         }
2795
2796                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2797                                     tp->pci_clock_ctrl | newbits3, 40);
2798                 }
2799         }
2800
2801         if (!(device_should_wake) &&
2802             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2803                 tg3_power_down_phy(tp, do_low_power);
2804
2805         tg3_frob_aux_power(tp);
2806
2807         /* Workaround for unstable PLL clock */
2808         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2809             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2810                 u32 val = tr32(0x7d00);
2811
2812                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2813                 tw32(0x7d00, val);
2814                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2815                         int err;
2816
2817                         err = tg3_nvram_lock(tp);
2818                         tg3_halt_cpu(tp, RX_CPU_BASE);
2819                         if (!err)
2820                                 tg3_nvram_unlock(tp);
2821                 }
2822         }
2823
2824         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2825
2826         if (device_should_wake)
2827                 pci_enable_wake(tp->pdev, state, true);
2828
2829         /* Finally, set the new power state. */
2830         pci_set_power_state(tp->pdev, state);
2831
2832         return 0;
2833 }
2834
2835 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2836 {
2837         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2838         case MII_TG3_AUX_STAT_10HALF:
2839                 *speed = SPEED_10;
2840                 *duplex = DUPLEX_HALF;
2841                 break;
2842
2843         case MII_TG3_AUX_STAT_10FULL:
2844                 *speed = SPEED_10;
2845                 *duplex = DUPLEX_FULL;
2846                 break;
2847
2848         case MII_TG3_AUX_STAT_100HALF:
2849                 *speed = SPEED_100;
2850                 *duplex = DUPLEX_HALF;
2851                 break;
2852
2853         case MII_TG3_AUX_STAT_100FULL:
2854                 *speed = SPEED_100;
2855                 *duplex = DUPLEX_FULL;
2856                 break;
2857
2858         case MII_TG3_AUX_STAT_1000HALF:
2859                 *speed = SPEED_1000;
2860                 *duplex = DUPLEX_HALF;
2861                 break;
2862
2863         case MII_TG3_AUX_STAT_1000FULL:
2864                 *speed = SPEED_1000;
2865                 *duplex = DUPLEX_FULL;
2866                 break;
2867
2868         default:
2869                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2870                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2871                                  SPEED_10;
2872                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2873                                   DUPLEX_HALF;
2874                         break;
2875                 }
2876                 *speed = SPEED_INVALID;
2877                 *duplex = DUPLEX_INVALID;
2878                 break;
2879         }
2880 }
2881
2882 static void tg3_phy_copper_begin(struct tg3 *tp)
2883 {
2884         u32 new_adv;
2885         int i;
2886
2887         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2888                 /* Entering low power mode.  Disable gigabit and
2889                  * 100baseT advertisements.
2890                  */
2891                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2892
2893                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2894                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2895                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2896                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2897
2898                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2899         } else if (tp->link_config.speed == SPEED_INVALID) {
2900                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2901                         tp->link_config.advertising &=
2902                                 ~(ADVERTISED_1000baseT_Half |
2903                                   ADVERTISED_1000baseT_Full);
2904
2905                 new_adv = ADVERTISE_CSMA;
2906                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2907                         new_adv |= ADVERTISE_10HALF;
2908                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2909                         new_adv |= ADVERTISE_10FULL;
2910                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2911                         new_adv |= ADVERTISE_100HALF;
2912                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2913                         new_adv |= ADVERTISE_100FULL;
2914
2915                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2916
2917                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2918
2919                 if (tp->link_config.advertising &
2920                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2921                         new_adv = 0;
2922                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2923                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2924                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2925                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2926                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
2927                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2928                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2929                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2930                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2931                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2932                 } else {
2933                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2934                 }
2935         } else {
2936                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2937                 new_adv |= ADVERTISE_CSMA;
2938
2939                 /* Asking for a specific link mode. */
2940                 if (tp->link_config.speed == SPEED_1000) {
2941                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2942
2943                         if (tp->link_config.duplex == DUPLEX_FULL)
2944                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2945                         else
2946                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2947                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2948                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2949                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2950                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2951                 } else {
2952                         if (tp->link_config.speed == SPEED_100) {
2953                                 if (tp->link_config.duplex == DUPLEX_FULL)
2954                                         new_adv |= ADVERTISE_100FULL;
2955                                 else
2956                                         new_adv |= ADVERTISE_100HALF;
2957                         } else {
2958                                 if (tp->link_config.duplex == DUPLEX_FULL)
2959                                         new_adv |= ADVERTISE_10FULL;
2960                                 else
2961                                         new_adv |= ADVERTISE_10HALF;
2962                         }
2963                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2964
2965                         new_adv = 0;
2966                 }
2967
2968                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2969         }
2970
2971         if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
2972                 u32 val = 0;
2973
2974                 tw32(TG3_CPMU_EEE_MODE,
2975                      tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2976
2977                 /* Enable SM_DSP clock and tx 6dB coding. */
2978                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
2979                       MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
2980                       MII_TG3_AUXCTL_ACTL_TX_6DB;
2981                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2982
2983                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2984                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
2985                     !tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
2986                         tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2,
2987                                          val | MII_TG3_DSP_CH34TP2_HIBW01);
2988
2989                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2990                         /* Advertise 100-BaseTX EEE ability */
2991                         if (tp->link_config.advertising &
2992                             ADVERTISED_100baseT_Full)
2993                                 val |= MDIO_AN_EEE_ADV_100TX;
2994                         /* Advertise 1000-BaseT EEE ability */
2995                         if (tp->link_config.advertising &
2996                             ADVERTISED_1000baseT_Full)
2997                                 val |= MDIO_AN_EEE_ADV_1000T;
2998                 }
2999                 tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3000
3001                 /* Turn off SM_DSP clock. */
3002                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
3003                       MII_TG3_AUXCTL_ACTL_TX_6DB;
3004                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3005         }
3006
3007         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
3008             tp->link_config.speed != SPEED_INVALID) {
3009                 u32 bmcr, orig_bmcr;
3010
3011                 tp->link_config.active_speed = tp->link_config.speed;
3012                 tp->link_config.active_duplex = tp->link_config.duplex;
3013
3014                 bmcr = 0;
3015                 switch (tp->link_config.speed) {
3016                 default:
3017                 case SPEED_10:
3018                         break;
3019
3020                 case SPEED_100:
3021                         bmcr |= BMCR_SPEED100;
3022                         break;
3023
3024                 case SPEED_1000:
3025                         bmcr |= TG3_BMCR_SPEED1000;
3026                         break;
3027                 }
3028
3029                 if (tp->link_config.duplex == DUPLEX_FULL)
3030                         bmcr |= BMCR_FULLDPLX;
3031
3032                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
3033                     (bmcr != orig_bmcr)) {
3034                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
3035                         for (i = 0; i < 1500; i++) {
3036                                 u32 tmp;
3037
3038                                 udelay(10);
3039                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
3040                                     tg3_readphy(tp, MII_BMSR, &tmp))
3041                                         continue;
3042                                 if (!(tmp & BMSR_LSTATUS)) {
3043                                         udelay(40);
3044                                         break;
3045                                 }
3046                         }
3047                         tg3_writephy(tp, MII_BMCR, bmcr);
3048                         udelay(40);
3049                 }
3050         } else {
3051                 tg3_writephy(tp, MII_BMCR,
3052                              BMCR_ANENABLE | BMCR_ANRESTART);
3053         }
3054 }
3055
3056 static int tg3_init_5401phy_dsp(struct tg3 *tp)
3057 {
3058         int err;
3059
3060         /* Turn off tap power management. */
3061         /* Set Extended packet length bit */
3062         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
3063
3064         err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
3065         err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
3066         err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
3067         err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
3068         err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
3069
3070         udelay(40);
3071
3072         return err;
3073 }
3074
3075 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3076 {
3077         u32 adv_reg, all_mask = 0;
3078
3079         if (mask & ADVERTISED_10baseT_Half)
3080                 all_mask |= ADVERTISE_10HALF;
3081         if (mask & ADVERTISED_10baseT_Full)
3082                 all_mask |= ADVERTISE_10FULL;
3083         if (mask & ADVERTISED_100baseT_Half)
3084                 all_mask |= ADVERTISE_100HALF;
3085         if (mask & ADVERTISED_100baseT_Full)
3086                 all_mask |= ADVERTISE_100FULL;
3087
3088         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3089                 return 0;
3090
3091         if ((adv_reg & all_mask) != all_mask)
3092                 return 0;
3093         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3094                 u32 tg3_ctrl;
3095
3096                 all_mask = 0;
3097                 if (mask & ADVERTISED_1000baseT_Half)
3098                         all_mask |= ADVERTISE_1000HALF;
3099                 if (mask & ADVERTISED_1000baseT_Full)
3100                         all_mask |= ADVERTISE_1000FULL;
3101
3102                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3103                         return 0;
3104
3105                 if ((tg3_ctrl & all_mask) != all_mask)
3106                         return 0;
3107         }
3108         return 1;
3109 }
3110
3111 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3112 {
3113         u32 curadv, reqadv;
3114
3115         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3116                 return 1;
3117
3118         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3119         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3120
3121         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3122                 if (curadv != reqadv)
3123                         return 0;
3124
3125                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3126                         tg3_readphy(tp, MII_LPA, rmtadv);
3127         } else {
3128                 /* Reprogram the advertisement register, even if it
3129                  * does not affect the current link.  If the link
3130                  * gets renegotiated in the future, we can save an
3131                  * additional renegotiation cycle by advertising
3132                  * it correctly in the first place.
3133                  */
3134                 if (curadv != reqadv) {
3135                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3136                                      ADVERTISE_PAUSE_ASYM);
3137                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3138                 }
3139         }
3140
3141         return 1;
3142 }
3143
3144 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3145 {
3146         int current_link_up;
3147         u32 bmsr, val;
3148         u32 lcl_adv, rmt_adv;
3149         u16 current_speed;
3150         u8 current_duplex;
3151         int i, err;
3152
3153         tw32(MAC_EVENT, 0);
3154
3155         tw32_f(MAC_STATUS,
3156              (MAC_STATUS_SYNC_CHANGED |
3157               MAC_STATUS_CFG_CHANGED |
3158               MAC_STATUS_MI_COMPLETION |
3159               MAC_STATUS_LNKSTATE_CHANGED));
3160         udelay(40);
3161
3162         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3163                 tw32_f(MAC_MI_MODE,
3164                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3165                 udelay(80);
3166         }
3167
3168         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3169
3170         /* Some third-party PHYs need to be reset on link going
3171          * down.
3172          */
3173         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3174              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3175              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3176             netif_carrier_ok(tp->dev)) {
3177                 tg3_readphy(tp, MII_BMSR, &bmsr);
3178                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3179                     !(bmsr & BMSR_LSTATUS))
3180                         force_reset = 1;
3181         }
3182         if (force_reset)
3183                 tg3_phy_reset(tp);
3184
3185         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3186                 tg3_readphy(tp, MII_BMSR, &bmsr);
3187                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3188                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3189                         bmsr = 0;
3190
3191                 if (!(bmsr & BMSR_LSTATUS)) {
3192                         err = tg3_init_5401phy_dsp(tp);
3193                         if (err)
3194                                 return err;
3195
3196                         tg3_readphy(tp, MII_BMSR, &bmsr);
3197                         for (i = 0; i < 1000; i++) {
3198                                 udelay(10);
3199                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3200                                     (bmsr & BMSR_LSTATUS)) {
3201                                         udelay(40);
3202                                         break;
3203                                 }
3204                         }
3205
3206                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3207                             TG3_PHY_REV_BCM5401_B0 &&
3208                             !(bmsr & BMSR_LSTATUS) &&
3209                             tp->link_config.active_speed == SPEED_1000) {
3210                                 err = tg3_phy_reset(tp);
3211                                 if (!err)
3212                                         err = tg3_init_5401phy_dsp(tp);
3213                                 if (err)
3214                                         return err;
3215                         }
3216                 }
3217         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3218                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3219                 /* 5701 {A0,B0} CRC bug workaround */
3220                 tg3_writephy(tp, 0x15, 0x0a75);
3221                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3222                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3223                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3224         }
3225
3226         /* Clear pending interrupts... */
3227         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3228         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3229
3230         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3231                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3232         else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3233                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3234
3235         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3236             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3237                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3238                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3239                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3240                 else
3241                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3242         }
3243
3244         current_link_up = 0;
3245         current_speed = SPEED_INVALID;
3246         current_duplex = DUPLEX_INVALID;
3247
3248         if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3249                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3250                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3251                 if (!(val & (1 << 10))) {
3252                         val |= (1 << 10);
3253                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3254                         goto relink;
3255                 }
3256         }
3257
3258         bmsr = 0;
3259         for (i = 0; i < 100; i++) {
3260                 tg3_readphy(tp, MII_BMSR, &bmsr);
3261                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3262                     (bmsr & BMSR_LSTATUS))
3263                         break;
3264                 udelay(40);
3265         }
3266
3267         if (bmsr & BMSR_LSTATUS) {
3268                 u32 aux_stat, bmcr;
3269
3270                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3271                 for (i = 0; i < 2000; i++) {
3272                         udelay(10);
3273                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3274                             aux_stat)
3275                                 break;
3276                 }
3277
3278                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3279                                              &current_speed,
3280                                              &current_duplex);
3281
3282                 bmcr = 0;
3283                 for (i = 0; i < 200; i++) {
3284                         tg3_readphy(tp, MII_BMCR, &bmcr);
3285                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3286                                 continue;
3287                         if (bmcr && bmcr != 0x7fff)
3288                                 break;
3289                         udelay(10);
3290                 }
3291
3292                 lcl_adv = 0;
3293                 rmt_adv = 0;
3294
3295                 tp->link_config.active_speed = current_speed;
3296                 tp->link_config.active_duplex = current_duplex;
3297
3298                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3299                         if ((bmcr & BMCR_ANENABLE) &&
3300                             tg3_copper_is_advertising_all(tp,
3301                                                 tp->link_config.advertising)) {
3302                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3303                                                                   &rmt_adv))
3304                                         current_link_up = 1;
3305                         }
3306                 } else {
3307                         if (!(bmcr & BMCR_ANENABLE) &&
3308                             tp->link_config.speed == current_speed &&
3309                             tp->link_config.duplex == current_duplex &&
3310                             tp->link_config.flowctrl ==
3311                             tp->link_config.active_flowctrl) {
3312                                 current_link_up = 1;
3313                         }
3314                 }
3315
3316                 if (current_link_up == 1 &&
3317                     tp->link_config.active_duplex == DUPLEX_FULL)
3318                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3319         }
3320
3321 relink:
3322         if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3323                 tg3_phy_copper_begin(tp);
3324
3325                 tg3_readphy(tp, MII_BMSR, &bmsr);
3326                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3327                     (bmsr & BMSR_LSTATUS))
3328                         current_link_up = 1;
3329         }
3330
3331         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3332         if (current_link_up == 1) {
3333                 if (tp->link_config.active_speed == SPEED_100 ||
3334                     tp->link_config.active_speed == SPEED_10)
3335                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3336                 else
3337                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3338         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3339                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3340         else
3341                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3342
3343         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3344         if (tp->link_config.active_duplex == DUPLEX_HALF)
3345                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3346
3347         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3348                 if (current_link_up == 1 &&
3349                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3350                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3351                 else
3352                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3353         }
3354
3355         /* ??? Without this setting Netgear GA302T PHY does not
3356          * ??? send/receive packets...
3357          */
3358         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3359             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3360                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3361                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3362                 udelay(80);
3363         }
3364
3365         tw32_f(MAC_MODE, tp->mac_mode);
3366         udelay(40);
3367
3368         tg3_phy_eee_adjust(tp, current_link_up);
3369
3370         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3371                 /* Polled via timer. */
3372                 tw32_f(MAC_EVENT, 0);
3373         } else {
3374                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3375         }
3376         udelay(40);
3377
3378         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3379             current_link_up == 1 &&
3380             tp->link_config.active_speed == SPEED_1000 &&
3381             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3382              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3383                 udelay(120);
3384                 tw32_f(MAC_STATUS,
3385                      (MAC_STATUS_SYNC_CHANGED |
3386                       MAC_STATUS_CFG_CHANGED));
3387                 udelay(40);
3388                 tg3_write_mem(tp,
3389                               NIC_SRAM_FIRMWARE_MBOX,
3390                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3391         }
3392
3393         /* Prevent send BD corruption. */
3394         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3395                 u16 oldlnkctl, newlnkctl;
3396
3397                 pci_read_config_word(tp->pdev,
3398                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3399                                      &oldlnkctl);
3400                 if (tp->link_config.active_speed == SPEED_100 ||
3401                     tp->link_config.active_speed == SPEED_10)
3402                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3403                 else
3404                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3405                 if (newlnkctl != oldlnkctl)
3406                         pci_write_config_word(tp->pdev,
3407                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3408                                               newlnkctl);
3409         }
3410
3411         if (current_link_up != netif_carrier_ok(tp->dev)) {
3412                 if (current_link_up)
3413                         netif_carrier_on(tp->dev);
3414                 else
3415                         netif_carrier_off(tp->dev);
3416                 tg3_link_report(tp);
3417         }
3418
3419         return 0;
3420 }
3421
3422 struct tg3_fiber_aneginfo {
3423         int state;
3424 #define ANEG_STATE_UNKNOWN              0
3425 #define ANEG_STATE_AN_ENABLE            1
3426 #define ANEG_STATE_RESTART_INIT         2
3427 #define ANEG_STATE_RESTART              3
3428 #define ANEG_STATE_DISABLE_LINK_OK      4
3429 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3430 #define ANEG_STATE_ABILITY_DETECT       6
3431 #define ANEG_STATE_ACK_DETECT_INIT      7
3432 #define ANEG_STATE_ACK_DETECT           8
3433 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3434 #define ANEG_STATE_COMPLETE_ACK         10
3435 #define ANEG_STATE_IDLE_DETECT_INIT     11
3436 #define ANEG_STATE_IDLE_DETECT          12
3437 #define ANEG_STATE_LINK_OK              13
3438 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3439 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3440
3441         u32 flags;
3442 #define MR_AN_ENABLE            0x00000001
3443 #define MR_RESTART_AN           0x00000002
3444 #define MR_AN_COMPLETE          0x00000004
3445 #define MR_PAGE_RX              0x00000008
3446 #define MR_NP_LOADED            0x00000010
3447 #define MR_TOGGLE_TX            0x00000020
3448 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3449 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3450 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3451 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3452 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3453 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3454 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3455 #define MR_TOGGLE_RX            0x00002000
3456 #define MR_NP_RX                0x00004000
3457
3458 #define MR_LINK_OK              0x80000000
3459
3460         unsigned long link_time, cur_time;
3461
3462         u32 ability_match_cfg;
3463         int ability_match_count;
3464
3465         char ability_match, idle_match, ack_match;
3466
3467         u32 txconfig, rxconfig;
3468 #define ANEG_CFG_NP             0x00000080
3469 #define ANEG_CFG_ACK            0x00000040
3470 #define ANEG_CFG_RF2            0x00000020
3471 #define ANEG_CFG_RF1            0x00000010
3472 #define ANEG_CFG_PS2            0x00000001
3473 #define ANEG_CFG_PS1            0x00008000
3474 #define ANEG_CFG_HD             0x00004000
3475 #define ANEG_CFG_FD             0x00002000
3476 #define ANEG_CFG_INVAL          0x00001f06
3477
3478 };
3479 #define ANEG_OK         0
3480 #define ANEG_DONE       1
3481 #define ANEG_TIMER_ENAB 2
3482 #define ANEG_FAILED     -1
3483
3484 #define ANEG_STATE_SETTLE_TIME  10000
3485
3486 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3487                                    struct tg3_fiber_aneginfo *ap)
3488 {
3489         u16 flowctrl;
3490         unsigned long delta;
3491         u32 rx_cfg_reg;
3492         int ret;
3493
3494         if (ap->state == ANEG_STATE_UNKNOWN) {
3495                 ap->rxconfig = 0;
3496                 ap->link_time = 0;
3497                 ap->cur_time = 0;
3498                 ap->ability_match_cfg = 0;
3499                 ap->ability_match_count = 0;
3500                 ap->ability_match = 0;
3501                 ap->idle_match = 0;
3502                 ap->ack_match = 0;
3503         }
3504         ap->cur_time++;
3505
3506         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3507                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3508
3509                 if (rx_cfg_reg != ap->ability_match_cfg) {
3510                         ap->ability_match_cfg = rx_cfg_reg;
3511                         ap->ability_match = 0;
3512                         ap->ability_match_count = 0;
3513                 } else {
3514                         if (++ap->ability_match_count > 1) {
3515                                 ap->ability_match = 1;
3516                                 ap->ability_match_cfg = rx_cfg_reg;
3517                         }
3518                 }
3519                 if (rx_cfg_reg & ANEG_CFG_ACK)
3520                         ap->ack_match = 1;
3521                 else
3522                         ap->ack_match = 0;
3523
3524                 ap->idle_match = 0;
3525         } else {
3526                 ap->idle_match = 1;
3527                 ap->ability_match_cfg = 0;
3528                 ap->ability_match_count = 0;
3529                 ap->ability_match = 0;
3530                 ap->ack_match = 0;
3531
3532                 rx_cfg_reg = 0;
3533         }
3534
3535         ap->rxconfig = rx_cfg_reg;
3536         ret = ANEG_OK;
3537
3538         switch (ap->state) {
3539         case ANEG_STATE_UNKNOWN:
3540                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3541                         ap->state = ANEG_STATE_AN_ENABLE;
3542
3543                 /* fallthru */
3544         case ANEG_STATE_AN_ENABLE:
3545                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3546                 if (ap->flags & MR_AN_ENABLE) {
3547                         ap->link_time = 0;
3548                         ap->cur_time = 0;
3549                         ap->ability_match_cfg = 0;
3550                         ap->ability_match_count = 0;
3551                         ap->ability_match = 0;
3552                         ap->idle_match = 0;
3553                         ap->ack_match = 0;
3554
3555                         ap->state = ANEG_STATE_RESTART_INIT;
3556                 } else {
3557                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3558                 }
3559                 break;
3560
3561         case ANEG_STATE_RESTART_INIT:
3562                 ap->link_time = ap->cur_time;
3563                 ap->flags &= ~(MR_NP_LOADED);
3564                 ap->txconfig = 0;
3565                 tw32(MAC_TX_AUTO_NEG, 0);
3566                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3567                 tw32_f(MAC_MODE, tp->mac_mode);
3568                 udelay(40);
3569
3570                 ret = ANEG_TIMER_ENAB;
3571                 ap->state = ANEG_STATE_RESTART;
3572
3573                 /* fallthru */
3574         case ANEG_STATE_RESTART:
3575                 delta = ap->cur_time - ap->link_time;
3576                 if (delta > ANEG_STATE_SETTLE_TIME)
3577                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3578                 else
3579                         ret = ANEG_TIMER_ENAB;
3580                 break;
3581
3582         case ANEG_STATE_DISABLE_LINK_OK:
3583                 ret = ANEG_DONE;
3584                 break;
3585
3586         case ANEG_STATE_ABILITY_DETECT_INIT:
3587                 ap->flags &= ~(MR_TOGGLE_TX);
3588                 ap->txconfig = ANEG_CFG_FD;
3589                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3590                 if (flowctrl & ADVERTISE_1000XPAUSE)
3591                         ap->txconfig |= ANEG_CFG_PS1;
3592                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3593                         ap->txconfig |= ANEG_CFG_PS2;
3594                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3595                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3596                 tw32_f(MAC_MODE, tp->mac_mode);
3597                 udelay(40);
3598
3599                 ap->state = ANEG_STATE_ABILITY_DETECT;
3600                 break;
3601
3602         case ANEG_STATE_ABILITY_DETECT:
3603                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3604                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3605                 break;
3606
3607         case ANEG_STATE_ACK_DETECT_INIT:
3608                 ap->txconfig |= ANEG_CFG_ACK;
3609                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3610                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3611                 tw32_f(MAC_MODE, tp->mac_mode);
3612                 udelay(40);
3613
3614                 ap->state = ANEG_STATE_ACK_DETECT;
3615
3616                 /* fallthru */
3617         case ANEG_STATE_ACK_DETECT:
3618                 if (ap->ack_match != 0) {
3619                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3620                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3621                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3622                         } else {
3623                                 ap->state = ANEG_STATE_AN_ENABLE;
3624                         }
3625                 } else if (ap->ability_match != 0 &&
3626                            ap->rxconfig == 0) {
3627                         ap->state = ANEG_STATE_AN_ENABLE;
3628                 }
3629                 break;
3630
3631         case ANEG_STATE_COMPLETE_ACK_INIT:
3632                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3633                         ret = ANEG_FAILED;
3634                         break;
3635                 }
3636                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3637                                MR_LP_ADV_HALF_DUPLEX |
3638                                MR_LP_ADV_SYM_PAUSE |
3639                                MR_LP_ADV_ASYM_PAUSE |
3640                                MR_LP_ADV_REMOTE_FAULT1 |
3641                                MR_LP_ADV_REMOTE_FAULT2 |
3642                                MR_LP_ADV_NEXT_PAGE |
3643                                MR_TOGGLE_RX |
3644                                MR_NP_RX);
3645                 if (ap->rxconfig & ANEG_CFG_FD)
3646                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3647                 if (ap->rxconfig & ANEG_CFG_HD)
3648                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3649                 if (ap->rxconfig & ANEG_CFG_PS1)
3650                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3651                 if (ap->rxconfig & ANEG_CFG_PS2)
3652                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3653                 if (ap->rxconfig & ANEG_CFG_RF1)
3654                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3655                 if (ap->rxconfig & ANEG_CFG_RF2)
3656                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3657                 if (ap->rxconfig & ANEG_CFG_NP)
3658                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3659
3660                 ap->link_time = ap->cur_time;
3661
3662                 ap->flags ^= (MR_TOGGLE_TX);
3663                 if (ap->rxconfig & 0x0008)
3664                         ap->flags |= MR_TOGGLE_RX;
3665                 if (ap->rxconfig & ANEG_CFG_NP)
3666                         ap->flags |= MR_NP_RX;
3667                 ap->flags |= MR_PAGE_RX;
3668
3669                 ap->state = ANEG_STATE_COMPLETE_ACK;
3670                 ret = ANEG_TIMER_ENAB;
3671                 break;
3672
3673         case ANEG_STATE_COMPLETE_ACK:
3674                 if (ap->ability_match != 0 &&
3675                     ap->rxconfig == 0) {
3676                         ap->state = ANEG_STATE_AN_ENABLE;
3677                         break;
3678                 }
3679                 delta = ap->cur_time - ap->link_time;
3680                 if (delta > ANEG_STATE_SETTLE_TIME) {
3681                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3682                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3683                         } else {
3684                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3685                                     !(ap->flags & MR_NP_RX)) {
3686                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3687                                 } else {
3688                                         ret = ANEG_FAILED;
3689                                 }
3690                         }
3691                 }
3692                 break;
3693
3694         case ANEG_STATE_IDLE_DETECT_INIT:
3695                 ap->link_time = ap->cur_time;
3696                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3697                 tw32_f(MAC_MODE, tp->mac_mode);
3698                 udelay(40);
3699
3700                 ap->state = ANEG_STATE_IDLE_DETECT;
3701                 ret = ANEG_TIMER_ENAB;
3702                 break;
3703
3704         case ANEG_STATE_IDLE_DETECT:
3705                 if (ap->ability_match != 0 &&
3706                     ap->rxconfig == 0) {
3707                         ap->state = ANEG_STATE_AN_ENABLE;
3708                         break;
3709                 }
3710                 delta = ap->cur_time - ap->link_time;
3711                 if (delta > ANEG_STATE_SETTLE_TIME) {
3712                         /* XXX another gem from the Broadcom driver :( */
3713                         ap->state = ANEG_STATE_LINK_OK;
3714                 }
3715                 break;
3716
3717         case ANEG_STATE_LINK_OK:
3718                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3719                 ret = ANEG_DONE;
3720                 break;
3721
3722         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3723                 /* ??? unimplemented */
3724                 break;
3725
3726         case ANEG_STATE_NEXT_PAGE_WAIT:
3727                 /* ??? unimplemented */
3728                 break;
3729
3730         default:
3731                 ret = ANEG_FAILED;
3732                 break;
3733         }
3734
3735         return ret;
3736 }
3737
3738 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3739 {
3740         int res = 0;
3741         struct tg3_fiber_aneginfo aninfo;
3742         int status = ANEG_FAILED;
3743         unsigned int tick;
3744         u32 tmp;
3745
3746         tw32_f(MAC_TX_AUTO_NEG, 0);
3747
3748         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3749         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3750         udelay(40);
3751
3752         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3753         udelay(40);
3754
3755         memset(&aninfo, 0, sizeof(aninfo));
3756         aninfo.flags |= MR_AN_ENABLE;
3757         aninfo.state = ANEG_STATE_UNKNOWN;
3758         aninfo.cur_time = 0;
3759         tick = 0;
3760         while (++tick < 195000) {
3761                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3762                 if (status == ANEG_DONE || status == ANEG_FAILED)
3763                         break;
3764
3765                 udelay(1);
3766         }
3767
3768         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3769         tw32_f(MAC_MODE, tp->mac_mode);
3770         udelay(40);
3771
3772         *txflags = aninfo.txconfig;
3773         *rxflags = aninfo.flags;
3774
3775         if (status == ANEG_DONE &&
3776             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3777                              MR_LP_ADV_FULL_DUPLEX)))
3778                 res = 1;
3779
3780         return res;
3781 }
3782
3783 static void tg3_init_bcm8002(struct tg3 *tp)
3784 {
3785         u32 mac_status = tr32(MAC_STATUS);
3786         int i;
3787
3788         /* Reset when initting first time or we have a link. */
3789         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3790             !(mac_status & MAC_STATUS_PCS_SYNCED))
3791                 return;
3792
3793         /* Set PLL lock range. */
3794         tg3_writephy(tp, 0x16, 0x8007);
3795
3796         /* SW reset */
3797         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3798
3799         /* Wait for reset to complete. */
3800         /* XXX schedule_timeout() ... */
3801         for (i = 0; i < 500; i++)
3802                 udelay(10);
3803
3804         /* Config mode; select PMA/Ch 1 regs. */
3805         tg3_writephy(tp, 0x10, 0x8411);
3806
3807         /* Enable auto-lock and comdet, select txclk for tx. */
3808         tg3_writephy(tp, 0x11, 0x0a10);
3809
3810         tg3_writephy(tp, 0x18, 0x00a0);
3811         tg3_writephy(tp, 0x16, 0x41ff);
3812
3813         /* Assert and deassert POR. */
3814         tg3_writephy(tp, 0x13, 0x0400);
3815         udelay(40);
3816         tg3_writephy(tp, 0x13, 0x0000);
3817
3818         tg3_writephy(tp, 0x11, 0x0a50);
3819         udelay(40);
3820         tg3_writephy(tp, 0x11, 0x0a10);
3821
3822         /* Wait for signal to stabilize */
3823         /* XXX schedule_timeout() ... */
3824         for (i = 0; i < 15000; i++)
3825                 udelay(10);
3826
3827         /* Deselect the channel register so we can read the PHYID
3828          * later.
3829          */
3830         tg3_writephy(tp, 0x10, 0x8011);
3831 }
3832
3833 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3834 {
3835         u16 flowctrl;
3836         u32 sg_dig_ctrl, sg_dig_status;
3837         u32 serdes_cfg, expected_sg_dig_ctrl;
3838         int workaround, port_a;
3839         int current_link_up;
3840
3841         serdes_cfg = 0;
3842         expected_sg_dig_ctrl = 0;
3843         workaround = 0;
3844         port_a = 1;
3845         current_link_up = 0;
3846
3847         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3848             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3849                 workaround = 1;
3850                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3851                         port_a = 0;
3852
3853                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3854                 /* preserve bits 20-23 for voltage regulator */
3855                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3856         }
3857
3858         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3859
3860         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3861                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3862                         if (workaround) {
3863                                 u32 val = serdes_cfg;
3864
3865                                 if (port_a)
3866                                         val |= 0xc010000;
3867                                 else
3868                                         val |= 0x4010000;
3869                                 tw32_f(MAC_SERDES_CFG, val);
3870                         }
3871
3872                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3873                 }
3874                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3875                         tg3_setup_flow_control(tp, 0, 0);
3876                         current_link_up = 1;
3877                 }
3878                 goto out;
3879         }
3880
3881         /* Want auto-negotiation.  */
3882         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3883
3884         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3885         if (flowctrl & ADVERTISE_1000XPAUSE)
3886                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3887         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3888                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3889
3890         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3891                 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3892                     tp->serdes_counter &&
3893                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3894                                     MAC_STATUS_RCVD_CFG)) ==
3895                      MAC_STATUS_PCS_SYNCED)) {
3896                         tp->serdes_counter--;
3897                         current_link_up = 1;
3898                         goto out;
3899                 }
3900 restart_autoneg:
3901                 if (workaround)
3902                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3903                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3904                 udelay(5);
3905                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3906
3907                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3908                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3909         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3910                                  MAC_STATUS_SIGNAL_DET)) {
3911                 sg_dig_status = tr32(SG_DIG_STATUS);
3912                 mac_status = tr32(MAC_STATUS);
3913
3914                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3915                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3916                         u32 local_adv = 0, remote_adv = 0;
3917
3918                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3919                                 local_adv |= ADVERTISE_1000XPAUSE;
3920                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3921                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3922
3923                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3924                                 remote_adv |= LPA_1000XPAUSE;
3925                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3926                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3927
3928                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3929                         current_link_up = 1;
3930                         tp->serdes_counter = 0;
3931                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3932                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3933                         if (tp->serdes_counter)
3934                                 tp->serdes_counter--;
3935                         else {
3936                                 if (workaround) {
3937                                         u32 val = serdes_cfg;
3938
3939                                         if (port_a)
3940                                                 val |= 0xc010000;
3941                                         else
3942                                                 val |= 0x4010000;
3943
3944                                         tw32_f(MAC_SERDES_CFG, val);
3945                                 }
3946
3947                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3948                                 udelay(40);
3949
3950                                 /* Link parallel detection - link is up */
3951                                 /* only if we have PCS_SYNC and not */
3952                                 /* receiving config code words */
3953                                 mac_status = tr32(MAC_STATUS);
3954                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3955                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3956                                         tg3_setup_flow_control(tp, 0, 0);
3957                                         current_link_up = 1;
3958                                         tp->phy_flags |=
3959                                                 TG3_PHYFLG_PARALLEL_DETECT;
3960                                         tp->serdes_counter =
3961                                                 SERDES_PARALLEL_DET_TIMEOUT;
3962                                 } else
3963                                         goto restart_autoneg;
3964                         }
3965                 }
3966         } else {
3967                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3968                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3969         }
3970
3971 out:
3972         return current_link_up;
3973 }
3974
3975 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3976 {
3977         int current_link_up = 0;
3978
3979         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3980                 goto out;
3981
3982         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3983                 u32 txflags, rxflags;
3984                 int i;
3985
3986                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3987                         u32 local_adv = 0, remote_adv = 0;
3988
3989                         if (txflags & ANEG_CFG_PS1)
3990                                 local_adv |= ADVERTISE_1000XPAUSE;
3991                         if (txflags & ANEG_CFG_PS2)
3992                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3993
3994                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3995                                 remote_adv |= LPA_1000XPAUSE;
3996                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3997                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3998
3999                         tg3_setup_flow_control(tp, local_adv, remote_adv);
4000
4001                         current_link_up = 1;
4002                 }
4003                 for (i = 0; i < 30; i++) {
4004                         udelay(20);
4005                         tw32_f(MAC_STATUS,
4006                                (MAC_STATUS_SYNC_CHANGED |
4007                                 MAC_STATUS_CFG_CHANGED));
4008                         udelay(40);
4009                         if ((tr32(MAC_STATUS) &
4010                              (MAC_STATUS_SYNC_CHANGED |
4011                               MAC_STATUS_CFG_CHANGED)) == 0)
4012                                 break;
4013                 }
4014
4015                 mac_status = tr32(MAC_STATUS);
4016                 if (current_link_up == 0 &&
4017                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
4018                     !(mac_status & MAC_STATUS_RCVD_CFG))
4019                         current_link_up = 1;
4020         } else {
4021                 tg3_setup_flow_control(tp, 0, 0);
4022
4023                 /* Forcing 1000FD link up. */
4024                 current_link_up = 1;
4025
4026                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
4027                 udelay(40);
4028
4029                 tw32_f(MAC_MODE, tp->mac_mode);
4030                 udelay(40);
4031         }
4032
4033 out:
4034         return current_link_up;
4035 }
4036
4037 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4038 {
4039         u32 orig_pause_cfg;
4040         u16 orig_active_speed;
4041         u8 orig_active_duplex;
4042         u32 mac_status;
4043         int current_link_up;
4044         int i;
4045
4046         orig_pause_cfg = tp->link_config.active_flowctrl;
4047         orig_active_speed = tp->link_config.active_speed;
4048         orig_active_duplex = tp->link_config.active_duplex;
4049
4050         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
4051             netif_carrier_ok(tp->dev) &&
4052             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
4053                 mac_status = tr32(MAC_STATUS);
4054                 mac_status &= (MAC_STATUS_PCS_SYNCED |
4055                                MAC_STATUS_SIGNAL_DET |
4056                                MAC_STATUS_CFG_CHANGED |
4057                                MAC_STATUS_RCVD_CFG);
4058                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
4059                                    MAC_STATUS_SIGNAL_DET)) {
4060                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4061                                             MAC_STATUS_CFG_CHANGED));
4062                         return 0;
4063                 }
4064         }
4065
4066         tw32_f(MAC_TX_AUTO_NEG, 0);
4067
4068         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
4069         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
4070         tw32_f(MAC_MODE, tp->mac_mode);
4071         udelay(40);
4072
4073         if (tp->phy_id == TG3_PHY_ID_BCM8002)
4074                 tg3_init_bcm8002(tp);
4075
4076         /* Enable link change event even when serdes polling.  */
4077         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4078         udelay(40);
4079
4080         current_link_up = 0;
4081         mac_status = tr32(MAC_STATUS);
4082
4083         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
4084                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4085         else
4086                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4087
4088         tp->napi[0].hw_status->status =
4089                 (SD_STATUS_UPDATED |
4090                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4091
4092         for (i = 0; i < 100; i++) {
4093                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4094                                     MAC_STATUS_CFG_CHANGED));
4095                 udelay(5);
4096                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4097                                          MAC_STATUS_CFG_CHANGED |
4098                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4099                         break;
4100         }
4101
4102         mac_status = tr32(MAC_STATUS);
4103         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4104                 current_link_up = 0;
4105                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4106                     tp->serdes_counter == 0) {
4107                         tw32_f(MAC_MODE, (tp->mac_mode |
4108                                           MAC_MODE_SEND_CONFIGS));
4109                         udelay(1);
4110                         tw32_f(MAC_MODE, tp->mac_mode);
4111                 }
4112         }
4113
4114         if (current_link_up == 1) {
4115                 tp->link_config.active_speed = SPEED_1000;
4116                 tp->link_config.active_duplex = DUPLEX_FULL;
4117                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4118                                     LED_CTRL_LNKLED_OVERRIDE |
4119                                     LED_CTRL_1000MBPS_ON));
4120         } else {
4121                 tp->link_config.active_speed = SPEED_INVALID;
4122                 tp->link_config.active_duplex = DUPLEX_INVALID;
4123                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4124                                     LED_CTRL_LNKLED_OVERRIDE |
4125                                     LED_CTRL_TRAFFIC_OVERRIDE));
4126         }
4127
4128         if (current_link_up != netif_carrier_ok(tp->dev)) {
4129                 if (current_link_up)
4130                         netif_carrier_on(tp->dev);
4131                 else
4132                         netif_carrier_off(tp->dev);
4133                 tg3_link_report(tp);
4134         } else {
4135                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4136                 if (orig_pause_cfg != now_pause_cfg ||
4137                     orig_active_speed != tp->link_config.active_speed ||
4138                     orig_active_duplex != tp->link_config.active_duplex)
4139                         tg3_link_report(tp);
4140         }
4141
4142         return 0;
4143 }
4144
4145 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4146 {
4147         int current_link_up, err = 0;
4148         u32 bmsr, bmcr;
4149         u16 current_speed;
4150         u8 current_duplex;
4151         u32 local_adv, remote_adv;
4152
4153         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4154         tw32_f(MAC_MODE, tp->mac_mode);
4155         udelay(40);
4156
4157         tw32(MAC_EVENT, 0);
4158
4159         tw32_f(MAC_STATUS,
4160              (MAC_STATUS_SYNC_CHANGED |
4161               MAC_STATUS_CFG_CHANGED |
4162               MAC_STATUS_MI_COMPLETION |
4163               MAC_STATUS_LNKSTATE_CHANGED));
4164         udelay(40);
4165
4166         if (force_reset)
4167                 tg3_phy_reset(tp);
4168
4169         current_link_up = 0;
4170         current_speed = SPEED_INVALID;
4171         current_duplex = DUPLEX_INVALID;
4172
4173         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4174         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4175         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4176                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4177                         bmsr |= BMSR_LSTATUS;
4178                 else
4179                         bmsr &= ~BMSR_LSTATUS;
4180         }
4181
4182         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4183
4184         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4185             (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4186                 /* do nothing, just check for link up at the end */
4187         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4188                 u32 adv, new_adv;
4189
4190                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4191                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4192                                   ADVERTISE_1000XPAUSE |
4193                                   ADVERTISE_1000XPSE_ASYM |
4194                                   ADVERTISE_SLCT);
4195
4196                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4197
4198                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4199                         new_adv |= ADVERTISE_1000XHALF;
4200                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4201                         new_adv |= ADVERTISE_1000XFULL;
4202
4203                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4204                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4205                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4206                         tg3_writephy(tp, MII_BMCR, bmcr);
4207
4208                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4209                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4210                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4211
4212                         return err;
4213                 }
4214         } else {
4215                 u32 new_bmcr;
4216
4217                 bmcr &= ~BMCR_SPEED1000;
4218                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4219
4220                 if (tp->link_config.duplex == DUPLEX_FULL)
4221                         new_bmcr |= BMCR_FULLDPLX;
4222
4223                 if (new_bmcr != bmcr) {
4224                         /* BMCR_SPEED1000 is a reserved bit that needs
4225                          * to be set on write.
4226                          */
4227                         new_bmcr |= BMCR_SPEED1000;
4228
4229                         /* Force a linkdown */
4230                         if (netif_carrier_ok(tp->dev)) {
4231                                 u32 adv;
4232
4233                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4234                                 adv &= ~(ADVERTISE_1000XFULL |
4235                                          ADVERTISE_1000XHALF |
4236                                          ADVERTISE_SLCT);
4237                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4238                                 tg3_writephy(tp, MII_BMCR, bmcr |
4239                                                            BMCR_ANRESTART |
4240                                                            BMCR_ANENABLE);
4241                                 udelay(10);
4242                                 netif_carrier_off(tp->dev);
4243                         }
4244                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4245                         bmcr = new_bmcr;
4246                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4247                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4248                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4249                             ASIC_REV_5714) {
4250                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4251                                         bmsr |= BMSR_LSTATUS;
4252                                 else
4253                                         bmsr &= ~BMSR_LSTATUS;
4254                         }
4255                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4256                 }
4257         }
4258
4259         if (bmsr & BMSR_LSTATUS) {
4260                 current_speed = SPEED_1000;
4261                 current_link_up = 1;
4262                 if (bmcr & BMCR_FULLDPLX)
4263                         current_duplex = DUPLEX_FULL;
4264                 else
4265                         current_duplex = DUPLEX_HALF;
4266
4267                 local_adv = 0;
4268                 remote_adv = 0;
4269
4270                 if (bmcr & BMCR_ANENABLE) {
4271                         u32 common;
4272
4273                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4274                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4275                         common = local_adv & remote_adv;
4276                         if (common & (ADVERTISE_1000XHALF |
4277                                       ADVERTISE_1000XFULL)) {
4278                                 if (common & ADVERTISE_1000XFULL)
4279                                         current_duplex = DUPLEX_FULL;
4280                                 else
4281                                         current_duplex = DUPLEX_HALF;
4282                         } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4283                                 /* Link is up via parallel detect */
4284                         } else {
4285                                 current_link_up = 0;
4286                         }
4287                 }
4288         }
4289
4290         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4291                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4292
4293         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4294         if (tp->link_config.active_duplex == DUPLEX_HALF)
4295                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4296
4297         tw32_f(MAC_MODE, tp->mac_mode);
4298         udelay(40);
4299
4300         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4301
4302         tp->link_config.active_speed = current_speed;
4303         tp->link_config.active_duplex = current_duplex;
4304
4305         if (current_link_up != netif_carrier_ok(tp->dev)) {
4306                 if (current_link_up)
4307                         netif_carrier_on(tp->dev);
4308                 else {
4309                         netif_carrier_off(tp->dev);
4310                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4311                 }
4312                 tg3_link_report(tp);
4313         }
4314         return err;
4315 }
4316
4317 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4318 {
4319         if (tp->serdes_counter) {
4320                 /* Give autoneg time to complete. */
4321                 tp->serdes_counter--;
4322                 return;
4323         }
4324
4325         if (!netif_carrier_ok(tp->dev) &&
4326             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4327                 u32 bmcr;
4328
4329                 tg3_readphy(tp, MII_BMCR, &bmcr);
4330                 if (bmcr & BMCR_ANENABLE) {
4331                         u32 phy1, phy2;
4332
4333                         /* Select shadow register 0x1f */
4334                         tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4335                         tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4336
4337                         /* Select expansion interrupt status register */
4338                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4339                                          MII_TG3_DSP_EXP1_INT_STAT);
4340                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4341                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4342
4343                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4344                                 /* We have signal detect and not receiving
4345                                  * config code words, link is up by parallel
4346                                  * detection.
4347                                  */
4348
4349                                 bmcr &= ~BMCR_ANENABLE;
4350                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4351                                 tg3_writephy(tp, MII_BMCR, bmcr);
4352                                 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4353                         }
4354                 }
4355         } else if (netif_carrier_ok(tp->dev) &&
4356                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4357                    (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4358                 u32 phy2;
4359
4360                 /* Select expansion interrupt status register */
4361                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4362                                  MII_TG3_DSP_EXP1_INT_STAT);
4363                 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4364                 if (phy2 & 0x20) {
4365                         u32 bmcr;
4366
4367                         /* Config code words received, turn on autoneg. */
4368                         tg3_readphy(tp, MII_BMCR, &bmcr);
4369                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4370
4371                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4372
4373                 }
4374         }
4375 }
4376
4377 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4378 {
4379         int err;
4380
4381         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4382                 err = tg3_setup_fiber_phy(tp, force_reset);
4383         else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4384                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4385         else
4386                 err = tg3_setup_copper_phy(tp, force_reset);
4387
4388         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4389                 u32 val, scale;
4390
4391                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4392                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4393                         scale = 65;
4394                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4395                         scale = 6;
4396                 else
4397                         scale = 12;
4398
4399                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4400                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4401                 tw32(GRC_MISC_CFG, val);
4402         }
4403
4404         if (tp->link_config.active_speed == SPEED_1000 &&
4405             tp->link_config.active_duplex == DUPLEX_HALF)
4406                 tw32(MAC_TX_LENGTHS,
4407                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4408                       (6 << TX_LENGTHS_IPG_SHIFT) |
4409                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4410         else
4411                 tw32(MAC_TX_LENGTHS,
4412                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4413                       (6 << TX_LENGTHS_IPG_SHIFT) |
4414                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4415
4416         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4417                 if (netif_carrier_ok(tp->dev)) {
4418                         tw32(HOSTCC_STAT_COAL_TICKS,
4419                              tp->coal.stats_block_coalesce_usecs);
4420                 } else {
4421                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4422                 }
4423         }
4424
4425         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4426                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4427                 if (!netif_carrier_ok(tp->dev))
4428                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4429                               tp->pwrmgmt_thresh;
4430                 else
4431                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4432                 tw32(PCIE_PWR_MGMT_THRESH, val);
4433         }
4434
4435         return err;
4436 }
4437
4438 static inline int tg3_irq_sync(struct tg3 *tp)
4439 {
4440         return tp->irq_sync;
4441 }
4442
4443 /* This is called whenever we suspect that the system chipset is re-
4444  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4445  * is bogus tx completions. We try to recover by setting the
4446  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4447  * in the workqueue.
4448  */
4449 static void tg3_tx_recover(struct tg3 *tp)
4450 {
4451         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4452                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4453
4454         netdev_warn(tp->dev,
4455                     "The system may be re-ordering memory-mapped I/O "
4456                     "cycles to the network device, attempting to recover. "
4457                     "Please report the problem to the driver maintainer "
4458                     "and include system chipset information.\n");
4459
4460         spin_lock(&tp->lock);
4461         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4462         spin_unlock(&tp->lock);
4463 }
4464
4465 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4466 {
4467         /* Tell compiler to fetch tx indices from memory. */
4468         barrier();
4469         return tnapi->tx_pending -
4470                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4471 }
4472
4473 /* Tigon3 never reports partial packet sends.  So we do not
4474  * need special logic to handle SKBs that have not had all
4475  * of their frags sent yet, like SunGEM does.
4476  */
4477 static void tg3_tx(struct tg3_napi *tnapi)
4478 {
4479         struct tg3 *tp = tnapi->tp;
4480         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4481         u32 sw_idx = tnapi->tx_cons;
4482         struct netdev_queue *txq;
4483         int index = tnapi - tp->napi;
4484
4485         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4486                 index--;
4487
4488         txq = netdev_get_tx_queue(tp->dev, index);
4489
4490         while (sw_idx != hw_idx) {
4491                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4492                 struct sk_buff *skb = ri->skb;
4493                 int i, tx_bug = 0;
4494
4495                 if (unlikely(skb == NULL)) {
4496                         tg3_tx_recover(tp);
4497                         return;
4498                 }
4499
4500                 pci_unmap_single(tp->pdev,
4501                                  dma_unmap_addr(ri, mapping),
4502                                  skb_headlen(skb),
4503                                  PCI_DMA_TODEVICE);
4504
4505                 ri->skb = NULL;
4506
4507                 sw_idx = NEXT_TX(sw_idx);
4508
4509                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4510                         ri = &tnapi->tx_buffers[sw_idx];
4511                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4512                                 tx_bug = 1;
4513
4514                         pci_unmap_page(tp->pdev,
4515                                        dma_unmap_addr(ri, mapping),
4516                                        skb_shinfo(skb)->frags[i].size,
4517                                        PCI_DMA_TODEVICE);
4518                         sw_idx = NEXT_TX(sw_idx);
4519                 }
4520
4521                 dev_kfree_skb(skb);
4522
4523                 if (unlikely(tx_bug)) {
4524                         tg3_tx_recover(tp);
4525                         return;
4526                 }
4527         }
4528
4529         tnapi->tx_cons = sw_idx;
4530
4531         /* Need to make the tx_cons update visible to tg3_start_xmit()
4532          * before checking for netif_queue_stopped().  Without the
4533          * memory barrier, there is a small possibility that tg3_start_xmit()
4534          * will miss it and cause the queue to be stopped forever.
4535          */
4536         smp_mb();
4537
4538         if (unlikely(netif_tx_queue_stopped(txq) &&
4539                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4540                 __netif_tx_lock(txq, smp_processor_id());
4541                 if (netif_tx_queue_stopped(txq) &&
4542                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4543                         netif_tx_wake_queue(txq);
4544                 __netif_tx_unlock(txq);
4545         }
4546 }
4547
4548 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4549 {
4550         if (!ri->skb)
4551                 return;
4552
4553         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4554                          map_sz, PCI_DMA_FROMDEVICE);
4555         dev_kfree_skb_any(ri->skb);
4556         ri->skb = NULL;
4557 }
4558
4559 /* Returns size of skb allocated or < 0 on error.
4560  *
4561  * We only need to fill in the address because the other members
4562  * of the RX descriptor are invariant, see tg3_init_rings.
4563  *
4564  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4565  * posting buffers we only dirty the first cache line of the RX
4566  * descriptor (containing the address).  Whereas for the RX status
4567  * buffers the cpu only reads the last cacheline of the RX descriptor
4568  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4569  */
4570 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4571                             u32 opaque_key, u32 dest_idx_unmasked)
4572 {
4573         struct tg3_rx_buffer_desc *desc;
4574         struct ring_info *map;
4575         struct sk_buff *skb;
4576         dma_addr_t mapping;
4577         int skb_size, dest_idx;
4578
4579         switch (opaque_key) {
4580         case RXD_OPAQUE_RING_STD:
4581                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4582                 desc = &tpr->rx_std[dest_idx];
4583                 map = &tpr->rx_std_buffers[dest_idx];
4584                 skb_size = tp->rx_pkt_map_sz;
4585                 break;
4586
4587         case RXD_OPAQUE_RING_JUMBO:
4588                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4589                 desc = &tpr->rx_jmb[dest_idx].std;
4590                 map = &tpr->rx_jmb_buffers[dest_idx];
4591                 skb_size = TG3_RX_JMB_MAP_SZ;
4592                 break;
4593
4594         default:
4595                 return -EINVAL;
4596         }
4597
4598         /* Do not overwrite any of the map or rp information
4599          * until we are sure we can commit to a new buffer.
4600          *
4601          * Callers depend upon this behavior and assume that
4602          * we leave everything unchanged if we fail.
4603          */
4604         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4605         if (skb == NULL)
4606                 return -ENOMEM;
4607
4608         skb_reserve(skb, tp->rx_offset);
4609
4610         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4611                                  PCI_DMA_FROMDEVICE);
4612         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4613                 dev_kfree_skb(skb);
4614                 return -EIO;
4615         }
4616
4617         map->skb = skb;
4618         dma_unmap_addr_set(map, mapping, mapping);
4619
4620         desc->addr_hi = ((u64)mapping >> 32);
4621         desc->addr_lo = ((u64)mapping & 0xffffffff);
4622
4623         return skb_size;
4624 }
4625
4626 /* We only need to move over in the address because the other
4627  * members of the RX descriptor are invariant.  See notes above
4628  * tg3_alloc_rx_skb for full details.
4629  */
4630 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4631                            struct tg3_rx_prodring_set *dpr,
4632                            u32 opaque_key, int src_idx,
4633                            u32 dest_idx_unmasked)
4634 {
4635         struct tg3 *tp = tnapi->tp;
4636         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4637         struct ring_info *src_map, *dest_map;
4638         struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
4639         int dest_idx;
4640
4641         switch (opaque_key) {
4642         case RXD_OPAQUE_RING_STD:
4643                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4644                 dest_desc = &dpr->rx_std[dest_idx];
4645                 dest_map = &dpr->rx_std_buffers[dest_idx];
4646                 src_desc = &spr->rx_std[src_idx];
4647                 src_map = &spr->rx_std_buffers[src_idx];
4648                 break;
4649
4650         case RXD_OPAQUE_RING_JUMBO:
4651                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4652                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4653                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4654                 src_desc = &spr->rx_jmb[src_idx].std;
4655                 src_map = &spr->rx_jmb_buffers[src_idx];
4656                 break;
4657
4658         default:
4659                 return;
4660         }
4661
4662         dest_map->skb = src_map->skb;
4663         dma_unmap_addr_set(dest_map, mapping,
4664                            dma_unmap_addr(src_map, mapping));
4665         dest_desc->addr_hi = src_desc->addr_hi;
4666         dest_desc->addr_lo = src_desc->addr_lo;
4667
4668         /* Ensure that the update to the skb happens after the physical
4669          * addresses have been transferred to the new BD location.
4670          */
4671         smp_wmb();
4672
4673         src_map->skb = NULL;
4674 }
4675
4676 /* The RX ring scheme is composed of multiple rings which post fresh
4677  * buffers to the chip, and one special ring the chip uses to report
4678  * status back to the host.
4679  *
4680  * The special ring reports the status of received packets to the
4681  * host.  The chip does not write into the original descriptor the
4682  * RX buffer was obtained from.  The chip simply takes the original
4683  * descriptor as provided by the host, updates the status and length
4684  * field, then writes this into the next status ring entry.
4685  *
4686  * Each ring the host uses to post buffers to the chip is described
4687  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4688  * it is first placed into the on-chip ram.  When the packet's length
4689  * is known, it walks down the TG3_BDINFO entries to select the ring.
4690  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4691  * which is within the range of the new packet's length is chosen.
4692  *
4693  * The "separate ring for rx status" scheme may sound queer, but it makes
4694  * sense from a cache coherency perspective.  If only the host writes
4695  * to the buffer post rings, and only the chip writes to the rx status
4696  * rings, then cache lines never move beyond shared-modified state.
4697  * If both the host and chip were to write into the same ring, cache line
4698  * eviction could occur since both entities want it in an exclusive state.
4699  */
4700 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4701 {
4702         struct tg3 *tp = tnapi->tp;
4703         u32 work_mask, rx_std_posted = 0;
4704         u32 std_prod_idx, jmb_prod_idx;
4705         u32 sw_idx = tnapi->rx_rcb_ptr;
4706         u16 hw_idx;
4707         int received;
4708         struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
4709
4710         hw_idx = *(tnapi->rx_rcb_prod_idx);
4711         /*
4712          * We need to order the read of hw_idx and the read of
4713          * the opaque cookie.
4714          */
4715         rmb();
4716         work_mask = 0;
4717         received = 0;
4718         std_prod_idx = tpr->rx_std_prod_idx;
4719         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4720         while (sw_idx != hw_idx && budget > 0) {
4721                 struct ring_info *ri;
4722                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4723                 unsigned int len;
4724                 struct sk_buff *skb;
4725                 dma_addr_t dma_addr;
4726                 u32 opaque_key, desc_idx, *post_ptr;
4727                 bool hw_vlan __maybe_unused = false;
4728                 u16 vtag __maybe_unused = 0;
4729
4730                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4731                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4732                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4733                         ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4734                         dma_addr = dma_unmap_addr(ri, mapping);
4735                         skb = ri->skb;
4736                         post_ptr = &std_prod_idx;
4737                         rx_std_posted++;
4738                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4739                         ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4740                         dma_addr = dma_unmap_addr(ri, mapping);
4741                         skb = ri->skb;
4742                         post_ptr = &jmb_prod_idx;
4743                 } else
4744                         goto next_pkt_nopost;
4745
4746                 work_mask |= opaque_key;
4747
4748                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4749                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4750                 drop_it:
4751                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4752                                        desc_idx, *post_ptr);
4753                 drop_it_no_recycle:
4754                         /* Other statistics kept track of by card. */
4755                         tp->rx_dropped++;
4756                         goto next_pkt;
4757                 }
4758
4759                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4760                       ETH_FCS_LEN;
4761
4762                 if (len > TG3_RX_COPY_THRESH(tp)) {
4763                         int skb_size;
4764
4765                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4766                                                     *post_ptr);
4767                         if (skb_size < 0)
4768                                 goto drop_it;
4769
4770                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4771                                          PCI_DMA_FROMDEVICE);
4772
4773                         /* Ensure that the update to the skb happens
4774                          * after the usage of the old DMA mapping.
4775                          */
4776                         smp_wmb();
4777
4778                         ri->skb = NULL;
4779
4780                         skb_put(skb, len);
4781                 } else {
4782                         struct sk_buff *copy_skb;
4783
4784                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4785                                        desc_idx, *post_ptr);
4786
4787                         copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
4788                                                     TG3_RAW_IP_ALIGN);
4789                         if (copy_skb == NULL)
4790                                 goto drop_it_no_recycle;
4791
4792                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
4793                         skb_put(copy_skb, len);
4794                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4795                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4796                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4797
4798                         /* We'll reuse the original ring buffer. */
4799                         skb = copy_skb;
4800                 }
4801
4802                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4803                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4804                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4805                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4806                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4807                 else
4808                         skb_checksum_none_assert(skb);
4809
4810                 skb->protocol = eth_type_trans(skb, tp->dev);
4811
4812                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4813                     skb->protocol != htons(ETH_P_8021Q)) {
4814                         dev_kfree_skb(skb);
4815                         goto drop_it_no_recycle;
4816                 }
4817
4818                 if (desc->type_flags & RXD_FLAG_VLAN &&
4819                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
4820                         vtag = desc->err_vlan & RXD_VLAN_MASK;
4821 #if TG3_VLAN_TAG_USED
4822                         if (tp->vlgrp)
4823                                 hw_vlan = true;
4824                         else
4825 #endif
4826                         {
4827                                 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
4828                                                     __skb_push(skb, VLAN_HLEN);
4829
4830                                 memmove(ve, skb->data + VLAN_HLEN,
4831                                         ETH_ALEN * 2);
4832                                 ve->h_vlan_proto = htons(ETH_P_8021Q);
4833                                 ve->h_vlan_TCI = htons(vtag);
4834                         }
4835                 }
4836
4837 #if TG3_VLAN_TAG_USED
4838                 if (hw_vlan)
4839                         vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
4840                 else
4841 #endif
4842                         napi_gro_receive(&tnapi->napi, skb);
4843
4844                 received++;
4845                 budget--;
4846
4847 next_pkt:
4848                 (*post_ptr)++;
4849
4850                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4851                         tpr->rx_std_prod_idx = std_prod_idx &
4852                                                tp->rx_std_ring_mask;
4853                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4854                                      tpr->rx_std_prod_idx);
4855                         work_mask &= ~RXD_OPAQUE_RING_STD;
4856                         rx_std_posted = 0;
4857                 }
4858 next_pkt_nopost:
4859                 sw_idx++;
4860                 sw_idx &= tp->rx_ret_ring_mask;
4861
4862                 /* Refresh hw_idx to see if there is new work */
4863                 if (sw_idx == hw_idx) {
4864                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4865                         rmb();
4866                 }
4867         }
4868
4869         /* ACK the status ring. */
4870         tnapi->rx_rcb_ptr = sw_idx;
4871         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4872
4873         /* Refill RX ring(s). */
4874         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4875                 if (work_mask & RXD_OPAQUE_RING_STD) {
4876                         tpr->rx_std_prod_idx = std_prod_idx &
4877                                                tp->rx_std_ring_mask;
4878                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4879                                      tpr->rx_std_prod_idx);
4880                 }
4881                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4882                         tpr->rx_jmb_prod_idx = jmb_prod_idx &
4883                                                tp->rx_jmb_ring_mask;
4884                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4885                                      tpr->rx_jmb_prod_idx);
4886                 }
4887                 mmiowb();
4888         } else if (work_mask) {
4889                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4890                  * updated before the producer indices can be updated.
4891                  */
4892                 smp_wmb();
4893
4894                 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
4895                 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
4896
4897                 if (tnapi != &tp->napi[1])
4898                         napi_schedule(&tp->napi[1].napi);
4899         }
4900
4901         return received;
4902 }
4903
4904 static void tg3_poll_link(struct tg3 *tp)
4905 {
4906         /* handle link change and other phy events */
4907         if (!(tp->tg3_flags &
4908               (TG3_FLAG_USE_LINKCHG_REG |
4909                TG3_FLAG_POLL_SERDES))) {
4910                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4911
4912                 if (sblk->status & SD_STATUS_LINK_CHG) {
4913                         sblk->status = SD_STATUS_UPDATED |
4914                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4915                         spin_lock(&tp->lock);
4916                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4917                                 tw32_f(MAC_STATUS,
4918                                      (MAC_STATUS_SYNC_CHANGED |
4919                                       MAC_STATUS_CFG_CHANGED |
4920                                       MAC_STATUS_MI_COMPLETION |
4921                                       MAC_STATUS_LNKSTATE_CHANGED));
4922                                 udelay(40);
4923                         } else
4924                                 tg3_setup_phy(tp, 0);
4925                         spin_unlock(&tp->lock);
4926                 }
4927         }
4928 }
4929
4930 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4931                                 struct tg3_rx_prodring_set *dpr,
4932                                 struct tg3_rx_prodring_set *spr)
4933 {
4934         u32 si, di, cpycnt, src_prod_idx;
4935         int i, err = 0;
4936
4937         while (1) {
4938                 src_prod_idx = spr->rx_std_prod_idx;
4939
4940                 /* Make sure updates to the rx_std_buffers[] entries and the
4941                  * standard producer index are seen in the correct order.
4942                  */
4943                 smp_rmb();
4944
4945                 if (spr->rx_std_cons_idx == src_prod_idx)
4946                         break;
4947
4948                 if (spr->rx_std_cons_idx < src_prod_idx)
4949                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4950                 else
4951                         cpycnt = tp->rx_std_ring_mask + 1 -
4952                                  spr->rx_std_cons_idx;
4953
4954                 cpycnt = min(cpycnt,
4955                              tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
4956
4957                 si = spr->rx_std_cons_idx;
4958                 di = dpr->rx_std_prod_idx;
4959
4960                 for (i = di; i < di + cpycnt; i++) {
4961                         if (dpr->rx_std_buffers[i].skb) {
4962                                 cpycnt = i - di;
4963                                 err = -ENOSPC;
4964                                 break;
4965                         }
4966                 }
4967
4968                 if (!cpycnt)
4969                         break;
4970
4971                 /* Ensure that updates to the rx_std_buffers ring and the
4972                  * shadowed hardware producer ring from tg3_recycle_skb() are
4973                  * ordered correctly WRT the skb check above.
4974                  */
4975                 smp_rmb();
4976
4977                 memcpy(&dpr->rx_std_buffers[di],
4978                        &spr->rx_std_buffers[si],
4979                        cpycnt * sizeof(struct ring_info));
4980
4981                 for (i = 0; i < cpycnt; i++, di++, si++) {
4982                         struct tg3_rx_buffer_desc *sbd, *dbd;
4983                         sbd = &spr->rx_std[si];
4984                         dbd = &dpr->rx_std[di];
4985                         dbd->addr_hi = sbd->addr_hi;
4986                         dbd->addr_lo = sbd->addr_lo;
4987                 }
4988
4989                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
4990                                        tp->rx_std_ring_mask;
4991                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
4992                                        tp->rx_std_ring_mask;
4993         }
4994
4995         while (1) {
4996                 src_prod_idx = spr->rx_jmb_prod_idx;
4997
4998                 /* Make sure updates to the rx_jmb_buffers[] entries and
4999                  * the jumbo producer index are seen in the correct order.
5000                  */
5001                 smp_rmb();
5002
5003                 if (spr->rx_jmb_cons_idx == src_prod_idx)
5004                         break;
5005
5006                 if (spr->rx_jmb_cons_idx < src_prod_idx)
5007                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
5008                 else
5009                         cpycnt = tp->rx_jmb_ring_mask + 1 -
5010                                  spr->rx_jmb_cons_idx;
5011
5012                 cpycnt = min(cpycnt,
5013                              tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
5014
5015                 si = spr->rx_jmb_cons_idx;
5016                 di = dpr->rx_jmb_prod_idx;
5017
5018                 for (i = di; i < di + cpycnt; i++) {
5019                         if (dpr->rx_jmb_buffers[i].skb) {
5020                                 cpycnt = i - di;
5021                                 err = -ENOSPC;
5022                                 break;
5023                         }
5024                 }
5025
5026                 if (!cpycnt)
5027                         break;
5028
5029                 /* Ensure that updates to the rx_jmb_buffers ring and the
5030                  * shadowed hardware producer ring from tg3_recycle_skb() are
5031                  * ordered correctly WRT the skb check above.
5032                  */
5033                 smp_rmb();
5034
5035                 memcpy(&dpr->rx_jmb_buffers[di],
5036                        &spr->rx_jmb_buffers[si],
5037                        cpycnt * sizeof(struct ring_info));
5038
5039                 for (i = 0; i < cpycnt; i++, di++, si++) {
5040                         struct tg3_rx_buffer_desc *sbd, *dbd;
5041                         sbd = &spr->rx_jmb[si].std;
5042                         dbd = &dpr->rx_jmb[di].std;
5043                         dbd->addr_hi = sbd->addr_hi;
5044                         dbd->addr_lo = sbd->addr_lo;
5045                 }
5046
5047                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
5048                                        tp->rx_jmb_ring_mask;
5049                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
5050                                        tp->rx_jmb_ring_mask;
5051         }
5052
5053         return err;
5054 }
5055
5056 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
5057 {
5058         struct tg3 *tp = tnapi->tp;
5059
5060         /* run TX completion thread */
5061         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
5062                 tg3_tx(tnapi);
5063                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5064                         return work_done;
5065         }
5066
5067         /* run RX thread, within the bounds set by NAPI.
5068          * All RX "locking" is done by ensuring outside
5069          * code synchronizes with tg3->napi.poll()
5070          */
5071         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
5072                 work_done += tg3_rx(tnapi, budget - work_done);
5073
5074         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
5075                 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
5076                 int i, err = 0;
5077                 u32 std_prod_idx = dpr->rx_std_prod_idx;
5078                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
5079
5080                 for (i = 1; i < tp->irq_cnt; i++)
5081                         err |= tg3_rx_prodring_xfer(tp, dpr,
5082                                                     &tp->napi[i].prodring);
5083
5084                 wmb();
5085
5086                 if (std_prod_idx != dpr->rx_std_prod_idx)
5087                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5088                                      dpr->rx_std_prod_idx);
5089
5090                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5091                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5092                                      dpr->rx_jmb_prod_idx);
5093
5094                 mmiowb();
5095
5096                 if (err)
5097                         tw32_f(HOSTCC_MODE, tp->coal_now);
5098         }
5099
5100         return work_done;
5101 }
5102
5103 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5104 {
5105         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5106         struct tg3 *tp = tnapi->tp;
5107         int work_done = 0;
5108         struct tg3_hw_status *sblk = tnapi->hw_status;
5109
5110         while (1) {
5111                 work_done = tg3_poll_work(tnapi, work_done, budget);
5112
5113                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5114                         goto tx_recovery;
5115
5116                 if (unlikely(work_done >= budget))
5117                         break;
5118
5119                 /* tp->last_tag is used in tg3_int_reenable() below
5120                  * to tell the hw how much work has been processed,
5121                  * so we must read it before checking for more work.
5122                  */
5123                 tnapi->last_tag = sblk->status_tag;
5124                 tnapi->last_irq_tag = tnapi->last_tag;
5125                 rmb();
5126
5127                 /* check for RX/TX work to do */
5128                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5129                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5130                         napi_complete(napi);
5131                         /* Reenable interrupts. */
5132                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5133                         mmiowb();
5134                         break;
5135                 }
5136         }
5137
5138         return work_done;
5139
5140 tx_recovery:
5141         /* work_done is guaranteed to be less than budget. */
5142         napi_complete(napi);
5143         schedule_work(&tp->reset_task);
5144         return work_done;
5145 }
5146
5147 static int tg3_poll(struct napi_struct *napi, int budget)
5148 {
5149         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5150         struct tg3 *tp = tnapi->tp;
5151         int work_done = 0;
5152         struct tg3_hw_status *sblk = tnapi->hw_status;
5153
5154         while (1) {
5155                 tg3_poll_link(tp);
5156
5157                 work_done = tg3_poll_work(tnapi, work_done, budget);
5158
5159                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5160                         goto tx_recovery;
5161
5162                 if (unlikely(work_done >= budget))
5163                         break;
5164
5165                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5166                         /* tp->last_tag is used in tg3_int_reenable() below
5167                          * to tell the hw how much work has been processed,
5168                          * so we must read it before checking for more work.
5169                          */
5170                         tnapi->last_tag = sblk->status_tag;
5171                         tnapi->last_irq_tag = tnapi->last_tag;
5172                         rmb();
5173                 } else
5174                         sblk->status &= ~SD_STATUS_UPDATED;
5175
5176                 if (likely(!tg3_has_work(tnapi))) {
5177                         napi_complete(napi);
5178                         tg3_int_reenable(tnapi);
5179                         break;
5180                 }
5181         }
5182
5183         return work_done;
5184
5185 tx_recovery:
5186         /* work_done is guaranteed to be less than budget. */
5187         napi_complete(napi);
5188         schedule_work(&tp->reset_task);
5189         return work_done;
5190 }
5191
5192 static void tg3_napi_disable(struct tg3 *tp)
5193 {
5194         int i;
5195
5196         for (i = tp->irq_cnt - 1; i >= 0; i--)
5197                 napi_disable(&tp->napi[i].napi);
5198 }
5199
5200 static void tg3_napi_enable(struct tg3 *tp)
5201 {
5202         int i;
5203
5204         for (i = 0; i < tp->irq_cnt; i++)
5205                 napi_enable(&tp->napi[i].napi);
5206 }
5207
5208 static void tg3_napi_init(struct tg3 *tp)
5209 {
5210         int i;
5211
5212         netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
5213         for (i = 1; i < tp->irq_cnt; i++)
5214                 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
5215 }
5216
5217 static void tg3_napi_fini(struct tg3 *tp)
5218 {
5219         int i;
5220
5221         for (i = 0; i < tp->irq_cnt; i++)
5222                 netif_napi_del(&tp->napi[i].napi);
5223 }
5224
5225 static inline void tg3_netif_stop(struct tg3 *tp)
5226 {
5227         tp->dev->trans_start = jiffies; /* prevent tx timeout */
5228         tg3_napi_disable(tp);
5229         netif_tx_disable(tp->dev);
5230 }
5231
5232 static inline void tg3_netif_start(struct tg3 *tp)
5233 {
5234         /* NOTE: unconditional netif_tx_wake_all_queues is only
5235          * appropriate so long as all callers are assured to
5236          * have free tx slots (such as after tg3_init_hw)
5237          */
5238         netif_tx_wake_all_queues(tp->dev);
5239
5240         tg3_napi_enable(tp);
5241         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
5242         tg3_enable_ints(tp);
5243 }
5244
5245 static void tg3_irq_quiesce(struct tg3 *tp)
5246 {
5247         int i;
5248
5249         BUG_ON(tp->irq_sync);
5250
5251         tp->irq_sync = 1;
5252         smp_mb();
5253
5254         for (i = 0; i < tp->irq_cnt; i++)
5255                 synchronize_irq(tp->napi[i].irq_vec);
5256 }
5257
5258 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5259  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5260  * with as well.  Most of the time, this is not necessary except when
5261  * shutting down the device.
5262  */
5263 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5264 {
5265         spin_lock_bh(&tp->lock);
5266         if (irq_sync)
5267                 tg3_irq_quiesce(tp);
5268 }
5269
5270 static inline void tg3_full_unlock(struct tg3 *tp)
5271 {
5272         spin_unlock_bh(&tp->lock);
5273 }
5274
5275 /* One-shot MSI handler - Chip automatically disables interrupt
5276  * after sending MSI so driver doesn't have to do it.
5277  */
5278 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5279 {
5280         struct tg3_napi *tnapi = dev_id;
5281         struct tg3 *tp = tnapi->tp;
5282
5283         prefetch(tnapi->hw_status);
5284         if (tnapi->rx_rcb)
5285                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5286
5287         if (likely(!tg3_irq_sync(tp)))
5288                 napi_schedule(&tnapi->napi);
5289
5290         return IRQ_HANDLED;
5291 }
5292
5293 /* MSI ISR - No need to check for interrupt sharing and no need to
5294  * flush status block and interrupt mailbox. PCI ordering rules
5295  * guarantee that MSI will arrive after the status block.
5296  */
5297 static irqreturn_t tg3_msi(int irq, void *dev_id)
5298 {
5299         struct tg3_napi *tnapi = dev_id;
5300         struct tg3 *tp = tnapi->tp;
5301
5302         prefetch(tnapi->hw_status);
5303         if (tnapi->rx_rcb)
5304                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5305         /*
5306          * Writing any value to intr-mbox-0 clears PCI INTA# and
5307          * chip-internal interrupt pending events.
5308          * Writing non-zero to intr-mbox-0 additional tells the
5309          * NIC to stop sending us irqs, engaging "in-intr-handler"
5310          * event coalescing.
5311          */
5312         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5313         if (likely(!tg3_irq_sync(tp)))
5314                 napi_schedule(&tnapi->napi);
5315
5316         return IRQ_RETVAL(1);
5317 }
5318
5319 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5320 {
5321         struct tg3_napi *tnapi = dev_id;
5322         struct tg3 *tp = tnapi->tp;
5323         struct tg3_hw_status *sblk = tnapi->hw_status;
5324         unsigned int handled = 1;
5325
5326         /* In INTx mode, it is possible for the interrupt to arrive at
5327          * the CPU before the status block posted prior to the interrupt.
5328          * Reading the PCI State register will confirm whether the
5329          * interrupt is ours and will flush the status block.
5330          */
5331         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5332                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5333                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5334                         handled = 0;
5335                         goto out;
5336                 }
5337         }
5338
5339         /*
5340          * Writing any value to intr-mbox-0 clears PCI INTA# and
5341          * chip-internal interrupt pending events.
5342          * Writing non-zero to intr-mbox-0 additional tells the
5343          * NIC to stop sending us irqs, engaging "in-intr-handler"
5344          * event coalescing.
5345          *
5346          * Flush the mailbox to de-assert the IRQ immediately to prevent
5347          * spurious interrupts.  The flush impacts performance but
5348          * excessive spurious interrupts can be worse in some cases.
5349          */
5350         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5351         if (tg3_irq_sync(tp))
5352                 goto out;
5353         sblk->status &= ~SD_STATUS_UPDATED;
5354         if (likely(tg3_has_work(tnapi))) {
5355                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5356                 napi_schedule(&tnapi->napi);
5357         } else {
5358                 /* No work, shared interrupt perhaps?  re-enable
5359                  * interrupts, and flush that PCI write
5360                  */
5361                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5362                                0x00000000);
5363         }
5364 out:
5365         return IRQ_RETVAL(handled);
5366 }
5367
5368 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5369 {
5370         struct tg3_napi *tnapi = dev_id;
5371         struct tg3 *tp = tnapi->tp;
5372         struct tg3_hw_status *sblk = tnapi->hw_status;
5373         unsigned int handled = 1;
5374
5375         /* In INTx mode, it is possible for the interrupt to arrive at
5376          * the CPU before the status block posted prior to the interrupt.
5377          * Reading the PCI State register will confirm whether the
5378          * interrupt is ours and will flush the status block.
5379          */
5380         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5381                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5382                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5383                         handled = 0;
5384                         goto out;
5385                 }
5386         }
5387
5388         /*
5389          * writing any value to intr-mbox-0 clears PCI INTA# and
5390          * chip-internal interrupt pending events.
5391          * writing non-zero to intr-mbox-0 additional tells the
5392          * NIC to stop sending us irqs, engaging "in-intr-handler"
5393          * event coalescing.
5394          *
5395          * Flush the mailbox to de-assert the IRQ immediately to prevent
5396          * spurious interrupts.  The flush impacts performance but
5397          * excessive spurious interrupts can be worse in some cases.
5398          */
5399         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5400
5401         /*
5402          * In a shared interrupt configuration, sometimes other devices'
5403          * interrupts will scream.  We record the current status tag here
5404          * so that the above check can report that the screaming interrupts
5405          * are unhandled.  Eventually they will be silenced.
5406          */
5407         tnapi->last_irq_tag = sblk->status_tag;
5408
5409         if (tg3_irq_sync(tp))
5410                 goto out;
5411
5412         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5413
5414         napi_schedule(&tnapi->napi);
5415
5416 out:
5417         return IRQ_RETVAL(handled);
5418 }
5419
5420 /* ISR for interrupt test */
5421 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5422 {
5423         struct tg3_napi *tnapi = dev_id;
5424         struct tg3 *tp = tnapi->tp;
5425         struct tg3_hw_status *sblk = tnapi->hw_status;
5426
5427         if ((sblk->status & SD_STATUS_UPDATED) ||
5428             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5429                 tg3_disable_ints(tp);
5430                 return IRQ_RETVAL(1);
5431         }
5432         return IRQ_RETVAL(0);
5433 }
5434
5435 static int tg3_init_hw(struct tg3 *, int);
5436 static int tg3_halt(struct tg3 *, int, int);
5437
5438 /* Restart hardware after configuration changes, self-test, etc.
5439  * Invoked with tp->lock held.
5440  */
5441 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5442         __releases(tp->lock)
5443         __acquires(tp->lock)
5444 {
5445         int err;
5446
5447         err = tg3_init_hw(tp, reset_phy);
5448         if (err) {
5449                 netdev_err(tp->dev,
5450                            "Failed to re-initialize device, aborting\n");
5451                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5452                 tg3_full_unlock(tp);
5453                 del_timer_sync(&tp->timer);
5454                 tp->irq_sync = 0;
5455                 tg3_napi_enable(tp);
5456                 dev_close(tp->dev);
5457                 tg3_full_lock(tp, 0);
5458         }
5459         return err;
5460 }
5461
5462 #ifdef CONFIG_NET_POLL_CONTROLLER
5463 static void tg3_poll_controller(struct net_device *dev)
5464 {
5465         int i;
5466         struct tg3 *tp = netdev_priv(dev);
5467
5468         for (i = 0; i < tp->irq_cnt; i++)
5469                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5470 }
5471 #endif
5472
5473 static void tg3_reset_task(struct work_struct *work)
5474 {
5475         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5476         int err;
5477         unsigned int restart_timer;
5478
5479         tg3_full_lock(tp, 0);
5480
5481         if (!netif_running(tp->dev)) {
5482                 tg3_full_unlock(tp);
5483                 return;
5484         }
5485
5486         tg3_full_unlock(tp);
5487
5488         tg3_phy_stop(tp);
5489
5490         tg3_netif_stop(tp);
5491
5492         tg3_full_lock(tp, 1);
5493
5494         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5495         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5496
5497         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5498                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5499                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5500                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5501                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5502         }
5503
5504         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5505         err = tg3_init_hw(tp, 1);
5506         if (err)
5507                 goto out;
5508
5509         tg3_netif_start(tp);
5510
5511         if (restart_timer)
5512                 mod_timer(&tp->timer, jiffies + 1);
5513
5514 out:
5515         tg3_full_unlock(tp);
5516
5517         if (!err)
5518                 tg3_phy_start(tp);
5519 }
5520
5521 static void tg3_dump_short_state(struct tg3 *tp)
5522 {
5523         netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5524                    tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5525         netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5526                    tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5527 }
5528
5529 static void tg3_tx_timeout(struct net_device *dev)
5530 {
5531         struct tg3 *tp = netdev_priv(dev);
5532
5533         if (netif_msg_tx_err(tp)) {
5534                 netdev_err(dev, "transmit timed out, resetting\n");
5535                 tg3_dump_short_state(tp);
5536         }
5537
5538         schedule_work(&tp->reset_task);
5539 }
5540
5541 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5542 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5543 {
5544         u32 base = (u32) mapping & 0xffffffff;
5545
5546         return (base > 0xffffdcc0) && (base + len + 8 < base);
5547 }
5548
5549 /* Test for DMA addresses > 40-bit */
5550 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5551                                           int len)
5552 {
5553 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5554         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5555                 return ((u64) mapping + len) > DMA_BIT_MASK(40);
5556         return 0;
5557 #else
5558         return 0;
5559 #endif
5560 }
5561
5562 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5563
5564 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5565 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5566                                        struct sk_buff *skb, u32 last_plus_one,
5567                                        u32 *start, u32 base_flags, u32 mss)
5568 {
5569         struct tg3 *tp = tnapi->tp;
5570         struct sk_buff *new_skb;
5571         dma_addr_t new_addr = 0;
5572         u32 entry = *start;
5573         int i, ret = 0;
5574
5575         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5576                 new_skb = skb_copy(skb, GFP_ATOMIC);
5577         else {
5578                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5579
5580                 new_skb = skb_copy_expand(skb,
5581                                           skb_headroom(skb) + more_headroom,
5582                                           skb_tailroom(skb), GFP_ATOMIC);
5583         }
5584
5585         if (!new_skb) {
5586                 ret = -1;
5587         } else {
5588                 /* New SKB is guaranteed to be linear. */
5589                 entry = *start;
5590                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5591                                           PCI_DMA_TODEVICE);
5592                 /* Make sure the mapping succeeded */
5593                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5594                         ret = -1;
5595                         dev_kfree_skb(new_skb);
5596                         new_skb = NULL;
5597
5598                 /* Make sure new skb does not cross any 4G boundaries.
5599                  * Drop the packet if it does.
5600                  */
5601                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5602                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5603                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5604                                          PCI_DMA_TODEVICE);
5605                         ret = -1;
5606                         dev_kfree_skb(new_skb);
5607                         new_skb = NULL;
5608                 } else {
5609                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5610                                     base_flags, 1 | (mss << 1));
5611                         *start = NEXT_TX(entry);
5612                 }
5613         }
5614
5615         /* Now clean up the sw ring entries. */
5616         i = 0;
5617         while (entry != last_plus_one) {
5618                 int len;
5619
5620                 if (i == 0)
5621                         len = skb_headlen(skb);
5622                 else
5623                         len = skb_shinfo(skb)->frags[i-1].size;
5624
5625                 pci_unmap_single(tp->pdev,
5626                                  dma_unmap_addr(&tnapi->tx_buffers[entry],
5627                                                 mapping),
5628                                  len, PCI_DMA_TODEVICE);
5629                 if (i == 0) {
5630                         tnapi->tx_buffers[entry].skb = new_skb;
5631                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5632                                            new_addr);
5633                 } else {
5634                         tnapi->tx_buffers[entry].skb = NULL;
5635                 }
5636                 entry = NEXT_TX(entry);
5637                 i++;
5638         }
5639
5640         dev_kfree_skb(skb);
5641
5642         return ret;
5643 }
5644
5645 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5646                         dma_addr_t mapping, int len, u32 flags,
5647                         u32 mss_and_is_end)
5648 {
5649         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5650         int is_end = (mss_and_is_end & 0x1);
5651         u32 mss = (mss_and_is_end >> 1);
5652         u32 vlan_tag = 0;
5653
5654         if (is_end)
5655                 flags |= TXD_FLAG_END;
5656         if (flags & TXD_FLAG_VLAN) {
5657                 vlan_tag = flags >> 16;
5658                 flags &= 0xffff;
5659         }
5660         vlan_tag |= (mss << TXD_MSS_SHIFT);
5661
5662         txd->addr_hi = ((u64) mapping >> 32);
5663         txd->addr_lo = ((u64) mapping & 0xffffffff);
5664         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5665         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5666 }
5667
5668 /* hard_start_xmit for devices that don't have any bugs and
5669  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5670  */
5671 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5672                                   struct net_device *dev)
5673 {
5674         struct tg3 *tp = netdev_priv(dev);
5675         u32 len, entry, base_flags, mss;
5676         dma_addr_t mapping;
5677         struct tg3_napi *tnapi;
5678         struct netdev_queue *txq;
5679         unsigned int i, last;
5680
5681         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5682         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5683         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5684                 tnapi++;
5685
5686         /* We are running in BH disabled context with netif_tx_lock
5687          * and TX reclaim runs via tp->napi.poll inside of a software
5688          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5689          * no IRQ context deadlocks to worry about either.  Rejoice!
5690          */
5691         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5692                 if (!netif_tx_queue_stopped(txq)) {
5693                         netif_tx_stop_queue(txq);
5694
5695                         /* This is a hard error, log it. */
5696                         netdev_err(dev,
5697                                    "BUG! Tx Ring full when queue awake!\n");
5698                 }
5699                 return NETDEV_TX_BUSY;
5700         }
5701
5702         entry = tnapi->tx_prod;
5703         base_flags = 0;
5704         mss = skb_shinfo(skb)->gso_size;
5705         if (mss) {
5706                 int tcp_opt_len, ip_tcp_len;
5707                 u32 hdrlen;
5708
5709                 if (skb_header_cloned(skb) &&
5710                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5711                         dev_kfree_skb(skb);
5712                         goto out_unlock;
5713                 }
5714
5715                 if (skb_is_gso_v6(skb)) {
5716                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5717                 } else {
5718                         struct iphdr *iph = ip_hdr(skb);
5719
5720                         tcp_opt_len = tcp_optlen(skb);
5721                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5722
5723                         iph->check = 0;
5724                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5725                         hdrlen = ip_tcp_len + tcp_opt_len;
5726                 }
5727
5728                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5729                         mss |= (hdrlen & 0xc) << 12;
5730                         if (hdrlen & 0x10)
5731                                 base_flags |= 0x00000010;
5732                         base_flags |= (hdrlen & 0x3e0) << 5;
5733                 } else
5734                         mss |= hdrlen << 9;
5735
5736                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5737                                TXD_FLAG_CPU_POST_DMA);
5738
5739                 tcp_hdr(skb)->check = 0;
5740
5741         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5742                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5743         }
5744
5745 #if TG3_VLAN_TAG_USED
5746         if (vlan_tx_tag_present(skb))
5747                 base_flags |= (TXD_FLAG_VLAN |
5748                                (vlan_tx_tag_get(skb) << 16));
5749 #endif
5750
5751         len = skb_headlen(skb);
5752
5753         /* Queue skb data, a.k.a. the main skb fragment. */
5754         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5755         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5756                 dev_kfree_skb(skb);
5757                 goto out_unlock;
5758         }
5759
5760         tnapi->tx_buffers[entry].skb = skb;
5761         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5762
5763         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&