tg3: Add 5785 ASIC revision
[linux-2.6.git] / drivers / net / tg3.c
1 /*
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  * Copyright (C) 2005-2007 Broadcom Corporation.
8  *
9  * Firmware is:
10  *      Derived from proprietary unpublished source code,
11  *      Copyright (C) 2000-2003 Broadcom Corporation.
12  *
13  *      Permission is hereby granted for the distribution of this firmware
14  *      data in hexadecimal or equivalent format, provided this copyright
15  *      notice is accompanying it.
16  */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
26 #include <linux/in.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/phy.h>
36 #include <linux/if_vlan.h>
37 #include <linux/ip.h>
38 #include <linux/tcp.h>
39 #include <linux/workqueue.h>
40 #include <linux/prefetch.h>
41 #include <linux/dma-mapping.h>
42
43 #include <net/checksum.h>
44 #include <net/ip.h>
45
46 #include <asm/system.h>
47 #include <asm/io.h>
48 #include <asm/byteorder.h>
49 #include <asm/uaccess.h>
50
51 #ifdef CONFIG_SPARC
52 #include <asm/idprom.h>
53 #include <asm/prom.h>
54 #endif
55
56 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
57 #define TG3_VLAN_TAG_USED 1
58 #else
59 #define TG3_VLAN_TAG_USED 0
60 #endif
61
62 #define TG3_TSO_SUPPORT 1
63
64 #include "tg3.h"
65
66 #define DRV_MODULE_NAME         "tg3"
67 #define PFX DRV_MODULE_NAME     ": "
68 #define DRV_MODULE_VERSION      "3.92"
69 #define DRV_MODULE_RELDATE      "May 2, 2008"
70
71 #define TG3_DEF_MAC_MODE        0
72 #define TG3_DEF_RX_MODE         0
73 #define TG3_DEF_TX_MODE         0
74 #define TG3_DEF_MSG_ENABLE        \
75         (NETIF_MSG_DRV          | \
76          NETIF_MSG_PROBE        | \
77          NETIF_MSG_LINK         | \
78          NETIF_MSG_TIMER        | \
79          NETIF_MSG_IFDOWN       | \
80          NETIF_MSG_IFUP         | \
81          NETIF_MSG_RX_ERR       | \
82          NETIF_MSG_TX_ERR)
83
84 /* length of time before we decide the hardware is borked,
85  * and dev->tx_timeout() should be called to fix the problem
86  */
87 #define TG3_TX_TIMEOUT                  (5 * HZ)
88
89 /* hardware minimum and maximum for a single frame's data payload */
90 #define TG3_MIN_MTU                     60
91 #define TG3_MAX_MTU(tp) \
92         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
93
94 /* These numbers seem to be hard coded in the NIC firmware somehow.
95  * You can't change the ring sizes, but you can change where you place
96  * them in the NIC onboard memory.
97  */
98 #define TG3_RX_RING_SIZE                512
99 #define TG3_DEF_RX_RING_PENDING         200
100 #define TG3_RX_JUMBO_RING_SIZE          256
101 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
102
103 /* Do not place this n-ring entries value into the tp struct itself,
104  * we really want to expose these constants to GCC so that modulo et
105  * al.  operations are done with shifts and masks instead of with
106  * hw multiply/modulo instructions.  Another solution would be to
107  * replace things like '% foo' with '& (foo - 1)'.
108  */
109 #define TG3_RX_RCB_RING_SIZE(tp)        \
110         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
111
112 #define TG3_TX_RING_SIZE                512
113 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
114
115 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
116                                  TG3_RX_RING_SIZE)
117 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
118                                  TG3_RX_JUMBO_RING_SIZE)
119 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
120                                    TG3_RX_RCB_RING_SIZE(tp))
121 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
122                                  TG3_TX_RING_SIZE)
123 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
124
125 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
126 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
127
128 /* minimum number of free TX descriptors required to wake up TX process */
129 #define TG3_TX_WAKEUP_THRESH(tp)                ((tp)->tx_pending / 4)
130
131 /* number of ETHTOOL_GSTATS u64's */
132 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
133
134 #define TG3_NUM_TEST            6
135
136 static char version[] __devinitdata =
137         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
138
139 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
140 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
141 MODULE_LICENSE("GPL");
142 MODULE_VERSION(DRV_MODULE_VERSION);
143
144 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
145 module_param(tg3_debug, int, 0);
146 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
147
148 static struct pci_device_id tg3_pci_tbl[] = {
149         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
150         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
151         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
152         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
153         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
154         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
155         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
156         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
157         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
158         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
159         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
160         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
161         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
162         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
163         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
164         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
165         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
166         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
167         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
168         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
169         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
170         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
171         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5785)},
208         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
209         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
210         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
211         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
212         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
213         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
214         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
215         {}
216 };
217
218 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
219
220 static const struct {
221         const char string[ETH_GSTRING_LEN];
222 } ethtool_stats_keys[TG3_NUM_STATS] = {
223         { "rx_octets" },
224         { "rx_fragments" },
225         { "rx_ucast_packets" },
226         { "rx_mcast_packets" },
227         { "rx_bcast_packets" },
228         { "rx_fcs_errors" },
229         { "rx_align_errors" },
230         { "rx_xon_pause_rcvd" },
231         { "rx_xoff_pause_rcvd" },
232         { "rx_mac_ctrl_rcvd" },
233         { "rx_xoff_entered" },
234         { "rx_frame_too_long_errors" },
235         { "rx_jabbers" },
236         { "rx_undersize_packets" },
237         { "rx_in_length_errors" },
238         { "rx_out_length_errors" },
239         { "rx_64_or_less_octet_packets" },
240         { "rx_65_to_127_octet_packets" },
241         { "rx_128_to_255_octet_packets" },
242         { "rx_256_to_511_octet_packets" },
243         { "rx_512_to_1023_octet_packets" },
244         { "rx_1024_to_1522_octet_packets" },
245         { "rx_1523_to_2047_octet_packets" },
246         { "rx_2048_to_4095_octet_packets" },
247         { "rx_4096_to_8191_octet_packets" },
248         { "rx_8192_to_9022_octet_packets" },
249
250         { "tx_octets" },
251         { "tx_collisions" },
252
253         { "tx_xon_sent" },
254         { "tx_xoff_sent" },
255         { "tx_flow_control" },
256         { "tx_mac_errors" },
257         { "tx_single_collisions" },
258         { "tx_mult_collisions" },
259         { "tx_deferred" },
260         { "tx_excessive_collisions" },
261         { "tx_late_collisions" },
262         { "tx_collide_2times" },
263         { "tx_collide_3times" },
264         { "tx_collide_4times" },
265         { "tx_collide_5times" },
266         { "tx_collide_6times" },
267         { "tx_collide_7times" },
268         { "tx_collide_8times" },
269         { "tx_collide_9times" },
270         { "tx_collide_10times" },
271         { "tx_collide_11times" },
272         { "tx_collide_12times" },
273         { "tx_collide_13times" },
274         { "tx_collide_14times" },
275         { "tx_collide_15times" },
276         { "tx_ucast_packets" },
277         { "tx_mcast_packets" },
278         { "tx_bcast_packets" },
279         { "tx_carrier_sense_errors" },
280         { "tx_discards" },
281         { "tx_errors" },
282
283         { "dma_writeq_full" },
284         { "dma_write_prioq_full" },
285         { "rxbds_empty" },
286         { "rx_discards" },
287         { "rx_errors" },
288         { "rx_threshold_hit" },
289
290         { "dma_readq_full" },
291         { "dma_read_prioq_full" },
292         { "tx_comp_queue_full" },
293
294         { "ring_set_send_prod_index" },
295         { "ring_status_update" },
296         { "nic_irqs" },
297         { "nic_avoided_irqs" },
298         { "nic_tx_threshold_hit" }
299 };
300
301 static const struct {
302         const char string[ETH_GSTRING_LEN];
303 } ethtool_test_keys[TG3_NUM_TEST] = {
304         { "nvram test     (online) " },
305         { "link test      (online) " },
306         { "register test  (offline)" },
307         { "memory test    (offline)" },
308         { "loopback test  (offline)" },
309         { "interrupt test (offline)" },
310 };
311
312 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
313 {
314         writel(val, tp->regs + off);
315 }
316
317 static u32 tg3_read32(struct tg3 *tp, u32 off)
318 {
319         return (readl(tp->regs + off));
320 }
321
322 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
323 {
324         writel(val, tp->aperegs + off);
325 }
326
327 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
328 {
329         return (readl(tp->aperegs + off));
330 }
331
332 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
333 {
334         unsigned long flags;
335
336         spin_lock_irqsave(&tp->indirect_lock, flags);
337         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
338         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
339         spin_unlock_irqrestore(&tp->indirect_lock, flags);
340 }
341
342 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
343 {
344         writel(val, tp->regs + off);
345         readl(tp->regs + off);
346 }
347
348 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
349 {
350         unsigned long flags;
351         u32 val;
352
353         spin_lock_irqsave(&tp->indirect_lock, flags);
354         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
355         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
356         spin_unlock_irqrestore(&tp->indirect_lock, flags);
357         return val;
358 }
359
360 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
361 {
362         unsigned long flags;
363
364         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
365                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
366                                        TG3_64BIT_REG_LOW, val);
367                 return;
368         }
369         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
370                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
371                                        TG3_64BIT_REG_LOW, val);
372                 return;
373         }
374
375         spin_lock_irqsave(&tp->indirect_lock, flags);
376         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
377         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
378         spin_unlock_irqrestore(&tp->indirect_lock, flags);
379
380         /* In indirect mode when disabling interrupts, we also need
381          * to clear the interrupt bit in the GRC local ctrl register.
382          */
383         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
384             (val == 0x1)) {
385                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
386                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
387         }
388 }
389
390 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
391 {
392         unsigned long flags;
393         u32 val;
394
395         spin_lock_irqsave(&tp->indirect_lock, flags);
396         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
397         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
398         spin_unlock_irqrestore(&tp->indirect_lock, flags);
399         return val;
400 }
401
402 /* usec_wait specifies the wait time in usec when writing to certain registers
403  * where it is unsafe to read back the register without some delay.
404  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
405  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
406  */
407 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
408 {
409         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
410             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
411                 /* Non-posted methods */
412                 tp->write32(tp, off, val);
413         else {
414                 /* Posted method */
415                 tg3_write32(tp, off, val);
416                 if (usec_wait)
417                         udelay(usec_wait);
418                 tp->read32(tp, off);
419         }
420         /* Wait again after the read for the posted method to guarantee that
421          * the wait time is met.
422          */
423         if (usec_wait)
424                 udelay(usec_wait);
425 }
426
427 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
428 {
429         tp->write32_mbox(tp, off, val);
430         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
431             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
432                 tp->read32_mbox(tp, off);
433 }
434
435 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
436 {
437         void __iomem *mbox = tp->regs + off;
438         writel(val, mbox);
439         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
440                 writel(val, mbox);
441         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
442                 readl(mbox);
443 }
444
445 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
446 {
447         return (readl(tp->regs + off + GRCMBOX_BASE));
448 }
449
450 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
451 {
452         writel(val, tp->regs + off + GRCMBOX_BASE);
453 }
454
455 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
456 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
457 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
458 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
459 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
460
461 #define tw32(reg,val)           tp->write32(tp, reg, val)
462 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
463 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
464 #define tr32(reg)               tp->read32(tp, reg)
465
466 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
467 {
468         unsigned long flags;
469
470         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
471             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
472                 return;
473
474         spin_lock_irqsave(&tp->indirect_lock, flags);
475         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
476                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
477                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
478
479                 /* Always leave this as zero. */
480                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
481         } else {
482                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
483                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
484
485                 /* Always leave this as zero. */
486                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
487         }
488         spin_unlock_irqrestore(&tp->indirect_lock, flags);
489 }
490
491 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
492 {
493         unsigned long flags;
494
495         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
496             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
497                 *val = 0;
498                 return;
499         }
500
501         spin_lock_irqsave(&tp->indirect_lock, flags);
502         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
503                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
504                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
505
506                 /* Always leave this as zero. */
507                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
508         } else {
509                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
510                 *val = tr32(TG3PCI_MEM_WIN_DATA);
511
512                 /* Always leave this as zero. */
513                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
514         }
515         spin_unlock_irqrestore(&tp->indirect_lock, flags);
516 }
517
518 static void tg3_ape_lock_init(struct tg3 *tp)
519 {
520         int i;
521
522         /* Make sure the driver hasn't any stale locks. */
523         for (i = 0; i < 8; i++)
524                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
525                                 APE_LOCK_GRANT_DRIVER);
526 }
527
528 static int tg3_ape_lock(struct tg3 *tp, int locknum)
529 {
530         int i, off;
531         int ret = 0;
532         u32 status;
533
534         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
535                 return 0;
536
537         switch (locknum) {
538                 case TG3_APE_LOCK_MEM:
539                         break;
540                 default:
541                         return -EINVAL;
542         }
543
544         off = 4 * locknum;
545
546         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
547
548         /* Wait for up to 1 millisecond to acquire lock. */
549         for (i = 0; i < 100; i++) {
550                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
551                 if (status == APE_LOCK_GRANT_DRIVER)
552                         break;
553                 udelay(10);
554         }
555
556         if (status != APE_LOCK_GRANT_DRIVER) {
557                 /* Revoke the lock request. */
558                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
559                                 APE_LOCK_GRANT_DRIVER);
560
561                 ret = -EBUSY;
562         }
563
564         return ret;
565 }
566
567 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
568 {
569         int off;
570
571         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
572                 return;
573
574         switch (locknum) {
575                 case TG3_APE_LOCK_MEM:
576                         break;
577                 default:
578                         return;
579         }
580
581         off = 4 * locknum;
582         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
583 }
584
585 static void tg3_disable_ints(struct tg3 *tp)
586 {
587         tw32(TG3PCI_MISC_HOST_CTRL,
588              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
589         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
590 }
591
592 static inline void tg3_cond_int(struct tg3 *tp)
593 {
594         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
595             (tp->hw_status->status & SD_STATUS_UPDATED))
596                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
597         else
598                 tw32(HOSTCC_MODE, tp->coalesce_mode |
599                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
600 }
601
602 static void tg3_enable_ints(struct tg3 *tp)
603 {
604         tp->irq_sync = 0;
605         wmb();
606
607         tw32(TG3PCI_MISC_HOST_CTRL,
608              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
609         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
610                        (tp->last_tag << 24));
611         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
612                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
613                                (tp->last_tag << 24));
614         tg3_cond_int(tp);
615 }
616
617 static inline unsigned int tg3_has_work(struct tg3 *tp)
618 {
619         struct tg3_hw_status *sblk = tp->hw_status;
620         unsigned int work_exists = 0;
621
622         /* check for phy events */
623         if (!(tp->tg3_flags &
624               (TG3_FLAG_USE_LINKCHG_REG |
625                TG3_FLAG_POLL_SERDES))) {
626                 if (sblk->status & SD_STATUS_LINK_CHG)
627                         work_exists = 1;
628         }
629         /* check for RX/TX work to do */
630         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
631             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
632                 work_exists = 1;
633
634         return work_exists;
635 }
636
637 /* tg3_restart_ints
638  *  similar to tg3_enable_ints, but it accurately determines whether there
639  *  is new work pending and can return without flushing the PIO write
640  *  which reenables interrupts
641  */
642 static void tg3_restart_ints(struct tg3 *tp)
643 {
644         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
645                      tp->last_tag << 24);
646         mmiowb();
647
648         /* When doing tagged status, this work check is unnecessary.
649          * The last_tag we write above tells the chip which piece of
650          * work we've completed.
651          */
652         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
653             tg3_has_work(tp))
654                 tw32(HOSTCC_MODE, tp->coalesce_mode |
655                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
656 }
657
658 static inline void tg3_netif_stop(struct tg3 *tp)
659 {
660         tp->dev->trans_start = jiffies; /* prevent tx timeout */
661         napi_disable(&tp->napi);
662         netif_tx_disable(tp->dev);
663 }
664
665 static inline void tg3_netif_start(struct tg3 *tp)
666 {
667         netif_wake_queue(tp->dev);
668         /* NOTE: unconditional netif_wake_queue is only appropriate
669          * so long as all callers are assured to have free tx slots
670          * (such as after tg3_init_hw)
671          */
672         napi_enable(&tp->napi);
673         tp->hw_status->status |= SD_STATUS_UPDATED;
674         tg3_enable_ints(tp);
675 }
676
677 static void tg3_switch_clocks(struct tg3 *tp)
678 {
679         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
680         u32 orig_clock_ctrl;
681
682         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
683             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
684                 return;
685
686         orig_clock_ctrl = clock_ctrl;
687         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
688                        CLOCK_CTRL_CLKRUN_OENABLE |
689                        0x1f);
690         tp->pci_clock_ctrl = clock_ctrl;
691
692         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
693                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
694                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
695                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
696                 }
697         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
698                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
699                             clock_ctrl |
700                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
701                             40);
702                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
703                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
704                             40);
705         }
706         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
707 }
708
709 #define PHY_BUSY_LOOPS  5000
710
711 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
712 {
713         u32 frame_val;
714         unsigned int loops;
715         int ret;
716
717         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
718                 tw32_f(MAC_MI_MODE,
719                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
720                 udelay(80);
721         }
722
723         *val = 0x0;
724
725         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
726                       MI_COM_PHY_ADDR_MASK);
727         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
728                       MI_COM_REG_ADDR_MASK);
729         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
730
731         tw32_f(MAC_MI_COM, frame_val);
732
733         loops = PHY_BUSY_LOOPS;
734         while (loops != 0) {
735                 udelay(10);
736                 frame_val = tr32(MAC_MI_COM);
737
738                 if ((frame_val & MI_COM_BUSY) == 0) {
739                         udelay(5);
740                         frame_val = tr32(MAC_MI_COM);
741                         break;
742                 }
743                 loops -= 1;
744         }
745
746         ret = -EBUSY;
747         if (loops != 0) {
748                 *val = frame_val & MI_COM_DATA_MASK;
749                 ret = 0;
750         }
751
752         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
753                 tw32_f(MAC_MI_MODE, tp->mi_mode);
754                 udelay(80);
755         }
756
757         return ret;
758 }
759
760 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
761 {
762         u32 frame_val;
763         unsigned int loops;
764         int ret;
765
766         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
767             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
768                 return 0;
769
770         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
771                 tw32_f(MAC_MI_MODE,
772                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
773                 udelay(80);
774         }
775
776         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
777                       MI_COM_PHY_ADDR_MASK);
778         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
779                       MI_COM_REG_ADDR_MASK);
780         frame_val |= (val & MI_COM_DATA_MASK);
781         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
782
783         tw32_f(MAC_MI_COM, frame_val);
784
785         loops = PHY_BUSY_LOOPS;
786         while (loops != 0) {
787                 udelay(10);
788                 frame_val = tr32(MAC_MI_COM);
789                 if ((frame_val & MI_COM_BUSY) == 0) {
790                         udelay(5);
791                         frame_val = tr32(MAC_MI_COM);
792                         break;
793                 }
794                 loops -= 1;
795         }
796
797         ret = -EBUSY;
798         if (loops != 0)
799                 ret = 0;
800
801         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
802                 tw32_f(MAC_MI_MODE, tp->mi_mode);
803                 udelay(80);
804         }
805
806         return ret;
807 }
808
809 static int tg3_bmcr_reset(struct tg3 *tp)
810 {
811         u32 phy_control;
812         int limit, err;
813
814         /* OK, reset it, and poll the BMCR_RESET bit until it
815          * clears or we time out.
816          */
817         phy_control = BMCR_RESET;
818         err = tg3_writephy(tp, MII_BMCR, phy_control);
819         if (err != 0)
820                 return -EBUSY;
821
822         limit = 5000;
823         while (limit--) {
824                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
825                 if (err != 0)
826                         return -EBUSY;
827
828                 if ((phy_control & BMCR_RESET) == 0) {
829                         udelay(40);
830                         break;
831                 }
832                 udelay(10);
833         }
834         if (limit <= 0)
835                 return -EBUSY;
836
837         return 0;
838 }
839
840 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
841 {
842         struct tg3 *tp = (struct tg3 *)bp->priv;
843         u32 val;
844
845         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
846                 return -EAGAIN;
847
848         if (tg3_readphy(tp, reg, &val))
849                 return -EIO;
850
851         return val;
852 }
853
854 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
855 {
856         struct tg3 *tp = (struct tg3 *)bp->priv;
857
858         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
859                 return -EAGAIN;
860
861         if (tg3_writephy(tp, reg, val))
862                 return -EIO;
863
864         return 0;
865 }
866
867 static int tg3_mdio_reset(struct mii_bus *bp)
868 {
869         return 0;
870 }
871
872 static void tg3_mdio_start(struct tg3 *tp)
873 {
874         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
875                 mutex_lock(&tp->mdio_bus.mdio_lock);
876                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
877                 mutex_unlock(&tp->mdio_bus.mdio_lock);
878         }
879
880         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
881         tw32_f(MAC_MI_MODE, tp->mi_mode);
882         udelay(80);
883 }
884
885 static void tg3_mdio_stop(struct tg3 *tp)
886 {
887         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
888                 mutex_lock(&tp->mdio_bus.mdio_lock);
889                 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
890                 mutex_unlock(&tp->mdio_bus.mdio_lock);
891         }
892 }
893
894 static int tg3_mdio_init(struct tg3 *tp)
895 {
896         int i;
897         u32 reg;
898         struct mii_bus *mdio_bus = &tp->mdio_bus;
899
900         tg3_mdio_start(tp);
901
902         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
903             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
904                 return 0;
905
906         memset(mdio_bus, 0, sizeof(*mdio_bus));
907
908         mdio_bus->name     = "tg3 mdio bus";
909         snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "%x",
910                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
911         mdio_bus->priv     = tp;
912         mdio_bus->dev      = &tp->pdev->dev;
913         mdio_bus->read     = &tg3_mdio_read;
914         mdio_bus->write    = &tg3_mdio_write;
915         mdio_bus->reset    = &tg3_mdio_reset;
916         mdio_bus->phy_mask = ~(1 << PHY_ADDR);
917         mdio_bus->irq      = &tp->mdio_irq[0];
918
919         for (i = 0; i < PHY_MAX_ADDR; i++)
920                 mdio_bus->irq[i] = PHY_POLL;
921
922         /* The bus registration will look for all the PHYs on the mdio bus.
923          * Unfortunately, it does not ensure the PHY is powered up before
924          * accessing the PHY ID registers.  A chip reset is the
925          * quickest way to bring the device back to an operational state..
926          */
927         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
928                 tg3_bmcr_reset(tp);
929
930         i = mdiobus_register(mdio_bus);
931         if (!i)
932                 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
933         else
934                 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
935                         tp->dev->name, i);
936
937         return i;
938 }
939
940 static void tg3_mdio_fini(struct tg3 *tp)
941 {
942         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
943                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
944                 mdiobus_unregister(&tp->mdio_bus);
945                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
946         }
947 }
948
949 /* tp->lock is held. */
950 static void tg3_wait_for_event_ack(struct tg3 *tp)
951 {
952         int i;
953
954         /* Wait for up to 2.5 milliseconds */
955         for (i = 0; i < 250000; i++) {
956                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
957                         break;
958                 udelay(10);
959         }
960 }
961
962 /* tp->lock is held. */
963 static void tg3_ump_link_report(struct tg3 *tp)
964 {
965         u32 reg;
966         u32 val;
967
968         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
969             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
970                 return;
971
972         tg3_wait_for_event_ack(tp);
973
974         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
975
976         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
977
978         val = 0;
979         if (!tg3_readphy(tp, MII_BMCR, &reg))
980                 val = reg << 16;
981         if (!tg3_readphy(tp, MII_BMSR, &reg))
982                 val |= (reg & 0xffff);
983         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
984
985         val = 0;
986         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
987                 val = reg << 16;
988         if (!tg3_readphy(tp, MII_LPA, &reg))
989                 val |= (reg & 0xffff);
990         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
991
992         val = 0;
993         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
994                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
995                         val = reg << 16;
996                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
997                         val |= (reg & 0xffff);
998         }
999         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1000
1001         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1002                 val = reg << 16;
1003         else
1004                 val = 0;
1005         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1006
1007         val = tr32(GRC_RX_CPU_EVENT);
1008         val |= GRC_RX_CPU_DRIVER_EVENT;
1009         tw32_f(GRC_RX_CPU_EVENT, val);
1010 }
1011
1012 static void tg3_link_report(struct tg3 *tp)
1013 {
1014         if (!netif_carrier_ok(tp->dev)) {
1015                 if (netif_msg_link(tp))
1016                         printk(KERN_INFO PFX "%s: Link is down.\n",
1017                                tp->dev->name);
1018                 tg3_ump_link_report(tp);
1019         } else if (netif_msg_link(tp)) {
1020                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1021                        tp->dev->name,
1022                        (tp->link_config.active_speed == SPEED_1000 ?
1023                         1000 :
1024                         (tp->link_config.active_speed == SPEED_100 ?
1025                          100 : 10)),
1026                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1027                         "full" : "half"));
1028
1029                 printk(KERN_INFO PFX
1030                        "%s: Flow control is %s for TX and %s for RX.\n",
1031                        tp->dev->name,
1032                        (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_TX) ?
1033                        "on" : "off",
1034                        (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_RX) ?
1035                        "on" : "off");
1036                 tg3_ump_link_report(tp);
1037         }
1038 }
1039
1040 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1041 {
1042         u16 miireg;
1043
1044         if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
1045                 miireg = ADVERTISE_PAUSE_CAP;
1046         else if (flow_ctrl & TG3_FLOW_CTRL_TX)
1047                 miireg = ADVERTISE_PAUSE_ASYM;
1048         else if (flow_ctrl & TG3_FLOW_CTRL_RX)
1049                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1050         else
1051                 miireg = 0;
1052
1053         return miireg;
1054 }
1055
1056 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1057 {
1058         u16 miireg;
1059
1060         if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
1061                 miireg = ADVERTISE_1000XPAUSE;
1062         else if (flow_ctrl & TG3_FLOW_CTRL_TX)
1063                 miireg = ADVERTISE_1000XPSE_ASYM;
1064         else if (flow_ctrl & TG3_FLOW_CTRL_RX)
1065                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1066         else
1067                 miireg = 0;
1068
1069         return miireg;
1070 }
1071
1072 static u8 tg3_resolve_flowctrl_1000T(u16 lcladv, u16 rmtadv)
1073 {
1074         u8 cap = 0;
1075
1076         if (lcladv & ADVERTISE_PAUSE_CAP) {
1077                 if (lcladv & ADVERTISE_PAUSE_ASYM) {
1078                         if (rmtadv & LPA_PAUSE_CAP)
1079                                 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1080                         else if (rmtadv & LPA_PAUSE_ASYM)
1081                                 cap = TG3_FLOW_CTRL_RX;
1082                 } else {
1083                         if (rmtadv & LPA_PAUSE_CAP)
1084                                 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1085                 }
1086         } else if (lcladv & ADVERTISE_PAUSE_ASYM) {
1087                 if ((rmtadv & LPA_PAUSE_CAP) && (rmtadv & LPA_PAUSE_ASYM))
1088                         cap = TG3_FLOW_CTRL_TX;
1089         }
1090
1091         return cap;
1092 }
1093
1094 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1095 {
1096         u8 cap = 0;
1097
1098         if (lcladv & ADVERTISE_1000XPAUSE) {
1099                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1100                         if (rmtadv & LPA_1000XPAUSE)
1101                                 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1102                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1103                                 cap = TG3_FLOW_CTRL_RX;
1104                 } else {
1105                         if (rmtadv & LPA_1000XPAUSE)
1106                                 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1107                 }
1108         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1109                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1110                         cap = TG3_FLOW_CTRL_TX;
1111         }
1112
1113         return cap;
1114 }
1115
1116 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1117 {
1118         u8 autoneg;
1119         u8 flowctrl = 0;
1120         u32 old_rx_mode = tp->rx_mode;
1121         u32 old_tx_mode = tp->tx_mode;
1122
1123         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1124                 autoneg = tp->mdio_bus.phy_map[PHY_ADDR]->autoneg;
1125         else
1126                 autoneg = tp->link_config.autoneg;
1127
1128         if (autoneg == AUTONEG_ENABLE &&
1129             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1130                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1131                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1132                 else
1133                         flowctrl = tg3_resolve_flowctrl_1000T(lcladv, rmtadv);
1134         } else
1135                 flowctrl = tp->link_config.flowctrl;
1136
1137         tp->link_config.active_flowctrl = flowctrl;
1138
1139         if (flowctrl & TG3_FLOW_CTRL_RX)
1140                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1141         else
1142                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1143
1144         if (old_rx_mode != tp->rx_mode)
1145                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1146
1147         if (flowctrl & TG3_FLOW_CTRL_TX)
1148                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1149         else
1150                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1151
1152         if (old_tx_mode != tp->tx_mode)
1153                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1154 }
1155
1156 static void tg3_adjust_link(struct net_device *dev)
1157 {
1158         u8 oldflowctrl, linkmesg = 0;
1159         u32 mac_mode, lcl_adv, rmt_adv;
1160         struct tg3 *tp = netdev_priv(dev);
1161         struct phy_device *phydev = tp->mdio_bus.phy_map[PHY_ADDR];
1162
1163         spin_lock(&tp->lock);
1164
1165         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1166                                     MAC_MODE_HALF_DUPLEX);
1167
1168         oldflowctrl = tp->link_config.active_flowctrl;
1169
1170         if (phydev->link) {
1171                 lcl_adv = 0;
1172                 rmt_adv = 0;
1173
1174                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1175                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1176                 else
1177                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1178
1179                 if (phydev->duplex == DUPLEX_HALF)
1180                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1181                 else {
1182                         lcl_adv = tg3_advert_flowctrl_1000T(
1183                                   tp->link_config.flowctrl);
1184
1185                         if (phydev->pause)
1186                                 rmt_adv = LPA_PAUSE_CAP;
1187                         if (phydev->asym_pause)
1188                                 rmt_adv |= LPA_PAUSE_ASYM;
1189                 }
1190
1191                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1192         } else
1193                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1194
1195         if (mac_mode != tp->mac_mode) {
1196                 tp->mac_mode = mac_mode;
1197                 tw32_f(MAC_MODE, tp->mac_mode);
1198                 udelay(40);
1199         }
1200
1201         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1202                 tw32(MAC_TX_LENGTHS,
1203                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1204                       (6 << TX_LENGTHS_IPG_SHIFT) |
1205                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1206         else
1207                 tw32(MAC_TX_LENGTHS,
1208                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1209                       (6 << TX_LENGTHS_IPG_SHIFT) |
1210                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1211
1212         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1213             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1214             phydev->speed != tp->link_config.active_speed ||
1215             phydev->duplex != tp->link_config.active_duplex ||
1216             oldflowctrl != tp->link_config.active_flowctrl)
1217             linkmesg = 1;
1218
1219         tp->link_config.active_speed = phydev->speed;
1220         tp->link_config.active_duplex = phydev->duplex;
1221
1222         spin_unlock(&tp->lock);
1223
1224         if (linkmesg)
1225                 tg3_link_report(tp);
1226 }
1227
1228 static int tg3_phy_init(struct tg3 *tp)
1229 {
1230         struct phy_device *phydev;
1231
1232         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1233                 return 0;
1234
1235         /* Bring the PHY back to a known state. */
1236         tg3_bmcr_reset(tp);
1237
1238         phydev = tp->mdio_bus.phy_map[PHY_ADDR];
1239
1240         /* Attach the MAC to the PHY. */
1241         phydev = phy_connect(tp->dev, phydev->dev.bus_id,
1242                              tg3_adjust_link, 0, phydev->interface);
1243         if (IS_ERR(phydev)) {
1244                 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1245                 return PTR_ERR(phydev);
1246         }
1247
1248         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1249
1250         /* Mask with MAC supported features. */
1251         phydev->supported &= (PHY_GBIT_FEATURES |
1252                               SUPPORTED_Pause |
1253                               SUPPORTED_Asym_Pause);
1254
1255         phydev->advertising = phydev->supported;
1256
1257         printk(KERN_INFO
1258                "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
1259                tp->dev->name, phydev->drv->name, phydev->dev.bus_id);
1260
1261         return 0;
1262 }
1263
1264 static void tg3_phy_start(struct tg3 *tp)
1265 {
1266         struct phy_device *phydev;
1267
1268         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1269                 return;
1270
1271         phydev = tp->mdio_bus.phy_map[PHY_ADDR];
1272
1273         if (tp->link_config.phy_is_low_power) {
1274                 tp->link_config.phy_is_low_power = 0;
1275                 phydev->speed = tp->link_config.orig_speed;
1276                 phydev->duplex = tp->link_config.orig_duplex;
1277                 phydev->autoneg = tp->link_config.orig_autoneg;
1278                 phydev->advertising = tp->link_config.orig_advertising;
1279         }
1280
1281         phy_start(phydev);
1282
1283         phy_start_aneg(phydev);
1284 }
1285
1286 static void tg3_phy_stop(struct tg3 *tp)
1287 {
1288         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1289                 return;
1290
1291         phy_stop(tp->mdio_bus.phy_map[PHY_ADDR]);
1292 }
1293
1294 static void tg3_phy_fini(struct tg3 *tp)
1295 {
1296         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1297                 phy_disconnect(tp->mdio_bus.phy_map[PHY_ADDR]);
1298                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1299         }
1300 }
1301
1302 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1303 {
1304         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1305         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1306 }
1307
1308 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1309 {
1310         u32 phy;
1311
1312         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1313             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1314                 return;
1315
1316         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1317                 u32 ephy;
1318
1319                 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
1320                         tg3_writephy(tp, MII_TG3_EPHY_TEST,
1321                                      ephy | MII_TG3_EPHY_SHADOW_EN);
1322                         if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
1323                                 if (enable)
1324                                         phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
1325                                 else
1326                                         phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
1327                                 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
1328                         }
1329                         tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
1330                 }
1331         } else {
1332                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1333                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1334                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1335                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1336                         if (enable)
1337                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1338                         else
1339                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1340                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1341                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1342                 }
1343         }
1344 }
1345
1346 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1347 {
1348         u32 val;
1349
1350         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1351                 return;
1352
1353         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1354             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1355                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1356                              (val | (1 << 15) | (1 << 4)));
1357 }
1358
1359 static void tg3_phy_apply_otp(struct tg3 *tp)
1360 {
1361         u32 otp, phy;
1362
1363         if (!tp->phy_otp)
1364                 return;
1365
1366         otp = tp->phy_otp;
1367
1368         /* Enable SM_DSP clock and tx 6dB coding. */
1369         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1370               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1371               MII_TG3_AUXCTL_ACTL_TX_6DB;
1372         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1373
1374         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1375         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1376         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1377
1378         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1379               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1380         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1381
1382         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1383         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1384         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1385
1386         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1387         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1388
1389         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1390         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1391
1392         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1393               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1394         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1395
1396         /* Turn off SM_DSP clock. */
1397         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1398               MII_TG3_AUXCTL_ACTL_TX_6DB;
1399         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1400 }
1401
1402 static int tg3_wait_macro_done(struct tg3 *tp)
1403 {
1404         int limit = 100;
1405
1406         while (limit--) {
1407                 u32 tmp32;
1408
1409                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1410                         if ((tmp32 & 0x1000) == 0)
1411                                 break;
1412                 }
1413         }
1414         if (limit <= 0)
1415                 return -EBUSY;
1416
1417         return 0;
1418 }
1419
1420 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1421 {
1422         static const u32 test_pat[4][6] = {
1423         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1424         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1425         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1426         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1427         };
1428         int chan;
1429
1430         for (chan = 0; chan < 4; chan++) {
1431                 int i;
1432
1433                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1434                              (chan * 0x2000) | 0x0200);
1435                 tg3_writephy(tp, 0x16, 0x0002);
1436
1437                 for (i = 0; i < 6; i++)
1438                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1439                                      test_pat[chan][i]);
1440
1441                 tg3_writephy(tp, 0x16, 0x0202);
1442                 if (tg3_wait_macro_done(tp)) {
1443                         *resetp = 1;
1444                         return -EBUSY;
1445                 }
1446
1447                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1448                              (chan * 0x2000) | 0x0200);
1449                 tg3_writephy(tp, 0x16, 0x0082);
1450                 if (tg3_wait_macro_done(tp)) {
1451                         *resetp = 1;
1452                         return -EBUSY;
1453                 }
1454
1455                 tg3_writephy(tp, 0x16, 0x0802);
1456                 if (tg3_wait_macro_done(tp)) {
1457                         *resetp = 1;
1458                         return -EBUSY;
1459                 }
1460
1461                 for (i = 0; i < 6; i += 2) {
1462                         u32 low, high;
1463
1464                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1465                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1466                             tg3_wait_macro_done(tp)) {
1467                                 *resetp = 1;
1468                                 return -EBUSY;
1469                         }
1470                         low &= 0x7fff;
1471                         high &= 0x000f;
1472                         if (low != test_pat[chan][i] ||
1473                             high != test_pat[chan][i+1]) {
1474                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1475                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1476                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1477
1478                                 return -EBUSY;
1479                         }
1480                 }
1481         }
1482
1483         return 0;
1484 }
1485
1486 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1487 {
1488         int chan;
1489
1490         for (chan = 0; chan < 4; chan++) {
1491                 int i;
1492
1493                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1494                              (chan * 0x2000) | 0x0200);
1495                 tg3_writephy(tp, 0x16, 0x0002);
1496                 for (i = 0; i < 6; i++)
1497                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1498                 tg3_writephy(tp, 0x16, 0x0202);
1499                 if (tg3_wait_macro_done(tp))
1500                         return -EBUSY;
1501         }
1502
1503         return 0;
1504 }
1505
1506 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1507 {
1508         u32 reg32, phy9_orig;
1509         int retries, do_phy_reset, err;
1510
1511         retries = 10;
1512         do_phy_reset = 1;
1513         do {
1514                 if (do_phy_reset) {
1515                         err = tg3_bmcr_reset(tp);
1516                         if (err)
1517                                 return err;
1518                         do_phy_reset = 0;
1519                 }
1520
1521                 /* Disable transmitter and interrupt.  */
1522                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1523                         continue;
1524
1525                 reg32 |= 0x3000;
1526                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1527
1528                 /* Set full-duplex, 1000 mbps.  */
1529                 tg3_writephy(tp, MII_BMCR,
1530                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1531
1532                 /* Set to master mode.  */
1533                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1534                         continue;
1535
1536                 tg3_writephy(tp, MII_TG3_CTRL,
1537                              (MII_TG3_CTRL_AS_MASTER |
1538                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1539
1540                 /* Enable SM_DSP_CLOCK and 6dB.  */
1541                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1542
1543                 /* Block the PHY control access.  */
1544                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1545                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1546
1547                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1548                 if (!err)
1549                         break;
1550         } while (--retries);
1551
1552         err = tg3_phy_reset_chanpat(tp);
1553         if (err)
1554                 return err;
1555
1556         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1557         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1558
1559         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1560         tg3_writephy(tp, 0x16, 0x0000);
1561
1562         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1563             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1564                 /* Set Extended packet length bit for jumbo frames */
1565                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1566         }
1567         else {
1568                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1569         }
1570
1571         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1572
1573         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1574                 reg32 &= ~0x3000;
1575                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1576         } else if (!err)
1577                 err = -EBUSY;
1578
1579         return err;
1580 }
1581
1582 /* This will reset the tigon3 PHY if there is no valid
1583  * link unless the FORCE argument is non-zero.
1584  */
1585 static int tg3_phy_reset(struct tg3 *tp)
1586 {
1587         u32 cpmuctrl;
1588         u32 phy_status;
1589         int err;
1590
1591         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1592                 u32 val;
1593
1594                 val = tr32(GRC_MISC_CFG);
1595                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1596                 udelay(40);
1597         }
1598         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1599         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1600         if (err != 0)
1601                 return -EBUSY;
1602
1603         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1604                 netif_carrier_off(tp->dev);
1605                 tg3_link_report(tp);
1606         }
1607
1608         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1609             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1610             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1611                 err = tg3_phy_reset_5703_4_5(tp);
1612                 if (err)
1613                         return err;
1614                 goto out;
1615         }
1616
1617         cpmuctrl = 0;
1618         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1619             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1620                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1621                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1622                         tw32(TG3_CPMU_CTRL,
1623                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1624         }
1625
1626         err = tg3_bmcr_reset(tp);
1627         if (err)
1628                 return err;
1629
1630         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1631                 u32 phy;
1632
1633                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1634                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1635
1636                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1637         }
1638
1639         if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
1640                 u32 val;
1641
1642                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1643                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1644                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1645                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1646                         udelay(40);
1647                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1648                 }
1649
1650                 /* Disable GPHY autopowerdown. */
1651                 tg3_writephy(tp, MII_TG3_MISC_SHDW,
1652                              MII_TG3_MISC_SHDW_WREN |
1653                              MII_TG3_MISC_SHDW_APD_SEL |
1654                              MII_TG3_MISC_SHDW_APD_WKTM_84MS);
1655         }
1656
1657         tg3_phy_apply_otp(tp);
1658
1659 out:
1660         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1661                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1662                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1663                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1664                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1665                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1666                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1667         }
1668         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1669                 tg3_writephy(tp, 0x1c, 0x8d68);
1670                 tg3_writephy(tp, 0x1c, 0x8d68);
1671         }
1672         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1673                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1674                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1675                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1676                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1677                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1678                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1679                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1680                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1681         }
1682         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1683                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1684                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1685                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1686                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1687                         tg3_writephy(tp, MII_TG3_TEST1,
1688                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1689                 } else
1690                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1691                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1692         }
1693         /* Set Extended packet length bit (bit 14) on all chips that */
1694         /* support jumbo frames */
1695         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1696                 /* Cannot do read-modify-write on 5401 */
1697                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1698         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1699                 u32 phy_reg;
1700
1701                 /* Set bit 14 with read-modify-write to preserve other bits */
1702                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1703                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1704                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1705         }
1706
1707         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1708          * jumbo frames transmission.
1709          */
1710         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1711                 u32 phy_reg;
1712
1713                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1714                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1715                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1716         }
1717
1718         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1719                 /* adjust output voltage */
1720                 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1721         }
1722
1723         tg3_phy_toggle_automdix(tp, 1);
1724         tg3_phy_set_wirespeed(tp);
1725         return 0;
1726 }
1727
1728 static void tg3_frob_aux_power(struct tg3 *tp)
1729 {
1730         struct tg3 *tp_peer = tp;
1731
1732         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1733                 return;
1734
1735         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1736             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1737                 struct net_device *dev_peer;
1738
1739                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1740                 /* remove_one() may have been run on the peer. */
1741                 if (!dev_peer)
1742                         tp_peer = tp;
1743                 else
1744                         tp_peer = netdev_priv(dev_peer);
1745         }
1746
1747         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1748             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1749             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1750             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1751                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1752                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1753                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1754                                     (GRC_LCLCTRL_GPIO_OE0 |
1755                                      GRC_LCLCTRL_GPIO_OE1 |
1756                                      GRC_LCLCTRL_GPIO_OE2 |
1757                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1758                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1759                                     100);
1760                 } else {
1761                         u32 no_gpio2;
1762                         u32 grc_local_ctrl = 0;
1763
1764                         if (tp_peer != tp &&
1765                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1766                                 return;
1767
1768                         /* Workaround to prevent overdrawing Amps. */
1769                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1770                             ASIC_REV_5714) {
1771                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1772                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1773                                             grc_local_ctrl, 100);
1774                         }
1775
1776                         /* On 5753 and variants, GPIO2 cannot be used. */
1777                         no_gpio2 = tp->nic_sram_data_cfg &
1778                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1779
1780                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1781                                          GRC_LCLCTRL_GPIO_OE1 |
1782                                          GRC_LCLCTRL_GPIO_OE2 |
1783                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1784                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1785                         if (no_gpio2) {
1786                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1787                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
1788                         }
1789                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1790                                                     grc_local_ctrl, 100);
1791
1792                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1793
1794                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1795                                                     grc_local_ctrl, 100);
1796
1797                         if (!no_gpio2) {
1798                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1799                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1800                                             grc_local_ctrl, 100);
1801                         }
1802                 }
1803         } else {
1804                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1805                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1806                         if (tp_peer != tp &&
1807                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1808                                 return;
1809
1810                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1811                                     (GRC_LCLCTRL_GPIO_OE1 |
1812                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1813
1814                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1815                                     GRC_LCLCTRL_GPIO_OE1, 100);
1816
1817                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1818                                     (GRC_LCLCTRL_GPIO_OE1 |
1819                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1820                 }
1821         }
1822 }
1823
1824 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
1825 {
1826         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
1827                 return 1;
1828         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
1829                 if (speed != SPEED_10)
1830                         return 1;
1831         } else if (speed == SPEED_10)
1832                 return 1;
1833
1834         return 0;
1835 }
1836
1837 static int tg3_setup_phy(struct tg3 *, int);
1838
1839 #define RESET_KIND_SHUTDOWN     0
1840 #define RESET_KIND_INIT         1
1841 #define RESET_KIND_SUSPEND      2
1842
1843 static void tg3_write_sig_post_reset(struct tg3 *, int);
1844 static int tg3_halt_cpu(struct tg3 *, u32);
1845 static int tg3_nvram_lock(struct tg3 *);
1846 static void tg3_nvram_unlock(struct tg3 *);
1847
1848 static void tg3_power_down_phy(struct tg3 *tp)
1849 {
1850         u32 val;
1851
1852         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1853                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1854                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
1855                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
1856
1857                         sg_dig_ctrl |=
1858                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
1859                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
1860                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
1861                 }
1862                 return;
1863         }
1864
1865         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1866                 tg3_bmcr_reset(tp);
1867                 val = tr32(GRC_MISC_CFG);
1868                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1869                 udelay(40);
1870                 return;
1871         } else if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
1872                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1873                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1874                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1875         }
1876
1877         /* The PHY should not be powered down on some chips because
1878          * of bugs.
1879          */
1880         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1881             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1882             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1883              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1884                 return;
1885
1886         if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
1887                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1888                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1889                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
1890                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1891         }
1892
1893         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1894 }
1895
1896 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1897 {
1898         u32 misc_host_ctrl;
1899         u16 power_control, power_caps;
1900         int pm = tp->pm_cap;
1901
1902         /* Make sure register accesses (indirect or otherwise)
1903          * will function correctly.
1904          */
1905         pci_write_config_dword(tp->pdev,
1906                                TG3PCI_MISC_HOST_CTRL,
1907                                tp->misc_host_ctrl);
1908
1909         pci_read_config_word(tp->pdev,
1910                              pm + PCI_PM_CTRL,
1911                              &power_control);
1912         power_control |= PCI_PM_CTRL_PME_STATUS;
1913         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1914         switch (state) {
1915         case PCI_D0:
1916                 power_control |= 0;
1917                 pci_write_config_word(tp->pdev,
1918                                       pm + PCI_PM_CTRL,
1919                                       power_control);
1920                 udelay(100);    /* Delay after power state change */
1921
1922                 /* Switch out of Vaux if it is a NIC */
1923                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
1924                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1925
1926                 return 0;
1927
1928         case PCI_D1:
1929                 power_control |= 1;
1930                 break;
1931
1932         case PCI_D2:
1933                 power_control |= 2;
1934                 break;
1935
1936         case PCI_D3hot:
1937                 power_control |= 3;
1938                 break;
1939
1940         default:
1941                 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1942                        "requested.\n",
1943                        tp->dev->name, state);
1944                 return -EINVAL;
1945         };
1946
1947         power_control |= PCI_PM_CTRL_PME_ENABLE;
1948
1949         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1950         tw32(TG3PCI_MISC_HOST_CTRL,
1951              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1952
1953         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
1954                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
1955                     !tp->link_config.phy_is_low_power) {
1956                         struct phy_device *phydev;
1957                         u32 advertising;
1958
1959                         phydev = tp->mdio_bus.phy_map[PHY_ADDR];
1960
1961                         tp->link_config.phy_is_low_power = 1;
1962
1963                         tp->link_config.orig_speed = phydev->speed;
1964                         tp->link_config.orig_duplex = phydev->duplex;
1965                         tp->link_config.orig_autoneg = phydev->autoneg;
1966                         tp->link_config.orig_advertising = phydev->advertising;
1967
1968                         advertising = ADVERTISED_TP |
1969                                       ADVERTISED_Pause |
1970                                       ADVERTISED_Autoneg |
1971                                       ADVERTISED_10baseT_Half;
1972
1973                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
1974                             (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
1975                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1976                                         advertising |=
1977                                                 ADVERTISED_100baseT_Half |
1978                                                 ADVERTISED_100baseT_Full |
1979                                                 ADVERTISED_10baseT_Full;
1980                                 else
1981                                         advertising |= ADVERTISED_10baseT_Full;
1982                         }
1983
1984                         phydev->advertising = advertising;
1985
1986                         phy_start_aneg(phydev);
1987                 }
1988         } else {
1989                 if (tp->link_config.phy_is_low_power == 0) {
1990                         tp->link_config.phy_is_low_power = 1;
1991                         tp->link_config.orig_speed = tp->link_config.speed;
1992                         tp->link_config.orig_duplex = tp->link_config.duplex;
1993                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
1994                 }
1995
1996                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1997                         tp->link_config.speed = SPEED_10;
1998                         tp->link_config.duplex = DUPLEX_HALF;
1999                         tp->link_config.autoneg = AUTONEG_ENABLE;
2000                         tg3_setup_phy(tp, 0);
2001                 }
2002         }
2003
2004         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2005                 u32 val;
2006
2007                 val = tr32(GRC_VCPU_EXT_CTRL);
2008                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2009         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2010                 int i;
2011                 u32 val;
2012
2013                 for (i = 0; i < 200; i++) {
2014                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2015                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2016                                 break;
2017                         msleep(1);
2018                 }
2019         }
2020         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2021                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2022                                                      WOL_DRV_STATE_SHUTDOWN |
2023                                                      WOL_DRV_WOL |
2024                                                      WOL_SET_MAGIC_PKT);
2025
2026         pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
2027
2028         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
2029                 u32 mac_mode;
2030
2031                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2032                         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
2033                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2034                                 udelay(40);
2035                         }
2036
2037                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2038                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2039                         else
2040                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2041
2042                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2043                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2044                             ASIC_REV_5700) {
2045                                 u32 speed = (tp->tg3_flags &
2046                                              TG3_FLAG_WOL_SPEED_100MB) ?
2047                                              SPEED_100 : SPEED_10;
2048                                 if (tg3_5700_link_polarity(tp, speed))
2049                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2050                                 else
2051                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2052                         }
2053                 } else {
2054                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2055                 }
2056
2057                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2058                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2059
2060                 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
2061                      (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
2062                         mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2063
2064                 tw32_f(MAC_MODE, mac_mode);
2065                 udelay(100);
2066
2067                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2068                 udelay(10);
2069         }
2070
2071         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2072             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2073              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2074                 u32 base_val;
2075
2076                 base_val = tp->pci_clock_ctrl;
2077                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2078                              CLOCK_CTRL_TXCLK_DISABLE);
2079
2080                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2081                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2082         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2083                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2084                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2085                 /* do nothing */
2086         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2087                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2088                 u32 newbits1, newbits2;
2089
2090                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2091                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2092                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2093                                     CLOCK_CTRL_TXCLK_DISABLE |
2094                                     CLOCK_CTRL_ALTCLK);
2095                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2096                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2097                         newbits1 = CLOCK_CTRL_625_CORE;
2098                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2099                 } else {
2100                         newbits1 = CLOCK_CTRL_ALTCLK;
2101                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2102                 }
2103
2104                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2105                             40);
2106
2107                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2108                             40);
2109
2110                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2111                         u32 newbits3;
2112
2113                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2114                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2115                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2116                                             CLOCK_CTRL_TXCLK_DISABLE |
2117                                             CLOCK_CTRL_44MHZ_CORE);
2118                         } else {
2119                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2120                         }
2121
2122                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2123                                     tp->pci_clock_ctrl | newbits3, 40);
2124                 }
2125         }
2126
2127         if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
2128             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
2129             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
2130                 tg3_power_down_phy(tp);
2131
2132         tg3_frob_aux_power(tp);
2133
2134         /* Workaround for unstable PLL clock */
2135         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2136             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2137                 u32 val = tr32(0x7d00);
2138
2139                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2140                 tw32(0x7d00, val);
2141                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2142                         int err;
2143
2144                         err = tg3_nvram_lock(tp);
2145                         tg3_halt_cpu(tp, RX_CPU_BASE);
2146                         if (!err)
2147                                 tg3_nvram_unlock(tp);
2148                 }
2149         }
2150
2151         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2152
2153         /* Finally, set the new power state. */
2154         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
2155         udelay(100);    /* Delay after power state change */
2156
2157         return 0;
2158 }
2159
2160 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2161 {
2162         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2163         case MII_TG3_AUX_STAT_10HALF:
2164                 *speed = SPEED_10;
2165                 *duplex = DUPLEX_HALF;
2166                 break;
2167
2168         case MII_TG3_AUX_STAT_10FULL:
2169                 *speed = SPEED_10;
2170                 *duplex = DUPLEX_FULL;
2171                 break;
2172
2173         case MII_TG3_AUX_STAT_100HALF:
2174                 *speed = SPEED_100;
2175                 *duplex = DUPLEX_HALF;
2176                 break;
2177
2178         case MII_TG3_AUX_STAT_100FULL:
2179                 *speed = SPEED_100;
2180                 *duplex = DUPLEX_FULL;
2181                 break;
2182
2183         case MII_TG3_AUX_STAT_1000HALF:
2184                 *speed = SPEED_1000;
2185                 *duplex = DUPLEX_HALF;
2186                 break;
2187
2188         case MII_TG3_AUX_STAT_1000FULL:
2189                 *speed = SPEED_1000;
2190                 *duplex = DUPLEX_FULL;
2191                 break;
2192
2193         default:
2194                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2195                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2196                                  SPEED_10;
2197                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2198                                   DUPLEX_HALF;
2199                         break;
2200                 }
2201                 *speed = SPEED_INVALID;
2202                 *duplex = DUPLEX_INVALID;
2203                 break;
2204         };
2205 }
2206
2207 static void tg3_phy_copper_begin(struct tg3 *tp)
2208 {
2209         u32 new_adv;
2210         int i;
2211
2212         if (tp->link_config.phy_is_low_power) {
2213                 /* Entering low power mode.  Disable gigabit and
2214                  * 100baseT advertisements.
2215                  */
2216                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2217
2218                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2219                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2220                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2221                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2222
2223                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2224         } else if (tp->link_config.speed == SPEED_INVALID) {
2225                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2226                         tp->link_config.advertising &=
2227                                 ~(ADVERTISED_1000baseT_Half |
2228                                   ADVERTISED_1000baseT_Full);
2229
2230                 new_adv = ADVERTISE_CSMA;
2231                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2232                         new_adv |= ADVERTISE_10HALF;
2233                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2234                         new_adv |= ADVERTISE_10FULL;
2235                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2236                         new_adv |= ADVERTISE_100HALF;
2237                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2238                         new_adv |= ADVERTISE_100FULL;
2239
2240                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2241
2242                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2243
2244                 if (tp->link_config.advertising &
2245                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2246                         new_adv = 0;
2247                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2248                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2249                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2250                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2251                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2252                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2253                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2254                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2255                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2256                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2257                 } else {
2258                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2259                 }
2260         } else {
2261                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2262                 new_adv |= ADVERTISE_CSMA;
2263
2264                 /* Asking for a specific link mode. */
2265                 if (tp->link_config.speed == SPEED_1000) {
2266                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2267
2268                         if (tp->link_config.duplex == DUPLEX_FULL)
2269                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2270                         else
2271                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2272                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2273                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2274                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2275                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2276                 } else {
2277                         if (tp->link_config.speed == SPEED_100) {
2278                                 if (tp->link_config.duplex == DUPLEX_FULL)
2279                                         new_adv |= ADVERTISE_100FULL;
2280                                 else
2281                                         new_adv |= ADVERTISE_100HALF;
2282                         } else {
2283                                 if (tp->link_config.duplex == DUPLEX_FULL)
2284                                         new_adv |= ADVERTISE_10FULL;
2285                                 else
2286                                         new_adv |= ADVERTISE_10HALF;
2287                         }
2288                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2289
2290                         new_adv = 0;
2291                 }
2292
2293                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2294         }
2295
2296         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2297             tp->link_config.speed != SPEED_INVALID) {
2298                 u32 bmcr, orig_bmcr;
2299
2300                 tp->link_config.active_speed = tp->link_config.speed;
2301                 tp->link_config.active_duplex = tp->link_config.duplex;
2302
2303                 bmcr = 0;
2304                 switch (tp->link_config.speed) {
2305                 default:
2306                 case SPEED_10:
2307                         break;
2308
2309                 case SPEED_100:
2310                         bmcr |= BMCR_SPEED100;
2311                         break;
2312
2313                 case SPEED_1000:
2314                         bmcr |= TG3_BMCR_SPEED1000;
2315                         break;
2316                 };
2317
2318                 if (tp->link_config.duplex == DUPLEX_FULL)
2319                         bmcr |= BMCR_FULLDPLX;
2320
2321                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2322                     (bmcr != orig_bmcr)) {
2323                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2324                         for (i = 0; i < 1500; i++) {
2325                                 u32 tmp;
2326
2327                                 udelay(10);
2328                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2329                                     tg3_readphy(tp, MII_BMSR, &tmp))
2330                                         continue;
2331                                 if (!(tmp & BMSR_LSTATUS)) {
2332                                         udelay(40);
2333                                         break;
2334                                 }
2335                         }
2336                         tg3_writephy(tp, MII_BMCR, bmcr);
2337                         udelay(40);
2338                 }
2339         } else {
2340                 tg3_writephy(tp, MII_BMCR,
2341                              BMCR_ANENABLE | BMCR_ANRESTART);
2342         }
2343 }
2344
2345 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2346 {
2347         int err;
2348
2349         /* Turn off tap power management. */
2350         /* Set Extended packet length bit */
2351         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2352
2353         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2354         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2355
2356         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2357         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2358
2359         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2360         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2361
2362         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2363         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2364
2365         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2366         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2367
2368         udelay(40);
2369
2370         return err;
2371 }
2372
2373 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2374 {
2375         u32 adv_reg, all_mask = 0;
2376
2377         if (mask & ADVERTISED_10baseT_Half)
2378                 all_mask |= ADVERTISE_10HALF;
2379         if (mask & ADVERTISED_10baseT_Full)
2380                 all_mask |= ADVERTISE_10FULL;
2381         if (mask & ADVERTISED_100baseT_Half)
2382                 all_mask |= ADVERTISE_100HALF;
2383         if (mask & ADVERTISED_100baseT_Full)
2384                 all_mask |= ADVERTISE_100FULL;
2385
2386         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2387                 return 0;
2388
2389         if ((adv_reg & all_mask) != all_mask)
2390                 return 0;
2391         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2392                 u32 tg3_ctrl;
2393
2394                 all_mask = 0;
2395                 if (mask & ADVERTISED_1000baseT_Half)
2396                         all_mask |= ADVERTISE_1000HALF;
2397                 if (mask & ADVERTISED_1000baseT_Full)
2398                         all_mask |= ADVERTISE_1000FULL;
2399
2400                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2401                         return 0;
2402
2403                 if ((tg3_ctrl & all_mask) != all_mask)
2404                         return 0;
2405         }
2406         return 1;
2407 }
2408
2409 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2410 {
2411         u32 curadv, reqadv;
2412
2413         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2414                 return 1;
2415
2416         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2417         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2418
2419         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2420                 if (curadv != reqadv)
2421                         return 0;
2422
2423                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2424                         tg3_readphy(tp, MII_LPA, rmtadv);
2425         } else {
2426                 /* Reprogram the advertisement register, even if it
2427                  * does not affect the current link.  If the link
2428                  * gets renegotiated in the future, we can save an
2429                  * additional renegotiation cycle by advertising
2430                  * it correctly in the first place.
2431                  */
2432                 if (curadv != reqadv) {
2433                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2434                                      ADVERTISE_PAUSE_ASYM);
2435                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2436                 }
2437         }
2438
2439         return 1;
2440 }
2441
2442 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2443 {
2444         int current_link_up;
2445         u32 bmsr, dummy;
2446         u32 lcl_adv, rmt_adv;
2447         u16 current_speed;
2448         u8 current_duplex;
2449         int i, err;
2450
2451         tw32(MAC_EVENT, 0);
2452
2453         tw32_f(MAC_STATUS,
2454              (MAC_STATUS_SYNC_CHANGED |
2455               MAC_STATUS_CFG_CHANGED |
2456               MAC_STATUS_MI_COMPLETION |
2457               MAC_STATUS_LNKSTATE_CHANGED));
2458         udelay(40);
2459
2460         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2461                 tw32_f(MAC_MI_MODE,
2462                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2463                 udelay(80);
2464         }
2465
2466         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2467
2468         /* Some third-party PHYs need to be reset on link going
2469          * down.
2470          */
2471         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2472              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2473              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2474             netif_carrier_ok(tp->dev)) {
2475                 tg3_readphy(tp, MII_BMSR, &bmsr);
2476                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2477                     !(bmsr & BMSR_LSTATUS))
2478                         force_reset = 1;
2479         }
2480         if (force_reset)
2481                 tg3_phy_reset(tp);
2482
2483         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2484                 tg3_readphy(tp, MII_BMSR, &bmsr);
2485                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2486                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2487                         bmsr = 0;
2488
2489                 if (!(bmsr & BMSR_LSTATUS)) {
2490                         err = tg3_init_5401phy_dsp(tp);
2491                         if (err)
2492                                 return err;
2493
2494                         tg3_readphy(tp, MII_BMSR, &bmsr);
2495                         for (i = 0; i < 1000; i++) {
2496                                 udelay(10);
2497                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2498                                     (bmsr & BMSR_LSTATUS)) {
2499                                         udelay(40);
2500                                         break;
2501                                 }
2502                         }
2503
2504                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
2505                             !(bmsr & BMSR_LSTATUS) &&
2506                             tp->link_config.active_speed == SPEED_1000) {
2507                                 err = tg3_phy_reset(tp);
2508                                 if (!err)
2509                                         err = tg3_init_5401phy_dsp(tp);
2510                                 if (err)
2511                                         return err;
2512                         }
2513                 }
2514         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2515                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2516                 /* 5701 {A0,B0} CRC bug workaround */
2517                 tg3_writephy(tp, 0x15, 0x0a75);
2518                 tg3_writephy(tp, 0x1c, 0x8c68);
2519                 tg3_writephy(tp, 0x1c, 0x8d68);
2520                 tg3_writephy(tp, 0x1c, 0x8c68);
2521         }
2522
2523         /* Clear pending interrupts... */
2524         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2525         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2526
2527         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
2528                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
2529         else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
2530                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
2531
2532         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2533             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2534                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
2535                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2536                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
2537                 else
2538                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
2539         }
2540
2541         current_link_up = 0;
2542         current_speed = SPEED_INVALID;
2543         current_duplex = DUPLEX_INVALID;
2544
2545         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
2546                 u32 val;
2547
2548                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
2549                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
2550                 if (!(val & (1 << 10))) {
2551                         val |= (1 << 10);
2552                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2553                         goto relink;
2554                 }
2555         }
2556
2557         bmsr = 0;
2558         for (i = 0; i < 100; i++) {
2559                 tg3_readphy(tp, MII_BMSR, &bmsr);
2560                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2561                     (bmsr & BMSR_LSTATUS))
2562                         break;
2563                 udelay(40);
2564         }
2565
2566         if (bmsr & BMSR_LSTATUS) {
2567                 u32 aux_stat, bmcr;
2568
2569                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
2570                 for (i = 0; i < 2000; i++) {
2571                         udelay(10);
2572                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
2573                             aux_stat)
2574                                 break;
2575                 }
2576
2577                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
2578                                              &current_speed,
2579                                              &current_duplex);
2580
2581                 bmcr = 0;
2582                 for (i = 0; i < 200; i++) {
2583                         tg3_readphy(tp, MII_BMCR, &bmcr);
2584                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
2585                                 continue;
2586                         if (bmcr && bmcr != 0x7fff)
2587                                 break;
2588                         udelay(10);
2589                 }
2590
2591                 lcl_adv = 0;
2592                 rmt_adv = 0;
2593
2594                 tp->link_config.active_speed = current_speed;
2595                 tp->link_config.active_duplex = current_duplex;
2596
2597                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2598                         if ((bmcr & BMCR_ANENABLE) &&
2599                             tg3_copper_is_advertising_all(tp,
2600                                                 tp->link_config.advertising)) {
2601                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
2602                                                                   &rmt_adv))
2603                                         current_link_up = 1;
2604                         }
2605                 } else {
2606                         if (!(bmcr & BMCR_ANENABLE) &&
2607                             tp->link_config.speed == current_speed &&
2608                             tp->link_config.duplex == current_duplex &&
2609                             tp->link_config.flowctrl ==
2610                             tp->link_config.active_flowctrl) {
2611                                 current_link_up = 1;
2612                         }
2613                 }
2614
2615                 if (current_link_up == 1 &&
2616                     tp->link_config.active_duplex == DUPLEX_FULL)
2617                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2618         }
2619
2620 relink:
2621         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
2622                 u32 tmp;
2623
2624                 tg3_phy_copper_begin(tp);
2625
2626                 tg3_readphy(tp, MII_BMSR, &tmp);
2627                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
2628                     (tmp & BMSR_LSTATUS))
2629                         current_link_up = 1;
2630         }
2631
2632         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
2633         if (current_link_up == 1) {
2634                 if (tp->link_config.active_speed == SPEED_100 ||
2635                     tp->link_config.active_speed == SPEED_10)
2636                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
2637                 else
2638                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2639         } else
2640                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2641
2642         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2643         if (tp->link_config.active_duplex == DUPLEX_HALF)
2644                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2645
2646         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
2647                 if (current_link_up == 1 &&
2648                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
2649                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2650                 else
2651                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2652         }
2653
2654         /* ??? Without this setting Netgear GA302T PHY does not
2655          * ??? send/receive packets...
2656          */
2657         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2658             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2659                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2660                 tw32_f(MAC_MI_MODE, tp->mi_mode);
2661                 udelay(80);
2662         }
2663
2664         tw32_f(MAC_MODE, tp->mac_mode);
2665         udelay(40);
2666
2667         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2668                 /* Polled via timer. */
2669                 tw32_f(MAC_EVENT, 0);
2670         } else {
2671                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2672         }
2673         udelay(40);
2674
2675         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2676             current_link_up == 1 &&
2677             tp->link_config.active_speed == SPEED_1000 &&
2678             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2679              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2680                 udelay(120);
2681                 tw32_f(MAC_STATUS,
2682                      (MAC_STATUS_SYNC_CHANGED |
2683                       MAC_STATUS_CFG_CHANGED));
2684                 udelay(40);
2685                 tg3_write_mem(tp,
2686                               NIC_SRAM_FIRMWARE_MBOX,
2687                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2688         }
2689
2690         if (current_link_up != netif_carrier_ok(tp->dev)) {
2691                 if (current_link_up)
2692                         netif_carrier_on(tp->dev);
2693                 else
2694                         netif_carrier_off(tp->dev);
2695                 tg3_link_report(tp);
2696         }
2697
2698         return 0;
2699 }
2700
2701 struct tg3_fiber_aneginfo {
2702         int state;
2703 #define ANEG_STATE_UNKNOWN              0
2704 #define ANEG_STATE_AN_ENABLE            1
2705 #define ANEG_STATE_RESTART_INIT         2
2706 #define ANEG_STATE_RESTART              3
2707 #define ANEG_STATE_DISABLE_LINK_OK      4
2708 #define ANEG_STATE_ABILITY_DETECT_INIT  5
2709 #define ANEG_STATE_ABILITY_DETECT       6
2710 #define ANEG_STATE_ACK_DETECT_INIT      7
2711 #define ANEG_STATE_ACK_DETECT           8
2712 #define ANEG_STATE_COMPLETE_ACK_INIT    9
2713 #define ANEG_STATE_COMPLETE_ACK         10
2714 #define ANEG_STATE_IDLE_DETECT_INIT     11
2715 #define ANEG_STATE_IDLE_DETECT          12
2716 #define ANEG_STATE_LINK_OK              13
2717 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
2718 #define ANEG_STATE_NEXT_PAGE_WAIT       15
2719
2720         u32 flags;
2721 #define MR_AN_ENABLE            0x00000001
2722 #define MR_RESTART_AN           0x00000002
2723 #define MR_AN_COMPLETE          0x00000004
2724 #define MR_PAGE_RX              0x00000008
2725 #define MR_NP_LOADED            0x00000010
2726 #define MR_TOGGLE_TX            0x00000020
2727 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
2728 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
2729 #define MR_LP_ADV_SYM_PAUSE     0x00000100
2730 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
2731 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2732 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2733 #define MR_LP_ADV_NEXT_PAGE     0x00001000
2734 #define MR_TOGGLE_RX            0x00002000
2735 #define MR_NP_RX                0x00004000
2736
2737 #define MR_LINK_OK              0x80000000
2738
2739         unsigned long link_time, cur_time;
2740
2741         u32 ability_match_cfg;
2742         int ability_match_count;
2743
2744         char ability_match, idle_match, ack_match;
2745
2746         u32 txconfig, rxconfig;
2747 #define ANEG_CFG_NP             0x00000080
2748 #define ANEG_CFG_ACK            0x00000040
2749 #define ANEG_CFG_RF2            0x00000020
2750 #define ANEG_CFG_RF1            0x00000010
2751 #define ANEG_CFG_PS2            0x00000001
2752 #define ANEG_CFG_PS1            0x00008000
2753 #define ANEG_CFG_HD             0x00004000
2754 #define ANEG_CFG_FD             0x00002000
2755 #define ANEG_CFG_INVAL          0x00001f06
2756
2757 };
2758 #define ANEG_OK         0
2759 #define ANEG_DONE       1
2760 #define ANEG_TIMER_ENAB 2
2761 #define ANEG_FAILED     -1
2762
2763 #define ANEG_STATE_SETTLE_TIME  10000
2764
2765 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2766                                    struct tg3_fiber_aneginfo *ap)
2767 {
2768         u16 flowctrl;
2769         unsigned long delta;
2770         u32 rx_cfg_reg;
2771         int ret;
2772
2773         if (ap->state == ANEG_STATE_UNKNOWN) {
2774                 ap->rxconfig = 0;
2775                 ap->link_time = 0;
2776                 ap->cur_time = 0;
2777                 ap->ability_match_cfg = 0;
2778                 ap->ability_match_count = 0;
2779                 ap->ability_match = 0;
2780                 ap->idle_match = 0;
2781                 ap->ack_match = 0;
2782         }
2783         ap->cur_time++;
2784
2785         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2786                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2787
2788                 if (rx_cfg_reg != ap->ability_match_cfg) {
2789                         ap->ability_match_cfg = rx_cfg_reg;
2790                         ap->ability_match = 0;
2791                         ap->ability_match_count = 0;
2792                 } else {
2793                         if (++ap->ability_match_count > 1) {
2794                                 ap->ability_match = 1;
2795                                 ap->ability_match_cfg = rx_cfg_reg;
2796                         }
2797                 }
2798                 if (rx_cfg_reg & ANEG_CFG_ACK)
2799                         ap->ack_match = 1;
2800                 else
2801                         ap->ack_match = 0;
2802
2803                 ap->idle_match = 0;
2804         } else {
2805                 ap->idle_match = 1;
2806                 ap->ability_match_cfg = 0;
2807                 ap->ability_match_count = 0;
2808                 ap->ability_match = 0;
2809                 ap->ack_match = 0;
2810
2811                 rx_cfg_reg = 0;
2812         }
2813
2814         ap->rxconfig = rx_cfg_reg;
2815         ret = ANEG_OK;
2816
2817         switch(ap->state) {
2818         case ANEG_STATE_UNKNOWN:
2819                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2820                         ap->state = ANEG_STATE_AN_ENABLE;
2821
2822                 /* fallthru */
2823         case ANEG_STATE_AN_ENABLE:
2824                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2825                 if (ap->flags & MR_AN_ENABLE) {
2826                         ap->link_time = 0;
2827                         ap->cur_time = 0;
2828                         ap->ability_match_cfg = 0;
2829                         ap->ability_match_count = 0;
2830                         ap->ability_match = 0;
2831                         ap->idle_match = 0;
2832                         ap->ack_match = 0;
2833
2834                         ap->state = ANEG_STATE_RESTART_INIT;
2835                 } else {
2836                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
2837                 }
2838                 break;
2839
2840         case ANEG_STATE_RESTART_INIT:
2841                 ap->link_time = ap->cur_time;
2842                 ap->flags &= ~(MR_NP_LOADED);
2843                 ap->txconfig = 0;
2844                 tw32(MAC_TX_AUTO_NEG, 0);
2845                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2846                 tw32_f(MAC_MODE, tp->mac_mode);
2847                 udelay(40);
2848
2849                 ret = ANEG_TIMER_ENAB;
2850                 ap->state = ANEG_STATE_RESTART;
2851
2852                 /* fallthru */
2853         case ANEG_STATE_RESTART:
2854                 delta = ap->cur_time - ap->link_time;
2855                 if (delta > ANEG_STATE_SETTLE_TIME) {
2856                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2857                 } else {
2858                         ret = ANEG_TIMER_ENAB;
2859                 }
2860                 break;
2861
2862         case ANEG_STATE_DISABLE_LINK_OK:
2863                 ret = ANEG_DONE;
2864                 break;
2865
2866         case ANEG_STATE_ABILITY_DETECT_INIT:
2867                 ap->flags &= ~(MR_TOGGLE_TX);
2868                 ap->txconfig = ANEG_CFG_FD;
2869                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
2870                 if (flowctrl & ADVERTISE_1000XPAUSE)
2871                         ap->txconfig |= ANEG_CFG_PS1;
2872                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
2873                         ap->txconfig |= ANEG_CFG_PS2;
2874                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2875                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2876                 tw32_f(MAC_MODE, tp->mac_mode);
2877                 udelay(40);
2878
2879                 ap->state = ANEG_STATE_ABILITY_DETECT;
2880                 break;
2881
2882         case ANEG_STATE_ABILITY_DETECT:
2883                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2884                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
2885                 }
2886                 break;
2887
2888         case ANEG_STATE_ACK_DETECT_INIT:
2889                 ap->txconfig |= ANEG_CFG_ACK;
2890                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2891                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2892                 tw32_f(MAC_MODE, tp->mac_mode);
2893                 udelay(40);
2894
2895                 ap->state = ANEG_STATE_ACK_DETECT;
2896
2897                 /* fallthru */
2898         case ANEG_STATE_ACK_DETECT:
2899                 if (ap->ack_match != 0) {
2900                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2901                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2902                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2903                         } else {
2904                                 ap->state = ANEG_STATE_AN_ENABLE;
2905                         }
2906                 } else if (ap->ability_match != 0 &&
2907                            ap->rxconfig == 0) {
2908                         ap->state = ANEG_STATE_AN_ENABLE;
2909                 }
2910                 break;
2911
2912         case ANEG_STATE_COMPLETE_ACK_INIT:
2913                 if (ap->rxconfig & ANEG_CFG_INVAL) {
2914                         ret = ANEG_FAILED;
2915                         break;
2916                 }
2917                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2918                                MR_LP_ADV_HALF_DUPLEX |
2919                                MR_LP_ADV_SYM_PAUSE |
2920                                MR_LP_ADV_ASYM_PAUSE |
2921                                MR_LP_ADV_REMOTE_FAULT1 |
2922                                MR_LP_ADV_REMOTE_FAULT2 |
2923                                MR_LP_ADV_NEXT_PAGE |
2924                                MR_TOGGLE_RX |
2925                                MR_NP_RX);
2926                 if (ap->rxconfig & ANEG_CFG_FD)
2927                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2928                 if (ap->rxconfig & ANEG_CFG_HD)
2929                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2930                 if (ap->rxconfig & ANEG_CFG_PS1)
2931                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
2932                 if (ap->rxconfig & ANEG_CFG_PS2)
2933                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2934                 if (ap->rxconfig & ANEG_CFG_RF1)
2935                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2936                 if (ap->rxconfig & ANEG_CFG_RF2)
2937                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2938                 if (ap->rxconfig & ANEG_CFG_NP)
2939                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
2940
2941                 ap->link_time = ap->cur_time;
2942
2943                 ap->flags ^= (MR_TOGGLE_TX);
2944                 if (ap->rxconfig & 0x0008)
2945                         ap->flags |= MR_TOGGLE_RX;
2946                 if (ap->rxconfig & ANEG_CFG_NP)
2947                         ap->flags |= MR_NP_RX;
2948                 ap->flags |= MR_PAGE_RX;
2949
2950                 ap->state = ANEG_STATE_COMPLETE_ACK;
2951                 ret = ANEG_TIMER_ENAB;
2952                 break;
2953
2954         case ANEG_STATE_COMPLETE_ACK:
2955                 if (ap->ability_match != 0 &&
2956                     ap->rxconfig == 0) {
2957                         ap->state = ANEG_STATE_AN_ENABLE;
2958                         break;
2959                 }
2960                 delta = ap->cur_time - ap->link_time;
2961                 if (delta > ANEG_STATE_SETTLE_TIME) {
2962                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2963                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2964                         } else {
2965                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2966                                     !(ap->flags & MR_NP_RX)) {
2967                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2968                                 } else {
2969                                         ret = ANEG_FAILED;
2970                                 }
2971                         }
2972                 }
2973                 break;
2974
2975         case ANEG_STATE_IDLE_DETECT_INIT:
2976                 ap->link_time = ap->cur_time;
2977                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2978                 tw32_f(MAC_MODE, tp->mac_mode);
2979                 udelay(40);
2980
2981                 ap->state = ANEG_STATE_IDLE_DETECT;
2982                 ret = ANEG_TIMER_ENAB;
2983                 break;
2984
2985         case ANEG_STATE_IDLE_DETECT:
2986                 if (ap->ability_match != 0 &&
2987                     ap->rxconfig == 0) {
2988                         ap->state = ANEG_STATE_AN_ENABLE;
2989                         break;
2990                 }
2991                 delta = ap->cur_time - ap->link_time;
2992                 if (delta > ANEG_STATE_SETTLE_TIME) {
2993                         /* XXX another gem from the Broadcom driver :( */
2994                         ap->state = ANEG_STATE_LINK_OK;
2995                 }
2996                 break;
2997
2998         case ANEG_STATE_LINK_OK:
2999                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3000                 ret = ANEG_DONE;
3001                 break;
3002
3003         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3004                 /* ??? unimplemented */
3005                 break;
3006
3007         case ANEG_STATE_NEXT_PAGE_WAIT:
3008                 /* ??? unimplemented */
3009                 break;
3010
3011         default:
3012                 ret = ANEG_FAILED;
3013                 break;
3014         };
3015
3016         return ret;
3017 }
3018
3019 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3020 {
3021         int res = 0;
3022         struct tg3_fiber_aneginfo aninfo;
3023         int status = ANEG_FAILED;
3024         unsigned int tick;
3025         u32 tmp;
3026
3027         tw32_f(MAC_TX_AUTO_NEG, 0);
3028
3029         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3030         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3031         udelay(40);
3032
3033         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3034         udelay(40);
3035
3036         memset(&aninfo, 0, sizeof(aninfo));
3037         aninfo.flags |= MR_AN_ENABLE;
3038         aninfo.state = ANEG_STATE_UNKNOWN;
3039         aninfo.cur_time = 0;
3040         tick = 0;
3041         while (++tick < 195000) {
3042                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3043                 if (status == ANEG_DONE || status == ANEG_FAILED)
3044                         break;
3045
3046                 udelay(1);
3047         }
3048
3049         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3050         tw32_f(MAC_MODE, tp->mac_mode);
3051         udelay(40);
3052
3053         *txflags = aninfo.txconfig;
3054         *rxflags = aninfo.flags;
3055
3056         if (status == ANEG_DONE &&
3057             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3058                              MR_LP_ADV_FULL_DUPLEX)))
3059                 res = 1;
3060
3061         return res;
3062 }
3063
3064 static void tg3_init_bcm8002(struct tg3 *tp)
3065 {
3066         u32 mac_status = tr32(MAC_STATUS);
3067         int i;
3068
3069         /* Reset when initting first time or we have a link. */
3070         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3071             !(mac_status & MAC_STATUS_PCS_SYNCED))
3072                 return;
3073
3074         /* Set PLL lock range. */
3075         tg3_writephy(tp, 0x16, 0x8007);
3076
3077         /* SW reset */
3078         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3079
3080         /* Wait for reset to complete. */
3081         /* XXX schedule_timeout() ... */
3082         for (i = 0; i < 500; i++)
3083                 udelay(10);
3084
3085         /* Config mode; select PMA/Ch 1 regs. */
3086         tg3_writephy(tp, 0x10, 0x8411);
3087
3088         /* Enable auto-lock and comdet, select txclk for tx. */
3089         tg3_writephy(tp, 0x11, 0x0a10);
3090
3091         tg3_writephy(tp, 0x18, 0x00a0);
3092         tg3_writephy(tp, 0x16, 0x41ff);
3093
3094         /* Assert and deassert POR. */
3095         tg3_writephy(tp, 0x13, 0x0400);
3096         udelay(40);
3097         tg3_writephy(tp, 0x13, 0x0000);
3098
3099         tg3_writephy(tp, 0x11, 0x0a50);
3100         udelay(40);
3101         tg3_writephy(tp, 0x11, 0x0a10);
3102
3103         /* Wait for signal to stabilize */
3104         /* XXX schedule_timeout() ... */
3105         for (i = 0; i < 15000; i++)
3106                 udelay(10);
3107
3108         /* Deselect the channel register so we can read the PHYID
3109          * later.
3110          */
3111         tg3_writephy(tp, 0x10, 0x8011);
3112 }
3113
3114 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3115 {
3116         u16 flowctrl;
3117         u32 sg_dig_ctrl, sg_dig_status;
3118         u32 serdes_cfg, expected_sg_dig_ctrl;
3119         int workaround, port_a;
3120         int current_link_up;
3121
3122         serdes_cfg = 0;
3123         expected_sg_dig_ctrl = 0;
3124         workaround = 0;
3125         port_a = 1;
3126         current_link_up = 0;
3127
3128         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3129             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3130                 workaround = 1;
3131                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3132                         port_a = 0;
3133
3134                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3135                 /* preserve bits 20-23 for voltage regulator */
3136                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3137         }
3138
3139         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3140
3141         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3142                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3143                         if (workaround) {
3144                                 u32 val = serdes_cfg;
3145
3146                                 if (port_a)
3147                                         val |= 0xc010000;
3148                                 else
3149                                         val |= 0x4010000;
3150                                 tw32_f(MAC_SERDES_CFG, val);
3151                         }
3152
3153                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3154                 }
3155                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3156                         tg3_setup_flow_control(tp, 0, 0);
3157                         current_link_up = 1;
3158                 }
3159                 goto out;
3160         }
3161
3162         /* Want auto-negotiation.  */
3163         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3164
3165         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3166         if (flowctrl & ADVERTISE_1000XPAUSE)
3167                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3168         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3169                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3170
3171         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3172                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3173                     tp->serdes_counter &&
3174                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3175                                     MAC_STATUS_RCVD_CFG)) ==
3176                      MAC_STATUS_PCS_SYNCED)) {
3177                         tp->serdes_counter--;
3178                         current_link_up = 1;
3179                         goto out;
3180                 }
3181 restart_autoneg:
3182                 if (workaround)
3183                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3184                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3185                 udelay(5);
3186                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3187
3188                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3189                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3190         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3191                                  MAC_STATUS_SIGNAL_DET)) {
3192                 sg_dig_status = tr32(SG_DIG_STATUS);
3193                 mac_status = tr32(MAC_STATUS);
3194
3195                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3196                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3197                         u32 local_adv = 0, remote_adv = 0;
3198
3199                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3200                                 local_adv |= ADVERTISE_1000XPAUSE;
3201                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3202                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3203
3204                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3205                                 remote_adv |= LPA_1000XPAUSE;
3206                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3207                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3208
3209                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3210                         current_link_up = 1;
3211                         tp->serdes_counter = 0;
3212                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3213                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3214                         if (tp->serdes_counter)
3215                                 tp->serdes_counter--;
3216                         else {
3217                                 if (workaround) {
3218                                         u32 val = serdes_cfg;
3219
3220                                         if (port_a)
3221                                                 val |= 0xc010000;
3222                                         else
3223                                                 val |= 0x4010000;
3224
3225                                         tw32_f(MAC_SERDES_CFG, val);
3226                                 }
3227
3228                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3229                                 udelay(40);
3230
3231                                 /* Link parallel detection - link is up */
3232                                 /* only if we have PCS_SYNC and not */
3233                                 /* receiving config code words */
3234                                 mac_status = tr32(MAC_STATUS);
3235                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3236                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3237                                         tg3_setup_flow_control(tp, 0, 0);
3238                                         current_link_up = 1;
3239                                         tp->tg3_flags2 |=
3240                                                 TG3_FLG2_PARALLEL_DETECT;
3241                                         tp->serdes_counter =
3242                                                 SERDES_PARALLEL_DET_TIMEOUT;
3243                                 } else
3244                                         goto restart_autoneg;
3245                         }
3246                 }
3247         } else {
3248                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3249                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3250         }
3251
3252 out:
3253         return current_link_up;
3254 }
3255
3256 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3257 {
3258         int current_link_up = 0;
3259
3260         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3261                 goto out;
3262
3263         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3264                 u32 txflags, rxflags;
3265                 int i;
3266
3267                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3268                         u32 local_adv = 0, remote_adv = 0;
3269
3270                         if (txflags & ANEG_CFG_PS1)
3271                                 local_adv |= ADVERTISE_1000XPAUSE;
3272                         if (txflags & ANEG_CFG_PS2)
3273                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3274
3275                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3276                                 remote_adv |= LPA_1000XPAUSE;
3277                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3278                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3279
3280                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3281
3282                         current_link_up = 1;
3283                 }
3284                 for (i = 0; i < 30; i++) {
3285                         udelay(20);
3286                         tw32_f(MAC_STATUS,
3287                                (MAC_STATUS_SYNC_CHANGED |
3288                                 MAC_STATUS_CFG_CHANGED));
3289                         udelay(40);
3290                         if ((tr32(MAC_STATUS) &
3291                              (MAC_STATUS_SYNC_CHANGED |
3292                               MAC_STATUS_CFG_CHANGED)) == 0)
3293                                 break;
3294                 }
3295
3296                 mac_status = tr32(MAC_STATUS);
3297                 if (current_link_up == 0 &&
3298                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3299                     !(mac_status & MAC_STATUS_RCVD_CFG))
3300                         current_link_up = 1;
3301         } else {
3302                 tg3_setup_flow_control(tp, 0, 0);
3303
3304                 /* Forcing 1000FD link up. */
3305                 current_link_up = 1;
3306
3307                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3308                 udelay(40);
3309
3310                 tw32_f(MAC_MODE, tp->mac_mode);
3311                 udelay(40);
3312         }
3313
3314 out:
3315         return current_link_up;
3316 }
3317
3318 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3319 {
3320         u32 orig_pause_cfg;
3321         u16 orig_active_speed;
3322         u8 orig_active_duplex;
3323         u32 mac_status;
3324         int current_link_up;
3325         int i;
3326
3327         orig_pause_cfg = tp->link_config.active_flowctrl;
3328         orig_active_speed = tp->link_config.active_speed;
3329         orig_active_duplex = tp->link_config.active_duplex;
3330
3331         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3332             netif_carrier_ok(tp->dev) &&
3333             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3334                 mac_status = tr32(MAC_STATUS);
3335                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3336                                MAC_STATUS_SIGNAL_DET |
3337                                MAC_STATUS_CFG_CHANGED |
3338                                MAC_STATUS_RCVD_CFG);
3339                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3340                                    MAC_STATUS_SIGNAL_DET)) {
3341                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3342                                             MAC_STATUS_CFG_CHANGED));
3343                         return 0;
3344                 }
3345         }
3346
3347         tw32_f(MAC_TX_AUTO_NEG, 0);
3348
3349         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3350         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3351         tw32_f(MAC_MODE, tp->mac_mode);
3352         udelay(40);
3353
3354         if (tp->phy_id == PHY_ID_BCM8002)
3355                 tg3_init_bcm8002(tp);
3356
3357         /* Enable link change event even when serdes polling.  */
3358         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3359         udelay(40);
3360
3361         current_link_up = 0;
3362         mac_status = tr32(MAC_STATUS);
3363
3364         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3365                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3366         else
3367                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3368
3369         tp->hw_status->status =
3370                 (SD_STATUS_UPDATED |
3371                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3372
3373         for (i = 0; i < 100; i++) {
3374                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3375                                     MAC_STATUS_CFG_CHANGED));
3376                 udelay(5);
3377                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3378                                          MAC_STATUS_CFG_CHANGED |
3379                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3380                         break;
3381         }
3382
3383         mac_status = tr32(MAC_STATUS);
3384         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3385                 current_link_up = 0;
3386                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3387                     tp->serdes_counter == 0) {
3388                         tw32_f(MAC_MODE, (tp->mac_mode |
3389                                           MAC_MODE_SEND_CONFIGS));
3390                         udelay(1);
3391                         tw32_f(MAC_MODE, tp->mac_mode);
3392                 }
3393         }
3394
3395         if (current_link_up == 1) {
3396                 tp->link_config.active_speed = SPEED_1000;
3397                 tp->link_config.active_duplex = DUPLEX_FULL;
3398                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3399                                     LED_CTRL_LNKLED_OVERRIDE |
3400                                     LED_CTRL_1000MBPS_ON));
3401         } else {
3402                 tp->link_config.active_speed = SPEED_INVALID;
3403                 tp->link_config.active_duplex = DUPLEX_INVALID;
3404                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3405                                     LED_CTRL_LNKLED_OVERRIDE |
3406                                     LED_CTRL_TRAFFIC_OVERRIDE));
3407         }
3408
3409         if (current_link_up != netif_carrier_ok(tp->dev)) {
3410                 if (current_link_up)
3411                         netif_carrier_on(tp->dev);
3412                 else
3413                         netif_carrier_off(tp->dev);
3414                 tg3_link_report(tp);
3415         } else {
3416                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
3417                 if (orig_pause_cfg != now_pause_cfg ||
3418                     orig_active_speed != tp->link_config.active_speed ||
3419                     orig_active_duplex != tp->link_config.active_duplex)
3420                         tg3_link_report(tp);
3421         }
3422
3423         return 0;
3424 }
3425
3426 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3427 {
3428         int current_link_up, err = 0;
3429         u32 bmsr, bmcr;
3430         u16 current_speed;
3431         u8 current_duplex;
3432         u32 local_adv, remote_adv;
3433
3434         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3435         tw32_f(MAC_MODE, tp->mac_mode);
3436         udelay(40);
3437
3438         tw32(MAC_EVENT, 0);
3439
3440         tw32_f(MAC_STATUS,
3441              (MAC_STATUS_SYNC_CHANGED |
3442               MAC_STATUS_CFG_CHANGED |
3443               MAC_STATUS_MI_COMPLETION |
3444               MAC_STATUS_LNKSTATE_CHANGED));
3445         udelay(40);
3446
3447         if (force_reset)
3448                 tg3_phy_reset(tp);
3449
3450         current_link_up = 0;
3451         current_speed = SPEED_INVALID;
3452         current_duplex = DUPLEX_INVALID;
3453
3454         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3455         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3456         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3457                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3458                         bmsr |= BMSR_LSTATUS;
3459                 else
3460                         bmsr &= ~BMSR_LSTATUS;
3461         }
3462
3463         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3464
3465         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
3466             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3467              tp->link_config.flowctrl == tp->link_config.active_flowctrl) {
3468                 /* do nothing, just check for link up at the end */
3469         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3470                 u32 adv, new_adv;
3471
3472                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3473                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
3474                                   ADVERTISE_1000XPAUSE |
3475                                   ADVERTISE_1000XPSE_ASYM |
3476                                   ADVERTISE_SLCT);
3477
3478                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3479
3480                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
3481                         new_adv |= ADVERTISE_1000XHALF;
3482                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
3483                         new_adv |= ADVERTISE_1000XFULL;
3484
3485                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
3486                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
3487                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
3488                         tg3_writephy(tp, MII_BMCR, bmcr);
3489
3490                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3491                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
3492                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3493
3494                         return err;
3495                 }
3496         } else {
3497                 u32 new_bmcr;
3498
3499                 bmcr &= ~BMCR_SPEED1000;
3500                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
3501
3502                 if (tp->link_config.duplex == DUPLEX_FULL)
3503                         new_bmcr |= BMCR_FULLDPLX;
3504
3505                 if (new_bmcr != bmcr) {
3506                         /* BMCR_SPEED1000 is a reserved bit that needs
3507                          * to be set on write.
3508                          */
3509                         new_bmcr |= BMCR_SPEED1000;
3510
3511                         /* Force a linkdown */
3512                         if (netif_carrier_ok(tp->dev)) {
3513                                 u32 adv;
3514
3515                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3516                                 adv &= ~(ADVERTISE_1000XFULL |
3517                                          ADVERTISE_1000XHALF |
3518                                          ADVERTISE_SLCT);
3519                                 tg3_writephy(tp, MII_ADVERTISE, adv);
3520                                 tg3_writephy(tp, MII_BMCR, bmcr |
3521                                                            BMCR_ANRESTART |
3522                                                            BMCR_ANENABLE);
3523                                 udelay(10);
3524                                 netif_carrier_off(tp->dev);
3525                         }
3526                         tg3_writephy(tp, MII_BMCR, new_bmcr);
3527                         bmcr = new_bmcr;
3528                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3529                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3530                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
3531                             ASIC_REV_5714) {
3532                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3533                                         bmsr |= BMSR_LSTATUS;
3534                                 else
3535                                         bmsr &= ~BMSR_LSTATUS;
3536                         }
3537                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3538                 }
3539         }
3540
3541         if (bmsr & BMSR_LSTATUS) {
3542                 current_speed = SPEED_1000;
3543                 current_link_up = 1;
3544                 if (bmcr & BMCR_FULLDPLX)
3545                         current_duplex = DUPLEX_FULL;
3546                 else
3547                         current_duplex = DUPLEX_HALF;
3548
3549                 local_adv = 0;
3550                 remote_adv = 0;
3551
3552                 if (bmcr & BMCR_ANENABLE) {
3553                         u32 common;
3554
3555                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
3556                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
3557                         common = local_adv & remote_adv;
3558                         if (common & (ADVERTISE_1000XHALF |
3559                                       ADVERTISE_1000XFULL)) {
3560                                 if (common & ADVERTISE_1000XFULL)
3561                                         current_duplex = DUPLEX_FULL;
3562                                 else
3563                                         current_duplex = DUPLEX_HALF;
3564                         }
3565                         else
3566                                 current_link_up = 0;
3567                 }
3568         }
3569
3570         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
3571                 tg3_setup_flow_control(tp, local_adv, remote_adv);
3572
3573         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3574         if (tp->link_config.active_duplex == DUPLEX_HALF)
3575                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3576
3577         tw32_f(MAC_MODE, tp->mac_mode);
3578         udelay(40);
3579
3580         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3581
3582         tp->link_config.active_speed = current_speed;
3583         tp->link_config.active_duplex = current_duplex;
3584
3585         if (current_link_up != netif_carrier_ok(tp->dev)) {
3586                 if (current_link_up)
3587                         netif_carrier_on(tp->dev);
3588                 else {
3589                         netif_carrier_off(tp->dev);
3590                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3591                 }
3592                 tg3_link_report(tp);
3593         }
3594         return err;
3595 }
3596
3597 static void tg3_serdes_parallel_detect(struct tg3 *tp)
3598 {
3599         if (tp->serdes_counter) {
3600                 /* Give autoneg time to complete. */
3601                 tp->serdes_counter--;
3602                 return;
3603         }
3604         if (!netif_carrier_ok(tp->dev) &&
3605             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
3606                 u32 bmcr;
3607
3608                 tg3_readphy(tp, MII_BMCR, &bmcr);
3609                 if (bmcr & BMCR_ANENABLE) {
3610                         u32 phy1, phy2;
3611
3612                         /* Select shadow register 0x1f */
3613                         tg3_writephy(tp, 0x1c, 0x7c00);
3614                         tg3_readphy(tp, 0x1c, &phy1);
3615
3616                         /* Select expansion interrupt status register */
3617                         tg3_writephy(tp, 0x17, 0x0f01);
3618                         tg3_readphy(tp, 0x15, &phy2);
3619                         tg3_readphy(tp, 0x15, &phy2);
3620
3621                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
3622                                 /* We have signal detect and not receiving
3623                                  * config code words, link is up by parallel
3624                                  * detection.
3625                                  */
3626
3627                                 bmcr &= ~BMCR_ANENABLE;
3628                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
3629                                 tg3_writephy(tp, MII_BMCR, bmcr);
3630                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
3631                         }
3632                 }
3633         }
3634         else if (netif_carrier_ok(tp->dev) &&
3635                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
3636                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3637                 u32 phy2;
3638
3639                 /* Select expansion interrupt status register */
3640                 tg3_writephy(tp, 0x17, 0x0f01);
3641                 tg3_readphy(tp, 0x15, &phy2);
3642                 if (phy2 & 0x20) {
3643                         u32 bmcr;
3644
3645                         /* Config code words received, turn on autoneg. */
3646                         tg3_readphy(tp, MII_BMCR, &bmcr);
3647                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
3648
3649                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3650
3651                 }
3652         }
3653 }
3654
3655 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
3656 {
3657         int err;
3658
3659         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
3660                 err = tg3_setup_fiber_phy(tp, force_reset);
3661         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
3662                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
3663         } else {
3664                 err = tg3_setup_copper_phy(tp, force_reset);
3665         }
3666
3667         if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
3668             tp->pci_chip_rev_id == CHIPREV_ID_5784_A1) {
3669                 u32 val, scale;
3670
3671                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
3672                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
3673                         scale = 65;
3674                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
3675                         scale = 6;
3676                 else
3677                         scale = 12;
3678
3679                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
3680                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
3681                 tw32(GRC_MISC_CFG, val);
3682         }
3683
3684         if (tp->link_config.active_speed == SPEED_1000 &&
3685             tp->link_config.active_duplex == DUPLEX_HALF)
3686                 tw32(MAC_TX_LENGTHS,
3687                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3688                       (6 << TX_LENGTHS_IPG_SHIFT) |
3689                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3690         else
3691                 tw32(MAC_TX_LENGTHS,
3692                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3693                       (6 << TX_LENGTHS_IPG_SHIFT) |
3694                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3695
3696         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3697                 if (netif_carrier_ok(tp->dev)) {
3698                         tw32(HOSTCC_STAT_COAL_TICKS,
3699                              tp->coal.stats_block_coalesce_usecs);
3700                 } else {
3701                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
3702                 }
3703         }
3704
3705         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
3706                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
3707                 if (!netif_carrier_ok(tp->dev))
3708                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
3709                               tp->pwrmgmt_thresh;
3710                 else
3711                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
3712                 tw32(PCIE_PWR_MGMT_THRESH, val);
3713         }
3714
3715         return err;
3716 }
3717
3718 /* This is called whenever we suspect that the system chipset is re-
3719  * ordering the sequence of MMIO to the tx send mailbox. The symptom
3720  * is bogus tx completions. We try to recover by setting the
3721  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3722  * in the workqueue.
3723  */
3724 static void tg3_tx_recover(struct tg3 *tp)
3725 {
3726         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3727                tp->write32_tx_mbox == tg3_write_indirect_mbox);
3728
3729         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3730                "mapped I/O cycles to the network device, attempting to "
3731                "recover. Please report the problem to the driver maintainer "
3732                "and include system chipset information.\n", tp->dev->name);
3733
3734         spin_lock(&tp->lock);
3735         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3736         spin_unlock(&tp->lock);
3737 }
3738
3739 static inline u32 tg3_tx_avail(struct tg3 *tp)
3740 {
3741         smp_mb();
3742         return (tp->tx_pending -
3743                 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3744 }
3745
3746 /* Tigon3 never reports partial packet sends.  So we do not
3747  * need special logic to handle SKBs that have not had all
3748  * of their frags sent yet, like SunGEM does.
3749  */
3750 static void tg3_tx(struct tg3 *tp)
3751 {
3752         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3753         u32 sw_idx = tp->tx_cons;
3754
3755         while (sw_idx != hw_idx) {
3756                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3757                 struct sk_buff *skb = ri->skb;
3758                 int i, tx_bug = 0;
3759
3760                 if (unlikely(skb == NULL)) {
3761                         tg3_tx_recover(tp);
3762                         return;
3763                 }
3764
3765                 pci_unmap_single(tp->pdev,
3766                                  pci_unmap_addr(ri, mapping),
3767                                  skb_headlen(skb),
3768                                  PCI_DMA_TODEVICE);
3769
3770                 ri->skb = NULL;
3771
3772                 sw_idx = NEXT_TX(sw_idx);
3773
3774                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3775                         ri = &tp->tx_buffers[sw_idx];
3776                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3777                                 tx_bug = 1;
3778
3779                         pci_unmap_page(tp->pdev,
3780                                        pci_unmap_addr(ri, mapping),
3781                                        skb_shinfo(skb)->frags[i].size,
3782                                        PCI_DMA_TODEVICE);
3783
3784                         sw_idx = NEXT_TX(sw_idx);
3785                 }
3786
3787                 dev_kfree_skb(skb);
3788
3789                 if (unlikely(tx_bug)) {
3790                         tg3_tx_recover(tp);
3791                         return;
3792                 }
3793         }
3794
3795         tp->tx_cons = sw_idx;
3796
3797         /* Need to make the tx_cons update visible to tg3_start_xmit()
3798          * before checking for netif_queue_stopped().  Without the
3799          * memory barrier, there is a small possibility that tg3_start_xmit()
3800          * will miss it and cause the queue to be stopped forever.
3801          */
3802         smp_mb();
3803
3804         if (unlikely(netif_queue_stopped(tp->dev) &&
3805                      (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3806                 netif_tx_lock(tp->dev);
3807                 if (netif_queue_stopped(tp->dev) &&
3808                     (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3809                         netif_wake_queue(tp->dev);
3810                 netif_tx_unlock(tp->dev);
3811         }
3812 }
3813
3814 /* Returns size of skb allocated or < 0 on error.
3815  *
3816  * We only need to fill in the address because the other members
3817  * of the RX descriptor are invariant, see tg3_init_rings.
3818  *
3819  * Note the purposeful assymetry of cpu vs. chip accesses.  For
3820  * posting buffers we only dirty the first cache line of the RX
3821  * descriptor (containing the address).  Whereas for the RX status
3822  * buffers the cpu only reads the last cacheline of the RX descriptor
3823  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3824  */
3825 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3826                             int src_idx, u32 dest_idx_unmasked)
3827 {
3828         struct tg3_rx_buffer_desc *desc;
3829         struct ring_info *map, *src_map;
3830         struct sk_buff *skb;
3831         dma_addr_t mapping;
3832         int skb_size, dest_idx;
3833
3834         src_map = NULL;
3835         switch (opaque_key) {
3836         case RXD_OPAQUE_RING_STD:
3837                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3838                 desc = &tp->rx_std[dest_idx];
3839                 map = &tp->rx_std_buffers[dest_idx];
3840                 if (src_idx >= 0)
3841                         src_map = &tp->rx_std_buffers[src_idx];
3842                 skb_size = tp->rx_pkt_buf_sz;
3843                 break;
3844
3845         case RXD_OPAQUE_RING_JUMBO:
3846                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3847                 desc = &tp->rx_jumbo[dest_idx];
3848                 map = &tp->rx_jumbo_buffers[dest_idx];
3849                 if (src_idx >= 0)
3850                         src_map = &tp->rx_jumbo_buffers[src_idx];
3851                 skb_size = RX_JUMBO_PKT_BUF_SZ;
3852                 break;
3853
3854         default:
3855                 return -EINVAL;
3856         };
3857
3858         /* Do not overwrite any of the map or rp information
3859          * until we are sure we can commit to a new buffer.
3860          *
3861          * Callers depend upon this behavior and assume that
3862          * we leave everything unchanged if we fail.
3863          */
3864         skb = netdev_alloc_skb(tp->dev, skb_size);
3865         if (skb == NULL)
3866                 return -ENOMEM;
3867
3868         skb_reserve(skb, tp->rx_offset);
3869
3870         mapping = pci_map_single(tp->pdev, skb->data,
3871                                  skb_size - tp->rx_offset,
3872                                  PCI_DMA_FROMDEVICE);
3873
3874         map->skb = skb;
3875         pci_unmap_addr_set(map, mapping, mapping);
3876
3877         if (src_map != NULL)
3878                 src_map->skb = NULL;
3879
3880         desc->addr_hi = ((u64)mapping >> 32);
3881         desc->addr_lo = ((u64)mapping & 0xffffffff);
3882
3883         return skb_size;
3884 }
3885
3886 /* We only need to move over in the address because the other
3887  * members of the RX descriptor are invariant.  See notes above
3888  * tg3_alloc_rx_skb for full details.
3889  */
3890 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3891                            int src_idx, u32 dest_idx_unmasked)
3892 {
3893         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3894         struct ring_info *src_map, *dest_map;
3895         int dest_idx;
3896
3897         switch (opaque_key) {
3898         case RXD_OPAQUE_RING_STD:
3899                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3900                 dest_desc = &tp->rx_std[dest_idx];
3901                 dest_map = &tp->rx_std_buffers[dest_idx];
3902                 src_desc = &tp->rx_std[src_idx];
3903                 src_map = &tp->rx_std_buffers[src_idx];
3904                 break;
3905
3906         case RXD_OPAQUE_RING_JUMBO:
3907                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3908                 dest_desc = &tp->rx_jumbo[dest_idx];
3909                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3910                 src_desc = &tp->rx_jumbo[src_idx];
3911                 src_map = &tp->rx_jumbo_buffers[src_idx];
3912                 break;
3913
3914         default:
3915                 return;
3916         };
3917
3918         dest_map->skb = src_map->skb;
3919         pci_unmap_addr_set(dest_map, mapping,
3920                            pci_unmap_addr(src_map, mapping));
3921         dest_desc->addr_hi = src_desc->addr_hi;
3922         dest_desc->addr_lo = src_desc->addr_lo;
3923
3924         src_map->skb = NULL;
3925 }
3926
3927 #if TG3_VLAN_TAG_USED
3928 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3929 {
3930         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3931 }
3932 #endif
3933
3934 /* The RX ring scheme is composed of multiple rings which post fresh
3935  * buffers to the chip, and one special ring the chip uses to report
3936  * status back to the host.
3937  *
3938  * The special ring reports the status of received packets to the
3939  * host.  The chip does not write into the original descriptor the
3940  * RX buffer was obtained from.  The chip simply takes the original
3941  * descriptor as provided by the host, updates the status and length
3942  * field, then writes this into the next status ring entry.
3943  *
3944  * Each ring the host uses to post buffers to the chip is described
3945  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
3946  * it is first placed into the on-chip ram.  When the packet's length
3947  * is known, it walks down the TG3_BDINFO entries to select the ring.
3948  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3949  * which is within the range of the new packet's length is chosen.
3950  *
3951  * The "separate ring for rx status" scheme may sound queer, but it makes
3952  * sense from a cache coherency perspective.  If only the host writes
3953  * to the buffer post rings, and only the chip writes to the rx status
3954  * rings, then cache lines never move beyond shared-modified state.
3955  * If both the host and chip were to write into the same ring, cache line
3956  * eviction could occur since both entities want it in an exclusive state.
3957  */
3958 static int tg3_rx(struct tg3 *tp, int budget)
3959 {
3960         u32 work_mask, rx_std_posted = 0;
3961         u32 sw_idx = tp->rx_rcb_ptr;
3962         u16 hw_idx;
3963         int received;
3964
3965         hw_idx = tp->hw_status->idx[0].rx_producer;
3966         /*
3967          * We need to order the read of hw_idx and the read of
3968          * the opaque cookie.
3969          */
3970         rmb();
3971         work_mask = 0;
3972         received = 0;
3973         while (sw_idx != hw_idx && budget > 0) {
3974                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3975                 unsigned int len;
3976                 struct sk_buff *skb;
3977                 dma_addr_t dma_addr;
3978                 u32 opaque_key, desc_idx, *post_ptr;
3979
3980                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3981                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3982                 if (opaque_key == RXD_OPAQUE_RING_STD) {
3983                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3984                                                   mapping);
3985                         skb = tp->rx_std_buffers[desc_idx].skb;
3986                         post_ptr = &tp->rx_std_ptr;
3987                         rx_std_posted++;
3988                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3989                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3990                                                   mapping);
3991                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
3992                         post_ptr = &tp->rx_jumbo_ptr;
3993                 }
3994                 else {
3995                         goto next_pkt_nopost;
3996                 }
3997
3998                 work_mask |= opaque_key;
3999
4000                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4001                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4002                 drop_it:
4003                         tg3_recycle_rx(tp, opaque_key,
4004                                        desc_idx, *post_ptr);
4005                 drop_it_no_recycle:
4006                         /* Other statistics kept track of by card. */
4007                         tp->net_stats.rx_dropped++;
4008                         goto next_pkt;
4009                 }
4010
4011                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
4012
4013                 if (len > RX_COPY_THRESHOLD
4014                         && tp->rx_offset == 2
4015                         /* rx_offset != 2 iff this is a 5701 card running
4016                          * in PCI-X mode [see tg3_get_invariants()] */
4017                 ) {
4018                         int skb_size;
4019
4020                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
4021                                                     desc_idx, *post_ptr);
4022                         if (skb_size < 0)
4023                                 goto drop_it;
4024
4025                         pci_unmap_single(tp->pdev, dma_addr,
4026                                          skb_size - tp->rx_offset,
4027                                          PCI_DMA_FROMDEVICE);
4028
4029                         skb_put(skb, len);
4030                 } else {
4031                         struct sk_buff *copy_skb;
4032
4033                         tg3_recycle_rx(tp, opaque_key,
4034                                        desc_idx, *post_ptr);
4035
4036                         copy_skb = netdev_alloc_skb(tp->dev, len + 2);
4037                         if (copy_skb == NULL)
4038                                 goto drop_it_no_recycle;
4039
4040                         skb_reserve(copy_skb, 2);
4041                         skb_put(copy_skb, len);
4042                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4043                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4044                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4045
4046                         /* We'll reuse the original ring buffer. */
4047                         skb = copy_skb;
4048                 }
4049
4050                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4051                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4052                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4053                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4054                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4055                 else
4056                         skb->ip_summed = CHECKSUM_NONE;
4057
4058                 skb->protocol = eth_type_trans(skb, tp->dev);
4059 #if TG3_VLAN_TAG_USED
4060                 if (tp->vlgrp != NULL &&
4061                     desc->type_flags & RXD_FLAG_VLAN) {
4062                         tg3_vlan_rx(tp, skb,
4063                                     desc->err_vlan & RXD_VLAN_MASK);
4064                 } else
4065 #endif
4066                         netif_receive_skb(skb);
4067
4068                 tp->dev->last_rx = jiffies;
4069                 received++;
4070                 budget--;
4071
4072 next_pkt:
4073                 (*post_ptr)++;
4074
4075                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4076                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4077
4078                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4079                                      TG3_64BIT_REG_LOW, idx);
4080                         work_mask &= ~RXD_OPAQUE_RING_STD;
4081                         rx_std_posted = 0;
4082                 }
4083 next_pkt_nopost:
4084                 sw_idx++;
4085                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4086
4087                 /* Refresh hw_idx to see if there is new work */
4088                 if (sw_idx == hw_idx) {
4089                         hw_idx = tp->hw_status->idx[0].rx_producer;
4090                         rmb();
4091                 }
4092         }
4093
4094         /* ACK the status ring. */
4095         tp->rx_rcb_ptr = sw_idx;
4096         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
4097
4098         /* Refill RX ring(s). */
4099         if (work_mask & RXD_OPAQUE_RING_STD) {
4100                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
4101                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4102                              sw_idx);
4103         }
4104         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4105                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
4106                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4107                              sw_idx);
4108         }
4109         mmiowb();
4110
4111         return received;
4112 }
4113
4114 static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
4115 {
4116         struct tg3_hw_status *sblk = tp->hw_status;
4117
4118         /* handle link change and other phy events */
4119         if (!(tp->tg3_flags &
4120               (TG3_FLAG_USE_LINKCHG_REG |
4121                TG3_FLAG_POLL_SERDES))) {
4122                 if (sblk->status & SD_STATUS_LINK_CHG) {
4123                         sblk->status = SD_STATUS_UPDATED |
4124                                 (sblk->status & ~SD_STATUS_LINK_CHG);
4125                         spin_lock(&tp->lock);
4126                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4127                                 tw32_f(MAC_STATUS,
4128                                      (MAC_STATUS_SYNC_CHANGED |
4129                                       MAC_STATUS_CFG_CHANGED |
4130                                       MAC_STATUS_MI_COMPLETION |
4131                                       MAC_STATUS_LNKSTATE_CHANGED));
4132                                 udelay(40);
4133                         } else
4134                                 tg3_setup_phy(tp, 0);
4135                         spin_unlock(&tp->lock);
4136                 }
4137         }
4138
4139         /* run TX completion thread */
4140         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
4141                 tg3_tx(tp);
4142                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4143                         return work_done;
4144         }
4145
4146         /* run RX thread, within the bounds set by NAPI.
4147          * All RX "locking" is done by ensuring outside
4148          * code synchronizes with tg3->napi.poll()
4149          */
4150         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
4151                 work_done += tg3_rx(tp, budget - work_done);
4152
4153         return work_done;
4154 }
4155
4156 static int tg3_poll(struct napi_struct *napi, int budget)
4157 {
4158         struct tg3 *tp = container_of(napi, struct tg3, napi);
4159         int work_done = 0;
4160         struct tg3_hw_status *sblk = tp->hw_status;
4161
4162         while (1) {
4163                 work_done = tg3_poll_work(tp, work_done, budget);
4164
4165                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4166                         goto tx_recovery;
4167
4168                 if (unlikely(work_done >= budget))
4169                         break;
4170
4171                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4172                         /* tp->last_tag is used in tg3_restart_ints() below
4173                          * to tell the hw how much work has been processed,
4174                          * so we must read it before checking for more work.
4175                          */
4176                         tp->last_tag = sblk->status_tag;
4177                         rmb();
4178                 } else
4179                         sblk->status &= ~SD_STATUS_UPDATED;
4180
4181                 if (likely(!tg3_has_work(tp))) {
4182                         netif_rx_complete(tp->dev, napi);
4183                         tg3_restart_ints(tp);
4184                         break;
4185                 }
4186         }
4187
4188         return work_done;
4189
4190 tx_recovery:
4191         /* work_done is guaranteed to be less than budget. */
4192         netif_rx_complete(tp->dev, napi);
4193         schedule_work(&tp->reset_task);
4194         return work_done;
4195 }
4196
4197 static void tg3_irq_quiesce(struct tg3 *tp)
4198 {
4199         BUG_ON(tp->irq_sync);
4200
4201         tp->irq_sync = 1;
4202         smp_mb();
4203
4204         synchronize_irq(tp->pdev->irq);
4205 }
4206
4207 static inline int tg3_irq_sync(struct tg3 *tp)
4208 {
4209         return tp->irq_sync;
4210 }
4211
4212 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4213  * If irq_sync is non-zero, then the IRQ handler must be synchronized
4214  * with as well.  Most of the time, this is not necessary except when
4215  * shutting down the device.
4216  */
4217 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4218 {
4219         spin_lock_bh(&tp->lock);
4220         if (irq_sync)
4221                 tg3_irq_quiesce(tp);
4222 }
4223
4224 static inline void tg3_full_unlock(struct tg3 *tp)
4225 {
4226         spin_unlock_bh(&tp->lock);
4227 }
4228
4229 /* One-shot MSI handler - Chip automatically disables interrupt
4230  * after sending MSI so driver doesn't have to do it.
4231  */
4232 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4233 {
4234         struct net_device *dev = dev_id;
4235         struct tg3 *tp = netdev_priv(dev);
4236
4237         prefetch(tp->hw_status);
4238         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4239
4240         if (likely(!tg3_irq_sync(tp)))
4241                 netif_rx_schedule(dev, &tp->napi);
4242
4243         return IRQ_HANDLED;
4244 }
4245
4246 /* MSI ISR - No need to check for interrupt sharing and no need to
4247  * flush status block and interrupt mailbox. PCI ordering rules
4248  * guarantee that MSI will arrive after the status block.
4249  */
4250 static irqreturn_t tg3_msi(int irq, void *dev_id)
4251 {
4252         struct net_device *dev = dev_id;
4253         struct tg3 *tp = netdev_priv(dev);
4254
4255         prefetch(tp->hw_status);
4256         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4257         /*
4258          * Writing any value to intr-mbox-0 clears PCI INTA# and
4259          * chip-internal interrupt pending events.
4260          * Writing non-zero to intr-mbox-0 additional tells the
4261          * NIC to stop sending us irqs, engaging "in-intr-handler"
4262          * event coalescing.
4263          */
4264         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4265         if (likely(!tg3_irq_sync(tp)))
4266                 netif_rx_schedule(dev, &tp->napi);
4267
4268         return IRQ_RETVAL(1);
4269 }
4270
4271 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4272 {
4273         struct net_device *dev = dev_id;
4274         struct tg3 *tp = netdev_priv(dev);
4275         struct tg3_hw_status *sblk = tp->hw_status;
4276         unsigned int handled = 1;
4277
4278         /* In INTx mode, it is possible for the interrupt to arrive at
4279          * the CPU before the status block posted prior to the interrupt.
4280          * Reading the PCI State register will confirm whether the
4281          * interrupt is ours and will flush the status block.
4282          */
4283         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4284                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4285                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4286                         handled = 0;
4287                         goto out;
4288                 }
4289         }
4290
4291         /*
4292          * Writing any value to intr-mbox-0 clears PCI INTA# and
4293          * chip-internal interrupt pending events.
4294          * Writing non-zero to intr-mbox-0 additional tells the
4295          * NIC to stop sending us irqs, engaging "in-intr-handler"
4296          * event coalescing.
4297          *
4298          * Flush the mailbox to de-assert the IRQ immediately to prevent
4299          * spurious interrupts.  The flush impacts performance but
4300          * excessive spurious interrupts can be worse in some cases.
4301          */
4302         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4303         if (tg3_irq_sync(tp))
4304                 goto out;
4305         sblk->status &= ~SD_STATUS_UPDATED;
4306         if (likely(tg3_has_work(tp))) {
4307                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4308                 netif_rx_schedule(dev, &tp->napi);
4309         } else {
4310                 /* No work, shared interrupt perhaps?  re-enable
4311                  * interrupts, and flush that PCI write
4312                  */
4313                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4314                                0x00000000);
4315         }
4316 out:
4317         return IRQ_RETVAL(handled);
4318 }
4319
4320 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4321 {
4322         struct net_device *dev = dev_id;
4323         struct tg3 *tp = netdev_priv(dev);
4324         struct tg3_hw_status *sblk = tp->hw_status;
4325         unsigned int handled = 1;
4326
4327         /* In INTx mode, it is possible for the interrupt to arrive at
4328          * the CPU before the status block posted prior to the interrupt.
4329          * Reading the PCI State register will confirm whether the
4330          * interrupt is ours and will flush the status block.
4331          */
4332         if (unlikely(sblk->status_tag == tp->last_tag)) {
4333                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4334                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4335                         handled = 0;
4336                         goto out;
4337                 }
4338         }
4339
4340         /*
4341          * writing any value to intr-mbox-0 clears PCI INTA# and
4342          * chip-internal interrupt pending events.
4343          * writing non-zero to intr-mbox-0 additional tells the
4344          * NIC to stop sending us irqs, engaging "in-intr-handler"
4345          * event coalescing.
4346          *
4347          * Flush the mailbox to de-assert the IRQ immediately to prevent
4348          * spurious interrupts.  The flush impacts performance but
4349          * excessive spurious interrupts can be worse in some cases.
4350          */
4351         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4352         if (tg3_irq_sync(tp))
4353                 goto out;
4354         if (netif_rx_schedule_prep(dev, &tp->napi)) {
4355                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4356                 /* Update last_tag to mark that this status has been
4357                  * seen. Because interrupt may be shared, we may be
4358                  * racing with tg3_poll(), so only update last_tag
4359                  * if tg3_poll() is not scheduled.
4360                  */
4361                 tp->last_tag = sblk->status_tag;
4362                 __netif_rx_schedule(dev, &tp->napi);
4363         }
4364 out:
4365         return IRQ_RETVAL(handled);
4366 }
4367
4368 /* ISR for interrupt test */
4369 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4370 {
4371         struct net_device *dev = dev_id;
4372         struct tg3 *tp = netdev_priv(dev);
4373         struct tg3_hw_status *sblk = tp->hw_status;
4374
4375         if ((sblk->status & SD_STATUS_UPDATED) ||
4376             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4377                 tg3_disable_ints(tp);
4378                 return IRQ_RETVAL(1);
4379         }
4380         return IRQ_RETVAL(0);
4381 }
4382
4383 static int tg3_init_hw(struct tg3 *, int);
4384 static int tg3_halt(struct tg3 *, int, int);
4385
4386 /* Restart hardware after configuration changes, self-test, etc.
4387  * Invoked with tp->lock held.
4388  */
4389 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4390         __releases(tp->lock)
4391         __acquires(tp->lock)
4392 {
4393         int err;
4394
4395         err = tg3_init_hw(tp, reset_phy);
4396         if (err) {
4397                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4398                        "aborting.\n", tp->dev->name);
4399                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4400                 tg3_full_unlock(tp);
4401                 del_timer_sync(&tp->timer);
4402                 tp->irq_sync = 0;
4403                 napi_enable(&tp->napi);
4404                 dev_close(tp->dev);
4405                 tg3_full_lock(tp, 0);
4406         }
4407         return err;
4408 }
4409
4410 #ifdef CONFIG_NET_POLL_CONTROLLER
4411 static void tg3_poll_controller(struct net_device *dev)
4412 {
4413         struct tg3 *tp = netdev_priv(dev);
4414
4415         tg3_interrupt(tp->pdev->irq, dev);
4416 }
4417 #endif
4418
4419 static void tg3_reset_task(struct work_struct *work)
4420 {
4421         struct tg3 *tp = container_of(work, struct tg3, reset_task);
4422         int err;
4423         unsigned int restart_timer;
4424
4425         tg3_full_lock(tp, 0);
4426
4427         if (!netif_running(tp->dev)) {
4428                 tg3_full_unlock(tp);
4429                 return;
4430         }
4431
4432         tg3_full_unlock(tp);
4433
4434         tg3_phy_stop(tp);
4435
4436         tg3_netif_stop(tp);
4437
4438         tg3_full_lock(tp, 1);
4439
4440         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4441         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4442
4443         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4444                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4445                 tp->write32_rx_mbox = tg3_write_flush_reg32;
4446                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4447                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4448         }
4449
4450         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
4451         err = tg3_init_hw(tp, 1);
4452         if (err)
4453                 goto out;
4454
4455         tg3_netif_start(tp);
4456
4457         if (restart_timer)
4458                 mod_timer(&tp->timer, jiffies + 1);
4459
4460 out:
4461         tg3_full_unlock(tp);
4462
4463         if (!err)
4464                 tg3_phy_start(tp);
4465 }
4466
4467 static void tg3_dump_short_state(struct tg3 *tp)
4468 {
4469         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
4470                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
4471         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
4472                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
4473 }
4474
4475 static void tg3_tx_timeout(struct net_device *dev)
4476 {
4477         struct tg3 *tp = netdev_priv(dev);
4478
4479         if (netif_msg_tx_err(tp)) {
4480                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
4481                        dev->name);
4482                 tg3_dump_short_state(tp);
4483         }
4484
4485         schedule_work(&tp->reset_task);
4486 }
4487
4488 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
4489 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
4490 {
4491         u32 base = (u32) mapping & 0xffffffff;
4492
4493         return ((base > 0xffffdcc0) &&
4494                 (base + len + 8 < base));
4495 }
4496
4497 /* Test for DMA addresses > 40-bit */
4498 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
4499                                           int len)
4500 {
4501 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
4502         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
4503                 return (((u64) mapping + len) > DMA_40BIT_MASK);
4504         return 0;
4505 #else
4506         return 0;
4507 #endif
4508 }
4509
4510 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
4511
4512 /* Workaround 4GB and 40-bit hardware DMA bugs. */
4513 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
4514                                        u32 last_plus_one, u32 *start,
4515                                        u32 base_flags, u32 mss)
4516 {
4517         struct sk_buff *new_skb;
4518         dma_addr_t new_addr = 0;
4519         u32 entry = *start;
4520         int i, ret = 0;
4521
4522         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
4523                 new_skb = skb_copy(skb, GFP_ATOMIC);
4524         else {
4525                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
4526
4527                 new_skb = skb_copy_expand(skb,
4528                                           skb_headroom(skb) + more_headroom,
4529                                           skb_tailroom(skb), GFP_ATOMIC);
4530         }
4531
4532         if (!new_skb) {
4533                 ret = -1;
4534         } else {
4535                 /* New SKB is guaranteed to be linear. */
4536                 entry = *start;
4537                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
4538                                           PCI_DMA_TODEVICE);
4539                 /* Make sure new skb does not cross any 4G boundaries.
4540                  * Drop the packet if it does.
4541                  */
4542                 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
4543                         ret = -1;
4544                         dev_kfree_skb(new_skb);
4545                         new_skb = NULL;
4546                 } else {
4547                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
4548                                     base_flags, 1 | (mss << 1));
4549                         *start = NEXT_TX(entry);
4550                 }
4551         }
4552
4553         /* Now clean up the sw ring entries. */
4554         i = 0;
4555         while (entry != last_plus_one) {
4556                 int len;
4557
4558                 if (i == 0)
4559                         len = skb_headlen(skb);
4560                 else
4561                         len = skb_shinfo(skb)->frags[i-1].size;
4562                 pci_unmap_single(tp->pdev,
4563                                  pci_unmap_addr(&tp->tx_buffers[entry], mapping),
4564                                  len, PCI_DMA_TODEVICE);
4565                 if (i == 0) {
4566                         tp->tx_buffers[entry].skb = new_skb;
4567                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
4568                 } else {
4569                         tp->tx_buffers[entry].skb = NULL;
4570                 }
4571                 entry = NEXT_TX(entry);
4572                 i++;
4573         }
4574
4575         dev_kfree_skb(skb);
4576
4577         return ret;
4578 }
4579
4580 static void tg3_set_txd(struct tg3 *tp, int entry,
4581                         dma_addr_t mapping, int len, u32 flags,
4582                         u32 mss_and_is_end)
4583 {
4584         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
4585         int is_end = (mss_and_is_end & 0x1);
4586         u32 mss = (mss_and_is_end >> 1);
4587         u32 vlan_tag = 0;
4588
4589         if (is_end)
4590                 flags |= TXD_FLAG_END;
4591         if (flags & TXD_FLAG_VLAN) {
4592                 vlan_tag = flags >> 16;
4593                 flags &= 0xffff;
4594         }
4595         vlan_tag |= (mss << TXD_MSS_SHIFT);
4596
4597         txd->addr_hi = ((u64) mapping >> 32);
4598         txd->addr_lo = ((u64) mapping & 0xffffffff);
4599         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
4600         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
4601 }
4602
4603 /* hard_start_xmit for devices that don't have any bugs and
4604  * support TG3_FLG2_HW_TSO_2 only.
4605  */
4606 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
4607 {
4608         struct tg3 *tp = netdev_priv(dev);
4609         dma_addr_t mapping;
4610         u32 len, entry, base_flags, mss;
4611
4612         len = skb_headlen(skb);
4613
4614         /* We are running in BH disabled context with netif_tx_lock
4615          * and TX reclaim runs via tp->napi.poll inside of a software
4616          * interrupt.  Furthermore, IRQ processing runs lockless so we have
4617          * no IRQ context deadlocks to worry about either.  Rejoice!
4618          */
4619         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4620                 if (!netif_queue_stopped(dev)) {
4621                         netif_stop_queue(dev);
4622
4623                         /* This is a hard error, log it. */
4624                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4625                                "queue awake!\n", dev->name);
4626                 }
4627                 return NETDEV_TX_BUSY;
4628         }
4629
4630         entry = tp->tx_prod;
4631         base_flags = 0;
4632         mss = 0;
4633         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4634                 int tcp_opt_len, ip_tcp_len;
4635
4636                 if (skb_header_cloned(skb) &&
4637                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4638                         dev_kfree_skb(skb);
4639                         goto out_unlock;
4640                 }
4641
4642                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
4643                         mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
4644                 else {
4645                         struct iphdr *iph = ip_hdr(skb);
4646
4647                         tcp_opt_len = tcp_optlen(skb);
4648                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4649
4650                         iph->check = 0;
4651                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
4652                         mss |= (ip_tcp_len + tcp_opt_len) << 9;
4653                 }
4654
4655                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4656                                TXD_FLAG_CPU_POST_DMA);
4657
4658                 tcp_hdr(skb)->check = 0;
4659
4660         }
4661         else if (skb->ip_summed == CHECKSUM_PARTIAL)
4662                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4663 #if TG3_VLAN_TAG_USED
4664         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4665                 base_flags |= (TXD_FLAG_VLAN |
4666                                (vlan_tx_tag_get(skb) << 16));
4667 #endif
4668
4669         /* Queue skb data, a.k.a. the main skb fragment. */
4670         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4671
4672         tp->tx_buffers[entry].skb = skb;
4673         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4674
4675         tg3_set_txd(tp, entry, mapping, len, base_flags,
4676                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4677
4678         entry = NEXT_TX(entry);
4679
4680         /* Now loop through additional data fragments, and queue them. */
4681         if (skb_shinfo(skb)->nr_frags > 0) {
4682                 unsigned int i, last;
4683
4684                 last = skb_shinfo(skb)->nr_frags - 1;
4685                 for (i = 0; i <= last; i++) {
4686                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4687
4688                         len = frag->size;
4689                         mapping = pci_map_page(tp->pdev,
4690                                                frag->page,
4691                                                frag->page_offset,
4692                                                len, PCI_DMA_TODEVICE);
4693
4694                         tp->tx_buffers[entry].skb = NULL;
4695                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4696
4697                         tg3_set_txd(tp, entry, mapping, len,
4698                                     base_flags, (i == last) | (mss << 1));
4699
4700                         entry = NEXT_TX(entry);
4701                 }
4702         }
4703
4704         /* Packets are ready, update Tx producer idx local and on card. */
4705         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4706
4707         tp->tx_prod = entry;
4708         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4709                 netif_stop_queue(dev);
4710                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4711                         netif_wake_queue(tp->dev);
4712         }
4713
4714 out_unlock:
4715         mmiowb();
4716
4717         dev->trans_start = jiffies;
4718
4719         return NETDEV_TX_OK;
4720 }
4721
4722 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
4723
4724 /* Use GSO to workaround a rare TSO bug that may be triggered when the
4725  * TSO header is greater than 80 bytes.
4726  */
4727 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
4728 {
4729         struct sk_buff *segs, *nskb;
4730
4731         /* Estimate the number of fragments in the worst case */
4732         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
4733                 netif_stop_queue(tp->dev);
4734                 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
4735                         return NETDEV_TX_BUSY;
4736
4737                 netif_wake_queue(tp->dev);
4738         }
4739
4740         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
4741         if (IS_ERR(segs))
4742                 goto tg3_tso_bug_end;
4743
4744         do {
4745                 nskb = segs;
4746                 segs = segs->next;
4747                 nskb->next = NULL;
4748                 tg3_start_xmit_dma_bug(nskb, tp->dev);
4749         } while (segs);
4750
4751 tg3_tso_bug_end:
4752         dev_kfree_skb(skb);
4753
4754         return NETDEV_TX_OK;
4755 }
4756
4757 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
4758  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
4759  */
4760 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
4761 {
4762         struct tg3 *tp = netdev_priv(dev);
4763         dma_addr_t mapping;
4764         u32 len, entry, base_flags, mss;
4765         int would_hit_hwbug;
4766
4767         len = skb_headlen(skb);
4768
4769         /* We are running in BH disabled context with netif_tx_lock
4770          * and TX reclaim runs via tp->napi.poll inside of a software
4771          * interrupt.  Furthermore, IRQ processing runs lockless so we have
4772          * no IRQ context deadlocks to worry about either.  Rejoice!
4773          */
4774         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4775                 if (!netif_queue_stopped(dev)) {
4776                         netif_stop_queue(dev);
4777
4778                         /* This is a hard error, log it. */
4779                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4780                                "queue awake!\n", dev->name);
4781                 }
4782                 return NETDEV_TX_BUSY;
4783         }
4784
4785         entry = tp->tx_prod;
4786         base_flags = 0;
4787         if (skb->ip_summed == CHECKSUM_PARTIAL)
4788                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4789         mss = 0;
4790         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4791                 struct iphdr *iph;
4792                 int tcp_opt_len, ip_tcp_len, hdr_len;
4793
4794                 if (skb_header_cloned(skb) &&
4795                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4796                         dev_kfree_skb(skb);
4797                         goto out_unlock;
4798                 }
4799
4800                 tcp_opt_len = tcp_optlen(skb);
4801                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4802
4803                 hdr_len = ip_tcp_len + tcp_opt_len;
4804                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4805                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
4806                         return (tg3_tso_bug(tp, skb));
4807
4808                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4809                                TXD_FLAG_CPU_POST_DMA);
4810
4811                 iph = ip_hdr(skb);
4812                 iph->check = 0;
4813                 iph->tot_len = htons(mss + hdr_len);
4814                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4815                         tcp_hdr(skb)->check = 0;
4816                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4817                 } else
4818                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4819                                                                  iph->daddr, 0,
4820                                                                  IPPROTO_TCP,
4821                                                                  0);
4822
4823                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4824                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4825                         if (tcp_opt_len || iph->ihl > 5) {
4826                                 int tsflags;
4827
4828                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4829                                 mss |= (tsflags << 11);
4830                         }
4831                 } else {
4832                         if (tcp_opt_len || iph->ihl > 5) {
4833                                 int tsflags;
4834
4835                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4836                                 base_flags |= tsflags << 12;
4837                         }
4838                 }
4839         }
4840 #if TG3_VLAN_TAG_USED
4841         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4842                 base_flags |= (TXD_FLAG_VLAN |
4843                                (vlan_tx_tag_get(skb) << 16));
4844 #endif
4845
4846         /* Queue skb data, a.k.a. the main skb fragment. */
4847         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4848
4849         tp->tx_buffers[entry].skb = skb;
4850         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4851
4852         would_hit_hwbug = 0;
4853
4854         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
4855                 would_hit_hwbug = 1;
4856         else if (tg3_4g_overflow_test(mapping, len))
4857                 would_hit_hwbug = 1;
4858
4859         tg3_set_txd(tp, entry, mapping, len, base_flags,
4860                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4861
4862         entry = NEXT_TX(entry);
4863
4864         /* Now loop through additional data fragments, and queue them. */
4865         if (skb_shinfo(skb)->nr_frags > 0) {
4866                 unsigned int i, last;
4867
4868                 last = skb_shinfo(skb)->nr_frags - 1;
4869                 for (i = 0; i <= last; i++) {
4870                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4871
4872                         len = frag->size;
4873                         mapping = pci_map_page(tp->pdev,
4874                                                frag->page,
4875                                                frag->page_offset,
4876                                                len, PCI_DMA_TODEVICE);
4877
4878                         tp->tx_buffers[entry].skb = NULL;
4879                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4880
4881                         if (tg3_4g_overflow_test(mapping, len))
4882                                 would_hit_hwbug = 1;
4883
4884                         if (tg3_40bit_overflow_test(tp, mapping, len))
4885                                 would_hit_hwbug = 1;
4886
4887                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4888                                 tg3_set_txd(tp, entry, mapping, len,
4889                                             base_flags, (i == last)|(mss << 1));
4890                         else
4891                                 tg3_set_txd(tp, entry, mapping, len,
4892                                             base_flags, (i == last));
4893
4894                         entry = NEXT_TX(entry);
4895                 }
4896         }
4897
4898         if (would_hit_hwbug) {
4899                 u32 last_plus_one = entry;
4900                 u32 start;
4901
4902                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4903                 start &= (TG3_TX_RING_SIZE - 1);
4904
4905                 /* If the workaround fails due to memory/mapping
4906                  * failure, silently drop this packet.
4907                  */
4908                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
4909                                                 &start, base_flags, mss))
4910                         goto out_unlock;
4911
4912                 entry = start;
4913         }
4914
4915         /* Packets are ready, update Tx producer idx local and on card. */
4916         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4917
4918         tp->tx_prod = entry;
4919         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4920                 netif_stop_queue(dev);
4921                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4922                         netif_wake_queue(tp->dev);
4923         }
4924
4925 out_unlock:
4926         mmiowb();
4927
4928         dev->trans_start = jiffies;
4929
4930         return NETDEV_TX_OK;
4931 }
4932
4933 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4934                                int new_mtu)
4935 {
4936         dev->mtu = new_mtu;
4937
4938         if (new_mtu > ETH_DATA_LEN) {
4939                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4940                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4941                         ethtool_op_set_tso(dev, 0);
4942                 }
4943                 else
4944                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4945         } else {
4946                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4947                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4948                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
4949         }
4950 }
4951
4952 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4953 {
4954         struct tg3 *tp = netdev_priv(dev);
4955         int err;
4956
4957         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4958                 return -EINVAL;
4959
4960         if (!netif_running(dev)) {
4961                 /* We'll just catch it later when the
4962                  * device is up'd.
4963                  */
4964                 tg3_set_mtu(dev, tp, new_mtu);
4965                 return 0;
4966         }
4967
4968         tg3_phy_stop(tp);
4969
4970         tg3_netif_stop(tp);
4971
4972         tg3_full_lock(tp, 1);
4973
4974         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4975
4976         tg3_set_mtu(dev, tp, new_mtu);
4977
4978         err = tg3_restart_hw(tp, 0);
4979
4980         if (!err)
4981                 tg3_netif_start(tp);
4982
4983         tg3_full_unlock(tp);
4984
4985         if (!err)
4986                 tg3_phy_start(tp);
4987
4988         return err;
4989 }
4990
4991 /* Free up pending packets in all rx/tx rings.
4992  *
4993  * The chip has been shut down and the driver detached from
4994  * the networking, so no interrupts or new tx packets will
4995  * end up in the driver.  tp->{tx,}lock is not held and we are not
4996  * in an interrupt context and thus may sleep.
4997  */
4998 static void tg3_free_rings(struct tg3 *tp)
4999 {
5000         struct ring_info *rxp;
5001         int i;
5002
5003         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5004                 rxp = &tp->rx_std_buffers[i];
5005
5006                 if (rxp->skb == NULL)
5007                         continue;
5008                 pci_unmap_single(tp->pdev,
5009                                  pci_unmap_addr(rxp, mapping),
5010                                  tp->rx_pkt_buf_sz - tp->rx_offset,
5011                                  PCI_DMA_FROMDEVICE);
5012                 dev_kfree_skb_any(rxp->skb);
5013                 rxp->skb = NULL;
5014         }
5015
5016         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5017                 rxp = &tp->rx_jumbo_buffers[i];
5018
5019                 if (rxp->skb == NULL)
5020                         continue;
5021                 pci_unmap_single(tp->pdev,
5022                                  pci_unmap_addr(rxp, mapping),
5023                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
5024                                  PCI_DMA_FROMDEVICE);
5025                 dev_kfree_skb_any(rxp->skb);
5026                 rxp->skb = NULL;
5027         }
5028
5029         for (i = 0; i < TG3_TX_RING_SIZE; ) {
5030                 struct tx_ring_info *txp;
5031                 struct sk_buff *skb;
5032                 int j;
5033
5034                 txp = &tp->tx_buffers[i];
5035                 skb = txp->skb;
5036
5037                 if (skb == NULL) {
5038                         i++;
5039                         continue;
5040                 }
5041
5042                 pci_unmap_single(tp->pdev,
5043                                  pci_unmap_addr(txp, mapping),
5044                                  skb_headlen(skb),
5045                                  PCI_DMA_TODEVICE);
5046                 txp->skb = NULL;
5047
5048                 i++;
5049
5050                 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
5051                         txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
5052                         pci_unmap_page(tp->pdev,
5053                                        pci_unmap_addr(txp, mapping),
5054                                        skb_shinfo(skb)->frags[j].size,
5055                                        PCI_DMA_TODEVICE);
5056                         i++;
5057                 }
5058
5059                 dev_kfree_skb_any(skb);
5060         }
5061 }
5062
5063 /* Initialize tx/rx rings for packet processing.
5064  *
5065  * The chip has been shut down and the driver detached from
5066  * the networking, so no interrupts or new tx packets will
5067  * end up in the driver.  tp->{tx,}lock are held and thus
5068  * we may not sleep.
5069  */
5070 static int tg3_init_rings(struct tg3 *tp)
5071 {
5072         u32 i;
5073
5074         /* Free up all the SKBs. */
5075         tg3_free_rings(tp);
5076
5077         /* Zero out all descriptors. */
5078         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
5079         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
5080         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5081         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
5082
5083         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
5084         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5085             (tp->dev->mtu > ETH_DATA_LEN))
5086                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
5087
5088         /* Initialize invariants of the rings, we only set this
5089          * stuff once.  This works because the card does not
5090          * write into the rx buffer posting rings.
5091          */
5092         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5093                 struct tg3_rx_buffer_desc *rxd;
5094
5095                 rxd = &tp->rx_std[i];
5096                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
5097                         << RXD_LEN_SHIFT;
5098                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5099                 rxd->opaque = (RXD_OPAQUE_RING_STD |
5100                                (i << RXD_OPAQUE_INDEX_SHIFT));
5101         }
5102
5103         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5104                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5105                         struct tg3_rx_buffer_desc *rxd;
5106
5107                         rxd = &tp->rx_jumbo[i];
5108                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
5109                                 << RXD_LEN_SHIFT;
5110                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5111                                 RXD_FLAG_JUMBO;
5112                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5113                                (i << RXD_OPAQUE_INDEX_SHIFT));
5114                 }
5115         }
5116
5117         /* Now allocate fresh SKBs for each rx ring. */
5118         for (i = 0; i < tp->rx_pending; i++) {
5119                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5120                         printk(KERN_WARNING PFX
5121                                "%s: Using a smaller RX standard ring, "
5122                                "only %d out of %d buffers were allocated "
5123                                "successfully.\n",
5124                                tp->dev->name, i, tp->rx_pending);
5125                         if (i == 0)
5126                                 return -ENOMEM;
5127                         tp->rx_pending = i;
5128                         break;
5129                 }
5130         }
5131
5132         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5133                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5134                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
5135                                              -1, i) < 0) {
5136                                 printk(KERN_WARNING PFX
5137                                        "%s: Using a smaller RX jumbo ring, "
5138                                        "only %d out of %d buffers were "
5139                                        "allocated successfully.\n",
5140                                        tp->dev->name, i, tp->rx_jumbo_pending);
5141                                 if (i == 0) {
5142                                         tg3_free_rings(tp);
5143                                         return -ENOMEM;
5144                                 }
5145                                 tp->rx_jumbo_pending = i;
5146                                 break;
5147                         }
5148                 }
5149         }
5150         return 0;
5151 }
5152
5153 /*
5154  * Must not be invoked with interrupt sources disabled and
5155  * the hardware shutdown down.
5156  */
5157 static void tg3_free_consistent(struct tg3 *tp)
5158 {
5159         kfree(tp->rx_std_buffers);
5160         tp->rx_std_buffers = NULL;
5161         if (tp->rx_std) {
5162                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5163                                     tp->rx_std, tp->rx_std_mapping);
5164                 tp->rx_std = NULL;
5165         }
5166         if (tp->rx_jumbo) {
5167                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5168                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
5169                 tp->rx_jumbo = NULL;
5170         }
5171         if (tp->rx_rcb) {
5172                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5173                                     tp->rx_rcb, tp->rx_rcb_mapping);
5174                 tp->rx_rcb = NULL;
5175         }
5176         if (tp->tx_ring) {
5177                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5178                         tp->tx_ring, tp->tx_desc_mapping);
5179                 tp->tx_ring = NULL;
5180         }
5181         if (tp->hw_status) {
5182                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5183                                     tp->hw_status, tp->status_mapping);
5184                 tp->hw_status = NULL;
5185         }
5186         if (tp->hw_stats) {
5187                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5188                                     tp->hw_stats, tp->stats_mapping);
5189                 tp->hw_stats = NULL;
5190         }
5191 }
5192
5193 /*
5194  * Must not be invoked with interrupt sources disabled and
5195  * the hardware shutdown down.  Can sleep.
5196  */
5197 static int tg3_alloc_consistent(struct tg3 *tp)
5198 {
5199         tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
5200                                       (TG3_RX_RING_SIZE +
5201                                        TG3_RX_JUMBO_RING_SIZE)) +
5202                                      (sizeof(struct tx_ring_info) *
5203                                       TG3_TX_RING_SIZE),
5204                                      GFP_KERNEL);
5205         if (!tp->rx_std_buffers)
5206                 return -ENOMEM;
5207
5208         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
5209         tp->tx_buffers = (struct tx_ring_info *)
5210                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
5211
5212         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5213                                           &tp->rx_std_mapping);
5214         if (!tp->rx_std)
5215                 goto err_out;
5216
5217         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5218                                             &tp->rx_jumbo_mapping);
5219
5220         if (!tp->rx_jumbo)
5221                 goto err_out;
5222
5223         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5224                                           &tp->rx_rcb_mapping);
5225         if (!tp->rx_rcb)
5226                 goto err_out;
5227
5228         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5229                                            &tp->tx_desc_mapping);
5230         if (!tp->tx_ring)
5231                 goto err_out;
5232
5233         tp->hw_status = pci_alloc_consistent(tp->pdev,
5234                                              TG3_HW_STATUS_SIZE,
5235                                              &tp->status_mapping);
5236         if (!tp->hw_status)
5237                 goto err_out;
5238
5239         tp->hw_stats = pci_alloc_consistent(tp->pdev,
5240                                             sizeof(struct tg3_hw_stats),
5241                                             &tp->stats_mapping);
5242         if (!tp->hw_stats)
5243                 goto err_out;
5244
5245         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5246         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5247
5248         return 0;
5249
5250 err_out:
5251         tg3_free_consistent(tp);
5252         return -ENOMEM;
5253 }
5254
5255 #define MAX_WAIT_CNT 1000
5256
5257 /* To stop a block, clear the enable bit and poll till it
5258  * clears.  tp->lock is held.
5259  */
5260 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
5261 {
5262         unsigned int i;
5263         u32 val;
5264
5265         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5266                 switch (ofs) {
5267                 case RCVLSC_MODE:
5268                 case DMAC_MODE:
5269                 case MBFREE_MODE:
5270                 case BUFMGR_MODE:
5271                 case MEMARB_MODE:
5272                         /* We can't enable/disable these bits of the
5273                          * 5705/5750, just say success.
5274                          */
5275                         return 0;
5276
5277                 default:
5278                         break;
5279                 };
5280         }
5281
5282         val = tr32(ofs);
5283         val &= ~enable_bit;
5284         tw32_f(ofs, val);
5285
5286         for (i = 0; i < MAX_WAIT_CNT; i++) {
5287                 udelay(100);
5288                 val = tr32(ofs);
5289                 if ((val & enable_bit) == 0)
5290                         break;
5291         }
5292
5293         if (i == MAX_WAIT_CNT && !silent) {
5294                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5295                        "ofs=%lx enable_bit=%x\n",
5296                        ofs, enable_bit);
5297                 return -ENODEV;
5298         }
5299
5300         return 0;
5301 }
5302
5303 /* tp->lock is held. */
5304 static int tg3_abort_hw(struct tg3 *tp, int silent)
5305 {
5306         int i, err;
5307
5308         tg3_disable_ints(tp);
5309
5310         tp->rx_mode &= ~RX_MODE_ENABLE;
5311         tw32_f(MAC_RX_MODE, tp->rx_mode);
5312         udelay(10);
5313
5314         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5315         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5316         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5317         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5318         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5319         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5320
5321         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5322         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5323         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5324         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5325         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5326         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5327         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
5328
5329         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5330         tw32_f(MAC_MODE, tp->mac_mode);
5331         udelay(40);
5332
5333         tp->tx_mode &= ~TX_MODE_ENABLE;
5334         tw32_f(MAC_TX_MODE, tp->tx_mode);
5335
5336         for (i = 0; i < MAX_WAIT_CNT; i++) {
5337                 udelay(100);
5338                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5339                         break;
5340         }
5341         if (i >= MAX_WAIT_CNT) {
5342                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5343                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5344                        tp->dev->name, tr32(MAC_TX_MODE));
5345                 err |= -ENODEV;
5346         }
5347
5348         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
5349         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5350         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
5351
5352         tw32(FTQ_RESET, 0xffffffff);
5353         tw32(FTQ_RESET, 0x00000000);
5354
5355         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5356         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
5357
5358         if (tp->hw_status)
5359                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5360         if (tp->hw_stats)
5361                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5362
5363         return err;
5364 }
5365
5366 /* tp->lock is held. */
5367 static int tg3_nvram_lock(struct tg3 *tp)
5368 {
5369         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
5370                 int i;
5371
5372                 if (tp->nvram_lock_cnt == 0) {
5373                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
5374                         for (i = 0; i < 8000; i++) {
5375                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
5376                                         break;
5377                                 udelay(20);
5378                         }
5379                         if (i == 8000) {
5380                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
5381                                 return -ENODEV;
5382                         }
5383                 }
5384                 tp->nvram_lock_cnt++;
5385         }
5386         return 0;
5387 }
5388
5389 /* tp->lock is held. */
5390 static void tg3_nvram_unlock(struct tg3 *tp)
5391 {
5392         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
5393                 if (tp->nvram_lock_cnt > 0)
5394                         tp->nvram_lock_cnt--;
5395                 if (tp->nvram_lock_cnt == 0)
5396                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
5397         }
5398 }
5399
5400 /* tp->lock is held. */
5401 static void tg3_enable_nvram_access(struct tg3 *tp)
5402 {
5403         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5404             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5405                 u32 nvaccess = tr32(NVRAM_ACCESS);
5406
5407                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
5408         }
5409 }
5410
5411 /* tp->lock is held. */
5412 static void tg3_disable_nvram_access(struct tg3 *tp)
5413 {
5414         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5415             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5416                 u32 nvaccess = tr32(NVRAM_ACCESS);
5417
5418                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
5419         }
5420 }
5421
5422 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5423 {
5424         int i;
5425         u32 apedata;
5426
5427         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5428         if (apedata != APE_SEG_SIG_MAGIC)
5429                 return;
5430
5431         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
5432         if (apedata != APE_FW_STATUS_READY)
5433                 return;
5434
5435         /* Wait for up to 1 millisecond for APE to service previous event. */
5436         for (i = 0; i < 10; i++) {
5437                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5438                         return;
5439
5440                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5441
5442                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5443                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5444                                         event | APE_EVENT_STATUS_EVENT_PENDING);
5445
5446                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5447
5448                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5449                         break;
5450
5451                 udelay(100);
5452         }
5453
5454         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5455                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5456 }
5457
5458 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5459 {
5460         u32 event;
5461         u32 apedata;
5462
5463         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5464                 return;
5465
5466         switch (kind) {
5467                 case RESET_KIND_INIT:
5468                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5469                                         APE_HOST_SEG_SIG_MAGIC);
5470                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5471                                         APE_HOST_SEG_LEN_MAGIC);
5472                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5473                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5474                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
5475                                         APE_HOST_DRIVER_ID_MAGIC);
5476                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
5477                                         APE_HOST_BEHAV_NO_PHYLOCK);
5478
5479                         event = APE_EVENT_STATUS_STATE_START;
5480                         break;
5481                 case RESET_KIND_SHUTDOWN:
5482                         event = APE_EVENT_STATUS_STATE_UNLOAD;
5483                         break;
5484                 case RESET_KIND_SUSPEND:
5485                         event = APE_EVENT_STATUS_STATE_SUSPEND;
5486                         break;
5487                 default:
5488                         return;
5489         }
5490
5491         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
5492
5493         tg3_ape_send_event(tp, event);
5494 }
5495
5496 /* tp->lock is held. */
5497 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
5498 {
5499         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
5500                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
5501
5502         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5503                 switch (kind) {
5504                 case RESET_KIND_INIT:
5505                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5506                                       DRV_STATE_START);
5507                         break;
5508
5509                 case RESET_KIND_SHUTDOWN:
5510                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5511                                       DRV_STATE_UNLOAD);
5512                         break;
5513
5514                 case RESET_KIND_SUSPEND:
5515                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5516                                       DRV_STATE_SUSPEND);
5517                         break;
5518
5519                 default:
5520                         break;
5521                 };
5522         }
5523
5524         if (kind == RESET_KIND_INIT ||
5525             kind == RESET_KIND_SUSPEND)
5526                 tg3_ape_driver_state_change(tp, kind);
5527 }
5528
5529 /* tp->lock is held. */
5530 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
5531 {
5532         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5533                 switch (kind) {
5534                 case RESET_KIND_INIT:
5535                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5536                                       DRV_STATE_START_DONE);
5537                         break;
5538
5539                 case RESET_KIND_SHUTDOWN:
5540                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5541                                       DRV_STATE_UNLOAD_DONE);
5542                         break;
5543
5544                 default:
5545                         break;
5546                 };
5547         }
5548
5549         if (kind == RESET_KIND_SHUTDOWN)
5550                 tg3_ape_driver_state_change(tp, kind);
5551 }
5552
5553 /* tp->lock is held. */
5554 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
5555 {
5556         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5557                 switch (kind) {
5558                 case RESET_KIND_INIT:
5559                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5560                                       DRV_STATE_START);
5561                         break;
5562
5563                 case RESET_KIND_SHUTDOWN:
5564                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5565                                       DRV_STATE_UNLOAD);
5566                         break;
5567
5568                 case RESET_KIND_SUSPEND:
5569                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5570                                       DRV_STATE_SUSPEND);
5571                         break;
5572
5573                 default:
5574                         break;
5575                 };
5576         }
5577 }
5578
5579 static int tg3_poll_fw(struct tg3 *tp)
5580 {
5581         int i;
5582         u32 val;
5583
5584         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5585                 /* Wait up to 20ms for init done. */
5586                 for (i = 0; i < 200; i++) {
5587                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
5588                                 return 0;
5589                         udelay(100);
5590                 }
5591                 return -ENODEV;
5592         }
5593
5594         /* Wait for firmware initialization to complete. */
5595         for (i = 0; i < 100000; i++) {
5596                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
5597                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
5598                         break;
5599                 udelay(10);
5600         }
5601
5602         /* Chip might not be fitted with firmware.  Some Sun onboard
5603          * parts are configured like that.  So don't signal the timeout
5604          * of the above loop as an error, but do report the lack of
5605          * running firmware once.
5606          */
5607         if (i >= 100000 &&
5608             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
5609                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
5610
5611                 printk(KERN_INFO PFX "%s: No firmware running.\n",
5612                        tp->dev->name);
5613         }
5614
5615         return 0;
5616 }
5617
5618 /* Save PCI command register before chip reset */
5619 static void tg3_save_pci_state(struct tg3 *tp)
5620 {
5621         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
5622 }
5623
5624 /* Restore PCI state after chip reset */
5625 static void tg3_restore_pci_state(struct tg3 *tp)
5626 {
5627         u32 val;
5628
5629         /* Re-enable indirect register accesses. */
5630         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
5631                                tp->misc_host_ctrl);
5632
5633         /* Set MAX PCI retry to zero. */
5634         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
5635         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5636             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
5637                 val |= PCISTATE_RETRY_SAME_DMA;
5638         /* Allow reads and writes to the APE register and memory space. */
5639         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
5640                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
5641                        PCISTATE_ALLOW_APE_SHMEM_WR;
5642         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
5643
5644         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
5645
5646         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
5647                 pcie_set_readrq(tp->pdev, 4096);
5648         else {
5649                 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
5650                                       tp->pci_cacheline_sz);
5651                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
5652                                       tp->pci_lat_timer);
5653         }
5654
5655         /* Make sure PCI-X relaxed ordering bit is clear. */
5656         if (tp->pcix_cap) {
5657                 u16 pcix_cmd;
5658
5659                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5660                                      &pcix_cmd);
5661                 pcix_cmd &= ~PCI_X_CMD_ERO;
5662                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5663                                       pcix_cmd);
5664         }
5665
5666         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5667
5668                 /* Chip reset on 5780 will reset MSI enable bit,
5669                  * so need to restore it.
5670                  */
5671                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
5672                         u16 ctrl;
5673
5674                         pci_read_config_word(tp->pdev,
5675                                              tp->msi_cap + PCI_MSI_FLAGS,
5676                                              &ctrl);
5677                         pci_write_config_word(tp->pdev,
5678                                               tp->msi_cap + PCI_MSI_FLAGS,
5679                                               ctrl | PCI_MSI_FLAGS_ENABLE);
5680                         val = tr32(MSGINT_MODE);
5681                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
5682                 }
5683         }
5684 }
5685
5686 static void tg3_stop_fw(struct tg3 *);
5687
5688 /* tp->lock is held. */
5689 static int tg3_chip_reset(struct tg3 *tp)
5690 {
5691         u32 val;
5692         void (*write_op)(struct tg3 *, u32, u32);
5693         int err;
5694
5695         tg3_nvram_lock(tp);
5696
5697         tg3_mdio_stop(tp);
5698
5699         /* No matching tg3_nvram_unlock() after this because
5700          * chip reset below will undo the nvram lock.
5701          */
5702         tp->nvram_lock_cnt = 0;
5703
5704         /* GRC_MISC_CFG core clock reset will clear the memory
5705          * enable bit in PCI register 4 and the MSI enable bit
5706          * on some chips, so we save relevant registers here.
5707          */
5708         tg3_save_pci_state(tp);
5709
5710         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
5711             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
5712             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
5713             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
5714             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
5715             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
5716                 tw32(GRC_FASTBOOT_PC, 0);
5717
5718         /*
5719          * We must avoid the readl() that normally takes place.
5720          * It locks machines, causes machine checks, and other
5721          * fun things.  So, temporarily disable the 5701
5722          * hardware workaround, while we do the reset.
5723          */
5724         write_op = tp->write32;
5725         if (write_op == tg3_write_flush_reg32)
5726                 tp->write32 = tg3_write32;
5727
5728         /* Prevent the irq handler from reading or writing PCI registers
5729          * during chip reset when the memory enable bit in the PCI command
5730          * register may be cleared.  The chip does not generate interrupt
5731          * at this time, but the irq handler may still be called due to irq
5732          * sharing or irqpoll.
5733          */
5734         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
5735         if (tp->hw_status) {
5736                 tp->hw_status->status = 0;
5737                 tp->hw_status->status_tag = 0;
5738         }
5739         tp->last_tag = 0;
5740         smp_mb();
5741         synchronize_irq(tp->pdev->irq);
5742
5743         /* do the reset */
5744         val = GRC_MISC_CFG_CORECLK_RESET;
5745
5746         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
5747                 if (tr32(0x7e2c) == 0x60) {
5748                         tw32(0x7e2c, 0x20);
5749                 }
5750                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
5751                         tw32(GRC_MISC_CFG, (1 << 29));
5752                         val |= (1 << 29);
5753                 }
5754         }
5755
5756         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5757                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
5758                 tw32(GRC_VCPU_EXT_CTRL,
5759                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
5760         }
5761
5762         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5763                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
5764