tg3: Automatically size stat/test string arrays
[linux-2.6.git] / drivers / net / tg3.c
1 /*
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  * Copyright (C) 2005-2011 Broadcom Corporation.
8  *
9  * Firmware is:
10  *      Derived from proprietary unpublished source code,
11  *      Copyright (C) 2000-2003 Broadcom Corporation.
12  *
13  *      Permission is hereby granted for the distribution of this firmware
14  *      data in hexadecimal or equivalent format, provided this copyright
15  *      notice is accompanying it.
16  */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/in.h>
28 #include <linux/init.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mdio.h>
36 #include <linux/mii.h>
37 #include <linux/phy.h>
38 #include <linux/brcmphy.h>
39 #include <linux/if_vlan.h>
40 #include <linux/ip.h>
41 #include <linux/tcp.h>
42 #include <linux/workqueue.h>
43 #include <linux/prefetch.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/firmware.h>
46
47 #include <net/checksum.h>
48 #include <net/ip.h>
49
50 #include <asm/system.h>
51 #include <linux/io.h>
52 #include <asm/byteorder.h>
53 #include <linux/uaccess.h>
54
55 #ifdef CONFIG_SPARC
56 #include <asm/idprom.h>
57 #include <asm/prom.h>
58 #endif
59
60 #define BAR_0   0
61 #define BAR_2   2
62
63 #include "tg3.h"
64
65 #define DRV_MODULE_NAME         "tg3"
66 #define TG3_MAJ_NUM                     3
67 #define TG3_MIN_NUM                     117
68 #define DRV_MODULE_VERSION      \
69         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
70 #define DRV_MODULE_RELDATE      "January 25, 2011"
71
72 #define TG3_DEF_MAC_MODE        0
73 #define TG3_DEF_RX_MODE         0
74 #define TG3_DEF_TX_MODE         0
75 #define TG3_DEF_MSG_ENABLE        \
76         (NETIF_MSG_DRV          | \
77          NETIF_MSG_PROBE        | \
78          NETIF_MSG_LINK         | \
79          NETIF_MSG_TIMER        | \
80          NETIF_MSG_IFDOWN       | \
81          NETIF_MSG_IFUP         | \
82          NETIF_MSG_RX_ERR       | \
83          NETIF_MSG_TX_ERR)
84
85 /* length of time before we decide the hardware is borked,
86  * and dev->tx_timeout() should be called to fix the problem
87  */
88 #define TG3_TX_TIMEOUT                  (5 * HZ)
89
90 /* hardware minimum and maximum for a single frame's data payload */
91 #define TG3_MIN_MTU                     60
92 #define TG3_MAX_MTU(tp) \
93         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
94
95 /* These numbers seem to be hard coded in the NIC firmware somehow.
96  * You can't change the ring sizes, but you can change where you place
97  * them in the NIC onboard memory.
98  */
99 #define TG3_RX_STD_RING_SIZE(tp) \
100         ((tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) ? \
101          TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
102 #define TG3_DEF_RX_RING_PENDING         200
103 #define TG3_RX_JMB_RING_SIZE(tp) \
104         ((tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) ? \
105          TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
106 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
107 #define TG3_RSS_INDIR_TBL_SIZE          128
108
109 /* Do not place this n-ring entries value into the tp struct itself,
110  * we really want to expose these constants to GCC so that modulo et
111  * al.  operations are done with shifts and masks instead of with
112  * hw multiply/modulo instructions.  Another solution would be to
113  * replace things like '% foo' with '& (foo - 1)'.
114  */
115
116 #define TG3_TX_RING_SIZE                512
117 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
118
119 #define TG3_RX_STD_RING_BYTES(tp) \
120         (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
121 #define TG3_RX_JMB_RING_BYTES(tp) \
122         (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
123 #define TG3_RX_RCB_RING_BYTES(tp) \
124         (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
125 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
126                                  TG3_TX_RING_SIZE)
127 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
128
129 #define TG3_DMA_BYTE_ENAB               64
130
131 #define TG3_RX_STD_DMA_SZ               1536
132 #define TG3_RX_JMB_DMA_SZ               9046
133
134 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
135
136 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
137 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
138
139 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
140         (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
141
142 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
143         (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
144
145 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
146  * that are at least dword aligned when used in PCIX mode.  The driver
147  * works around this bug by double copying the packet.  This workaround
148  * is built into the normal double copy length check for efficiency.
149  *
150  * However, the double copy is only necessary on those architectures
151  * where unaligned memory accesses are inefficient.  For those architectures
152  * where unaligned memory accesses incur little penalty, we can reintegrate
153  * the 5701 in the normal rx path.  Doing so saves a device structure
154  * dereference by hardcoding the double copy threshold in place.
155  */
156 #define TG3_RX_COPY_THRESHOLD           256
157 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
158         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
159 #else
160         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
161 #endif
162
163 /* minimum number of free TX descriptors required to wake up TX process */
164 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
165
166 #define TG3_RAW_IP_ALIGN 2
167
168 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
169
170 #define FIRMWARE_TG3            "tigon/tg3.bin"
171 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
172 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
173
174 static char version[] __devinitdata =
175         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
176
177 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
178 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
179 MODULE_LICENSE("GPL");
180 MODULE_VERSION(DRV_MODULE_VERSION);
181 MODULE_FIRMWARE(FIRMWARE_TG3);
182 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
183 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
184
185 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
186 module_param(tg3_debug, int, 0);
187 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
188
189 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
263         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
264         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
265         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
266         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
267         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
268         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
269         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
270         {}
271 };
272
273 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
274
275 static const struct {
276         const char string[ETH_GSTRING_LEN];
277 } ethtool_stats_keys[] = {
278         { "rx_octets" },
279         { "rx_fragments" },
280         { "rx_ucast_packets" },
281         { "rx_mcast_packets" },
282         { "rx_bcast_packets" },
283         { "rx_fcs_errors" },
284         { "rx_align_errors" },
285         { "rx_xon_pause_rcvd" },
286         { "rx_xoff_pause_rcvd" },
287         { "rx_mac_ctrl_rcvd" },
288         { "rx_xoff_entered" },
289         { "rx_frame_too_long_errors" },
290         { "rx_jabbers" },
291         { "rx_undersize_packets" },
292         { "rx_in_length_errors" },
293         { "rx_out_length_errors" },
294         { "rx_64_or_less_octet_packets" },
295         { "rx_65_to_127_octet_packets" },
296         { "rx_128_to_255_octet_packets" },
297         { "rx_256_to_511_octet_packets" },
298         { "rx_512_to_1023_octet_packets" },
299         { "rx_1024_to_1522_octet_packets" },
300         { "rx_1523_to_2047_octet_packets" },
301         { "rx_2048_to_4095_octet_packets" },
302         { "rx_4096_to_8191_octet_packets" },
303         { "rx_8192_to_9022_octet_packets" },
304
305         { "tx_octets" },
306         { "tx_collisions" },
307
308         { "tx_xon_sent" },
309         { "tx_xoff_sent" },
310         { "tx_flow_control" },
311         { "tx_mac_errors" },
312         { "tx_single_collisions" },
313         { "tx_mult_collisions" },
314         { "tx_deferred" },
315         { "tx_excessive_collisions" },
316         { "tx_late_collisions" },
317         { "tx_collide_2times" },
318         { "tx_collide_3times" },
319         { "tx_collide_4times" },
320         { "tx_collide_5times" },
321         { "tx_collide_6times" },
322         { "tx_collide_7times" },
323         { "tx_collide_8times" },
324         { "tx_collide_9times" },
325         { "tx_collide_10times" },
326         { "tx_collide_11times" },
327         { "tx_collide_12times" },
328         { "tx_collide_13times" },
329         { "tx_collide_14times" },
330         { "tx_collide_15times" },
331         { "tx_ucast_packets" },
332         { "tx_mcast_packets" },
333         { "tx_bcast_packets" },
334         { "tx_carrier_sense_errors" },
335         { "tx_discards" },
336         { "tx_errors" },
337
338         { "dma_writeq_full" },
339         { "dma_write_prioq_full" },
340         { "rxbds_empty" },
341         { "rx_discards" },
342         { "rx_errors" },
343         { "rx_threshold_hit" },
344
345         { "dma_readq_full" },
346         { "dma_read_prioq_full" },
347         { "tx_comp_queue_full" },
348
349         { "ring_set_send_prod_index" },
350         { "ring_status_update" },
351         { "nic_irqs" },
352         { "nic_avoided_irqs" },
353         { "nic_tx_threshold_hit" }
354 };
355
356 #define TG3_NUM_STATS   ARRAY_SIZE(ethtool_stats_keys)
357
358
359 static const struct {
360         const char string[ETH_GSTRING_LEN];
361 } ethtool_test_keys[] = {
362         { "nvram test     (online) " },
363         { "link test      (online) " },
364         { "register test  (offline)" },
365         { "memory test    (offline)" },
366         { "loopback test  (offline)" },
367         { "interrupt test (offline)" },
368 };
369
370 #define TG3_NUM_TEST    ARRAY_SIZE(ethtool_test_keys)
371
372
373 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
374 {
375         writel(val, tp->regs + off);
376 }
377
378 static u32 tg3_read32(struct tg3 *tp, u32 off)
379 {
380         return readl(tp->regs + off);
381 }
382
383 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
384 {
385         writel(val, tp->aperegs + off);
386 }
387
388 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
389 {
390         return readl(tp->aperegs + off);
391 }
392
393 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
394 {
395         unsigned long flags;
396
397         spin_lock_irqsave(&tp->indirect_lock, flags);
398         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
399         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
400         spin_unlock_irqrestore(&tp->indirect_lock, flags);
401 }
402
403 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
404 {
405         writel(val, tp->regs + off);
406         readl(tp->regs + off);
407 }
408
409 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
410 {
411         unsigned long flags;
412         u32 val;
413
414         spin_lock_irqsave(&tp->indirect_lock, flags);
415         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
416         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
417         spin_unlock_irqrestore(&tp->indirect_lock, flags);
418         return val;
419 }
420
421 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
422 {
423         unsigned long flags;
424
425         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
426                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
427                                        TG3_64BIT_REG_LOW, val);
428                 return;
429         }
430         if (off == TG3_RX_STD_PROD_IDX_REG) {
431                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
432                                        TG3_64BIT_REG_LOW, val);
433                 return;
434         }
435
436         spin_lock_irqsave(&tp->indirect_lock, flags);
437         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
438         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
439         spin_unlock_irqrestore(&tp->indirect_lock, flags);
440
441         /* In indirect mode when disabling interrupts, we also need
442          * to clear the interrupt bit in the GRC local ctrl register.
443          */
444         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
445             (val == 0x1)) {
446                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
447                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
448         }
449 }
450
451 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
452 {
453         unsigned long flags;
454         u32 val;
455
456         spin_lock_irqsave(&tp->indirect_lock, flags);
457         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
458         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
459         spin_unlock_irqrestore(&tp->indirect_lock, flags);
460         return val;
461 }
462
463 /* usec_wait specifies the wait time in usec when writing to certain registers
464  * where it is unsafe to read back the register without some delay.
465  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
466  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
467  */
468 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
469 {
470         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
471             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
472                 /* Non-posted methods */
473                 tp->write32(tp, off, val);
474         else {
475                 /* Posted method */
476                 tg3_write32(tp, off, val);
477                 if (usec_wait)
478                         udelay(usec_wait);
479                 tp->read32(tp, off);
480         }
481         /* Wait again after the read for the posted method to guarantee that
482          * the wait time is met.
483          */
484         if (usec_wait)
485                 udelay(usec_wait);
486 }
487
488 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
489 {
490         tp->write32_mbox(tp, off, val);
491         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
492             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
493                 tp->read32_mbox(tp, off);
494 }
495
496 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
497 {
498         void __iomem *mbox = tp->regs + off;
499         writel(val, mbox);
500         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
501                 writel(val, mbox);
502         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
503                 readl(mbox);
504 }
505
506 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
507 {
508         return readl(tp->regs + off + GRCMBOX_BASE);
509 }
510
511 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
512 {
513         writel(val, tp->regs + off + GRCMBOX_BASE);
514 }
515
516 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
517 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
518 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
519 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
520 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
521
522 #define tw32(reg, val)                  tp->write32(tp, reg, val)
523 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
524 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
525 #define tr32(reg)                       tp->read32(tp, reg)
526
527 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
528 {
529         unsigned long flags;
530
531         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
532             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
533                 return;
534
535         spin_lock_irqsave(&tp->indirect_lock, flags);
536         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
537                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
538                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
539
540                 /* Always leave this as zero. */
541                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
542         } else {
543                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
544                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
545
546                 /* Always leave this as zero. */
547                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
548         }
549         spin_unlock_irqrestore(&tp->indirect_lock, flags);
550 }
551
552 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
553 {
554         unsigned long flags;
555
556         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
557             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
558                 *val = 0;
559                 return;
560         }
561
562         spin_lock_irqsave(&tp->indirect_lock, flags);
563         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
564                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
565                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
566
567                 /* Always leave this as zero. */
568                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
569         } else {
570                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
571                 *val = tr32(TG3PCI_MEM_WIN_DATA);
572
573                 /* Always leave this as zero. */
574                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
575         }
576         spin_unlock_irqrestore(&tp->indirect_lock, flags);
577 }
578
579 static void tg3_ape_lock_init(struct tg3 *tp)
580 {
581         int i;
582         u32 regbase;
583
584         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
585                 regbase = TG3_APE_LOCK_GRANT;
586         else
587                 regbase = TG3_APE_PER_LOCK_GRANT;
588
589         /* Make sure the driver hasn't any stale locks. */
590         for (i = 0; i < 8; i++)
591                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
592 }
593
594 static int tg3_ape_lock(struct tg3 *tp, int locknum)
595 {
596         int i, off;
597         int ret = 0;
598         u32 status, req, gnt;
599
600         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
601                 return 0;
602
603         switch (locknum) {
604         case TG3_APE_LOCK_GRC:
605         case TG3_APE_LOCK_MEM:
606                 break;
607         default:
608                 return -EINVAL;
609         }
610
611         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
612                 req = TG3_APE_LOCK_REQ;
613                 gnt = TG3_APE_LOCK_GRANT;
614         } else {
615                 req = TG3_APE_PER_LOCK_REQ;
616                 gnt = TG3_APE_PER_LOCK_GRANT;
617         }
618
619         off = 4 * locknum;
620
621         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
622
623         /* Wait for up to 1 millisecond to acquire lock. */
624         for (i = 0; i < 100; i++) {
625                 status = tg3_ape_read32(tp, gnt + off);
626                 if (status == APE_LOCK_GRANT_DRIVER)
627                         break;
628                 udelay(10);
629         }
630
631         if (status != APE_LOCK_GRANT_DRIVER) {
632                 /* Revoke the lock request. */
633                 tg3_ape_write32(tp, gnt + off,
634                                 APE_LOCK_GRANT_DRIVER);
635
636                 ret = -EBUSY;
637         }
638
639         return ret;
640 }
641
642 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
643 {
644         u32 gnt;
645
646         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
647                 return;
648
649         switch (locknum) {
650         case TG3_APE_LOCK_GRC:
651         case TG3_APE_LOCK_MEM:
652                 break;
653         default:
654                 return;
655         }
656
657         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
658                 gnt = TG3_APE_LOCK_GRANT;
659         else
660                 gnt = TG3_APE_PER_LOCK_GRANT;
661
662         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
663 }
664
665 static void tg3_disable_ints(struct tg3 *tp)
666 {
667         int i;
668
669         tw32(TG3PCI_MISC_HOST_CTRL,
670              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
671         for (i = 0; i < tp->irq_max; i++)
672                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
673 }
674
675 static void tg3_enable_ints(struct tg3 *tp)
676 {
677         int i;
678
679         tp->irq_sync = 0;
680         wmb();
681
682         tw32(TG3PCI_MISC_HOST_CTRL,
683              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
684
685         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
686         for (i = 0; i < tp->irq_cnt; i++) {
687                 struct tg3_napi *tnapi = &tp->napi[i];
688
689                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
690                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
691                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
692
693                 tp->coal_now |= tnapi->coal_now;
694         }
695
696         /* Force an initial interrupt */
697         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
698             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
699                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
700         else
701                 tw32(HOSTCC_MODE, tp->coal_now);
702
703         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
704 }
705
706 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
707 {
708         struct tg3 *tp = tnapi->tp;
709         struct tg3_hw_status *sblk = tnapi->hw_status;
710         unsigned int work_exists = 0;
711
712         /* check for phy events */
713         if (!(tp->tg3_flags &
714               (TG3_FLAG_USE_LINKCHG_REG |
715                TG3_FLAG_POLL_SERDES))) {
716                 if (sblk->status & SD_STATUS_LINK_CHG)
717                         work_exists = 1;
718         }
719         /* check for RX/TX work to do */
720         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
721             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
722                 work_exists = 1;
723
724         return work_exists;
725 }
726
727 /* tg3_int_reenable
728  *  similar to tg3_enable_ints, but it accurately determines whether there
729  *  is new work pending and can return without flushing the PIO write
730  *  which reenables interrupts
731  */
732 static void tg3_int_reenable(struct tg3_napi *tnapi)
733 {
734         struct tg3 *tp = tnapi->tp;
735
736         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
737         mmiowb();
738
739         /* When doing tagged status, this work check is unnecessary.
740          * The last_tag we write above tells the chip which piece of
741          * work we've completed.
742          */
743         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
744             tg3_has_work(tnapi))
745                 tw32(HOSTCC_MODE, tp->coalesce_mode |
746                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
747 }
748
749 static void tg3_switch_clocks(struct tg3 *tp)
750 {
751         u32 clock_ctrl;
752         u32 orig_clock_ctrl;
753
754         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
755             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
756                 return;
757
758         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
759
760         orig_clock_ctrl = clock_ctrl;
761         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
762                        CLOCK_CTRL_CLKRUN_OENABLE |
763                        0x1f);
764         tp->pci_clock_ctrl = clock_ctrl;
765
766         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
767                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
768                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
769                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
770                 }
771         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
772                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
773                             clock_ctrl |
774                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
775                             40);
776                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
777                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
778                             40);
779         }
780         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
781 }
782
783 #define PHY_BUSY_LOOPS  5000
784
785 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
786 {
787         u32 frame_val;
788         unsigned int loops;
789         int ret;
790
791         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
792                 tw32_f(MAC_MI_MODE,
793                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
794                 udelay(80);
795         }
796
797         *val = 0x0;
798
799         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
800                       MI_COM_PHY_ADDR_MASK);
801         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
802                       MI_COM_REG_ADDR_MASK);
803         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
804
805         tw32_f(MAC_MI_COM, frame_val);
806
807         loops = PHY_BUSY_LOOPS;
808         while (loops != 0) {
809                 udelay(10);
810                 frame_val = tr32(MAC_MI_COM);
811
812                 if ((frame_val & MI_COM_BUSY) == 0) {
813                         udelay(5);
814                         frame_val = tr32(MAC_MI_COM);
815                         break;
816                 }
817                 loops -= 1;
818         }
819
820         ret = -EBUSY;
821         if (loops != 0) {
822                 *val = frame_val & MI_COM_DATA_MASK;
823                 ret = 0;
824         }
825
826         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
827                 tw32_f(MAC_MI_MODE, tp->mi_mode);
828                 udelay(80);
829         }
830
831         return ret;
832 }
833
834 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
835 {
836         u32 frame_val;
837         unsigned int loops;
838         int ret;
839
840         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
841             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
842                 return 0;
843
844         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
845                 tw32_f(MAC_MI_MODE,
846                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
847                 udelay(80);
848         }
849
850         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
851                       MI_COM_PHY_ADDR_MASK);
852         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
853                       MI_COM_REG_ADDR_MASK);
854         frame_val |= (val & MI_COM_DATA_MASK);
855         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
856
857         tw32_f(MAC_MI_COM, frame_val);
858
859         loops = PHY_BUSY_LOOPS;
860         while (loops != 0) {
861                 udelay(10);
862                 frame_val = tr32(MAC_MI_COM);
863                 if ((frame_val & MI_COM_BUSY) == 0) {
864                         udelay(5);
865                         frame_val = tr32(MAC_MI_COM);
866                         break;
867                 }
868                 loops -= 1;
869         }
870
871         ret = -EBUSY;
872         if (loops != 0)
873                 ret = 0;
874
875         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
876                 tw32_f(MAC_MI_MODE, tp->mi_mode);
877                 udelay(80);
878         }
879
880         return ret;
881 }
882
883 static int tg3_bmcr_reset(struct tg3 *tp)
884 {
885         u32 phy_control;
886         int limit, err;
887
888         /* OK, reset it, and poll the BMCR_RESET bit until it
889          * clears or we time out.
890          */
891         phy_control = BMCR_RESET;
892         err = tg3_writephy(tp, MII_BMCR, phy_control);
893         if (err != 0)
894                 return -EBUSY;
895
896         limit = 5000;
897         while (limit--) {
898                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
899                 if (err != 0)
900                         return -EBUSY;
901
902                 if ((phy_control & BMCR_RESET) == 0) {
903                         udelay(40);
904                         break;
905                 }
906                 udelay(10);
907         }
908         if (limit < 0)
909                 return -EBUSY;
910
911         return 0;
912 }
913
914 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
915 {
916         struct tg3 *tp = bp->priv;
917         u32 val;
918
919         spin_lock_bh(&tp->lock);
920
921         if (tg3_readphy(tp, reg, &val))
922                 val = -EIO;
923
924         spin_unlock_bh(&tp->lock);
925
926         return val;
927 }
928
929 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
930 {
931         struct tg3 *tp = bp->priv;
932         u32 ret = 0;
933
934         spin_lock_bh(&tp->lock);
935
936         if (tg3_writephy(tp, reg, val))
937                 ret = -EIO;
938
939         spin_unlock_bh(&tp->lock);
940
941         return ret;
942 }
943
944 static int tg3_mdio_reset(struct mii_bus *bp)
945 {
946         return 0;
947 }
948
949 static void tg3_mdio_config_5785(struct tg3 *tp)
950 {
951         u32 val;
952         struct phy_device *phydev;
953
954         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
955         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
956         case PHY_ID_BCM50610:
957         case PHY_ID_BCM50610M:
958                 val = MAC_PHYCFG2_50610_LED_MODES;
959                 break;
960         case PHY_ID_BCMAC131:
961                 val = MAC_PHYCFG2_AC131_LED_MODES;
962                 break;
963         case PHY_ID_RTL8211C:
964                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
965                 break;
966         case PHY_ID_RTL8201E:
967                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
968                 break;
969         default:
970                 return;
971         }
972
973         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
974                 tw32(MAC_PHYCFG2, val);
975
976                 val = tr32(MAC_PHYCFG1);
977                 val &= ~(MAC_PHYCFG1_RGMII_INT |
978                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
979                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
980                 tw32(MAC_PHYCFG1, val);
981
982                 return;
983         }
984
985         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
986                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
987                        MAC_PHYCFG2_FMODE_MASK_MASK |
988                        MAC_PHYCFG2_GMODE_MASK_MASK |
989                        MAC_PHYCFG2_ACT_MASK_MASK   |
990                        MAC_PHYCFG2_QUAL_MASK_MASK |
991                        MAC_PHYCFG2_INBAND_ENABLE;
992
993         tw32(MAC_PHYCFG2, val);
994
995         val = tr32(MAC_PHYCFG1);
996         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
997                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
998         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
999                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1000                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1001                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1002                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1003         }
1004         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1005                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1006         tw32(MAC_PHYCFG1, val);
1007
1008         val = tr32(MAC_EXT_RGMII_MODE);
1009         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1010                  MAC_RGMII_MODE_RX_QUALITY |
1011                  MAC_RGMII_MODE_RX_ACTIVITY |
1012                  MAC_RGMII_MODE_RX_ENG_DET |
1013                  MAC_RGMII_MODE_TX_ENABLE |
1014                  MAC_RGMII_MODE_TX_LOWPWR |
1015                  MAC_RGMII_MODE_TX_RESET);
1016         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1017                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1018                         val |= MAC_RGMII_MODE_RX_INT_B |
1019                                MAC_RGMII_MODE_RX_QUALITY |
1020                                MAC_RGMII_MODE_RX_ACTIVITY |
1021                                MAC_RGMII_MODE_RX_ENG_DET;
1022                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1023                         val |= MAC_RGMII_MODE_TX_ENABLE |
1024                                MAC_RGMII_MODE_TX_LOWPWR |
1025                                MAC_RGMII_MODE_TX_RESET;
1026         }
1027         tw32(MAC_EXT_RGMII_MODE, val);
1028 }
1029
1030 static void tg3_mdio_start(struct tg3 *tp)
1031 {
1032         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1033         tw32_f(MAC_MI_MODE, tp->mi_mode);
1034         udelay(80);
1035
1036         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1037             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1038                 tg3_mdio_config_5785(tp);
1039 }
1040
1041 static int tg3_mdio_init(struct tg3 *tp)
1042 {
1043         int i;
1044         u32 reg;
1045         struct phy_device *phydev;
1046
1047         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
1048                 u32 is_serdes;
1049
1050                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1051
1052                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1053                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1054                 else
1055                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1056                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1057                 if (is_serdes)
1058                         tp->phy_addr += 7;
1059         } else
1060                 tp->phy_addr = TG3_PHY_MII_ADDR;
1061
1062         tg3_mdio_start(tp);
1063
1064         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1065             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1066                 return 0;
1067
1068         tp->mdio_bus = mdiobus_alloc();
1069         if (tp->mdio_bus == NULL)
1070                 return -ENOMEM;
1071
1072         tp->mdio_bus->name     = "tg3 mdio bus";
1073         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1074                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1075         tp->mdio_bus->priv     = tp;
1076         tp->mdio_bus->parent   = &tp->pdev->dev;
1077         tp->mdio_bus->read     = &tg3_mdio_read;
1078         tp->mdio_bus->write    = &tg3_mdio_write;
1079         tp->mdio_bus->reset    = &tg3_mdio_reset;
1080         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1081         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1082
1083         for (i = 0; i < PHY_MAX_ADDR; i++)
1084                 tp->mdio_bus->irq[i] = PHY_POLL;
1085
1086         /* The bus registration will look for all the PHYs on the mdio bus.
1087          * Unfortunately, it does not ensure the PHY is powered up before
1088          * accessing the PHY ID registers.  A chip reset is the
1089          * quickest way to bring the device back to an operational state..
1090          */
1091         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1092                 tg3_bmcr_reset(tp);
1093
1094         i = mdiobus_register(tp->mdio_bus);
1095         if (i) {
1096                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1097                 mdiobus_free(tp->mdio_bus);
1098                 return i;
1099         }
1100
1101         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1102
1103         if (!phydev || !phydev->drv) {
1104                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1105                 mdiobus_unregister(tp->mdio_bus);
1106                 mdiobus_free(tp->mdio_bus);
1107                 return -ENODEV;
1108         }
1109
1110         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1111         case PHY_ID_BCM57780:
1112                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1113                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1114                 break;
1115         case PHY_ID_BCM50610:
1116         case PHY_ID_BCM50610M:
1117                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1118                                      PHY_BRCM_RX_REFCLK_UNUSED |
1119                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1120                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1121                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1122                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1123                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1124                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1125                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1126                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1127                 /* fallthru */
1128         case PHY_ID_RTL8211C:
1129                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1130                 break;
1131         case PHY_ID_RTL8201E:
1132         case PHY_ID_BCMAC131:
1133                 phydev->interface = PHY_INTERFACE_MODE_MII;
1134                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1135                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1136                 break;
1137         }
1138
1139         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1140
1141         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1142                 tg3_mdio_config_5785(tp);
1143
1144         return 0;
1145 }
1146
1147 static void tg3_mdio_fini(struct tg3 *tp)
1148 {
1149         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1150                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1151                 mdiobus_unregister(tp->mdio_bus);
1152                 mdiobus_free(tp->mdio_bus);
1153         }
1154 }
1155
1156 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1157 {
1158         int err;
1159
1160         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1161         if (err)
1162                 goto done;
1163
1164         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1165         if (err)
1166                 goto done;
1167
1168         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1169                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1170         if (err)
1171                 goto done;
1172
1173         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1174
1175 done:
1176         return err;
1177 }
1178
1179 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1180 {
1181         int err;
1182
1183         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1184         if (err)
1185                 goto done;
1186
1187         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1188         if (err)
1189                 goto done;
1190
1191         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1192                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1193         if (err)
1194                 goto done;
1195
1196         err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1197
1198 done:
1199         return err;
1200 }
1201
1202 /* tp->lock is held. */
1203 static inline void tg3_generate_fw_event(struct tg3 *tp)
1204 {
1205         u32 val;
1206
1207         val = tr32(GRC_RX_CPU_EVENT);
1208         val |= GRC_RX_CPU_DRIVER_EVENT;
1209         tw32_f(GRC_RX_CPU_EVENT, val);
1210
1211         tp->last_event_jiffies = jiffies;
1212 }
1213
1214 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1215
1216 /* tp->lock is held. */
1217 static void tg3_wait_for_event_ack(struct tg3 *tp)
1218 {
1219         int i;
1220         unsigned int delay_cnt;
1221         long time_remain;
1222
1223         /* If enough time has passed, no wait is necessary. */
1224         time_remain = (long)(tp->last_event_jiffies + 1 +
1225                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1226                       (long)jiffies;
1227         if (time_remain < 0)
1228                 return;
1229
1230         /* Check if we can shorten the wait time. */
1231         delay_cnt = jiffies_to_usecs(time_remain);
1232         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1233                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1234         delay_cnt = (delay_cnt >> 3) + 1;
1235
1236         for (i = 0; i < delay_cnt; i++) {
1237                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1238                         break;
1239                 udelay(8);
1240         }
1241 }
1242
1243 /* tp->lock is held. */
1244 static void tg3_ump_link_report(struct tg3 *tp)
1245 {
1246         u32 reg;
1247         u32 val;
1248
1249         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1250             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1251                 return;
1252
1253         tg3_wait_for_event_ack(tp);
1254
1255         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1256
1257         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1258
1259         val = 0;
1260         if (!tg3_readphy(tp, MII_BMCR, &reg))
1261                 val = reg << 16;
1262         if (!tg3_readphy(tp, MII_BMSR, &reg))
1263                 val |= (reg & 0xffff);
1264         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1265
1266         val = 0;
1267         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1268                 val = reg << 16;
1269         if (!tg3_readphy(tp, MII_LPA, &reg))
1270                 val |= (reg & 0xffff);
1271         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1272
1273         val = 0;
1274         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1275                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1276                         val = reg << 16;
1277                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1278                         val |= (reg & 0xffff);
1279         }
1280         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1281
1282         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1283                 val = reg << 16;
1284         else
1285                 val = 0;
1286         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1287
1288         tg3_generate_fw_event(tp);
1289 }
1290
1291 static void tg3_link_report(struct tg3 *tp)
1292 {
1293         if (!netif_carrier_ok(tp->dev)) {
1294                 netif_info(tp, link, tp->dev, "Link is down\n");
1295                 tg3_ump_link_report(tp);
1296         } else if (netif_msg_link(tp)) {
1297                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1298                             (tp->link_config.active_speed == SPEED_1000 ?
1299                              1000 :
1300                              (tp->link_config.active_speed == SPEED_100 ?
1301                               100 : 10)),
1302                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1303                              "full" : "half"));
1304
1305                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1306                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1307                             "on" : "off",
1308                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1309                             "on" : "off");
1310                 tg3_ump_link_report(tp);
1311         }
1312 }
1313
1314 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1315 {
1316         u16 miireg;
1317
1318         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1319                 miireg = ADVERTISE_PAUSE_CAP;
1320         else if (flow_ctrl & FLOW_CTRL_TX)
1321                 miireg = ADVERTISE_PAUSE_ASYM;
1322         else if (flow_ctrl & FLOW_CTRL_RX)
1323                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1324         else
1325                 miireg = 0;
1326
1327         return miireg;
1328 }
1329
1330 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1331 {
1332         u16 miireg;
1333
1334         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1335                 miireg = ADVERTISE_1000XPAUSE;
1336         else if (flow_ctrl & FLOW_CTRL_TX)
1337                 miireg = ADVERTISE_1000XPSE_ASYM;
1338         else if (flow_ctrl & FLOW_CTRL_RX)
1339                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1340         else
1341                 miireg = 0;
1342
1343         return miireg;
1344 }
1345
1346 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1347 {
1348         u8 cap = 0;
1349
1350         if (lcladv & ADVERTISE_1000XPAUSE) {
1351                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1352                         if (rmtadv & LPA_1000XPAUSE)
1353                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1354                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1355                                 cap = FLOW_CTRL_RX;
1356                 } else {
1357                         if (rmtadv & LPA_1000XPAUSE)
1358                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1359                 }
1360         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1361                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1362                         cap = FLOW_CTRL_TX;
1363         }
1364
1365         return cap;
1366 }
1367
1368 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1369 {
1370         u8 autoneg;
1371         u8 flowctrl = 0;
1372         u32 old_rx_mode = tp->rx_mode;
1373         u32 old_tx_mode = tp->tx_mode;
1374
1375         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1376                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1377         else
1378                 autoneg = tp->link_config.autoneg;
1379
1380         if (autoneg == AUTONEG_ENABLE &&
1381             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1382                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1383                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1384                 else
1385                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1386         } else
1387                 flowctrl = tp->link_config.flowctrl;
1388
1389         tp->link_config.active_flowctrl = flowctrl;
1390
1391         if (flowctrl & FLOW_CTRL_RX)
1392                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1393         else
1394                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1395
1396         if (old_rx_mode != tp->rx_mode)
1397                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1398
1399         if (flowctrl & FLOW_CTRL_TX)
1400                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1401         else
1402                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1403
1404         if (old_tx_mode != tp->tx_mode)
1405                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1406 }
1407
1408 static void tg3_adjust_link(struct net_device *dev)
1409 {
1410         u8 oldflowctrl, linkmesg = 0;
1411         u32 mac_mode, lcl_adv, rmt_adv;
1412         struct tg3 *tp = netdev_priv(dev);
1413         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1414
1415         spin_lock_bh(&tp->lock);
1416
1417         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1418                                     MAC_MODE_HALF_DUPLEX);
1419
1420         oldflowctrl = tp->link_config.active_flowctrl;
1421
1422         if (phydev->link) {
1423                 lcl_adv = 0;
1424                 rmt_adv = 0;
1425
1426                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1427                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1428                 else if (phydev->speed == SPEED_1000 ||
1429                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1430                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1431                 else
1432                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1433
1434                 if (phydev->duplex == DUPLEX_HALF)
1435                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1436                 else {
1437                         lcl_adv = tg3_advert_flowctrl_1000T(
1438                                   tp->link_config.flowctrl);
1439
1440                         if (phydev->pause)
1441                                 rmt_adv = LPA_PAUSE_CAP;
1442                         if (phydev->asym_pause)
1443                                 rmt_adv |= LPA_PAUSE_ASYM;
1444                 }
1445
1446                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1447         } else
1448                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1449
1450         if (mac_mode != tp->mac_mode) {
1451                 tp->mac_mode = mac_mode;
1452                 tw32_f(MAC_MODE, tp->mac_mode);
1453                 udelay(40);
1454         }
1455
1456         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1457                 if (phydev->speed == SPEED_10)
1458                         tw32(MAC_MI_STAT,
1459                              MAC_MI_STAT_10MBPS_MODE |
1460                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1461                 else
1462                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1463         }
1464
1465         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1466                 tw32(MAC_TX_LENGTHS,
1467                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1468                       (6 << TX_LENGTHS_IPG_SHIFT) |
1469                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1470         else
1471                 tw32(MAC_TX_LENGTHS,
1472                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1473                       (6 << TX_LENGTHS_IPG_SHIFT) |
1474                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1475
1476         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1477             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1478             phydev->speed != tp->link_config.active_speed ||
1479             phydev->duplex != tp->link_config.active_duplex ||
1480             oldflowctrl != tp->link_config.active_flowctrl)
1481                 linkmesg = 1;
1482
1483         tp->link_config.active_speed = phydev->speed;
1484         tp->link_config.active_duplex = phydev->duplex;
1485
1486         spin_unlock_bh(&tp->lock);
1487
1488         if (linkmesg)
1489                 tg3_link_report(tp);
1490 }
1491
1492 static int tg3_phy_init(struct tg3 *tp)
1493 {
1494         struct phy_device *phydev;
1495
1496         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1497                 return 0;
1498
1499         /* Bring the PHY back to a known state. */
1500         tg3_bmcr_reset(tp);
1501
1502         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1503
1504         /* Attach the MAC to the PHY. */
1505         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1506                              phydev->dev_flags, phydev->interface);
1507         if (IS_ERR(phydev)) {
1508                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1509                 return PTR_ERR(phydev);
1510         }
1511
1512         /* Mask with MAC supported features. */
1513         switch (phydev->interface) {
1514         case PHY_INTERFACE_MODE_GMII:
1515         case PHY_INTERFACE_MODE_RGMII:
1516                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1517                         phydev->supported &= (PHY_GBIT_FEATURES |
1518                                               SUPPORTED_Pause |
1519                                               SUPPORTED_Asym_Pause);
1520                         break;
1521                 }
1522                 /* fallthru */
1523         case PHY_INTERFACE_MODE_MII:
1524                 phydev->supported &= (PHY_BASIC_FEATURES |
1525                                       SUPPORTED_Pause |
1526                                       SUPPORTED_Asym_Pause);
1527                 break;
1528         default:
1529                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1530                 return -EINVAL;
1531         }
1532
1533         tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1534
1535         phydev->advertising = phydev->supported;
1536
1537         return 0;
1538 }
1539
1540 static void tg3_phy_start(struct tg3 *tp)
1541 {
1542         struct phy_device *phydev;
1543
1544         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1545                 return;
1546
1547         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1548
1549         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1550                 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1551                 phydev->speed = tp->link_config.orig_speed;
1552                 phydev->duplex = tp->link_config.orig_duplex;
1553                 phydev->autoneg = tp->link_config.orig_autoneg;
1554                 phydev->advertising = tp->link_config.orig_advertising;
1555         }
1556
1557         phy_start(phydev);
1558
1559         phy_start_aneg(phydev);
1560 }
1561
1562 static void tg3_phy_stop(struct tg3 *tp)
1563 {
1564         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1565                 return;
1566
1567         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1568 }
1569
1570 static void tg3_phy_fini(struct tg3 *tp)
1571 {
1572         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1573                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1574                 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1575         }
1576 }
1577
1578 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1579 {
1580         int err;
1581
1582         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1583         if (!err)
1584                 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1585
1586         return err;
1587 }
1588
1589 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1590 {
1591         int err;
1592
1593         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1594         if (!err)
1595                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1596
1597         return err;
1598 }
1599
1600 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1601 {
1602         u32 phytest;
1603
1604         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1605                 u32 phy;
1606
1607                 tg3_writephy(tp, MII_TG3_FET_TEST,
1608                              phytest | MII_TG3_FET_SHADOW_EN);
1609                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1610                         if (enable)
1611                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1612                         else
1613                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1614                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1615                 }
1616                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1617         }
1618 }
1619
1620 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1621 {
1622         u32 reg;
1623
1624         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1625             ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
1626              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1627                 return;
1628
1629         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1630                 tg3_phy_fet_toggle_apd(tp, enable);
1631                 return;
1632         }
1633
1634         reg = MII_TG3_MISC_SHDW_WREN |
1635               MII_TG3_MISC_SHDW_SCR5_SEL |
1636               MII_TG3_MISC_SHDW_SCR5_LPED |
1637               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1638               MII_TG3_MISC_SHDW_SCR5_SDTL |
1639               MII_TG3_MISC_SHDW_SCR5_C125OE;
1640         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1641                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1642
1643         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1644
1645
1646         reg = MII_TG3_MISC_SHDW_WREN |
1647               MII_TG3_MISC_SHDW_APD_SEL |
1648               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1649         if (enable)
1650                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1651
1652         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1653 }
1654
1655 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1656 {
1657         u32 phy;
1658
1659         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1660             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1661                 return;
1662
1663         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1664                 u32 ephy;
1665
1666                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1667                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1668
1669                         tg3_writephy(tp, MII_TG3_FET_TEST,
1670                                      ephy | MII_TG3_FET_SHADOW_EN);
1671                         if (!tg3_readphy(tp, reg, &phy)) {
1672                                 if (enable)
1673                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1674                                 else
1675                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1676                                 tg3_writephy(tp, reg, phy);
1677                         }
1678                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1679                 }
1680         } else {
1681                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1682                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1683                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1684                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1685                         if (enable)
1686                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1687                         else
1688                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1689                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1690                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1691                 }
1692         }
1693 }
1694
1695 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1696 {
1697         u32 val;
1698
1699         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1700                 return;
1701
1702         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1703             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1704                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1705                              (val | (1 << 15) | (1 << 4)));
1706 }
1707
1708 static void tg3_phy_apply_otp(struct tg3 *tp)
1709 {
1710         u32 otp, phy;
1711
1712         if (!tp->phy_otp)
1713                 return;
1714
1715         otp = tp->phy_otp;
1716
1717         /* Enable SM_DSP clock and tx 6dB coding. */
1718         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1719               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1720               MII_TG3_AUXCTL_ACTL_TX_6DB;
1721         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1722
1723         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1724         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1725         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1726
1727         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1728               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1729         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1730
1731         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1732         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1733         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1734
1735         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1736         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1737
1738         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1739         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1740
1741         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1742               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1743         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1744
1745         /* Turn off SM_DSP clock. */
1746         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1747               MII_TG3_AUXCTL_ACTL_TX_6DB;
1748         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1749 }
1750
1751 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
1752 {
1753         u32 val;
1754
1755         if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
1756                 return;
1757
1758         tp->setlpicnt = 0;
1759
1760         if (tp->link_config.autoneg == AUTONEG_ENABLE &&
1761             current_link_up == 1 &&
1762             tp->link_config.active_duplex == DUPLEX_FULL &&
1763             (tp->link_config.active_speed == SPEED_100 ||
1764              tp->link_config.active_speed == SPEED_1000)) {
1765                 u32 eeectl;
1766
1767                 if (tp->link_config.active_speed == SPEED_1000)
1768                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
1769                 else
1770                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
1771
1772                 tw32(TG3_CPMU_EEE_CTRL, eeectl);
1773
1774                 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
1775                                   TG3_CL45_D7_EEERES_STAT, &val);
1776
1777                 switch (val) {
1778                 case TG3_CL45_D7_EEERES_STAT_LP_1000T:
1779                         switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
1780                         case ASIC_REV_5717:
1781                         case ASIC_REV_5719:
1782                         case ASIC_REV_57765:
1783                                 /* Enable SM_DSP clock and tx 6dB coding. */
1784                                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1785                                       MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1786                                       MII_TG3_AUXCTL_ACTL_TX_6DB;
1787                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1788
1789                                 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
1790
1791                                 /* Turn off SM_DSP clock. */
1792                                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1793                                       MII_TG3_AUXCTL_ACTL_TX_6DB;
1794                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1795                         }
1796                         /* Fallthrough */
1797                 case TG3_CL45_D7_EEERES_STAT_LP_100TX:
1798                         tp->setlpicnt = 2;
1799                 }
1800         }
1801
1802         if (!tp->setlpicnt) {
1803                 val = tr32(TG3_CPMU_EEE_MODE);
1804                 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
1805         }
1806 }
1807
1808 static int tg3_wait_macro_done(struct tg3 *tp)
1809 {
1810         int limit = 100;
1811
1812         while (limit--) {
1813                 u32 tmp32;
1814
1815                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1816                         if ((tmp32 & 0x1000) == 0)
1817                                 break;
1818                 }
1819         }
1820         if (limit < 0)
1821                 return -EBUSY;
1822
1823         return 0;
1824 }
1825
1826 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1827 {
1828         static const u32 test_pat[4][6] = {
1829         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1830         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1831         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1832         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1833         };
1834         int chan;
1835
1836         for (chan = 0; chan < 4; chan++) {
1837                 int i;
1838
1839                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1840                              (chan * 0x2000) | 0x0200);
1841                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1842
1843                 for (i = 0; i < 6; i++)
1844                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1845                                      test_pat[chan][i]);
1846
1847                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1848                 if (tg3_wait_macro_done(tp)) {
1849                         *resetp = 1;
1850                         return -EBUSY;
1851                 }
1852
1853                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1854                              (chan * 0x2000) | 0x0200);
1855                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1856                 if (tg3_wait_macro_done(tp)) {
1857                         *resetp = 1;
1858                         return -EBUSY;
1859                 }
1860
1861                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1862                 if (tg3_wait_macro_done(tp)) {
1863                         *resetp = 1;
1864                         return -EBUSY;
1865                 }
1866
1867                 for (i = 0; i < 6; i += 2) {
1868                         u32 low, high;
1869
1870                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1871                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1872                             tg3_wait_macro_done(tp)) {
1873                                 *resetp = 1;
1874                                 return -EBUSY;
1875                         }
1876                         low &= 0x7fff;
1877                         high &= 0x000f;
1878                         if (low != test_pat[chan][i] ||
1879                             high != test_pat[chan][i+1]) {
1880                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1881                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1882                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1883
1884                                 return -EBUSY;
1885                         }
1886                 }
1887         }
1888
1889         return 0;
1890 }
1891
1892 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1893 {
1894         int chan;
1895
1896         for (chan = 0; chan < 4; chan++) {
1897                 int i;
1898
1899                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1900                              (chan * 0x2000) | 0x0200);
1901                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1902                 for (i = 0; i < 6; i++)
1903                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1904                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1905                 if (tg3_wait_macro_done(tp))
1906                         return -EBUSY;
1907         }
1908
1909         return 0;
1910 }
1911
1912 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1913 {
1914         u32 reg32, phy9_orig;
1915         int retries, do_phy_reset, err;
1916
1917         retries = 10;
1918         do_phy_reset = 1;
1919         do {
1920                 if (do_phy_reset) {
1921                         err = tg3_bmcr_reset(tp);
1922                         if (err)
1923                                 return err;
1924                         do_phy_reset = 0;
1925                 }
1926
1927                 /* Disable transmitter and interrupt.  */
1928                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1929                         continue;
1930
1931                 reg32 |= 0x3000;
1932                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1933
1934                 /* Set full-duplex, 1000 mbps.  */
1935                 tg3_writephy(tp, MII_BMCR,
1936                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1937
1938                 /* Set to master mode.  */
1939                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1940                         continue;
1941
1942                 tg3_writephy(tp, MII_TG3_CTRL,
1943                              (MII_TG3_CTRL_AS_MASTER |
1944                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1945
1946                 /* Enable SM_DSP_CLOCK and 6dB.  */
1947                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1948
1949                 /* Block the PHY control access.  */
1950                 tg3_phydsp_write(tp, 0x8005, 0x0800);
1951
1952                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1953                 if (!err)
1954                         break;
1955         } while (--retries);
1956
1957         err = tg3_phy_reset_chanpat(tp);
1958         if (err)
1959                 return err;
1960
1961         tg3_phydsp_write(tp, 0x8005, 0x0000);
1962
1963         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1964         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1965
1966         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1967             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1968                 /* Set Extended packet length bit for jumbo frames */
1969                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1970         } else {
1971                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1972         }
1973
1974         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1975
1976         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1977                 reg32 &= ~0x3000;
1978                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1979         } else if (!err)
1980                 err = -EBUSY;
1981
1982         return err;
1983 }
1984
1985 /* This will reset the tigon3 PHY if there is no valid
1986  * link unless the FORCE argument is non-zero.
1987  */
1988 static int tg3_phy_reset(struct tg3 *tp)
1989 {
1990         u32 val, cpmuctrl;
1991         int err;
1992
1993         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1994                 val = tr32(GRC_MISC_CFG);
1995                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1996                 udelay(40);
1997         }
1998         err  = tg3_readphy(tp, MII_BMSR, &val);
1999         err |= tg3_readphy(tp, MII_BMSR, &val);
2000         if (err != 0)
2001                 return -EBUSY;
2002
2003         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
2004                 netif_carrier_off(tp->dev);
2005                 tg3_link_report(tp);
2006         }
2007
2008         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2009             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2010             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2011                 err = tg3_phy_reset_5703_4_5(tp);
2012                 if (err)
2013                         return err;
2014                 goto out;
2015         }
2016
2017         cpmuctrl = 0;
2018         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2019             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2020                 cpmuctrl = tr32(TG3_CPMU_CTRL);
2021                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2022                         tw32(TG3_CPMU_CTRL,
2023                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2024         }
2025
2026         err = tg3_bmcr_reset(tp);
2027         if (err)
2028                 return err;
2029
2030         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2031                 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2032                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2033
2034                 tw32(TG3_CPMU_CTRL, cpmuctrl);
2035         }
2036
2037         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2038             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2039                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2040                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2041                     CPMU_LSPD_1000MB_MACCLK_12_5) {
2042                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2043                         udelay(40);
2044                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2045                 }
2046         }
2047
2048         if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
2049             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2050                 return 0;
2051
2052         tg3_phy_apply_otp(tp);
2053
2054         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2055                 tg3_phy_toggle_apd(tp, true);
2056         else
2057                 tg3_phy_toggle_apd(tp, false);
2058
2059 out:
2060         if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
2061                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2062                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2063                 tg3_phydsp_write(tp, 0x000a, 0x0323);
2064                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2065         }
2066         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2067                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2068                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2069         }
2070         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2071                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2072                 tg3_phydsp_write(tp, 0x000a, 0x310b);
2073                 tg3_phydsp_write(tp, 0x201f, 0x9506);
2074                 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2075                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2076         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2077                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2078                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2079                 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2080                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2081                         tg3_writephy(tp, MII_TG3_TEST1,
2082                                      MII_TG3_TEST1_TRIM_EN | 0x4);
2083                 } else
2084                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2085                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2086         }
2087         /* Set Extended packet length bit (bit 14) on all chips that */
2088         /* support jumbo frames */
2089         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2090                 /* Cannot do read-modify-write on 5401 */
2091                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2092         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2093                 /* Set bit 14 with read-modify-write to preserve other bits */
2094                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2095                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
2096                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000);
2097         }
2098
2099         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2100          * jumbo frames transmission.
2101          */
2102         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2103                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2104                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2105                                      val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2106         }
2107
2108         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2109                 /* adjust output voltage */
2110                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2111         }
2112
2113         tg3_phy_toggle_automdix(tp, 1);
2114         tg3_phy_set_wirespeed(tp);
2115         return 0;
2116 }
2117
2118 static void tg3_frob_aux_power(struct tg3 *tp)
2119 {
2120         bool need_vaux = false;
2121
2122         /* The GPIOs do something completely different on 57765. */
2123         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2124             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2125             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2126                 return;
2127
2128         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2129              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2130              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2131              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) &&
2132             tp->pdev_peer != tp->pdev) {
2133                 struct net_device *dev_peer;
2134
2135                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2136
2137                 /* remove_one() may have been run on the peer. */
2138                 if (dev_peer) {
2139                         struct tg3 *tp_peer = netdev_priv(dev_peer);
2140
2141                         if (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE)
2142                                 return;
2143
2144                         if ((tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) ||
2145                             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF))
2146                                 need_vaux = true;
2147                 }
2148         }
2149
2150         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) ||
2151             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2152                 need_vaux = true;
2153
2154         if (need_vaux) {
2155                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2156                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2157                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2158                                     (GRC_LCLCTRL_GPIO_OE0 |
2159                                      GRC_LCLCTRL_GPIO_OE1 |
2160                                      GRC_LCLCTRL_GPIO_OE2 |
2161                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2162                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2163                                     100);
2164                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2165                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2166                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2167                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2168                                              GRC_LCLCTRL_GPIO_OE1 |
2169                                              GRC_LCLCTRL_GPIO_OE2 |
2170                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2171                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2172                                              tp->grc_local_ctrl;
2173                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2174
2175                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2176                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2177
2178                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2179                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2180                 } else {
2181                         u32 no_gpio2;
2182                         u32 grc_local_ctrl = 0;
2183
2184                         /* Workaround to prevent overdrawing Amps. */
2185                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2186                             ASIC_REV_5714) {
2187                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2188                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2189                                             grc_local_ctrl, 100);
2190                         }
2191
2192                         /* On 5753 and variants, GPIO2 cannot be used. */
2193                         no_gpio2 = tp->nic_sram_data_cfg &
2194                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2195
2196                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2197                                          GRC_LCLCTRL_GPIO_OE1 |
2198                                          GRC_LCLCTRL_GPIO_OE2 |
2199                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2200                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2201                         if (no_gpio2) {
2202                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2203                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2204                         }
2205                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2206                                                     grc_local_ctrl, 100);
2207
2208                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2209
2210                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2211                                                     grc_local_ctrl, 100);
2212
2213                         if (!no_gpio2) {
2214                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2215                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2216                                             grc_local_ctrl, 100);
2217                         }
2218                 }
2219         } else {
2220                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2221                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2222                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2223                                     (GRC_LCLCTRL_GPIO_OE1 |
2224                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2225
2226                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2227                                     GRC_LCLCTRL_GPIO_OE1, 100);
2228
2229                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2230                                     (GRC_LCLCTRL_GPIO_OE1 |
2231                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2232                 }
2233         }
2234 }
2235
2236 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2237 {
2238         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2239                 return 1;
2240         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2241                 if (speed != SPEED_10)
2242                         return 1;
2243         } else if (speed == SPEED_10)
2244                 return 1;
2245
2246         return 0;
2247 }
2248
2249 static int tg3_setup_phy(struct tg3 *, int);
2250
2251 #define RESET_KIND_SHUTDOWN     0
2252 #define RESET_KIND_INIT         1
2253 #define RESET_KIND_SUSPEND      2
2254
2255 static void tg3_write_sig_post_reset(struct tg3 *, int);
2256 static int tg3_halt_cpu(struct tg3 *, u32);
2257
2258 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2259 {
2260         u32 val;
2261
2262         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2263                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2264                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2265                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2266
2267                         sg_dig_ctrl |=
2268                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2269                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2270                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2271                 }
2272                 return;
2273         }
2274
2275         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2276                 tg3_bmcr_reset(tp);
2277                 val = tr32(GRC_MISC_CFG);
2278                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2279                 udelay(40);
2280                 return;
2281         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2282                 u32 phytest;
2283                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2284                         u32 phy;
2285
2286                         tg3_writephy(tp, MII_ADVERTISE, 0);
2287                         tg3_writephy(tp, MII_BMCR,
2288                                      BMCR_ANENABLE | BMCR_ANRESTART);
2289
2290                         tg3_writephy(tp, MII_TG3_FET_TEST,
2291                                      phytest | MII_TG3_FET_SHADOW_EN);
2292                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2293                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2294                                 tg3_writephy(tp,
2295                                              MII_TG3_FET_SHDW_AUXMODE4,
2296                                              phy);
2297                         }
2298                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2299                 }
2300                 return;
2301         } else if (do_low_power) {
2302                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2303                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2304
2305                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2306                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2307                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2308                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2309                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2310         }
2311
2312         /* The PHY should not be powered down on some chips because
2313          * of bugs.
2314          */
2315         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2316             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2317             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2318              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2319                 return;
2320
2321         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2322             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2323                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2324                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2325                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2326                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2327         }
2328
2329         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2330 }
2331
2332 /* tp->lock is held. */
2333 static int tg3_nvram_lock(struct tg3 *tp)
2334 {
2335         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2336                 int i;
2337
2338                 if (tp->nvram_lock_cnt == 0) {
2339                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2340                         for (i = 0; i < 8000; i++) {
2341                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2342                                         break;
2343                                 udelay(20);
2344                         }
2345                         if (i == 8000) {
2346                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2347                                 return -ENODEV;
2348                         }
2349                 }
2350                 tp->nvram_lock_cnt++;
2351         }
2352         return 0;
2353 }
2354
2355 /* tp->lock is held. */
2356 static void tg3_nvram_unlock(struct tg3 *tp)
2357 {
2358         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2359                 if (tp->nvram_lock_cnt > 0)
2360                         tp->nvram_lock_cnt--;
2361                 if (tp->nvram_lock_cnt == 0)
2362                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2363         }
2364 }
2365
2366 /* tp->lock is held. */
2367 static void tg3_enable_nvram_access(struct tg3 *tp)
2368 {
2369         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2370             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2371                 u32 nvaccess = tr32(NVRAM_ACCESS);
2372
2373                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2374         }
2375 }
2376
2377 /* tp->lock is held. */
2378 static void tg3_disable_nvram_access(struct tg3 *tp)
2379 {
2380         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2381             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2382                 u32 nvaccess = tr32(NVRAM_ACCESS);
2383
2384                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2385         }
2386 }
2387
2388 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2389                                         u32 offset, u32 *val)
2390 {
2391         u32 tmp;
2392         int i;
2393
2394         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2395                 return -EINVAL;
2396
2397         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2398                                         EEPROM_ADDR_DEVID_MASK |
2399                                         EEPROM_ADDR_READ);
2400         tw32(GRC_EEPROM_ADDR,
2401              tmp |
2402              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2403              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2404               EEPROM_ADDR_ADDR_MASK) |
2405              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2406
2407         for (i = 0; i < 1000; i++) {
2408                 tmp = tr32(GRC_EEPROM_ADDR);
2409
2410                 if (tmp & EEPROM_ADDR_COMPLETE)
2411                         break;
2412                 msleep(1);
2413         }
2414         if (!(tmp & EEPROM_ADDR_COMPLETE))
2415                 return -EBUSY;
2416
2417         tmp = tr32(GRC_EEPROM_DATA);
2418
2419         /*
2420          * The data will always be opposite the native endian
2421          * format.  Perform a blind byteswap to compensate.
2422          */
2423         *val = swab32(tmp);
2424
2425         return 0;
2426 }
2427
2428 #define NVRAM_CMD_TIMEOUT 10000
2429
2430 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2431 {
2432         int i;
2433
2434         tw32(NVRAM_CMD, nvram_cmd);
2435         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2436                 udelay(10);
2437                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2438                         udelay(10);
2439                         break;
2440                 }
2441         }
2442
2443         if (i == NVRAM_CMD_TIMEOUT)
2444                 return -EBUSY;
2445
2446         return 0;
2447 }
2448
2449 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2450 {
2451         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2452             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2453             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2454            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2455             (tp->nvram_jedecnum == JEDEC_ATMEL))
2456
2457                 addr = ((addr / tp->nvram_pagesize) <<
2458                         ATMEL_AT45DB0X1B_PAGE_POS) +
2459                        (addr % tp->nvram_pagesize);
2460
2461         return addr;
2462 }
2463
2464 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2465 {
2466         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2467             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2468             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2469            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2470             (tp->nvram_jedecnum == JEDEC_ATMEL))
2471
2472                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2473                         tp->nvram_pagesize) +
2474                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2475
2476         return addr;
2477 }
2478
2479 /* NOTE: Data read in from NVRAM is byteswapped according to
2480  * the byteswapping settings for all other register accesses.
2481  * tg3 devices are BE devices, so on a BE machine, the data
2482  * returned will be exactly as it is seen in NVRAM.  On a LE
2483  * machine, the 32-bit value will be byteswapped.
2484  */
2485 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2486 {
2487         int ret;
2488
2489         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2490                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2491
2492         offset = tg3_nvram_phys_addr(tp, offset);
2493
2494         if (offset > NVRAM_ADDR_MSK)
2495                 return -EINVAL;
2496
2497         ret = tg3_nvram_lock(tp);
2498         if (ret)
2499                 return ret;
2500
2501         tg3_enable_nvram_access(tp);
2502
2503         tw32(NVRAM_ADDR, offset);
2504         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2505                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2506
2507         if (ret == 0)
2508                 *val = tr32(NVRAM_RDDATA);
2509
2510         tg3_disable_nvram_access(tp);
2511
2512         tg3_nvram_unlock(tp);
2513
2514         return ret;
2515 }
2516
2517 /* Ensures NVRAM data is in bytestream format. */
2518 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2519 {
2520         u32 v;
2521         int res = tg3_nvram_read(tp, offset, &v);
2522         if (!res)
2523                 *val = cpu_to_be32(v);
2524         return res;
2525 }
2526
2527 /* tp->lock is held. */
2528 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2529 {
2530         u32 addr_high, addr_low;
2531         int i;
2532
2533         addr_high = ((tp->dev->dev_addr[0] << 8) |
2534                      tp->dev->dev_addr[1]);
2535         addr_low = ((tp->dev->dev_addr[2] << 24) |
2536                     (tp->dev->dev_addr[3] << 16) |
2537                     (tp->dev->dev_addr[4] <<  8) |
2538                     (tp->dev->dev_addr[5] <<  0));
2539         for (i = 0; i < 4; i++) {
2540                 if (i == 1 && skip_mac_1)
2541                         continue;
2542                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2543                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2544         }
2545
2546         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2547             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2548                 for (i = 0; i < 12; i++) {
2549                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2550                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2551                 }
2552         }
2553
2554         addr_high = (tp->dev->dev_addr[0] +
2555                      tp->dev->dev_addr[1] +
2556                      tp->dev->dev_addr[2] +
2557                      tp->dev->dev_addr[3] +
2558                      tp->dev->dev_addr[4] +
2559                      tp->dev->dev_addr[5]) &
2560                 TX_BACKOFF_SEED_MASK;
2561         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2562 }
2563
2564 static void tg3_enable_register_access(struct tg3 *tp)
2565 {
2566         /*
2567          * Make sure register accesses (indirect or otherwise) will function
2568          * correctly.
2569          */
2570         pci_write_config_dword(tp->pdev,
2571                                TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
2572 }
2573
2574 static int tg3_power_up(struct tg3 *tp)
2575 {
2576         tg3_enable_register_access(tp);
2577
2578         pci_set_power_state(tp->pdev, PCI_D0);
2579
2580         /* Switch out of Vaux if it is a NIC */
2581         if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2582                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2583
2584         return 0;
2585 }
2586
2587 static int tg3_power_down_prepare(struct tg3 *tp)
2588 {
2589         u32 misc_host_ctrl;
2590         bool device_should_wake, do_low_power;
2591
2592         tg3_enable_register_access(tp);
2593
2594         /* Restore the CLKREQ setting. */
2595         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2596                 u16 lnkctl;
2597
2598                 pci_read_config_word(tp->pdev,
2599                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2600                                      &lnkctl);
2601                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2602                 pci_write_config_word(tp->pdev,
2603                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2604                                       lnkctl);
2605         }
2606
2607         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2608         tw32(TG3PCI_MISC_HOST_CTRL,
2609              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2610
2611         device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
2612                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2613
2614         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2615                 do_low_power = false;
2616                 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2617                     !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2618                         struct phy_device *phydev;
2619                         u32 phyid, advertising;
2620
2621                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2622
2623                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2624
2625                         tp->link_config.orig_speed = phydev->speed;
2626                         tp->link_config.orig_duplex = phydev->duplex;
2627                         tp->link_config.orig_autoneg = phydev->autoneg;
2628                         tp->link_config.orig_advertising = phydev->advertising;
2629
2630                         advertising = ADVERTISED_TP |
2631                                       ADVERTISED_Pause |
2632                                       ADVERTISED_Autoneg |
2633                                       ADVERTISED_10baseT_Half;
2634
2635                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2636                             device_should_wake) {
2637                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2638                                         advertising |=
2639                                                 ADVERTISED_100baseT_Half |
2640                                                 ADVERTISED_100baseT_Full |
2641                                                 ADVERTISED_10baseT_Full;
2642                                 else
2643                                         advertising |= ADVERTISED_10baseT_Full;
2644                         }
2645
2646                         phydev->advertising = advertising;
2647
2648                         phy_start_aneg(phydev);
2649
2650                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2651                         if (phyid != PHY_ID_BCMAC131) {
2652                                 phyid &= PHY_BCM_OUI_MASK;
2653                                 if (phyid == PHY_BCM_OUI_1 ||
2654                                     phyid == PHY_BCM_OUI_2 ||
2655                                     phyid == PHY_BCM_OUI_3)
2656                                         do_low_power = true;
2657                         }
2658                 }
2659         } else {
2660                 do_low_power = true;
2661
2662                 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2663                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2664                         tp->link_config.orig_speed = tp->link_config.speed;
2665                         tp->link_config.orig_duplex = tp->link_config.duplex;
2666                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2667                 }
2668
2669                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2670                         tp->link_config.speed = SPEED_10;
2671                         tp->link_config.duplex = DUPLEX_HALF;
2672                         tp->link_config.autoneg = AUTONEG_ENABLE;
2673                         tg3_setup_phy(tp, 0);
2674                 }
2675         }
2676
2677         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2678                 u32 val;
2679
2680                 val = tr32(GRC_VCPU_EXT_CTRL);
2681                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2682         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2683                 int i;
2684                 u32 val;
2685
2686                 for (i = 0; i < 200; i++) {
2687                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2688                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2689                                 break;
2690                         msleep(1);
2691                 }
2692         }
2693         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2694                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2695                                                      WOL_DRV_STATE_SHUTDOWN |
2696                                                      WOL_DRV_WOL |
2697                                                      WOL_SET_MAGIC_PKT);
2698
2699         if (device_should_wake) {
2700                 u32 mac_mode;
2701
2702                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2703                         if (do_low_power) {
2704                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2705                                 udelay(40);
2706                         }
2707
2708                         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2709                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2710                         else
2711                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2712
2713                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2714                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2715                             ASIC_REV_5700) {
2716                                 u32 speed = (tp->tg3_flags &
2717                                              TG3_FLAG_WOL_SPEED_100MB) ?
2718                                              SPEED_100 : SPEED_10;
2719                                 if (tg3_5700_link_polarity(tp, speed))
2720                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2721                                 else
2722                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2723                         }
2724                 } else {
2725                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2726                 }
2727
2728                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2729                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2730
2731                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2732                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2733                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2734                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2735                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2736                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2737
2738                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
2739                         mac_mode |= MAC_MODE_APE_TX_EN |
2740                                     MAC_MODE_APE_RX_EN |
2741                                     MAC_MODE_TDE_ENABLE;
2742
2743                 tw32_f(MAC_MODE, mac_mode);
2744                 udelay(100);
2745
2746                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2747                 udelay(10);
2748         }
2749
2750         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2751             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2752              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2753                 u32 base_val;
2754
2755                 base_val = tp->pci_clock_ctrl;
2756                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2757                              CLOCK_CTRL_TXCLK_DISABLE);
2758
2759                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2760                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2761         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2762                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2763                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2764                 /* do nothing */
2765         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2766                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2767                 u32 newbits1, newbits2;
2768
2769                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2770                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2771                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2772                                     CLOCK_CTRL_TXCLK_DISABLE |
2773                                     CLOCK_CTRL_ALTCLK);
2774                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2775                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2776                         newbits1 = CLOCK_CTRL_625_CORE;
2777                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2778                 } else {
2779                         newbits1 = CLOCK_CTRL_ALTCLK;
2780                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2781                 }
2782
2783                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2784                             40);
2785
2786                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2787                             40);
2788
2789                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2790                         u32 newbits3;
2791
2792                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2793                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2794                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2795                                             CLOCK_CTRL_TXCLK_DISABLE |
2796                                             CLOCK_CTRL_44MHZ_CORE);
2797                         } else {
2798                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2799                         }
2800
2801                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2802                                     tp->pci_clock_ctrl | newbits3, 40);
2803                 }
2804         }
2805
2806         if (!(device_should_wake) &&
2807             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2808                 tg3_power_down_phy(tp, do_low_power);
2809
2810         tg3_frob_aux_power(tp);
2811
2812         /* Workaround for unstable PLL clock */
2813         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2814             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2815                 u32 val = tr32(0x7d00);
2816
2817                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2818                 tw32(0x7d00, val);
2819                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2820                         int err;
2821
2822                         err = tg3_nvram_lock(tp);
2823                         tg3_halt_cpu(tp, RX_CPU_BASE);
2824                         if (!err)
2825                                 tg3_nvram_unlock(tp);
2826                 }
2827         }
2828
2829         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2830
2831         return 0;
2832 }
2833
2834 static void tg3_power_down(struct tg3 *tp)
2835 {
2836         tg3_power_down_prepare(tp);
2837
2838         pci_wake_from_d3(tp->pdev, tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2839         pci_set_power_state(tp->pdev, PCI_D3hot);
2840 }
2841
2842 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2843 {
2844         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2845         case MII_TG3_AUX_STAT_10HALF:
2846                 *speed = SPEED_10;
2847                 *duplex = DUPLEX_HALF;
2848                 break;
2849
2850         case MII_TG3_AUX_STAT_10FULL:
2851                 *speed = SPEED_10;
2852                 *duplex = DUPLEX_FULL;
2853                 break;
2854
2855         case MII_TG3_AUX_STAT_100HALF:
2856                 *speed = SPEED_100;
2857                 *duplex = DUPLEX_HALF;
2858                 break;
2859
2860         case MII_TG3_AUX_STAT_100FULL:
2861                 *speed = SPEED_100;
2862                 *duplex = DUPLEX_FULL;
2863                 break;
2864
2865         case MII_TG3_AUX_STAT_1000HALF:
2866                 *speed = SPEED_1000;
2867                 *duplex = DUPLEX_HALF;
2868                 break;
2869
2870         case MII_TG3_AUX_STAT_1000FULL:
2871                 *speed = SPEED_1000;
2872                 *duplex = DUPLEX_FULL;
2873                 break;
2874
2875         default:
2876                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2877                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2878                                  SPEED_10;
2879                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2880                                   DUPLEX_HALF;
2881                         break;
2882                 }
2883                 *speed = SPEED_INVALID;
2884                 *duplex = DUPLEX_INVALID;
2885                 break;
2886         }
2887 }
2888
2889 static void tg3_phy_copper_begin(struct tg3 *tp)
2890 {
2891         u32 new_adv;
2892         int i;
2893
2894         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2895                 /* Entering low power mode.  Disable gigabit and
2896                  * 100baseT advertisements.
2897                  */
2898                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2899
2900                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2901                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2902                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2903                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2904
2905                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2906         } else if (tp->link_config.speed == SPEED_INVALID) {
2907                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2908                         tp->link_config.advertising &=
2909                                 ~(ADVERTISED_1000baseT_Half |
2910                                   ADVERTISED_1000baseT_Full);
2911
2912                 new_adv = ADVERTISE_CSMA;
2913                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2914                         new_adv |= ADVERTISE_10HALF;
2915                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2916                         new_adv |= ADVERTISE_10FULL;
2917                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2918                         new_adv |= ADVERTISE_100HALF;
2919                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2920                         new_adv |= ADVERTISE_100FULL;
2921
2922                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2923
2924                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2925
2926                 if (tp->link_config.advertising &
2927                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2928                         new_adv = 0;
2929                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2930                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2931                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2932                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2933                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
2934                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2935                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2936                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2937                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2938                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2939                 } else {
2940                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2941                 }
2942         } else {
2943                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2944                 new_adv |= ADVERTISE_CSMA;
2945
2946                 /* Asking for a specific link mode. */
2947                 if (tp->link_config.speed == SPEED_1000) {
2948                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2949
2950                         if (tp->link_config.duplex == DUPLEX_FULL)
2951                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2952                         else
2953                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2954                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2955                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2956                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2957                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2958                 } else {
2959                         if (tp->link_config.speed == SPEED_100) {
2960                                 if (tp->link_config.duplex == DUPLEX_FULL)
2961                                         new_adv |= ADVERTISE_100FULL;
2962                                 else
2963                                         new_adv |= ADVERTISE_100HALF;
2964                         } else {
2965                                 if (tp->link_config.duplex == DUPLEX_FULL)
2966                                         new_adv |= ADVERTISE_10FULL;
2967                                 else
2968                                         new_adv |= ADVERTISE_10HALF;
2969                         }
2970                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2971
2972                         new_adv = 0;
2973                 }
2974
2975                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2976         }
2977
2978         if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
2979                 u32 val;
2980
2981                 tw32(TG3_CPMU_EEE_MODE,
2982                      tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2983
2984                 /* Enable SM_DSP clock and tx 6dB coding. */
2985                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
2986                       MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
2987                       MII_TG3_AUXCTL_ACTL_TX_6DB;
2988                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2989
2990                 switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
2991                 case ASIC_REV_5717:
2992                 case ASIC_REV_57765:
2993                         if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
2994                                 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
2995                                                  MII_TG3_DSP_CH34TP2_HIBW01);
2996                         /* Fall through */
2997                 case ASIC_REV_5719:
2998                         val = MII_TG3_DSP_TAP26_ALNOKO |
2999                               MII_TG3_DSP_TAP26_RMRXSTO |
3000                               MII_TG3_DSP_TAP26_OPCSINPT;
3001                         tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
3002                 }
3003
3004                 val = 0;
3005                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3006                         /* Advertise 100-BaseTX EEE ability */
3007                         if (tp->link_config.advertising &
3008                             ADVERTISED_100baseT_Full)
3009                                 val |= MDIO_AN_EEE_ADV_100TX;
3010                         /* Advertise 1000-BaseT EEE ability */
3011                         if (tp->link_config.advertising &
3012                             ADVERTISED_1000baseT_Full)
3013                                 val |= MDIO_AN_EEE_ADV_1000T;
3014                 }
3015                 tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3016
3017                 /* Turn off SM_DSP clock. */
3018                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
3019                       MII_TG3_AUXCTL_ACTL_TX_6DB;
3020                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3021         }
3022
3023         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
3024             tp->link_config.speed != SPEED_INVALID) {
3025                 u32 bmcr, orig_bmcr;
3026
3027                 tp->link_config.active_speed = tp->link_config.speed;
3028                 tp->link_config.active_duplex = tp->link_config.duplex;
3029
3030                 bmcr = 0;
3031                 switch (tp->link_config.speed) {
3032                 default:
3033                 case SPEED_10:
3034                         break;
3035
3036                 case SPEED_100:
3037                         bmcr |= BMCR_SPEED100;
3038                         break;
3039
3040                 case SPEED_1000:
3041                         bmcr |= TG3_BMCR_SPEED1000;
3042                         break;
3043                 }
3044
3045                 if (tp->link_config.duplex == DUPLEX_FULL)
3046                         bmcr |= BMCR_FULLDPLX;
3047
3048                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
3049                     (bmcr != orig_bmcr)) {
3050                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
3051                         for (i = 0; i < 1500; i++) {
3052                                 u32 tmp;
3053
3054                                 udelay(10);
3055                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
3056                                     tg3_readphy(tp, MII_BMSR, &tmp))
3057                                         continue;
3058                                 if (!(tmp & BMSR_LSTATUS)) {
3059                                         udelay(40);
3060                                         break;
3061                                 }
3062                         }
3063                         tg3_writephy(tp, MII_BMCR, bmcr);
3064                         udelay(40);
3065                 }
3066         } else {
3067                 tg3_writephy(tp, MII_BMCR,
3068                              BMCR_ANENABLE | BMCR_ANRESTART);
3069         }
3070 }
3071
3072 static int tg3_init_5401phy_dsp(struct tg3 *tp)
3073 {
3074         int err;
3075
3076         /* Turn off tap power management. */
3077         /* Set Extended packet length bit */
3078         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
3079
3080         err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
3081         err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
3082         err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
3083         err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
3084         err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
3085
3086         udelay(40);
3087
3088         return err;
3089 }
3090
3091 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3092 {
3093         u32 adv_reg, all_mask = 0;
3094
3095         if (mask & ADVERTISED_10baseT_Half)
3096                 all_mask |= ADVERTISE_10HALF;
3097         if (mask & ADVERTISED_10baseT_Full)
3098                 all_mask |= ADVERTISE_10FULL;
3099         if (mask & ADVERTISED_100baseT_Half)
3100                 all_mask |= ADVERTISE_100HALF;
3101         if (mask & ADVERTISED_100baseT_Full)
3102                 all_mask |= ADVERTISE_100FULL;
3103
3104         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3105                 return 0;
3106
3107         if ((adv_reg & all_mask) != all_mask)
3108                 return 0;
3109         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3110                 u32 tg3_ctrl;
3111
3112                 all_mask = 0;
3113                 if (mask & ADVERTISED_1000baseT_Half)
3114                         all_mask |= ADVERTISE_1000HALF;
3115                 if (mask & ADVERTISED_1000baseT_Full)
3116                         all_mask |= ADVERTISE_1000FULL;
3117
3118                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3119                         return 0;
3120
3121                 if ((tg3_ctrl & all_mask) != all_mask)
3122                         return 0;
3123         }
3124         return 1;
3125 }
3126
3127 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3128 {
3129         u32 curadv, reqadv;
3130
3131         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3132                 return 1;
3133
3134         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3135         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3136
3137         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3138                 if (curadv != reqadv)
3139                         return 0;
3140
3141                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3142                         tg3_readphy(tp, MII_LPA, rmtadv);
3143         } else {
3144                 /* Reprogram the advertisement register, even if it
3145                  * does not affect the current link.  If the link
3146                  * gets renegotiated in the future, we can save an
3147                  * additional renegotiation cycle by advertising
3148                  * it correctly in the first place.
3149                  */
3150                 if (curadv != reqadv) {
3151                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3152                                      ADVERTISE_PAUSE_ASYM);
3153                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3154                 }
3155         }
3156
3157         return 1;
3158 }
3159
3160 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3161 {
3162         int current_link_up;
3163         u32 bmsr, val;
3164         u32 lcl_adv, rmt_adv;
3165         u16 current_speed;
3166         u8 current_duplex;
3167         int i, err;
3168
3169         tw32(MAC_EVENT, 0);
3170
3171         tw32_f(MAC_STATUS,
3172              (MAC_STATUS_SYNC_CHANGED |
3173               MAC_STATUS_CFG_CHANGED |
3174               MAC_STATUS_MI_COMPLETION |
3175               MAC_STATUS_LNKSTATE_CHANGED));
3176         udelay(40);
3177
3178         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3179                 tw32_f(MAC_MI_MODE,
3180                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3181                 udelay(80);
3182         }
3183
3184         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3185
3186         /* Some third-party PHYs need to be reset on link going
3187          * down.
3188          */
3189         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3190              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3191              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3192             netif_carrier_ok(tp->dev)) {
3193                 tg3_readphy(tp, MII_BMSR, &bmsr);
3194                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3195                     !(bmsr & BMSR_LSTATUS))
3196                         force_reset = 1;
3197         }
3198         if (force_reset)
3199                 tg3_phy_reset(tp);
3200
3201         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3202                 tg3_readphy(tp, MII_BMSR, &bmsr);
3203                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3204                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3205                         bmsr = 0;
3206
3207                 if (!(bmsr & BMSR_LSTATUS)) {
3208                         err = tg3_init_5401phy_dsp(tp);
3209                         if (err)
3210                                 return err;
3211
3212                         tg3_readphy(tp, MII_BMSR, &bmsr);
3213                         for (i = 0; i < 1000; i++) {
3214                                 udelay(10);
3215                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3216                                     (bmsr & BMSR_LSTATUS)) {
3217                                         udelay(40);
3218                                         break;
3219                                 }
3220                         }
3221
3222                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3223                             TG3_PHY_REV_BCM5401_B0 &&
3224                             !(bmsr & BMSR_LSTATUS) &&
3225                             tp->link_config.active_speed == SPEED_1000) {
3226                                 err = tg3_phy_reset(tp);
3227                                 if (!err)
3228                                         err = tg3_init_5401phy_dsp(tp);
3229                                 if (err)
3230                                         return err;
3231                         }
3232                 }
3233         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3234                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3235                 /* 5701 {A0,B0} CRC bug workaround */
3236                 tg3_writephy(tp, 0x15, 0x0a75);
3237                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3238                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3239                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3240         }
3241
3242         /* Clear pending interrupts... */
3243         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3244         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3245
3246         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3247                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3248         else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3249                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3250
3251         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3252             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3253                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3254                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3255                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3256                 else
3257                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3258         }
3259
3260         current_link_up = 0;
3261         current_speed = SPEED_INVALID;
3262         current_duplex = DUPLEX_INVALID;
3263
3264         if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3265                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3266                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3267                 if (!(val & (1 << 10))) {
3268                         val |= (1 << 10);
3269                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3270                         goto relink;
3271                 }
3272         }
3273
3274         bmsr = 0;
3275         for (i = 0; i < 100; i++) {
3276                 tg3_readphy(tp, MII_BMSR, &bmsr);
3277                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3278                     (bmsr & BMSR_LSTATUS))
3279                         break;
3280                 udelay(40);
3281         }
3282
3283         if (bmsr & BMSR_LSTATUS) {
3284                 u32 aux_stat, bmcr;
3285
3286                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3287                 for (i = 0; i < 2000; i++) {
3288                         udelay(10);
3289                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3290                             aux_stat)
3291                                 break;
3292                 }
3293
3294                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3295                                              &current_speed,
3296                                              &current_duplex);
3297
3298                 bmcr = 0;
3299                 for (i = 0; i < 200; i++) {
3300                         tg3_readphy(tp, MII_BMCR, &bmcr);
3301                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3302                                 continue;
3303                         if (bmcr && bmcr != 0x7fff)
3304                                 break;
3305                         udelay(10);
3306                 }
3307
3308                 lcl_adv = 0;
3309                 rmt_adv = 0;
3310
3311                 tp->link_config.active_speed = current_speed;
3312                 tp->link_config.active_duplex = current_duplex;
3313
3314                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3315                         if ((bmcr & BMCR_ANENABLE) &&
3316                             tg3_copper_is_advertising_all(tp,
3317                                                 tp->link_config.advertising)) {
3318                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3319                                                                   &rmt_adv))
3320                                         current_link_up = 1;
3321                         }
3322                 } else {
3323                         if (!(bmcr & BMCR_ANENABLE) &&
3324                             tp->link_config.speed == current_speed &&
3325                             tp->link_config.duplex == current_duplex &&
3326                             tp->link_config.flowctrl ==
3327                             tp->link_config.active_flowctrl) {
3328                                 current_link_up = 1;
3329                         }
3330                 }
3331
3332                 if (current_link_up == 1 &&
3333                     tp->link_config.active_duplex == DUPLEX_FULL)
3334                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3335         }
3336
3337 relink:
3338         if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3339                 tg3_phy_copper_begin(tp);
3340
3341                 tg3_readphy(tp, MII_BMSR, &bmsr);
3342                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3343                     (bmsr & BMSR_LSTATUS))
3344                         current_link_up = 1;
3345         }
3346
3347         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3348         if (current_link_up == 1) {
3349                 if (tp->link_config.active_speed == SPEED_100 ||
3350                     tp->link_config.active_speed == SPEED_10)
3351                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3352                 else
3353                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3354         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3355                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3356         else
3357                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3358
3359         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3360         if (tp->link_config.active_duplex == DUPLEX_HALF)
3361                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3362
3363         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3364                 if (current_link_up == 1 &&
3365                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3366                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3367                 else
3368                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3369         }
3370
3371         /* ??? Without this setting Netgear GA302T PHY does not
3372          * ??? send/receive packets...
3373          */
3374         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3375             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3376                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3377                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3378                 udelay(80);
3379         }
3380
3381         tw32_f(MAC_MODE, tp->mac_mode);
3382         udelay(40);
3383
3384         tg3_phy_eee_adjust(tp, current_link_up);
3385
3386         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3387                 /* Polled via timer. */
3388                 tw32_f(MAC_EVENT, 0);
3389         } else {
3390                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3391         }
3392         udelay(40);
3393
3394         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3395             current_link_up == 1 &&
3396             tp->link_config.active_speed == SPEED_1000 &&
3397             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3398              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3399                 udelay(120);
3400                 tw32_f(MAC_STATUS,
3401                      (MAC_STATUS_SYNC_CHANGED |
3402                       MAC_STATUS_CFG_CHANGED));
3403                 udelay(40);
3404                 tg3_write_mem(tp,
3405                               NIC_SRAM_FIRMWARE_MBOX,
3406                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3407         }
3408
3409         /* Prevent send BD corruption. */
3410         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3411                 u16 oldlnkctl, newlnkctl;
3412
3413                 pci_read_config_word(tp->pdev,
3414                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3415                                      &oldlnkctl);
3416                 if (tp->link_config.active_speed == SPEED_100 ||
3417                     tp->link_config.active_speed == SPEED_10)
3418                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3419                 else
3420                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3421                 if (newlnkctl != oldlnkctl)
3422                         pci_write_config_word(tp->pdev,
3423                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3424                                               newlnkctl);
3425         }
3426
3427         if (current_link_up != netif_carrier_ok(tp->dev)) {
3428                 if (current_link_up)
3429                         netif_carrier_on(tp->dev);
3430                 else
3431                         netif_carrier_off(tp->dev);
3432                 tg3_link_report(tp);
3433         }
3434
3435         return 0;
3436 }
3437
3438 struct tg3_fiber_aneginfo {
3439         int state;
3440 #define ANEG_STATE_UNKNOWN              0
3441 #define ANEG_STATE_AN_ENABLE            1
3442 #define ANEG_STATE_RESTART_INIT         2
3443 #define ANEG_STATE_RESTART              3
3444 #define ANEG_STATE_DISABLE_LINK_OK      4
3445 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3446 #define ANEG_STATE_ABILITY_DETECT       6
3447 #define ANEG_STATE_ACK_DETECT_INIT      7
3448 #define ANEG_STATE_ACK_DETECT           8
3449 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3450 #define ANEG_STATE_COMPLETE_ACK         10
3451 #define ANEG_STATE_IDLE_DETECT_INIT     11
3452 #define ANEG_STATE_IDLE_DETECT          12
3453 #define ANEG_STATE_LINK_OK              13
3454 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3455 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3456
3457         u32 flags;
3458 #define MR_AN_ENABLE            0x00000001
3459 #define MR_RESTART_AN           0x00000002
3460 #define MR_AN_COMPLETE          0x00000004
3461 #define MR_PAGE_RX              0x00000008
3462 #define MR_NP_LOADED            0x00000010
3463 #define MR_TOGGLE_TX            0x00000020
3464 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3465 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3466 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3467 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3468 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3469 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3470 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3471 #define MR_TOGGLE_RX            0x00002000
3472 #define MR_NP_RX                0x00004000
3473
3474 #define MR_LINK_OK              0x80000000
3475
3476         unsigned long link_time, cur_time;
3477
3478         u32 ability_match_cfg;
3479         int ability_match_count;
3480
3481         char ability_match, idle_match, ack_match;
3482
3483         u32 txconfig, rxconfig;
3484 #define ANEG_CFG_NP             0x00000080
3485 #define ANEG_CFG_ACK            0x00000040
3486 #define ANEG_CFG_RF2            0x00000020
3487 #define ANEG_CFG_RF1            0x00000010
3488 #define ANEG_CFG_PS2            0x00000001
3489 #define ANEG_CFG_PS1            0x00008000
3490 #define ANEG_CFG_HD             0x00004000
3491 #define ANEG_CFG_FD             0x00002000
3492 #define ANEG_CFG_INVAL          0x00001f06
3493
3494 };
3495 #define ANEG_OK         0
3496 #define ANEG_DONE       1
3497 #define ANEG_TIMER_ENAB 2
3498 #define ANEG_FAILED     -1
3499
3500 #define ANEG_STATE_SETTLE_TIME  10000
3501
3502 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3503                                    struct tg3_fiber_aneginfo *ap)
3504 {
3505         u16 flowctrl;
3506         unsigned long delta;
3507         u32 rx_cfg_reg;
3508         int ret;
3509
3510         if (ap->state == ANEG_STATE_UNKNOWN) {
3511                 ap->rxconfig = 0;
3512                 ap->link_time = 0;
3513                 ap->cur_time = 0;
3514                 ap->ability_match_cfg = 0;
3515                 ap->ability_match_count = 0;
3516                 ap->ability_match = 0;
3517                 ap->idle_match = 0;
3518                 ap->ack_match = 0;
3519         }
3520         ap->cur_time++;
3521
3522         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3523                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3524
3525                 if (rx_cfg_reg != ap->ability_match_cfg) {
3526                         ap->ability_match_cfg = rx_cfg_reg;
3527                         ap->ability_match = 0;
3528                         ap->ability_match_count = 0;
3529                 } else {
3530                         if (++ap->ability_match_count > 1) {
3531                                 ap->ability_match = 1;
3532                                 ap->ability_match_cfg = rx_cfg_reg;
3533                         }
3534                 }
3535                 if (rx_cfg_reg & ANEG_CFG_ACK)
3536                         ap->ack_match = 1;
3537                 else
3538                         ap->ack_match = 0;
3539
3540                 ap->idle_match = 0;
3541         } else {
3542                 ap->idle_match = 1;
3543                 ap->ability_match_cfg = 0;
3544                 ap->ability_match_count = 0;
3545                 ap->ability_match = 0;
3546                 ap->ack_match = 0;
3547
3548                 rx_cfg_reg = 0;
3549         }
3550
3551         ap->rxconfig = rx_cfg_reg;
3552         ret = ANEG_OK;
3553
3554         switch (ap->state) {
3555         case ANEG_STATE_UNKNOWN:
3556                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3557                         ap->state = ANEG_STATE_AN_ENABLE;
3558
3559                 /* fallthru */
3560         case ANEG_STATE_AN_ENABLE:
3561                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3562                 if (ap->flags & MR_AN_ENABLE) {
3563                         ap->link_time = 0;
3564                         ap->cur_time = 0;
3565                         ap->ability_match_cfg = 0;
3566                         ap->ability_match_count = 0;
3567                         ap->ability_match = 0;
3568                         ap->idle_match = 0;
3569                         ap->ack_match = 0;
3570
3571                         ap->state = ANEG_STATE_RESTART_INIT;
3572                 } else {
3573                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3574                 }
3575                 break;
3576
3577         case ANEG_STATE_RESTART_INIT:
3578                 ap->link_time = ap->cur_time;
3579                 ap->flags &= ~(MR_NP_LOADED);
3580                 ap->txconfig = 0;
3581                 tw32(MAC_TX_AUTO_NEG, 0);
3582                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3583                 tw32_f(MAC_MODE, tp->mac_mode);
3584                 udelay(40);
3585
3586                 ret = ANEG_TIMER_ENAB;
3587                 ap->state = ANEG_STATE_RESTART;
3588
3589                 /* fallthru */
3590         case ANEG_STATE_RESTART:
3591                 delta = ap->cur_time - ap->link_time;
3592                 if (delta > ANEG_STATE_SETTLE_TIME)
3593                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3594                 else
3595                         ret = ANEG_TIMER_ENAB;
3596                 break;
3597
3598         case ANEG_STATE_DISABLE_LINK_OK:
3599                 ret = ANEG_DONE;
3600                 break;
3601
3602         case ANEG_STATE_ABILITY_DETECT_INIT:
3603                 ap->flags &= ~(MR_TOGGLE_TX);
3604                 ap->txconfig = ANEG_CFG_FD;
3605                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3606                 if (flowctrl & ADVERTISE_1000XPAUSE)
3607                         ap->txconfig |= ANEG_CFG_PS1;
3608                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3609                         ap->txconfig |= ANEG_CFG_PS2;
3610                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3611                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3612                 tw32_f(MAC_MODE, tp->mac_mode);
3613                 udelay(40);
3614
3615                 ap->state = ANEG_STATE_ABILITY_DETECT;
3616                 break;
3617
3618         case ANEG_STATE_ABILITY_DETECT:
3619                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3620                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3621                 break;
3622
3623         case ANEG_STATE_ACK_DETECT_INIT:
3624                 ap->txconfig |= ANEG_CFG_ACK;
3625                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3626                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3627                 tw32_f(MAC_MODE, tp->mac_mode);
3628                 udelay(40);
3629
3630                 ap->state = ANEG_STATE_ACK_DETECT;
3631
3632                 /* fallthru */
3633         case ANEG_STATE_ACK_DETECT:
3634                 if (ap->ack_match != 0) {
3635                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3636                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3637                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3638                         } else {
3639                                 ap->state = ANEG_STATE_AN_ENABLE;
3640                         }
3641                 } else if (ap->ability_match != 0 &&
3642                            ap->rxconfig == 0) {
3643                         ap->state = ANEG_STATE_AN_ENABLE;
3644                 }
3645                 break;
3646
3647         case ANEG_STATE_COMPLETE_ACK_INIT:
3648                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3649                         ret = ANEG_FAILED;
3650                         break;
3651                 }
3652                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3653                                MR_LP_ADV_HALF_DUPLEX |
3654                                MR_LP_ADV_SYM_PAUSE |
3655                                MR_LP_ADV_ASYM_PAUSE |
3656                                MR_LP_ADV_REMOTE_FAULT1 |
3657                                MR_LP_ADV_REMOTE_FAULT2 |
3658                                MR_LP_ADV_NEXT_PAGE |
3659                                MR_TOGGLE_RX |
3660                                MR_NP_RX);
3661                 if (ap->rxconfig & ANEG_CFG_FD)
3662                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3663                 if (ap->rxconfig & ANEG_CFG_HD)
3664                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3665                 if (ap->rxconfig & ANEG_CFG_PS1)
3666                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3667                 if (ap->rxconfig & ANEG_CFG_PS2)
3668                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3669                 if (ap->rxconfig & ANEG_CFG_RF1)
3670                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3671                 if (ap->rxconfig & ANEG_CFG_RF2)
3672                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3673                 if (ap->rxconfig & ANEG_CFG_NP)
3674                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3675
3676                 ap->link_time = ap->cur_time;
3677
3678                 ap->flags ^= (MR_TOGGLE_TX);
3679                 if (ap->rxconfig & 0x0008)
3680                         ap->flags |= MR_TOGGLE_RX;
3681                 if (ap->rxconfig & ANEG_CFG_NP)
3682                         ap->flags |= MR_NP_RX;
3683                 ap->flags |= MR_PAGE_RX;
3684
3685                 ap->state = ANEG_STATE_COMPLETE_ACK;
3686                 ret = ANEG_TIMER_ENAB;
3687                 break;
3688
3689         case ANEG_STATE_COMPLETE_ACK:
3690                 if (ap->ability_match != 0 &&
3691                     ap->rxconfig == 0) {
3692                         ap->state = ANEG_STATE_AN_ENABLE;
3693                         break;
3694                 }
3695                 delta = ap->cur_time - ap->link_time;
3696                 if (delta > ANEG_STATE_SETTLE_TIME) {
3697                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3698                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3699                         } else {
3700                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3701                                     !(ap->flags & MR_NP_RX)) {
3702                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3703                                 } else {
3704                                         ret = ANEG_FAILED;
3705                                 }
3706                         }
3707                 }
3708                 break;
3709
3710         case ANEG_STATE_IDLE_DETECT_INIT:
3711                 ap->link_time = ap->cur_time;
3712                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3713                 tw32_f(MAC_MODE, tp->mac_mode);
3714                 udelay(40);
3715
3716                 ap->state = ANEG_STATE_IDLE_DETECT;
3717                 ret = ANEG_TIMER_ENAB;
3718                 break;
3719
3720         case ANEG_STATE_IDLE_DETECT:
3721                 if (ap->ability_match != 0 &&
3722                     ap->rxconfig == 0) {
3723                         ap->state = ANEG_STATE_AN_ENABLE;
3724                         break;
3725                 }
3726                 delta = ap->cur_time - ap->link_time;
3727                 if (delta > ANEG_STATE_SETTLE_TIME) {
3728                         /* XXX another gem from the Broadcom driver :( */
3729                         ap->state = ANEG_STATE_LINK_OK;
3730                 }
3731                 break;
3732
3733         case ANEG_STATE_LINK_OK:
3734                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3735                 ret = ANEG_DONE;
3736                 break;
3737
3738         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3739                 /* ??? unimplemented */
3740                 break;
3741
3742         case ANEG_STATE_NEXT_PAGE_WAIT:
3743                 /* ??? unimplemented */
3744                 break;
3745
3746         default:
3747                 ret = ANEG_FAILED;
3748                 break;
3749         }
3750
3751         return ret;
3752 }
3753
3754 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3755 {
3756         int res = 0;
3757         struct tg3_fiber_aneginfo aninfo;
3758         int status = ANEG_FAILED;
3759         unsigned int tick;
3760         u32 tmp;
3761
3762         tw32_f(MAC_TX_AUTO_NEG, 0);
3763
3764         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3765         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3766         udelay(40);
3767
3768         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3769         udelay(40);
3770
3771         memset(&aninfo, 0, sizeof(aninfo));
3772         aninfo.flags |= MR_AN_ENABLE;
3773         aninfo.state = ANEG_STATE_UNKNOWN;
3774         aninfo.cur_time = 0;
3775         tick = 0;
3776         while (++tick < 195000) {
3777                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3778                 if (status == ANEG_DONE || status == ANEG_FAILED)
3779                         break;
3780
3781                 udelay(1);
3782         }
3783
3784         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3785         tw32_f(MAC_MODE, tp->mac_mode);
3786         udelay(40);
3787
3788         *txflags = aninfo.txconfig;
3789         *rxflags = aninfo.flags;
3790
3791         if (status == ANEG_DONE &&
3792             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3793                              MR_LP_ADV_FULL_DUPLEX)))
3794                 res = 1;
3795
3796         return res;
3797 }
3798
3799 static void tg3_init_bcm8002(struct tg3 *tp)
3800 {
3801         u32 mac_status = tr32(MAC_STATUS);
3802         int i;
3803
3804         /* Reset when initting first time or we have a link. */
3805         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3806             !(mac_status & MAC_STATUS_PCS_SYNCED))
3807                 return;
3808
3809         /* Set PLL lock range. */
3810         tg3_writephy(tp, 0x16, 0x8007);
3811
3812         /* SW reset */
3813         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3814
3815         /* Wait for reset to complete. */
3816         /* XXX schedule_timeout() ... */
3817         for (i = 0; i < 500; i++)
3818                 udelay(10);
3819
3820         /* Config mode; select PMA/Ch 1 regs. */
3821         tg3_writephy(tp, 0x10, 0x8411);
3822
3823         /* Enable auto-lock and comdet, select txclk for tx. */
3824         tg3_writephy(tp, 0x11, 0x0a10);
3825
3826         tg3_writephy(tp, 0x18, 0x00a0);
3827         tg3_writephy(tp, 0x16, 0x41ff);
3828
3829         /* Assert and deassert POR. */
3830         tg3_writephy(tp, 0x13, 0x0400);
3831         udelay(40);
3832         tg3_writephy(tp, 0x13, 0x0000);
3833
3834         tg3_writephy(tp, 0x11, 0x0a50);
3835         udelay(40);
3836         tg3_writephy(tp, 0x11, 0x0a10);
3837
3838         /* Wait for signal to stabilize */
3839         /* XXX schedule_timeout() ... */
3840         for (i = 0; i < 15000; i++)
3841                 udelay(10);
3842
3843         /* Deselect the channel register so we can read the PHYID
3844          * later.
3845          */
3846         tg3_writephy(tp, 0x10, 0x8011);
3847 }
3848
3849 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3850 {
3851         u16 flowctrl;
3852         u32 sg_dig_ctrl, sg_dig_status;
3853         u32 serdes_cfg, expected_sg_dig_ctrl;
3854         int workaround, port_a;
3855         int current_link_up;
3856
3857         serdes_cfg = 0;
3858         expected_sg_dig_ctrl = 0;
3859         workaround = 0;
3860         port_a = 1;
3861         current_link_up = 0;
3862
3863         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3864             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3865                 workaround = 1;
3866                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3867                         port_a = 0;
3868
3869                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3870                 /* preserve bits 20-23 for voltage regulator */
3871                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3872         }
3873
3874         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3875
3876         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3877                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3878                         if (workaround) {
3879                                 u32 val = serdes_cfg;
3880
3881                                 if (port_a)
3882                                         val |= 0xc010000;
3883                                 else
3884                                         val |= 0x4010000;
3885                                 tw32_f(MAC_SERDES_CFG, val);
3886                         }
3887
3888                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3889                 }
3890                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3891                         tg3_setup_flow_control(tp, 0, 0);
3892                         current_link_up = 1;
3893                 }
3894                 goto out;
3895         }
3896
3897         /* Want auto-negotiation.  */
3898         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3899
3900         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3901         if (flowctrl & ADVERTISE_1000XPAUSE)
3902                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3903         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3904                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3905
3906         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3907                 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3908                     tp->serdes_counter &&
3909                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3910                                     MAC_STATUS_RCVD_CFG)) ==
3911                      MAC_STATUS_PCS_SYNCED)) {
3912                         tp->serdes_counter--;
3913                         current_link_up = 1;
3914                         goto out;
3915                 }
3916 restart_autoneg:
3917                 if (workaround)
3918                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3919                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3920                 udelay(5);
3921                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3922
3923                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3924                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3925         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3926                                  MAC_STATUS_SIGNAL_DET)) {
3927                 sg_dig_status = tr32(SG_DIG_STATUS);
3928                 mac_status = tr32(MAC_STATUS);
3929
3930                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3931                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3932                         u32 local_adv = 0, remote_adv = 0;
3933
3934                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3935                                 local_adv |= ADVERTISE_1000XPAUSE;
3936                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3937                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3938
3939                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3940                                 remote_adv |= LPA_1000XPAUSE;
3941                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3942                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3943
3944                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3945                         current_link_up = 1;
3946                         tp->serdes_counter = 0;
3947                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3948                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3949                         if (tp->serdes_counter)
3950                                 tp->serdes_counter--;
3951                         else {
3952                                 if (workaround) {
3953                                         u32 val = serdes_cfg;
3954
3955                                         if (port_a)
3956                                                 val |= 0xc010000;
3957                                         else
3958                                                 val |= 0x4010000;
3959
3960                                         tw32_f(MAC_SERDES_CFG, val);
3961                                 }
3962
3963                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3964                                 udelay(40);
3965
3966                                 /* Link parallel detection - link is up */
3967                                 /* only if we have PCS_SYNC and not */
3968                                 /* receiving config code words */
3969                                 mac_status = tr32(MAC_STATUS);
3970                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3971                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3972                                         tg3_setup_flow_control(tp, 0, 0);
3973                                         current_link_up = 1;
3974                                         tp->phy_flags |=
3975                                                 TG3_PHYFLG_PARALLEL_DETECT;
3976                                         tp->serdes_counter =
3977                                                 SERDES_PARALLEL_DET_TIMEOUT;
3978                                 } else
3979                                         goto restart_autoneg;
3980                         }
3981                 }
3982         } else {
3983                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3984                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3985         }
3986
3987 out:
3988         return current_link_up;
3989 }
3990
3991 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3992 {
3993         int current_link_up = 0;
3994
3995         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3996                 goto out;
3997
3998         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3999                 u32 txflags, rxflags;
4000                 int i;
4001
4002                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
4003                         u32 local_adv = 0, remote_adv = 0;
4004
4005                         if (txflags & ANEG_CFG_PS1)
4006                                 local_adv |= ADVERTISE_1000XPAUSE;
4007                         if (txflags & ANEG_CFG_PS2)
4008                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
4009
4010                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
4011                                 remote_adv |= LPA_1000XPAUSE;
4012                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
4013                                 remote_adv |= LPA_1000XPAUSE_ASYM;
4014
4015                         tg3_setup_flow_control(tp, local_adv, remote_adv);
4016
4017                         current_link_up = 1;
4018                 }
4019                 for (i = 0; i < 30; i++) {
4020                         udelay(20);
4021                         tw32_f(MAC_STATUS,
4022                                (MAC_STATUS_SYNC_CHANGED |
4023                                 MAC_STATUS_CFG_CHANGED));
4024                         udelay(40);
4025                         if ((tr32(MAC_STATUS) &
4026                              (MAC_STATUS_SYNC_CHANGED |
4027                               MAC_STATUS_CFG_CHANGED)) == 0)
4028                                 break;
4029                 }
4030
4031                 mac_status = tr32(MAC_STATUS);
4032                 if (current_link_up == 0 &&
4033                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
4034                     !(mac_status & MAC_STATUS_RCVD_CFG))
4035                         current_link_up = 1;
4036         } else {
4037                 tg3_setup_flow_control(tp, 0, 0);
4038
4039                 /* Forcing 1000FD link up. */
4040                 current_link_up = 1;
4041
4042                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
4043                 udelay(40);
4044
4045                 tw32_f(MAC_MODE, tp->mac_mode);
4046                 udelay(40);
4047         }
4048
4049 out:
4050         return current_link_up;
4051 }
4052
4053 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4054 {
4055         u32 orig_pause_cfg;
4056         u16 orig_active_speed;
4057         u8 orig_active_duplex;
4058         u32 mac_status;
4059         int current_link_up;
4060         int i;
4061
4062         orig_pause_cfg = tp->link_config.active_flowctrl;
4063         orig_active_speed = tp->link_config.active_speed;
4064         orig_active_duplex = tp->link_config.active_duplex;
4065
4066         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
4067             netif_carrier_ok(tp->dev) &&
4068             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
4069                 mac_status = tr32(MAC_STATUS);
4070                 mac_status &= (MAC_STATUS_PCS_SYNCED |
4071                                MAC_STATUS_SIGNAL_DET |
4072                                MAC_STATUS_CFG_CHANGED |
4073                                MAC_STATUS_RCVD_CFG);
4074                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
4075                                    MAC_STATUS_SIGNAL_DET)) {
4076                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4077                                             MAC_STATUS_CFG_CHANGED));
4078                         return 0;
4079                 }
4080         }
4081
4082         tw32_f(MAC_TX_AUTO_NEG, 0);
4083
4084         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
4085         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
4086         tw32_f(MAC_MODE, tp->mac_mode);
4087         udelay(40);
4088
4089         if (tp->phy_id == TG3_PHY_ID_BCM8002)
4090                 tg3_init_bcm8002(tp);
4091
4092         /* Enable link change event even when serdes polling.  */
4093         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4094         udelay(40);
4095
4096         current_link_up = 0;
4097         mac_status = tr32(MAC_STATUS);
4098
4099         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
4100                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4101         else
4102                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4103
4104         tp->napi[0].hw_status->status =
4105                 (SD_STATUS_UPDATED |
4106                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4107
4108         for (i = 0; i < 100; i++) {
4109                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4110                                     MAC_STATUS_CFG_CHANGED));
4111                 udelay(5);
4112                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4113                                          MAC_STATUS_CFG_CHANGED |
4114                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4115                         break;
4116         }
4117
4118         mac_status = tr32(MAC_STATUS);
4119         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4120                 current_link_up = 0;
4121                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4122                     tp->serdes_counter == 0) {
4123                         tw32_f(MAC_MODE, (tp->mac_mode |
4124                                           MAC_MODE_SEND_CONFIGS));
4125                         udelay(1);
4126                         tw32_f(MAC_MODE, tp->mac_mode);
4127                 }
4128         }
4129
4130         if (current_link_up == 1) {
4131                 tp->link_config.active_speed = SPEED_1000;
4132                 tp->link_config.active_duplex = DUPLEX_FULL;
4133                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4134                                     LED_CTRL_LNKLED_OVERRIDE |
4135                                     LED_CTRL_1000MBPS_ON));
4136         } else {
4137                 tp->link_config.active_speed = SPEED_INVALID;
4138                 tp->link_config.active_duplex = DUPLEX_INVALID;
4139                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4140                                     LED_CTRL_LNKLED_OVERRIDE |
4141                                     LED_CTRL_TRAFFIC_OVERRIDE));
4142         }
4143
4144         if (current_link_up != netif_carrier_ok(tp->dev)) {
4145                 if (current_link_up)
4146                         netif_carrier_on(tp->dev);
4147                 else
4148                         netif_carrier_off(tp->dev);
4149                 tg3_link_report(tp);
4150         } else {
4151                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4152                 if (orig_pause_cfg != now_pause_cfg ||
4153                     orig_active_speed != tp->link_config.active_speed ||
4154                     orig_active_duplex != tp->link_config.active_duplex)
4155                         tg3_link_report(tp);
4156         }
4157
4158         return 0;
4159 }
4160
4161 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4162 {
4163         int current_link_up, err = 0;
4164         u32 bmsr, bmcr;
4165         u16 current_speed;
4166         u8 current_duplex;
4167         u32 local_adv, remote_adv;
4168
4169         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4170         tw32_f(MAC_MODE, tp->mac_mode);
4171         udelay(40);
4172
4173         tw32(MAC_EVENT, 0);
4174
4175         tw32_f(MAC_STATUS,
4176              (MAC_STATUS_SYNC_CHANGED |
4177               MAC_STATUS_CFG_CHANGED |
4178               MAC_STATUS_MI_COMPLETION |
4179               MAC_STATUS_LNKSTATE_CHANGED));
4180         udelay(40);
4181
4182         if (force_reset)
4183                 tg3_phy_reset(tp);
4184
4185         current_link_up = 0;
4186         current_speed = SPEED_INVALID;
4187         current_duplex = DUPLEX_INVALID;
4188
4189         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4190         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4191         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4192                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4193                         bmsr |= BMSR_LSTATUS;
4194                 else
4195                         bmsr &= ~BMSR_LSTATUS;
4196         }
4197
4198         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4199
4200         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4201             (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4202                 /* do nothing, just check for link up at the end */
4203         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4204                 u32 adv, new_adv;
4205
4206                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4207                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4208                                   ADVERTISE_1000XPAUSE |
4209                                   ADVERTISE_1000XPSE_ASYM |
4210                                   ADVERTISE_SLCT);
4211
4212                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4213
4214                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4215                         new_adv |= ADVERTISE_1000XHALF;
4216                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4217                         new_adv |= ADVERTISE_1000XFULL;
4218
4219                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4220                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4221                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4222                         tg3_writephy(tp, MII_BMCR, bmcr);
4223
4224                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4225                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4226                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4227
4228                         return err;
4229                 }
4230         } else {
4231                 u32 new_bmcr;
4232
4233                 bmcr &= ~BMCR_SPEED1000;
4234                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4235
4236                 if (tp->link_config.duplex == DUPLEX_FULL)
4237                         new_bmcr |= BMCR_FULLDPLX;
4238
4239                 if (new_bmcr != bmcr) {
4240                         /* BMCR_SPEED1000 is a reserved bit that needs
4241                          * to be set on write.
4242                          */
4243                         new_bmcr |= BMCR_SPEED1000;
4244
4245                         /* Force a linkdown */
4246                         if (netif_carrier_ok(tp->dev)) {
4247                                 u32 adv;
4248
4249                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4250                                 adv &= ~(ADVERTISE_1000XFULL |
4251                                          ADVERTISE_1000XHALF |
4252                                          ADVERTISE_SLCT);
4253                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4254                                 tg3_writephy(tp, MII_BMCR, bmcr |
4255                                                            BMCR_ANRESTART |
4256                                                            BMCR_ANENABLE);
4257                                 udelay(10);
4258                                 netif_carrier_off(tp->dev);
4259                         }
4260                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4261                         bmcr = new_bmcr;
4262                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4263                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4264                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4265                             ASIC_REV_5714) {
4266                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4267                                         bmsr |= BMSR_LSTATUS;
4268                                 else
4269                                         bmsr &= ~BMSR_LSTATUS;
4270                         }
4271                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4272                 }
4273         }
4274
4275         if (bmsr & BMSR_LSTATUS) {
4276                 current_speed = SPEED_1000;
4277                 current_link_up = 1;
4278                 if (bmcr & BMCR_FULLDPLX)
4279                         current_duplex = DUPLEX_FULL;
4280                 else
4281                         current_duplex = DUPLEX_HALF;
4282
4283                 local_adv = 0;
4284                 remote_adv = 0;
4285
4286                 if (bmcr & BMCR_ANENABLE) {
4287                         u32 common;
4288
4289                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4290                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4291                         common = local_adv & remote_adv;
4292                         if (common & (ADVERTISE_1000XHALF |
4293                                       ADVERTISE_1000XFULL)) {
4294                                 if (common & ADVERTISE_1000XFULL)
4295                                         current_duplex = DUPLEX_FULL;
4296                                 else
4297                                         current_duplex = DUPLEX_HALF;
4298                         } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4299                                 /* Link is up via parallel detect */
4300                         } else {
4301                                 current_link_up = 0;
4302                         }
4303                 }
4304         }
4305
4306         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4307                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4308
4309         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4310         if (tp->link_config.active_duplex == DUPLEX_HALF)
4311                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4312
4313         tw32_f(MAC_MODE, tp->mac_mode);
4314         udelay(40);
4315
4316         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4317
4318         tp->link_config.active_speed = current_speed;
4319         tp->link_config.active_duplex = current_duplex;
4320
4321         if (current_link_up != netif_carrier_ok(tp->dev)) {
4322                 if (current_link_up)
4323                         netif_carrier_on(tp->dev);
4324                 else {
4325                         netif_carrier_off(tp->dev);
4326                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4327                 }
4328                 tg3_link_report(tp);
4329         }
4330         return err;
4331 }
4332
4333 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4334 {
4335         if (tp->serdes_counter) {
4336                 /* Give autoneg time to complete. */
4337                 tp->serdes_counter--;
4338                 return;
4339         }
4340
4341         if (!netif_carrier_ok(tp->dev) &&
4342             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4343                 u32 bmcr;
4344
4345                 tg3_readphy(tp, MII_BMCR, &bmcr);
4346                 if (bmcr & BMCR_ANENABLE) {
4347                         u32 phy1, phy2;
4348
4349                         /* Select shadow register 0x1f */
4350                         tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4351                         tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4352
4353                         /* Select expansion interrupt status register */
4354                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4355                                          MII_TG3_DSP_EXP1_INT_STAT);
4356                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4357                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4358
4359                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4360                                 /* We have signal detect and not receiving
4361                                  * config code words, link is up by parallel
4362                                  * detection.
4363                                  */
4364
4365                                 bmcr &= ~BMCR_ANENABLE;
4366                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4367                                 tg3_writephy(tp, MII_BMCR, bmcr);
4368                                 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4369                         }
4370                 }
4371         } else if (netif_carrier_ok(tp->dev) &&
4372                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4373                    (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4374                 u32 phy2;
4375
4376                 /* Select expansion interrupt status register */
4377                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4378                                  MII_TG3_DSP_EXP1_INT_STAT);
4379                 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4380                 if (phy2 & 0x20) {
4381                         u32 bmcr;
4382
4383                         /* Config code words received, turn on autoneg. */
4384                         tg3_readphy(tp, MII_BMCR, &bmcr);
4385                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4386
4387                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4388
4389                 }
4390         }
4391 }
4392
4393 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4394 {
4395         u32 val;
4396         int err;
4397
4398         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4399                 err = tg3_setup_fiber_phy(tp, force_reset);
4400         else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4401                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4402         else
4403                 err = tg3_setup_copper_phy(tp, force_reset);
4404
4405         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4406                 u32 scale;
4407
4408                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4409                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4410                         scale = 65;
4411                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4412                         scale = 6;
4413                 else
4414                         scale = 12;
4415
4416                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4417                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4418                 tw32(GRC_MISC_CFG, val);
4419         }
4420
4421         val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4422               (6 << TX_LENGTHS_IPG_SHIFT);
4423         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
4424                 val |= tr32(MAC_TX_LENGTHS) &
4425                        (TX_LENGTHS_JMB_FRM_LEN_MSK |
4426                         TX_LENGTHS_CNT_DWN_VAL_MSK);
4427
4428         if (tp->link_config.active_speed == SPEED_1000 &&
4429             tp->link_config.active_duplex == DUPLEX_HALF)
4430                 tw32(MAC_TX_LENGTHS, val |
4431                      (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
4432         else
4433                 tw32(MAC_TX_LENGTHS, val |
4434                      (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
4435
4436         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4437                 if (netif_carrier_ok(tp->dev)) {
4438                         tw32(HOSTCC_STAT_COAL_TICKS,
4439                              tp->coal.stats_block_coalesce_usecs);
4440                 } else {
4441                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4442                 }
4443         }
4444
4445         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4446                 val = tr32(PCIE_PWR_MGMT_THRESH);
4447                 if (!netif_carrier_ok(tp->dev))
4448                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4449                               tp->pwrmgmt_thresh;
4450                 else
4451                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4452                 tw32(PCIE_PWR_MGMT_THRESH, val);
4453         }
4454
4455         return err;
4456 }
4457
4458 static inline int tg3_irq_sync(struct tg3 *tp)
4459 {
4460         return tp->irq_sync;
4461 }
4462
4463 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
4464 {
4465         int i;
4466
4467         dst = (u32 *)((u8 *)dst + off);
4468         for (i = 0; i < len; i += sizeof(u32))
4469                 *dst++ = tr32(off + i);
4470 }
4471
4472 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
4473 {
4474         tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
4475         tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
4476         tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
4477         tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
4478         tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
4479         tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
4480         tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
4481         tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
4482         tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
4483         tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
4484         tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
4485         tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
4486         tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
4487         tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
4488         tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
4489         tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
4490         tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
4491         tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
4492         tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
4493
4494         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX)
4495                 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
4496
4497         tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
4498         tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
4499         tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
4500         tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
4501         tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
4502         tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
4503         tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
4504         tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
4505
4506         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4507                 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
4508                 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
4509                 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
4510         }
4511
4512         tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
4513         tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
4514         tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
4515         tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
4516         tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
4517
4518         if (tp->tg3_flags & TG3_FLAG_NVRAM)
4519                 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
4520 }
4521
4522 static void tg3_dump_state(struct tg3 *tp)
4523 {
4524         int i;
4525         u32 *regs;
4526
4527         regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
4528         if (!regs) {
4529                 netdev_err(tp->dev, "Failed allocating register dump buffer\n");
4530                 return;
4531         }
4532
4533         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4534                 /* Read up to but not including private PCI registers */
4535                 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
4536                         regs[i / sizeof(u32)] = tr32(i);
4537         } else
4538                 tg3_dump_legacy_regs(tp, regs);
4539
4540         for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
4541                 if (!regs[i + 0] && !regs[i + 1] &&
4542                     !regs[i + 2] && !regs[i + 3])
4543                         continue;
4544
4545                 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
4546                            i * 4,
4547                            regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
4548         }
4549
4550         kfree(regs);
4551
4552         for (i = 0; i < tp->irq_cnt; i++) {
4553                 struct tg3_napi *tnapi = &tp->napi[i];
4554
4555                 /* SW status block */
4556                 netdev_err(tp->dev,
4557                          "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
4558                            i,
4559                            tnapi->hw_status->status,
4560                            tnapi->hw_status->status_tag,
4561                            tnapi->hw_status->rx_jumbo_consumer,
4562                            tnapi->hw_status->rx_consumer,
4563                            tnapi->hw_status->rx_mini_consumer,
4564                            tnapi->hw_status->idx[0].rx_producer,
4565                            tnapi->hw_status->idx[0].tx_consumer);
4566
4567                 netdev_err(tp->dev,
4568                 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
4569                            i,
4570                            tnapi->last_tag, tnapi->last_irq_tag,
4571                            tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
4572                            tnapi->rx_rcb_ptr,
4573                            tnapi->prodring.rx_std_prod_idx,
4574                            tnapi->prodring.rx_std_cons_idx,
4575                            tnapi->prodring.rx_jmb_prod_idx,
4576                            tnapi->prodring.rx_jmb_cons_idx);
4577         }
4578 }
4579
4580 /* This is called whenever we suspect that the system chipset is re-
4581  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4582  * is bogus tx completions. We try to recover by setting the
4583  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4584  * in the workqueue.
4585  */
4586 static void tg3_tx_recover(struct tg3 *tp)
4587 {
4588         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4589                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4590
4591         netdev_warn(tp->dev,
4592                     "The system may be re-ordering memory-mapped I/O "
4593                     "cycles to the network device, attempting to recover. "
4594                     "Please report the problem to the driver maintainer "
4595                     "and include system chipset information.\n");
4596
4597         spin_lock(&tp->lock);
4598         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4599         spin_unlock(&tp->lock);
4600 }
4601
4602 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4603 {
4604         /* Tell compiler to fetch tx indices from memory. */
4605         barrier();
4606         return tnapi->tx_pending -
4607                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4608 }
4609
4610 /* Tigon3 never reports partial packet sends.  So we do not
4611  * need special logic to handle SKBs that have not had all
4612  * of their frags sent yet, like SunGEM does.
4613  */
4614 static void tg3_tx(struct tg3_napi *tnapi)
4615 {
4616         struct tg3 *tp = tnapi->tp;
4617         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4618         u32 sw_idx = tnapi->tx_cons;
4619         struct netdev_queue *txq;
4620         int index = tnapi - tp->napi;
4621
4622         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4623                 index--;
4624
4625         txq = netdev_get_tx_queue(tp->dev, index);
4626
4627         while (sw_idx != hw_idx) {
4628                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4629                 struct sk_buff *skb = ri->skb;
4630                 int i, tx_bug = 0;
4631
4632                 if (unlikely(skb == NULL)) {
4633                         tg3_tx_recover(tp);
4634                         return;
4635                 }
4636
4637                 pci_unmap_single(tp->pdev,
4638                                  dma_unmap_addr(ri, mapping),
4639                                  skb_headlen(skb),
4640                                  PCI_DMA_TODEVICE);
4641
4642                 ri->skb = NULL;
4643
4644                 sw_idx = NEXT_TX(sw_idx);
4645
4646                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4647                         ri = &tnapi->tx_buffers[sw_idx];
4648                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4649                                 tx_bug = 1;
4650
4651                         pci_unmap_page(tp->pdev,
4652                                        dma_unmap_addr(ri, mapping),
4653                                        skb_shinfo(skb)->frags[i].size,
4654                                        PCI_DMA_TODEVICE);
4655                         sw_idx = NEXT_TX(sw_idx);
4656                 }
4657
4658                 dev_kfree_skb(skb);
4659
4660                 if (unlikely(tx_bug)) {
4661                         tg3_tx_recover(tp);
4662                         return;
4663                 }
4664         }
4665
4666         tnapi->tx_cons = sw_idx;
4667
4668         /* Need to make the tx_cons update visible to tg3_start_xmit()
4669          * before checking for netif_queue_stopped().  Without the
4670          * memory barrier, there is a small possibility that tg3_start_xmit()
4671          * will miss it and cause the queue to be stopped forever.
4672          */
4673         smp_mb();
4674
4675         if (unlikely(netif_tx_queue_stopped(txq) &&
4676                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4677                 __netif_tx_lock(txq, smp_processor_id());
4678                 if (netif_tx_queue_stopped(txq) &&
4679                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4680                         netif_tx_wake_queue(txq);
4681                 __netif_tx_unlock(txq);
4682         }
4683 }
4684
4685 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4686 {
4687         if (!ri->skb)
4688                 return;
4689
4690         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4691                          map_sz, PCI_DMA_FROMDEVICE);
4692         dev_kfree_skb_any(ri->skb);
4693         ri->skb = NULL;
4694 }
4695
4696 /* Returns size of skb allocated or < 0 on error.
4697  *
4698  * We only need to fill in the address because the other members
4699  * of the RX descriptor are invariant, see tg3_init_rings.
4700  *
4701  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4702  * posting buffers we only dirty the first cache line of the RX
4703  * descriptor (containing the address).  Whereas for the RX status
4704  * buffers the cpu only reads the last cacheline of the RX descriptor
4705  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4706  */
4707 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4708                             u32 opaque_key, u32 dest_idx_unmasked)
4709 {
4710         struct tg3_rx_buffer_desc *desc;
4711         struct ring_info *map;
4712         struct sk_buff *skb;
4713         dma_addr_t mapping;
4714         int skb_size, dest_idx;
4715
4716         switch (opaque_key) {
4717         case RXD_OPAQUE_RING_STD:
4718                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4719                 desc = &tpr->rx_std[dest_idx];
4720                 map = &tpr->rx_std_buffers[dest_idx];
4721                 skb_size = tp->rx_pkt_map_sz;
4722                 break;
4723
4724         case RXD_OPAQUE_RING_JUMBO:
4725                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4726                 desc = &tpr->rx_jmb[dest_idx].std;
4727                 map = &tpr->rx_jmb_buffers[dest_idx];
4728                 skb_size = TG3_RX_JMB_MAP_SZ;
4729                 break;
4730
4731         default:
4732                 return -EINVAL;
4733         }
4734
4735         /* Do not overwrite any of the map or rp information
4736          * until we are sure we can commit to a new buffer.
4737          *
4738          * Callers depend upon this behavior and assume that
4739          * we leave everything unchanged if we fail.
4740          */
4741         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4742         if (skb == NULL)
4743                 return -ENOMEM;
4744
4745         skb_reserve(skb, tp->rx_offset);
4746
4747         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4748                                  PCI_DMA_FROMDEVICE);
4749         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4750                 dev_kfree_skb(skb);
4751                 return -EIO;
4752         }
4753
4754         map->skb = skb;
4755         dma_unmap_addr_set(map, mapping, mapping);
4756
4757         desc->addr_hi = ((u64)mapping >> 32);
4758         desc->addr_lo = ((u64)mapping & 0xffffffff);
4759
4760         return skb_size;
4761 }
4762
4763 /* We only need to move over in the address because the other
4764  * members of the RX descriptor are invariant.  See notes above
4765  * tg3_alloc_rx_skb for full details.
4766  */
4767 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4768                            struct tg3_rx_prodring_set *dpr,
4769                            u32 opaque_key, int src_idx,
4770                            u32 dest_idx_unmasked)
4771 {
4772         struct tg3 *tp = tnapi->tp;
4773         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4774         struct ring_info *src_map, *dest_map;
4775         struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
4776         int dest_idx;
4777
4778         switch (opaque_key) {
4779         case RXD_OPAQUE_RING_STD:
4780                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4781                 dest_desc = &dpr->rx_std[dest_idx];
4782                 dest_map = &dpr->rx_std_buffers[dest_idx];
4783                 src_desc = &spr->rx_std[src_idx];
4784                 src_map = &spr->rx_std_buffers[src_idx];
4785                 break;
4786
4787         case RXD_OPAQUE_RING_JUMBO:
4788                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4789                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4790                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4791                 src_desc = &spr->rx_jmb[src_idx].std;
4792                 src_map = &spr->rx_jmb_buffers[src_idx];
4793                 break;
4794
4795         default:
4796                 return;
4797         }
4798
4799         dest_map->skb = src_map->skb;
4800         dma_unmap_addr_set(dest_map, mapping,
4801                            dma_unmap_addr(src_map, mapping));
4802         dest_desc->addr_hi = src_desc->addr_hi;
4803         dest_desc->addr_lo = src_desc->addr_lo;
4804
4805         /* Ensure that the update to the skb happens after the physical
4806          * addresses have been transferred to the new BD location.
4807          */
4808         smp_wmb();
4809
4810         src_map->skb = NULL;
4811 }
4812
4813 /* The RX ring scheme is composed of multiple rings which post fresh
4814  * buffers to the chip, and one special ring the chip uses to report
4815  * status back to the host.
4816  *
4817  * The special ring reports the status of received packets to the
4818  * host.  The chip does not write into the original descriptor the
4819  * RX buffer was obtained from.  The chip simply takes the original
4820  * descriptor as provided by the host, updates the status and length
4821  * field, then writes this into the next status ring entry.
4822  *
4823  * Each ring the host uses to post buffers to the chip is described
4824  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4825  * it is first placed into the on-chip ram.  When the packet's length
4826  * is known, it walks down the TG3_BDINFO entries to select the ring.
4827  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4828  * which is within the range of the new packet's length is chosen.
4829  *
4830  * The "separate ring for rx status" scheme may sound queer, but it makes
4831  * sense from a cache coherency perspective.  If only the host writes
4832  * to the buffer post rings, and only the chip writes to the rx status
4833  * rings, then cache lines never move beyond shared-modified state.
4834  * If both the host and chip were to write into the same ring, cache line
4835  * eviction could occur since both entities want it in an exclusive state.
4836  */
4837 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4838 {
4839         struct tg3 *tp = tnapi->tp;
4840         u32 work_mask, rx_std_posted = 0;
4841         u32 std_prod_idx, jmb_prod_idx;
4842         u32 sw_idx = tnapi->rx_rcb_ptr;
4843         u16 hw_idx;
4844         int received;
4845         struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
4846
4847         hw_idx = *(tnapi->rx_rcb_prod_idx);
4848         /*
4849          * We need to order the read of hw_idx and the read of
4850          * the opaque cookie.
4851          */
4852         rmb();
4853         work_mask = 0;
4854         received = 0;
4855         std_prod_idx = tpr->rx_std_prod_idx;
4856         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4857         while (sw_idx != hw_idx && budget > 0) {
4858                 struct ring_info *ri;
4859                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4860                 unsigned int len;
4861                 struct sk_buff *skb;
4862                 dma_addr_t dma_addr;
4863                 u32 opaque_key, desc_idx, *post_ptr;
4864
4865                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4866                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4867                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4868                         ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4869                         dma_addr = dma_unmap_addr(ri, mapping);
4870                         skb = ri->skb;
4871                         post_ptr = &std_prod_idx;
4872                         rx_std_posted++;
4873                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4874                         ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4875                         dma_addr = dma_unmap_addr(ri, mapping);
4876                         skb = ri->skb;
4877                         post_ptr = &jmb_prod_idx;
4878                 } else
4879                         goto next_pkt_nopost;
4880
4881                 work_mask |= opaque_key;
4882
4883                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4884                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4885                 drop_it:
4886                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4887                                        desc_idx, *post_ptr);
4888                 drop_it_no_recycle:
4889                         /* Other statistics kept track of by card. */
4890                         tp->rx_dropped++;
4891                         goto next_pkt;
4892                 }
4893
4894                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4895                       ETH_FCS_LEN;
4896
4897                 if (len > TG3_RX_COPY_THRESH(tp)) {
4898                         int skb_size;
4899
4900                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4901                                                     *post_ptr);
4902                         if (skb_size < 0)
4903                                 goto drop_it;
4904
4905                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4906                                          PCI_DMA_FROMDEVICE);
4907
4908                         /* Ensure that the update to the skb happens
4909                          * after the usage of the old DMA mapping.
4910                          */
4911                         smp_wmb();
4912
4913                         ri->skb = NULL;
4914
4915                         skb_put(skb, len);
4916                 } else {
4917                         struct sk_buff *copy_skb;
4918
4919                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4920                                        desc_idx, *post_ptr);
4921
4922                         copy_skb = netdev_alloc_skb(tp->dev, len +
4923                                                     TG3_RAW_IP_ALIGN);
4924                         if (copy_skb == NULL)
4925                                 goto drop_it_no_recycle;
4926
4927                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4928                         skb_put(copy_skb, len);
4929                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4930                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4931                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4932
4933                         /* We'll reuse the original ring buffer. */
4934                         skb = copy_skb;
4935                 }
4936
4937                 if ((tp->dev->features & NETIF_F_RXCSUM) &&
4938                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4939                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4940                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4941                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4942                 else
4943                         skb_checksum_none_assert(skb);
4944
4945                 skb->protocol = eth_type_trans(skb, tp->dev);
4946
4947                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4948                     skb->protocol != htons(ETH_P_8021Q)) {
4949                         dev_kfree_skb(skb);
4950                         goto drop_it_no_recycle;
4951                 }
4952
4953                 if (desc->type_flags & RXD_FLAG_VLAN &&
4954                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
4955                         __vlan_hwaccel_put_tag(skb,
4956                                                desc->err_vlan & RXD_VLAN_MASK);
4957
4958                 napi_gro_receive(&tnapi->napi, skb);
4959
4960                 received++;
4961                 budget--;
4962
4963 next_pkt:
4964                 (*post_ptr)++;
4965
4966                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4967                         tpr->rx_std_prod_idx = std_prod_idx &
4968                                                tp->rx_std_ring_mask;
4969                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4970                                      tpr->rx_std_prod_idx);
4971                         work_mask &= ~RXD_OPAQUE_RING_STD;
4972                         rx_std_posted = 0;
4973                 }
4974 next_pkt_nopost:
4975                 sw_idx++;
4976                 sw_idx &= tp->rx_ret_ring_mask;
4977
4978                 /* Refresh hw_idx to see if there is new work */
4979                 if (sw_idx == hw_idx) {
4980                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4981                         rmb();
4982                 }
4983         }
4984
4985         /* ACK the status ring. */
4986         tnapi->rx_rcb_ptr = sw_idx;
4987         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4988
4989         /* Refill RX ring(s). */
4990         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4991                 if (work_mask & RXD_OPAQUE_RING_STD) {
4992                         tpr->rx_std_prod_idx = std_prod_idx &
4993                                                tp->rx_std_ring_mask;
4994                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4995                                      tpr->rx_std_prod_idx);
4996                 }
4997                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4998                         tpr->rx_jmb_prod_idx = jmb_prod_idx &
4999                                                tp->rx_jmb_ring_mask;
5000                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5001                                      tpr->rx_jmb_prod_idx);
5002                 }
5003                 mmiowb();
5004         } else if (work_mask) {
5005                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
5006                  * updated before the producer indices can be updated.
5007                  */
5008                 smp_wmb();
5009
5010                 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
5011                 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
5012
5013                 if (tnapi != &tp->napi[1])
5014                         napi_schedule(&tp->napi[1].napi);
5015         }
5016
5017         return received;
5018 }
5019
5020 static void tg3_poll_link(struct tg3 *tp)
5021 {
5022         /* handle link change and other phy events */
5023         if (!(tp->tg3_flags &
5024               (TG3_FLAG_USE_LINKCHG_REG |
5025                TG3_FLAG_POLL_SERDES))) {
5026                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
5027
5028                 if (sblk->status & SD_STATUS_LINK_CHG) {
5029                         sblk->status = SD_STATUS_UPDATED |
5030                                        (sblk->status & ~SD_STATUS_LINK_CHG);
5031                         spin_lock(&tp->lock);
5032                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
5033                                 tw32_f(MAC_STATUS,
5034                                      (MAC_STATUS_SYNC_CHANGED |
5035                                       MAC_STATUS_CFG_CHANGED |
5036                                       MAC_STATUS_MI_COMPLETION |
5037                                       MAC_STATUS_LNKSTATE_CHANGED));
5038                                 udelay(40);
5039                         } else
5040                                 tg3_setup_phy(tp, 0);
5041                         spin_unlock(&tp->lock);
5042                 }
5043         }
5044 }
5045
5046 static int tg3_rx_prodring_xfer(struct tg3 *tp,
5047                                 struct tg3_rx_prodring_set *dpr,
5048                                 struct tg3_rx_prodring_set *spr)
5049 {
5050         u32 si, di, cpycnt, src_prod_idx;
5051         int i, err = 0;
5052
5053         while (1) {
5054                 src_prod_idx = spr->rx_std_prod_idx;
5055
5056                 /* Make sure updates to the rx_std_buffers[] entries and the
5057                  * standard producer index are seen in the correct order.
5058                  */
5059                 smp_rmb();
5060
5061                 if (spr->rx_std_cons_idx == src_prod_idx)
5062                         break;
5063
5064                 if (spr->rx_std_cons_idx < src_prod_idx)
5065                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
5066                 else
5067                         cpycnt = tp->rx_std_ring_mask + 1 -
5068                                  spr->rx_std_cons_idx;
5069
5070                 cpycnt = min(cpycnt,
5071                              tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
5072
5073                 si = spr->rx_std_cons_idx;
5074                 di = dpr->rx_std_prod_idx;
5075
5076                 for (i = di; i < di + cpycnt; i++) {
5077                         if (dpr->rx_std_buffers[i].skb) {
5078                                 cpycnt = i - di;
5079                                 err = -ENOSPC;
5080                                 break;
5081                         }
5082                 }
5083
5084                 if (!cpycnt)
5085                         break;
5086
5087                 /* Ensure that updates to the rx_std_buffers ring and the
5088                  * shadowed hardware producer ring from tg3_recycle_skb() are
5089                  * ordered correctly WRT the skb check above.
5090                  */
5091                 smp_rmb();
5092
5093                 memcpy(&dpr->rx_std_buffers[di],
5094                        &spr->rx_std_buffers[si],
5095                        cpycnt * sizeof(struct ring_info));
5096
5097                 for (i = 0; i < cpycnt; i++, di++, si++) {
5098                         struct tg3_rx_buffer_desc *sbd, *dbd;
5099                         sbd = &spr->rx_std[si];
5100                         dbd = &dpr->rx_std[di];
5101                         dbd->addr_hi = sbd->addr_hi;
5102                         dbd->addr_lo = sbd->addr_lo;
5103                 }
5104
5105                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
5106                                        tp->rx_std_ring_mask;
5107                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
5108                                        tp->rx_std_ring_mask;
5109         }
5110
5111         while (1) {
5112                 src_prod_idx = spr->rx_jmb_prod_idx;
5113
5114                 /* Make sure updates to the rx_jmb_buffers[] entries and
5115                  * the jumbo producer index are seen in the correct order.
5116                  */
5117                 smp_rmb();
5118
5119                 if (spr->rx_jmb_cons_idx == src_prod_idx)
5120                         break;
5121
5122                 if (spr->rx_jmb_cons_idx < src_prod_idx)
5123                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
5124                 else
5125                         cpycnt = tp->rx_jmb_ring_mask + 1 -
5126                                  spr->rx_jmb_cons_idx;
5127
5128                 cpycnt = min(cpycnt,
5129                              tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
5130
5131                 si = spr->rx_jmb_cons_idx;
5132                 di = dpr->rx_jmb_prod_idx;
5133
5134                 for (i = di; i < di + cpycnt; i++) {
5135                         if (dpr->rx_jmb_buffers[i].skb) {
5136                                 cpycnt = i - di;
5137                                 err = -ENOSPC;
5138                                 break;
5139                         }
5140                 }
5141
5142                 if (!cpycnt)
5143                         break;
5144
5145                 /* Ensure that updates to the rx_jmb_buffers ring and the
5146                  * shadowed hardware producer ring from tg3_recycle_skb() are
5147                  * ordered correctly WRT the skb check above.
5148                  */
5149                 smp_rmb();
5150
5151                 memcpy(&dpr->rx_jmb_buffers[di],
5152                        &spr->rx_jmb_buffers[si],
5153                        cpycnt * sizeof(struct ring_info));
5154
5155                 for (i = 0; i < cpycnt; i++, di++, si++) {
5156                         struct tg3_rx_buffer_desc *sbd, *dbd;
5157                         sbd = &spr->rx_jmb[si].std;
5158                         dbd = &dpr->rx_jmb[di].std;
5159                         dbd->addr_hi = sbd->addr_hi;
5160                         dbd->addr_lo = sbd->addr_lo;
5161                 }
5162
5163                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
5164                                        tp->rx_jmb_ring_mask;
5165                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
5166                                        tp->rx_jmb_ring_mask;
5167         }
5168
5169         return err;
5170 }
5171
5172 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
5173 {
5174         struct tg3 *tp = tnapi->tp;
5175
5176         /* run TX completion thread */
5177         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
5178                 tg3_tx(tnapi);
5179                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5180                         return work_done;
5181         }
5182
5183         /* run RX thread, within the bounds set by NAPI.
5184          * All RX "locking" is done by ensuring outside
5185          * code synchronizes with tg3->napi.poll()
5186          */
5187         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
5188                 work_done += tg3_rx(tnapi, budget - work_done);
5189
5190         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
5191                 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
5192                 int i, err = 0;
5193                 u32 std_prod_idx = dpr->rx_std_prod_idx;
5194                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
5195
5196                 for (i = 1; i < tp->irq_cnt; i++)
5197                         err |= tg3_rx_prodring_xfer(tp, dpr,
5198                                                     &tp->napi[i].prodring);
5199
5200                 wmb();
5201
5202                 if (std_prod_idx != dpr->rx_std_prod_idx)
5203                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5204                                      dpr->rx_std_prod_idx);
5205
5206                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5207                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5208                                      dpr->rx_jmb_prod_idx);
5209
5210                 mmiowb();
5211
5212                 if (err)
5213                         tw32_f(HOSTCC_MODE, tp->coal_now);
5214         }
5215
5216         return work_done;
5217 }
5218
5219 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5220 {
5221         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5222         struct tg3 *tp = tnapi->tp;
5223         int work_done = 0;
5224         struct tg3_hw_status *sblk = tnapi->hw_status;
5225
5226         while (1) {
5227                 work_done = tg3_poll_work(tnapi, work_done, budget);
5228
5229                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5230                         goto tx_recovery;
5231
5232                 if (unlikely(work_done >= budget))
5233                         break;
5234
5235                 /* tp->last_tag is used in tg3_int_reenable() below
5236                  * to tell the hw how much work has been processed,
5237                  * so we must read it before checking for more work.
5238                  */
5239                 tnapi->last_tag = sblk->status_tag;
5240                 tnapi->last_irq_tag = tnapi->last_tag;
5241                 rmb();
5242
5243                 /* check for RX/TX work to do */
5244                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5245                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5246                         napi_complete(napi);
5247                         /* Reenable interrupts. */
5248                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5249                         mmiowb();
5250                         break;
5251                 }
5252         }
5253
5254         return work_done;
5255
5256 tx_recovery:
5257         /* work_done is guaranteed to be less than budget. */
5258         napi_complete(napi);
5259         schedule_work(&tp->reset_task);
5260         return work_done;
5261 }
5262
5263 static void tg3_process_error(struct tg3 *tp)
5264 {
5265         u32 val;
5266         bool real_error = false;
5267
5268         if (tp->tg3_flags & TG3_FLAG_ERROR_PROCESSED)
5269                 return;
5270
5271         /* Check Flow Attention register */
5272         val = tr32(HOSTCC_FLOW_ATTN);
5273         if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
5274                 netdev_err(tp->dev, "FLOW Attention error.  Resetting chip.\n");
5275                 real_error = true;
5276         }
5277
5278         if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
5279                 netdev_err(tp->dev, "MSI Status error.  Resetting chip.\n");
5280                 real_error = true;
5281         }
5282
5283         if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
5284                 netdev_err(tp->dev, "DMA Status error.  Resetting chip.\n");
5285                 real_error = true;
5286         }
5287
5288         if (!real_error)
5289                 return;
5290
5291         tg3_dump_state(tp);
5292
5293         tp->tg3_flags |= TG3_FLAG_ERROR_PROCESSED;
5294         schedule_work(&tp->reset_task);
5295 }
5296
5297 static int tg3_poll(struct napi_struct *napi, int budget)
5298 {
5299         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5300         struct tg3 *tp = tnapi->tp;
5301         int work_done = 0;
5302         struct tg3_hw_status *sblk = tnapi->hw_status;
5303
5304         while (1) {
5305                 if (sblk->status & SD_STATUS_ERROR)
5306                         tg3_process_error(tp);
5307
5308                 tg3_poll_link(tp);
5309
5310                 work_done = tg3_poll_work(tnapi, work_done, budget);
5311
5312                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5313                         goto tx_recovery;
5314
5315                 if (unlikely(work_done >= budget))
5316                         break;
5317
5318                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5319                         /* tp->last_tag is used in tg3_int_reenable() below
5320                          * to tell the hw how much work has been processed,
5321                          * so we must read it before checking for more work.
5322                          */
5323                         tnapi->last_tag = sblk->status_tag;
5324                         tnapi->last_irq_tag = tnapi->last_tag;
5325                         rmb();
5326                 } else
5327                         sblk->status &= ~SD_STATUS_UPDATED;
5328
5329                 if (likely(!tg3_has_work(tnapi))) {
5330                         napi_complete(napi);
5331                         tg3_int_reenable(tnapi);
5332                         break;
5333                 }
5334         }
5335
5336         return work_done;
5337
5338 tx_recovery:
5339         /* work_done is guaranteed to be less than budget. */
5340         napi_complete(napi);
5341         schedule_work(&tp->reset_task);
5342         return work_done;
5343 }
5344
5345 static void tg3_napi_disable(struct tg3 *tp)
5346 {
5347         int i;
5348
5349         for (i = tp->irq_cnt - 1; i >= 0; i--)
5350                 napi_disable(&tp->napi[i].napi);
5351 }
5352
5353 static void tg3_napi_enable(struct tg3 *tp)
5354 {
5355         int i;
5356
5357         for (i = 0; i < tp->irq_cnt; i++)
5358                 napi_enable(&tp->napi[i].napi);
5359 }
5360
5361 static void tg3_napi_init(struct tg3 *tp)
5362 {
5363         int i;
5364
5365         netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
5366         for (i = 1; i < tp->irq_cnt; i++)
5367                 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
5368 }
5369
5370 static void tg3_napi_fini(struct tg3 *tp)
5371 {
5372         int i;
5373
5374         for (i = 0; i < tp->irq_cnt; i++)
5375                 netif_napi_del(&tp->napi[i].napi);
5376 }
5377
5378 static inline void tg3_netif_stop(struct tg3 *tp)
5379 {
5380         tp->dev->trans_start = jiffies; /* prevent tx timeout */
5381         tg3_napi_disable(tp);
5382         netif_tx_disable(tp->dev);
5383 }
5384
5385 static inline void tg3_netif_start(struct tg3 *tp)
5386 {
5387         /* NOTE: unconditional netif_tx_wake_all_queues is only
5388          * appropriate so long as all callers are assured to
5389          * have free tx slots (such as after tg3_init_hw)
5390          */
5391         netif_tx_wake_all_queues(tp->dev);
5392
5393         tg3_napi_enable(tp);
5394         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
5395         tg3_enable_ints(tp);
5396 }
5397
5398 static void tg3_irq_quiesce(struct tg3 *tp)
5399 {
5400         int i;
5401
5402         BUG_ON(tp->irq_sync);
5403
5404         tp->irq_sync = 1;
5405         smp_mb();
5406
5407         for (i = 0; i < tp->irq_cnt; i++)
5408                 synchronize_irq(tp->napi[i].irq_vec);
5409 }
5410
5411 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5412  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5413  * with as well.  Most of the time, this is not necessary except when
5414  * shutting down the device.
5415  */
5416 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5417 {
5418         spin_lock_bh(&tp->lock);
5419         if (irq_sync)
5420                 tg3_irq_quiesce(tp);
5421 }
5422
5423 static inline void tg3_full_unlock(struct tg3 *tp)
5424 {
5425         spin_unlock_bh(&tp->lock);
5426 }
5427
5428 /* One-shot MSI handler - Chip automatically disables interrupt
5429  * after sending MSI so driver doesn't have to do it.
5430  */
5431 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5432 {
5433         struct tg3_napi *tnapi = dev_id;
5434         struct tg3 *tp = tnapi->tp;
5435
5436         prefetch(tnapi->hw_status);
5437         if (tnapi->rx_rcb)
5438                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5439
5440         if (likely(!tg3_irq_sync(tp)))
5441                 napi_schedule(&tnapi->napi);
5442
5443         return IRQ_HANDLED;
5444 }
5445
5446 /* MSI ISR - No need to check for interrupt sharing and no need to
5447  * flush status block and interrupt mailbox. PCI ordering rules
5448  * guarantee that MSI will arrive after the status block.
5449  */
5450 static irqreturn_t tg3_msi(int irq, void *dev_id)
5451 {
5452         struct tg3_napi *tnapi = dev_id;
5453         struct tg3 *tp = tnapi->tp;
5454
5455         prefetch(tnapi->hw_status);
5456         if (tnapi->rx_rcb)
5457                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5458         /*
5459          * Writing any value to intr-mbox-0 clears PCI INTA# and
5460          * chip-internal interrupt pending events.
5461          * Writing non-zero to intr-mbox-0 additional tells the
5462          * NIC to stop sending us irqs, engaging "in-intr-handler"
5463          * event coalescing.
5464          */
5465         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5466         if (likely(!tg3_irq_sync(tp)))
5467                 napi_schedule(&tnapi->napi);
5468
5469         return IRQ_RETVAL(1);
5470 }
5471
5472 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5473 {
5474         struct tg3_napi *tnapi = dev_id;
5475         struct tg3 *tp = tnapi->tp;
5476         struct tg3_hw_status *sblk = tnapi->hw_status;
5477         unsigned int handled = 1;
5478
5479         /* In INTx mode, it is possible for the interrupt to arrive at
5480          * the CPU before the status block posted prior to the interrupt.
5481          * Reading the PCI State register will confirm whether the
5482          * interrupt is ours and will flush the status block.
5483          */
5484         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5485                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5486                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5487                         handled = 0;
5488                         goto out;
5489                 }
5490         }
5491
5492         /*
5493          * Writing any value to intr-mbox-0 clears PCI INTA# and
5494          * chip-internal interrupt pending events.
5495          * Writing non-zero to intr-mbox-0 additional tells the
5496          * NIC to stop sending us irqs, engaging "in-intr-handler"
5497          * event coalescing.
5498          *
5499          * Flush the mailbox to de-assert the IRQ immediately to prevent
5500          * spurious interrupts.  The flush impacts performance but
5501          * excessive spurious interrupts can be worse in some cases.
5502          */
5503         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5504         if (tg3_irq_sync(tp))
5505                 goto out;
5506         sblk->status &= ~SD_STATUS_UPDATED;
5507         if (likely(tg3_has_work(tnapi))) {
5508                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5509                 napi_schedule(&tnapi->napi);
5510         } else {
5511                 /* No work, shared interrupt perhaps?  re-enable
5512                  * interrupts, and flush that PCI write
5513                  */
5514                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5515                                0x00000000);
5516         }
5517 out:
5518         return IRQ_RETVAL(handled);
5519 }
5520
5521 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5522 {
5523         struct tg3_napi *tnapi = dev_id;
5524         struct tg3 *tp = tnapi->tp;
5525         struct tg3_hw_status *sblk = tnapi->hw_status;
5526         unsigned int handled = 1;
5527
5528         /* In INTx mode, it is possible for the interrupt to arrive at
5529          * the CPU before the status block posted prior to the interrupt.
5530          * Reading the PCI State register will confirm whether the
5531          * interrupt is ours and will flush the status block.
5532          */
5533         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5534                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5535                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5536                         handled = 0;
5537                         goto out;
5538                 }
5539         }
5540
5541         /*
5542          * writing any value to intr-mbox-0 clears PCI INTA# and
5543          * chip-internal interrupt pending events.
5544          * writing non-zero to intr-mbox-0 additional tells the
5545          * NIC to stop sending us irqs, engaging "in-intr-handler"
5546          * event coalescing.
5547          *
5548          * Flush the mailbox to de-assert the IRQ immediately to prevent
5549          * spurious interrupts.  The flush impacts performance but
5550          * excessive spurious interrupts can be worse in some cases.
5551          */
5552         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5553
5554         /*
5555          * In a shared interrupt configuration, sometimes other devices'
5556          * interrupts will scream.  We record the current status tag here
5557          * so that the above check can report that the screaming interrupts
5558          * are unhandled.  Eventually they will be silenced.
5559          */
5560         tnapi->last_irq_tag = sblk->status_tag;
5561
5562         if (tg3_irq_sync(tp))
5563                 goto out;
5564
5565         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5566
5567         napi_schedule(&tnapi->napi);
5568
5569 out:
5570         return IRQ_RETVAL(handled);
5571 }
5572
5573 /* ISR for interrupt test */
5574 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5575 {
5576         struct tg3_napi *tnapi = dev_id;
5577         struct tg3 *tp = tnapi->tp;
5578         struct tg3_hw_status *sblk = tnapi->hw_status;
5579
5580         if ((sblk->status & SD_STATUS_UPDATED) ||
5581             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5582                 tg3_disable_ints(tp);
5583                 return IRQ_RETVAL(1);
5584         }
5585         return IRQ_RETVAL(0);
5586 }
5587
5588 static int tg3_init_hw(struct tg3 *, int);
5589 static int tg3_halt(struct tg3 *, int, int);
5590
5591 /* Restart hardware after configuration changes, self-test, etc.
5592  * Invoked with tp->lock held.
5593  */
5594 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5595         __releases(tp->lock)
5596         __acquires(tp->lock)
5597 {
5598         int err;
5599
5600         err = tg3_init_hw(tp, reset_phy);
5601         if (err) {
5602                 netdev_err(tp->dev,
5603                            "Failed to re-initialize device, aborting\n");
5604                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5605                 tg3_full_unlock(tp);
5606                 del_timer_sync(&tp->timer);
5607                 tp->irq_sync = 0;
5608                 tg3_napi_enable(tp);
5609                 dev_close(tp->dev);
5610                 tg3_full_lock(tp, 0);
5611         }
5612         return err;
5613 }
5614
5615 #ifdef CONFIG_NET_POLL_CONTROLLER
5616 static void tg3_poll_controller(struct net_device *dev)
5617 {
5618         int i;
5619         struct tg3 *tp = netdev_priv(dev);
5620
5621         for (i = 0; i < tp->irq_cnt; i++)
5622                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5623 }
5624 #endif
5625
5626 static void tg3_reset_task(struct work_struct *work)
5627 {
5628         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5629         int err;
5630         unsigned int restart_timer;
5631
5632         tg3_full_lock(tp, 0);
5633
5634         if (!netif_running(tp->dev)) {
5635                 tg3_full_unlock(tp);
5636                 return;
5637         }
5638
5639         tg3_full_unlock(tp);
5640
5641         tg3_phy_stop(tp);
5642
5643         tg3_netif_stop(tp);
5644
5645         tg3_full_lock(tp, 1);
5646
5647         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5648         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5649
5650         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5651                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5652                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5653                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5654                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5655         }
5656
5657         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5658         err = tg3_init_hw(tp, 1);
5659         if (err)
5660                 goto out;
5661
5662         tg3_netif_start(tp);
5663
5664         if (restart_timer)
5665                 mod_timer(&tp->timer, jiffies + 1);
5666
5667 out:
5668         tg3_full_unlock(tp);
5669
5670         if (!err)
5671                 tg3_phy_start(tp);
5672 }
5673
5674 static void tg3_tx_timeout(struct net_device *dev)
5675 {
5676         struct tg3 *tp = netdev_priv(dev);
5677
5678         if (netif_msg_tx_err(tp)) {
5679                 netdev_err(dev, "transmit timed out, resetting\n");
5680                 tg3_dump_state(tp);
5681         }
5682
5683         schedule_work(&tp->reset_task);
5684 }
5685
5686 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5687 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5688 {
5689         u32 base = (u32) mapping & 0xffffffff;
5690
5691         return (base > 0xffffdcc0) && (base + len + 8 < base);
5692 }
5693
5694 /* Test for DMA addresses > 40-bit */
5695 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5696                                           int len)
5697 {
5698 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5699         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5700                 return ((u64) mapping + len) > DMA_BIT_MASK(40);
5701         return 0;
5702 #else
5703         return 0;
5704 #endif
5705 }
5706
5707 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5708
5709 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5710 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5711                                        struct sk_buff *skb, u32 last_plus_one,
5712                                        u32 *start, u32 base_flags, u32 mss)
5713 {
5714         struct tg3 *tp = tnapi->tp;
5715         struct sk_buff *new_skb;
5716         dma_addr_t new_addr = 0;
5717         u32 entry = *start;
5718         int i, ret = 0;
5719
5720         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5721                 new_skb = skb_copy(skb, GFP_ATOMIC);
5722         else {
5723                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5724
5725                 new_skb = skb_copy_expand(skb,
5726                                           skb_headroom(skb) + more_headroom,
5727                                           skb_tailroom(skb), GFP_ATOMIC);
5728         }
5729
5730         if (!new_skb) {
5731                 ret = -1;
5732         } else {
5733                 /* New SKB is guaranteed to be linear. */
5734                 entry = *start;
5735                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5736                                           PCI_DMA_TODEVICE);
5737                 /* Make sure the mapping succeeded */
5738                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5739                         ret = -1;
5740                         dev_kfree_skb(new_skb);
5741                         new_skb = NULL;
5742
5743                 /* Make sure new skb does not cross any 4G boundaries.
5744                  * Drop the packet if it does.
5745                  */
5746                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5747                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5748                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5749                                          PCI_DMA_TODEVICE);
5750                         ret = -1;
5751                         dev_kfree_skb(new_skb);
5752                         new_skb = NULL;
5753                 } else {
5754                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5755                                     base_flags, 1 | (mss << 1));
5756                         *start = NEXT_TX(entry);
5757                 }
5758         }
5759
5760         /* Now clean up the sw ring entries. */
5761         i = 0;
5762         while (entry != last_plus_one) {
5763                 int len;
5764
5765                 if (i == 0)
5766                         len = skb_headlen(skb);
5767                 else
5768                         len = skb_shinfo(skb)->frags[i-1].size;
5769
5770                 pci_unmap_single(tp->pdev,
5771                                  dma_unmap_addr(&tnapi->tx_buffers[entry],