tg3: Use netif_set_real_num_{rx,tx}_queues()
[linux-2.6.git] / drivers / net / tg3.c
1 /*
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  * Copyright (C) 2005-2010 Broadcom Corporation.
8  *
9  * Firmware is:
10  *      Derived from proprietary unpublished source code,
11  *      Copyright (C) 2000-2003 Broadcom Corporation.
12  *
13  *      Permission is hereby granted for the distribution of this firmware
14  *      data in hexadecimal or equivalent format, provided this copyright
15  *      notice is accompanying it.
16  */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/in.h>
28 #include <linux/init.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mii.h>
36 #include <linux/phy.h>
37 #include <linux/brcmphy.h>
38 #include <linux/if_vlan.h>
39 #include <linux/ip.h>
40 #include <linux/tcp.h>
41 #include <linux/workqueue.h>
42 #include <linux/prefetch.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/firmware.h>
45
46 #include <net/checksum.h>
47 #include <net/ip.h>
48
49 #include <asm/system.h>
50 #include <asm/io.h>
51 #include <asm/byteorder.h>
52 #include <asm/uaccess.h>
53
54 #ifdef CONFIG_SPARC
55 #include <asm/idprom.h>
56 #include <asm/prom.h>
57 #endif
58
59 #define BAR_0   0
60 #define BAR_2   2
61
62 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
63 #define TG3_VLAN_TAG_USED 1
64 #else
65 #define TG3_VLAN_TAG_USED 0
66 #endif
67
68 #include "tg3.h"
69
70 #define DRV_MODULE_NAME         "tg3"
71 #define TG3_MAJ_NUM                     3
72 #define TG3_MIN_NUM                     113
73 #define DRV_MODULE_VERSION      \
74         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
75 #define DRV_MODULE_RELDATE      "August 2, 2010"
76
77 #define TG3_DEF_MAC_MODE        0
78 #define TG3_DEF_RX_MODE         0
79 #define TG3_DEF_TX_MODE         0
80 #define TG3_DEF_MSG_ENABLE        \
81         (NETIF_MSG_DRV          | \
82          NETIF_MSG_PROBE        | \
83          NETIF_MSG_LINK         | \
84          NETIF_MSG_TIMER        | \
85          NETIF_MSG_IFDOWN       | \
86          NETIF_MSG_IFUP         | \
87          NETIF_MSG_RX_ERR       | \
88          NETIF_MSG_TX_ERR)
89
90 /* length of time before we decide the hardware is borked,
91  * and dev->tx_timeout() should be called to fix the problem
92  */
93 #define TG3_TX_TIMEOUT                  (5 * HZ)
94
95 /* hardware minimum and maximum for a single frame's data payload */
96 #define TG3_MIN_MTU                     60
97 #define TG3_MAX_MTU(tp) \
98         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
99
100 /* These numbers seem to be hard coded in the NIC firmware somehow.
101  * You can't change the ring sizes, but you can change where you place
102  * them in the NIC onboard memory.
103  */
104 #define TG3_RX_RING_SIZE                512
105 #define TG3_DEF_RX_RING_PENDING         200
106 #define TG3_RX_JUMBO_RING_SIZE          256
107 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
108 #define TG3_RSS_INDIR_TBL_SIZE          128
109
110 /* Do not place this n-ring entries value into the tp struct itself,
111  * we really want to expose these constants to GCC so that modulo et
112  * al.  operations are done with shifts and masks instead of with
113  * hw multiply/modulo instructions.  Another solution would be to
114  * replace things like '% foo' with '& (foo - 1)'.
115  */
116 #define TG3_RX_RCB_RING_SIZE(tp)        \
117         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
118           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
119
120 #define TG3_TX_RING_SIZE                512
121 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
122
123 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
124                                  TG3_RX_RING_SIZE)
125 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
126                                  TG3_RX_JUMBO_RING_SIZE)
127 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
128                                  TG3_RX_RCB_RING_SIZE(tp))
129 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
130                                  TG3_TX_RING_SIZE)
131 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
132
133 #define TG3_RX_DMA_ALIGN                16
134 #define TG3_RX_HEADROOM                 ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
135
136 #define TG3_DMA_BYTE_ENAB               64
137
138 #define TG3_RX_STD_DMA_SZ               1536
139 #define TG3_RX_JMB_DMA_SZ               9046
140
141 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
142
143 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
144 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
145
146 #define TG3_RX_STD_BUFF_RING_SIZE \
147         (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
148
149 #define TG3_RX_JMB_BUFF_RING_SIZE \
150         (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
151
152 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
153  * that are at least dword aligned when used in PCIX mode.  The driver
154  * works around this bug by double copying the packet.  This workaround
155  * is built into the normal double copy length check for efficiency.
156  *
157  * However, the double copy is only necessary on those architectures
158  * where unaligned memory accesses are inefficient.  For those architectures
159  * where unaligned memory accesses incur little penalty, we can reintegrate
160  * the 5701 in the normal rx path.  Doing so saves a device structure
161  * dereference by hardcoding the double copy threshold in place.
162  */
163 #define TG3_RX_COPY_THRESHOLD           256
164 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
165         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
166 #else
167         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
168 #endif
169
170 /* minimum number of free TX descriptors required to wake up TX process */
171 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
172
173 #define TG3_RAW_IP_ALIGN 2
174
175 /* number of ETHTOOL_GSTATS u64's */
176 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
177
178 #define TG3_NUM_TEST            6
179
180 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
181
182 #define FIRMWARE_TG3            "tigon/tg3.bin"
183 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
184 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
185
186 static char version[] __devinitdata =
187         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
188
189 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
190 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
191 MODULE_LICENSE("GPL");
192 MODULE_VERSION(DRV_MODULE_VERSION);
193 MODULE_FIRMWARE(FIRMWARE_TG3);
194 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
195 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
196
197 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
198 module_param(tg3_debug, int, 0);
199 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
200
201 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
268         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
269         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
270         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
271         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
272         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
273         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
274         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
275         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
276         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
277         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
278         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
279         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
280         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
281         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
282         {}
283 };
284
285 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
286
287 static const struct {
288         const char string[ETH_GSTRING_LEN];
289 } ethtool_stats_keys[TG3_NUM_STATS] = {
290         { "rx_octets" },
291         { "rx_fragments" },
292         { "rx_ucast_packets" },
293         { "rx_mcast_packets" },
294         { "rx_bcast_packets" },
295         { "rx_fcs_errors" },
296         { "rx_align_errors" },
297         { "rx_xon_pause_rcvd" },
298         { "rx_xoff_pause_rcvd" },
299         { "rx_mac_ctrl_rcvd" },
300         { "rx_xoff_entered" },
301         { "rx_frame_too_long_errors" },
302         { "rx_jabbers" },
303         { "rx_undersize_packets" },
304         { "rx_in_length_errors" },
305         { "rx_out_length_errors" },
306         { "rx_64_or_less_octet_packets" },
307         { "rx_65_to_127_octet_packets" },
308         { "rx_128_to_255_octet_packets" },
309         { "rx_256_to_511_octet_packets" },
310         { "rx_512_to_1023_octet_packets" },
311         { "rx_1024_to_1522_octet_packets" },
312         { "rx_1523_to_2047_octet_packets" },
313         { "rx_2048_to_4095_octet_packets" },
314         { "rx_4096_to_8191_octet_packets" },
315         { "rx_8192_to_9022_octet_packets" },
316
317         { "tx_octets" },
318         { "tx_collisions" },
319
320         { "tx_xon_sent" },
321         { "tx_xoff_sent" },
322         { "tx_flow_control" },
323         { "tx_mac_errors" },
324         { "tx_single_collisions" },
325         { "tx_mult_collisions" },
326         { "tx_deferred" },
327         { "tx_excessive_collisions" },
328         { "tx_late_collisions" },
329         { "tx_collide_2times" },
330         { "tx_collide_3times" },
331         { "tx_collide_4times" },
332         { "tx_collide_5times" },
333         { "tx_collide_6times" },
334         { "tx_collide_7times" },
335         { "tx_collide_8times" },
336         { "tx_collide_9times" },
337         { "tx_collide_10times" },
338         { "tx_collide_11times" },
339         { "tx_collide_12times" },
340         { "tx_collide_13times" },
341         { "tx_collide_14times" },
342         { "tx_collide_15times" },
343         { "tx_ucast_packets" },
344         { "tx_mcast_packets" },
345         { "tx_bcast_packets" },
346         { "tx_carrier_sense_errors" },
347         { "tx_discards" },
348         { "tx_errors" },
349
350         { "dma_writeq_full" },
351         { "dma_write_prioq_full" },
352         { "rxbds_empty" },
353         { "rx_discards" },
354         { "rx_errors" },
355         { "rx_threshold_hit" },
356
357         { "dma_readq_full" },
358         { "dma_read_prioq_full" },
359         { "tx_comp_queue_full" },
360
361         { "ring_set_send_prod_index" },
362         { "ring_status_update" },
363         { "nic_irqs" },
364         { "nic_avoided_irqs" },
365         { "nic_tx_threshold_hit" }
366 };
367
368 static const struct {
369         const char string[ETH_GSTRING_LEN];
370 } ethtool_test_keys[TG3_NUM_TEST] = {
371         { "nvram test     (online) " },
372         { "link test      (online) " },
373         { "register test  (offline)" },
374         { "memory test    (offline)" },
375         { "loopback test  (offline)" },
376         { "interrupt test (offline)" },
377 };
378
379 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
380 {
381         writel(val, tp->regs + off);
382 }
383
384 static u32 tg3_read32(struct tg3 *tp, u32 off)
385 {
386         return readl(tp->regs + off);
387 }
388
389 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
390 {
391         writel(val, tp->aperegs + off);
392 }
393
394 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
395 {
396         return readl(tp->aperegs + off);
397 }
398
399 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
400 {
401         unsigned long flags;
402
403         spin_lock_irqsave(&tp->indirect_lock, flags);
404         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
405         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
406         spin_unlock_irqrestore(&tp->indirect_lock, flags);
407 }
408
409 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
410 {
411         writel(val, tp->regs + off);
412         readl(tp->regs + off);
413 }
414
415 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
416 {
417         unsigned long flags;
418         u32 val;
419
420         spin_lock_irqsave(&tp->indirect_lock, flags);
421         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
422         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
423         spin_unlock_irqrestore(&tp->indirect_lock, flags);
424         return val;
425 }
426
427 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
428 {
429         unsigned long flags;
430
431         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
432                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
433                                        TG3_64BIT_REG_LOW, val);
434                 return;
435         }
436         if (off == TG3_RX_STD_PROD_IDX_REG) {
437                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
438                                        TG3_64BIT_REG_LOW, val);
439                 return;
440         }
441
442         spin_lock_irqsave(&tp->indirect_lock, flags);
443         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
444         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
445         spin_unlock_irqrestore(&tp->indirect_lock, flags);
446
447         /* In indirect mode when disabling interrupts, we also need
448          * to clear the interrupt bit in the GRC local ctrl register.
449          */
450         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
451             (val == 0x1)) {
452                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
453                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
454         }
455 }
456
457 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
458 {
459         unsigned long flags;
460         u32 val;
461
462         spin_lock_irqsave(&tp->indirect_lock, flags);
463         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
464         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
465         spin_unlock_irqrestore(&tp->indirect_lock, flags);
466         return val;
467 }
468
469 /* usec_wait specifies the wait time in usec when writing to certain registers
470  * where it is unsafe to read back the register without some delay.
471  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
472  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
473  */
474 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
475 {
476         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
477             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
478                 /* Non-posted methods */
479                 tp->write32(tp, off, val);
480         else {
481                 /* Posted method */
482                 tg3_write32(tp, off, val);
483                 if (usec_wait)
484                         udelay(usec_wait);
485                 tp->read32(tp, off);
486         }
487         /* Wait again after the read for the posted method to guarantee that
488          * the wait time is met.
489          */
490         if (usec_wait)
491                 udelay(usec_wait);
492 }
493
494 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
495 {
496         tp->write32_mbox(tp, off, val);
497         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
498             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
499                 tp->read32_mbox(tp, off);
500 }
501
502 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
503 {
504         void __iomem *mbox = tp->regs + off;
505         writel(val, mbox);
506         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
507                 writel(val, mbox);
508         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
509                 readl(mbox);
510 }
511
512 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
513 {
514         return readl(tp->regs + off + GRCMBOX_BASE);
515 }
516
517 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
518 {
519         writel(val, tp->regs + off + GRCMBOX_BASE);
520 }
521
522 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
523 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
524 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
525 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
526 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
527
528 #define tw32(reg, val)                  tp->write32(tp, reg, val)
529 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
530 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
531 #define tr32(reg)                       tp->read32(tp, reg)
532
533 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
534 {
535         unsigned long flags;
536
537         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
538             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
539                 return;
540
541         spin_lock_irqsave(&tp->indirect_lock, flags);
542         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
543                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
544                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
545
546                 /* Always leave this as zero. */
547                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
548         } else {
549                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
550                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
551
552                 /* Always leave this as zero. */
553                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
554         }
555         spin_unlock_irqrestore(&tp->indirect_lock, flags);
556 }
557
558 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
559 {
560         unsigned long flags;
561
562         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
563             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
564                 *val = 0;
565                 return;
566         }
567
568         spin_lock_irqsave(&tp->indirect_lock, flags);
569         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
570                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
571                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
572
573                 /* Always leave this as zero. */
574                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
575         } else {
576                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
577                 *val = tr32(TG3PCI_MEM_WIN_DATA);
578
579                 /* Always leave this as zero. */
580                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
581         }
582         spin_unlock_irqrestore(&tp->indirect_lock, flags);
583 }
584
585 static void tg3_ape_lock_init(struct tg3 *tp)
586 {
587         int i;
588         u32 regbase;
589
590         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
591                 regbase = TG3_APE_LOCK_GRANT;
592         else
593                 regbase = TG3_APE_PER_LOCK_GRANT;
594
595         /* Make sure the driver hasn't any stale locks. */
596         for (i = 0; i < 8; i++)
597                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
598 }
599
600 static int tg3_ape_lock(struct tg3 *tp, int locknum)
601 {
602         int i, off;
603         int ret = 0;
604         u32 status, req, gnt;
605
606         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
607                 return 0;
608
609         switch (locknum) {
610         case TG3_APE_LOCK_GRC:
611         case TG3_APE_LOCK_MEM:
612                 break;
613         default:
614                 return -EINVAL;
615         }
616
617         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
618                 req = TG3_APE_LOCK_REQ;
619                 gnt = TG3_APE_LOCK_GRANT;
620         } else {
621                 req = TG3_APE_PER_LOCK_REQ;
622                 gnt = TG3_APE_PER_LOCK_GRANT;
623         }
624
625         off = 4 * locknum;
626
627         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
628
629         /* Wait for up to 1 millisecond to acquire lock. */
630         for (i = 0; i < 100; i++) {
631                 status = tg3_ape_read32(tp, gnt + off);
632                 if (status == APE_LOCK_GRANT_DRIVER)
633                         break;
634                 udelay(10);
635         }
636
637         if (status != APE_LOCK_GRANT_DRIVER) {
638                 /* Revoke the lock request. */
639                 tg3_ape_write32(tp, gnt + off,
640                                 APE_LOCK_GRANT_DRIVER);
641
642                 ret = -EBUSY;
643         }
644
645         return ret;
646 }
647
648 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
649 {
650         u32 gnt;
651
652         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
653                 return;
654
655         switch (locknum) {
656         case TG3_APE_LOCK_GRC:
657         case TG3_APE_LOCK_MEM:
658                 break;
659         default:
660                 return;
661         }
662
663         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
664                 gnt = TG3_APE_LOCK_GRANT;
665         else
666                 gnt = TG3_APE_PER_LOCK_GRANT;
667
668         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
669 }
670
671 static void tg3_disable_ints(struct tg3 *tp)
672 {
673         int i;
674
675         tw32(TG3PCI_MISC_HOST_CTRL,
676              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
677         for (i = 0; i < tp->irq_max; i++)
678                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
679 }
680
681 static void tg3_enable_ints(struct tg3 *tp)
682 {
683         int i;
684
685         tp->irq_sync = 0;
686         wmb();
687
688         tw32(TG3PCI_MISC_HOST_CTRL,
689              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
690
691         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
692         for (i = 0; i < tp->irq_cnt; i++) {
693                 struct tg3_napi *tnapi = &tp->napi[i];
694
695                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
696                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
697                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
698
699                 tp->coal_now |= tnapi->coal_now;
700         }
701
702         /* Force an initial interrupt */
703         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
704             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
705                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
706         else
707                 tw32(HOSTCC_MODE, tp->coal_now);
708
709         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
710 }
711
712 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
713 {
714         struct tg3 *tp = tnapi->tp;
715         struct tg3_hw_status *sblk = tnapi->hw_status;
716         unsigned int work_exists = 0;
717
718         /* check for phy events */
719         if (!(tp->tg3_flags &
720               (TG3_FLAG_USE_LINKCHG_REG |
721                TG3_FLAG_POLL_SERDES))) {
722                 if (sblk->status & SD_STATUS_LINK_CHG)
723                         work_exists = 1;
724         }
725         /* check for RX/TX work to do */
726         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
727             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
728                 work_exists = 1;
729
730         return work_exists;
731 }
732
733 /* tg3_int_reenable
734  *  similar to tg3_enable_ints, but it accurately determines whether there
735  *  is new work pending and can return without flushing the PIO write
736  *  which reenables interrupts
737  */
738 static void tg3_int_reenable(struct tg3_napi *tnapi)
739 {
740         struct tg3 *tp = tnapi->tp;
741
742         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
743         mmiowb();
744
745         /* When doing tagged status, this work check is unnecessary.
746          * The last_tag we write above tells the chip which piece of
747          * work we've completed.
748          */
749         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
750             tg3_has_work(tnapi))
751                 tw32(HOSTCC_MODE, tp->coalesce_mode |
752                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
753 }
754
755 static void tg3_napi_disable(struct tg3 *tp)
756 {
757         int i;
758
759         for (i = tp->irq_cnt - 1; i >= 0; i--)
760                 napi_disable(&tp->napi[i].napi);
761 }
762
763 static void tg3_napi_enable(struct tg3 *tp)
764 {
765         int i;
766
767         for (i = 0; i < tp->irq_cnt; i++)
768                 napi_enable(&tp->napi[i].napi);
769 }
770
771 static inline void tg3_netif_stop(struct tg3 *tp)
772 {
773         tp->dev->trans_start = jiffies; /* prevent tx timeout */
774         tg3_napi_disable(tp);
775         netif_tx_disable(tp->dev);
776 }
777
778 static inline void tg3_netif_start(struct tg3 *tp)
779 {
780         /* NOTE: unconditional netif_tx_wake_all_queues is only
781          * appropriate so long as all callers are assured to
782          * have free tx slots (such as after tg3_init_hw)
783          */
784         netif_tx_wake_all_queues(tp->dev);
785
786         tg3_napi_enable(tp);
787         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
788         tg3_enable_ints(tp);
789 }
790
791 static void tg3_switch_clocks(struct tg3 *tp)
792 {
793         u32 clock_ctrl;
794         u32 orig_clock_ctrl;
795
796         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
797             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
798                 return;
799
800         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
801
802         orig_clock_ctrl = clock_ctrl;
803         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
804                        CLOCK_CTRL_CLKRUN_OENABLE |
805                        0x1f);
806         tp->pci_clock_ctrl = clock_ctrl;
807
808         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
809                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
810                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
811                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
812                 }
813         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
814                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
815                             clock_ctrl |
816                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
817                             40);
818                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
819                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
820                             40);
821         }
822         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
823 }
824
825 #define PHY_BUSY_LOOPS  5000
826
827 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
828 {
829         u32 frame_val;
830         unsigned int loops;
831         int ret;
832
833         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
834                 tw32_f(MAC_MI_MODE,
835                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
836                 udelay(80);
837         }
838
839         *val = 0x0;
840
841         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
842                       MI_COM_PHY_ADDR_MASK);
843         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
844                       MI_COM_REG_ADDR_MASK);
845         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
846
847         tw32_f(MAC_MI_COM, frame_val);
848
849         loops = PHY_BUSY_LOOPS;
850         while (loops != 0) {
851                 udelay(10);
852                 frame_val = tr32(MAC_MI_COM);
853
854                 if ((frame_val & MI_COM_BUSY) == 0) {
855                         udelay(5);
856                         frame_val = tr32(MAC_MI_COM);
857                         break;
858                 }
859                 loops -= 1;
860         }
861
862         ret = -EBUSY;
863         if (loops != 0) {
864                 *val = frame_val & MI_COM_DATA_MASK;
865                 ret = 0;
866         }
867
868         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
869                 tw32_f(MAC_MI_MODE, tp->mi_mode);
870                 udelay(80);
871         }
872
873         return ret;
874 }
875
876 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
877 {
878         u32 frame_val;
879         unsigned int loops;
880         int ret;
881
882         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
883             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
884                 return 0;
885
886         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
887                 tw32_f(MAC_MI_MODE,
888                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
889                 udelay(80);
890         }
891
892         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
893                       MI_COM_PHY_ADDR_MASK);
894         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
895                       MI_COM_REG_ADDR_MASK);
896         frame_val |= (val & MI_COM_DATA_MASK);
897         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
898
899         tw32_f(MAC_MI_COM, frame_val);
900
901         loops = PHY_BUSY_LOOPS;
902         while (loops != 0) {
903                 udelay(10);
904                 frame_val = tr32(MAC_MI_COM);
905                 if ((frame_val & MI_COM_BUSY) == 0) {
906                         udelay(5);
907                         frame_val = tr32(MAC_MI_COM);
908                         break;
909                 }
910                 loops -= 1;
911         }
912
913         ret = -EBUSY;
914         if (loops != 0)
915                 ret = 0;
916
917         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
918                 tw32_f(MAC_MI_MODE, tp->mi_mode);
919                 udelay(80);
920         }
921
922         return ret;
923 }
924
925 static int tg3_bmcr_reset(struct tg3 *tp)
926 {
927         u32 phy_control;
928         int limit, err;
929
930         /* OK, reset it, and poll the BMCR_RESET bit until it
931          * clears or we time out.
932          */
933         phy_control = BMCR_RESET;
934         err = tg3_writephy(tp, MII_BMCR, phy_control);
935         if (err != 0)
936                 return -EBUSY;
937
938         limit = 5000;
939         while (limit--) {
940                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
941                 if (err != 0)
942                         return -EBUSY;
943
944                 if ((phy_control & BMCR_RESET) == 0) {
945                         udelay(40);
946                         break;
947                 }
948                 udelay(10);
949         }
950         if (limit < 0)
951                 return -EBUSY;
952
953         return 0;
954 }
955
956 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
957 {
958         struct tg3 *tp = bp->priv;
959         u32 val;
960
961         spin_lock_bh(&tp->lock);
962
963         if (tg3_readphy(tp, reg, &val))
964                 val = -EIO;
965
966         spin_unlock_bh(&tp->lock);
967
968         return val;
969 }
970
971 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
972 {
973         struct tg3 *tp = bp->priv;
974         u32 ret = 0;
975
976         spin_lock_bh(&tp->lock);
977
978         if (tg3_writephy(tp, reg, val))
979                 ret = -EIO;
980
981         spin_unlock_bh(&tp->lock);
982
983         return ret;
984 }
985
986 static int tg3_mdio_reset(struct mii_bus *bp)
987 {
988         return 0;
989 }
990
991 static void tg3_mdio_config_5785(struct tg3 *tp)
992 {
993         u32 val;
994         struct phy_device *phydev;
995
996         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
997         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
998         case PHY_ID_BCM50610:
999         case PHY_ID_BCM50610M:
1000                 val = MAC_PHYCFG2_50610_LED_MODES;
1001                 break;
1002         case PHY_ID_BCMAC131:
1003                 val = MAC_PHYCFG2_AC131_LED_MODES;
1004                 break;
1005         case PHY_ID_RTL8211C:
1006                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1007                 break;
1008         case PHY_ID_RTL8201E:
1009                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1010                 break;
1011         default:
1012                 return;
1013         }
1014
1015         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1016                 tw32(MAC_PHYCFG2, val);
1017
1018                 val = tr32(MAC_PHYCFG1);
1019                 val &= ~(MAC_PHYCFG1_RGMII_INT |
1020                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1021                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1022                 tw32(MAC_PHYCFG1, val);
1023
1024                 return;
1025         }
1026
1027         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
1028                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1029                        MAC_PHYCFG2_FMODE_MASK_MASK |
1030                        MAC_PHYCFG2_GMODE_MASK_MASK |
1031                        MAC_PHYCFG2_ACT_MASK_MASK   |
1032                        MAC_PHYCFG2_QUAL_MASK_MASK |
1033                        MAC_PHYCFG2_INBAND_ENABLE;
1034
1035         tw32(MAC_PHYCFG2, val);
1036
1037         val = tr32(MAC_PHYCFG1);
1038         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1039                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1040         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1041                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1042                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1043                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1044                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1045         }
1046         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1047                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1048         tw32(MAC_PHYCFG1, val);
1049
1050         val = tr32(MAC_EXT_RGMII_MODE);
1051         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1052                  MAC_RGMII_MODE_RX_QUALITY |
1053                  MAC_RGMII_MODE_RX_ACTIVITY |
1054                  MAC_RGMII_MODE_RX_ENG_DET |
1055                  MAC_RGMII_MODE_TX_ENABLE |
1056                  MAC_RGMII_MODE_TX_LOWPWR |
1057                  MAC_RGMII_MODE_TX_RESET);
1058         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1059                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1060                         val |= MAC_RGMII_MODE_RX_INT_B |
1061                                MAC_RGMII_MODE_RX_QUALITY |
1062                                MAC_RGMII_MODE_RX_ACTIVITY |
1063                                MAC_RGMII_MODE_RX_ENG_DET;
1064                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1065                         val |= MAC_RGMII_MODE_TX_ENABLE |
1066                                MAC_RGMII_MODE_TX_LOWPWR |
1067                                MAC_RGMII_MODE_TX_RESET;
1068         }
1069         tw32(MAC_EXT_RGMII_MODE, val);
1070 }
1071
1072 static void tg3_mdio_start(struct tg3 *tp)
1073 {
1074         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1075         tw32_f(MAC_MI_MODE, tp->mi_mode);
1076         udelay(80);
1077
1078         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1079             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1080                 tg3_mdio_config_5785(tp);
1081 }
1082
1083 static int tg3_mdio_init(struct tg3 *tp)
1084 {
1085         int i;
1086         u32 reg;
1087         struct phy_device *phydev;
1088
1089         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1090             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
1091                 u32 is_serdes;
1092
1093                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1094
1095                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1096                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1097                 else
1098                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1099                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1100                 if (is_serdes)
1101                         tp->phy_addr += 7;
1102         } else
1103                 tp->phy_addr = TG3_PHY_MII_ADDR;
1104
1105         tg3_mdio_start(tp);
1106
1107         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1108             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1109                 return 0;
1110
1111         tp->mdio_bus = mdiobus_alloc();
1112         if (tp->mdio_bus == NULL)
1113                 return -ENOMEM;
1114
1115         tp->mdio_bus->name     = "tg3 mdio bus";
1116         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1117                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1118         tp->mdio_bus->priv     = tp;
1119         tp->mdio_bus->parent   = &tp->pdev->dev;
1120         tp->mdio_bus->read     = &tg3_mdio_read;
1121         tp->mdio_bus->write    = &tg3_mdio_write;
1122         tp->mdio_bus->reset    = &tg3_mdio_reset;
1123         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1124         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1125
1126         for (i = 0; i < PHY_MAX_ADDR; i++)
1127                 tp->mdio_bus->irq[i] = PHY_POLL;
1128
1129         /* The bus registration will look for all the PHYs on the mdio bus.
1130          * Unfortunately, it does not ensure the PHY is powered up before
1131          * accessing the PHY ID registers.  A chip reset is the
1132          * quickest way to bring the device back to an operational state..
1133          */
1134         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1135                 tg3_bmcr_reset(tp);
1136
1137         i = mdiobus_register(tp->mdio_bus);
1138         if (i) {
1139                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1140                 mdiobus_free(tp->mdio_bus);
1141                 return i;
1142         }
1143
1144         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1145
1146         if (!phydev || !phydev->drv) {
1147                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1148                 mdiobus_unregister(tp->mdio_bus);
1149                 mdiobus_free(tp->mdio_bus);
1150                 return -ENODEV;
1151         }
1152
1153         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1154         case PHY_ID_BCM57780:
1155                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1156                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1157                 break;
1158         case PHY_ID_BCM50610:
1159         case PHY_ID_BCM50610M:
1160                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1161                                      PHY_BRCM_RX_REFCLK_UNUSED |
1162                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1163                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1164                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1165                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1166                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1167                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1168                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1169                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1170                 /* fallthru */
1171         case PHY_ID_RTL8211C:
1172                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1173                 break;
1174         case PHY_ID_RTL8201E:
1175         case PHY_ID_BCMAC131:
1176                 phydev->interface = PHY_INTERFACE_MODE_MII;
1177                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1178                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1179                 break;
1180         }
1181
1182         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1183
1184         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1185                 tg3_mdio_config_5785(tp);
1186
1187         return 0;
1188 }
1189
1190 static void tg3_mdio_fini(struct tg3 *tp)
1191 {
1192         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1193                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1194                 mdiobus_unregister(tp->mdio_bus);
1195                 mdiobus_free(tp->mdio_bus);
1196         }
1197 }
1198
1199 /* tp->lock is held. */
1200 static inline void tg3_generate_fw_event(struct tg3 *tp)
1201 {
1202         u32 val;
1203
1204         val = tr32(GRC_RX_CPU_EVENT);
1205         val |= GRC_RX_CPU_DRIVER_EVENT;
1206         tw32_f(GRC_RX_CPU_EVENT, val);
1207
1208         tp->last_event_jiffies = jiffies;
1209 }
1210
1211 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1212
1213 /* tp->lock is held. */
1214 static void tg3_wait_for_event_ack(struct tg3 *tp)
1215 {
1216         int i;
1217         unsigned int delay_cnt;
1218         long time_remain;
1219
1220         /* If enough time has passed, no wait is necessary. */
1221         time_remain = (long)(tp->last_event_jiffies + 1 +
1222                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1223                       (long)jiffies;
1224         if (time_remain < 0)
1225                 return;
1226
1227         /* Check if we can shorten the wait time. */
1228         delay_cnt = jiffies_to_usecs(time_remain);
1229         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1230                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1231         delay_cnt = (delay_cnt >> 3) + 1;
1232
1233         for (i = 0; i < delay_cnt; i++) {
1234                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1235                         break;
1236                 udelay(8);
1237         }
1238 }
1239
1240 /* tp->lock is held. */
1241 static void tg3_ump_link_report(struct tg3 *tp)
1242 {
1243         u32 reg;
1244         u32 val;
1245
1246         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1247             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1248                 return;
1249
1250         tg3_wait_for_event_ack(tp);
1251
1252         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1253
1254         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1255
1256         val = 0;
1257         if (!tg3_readphy(tp, MII_BMCR, &reg))
1258                 val = reg << 16;
1259         if (!tg3_readphy(tp, MII_BMSR, &reg))
1260                 val |= (reg & 0xffff);
1261         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1262
1263         val = 0;
1264         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1265                 val = reg << 16;
1266         if (!tg3_readphy(tp, MII_LPA, &reg))
1267                 val |= (reg & 0xffff);
1268         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1269
1270         val = 0;
1271         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1272                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1273                         val = reg << 16;
1274                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1275                         val |= (reg & 0xffff);
1276         }
1277         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1278
1279         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1280                 val = reg << 16;
1281         else
1282                 val = 0;
1283         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1284
1285         tg3_generate_fw_event(tp);
1286 }
1287
1288 static void tg3_link_report(struct tg3 *tp)
1289 {
1290         if (!netif_carrier_ok(tp->dev)) {
1291                 netif_info(tp, link, tp->dev, "Link is down\n");
1292                 tg3_ump_link_report(tp);
1293         } else if (netif_msg_link(tp)) {
1294                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1295                             (tp->link_config.active_speed == SPEED_1000 ?
1296                              1000 :
1297                              (tp->link_config.active_speed == SPEED_100 ?
1298                               100 : 10)),
1299                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1300                              "full" : "half"));
1301
1302                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1303                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1304                             "on" : "off",
1305                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1306                             "on" : "off");
1307                 tg3_ump_link_report(tp);
1308         }
1309 }
1310
1311 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1312 {
1313         u16 miireg;
1314
1315         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1316                 miireg = ADVERTISE_PAUSE_CAP;
1317         else if (flow_ctrl & FLOW_CTRL_TX)
1318                 miireg = ADVERTISE_PAUSE_ASYM;
1319         else if (flow_ctrl & FLOW_CTRL_RX)
1320                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1321         else
1322                 miireg = 0;
1323
1324         return miireg;
1325 }
1326
1327 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1328 {
1329         u16 miireg;
1330
1331         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1332                 miireg = ADVERTISE_1000XPAUSE;
1333         else if (flow_ctrl & FLOW_CTRL_TX)
1334                 miireg = ADVERTISE_1000XPSE_ASYM;
1335         else if (flow_ctrl & FLOW_CTRL_RX)
1336                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1337         else
1338                 miireg = 0;
1339
1340         return miireg;
1341 }
1342
1343 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1344 {
1345         u8 cap = 0;
1346
1347         if (lcladv & ADVERTISE_1000XPAUSE) {
1348                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1349                         if (rmtadv & LPA_1000XPAUSE)
1350                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1351                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1352                                 cap = FLOW_CTRL_RX;
1353                 } else {
1354                         if (rmtadv & LPA_1000XPAUSE)
1355                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1356                 }
1357         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1358                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1359                         cap = FLOW_CTRL_TX;
1360         }
1361
1362         return cap;
1363 }
1364
1365 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1366 {
1367         u8 autoneg;
1368         u8 flowctrl = 0;
1369         u32 old_rx_mode = tp->rx_mode;
1370         u32 old_tx_mode = tp->tx_mode;
1371
1372         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1373                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1374         else
1375                 autoneg = tp->link_config.autoneg;
1376
1377         if (autoneg == AUTONEG_ENABLE &&
1378             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1379                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1380                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1381                 else
1382                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1383         } else
1384                 flowctrl = tp->link_config.flowctrl;
1385
1386         tp->link_config.active_flowctrl = flowctrl;
1387
1388         if (flowctrl & FLOW_CTRL_RX)
1389                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1390         else
1391                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1392
1393         if (old_rx_mode != tp->rx_mode)
1394                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1395
1396         if (flowctrl & FLOW_CTRL_TX)
1397                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1398         else
1399                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1400
1401         if (old_tx_mode != tp->tx_mode)
1402                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1403 }
1404
1405 static void tg3_adjust_link(struct net_device *dev)
1406 {
1407         u8 oldflowctrl, linkmesg = 0;
1408         u32 mac_mode, lcl_adv, rmt_adv;
1409         struct tg3 *tp = netdev_priv(dev);
1410         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1411
1412         spin_lock_bh(&tp->lock);
1413
1414         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1415                                     MAC_MODE_HALF_DUPLEX);
1416
1417         oldflowctrl = tp->link_config.active_flowctrl;
1418
1419         if (phydev->link) {
1420                 lcl_adv = 0;
1421                 rmt_adv = 0;
1422
1423                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1424                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1425                 else if (phydev->speed == SPEED_1000 ||
1426                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1427                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1428                 else
1429                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1430
1431                 if (phydev->duplex == DUPLEX_HALF)
1432                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1433                 else {
1434                         lcl_adv = tg3_advert_flowctrl_1000T(
1435                                   tp->link_config.flowctrl);
1436
1437                         if (phydev->pause)
1438                                 rmt_adv = LPA_PAUSE_CAP;
1439                         if (phydev->asym_pause)
1440                                 rmt_adv |= LPA_PAUSE_ASYM;
1441                 }
1442
1443                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1444         } else
1445                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1446
1447         if (mac_mode != tp->mac_mode) {
1448                 tp->mac_mode = mac_mode;
1449                 tw32_f(MAC_MODE, tp->mac_mode);
1450                 udelay(40);
1451         }
1452
1453         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1454                 if (phydev->speed == SPEED_10)
1455                         tw32(MAC_MI_STAT,
1456                              MAC_MI_STAT_10MBPS_MODE |
1457                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1458                 else
1459                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1460         }
1461
1462         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1463                 tw32(MAC_TX_LENGTHS,
1464                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1465                       (6 << TX_LENGTHS_IPG_SHIFT) |
1466                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1467         else
1468                 tw32(MAC_TX_LENGTHS,
1469                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1470                       (6 << TX_LENGTHS_IPG_SHIFT) |
1471                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1472
1473         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1474             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1475             phydev->speed != tp->link_config.active_speed ||
1476             phydev->duplex != tp->link_config.active_duplex ||
1477             oldflowctrl != tp->link_config.active_flowctrl)
1478                 linkmesg = 1;
1479
1480         tp->link_config.active_speed = phydev->speed;
1481         tp->link_config.active_duplex = phydev->duplex;
1482
1483         spin_unlock_bh(&tp->lock);
1484
1485         if (linkmesg)
1486                 tg3_link_report(tp);
1487 }
1488
1489 static int tg3_phy_init(struct tg3 *tp)
1490 {
1491         struct phy_device *phydev;
1492
1493         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1494                 return 0;
1495
1496         /* Bring the PHY back to a known state. */
1497         tg3_bmcr_reset(tp);
1498
1499         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1500
1501         /* Attach the MAC to the PHY. */
1502         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1503                              phydev->dev_flags, phydev->interface);
1504         if (IS_ERR(phydev)) {
1505                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1506                 return PTR_ERR(phydev);
1507         }
1508
1509         /* Mask with MAC supported features. */
1510         switch (phydev->interface) {
1511         case PHY_INTERFACE_MODE_GMII:
1512         case PHY_INTERFACE_MODE_RGMII:
1513                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1514                         phydev->supported &= (PHY_GBIT_FEATURES |
1515                                               SUPPORTED_Pause |
1516                                               SUPPORTED_Asym_Pause);
1517                         break;
1518                 }
1519                 /* fallthru */
1520         case PHY_INTERFACE_MODE_MII:
1521                 phydev->supported &= (PHY_BASIC_FEATURES |
1522                                       SUPPORTED_Pause |
1523                                       SUPPORTED_Asym_Pause);
1524                 break;
1525         default:
1526                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1527                 return -EINVAL;
1528         }
1529
1530         tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1531
1532         phydev->advertising = phydev->supported;
1533
1534         return 0;
1535 }
1536
1537 static void tg3_phy_start(struct tg3 *tp)
1538 {
1539         struct phy_device *phydev;
1540
1541         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1542                 return;
1543
1544         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1545
1546         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1547                 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1548                 phydev->speed = tp->link_config.orig_speed;
1549                 phydev->duplex = tp->link_config.orig_duplex;
1550                 phydev->autoneg = tp->link_config.orig_autoneg;
1551                 phydev->advertising = tp->link_config.orig_advertising;
1552         }
1553
1554         phy_start(phydev);
1555
1556         phy_start_aneg(phydev);
1557 }
1558
1559 static void tg3_phy_stop(struct tg3 *tp)
1560 {
1561         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1562                 return;
1563
1564         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1565 }
1566
1567 static void tg3_phy_fini(struct tg3 *tp)
1568 {
1569         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1570                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1571                 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1572         }
1573 }
1574
1575 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1576 {
1577         int err;
1578
1579         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1580         if (!err)
1581                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1582
1583         return err;
1584 }
1585
1586 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1587 {
1588         u32 phytest;
1589
1590         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1591                 u32 phy;
1592
1593                 tg3_writephy(tp, MII_TG3_FET_TEST,
1594                              phytest | MII_TG3_FET_SHADOW_EN);
1595                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1596                         if (enable)
1597                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1598                         else
1599                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1600                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1601                 }
1602                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1603         }
1604 }
1605
1606 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1607 {
1608         u32 reg;
1609
1610         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1611             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1612               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1613              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1614                 return;
1615
1616         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1617                 tg3_phy_fet_toggle_apd(tp, enable);
1618                 return;
1619         }
1620
1621         reg = MII_TG3_MISC_SHDW_WREN |
1622               MII_TG3_MISC_SHDW_SCR5_SEL |
1623               MII_TG3_MISC_SHDW_SCR5_LPED |
1624               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1625               MII_TG3_MISC_SHDW_SCR5_SDTL |
1626               MII_TG3_MISC_SHDW_SCR5_C125OE;
1627         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1628                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1629
1630         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1631
1632
1633         reg = MII_TG3_MISC_SHDW_WREN |
1634               MII_TG3_MISC_SHDW_APD_SEL |
1635               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1636         if (enable)
1637                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1638
1639         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1640 }
1641
1642 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1643 {
1644         u32 phy;
1645
1646         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1647             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1648                 return;
1649
1650         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1651                 u32 ephy;
1652
1653                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1654                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1655
1656                         tg3_writephy(tp, MII_TG3_FET_TEST,
1657                                      ephy | MII_TG3_FET_SHADOW_EN);
1658                         if (!tg3_readphy(tp, reg, &phy)) {
1659                                 if (enable)
1660                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1661                                 else
1662                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1663                                 tg3_writephy(tp, reg, phy);
1664                         }
1665                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1666                 }
1667         } else {
1668                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1669                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1670                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1671                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1672                         if (enable)
1673                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1674                         else
1675                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1676                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1677                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1678                 }
1679         }
1680 }
1681
1682 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1683 {
1684         u32 val;
1685
1686         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1687                 return;
1688
1689         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1690             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1691                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1692                              (val | (1 << 15) | (1 << 4)));
1693 }
1694
1695 static void tg3_phy_apply_otp(struct tg3 *tp)
1696 {
1697         u32 otp, phy;
1698
1699         if (!tp->phy_otp)
1700                 return;
1701
1702         otp = tp->phy_otp;
1703
1704         /* Enable SM_DSP clock and tx 6dB coding. */
1705         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1706               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1707               MII_TG3_AUXCTL_ACTL_TX_6DB;
1708         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1709
1710         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1711         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1712         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1713
1714         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1715               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1716         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1717
1718         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1719         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1720         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1721
1722         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1723         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1724
1725         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1726         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1727
1728         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1729               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1730         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1731
1732         /* Turn off SM_DSP clock. */
1733         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1734               MII_TG3_AUXCTL_ACTL_TX_6DB;
1735         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1736 }
1737
1738 static int tg3_wait_macro_done(struct tg3 *tp)
1739 {
1740         int limit = 100;
1741
1742         while (limit--) {
1743                 u32 tmp32;
1744
1745                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1746                         if ((tmp32 & 0x1000) == 0)
1747                                 break;
1748                 }
1749         }
1750         if (limit < 0)
1751                 return -EBUSY;
1752
1753         return 0;
1754 }
1755
1756 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1757 {
1758         static const u32 test_pat[4][6] = {
1759         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1760         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1761         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1762         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1763         };
1764         int chan;
1765
1766         for (chan = 0; chan < 4; chan++) {
1767                 int i;
1768
1769                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1770                              (chan * 0x2000) | 0x0200);
1771                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1772
1773                 for (i = 0; i < 6; i++)
1774                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1775                                      test_pat[chan][i]);
1776
1777                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1778                 if (tg3_wait_macro_done(tp)) {
1779                         *resetp = 1;
1780                         return -EBUSY;
1781                 }
1782
1783                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1784                              (chan * 0x2000) | 0x0200);
1785                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1786                 if (tg3_wait_macro_done(tp)) {
1787                         *resetp = 1;
1788                         return -EBUSY;
1789                 }
1790
1791                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1792                 if (tg3_wait_macro_done(tp)) {
1793                         *resetp = 1;
1794                         return -EBUSY;
1795                 }
1796
1797                 for (i = 0; i < 6; i += 2) {
1798                         u32 low, high;
1799
1800                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1801                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1802                             tg3_wait_macro_done(tp)) {
1803                                 *resetp = 1;
1804                                 return -EBUSY;
1805                         }
1806                         low &= 0x7fff;
1807                         high &= 0x000f;
1808                         if (low != test_pat[chan][i] ||
1809                             high != test_pat[chan][i+1]) {
1810                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1811                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1812                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1813
1814                                 return -EBUSY;
1815                         }
1816                 }
1817         }
1818
1819         return 0;
1820 }
1821
1822 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1823 {
1824         int chan;
1825
1826         for (chan = 0; chan < 4; chan++) {
1827                 int i;
1828
1829                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1830                              (chan * 0x2000) | 0x0200);
1831                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1832                 for (i = 0; i < 6; i++)
1833                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1834                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1835                 if (tg3_wait_macro_done(tp))
1836                         return -EBUSY;
1837         }
1838
1839         return 0;
1840 }
1841
1842 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1843 {
1844         u32 reg32, phy9_orig;
1845         int retries, do_phy_reset, err;
1846
1847         retries = 10;
1848         do_phy_reset = 1;
1849         do {
1850                 if (do_phy_reset) {
1851                         err = tg3_bmcr_reset(tp);
1852                         if (err)
1853                                 return err;
1854                         do_phy_reset = 0;
1855                 }
1856
1857                 /* Disable transmitter and interrupt.  */
1858                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1859                         continue;
1860
1861                 reg32 |= 0x3000;
1862                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1863
1864                 /* Set full-duplex, 1000 mbps.  */
1865                 tg3_writephy(tp, MII_BMCR,
1866                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1867
1868                 /* Set to master mode.  */
1869                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1870                         continue;
1871
1872                 tg3_writephy(tp, MII_TG3_CTRL,
1873                              (MII_TG3_CTRL_AS_MASTER |
1874                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1875
1876                 /* Enable SM_DSP_CLOCK and 6dB.  */
1877                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1878
1879                 /* Block the PHY control access.  */
1880                 tg3_phydsp_write(tp, 0x8005, 0x0800);
1881
1882                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1883                 if (!err)
1884                         break;
1885         } while (--retries);
1886
1887         err = tg3_phy_reset_chanpat(tp);
1888         if (err)
1889                 return err;
1890
1891         tg3_phydsp_write(tp, 0x8005, 0x0000);
1892
1893         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1894         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1895
1896         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1897             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1898                 /* Set Extended packet length bit for jumbo frames */
1899                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1900         } else {
1901                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1902         }
1903
1904         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1905
1906         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1907                 reg32 &= ~0x3000;
1908                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1909         } else if (!err)
1910                 err = -EBUSY;
1911
1912         return err;
1913 }
1914
1915 /* This will reset the tigon3 PHY if there is no valid
1916  * link unless the FORCE argument is non-zero.
1917  */
1918 static int tg3_phy_reset(struct tg3 *tp)
1919 {
1920         u32 val, cpmuctrl;
1921         int err;
1922
1923         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1924                 val = tr32(GRC_MISC_CFG);
1925                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1926                 udelay(40);
1927         }
1928         err  = tg3_readphy(tp, MII_BMSR, &val);
1929         err |= tg3_readphy(tp, MII_BMSR, &val);
1930         if (err != 0)
1931                 return -EBUSY;
1932
1933         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1934                 netif_carrier_off(tp->dev);
1935                 tg3_link_report(tp);
1936         }
1937
1938         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1939             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1940             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1941                 err = tg3_phy_reset_5703_4_5(tp);
1942                 if (err)
1943                         return err;
1944                 goto out;
1945         }
1946
1947         cpmuctrl = 0;
1948         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1949             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1950                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1951                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1952                         tw32(TG3_CPMU_CTRL,
1953                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1954         }
1955
1956         err = tg3_bmcr_reset(tp);
1957         if (err)
1958                 return err;
1959
1960         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1961                 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1962                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
1963
1964                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1965         }
1966
1967         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1968             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1969                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1970                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1971                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1972                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1973                         udelay(40);
1974                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1975                 }
1976         }
1977
1978         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1979              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1980             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
1981                 return 0;
1982
1983         tg3_phy_apply_otp(tp);
1984
1985         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
1986                 tg3_phy_toggle_apd(tp, true);
1987         else
1988                 tg3_phy_toggle_apd(tp, false);
1989
1990 out:
1991         if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
1992                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1993                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
1994                 tg3_phydsp_write(tp, 0x000a, 0x0323);
1995                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1996         }
1997         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
1998                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
1999                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2000         }
2001         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2002                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2003                 tg3_phydsp_write(tp, 0x000a, 0x310b);
2004                 tg3_phydsp_write(tp, 0x201f, 0x9506);
2005                 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2006                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2007         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2008                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2009                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2010                 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2011                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2012                         tg3_writephy(tp, MII_TG3_TEST1,
2013                                      MII_TG3_TEST1_TRIM_EN | 0x4);
2014                 } else
2015                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2016                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2017         }
2018         /* Set Extended packet length bit (bit 14) on all chips that */
2019         /* support jumbo frames */
2020         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2021                 /* Cannot do read-modify-write on 5401 */
2022                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2023         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2024                 /* Set bit 14 with read-modify-write to preserve other bits */
2025                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2026                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
2027                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000);
2028         }
2029
2030         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2031          * jumbo frames transmission.
2032          */
2033         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2034                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2035                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2036                                      val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2037         }
2038
2039         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2040                 /* adjust output voltage */
2041                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2042         }
2043
2044         tg3_phy_toggle_automdix(tp, 1);
2045         tg3_phy_set_wirespeed(tp);
2046         return 0;
2047 }
2048
2049 static void tg3_frob_aux_power(struct tg3 *tp)
2050 {
2051         struct tg3 *tp_peer = tp;
2052
2053         /* The GPIOs do something completely different on 57765. */
2054         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2055             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2056             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2057                 return;
2058
2059         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2060             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2061             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2062                 struct net_device *dev_peer;
2063
2064                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2065                 /* remove_one() may have been run on the peer. */
2066                 if (!dev_peer)
2067                         tp_peer = tp;
2068                 else
2069                         tp_peer = netdev_priv(dev_peer);
2070         }
2071
2072         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2073             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2074             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2075             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2076                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2077                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2078                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2079                                     (GRC_LCLCTRL_GPIO_OE0 |
2080                                      GRC_LCLCTRL_GPIO_OE1 |
2081                                      GRC_LCLCTRL_GPIO_OE2 |
2082                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2083                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2084                                     100);
2085                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2086                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2087                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2088                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2089                                              GRC_LCLCTRL_GPIO_OE1 |
2090                                              GRC_LCLCTRL_GPIO_OE2 |
2091                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2092                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2093                                              tp->grc_local_ctrl;
2094                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2095
2096                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2097                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2098
2099                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2100                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2101                 } else {
2102                         u32 no_gpio2;
2103                         u32 grc_local_ctrl = 0;
2104
2105                         if (tp_peer != tp &&
2106                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2107                                 return;
2108
2109                         /* Workaround to prevent overdrawing Amps. */
2110                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2111                             ASIC_REV_5714) {
2112                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2113                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2114                                             grc_local_ctrl, 100);
2115                         }
2116
2117                         /* On 5753 and variants, GPIO2 cannot be used. */
2118                         no_gpio2 = tp->nic_sram_data_cfg &
2119                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2120
2121                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2122                                          GRC_LCLCTRL_GPIO_OE1 |
2123                                          GRC_LCLCTRL_GPIO_OE2 |
2124                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2125                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2126                         if (no_gpio2) {
2127                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2128                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2129                         }
2130                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2131                                                     grc_local_ctrl, 100);
2132
2133                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2134
2135                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2136                                                     grc_local_ctrl, 100);
2137
2138                         if (!no_gpio2) {
2139                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2140                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2141                                             grc_local_ctrl, 100);
2142                         }
2143                 }
2144         } else {
2145                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2146                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2147                         if (tp_peer != tp &&
2148                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2149                                 return;
2150
2151                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2152                                     (GRC_LCLCTRL_GPIO_OE1 |
2153                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2154
2155                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2156                                     GRC_LCLCTRL_GPIO_OE1, 100);
2157
2158                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2159                                     (GRC_LCLCTRL_GPIO_OE1 |
2160                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2161                 }
2162         }
2163 }
2164
2165 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2166 {
2167         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2168                 return 1;
2169         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2170                 if (speed != SPEED_10)
2171                         return 1;
2172         } else if (speed == SPEED_10)
2173                 return 1;
2174
2175         return 0;
2176 }
2177
2178 static int tg3_setup_phy(struct tg3 *, int);
2179
2180 #define RESET_KIND_SHUTDOWN     0
2181 #define RESET_KIND_INIT         1
2182 #define RESET_KIND_SUSPEND      2
2183
2184 static void tg3_write_sig_post_reset(struct tg3 *, int);
2185 static int tg3_halt_cpu(struct tg3 *, u32);
2186
2187 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2188 {
2189         u32 val;
2190
2191         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2192                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2193                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2194                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2195
2196                         sg_dig_ctrl |=
2197                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2198                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2199                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2200                 }
2201                 return;
2202         }
2203
2204         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2205                 tg3_bmcr_reset(tp);
2206                 val = tr32(GRC_MISC_CFG);
2207                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2208                 udelay(40);
2209                 return;
2210         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2211                 u32 phytest;
2212                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2213                         u32 phy;
2214
2215                         tg3_writephy(tp, MII_ADVERTISE, 0);
2216                         tg3_writephy(tp, MII_BMCR,
2217                                      BMCR_ANENABLE | BMCR_ANRESTART);
2218
2219                         tg3_writephy(tp, MII_TG3_FET_TEST,
2220                                      phytest | MII_TG3_FET_SHADOW_EN);
2221                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2222                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2223                                 tg3_writephy(tp,
2224                                              MII_TG3_FET_SHDW_AUXMODE4,
2225                                              phy);
2226                         }
2227                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2228                 }
2229                 return;
2230         } else if (do_low_power) {
2231                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2232                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2233
2234                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2235                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2236                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2237                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2238                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2239         }
2240
2241         /* The PHY should not be powered down on some chips because
2242          * of bugs.
2243          */
2244         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2245             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2246             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2247              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2248                 return;
2249
2250         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2251             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2252                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2253                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2254                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2255                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2256         }
2257
2258         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2259 }
2260
2261 /* tp->lock is held. */
2262 static int tg3_nvram_lock(struct tg3 *tp)
2263 {
2264         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2265                 int i;
2266
2267                 if (tp->nvram_lock_cnt == 0) {
2268                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2269                         for (i = 0; i < 8000; i++) {
2270                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2271                                         break;
2272                                 udelay(20);
2273                         }
2274                         if (i == 8000) {
2275                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2276                                 return -ENODEV;
2277                         }
2278                 }
2279                 tp->nvram_lock_cnt++;
2280         }
2281         return 0;
2282 }
2283
2284 /* tp->lock is held. */
2285 static void tg3_nvram_unlock(struct tg3 *tp)
2286 {
2287         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2288                 if (tp->nvram_lock_cnt > 0)
2289                         tp->nvram_lock_cnt--;
2290                 if (tp->nvram_lock_cnt == 0)
2291                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2292         }
2293 }
2294
2295 /* tp->lock is held. */
2296 static void tg3_enable_nvram_access(struct tg3 *tp)
2297 {
2298         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2299             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2300                 u32 nvaccess = tr32(NVRAM_ACCESS);
2301
2302                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2303         }
2304 }
2305
2306 /* tp->lock is held. */
2307 static void tg3_disable_nvram_access(struct tg3 *tp)
2308 {
2309         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2310             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2311                 u32 nvaccess = tr32(NVRAM_ACCESS);
2312
2313                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2314         }
2315 }
2316
2317 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2318                                         u32 offset, u32 *val)
2319 {
2320         u32 tmp;
2321         int i;
2322
2323         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2324                 return -EINVAL;
2325
2326         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2327                                         EEPROM_ADDR_DEVID_MASK |
2328                                         EEPROM_ADDR_READ);
2329         tw32(GRC_EEPROM_ADDR,
2330              tmp |
2331              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2332              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2333               EEPROM_ADDR_ADDR_MASK) |
2334              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2335
2336         for (i = 0; i < 1000; i++) {
2337                 tmp = tr32(GRC_EEPROM_ADDR);
2338
2339                 if (tmp & EEPROM_ADDR_COMPLETE)
2340                         break;
2341                 msleep(1);
2342         }
2343         if (!(tmp & EEPROM_ADDR_COMPLETE))
2344                 return -EBUSY;
2345
2346         tmp = tr32(GRC_EEPROM_DATA);
2347
2348         /*
2349          * The data will always be opposite the native endian
2350          * format.  Perform a blind byteswap to compensate.
2351          */
2352         *val = swab32(tmp);
2353
2354         return 0;
2355 }
2356
2357 #define NVRAM_CMD_TIMEOUT 10000
2358
2359 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2360 {
2361         int i;
2362
2363         tw32(NVRAM_CMD, nvram_cmd);
2364         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2365                 udelay(10);
2366                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2367                         udelay(10);
2368                         break;
2369                 }
2370         }
2371
2372         if (i == NVRAM_CMD_TIMEOUT)
2373                 return -EBUSY;
2374
2375         return 0;
2376 }
2377
2378 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2379 {
2380         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2381             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2382             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2383            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2384             (tp->nvram_jedecnum == JEDEC_ATMEL))
2385
2386                 addr = ((addr / tp->nvram_pagesize) <<
2387                         ATMEL_AT45DB0X1B_PAGE_POS) +
2388                        (addr % tp->nvram_pagesize);
2389
2390         return addr;
2391 }
2392
2393 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2394 {
2395         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2396             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2397             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2398            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2399             (tp->nvram_jedecnum == JEDEC_ATMEL))
2400
2401                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2402                         tp->nvram_pagesize) +
2403                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2404
2405         return addr;
2406 }
2407
2408 /* NOTE: Data read in from NVRAM is byteswapped according to
2409  * the byteswapping settings for all other register accesses.
2410  * tg3 devices are BE devices, so on a BE machine, the data
2411  * returned will be exactly as it is seen in NVRAM.  On a LE
2412  * machine, the 32-bit value will be byteswapped.
2413  */
2414 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2415 {
2416         int ret;
2417
2418         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2419                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2420
2421         offset = tg3_nvram_phys_addr(tp, offset);
2422
2423         if (offset > NVRAM_ADDR_MSK)
2424                 return -EINVAL;
2425
2426         ret = tg3_nvram_lock(tp);
2427         if (ret)
2428                 return ret;
2429
2430         tg3_enable_nvram_access(tp);
2431
2432         tw32(NVRAM_ADDR, offset);
2433         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2434                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2435
2436         if (ret == 0)
2437                 *val = tr32(NVRAM_RDDATA);
2438
2439         tg3_disable_nvram_access(tp);
2440
2441         tg3_nvram_unlock(tp);
2442
2443         return ret;
2444 }
2445
2446 /* Ensures NVRAM data is in bytestream format. */
2447 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2448 {
2449         u32 v;
2450         int res = tg3_nvram_read(tp, offset, &v);
2451         if (!res)
2452                 *val = cpu_to_be32(v);
2453         return res;
2454 }
2455
2456 /* tp->lock is held. */
2457 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2458 {
2459         u32 addr_high, addr_low;
2460         int i;
2461
2462         addr_high = ((tp->dev->dev_addr[0] << 8) |
2463                      tp->dev->dev_addr[1]);
2464         addr_low = ((tp->dev->dev_addr[2] << 24) |
2465                     (tp->dev->dev_addr[3] << 16) |
2466                     (tp->dev->dev_addr[4] <<  8) |
2467                     (tp->dev->dev_addr[5] <<  0));
2468         for (i = 0; i < 4; i++) {
2469                 if (i == 1 && skip_mac_1)
2470                         continue;
2471                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2472                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2473         }
2474
2475         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2476             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2477                 for (i = 0; i < 12; i++) {
2478                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2479                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2480                 }
2481         }
2482
2483         addr_high = (tp->dev->dev_addr[0] +
2484                      tp->dev->dev_addr[1] +
2485                      tp->dev->dev_addr[2] +
2486                      tp->dev->dev_addr[3] +
2487                      tp->dev->dev_addr[4] +
2488                      tp->dev->dev_addr[5]) &
2489                 TX_BACKOFF_SEED_MASK;
2490         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2491 }
2492
2493 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2494 {
2495         u32 misc_host_ctrl;
2496         bool device_should_wake, do_low_power;
2497
2498         /* Make sure register accesses (indirect or otherwise)
2499          * will function correctly.
2500          */
2501         pci_write_config_dword(tp->pdev,
2502                                TG3PCI_MISC_HOST_CTRL,
2503                                tp->misc_host_ctrl);
2504
2505         switch (state) {
2506         case PCI_D0:
2507                 pci_enable_wake(tp->pdev, state, false);
2508                 pci_set_power_state(tp->pdev, PCI_D0);
2509
2510                 /* Switch out of Vaux if it is a NIC */
2511                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2512                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2513
2514                 return 0;
2515
2516         case PCI_D1:
2517         case PCI_D2:
2518         case PCI_D3hot:
2519                 break;
2520
2521         default:
2522                 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2523                            state);
2524                 return -EINVAL;
2525         }
2526
2527         /* Restore the CLKREQ setting. */
2528         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2529                 u16 lnkctl;
2530
2531                 pci_read_config_word(tp->pdev,
2532                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2533                                      &lnkctl);
2534                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2535                 pci_write_config_word(tp->pdev,
2536                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2537                                       lnkctl);
2538         }
2539
2540         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2541         tw32(TG3PCI_MISC_HOST_CTRL,
2542              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2543
2544         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2545                              device_may_wakeup(&tp->pdev->dev) &&
2546                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2547
2548         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2549                 do_low_power = false;
2550                 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2551                     !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2552                         struct phy_device *phydev;
2553                         u32 phyid, advertising;
2554
2555                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2556
2557                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2558
2559                         tp->link_config.orig_speed = phydev->speed;
2560                         tp->link_config.orig_duplex = phydev->duplex;
2561                         tp->link_config.orig_autoneg = phydev->autoneg;
2562                         tp->link_config.orig_advertising = phydev->advertising;
2563
2564                         advertising = ADVERTISED_TP |
2565                                       ADVERTISED_Pause |
2566                                       ADVERTISED_Autoneg |
2567                                       ADVERTISED_10baseT_Half;
2568
2569                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2570                             device_should_wake) {
2571                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2572                                         advertising |=
2573                                                 ADVERTISED_100baseT_Half |
2574                                                 ADVERTISED_100baseT_Full |
2575                                                 ADVERTISED_10baseT_Full;
2576                                 else
2577                                         advertising |= ADVERTISED_10baseT_Full;
2578                         }
2579
2580                         phydev->advertising = advertising;
2581
2582                         phy_start_aneg(phydev);
2583
2584                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2585                         if (phyid != PHY_ID_BCMAC131) {
2586                                 phyid &= PHY_BCM_OUI_MASK;
2587                                 if (phyid == PHY_BCM_OUI_1 ||
2588                                     phyid == PHY_BCM_OUI_2 ||
2589                                     phyid == PHY_BCM_OUI_3)
2590                                         do_low_power = true;
2591                         }
2592                 }
2593         } else {
2594                 do_low_power = true;
2595
2596                 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2597                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2598                         tp->link_config.orig_speed = tp->link_config.speed;
2599                         tp->link_config.orig_duplex = tp->link_config.duplex;
2600                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2601                 }
2602
2603                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2604                         tp->link_config.speed = SPEED_10;
2605                         tp->link_config.duplex = DUPLEX_HALF;
2606                         tp->link_config.autoneg = AUTONEG_ENABLE;
2607                         tg3_setup_phy(tp, 0);
2608                 }
2609         }
2610
2611         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2612                 u32 val;
2613
2614                 val = tr32(GRC_VCPU_EXT_CTRL);
2615                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2616         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2617                 int i;
2618                 u32 val;
2619
2620                 for (i = 0; i < 200; i++) {
2621                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2622                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2623                                 break;
2624                         msleep(1);
2625                 }
2626         }
2627         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2628                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2629                                                      WOL_DRV_STATE_SHUTDOWN |
2630                                                      WOL_DRV_WOL |
2631                                                      WOL_SET_MAGIC_PKT);
2632
2633         if (device_should_wake) {
2634                 u32 mac_mode;
2635
2636                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2637                         if (do_low_power) {
2638                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2639                                 udelay(40);
2640                         }
2641
2642                         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2643                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2644                         else
2645                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2646
2647                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2648                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2649                             ASIC_REV_5700) {
2650                                 u32 speed = (tp->tg3_flags &
2651                                              TG3_FLAG_WOL_SPEED_100MB) ?
2652                                              SPEED_100 : SPEED_10;
2653                                 if (tg3_5700_link_polarity(tp, speed))
2654                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2655                                 else
2656                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2657                         }
2658                 } else {
2659                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2660                 }
2661
2662                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2663                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2664
2665                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2666                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2667                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2668                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2669                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2670                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2671
2672                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2673                         mac_mode |= tp->mac_mode &
2674                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2675                         if (mac_mode & MAC_MODE_APE_TX_EN)
2676                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2677                 }
2678
2679                 tw32_f(MAC_MODE, mac_mode);
2680                 udelay(100);
2681
2682                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2683                 udelay(10);
2684         }
2685
2686         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2687             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2688              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2689                 u32 base_val;
2690
2691                 base_val = tp->pci_clock_ctrl;
2692                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2693                              CLOCK_CTRL_TXCLK_DISABLE);
2694
2695                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2696                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2697         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2698                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2699                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2700                 /* do nothing */
2701         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2702                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2703                 u32 newbits1, newbits2;
2704
2705                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2706                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2707                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2708                                     CLOCK_CTRL_TXCLK_DISABLE |
2709                                     CLOCK_CTRL_ALTCLK);
2710                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2711                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2712                         newbits1 = CLOCK_CTRL_625_CORE;
2713                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2714                 } else {
2715                         newbits1 = CLOCK_CTRL_ALTCLK;
2716                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2717                 }
2718
2719                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2720                             40);
2721
2722                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2723                             40);
2724
2725                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2726                         u32 newbits3;
2727
2728                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2729                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2730                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2731                                             CLOCK_CTRL_TXCLK_DISABLE |
2732                                             CLOCK_CTRL_44MHZ_CORE);
2733                         } else {
2734                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2735                         }
2736
2737                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2738                                     tp->pci_clock_ctrl | newbits3, 40);
2739                 }
2740         }
2741
2742         if (!(device_should_wake) &&
2743             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2744                 tg3_power_down_phy(tp, do_low_power);
2745
2746         tg3_frob_aux_power(tp);
2747
2748         /* Workaround for unstable PLL clock */
2749         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2750             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2751                 u32 val = tr32(0x7d00);
2752
2753                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2754                 tw32(0x7d00, val);
2755                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2756                         int err;
2757
2758                         err = tg3_nvram_lock(tp);
2759                         tg3_halt_cpu(tp, RX_CPU_BASE);
2760                         if (!err)
2761                                 tg3_nvram_unlock(tp);
2762                 }
2763         }
2764
2765         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2766
2767         if (device_should_wake)
2768                 pci_enable_wake(tp->pdev, state, true);
2769
2770         /* Finally, set the new power state. */
2771         pci_set_power_state(tp->pdev, state);
2772
2773         return 0;
2774 }
2775
2776 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2777 {
2778         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2779         case MII_TG3_AUX_STAT_10HALF:
2780                 *speed = SPEED_10;
2781                 *duplex = DUPLEX_HALF;
2782                 break;
2783
2784         case MII_TG3_AUX_STAT_10FULL:
2785                 *speed = SPEED_10;
2786                 *duplex = DUPLEX_FULL;
2787                 break;
2788
2789         case MII_TG3_AUX_STAT_100HALF:
2790                 *speed = SPEED_100;
2791                 *duplex = DUPLEX_HALF;
2792                 break;
2793
2794         case MII_TG3_AUX_STAT_100FULL:
2795                 *speed = SPEED_100;
2796                 *duplex = DUPLEX_FULL;
2797                 break;
2798
2799         case MII_TG3_AUX_STAT_1000HALF:
2800                 *speed = SPEED_1000;
2801                 *duplex = DUPLEX_HALF;
2802                 break;
2803
2804         case MII_TG3_AUX_STAT_1000FULL:
2805                 *speed = SPEED_1000;
2806                 *duplex = DUPLEX_FULL;
2807                 break;
2808
2809         default:
2810                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2811                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2812                                  SPEED_10;
2813                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2814                                   DUPLEX_HALF;
2815                         break;
2816                 }
2817                 *speed = SPEED_INVALID;
2818                 *duplex = DUPLEX_INVALID;
2819                 break;
2820         }
2821 }
2822
2823 static void tg3_phy_copper_begin(struct tg3 *tp)
2824 {
2825         u32 new_adv;
2826         int i;
2827
2828         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2829                 /* Entering low power mode.  Disable gigabit and
2830                  * 100baseT advertisements.
2831                  */
2832                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2833
2834                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2835                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2836                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2837                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2838
2839                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2840         } else if (tp->link_config.speed == SPEED_INVALID) {
2841                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2842                         tp->link_config.advertising &=
2843                                 ~(ADVERTISED_1000baseT_Half |
2844                                   ADVERTISED_1000baseT_Full);
2845
2846                 new_adv = ADVERTISE_CSMA;
2847                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2848                         new_adv |= ADVERTISE_10HALF;
2849                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2850                         new_adv |= ADVERTISE_10FULL;
2851                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2852                         new_adv |= ADVERTISE_100HALF;
2853                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2854                         new_adv |= ADVERTISE_100FULL;
2855
2856                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2857
2858                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2859
2860                 if (tp->link_config.advertising &
2861                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2862                         new_adv = 0;
2863                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2864                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2865                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2866                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2867                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
2868                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2869                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2870                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2871                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2872                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2873                 } else {
2874                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2875                 }
2876         } else {
2877                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2878                 new_adv |= ADVERTISE_CSMA;
2879
2880                 /* Asking for a specific link mode. */
2881                 if (tp->link_config.speed == SPEED_1000) {
2882                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2883
2884                         if (tp->link_config.duplex == DUPLEX_FULL)
2885                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2886                         else
2887                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2888                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2889                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2890                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2891                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2892                 } else {
2893                         if (tp->link_config.speed == SPEED_100) {
2894                                 if (tp->link_config.duplex == DUPLEX_FULL)
2895                                         new_adv |= ADVERTISE_100FULL;
2896                                 else
2897                                         new_adv |= ADVERTISE_100HALF;
2898                         } else {
2899                                 if (tp->link_config.duplex == DUPLEX_FULL)
2900                                         new_adv |= ADVERTISE_10FULL;
2901                                 else
2902                                         new_adv |= ADVERTISE_10HALF;
2903                         }
2904                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2905
2906                         new_adv = 0;
2907                 }
2908
2909                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2910         }
2911
2912         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2913             tp->link_config.speed != SPEED_INVALID) {
2914                 u32 bmcr, orig_bmcr;
2915
2916                 tp->link_config.active_speed = tp->link_config.speed;
2917                 tp->link_config.active_duplex = tp->link_config.duplex;
2918
2919                 bmcr = 0;
2920                 switch (tp->link_config.speed) {
2921                 default:
2922                 case SPEED_10:
2923                         break;
2924
2925                 case SPEED_100:
2926                         bmcr |= BMCR_SPEED100;
2927                         break;
2928
2929                 case SPEED_1000:
2930                         bmcr |= TG3_BMCR_SPEED1000;
2931                         break;
2932                 }
2933
2934                 if (tp->link_config.duplex == DUPLEX_FULL)
2935                         bmcr |= BMCR_FULLDPLX;
2936
2937                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2938                     (bmcr != orig_bmcr)) {
2939                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2940                         for (i = 0; i < 1500; i++) {
2941                                 u32 tmp;
2942
2943                                 udelay(10);
2944                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2945                                     tg3_readphy(tp, MII_BMSR, &tmp))
2946                                         continue;
2947                                 if (!(tmp & BMSR_LSTATUS)) {
2948                                         udelay(40);
2949                                         break;
2950                                 }
2951                         }
2952                         tg3_writephy(tp, MII_BMCR, bmcr);
2953                         udelay(40);
2954                 }
2955         } else {
2956                 tg3_writephy(tp, MII_BMCR,
2957                              BMCR_ANENABLE | BMCR_ANRESTART);
2958         }
2959 }
2960
2961 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2962 {
2963         int err;
2964
2965         /* Turn off tap power management. */
2966         /* Set Extended packet length bit */
2967         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2968
2969         err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
2970         err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
2971         err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
2972         err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
2973         err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
2974
2975         udelay(40);
2976
2977         return err;
2978 }
2979
2980 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2981 {
2982         u32 adv_reg, all_mask = 0;
2983
2984         if (mask & ADVERTISED_10baseT_Half)
2985                 all_mask |= ADVERTISE_10HALF;
2986         if (mask & ADVERTISED_10baseT_Full)
2987                 all_mask |= ADVERTISE_10FULL;
2988         if (mask & ADVERTISED_100baseT_Half)
2989                 all_mask |= ADVERTISE_100HALF;
2990         if (mask & ADVERTISED_100baseT_Full)
2991                 all_mask |= ADVERTISE_100FULL;
2992
2993         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2994                 return 0;
2995
2996         if ((adv_reg & all_mask) != all_mask)
2997                 return 0;
2998         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
2999                 u32 tg3_ctrl;
3000
3001                 all_mask = 0;
3002                 if (mask & ADVERTISED_1000baseT_Half)
3003                         all_mask |= ADVERTISE_1000HALF;
3004                 if (mask & ADVERTISED_1000baseT_Full)
3005                         all_mask |= ADVERTISE_1000FULL;
3006
3007                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3008                         return 0;
3009
3010                 if ((tg3_ctrl & all_mask) != all_mask)
3011                         return 0;
3012         }
3013         return 1;
3014 }
3015
3016 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3017 {
3018         u32 curadv, reqadv;
3019
3020         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3021                 return 1;
3022
3023         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3024         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3025
3026         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3027                 if (curadv != reqadv)
3028                         return 0;
3029
3030                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3031                         tg3_readphy(tp, MII_LPA, rmtadv);
3032         } else {
3033                 /* Reprogram the advertisement register, even if it
3034                  * does not affect the current link.  If the link
3035                  * gets renegotiated in the future, we can save an
3036                  * additional renegotiation cycle by advertising
3037                  * it correctly in the first place.
3038                  */
3039                 if (curadv != reqadv) {
3040                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3041                                      ADVERTISE_PAUSE_ASYM);
3042                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3043                 }
3044         }
3045
3046         return 1;
3047 }
3048
3049 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3050 {
3051         int current_link_up;
3052         u32 bmsr, val;
3053         u32 lcl_adv, rmt_adv;
3054         u16 current_speed;
3055         u8 current_duplex;
3056         int i, err;
3057
3058         tw32(MAC_EVENT, 0);
3059
3060         tw32_f(MAC_STATUS,
3061              (MAC_STATUS_SYNC_CHANGED |
3062               MAC_STATUS_CFG_CHANGED |
3063               MAC_STATUS_MI_COMPLETION |
3064               MAC_STATUS_LNKSTATE_CHANGED));
3065         udelay(40);
3066
3067         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3068                 tw32_f(MAC_MI_MODE,
3069                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3070                 udelay(80);
3071         }
3072
3073         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3074
3075         /* Some third-party PHYs need to be reset on link going
3076          * down.
3077          */
3078         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3079              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3080              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3081             netif_carrier_ok(tp->dev)) {
3082                 tg3_readphy(tp, MII_BMSR, &bmsr);
3083                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3084                     !(bmsr & BMSR_LSTATUS))
3085                         force_reset = 1;
3086         }
3087         if (force_reset)
3088                 tg3_phy_reset(tp);
3089
3090         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3091                 tg3_readphy(tp, MII_BMSR, &bmsr);
3092                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3093                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3094                         bmsr = 0;
3095
3096                 if (!(bmsr & BMSR_LSTATUS)) {
3097                         err = tg3_init_5401phy_dsp(tp);
3098                         if (err)
3099                                 return err;
3100
3101                         tg3_readphy(tp, MII_BMSR, &bmsr);
3102                         for (i = 0; i < 1000; i++) {
3103                                 udelay(10);
3104                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3105                                     (bmsr & BMSR_LSTATUS)) {
3106                                         udelay(40);
3107                                         break;
3108                                 }
3109                         }
3110
3111                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3112                             TG3_PHY_REV_BCM5401_B0 &&
3113                             !(bmsr & BMSR_LSTATUS) &&
3114                             tp->link_config.active_speed == SPEED_1000) {
3115                                 err = tg3_phy_reset(tp);
3116                                 if (!err)
3117                                         err = tg3_init_5401phy_dsp(tp);
3118                                 if (err)
3119                                         return err;
3120                         }
3121                 }
3122         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3123                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3124                 /* 5701 {A0,B0} CRC bug workaround */
3125                 tg3_writephy(tp, 0x15, 0x0a75);
3126                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3127                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3128                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3129         }
3130
3131         /* Clear pending interrupts... */
3132         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3133         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3134
3135         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3136                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3137         else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3138                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3139
3140         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3141             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3142                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3143                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3144                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3145                 else
3146                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3147         }
3148
3149         current_link_up = 0;
3150         current_speed = SPEED_INVALID;
3151         current_duplex = DUPLEX_INVALID;
3152
3153         if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3154                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3155                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3156                 if (!(val & (1 << 10))) {
3157                         val |= (1 << 10);
3158                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3159                         goto relink;
3160                 }
3161         }
3162
3163         bmsr = 0;
3164         for (i = 0; i < 100; i++) {
3165                 tg3_readphy(tp, MII_BMSR, &bmsr);
3166                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3167                     (bmsr & BMSR_LSTATUS))
3168                         break;
3169                 udelay(40);
3170         }
3171
3172         if (bmsr & BMSR_LSTATUS) {
3173                 u32 aux_stat, bmcr;
3174
3175                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3176                 for (i = 0; i < 2000; i++) {
3177                         udelay(10);
3178                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3179                             aux_stat)
3180                                 break;
3181                 }
3182
3183                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3184                                              &current_speed,
3185                                              &current_duplex);
3186
3187                 bmcr = 0;
3188                 for (i = 0; i < 200; i++) {
3189                         tg3_readphy(tp, MII_BMCR, &bmcr);
3190                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3191                                 continue;
3192                         if (bmcr && bmcr != 0x7fff)
3193                                 break;
3194                         udelay(10);
3195                 }
3196
3197                 lcl_adv = 0;
3198                 rmt_adv = 0;
3199
3200                 tp->link_config.active_speed = current_speed;
3201                 tp->link_config.active_duplex = current_duplex;
3202
3203                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3204                         if ((bmcr & BMCR_ANENABLE) &&
3205                             tg3_copper_is_advertising_all(tp,
3206                                                 tp->link_config.advertising)) {
3207                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3208                                                                   &rmt_adv))
3209                                         current_link_up = 1;
3210                         }
3211                 } else {
3212                         if (!(bmcr & BMCR_ANENABLE) &&
3213                             tp->link_config.speed == current_speed &&
3214                             tp->link_config.duplex == current_duplex &&
3215                             tp->link_config.flowctrl ==
3216                             tp->link_config.active_flowctrl) {
3217                                 current_link_up = 1;
3218                         }
3219                 }
3220
3221                 if (current_link_up == 1 &&
3222                     tp->link_config.active_duplex == DUPLEX_FULL)
3223                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3224         }
3225
3226 relink:
3227         if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3228                 tg3_phy_copper_begin(tp);
3229
3230                 tg3_readphy(tp, MII_BMSR, &bmsr);
3231                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3232                     (bmsr & BMSR_LSTATUS))
3233                         current_link_up = 1;
3234         }
3235
3236         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3237         if (current_link_up == 1) {
3238                 if (tp->link_config.active_speed == SPEED_100 ||
3239                     tp->link_config.active_speed == SPEED_10)
3240                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3241                 else
3242                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3243         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3244                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3245         else
3246                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3247
3248         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3249         if (tp->link_config.active_duplex == DUPLEX_HALF)
3250                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3251
3252         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3253                 if (current_link_up == 1 &&
3254                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3255                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3256                 else
3257                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3258         }
3259
3260         /* ??? Without this setting Netgear GA302T PHY does not
3261          * ??? send/receive packets...
3262          */
3263         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3264             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3265                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3266                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3267                 udelay(80);
3268         }
3269
3270         tw32_f(MAC_MODE, tp->mac_mode);
3271         udelay(40);
3272
3273         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3274                 /* Polled via timer. */
3275                 tw32_f(MAC_EVENT, 0);
3276         } else {
3277                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3278         }
3279         udelay(40);
3280
3281         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3282             current_link_up == 1 &&
3283             tp->link_config.active_speed == SPEED_1000 &&
3284             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3285              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3286                 udelay(120);
3287                 tw32_f(MAC_STATUS,
3288                      (MAC_STATUS_SYNC_CHANGED |
3289                       MAC_STATUS_CFG_CHANGED));
3290                 udelay(40);
3291                 tg3_write_mem(tp,
3292                               NIC_SRAM_FIRMWARE_MBOX,
3293                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3294         }
3295
3296         /* Prevent send BD corruption. */
3297         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3298                 u16 oldlnkctl, newlnkctl;
3299
3300                 pci_read_config_word(tp->pdev,
3301                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3302                                      &oldlnkctl);
3303                 if (tp->link_config.active_speed == SPEED_100 ||
3304                     tp->link_config.active_speed == SPEED_10)
3305                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3306                 else
3307                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3308                 if (newlnkctl != oldlnkctl)
3309                         pci_write_config_word(tp->pdev,
3310                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3311                                               newlnkctl);
3312         }
3313
3314         if (current_link_up != netif_carrier_ok(tp->dev)) {
3315                 if (current_link_up)
3316                         netif_carrier_on(tp->dev);
3317                 else
3318                         netif_carrier_off(tp->dev);
3319                 tg3_link_report(tp);
3320         }
3321
3322         return 0;
3323 }
3324
3325 struct tg3_fiber_aneginfo {
3326         int state;
3327 #define ANEG_STATE_UNKNOWN              0
3328 #define ANEG_STATE_AN_ENABLE            1
3329 #define ANEG_STATE_RESTART_INIT         2
3330 #define ANEG_STATE_RESTART              3
3331 #define ANEG_STATE_DISABLE_LINK_OK      4
3332 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3333 #define ANEG_STATE_ABILITY_DETECT       6
3334 #define ANEG_STATE_ACK_DETECT_INIT      7
3335 #define ANEG_STATE_ACK_DETECT           8
3336 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3337 #define ANEG_STATE_COMPLETE_ACK         10
3338 #define ANEG_STATE_IDLE_DETECT_INIT     11
3339 #define ANEG_STATE_IDLE_DETECT          12
3340 #define ANEG_STATE_LINK_OK              13
3341 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3342 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3343
3344         u32 flags;
3345 #define MR_AN_ENABLE            0x00000001
3346 #define MR_RESTART_AN           0x00000002
3347 #define MR_AN_COMPLETE          0x00000004
3348 #define MR_PAGE_RX              0x00000008
3349 #define MR_NP_LOADED            0x00000010
3350 #define MR_TOGGLE_TX            0x00000020
3351 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3352 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3353 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3354 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3355 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3356 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3357 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3358 #define MR_TOGGLE_RX            0x00002000
3359 #define MR_NP_RX                0x00004000
3360
3361 #define MR_LINK_OK              0x80000000
3362
3363         unsigned long link_time, cur_time;
3364
3365         u32 ability_match_cfg;
3366         int ability_match_count;
3367
3368         char ability_match, idle_match, ack_match;
3369
3370         u32 txconfig, rxconfig;
3371 #define ANEG_CFG_NP             0x00000080
3372 #define ANEG_CFG_ACK            0x00000040
3373 #define ANEG_CFG_RF2            0x00000020
3374 #define ANEG_CFG_RF1            0x00000010
3375 #define ANEG_CFG_PS2            0x00000001
3376 #define ANEG_CFG_PS1            0x00008000
3377 #define ANEG_CFG_HD             0x00004000
3378 #define ANEG_CFG_FD             0x00002000
3379 #define ANEG_CFG_INVAL          0x00001f06
3380
3381 };
3382 #define ANEG_OK         0
3383 #define ANEG_DONE       1
3384 #define ANEG_TIMER_ENAB 2
3385 #define ANEG_FAILED     -1
3386
3387 #define ANEG_STATE_SETTLE_TIME  10000
3388
3389 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3390                                    struct tg3_fiber_aneginfo *ap)
3391 {
3392         u16 flowctrl;
3393         unsigned long delta;
3394         u32 rx_cfg_reg;
3395         int ret;
3396
3397         if (ap->state == ANEG_STATE_UNKNOWN) {
3398                 ap->rxconfig = 0;
3399                 ap->link_time = 0;
3400                 ap->cur_time = 0;
3401                 ap->ability_match_cfg = 0;
3402                 ap->ability_match_count = 0;
3403                 ap->ability_match = 0;
3404                 ap->idle_match = 0;
3405                 ap->ack_match = 0;
3406         }
3407         ap->cur_time++;
3408
3409         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3410                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3411
3412                 if (rx_cfg_reg != ap->ability_match_cfg) {
3413                         ap->ability_match_cfg = rx_cfg_reg;
3414                         ap->ability_match = 0;
3415                         ap->ability_match_count = 0;
3416                 } else {
3417                         if (++ap->ability_match_count > 1) {
3418                                 ap->ability_match = 1;
3419                                 ap->ability_match_cfg = rx_cfg_reg;
3420                         }
3421                 }
3422                 if (rx_cfg_reg & ANEG_CFG_ACK)
3423                         ap->ack_match = 1;
3424                 else
3425                         ap->ack_match = 0;
3426
3427                 ap->idle_match = 0;
3428         } else {
3429                 ap->idle_match = 1;
3430                 ap->ability_match_cfg = 0;
3431                 ap->ability_match_count = 0;
3432                 ap->ability_match = 0;
3433                 ap->ack_match = 0;
3434
3435                 rx_cfg_reg = 0;
3436         }
3437
3438         ap->rxconfig = rx_cfg_reg;
3439         ret = ANEG_OK;
3440
3441         switch (ap->state) {
3442         case ANEG_STATE_UNKNOWN:
3443                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3444                         ap->state = ANEG_STATE_AN_ENABLE;
3445
3446                 /* fallthru */
3447         case ANEG_STATE_AN_ENABLE:
3448                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3449                 if (ap->flags & MR_AN_ENABLE) {
3450                         ap->link_time = 0;
3451                         ap->cur_time = 0;
3452                         ap->ability_match_cfg = 0;
3453                         ap->ability_match_count = 0;
3454                         ap->ability_match = 0;
3455                         ap->idle_match = 0;
3456                         ap->ack_match = 0;
3457
3458                         ap->state = ANEG_STATE_RESTART_INIT;
3459                 } else {
3460                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3461                 }
3462                 break;
3463
3464         case ANEG_STATE_RESTART_INIT:
3465                 ap->link_time = ap->cur_time;
3466                 ap->flags &= ~(MR_NP_LOADED);
3467                 ap->txconfig = 0;
3468                 tw32(MAC_TX_AUTO_NEG, 0);
3469                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3470                 tw32_f(MAC_MODE, tp->mac_mode);
3471                 udelay(40);
3472
3473                 ret = ANEG_TIMER_ENAB;
3474                 ap->state = ANEG_STATE_RESTART;
3475
3476                 /* fallthru */
3477         case ANEG_STATE_RESTART:
3478                 delta = ap->cur_time - ap->link_time;
3479                 if (delta > ANEG_STATE_SETTLE_TIME)
3480                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3481                 else
3482                         ret = ANEG_TIMER_ENAB;
3483                 break;
3484
3485         case ANEG_STATE_DISABLE_LINK_OK:
3486                 ret = ANEG_DONE;
3487                 break;
3488
3489         case ANEG_STATE_ABILITY_DETECT_INIT:
3490                 ap->flags &= ~(MR_TOGGLE_TX);
3491                 ap->txconfig = ANEG_CFG_FD;
3492                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3493                 if (flowctrl & ADVERTISE_1000XPAUSE)
3494                         ap->txconfig |= ANEG_CFG_PS1;
3495                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3496                         ap->txconfig |= ANEG_CFG_PS2;
3497                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3498                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3499                 tw32_f(MAC_MODE, tp->mac_mode);
3500                 udelay(40);
3501
3502                 ap->state = ANEG_STATE_ABILITY_DETECT;
3503                 break;
3504
3505         case ANEG_STATE_ABILITY_DETECT:
3506                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3507                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3508                 break;
3509
3510         case ANEG_STATE_ACK_DETECT_INIT:
3511                 ap->txconfig |= ANEG_CFG_ACK;
3512                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3513                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3514                 tw32_f(MAC_MODE, tp->mac_mode);
3515                 udelay(40);
3516
3517                 ap->state = ANEG_STATE_ACK_DETECT;
3518
3519                 /* fallthru */
3520         case ANEG_STATE_ACK_DETECT:
3521                 if (ap->ack_match != 0) {
3522                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3523                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3524                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3525                         } else {
3526                                 ap->state = ANEG_STATE_AN_ENABLE;
3527                         }
3528                 } else if (ap->ability_match != 0 &&
3529                            ap->rxconfig == 0) {
3530                         ap->state = ANEG_STATE_AN_ENABLE;
3531                 }
3532                 break;
3533
3534         case ANEG_STATE_COMPLETE_ACK_INIT:
3535                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3536                         ret = ANEG_FAILED;
3537                         break;
3538                 }
3539                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3540                                MR_LP_ADV_HALF_DUPLEX |
3541                                MR_LP_ADV_SYM_PAUSE |
3542                                MR_LP_ADV_ASYM_PAUSE |
3543                                MR_LP_ADV_REMOTE_FAULT1 |
3544                                MR_LP_ADV_REMOTE_FAULT2 |
3545                                MR_LP_ADV_NEXT_PAGE |
3546                                MR_TOGGLE_RX |
3547                                MR_NP_RX);
3548                 if (ap->rxconfig & ANEG_CFG_FD)
3549                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3550                 if (ap->rxconfig & ANEG_CFG_HD)
3551                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3552                 if (ap->rxconfig & ANEG_CFG_PS1)
3553                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3554                 if (ap->rxconfig & ANEG_CFG_PS2)
3555                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3556                 if (ap->rxconfig & ANEG_CFG_RF1)
3557                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3558                 if (ap->rxconfig & ANEG_CFG_RF2)
3559                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3560                 if (ap->rxconfig & ANEG_CFG_NP)
3561                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3562
3563                 ap->link_time = ap->cur_time;
3564
3565                 ap->flags ^= (MR_TOGGLE_TX);
3566                 if (ap->rxconfig & 0x0008)
3567                         ap->flags |= MR_TOGGLE_RX;
3568                 if (ap->rxconfig & ANEG_CFG_NP)
3569                         ap->flags |= MR_NP_RX;
3570                 ap->flags |= MR_PAGE_RX;
3571
3572                 ap->state = ANEG_STATE_COMPLETE_ACK;
3573                 ret = ANEG_TIMER_ENAB;
3574                 break;
3575
3576         case ANEG_STATE_COMPLETE_ACK:
3577                 if (ap->ability_match != 0 &&
3578                     ap->rxconfig == 0) {
3579                         ap->state = ANEG_STATE_AN_ENABLE;
3580                         break;
3581                 }
3582                 delta = ap->cur_time - ap->link_time;
3583                 if (delta > ANEG_STATE_SETTLE_TIME) {
3584                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3585                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3586                         } else {
3587                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3588                                     !(ap->flags & MR_NP_RX)) {
3589                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3590                                 } else {
3591                                         ret = ANEG_FAILED;
3592                                 }
3593                         }
3594                 }
3595                 break;
3596
3597         case ANEG_STATE_IDLE_DETECT_INIT:
3598                 ap->link_time = ap->cur_time;
3599                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3600                 tw32_f(MAC_MODE, tp->mac_mode);
3601                 udelay(40);
3602
3603                 ap->state = ANEG_STATE_IDLE_DETECT;
3604                 ret = ANEG_TIMER_ENAB;
3605                 break;
3606
3607         case ANEG_STATE_IDLE_DETECT:
3608                 if (ap->ability_match != 0 &&
3609                     ap->rxconfig == 0) {
3610                         ap->state = ANEG_STATE_AN_ENABLE;
3611                         break;
3612                 }
3613                 delta = ap->cur_time - ap->link_time;
3614                 if (delta > ANEG_STATE_SETTLE_TIME) {
3615                         /* XXX another gem from the Broadcom driver :( */
3616                         ap->state = ANEG_STATE_LINK_OK;
3617                 }
3618                 break;
3619
3620         case ANEG_STATE_LINK_OK:
3621                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3622                 ret = ANEG_DONE;
3623                 break;
3624
3625         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3626                 /* ??? unimplemented */
3627                 break;
3628
3629         case ANEG_STATE_NEXT_PAGE_WAIT:
3630                 /* ??? unimplemented */
3631                 break;
3632
3633         default:
3634                 ret = ANEG_FAILED;
3635                 break;
3636         }
3637
3638         return ret;
3639 }
3640
3641 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3642 {
3643         int res = 0;
3644         struct tg3_fiber_aneginfo aninfo;
3645         int status = ANEG_FAILED;
3646         unsigned int tick;
3647         u32 tmp;
3648
3649         tw32_f(MAC_TX_AUTO_NEG, 0);
3650
3651         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3652         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3653         udelay(40);
3654
3655         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3656         udelay(40);
3657
3658         memset(&aninfo, 0, sizeof(aninfo));
3659         aninfo.flags |= MR_AN_ENABLE;
3660         aninfo.state = ANEG_STATE_UNKNOWN;
3661         aninfo.cur_time = 0;
3662         tick = 0;
3663         while (++tick < 195000) {
3664                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3665                 if (status == ANEG_DONE || status == ANEG_FAILED)
3666                         break;
3667
3668                 udelay(1);
3669         }
3670
3671         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3672         tw32_f(MAC_MODE, tp->mac_mode);
3673         udelay(40);
3674
3675         *txflags = aninfo.txconfig;
3676         *rxflags = aninfo.flags;
3677
3678         if (status == ANEG_DONE &&
3679             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3680                              MR_LP_ADV_FULL_DUPLEX)))
3681                 res = 1;
3682
3683         return res;
3684 }
3685
3686 static void tg3_init_bcm8002(struct tg3 *tp)
3687 {
3688         u32 mac_status = tr32(MAC_STATUS);
3689         int i;
3690
3691         /* Reset when initting first time or we have a link. */
3692         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3693             !(mac_status & MAC_STATUS_PCS_SYNCED))
3694                 return;
3695
3696         /* Set PLL lock range. */
3697         tg3_writephy(tp, 0x16, 0x8007);
3698
3699         /* SW reset */
3700         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3701
3702         /* Wait for reset to complete. */
3703         /* XXX schedule_timeout() ... */
3704         for (i = 0; i < 500; i++)
3705                 udelay(10);
3706
3707         /* Config mode; select PMA/Ch 1 regs. */
3708         tg3_writephy(tp, 0x10, 0x8411);
3709
3710         /* Enable auto-lock and comdet, select txclk for tx. */
3711         tg3_writephy(tp, 0x11, 0x0a10);
3712
3713         tg3_writephy(tp, 0x18, 0x00a0);
3714         tg3_writephy(tp, 0x16, 0x41ff);
3715
3716         /* Assert and deassert POR. */
3717         tg3_writephy(tp, 0x13, 0x0400);
3718         udelay(40);
3719         tg3_writephy(tp, 0x13, 0x0000);
3720
3721         tg3_writephy(tp, 0x11, 0x0a50);
3722         udelay(40);
3723         tg3_writephy(tp, 0x11, 0x0a10);
3724
3725         /* Wait for signal to stabilize */
3726         /* XXX schedule_timeout() ... */
3727         for (i = 0; i < 15000; i++)
3728                 udelay(10);
3729
3730         /* Deselect the channel register so we can read the PHYID
3731          * later.
3732          */
3733         tg3_writephy(tp, 0x10, 0x8011);
3734 }
3735
3736 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3737 {
3738         u16 flowctrl;
3739         u32 sg_dig_ctrl, sg_dig_status;
3740         u32 serdes_cfg, expected_sg_dig_ctrl;
3741         int workaround, port_a;
3742         int current_link_up;
3743
3744         serdes_cfg = 0;
3745         expected_sg_dig_ctrl = 0;
3746         workaround = 0;
3747         port_a = 1;
3748         current_link_up = 0;
3749
3750         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3751             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3752                 workaround = 1;
3753                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3754                         port_a = 0;
3755
3756                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3757                 /* preserve bits 20-23 for voltage regulator */
3758                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3759         }
3760
3761         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3762
3763         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3764                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3765                         if (workaround) {
3766                                 u32 val = serdes_cfg;
3767
3768                                 if (port_a)
3769                                         val |= 0xc010000;
3770                                 else
3771                                         val |= 0x4010000;
3772                                 tw32_f(MAC_SERDES_CFG, val);
3773                         }
3774
3775                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3776                 }
3777                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3778                         tg3_setup_flow_control(tp, 0, 0);
3779                         current_link_up = 1;
3780                 }
3781                 goto out;
3782         }
3783
3784         /* Want auto-negotiation.  */
3785         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3786
3787         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3788         if (flowctrl & ADVERTISE_1000XPAUSE)
3789                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3790         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3791                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3792
3793         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3794                 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3795                     tp->serdes_counter &&
3796                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3797                                     MAC_STATUS_RCVD_CFG)) ==
3798                      MAC_STATUS_PCS_SYNCED)) {
3799                         tp->serdes_counter--;
3800                         current_link_up = 1;
3801                         goto out;
3802                 }
3803 restart_autoneg:
3804                 if (workaround)
3805                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3806                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3807                 udelay(5);
3808                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3809
3810                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3811                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3812         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3813                                  MAC_STATUS_SIGNAL_DET)) {
3814                 sg_dig_status = tr32(SG_DIG_STATUS);
3815                 mac_status = tr32(MAC_STATUS);
3816
3817                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3818                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3819                         u32 local_adv = 0, remote_adv = 0;
3820
3821                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3822                                 local_adv |= ADVERTISE_1000XPAUSE;
3823                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3824                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3825
3826                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3827                                 remote_adv |= LPA_1000XPAUSE;
3828                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3829                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3830
3831                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3832                         current_link_up = 1;
3833                         tp->serdes_counter = 0;
3834                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3835                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3836                         if (tp->serdes_counter)
3837                                 tp->serdes_counter--;
3838                         else {
3839                                 if (workaround) {
3840                                         u32 val = serdes_cfg;
3841
3842                                         if (port_a)
3843                                                 val |= 0xc010000;
3844                                         else
3845                                                 val |= 0x4010000;
3846
3847                                         tw32_f(MAC_SERDES_CFG, val);
3848                                 }
3849
3850                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3851                                 udelay(40);
3852
3853                                 /* Link parallel detection - link is up */
3854                                 /* only if we have PCS_SYNC and not */
3855                                 /* receiving config code words */
3856                                 mac_status = tr32(MAC_STATUS);
3857                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3858                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3859                                         tg3_setup_flow_control(tp, 0, 0);
3860                                         current_link_up = 1;
3861                                         tp->phy_flags |=
3862                                                 TG3_PHYFLG_PARALLEL_DETECT;
3863                                         tp->serdes_counter =
3864                                                 SERDES_PARALLEL_DET_TIMEOUT;
3865                                 } else
3866                                         goto restart_autoneg;
3867                         }
3868                 }
3869         } else {
3870                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3871                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3872         }
3873
3874 out:
3875         return current_link_up;
3876 }
3877
3878 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3879 {
3880         int current_link_up = 0;
3881
3882         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3883                 goto out;
3884
3885         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3886                 u32 txflags, rxflags;
3887                 int i;
3888
3889                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3890                         u32 local_adv = 0, remote_adv = 0;
3891
3892                         if (txflags & ANEG_CFG_PS1)
3893                                 local_adv |= ADVERTISE_1000XPAUSE;
3894                         if (txflags & ANEG_CFG_PS2)
3895                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3896
3897                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3898                                 remote_adv |= LPA_1000XPAUSE;
3899                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3900                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3901
3902                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3903
3904                         current_link_up = 1;
3905                 }
3906                 for (i = 0; i < 30; i++) {
3907                         udelay(20);
3908                         tw32_f(MAC_STATUS,
3909                                (MAC_STATUS_SYNC_CHANGED |
3910                                 MAC_STATUS_CFG_CHANGED));
3911                         udelay(40);
3912                         if ((tr32(MAC_STATUS) &
3913                              (MAC_STATUS_SYNC_CHANGED |
3914                               MAC_STATUS_CFG_CHANGED)) == 0)
3915                                 break;
3916                 }
3917
3918                 mac_status = tr32(MAC_STATUS);
3919                 if (current_link_up == 0 &&
3920                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3921                     !(mac_status & MAC_STATUS_RCVD_CFG))
3922                         current_link_up = 1;
3923         } else {
3924                 tg3_setup_flow_control(tp, 0, 0);
3925
3926                 /* Forcing 1000FD link up. */
3927                 current_link_up = 1;
3928
3929                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3930                 udelay(40);
3931
3932                 tw32_f(MAC_MODE, tp->mac_mode);
3933                 udelay(40);
3934         }
3935
3936 out:
3937         return current_link_up;
3938 }
3939
3940 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3941 {
3942         u32 orig_pause_cfg;
3943         u16 orig_active_speed;
3944         u8 orig_active_duplex;
3945         u32 mac_status;
3946         int current_link_up;
3947         int i;
3948
3949         orig_pause_cfg = tp->link_config.active_flowctrl;
3950         orig_active_speed = tp->link_config.active_speed;
3951         orig_active_duplex = tp->link_config.active_duplex;
3952
3953         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3954             netif_carrier_ok(tp->dev) &&
3955             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3956                 mac_status = tr32(MAC_STATUS);
3957                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3958                                MAC_STATUS_SIGNAL_DET |
3959                                MAC_STATUS_CFG_CHANGED |
3960                                MAC_STATUS_RCVD_CFG);
3961                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3962                                    MAC_STATUS_SIGNAL_DET)) {
3963                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3964                                             MAC_STATUS_CFG_CHANGED));
3965                         return 0;
3966                 }
3967         }
3968
3969         tw32_f(MAC_TX_AUTO_NEG, 0);
3970
3971         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3972         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3973         tw32_f(MAC_MODE, tp->mac_mode);
3974         udelay(40);
3975
3976         if (tp->phy_id == TG3_PHY_ID_BCM8002)
3977                 tg3_init_bcm8002(tp);
3978
3979         /* Enable link change event even when serdes polling.  */
3980         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3981         udelay(40);
3982
3983         current_link_up = 0;
3984         mac_status = tr32(MAC_STATUS);
3985
3986         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3987                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3988         else
3989                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3990
3991         tp->napi[0].hw_status->status =
3992                 (SD_STATUS_UPDATED |
3993                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3994
3995         for (i = 0; i < 100; i++) {
3996                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3997                                     MAC_STATUS_CFG_CHANGED));
3998                 udelay(5);
3999                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4000                                          MAC_STATUS_CFG_CHANGED |
4001                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4002                         break;
4003         }
4004
4005         mac_status = tr32(MAC_STATUS);
4006         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4007                 current_link_up = 0;
4008                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4009                     tp->serdes_counter == 0) {
4010                         tw32_f(MAC_MODE, (tp->mac_mode |
4011                                           MAC_MODE_SEND_CONFIGS));
4012                         udelay(1);
4013                         tw32_f(MAC_MODE, tp->mac_mode);
4014                 }
4015         }
4016
4017         if (current_link_up == 1) {
4018                 tp->link_config.active_speed = SPEED_1000;
4019                 tp->link_config.active_duplex = DUPLEX_FULL;
4020                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4021                                     LED_CTRL_LNKLED_OVERRIDE |
4022                                     LED_CTRL_1000MBPS_ON));
4023         } else {
4024                 tp->link_config.active_speed = SPEED_INVALID;
4025                 tp->link_config.active_duplex = DUPLEX_INVALID;
4026                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4027                                     LED_CTRL_LNKLED_OVERRIDE |
4028                                     LED_CTRL_TRAFFIC_OVERRIDE));
4029         }
4030
4031         if (current_link_up != netif_carrier_ok(tp->dev)) {
4032                 if (current_link_up)
4033                         netif_carrier_on(tp->dev);
4034                 else
4035                         netif_carrier_off(tp->dev);
4036                 tg3_link_report(tp);
4037         } else {
4038                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4039                 if (orig_pause_cfg != now_pause_cfg ||
4040                     orig_active_speed != tp->link_config.active_speed ||
4041                     orig_active_duplex != tp->link_config.active_duplex)
4042                         tg3_link_report(tp);
4043         }
4044
4045         return 0;
4046 }
4047
4048 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4049 {
4050         int current_link_up, err = 0;
4051         u32 bmsr, bmcr;
4052         u16 current_speed;
4053         u8 current_duplex;
4054         u32 local_adv, remote_adv;
4055
4056         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4057         tw32_f(MAC_MODE, tp->mac_mode);
4058         udelay(40);
4059
4060         tw32(MAC_EVENT, 0);
4061
4062         tw32_f(MAC_STATUS,
4063              (MAC_STATUS_SYNC_CHANGED |
4064               MAC_STATUS_CFG_CHANGED |
4065               MAC_STATUS_MI_COMPLETION |
4066               MAC_STATUS_LNKSTATE_CHANGED));
4067         udelay(40);
4068
4069         if (force_reset)
4070                 tg3_phy_reset(tp);
4071
4072         current_link_up = 0;
4073         current_speed = SPEED_INVALID;
4074         current_duplex = DUPLEX_INVALID;
4075
4076         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4077         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4078         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4079                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4080                         bmsr |= BMSR_LSTATUS;
4081                 else
4082                         bmsr &= ~BMSR_LSTATUS;
4083         }
4084
4085         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4086
4087         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4088             (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4089                 /* do nothing, just check for link up at the end */
4090         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4091                 u32 adv, new_adv;
4092
4093                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4094                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4095                                   ADVERTISE_1000XPAUSE |
4096                                   ADVERTISE_1000XPSE_ASYM |
4097                                   ADVERTISE_SLCT);
4098
4099                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4100
4101                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4102                         new_adv |= ADVERTISE_1000XHALF;
4103                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4104                         new_adv |= ADVERTISE_1000XFULL;
4105
4106                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4107                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4108                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4109                         tg3_writephy(tp, MII_BMCR, bmcr);
4110
4111                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4112                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4113                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4114
4115                         return err;
4116                 }
4117         } else {
4118                 u32 new_bmcr;
4119
4120                 bmcr &= ~BMCR_SPEED1000;
4121                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4122
4123                 if (tp->link_config.duplex == DUPLEX_FULL)
4124                         new_bmcr |= BMCR_FULLDPLX;
4125
4126                 if (new_bmcr != bmcr) {
4127                         /* BMCR_SPEED1000 is a reserved bit that needs
4128                          * to be set on write.
4129                          */
4130                         new_bmcr |= BMCR_SPEED1000;
4131
4132                         /* Force a linkdown */
4133                         if (netif_carrier_ok(tp->dev)) {
4134                                 u32 adv;
4135
4136                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4137                                 adv &= ~(ADVERTISE_1000XFULL |
4138                                          ADVERTISE_1000XHALF |
4139                                          ADVERTISE_SLCT);
4140                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4141                                 tg3_writephy(tp, MII_BMCR, bmcr |
4142                                                            BMCR_ANRESTART |
4143                                                            BMCR_ANENABLE);
4144                                 udelay(10);
4145                                 netif_carrier_off(tp->dev);
4146                         }
4147                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4148                         bmcr = new_bmcr;
4149                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4150                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4151                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4152                             ASIC_REV_5714) {
4153                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4154                                         bmsr |= BMSR_LSTATUS;
4155                                 else
4156                                         bmsr &= ~BMSR_LSTATUS;
4157                         }
4158                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4159                 }
4160         }
4161
4162         if (bmsr & BMSR_LSTATUS) {
4163                 current_speed = SPEED_1000;
4164                 current_link_up = 1;
4165                 if (bmcr & BMCR_FULLDPLX)
4166                         current_duplex = DUPLEX_FULL;
4167                 else
4168                         current_duplex = DUPLEX_HALF;
4169
4170                 local_adv = 0;
4171                 remote_adv = 0;
4172
4173                 if (bmcr & BMCR_ANENABLE) {
4174                         u32 common;
4175
4176                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4177                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4178                         common = local_adv & remote_adv;
4179                         if (common & (ADVERTISE_1000XHALF |
4180                                       ADVERTISE_1000XFULL)) {
4181                                 if (common & ADVERTISE_1000XFULL)
4182                                         current_duplex = DUPLEX_FULL;
4183                                 else
4184                                         current_duplex = DUPLEX_HALF;
4185                         } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4186                                 /* Link is up via parallel detect */
4187                         } else {
4188                                 current_link_up = 0;
4189                         }
4190                 }
4191         }
4192
4193         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4194                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4195
4196         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4197         if (tp->link_config.active_duplex == DUPLEX_HALF)
4198                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4199
4200         tw32_f(MAC_MODE, tp->mac_mode);
4201         udelay(40);
4202
4203         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4204
4205         tp->link_config.active_speed = current_speed;
4206         tp->link_config.active_duplex = current_duplex;
4207
4208         if (current_link_up != netif_carrier_ok(tp->dev)) {
4209                 if (current_link_up)
4210                         netif_carrier_on(tp->dev);
4211                 else {
4212                         netif_carrier_off(tp->dev);
4213                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4214                 }
4215                 tg3_link_report(tp);
4216         }
4217         return err;
4218 }
4219
4220 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4221 {
4222         if (tp->serdes_counter) {
4223                 /* Give autoneg time to complete. */
4224                 tp->serdes_counter--;
4225                 return;
4226         }
4227
4228         if (!netif_carrier_ok(tp->dev) &&
4229             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4230                 u32 bmcr;
4231
4232                 tg3_readphy(tp, MII_BMCR, &bmcr);
4233                 if (bmcr & BMCR_ANENABLE) {
4234                         u32 phy1, phy2;
4235
4236                         /* Select shadow register 0x1f */
4237                         tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4238                         tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4239
4240                         /* Select expansion interrupt status register */
4241                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4242                                          MII_TG3_DSP_EXP1_INT_STAT);
4243                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4244                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4245
4246                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4247                                 /* We have signal detect and not receiving
4248                                  * config code words, link is up by parallel
4249                                  * detection.
4250                                  */
4251
4252                                 bmcr &= ~BMCR_ANENABLE;
4253                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4254                                 tg3_writephy(tp, MII_BMCR, bmcr);
4255                                 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4256                         }
4257                 }
4258         } else if (netif_carrier_ok(tp->dev) &&
4259                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4260                    (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4261                 u32 phy2;
4262
4263                 /* Select expansion interrupt status register */
4264                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4265                                  MII_TG3_DSP_EXP1_INT_STAT);
4266                 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4267                 if (phy2 & 0x20) {
4268                         u32 bmcr;
4269
4270                         /* Config code words received, turn on autoneg. */
4271                         tg3_readphy(tp, MII_BMCR, &bmcr);
4272                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4273
4274                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4275
4276                 }
4277         }
4278 }
4279
4280 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4281 {
4282         int err;
4283
4284         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4285                 err = tg3_setup_fiber_phy(tp, force_reset);
4286         else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4287                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4288         else
4289                 err = tg3_setup_copper_phy(tp, force_reset);
4290
4291         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4292                 u32 val, scale;
4293
4294                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4295                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4296                         scale = 65;
4297                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4298                         scale = 6;
4299                 else
4300                         scale = 12;
4301
4302                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4303                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4304                 tw32(GRC_MISC_CFG, val);
4305         }
4306
4307         if (tp->link_config.active_speed == SPEED_1000 &&
4308             tp->link_config.active_duplex == DUPLEX_HALF)
4309                 tw32(MAC_TX_LENGTHS,
4310                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4311                       (6 << TX_LENGTHS_IPG_SHIFT) |
4312                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4313         else
4314                 tw32(MAC_TX_LENGTHS,
4315                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4316                       (6 << TX_LENGTHS_IPG_SHIFT) |
4317                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4318
4319         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4320                 if (netif_carrier_ok(tp->dev)) {
4321                         tw32(HOSTCC_STAT_COAL_TICKS,
4322                              tp->coal.stats_block_coalesce_usecs);
4323                 } else {
4324                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4325                 }
4326         }
4327
4328         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4329                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4330                 if (!netif_carrier_ok(tp->dev))
4331                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4332                               tp->pwrmgmt_thresh;
4333                 else
4334                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4335                 tw32(PCIE_PWR_MGMT_THRESH, val);
4336         }
4337
4338         return err;
4339 }
4340
4341 /* This is called whenever we suspect that the system chipset is re-
4342  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4343  * is bogus tx completions. We try to recover by setting the
4344  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4345  * in the workqueue.
4346  */
4347 static void tg3_tx_recover(struct tg3 *tp)
4348 {
4349         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4350                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4351
4352         netdev_warn(tp->dev,
4353                     "The system may be re-ordering memory-mapped I/O "
4354                     "cycles to the network device, attempting to recover. "
4355                     "Please report the problem to the driver maintainer "
4356                     "and include system chipset information.\n");
4357
4358         spin_lock(&tp->lock);
4359         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4360         spin_unlock(&tp->lock);
4361 }
4362
4363 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4364 {
4365         /* Tell compiler to fetch tx indices from memory. */
4366         barrier();
4367         return tnapi->tx_pending -
4368                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4369 }
4370
4371 /* Tigon3 never reports partial packet sends.  So we do not
4372  * need special logic to handle SKBs that have not had all
4373  * of their frags sent yet, like SunGEM does.
4374  */
4375 static void tg3_tx(struct tg3_napi *tnapi)
4376 {
4377         struct tg3 *tp = tnapi->tp;
4378         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4379         u32 sw_idx = tnapi->tx_cons;
4380         struct netdev_queue *txq;
4381         int index = tnapi - tp->napi;
4382
4383         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4384                 index--;
4385
4386         txq = netdev_get_tx_queue(tp->dev, index);
4387
4388         while (sw_idx != hw_idx) {
4389                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4390                 struct sk_buff *skb = ri->skb;
4391                 int i, tx_bug = 0;
4392
4393                 if (unlikely(skb == NULL)) {
4394                         tg3_tx_recover(tp);
4395                         return;
4396                 }
4397
4398                 pci_unmap_single(tp->pdev,
4399                                  dma_unmap_addr(ri, mapping),
4400                                  skb_headlen(skb),
4401                                  PCI_DMA_TODEVICE);
4402
4403                 ri->skb = NULL;
4404
4405                 sw_idx = NEXT_TX(sw_idx);
4406
4407                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4408                         ri = &tnapi->tx_buffers[sw_idx];
4409                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4410                                 tx_bug = 1;
4411
4412                         pci_unmap_page(tp->pdev,
4413                                        dma_unmap_addr(ri, mapping),
4414                                        skb_shinfo(skb)->frags[i].size,
4415                                        PCI_DMA_TODEVICE);
4416                         sw_idx = NEXT_TX(sw_idx);
4417                 }
4418
4419                 dev_kfree_skb(skb);
4420
4421                 if (unlikely(tx_bug)) {
4422                         tg3_tx_recover(tp);
4423                         return;
4424                 }
4425         }
4426
4427         tnapi->tx_cons = sw_idx;
4428
4429         /* Need to make the tx_cons update visible to tg3_start_xmit()
4430          * before checking for netif_queue_stopped().  Without the
4431          * memory barrier, there is a small possibility that tg3_start_xmit()
4432          * will miss it and cause the queue to be stopped forever.
4433          */
4434         smp_mb();
4435
4436         if (unlikely(netif_tx_queue_stopped(txq) &&
4437                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4438                 __netif_tx_lock(txq, smp_processor_id());
4439                 if (netif_tx_queue_stopped(txq) &&
4440                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4441                         netif_tx_wake_queue(txq);
4442                 __netif_tx_unlock(txq);
4443         }
4444 }
4445
4446 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4447 {
4448         if (!ri->skb)
4449                 return;
4450
4451         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4452                          map_sz, PCI_DMA_FROMDEVICE);
4453         dev_kfree_skb_any(ri->skb);
4454         ri->skb = NULL;
4455 }
4456
4457 /* Returns size of skb allocated or < 0 on error.
4458  *
4459  * We only need to fill in the address because the other members
4460  * of the RX descriptor are invariant, see tg3_init_rings.
4461  *
4462  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4463  * posting buffers we only dirty the first cache line of the RX
4464  * descriptor (containing the address).  Whereas for the RX status
4465  * buffers the cpu only reads the last cacheline of the RX descriptor
4466  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4467  */
4468 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4469                             u32 opaque_key, u32 dest_idx_unmasked)
4470 {
4471         struct tg3_rx_buffer_desc *desc;
4472         struct ring_info *map, *src_map;
4473         struct sk_buff *skb;
4474         dma_addr_t mapping;
4475         int skb_size, dest_idx;
4476
4477         src_map = NULL;
4478         switch (opaque_key) {
4479         case RXD_OPAQUE_RING_STD:
4480                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4481                 desc = &tpr->rx_std[dest_idx];
4482                 map = &tpr->rx_std_buffers[dest_idx];
4483                 skb_size = tp->rx_pkt_map_sz;
4484                 break;
4485
4486         case RXD_OPAQUE_RING_JUMBO:
4487                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4488                 desc = &tpr->rx_jmb[dest_idx].std;
4489                 map = &tpr->rx_jmb_buffers[dest_idx];
4490                 skb_size = TG3_RX_JMB_MAP_SZ;
4491                 break;
4492
4493         default:
4494                 return -EINVAL;
4495         }
4496
4497         /* Do not overwrite any of the map or rp information
4498          * until we are sure we can commit to a new buffer.
4499          *
4500          * Callers depend upon this behavior and assume that
4501          * we leave everything unchanged if we fail.
4502          */
4503         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4504         if (skb == NULL)
4505                 return -ENOMEM;
4506
4507         skb_reserve(skb, tp->rx_offset);
4508
4509         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4510                                  PCI_DMA_FROMDEVICE);
4511         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4512                 dev_kfree_skb(skb);
4513                 return -EIO;
4514         }
4515
4516         map->skb = skb;
4517         dma_unmap_addr_set(map, mapping, mapping);
4518
4519         desc->addr_hi = ((u64)mapping >> 32);
4520         desc->addr_lo = ((u64)mapping & 0xffffffff);
4521
4522         return skb_size;
4523 }
4524
4525 /* We only need to move over in the address because the other
4526  * members of the RX descriptor are invariant.  See notes above
4527  * tg3_alloc_rx_skb for full details.
4528  */
4529 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4530                            struct tg3_rx_prodring_set *dpr,
4531                            u32 opaque_key, int src_idx,
4532                            u32 dest_idx_unmasked)
4533 {
4534         struct tg3 *tp = tnapi->tp;
4535         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4536         struct ring_info *src_map, *dest_map;
4537         struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
4538         int dest_idx;
4539
4540         switch (opaque_key) {
4541         case RXD_OPAQUE_RING_STD:
4542                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4543                 dest_desc = &dpr->rx_std[dest_idx];
4544                 dest_map = &dpr->rx_std_buffers[dest_idx];
4545                 src_desc = &spr->rx_std[src_idx];
4546                 src_map = &spr->rx_std_buffers[src_idx];
4547                 break;
4548
4549         case RXD_OPAQUE_RING_JUMBO:
4550                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4551                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4552                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4553                 src_desc = &spr->rx_jmb[src_idx].std;
4554                 src_map = &spr->rx_jmb_buffers[src_idx];
4555                 break;
4556
4557         default:
4558                 return;
4559         }
4560
4561         dest_map->skb = src_map->skb;
4562         dma_unmap_addr_set(dest_map, mapping,
4563                            dma_unmap_addr(src_map, mapping));
4564         dest_desc->addr_hi = src_desc->addr_hi;
4565         dest_desc->addr_lo = src_desc->addr_lo;
4566
4567         /* Ensure that the update to the skb happens after the physical
4568          * addresses have been transferred to the new BD location.
4569          */
4570         smp_wmb();
4571
4572         src_map->skb = NULL;
4573 }
4574
4575 /* The RX ring scheme is composed of multiple rings which post fresh
4576  * buffers to the chip, and one special ring the chip uses to report
4577  * status back to the host.
4578  *
4579  * The special ring reports the status of received packets to the
4580  * host.  The chip does not write into the original descriptor the
4581  * RX buffer was obtained from.  The chip simply takes the original
4582  * descriptor as provided by the host, updates the status and length
4583  * field, then writes this into the next status ring entry.
4584  *
4585  * Each ring the host uses to post buffers to the chip is described
4586  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4587  * it is first placed into the on-chip ram.  When the packet's length
4588  * is known, it walks down the TG3_BDINFO entries to select the ring.
4589  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4590  * which is within the range of the new packet's length is chosen.
4591  *
4592  * The "separate ring for rx status" scheme may sound queer, but it makes
4593  * sense from a cache coherency perspective.  If only the host writes
4594  * to the buffer post rings, and only the chip writes to the rx status
4595  * rings, then cache lines never move beyond shared-modified state.
4596  * If both the host and chip were to write into the same ring, cache line
4597  * eviction could occur since both entities want it in an exclusive state.
4598  */
4599 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4600 {
4601         struct tg3 *tp = tnapi->tp;
4602         u32 work_mask, rx_std_posted = 0;
4603         u32 std_prod_idx, jmb_prod_idx;
4604         u32 sw_idx = tnapi->rx_rcb_ptr;
4605         u16 hw_idx;
4606         int received;
4607         struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
4608
4609         hw_idx = *(tnapi->rx_rcb_prod_idx);
4610         /*
4611          * We need to order the read of hw_idx and the read of
4612          * the opaque cookie.
4613          */
4614         rmb();
4615         work_mask = 0;
4616         received = 0;
4617         std_prod_idx = tpr->rx_std_prod_idx;
4618         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4619         while (sw_idx != hw_idx && budget > 0) {
4620                 struct ring_info *ri;
4621                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4622                 unsigned int len;
4623                 struct sk_buff *skb;
4624                 dma_addr_t dma_addr;
4625                 u32 opaque_key, desc_idx, *post_ptr;
4626                 bool hw_vlan __maybe_unused = false;
4627                 u16 vtag __maybe_unused = 0;
4628
4629                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4630                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4631                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4632                         ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4633                         dma_addr = dma_unmap_addr(ri, mapping);
4634                         skb = ri->skb;
4635                         post_ptr = &std_prod_idx;
4636                         rx_std_posted++;
4637                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4638                         ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4639                         dma_addr = dma_unmap_addr(ri, mapping);
4640                         skb = ri->skb;
4641                         post_ptr = &jmb_prod_idx;
4642                 } else
4643                         goto next_pkt_nopost;
4644
4645                 work_mask |= opaque_key;
4646
4647                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4648                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4649                 drop_it:
4650                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4651                                        desc_idx, *post_ptr);
4652                 drop_it_no_recycle:
4653                         /* Other statistics kept track of by card. */
4654                         tp->net_stats.rx_dropped++;
4655                         goto next_pkt;
4656                 }
4657
4658                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4659                       ETH_FCS_LEN;
4660
4661                 if (len > TG3_RX_COPY_THRESH(tp)) {
4662                         int skb_size;
4663
4664                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4665                                                     *post_ptr);
4666                         if (skb_size < 0)
4667                                 goto drop_it;
4668
4669                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4670                                          PCI_DMA_FROMDEVICE);
4671
4672                         /* Ensure that the update to the skb happens
4673                          * after the usage of the old DMA mapping.
4674                          */
4675                         smp_wmb();
4676
4677                         ri->skb = NULL;
4678
4679                         skb_put(skb, len);
4680                 } else {
4681                         struct sk_buff *copy_skb;
4682
4683                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4684                                        desc_idx, *post_ptr);
4685
4686                         copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
4687                                                     TG3_RAW_IP_ALIGN);
4688                         if (copy_skb == NULL)
4689                                 goto drop_it_no_recycle;
4690
4691                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
4692                         skb_put(copy_skb, len);
4693                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4694                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4695                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4696
4697                         /* We'll reuse the original ring buffer. */
4698                         skb = copy_skb;
4699                 }
4700
4701                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4702                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4703                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4704                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4705                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4706                 else
4707                         skb_checksum_none_assert(skb);
4708
4709                 skb->protocol = eth_type_trans(skb, tp->dev);
4710
4711                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4712                     skb->protocol != htons(ETH_P_8021Q)) {
4713                         dev_kfree_skb(skb);
4714                         goto next_pkt;
4715                 }
4716
4717                 if (desc->type_flags & RXD_FLAG_VLAN &&
4718                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
4719                         vtag = desc->err_vlan & RXD_VLAN_MASK;
4720 #if TG3_VLAN_TAG_USED
4721                         if (tp->vlgrp)
4722                                 hw_vlan = true;
4723                         else
4724 #endif
4725                         {
4726                                 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
4727                                                     __skb_push(skb, VLAN_HLEN);
4728
4729                                 memmove(ve, skb->data + VLAN_HLEN,
4730                                         ETH_ALEN * 2);
4731                                 ve->h_vlan_proto = htons(ETH_P_8021Q);
4732                                 ve->h_vlan_TCI = htons(vtag);
4733                         }
4734                 }
4735
4736 #if TG3_VLAN_TAG_USED
4737                 if (hw_vlan)
4738                         vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
4739                 else
4740 #endif
4741                         napi_gro_receive(&tnapi->napi, skb);
4742
4743                 received++;
4744                 budget--;
4745
4746 next_pkt:
4747                 (*post_ptr)++;
4748
4749                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4750                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4751                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4752                                      tpr->rx_std_prod_idx);
4753                         work_mask &= ~RXD_OPAQUE_RING_STD;
4754                         rx_std_posted = 0;
4755                 }
4756 next_pkt_nopost:
4757                 sw_idx++;
4758                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4759
4760                 /* Refresh hw_idx to see if there is new work */
4761                 if (sw_idx == hw_idx) {
4762                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4763                         rmb();
4764                 }
4765         }
4766
4767         /* ACK the status ring. */
4768         tnapi->rx_rcb_ptr = sw_idx;
4769         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4770
4771         /* Refill RX ring(s). */
4772         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4773                 if (work_mask & RXD_OPAQUE_RING_STD) {
4774                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4775                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4776                                      tpr->rx_std_prod_idx);
4777                 }
4778                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4779                         tpr->rx_jmb_prod_idx = jmb_prod_idx %
4780                                                TG3_RX_JUMBO_RING_SIZE;
4781                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4782                                      tpr->rx_jmb_prod_idx);
4783                 }
4784                 mmiowb();
4785         } else if (work_mask) {
4786                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4787                  * updated before the producer indices can be updated.
4788                  */
4789                 smp_wmb();
4790
4791                 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4792                 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4793
4794                 if (tnapi != &tp->napi[1])
4795                         napi_schedule(&tp->napi[1].napi);
4796         }
4797
4798         return received;
4799 }
4800
4801 static void tg3_poll_link(struct tg3 *tp)
4802 {
4803         /* handle link change and other phy events */
4804         if (!(tp->tg3_flags &
4805               (TG3_FLAG_USE_LINKCHG_REG |
4806                TG3_FLAG_POLL_SERDES))) {
4807                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4808
4809                 if (sblk->status & SD_STATUS_LINK_CHG) {
4810                         sblk->status = SD_STATUS_UPDATED |
4811                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4812                         spin_lock(&tp->lock);
4813                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4814                                 tw32_f(MAC_STATUS,
4815                                      (MAC_STATUS_SYNC_CHANGED |
4816                                       MAC_STATUS_CFG_CHANGED |
4817                                       MAC_STATUS_MI_COMPLETION |
4818                                       MAC_STATUS_LNKSTATE_CHANGED));
4819                                 udelay(40);
4820                         } else
4821                                 tg3_setup_phy(tp, 0);
4822                         spin_unlock(&tp->lock);
4823                 }
4824         }
4825 }
4826
4827 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4828                                 struct tg3_rx_prodring_set *dpr,
4829                                 struct tg3_rx_prodring_set *spr)
4830 {
4831         u32 si, di, cpycnt, src_prod_idx;
4832         int i, err = 0;
4833
4834         while (1) {
4835                 src_prod_idx = spr->rx_std_prod_idx;
4836
4837                 /* Make sure updates to the rx_std_buffers[] entries and the
4838                  * standard producer index are seen in the correct order.
4839                  */
4840                 smp_rmb();
4841
4842                 if (spr->rx_std_cons_idx == src_prod_idx)
4843                         break;
4844
4845                 if (spr->rx_std_cons_idx < src_prod_idx)
4846                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4847                 else
4848                         cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4849
4850                 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4851
4852                 si = spr->rx_std_cons_idx;
4853                 di = dpr->rx_std_prod_idx;
4854
4855                 for (i = di; i < di + cpycnt; i++) {
4856                         if (dpr->rx_std_buffers[i].skb) {
4857                                 cpycnt = i - di;
4858                                 err = -ENOSPC;
4859                                 break;
4860                         }
4861                 }
4862
4863                 if (!cpycnt)
4864                         break;
4865
4866                 /* Ensure that updates to the rx_std_buffers ring and the
4867                  * shadowed hardware producer ring from tg3_recycle_skb() are
4868                  * ordered correctly WRT the skb check above.
4869                  */
4870                 smp_rmb();
4871
4872                 memcpy(&dpr->rx_std_buffers[di],
4873                        &spr->rx_std_buffers[si],
4874                        cpycnt * sizeof(struct ring_info));
4875
4876                 for (i = 0; i < cpycnt; i++, di++, si++) {
4877                         struct tg3_rx_buffer_desc *sbd, *dbd;
4878                         sbd = &spr->rx_std[si];
4879                         dbd = &dpr->rx_std[di];
4880                         dbd->addr_hi = sbd->addr_hi;
4881                         dbd->addr_lo = sbd->addr_lo;
4882                 }
4883
4884                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4885                                        TG3_RX_RING_SIZE;
4886                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4887                                        TG3_RX_RING_SIZE;
4888         }
4889
4890         while (1) {
4891                 src_prod_idx = spr->rx_jmb_prod_idx;
4892
4893                 /* Make sure updates to the rx_jmb_buffers[] entries and
4894                  * the jumbo producer index are seen in the correct order.
4895                  */
4896                 smp_rmb();
4897
4898                 if (spr->rx_jmb_cons_idx == src_prod_idx)
4899                         break;
4900
4901                 if (spr->rx_jmb_cons_idx < src_prod_idx)
4902                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4903                 else
4904                         cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4905
4906                 cpycnt = min(cpycnt,
4907                              TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4908
4909                 si = spr->rx_jmb_cons_idx;
4910                 di = dpr->rx_jmb_prod_idx;
4911
4912                 for (i = di; i < di + cpycnt; i++) {
4913                         if (dpr->rx_jmb_buffers[i].skb) {
4914                                 cpycnt = i - di;
4915                                 err = -ENOSPC;
4916                                 break;
4917                         }
4918                 }
4919
4920                 if (!cpycnt)
4921                         break;
4922
4923                 /* Ensure that updates to the rx_jmb_buffers ring and the
4924                  * shadowed hardware producer ring from tg3_recycle_skb() are
4925                  * ordered correctly WRT the skb check above.
4926                  */
4927                 smp_rmb();
4928
4929                 memcpy(&dpr->rx_jmb_buffers[di],
4930                        &spr->rx_jmb_buffers[si],
4931                        cpycnt * sizeof(struct ring_info));
4932
4933                 for (i = 0; i < cpycnt; i++, di++, si++) {
4934                         struct tg3_rx_buffer_desc *sbd, *dbd;
4935                         sbd = &spr->rx_jmb[si].std;
4936                         dbd = &dpr->rx_jmb[di].std;
4937                         dbd->addr_hi = sbd->addr_hi;
4938                         dbd->addr_lo = sbd->addr_lo;
4939                 }
4940
4941                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4942                                        TG3_RX_JUMBO_RING_SIZE;
4943                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4944                                        TG3_RX_JUMBO_RING_SIZE;
4945         }
4946
4947         return err;
4948 }
4949
4950 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4951 {
4952         struct tg3 *tp = tnapi->tp;
4953
4954         /* run TX completion thread */
4955         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4956                 tg3_tx(tnapi);
4957                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4958                         return work_done;
4959         }
4960
4961         /* run RX thread, within the bounds set by NAPI.
4962          * All RX "locking" is done by ensuring outside
4963          * code synchronizes with tg3->napi.poll()
4964          */
4965         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4966                 work_done += tg3_rx(tnapi, budget - work_done);
4967
4968         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4969                 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
4970                 int i, err = 0;
4971                 u32 std_prod_idx = dpr->rx_std_prod_idx;
4972                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
4973
4974                 for (i = 1; i < tp->irq_cnt; i++)
4975                         err |= tg3_rx_prodring_xfer(tp, dpr,
4976                                                     &tp->napi[i].prodring);
4977
4978                 wmb();
4979
4980                 if (std_prod_idx != dpr->rx_std_prod_idx)
4981                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4982                                      dpr->rx_std_prod_idx);
4983
4984                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
4985                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4986                                      dpr->rx_jmb_prod_idx);
4987
4988                 mmiowb();
4989
4990                 if (err)
4991                         tw32_f(HOSTCC_MODE, tp->coal_now);
4992         }
4993
4994         return work_done;
4995 }
4996
4997 static int tg3_poll_msix(struct napi_struct *napi, int budget)
4998 {
4999         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5000         struct tg3 *tp = tnapi->tp;
5001         int work_done = 0;
5002         struct tg3_hw_status *sblk = tnapi->hw_status;
5003
5004         while (1) {
5005                 work_done = tg3_poll_work(tnapi, work_done, budget);
5006
5007                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5008                         goto tx_recovery;
5009
5010                 if (unlikely(work_done >= budget))
5011                         break;
5012
5013                 /* tp->last_tag is used in tg3_int_reenable() below
5014                  * to tell the hw how much work has been processed,
5015                  * so we must read it before checking for more work.
5016                  */
5017                 tnapi->last_tag = sblk->status_tag;
5018                 tnapi->last_irq_tag = tnapi->last_tag;
5019                 rmb();
5020
5021                 /* check for RX/TX work to do */
5022                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5023                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5024                         napi_complete(napi);
5025                         /* Reenable interrupts. */
5026                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5027                         mmiowb();
5028                         break;
5029                 }
5030         }
5031
5032         return work_done;
5033
5034 tx_recovery:
5035         /* work_done is guaranteed to be less than budget. */
5036         napi_complete(napi);
5037         schedule_work(&tp->reset_task);
5038         return work_done;
5039 }
5040
5041 static int tg3_poll(struct napi_struct *napi, int budget)
5042 {
5043         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5044         struct tg3 *tp = tnapi->tp;
5045         int work_done = 0;
5046         struct tg3_hw_status *sblk = tnapi->hw_status;
5047
5048         while (1) {
5049                 tg3_poll_link(tp);
5050
5051                 work_done = tg3_poll_work(tnapi, work_done, budget);
5052
5053                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5054                         goto tx_recovery;
5055
5056                 if (unlikely(work_done >= budget))
5057                         break;
5058
5059                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5060                         /* tp->last_tag is used in tg3_int_reenable() below
5061                          * to tell the hw how much work has been processed,
5062                          * so we must read it before checking for more work.
5063                          */
5064                         tnapi->last_tag = sblk->status_tag;
5065                         tnapi->last_irq_tag = tnapi->last_tag;
5066                         rmb();
5067                 } else
5068                         sblk->status &= ~SD_STATUS_UPDATED;
5069
5070                 if (likely(!tg3_has_work(tnapi))) {
5071                         napi_complete(napi);
5072                         tg3_int_reenable(tnapi);
5073                         break;
5074                 }
5075         }
5076
5077         return work_done;
5078
5079 tx_recovery:
5080         /* work_done is guaranteed to be less than budget. */
5081         napi_complete(napi);
5082         schedule_work(&tp->reset_task);
5083         return work_done;
5084 }
5085
5086 static void tg3_irq_quiesce(struct tg3 *tp)
5087 {
5088         int i;
5089
5090         BUG_ON(tp->irq_sync);
5091
5092         tp->irq_sync = 1;
5093         smp_mb();
5094
5095         for (i = 0; i < tp->irq_cnt; i++)
5096                 synchronize_irq(tp->napi[i].irq_vec);
5097 }
5098
5099 static inline int tg3_irq_sync(struct tg3 *tp)
5100 {
5101         return tp->irq_sync;
5102 }
5103
5104 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5105  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5106  * with as well.  Most of the time, this is not necessary except when
5107  * shutting down the device.
5108  */
5109 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5110 {
5111         spin_lock_bh(&tp->lock);
5112         if (irq_sync)
5113                 tg3_irq_quiesce(tp);
5114 }
5115
5116 static inline void tg3_full_unlock(struct tg3 *tp)
5117 {
5118         spin_unlock_bh(&tp->lock);
5119 }
5120
5121 /* One-shot MSI handler - Chip automatically disables interrupt
5122  * after sending MSI so driver doesn't have to do it.
5123  */
5124 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5125 {
5126         struct tg3_napi *tnapi = dev_id;
5127         struct tg3 *tp = tnapi->tp;
5128
5129         prefetch(tnapi->hw_status);
5130         if (tnapi->rx_rcb)
5131                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5132
5133         if (likely(!tg3_irq_sync(tp)))
5134                 napi_schedule(&tnapi->napi);
5135
5136         return IRQ_HANDLED;
5137 }
5138
5139 /* MSI ISR - No need to check for interrupt sharing and no need to
5140  * flush status block and interrupt mailbox. PCI ordering rules
5141  * guarantee that MSI will arrive after the status block.
5142  */
5143 static irqreturn_t tg3_msi(int irq, void *dev_id)
5144 {
5145         struct tg3_napi *tnapi = dev_id;
5146         struct tg3 *tp = tnapi->tp;
5147
5148         prefetch(tnapi->hw_status);
5149         if (tnapi->rx_rcb)
5150                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5151         /*
5152          * Writing any value to intr-mbox-0 clears PCI INTA# and
5153          * chip-internal interrupt pending events.
5154          * Writing non-zero to intr-mbox-0 additional tells the
5155          * NIC to stop sending us irqs, engaging "in-intr-handler"
5156          * event coalescing.
5157          */
5158         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5159         if (likely(!tg3_irq_sync(tp)))
5160                 napi_schedule(&tnapi->napi);
5161
5162         return IRQ_RETVAL(1);
5163 }
5164
5165 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5166 {
5167         struct tg3_napi *tnapi = dev_id;
5168         struct tg3 *tp = tnapi->tp;
5169         struct tg3_hw_status *sblk = tnapi->hw_status;
5170         unsigned int handled = 1;
5171
5172         /* In INTx mode, it is possible for the interrupt to arrive at
5173          * the CPU before the status block posted prior to the interrupt.
5174          * Reading the PCI State register will confirm whether the
5175          * interrupt is ours and will flush the status block.
5176          */
5177         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5178                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5179                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5180                         handled = 0;
5181                         goto out;
5182                 }
5183         }
5184
5185         /*
5186          * Writing any value to intr-mbox-0 clears PCI INTA# and
5187          * chip-internal interrupt pending events.
5188          * Writing non-zero to intr-mbox-0 additional tells the
5189          * NIC to stop sending us irqs, engaging "in-intr-handler"
5190          * event coalescing.
5191          *
5192          * Flush the mailbox to de-assert the IRQ immediately to prevent
5193          * spurious interrupts.  The flush impacts performance but
5194          * excessive spurious interrupts can be worse in some cases.
5195          */
5196         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5197         if (tg3_irq_sync(tp))
5198                 goto out;
5199         sblk->status &= ~SD_STATUS_UPDATED;
5200         if (likely(tg3_has_work(tnapi))) {
5201                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5202                 napi_schedule(&tnapi->napi);
5203         } else {
5204                 /* No work, shared interrupt perhaps?  re-enable
5205                  * interrupts, and flush that PCI write
5206                  */
5207                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5208                                0x00000000);
5209         }
5210 out:
5211         return IRQ_RETVAL(handled);
5212 }
5213
5214 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5215 {
5216         struct tg3_napi *tnapi = dev_id;
5217         struct tg3 *tp = tnapi->tp;
5218         struct tg3_hw_status *sblk = tnapi->hw_status;
5219         unsigned int handled = 1;
5220
5221         /* In INTx mode, it is possible for the interrupt to arrive at
5222          * the CPU before the status block posted prior to the interrupt.
5223          * Reading the PCI State register will confirm whether the
5224          * interrupt is ours and will flush the status block.
5225          */
5226         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5227                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5228                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5229                         handled = 0;
5230                         goto out;
5231                 }
5232         }
5233
5234         /*
5235          * writing any value to intr-mbox-0 clears PCI INTA# and
5236          * chip-internal interrupt pending events.
5237          * writing non-zero to intr-mbox-0 additional tells the
5238          * NIC to stop sending us irqs, engaging "in-intr-handler"
5239          * event coalescing.
5240          *
5241          * Flush the mailbox to de-assert the IRQ immediately to prevent
5242          * spurious interrupts.  The flush impacts performance but
5243          * excessive spurious interrupts can be worse in some cases.
5244          */
5245         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5246
5247         /*
5248          * In a shared interrupt configuration, sometimes other devices'
5249          * interrupts will scream.  We record the current status tag here
5250          * so that the above check can report that the screaming interrupts
5251          * are unhandled.  Eventually they will be silenced.
5252          */
5253         tnapi->last_irq_tag = sblk->status_tag;
5254
5255         if (tg3_irq_sync(tp))
5256                 goto out;
5257
5258         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5259
5260         napi_schedule(&tnapi->napi);
5261
5262 out:
5263         return IRQ_RETVAL(handled);
5264 }
5265
5266 /* ISR for interrupt test */
5267 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5268 {
5269         struct tg3_napi *tnapi = dev_id;
5270         struct tg3 *tp = tnapi->tp;
5271         struct tg3_hw_status *sblk = tnapi->hw_status;
5272
5273         if ((sblk->status & SD_STATUS_UPDATED) ||
5274             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5275                 tg3_disable_ints(tp);
5276                 return IRQ_RETVAL(1);
5277         }
5278         return IRQ_RETVAL(0);
5279 }
5280
5281 static int tg3_init_hw(struct tg3 *, int);
5282 static int tg3_halt(struct tg3 *, int, int);
5283
5284 /* Restart hardware after configuration changes, self-test, etc.
5285  * Invoked with tp->lock held.
5286  */
5287 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5288         __releases(tp->lock)
5289         __acquires(tp->lock)
5290 {
5291         int err;
5292
5293         err = tg3_init_hw(tp, reset_phy);
5294         if (err) {
5295                 netdev_err(tp->dev,
5296                            "Failed to re-initialize device, aborting\n");
5297                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5298                 tg3_full_unlock(tp);
5299                 del_timer_sync(&tp->timer);
5300                 tp->irq_sync = 0;
5301                 tg3_napi_enable(tp);
5302                 dev_close(tp->dev);
5303                 tg3_full_lock(tp, 0);
5304         }
5305         return err;
5306 }
5307
5308 #ifdef CONFIG_NET_POLL_CONTROLLER
5309 static void tg3_poll_controller(struct net_device *dev)
5310 {
5311         int i;
5312         struct tg3 *tp = netdev_priv(dev);
5313
5314         for (i = 0; i < tp->irq_cnt; i++)
5315                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5316 }
5317 #endif
5318
5319 static void tg3_reset_task(struct work_struct *work)
5320 {
5321         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5322         int err;
5323         unsigned int restart_timer;
5324
5325         tg3_full_lock(tp, 0);
5326
5327         if (!netif_running(tp->dev)) {
5328                 tg3_full_unlock(tp);
5329                 return;
5330         }
5331
5332         tg3_full_unlock(tp);
5333
5334         tg3_phy_stop(tp);
5335
5336         tg3_netif_stop(tp);
5337
5338         tg3_full_lock(tp, 1);
5339
5340         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5341         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5342
5343         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5344                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5345                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5346                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5347                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5348         }
5349
5350         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5351         err = tg3_init_hw(tp, 1);
5352         if (err)
5353                 goto out;
5354
5355         tg3_netif_start(tp);
5356
5357         if (restart_timer)
5358                 mod_timer(&tp->timer, jiffies + 1);
5359
5360 out:
5361         tg3_full_unlock(tp);
5362
5363         if (!err)
5364                 tg3_phy_start(tp);
5365 }
5366
5367 static void tg3_dump_short_state(struct tg3 *tp)
5368 {
5369         netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5370                    tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5371         netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5372                    tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5373 }
5374
5375 static void tg3_tx_timeout(struct net_device *dev)
5376 {
5377         struct tg3 *tp = netdev_priv(dev);
5378
5379         if (netif_msg_tx_err(tp)) {
5380                 netdev_err(dev, "transmit timed out, resetting\n");
5381                 tg3_dump_short_state(tp);
5382         }
5383
5384         schedule_work(&tp->reset_task);
5385 }
5386
5387 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5388 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5389 {
5390         u32 base = (u32) mapping & 0xffffffff;
5391
5392         return (base > 0xffffdcc0) && (base + len + 8 < base);
5393 }
5394
5395 /* Test for DMA addresses > 40-bit */
5396 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5397                                           int len)
5398 {
5399 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5400         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5401                 return ((u64) mapping + len) > DMA_BIT_MASK(40);
5402         return 0;
5403 #else
5404         return 0;
5405 #endif
5406 }
5407
5408 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5409
5410 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5411 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5412                                        struct sk_buff *skb, u32 last_plus_one,
5413                                        u32 *start, u32 base_flags, u32 mss)
5414 {
5415         struct tg3 *tp = tnapi->tp;
5416         struct sk_buff *new_skb;
5417         dma_addr_t new_addr = 0;
5418         u32 entry = *start;
5419         int i, ret = 0;
5420
5421         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5422                 new_skb = skb_copy(skb, GFP_ATOMIC);
5423         else {
5424                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5425
5426                 new_skb = skb_copy_expand(skb,
5427                                           skb_headroom(skb) + more_headroom,
5428                                           skb_tailroom(skb), GFP_ATOMIC);
5429         }
5430
5431         if (!new_skb) {
5432                 ret = -1;
5433         } else {
5434                 /* New SKB is guaranteed to be linear. */
5435                 entry = *start;
5436                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5437                                           PCI_DMA_TODEVICE);
5438                 /* Make sure the mapping succeeded */
5439                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5440                         ret = -1;
5441                         dev_kfree_skb(new_skb);
5442                         new_skb = NULL;
5443
5444                 /* Make sure new skb does not cross any 4G boundaries.
5445                  * Drop the packet if it does.
5446                  */
5447                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5448                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5449                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5450                                          PCI_DMA_TODEVICE);
5451                         ret = -1;
5452                         dev_kfree_skb(new_skb);
5453                         new_skb = NULL;
5454                 } else {
5455                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5456                                     base_flags, 1 | (mss << 1));
5457                         *start = NEXT_TX(entry);
5458                 }
5459         }
5460
5461         /* Now clean up the sw ring entries. */
5462         i = 0;
5463         while (entry != last_plus_one) {
5464                 int len;
5465
5466                 if (i == 0)
5467                         len = skb_headlen(skb);
5468                 else
5469                         len = skb_shinfo(skb)->frags[i-1].size;
5470
5471                 pci_unmap_single(tp->pdev,
5472                                  dma_unmap_addr(&tnapi->tx_buffers[entry],
5473                                                 mapping),
5474                                  len, PCI_DMA_TODEVICE);
5475                 if (i == 0) {
5476                         tnapi->tx_buffers[entry].skb = new_skb;
5477                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5478                                            new_addr);
5479                 } else {
5480                         tnapi->tx_buffers[entry].skb = NULL;
5481                 }
5482                 entry = NEXT_TX(entry);
5483                 i++;
5484         }
5485
5486         dev_kfree_skb(skb);
5487
5488         return ret;
5489 }
5490
5491 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5492                         dma_addr_t mapping, int len, u32 flags,
5493                         u32 mss_and_is_end)
5494 {
5495         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5496         int is_end = (mss_and_is_end & 0x1);
5497         u32 mss = (mss_and_is_end >> 1);
5498         u32 vlan_tag = 0;
5499
5500         if (is_end)
5501                 flags |= TXD_FLAG_END;
5502         if (flags & TXD_FLAG_VLAN) {
5503                 vlan_tag = flags >> 16;
5504                 flags &= 0xffff;
5505         }
5506         vlan_tag |= (mss << TXD_MSS_SHIFT);
5507
5508         txd->addr_hi = ((u64) mapping >> 32);
5509         txd->addr_lo = ((u64) mapping & 0xffffffff);
5510         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5511         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5512 }
5513
5514 /* hard_start_xmit for devices that don't have any bugs and
5515  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5516  */
5517 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5518                                   struct net_device *dev)
5519 {
5520         struct tg3 *tp = netdev_priv(dev);
5521         u32 len, entry, base_flags, mss;
5522         dma_addr_t mapping;
5523         struct tg3_napi *tnapi;
5524         struct netdev_queue *txq;
5525         unsigned int i, last;
5526
5527         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5528         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5529         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5530                 tnapi++;
5531
5532         /* We are running in BH disabled context with netif_tx_lock
5533          * and TX reclaim runs via tp->napi.poll inside of a software
5534          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5535          * no IRQ context deadlocks to worry about either.  Rejoice!
5536          */
5537         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5538                 if (!netif_tx_queue_stopped(txq)) {
5539                         netif_tx_stop_queue(txq);
5540
5541                         /* This is a hard error, log it. */
5542                         netdev_err(dev,
5543                                    "BUG! Tx Ring full when queue awake!\n");
5544                 }
5545                 return NETDEV_TX_BUSY;
5546         }
5547
5548         entry = tnapi->tx_prod;
5549         base_flags = 0;
5550         mss = skb_shinfo(skb)->gso_size;
5551         if (mss) {
5552                 int tcp_opt_len, ip_tcp_len;
5553                 u32 hdrlen;
5554
5555                 if (skb_header_cloned(skb) &&
5556                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5557                         dev_kfree_skb(skb);
5558                         goto out_unlock;
5559                 }
5560
5561                 if (skb_is_gso_v6(skb)) {
5562                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5563                 } else {
5564                         struct iphdr *iph = ip_hdr(skb);
5565
5566                         tcp_opt_len = tcp_optlen(skb);
5567                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5568
5569                         iph->check = 0;
5570                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5571                         hdrlen = ip_tcp_len + tcp_opt_len;
5572                 }
5573
5574                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5575                         mss |= (hdrlen & 0xc) << 12;
5576                         if (hdrlen & 0x10)
5577                                 base_flags |= 0x00000010;
5578                         base_flags |= (hdrlen & 0x3e0) << 5;
5579                 } else
5580                         mss |= hdrlen << 9;
5581
5582                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5583                                TXD_FLAG_CPU_POST_DMA);
5584
5585                 tcp_hdr(skb)->check = 0;
5586
5587         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5588                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5589         }
5590
5591 #if TG3_VLAN_TAG_USED
5592         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5593                 base_flags |= (TXD_FLAG_VLAN |
5594                                (vlan_tx_tag_get(skb) << 16));
5595 #endif
5596
5597         len = skb_headlen(skb);
5598
5599         /* Queue skb data, a.k.a. the main skb fragment. */
5600         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5601         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5602                 dev_kfree_skb(skb);
5603                 goto out_unlock;
5604         }
5605
5606         tnapi->tx_buffers[entry].skb = skb;
5607         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5608
5609         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5610             !mss && skb->len > ETH_DATA_LEN)
5611                 base_flags |= TXD_FLAG_JMB_PKT;
5612
5613         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5614                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5615
5616         entry = NEXT_TX(entry);
5617
5618         /* Now loop through additional data fragments, and queue them. */
5619         if (skb_shinfo(skb)->nr_frags > 0) {
5620                 last = skb_shinfo(skb)->nr_frags - 1;
5621                 for (i = 0; i <= last; i++) {
5622                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5623
5624                         len = frag->size;
5625                         mapping = pci_map_page(tp->pdev,
5626                                                frag->page,
5627                                                frag->page_offset,
5628                                                len, PCI_DMA_TODEVICE);
5629                         if (pci_dma_mapping_error(tp->pdev, mapping))
5630                                 goto dma_error;
5631
5632                         tnapi->tx_buffers[entry].skb = NULL;
5633                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5634                                            mapping);
5635
5636                         tg3_set_txd(tnapi, entry, mapping, len,
5637                                     base_flags, (i == last) | (mss << 1));
5638
5639                         entry = NEXT_TX(entry);
5640                 }
5641         }
5642
5643         /* Packets are ready, update Tx producer idx local and on card. */
5644         tw32_tx_mbox(tnapi->prodmbox, entry);
5645
5646         tnapi->tx_prod = entry;
5647         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5648                 netif_tx_stop_queue(txq);
5649
5650                 /* netif_tx_stop_queue() must be done before checking
5651                  * checking tx index in tg3_tx_avail() below, because in
5652                  * tg3_tx(), we update tx index before checking for
5653                  * netif_tx_queue_stopped().
5654                  */
5655                 smp_mb();
5656                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5657                         netif_tx_wake_queue(txq);
5658         }
5659
5660 out_unlock:
5661         mmiowb();
5662
5663         return NETDEV_TX_OK;
5664
5665 dma_error:
5666         last = i;
5667         entry = tnapi->tx_prod;
5668         tnapi->tx_buffers[entry].skb = NULL;
5669         pci_unmap_single(tp->pdev,
5670                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5671                          skb_headlen(skb),
5672                          PCI_DMA_TODEVICE);
5673         for (i = 0; i <= last; i++) {
5674                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5675                 entry = NEXT_TX(entry);
5676
5677                 pci_unmap_page(tp->pdev,
5678                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5679                                               mapping),
5680                                frag->size, PCI_DMA_TODEVICE);
5681         }
5682
5683         dev_kfree_skb(skb);
5684         return NETDEV_TX_OK;
5685 }
5686
5687 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5688                                           struct net_device *);
5689
5690 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5691  * TSO header is greater than 80 bytes.
5692  */
5693 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5694 {
5695         struct sk_buff *segs, *nskb;
5696         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5697
5698         /* Estimate the number of fragments in the worst case */
5699         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5700                 netif_stop_queue(tp->dev);
5701
5702                 /* netif_tx_stop_queue() must be done before checking
5703                  * checking tx index in tg3_tx_avail() below, because in
5704                  * tg3_tx(), we update tx index before checking for
5705                  * netif_tx_queue_stopped().
5706                  */
5707                 smp_mb();
5708                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5709                         return NETDEV_TX_BUSY;
5710
5711                 netif_wake_queue(tp->dev);
5712         }
5713
5714         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5715         if (IS_ERR(segs))
5716                 goto tg3_tso_bug_end;
5717
5718         do {
5719                 nskb = segs;
5720                 segs = segs->next;
5721                 nskb->next = NULL;
5722                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5723         } while (segs);
5724
5725 tg3_tso_bug_end:
5726         dev_kfree_skb(skb);
5727
5728         return NETDEV_TX_OK;
5729 }
5730
5731 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5732  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5733  */
5734 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5735                                           struct net_device *dev)
5736 {
5737         struct tg3 *tp = netdev_priv(dev);
5738         u32 len, entry, base_flags, mss;
5739         int would_hit_hwbug;
5740         dma_addr_t mapping;
5741         struct tg3_napi *tnapi;
5742         struct netdev_queue *txq;
5743         unsigned int i, last;
5744
5745         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5746         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5747         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5748                 tnapi++;
5749
<