tg3: Allow single MSI-X vector allocations
[linux-2.6.git] / drivers / net / tg3.c
1 /*
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  * Copyright (C) 2005-2010 Broadcom Corporation.
8  *
9  * Firmware is:
10  *      Derived from proprietary unpublished source code,
11  *      Copyright (C) 2000-2003 Broadcom Corporation.
12  *
13  *      Permission is hereby granted for the distribution of this firmware
14  *      data in hexadecimal or equivalent format, provided this copyright
15  *      notice is accompanying it.
16  */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
26 #include <linux/in.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/phy.h>
36 #include <linux/brcmphy.h>
37 #include <linux/if_vlan.h>
38 #include <linux/ip.h>
39 #include <linux/tcp.h>
40 #include <linux/workqueue.h>
41 #include <linux/prefetch.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/firmware.h>
44
45 #include <net/checksum.h>
46 #include <net/ip.h>
47
48 #include <asm/system.h>
49 #include <asm/io.h>
50 #include <asm/byteorder.h>
51 #include <asm/uaccess.h>
52
53 #ifdef CONFIG_SPARC
54 #include <asm/idprom.h>
55 #include <asm/prom.h>
56 #endif
57
58 #define BAR_0   0
59 #define BAR_2   2
60
61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62 #define TG3_VLAN_TAG_USED 1
63 #else
64 #define TG3_VLAN_TAG_USED 0
65 #endif
66
67 #include "tg3.h"
68
69 #define DRV_MODULE_NAME         "tg3"
70 #define DRV_MODULE_VERSION      "3.110"
71 #define DRV_MODULE_RELDATE      "April 9, 2010"
72
73 #define TG3_DEF_MAC_MODE        0
74 #define TG3_DEF_RX_MODE         0
75 #define TG3_DEF_TX_MODE         0
76 #define TG3_DEF_MSG_ENABLE        \
77         (NETIF_MSG_DRV          | \
78          NETIF_MSG_PROBE        | \
79          NETIF_MSG_LINK         | \
80          NETIF_MSG_TIMER        | \
81          NETIF_MSG_IFDOWN       | \
82          NETIF_MSG_IFUP         | \
83          NETIF_MSG_RX_ERR       | \
84          NETIF_MSG_TX_ERR)
85
86 /* length of time before we decide the hardware is borked,
87  * and dev->tx_timeout() should be called to fix the problem
88  */
89 #define TG3_TX_TIMEOUT                  (5 * HZ)
90
91 /* hardware minimum and maximum for a single frame's data payload */
92 #define TG3_MIN_MTU                     60
93 #define TG3_MAX_MTU(tp) \
94         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
95
96 /* These numbers seem to be hard coded in the NIC firmware somehow.
97  * You can't change the ring sizes, but you can change where you place
98  * them in the NIC onboard memory.
99  */
100 #define TG3_RX_RING_SIZE                512
101 #define TG3_DEF_RX_RING_PENDING         200
102 #define TG3_RX_JUMBO_RING_SIZE          256
103 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
104 #define TG3_RSS_INDIR_TBL_SIZE          128
105
106 /* Do not place this n-ring entries value into the tp struct itself,
107  * we really want to expose these constants to GCC so that modulo et
108  * al.  operations are done with shifts and masks instead of with
109  * hw multiply/modulo instructions.  Another solution would be to
110  * replace things like '% foo' with '& (foo - 1)'.
111  */
112 #define TG3_RX_RCB_RING_SIZE(tp)        \
113         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
114           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
115
116 #define TG3_TX_RING_SIZE                512
117 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
118
119 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
120                                  TG3_RX_RING_SIZE)
121 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
122                                  TG3_RX_JUMBO_RING_SIZE)
123 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
124                                  TG3_RX_RCB_RING_SIZE(tp))
125 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
126                                  TG3_TX_RING_SIZE)
127 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
128
129 #define TG3_RX_DMA_ALIGN                16
130 #define TG3_RX_HEADROOM                 ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
131
132 #define TG3_DMA_BYTE_ENAB               64
133
134 #define TG3_RX_STD_DMA_SZ               1536
135 #define TG3_RX_JMB_DMA_SZ               9046
136
137 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
138
139 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
140 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
141
142 #define TG3_RX_STD_BUFF_RING_SIZE \
143         (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
144
145 #define TG3_RX_JMB_BUFF_RING_SIZE \
146         (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
147
148 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
149  * that are at least dword aligned when used in PCIX mode.  The driver
150  * works around this bug by double copying the packet.  This workaround
151  * is built into the normal double copy length check for efficiency.
152  *
153  * However, the double copy is only necessary on those architectures
154  * where unaligned memory accesses are inefficient.  For those architectures
155  * where unaligned memory accesses incur little penalty, we can reintegrate
156  * the 5701 in the normal rx path.  Doing so saves a device structure
157  * dereference by hardcoding the double copy threshold in place.
158  */
159 #define TG3_RX_COPY_THRESHOLD           256
160 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
161         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
162 #else
163         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
164 #endif
165
166 /* minimum number of free TX descriptors required to wake up TX process */
167 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
168
169 #define TG3_RAW_IP_ALIGN 2
170
171 /* number of ETHTOOL_GSTATS u64's */
172 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
173
174 #define TG3_NUM_TEST            6
175
176 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
177
178 #define FIRMWARE_TG3            "tigon/tg3.bin"
179 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
180 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
181
182 static char version[] __devinitdata =
183         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
184
185 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
186 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
187 MODULE_LICENSE("GPL");
188 MODULE_VERSION(DRV_MODULE_VERSION);
189 MODULE_FIRMWARE(FIRMWARE_TG3);
190 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
191 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
192
193 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
194 module_param(tg3_debug, int, 0);
195 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
196
197 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
268         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
269         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
270         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
271         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
272         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
273         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
274         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
275         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
276         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
277         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
278         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
279         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
280         {}
281 };
282
283 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
284
285 static const struct {
286         const char string[ETH_GSTRING_LEN];
287 } ethtool_stats_keys[TG3_NUM_STATS] = {
288         { "rx_octets" },
289         { "rx_fragments" },
290         { "rx_ucast_packets" },
291         { "rx_mcast_packets" },
292         { "rx_bcast_packets" },
293         { "rx_fcs_errors" },
294         { "rx_align_errors" },
295         { "rx_xon_pause_rcvd" },
296         { "rx_xoff_pause_rcvd" },
297         { "rx_mac_ctrl_rcvd" },
298         { "rx_xoff_entered" },
299         { "rx_frame_too_long_errors" },
300         { "rx_jabbers" },
301         { "rx_undersize_packets" },
302         { "rx_in_length_errors" },
303         { "rx_out_length_errors" },
304         { "rx_64_or_less_octet_packets" },
305         { "rx_65_to_127_octet_packets" },
306         { "rx_128_to_255_octet_packets" },
307         { "rx_256_to_511_octet_packets" },
308         { "rx_512_to_1023_octet_packets" },
309         { "rx_1024_to_1522_octet_packets" },
310         { "rx_1523_to_2047_octet_packets" },
311         { "rx_2048_to_4095_octet_packets" },
312         { "rx_4096_to_8191_octet_packets" },
313         { "rx_8192_to_9022_octet_packets" },
314
315         { "tx_octets" },
316         { "tx_collisions" },
317
318         { "tx_xon_sent" },
319         { "tx_xoff_sent" },
320         { "tx_flow_control" },
321         { "tx_mac_errors" },
322         { "tx_single_collisions" },
323         { "tx_mult_collisions" },
324         { "tx_deferred" },
325         { "tx_excessive_collisions" },
326         { "tx_late_collisions" },
327         { "tx_collide_2times" },
328         { "tx_collide_3times" },
329         { "tx_collide_4times" },
330         { "tx_collide_5times" },
331         { "tx_collide_6times" },
332         { "tx_collide_7times" },
333         { "tx_collide_8times" },
334         { "tx_collide_9times" },
335         { "tx_collide_10times" },
336         { "tx_collide_11times" },
337         { "tx_collide_12times" },
338         { "tx_collide_13times" },
339         { "tx_collide_14times" },
340         { "tx_collide_15times" },
341         { "tx_ucast_packets" },
342         { "tx_mcast_packets" },
343         { "tx_bcast_packets" },
344         { "tx_carrier_sense_errors" },
345         { "tx_discards" },
346         { "tx_errors" },
347
348         { "dma_writeq_full" },
349         { "dma_write_prioq_full" },
350         { "rxbds_empty" },
351         { "rx_discards" },
352         { "rx_errors" },
353         { "rx_threshold_hit" },
354
355         { "dma_readq_full" },
356         { "dma_read_prioq_full" },
357         { "tx_comp_queue_full" },
358
359         { "ring_set_send_prod_index" },
360         { "ring_status_update" },
361         { "nic_irqs" },
362         { "nic_avoided_irqs" },
363         { "nic_tx_threshold_hit" }
364 };
365
366 static const struct {
367         const char string[ETH_GSTRING_LEN];
368 } ethtool_test_keys[TG3_NUM_TEST] = {
369         { "nvram test     (online) " },
370         { "link test      (online) " },
371         { "register test  (offline)" },
372         { "memory test    (offline)" },
373         { "loopback test  (offline)" },
374         { "interrupt test (offline)" },
375 };
376
377 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
378 {
379         writel(val, tp->regs + off);
380 }
381
382 static u32 tg3_read32(struct tg3 *tp, u32 off)
383 {
384         return readl(tp->regs + off);
385 }
386
387 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
388 {
389         writel(val, tp->aperegs + off);
390 }
391
392 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
393 {
394         return readl(tp->aperegs + off);
395 }
396
397 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
398 {
399         unsigned long flags;
400
401         spin_lock_irqsave(&tp->indirect_lock, flags);
402         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
403         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
404         spin_unlock_irqrestore(&tp->indirect_lock, flags);
405 }
406
407 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
408 {
409         writel(val, tp->regs + off);
410         readl(tp->regs + off);
411 }
412
413 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
414 {
415         unsigned long flags;
416         u32 val;
417
418         spin_lock_irqsave(&tp->indirect_lock, flags);
419         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
420         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
421         spin_unlock_irqrestore(&tp->indirect_lock, flags);
422         return val;
423 }
424
425 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
426 {
427         unsigned long flags;
428
429         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
430                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
431                                        TG3_64BIT_REG_LOW, val);
432                 return;
433         }
434         if (off == TG3_RX_STD_PROD_IDX_REG) {
435                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
436                                        TG3_64BIT_REG_LOW, val);
437                 return;
438         }
439
440         spin_lock_irqsave(&tp->indirect_lock, flags);
441         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
442         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
443         spin_unlock_irqrestore(&tp->indirect_lock, flags);
444
445         /* In indirect mode when disabling interrupts, we also need
446          * to clear the interrupt bit in the GRC local ctrl register.
447          */
448         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
449             (val == 0x1)) {
450                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
451                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
452         }
453 }
454
455 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
456 {
457         unsigned long flags;
458         u32 val;
459
460         spin_lock_irqsave(&tp->indirect_lock, flags);
461         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
462         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
463         spin_unlock_irqrestore(&tp->indirect_lock, flags);
464         return val;
465 }
466
467 /* usec_wait specifies the wait time in usec when writing to certain registers
468  * where it is unsafe to read back the register without some delay.
469  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
470  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
471  */
472 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
473 {
474         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
475             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
476                 /* Non-posted methods */
477                 tp->write32(tp, off, val);
478         else {
479                 /* Posted method */
480                 tg3_write32(tp, off, val);
481                 if (usec_wait)
482                         udelay(usec_wait);
483                 tp->read32(tp, off);
484         }
485         /* Wait again after the read for the posted method to guarantee that
486          * the wait time is met.
487          */
488         if (usec_wait)
489                 udelay(usec_wait);
490 }
491
492 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
493 {
494         tp->write32_mbox(tp, off, val);
495         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
496             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
497                 tp->read32_mbox(tp, off);
498 }
499
500 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
501 {
502         void __iomem *mbox = tp->regs + off;
503         writel(val, mbox);
504         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
505                 writel(val, mbox);
506         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
507                 readl(mbox);
508 }
509
510 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
511 {
512         return readl(tp->regs + off + GRCMBOX_BASE);
513 }
514
515 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
516 {
517         writel(val, tp->regs + off + GRCMBOX_BASE);
518 }
519
520 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
521 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
522 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
523 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
524 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
525
526 #define tw32(reg, val)                  tp->write32(tp, reg, val)
527 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
528 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
529 #define tr32(reg)                       tp->read32(tp, reg)
530
531 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
532 {
533         unsigned long flags;
534
535         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
536             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
537                 return;
538
539         spin_lock_irqsave(&tp->indirect_lock, flags);
540         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
541                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
542                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
543
544                 /* Always leave this as zero. */
545                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
546         } else {
547                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
548                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
549
550                 /* Always leave this as zero. */
551                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
552         }
553         spin_unlock_irqrestore(&tp->indirect_lock, flags);
554 }
555
556 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
557 {
558         unsigned long flags;
559
560         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
561             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
562                 *val = 0;
563                 return;
564         }
565
566         spin_lock_irqsave(&tp->indirect_lock, flags);
567         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
568                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
569                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
570
571                 /* Always leave this as zero. */
572                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
573         } else {
574                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
575                 *val = tr32(TG3PCI_MEM_WIN_DATA);
576
577                 /* Always leave this as zero. */
578                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
579         }
580         spin_unlock_irqrestore(&tp->indirect_lock, flags);
581 }
582
583 static void tg3_ape_lock_init(struct tg3 *tp)
584 {
585         int i;
586         u32 regbase;
587
588         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
589                 regbase = TG3_APE_LOCK_GRANT;
590         else
591                 regbase = TG3_APE_PER_LOCK_GRANT;
592
593         /* Make sure the driver hasn't any stale locks. */
594         for (i = 0; i < 8; i++)
595                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
596 }
597
598 static int tg3_ape_lock(struct tg3 *tp, int locknum)
599 {
600         int i, off;
601         int ret = 0;
602         u32 status, req, gnt;
603
604         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
605                 return 0;
606
607         switch (locknum) {
608         case TG3_APE_LOCK_GRC:
609         case TG3_APE_LOCK_MEM:
610                 break;
611         default:
612                 return -EINVAL;
613         }
614
615         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
616                 req = TG3_APE_LOCK_REQ;
617                 gnt = TG3_APE_LOCK_GRANT;
618         } else {
619                 req = TG3_APE_PER_LOCK_REQ;
620                 gnt = TG3_APE_PER_LOCK_GRANT;
621         }
622
623         off = 4 * locknum;
624
625         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
626
627         /* Wait for up to 1 millisecond to acquire lock. */
628         for (i = 0; i < 100; i++) {
629                 status = tg3_ape_read32(tp, gnt + off);
630                 if (status == APE_LOCK_GRANT_DRIVER)
631                         break;
632                 udelay(10);
633         }
634
635         if (status != APE_LOCK_GRANT_DRIVER) {
636                 /* Revoke the lock request. */
637                 tg3_ape_write32(tp, gnt + off,
638                                 APE_LOCK_GRANT_DRIVER);
639
640                 ret = -EBUSY;
641         }
642
643         return ret;
644 }
645
646 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
647 {
648         u32 gnt;
649
650         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
651                 return;
652
653         switch (locknum) {
654         case TG3_APE_LOCK_GRC:
655         case TG3_APE_LOCK_MEM:
656                 break;
657         default:
658                 return;
659         }
660
661         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
662                 gnt = TG3_APE_LOCK_GRANT;
663         else
664                 gnt = TG3_APE_PER_LOCK_GRANT;
665
666         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
667 }
668
669 static void tg3_disable_ints(struct tg3 *tp)
670 {
671         int i;
672
673         tw32(TG3PCI_MISC_HOST_CTRL,
674              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
675         for (i = 0; i < tp->irq_max; i++)
676                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
677 }
678
679 static void tg3_enable_ints(struct tg3 *tp)
680 {
681         int i;
682
683         tp->irq_sync = 0;
684         wmb();
685
686         tw32(TG3PCI_MISC_HOST_CTRL,
687              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
688
689         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
690         for (i = 0; i < tp->irq_cnt; i++) {
691                 struct tg3_napi *tnapi = &tp->napi[i];
692
693                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
694                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
695                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
696
697                 tp->coal_now |= tnapi->coal_now;
698         }
699
700         /* Force an initial interrupt */
701         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
702             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
703                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
704         else
705                 tw32(HOSTCC_MODE, tp->coal_now);
706
707         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
708 }
709
710 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
711 {
712         struct tg3 *tp = tnapi->tp;
713         struct tg3_hw_status *sblk = tnapi->hw_status;
714         unsigned int work_exists = 0;
715
716         /* check for phy events */
717         if (!(tp->tg3_flags &
718               (TG3_FLAG_USE_LINKCHG_REG |
719                TG3_FLAG_POLL_SERDES))) {
720                 if (sblk->status & SD_STATUS_LINK_CHG)
721                         work_exists = 1;
722         }
723         /* check for RX/TX work to do */
724         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
725             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
726                 work_exists = 1;
727
728         return work_exists;
729 }
730
731 /* tg3_int_reenable
732  *  similar to tg3_enable_ints, but it accurately determines whether there
733  *  is new work pending and can return without flushing the PIO write
734  *  which reenables interrupts
735  */
736 static void tg3_int_reenable(struct tg3_napi *tnapi)
737 {
738         struct tg3 *tp = tnapi->tp;
739
740         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
741         mmiowb();
742
743         /* When doing tagged status, this work check is unnecessary.
744          * The last_tag we write above tells the chip which piece of
745          * work we've completed.
746          */
747         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
748             tg3_has_work(tnapi))
749                 tw32(HOSTCC_MODE, tp->coalesce_mode |
750                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
751 }
752
753 static void tg3_napi_disable(struct tg3 *tp)
754 {
755         int i;
756
757         for (i = tp->irq_cnt - 1; i >= 0; i--)
758                 napi_disable(&tp->napi[i].napi);
759 }
760
761 static void tg3_napi_enable(struct tg3 *tp)
762 {
763         int i;
764
765         for (i = 0; i < tp->irq_cnt; i++)
766                 napi_enable(&tp->napi[i].napi);
767 }
768
769 static inline void tg3_netif_stop(struct tg3 *tp)
770 {
771         tp->dev->trans_start = jiffies; /* prevent tx timeout */
772         tg3_napi_disable(tp);
773         netif_tx_disable(tp->dev);
774 }
775
776 static inline void tg3_netif_start(struct tg3 *tp)
777 {
778         /* NOTE: unconditional netif_tx_wake_all_queues is only
779          * appropriate so long as all callers are assured to
780          * have free tx slots (such as after tg3_init_hw)
781          */
782         netif_tx_wake_all_queues(tp->dev);
783
784         tg3_napi_enable(tp);
785         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
786         tg3_enable_ints(tp);
787 }
788
789 static void tg3_switch_clocks(struct tg3 *tp)
790 {
791         u32 clock_ctrl;
792         u32 orig_clock_ctrl;
793
794         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
795             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
796                 return;
797
798         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
799
800         orig_clock_ctrl = clock_ctrl;
801         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
802                        CLOCK_CTRL_CLKRUN_OENABLE |
803                        0x1f);
804         tp->pci_clock_ctrl = clock_ctrl;
805
806         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
807                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
808                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
809                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
810                 }
811         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
812                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
813                             clock_ctrl |
814                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
815                             40);
816                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
817                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
818                             40);
819         }
820         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
821 }
822
823 #define PHY_BUSY_LOOPS  5000
824
825 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
826 {
827         u32 frame_val;
828         unsigned int loops;
829         int ret;
830
831         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
832                 tw32_f(MAC_MI_MODE,
833                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
834                 udelay(80);
835         }
836
837         *val = 0x0;
838
839         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
840                       MI_COM_PHY_ADDR_MASK);
841         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
842                       MI_COM_REG_ADDR_MASK);
843         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
844
845         tw32_f(MAC_MI_COM, frame_val);
846
847         loops = PHY_BUSY_LOOPS;
848         while (loops != 0) {
849                 udelay(10);
850                 frame_val = tr32(MAC_MI_COM);
851
852                 if ((frame_val & MI_COM_BUSY) == 0) {
853                         udelay(5);
854                         frame_val = tr32(MAC_MI_COM);
855                         break;
856                 }
857                 loops -= 1;
858         }
859
860         ret = -EBUSY;
861         if (loops != 0) {
862                 *val = frame_val & MI_COM_DATA_MASK;
863                 ret = 0;
864         }
865
866         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
867                 tw32_f(MAC_MI_MODE, tp->mi_mode);
868                 udelay(80);
869         }
870
871         return ret;
872 }
873
874 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
875 {
876         u32 frame_val;
877         unsigned int loops;
878         int ret;
879
880         if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
881             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
882                 return 0;
883
884         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
885                 tw32_f(MAC_MI_MODE,
886                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
887                 udelay(80);
888         }
889
890         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
891                       MI_COM_PHY_ADDR_MASK);
892         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
893                       MI_COM_REG_ADDR_MASK);
894         frame_val |= (val & MI_COM_DATA_MASK);
895         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
896
897         tw32_f(MAC_MI_COM, frame_val);
898
899         loops = PHY_BUSY_LOOPS;
900         while (loops != 0) {
901                 udelay(10);
902                 frame_val = tr32(MAC_MI_COM);
903                 if ((frame_val & MI_COM_BUSY) == 0) {
904                         udelay(5);
905                         frame_val = tr32(MAC_MI_COM);
906                         break;
907                 }
908                 loops -= 1;
909         }
910
911         ret = -EBUSY;
912         if (loops != 0)
913                 ret = 0;
914
915         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
916                 tw32_f(MAC_MI_MODE, tp->mi_mode);
917                 udelay(80);
918         }
919
920         return ret;
921 }
922
923 static int tg3_bmcr_reset(struct tg3 *tp)
924 {
925         u32 phy_control;
926         int limit, err;
927
928         /* OK, reset it, and poll the BMCR_RESET bit until it
929          * clears or we time out.
930          */
931         phy_control = BMCR_RESET;
932         err = tg3_writephy(tp, MII_BMCR, phy_control);
933         if (err != 0)
934                 return -EBUSY;
935
936         limit = 5000;
937         while (limit--) {
938                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
939                 if (err != 0)
940                         return -EBUSY;
941
942                 if ((phy_control & BMCR_RESET) == 0) {
943                         udelay(40);
944                         break;
945                 }
946                 udelay(10);
947         }
948         if (limit < 0)
949                 return -EBUSY;
950
951         return 0;
952 }
953
954 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
955 {
956         struct tg3 *tp = bp->priv;
957         u32 val;
958
959         spin_lock_bh(&tp->lock);
960
961         if (tg3_readphy(tp, reg, &val))
962                 val = -EIO;
963
964         spin_unlock_bh(&tp->lock);
965
966         return val;
967 }
968
969 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
970 {
971         struct tg3 *tp = bp->priv;
972         u32 ret = 0;
973
974         spin_lock_bh(&tp->lock);
975
976         if (tg3_writephy(tp, reg, val))
977                 ret = -EIO;
978
979         spin_unlock_bh(&tp->lock);
980
981         return ret;
982 }
983
984 static int tg3_mdio_reset(struct mii_bus *bp)
985 {
986         return 0;
987 }
988
989 static void tg3_mdio_config_5785(struct tg3 *tp)
990 {
991         u32 val;
992         struct phy_device *phydev;
993
994         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
995         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
996         case PHY_ID_BCM50610:
997         case PHY_ID_BCM50610M:
998                 val = MAC_PHYCFG2_50610_LED_MODES;
999                 break;
1000         case PHY_ID_BCMAC131:
1001                 val = MAC_PHYCFG2_AC131_LED_MODES;
1002                 break;
1003         case PHY_ID_RTL8211C:
1004                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1005                 break;
1006         case PHY_ID_RTL8201E:
1007                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1008                 break;
1009         default:
1010                 return;
1011         }
1012
1013         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1014                 tw32(MAC_PHYCFG2, val);
1015
1016                 val = tr32(MAC_PHYCFG1);
1017                 val &= ~(MAC_PHYCFG1_RGMII_INT |
1018                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1019                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1020                 tw32(MAC_PHYCFG1, val);
1021
1022                 return;
1023         }
1024
1025         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
1026                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1027                        MAC_PHYCFG2_FMODE_MASK_MASK |
1028                        MAC_PHYCFG2_GMODE_MASK_MASK |
1029                        MAC_PHYCFG2_ACT_MASK_MASK   |
1030                        MAC_PHYCFG2_QUAL_MASK_MASK |
1031                        MAC_PHYCFG2_INBAND_ENABLE;
1032
1033         tw32(MAC_PHYCFG2, val);
1034
1035         val = tr32(MAC_PHYCFG1);
1036         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1037                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1038         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1039                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1040                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1041                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1042                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1043         }
1044         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1045                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1046         tw32(MAC_PHYCFG1, val);
1047
1048         val = tr32(MAC_EXT_RGMII_MODE);
1049         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1050                  MAC_RGMII_MODE_RX_QUALITY |
1051                  MAC_RGMII_MODE_RX_ACTIVITY |
1052                  MAC_RGMII_MODE_RX_ENG_DET |
1053                  MAC_RGMII_MODE_TX_ENABLE |
1054                  MAC_RGMII_MODE_TX_LOWPWR |
1055                  MAC_RGMII_MODE_TX_RESET);
1056         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1057                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1058                         val |= MAC_RGMII_MODE_RX_INT_B |
1059                                MAC_RGMII_MODE_RX_QUALITY |
1060                                MAC_RGMII_MODE_RX_ACTIVITY |
1061                                MAC_RGMII_MODE_RX_ENG_DET;
1062                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1063                         val |= MAC_RGMII_MODE_TX_ENABLE |
1064                                MAC_RGMII_MODE_TX_LOWPWR |
1065                                MAC_RGMII_MODE_TX_RESET;
1066         }
1067         tw32(MAC_EXT_RGMII_MODE, val);
1068 }
1069
1070 static void tg3_mdio_start(struct tg3 *tp)
1071 {
1072         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1073         tw32_f(MAC_MI_MODE, tp->mi_mode);
1074         udelay(80);
1075
1076         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1077             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1078                 tg3_mdio_config_5785(tp);
1079 }
1080
1081 static int tg3_mdio_init(struct tg3 *tp)
1082 {
1083         int i;
1084         u32 reg;
1085         struct phy_device *phydev;
1086
1087         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1088                 u32 funcnum, is_serdes;
1089
1090                 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1091                 if (funcnum)
1092                         tp->phy_addr = 2;
1093                 else
1094                         tp->phy_addr = 1;
1095
1096                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1097                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1098                 else
1099                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1100                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1101                 if (is_serdes)
1102                         tp->phy_addr += 7;
1103         } else
1104                 tp->phy_addr = TG3_PHY_MII_ADDR;
1105
1106         tg3_mdio_start(tp);
1107
1108         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1109             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1110                 return 0;
1111
1112         tp->mdio_bus = mdiobus_alloc();
1113         if (tp->mdio_bus == NULL)
1114                 return -ENOMEM;
1115
1116         tp->mdio_bus->name     = "tg3 mdio bus";
1117         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1118                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1119         tp->mdio_bus->priv     = tp;
1120         tp->mdio_bus->parent   = &tp->pdev->dev;
1121         tp->mdio_bus->read     = &tg3_mdio_read;
1122         tp->mdio_bus->write    = &tg3_mdio_write;
1123         tp->mdio_bus->reset    = &tg3_mdio_reset;
1124         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1125         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1126
1127         for (i = 0; i < PHY_MAX_ADDR; i++)
1128                 tp->mdio_bus->irq[i] = PHY_POLL;
1129
1130         /* The bus registration will look for all the PHYs on the mdio bus.
1131          * Unfortunately, it does not ensure the PHY is powered up before
1132          * accessing the PHY ID registers.  A chip reset is the
1133          * quickest way to bring the device back to an operational state..
1134          */
1135         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1136                 tg3_bmcr_reset(tp);
1137
1138         i = mdiobus_register(tp->mdio_bus);
1139         if (i) {
1140                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1141                 mdiobus_free(tp->mdio_bus);
1142                 return i;
1143         }
1144
1145         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1146
1147         if (!phydev || !phydev->drv) {
1148                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1149                 mdiobus_unregister(tp->mdio_bus);
1150                 mdiobus_free(tp->mdio_bus);
1151                 return -ENODEV;
1152         }
1153
1154         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1155         case PHY_ID_BCM57780:
1156                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1157                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1158                 break;
1159         case PHY_ID_BCM50610:
1160         case PHY_ID_BCM50610M:
1161                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1162                                      PHY_BRCM_RX_REFCLK_UNUSED |
1163                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1164                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1165                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1166                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1167                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1168                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1169                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1170                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1171                 /* fallthru */
1172         case PHY_ID_RTL8211C:
1173                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1174                 break;
1175         case PHY_ID_RTL8201E:
1176         case PHY_ID_BCMAC131:
1177                 phydev->interface = PHY_INTERFACE_MODE_MII;
1178                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1179                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1180                 break;
1181         }
1182
1183         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1184
1185         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1186                 tg3_mdio_config_5785(tp);
1187
1188         return 0;
1189 }
1190
1191 static void tg3_mdio_fini(struct tg3 *tp)
1192 {
1193         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1194                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1195                 mdiobus_unregister(tp->mdio_bus);
1196                 mdiobus_free(tp->mdio_bus);
1197         }
1198 }
1199
1200 /* tp->lock is held. */
1201 static inline void tg3_generate_fw_event(struct tg3 *tp)
1202 {
1203         u32 val;
1204
1205         val = tr32(GRC_RX_CPU_EVENT);
1206         val |= GRC_RX_CPU_DRIVER_EVENT;
1207         tw32_f(GRC_RX_CPU_EVENT, val);
1208
1209         tp->last_event_jiffies = jiffies;
1210 }
1211
1212 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1213
1214 /* tp->lock is held. */
1215 static void tg3_wait_for_event_ack(struct tg3 *tp)
1216 {
1217         int i;
1218         unsigned int delay_cnt;
1219         long time_remain;
1220
1221         /* If enough time has passed, no wait is necessary. */
1222         time_remain = (long)(tp->last_event_jiffies + 1 +
1223                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1224                       (long)jiffies;
1225         if (time_remain < 0)
1226                 return;
1227
1228         /* Check if we can shorten the wait time. */
1229         delay_cnt = jiffies_to_usecs(time_remain);
1230         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1231                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1232         delay_cnt = (delay_cnt >> 3) + 1;
1233
1234         for (i = 0; i < delay_cnt; i++) {
1235                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1236                         break;
1237                 udelay(8);
1238         }
1239 }
1240
1241 /* tp->lock is held. */
1242 static void tg3_ump_link_report(struct tg3 *tp)
1243 {
1244         u32 reg;
1245         u32 val;
1246
1247         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1248             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1249                 return;
1250
1251         tg3_wait_for_event_ack(tp);
1252
1253         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1254
1255         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1256
1257         val = 0;
1258         if (!tg3_readphy(tp, MII_BMCR, &reg))
1259                 val = reg << 16;
1260         if (!tg3_readphy(tp, MII_BMSR, &reg))
1261                 val |= (reg & 0xffff);
1262         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1263
1264         val = 0;
1265         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1266                 val = reg << 16;
1267         if (!tg3_readphy(tp, MII_LPA, &reg))
1268                 val |= (reg & 0xffff);
1269         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1270
1271         val = 0;
1272         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1273                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1274                         val = reg << 16;
1275                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1276                         val |= (reg & 0xffff);
1277         }
1278         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1279
1280         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1281                 val = reg << 16;
1282         else
1283                 val = 0;
1284         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1285
1286         tg3_generate_fw_event(tp);
1287 }
1288
1289 static void tg3_link_report(struct tg3 *tp)
1290 {
1291         if (!netif_carrier_ok(tp->dev)) {
1292                 netif_info(tp, link, tp->dev, "Link is down\n");
1293                 tg3_ump_link_report(tp);
1294         } else if (netif_msg_link(tp)) {
1295                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1296                             (tp->link_config.active_speed == SPEED_1000 ?
1297                              1000 :
1298                              (tp->link_config.active_speed == SPEED_100 ?
1299                               100 : 10)),
1300                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1301                              "full" : "half"));
1302
1303                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1304                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1305                             "on" : "off",
1306                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1307                             "on" : "off");
1308                 tg3_ump_link_report(tp);
1309         }
1310 }
1311
1312 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1313 {
1314         u16 miireg;
1315
1316         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1317                 miireg = ADVERTISE_PAUSE_CAP;
1318         else if (flow_ctrl & FLOW_CTRL_TX)
1319                 miireg = ADVERTISE_PAUSE_ASYM;
1320         else if (flow_ctrl & FLOW_CTRL_RX)
1321                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1322         else
1323                 miireg = 0;
1324
1325         return miireg;
1326 }
1327
1328 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1329 {
1330         u16 miireg;
1331
1332         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1333                 miireg = ADVERTISE_1000XPAUSE;
1334         else if (flow_ctrl & FLOW_CTRL_TX)
1335                 miireg = ADVERTISE_1000XPSE_ASYM;
1336         else if (flow_ctrl & FLOW_CTRL_RX)
1337                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1338         else
1339                 miireg = 0;
1340
1341         return miireg;
1342 }
1343
1344 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1345 {
1346         u8 cap = 0;
1347
1348         if (lcladv & ADVERTISE_1000XPAUSE) {
1349                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1350                         if (rmtadv & LPA_1000XPAUSE)
1351                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1352                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1353                                 cap = FLOW_CTRL_RX;
1354                 } else {
1355                         if (rmtadv & LPA_1000XPAUSE)
1356                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1357                 }
1358         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1359                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1360                         cap = FLOW_CTRL_TX;
1361         }
1362
1363         return cap;
1364 }
1365
1366 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1367 {
1368         u8 autoneg;
1369         u8 flowctrl = 0;
1370         u32 old_rx_mode = tp->rx_mode;
1371         u32 old_tx_mode = tp->tx_mode;
1372
1373         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1374                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1375         else
1376                 autoneg = tp->link_config.autoneg;
1377
1378         if (autoneg == AUTONEG_ENABLE &&
1379             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1380                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1381                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1382                 else
1383                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1384         } else
1385                 flowctrl = tp->link_config.flowctrl;
1386
1387         tp->link_config.active_flowctrl = flowctrl;
1388
1389         if (flowctrl & FLOW_CTRL_RX)
1390                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1391         else
1392                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1393
1394         if (old_rx_mode != tp->rx_mode)
1395                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1396
1397         if (flowctrl & FLOW_CTRL_TX)
1398                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1399         else
1400                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1401
1402         if (old_tx_mode != tp->tx_mode)
1403                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1404 }
1405
1406 static void tg3_adjust_link(struct net_device *dev)
1407 {
1408         u8 oldflowctrl, linkmesg = 0;
1409         u32 mac_mode, lcl_adv, rmt_adv;
1410         struct tg3 *tp = netdev_priv(dev);
1411         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1412
1413         spin_lock_bh(&tp->lock);
1414
1415         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1416                                     MAC_MODE_HALF_DUPLEX);
1417
1418         oldflowctrl = tp->link_config.active_flowctrl;
1419
1420         if (phydev->link) {
1421                 lcl_adv = 0;
1422                 rmt_adv = 0;
1423
1424                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1425                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1426                 else if (phydev->speed == SPEED_1000 ||
1427                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1428                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1429                 else
1430                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1431
1432                 if (phydev->duplex == DUPLEX_HALF)
1433                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1434                 else {
1435                         lcl_adv = tg3_advert_flowctrl_1000T(
1436                                   tp->link_config.flowctrl);
1437
1438                         if (phydev->pause)
1439                                 rmt_adv = LPA_PAUSE_CAP;
1440                         if (phydev->asym_pause)
1441                                 rmt_adv |= LPA_PAUSE_ASYM;
1442                 }
1443
1444                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1445         } else
1446                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1447
1448         if (mac_mode != tp->mac_mode) {
1449                 tp->mac_mode = mac_mode;
1450                 tw32_f(MAC_MODE, tp->mac_mode);
1451                 udelay(40);
1452         }
1453
1454         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1455                 if (phydev->speed == SPEED_10)
1456                         tw32(MAC_MI_STAT,
1457                              MAC_MI_STAT_10MBPS_MODE |
1458                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1459                 else
1460                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1461         }
1462
1463         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1464                 tw32(MAC_TX_LENGTHS,
1465                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1466                       (6 << TX_LENGTHS_IPG_SHIFT) |
1467                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1468         else
1469                 tw32(MAC_TX_LENGTHS,
1470                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1471                       (6 << TX_LENGTHS_IPG_SHIFT) |
1472                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1473
1474         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1475             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1476             phydev->speed != tp->link_config.active_speed ||
1477             phydev->duplex != tp->link_config.active_duplex ||
1478             oldflowctrl != tp->link_config.active_flowctrl)
1479                 linkmesg = 1;
1480
1481         tp->link_config.active_speed = phydev->speed;
1482         tp->link_config.active_duplex = phydev->duplex;
1483
1484         spin_unlock_bh(&tp->lock);
1485
1486         if (linkmesg)
1487                 tg3_link_report(tp);
1488 }
1489
1490 static int tg3_phy_init(struct tg3 *tp)
1491 {
1492         struct phy_device *phydev;
1493
1494         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1495                 return 0;
1496
1497         /* Bring the PHY back to a known state. */
1498         tg3_bmcr_reset(tp);
1499
1500         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1501
1502         /* Attach the MAC to the PHY. */
1503         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1504                              phydev->dev_flags, phydev->interface);
1505         if (IS_ERR(phydev)) {
1506                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1507                 return PTR_ERR(phydev);
1508         }
1509
1510         /* Mask with MAC supported features. */
1511         switch (phydev->interface) {
1512         case PHY_INTERFACE_MODE_GMII:
1513         case PHY_INTERFACE_MODE_RGMII:
1514                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1515                         phydev->supported &= (PHY_GBIT_FEATURES |
1516                                               SUPPORTED_Pause |
1517                                               SUPPORTED_Asym_Pause);
1518                         break;
1519                 }
1520                 /* fallthru */
1521         case PHY_INTERFACE_MODE_MII:
1522                 phydev->supported &= (PHY_BASIC_FEATURES |
1523                                       SUPPORTED_Pause |
1524                                       SUPPORTED_Asym_Pause);
1525                 break;
1526         default:
1527                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1528                 return -EINVAL;
1529         }
1530
1531         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1532
1533         phydev->advertising = phydev->supported;
1534
1535         return 0;
1536 }
1537
1538 static void tg3_phy_start(struct tg3 *tp)
1539 {
1540         struct phy_device *phydev;
1541
1542         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1543                 return;
1544
1545         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1546
1547         if (tp->link_config.phy_is_low_power) {
1548                 tp->link_config.phy_is_low_power = 0;
1549                 phydev->speed = tp->link_config.orig_speed;
1550                 phydev->duplex = tp->link_config.orig_duplex;
1551                 phydev->autoneg = tp->link_config.orig_autoneg;
1552                 phydev->advertising = tp->link_config.orig_advertising;
1553         }
1554
1555         phy_start(phydev);
1556
1557         phy_start_aneg(phydev);
1558 }
1559
1560 static void tg3_phy_stop(struct tg3 *tp)
1561 {
1562         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1563                 return;
1564
1565         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1566 }
1567
1568 static void tg3_phy_fini(struct tg3 *tp)
1569 {
1570         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1571                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1572                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1573         }
1574 }
1575
1576 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1577 {
1578         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1579         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1580 }
1581
1582 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1583 {
1584         u32 phytest;
1585
1586         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1587                 u32 phy;
1588
1589                 tg3_writephy(tp, MII_TG3_FET_TEST,
1590                              phytest | MII_TG3_FET_SHADOW_EN);
1591                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1592                         if (enable)
1593                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1594                         else
1595                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1596                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1597                 }
1598                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1599         }
1600 }
1601
1602 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1603 {
1604         u32 reg;
1605
1606         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1607                 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1608              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1609                 return;
1610
1611         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1612                 tg3_phy_fet_toggle_apd(tp, enable);
1613                 return;
1614         }
1615
1616         reg = MII_TG3_MISC_SHDW_WREN |
1617               MII_TG3_MISC_SHDW_SCR5_SEL |
1618               MII_TG3_MISC_SHDW_SCR5_LPED |
1619               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1620               MII_TG3_MISC_SHDW_SCR5_SDTL |
1621               MII_TG3_MISC_SHDW_SCR5_C125OE;
1622         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1623                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1624
1625         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1626
1627
1628         reg = MII_TG3_MISC_SHDW_WREN |
1629               MII_TG3_MISC_SHDW_APD_SEL |
1630               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1631         if (enable)
1632                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1633
1634         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1635 }
1636
1637 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1638 {
1639         u32 phy;
1640
1641         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1642             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1643                 return;
1644
1645         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1646                 u32 ephy;
1647
1648                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1649                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1650
1651                         tg3_writephy(tp, MII_TG3_FET_TEST,
1652                                      ephy | MII_TG3_FET_SHADOW_EN);
1653                         if (!tg3_readphy(tp, reg, &phy)) {
1654                                 if (enable)
1655                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1656                                 else
1657                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1658                                 tg3_writephy(tp, reg, phy);
1659                         }
1660                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1661                 }
1662         } else {
1663                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1664                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1665                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1666                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1667                         if (enable)
1668                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1669                         else
1670                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1671                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1672                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1673                 }
1674         }
1675 }
1676
1677 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1678 {
1679         u32 val;
1680
1681         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1682                 return;
1683
1684         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1685             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1686                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1687                              (val | (1 << 15) | (1 << 4)));
1688 }
1689
1690 static void tg3_phy_apply_otp(struct tg3 *tp)
1691 {
1692         u32 otp, phy;
1693
1694         if (!tp->phy_otp)
1695                 return;
1696
1697         otp = tp->phy_otp;
1698
1699         /* Enable SM_DSP clock and tx 6dB coding. */
1700         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1701               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1702               MII_TG3_AUXCTL_ACTL_TX_6DB;
1703         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1704
1705         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1706         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1707         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1708
1709         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1710               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1711         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1712
1713         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1714         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1715         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1716
1717         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1718         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1719
1720         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1721         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1722
1723         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1724               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1725         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1726
1727         /* Turn off SM_DSP clock. */
1728         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1729               MII_TG3_AUXCTL_ACTL_TX_6DB;
1730         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1731 }
1732
1733 static int tg3_wait_macro_done(struct tg3 *tp)
1734 {
1735         int limit = 100;
1736
1737         while (limit--) {
1738                 u32 tmp32;
1739
1740                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1741                         if ((tmp32 & 0x1000) == 0)
1742                                 break;
1743                 }
1744         }
1745         if (limit < 0)
1746                 return -EBUSY;
1747
1748         return 0;
1749 }
1750
1751 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1752 {
1753         static const u32 test_pat[4][6] = {
1754         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1755         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1756         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1757         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1758         };
1759         int chan;
1760
1761         for (chan = 0; chan < 4; chan++) {
1762                 int i;
1763
1764                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1765                              (chan * 0x2000) | 0x0200);
1766                 tg3_writephy(tp, 0x16, 0x0002);
1767
1768                 for (i = 0; i < 6; i++)
1769                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1770                                      test_pat[chan][i]);
1771
1772                 tg3_writephy(tp, 0x16, 0x0202);
1773                 if (tg3_wait_macro_done(tp)) {
1774                         *resetp = 1;
1775                         return -EBUSY;
1776                 }
1777
1778                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1779                              (chan * 0x2000) | 0x0200);
1780                 tg3_writephy(tp, 0x16, 0x0082);
1781                 if (tg3_wait_macro_done(tp)) {
1782                         *resetp = 1;
1783                         return -EBUSY;
1784                 }
1785
1786                 tg3_writephy(tp, 0x16, 0x0802);
1787                 if (tg3_wait_macro_done(tp)) {
1788                         *resetp = 1;
1789                         return -EBUSY;
1790                 }
1791
1792                 for (i = 0; i < 6; i += 2) {
1793                         u32 low, high;
1794
1795                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1796                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1797                             tg3_wait_macro_done(tp)) {
1798                                 *resetp = 1;
1799                                 return -EBUSY;
1800                         }
1801                         low &= 0x7fff;
1802                         high &= 0x000f;
1803                         if (low != test_pat[chan][i] ||
1804                             high != test_pat[chan][i+1]) {
1805                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1806                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1807                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1808
1809                                 return -EBUSY;
1810                         }
1811                 }
1812         }
1813
1814         return 0;
1815 }
1816
1817 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1818 {
1819         int chan;
1820
1821         for (chan = 0; chan < 4; chan++) {
1822                 int i;
1823
1824                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1825                              (chan * 0x2000) | 0x0200);
1826                 tg3_writephy(tp, 0x16, 0x0002);
1827                 for (i = 0; i < 6; i++)
1828                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1829                 tg3_writephy(tp, 0x16, 0x0202);
1830                 if (tg3_wait_macro_done(tp))
1831                         return -EBUSY;
1832         }
1833
1834         return 0;
1835 }
1836
1837 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1838 {
1839         u32 reg32, phy9_orig;
1840         int retries, do_phy_reset, err;
1841
1842         retries = 10;
1843         do_phy_reset = 1;
1844         do {
1845                 if (do_phy_reset) {
1846                         err = tg3_bmcr_reset(tp);
1847                         if (err)
1848                                 return err;
1849                         do_phy_reset = 0;
1850                 }
1851
1852                 /* Disable transmitter and interrupt.  */
1853                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1854                         continue;
1855
1856                 reg32 |= 0x3000;
1857                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1858
1859                 /* Set full-duplex, 1000 mbps.  */
1860                 tg3_writephy(tp, MII_BMCR,
1861                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1862
1863                 /* Set to master mode.  */
1864                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1865                         continue;
1866
1867                 tg3_writephy(tp, MII_TG3_CTRL,
1868                              (MII_TG3_CTRL_AS_MASTER |
1869                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1870
1871                 /* Enable SM_DSP_CLOCK and 6dB.  */
1872                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1873
1874                 /* Block the PHY control access.  */
1875                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1876                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1877
1878                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1879                 if (!err)
1880                         break;
1881         } while (--retries);
1882
1883         err = tg3_phy_reset_chanpat(tp);
1884         if (err)
1885                 return err;
1886
1887         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1888         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1889
1890         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1891         tg3_writephy(tp, 0x16, 0x0000);
1892
1893         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1894             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1895                 /* Set Extended packet length bit for jumbo frames */
1896                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1897         } else {
1898                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1899         }
1900
1901         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1902
1903         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1904                 reg32 &= ~0x3000;
1905                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1906         } else if (!err)
1907                 err = -EBUSY;
1908
1909         return err;
1910 }
1911
1912 /* This will reset the tigon3 PHY if there is no valid
1913  * link unless the FORCE argument is non-zero.
1914  */
1915 static int tg3_phy_reset(struct tg3 *tp)
1916 {
1917         u32 cpmuctrl;
1918         u32 phy_status;
1919         int err;
1920
1921         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1922                 u32 val;
1923
1924                 val = tr32(GRC_MISC_CFG);
1925                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1926                 udelay(40);
1927         }
1928         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1929         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1930         if (err != 0)
1931                 return -EBUSY;
1932
1933         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1934                 netif_carrier_off(tp->dev);
1935                 tg3_link_report(tp);
1936         }
1937
1938         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1939             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1940             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1941                 err = tg3_phy_reset_5703_4_5(tp);
1942                 if (err)
1943                         return err;
1944                 goto out;
1945         }
1946
1947         cpmuctrl = 0;
1948         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1949             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1950                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1951                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1952                         tw32(TG3_CPMU_CTRL,
1953                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1954         }
1955
1956         err = tg3_bmcr_reset(tp);
1957         if (err)
1958                 return err;
1959
1960         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1961                 u32 phy;
1962
1963                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1964                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1965
1966                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1967         }
1968
1969         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1970             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1971                 u32 val;
1972
1973                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1974                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1975                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1976                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1977                         udelay(40);
1978                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1979                 }
1980         }
1981
1982         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1983             (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))
1984                 return 0;
1985
1986         tg3_phy_apply_otp(tp);
1987
1988         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1989                 tg3_phy_toggle_apd(tp, true);
1990         else
1991                 tg3_phy_toggle_apd(tp, false);
1992
1993 out:
1994         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1995                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1996                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1997                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1998                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1999                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
2000                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2001         }
2002         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
2003                 tg3_writephy(tp, 0x1c, 0x8d68);
2004                 tg3_writephy(tp, 0x1c, 0x8d68);
2005         }
2006         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
2007                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2008                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2009                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
2010                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2011                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
2012                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
2013                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
2014                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2015         } else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
2016                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2017                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2018                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
2019                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2020                         tg3_writephy(tp, MII_TG3_TEST1,
2021                                      MII_TG3_TEST1_TRIM_EN | 0x4);
2022                 } else
2023                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2024                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2025         }
2026         /* Set Extended packet length bit (bit 14) on all chips that */
2027         /* support jumbo frames */
2028         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2029                 /* Cannot do read-modify-write on 5401 */
2030                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2031         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2032                 u32 phy_reg;
2033
2034                 /* Set bit 14 with read-modify-write to preserve other bits */
2035                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2036                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
2037                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
2038         }
2039
2040         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2041          * jumbo frames transmission.
2042          */
2043         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2044                 u32 phy_reg;
2045
2046                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2047                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2048                                      phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2049         }
2050
2051         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2052                 /* adjust output voltage */
2053                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2054         }
2055
2056         tg3_phy_toggle_automdix(tp, 1);
2057         tg3_phy_set_wirespeed(tp);
2058         return 0;
2059 }
2060
2061 static void tg3_frob_aux_power(struct tg3 *tp)
2062 {
2063         struct tg3 *tp_peer = tp;
2064
2065         /* The GPIOs do something completely different on 57765. */
2066         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2067             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2068                 return;
2069
2070         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2071             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2072             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2073                 struct net_device *dev_peer;
2074
2075                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2076                 /* remove_one() may have been run on the peer. */
2077                 if (!dev_peer)
2078                         tp_peer = tp;
2079                 else
2080                         tp_peer = netdev_priv(dev_peer);
2081         }
2082
2083         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2084             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2085             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2086             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2087                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2088                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2089                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2090                                     (GRC_LCLCTRL_GPIO_OE0 |
2091                                      GRC_LCLCTRL_GPIO_OE1 |
2092                                      GRC_LCLCTRL_GPIO_OE2 |
2093                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2094                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2095                                     100);
2096                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2097                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2098                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2099                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2100                                              GRC_LCLCTRL_GPIO_OE1 |
2101                                              GRC_LCLCTRL_GPIO_OE2 |
2102                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2103                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2104                                              tp->grc_local_ctrl;
2105                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2106
2107                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2108                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2109
2110                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2111                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2112                 } else {
2113                         u32 no_gpio2;
2114                         u32 grc_local_ctrl = 0;
2115
2116                         if (tp_peer != tp &&
2117                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2118                                 return;
2119
2120                         /* Workaround to prevent overdrawing Amps. */
2121                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2122                             ASIC_REV_5714) {
2123                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2124                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2125                                             grc_local_ctrl, 100);
2126                         }
2127
2128                         /* On 5753 and variants, GPIO2 cannot be used. */
2129                         no_gpio2 = tp->nic_sram_data_cfg &
2130                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2131
2132                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2133                                          GRC_LCLCTRL_GPIO_OE1 |
2134                                          GRC_LCLCTRL_GPIO_OE2 |
2135                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2136                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2137                         if (no_gpio2) {
2138                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2139                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2140                         }
2141                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2142                                                     grc_local_ctrl, 100);
2143
2144                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2145
2146                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2147                                                     grc_local_ctrl, 100);
2148
2149                         if (!no_gpio2) {
2150                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2151                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2152                                             grc_local_ctrl, 100);
2153                         }
2154                 }
2155         } else {
2156                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2157                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2158                         if (tp_peer != tp &&
2159                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2160                                 return;
2161
2162                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2163                                     (GRC_LCLCTRL_GPIO_OE1 |
2164                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2165
2166                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2167                                     GRC_LCLCTRL_GPIO_OE1, 100);
2168
2169                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2170                                     (GRC_LCLCTRL_GPIO_OE1 |
2171                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2172                 }
2173         }
2174 }
2175
2176 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2177 {
2178         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2179                 return 1;
2180         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2181                 if (speed != SPEED_10)
2182                         return 1;
2183         } else if (speed == SPEED_10)
2184                 return 1;
2185
2186         return 0;
2187 }
2188
2189 static int tg3_setup_phy(struct tg3 *, int);
2190
2191 #define RESET_KIND_SHUTDOWN     0
2192 #define RESET_KIND_INIT         1
2193 #define RESET_KIND_SUSPEND      2
2194
2195 static void tg3_write_sig_post_reset(struct tg3 *, int);
2196 static int tg3_halt_cpu(struct tg3 *, u32);
2197
2198 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2199 {
2200         u32 val;
2201
2202         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2203                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2204                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2205                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2206
2207                         sg_dig_ctrl |=
2208                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2209                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2210                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2211                 }
2212                 return;
2213         }
2214
2215         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2216                 tg3_bmcr_reset(tp);
2217                 val = tr32(GRC_MISC_CFG);
2218                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2219                 udelay(40);
2220                 return;
2221         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2222                 u32 phytest;
2223                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2224                         u32 phy;
2225
2226                         tg3_writephy(tp, MII_ADVERTISE, 0);
2227                         tg3_writephy(tp, MII_BMCR,
2228                                      BMCR_ANENABLE | BMCR_ANRESTART);
2229
2230                         tg3_writephy(tp, MII_TG3_FET_TEST,
2231                                      phytest | MII_TG3_FET_SHADOW_EN);
2232                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2233                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2234                                 tg3_writephy(tp,
2235                                              MII_TG3_FET_SHDW_AUXMODE4,
2236                                              phy);
2237                         }
2238                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2239                 }
2240                 return;
2241         } else if (do_low_power) {
2242                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2243                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2244
2245                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2246                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2247                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2248                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2249                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2250         }
2251
2252         /* The PHY should not be powered down on some chips because
2253          * of bugs.
2254          */
2255         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2256             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2257             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2258              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2259                 return;
2260
2261         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2262             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2263                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2264                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2265                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2266                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2267         }
2268
2269         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2270 }
2271
2272 /* tp->lock is held. */
2273 static int tg3_nvram_lock(struct tg3 *tp)
2274 {
2275         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2276                 int i;
2277
2278                 if (tp->nvram_lock_cnt == 0) {
2279                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2280                         for (i = 0; i < 8000; i++) {
2281                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2282                                         break;
2283                                 udelay(20);
2284                         }
2285                         if (i == 8000) {
2286                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2287                                 return -ENODEV;
2288                         }
2289                 }
2290                 tp->nvram_lock_cnt++;
2291         }
2292         return 0;
2293 }
2294
2295 /* tp->lock is held. */
2296 static void tg3_nvram_unlock(struct tg3 *tp)
2297 {
2298         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2299                 if (tp->nvram_lock_cnt > 0)
2300                         tp->nvram_lock_cnt--;
2301                 if (tp->nvram_lock_cnt == 0)
2302                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2303         }
2304 }
2305
2306 /* tp->lock is held. */
2307 static void tg3_enable_nvram_access(struct tg3 *tp)
2308 {
2309         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2310             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2311                 u32 nvaccess = tr32(NVRAM_ACCESS);
2312
2313                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2314         }
2315 }
2316
2317 /* tp->lock is held. */
2318 static void tg3_disable_nvram_access(struct tg3 *tp)
2319 {
2320         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2321             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2322                 u32 nvaccess = tr32(NVRAM_ACCESS);
2323
2324                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2325         }
2326 }
2327
2328 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2329                                         u32 offset, u32 *val)
2330 {
2331         u32 tmp;
2332         int i;
2333
2334         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2335                 return -EINVAL;
2336
2337         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2338                                         EEPROM_ADDR_DEVID_MASK |
2339                                         EEPROM_ADDR_READ);
2340         tw32(GRC_EEPROM_ADDR,
2341              tmp |
2342              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2343              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2344               EEPROM_ADDR_ADDR_MASK) |
2345              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2346
2347         for (i = 0; i < 1000; i++) {
2348                 tmp = tr32(GRC_EEPROM_ADDR);
2349
2350                 if (tmp & EEPROM_ADDR_COMPLETE)
2351                         break;
2352                 msleep(1);
2353         }
2354         if (!(tmp & EEPROM_ADDR_COMPLETE))
2355                 return -EBUSY;
2356
2357         tmp = tr32(GRC_EEPROM_DATA);
2358
2359         /*
2360          * The data will always be opposite the native endian
2361          * format.  Perform a blind byteswap to compensate.
2362          */
2363         *val = swab32(tmp);
2364
2365         return 0;
2366 }
2367
2368 #define NVRAM_CMD_TIMEOUT 10000
2369
2370 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2371 {
2372         int i;
2373
2374         tw32(NVRAM_CMD, nvram_cmd);
2375         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2376                 udelay(10);
2377                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2378                         udelay(10);
2379                         break;
2380                 }
2381         }
2382
2383         if (i == NVRAM_CMD_TIMEOUT)
2384                 return -EBUSY;
2385
2386         return 0;
2387 }
2388
2389 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2390 {
2391         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2392             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2393             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2394            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2395             (tp->nvram_jedecnum == JEDEC_ATMEL))
2396
2397                 addr = ((addr / tp->nvram_pagesize) <<
2398                         ATMEL_AT45DB0X1B_PAGE_POS) +
2399                        (addr % tp->nvram_pagesize);
2400
2401         return addr;
2402 }
2403
2404 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2405 {
2406         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2407             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2408             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2409            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2410             (tp->nvram_jedecnum == JEDEC_ATMEL))
2411
2412                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2413                         tp->nvram_pagesize) +
2414                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2415
2416         return addr;
2417 }
2418
2419 /* NOTE: Data read in from NVRAM is byteswapped according to
2420  * the byteswapping settings for all other register accesses.
2421  * tg3 devices are BE devices, so on a BE machine, the data
2422  * returned will be exactly as it is seen in NVRAM.  On a LE
2423  * machine, the 32-bit value will be byteswapped.
2424  */
2425 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2426 {
2427         int ret;
2428
2429         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2430                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2431
2432         offset = tg3_nvram_phys_addr(tp, offset);
2433
2434         if (offset > NVRAM_ADDR_MSK)
2435                 return -EINVAL;
2436
2437         ret = tg3_nvram_lock(tp);
2438         if (ret)
2439                 return ret;
2440
2441         tg3_enable_nvram_access(tp);
2442
2443         tw32(NVRAM_ADDR, offset);
2444         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2445                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2446
2447         if (ret == 0)
2448                 *val = tr32(NVRAM_RDDATA);
2449
2450         tg3_disable_nvram_access(tp);
2451
2452         tg3_nvram_unlock(tp);
2453
2454         return ret;
2455 }
2456
2457 /* Ensures NVRAM data is in bytestream format. */
2458 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2459 {
2460         u32 v;
2461         int res = tg3_nvram_read(tp, offset, &v);
2462         if (!res)
2463                 *val = cpu_to_be32(v);
2464         return res;
2465 }
2466
2467 /* tp->lock is held. */
2468 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2469 {
2470         u32 addr_high, addr_low;
2471         int i;
2472
2473         addr_high = ((tp->dev->dev_addr[0] << 8) |
2474                      tp->dev->dev_addr[1]);
2475         addr_low = ((tp->dev->dev_addr[2] << 24) |
2476                     (tp->dev->dev_addr[3] << 16) |
2477                     (tp->dev->dev_addr[4] <<  8) |
2478                     (tp->dev->dev_addr[5] <<  0));
2479         for (i = 0; i < 4; i++) {
2480                 if (i == 1 && skip_mac_1)
2481                         continue;
2482                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2483                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2484         }
2485
2486         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2487             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2488                 for (i = 0; i < 12; i++) {
2489                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2490                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2491                 }
2492         }
2493
2494         addr_high = (tp->dev->dev_addr[0] +
2495                      tp->dev->dev_addr[1] +
2496                      tp->dev->dev_addr[2] +
2497                      tp->dev->dev_addr[3] +
2498                      tp->dev->dev_addr[4] +
2499                      tp->dev->dev_addr[5]) &
2500                 TX_BACKOFF_SEED_MASK;
2501         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2502 }
2503
2504 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2505 {
2506         u32 misc_host_ctrl;
2507         bool device_should_wake, do_low_power;
2508
2509         /* Make sure register accesses (indirect or otherwise)
2510          * will function correctly.
2511          */
2512         pci_write_config_dword(tp->pdev,
2513                                TG3PCI_MISC_HOST_CTRL,
2514                                tp->misc_host_ctrl);
2515
2516         switch (state) {
2517         case PCI_D0:
2518                 pci_enable_wake(tp->pdev, state, false);
2519                 pci_set_power_state(tp->pdev, PCI_D0);
2520
2521                 /* Switch out of Vaux if it is a NIC */
2522                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2523                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2524
2525                 return 0;
2526
2527         case PCI_D1:
2528         case PCI_D2:
2529         case PCI_D3hot:
2530                 break;
2531
2532         default:
2533                 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2534                            state);
2535                 return -EINVAL;
2536         }
2537
2538         /* Restore the CLKREQ setting. */
2539         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2540                 u16 lnkctl;
2541
2542                 pci_read_config_word(tp->pdev,
2543                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2544                                      &lnkctl);
2545                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2546                 pci_write_config_word(tp->pdev,
2547                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2548                                       lnkctl);
2549         }
2550
2551         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2552         tw32(TG3PCI_MISC_HOST_CTRL,
2553              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2554
2555         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2556                              device_may_wakeup(&tp->pdev->dev) &&
2557                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2558
2559         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2560                 do_low_power = false;
2561                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2562                     !tp->link_config.phy_is_low_power) {
2563                         struct phy_device *phydev;
2564                         u32 phyid, advertising;
2565
2566                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2567
2568                         tp->link_config.phy_is_low_power = 1;
2569
2570                         tp->link_config.orig_speed = phydev->speed;
2571                         tp->link_config.orig_duplex = phydev->duplex;
2572                         tp->link_config.orig_autoneg = phydev->autoneg;
2573                         tp->link_config.orig_advertising = phydev->advertising;
2574
2575                         advertising = ADVERTISED_TP |
2576                                       ADVERTISED_Pause |
2577                                       ADVERTISED_Autoneg |
2578                                       ADVERTISED_10baseT_Half;
2579
2580                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2581                             device_should_wake) {
2582                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2583                                         advertising |=
2584                                                 ADVERTISED_100baseT_Half |
2585                                                 ADVERTISED_100baseT_Full |
2586                                                 ADVERTISED_10baseT_Full;
2587                                 else
2588                                         advertising |= ADVERTISED_10baseT_Full;
2589                         }
2590
2591                         phydev->advertising = advertising;
2592
2593                         phy_start_aneg(phydev);
2594
2595                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2596                         if (phyid != PHY_ID_BCMAC131) {
2597                                 phyid &= PHY_BCM_OUI_MASK;
2598                                 if (phyid == PHY_BCM_OUI_1 ||
2599                                     phyid == PHY_BCM_OUI_2 ||
2600                                     phyid == PHY_BCM_OUI_3)
2601                                         do_low_power = true;
2602                         }
2603                 }
2604         } else {
2605                 do_low_power = true;
2606
2607                 if (tp->link_config.phy_is_low_power == 0) {
2608                         tp->link_config.phy_is_low_power = 1;
2609                         tp->link_config.orig_speed = tp->link_config.speed;
2610                         tp->link_config.orig_duplex = tp->link_config.duplex;
2611                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2612                 }
2613
2614                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2615                         tp->link_config.speed = SPEED_10;
2616                         tp->link_config.duplex = DUPLEX_HALF;
2617                         tp->link_config.autoneg = AUTONEG_ENABLE;
2618                         tg3_setup_phy(tp, 0);
2619                 }
2620         }
2621
2622         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2623                 u32 val;
2624
2625                 val = tr32(GRC_VCPU_EXT_CTRL);
2626                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2627         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2628                 int i;
2629                 u32 val;
2630
2631                 for (i = 0; i < 200; i++) {
2632                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2633                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2634                                 break;
2635                         msleep(1);
2636                 }
2637         }
2638         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2639                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2640                                                      WOL_DRV_STATE_SHUTDOWN |
2641                                                      WOL_DRV_WOL |
2642                                                      WOL_SET_MAGIC_PKT);
2643
2644         if (device_should_wake) {
2645                 u32 mac_mode;
2646
2647                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2648                         if (do_low_power) {
2649                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2650                                 udelay(40);
2651                         }
2652
2653                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2654                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2655                         else
2656                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2657
2658                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2659                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2660                             ASIC_REV_5700) {
2661                                 u32 speed = (tp->tg3_flags &
2662                                              TG3_FLAG_WOL_SPEED_100MB) ?
2663                                              SPEED_100 : SPEED_10;
2664                                 if (tg3_5700_link_polarity(tp, speed))
2665                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2666                                 else
2667                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2668                         }
2669                 } else {
2670                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2671                 }
2672
2673                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2674                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2675
2676                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2677                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2678                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2679                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2680                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2681                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2682
2683                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2684                         mac_mode |= tp->mac_mode &
2685                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2686                         if (mac_mode & MAC_MODE_APE_TX_EN)
2687                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2688                 }
2689
2690                 tw32_f(MAC_MODE, mac_mode);
2691                 udelay(100);
2692
2693                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2694                 udelay(10);
2695         }
2696
2697         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2698             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2699              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2700                 u32 base_val;
2701
2702                 base_val = tp->pci_clock_ctrl;
2703                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2704                              CLOCK_CTRL_TXCLK_DISABLE);
2705
2706                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2707                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2708         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2709                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2710                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2711                 /* do nothing */
2712         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2713                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2714                 u32 newbits1, newbits2;
2715
2716                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2717                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2718                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2719                                     CLOCK_CTRL_TXCLK_DISABLE |
2720                                     CLOCK_CTRL_ALTCLK);
2721                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2722                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2723                         newbits1 = CLOCK_CTRL_625_CORE;
2724                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2725                 } else {
2726                         newbits1 = CLOCK_CTRL_ALTCLK;
2727                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2728                 }
2729
2730                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2731                             40);
2732
2733                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2734                             40);
2735
2736                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2737                         u32 newbits3;
2738
2739                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2740                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2741                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2742                                             CLOCK_CTRL_TXCLK_DISABLE |
2743                                             CLOCK_CTRL_44MHZ_CORE);
2744                         } else {
2745                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2746                         }
2747
2748                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2749                                     tp->pci_clock_ctrl | newbits3, 40);
2750                 }
2751         }
2752
2753         if (!(device_should_wake) &&
2754             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2755                 tg3_power_down_phy(tp, do_low_power);
2756
2757         tg3_frob_aux_power(tp);
2758
2759         /* Workaround for unstable PLL clock */
2760         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2761             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2762                 u32 val = tr32(0x7d00);
2763
2764                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2765                 tw32(0x7d00, val);
2766                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2767                         int err;
2768
2769                         err = tg3_nvram_lock(tp);
2770                         tg3_halt_cpu(tp, RX_CPU_BASE);
2771                         if (!err)
2772                                 tg3_nvram_unlock(tp);
2773                 }
2774         }
2775
2776         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2777
2778         if (device_should_wake)
2779                 pci_enable_wake(tp->pdev, state, true);
2780
2781         /* Finally, set the new power state. */
2782         pci_set_power_state(tp->pdev, state);
2783
2784         return 0;
2785 }
2786
2787 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2788 {
2789         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2790         case MII_TG3_AUX_STAT_10HALF:
2791                 *speed = SPEED_10;
2792                 *duplex = DUPLEX_HALF;
2793                 break;
2794
2795         case MII_TG3_AUX_STAT_10FULL:
2796                 *speed = SPEED_10;
2797                 *duplex = DUPLEX_FULL;
2798                 break;
2799
2800         case MII_TG3_AUX_STAT_100HALF:
2801                 *speed = SPEED_100;
2802                 *duplex = DUPLEX_HALF;
2803                 break;
2804
2805         case MII_TG3_AUX_STAT_100FULL:
2806                 *speed = SPEED_100;
2807                 *duplex = DUPLEX_FULL;
2808                 break;
2809
2810         case MII_TG3_AUX_STAT_1000HALF:
2811                 *speed = SPEED_1000;
2812                 *duplex = DUPLEX_HALF;
2813                 break;
2814
2815         case MII_TG3_AUX_STAT_1000FULL:
2816                 *speed = SPEED_1000;
2817                 *duplex = DUPLEX_FULL;
2818                 break;
2819
2820         default:
2821                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2822                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2823                                  SPEED_10;
2824                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2825                                   DUPLEX_HALF;
2826                         break;
2827                 }
2828                 *speed = SPEED_INVALID;
2829                 *duplex = DUPLEX_INVALID;
2830                 break;
2831         }
2832 }
2833
2834 static void tg3_phy_copper_begin(struct tg3 *tp)
2835 {
2836         u32 new_adv;
2837         int i;
2838
2839         if (tp->link_config.phy_is_low_power) {
2840                 /* Entering low power mode.  Disable gigabit and
2841                  * 100baseT advertisements.
2842                  */
2843                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2844
2845                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2846                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2847                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2848                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2849
2850                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2851         } else if (tp->link_config.speed == SPEED_INVALID) {
2852                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2853                         tp->link_config.advertising &=
2854                                 ~(ADVERTISED_1000baseT_Half |
2855                                   ADVERTISED_1000baseT_Full);
2856
2857                 new_adv = ADVERTISE_CSMA;
2858                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2859                         new_adv |= ADVERTISE_10HALF;
2860                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2861                         new_adv |= ADVERTISE_10FULL;
2862                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2863                         new_adv |= ADVERTISE_100HALF;
2864                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2865                         new_adv |= ADVERTISE_100FULL;
2866
2867                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2868
2869                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2870
2871                 if (tp->link_config.advertising &
2872                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2873                         new_adv = 0;
2874                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2875                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2876                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2877                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2878                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2879                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2880                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2881                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2882                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2883                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2884                 } else {
2885                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2886                 }
2887         } else {
2888                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2889                 new_adv |= ADVERTISE_CSMA;
2890
2891                 /* Asking for a specific link mode. */
2892                 if (tp->link_config.speed == SPEED_1000) {
2893                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2894
2895                         if (tp->link_config.duplex == DUPLEX_FULL)
2896                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2897                         else
2898                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2899                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2900                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2901                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2902                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2903                 } else {
2904                         if (tp->link_config.speed == SPEED_100) {
2905                                 if (tp->link_config.duplex == DUPLEX_FULL)
2906                                         new_adv |= ADVERTISE_100FULL;
2907                                 else
2908                                         new_adv |= ADVERTISE_100HALF;
2909                         } else {
2910                                 if (tp->link_config.duplex == DUPLEX_FULL)
2911                                         new_adv |= ADVERTISE_10FULL;
2912                                 else
2913                                         new_adv |= ADVERTISE_10HALF;
2914                         }
2915                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2916
2917                         new_adv = 0;
2918                 }
2919
2920                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2921         }
2922
2923         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2924             tp->link_config.speed != SPEED_INVALID) {
2925                 u32 bmcr, orig_bmcr;
2926
2927                 tp->link_config.active_speed = tp->link_config.speed;
2928                 tp->link_config.active_duplex = tp->link_config.duplex;
2929
2930                 bmcr = 0;
2931                 switch (tp->link_config.speed) {
2932                 default:
2933                 case SPEED_10:
2934                         break;
2935
2936                 case SPEED_100:
2937                         bmcr |= BMCR_SPEED100;
2938                         break;
2939
2940                 case SPEED_1000:
2941                         bmcr |= TG3_BMCR_SPEED1000;
2942                         break;
2943                 }
2944
2945                 if (tp->link_config.duplex == DUPLEX_FULL)
2946                         bmcr |= BMCR_FULLDPLX;
2947
2948                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2949                     (bmcr != orig_bmcr)) {
2950                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2951                         for (i = 0; i < 1500; i++) {
2952                                 u32 tmp;
2953
2954                                 udelay(10);
2955                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2956                                     tg3_readphy(tp, MII_BMSR, &tmp))
2957                                         continue;
2958                                 if (!(tmp & BMSR_LSTATUS)) {
2959                                         udelay(40);
2960                                         break;
2961                                 }
2962                         }
2963                         tg3_writephy(tp, MII_BMCR, bmcr);
2964                         udelay(40);
2965                 }
2966         } else {
2967                 tg3_writephy(tp, MII_BMCR,
2968                              BMCR_ANENABLE | BMCR_ANRESTART);
2969         }
2970 }
2971
2972 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2973 {
2974         int err;
2975
2976         /* Turn off tap power management. */
2977         /* Set Extended packet length bit */
2978         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2979
2980         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2981         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2982
2983         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2984         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2985
2986         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2987         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2988
2989         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2990         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2991
2992         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2993         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2994
2995         udelay(40);
2996
2997         return err;
2998 }
2999
3000 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3001 {
3002         u32 adv_reg, all_mask = 0;
3003
3004         if (mask & ADVERTISED_10baseT_Half)
3005                 all_mask |= ADVERTISE_10HALF;
3006         if (mask & ADVERTISED_10baseT_Full)
3007                 all_mask |= ADVERTISE_10FULL;
3008         if (mask & ADVERTISED_100baseT_Half)
3009                 all_mask |= ADVERTISE_100HALF;
3010         if (mask & ADVERTISED_100baseT_Full)
3011                 all_mask |= ADVERTISE_100FULL;
3012
3013         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3014                 return 0;
3015
3016         if ((adv_reg & all_mask) != all_mask)
3017                 return 0;
3018         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
3019                 u32 tg3_ctrl;
3020
3021                 all_mask = 0;
3022                 if (mask & ADVERTISED_1000baseT_Half)
3023                         all_mask |= ADVERTISE_1000HALF;
3024                 if (mask & ADVERTISED_1000baseT_Full)
3025                         all_mask |= ADVERTISE_1000FULL;
3026
3027                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3028                         return 0;
3029
3030                 if ((tg3_ctrl & all_mask) != all_mask)
3031                         return 0;
3032         }
3033         return 1;
3034 }
3035
3036 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3037 {
3038         u32 curadv, reqadv;
3039
3040         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3041                 return 1;
3042
3043         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3044         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3045
3046         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3047                 if (curadv != reqadv)
3048                         return 0;
3049
3050                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3051                         tg3_readphy(tp, MII_LPA, rmtadv);
3052         } else {
3053                 /* Reprogram the advertisement register, even if it
3054                  * does not affect the current link.  If the link
3055                  * gets renegotiated in the future, we can save an
3056                  * additional renegotiation cycle by advertising
3057                  * it correctly in the first place.
3058                  */
3059                 if (curadv != reqadv) {
3060                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3061                                      ADVERTISE_PAUSE_ASYM);
3062                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3063                 }
3064         }
3065
3066         return 1;
3067 }
3068
3069 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3070 {
3071         int current_link_up;
3072         u32 bmsr, dummy;
3073         u32 lcl_adv, rmt_adv;
3074         u16 current_speed;
3075         u8 current_duplex;
3076         int i, err;
3077
3078         tw32(MAC_EVENT, 0);
3079
3080         tw32_f(MAC_STATUS,
3081              (MAC_STATUS_SYNC_CHANGED |
3082               MAC_STATUS_CFG_CHANGED |
3083               MAC_STATUS_MI_COMPLETION |
3084               MAC_STATUS_LNKSTATE_CHANGED));
3085         udelay(40);
3086
3087         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3088                 tw32_f(MAC_MI_MODE,
3089                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3090                 udelay(80);
3091         }
3092
3093         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3094
3095         /* Some third-party PHYs need to be reset on link going
3096          * down.
3097          */
3098         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3099              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3100              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3101             netif_carrier_ok(tp->dev)) {
3102                 tg3_readphy(tp, MII_BMSR, &bmsr);
3103                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3104                     !(bmsr & BMSR_LSTATUS))
3105                         force_reset = 1;
3106         }
3107         if (force_reset)
3108                 tg3_phy_reset(tp);
3109
3110         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3111                 tg3_readphy(tp, MII_BMSR, &bmsr);
3112                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3113                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3114                         bmsr = 0;
3115
3116                 if (!(bmsr & BMSR_LSTATUS)) {
3117                         err = tg3_init_5401phy_dsp(tp);
3118                         if (err)
3119                                 return err;
3120
3121                         tg3_readphy(tp, MII_BMSR, &bmsr);
3122                         for (i = 0; i < 1000; i++) {
3123                                 udelay(10);
3124                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3125                                     (bmsr & BMSR_LSTATUS)) {
3126                                         udelay(40);
3127                                         break;
3128                                 }
3129                         }
3130
3131                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3132                             TG3_PHY_REV_BCM5401_B0 &&
3133                             !(bmsr & BMSR_LSTATUS) &&
3134                             tp->link_config.active_speed == SPEED_1000) {
3135                                 err = tg3_phy_reset(tp);
3136                                 if (!err)
3137                                         err = tg3_init_5401phy_dsp(tp);
3138                                 if (err)
3139                                         return err;
3140                         }
3141                 }
3142         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3143                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3144                 /* 5701 {A0,B0} CRC bug workaround */
3145                 tg3_writephy(tp, 0x15, 0x0a75);
3146                 tg3_writephy(tp, 0x1c, 0x8c68);
3147                 tg3_writephy(tp, 0x1c, 0x8d68);
3148                 tg3_writephy(tp, 0x1c, 0x8c68);
3149         }
3150
3151         /* Clear pending interrupts... */
3152         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3153         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3154
3155         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3156                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3157         else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3158                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3159
3160         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3161             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3162                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3163                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3164                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3165                 else
3166                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3167         }
3168
3169         current_link_up = 0;
3170         current_speed = SPEED_INVALID;
3171         current_duplex = DUPLEX_INVALID;
3172
3173         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3174                 u32 val;
3175
3176                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3177                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3178                 if (!(val & (1 << 10))) {
3179                         val |= (1 << 10);
3180                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3181                         goto relink;
3182                 }
3183         }
3184
3185         bmsr = 0;
3186         for (i = 0; i < 100; i++) {
3187                 tg3_readphy(tp, MII_BMSR, &bmsr);
3188                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3189                     (bmsr & BMSR_LSTATUS))
3190                         break;
3191                 udelay(40);
3192         }
3193
3194         if (bmsr & BMSR_LSTATUS) {
3195                 u32 aux_stat, bmcr;
3196
3197                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3198                 for (i = 0; i < 2000; i++) {
3199                         udelay(10);
3200                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3201                             aux_stat)
3202                                 break;
3203                 }
3204
3205                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3206                                              &current_speed,
3207                                              &current_duplex);
3208
3209                 bmcr = 0;
3210                 for (i = 0; i < 200; i++) {
3211                         tg3_readphy(tp, MII_BMCR, &bmcr);
3212                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3213                                 continue;
3214                         if (bmcr && bmcr != 0x7fff)
3215                                 break;
3216                         udelay(10);
3217                 }
3218
3219                 lcl_adv = 0;
3220                 rmt_adv = 0;
3221
3222                 tp->link_config.active_speed = current_speed;
3223                 tp->link_config.active_duplex = current_duplex;
3224
3225                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3226                         if ((bmcr & BMCR_ANENABLE) &&
3227                             tg3_copper_is_advertising_all(tp,
3228                                                 tp->link_config.advertising)) {
3229                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3230                                                                   &rmt_adv))
3231                                         current_link_up = 1;
3232                         }
3233                 } else {
3234                         if (!(bmcr & BMCR_ANENABLE) &&
3235                             tp->link_config.speed == current_speed &&
3236                             tp->link_config.duplex == current_duplex &&
3237                             tp->link_config.flowctrl ==
3238                             tp->link_config.active_flowctrl) {
3239                                 current_link_up = 1;
3240                         }
3241                 }
3242
3243                 if (current_link_up == 1 &&
3244                     tp->link_config.active_duplex == DUPLEX_FULL)
3245                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3246         }
3247
3248 relink:
3249         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3250                 u32 tmp;
3251
3252                 tg3_phy_copper_begin(tp);
3253
3254                 tg3_readphy(tp, MII_BMSR, &tmp);
3255                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3256                     (tmp & BMSR_LSTATUS))
3257                         current_link_up = 1;
3258         }
3259
3260         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3261         if (current_link_up == 1) {
3262                 if (tp->link_config.active_speed == SPEED_100 ||
3263                     tp->link_config.active_speed == SPEED_10)
3264                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3265                 else
3266                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3267         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3268                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3269         else
3270                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3271
3272         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3273         if (tp->link_config.active_duplex == DUPLEX_HALF)
3274                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3275
3276         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3277                 if (current_link_up == 1 &&
3278                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3279                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3280                 else
3281                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3282         }
3283
3284         /* ??? Without this setting Netgear GA302T PHY does not
3285          * ??? send/receive packets...
3286          */
3287         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3288             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3289                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3290                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3291                 udelay(80);
3292         }
3293
3294         tw32_f(MAC_MODE, tp->mac_mode);
3295         udelay(40);
3296
3297         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3298                 /* Polled via timer. */
3299                 tw32_f(MAC_EVENT, 0);
3300         } else {
3301                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3302         }
3303         udelay(40);
3304
3305         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3306             current_link_up == 1 &&
3307             tp->link_config.active_speed == SPEED_1000 &&
3308             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3309              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3310                 udelay(120);
3311                 tw32_f(MAC_STATUS,
3312                      (MAC_STATUS_SYNC_CHANGED |
3313                       MAC_STATUS_CFG_CHANGED));
3314                 udelay(40);
3315                 tg3_write_mem(tp,
3316                               NIC_SRAM_FIRMWARE_MBOX,
3317                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3318         }
3319
3320         /* Prevent send BD corruption. */
3321         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3322                 u16 oldlnkctl, newlnkctl;
3323
3324                 pci_read_config_word(tp->pdev,
3325                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3326                                      &oldlnkctl);
3327                 if (tp->link_config.active_speed == SPEED_100 ||
3328                     tp->link_config.active_speed == SPEED_10)
3329                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3330                 else
3331                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3332                 if (newlnkctl != oldlnkctl)
3333                         pci_write_config_word(tp->pdev,
3334                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3335                                               newlnkctl);
3336         }
3337
3338         if (current_link_up != netif_carrier_ok(tp->dev)) {
3339                 if (current_link_up)
3340                         netif_carrier_on(tp->dev);
3341                 else
3342                         netif_carrier_off(tp->dev);
3343                 tg3_link_report(tp);
3344         }
3345
3346         return 0;
3347 }
3348
3349 struct tg3_fiber_aneginfo {
3350         int state;
3351 #define ANEG_STATE_UNKNOWN              0
3352 #define ANEG_STATE_AN_ENABLE            1
3353 #define ANEG_STATE_RESTART_INIT         2
3354 #define ANEG_STATE_RESTART              3
3355 #define ANEG_STATE_DISABLE_LINK_OK      4
3356 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3357 #define ANEG_STATE_ABILITY_DETECT       6
3358 #define ANEG_STATE_ACK_DETECT_INIT      7
3359 #define ANEG_STATE_ACK_DETECT           8
3360 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3361 #define ANEG_STATE_COMPLETE_ACK         10
3362 #define ANEG_STATE_IDLE_DETECT_INIT     11
3363 #define ANEG_STATE_IDLE_DETECT          12
3364 #define ANEG_STATE_LINK_OK              13
3365 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3366 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3367
3368         u32 flags;
3369 #define MR_AN_ENABLE            0x00000001
3370 #define MR_RESTART_AN           0x00000002
3371 #define MR_AN_COMPLETE          0x00000004
3372 #define MR_PAGE_RX              0x00000008
3373 #define MR_NP_LOADED            0x00000010
3374 #define MR_TOGGLE_TX            0x00000020
3375 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3376 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3377 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3378 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3379 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3380 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3381 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3382 #define MR_TOGGLE_RX            0x00002000
3383 #define MR_NP_RX                0x00004000
3384
3385 #define MR_LINK_OK              0x80000000
3386
3387         unsigned long link_time, cur_time;
3388
3389         u32 ability_match_cfg;
3390         int ability_match_count;
3391
3392         char ability_match, idle_match, ack_match;
3393
3394         u32 txconfig, rxconfig;
3395 #define ANEG_CFG_NP             0x00000080
3396 #define ANEG_CFG_ACK            0x00000040
3397 #define ANEG_CFG_RF2            0x00000020
3398 #define ANEG_CFG_RF1            0x00000010
3399 #define ANEG_CFG_PS2            0x00000001
3400 #define ANEG_CFG_PS1            0x00008000
3401 #define ANEG_CFG_HD             0x00004000
3402 #define ANEG_CFG_FD             0x00002000
3403 #define ANEG_CFG_INVAL          0x00001f06
3404
3405 };
3406 #define ANEG_OK         0
3407 #define ANEG_DONE       1
3408 #define ANEG_TIMER_ENAB 2
3409 #define ANEG_FAILED     -1
3410
3411 #define ANEG_STATE_SETTLE_TIME  10000
3412
3413 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3414                                    struct tg3_fiber_aneginfo *ap)
3415 {
3416         u16 flowctrl;
3417         unsigned long delta;
3418         u32 rx_cfg_reg;
3419         int ret;
3420
3421         if (ap->state == ANEG_STATE_UNKNOWN) {
3422                 ap->rxconfig = 0;
3423                 ap->link_time = 0;
3424                 ap->cur_time = 0;
3425                 ap->ability_match_cfg = 0;
3426                 ap->ability_match_count = 0;
3427                 ap->ability_match = 0;
3428                 ap->idle_match = 0;
3429                 ap->ack_match = 0;
3430         }
3431         ap->cur_time++;
3432
3433         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3434                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3435
3436                 if (rx_cfg_reg != ap->ability_match_cfg) {
3437                         ap->ability_match_cfg = rx_cfg_reg;
3438                         ap->ability_match = 0;
3439                         ap->ability_match_count = 0;
3440                 } else {
3441                         if (++ap->ability_match_count > 1) {
3442                                 ap->ability_match = 1;
3443                                 ap->ability_match_cfg = rx_cfg_reg;
3444                         }
3445                 }
3446                 if (rx_cfg_reg & ANEG_CFG_ACK)
3447                         ap->ack_match = 1;
3448                 else
3449                         ap->ack_match = 0;
3450
3451                 ap->idle_match = 0;
3452         } else {
3453                 ap->idle_match = 1;
3454                 ap->ability_match_cfg = 0;
3455                 ap->ability_match_count = 0;
3456                 ap->ability_match = 0;
3457                 ap->ack_match = 0;
3458
3459                 rx_cfg_reg = 0;
3460         }
3461
3462         ap->rxconfig = rx_cfg_reg;
3463         ret = ANEG_OK;
3464
3465         switch (ap->state) {
3466         case ANEG_STATE_UNKNOWN:
3467                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3468                         ap->state = ANEG_STATE_AN_ENABLE;
3469
3470                 /* fallthru */
3471         case ANEG_STATE_AN_ENABLE:
3472                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3473                 if (ap->flags & MR_AN_ENABLE) {
3474                         ap->link_time = 0;
3475                         ap->cur_time = 0;
3476                         ap->ability_match_cfg = 0;
3477                         ap->ability_match_count = 0;
3478                         ap->ability_match = 0;
3479                         ap->idle_match = 0;
3480                         ap->ack_match = 0;
3481
3482                         ap->state = ANEG_STATE_RESTART_INIT;
3483                 } else {
3484                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3485                 }
3486                 break;
3487
3488         case ANEG_STATE_RESTART_INIT:
3489                 ap->link_time = ap->cur_time;
3490                 ap->flags &= ~(MR_NP_LOADED);
3491                 ap->txconfig = 0;
3492                 tw32(MAC_TX_AUTO_NEG, 0);
3493                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3494                 tw32_f(MAC_MODE, tp->mac_mode);
3495                 udelay(40);
3496
3497                 ret = ANEG_TIMER_ENAB;
3498                 ap->state = ANEG_STATE_RESTART;
3499
3500                 /* fallthru */
3501         case ANEG_STATE_RESTART:
3502                 delta = ap->cur_time - ap->link_time;
3503                 if (delta > ANEG_STATE_SETTLE_TIME)
3504                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3505                 else
3506                         ret = ANEG_TIMER_ENAB;
3507                 break;
3508
3509         case ANEG_STATE_DISABLE_LINK_OK:
3510                 ret = ANEG_DONE;
3511                 break;
3512
3513         case ANEG_STATE_ABILITY_DETECT_INIT:
3514                 ap->flags &= ~(MR_TOGGLE_TX);
3515                 ap->txconfig = ANEG_CFG_FD;
3516                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3517                 if (flowctrl & ADVERTISE_1000XPAUSE)
3518                         ap->txconfig |= ANEG_CFG_PS1;
3519                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3520                         ap->txconfig |= ANEG_CFG_PS2;
3521                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3522                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3523                 tw32_f(MAC_MODE, tp->mac_mode);
3524                 udelay(40);
3525
3526                 ap->state = ANEG_STATE_ABILITY_DETECT;
3527                 break;
3528
3529         case ANEG_STATE_ABILITY_DETECT:
3530                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3531                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3532                 break;
3533
3534         case ANEG_STATE_ACK_DETECT_INIT:
3535                 ap->txconfig |= ANEG_CFG_ACK;
3536                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3537                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3538                 tw32_f(MAC_MODE, tp->mac_mode);
3539                 udelay(40);
3540
3541                 ap->state = ANEG_STATE_ACK_DETECT;
3542
3543                 /* fallthru */
3544         case ANEG_STATE_ACK_DETECT:
3545                 if (ap->ack_match != 0) {
3546                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3547                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3548                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3549                         } else {
3550                                 ap->state = ANEG_STATE_AN_ENABLE;
3551                         }
3552                 } else if (ap->ability_match != 0 &&
3553                            ap->rxconfig == 0) {
3554                         ap->state = ANEG_STATE_AN_ENABLE;
3555                 }
3556                 break;
3557
3558         case ANEG_STATE_COMPLETE_ACK_INIT:
3559                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3560                         ret = ANEG_FAILED;
3561                         break;
3562                 }
3563                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3564                                MR_LP_ADV_HALF_DUPLEX |
3565                                MR_LP_ADV_SYM_PAUSE |
3566                                MR_LP_ADV_ASYM_PAUSE |
3567                                MR_LP_ADV_REMOTE_FAULT1 |
3568                                MR_LP_ADV_REMOTE_FAULT2 |
3569                                MR_LP_ADV_NEXT_PAGE |
3570                                MR_TOGGLE_RX |
3571                                MR_NP_RX);
3572                 if (ap->rxconfig & ANEG_CFG_FD)
3573                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3574                 if (ap->rxconfig & ANEG_CFG_HD)
3575                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3576                 if (ap->rxconfig & ANEG_CFG_PS1)
3577                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3578                 if (ap->rxconfig & ANEG_CFG_PS2)
3579                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3580                 if (ap->rxconfig & ANEG_CFG_RF1)
3581                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3582                 if (ap->rxconfig & ANEG_CFG_RF2)
3583                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3584                 if (ap->rxconfig & ANEG_CFG_NP)
3585                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3586
3587                 ap->link_time = ap->cur_time;
3588
3589                 ap->flags ^= (MR_TOGGLE_TX);
3590                 if (ap->rxconfig & 0x0008)
3591                         ap->flags |= MR_TOGGLE_RX;
3592                 if (ap->rxconfig & ANEG_CFG_NP)
3593                         ap->flags |= MR_NP_RX;
3594                 ap->flags |= MR_PAGE_RX;
3595
3596                 ap->state = ANEG_STATE_COMPLETE_ACK;
3597                 ret = ANEG_TIMER_ENAB;
3598                 break;
3599
3600         case ANEG_STATE_COMPLETE_ACK:
3601                 if (ap->ability_match != 0 &&
3602                     ap->rxconfig == 0) {
3603                         ap->state = ANEG_STATE_AN_ENABLE;
3604                         break;
3605                 }
3606                 delta = ap->cur_time - ap->link_time;
3607                 if (delta > ANEG_STATE_SETTLE_TIME) {
3608                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3609                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3610                         } else {
3611                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3612                                     !(ap->flags & MR_NP_RX)) {
3613                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3614                                 } else {
3615                                         ret = ANEG_FAILED;
3616                                 }
3617                         }
3618                 }
3619                 break;
3620
3621         case ANEG_STATE_IDLE_DETECT_INIT:
3622                 ap->link_time = ap->cur_time;
3623                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3624                 tw32_f(MAC_MODE, tp->mac_mode);
3625                 udelay(40);
3626
3627                 ap->state = ANEG_STATE_IDLE_DETECT;
3628                 ret = ANEG_TIMER_ENAB;
3629                 break;
3630
3631         case ANEG_STATE_IDLE_DETECT:
3632                 if (ap->ability_match != 0 &&
3633                     ap->rxconfig == 0) {
3634                         ap->state = ANEG_STATE_AN_ENABLE;
3635                         break;
3636                 }
3637                 delta = ap->cur_time - ap->link_time;
3638                 if (delta > ANEG_STATE_SETTLE_TIME) {
3639                         /* XXX another gem from the Broadcom driver :( */
3640                         ap->state = ANEG_STATE_LINK_OK;
3641                 }
3642                 break;
3643
3644         case ANEG_STATE_LINK_OK:
3645                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3646                 ret = ANEG_DONE;
3647                 break;
3648
3649         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3650                 /* ??? unimplemented */
3651                 break;
3652
3653         case ANEG_STATE_NEXT_PAGE_WAIT:
3654                 /* ??? unimplemented */
3655                 break;
3656
3657         default:
3658                 ret = ANEG_FAILED;
3659                 break;
3660         }
3661
3662         return ret;
3663 }
3664
3665 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3666 {
3667         int res = 0;
3668         struct tg3_fiber_aneginfo aninfo;
3669         int status = ANEG_FAILED;
3670         unsigned int tick;
3671         u32 tmp;
3672
3673         tw32_f(MAC_TX_AUTO_NEG, 0);
3674
3675         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3676         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3677         udelay(40);
3678
3679         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3680         udelay(40);
3681
3682         memset(&aninfo, 0, sizeof(aninfo));
3683         aninfo.flags |= MR_AN_ENABLE;
3684         aninfo.state = ANEG_STATE_UNKNOWN;
3685         aninfo.cur_time = 0;
3686         tick = 0;
3687         while (++tick < 195000) {
3688                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3689                 if (status == ANEG_DONE || status == ANEG_FAILED)
3690                         break;
3691
3692                 udelay(1);
3693         }
3694
3695         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3696         tw32_f(MAC_MODE, tp->mac_mode);
3697         udelay(40);
3698
3699         *txflags = aninfo.txconfig;
3700         *rxflags = aninfo.flags;
3701
3702         if (status == ANEG_DONE &&
3703             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3704                              MR_LP_ADV_FULL_DUPLEX)))
3705                 res = 1;
3706
3707         return res;
3708 }
3709
3710 static void tg3_init_bcm8002(struct tg3 *tp)
3711 {
3712         u32 mac_status = tr32(MAC_STATUS);
3713         int i;
3714
3715         /* Reset when initting first time or we have a link. */
3716         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3717             !(mac_status & MAC_STATUS_PCS_SYNCED))
3718                 return;
3719
3720         /* Set PLL lock range. */
3721         tg3_writephy(tp, 0x16, 0x8007);
3722
3723         /* SW reset */
3724         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3725
3726         /* Wait for reset to complete. */
3727         /* XXX schedule_timeout() ... */
3728         for (i = 0; i < 500; i++)
3729                 udelay(10);
3730
3731         /* Config mode; select PMA/Ch 1 regs. */
3732         tg3_writephy(tp, 0x10, 0x8411);
3733
3734         /* Enable auto-lock and comdet, select txclk for tx. */
3735         tg3_writephy(tp, 0x11, 0x0a10);
3736
3737         tg3_writephy(tp, 0x18, 0x00a0);
3738         tg3_writephy(tp, 0x16, 0x41ff);
3739
3740         /* Assert and deassert POR. */
3741         tg3_writephy(tp, 0x13, 0x0400);
3742         udelay(40);
3743         tg3_writephy(tp, 0x13, 0x0000);
3744
3745         tg3_writephy(tp, 0x11, 0x0a50);
3746         udelay(40);
3747         tg3_writephy(tp, 0x11, 0x0a10);
3748
3749         /* Wait for signal to stabilize */
3750         /* XXX schedule_timeout() ... */
3751         for (i = 0; i < 15000; i++)
3752                 udelay(10);
3753
3754         /* Deselect the channel register so we can read the PHYID
3755          * later.
3756          */
3757         tg3_writephy(tp, 0x10, 0x8011);
3758 }
3759
3760 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3761 {
3762         u16 flowctrl;
3763         u32 sg_dig_ctrl, sg_dig_status;
3764         u32 serdes_cfg, expected_sg_dig_ctrl;
3765         int workaround, port_a;
3766         int current_link_up;
3767
3768         serdes_cfg = 0;
3769         expected_sg_dig_ctrl = 0;
3770         workaround = 0;
3771         port_a = 1;
3772         current_link_up = 0;
3773
3774         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3775             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3776                 workaround = 1;
3777                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3778                         port_a = 0;
3779
3780                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3781                 /* preserve bits 20-23 for voltage regulator */
3782                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3783         }
3784
3785         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3786
3787         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3788                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3789                         if (workaround) {
3790                                 u32 val = serdes_cfg;
3791
3792                                 if (port_a)
3793                                         val |= 0xc010000;
3794                                 else
3795                                         val |= 0x4010000;
3796                                 tw32_f(MAC_SERDES_CFG, val);
3797                         }
3798
3799                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3800                 }
3801                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3802                         tg3_setup_flow_control(tp, 0, 0);
3803                         current_link_up = 1;
3804                 }
3805                 goto out;
3806         }
3807
3808         /* Want auto-negotiation.  */
3809         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3810
3811         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3812         if (flowctrl & ADVERTISE_1000XPAUSE)
3813                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3814         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3815                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3816
3817         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3818                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3819                     tp->serdes_counter &&
3820                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3821                                     MAC_STATUS_RCVD_CFG)) ==
3822                      MAC_STATUS_PCS_SYNCED)) {
3823                         tp->serdes_counter--;
3824                         current_link_up = 1;
3825                         goto out;
3826                 }
3827 restart_autoneg:
3828                 if (workaround)
3829                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3830                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3831                 udelay(5);
3832                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3833
3834                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3835                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3836         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3837                                  MAC_STATUS_SIGNAL_DET)) {
3838                 sg_dig_status = tr32(SG_DIG_STATUS);
3839                 mac_status = tr32(MAC_STATUS);
3840
3841                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3842                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3843                         u32 local_adv = 0, remote_adv = 0;
3844
3845                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3846                                 local_adv |= ADVERTISE_1000XPAUSE;
3847                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3848                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3849
3850                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3851                                 remote_adv |= LPA_1000XPAUSE;
3852                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3853                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3854
3855                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3856                         current_link_up = 1;
3857                         tp->serdes_counter = 0;
3858                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3859                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3860                         if (tp->serdes_counter)
3861                                 tp->serdes_counter--;
3862                         else {
3863                                 if (workaround) {
3864                                         u32 val = serdes_cfg;
3865
3866                                         if (port_a)
3867                                                 val |= 0xc010000;
3868                                         else
3869                                                 val |= 0x4010000;
3870
3871                                         tw32_f(MAC_SERDES_CFG, val);
3872                                 }
3873
3874                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3875                                 udelay(40);
3876
3877                                 /* Link parallel detection - link is up */
3878                                 /* only if we have PCS_SYNC and not */
3879                                 /* receiving config code words */
3880                                 mac_status = tr32(MAC_STATUS);
3881                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3882                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3883                                         tg3_setup_flow_control(tp, 0, 0);
3884                                         current_link_up = 1;
3885                                         tp->tg3_flags2 |=
3886                                                 TG3_FLG2_PARALLEL_DETECT;
3887                                         tp->serdes_counter =
3888                                                 SERDES_PARALLEL_DET_TIMEOUT;
3889                                 } else
3890                                         goto restart_autoneg;
3891                         }
3892                 }
3893         } else {
3894                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3895                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3896         }
3897
3898 out:
3899         return current_link_up;
3900 }
3901
3902 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3903 {
3904         int current_link_up = 0;
3905
3906         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3907                 goto out;
3908
3909         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3910                 u32 txflags, rxflags;
3911                 int i;
3912
3913                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3914                         u32 local_adv = 0, remote_adv = 0;
3915
3916                         if (txflags & ANEG_CFG_PS1)
3917                                 local_adv |= ADVERTISE_1000XPAUSE;
3918                         if (txflags & ANEG_CFG_PS2)
3919                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3920
3921                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3922                                 remote_adv |= LPA_1000XPAUSE;
3923                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3924                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3925
3926                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3927
3928                         current_link_up = 1;
3929                 }
3930                 for (i = 0; i < 30; i++) {
3931                         udelay(20);
3932                         tw32_f(MAC_STATUS,
3933                                (MAC_STATUS_SYNC_CHANGED |
3934                                 MAC_STATUS_CFG_CHANGED));
3935                         udelay(40);
3936                         if ((tr32(MAC_STATUS) &
3937                              (MAC_STATUS_SYNC_CHANGED |
3938                               MAC_STATUS_CFG_CHANGED)) == 0)
3939                                 break;
3940                 }
3941
3942                 mac_status = tr32(MAC_STATUS);
3943                 if (current_link_up == 0 &&
3944                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3945                     !(mac_status & MAC_STATUS_RCVD_CFG))
3946                         current_link_up = 1;
3947         } else {
3948                 tg3_setup_flow_control(tp, 0, 0);
3949
3950                 /* Forcing 1000FD link up. */
3951                 current_link_up = 1;
3952
3953                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3954                 udelay(40);
3955
3956                 tw32_f(MAC_MODE, tp->mac_mode);
3957                 udelay(40);
3958         }
3959
3960 out:
3961         return current_link_up;
3962 }
3963
3964 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3965 {
3966         u32 orig_pause_cfg;
3967         u16 orig_active_speed;
3968         u8 orig_active_duplex;
3969         u32 mac_status;
3970         int current_link_up;
3971         int i;
3972
3973         orig_pause_cfg = tp->link_config.active_flowctrl;
3974         orig_active_speed = tp->link_config.active_speed;
3975         orig_active_duplex = tp->link_config.active_duplex;
3976
3977         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3978             netif_carrier_ok(tp->dev) &&
3979             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3980                 mac_status = tr32(MAC_STATUS);
3981                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3982                                MAC_STATUS_SIGNAL_DET |
3983                                MAC_STATUS_CFG_CHANGED |
3984                                MAC_STATUS_RCVD_CFG);
3985                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3986                                    MAC_STATUS_SIGNAL_DET)) {
3987                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3988                                             MAC_STATUS_CFG_CHANGED));
3989                         return 0;
3990                 }
3991         }
3992
3993         tw32_f(MAC_TX_AUTO_NEG, 0);
3994
3995         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3996         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3997         tw32_f(MAC_MODE, tp->mac_mode);
3998         udelay(40);
3999
4000         if (tp->phy_id == TG3_PHY_ID_BCM8002)
4001                 tg3_init_bcm8002(tp);
4002
4003         /* Enable link change event even when serdes polling.  */
4004         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4005         udelay(40);
4006
4007         current_link_up = 0;
4008         mac_status = tr32(MAC_STATUS);
4009
4010         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
4011                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4012         else
4013                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4014
4015         tp->napi[0].hw_status->status =
4016                 (SD_STATUS_UPDATED |
4017                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4018
4019         for (i = 0; i < 100; i++) {
4020                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4021                                     MAC_STATUS_CFG_CHANGED));
4022                 udelay(5);
4023                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4024                                          MAC_STATUS_CFG_CHANGED |
4025                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4026                         break;
4027         }
4028
4029         mac_status = tr32(MAC_STATUS);
4030         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4031                 current_link_up = 0;
4032                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4033                     tp->serdes_counter == 0) {
4034                         tw32_f(MAC_MODE, (tp->mac_mode |
4035                                           MAC_MODE_SEND_CONFIGS));
4036                         udelay(1);
4037                         tw32_f(MAC_MODE, tp->mac_mode);
4038                 }
4039         }
4040
4041         if (current_link_up == 1) {
4042                 tp->link_config.active_speed = SPEED_1000;
4043                 tp->link_config.active_duplex = DUPLEX_FULL;
4044                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4045                                     LED_CTRL_LNKLED_OVERRIDE |
4046                                     LED_CTRL_1000MBPS_ON));
4047         } else {
4048                 tp->link_config.active_speed = SPEED_INVALID;
4049                 tp->link_config.active_duplex = DUPLEX_INVALID;
4050                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4051                                     LED_CTRL_LNKLED_OVERRIDE |
4052                                     LED_CTRL_TRAFFIC_OVERRIDE));
4053         }
4054
4055         if (current_link_up != netif_carrier_ok(tp->dev)) {
4056                 if (current_link_up)
4057                         netif_carrier_on(tp->dev);
4058                 else
4059                         netif_carrier_off(tp->dev);
4060                 tg3_link_report(tp);
4061         } else {
4062                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4063                 if (orig_pause_cfg != now_pause_cfg ||
4064                     orig_active_speed != tp->link_config.active_speed ||
4065                     orig_active_duplex != tp->link_config.active_duplex)
4066                         tg3_link_report(tp);
4067         }
4068
4069         return 0;
4070 }
4071
4072 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4073 {
4074         int current_link_up, err = 0;
4075         u32 bmsr, bmcr;
4076         u16 current_speed;
4077         u8 current_duplex;
4078         u32 local_adv, remote_adv;
4079
4080         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4081         tw32_f(MAC_MODE, tp->mac_mode);
4082         udelay(40);
4083
4084         tw32(MAC_EVENT, 0);
4085
4086         tw32_f(MAC_STATUS,
4087              (MAC_STATUS_SYNC_CHANGED |
4088               MAC_STATUS_CFG_CHANGED |
4089               MAC_STATUS_MI_COMPLETION |
4090               MAC_STATUS_LNKSTATE_CHANGED));
4091         udelay(40);
4092
4093         if (force_reset)
4094                 tg3_phy_reset(tp);
4095
4096         current_link_up = 0;
4097         current_speed = SPEED_INVALID;
4098         current_duplex = DUPLEX_INVALID;
4099
4100         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4101         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4102         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4103                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4104                         bmsr |= BMSR_LSTATUS;
4105                 else
4106                         bmsr &= ~BMSR_LSTATUS;
4107         }
4108
4109         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4110
4111         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4112             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4113                 /* do nothing, just check for link up at the end */
4114         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4115                 u32 adv, new_adv;
4116
4117                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4118                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4119                                   ADVERTISE_1000XPAUSE |
4120                                   ADVERTISE_1000XPSE_ASYM |
4121                                   ADVERTISE_SLCT);
4122
4123                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4124
4125                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4126                         new_adv |= ADVERTISE_1000XHALF;
4127                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4128                         new_adv |= ADVERTISE_1000XFULL;
4129
4130                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4131                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4132                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4133                         tg3_writephy(tp, MII_BMCR, bmcr);
4134
4135                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4136                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4137                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4138
4139                         return err;
4140                 }
4141         } else {
4142                 u32 new_bmcr;
4143
4144                 bmcr &= ~BMCR_SPEED1000;
4145                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4146
4147                 if (tp->link_config.duplex == DUPLEX_FULL)
4148                         new_bmcr |= BMCR_FULLDPLX;
4149
4150                 if (new_bmcr != bmcr) {
4151                         /* BMCR_SPEED1000 is a reserved bit that needs
4152                          * to be set on write.
4153                          */
4154                         new_bmcr |= BMCR_SPEED1000;
4155
4156                         /* Force a linkdown */
4157                         if (netif_carrier_ok(tp->dev)) {
4158                                 u32 adv;
4159
4160                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4161                                 adv &= ~(ADVERTISE_1000XFULL |
4162                                          ADVERTISE_1000XHALF |
4163                                          ADVERTISE_SLCT);
4164                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4165                                 tg3_writephy(tp, MII_BMCR, bmcr |
4166                                                            BMCR_ANRESTART |
4167                                                            BMCR_ANENABLE);
4168                                 udelay(10);
4169                                 netif_carrier_off(tp->dev);
4170                         }
4171                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4172                         bmcr = new_bmcr;
4173                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4174                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4175                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4176                             ASIC_REV_5714) {
4177                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4178                                         bmsr |= BMSR_LSTATUS;
4179                                 else
4180                                         bmsr &= ~BMSR_LSTATUS;
4181                         }
4182                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4183                 }
4184         }
4185
4186         if (bmsr & BMSR_LSTATUS) {
4187                 current_speed = SPEED_1000;
4188                 current_link_up = 1;
4189                 if (bmcr & BMCR_FULLDPLX)
4190                         current_duplex = DUPLEX_FULL;
4191                 else
4192                         current_duplex = DUPLEX_HALF;
4193
4194                 local_adv = 0;
4195                 remote_adv = 0;
4196
4197                 if (bmcr & BMCR_ANENABLE) {
4198                         u32 common;
4199
4200                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4201                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4202                         common = local_adv & remote_adv;
4203                         if (common & (ADVERTISE_1000XHALF |
4204                                       ADVERTISE_1000XFULL)) {
4205                                 if (common & ADVERTISE_1000XFULL)
4206                                         current_duplex = DUPLEX_FULL;
4207                                 else
4208                                         current_duplex = DUPLEX_HALF;
4209                         } else {
4210                                 current_link_up = 0;
4211                         }
4212                 }
4213         }
4214
4215         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4216                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4217
4218         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4219         if (tp->link_config.active_duplex == DUPLEX_HALF)
4220                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4221
4222         tw32_f(MAC_MODE, tp->mac_mode);
4223         udelay(40);
4224
4225         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4226
4227         tp->link_config.active_speed = current_speed;
4228         tp->link_config.active_duplex = current_duplex;
4229
4230         if (current_link_up != netif_carrier_ok(tp->dev)) {
4231                 if (current_link_up)
4232                         netif_carrier_on(tp->dev);
4233                 else {
4234                         netif_carrier_off(tp->dev);
4235                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4236                 }
4237                 tg3_link_report(tp);
4238         }
4239         return err;
4240 }
4241
4242 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4243 {
4244         if (tp->serdes_counter) {
4245                 /* Give autoneg time to complete. */
4246                 tp->serdes_counter--;
4247                 return;
4248         }
4249
4250         if (!netif_carrier_ok(tp->dev) &&
4251             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4252                 u32 bmcr;
4253
4254                 tg3_readphy(tp, MII_BMCR, &bmcr);
4255                 if (bmcr & BMCR_ANENABLE) {
4256                         u32 phy1, phy2;
4257
4258                         /* Select shadow register 0x1f */
4259                         tg3_writephy(tp, 0x1c, 0x7c00);
4260                         tg3_readphy(tp, 0x1c, &phy1);
4261
4262                         /* Select expansion interrupt status register */
4263                         tg3_writephy(tp, 0x17, 0x0f01);
4264                         tg3_readphy(tp, 0x15, &phy2);
4265                         tg3_readphy(tp, 0x15, &phy2);
4266
4267                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4268                                 /* We have signal detect and not receiving
4269                                  * config code words, link is up by parallel
4270                                  * detection.
4271                                  */
4272
4273                                 bmcr &= ~BMCR_ANENABLE;
4274                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4275                                 tg3_writephy(tp, MII_BMCR, bmcr);
4276                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4277                         }
4278                 }
4279         } else if (netif_carrier_ok(tp->dev) &&
4280                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4281                    (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4282                 u32 phy2;
4283
4284                 /* Select expansion interrupt status register */
4285                 tg3_writephy(tp, 0x17, 0x0f01);
4286                 tg3_readphy(tp, 0x15, &phy2);
4287                 if (phy2 & 0x20) {
4288                         u32 bmcr;
4289
4290                         /* Config code words received, turn on autoneg. */
4291                         tg3_readphy(tp, MII_BMCR, &bmcr);
4292                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4293
4294                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4295
4296                 }
4297         }
4298 }
4299
4300 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4301 {
4302         int err;
4303
4304         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
4305                 err = tg3_setup_fiber_phy(tp, force_reset);
4306         else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
4307                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4308         else
4309                 err = tg3_setup_copper_phy(tp, force_reset);
4310
4311         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4312                 u32 val, scale;
4313
4314                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4315                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4316                         scale = 65;
4317                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4318                         scale = 6;
4319                 else
4320                         scale = 12;
4321
4322                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4323                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4324                 tw32(GRC_MISC_CFG, val);
4325         }
4326
4327         if (tp->link_config.active_speed == SPEED_1000 &&
4328             tp->link_config.active_duplex == DUPLEX_HALF)
4329                 tw32(MAC_TX_LENGTHS,
4330                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4331                       (6 << TX_LENGTHS_IPG_SHIFT) |
4332                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4333         else
4334                 tw32(MAC_TX_LENGTHS,
4335                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4336                       (6 << TX_LENGTHS_IPG_SHIFT) |
4337                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4338
4339         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4340                 if (netif_carrier_ok(tp->dev)) {
4341                         tw32(HOSTCC_STAT_COAL_TICKS,
4342                              tp->coal.stats_block_coalesce_usecs);
4343                 } else {
4344                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4345                 }
4346         }
4347
4348         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4349                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4350                 if (!netif_carrier_ok(tp->dev))
4351                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4352                               tp->pwrmgmt_thresh;
4353                 else
4354                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4355                 tw32(PCIE_PWR_MGMT_THRESH, val);
4356         }
4357
4358         return err;
4359 }
4360
4361 /* This is called whenever we suspect that the system chipset is re-
4362  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4363  * is bogus tx completions. We try to recover by setting the
4364  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4365  * in the workqueue.
4366  */
4367 static void tg3_tx_recover(struct tg3 *tp)
4368 {
4369         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4370                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4371
4372         netdev_warn(tp->dev,
4373                     "The system may be re-ordering memory-mapped I/O "
4374                     "cycles to the network device, attempting to recover. "
4375                     "Please report the problem to the driver maintainer "
4376                     "and include system chipset information.\n");
4377
4378         spin_lock(&tp->lock);
4379         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4380         spin_unlock(&tp->lock);
4381 }
4382
4383 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4384 {
4385         smp_mb();
4386         return tnapi->tx_pending -
4387                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4388 }
4389
4390 /* Tigon3 never reports partial packet sends.  So we do not
4391  * need special logic to handle SKBs that have not had all
4392  * of their frags sent yet, like SunGEM does.
4393  */
4394 static void tg3_tx(struct tg3_napi *tnapi)
4395 {
4396         struct tg3 *tp = tnapi->tp;
4397         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4398         u32 sw_idx = tnapi->tx_cons;
4399         struct netdev_queue *txq;
4400         int index = tnapi - tp->napi;
4401
4402         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4403                 index--;
4404
4405         txq = netdev_get_tx_queue(tp->dev, index);
4406
4407         while (sw_idx != hw_idx) {
4408                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4409                 struct sk_buff *skb = ri->skb;
4410                 int i, tx_bug = 0;
4411
4412                 if (unlikely(skb == NULL)) {
4413                         tg3_tx_recover(tp);
4414                         return;
4415                 }
4416
4417                 pci_unmap_single(tp->pdev,
4418                                  dma_unmap_addr(ri, mapping),
4419                                  skb_headlen(skb),
4420                                  PCI_DMA_TODEVICE);
4421
4422                 ri->skb = NULL;
4423
4424                 sw_idx = NEXT_TX(sw_idx);
4425
4426                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4427                         ri = &tnapi->tx_buffers[sw_idx];
4428                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4429                                 tx_bug = 1;
4430
4431                         pci_unmap_page(tp->pdev,
4432                                        dma_unmap_addr(ri, mapping),
4433                                        skb_shinfo(skb)->frags[i].size,
4434                                        PCI_DMA_TODEVICE);
4435                         sw_idx = NEXT_TX(sw_idx);
4436                 }
4437
4438                 dev_kfree_skb(skb);
4439
4440                 if (unlikely(tx_bug)) {
4441                         tg3_tx_recover(tp);
4442                         return;
4443                 }
4444         }
4445
4446         tnapi->tx_cons = sw_idx;
4447
4448         /* Need to make the tx_cons update visible to tg3_start_xmit()
4449          * before checking for netif_queue_stopped().  Without the
4450          * memory barrier, there is a small possibility that tg3_start_xmit()
4451          * will miss it and cause the queue to be stopped forever.
4452          */
4453         smp_mb();
4454
4455         if (unlikely(netif_tx_queue_stopped(txq) &&
4456                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4457                 __netif_tx_lock(txq, smp_processor_id());
4458                 if (netif_tx_queue_stopped(txq) &&
4459                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4460                         netif_tx_wake_queue(txq);
4461                 __netif_tx_unlock(txq);
4462         }
4463 }
4464
4465 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4466 {
4467         if (!ri->skb)
4468                 return;
4469
4470         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4471                          map_sz, PCI_DMA_FROMDEVICE);
4472         dev_kfree_skb_any(ri->skb);
4473         ri->skb = NULL;
4474 }
4475
4476 /* Returns size of skb allocated or < 0 on error.
4477  *
4478  * We only need to fill in the address because the other members
4479  * of the RX descriptor are invariant, see tg3_init_rings.
4480  *
4481  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4482  * posting buffers we only dirty the first cache line of the RX
4483  * descriptor (containing the address).  Whereas for the RX status
4484  * buffers the cpu only reads the last cacheline of the RX descriptor
4485  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4486  */
4487 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4488                             u32 opaque_key, u32 dest_idx_unmasked)
4489 {
4490         struct tg3_rx_buffer_desc *desc;
4491         struct ring_info *map, *src_map;
4492         struct sk_buff *skb;
4493         dma_addr_t mapping;
4494         int skb_size, dest_idx;
4495
4496         src_map = NULL;
4497         switch (opaque_key) {
4498         case RXD_OPAQUE_RING_STD:
4499                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4500                 desc = &tpr->rx_std[dest_idx];
4501                 map = &tpr->rx_std_buffers[dest_idx];
4502                 skb_size = tp->rx_pkt_map_sz;
4503                 break;
4504
4505         case RXD_OPAQUE_RING_JUMBO:
4506                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4507                 desc = &tpr->rx_jmb[dest_idx].std;
4508                 map = &tpr->rx_jmb_buffers[dest_idx];
4509                 skb_size = TG3_RX_JMB_MAP_SZ;
4510                 break;
4511
4512         default:
4513                 return -EINVAL;
4514         }
4515
4516         /* Do not overwrite any of the map or rp information
4517          * until we are sure we can commit to a new buffer.
4518          *
4519          * Callers depend upon this behavior and assume that
4520          * we leave everything unchanged if we fail.
4521          */
4522         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4523         if (skb == NULL)
4524                 return -ENOMEM;
4525
4526         skb_reserve(skb, tp->rx_offset);
4527
4528         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4529                                  PCI_DMA_FROMDEVICE);
4530         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4531                 dev_kfree_skb(skb);
4532                 return -EIO;
4533         }
4534
4535         map->skb = skb;
4536         dma_unmap_addr_set(map, mapping, mapping);
4537
4538         desc->addr_hi = ((u64)mapping >> 32);
4539         desc->addr_lo = ((u64)mapping & 0xffffffff);
4540
4541         return skb_size;
4542 }
4543
4544 /* We only need to move over in the address because the other
4545  * members of the RX descriptor are invariant.  See notes above
4546  * tg3_alloc_rx_skb for full details.
4547  */
4548 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4549                            struct tg3_rx_prodring_set *dpr,
4550                            u32 opaque_key, int src_idx,
4551                            u32 dest_idx_unmasked)
4552 {
4553         struct tg3 *tp = tnapi->tp;
4554         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4555         struct ring_info *src_map, *dest_map;
4556         struct tg3_rx_prodring_set *spr = &tp->prodring[0];
4557         int dest_idx;
4558
4559         switch (opaque_key) {
4560         case RXD_OPAQUE_RING_STD:
4561                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4562                 dest_desc = &dpr->rx_std[dest_idx];
4563                 dest_map = &dpr->rx_std_buffers[dest_idx];
4564                 src_desc = &spr->rx_std[src_idx];
4565                 src_map = &spr->rx_std_buffers[src_idx];
4566                 break;
4567
4568         case RXD_OPAQUE_RING_JUMBO:
4569                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4570                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4571                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4572                 src_desc = &spr->rx_jmb[src_idx].std;
4573                 src_map = &spr->rx_jmb_buffers[src_idx];
4574                 break;
4575
4576         default:
4577                 return;
4578         }
4579
4580         dest_map->skb = src_map->skb;
4581         dma_unmap_addr_set(dest_map, mapping,
4582                            dma_unmap_addr(src_map, mapping));
4583         dest_desc->addr_hi = src_desc->addr_hi;
4584         dest_desc->addr_lo = src_desc->addr_lo;
4585
4586         /* Ensure that the update to the skb happens after the physical
4587          * addresses have been transferred to the new BD location.
4588          */
4589         smp_wmb();
4590
4591         src_map->skb = NULL;
4592 }
4593
4594 /* The RX ring scheme is composed of multiple rings which post fresh
4595  * buffers to the chip, and one special ring the chip uses to report
4596  * status back to the host.
4597  *
4598  * The special ring reports the status of received packets to the
4599  * host.  The chip does not write into the original descriptor the
4600  * RX buffer was obtained from.  The chip simply takes the original
4601  * descriptor as provided by the host, updates the status and length
4602  * field, then writes this into the next status ring entry.
4603  *
4604  * Each ring the host uses to post buffers to the chip is described
4605  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4606  * it is first placed into the on-chip ram.  When the packet's length
4607  * is known, it walks down the TG3_BDINFO entries to select the ring.
4608  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4609  * which is within the range of the new packet's length is chosen.
4610  *
4611  * The "separate ring for rx status" scheme may sound queer, but it makes
4612  * sense from a cache coherency perspective.  If only the host writes
4613  * to the buffer post rings, and only the chip writes to the rx status
4614  * rings, then cache lines never move beyond shared-modified state.
4615  * If both the host and chip were to write into the same ring, cache line
4616  * eviction could occur since both entities want it in an exclusive state.
4617  */
4618 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4619 {
4620         struct tg3 *tp = tnapi->tp;
4621         u32 work_mask, rx_std_posted = 0;
4622         u32 std_prod_idx, jmb_prod_idx;
4623         u32 sw_idx = tnapi->rx_rcb_ptr;
4624         u16 hw_idx;
4625         int received;
4626         struct tg3_rx_prodring_set *tpr = tnapi->prodring;
4627
4628         hw_idx = *(tnapi->rx_rcb_prod_idx);
4629         /*
4630          * We need to order the read of hw_idx and the read of
4631          * the opaque cookie.
4632          */
4633         rmb();
4634         work_mask = 0;
4635         received = 0;
4636         std_prod_idx = tpr->rx_std_prod_idx;
4637         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4638         while (sw_idx != hw_idx && budget > 0) {
4639                 struct ring_info *ri;
4640                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4641                 unsigned int len;
4642                 struct sk_buff *skb;
4643                 dma_addr_t dma_addr;
4644                 u32 opaque_key, desc_idx, *post_ptr;
4645                 bool hw_vlan __maybe_unused = false;
4646                 u16 vtag __maybe_unused = 0;
4647
4648                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4649                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4650                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4651                         ri = &tp->prodring[0].rx_std_buffers[desc_idx];
4652                         dma_addr = dma_unmap_addr(ri, mapping);
4653                         skb = ri->skb;
4654                         post_ptr = &std_prod_idx;
4655                         rx_std_posted++;
4656                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4657                         ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
4658                         dma_addr = dma_unmap_addr(ri, mapping);
4659                         skb = ri->skb;
4660                         post_ptr = &jmb_prod_idx;
4661                 } else
4662                         goto next_pkt_nopost;
4663
4664                 work_mask |= opaque_key;
4665
4666                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4667                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4668                 drop_it:
4669                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4670                                        desc_idx, *post_ptr);
4671                 drop_it_no_recycle:
4672                         /* Other statistics kept track of by card. */
4673                         tp->net_stats.rx_dropped++;
4674                         goto next_pkt;
4675                 }
4676
4677                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4678                       ETH_FCS_LEN;
4679
4680                 if (len > TG3_RX_COPY_THRESH(tp)) {
4681                         int skb_size;
4682
4683                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4684                                                     *post_ptr);
4685                         if (skb_size < 0)
4686                                 goto drop_it;
4687
4688                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4689                                          PCI_DMA_FROMDEVICE);
4690
4691                         /* Ensure that the update to the skb happens
4692                          * after the usage of the old DMA mapping.
4693                          */
4694                         smp_wmb();
4695
4696                         ri->skb = NULL;
4697
4698                         skb_put(skb, len);
4699                 } else {
4700                         struct sk_buff *copy_skb;
4701
4702                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4703                                        desc_idx, *post_ptr);
4704
4705                         copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
4706                                                     TG3_RAW_IP_ALIGN);
4707                         if (copy_skb == NULL)
4708                                 goto drop_it_no_recycle;
4709
4710                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
4711                         skb_put(copy_skb, len);
4712                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4713                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4714                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4715
4716                         /* We'll reuse the original ring buffer. */
4717                         skb = copy_skb;
4718                 }
4719
4720                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4721                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4722                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4723                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4724                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4725                 else
4726                         skb->ip_summed = CHECKSUM_NONE;
4727
4728                 skb->protocol = eth_type_trans(skb, tp->dev);
4729
4730                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4731                     skb->protocol != htons(ETH_P_8021Q)) {
4732                         dev_kfree_skb(skb);
4733                         goto next_pkt;
4734                 }
4735
4736                 if (desc->type_flags & RXD_FLAG_VLAN &&
4737                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
4738                         vtag = desc->err_vlan & RXD_VLAN_MASK;
4739 #if TG3_VLAN_TAG_USED
4740                         if (tp->vlgrp)
4741                                 hw_vlan = true;
4742                         else
4743 #endif
4744                         {
4745                                 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
4746                                                     __skb_push(skb, VLAN_HLEN);
4747
4748                                 memmove(ve, skb->data + VLAN_HLEN,
4749                                         ETH_ALEN * 2);
4750                                 ve->h_vlan_proto = htons(ETH_P_8021Q);
4751                                 ve->h_vlan_TCI = htons(vtag);
4752                         }
4753                 }
4754
4755 #if TG3_VLAN_TAG_USED
4756                 if (hw_vlan)
4757                         vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
4758                 else
4759 #endif
4760                         napi_gro_receive(&tnapi->napi, skb);
4761
4762                 received++;
4763                 budget--;
4764
4765 next_pkt:
4766                 (*post_ptr)++;
4767
4768                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4769                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4770                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4771                                      tpr->rx_std_prod_idx);
4772                         work_mask &= ~RXD_OPAQUE_RING_STD;
4773                         rx_std_posted = 0;
4774                 }
4775 next_pkt_nopost:
4776                 sw_idx++;
4777                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4778
4779                 /* Refresh hw_idx to see if there is new work */
4780                 if (sw_idx == hw_idx) {
4781                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4782                         rmb();
4783                 }
4784         }
4785
4786         /* ACK the status ring. */
4787         tnapi->rx_rcb_ptr = sw_idx;
4788         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4789
4790         /* Refill RX ring(s). */
4791         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4792                 if (work_mask & RXD_OPAQUE_RING_STD) {
4793                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4794                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4795                                      tpr->rx_std_prod_idx);
4796                 }
4797                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4798                         tpr->rx_jmb_prod_idx = jmb_prod_idx %
4799                                                TG3_RX_JUMBO_RING_SIZE;
4800                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4801                                      tpr->rx_jmb_prod_idx);
4802                 }
4803                 mmiowb();
4804         } else if (work_mask) {
4805                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4806                  * updated before the producer indices can be updated.
4807                  */
4808                 smp_wmb();
4809
4810                 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4811                 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4812
4813                 if (tnapi != &tp->napi[1])
4814                         napi_schedule(&tp->napi[1].napi);
4815         }
4816
4817         return received;
4818 }
4819
4820 static void tg3_poll_link(struct tg3 *tp)
4821 {
4822         /* handle link change and other phy events */
4823         if (!(tp->tg3_flags &
4824               (TG3_FLAG_USE_LINKCHG_REG |
4825                TG3_FLAG_POLL_SERDES))) {
4826                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4827
4828                 if (sblk->status & SD_STATUS_LINK_CHG) {
4829                         sblk->status = SD_STATUS_UPDATED |
4830                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4831                         spin_lock(&tp->lock);
4832                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4833                                 tw32_f(MAC_STATUS,
4834                                      (MAC_STATUS_SYNC_CHANGED |
4835                                       MAC_STATUS_CFG_CHANGED |
4836                                       MAC_STATUS_MI_COMPLETION |
4837                                       MAC_STATUS_LNKSTATE_CHANGED));
4838                                 udelay(40);
4839                         } else
4840                                 tg3_setup_phy(tp, 0);
4841                         spin_unlock(&tp->lock);
4842                 }
4843         }
4844 }
4845
4846 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4847                                 struct tg3_rx_prodring_set *dpr,
4848                                 struct tg3_rx_prodring_set *spr)
4849 {
4850         u32 si, di, cpycnt, src_prod_idx;
4851         int i, err = 0;
4852
4853         while (1) {
4854                 src_prod_idx = spr->rx_std_prod_idx;
4855
4856                 /* Make sure updates to the rx_std_buffers[] entries and the
4857                  * standard producer index are seen in the correct order.
4858                  */
4859                 smp_rmb();
4860
4861                 if (spr->rx_std_cons_idx == src_prod_idx)
4862                         break;
4863
4864                 if (spr->rx_std_cons_idx < src_prod_idx)
4865                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4866                 else
4867                         cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4868
4869                 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4870
4871                 si = spr->rx_std_cons_idx;
4872                 di = dpr->rx_std_prod_idx;
4873
4874                 for (i = di; i < di + cpycnt; i++) {
4875                         if (dpr->rx_std_buffers[i].skb) {
4876                                 cpycnt = i - di;
4877                                 err = -ENOSPC;
4878                                 break;
4879                         }
4880                 }
4881
4882                 if (!cpycnt)
4883                         break;
4884
4885                 /* Ensure that updates to the rx_std_buffers ring and the
4886                  * shadowed hardware producer ring from tg3_recycle_skb() are
4887                  * ordered correctly WRT the skb check above.
4888                  */
4889                 smp_rmb();
4890
4891                 memcpy(&dpr->rx_std_buffers[di],
4892                        &spr->rx_std_buffers[si],
4893                        cpycnt * sizeof(struct ring_info));
4894
4895                 for (i = 0; i < cpycnt; i++, di++, si++) {
4896                         struct tg3_rx_buffer_desc *sbd, *dbd;
4897                         sbd = &spr->rx_std[si];
4898                         dbd = &dpr->rx_std[di];
4899                         dbd->addr_hi = sbd->addr_hi;
4900                         dbd->addr_lo = sbd->addr_lo;
4901                 }
4902
4903                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4904                                        TG3_RX_RING_SIZE;
4905                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4906                                        TG3_RX_RING_SIZE;
4907         }
4908
4909         while (1) {
4910                 src_prod_idx = spr->rx_jmb_prod_idx;
4911
4912                 /* Make sure updates to the rx_jmb_buffers[] entries and
4913                  * the jumbo producer index are seen in the correct order.
4914                  */
4915                 smp_rmb();
4916
4917                 if (spr->rx_jmb_cons_idx == src_prod_idx)
4918                         break;
4919
4920                 if (spr->rx_jmb_cons_idx < src_prod_idx)
4921                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4922                 else
4923                         cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4924
4925                 cpycnt = min(cpycnt,
4926                              TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4927
4928                 si = spr->rx_jmb_cons_idx;
4929                 di = dpr->rx_jmb_prod_idx;
4930
4931                 for (i = di; i < di + cpycnt; i++) {
4932                         if (dpr->rx_jmb_buffers[i].skb) {
4933                                 cpycnt = i - di;
4934                                 err = -ENOSPC;
4935                                 break;
4936                         }
4937                 }
4938
4939                 if (!cpycnt)
4940                         break;
4941
4942                 /* Ensure that updates to the rx_jmb_buffers ring and the
4943                  * shadowed hardware producer ring from tg3_recycle_skb() are
4944                  * ordered correctly WRT the skb check above.
4945                  */
4946                 smp_rmb();
4947
4948                 memcpy(&dpr->rx_jmb_buffers[di],
4949                        &spr->rx_jmb_buffers[si],
4950                        cpycnt * sizeof(struct ring_info));
4951
4952                 for (i = 0; i < cpycnt; i++, di++, si++) {
4953                         struct tg3_rx_buffer_desc *sbd, *dbd;
4954                         sbd = &spr->rx_jmb[si].std;
4955                         dbd = &dpr->rx_jmb[di].std;
4956                         dbd->addr_hi = sbd->addr_hi;
4957                         dbd->addr_lo = sbd->addr_lo;
4958                 }
4959
4960                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4961                                        TG3_RX_JUMBO_RING_SIZE;
4962                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4963                                        TG3_RX_JUMBO_RING_SIZE;
4964         }
4965
4966         return err;
4967 }
4968
4969 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4970 {
4971         struct tg3 *tp = tnapi->tp;
4972
4973         /* run TX completion thread */
4974         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4975                 tg3_tx(tnapi);
4976                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4977                         return work_done;
4978         }
4979
4980         /* run RX thread, within the bounds set by NAPI.
4981          * All RX "locking" is done by ensuring outside
4982          * code synchronizes with tg3->napi.poll()
4983          */
4984         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4985                 work_done += tg3_rx(tnapi, budget - work_done);
4986
4987         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4988                 struct tg3_rx_prodring_set *dpr = &tp->prodring[0];
4989                 int i, err = 0;
4990                 u32 std_prod_idx = dpr->rx_std_prod_idx;
4991                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
4992
4993                 for (i = 1; i < tp->irq_cnt; i++)
4994                         err |= tg3_rx_prodring_xfer(tp, dpr,
4995                                                     tp->napi[i].prodring);
4996
4997                 wmb();
4998
4999                 if (std_prod_idx != dpr->rx_std_prod_idx)
5000                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5001                                      dpr->rx_std_prod_idx);
5002
5003                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5004                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5005                                      dpr->rx_jmb_prod_idx);
5006
5007                 mmiowb();
5008
5009                 if (err)
5010                         tw32_f(HOSTCC_MODE, tp->coal_now);
5011         }
5012
5013         return work_done;
5014 }
5015
5016 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5017 {
5018         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5019         struct tg3 *tp = tnapi->tp;
5020         int work_done = 0;
5021         struct tg3_hw_status *sblk = tnapi->hw_status;
5022
5023         while (1) {
5024                 work_done = tg3_poll_work(tnapi, work_done, budget);
5025
5026                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5027                         goto tx_recovery;
5028
5029                 if (unlikely(work_done >= budget))
5030                         break;
5031
5032                 /* tp->last_tag is used in tg3_int_reenable() below
5033                  * to tell the hw how much work has been processed,
5034                  * so we must read it before checking for more work.
5035                  */
5036                 tnapi->last_tag = sblk->status_tag;
5037                 tnapi->last_irq_tag = tnapi->last_tag;
5038                 rmb();
5039
5040                 /* check for RX/TX work to do */
5041                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5042                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5043                         napi_complete(napi);
5044                         /* Reenable interrupts. */
5045                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5046                         mmiowb();
5047                         break;
5048                 }
5049         }
5050
5051         return work_done;
5052
5053 tx_recovery:
5054         /* work_done is guaranteed to be less than budget. */
5055         napi_complete(napi);
5056         schedule_work(&tp->reset_task);
5057         return work_done;
5058 }
5059
5060 static int tg3_poll(struct napi_struct *napi, int budget)
5061 {
5062         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5063         struct tg3 *tp = tnapi->tp;
5064         int work_done = 0;
5065         struct tg3_hw_status *sblk = tnapi->hw_status;
5066
5067         while (1) {
5068                 tg3_poll_link(tp);
5069
5070                 work_done = tg3_poll_work(tnapi, work_done, budget);
5071
5072                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5073                         goto tx_recovery;
5074
5075                 if (unlikely(work_done >= budget))
5076                         break;
5077
5078                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5079                         /* tp->last_tag is used in tg3_int_reenable() below
5080                          * to tell the hw how much work has been processed,
5081                          * so we must read it before checking for more work.
5082                          */
5083                         tnapi->last_tag = sblk->status_tag;
5084                         tnapi->last_irq_tag = tnapi->last_tag;
5085                         rmb();
5086                 } else
5087                         sblk->status &= ~SD_STATUS_UPDATED;
5088
5089                 if (likely(!tg3_has_work(tnapi))) {
5090                         napi_complete(napi);
5091                         tg3_int_reenable(tnapi);
5092                         break;
5093                 }
5094         }
5095
5096         return work_done;
5097
5098 tx_recovery:
5099         /* work_done is guaranteed to be less than budget. */
5100         napi_complete(napi);
5101         schedule_work(&tp->reset_task);
5102         return work_done;
5103 }
5104
5105 static void tg3_irq_quiesce(struct tg3 *tp)
5106 {
5107         int i;
5108
5109         BUG_ON(tp->irq_sync);
5110
5111         tp->irq_sync = 1;
5112         smp_mb();
5113
5114         for (i = 0; i < tp->irq_cnt; i++)
5115                 synchronize_irq(tp->napi[i].irq_vec);
5116 }
5117
5118 static inline int tg3_irq_sync(struct tg3 *tp)
5119 {
5120         return tp->irq_sync;
5121 }
5122
5123 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5124  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5125  * with as well.  Most of the time, this is not necessary except when
5126  * shutting down the device.
5127  */
5128 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5129 {
5130         spin_lock_bh(&tp->lock);
5131         if (irq_sync)
5132                 tg3_irq_quiesce(tp);
5133 }
5134
5135 static inline void tg3_full_unlock(struct tg3 *tp)
5136 {
5137         spin_unlock_bh(&tp->lock);
5138 }
5139
5140 /* One-shot MSI handler - Chip automatically disables interrupt
5141  * after sending MSI so driver doesn't have to do it.
5142  */
5143 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5144 {
5145         struct tg3_napi *tnapi = dev_id;
5146         struct tg3 *tp = tnapi->tp;
5147
5148         prefetch(tnapi->hw_status);
5149         if (tnapi->rx_rcb)
5150                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5151
5152         if (likely(!tg3_irq_sync(tp)))
5153                 napi_schedule(&tnapi->napi);
5154
5155         return IRQ_HANDLED;
5156 }
5157
5158 /* MSI ISR - No need to check for interrupt sharing and no need to
5159  * flush status block and interrupt mailbox. PCI ordering rules
5160  * guarantee that MSI will arrive after the status block.
5161  */
5162 static irqreturn_t tg3_msi(int irq, void *dev_id)
5163 {
5164         struct tg3_napi *tnapi = dev_id;
5165         struct tg3 *tp = tnapi->tp;
5166
5167         prefetch(tnapi->hw_status);
5168         if (tnapi->rx_rcb)
5169                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5170         /*
5171          * Writing any value to intr-mbox-0 clears PCI INTA# and
5172          * chip-internal interrupt pending events.
5173          * Writing non-zero to intr-mbox-0 additional tells the
5174          * NIC to stop sending us irqs, engaging "in-intr-handler"
5175          * event coalescing.
5176          */
5177         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5178         if (likely(!tg3_irq_sync(tp)))
5179                 napi_schedule(&tnapi->napi);
5180
5181         return IRQ_RETVAL(1);
5182 }
5183
5184 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5185 {
5186         struct tg3_napi *tnapi = dev_id;
5187         struct tg3 *tp = tnapi->tp;
5188         struct tg3_hw_status *sblk = tnapi->hw_status;
5189         unsigned int handled = 1;
5190
5191         /* In INTx mode, it is possible for the interrupt to arrive at
5192          * the CPU before the status block posted prior to the interrupt.
5193          * Reading the PCI State register will confirm whether the
5194          * interrupt is ours and will flush the status block.
5195          */
5196         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5197                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5198                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5199                         handled = 0;
5200                         goto out;
5201                 }
5202         }
5203
5204         /*
5205          * Writing any value to intr-mbox-0 clears PCI INTA# and
5206          * chip-internal interrupt pending events.
5207          * Writing non-zero to intr-mbox-0 additional tells the
5208          * NIC to stop sending us irqs, engaging "in-intr-handler"
5209          * event coalescing.
5210          *
5211          * Flush the mailbox to de-assert the IRQ immediately to prevent
5212          * spurious interrupts.  The flush impacts performance but
5213          * excessive spurious interrupts can be worse in some cases.
5214          */
5215         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5216         if (tg3_irq_sync(tp))
5217                 goto out;
5218         sblk->status &= ~SD_STATUS_UPDATED;
5219         if (likely(tg3_has_work(tnapi))) {
5220                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5221                 napi_schedule(&tnapi->napi);
5222         } else {
5223                 /* No work, shared interrupt perhaps?  re-enable
5224                  * interrupts, and flush that PCI write
5225                  */
5226                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5227                                0x00000000);
5228         }
5229 out:
5230         return IRQ_RETVAL(handled);
5231 }
5232
5233 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5234 {
5235         struct tg3_napi *tnapi = dev_id;
5236         struct tg3 *tp = tnapi->tp;
5237         struct tg3_hw_status *sblk = tnapi->hw_status;
5238         unsigned int handled = 1;
5239
5240         /* In INTx mode, it is possible for the interrupt to arrive at
5241          * the CPU before the status block posted prior to the interrupt.
5242          * Reading the PCI State register will confirm whether the
5243          * interrupt is ours and will flush the status block.
5244          */
5245         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5246                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5247                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5248                         handled = 0;
5249                         goto out;
5250                 }
5251         }
5252
5253         /*
5254          * writing any value to intr-mbox-0 clears PCI INTA# and
5255          * chip-internal interrupt pending events.
5256          * writing non-zero to intr-mbox-0 additional tells the
5257          * NIC to stop sending us irqs, engaging "in-intr-handler"
5258          * event coalescing.
5259          *
5260          * Flush the mailbox to de-assert the IRQ immediately to prevent
5261          * spurious interrupts.  The flush impacts performance but
5262          * excessive spurious interrupts can be worse in some cases.
5263          */
5264         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5265
5266         /*
5267          * In a shared interrupt configuration, sometimes other devices'
5268          * interrupts will scream.  We record the current status tag here
5269          * so that the above check can report that the screaming interrupts
5270          * are unhandled.  Eventually they will be silenced.
5271          */
5272         tnapi->last_irq_tag = sblk->status_tag;
5273
5274         if (tg3_irq_sync(tp))
5275                 goto out;
5276
5277         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5278
5279         napi_schedule(&tnapi->napi);
5280
5281 out:
5282         return IRQ_RETVAL(handled);
5283 }
5284
5285 /* ISR for interrupt test */
5286 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5287 {
5288         struct tg3_napi *tnapi = dev_id;
5289         struct tg3 *tp = tnapi->tp;
5290         struct tg3_hw_status *sblk = tnapi->hw_status;
5291
5292         if ((sblk->status & SD_STATUS_UPDATED) ||
5293             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5294                 tg3_disable_ints(tp);
5295                 return IRQ_RETVAL(1);
5296         }
5297         return IRQ_RETVAL(0);
5298 }
5299
5300 static int tg3_init_hw(struct tg3 *, int);
5301 static int tg3_halt(struct tg3 *, int, int);
5302
5303 /* Restart hardware after configuration changes, self-test, etc.
5304  * Invoked with tp->lock held.
5305  */
5306 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5307         __releases(tp->lock)
5308         __acquires(tp->lock)
5309 {
5310         int err;
5311
5312         err = tg3_init_hw(tp, reset_phy);
5313         if (err) {
5314                 netdev_err(tp->dev,
5315                            "Failed to re-initialize device, aborting\n");
5316                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5317                 tg3_full_unlock(tp);
5318                 del_timer_sync(&tp->timer);
5319                 tp->irq_sync = 0;
5320                 tg3_napi_enable(tp);
5321                 dev_close(tp->dev);
5322                 tg3_full_lock(tp, 0);
5323         }
5324         return err;
5325 }
5326
5327 #ifdef CONFIG_NET_POLL_CONTROLLER
5328 static void tg3_poll_controller(struct net_device *dev)
5329 {
5330         int i;
5331         struct tg3 *tp = netdev_priv(dev);
5332
5333         for (i = 0; i < tp->irq_cnt; i++)
5334                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5335 }
5336 #endif
5337
5338 static void tg3_reset_task(struct work_struct *work)
5339 {
5340         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5341         int err;
5342         unsigned int restart_timer;
5343
5344         tg3_full_lock(tp, 0);
5345
5346         if (!netif_running(tp->dev)) {
5347                 tg3_full_unlock(tp);
5348                 return;
5349         }
5350
5351         tg3_full_unlock(tp);
5352
5353         tg3_phy_stop(tp);
5354
5355         tg3_netif_stop(tp);
5356
5357         tg3_full_lock(tp, 1);
5358
5359         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5360         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5361
5362         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5363                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5364                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5365                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5366                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5367         }
5368
5369         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5370         err = tg3_init_hw(tp, 1);
5371         if (err)
5372                 goto out;
5373
5374         tg3_netif_start(tp);
5375
5376         if (restart_timer)
5377                 mod_timer(&tp->timer, jiffies + 1);
5378
5379 out:
5380         tg3_full_unlock(tp);
5381
5382         if (!err)
5383                 tg3_phy_start(tp);
5384 }
5385
5386 static void tg3_dump_short_state(struct tg3 *tp)
5387 {
5388         netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5389                    tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5390         netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5391                    tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5392 }
5393
5394 static void tg3_tx_timeout(struct net_device *dev)
5395 {
5396         struct tg3 *tp = netdev_priv(dev);
5397
5398         if (netif_msg_tx_err(tp)) {
5399                 netdev_err(dev, "transmit timed out, resetting\n");
5400                 tg3_dump_short_state(tp);
5401         }
5402
5403         schedule_work(&tp->reset_task);
5404 }
5405
5406 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5407 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5408 {
5409         u32 base = (u32) mapping & 0xffffffff;
5410
5411         return ((base > 0xffffdcc0) &&
5412                 (base + len + 8 < base));
5413 }
5414
5415 /* Test for DMA addresses > 40-bit */
5416 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5417                                           int len)
5418 {
5419 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5420         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5421                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5422         return 0;
5423 #else
5424         return 0;
5425 #endif
5426 }
5427
5428 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5429
5430 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5431 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5432                                        struct sk_buff *skb, u32 last_plus_one,
5433                                        u32 *start, u32 base_flags, u32 mss)
5434 {
5435         struct tg3 *tp = tnapi->tp;
5436         struct sk_buff *new_skb;
5437         dma_addr_t new_addr = 0;
5438         u32 entry = *start;
5439         int i, ret = 0;
5440
5441         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5442                 new_skb = skb_copy(skb, GFP_ATOMIC);
5443         else {
5444                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5445
5446                 new_skb = skb_copy_expand(skb,
5447                                           skb_headroom(skb) + more_headroom,
5448                                           skb_tailroom(skb), GFP_ATOMIC);
5449         }
5450
5451         if (!new_skb) {
5452                 ret = -1;
5453         } else {
5454                 /* New SKB is guaranteed to be linear. */
5455                 entry = *start;
5456                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5457                                           PCI_DMA_TODEVICE);
5458                 /* Make sure the mapping succeeded */
5459                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5460                         ret = -1;
5461                         dev_kfree_skb(new_skb);
5462                         new_skb = NULL;
5463
5464                 /* Make sure new skb does not cross any 4G boundaries.
5465                  * Drop the packet if it does.
5466                  */
5467                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5468                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5469                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5470                                          PCI_DMA_TODEVICE);
5471                         ret = -1;
5472                         dev_kfree_skb(new_skb);
5473                         new_skb = NULL;
5474                 } else {
5475                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5476                                     base_flags, 1 | (mss << 1));
5477                         *start = NEXT_TX(entry);
5478                 }
5479         }
5480
5481         /* Now clean up the sw ring entries. */
5482         i = 0;
5483         while (entry != last_plus_one) {
5484                 int len;
5485
5486                 if (i == 0)
5487                         len = skb_headlen(skb);
5488                 else
5489                         len = skb_shinfo(skb)->frags[i-1].size;
5490
5491                 pci_unmap_single(tp->pdev,
5492                                  dma_unmap_addr(&tnapi->tx_buffers[entry],
5493                                                 mapping),
5494                                  len, PCI_DMA_TODEVICE);
5495                 if (i == 0) {
5496                         tnapi->tx_buffers[entry].skb = new_skb;
5497                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5498                                            new_addr);
5499                 } else {
5500                         tnapi->tx_buffers[entry].skb = NULL;
5501                 }
5502                 entry = NEXT_TX(entry);
5503                 i++;
5504         }
5505
5506         dev_kfree_skb(skb);
5507
5508         return ret;
5509 }
5510
5511 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5512                         dma_addr_t mapping, int len, u32 flags,
5513                         u32 mss_and_is_end)
5514 {
5515         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5516         int is_end = (mss_and_is_end & 0x1);
5517         u32 mss = (mss_and_is_end >> 1);
5518         u32 vlan_tag = 0;
5519
5520         if (is_end)
5521                 flags |= TXD_FLAG_END;
5522         if (flags & TXD_FLAG_VLAN) {
5523                 vlan_tag = flags >> 16;
5524                 flags &= 0xffff;
5525         }
5526         vlan_tag |= (mss << TXD_MSS_SHIFT);
5527
5528         txd->addr_hi = ((u64) mapping >> 32);
5529         txd->addr_lo = ((u64) mapping & 0xffffffff);
5530         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5531         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5532 }
5533
5534 /* hard_start_xmit for devices that don't have any bugs and
5535  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5536  */
5537 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5538                                   struct net_device *dev)
5539 {
5540         struct tg3 *tp = netdev_priv(dev);
5541         u32 len, entry, base_flags, mss;
5542         dma_addr_t mapping;
5543         struct tg3_napi *tnapi;
5544         struct netdev_queue *txq;
5545         unsigned int i, last;
5546
5547         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5548         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5549         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5550                 tnapi++;
5551
5552         /* We are running in BH disabled context with netif_tx_lock
5553          * and TX reclaim runs via tp->napi.poll inside of a software
5554          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5555          * no IRQ context deadlocks to worry about either.  Rejoice!
5556          */
5557         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5558                 if (!netif_tx_queue_stopped(txq)) {
5559                         netif_tx_stop_queue(txq);
5560
5561                         /* This is a hard error, log it. */
5562                         netdev_err(dev,
5563                                    "BUG! Tx Ring full when queue awake!\n");
5564                 }
5565                 return NETDEV_TX_BUSY;
5566         }
5567
5568         entry = tnapi->tx_prod;
5569         base_flags = 0;
5570         mss = 0;
5571         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5572                 int tcp_opt_len, ip_tcp_len;
5573                 u32 hdrlen;
5574
5575                 if (skb_header_cloned(skb) &&
5576                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5577                         dev_kfree_skb(skb);
5578                         goto out_unlock;
5579                 }
5580
5581                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5582                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5583                 else {
5584                         struct iphdr *iph = ip_hdr(skb);
5585
5586                         tcp_opt_len = tcp_optlen(skb);
5587                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5588
5589                         iph->check = 0;
5590                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5591                         hdrlen = ip_tcp_len + tcp_opt_len;
5592                 }
5593
5594                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5595                         mss |= (hdrlen & 0xc) << 12;
5596                         if (hdrlen & 0x10)
5597                                 base_flags |= 0x00000010;
5598                         base_flags |= (hdrlen & 0x3e0) << 5;
5599                 } else
5600                         mss |= hdrlen << 9;
5601
5602                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5603                                TXD_FLAG_CPU_POST_DMA);
5604
5605                 tcp_hdr(skb)->check = 0;
5606
5607         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5608                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5609         }
5610
5611 #if TG3_VLAN_TAG_USED
5612         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5613                 base_flags |= (TXD_FLAG_VLAN |
5614                                (vlan_tx_tag_get(skb) << 16));
5615 #endif
5616
5617         len = skb_headlen(skb);
5618
5619         /* Queue skb data, a.k.a. the main skb fragment. */
5620         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5621         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5622                 dev_kfree_skb(skb);
5623                 goto out_unlock;
5624         }
5625
5626         tnapi->tx_buffers[entry].skb = skb;
5627         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5628
5629         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5630             !mss && skb->len > ETH_DATA_LEN)
5631                 base_flags |= TXD_FLAG_JMB_PKT;
5632
5633         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5634                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5635
5636         entry = NEXT_TX(entry);
5637
5638         /* Now loop through additional data fragments, and queue them. */
5639         if (skb_shinfo(skb)->nr_frags > 0) {
5640                 last = skb_shinfo(skb)->nr_frags - 1;
5641                 for (i = 0; i <= last; i++) {
5642                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5643
5644                         len = frag->size;
5645                         mapping = pci_map_page(tp->pdev,
5646                                                frag->page,
5647                                                frag->page_offset,
5648                                                len, PCI_DMA_TODEVICE);
5649                         if (pci_dma_mapping_error(tp->pdev, mapping))
5650                                 goto dma_error;
5651
5652                         tnapi->tx_buffers[entry].skb = NULL;
5653                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5654                                            mapping);
5655
5656                         tg3_set_txd(tnapi, entry, mapping, len,
5657                                     base_flags, (i == last) | (mss << 1));
5658
5659                         entry = NEXT_TX(entry);
5660                 }
5661         }
5662
5663         /* Packets are ready, update Tx producer idx local and on card. */
5664         tw32_tx_mbox(tnapi->prodmbox, entry);
5665
5666         tnapi->tx_prod = entry;
5667         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5668                 netif_tx_stop_queue(txq);
5669                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5670                         netif_tx_wake_queue(txq);
5671         }
5672
5673 out_unlock:
5674         mmiowb();
5675
5676         return NETDEV_TX_OK;
5677
5678 dma_error:
5679         last = i;
5680         entry = tnapi->tx_prod;
5681         tnapi->tx_buffers[entry].skb = NULL;
5682         pci_unmap_single(tp->pdev,
5683                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5684                          skb_headlen(skb),
5685                          PCI_DMA_TODEVICE);
5686         for (i = 0; i <= last; i++) {
5687                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5688                 entry = NEXT_TX(entry);
5689
5690                 pci_unmap_page(tp->pdev,
5691                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5692                                               mapping),
5693                                frag->size, PCI_DMA_TODEVICE);
5694         }
5695
5696         dev_kfree_skb(skb);
5697         return NETDEV_TX_OK;
5698 }
5699
5700 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5701                                           struct net_device *);
5702
5703 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5704  * TSO header is greater than 80 bytes.
5705  */
5706 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5707 {
5708         struct sk_buff *segs, *nskb;
5709         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5710
5711         /* Estimate the number of fragments in the worst case */
5712         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5713                 netif_stop_queue(tp->dev);
5714                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5715                         return NETDEV_TX_BUSY;
5716
5717                 netif_wake_queue(tp->dev);
5718         }
5719
5720         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5721         if (IS_ERR(segs))
5722                 goto tg3_tso_bug_end;
5723
5724         do {
5725                 nskb = segs;
5726                 segs = segs->next;
5727                 nskb->next = NULL;
5728                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5729         } while (segs);
5730
5731 tg3_tso_bug_end:
5732         dev_kfree_skb(skb);
5733
5734         return NETDEV_TX_OK;
5735 }
5736
5737 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5738  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5739  */
5740 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5741                                           struct net_device *dev)
5742 {
5743         struct tg3 *tp = netdev_priv(dev);
5744         u32 len, entry, base_flags, mss;
5745         int would_hit_hwbug;
5746         dma_addr_t mapping;
5747         struct tg3_napi *tnapi;
5748         struct netdev_queue *txq;
5749         unsigned int i, last;
5750
5751         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5752         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5753         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5754                 tnapi++;
5755
5756         /* We are running in BH disabled context with netif_tx_lock
5757          * and TX reclaim runs via tp->napi.poll inside of a software
5758          * interrupt.&nbs