net/tg3: simplify conditional
[linux-2.6.git] / drivers / net / tg3.c
1 /*
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  * Copyright (C) 2005-2010 Broadcom Corporation.
8  *
9  * Firmware is:
10  *      Derived from proprietary unpublished source code,
11  *      Copyright (C) 2000-2003 Broadcom Corporation.
12  *
13  *      Permission is hereby granted for the distribution of this firmware
14  *      data in hexadecimal or equivalent format, provided this copyright
15  *      notice is accompanying it.
16  */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/in.h>
28 #include <linux/init.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mii.h>
36 #include <linux/phy.h>
37 #include <linux/brcmphy.h>
38 #include <linux/if_vlan.h>
39 #include <linux/ip.h>
40 #include <linux/tcp.h>
41 #include <linux/workqueue.h>
42 #include <linux/prefetch.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/firmware.h>
45
46 #include <net/checksum.h>
47 #include <net/ip.h>
48
49 #include <asm/system.h>
50 #include <asm/io.h>
51 #include <asm/byteorder.h>
52 #include <asm/uaccess.h>
53
54 #ifdef CONFIG_SPARC
55 #include <asm/idprom.h>
56 #include <asm/prom.h>
57 #endif
58
59 #define BAR_0   0
60 #define BAR_2   2
61
62 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
63 #define TG3_VLAN_TAG_USED 1
64 #else
65 #define TG3_VLAN_TAG_USED 0
66 #endif
67
68 #include "tg3.h"
69
70 #define DRV_MODULE_NAME         "tg3"
71 #define TG3_MAJ_NUM                     3
72 #define TG3_MIN_NUM                     114
73 #define DRV_MODULE_VERSION      \
74         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
75 #define DRV_MODULE_RELDATE      "September 30, 2010"
76
77 #define TG3_DEF_MAC_MODE        0
78 #define TG3_DEF_RX_MODE         0
79 #define TG3_DEF_TX_MODE         0
80 #define TG3_DEF_MSG_ENABLE        \
81         (NETIF_MSG_DRV          | \
82          NETIF_MSG_PROBE        | \
83          NETIF_MSG_LINK         | \
84          NETIF_MSG_TIMER        | \
85          NETIF_MSG_IFDOWN       | \
86          NETIF_MSG_IFUP         | \
87          NETIF_MSG_RX_ERR       | \
88          NETIF_MSG_TX_ERR)
89
90 /* length of time before we decide the hardware is borked,
91  * and dev->tx_timeout() should be called to fix the problem
92  */
93 #define TG3_TX_TIMEOUT                  (5 * HZ)
94
95 /* hardware minimum and maximum for a single frame's data payload */
96 #define TG3_MIN_MTU                     60
97 #define TG3_MAX_MTU(tp) \
98         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
99
100 /* These numbers seem to be hard coded in the NIC firmware somehow.
101  * You can't change the ring sizes, but you can change where you place
102  * them in the NIC onboard memory.
103  */
104 #define TG3_RX_STD_RING_SIZE(tp) \
105         ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
106           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
107          RX_STD_MAX_SIZE_5717 : 512)
108 #define TG3_DEF_RX_RING_PENDING         200
109 #define TG3_RX_JMB_RING_SIZE(tp) \
110         ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
111           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
112          1024 : 256)
113 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
114 #define TG3_RSS_INDIR_TBL_SIZE          128
115
116 /* Do not place this n-ring entries value into the tp struct itself,
117  * we really want to expose these constants to GCC so that modulo et
118  * al.  operations are done with shifts and masks instead of with
119  * hw multiply/modulo instructions.  Another solution would be to
120  * replace things like '% foo' with '& (foo - 1)'.
121  */
122
123 #define TG3_TX_RING_SIZE                512
124 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
125
126 #define TG3_RX_STD_RING_BYTES(tp) \
127         (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
128 #define TG3_RX_JMB_RING_BYTES(tp) \
129         (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
130 #define TG3_RX_RCB_RING_BYTES(tp) \
131         (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
132 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
133                                  TG3_TX_RING_SIZE)
134 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
135
136 #define TG3_RX_DMA_ALIGN                16
137 #define TG3_RX_HEADROOM                 ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
138
139 #define TG3_DMA_BYTE_ENAB               64
140
141 #define TG3_RX_STD_DMA_SZ               1536
142 #define TG3_RX_JMB_DMA_SZ               9046
143
144 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
145
146 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
147 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
148
149 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
150         (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
151
152 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
153         (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
154
155 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
156  * that are at least dword aligned when used in PCIX mode.  The driver
157  * works around this bug by double copying the packet.  This workaround
158  * is built into the normal double copy length check for efficiency.
159  *
160  * However, the double copy is only necessary on those architectures
161  * where unaligned memory accesses are inefficient.  For those architectures
162  * where unaligned memory accesses incur little penalty, we can reintegrate
163  * the 5701 in the normal rx path.  Doing so saves a device structure
164  * dereference by hardcoding the double copy threshold in place.
165  */
166 #define TG3_RX_COPY_THRESHOLD           256
167 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
168         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
169 #else
170         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
171 #endif
172
173 /* minimum number of free TX descriptors required to wake up TX process */
174 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
175
176 #define TG3_RAW_IP_ALIGN 2
177
178 /* number of ETHTOOL_GSTATS u64's */
179 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
180
181 #define TG3_NUM_TEST            6
182
183 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
184
185 #define FIRMWARE_TG3            "tigon/tg3.bin"
186 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
187 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
188
189 static char version[] __devinitdata =
190         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
191
192 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
193 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
194 MODULE_LICENSE("GPL");
195 MODULE_VERSION(DRV_MODULE_VERSION);
196 MODULE_FIRMWARE(FIRMWARE_TG3);
197 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
198 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
199
200 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
201 module_param(tg3_debug, int, 0);
202 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
203
204 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
268         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
269         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
270         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
271         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
272         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
273         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
274         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
275         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
276         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
277         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
278         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
279         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
280         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
281         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
282         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
283         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
284         {}
285 };
286
287 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
288
289 static const struct {
290         const char string[ETH_GSTRING_LEN];
291 } ethtool_stats_keys[TG3_NUM_STATS] = {
292         { "rx_octets" },
293         { "rx_fragments" },
294         { "rx_ucast_packets" },
295         { "rx_mcast_packets" },
296         { "rx_bcast_packets" },
297         { "rx_fcs_errors" },
298         { "rx_align_errors" },
299         { "rx_xon_pause_rcvd" },
300         { "rx_xoff_pause_rcvd" },
301         { "rx_mac_ctrl_rcvd" },
302         { "rx_xoff_entered" },
303         { "rx_frame_too_long_errors" },
304         { "rx_jabbers" },
305         { "rx_undersize_packets" },
306         { "rx_in_length_errors" },
307         { "rx_out_length_errors" },
308         { "rx_64_or_less_octet_packets" },
309         { "rx_65_to_127_octet_packets" },
310         { "rx_128_to_255_octet_packets" },
311         { "rx_256_to_511_octet_packets" },
312         { "rx_512_to_1023_octet_packets" },
313         { "rx_1024_to_1522_octet_packets" },
314         { "rx_1523_to_2047_octet_packets" },
315         { "rx_2048_to_4095_octet_packets" },
316         { "rx_4096_to_8191_octet_packets" },
317         { "rx_8192_to_9022_octet_packets" },
318
319         { "tx_octets" },
320         { "tx_collisions" },
321
322         { "tx_xon_sent" },
323         { "tx_xoff_sent" },
324         { "tx_flow_control" },
325         { "tx_mac_errors" },
326         { "tx_single_collisions" },
327         { "tx_mult_collisions" },
328         { "tx_deferred" },
329         { "tx_excessive_collisions" },
330         { "tx_late_collisions" },
331         { "tx_collide_2times" },
332         { "tx_collide_3times" },
333         { "tx_collide_4times" },
334         { "tx_collide_5times" },
335         { "tx_collide_6times" },
336         { "tx_collide_7times" },
337         { "tx_collide_8times" },
338         { "tx_collide_9times" },
339         { "tx_collide_10times" },
340         { "tx_collide_11times" },
341         { "tx_collide_12times" },
342         { "tx_collide_13times" },
343         { "tx_collide_14times" },
344         { "tx_collide_15times" },
345         { "tx_ucast_packets" },
346         { "tx_mcast_packets" },
347         { "tx_bcast_packets" },
348         { "tx_carrier_sense_errors" },
349         { "tx_discards" },
350         { "tx_errors" },
351
352         { "dma_writeq_full" },
353         { "dma_write_prioq_full" },
354         { "rxbds_empty" },
355         { "rx_discards" },
356         { "rx_errors" },
357         { "rx_threshold_hit" },
358
359         { "dma_readq_full" },
360         { "dma_read_prioq_full" },
361         { "tx_comp_queue_full" },
362
363         { "ring_set_send_prod_index" },
364         { "ring_status_update" },
365         { "nic_irqs" },
366         { "nic_avoided_irqs" },
367         { "nic_tx_threshold_hit" }
368 };
369
370 static const struct {
371         const char string[ETH_GSTRING_LEN];
372 } ethtool_test_keys[TG3_NUM_TEST] = {
373         { "nvram test     (online) " },
374         { "link test      (online) " },
375         { "register test  (offline)" },
376         { "memory test    (offline)" },
377         { "loopback test  (offline)" },
378         { "interrupt test (offline)" },
379 };
380
381 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
382 {
383         writel(val, tp->regs + off);
384 }
385
386 static u32 tg3_read32(struct tg3 *tp, u32 off)
387 {
388         return readl(tp->regs + off);
389 }
390
391 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
392 {
393         writel(val, tp->aperegs + off);
394 }
395
396 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
397 {
398         return readl(tp->aperegs + off);
399 }
400
401 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
402 {
403         unsigned long flags;
404
405         spin_lock_irqsave(&tp->indirect_lock, flags);
406         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
407         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
408         spin_unlock_irqrestore(&tp->indirect_lock, flags);
409 }
410
411 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
412 {
413         writel(val, tp->regs + off);
414         readl(tp->regs + off);
415 }
416
417 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
418 {
419         unsigned long flags;
420         u32 val;
421
422         spin_lock_irqsave(&tp->indirect_lock, flags);
423         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
424         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
425         spin_unlock_irqrestore(&tp->indirect_lock, flags);
426         return val;
427 }
428
429 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
430 {
431         unsigned long flags;
432
433         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
434                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
435                                        TG3_64BIT_REG_LOW, val);
436                 return;
437         }
438         if (off == TG3_RX_STD_PROD_IDX_REG) {
439                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
440                                        TG3_64BIT_REG_LOW, val);
441                 return;
442         }
443
444         spin_lock_irqsave(&tp->indirect_lock, flags);
445         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
446         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
447         spin_unlock_irqrestore(&tp->indirect_lock, flags);
448
449         /* In indirect mode when disabling interrupts, we also need
450          * to clear the interrupt bit in the GRC local ctrl register.
451          */
452         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
453             (val == 0x1)) {
454                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
455                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
456         }
457 }
458
459 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
460 {
461         unsigned long flags;
462         u32 val;
463
464         spin_lock_irqsave(&tp->indirect_lock, flags);
465         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
466         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
467         spin_unlock_irqrestore(&tp->indirect_lock, flags);
468         return val;
469 }
470
471 /* usec_wait specifies the wait time in usec when writing to certain registers
472  * where it is unsafe to read back the register without some delay.
473  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
474  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
475  */
476 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
477 {
478         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
479             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
480                 /* Non-posted methods */
481                 tp->write32(tp, off, val);
482         else {
483                 /* Posted method */
484                 tg3_write32(tp, off, val);
485                 if (usec_wait)
486                         udelay(usec_wait);
487                 tp->read32(tp, off);
488         }
489         /* Wait again after the read for the posted method to guarantee that
490          * the wait time is met.
491          */
492         if (usec_wait)
493                 udelay(usec_wait);
494 }
495
496 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
497 {
498         tp->write32_mbox(tp, off, val);
499         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
500             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
501                 tp->read32_mbox(tp, off);
502 }
503
504 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
505 {
506         void __iomem *mbox = tp->regs + off;
507         writel(val, mbox);
508         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
509                 writel(val, mbox);
510         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
511                 readl(mbox);
512 }
513
514 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
515 {
516         return readl(tp->regs + off + GRCMBOX_BASE);
517 }
518
519 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
520 {
521         writel(val, tp->regs + off + GRCMBOX_BASE);
522 }
523
524 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
525 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
526 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
527 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
528 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
529
530 #define tw32(reg, val)                  tp->write32(tp, reg, val)
531 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
532 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
533 #define tr32(reg)                       tp->read32(tp, reg)
534
535 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
536 {
537         unsigned long flags;
538
539         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
540             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
541                 return;
542
543         spin_lock_irqsave(&tp->indirect_lock, flags);
544         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
545                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
546                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
547
548                 /* Always leave this as zero. */
549                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
550         } else {
551                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
552                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
553
554                 /* Always leave this as zero. */
555                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
556         }
557         spin_unlock_irqrestore(&tp->indirect_lock, flags);
558 }
559
560 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
561 {
562         unsigned long flags;
563
564         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
565             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
566                 *val = 0;
567                 return;
568         }
569
570         spin_lock_irqsave(&tp->indirect_lock, flags);
571         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
572                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
573                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
574
575                 /* Always leave this as zero. */
576                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
577         } else {
578                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
579                 *val = tr32(TG3PCI_MEM_WIN_DATA);
580
581                 /* Always leave this as zero. */
582                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
583         }
584         spin_unlock_irqrestore(&tp->indirect_lock, flags);
585 }
586
587 static void tg3_ape_lock_init(struct tg3 *tp)
588 {
589         int i;
590         u32 regbase;
591
592         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
593                 regbase = TG3_APE_LOCK_GRANT;
594         else
595                 regbase = TG3_APE_PER_LOCK_GRANT;
596
597         /* Make sure the driver hasn't any stale locks. */
598         for (i = 0; i < 8; i++)
599                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
600 }
601
602 static int tg3_ape_lock(struct tg3 *tp, int locknum)
603 {
604         int i, off;
605         int ret = 0;
606         u32 status, req, gnt;
607
608         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
609                 return 0;
610
611         switch (locknum) {
612         case TG3_APE_LOCK_GRC:
613         case TG3_APE_LOCK_MEM:
614                 break;
615         default:
616                 return -EINVAL;
617         }
618
619         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
620                 req = TG3_APE_LOCK_REQ;
621                 gnt = TG3_APE_LOCK_GRANT;
622         } else {
623                 req = TG3_APE_PER_LOCK_REQ;
624                 gnt = TG3_APE_PER_LOCK_GRANT;
625         }
626
627         off = 4 * locknum;
628
629         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
630
631         /* Wait for up to 1 millisecond to acquire lock. */
632         for (i = 0; i < 100; i++) {
633                 status = tg3_ape_read32(tp, gnt + off);
634                 if (status == APE_LOCK_GRANT_DRIVER)
635                         break;
636                 udelay(10);
637         }
638
639         if (status != APE_LOCK_GRANT_DRIVER) {
640                 /* Revoke the lock request. */
641                 tg3_ape_write32(tp, gnt + off,
642                                 APE_LOCK_GRANT_DRIVER);
643
644                 ret = -EBUSY;
645         }
646
647         return ret;
648 }
649
650 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
651 {
652         u32 gnt;
653
654         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
655                 return;
656
657         switch (locknum) {
658         case TG3_APE_LOCK_GRC:
659         case TG3_APE_LOCK_MEM:
660                 break;
661         default:
662                 return;
663         }
664
665         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
666                 gnt = TG3_APE_LOCK_GRANT;
667         else
668                 gnt = TG3_APE_PER_LOCK_GRANT;
669
670         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
671 }
672
673 static void tg3_disable_ints(struct tg3 *tp)
674 {
675         int i;
676
677         tw32(TG3PCI_MISC_HOST_CTRL,
678              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
679         for (i = 0; i < tp->irq_max; i++)
680                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
681 }
682
683 static void tg3_enable_ints(struct tg3 *tp)
684 {
685         int i;
686
687         tp->irq_sync = 0;
688         wmb();
689
690         tw32(TG3PCI_MISC_HOST_CTRL,
691              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
692
693         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
694         for (i = 0; i < tp->irq_cnt; i++) {
695                 struct tg3_napi *tnapi = &tp->napi[i];
696
697                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
698                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
699                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
700
701                 tp->coal_now |= tnapi->coal_now;
702         }
703
704         /* Force an initial interrupt */
705         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
706             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
707                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
708         else
709                 tw32(HOSTCC_MODE, tp->coal_now);
710
711         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
712 }
713
714 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
715 {
716         struct tg3 *tp = tnapi->tp;
717         struct tg3_hw_status *sblk = tnapi->hw_status;
718         unsigned int work_exists = 0;
719
720         /* check for phy events */
721         if (!(tp->tg3_flags &
722               (TG3_FLAG_USE_LINKCHG_REG |
723                TG3_FLAG_POLL_SERDES))) {
724                 if (sblk->status & SD_STATUS_LINK_CHG)
725                         work_exists = 1;
726         }
727         /* check for RX/TX work to do */
728         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
729             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
730                 work_exists = 1;
731
732         return work_exists;
733 }
734
735 /* tg3_int_reenable
736  *  similar to tg3_enable_ints, but it accurately determines whether there
737  *  is new work pending and can return without flushing the PIO write
738  *  which reenables interrupts
739  */
740 static void tg3_int_reenable(struct tg3_napi *tnapi)
741 {
742         struct tg3 *tp = tnapi->tp;
743
744         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
745         mmiowb();
746
747         /* When doing tagged status, this work check is unnecessary.
748          * The last_tag we write above tells the chip which piece of
749          * work we've completed.
750          */
751         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
752             tg3_has_work(tnapi))
753                 tw32(HOSTCC_MODE, tp->coalesce_mode |
754                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
755 }
756
757 static void tg3_switch_clocks(struct tg3 *tp)
758 {
759         u32 clock_ctrl;
760         u32 orig_clock_ctrl;
761
762         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
763             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
764                 return;
765
766         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
767
768         orig_clock_ctrl = clock_ctrl;
769         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
770                        CLOCK_CTRL_CLKRUN_OENABLE |
771                        0x1f);
772         tp->pci_clock_ctrl = clock_ctrl;
773
774         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
775                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
776                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
777                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
778                 }
779         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
780                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
781                             clock_ctrl |
782                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
783                             40);
784                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
785                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
786                             40);
787         }
788         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
789 }
790
791 #define PHY_BUSY_LOOPS  5000
792
793 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
794 {
795         u32 frame_val;
796         unsigned int loops;
797         int ret;
798
799         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
800                 tw32_f(MAC_MI_MODE,
801                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
802                 udelay(80);
803         }
804
805         *val = 0x0;
806
807         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
808                       MI_COM_PHY_ADDR_MASK);
809         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
810                       MI_COM_REG_ADDR_MASK);
811         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
812
813         tw32_f(MAC_MI_COM, frame_val);
814
815         loops = PHY_BUSY_LOOPS;
816         while (loops != 0) {
817                 udelay(10);
818                 frame_val = tr32(MAC_MI_COM);
819
820                 if ((frame_val & MI_COM_BUSY) == 0) {
821                         udelay(5);
822                         frame_val = tr32(MAC_MI_COM);
823                         break;
824                 }
825                 loops -= 1;
826         }
827
828         ret = -EBUSY;
829         if (loops != 0) {
830                 *val = frame_val & MI_COM_DATA_MASK;
831                 ret = 0;
832         }
833
834         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
835                 tw32_f(MAC_MI_MODE, tp->mi_mode);
836                 udelay(80);
837         }
838
839         return ret;
840 }
841
842 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
843 {
844         u32 frame_val;
845         unsigned int loops;
846         int ret;
847
848         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
849             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
850                 return 0;
851
852         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
853                 tw32_f(MAC_MI_MODE,
854                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
855                 udelay(80);
856         }
857
858         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
859                       MI_COM_PHY_ADDR_MASK);
860         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
861                       MI_COM_REG_ADDR_MASK);
862         frame_val |= (val & MI_COM_DATA_MASK);
863         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
864
865         tw32_f(MAC_MI_COM, frame_val);
866
867         loops = PHY_BUSY_LOOPS;
868         while (loops != 0) {
869                 udelay(10);
870                 frame_val = tr32(MAC_MI_COM);
871                 if ((frame_val & MI_COM_BUSY) == 0) {
872                         udelay(5);
873                         frame_val = tr32(MAC_MI_COM);
874                         break;
875                 }
876                 loops -= 1;
877         }
878
879         ret = -EBUSY;
880         if (loops != 0)
881                 ret = 0;
882
883         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
884                 tw32_f(MAC_MI_MODE, tp->mi_mode);
885                 udelay(80);
886         }
887
888         return ret;
889 }
890
891 static int tg3_bmcr_reset(struct tg3 *tp)
892 {
893         u32 phy_control;
894         int limit, err;
895
896         /* OK, reset it, and poll the BMCR_RESET bit until it
897          * clears or we time out.
898          */
899         phy_control = BMCR_RESET;
900         err = tg3_writephy(tp, MII_BMCR, phy_control);
901         if (err != 0)
902                 return -EBUSY;
903
904         limit = 5000;
905         while (limit--) {
906                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
907                 if (err != 0)
908                         return -EBUSY;
909
910                 if ((phy_control & BMCR_RESET) == 0) {
911                         udelay(40);
912                         break;
913                 }
914                 udelay(10);
915         }
916         if (limit < 0)
917                 return -EBUSY;
918
919         return 0;
920 }
921
922 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
923 {
924         struct tg3 *tp = bp->priv;
925         u32 val;
926
927         spin_lock_bh(&tp->lock);
928
929         if (tg3_readphy(tp, reg, &val))
930                 val = -EIO;
931
932         spin_unlock_bh(&tp->lock);
933
934         return val;
935 }
936
937 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
938 {
939         struct tg3 *tp = bp->priv;
940         u32 ret = 0;
941
942         spin_lock_bh(&tp->lock);
943
944         if (tg3_writephy(tp, reg, val))
945                 ret = -EIO;
946
947         spin_unlock_bh(&tp->lock);
948
949         return ret;
950 }
951
952 static int tg3_mdio_reset(struct mii_bus *bp)
953 {
954         return 0;
955 }
956
957 static void tg3_mdio_config_5785(struct tg3 *tp)
958 {
959         u32 val;
960         struct phy_device *phydev;
961
962         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
963         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
964         case PHY_ID_BCM50610:
965         case PHY_ID_BCM50610M:
966                 val = MAC_PHYCFG2_50610_LED_MODES;
967                 break;
968         case PHY_ID_BCMAC131:
969                 val = MAC_PHYCFG2_AC131_LED_MODES;
970                 break;
971         case PHY_ID_RTL8211C:
972                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
973                 break;
974         case PHY_ID_RTL8201E:
975                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
976                 break;
977         default:
978                 return;
979         }
980
981         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
982                 tw32(MAC_PHYCFG2, val);
983
984                 val = tr32(MAC_PHYCFG1);
985                 val &= ~(MAC_PHYCFG1_RGMII_INT |
986                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
987                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
988                 tw32(MAC_PHYCFG1, val);
989
990                 return;
991         }
992
993         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
994                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
995                        MAC_PHYCFG2_FMODE_MASK_MASK |
996                        MAC_PHYCFG2_GMODE_MASK_MASK |
997                        MAC_PHYCFG2_ACT_MASK_MASK   |
998                        MAC_PHYCFG2_QUAL_MASK_MASK |
999                        MAC_PHYCFG2_INBAND_ENABLE;
1000
1001         tw32(MAC_PHYCFG2, val);
1002
1003         val = tr32(MAC_PHYCFG1);
1004         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1005                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1006         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1007                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1008                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1009                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1010                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1011         }
1012         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1013                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1014         tw32(MAC_PHYCFG1, val);
1015
1016         val = tr32(MAC_EXT_RGMII_MODE);
1017         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1018                  MAC_RGMII_MODE_RX_QUALITY |
1019                  MAC_RGMII_MODE_RX_ACTIVITY |
1020                  MAC_RGMII_MODE_RX_ENG_DET |
1021                  MAC_RGMII_MODE_TX_ENABLE |
1022                  MAC_RGMII_MODE_TX_LOWPWR |
1023                  MAC_RGMII_MODE_TX_RESET);
1024         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1025                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1026                         val |= MAC_RGMII_MODE_RX_INT_B |
1027                                MAC_RGMII_MODE_RX_QUALITY |
1028                                MAC_RGMII_MODE_RX_ACTIVITY |
1029                                MAC_RGMII_MODE_RX_ENG_DET;
1030                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1031                         val |= MAC_RGMII_MODE_TX_ENABLE |
1032                                MAC_RGMII_MODE_TX_LOWPWR |
1033                                MAC_RGMII_MODE_TX_RESET;
1034         }
1035         tw32(MAC_EXT_RGMII_MODE, val);
1036 }
1037
1038 static void tg3_mdio_start(struct tg3 *tp)
1039 {
1040         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1041         tw32_f(MAC_MI_MODE, tp->mi_mode);
1042         udelay(80);
1043
1044         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1045             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1046                 tg3_mdio_config_5785(tp);
1047 }
1048
1049 static int tg3_mdio_init(struct tg3 *tp)
1050 {
1051         int i;
1052         u32 reg;
1053         struct phy_device *phydev;
1054
1055         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1056             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
1057                 u32 is_serdes;
1058
1059                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1060
1061                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1062                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1063                 else
1064                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1065                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1066                 if (is_serdes)
1067                         tp->phy_addr += 7;
1068         } else
1069                 tp->phy_addr = TG3_PHY_MII_ADDR;
1070
1071         tg3_mdio_start(tp);
1072
1073         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1074             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1075                 return 0;
1076
1077         tp->mdio_bus = mdiobus_alloc();
1078         if (tp->mdio_bus == NULL)
1079                 return -ENOMEM;
1080
1081         tp->mdio_bus->name     = "tg3 mdio bus";
1082         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1083                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1084         tp->mdio_bus->priv     = tp;
1085         tp->mdio_bus->parent   = &tp->pdev->dev;
1086         tp->mdio_bus->read     = &tg3_mdio_read;
1087         tp->mdio_bus->write    = &tg3_mdio_write;
1088         tp->mdio_bus->reset    = &tg3_mdio_reset;
1089         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1090         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1091
1092         for (i = 0; i < PHY_MAX_ADDR; i++)
1093                 tp->mdio_bus->irq[i] = PHY_POLL;
1094
1095         /* The bus registration will look for all the PHYs on the mdio bus.
1096          * Unfortunately, it does not ensure the PHY is powered up before
1097          * accessing the PHY ID registers.  A chip reset is the
1098          * quickest way to bring the device back to an operational state..
1099          */
1100         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1101                 tg3_bmcr_reset(tp);
1102
1103         i = mdiobus_register(tp->mdio_bus);
1104         if (i) {
1105                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1106                 mdiobus_free(tp->mdio_bus);
1107                 return i;
1108         }
1109
1110         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1111
1112         if (!phydev || !phydev->drv) {
1113                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1114                 mdiobus_unregister(tp->mdio_bus);
1115                 mdiobus_free(tp->mdio_bus);
1116                 return -ENODEV;
1117         }
1118
1119         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1120         case PHY_ID_BCM57780:
1121                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1122                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1123                 break;
1124         case PHY_ID_BCM50610:
1125         case PHY_ID_BCM50610M:
1126                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1127                                      PHY_BRCM_RX_REFCLK_UNUSED |
1128                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1129                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1130                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1131                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1132                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1133                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1134                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1135                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1136                 /* fallthru */
1137         case PHY_ID_RTL8211C:
1138                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1139                 break;
1140         case PHY_ID_RTL8201E:
1141         case PHY_ID_BCMAC131:
1142                 phydev->interface = PHY_INTERFACE_MODE_MII;
1143                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1144                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1145                 break;
1146         }
1147
1148         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1149
1150         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1151                 tg3_mdio_config_5785(tp);
1152
1153         return 0;
1154 }
1155
1156 static void tg3_mdio_fini(struct tg3 *tp)
1157 {
1158         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1159                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1160                 mdiobus_unregister(tp->mdio_bus);
1161                 mdiobus_free(tp->mdio_bus);
1162         }
1163 }
1164
1165 /* tp->lock is held. */
1166 static inline void tg3_generate_fw_event(struct tg3 *tp)
1167 {
1168         u32 val;
1169
1170         val = tr32(GRC_RX_CPU_EVENT);
1171         val |= GRC_RX_CPU_DRIVER_EVENT;
1172         tw32_f(GRC_RX_CPU_EVENT, val);
1173
1174         tp->last_event_jiffies = jiffies;
1175 }
1176
1177 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1178
1179 /* tp->lock is held. */
1180 static void tg3_wait_for_event_ack(struct tg3 *tp)
1181 {
1182         int i;
1183         unsigned int delay_cnt;
1184         long time_remain;
1185
1186         /* If enough time has passed, no wait is necessary. */
1187         time_remain = (long)(tp->last_event_jiffies + 1 +
1188                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1189                       (long)jiffies;
1190         if (time_remain < 0)
1191                 return;
1192
1193         /* Check if we can shorten the wait time. */
1194         delay_cnt = jiffies_to_usecs(time_remain);
1195         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1196                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1197         delay_cnt = (delay_cnt >> 3) + 1;
1198
1199         for (i = 0; i < delay_cnt; i++) {
1200                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1201                         break;
1202                 udelay(8);
1203         }
1204 }
1205
1206 /* tp->lock is held. */
1207 static void tg3_ump_link_report(struct tg3 *tp)
1208 {
1209         u32 reg;
1210         u32 val;
1211
1212         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1213             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1214                 return;
1215
1216         tg3_wait_for_event_ack(tp);
1217
1218         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1219
1220         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1221
1222         val = 0;
1223         if (!tg3_readphy(tp, MII_BMCR, &reg))
1224                 val = reg << 16;
1225         if (!tg3_readphy(tp, MII_BMSR, &reg))
1226                 val |= (reg & 0xffff);
1227         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1228
1229         val = 0;
1230         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1231                 val = reg << 16;
1232         if (!tg3_readphy(tp, MII_LPA, &reg))
1233                 val |= (reg & 0xffff);
1234         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1235
1236         val = 0;
1237         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1238                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1239                         val = reg << 16;
1240                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1241                         val |= (reg & 0xffff);
1242         }
1243         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1244
1245         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1246                 val = reg << 16;
1247         else
1248                 val = 0;
1249         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1250
1251         tg3_generate_fw_event(tp);
1252 }
1253
1254 static void tg3_link_report(struct tg3 *tp)
1255 {
1256         if (!netif_carrier_ok(tp->dev)) {
1257                 netif_info(tp, link, tp->dev, "Link is down\n");
1258                 tg3_ump_link_report(tp);
1259         } else if (netif_msg_link(tp)) {
1260                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1261                             (tp->link_config.active_speed == SPEED_1000 ?
1262                              1000 :
1263                              (tp->link_config.active_speed == SPEED_100 ?
1264                               100 : 10)),
1265                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1266                              "full" : "half"));
1267
1268                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1269                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1270                             "on" : "off",
1271                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1272                             "on" : "off");
1273                 tg3_ump_link_report(tp);
1274         }
1275 }
1276
1277 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1278 {
1279         u16 miireg;
1280
1281         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1282                 miireg = ADVERTISE_PAUSE_CAP;
1283         else if (flow_ctrl & FLOW_CTRL_TX)
1284                 miireg = ADVERTISE_PAUSE_ASYM;
1285         else if (flow_ctrl & FLOW_CTRL_RX)
1286                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1287         else
1288                 miireg = 0;
1289
1290         return miireg;
1291 }
1292
1293 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1294 {
1295         u16 miireg;
1296
1297         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1298                 miireg = ADVERTISE_1000XPAUSE;
1299         else if (flow_ctrl & FLOW_CTRL_TX)
1300                 miireg = ADVERTISE_1000XPSE_ASYM;
1301         else if (flow_ctrl & FLOW_CTRL_RX)
1302                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1303         else
1304                 miireg = 0;
1305
1306         return miireg;
1307 }
1308
1309 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1310 {
1311         u8 cap = 0;
1312
1313         if (lcladv & ADVERTISE_1000XPAUSE) {
1314                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1315                         if (rmtadv & LPA_1000XPAUSE)
1316                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1317                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1318                                 cap = FLOW_CTRL_RX;
1319                 } else {
1320                         if (rmtadv & LPA_1000XPAUSE)
1321                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1322                 }
1323         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1324                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1325                         cap = FLOW_CTRL_TX;
1326         }
1327
1328         return cap;
1329 }
1330
1331 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1332 {
1333         u8 autoneg;
1334         u8 flowctrl = 0;
1335         u32 old_rx_mode = tp->rx_mode;
1336         u32 old_tx_mode = tp->tx_mode;
1337
1338         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1339                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1340         else
1341                 autoneg = tp->link_config.autoneg;
1342
1343         if (autoneg == AUTONEG_ENABLE &&
1344             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1345                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1346                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1347                 else
1348                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1349         } else
1350                 flowctrl = tp->link_config.flowctrl;
1351
1352         tp->link_config.active_flowctrl = flowctrl;
1353
1354         if (flowctrl & FLOW_CTRL_RX)
1355                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1356         else
1357                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1358
1359         if (old_rx_mode != tp->rx_mode)
1360                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1361
1362         if (flowctrl & FLOW_CTRL_TX)
1363                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1364         else
1365                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1366
1367         if (old_tx_mode != tp->tx_mode)
1368                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1369 }
1370
1371 static void tg3_adjust_link(struct net_device *dev)
1372 {
1373         u8 oldflowctrl, linkmesg = 0;
1374         u32 mac_mode, lcl_adv, rmt_adv;
1375         struct tg3 *tp = netdev_priv(dev);
1376         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1377
1378         spin_lock_bh(&tp->lock);
1379
1380         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1381                                     MAC_MODE_HALF_DUPLEX);
1382
1383         oldflowctrl = tp->link_config.active_flowctrl;
1384
1385         if (phydev->link) {
1386                 lcl_adv = 0;
1387                 rmt_adv = 0;
1388
1389                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1390                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1391                 else if (phydev->speed == SPEED_1000 ||
1392                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1393                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1394                 else
1395                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1396
1397                 if (phydev->duplex == DUPLEX_HALF)
1398                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1399                 else {
1400                         lcl_adv = tg3_advert_flowctrl_1000T(
1401                                   tp->link_config.flowctrl);
1402
1403                         if (phydev->pause)
1404                                 rmt_adv = LPA_PAUSE_CAP;
1405                         if (phydev->asym_pause)
1406                                 rmt_adv |= LPA_PAUSE_ASYM;
1407                 }
1408
1409                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1410         } else
1411                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1412
1413         if (mac_mode != tp->mac_mode) {
1414                 tp->mac_mode = mac_mode;
1415                 tw32_f(MAC_MODE, tp->mac_mode);
1416                 udelay(40);
1417         }
1418
1419         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1420                 if (phydev->speed == SPEED_10)
1421                         tw32(MAC_MI_STAT,
1422                              MAC_MI_STAT_10MBPS_MODE |
1423                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1424                 else
1425                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1426         }
1427
1428         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1429                 tw32(MAC_TX_LENGTHS,
1430                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1431                       (6 << TX_LENGTHS_IPG_SHIFT) |
1432                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1433         else
1434                 tw32(MAC_TX_LENGTHS,
1435                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1436                       (6 << TX_LENGTHS_IPG_SHIFT) |
1437                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1438
1439         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1440             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1441             phydev->speed != tp->link_config.active_speed ||
1442             phydev->duplex != tp->link_config.active_duplex ||
1443             oldflowctrl != tp->link_config.active_flowctrl)
1444                 linkmesg = 1;
1445
1446         tp->link_config.active_speed = phydev->speed;
1447         tp->link_config.active_duplex = phydev->duplex;
1448
1449         spin_unlock_bh(&tp->lock);
1450
1451         if (linkmesg)
1452                 tg3_link_report(tp);
1453 }
1454
1455 static int tg3_phy_init(struct tg3 *tp)
1456 {
1457         struct phy_device *phydev;
1458
1459         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1460                 return 0;
1461
1462         /* Bring the PHY back to a known state. */
1463         tg3_bmcr_reset(tp);
1464
1465         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1466
1467         /* Attach the MAC to the PHY. */
1468         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1469                              phydev->dev_flags, phydev->interface);
1470         if (IS_ERR(phydev)) {
1471                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1472                 return PTR_ERR(phydev);
1473         }
1474
1475         /* Mask with MAC supported features. */
1476         switch (phydev->interface) {
1477         case PHY_INTERFACE_MODE_GMII:
1478         case PHY_INTERFACE_MODE_RGMII:
1479                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1480                         phydev->supported &= (PHY_GBIT_FEATURES |
1481                                               SUPPORTED_Pause |
1482                                               SUPPORTED_Asym_Pause);
1483                         break;
1484                 }
1485                 /* fallthru */
1486         case PHY_INTERFACE_MODE_MII:
1487                 phydev->supported &= (PHY_BASIC_FEATURES |
1488                                       SUPPORTED_Pause |
1489                                       SUPPORTED_Asym_Pause);
1490                 break;
1491         default:
1492                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1493                 return -EINVAL;
1494         }
1495
1496         tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1497
1498         phydev->advertising = phydev->supported;
1499
1500         return 0;
1501 }
1502
1503 static void tg3_phy_start(struct tg3 *tp)
1504 {
1505         struct phy_device *phydev;
1506
1507         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1508                 return;
1509
1510         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1511
1512         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1513                 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1514                 phydev->speed = tp->link_config.orig_speed;
1515                 phydev->duplex = tp->link_config.orig_duplex;
1516                 phydev->autoneg = tp->link_config.orig_autoneg;
1517                 phydev->advertising = tp->link_config.orig_advertising;
1518         }
1519
1520         phy_start(phydev);
1521
1522         phy_start_aneg(phydev);
1523 }
1524
1525 static void tg3_phy_stop(struct tg3 *tp)
1526 {
1527         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1528                 return;
1529
1530         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1531 }
1532
1533 static void tg3_phy_fini(struct tg3 *tp)
1534 {
1535         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1536                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1537                 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1538         }
1539 }
1540
1541 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1542 {
1543         int err;
1544
1545         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1546         if (!err)
1547                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1548
1549         return err;
1550 }
1551
1552 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1553 {
1554         u32 phytest;
1555
1556         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1557                 u32 phy;
1558
1559                 tg3_writephy(tp, MII_TG3_FET_TEST,
1560                              phytest | MII_TG3_FET_SHADOW_EN);
1561                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1562                         if (enable)
1563                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1564                         else
1565                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1566                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1567                 }
1568                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1569         }
1570 }
1571
1572 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1573 {
1574         u32 reg;
1575
1576         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1577             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1578               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1579              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1580                 return;
1581
1582         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1583                 tg3_phy_fet_toggle_apd(tp, enable);
1584                 return;
1585         }
1586
1587         reg = MII_TG3_MISC_SHDW_WREN |
1588               MII_TG3_MISC_SHDW_SCR5_SEL |
1589               MII_TG3_MISC_SHDW_SCR5_LPED |
1590               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1591               MII_TG3_MISC_SHDW_SCR5_SDTL |
1592               MII_TG3_MISC_SHDW_SCR5_C125OE;
1593         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1594                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1595
1596         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1597
1598
1599         reg = MII_TG3_MISC_SHDW_WREN |
1600               MII_TG3_MISC_SHDW_APD_SEL |
1601               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1602         if (enable)
1603                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1604
1605         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1606 }
1607
1608 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1609 {
1610         u32 phy;
1611
1612         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1613             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1614                 return;
1615
1616         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1617                 u32 ephy;
1618
1619                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1620                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1621
1622                         tg3_writephy(tp, MII_TG3_FET_TEST,
1623                                      ephy | MII_TG3_FET_SHADOW_EN);
1624                         if (!tg3_readphy(tp, reg, &phy)) {
1625                                 if (enable)
1626                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1627                                 else
1628                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1629                                 tg3_writephy(tp, reg, phy);
1630                         }
1631                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1632                 }
1633         } else {
1634                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1635                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1636                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1637                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1638                         if (enable)
1639                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1640                         else
1641                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1642                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1643                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1644                 }
1645         }
1646 }
1647
1648 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1649 {
1650         u32 val;
1651
1652         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1653                 return;
1654
1655         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1656             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1657                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1658                              (val | (1 << 15) | (1 << 4)));
1659 }
1660
1661 static void tg3_phy_apply_otp(struct tg3 *tp)
1662 {
1663         u32 otp, phy;
1664
1665         if (!tp->phy_otp)
1666                 return;
1667
1668         otp = tp->phy_otp;
1669
1670         /* Enable SM_DSP clock and tx 6dB coding. */
1671         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1672               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1673               MII_TG3_AUXCTL_ACTL_TX_6DB;
1674         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1675
1676         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1677         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1678         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1679
1680         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1681               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1682         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1683
1684         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1685         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1686         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1687
1688         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1689         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1690
1691         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1692         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1693
1694         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1695               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1696         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1697
1698         /* Turn off SM_DSP clock. */
1699         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1700               MII_TG3_AUXCTL_ACTL_TX_6DB;
1701         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1702 }
1703
1704 static int tg3_wait_macro_done(struct tg3 *tp)
1705 {
1706         int limit = 100;
1707
1708         while (limit--) {
1709                 u32 tmp32;
1710
1711                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1712                         if ((tmp32 & 0x1000) == 0)
1713                                 break;
1714                 }
1715         }
1716         if (limit < 0)
1717                 return -EBUSY;
1718
1719         return 0;
1720 }
1721
1722 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1723 {
1724         static const u32 test_pat[4][6] = {
1725         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1726         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1727         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1728         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1729         };
1730         int chan;
1731
1732         for (chan = 0; chan < 4; chan++) {
1733                 int i;
1734
1735                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1736                              (chan * 0x2000) | 0x0200);
1737                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1738
1739                 for (i = 0; i < 6; i++)
1740                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1741                                      test_pat[chan][i]);
1742
1743                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1744                 if (tg3_wait_macro_done(tp)) {
1745                         *resetp = 1;
1746                         return -EBUSY;
1747                 }
1748
1749                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1750                              (chan * 0x2000) | 0x0200);
1751                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1752                 if (tg3_wait_macro_done(tp)) {
1753                         *resetp = 1;
1754                         return -EBUSY;
1755                 }
1756
1757                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1758                 if (tg3_wait_macro_done(tp)) {
1759                         *resetp = 1;
1760                         return -EBUSY;
1761                 }
1762
1763                 for (i = 0; i < 6; i += 2) {
1764                         u32 low, high;
1765
1766                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1767                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1768                             tg3_wait_macro_done(tp)) {
1769                                 *resetp = 1;
1770                                 return -EBUSY;
1771                         }
1772                         low &= 0x7fff;
1773                         high &= 0x000f;
1774                         if (low != test_pat[chan][i] ||
1775                             high != test_pat[chan][i+1]) {
1776                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1777                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1778                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1779
1780                                 return -EBUSY;
1781                         }
1782                 }
1783         }
1784
1785         return 0;
1786 }
1787
1788 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1789 {
1790         int chan;
1791
1792         for (chan = 0; chan < 4; chan++) {
1793                 int i;
1794
1795                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1796                              (chan * 0x2000) | 0x0200);
1797                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1798                 for (i = 0; i < 6; i++)
1799                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1800                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1801                 if (tg3_wait_macro_done(tp))
1802                         return -EBUSY;
1803         }
1804
1805         return 0;
1806 }
1807
1808 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1809 {
1810         u32 reg32, phy9_orig;
1811         int retries, do_phy_reset, err;
1812
1813         retries = 10;
1814         do_phy_reset = 1;
1815         do {
1816                 if (do_phy_reset) {
1817                         err = tg3_bmcr_reset(tp);
1818                         if (err)
1819                                 return err;
1820                         do_phy_reset = 0;
1821                 }
1822
1823                 /* Disable transmitter and interrupt.  */
1824                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1825                         continue;
1826
1827                 reg32 |= 0x3000;
1828                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1829
1830                 /* Set full-duplex, 1000 mbps.  */
1831                 tg3_writephy(tp, MII_BMCR,
1832                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1833
1834                 /* Set to master mode.  */
1835                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1836                         continue;
1837
1838                 tg3_writephy(tp, MII_TG3_CTRL,
1839                              (MII_TG3_CTRL_AS_MASTER |
1840                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1841
1842                 /* Enable SM_DSP_CLOCK and 6dB.  */
1843                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1844
1845                 /* Block the PHY control access.  */
1846                 tg3_phydsp_write(tp, 0x8005, 0x0800);
1847
1848                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1849                 if (!err)
1850                         break;
1851         } while (--retries);
1852
1853         err = tg3_phy_reset_chanpat(tp);
1854         if (err)
1855                 return err;
1856
1857         tg3_phydsp_write(tp, 0x8005, 0x0000);
1858
1859         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1860         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1861
1862         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1863             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1864                 /* Set Extended packet length bit for jumbo frames */
1865                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1866         } else {
1867                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1868         }
1869
1870         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1871
1872         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1873                 reg32 &= ~0x3000;
1874                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1875         } else if (!err)
1876                 err = -EBUSY;
1877
1878         return err;
1879 }
1880
1881 /* This will reset the tigon3 PHY if there is no valid
1882  * link unless the FORCE argument is non-zero.
1883  */
1884 static int tg3_phy_reset(struct tg3 *tp)
1885 {
1886         u32 val, cpmuctrl;
1887         int err;
1888
1889         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1890                 val = tr32(GRC_MISC_CFG);
1891                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1892                 udelay(40);
1893         }
1894         err  = tg3_readphy(tp, MII_BMSR, &val);
1895         err |= tg3_readphy(tp, MII_BMSR, &val);
1896         if (err != 0)
1897                 return -EBUSY;
1898
1899         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1900                 netif_carrier_off(tp->dev);
1901                 tg3_link_report(tp);
1902         }
1903
1904         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1905             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1906             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1907                 err = tg3_phy_reset_5703_4_5(tp);
1908                 if (err)
1909                         return err;
1910                 goto out;
1911         }
1912
1913         cpmuctrl = 0;
1914         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1915             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1916                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1917                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1918                         tw32(TG3_CPMU_CTRL,
1919                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1920         }
1921
1922         err = tg3_bmcr_reset(tp);
1923         if (err)
1924                 return err;
1925
1926         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1927                 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1928                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
1929
1930                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1931         }
1932
1933         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1934             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1935                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1936                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1937                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1938                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1939                         udelay(40);
1940                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1941                 }
1942         }
1943
1944         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1945              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1946             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
1947                 return 0;
1948
1949         tg3_phy_apply_otp(tp);
1950
1951         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
1952                 tg3_phy_toggle_apd(tp, true);
1953         else
1954                 tg3_phy_toggle_apd(tp, false);
1955
1956 out:
1957         if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
1958                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1959                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
1960                 tg3_phydsp_write(tp, 0x000a, 0x0323);
1961                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1962         }
1963         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
1964                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
1965                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
1966         }
1967         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
1968                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1969                 tg3_phydsp_write(tp, 0x000a, 0x310b);
1970                 tg3_phydsp_write(tp, 0x201f, 0x9506);
1971                 tg3_phydsp_write(tp, 0x401f, 0x14e2);
1972                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1973         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
1974                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1975                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1976                 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
1977                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1978                         tg3_writephy(tp, MII_TG3_TEST1,
1979                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1980                 } else
1981                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1982                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1983         }
1984         /* Set Extended packet length bit (bit 14) on all chips that */
1985         /* support jumbo frames */
1986         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1987                 /* Cannot do read-modify-write on 5401 */
1988                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1989         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1990                 /* Set bit 14 with read-modify-write to preserve other bits */
1991                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1992                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1993                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000);
1994         }
1995
1996         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1997          * jumbo frames transmission.
1998          */
1999         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2000                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2001                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2002                                      val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2003         }
2004
2005         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2006                 /* adjust output voltage */
2007                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2008         }
2009
2010         tg3_phy_toggle_automdix(tp, 1);
2011         tg3_phy_set_wirespeed(tp);
2012         return 0;
2013 }
2014
2015 static void tg3_frob_aux_power(struct tg3 *tp)
2016 {
2017         struct tg3 *tp_peer = tp;
2018
2019         /* The GPIOs do something completely different on 57765. */
2020         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2021             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2022             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2023                 return;
2024
2025         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2026             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2027             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2028                 struct net_device *dev_peer;
2029
2030                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2031                 /* remove_one() may have been run on the peer. */
2032                 if (!dev_peer)
2033                         tp_peer = tp;
2034                 else
2035                         tp_peer = netdev_priv(dev_peer);
2036         }
2037
2038         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2039             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2040             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2041             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2042                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2043                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2044                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2045                                     (GRC_LCLCTRL_GPIO_OE0 |
2046                                      GRC_LCLCTRL_GPIO_OE1 |
2047                                      GRC_LCLCTRL_GPIO_OE2 |
2048                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2049                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2050                                     100);
2051                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2052                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2053                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2054                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2055                                              GRC_LCLCTRL_GPIO_OE1 |
2056                                              GRC_LCLCTRL_GPIO_OE2 |
2057                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2058                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2059                                              tp->grc_local_ctrl;
2060                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2061
2062                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2063                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2064
2065                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2066                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2067                 } else {
2068                         u32 no_gpio2;
2069                         u32 grc_local_ctrl = 0;
2070
2071                         if (tp_peer != tp &&
2072                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2073                                 return;
2074
2075                         /* Workaround to prevent overdrawing Amps. */
2076                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2077                             ASIC_REV_5714) {
2078                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2079                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2080                                             grc_local_ctrl, 100);
2081                         }
2082
2083                         /* On 5753 and variants, GPIO2 cannot be used. */
2084                         no_gpio2 = tp->nic_sram_data_cfg &
2085                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2086
2087                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2088                                          GRC_LCLCTRL_GPIO_OE1 |
2089                                          GRC_LCLCTRL_GPIO_OE2 |
2090                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2091                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2092                         if (no_gpio2) {
2093                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2094                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2095                         }
2096                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2097                                                     grc_local_ctrl, 100);
2098
2099                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2100
2101                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2102                                                     grc_local_ctrl, 100);
2103
2104                         if (!no_gpio2) {
2105                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2106                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2107                                             grc_local_ctrl, 100);
2108                         }
2109                 }
2110         } else {
2111                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2112                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2113                         if (tp_peer != tp &&
2114                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2115                                 return;
2116
2117                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2118                                     (GRC_LCLCTRL_GPIO_OE1 |
2119                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2120
2121                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2122                                     GRC_LCLCTRL_GPIO_OE1, 100);
2123
2124                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2125                                     (GRC_LCLCTRL_GPIO_OE1 |
2126                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2127                 }
2128         }
2129 }
2130
2131 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2132 {
2133         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2134                 return 1;
2135         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2136                 if (speed != SPEED_10)
2137                         return 1;
2138         } else if (speed == SPEED_10)
2139                 return 1;
2140
2141         return 0;
2142 }
2143
2144 static int tg3_setup_phy(struct tg3 *, int);
2145
2146 #define RESET_KIND_SHUTDOWN     0
2147 #define RESET_KIND_INIT         1
2148 #define RESET_KIND_SUSPEND      2
2149
2150 static void tg3_write_sig_post_reset(struct tg3 *, int);
2151 static int tg3_halt_cpu(struct tg3 *, u32);
2152
2153 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2154 {
2155         u32 val;
2156
2157         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2158                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2159                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2160                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2161
2162                         sg_dig_ctrl |=
2163                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2164                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2165                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2166                 }
2167                 return;
2168         }
2169
2170         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2171                 tg3_bmcr_reset(tp);
2172                 val = tr32(GRC_MISC_CFG);
2173                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2174                 udelay(40);
2175                 return;
2176         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2177                 u32 phytest;
2178                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2179                         u32 phy;
2180
2181                         tg3_writephy(tp, MII_ADVERTISE, 0);
2182                         tg3_writephy(tp, MII_BMCR,
2183                                      BMCR_ANENABLE | BMCR_ANRESTART);
2184
2185                         tg3_writephy(tp, MII_TG3_FET_TEST,
2186                                      phytest | MII_TG3_FET_SHADOW_EN);
2187                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2188                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2189                                 tg3_writephy(tp,
2190                                              MII_TG3_FET_SHDW_AUXMODE4,
2191                                              phy);
2192                         }
2193                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2194                 }
2195                 return;
2196         } else if (do_low_power) {
2197                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2198                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2199
2200                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2201                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2202                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2203                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2204                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2205         }
2206
2207         /* The PHY should not be powered down on some chips because
2208          * of bugs.
2209          */
2210         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2211             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2212             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2213              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2214                 return;
2215
2216         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2217             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2218                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2219                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2220                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2221                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2222         }
2223
2224         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2225 }
2226
2227 /* tp->lock is held. */
2228 static int tg3_nvram_lock(struct tg3 *tp)
2229 {
2230         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2231                 int i;
2232
2233                 if (tp->nvram_lock_cnt == 0) {
2234                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2235                         for (i = 0; i < 8000; i++) {
2236                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2237                                         break;
2238                                 udelay(20);
2239                         }
2240                         if (i == 8000) {
2241                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2242                                 return -ENODEV;
2243                         }
2244                 }
2245                 tp->nvram_lock_cnt++;
2246         }
2247         return 0;
2248 }
2249
2250 /* tp->lock is held. */
2251 static void tg3_nvram_unlock(struct tg3 *tp)
2252 {
2253         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2254                 if (tp->nvram_lock_cnt > 0)
2255                         tp->nvram_lock_cnt--;
2256                 if (tp->nvram_lock_cnt == 0)
2257                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2258         }
2259 }
2260
2261 /* tp->lock is held. */
2262 static void tg3_enable_nvram_access(struct tg3 *tp)
2263 {
2264         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2265             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2266                 u32 nvaccess = tr32(NVRAM_ACCESS);
2267
2268                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2269         }
2270 }
2271
2272 /* tp->lock is held. */
2273 static void tg3_disable_nvram_access(struct tg3 *tp)
2274 {
2275         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2276             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2277                 u32 nvaccess = tr32(NVRAM_ACCESS);
2278
2279                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2280         }
2281 }
2282
2283 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2284                                         u32 offset, u32 *val)
2285 {
2286         u32 tmp;
2287         int i;
2288
2289         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2290                 return -EINVAL;
2291
2292         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2293                                         EEPROM_ADDR_DEVID_MASK |
2294                                         EEPROM_ADDR_READ);
2295         tw32(GRC_EEPROM_ADDR,
2296              tmp |
2297              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2298              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2299               EEPROM_ADDR_ADDR_MASK) |
2300              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2301
2302         for (i = 0; i < 1000; i++) {
2303                 tmp = tr32(GRC_EEPROM_ADDR);
2304
2305                 if (tmp & EEPROM_ADDR_COMPLETE)
2306                         break;
2307                 msleep(1);
2308         }
2309         if (!(tmp & EEPROM_ADDR_COMPLETE))
2310                 return -EBUSY;
2311
2312         tmp = tr32(GRC_EEPROM_DATA);
2313
2314         /*
2315          * The data will always be opposite the native endian
2316          * format.  Perform a blind byteswap to compensate.
2317          */
2318         *val = swab32(tmp);
2319
2320         return 0;
2321 }
2322
2323 #define NVRAM_CMD_TIMEOUT 10000
2324
2325 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2326 {
2327         int i;
2328
2329         tw32(NVRAM_CMD, nvram_cmd);
2330         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2331                 udelay(10);
2332                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2333                         udelay(10);
2334                         break;
2335                 }
2336         }
2337
2338         if (i == NVRAM_CMD_TIMEOUT)
2339                 return -EBUSY;
2340
2341         return 0;
2342 }
2343
2344 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2345 {
2346         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2347             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2348             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2349            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2350             (tp->nvram_jedecnum == JEDEC_ATMEL))
2351
2352                 addr = ((addr / tp->nvram_pagesize) <<
2353                         ATMEL_AT45DB0X1B_PAGE_POS) +
2354                        (addr % tp->nvram_pagesize);
2355
2356         return addr;
2357 }
2358
2359 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2360 {
2361         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2362             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2363             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2364            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2365             (tp->nvram_jedecnum == JEDEC_ATMEL))
2366
2367                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2368                         tp->nvram_pagesize) +
2369                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2370
2371         return addr;
2372 }
2373
2374 /* NOTE: Data read in from NVRAM is byteswapped according to
2375  * the byteswapping settings for all other register accesses.
2376  * tg3 devices are BE devices, so on a BE machine, the data
2377  * returned will be exactly as it is seen in NVRAM.  On a LE
2378  * machine, the 32-bit value will be byteswapped.
2379  */
2380 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2381 {
2382         int ret;
2383
2384         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2385                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2386
2387         offset = tg3_nvram_phys_addr(tp, offset);
2388
2389         if (offset > NVRAM_ADDR_MSK)
2390                 return -EINVAL;
2391
2392         ret = tg3_nvram_lock(tp);
2393         if (ret)
2394                 return ret;
2395
2396         tg3_enable_nvram_access(tp);
2397
2398         tw32(NVRAM_ADDR, offset);
2399         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2400                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2401
2402         if (ret == 0)
2403                 *val = tr32(NVRAM_RDDATA);
2404
2405         tg3_disable_nvram_access(tp);
2406
2407         tg3_nvram_unlock(tp);
2408
2409         return ret;
2410 }
2411
2412 /* Ensures NVRAM data is in bytestream format. */
2413 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2414 {
2415         u32 v;
2416         int res = tg3_nvram_read(tp, offset, &v);
2417         if (!res)
2418                 *val = cpu_to_be32(v);
2419         return res;
2420 }
2421
2422 /* tp->lock is held. */
2423 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2424 {
2425         u32 addr_high, addr_low;
2426         int i;
2427
2428         addr_high = ((tp->dev->dev_addr[0] << 8) |
2429                      tp->dev->dev_addr[1]);
2430         addr_low = ((tp->dev->dev_addr[2] << 24) |
2431                     (tp->dev->dev_addr[3] << 16) |
2432                     (tp->dev->dev_addr[4] <<  8) |
2433                     (tp->dev->dev_addr[5] <<  0));
2434         for (i = 0; i < 4; i++) {
2435                 if (i == 1 && skip_mac_1)
2436                         continue;
2437                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2438                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2439         }
2440
2441         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2442             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2443                 for (i = 0; i < 12; i++) {
2444                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2445                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2446                 }
2447         }
2448
2449         addr_high = (tp->dev->dev_addr[0] +
2450                      tp->dev->dev_addr[1] +
2451                      tp->dev->dev_addr[2] +
2452                      tp->dev->dev_addr[3] +
2453                      tp->dev->dev_addr[4] +
2454                      tp->dev->dev_addr[5]) &
2455                 TX_BACKOFF_SEED_MASK;
2456         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2457 }
2458
2459 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2460 {
2461         u32 misc_host_ctrl;
2462         bool device_should_wake, do_low_power;
2463
2464         /* Make sure register accesses (indirect or otherwise)
2465          * will function correctly.
2466          */
2467         pci_write_config_dword(tp->pdev,
2468                                TG3PCI_MISC_HOST_CTRL,
2469                                tp->misc_host_ctrl);
2470
2471         switch (state) {
2472         case PCI_D0:
2473                 pci_enable_wake(tp->pdev, state, false);
2474                 pci_set_power_state(tp->pdev, PCI_D0);
2475
2476                 /* Switch out of Vaux if it is a NIC */
2477                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2478                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2479
2480                 return 0;
2481
2482         case PCI_D1:
2483         case PCI_D2:
2484         case PCI_D3hot:
2485                 break;
2486
2487         default:
2488                 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2489                            state);
2490                 return -EINVAL;
2491         }
2492
2493         /* Restore the CLKREQ setting. */
2494         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2495                 u16 lnkctl;
2496
2497                 pci_read_config_word(tp->pdev,
2498                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2499                                      &lnkctl);
2500                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2501                 pci_write_config_word(tp->pdev,
2502                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2503                                       lnkctl);
2504         }
2505
2506         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2507         tw32(TG3PCI_MISC_HOST_CTRL,
2508              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2509
2510         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2511                              device_may_wakeup(&tp->pdev->dev) &&
2512                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2513
2514         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2515                 do_low_power = false;
2516                 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2517                     !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2518                         struct phy_device *phydev;
2519                         u32 phyid, advertising;
2520
2521                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2522
2523                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2524
2525                         tp->link_config.orig_speed = phydev->speed;
2526                         tp->link_config.orig_duplex = phydev->duplex;
2527                         tp->link_config.orig_autoneg = phydev->autoneg;
2528                         tp->link_config.orig_advertising = phydev->advertising;
2529
2530                         advertising = ADVERTISED_TP |
2531                                       ADVERTISED_Pause |
2532                                       ADVERTISED_Autoneg |
2533                                       ADVERTISED_10baseT_Half;
2534
2535                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2536                             device_should_wake) {
2537                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2538                                         advertising |=
2539                                                 ADVERTISED_100baseT_Half |
2540                                                 ADVERTISED_100baseT_Full |
2541                                                 ADVERTISED_10baseT_Full;
2542                                 else
2543                                         advertising |= ADVERTISED_10baseT_Full;
2544                         }
2545
2546                         phydev->advertising = advertising;
2547
2548                         phy_start_aneg(phydev);
2549
2550                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2551                         if (phyid != PHY_ID_BCMAC131) {
2552                                 phyid &= PHY_BCM_OUI_MASK;
2553                                 if (phyid == PHY_BCM_OUI_1 ||
2554                                     phyid == PHY_BCM_OUI_2 ||
2555                                     phyid == PHY_BCM_OUI_3)
2556                                         do_low_power = true;
2557                         }
2558                 }
2559         } else {
2560                 do_low_power = true;
2561
2562                 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2563                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2564                         tp->link_config.orig_speed = tp->link_config.speed;
2565                         tp->link_config.orig_duplex = tp->link_config.duplex;
2566                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2567                 }
2568
2569                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2570                         tp->link_config.speed = SPEED_10;
2571                         tp->link_config.duplex = DUPLEX_HALF;
2572                         tp->link_config.autoneg = AUTONEG_ENABLE;
2573                         tg3_setup_phy(tp, 0);
2574                 }
2575         }
2576
2577         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2578                 u32 val;
2579
2580                 val = tr32(GRC_VCPU_EXT_CTRL);
2581                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2582         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2583                 int i;
2584                 u32 val;
2585
2586                 for (i = 0; i < 200; i++) {
2587                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2588                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2589                                 break;
2590                         msleep(1);
2591                 }
2592         }
2593         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2594                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2595                                                      WOL_DRV_STATE_SHUTDOWN |
2596                                                      WOL_DRV_WOL |
2597                                                      WOL_SET_MAGIC_PKT);
2598
2599         if (device_should_wake) {
2600                 u32 mac_mode;
2601
2602                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2603                         if (do_low_power) {
2604                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2605                                 udelay(40);
2606                         }
2607
2608                         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2609                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2610                         else
2611                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2612
2613                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2614                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2615                             ASIC_REV_5700) {
2616                                 u32 speed = (tp->tg3_flags &
2617                                              TG3_FLAG_WOL_SPEED_100MB) ?
2618                                              SPEED_100 : SPEED_10;
2619                                 if (tg3_5700_link_polarity(tp, speed))
2620                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2621                                 else
2622                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2623                         }
2624                 } else {
2625                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2626                 }
2627
2628                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2629                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2630
2631                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2632                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2633                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2634                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2635                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2636                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2637
2638                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2639                         mac_mode |= tp->mac_mode &
2640                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2641                         if (mac_mode & MAC_MODE_APE_TX_EN)
2642                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2643                 }
2644
2645                 tw32_f(MAC_MODE, mac_mode);
2646                 udelay(100);
2647
2648                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2649                 udelay(10);
2650         }
2651
2652         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2653             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2654              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2655                 u32 base_val;
2656
2657                 base_val = tp->pci_clock_ctrl;
2658                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2659                              CLOCK_CTRL_TXCLK_DISABLE);
2660
2661                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2662                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2663         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2664                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2665                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2666                 /* do nothing */
2667         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2668                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2669                 u32 newbits1, newbits2;
2670
2671                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2672                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2673                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2674                                     CLOCK_CTRL_TXCLK_DISABLE |
2675                                     CLOCK_CTRL_ALTCLK);
2676                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2677                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2678                         newbits1 = CLOCK_CTRL_625_CORE;
2679                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2680                 } else {
2681                         newbits1 = CLOCK_CTRL_ALTCLK;
2682                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2683                 }
2684
2685                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2686                             40);
2687
2688                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2689                             40);
2690
2691                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2692                         u32 newbits3;
2693
2694                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2695                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2696                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2697                                             CLOCK_CTRL_TXCLK_DISABLE |
2698                                             CLOCK_CTRL_44MHZ_CORE);
2699                         } else {
2700                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2701                         }
2702
2703                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2704                                     tp->pci_clock_ctrl | newbits3, 40);
2705                 }
2706         }
2707
2708         if (!(device_should_wake) &&
2709             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2710                 tg3_power_down_phy(tp, do_low_power);
2711
2712         tg3_frob_aux_power(tp);
2713
2714         /* Workaround for unstable PLL clock */
2715         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2716             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2717                 u32 val = tr32(0x7d00);
2718
2719                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2720                 tw32(0x7d00, val);
2721                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2722                         int err;
2723
2724                         err = tg3_nvram_lock(tp);
2725                         tg3_halt_cpu(tp, RX_CPU_BASE);
2726                         if (!err)
2727                                 tg3_nvram_unlock(tp);
2728                 }
2729         }
2730
2731         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2732
2733         if (device_should_wake)
2734                 pci_enable_wake(tp->pdev, state, true);
2735
2736         /* Finally, set the new power state. */
2737         pci_set_power_state(tp->pdev, state);
2738
2739         return 0;
2740 }
2741
2742 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2743 {
2744         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2745         case MII_TG3_AUX_STAT_10HALF:
2746                 *speed = SPEED_10;
2747                 *duplex = DUPLEX_HALF;
2748                 break;
2749
2750         case MII_TG3_AUX_STAT_10FULL:
2751                 *speed = SPEED_10;
2752                 *duplex = DUPLEX_FULL;
2753                 break;
2754
2755         case MII_TG3_AUX_STAT_100HALF:
2756                 *speed = SPEED_100;
2757                 *duplex = DUPLEX_HALF;
2758                 break;
2759
2760         case MII_TG3_AUX_STAT_100FULL:
2761                 *speed = SPEED_100;
2762                 *duplex = DUPLEX_FULL;
2763                 break;
2764
2765         case MII_TG3_AUX_STAT_1000HALF:
2766                 *speed = SPEED_1000;
2767                 *duplex = DUPLEX_HALF;
2768                 break;
2769
2770         case MII_TG3_AUX_STAT_1000FULL:
2771                 *speed = SPEED_1000;
2772                 *duplex = DUPLEX_FULL;
2773                 break;
2774
2775         default:
2776                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2777                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2778                                  SPEED_10;
2779                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2780                                   DUPLEX_HALF;
2781                         break;
2782                 }
2783                 *speed = SPEED_INVALID;
2784                 *duplex = DUPLEX_INVALID;
2785                 break;
2786         }
2787 }
2788
2789 static void tg3_phy_copper_begin(struct tg3 *tp)
2790 {
2791         u32 new_adv;
2792         int i;
2793
2794         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2795                 /* Entering low power mode.  Disable gigabit and
2796                  * 100baseT advertisements.
2797                  */
2798                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2799
2800                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2801                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2802                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2803                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2804
2805                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2806         } else if (tp->link_config.speed == SPEED_INVALID) {
2807                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2808                         tp->link_config.advertising &=
2809                                 ~(ADVERTISED_1000baseT_Half |
2810                                   ADVERTISED_1000baseT_Full);
2811
2812                 new_adv = ADVERTISE_CSMA;
2813                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2814                         new_adv |= ADVERTISE_10HALF;
2815                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2816                         new_adv |= ADVERTISE_10FULL;
2817                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2818                         new_adv |= ADVERTISE_100HALF;
2819                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2820                         new_adv |= ADVERTISE_100FULL;
2821
2822                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2823
2824                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2825
2826                 if (tp->link_config.advertising &
2827                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2828                         new_adv = 0;
2829                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2830                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2831                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2832                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2833                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
2834                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2835                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2836                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2837                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2838                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2839                 } else {
2840                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2841                 }
2842         } else {
2843                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2844                 new_adv |= ADVERTISE_CSMA;
2845
2846                 /* Asking for a specific link mode. */
2847                 if (tp->link_config.speed == SPEED_1000) {
2848                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2849
2850                         if (tp->link_config.duplex == DUPLEX_FULL)
2851                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2852                         else
2853                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2854                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2855                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2856                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2857                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2858                 } else {
2859                         if (tp->link_config.speed == SPEED_100) {
2860                                 if (tp->link_config.duplex == DUPLEX_FULL)
2861                                         new_adv |= ADVERTISE_100FULL;
2862                                 else
2863                                         new_adv |= ADVERTISE_100HALF;
2864                         } else {
2865                                 if (tp->link_config.duplex == DUPLEX_FULL)
2866                                         new_adv |= ADVERTISE_10FULL;
2867                                 else
2868                                         new_adv |= ADVERTISE_10HALF;
2869                         }
2870                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2871
2872                         new_adv = 0;
2873                 }
2874
2875                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2876         }
2877
2878         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2879             tp->link_config.speed != SPEED_INVALID) {
2880                 u32 bmcr, orig_bmcr;
2881
2882                 tp->link_config.active_speed = tp->link_config.speed;
2883                 tp->link_config.active_duplex = tp->link_config.duplex;
2884
2885                 bmcr = 0;
2886                 switch (tp->link_config.speed) {
2887                 default:
2888                 case SPEED_10:
2889                         break;
2890
2891                 case SPEED_100:
2892                         bmcr |= BMCR_SPEED100;
2893                         break;
2894
2895                 case SPEED_1000:
2896                         bmcr |= TG3_BMCR_SPEED1000;
2897                         break;
2898                 }
2899
2900                 if (tp->link_config.duplex == DUPLEX_FULL)
2901                         bmcr |= BMCR_FULLDPLX;
2902
2903                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2904                     (bmcr != orig_bmcr)) {
2905                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2906                         for (i = 0; i < 1500; i++) {
2907                                 u32 tmp;
2908
2909                                 udelay(10);
2910                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2911                                     tg3_readphy(tp, MII_BMSR, &tmp))
2912                                         continue;
2913                                 if (!(tmp & BMSR_LSTATUS)) {
2914                                         udelay(40);
2915                                         break;
2916                                 }
2917                         }
2918                         tg3_writephy(tp, MII_BMCR, bmcr);
2919                         udelay(40);
2920                 }
2921         } else {
2922                 tg3_writephy(tp, MII_BMCR,
2923                              BMCR_ANENABLE | BMCR_ANRESTART);
2924         }
2925 }
2926
2927 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2928 {
2929         int err;
2930
2931         /* Turn off tap power management. */
2932         /* Set Extended packet length bit */
2933         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2934
2935         err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
2936         err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
2937         err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
2938         err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
2939         err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
2940
2941         udelay(40);
2942
2943         return err;
2944 }
2945
2946 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2947 {
2948         u32 adv_reg, all_mask = 0;
2949
2950         if (mask & ADVERTISED_10baseT_Half)
2951                 all_mask |= ADVERTISE_10HALF;
2952         if (mask & ADVERTISED_10baseT_Full)
2953                 all_mask |= ADVERTISE_10FULL;
2954         if (mask & ADVERTISED_100baseT_Half)
2955                 all_mask |= ADVERTISE_100HALF;
2956         if (mask & ADVERTISED_100baseT_Full)
2957                 all_mask |= ADVERTISE_100FULL;
2958
2959         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2960                 return 0;
2961
2962         if ((adv_reg & all_mask) != all_mask)
2963                 return 0;
2964         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
2965                 u32 tg3_ctrl;
2966
2967                 all_mask = 0;
2968                 if (mask & ADVERTISED_1000baseT_Half)
2969                         all_mask |= ADVERTISE_1000HALF;
2970                 if (mask & ADVERTISED_1000baseT_Full)
2971                         all_mask |= ADVERTISE_1000FULL;
2972
2973                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2974                         return 0;
2975
2976                 if ((tg3_ctrl & all_mask) != all_mask)
2977                         return 0;
2978         }
2979         return 1;
2980 }
2981
2982 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2983 {
2984         u32 curadv, reqadv;
2985
2986         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2987                 return 1;
2988
2989         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2990         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2991
2992         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2993                 if (curadv != reqadv)
2994                         return 0;
2995
2996                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2997                         tg3_readphy(tp, MII_LPA, rmtadv);
2998         } else {
2999                 /* Reprogram the advertisement register, even if it
3000                  * does not affect the current link.  If the link
3001                  * gets renegotiated in the future, we can save an
3002                  * additional renegotiation cycle by advertising
3003                  * it correctly in the first place.
3004                  */
3005                 if (curadv != reqadv) {
3006                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3007                                      ADVERTISE_PAUSE_ASYM);
3008                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3009                 }
3010         }
3011
3012         return 1;
3013 }
3014
3015 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3016 {
3017         int current_link_up;
3018         u32 bmsr, val;
3019         u32 lcl_adv, rmt_adv;
3020         u16 current_speed;
3021         u8 current_duplex;
3022         int i, err;
3023
3024         tw32(MAC_EVENT, 0);
3025
3026         tw32_f(MAC_STATUS,
3027              (MAC_STATUS_SYNC_CHANGED |
3028               MAC_STATUS_CFG_CHANGED |
3029               MAC_STATUS_MI_COMPLETION |
3030               MAC_STATUS_LNKSTATE_CHANGED));
3031         udelay(40);
3032
3033         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3034                 tw32_f(MAC_MI_MODE,
3035                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3036                 udelay(80);
3037         }
3038
3039         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3040
3041         /* Some third-party PHYs need to be reset on link going
3042          * down.
3043          */
3044         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3045              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3046              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3047             netif_carrier_ok(tp->dev)) {
3048                 tg3_readphy(tp, MII_BMSR, &bmsr);
3049                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3050                     !(bmsr & BMSR_LSTATUS))
3051                         force_reset = 1;
3052         }
3053         if (force_reset)
3054                 tg3_phy_reset(tp);
3055
3056         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3057                 tg3_readphy(tp, MII_BMSR, &bmsr);
3058                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3059                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3060                         bmsr = 0;
3061
3062                 if (!(bmsr & BMSR_LSTATUS)) {
3063                         err = tg3_init_5401phy_dsp(tp);
3064                         if (err)
3065                                 return err;
3066
3067                         tg3_readphy(tp, MII_BMSR, &bmsr);
3068                         for (i = 0; i < 1000; i++) {
3069                                 udelay(10);
3070                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3071                                     (bmsr & BMSR_LSTATUS)) {
3072                                         udelay(40);
3073                                         break;
3074                                 }
3075                         }
3076
3077                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3078                             TG3_PHY_REV_BCM5401_B0 &&
3079                             !(bmsr & BMSR_LSTATUS) &&
3080                             tp->link_config.active_speed == SPEED_1000) {
3081                                 err = tg3_phy_reset(tp);
3082                                 if (!err)
3083                                         err = tg3_init_5401phy_dsp(tp);
3084                                 if (err)
3085                                         return err;
3086                         }
3087                 }
3088         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3089                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3090                 /* 5701 {A0,B0} CRC bug workaround */
3091                 tg3_writephy(tp, 0x15, 0x0a75);
3092                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3093                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3094                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3095         }
3096
3097         /* Clear pending interrupts... */
3098         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3099         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3100
3101         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3102                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3103         else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3104                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3105
3106         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3107             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3108                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3109                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3110                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3111                 else
3112                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3113         }
3114
3115         current_link_up = 0;
3116         current_speed = SPEED_INVALID;
3117         current_duplex = DUPLEX_INVALID;
3118
3119         if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3120                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3121                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3122                 if (!(val & (1 << 10))) {
3123                         val |= (1 << 10);
3124                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3125                         goto relink;
3126                 }
3127         }
3128
3129         bmsr = 0;
3130         for (i = 0; i < 100; i++) {
3131                 tg3_readphy(tp, MII_BMSR, &bmsr);
3132                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3133                     (bmsr & BMSR_LSTATUS))
3134                         break;
3135                 udelay(40);
3136         }
3137
3138         if (bmsr & BMSR_LSTATUS) {
3139                 u32 aux_stat, bmcr;
3140
3141                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3142                 for (i = 0; i < 2000; i++) {
3143                         udelay(10);
3144                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3145                             aux_stat)
3146                                 break;
3147                 }
3148
3149                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3150                                              &current_speed,
3151                                              &current_duplex);
3152
3153                 bmcr = 0;
3154                 for (i = 0; i < 200; i++) {
3155                         tg3_readphy(tp, MII_BMCR, &bmcr);
3156                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3157                                 continue;
3158                         if (bmcr && bmcr != 0x7fff)
3159                                 break;
3160                         udelay(10);
3161                 }
3162
3163                 lcl_adv = 0;
3164                 rmt_adv = 0;
3165
3166                 tp->link_config.active_speed = current_speed;
3167                 tp->link_config.active_duplex = current_duplex;
3168
3169                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3170                         if ((bmcr & BMCR_ANENABLE) &&
3171                             tg3_copper_is_advertising_all(tp,
3172                                                 tp->link_config.advertising)) {
3173                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3174                                                                   &rmt_adv))
3175                                         current_link_up = 1;
3176                         }
3177                 } else {
3178                         if (!(bmcr & BMCR_ANENABLE) &&
3179                             tp->link_config.speed == current_speed &&
3180                             tp->link_config.duplex == current_duplex &&
3181                             tp->link_config.flowctrl ==
3182                             tp->link_config.active_flowctrl) {
3183                                 current_link_up = 1;
3184                         }
3185                 }
3186
3187                 if (current_link_up == 1 &&
3188                     tp->link_config.active_duplex == DUPLEX_FULL)
3189                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3190         }
3191
3192 relink:
3193         if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3194                 tg3_phy_copper_begin(tp);
3195
3196                 tg3_readphy(tp, MII_BMSR, &bmsr);
3197                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3198                     (bmsr & BMSR_LSTATUS))
3199                         current_link_up = 1;
3200         }
3201
3202         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3203         if (current_link_up == 1) {
3204                 if (tp->link_config.active_speed == SPEED_100 ||
3205                     tp->link_config.active_speed == SPEED_10)
3206                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3207                 else
3208                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3209         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3210                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3211         else
3212                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3213
3214         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3215         if (tp->link_config.active_duplex == DUPLEX_HALF)
3216                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3217
3218         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3219                 if (current_link_up == 1 &&
3220                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3221                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3222                 else
3223                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3224         }
3225
3226         /* ??? Without this setting Netgear GA302T PHY does not
3227          * ??? send/receive packets...
3228          */
3229         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3230             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3231                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3232                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3233                 udelay(80);
3234         }
3235
3236         tw32_f(MAC_MODE, tp->mac_mode);
3237         udelay(40);
3238
3239         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3240                 /* Polled via timer. */
3241                 tw32_f(MAC_EVENT, 0);
3242         } else {
3243                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3244         }
3245         udelay(40);
3246
3247         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3248             current_link_up == 1 &&
3249             tp->link_config.active_speed == SPEED_1000 &&
3250             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3251              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3252                 udelay(120);
3253                 tw32_f(MAC_STATUS,
3254                      (MAC_STATUS_SYNC_CHANGED |
3255                       MAC_STATUS_CFG_CHANGED));
3256                 udelay(40);
3257                 tg3_write_mem(tp,
3258                               NIC_SRAM_FIRMWARE_MBOX,
3259                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3260         }
3261
3262         /* Prevent send BD corruption. */
3263         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3264                 u16 oldlnkctl, newlnkctl;
3265
3266                 pci_read_config_word(tp->pdev,
3267                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3268                                      &oldlnkctl);
3269                 if (tp->link_config.active_speed == SPEED_100 ||
3270                     tp->link_config.active_speed == SPEED_10)
3271                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3272                 else
3273                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3274                 if (newlnkctl != oldlnkctl)
3275                         pci_write_config_word(tp->pdev,
3276                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3277                                               newlnkctl);
3278         }
3279
3280         if (current_link_up != netif_carrier_ok(tp->dev)) {
3281                 if (current_link_up)
3282                         netif_carrier_on(tp->dev);
3283                 else
3284                         netif_carrier_off(tp->dev);
3285                 tg3_link_report(tp);
3286         }
3287
3288         return 0;
3289 }
3290
3291 struct tg3_fiber_aneginfo {
3292         int state;
3293 #define ANEG_STATE_UNKNOWN              0
3294 #define ANEG_STATE_AN_ENABLE            1
3295 #define ANEG_STATE_RESTART_INIT         2
3296 #define ANEG_STATE_RESTART              3
3297 #define ANEG_STATE_DISABLE_LINK_OK      4
3298 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3299 #define ANEG_STATE_ABILITY_DETECT       6
3300 #define ANEG_STATE_ACK_DETECT_INIT      7
3301 #define ANEG_STATE_ACK_DETECT           8
3302 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3303 #define ANEG_STATE_COMPLETE_ACK         10
3304 #define ANEG_STATE_IDLE_DETECT_INIT     11
3305 #define ANEG_STATE_IDLE_DETECT          12
3306 #define ANEG_STATE_LINK_OK              13
3307 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3308 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3309
3310         u32 flags;
3311 #define MR_AN_ENABLE            0x00000001
3312 #define MR_RESTART_AN           0x00000002
3313 #define MR_AN_COMPLETE          0x00000004
3314 #define MR_PAGE_RX              0x00000008
3315 #define MR_NP_LOADED            0x00000010
3316 #define MR_TOGGLE_TX            0x00000020
3317 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3318 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3319 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3320 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3321 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3322 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3323 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3324 #define MR_TOGGLE_RX            0x00002000
3325 #define MR_NP_RX                0x00004000
3326
3327 #define MR_LINK_OK              0x80000000
3328
3329         unsigned long link_time, cur_time;
3330
3331         u32 ability_match_cfg;
3332         int ability_match_count;
3333
3334         char ability_match, idle_match, ack_match;
3335
3336         u32 txconfig, rxconfig;
3337 #define ANEG_CFG_NP             0x00000080
3338 #define ANEG_CFG_ACK            0x00000040
3339 #define ANEG_CFG_RF2            0x00000020
3340 #define ANEG_CFG_RF1            0x00000010
3341 #define ANEG_CFG_PS2            0x00000001
3342 #define ANEG_CFG_PS1            0x00008000
3343 #define ANEG_CFG_HD             0x00004000
3344 #define ANEG_CFG_FD             0x00002000
3345 #define ANEG_CFG_INVAL          0x00001f06
3346
3347 };
3348 #define ANEG_OK         0
3349 #define ANEG_DONE       1
3350 #define ANEG_TIMER_ENAB 2
3351 #define ANEG_FAILED     -1
3352
3353 #define ANEG_STATE_SETTLE_TIME  10000
3354
3355 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3356                                    struct tg3_fiber_aneginfo *ap)
3357 {
3358         u16 flowctrl;
3359         unsigned long delta;
3360         u32 rx_cfg_reg;
3361         int ret;
3362
3363         if (ap->state == ANEG_STATE_UNKNOWN) {
3364                 ap->rxconfig = 0;
3365                 ap->link_time = 0;
3366                 ap->cur_time = 0;
3367                 ap->ability_match_cfg = 0;
3368                 ap->ability_match_count = 0;
3369                 ap->ability_match = 0;
3370                 ap->idle_match = 0;
3371                 ap->ack_match = 0;
3372         }
3373         ap->cur_time++;
3374
3375         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3376                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3377
3378                 if (rx_cfg_reg != ap->ability_match_cfg) {
3379                         ap->ability_match_cfg = rx_cfg_reg;
3380                         ap->ability_match = 0;
3381                         ap->ability_match_count = 0;
3382                 } else {
3383                         if (++ap->ability_match_count > 1) {
3384                                 ap->ability_match = 1;
3385                                 ap->ability_match_cfg = rx_cfg_reg;
3386                         }
3387                 }
3388                 if (rx_cfg_reg & ANEG_CFG_ACK)
3389                         ap->ack_match = 1;
3390                 else
3391                         ap->ack_match = 0;
3392
3393                 ap->idle_match = 0;
3394         } else {
3395                 ap->idle_match = 1;
3396                 ap->ability_match_cfg = 0;
3397                 ap->ability_match_count = 0;
3398                 ap->ability_match = 0;
3399                 ap->ack_match = 0;
3400
3401                 rx_cfg_reg = 0;
3402         }
3403
3404         ap->rxconfig = rx_cfg_reg;
3405         ret = ANEG_OK;
3406
3407         switch (ap->state) {
3408         case ANEG_STATE_UNKNOWN:
3409                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3410                         ap->state = ANEG_STATE_AN_ENABLE;
3411
3412                 /* fallthru */
3413         case ANEG_STATE_AN_ENABLE:
3414                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3415                 if (ap->flags & MR_AN_ENABLE) {
3416                         ap->link_time = 0;
3417                         ap->cur_time = 0;
3418                         ap->ability_match_cfg = 0;
3419                         ap->ability_match_count = 0;
3420                         ap->ability_match = 0;
3421                         ap->idle_match = 0;
3422                         ap->ack_match = 0;
3423
3424                         ap->state = ANEG_STATE_RESTART_INIT;
3425                 } else {
3426                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3427                 }
3428                 break;
3429
3430         case ANEG_STATE_RESTART_INIT:
3431                 ap->link_time = ap->cur_time;
3432                 ap->flags &= ~(MR_NP_LOADED);
3433                 ap->txconfig = 0;
3434                 tw32(MAC_TX_AUTO_NEG, 0);
3435                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3436                 tw32_f(MAC_MODE, tp->mac_mode);
3437                 udelay(40);
3438
3439                 ret = ANEG_TIMER_ENAB;
3440                 ap->state = ANEG_STATE_RESTART;
3441
3442                 /* fallthru */
3443         case ANEG_STATE_RESTART:
3444                 delta = ap->cur_time - ap->link_time;
3445                 if (delta > ANEG_STATE_SETTLE_TIME)
3446                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3447                 else
3448                         ret = ANEG_TIMER_ENAB;
3449                 break;
3450
3451         case ANEG_STATE_DISABLE_LINK_OK:
3452                 ret = ANEG_DONE;
3453                 break;
3454
3455         case ANEG_STATE_ABILITY_DETECT_INIT:
3456                 ap->flags &= ~(MR_TOGGLE_TX);
3457                 ap->txconfig = ANEG_CFG_FD;
3458                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3459                 if (flowctrl & ADVERTISE_1000XPAUSE)
3460                         ap->txconfig |= ANEG_CFG_PS1;
3461                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3462                         ap->txconfig |= ANEG_CFG_PS2;
3463                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3464                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3465                 tw32_f(MAC_MODE, tp->mac_mode);
3466                 udelay(40);
3467
3468                 ap->state = ANEG_STATE_ABILITY_DETECT;
3469                 break;
3470
3471         case ANEG_STATE_ABILITY_DETECT:
3472                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3473                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3474                 break;
3475
3476         case ANEG_STATE_ACK_DETECT_INIT:
3477                 ap->txconfig |= ANEG_CFG_ACK;
3478                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3479                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3480                 tw32_f(MAC_MODE, tp->mac_mode);
3481                 udelay(40);
3482
3483                 ap->state = ANEG_STATE_ACK_DETECT;
3484
3485                 /* fallthru */
3486         case ANEG_STATE_ACK_DETECT:
3487                 if (ap->ack_match != 0) {
3488                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3489                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3490                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3491                         } else {
3492                                 ap->state = ANEG_STATE_AN_ENABLE;
3493                         }
3494                 } else if (ap->ability_match != 0 &&
3495                            ap->rxconfig == 0) {
3496                         ap->state = ANEG_STATE_AN_ENABLE;
3497                 }
3498                 break;
3499
3500         case ANEG_STATE_COMPLETE_ACK_INIT:
3501                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3502                         ret = ANEG_FAILED;
3503                         break;
3504                 }
3505                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3506                                MR_LP_ADV_HALF_DUPLEX |
3507                                MR_LP_ADV_SYM_PAUSE |
3508                                MR_LP_ADV_ASYM_PAUSE |
3509                                MR_LP_ADV_REMOTE_FAULT1 |
3510                                MR_LP_ADV_REMOTE_FAULT2 |
3511                                MR_LP_ADV_NEXT_PAGE |
3512                                MR_TOGGLE_RX |
3513                                MR_NP_RX);
3514                 if (ap->rxconfig & ANEG_CFG_FD)
3515                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3516                 if (ap->rxconfig & ANEG_CFG_HD)
3517                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3518                 if (ap->rxconfig & ANEG_CFG_PS1)
3519                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3520                 if (ap->rxconfig & ANEG_CFG_PS2)
3521                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3522                 if (ap->rxconfig & ANEG_CFG_RF1)
3523                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3524                 if (ap->rxconfig & ANEG_CFG_RF2)
3525                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3526                 if (ap->rxconfig & ANEG_CFG_NP)
3527                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3528
3529                 ap->link_time = ap->cur_time;
3530
3531                 ap->flags ^= (MR_TOGGLE_TX);
3532                 if (ap->rxconfig & 0x0008)
3533                         ap->flags |= MR_TOGGLE_RX;
3534                 if (ap->rxconfig & ANEG_CFG_NP)
3535                         ap->flags |= MR_NP_RX;
3536                 ap->flags |= MR_PAGE_RX;
3537
3538                 ap->state = ANEG_STATE_COMPLETE_ACK;
3539                 ret = ANEG_TIMER_ENAB;
3540                 break;
3541
3542         case ANEG_STATE_COMPLETE_ACK:
3543                 if (ap->ability_match != 0 &&
3544                     ap->rxconfig == 0) {
3545                         ap->state = ANEG_STATE_AN_ENABLE;
3546                         break;
3547                 }
3548                 delta = ap->cur_time - ap->link_time;
3549                 if (delta > ANEG_STATE_SETTLE_TIME) {
3550                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3551                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3552                         } else {
3553                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3554                                     !(ap->flags & MR_NP_RX)) {
3555                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3556                                 } else {
3557                                         ret = ANEG_FAILED;
3558                                 }
3559                         }
3560                 }
3561                 break;
3562
3563         case ANEG_STATE_IDLE_DETECT_INIT:
3564                 ap->link_time = ap->cur_time;
3565                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3566                 tw32_f(MAC_MODE, tp->mac_mode);
3567                 udelay(40);
3568
3569                 ap->state = ANEG_STATE_IDLE_DETECT;
3570                 ret = ANEG_TIMER_ENAB;
3571                 break;
3572
3573         case ANEG_STATE_IDLE_DETECT:
3574                 if (ap->ability_match != 0 &&
3575                     ap->rxconfig == 0) {
3576                         ap->state = ANEG_STATE_AN_ENABLE;
3577                         break;
3578                 }
3579                 delta = ap->cur_time - ap->link_time;
3580                 if (delta > ANEG_STATE_SETTLE_TIME) {
3581                         /* XXX another gem from the Broadcom driver :( */
3582                         ap->state = ANEG_STATE_LINK_OK;
3583                 }
3584                 break;
3585
3586         case ANEG_STATE_LINK_OK:
3587                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3588                 ret = ANEG_DONE;
3589                 break;
3590
3591         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3592                 /* ??? unimplemented */
3593                 break;
3594
3595         case ANEG_STATE_NEXT_PAGE_WAIT:
3596                 /* ??? unimplemented */
3597                 break;
3598
3599         default:
3600                 ret = ANEG_FAILED;
3601                 break;
3602         }
3603
3604         return ret;
3605 }
3606
3607 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3608 {
3609         int res = 0;
3610         struct tg3_fiber_aneginfo aninfo;
3611         int status = ANEG_FAILED;
3612         unsigned int tick;
3613         u32 tmp;
3614
3615         tw32_f(MAC_TX_AUTO_NEG, 0);
3616
3617         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3618         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3619         udelay(40);
3620
3621         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3622         udelay(40);
3623
3624         memset(&aninfo, 0, sizeof(aninfo));
3625         aninfo.flags |= MR_AN_ENABLE;
3626         aninfo.state = ANEG_STATE_UNKNOWN;
3627         aninfo.cur_time = 0;
3628         tick = 0;
3629         while (++tick < 195000) {
3630                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3631                 if (status == ANEG_DONE || status == ANEG_FAILED)
3632                         break;
3633
3634                 udelay(1);
3635         }
3636
3637         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3638         tw32_f(MAC_MODE, tp->mac_mode);
3639         udelay(40);
3640
3641         *txflags = aninfo.txconfig;
3642         *rxflags = aninfo.flags;
3643
3644         if (status == ANEG_DONE &&
3645             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3646                              MR_LP_ADV_FULL_DUPLEX)))
3647                 res = 1;
3648
3649         return res;
3650 }
3651
3652 static void tg3_init_bcm8002(struct tg3 *tp)
3653 {
3654         u32 mac_status = tr32(MAC_STATUS);
3655         int i;
3656
3657         /* Reset when initting first time or we have a link. */
3658         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3659             !(mac_status & MAC_STATUS_PCS_SYNCED))
3660                 return;
3661
3662         /* Set PLL lock range. */
3663         tg3_writephy(tp, 0x16, 0x8007);
3664
3665         /* SW reset */
3666         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3667
3668         /* Wait for reset to complete. */
3669         /* XXX schedule_timeout() ... */
3670         for (i = 0; i < 500; i++)
3671                 udelay(10);
3672
3673         /* Config mode; select PMA/Ch 1 regs. */
3674         tg3_writephy(tp, 0x10, 0x8411);
3675
3676         /* Enable auto-lock and comdet, select txclk for tx. */
3677         tg3_writephy(tp, 0x11, 0x0a10);
3678
3679         tg3_writephy(tp, 0x18, 0x00a0);
3680         tg3_writephy(tp, 0x16, 0x41ff);
3681
3682         /* Assert and deassert POR. */
3683         tg3_writephy(tp, 0x13, 0x0400);
3684         udelay(40);
3685         tg3_writephy(tp, 0x13, 0x0000);
3686
3687         tg3_writephy(tp, 0x11, 0x0a50);
3688         udelay(40);
3689         tg3_writephy(tp, 0x11, 0x0a10);
3690
3691         /* Wait for signal to stabilize */
3692         /* XXX schedule_timeout() ... */
3693         for (i = 0; i < 15000; i++)
3694                 udelay(10);
3695
3696         /* Deselect the channel register so we can read the PHYID
3697          * later.
3698          */
3699         tg3_writephy(tp, 0x10, 0x8011);
3700 }
3701
3702 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3703 {
3704         u16 flowctrl;
3705         u32 sg_dig_ctrl, sg_dig_status;
3706         u32 serdes_cfg, expected_sg_dig_ctrl;
3707         int workaround, port_a;
3708         int current_link_up;
3709
3710         serdes_cfg = 0;
3711         expected_sg_dig_ctrl = 0;
3712         workaround = 0;
3713         port_a = 1;
3714         current_link_up = 0;
3715
3716         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3717             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3718                 workaround = 1;
3719                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3720                         port_a = 0;
3721
3722                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3723                 /* preserve bits 20-23 for voltage regulator */
3724                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3725         }
3726
3727         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3728
3729         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3730                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3731                         if (workaround) {
3732                                 u32 val = serdes_cfg;
3733
3734                                 if (port_a)
3735                                         val |= 0xc010000;
3736                                 else
3737                                         val |= 0x4010000;
3738                                 tw32_f(MAC_SERDES_CFG, val);
3739                         }
3740
3741                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3742                 }
3743                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3744                         tg3_setup_flow_control(tp, 0, 0);
3745                         current_link_up = 1;
3746                 }
3747                 goto out;
3748         }
3749
3750         /* Want auto-negotiation.  */
3751         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3752
3753         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3754         if (flowctrl & ADVERTISE_1000XPAUSE)
3755                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3756         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3757                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3758
3759         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3760                 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3761                     tp->serdes_counter &&
3762                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3763                                     MAC_STATUS_RCVD_CFG)) ==
3764                      MAC_STATUS_PCS_SYNCED)) {
3765                         tp->serdes_counter--;
3766                         current_link_up = 1;
3767                         goto out;
3768                 }
3769 restart_autoneg:
3770                 if (workaround)
3771                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3772                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3773                 udelay(5);
3774                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3775
3776                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3777                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3778         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3779                                  MAC_STATUS_SIGNAL_DET)) {
3780                 sg_dig_status = tr32(SG_DIG_STATUS);
3781                 mac_status = tr32(MAC_STATUS);
3782
3783                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3784                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3785                         u32 local_adv = 0, remote_adv = 0;
3786
3787                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3788                                 local_adv |= ADVERTISE_1000XPAUSE;
3789                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3790                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3791
3792                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3793                                 remote_adv |= LPA_1000XPAUSE;
3794                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3795                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3796
3797                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3798                         current_link_up = 1;
3799                         tp->serdes_counter = 0;
3800                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3801                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3802                         if (tp->serdes_counter)
3803                                 tp->serdes_counter--;
3804                         else {
3805                                 if (workaround) {
3806                                         u32 val = serdes_cfg;
3807
3808                                         if (port_a)
3809                                                 val |= 0xc010000;
3810                                         else
3811                                                 val |= 0x4010000;
3812
3813                                         tw32_f(MAC_SERDES_CFG, val);
3814                                 }
3815
3816                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3817                                 udelay(40);
3818
3819                                 /* Link parallel detection - link is up */
3820                                 /* only if we have PCS_SYNC and not */
3821                                 /* receiving config code words */
3822                                 mac_status = tr32(MAC_STATUS);
3823                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3824                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3825                                         tg3_setup_flow_control(tp, 0, 0);
3826                                         current_link_up = 1;
3827                                         tp->phy_flags |=
3828                                                 TG3_PHYFLG_PARALLEL_DETECT;
3829                                         tp->serdes_counter =
3830                                                 SERDES_PARALLEL_DET_TIMEOUT;
3831                                 } else
3832                                         goto restart_autoneg;
3833                         }
3834                 }
3835         } else {
3836                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3837                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3838         }
3839
3840 out:
3841         return current_link_up;
3842 }
3843
3844 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3845 {
3846         int current_link_up = 0;
3847
3848         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3849                 goto out;
3850
3851         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3852                 u32 txflags, rxflags;
3853                 int i;
3854
3855                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3856                         u32 local_adv = 0, remote_adv = 0;
3857
3858                         if (txflags & ANEG_CFG_PS1)
3859                                 local_adv |= ADVERTISE_1000XPAUSE;
3860                         if (txflags & ANEG_CFG_PS2)
3861                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3862
3863                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3864                                 remote_adv |= LPA_1000XPAUSE;
3865                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3866                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3867
3868                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3869
3870                         current_link_up = 1;
3871                 }
3872                 for (i = 0; i < 30; i++) {
3873                         udelay(20);
3874                         tw32_f(MAC_STATUS,
3875                                (MAC_STATUS_SYNC_CHANGED |
3876                                 MAC_STATUS_CFG_CHANGED));
3877                         udelay(40);
3878                         if ((tr32(MAC_STATUS) &
3879                              (MAC_STATUS_SYNC_CHANGED |
3880                               MAC_STATUS_CFG_CHANGED)) == 0)
3881                                 break;
3882                 }
3883
3884                 mac_status = tr32(MAC_STATUS);
3885                 if (current_link_up == 0 &&
3886                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3887                     !(mac_status & MAC_STATUS_RCVD_CFG))
3888                         current_link_up = 1;
3889         } else {
3890                 tg3_setup_flow_control(tp, 0, 0);
3891
3892                 /* Forcing 1000FD link up. */
3893                 current_link_up = 1;
3894
3895                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3896                 udelay(40);
3897
3898                 tw32_f(MAC_MODE, tp->mac_mode);
3899                 udelay(40);
3900         }
3901
3902 out:
3903         return current_link_up;
3904 }
3905
3906 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3907 {
3908         u32 orig_pause_cfg;
3909         u16 orig_active_speed;
3910         u8 orig_active_duplex;
3911         u32 mac_status;
3912         int current_link_up;
3913         int i;
3914
3915         orig_pause_cfg = tp->link_config.active_flowctrl;
3916         orig_active_speed = tp->link_config.active_speed;
3917         orig_active_duplex = tp->link_config.active_duplex;
3918
3919         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3920             netif_carrier_ok(tp->dev) &&
3921             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3922                 mac_status = tr32(MAC_STATUS);
3923                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3924                                MAC_STATUS_SIGNAL_DET |
3925                                MAC_STATUS_CFG_CHANGED |
3926                                MAC_STATUS_RCVD_CFG);
3927                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3928                                    MAC_STATUS_SIGNAL_DET)) {
3929                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3930                                             MAC_STATUS_CFG_CHANGED));
3931                         return 0;
3932                 }
3933         }
3934
3935         tw32_f(MAC_TX_AUTO_NEG, 0);
3936
3937         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3938         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3939         tw32_f(MAC_MODE, tp->mac_mode);
3940         udelay(40);
3941
3942         if (tp->phy_id == TG3_PHY_ID_BCM8002)
3943                 tg3_init_bcm8002(tp);
3944
3945         /* Enable link change event even when serdes polling.  */
3946         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3947         udelay(40);
3948
3949         current_link_up = 0;
3950         mac_status = tr32(MAC_STATUS);
3951
3952         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3953                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3954         else
3955                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3956
3957         tp->napi[0].hw_status->status =
3958                 (SD_STATUS_UPDATED |
3959                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3960
3961         for (i = 0; i < 100; i++) {
3962                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3963                                     MAC_STATUS_CFG_CHANGED));
3964                 udelay(5);
3965                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3966                                          MAC_STATUS_CFG_CHANGED |
3967                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3968                         break;
3969         }
3970
3971         mac_status = tr32(MAC_STATUS);
3972         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3973                 current_link_up = 0;
3974                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3975                     tp->serdes_counter == 0) {
3976                         tw32_f(MAC_MODE, (tp->mac_mode |
3977                                           MAC_MODE_SEND_CONFIGS));
3978                         udelay(1);
3979                         tw32_f(MAC_MODE, tp->mac_mode);
3980                 }
3981         }
3982
3983         if (current_link_up == 1) {
3984                 tp->link_config.active_speed = SPEED_1000;
3985                 tp->link_config.active_duplex = DUPLEX_FULL;
3986                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3987                                     LED_CTRL_LNKLED_OVERRIDE |
3988                                     LED_CTRL_1000MBPS_ON));
3989         } else {
3990                 tp->link_config.active_speed = SPEED_INVALID;
3991                 tp->link_config.active_duplex = DUPLEX_INVALID;
3992                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3993                                     LED_CTRL_LNKLED_OVERRIDE |
3994                                     LED_CTRL_TRAFFIC_OVERRIDE));
3995         }
3996
3997         if (current_link_up != netif_carrier_ok(tp->dev)) {
3998                 if (current_link_up)
3999                         netif_carrier_on(tp->dev);
4000                 else
4001                         netif_carrier_off(tp->dev);
4002                 tg3_link_report(tp);
4003         } else {
4004                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4005                 if (orig_pause_cfg != now_pause_cfg ||
4006                     orig_active_speed != tp->link_config.active_speed ||
4007                     orig_active_duplex != tp->link_config.active_duplex)
4008                         tg3_link_report(tp);
4009         }
4010
4011         return 0;
4012 }
4013
4014 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4015 {
4016         int current_link_up, err = 0;
4017         u32 bmsr, bmcr;
4018         u16 current_speed;
4019         u8 current_duplex;
4020         u32 local_adv, remote_adv;
4021
4022         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4023         tw32_f(MAC_MODE, tp->mac_mode);
4024         udelay(40);
4025
4026         tw32(MAC_EVENT, 0);
4027
4028         tw32_f(MAC_STATUS,
4029              (MAC_STATUS_SYNC_CHANGED |
4030               MAC_STATUS_CFG_CHANGED |
4031               MAC_STATUS_MI_COMPLETION |
4032               MAC_STATUS_LNKSTATE_CHANGED));
4033         udelay(40);
4034
4035         if (force_reset)
4036                 tg3_phy_reset(tp);
4037
4038         current_link_up = 0;
4039         current_speed = SPEED_INVALID;
4040         current_duplex = DUPLEX_INVALID;
4041
4042         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4043         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4044         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4045                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4046                         bmsr |= BMSR_LSTATUS;
4047                 else
4048                         bmsr &= ~BMSR_LSTATUS;
4049         }
4050
4051         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4052
4053         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4054             (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4055                 /* do nothing, just check for link up at the end */
4056         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4057                 u32 adv, new_adv;
4058
4059                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4060                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4061                                   ADVERTISE_1000XPAUSE |
4062                                   ADVERTISE_1000XPSE_ASYM |
4063                                   ADVERTISE_SLCT);
4064
4065                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4066
4067                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4068                         new_adv |= ADVERTISE_1000XHALF;
4069                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4070                         new_adv |= ADVERTISE_1000XFULL;
4071
4072                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4073                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4074                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4075                         tg3_writephy(tp, MII_BMCR, bmcr);
4076
4077                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4078                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4079                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4080
4081                         return err;
4082                 }
4083         } else {
4084                 u32 new_bmcr;
4085
4086                 bmcr &= ~BMCR_SPEED1000;
4087                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4088
4089                 if (tp->link_config.duplex == DUPLEX_FULL)
4090                         new_bmcr |= BMCR_FULLDPLX;
4091
4092                 if (new_bmcr != bmcr) {
4093                         /* BMCR_SPEED1000 is a reserved bit that needs
4094                          * to be set on write.
4095                          */
4096                         new_bmcr |= BMCR_SPEED1000;
4097
4098                         /* Force a linkdown */
4099                         if (netif_carrier_ok(tp->dev)) {
4100                                 u32 adv;
4101
4102                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4103                                 adv &= ~(ADVERTISE_1000XFULL |
4104                                          ADVERTISE_1000XHALF |
4105                                          ADVERTISE_SLCT);
4106                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4107                                 tg3_writephy(tp, MII_BMCR, bmcr |
4108                                                            BMCR_ANRESTART |
4109                                                            BMCR_ANENABLE);
4110                                 udelay(10);
4111                                 netif_carrier_off(tp->dev);
4112                         }
4113                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4114                         bmcr = new_bmcr;
4115                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4116                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4117                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4118                             ASIC_REV_5714) {
4119                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4120                                         bmsr |= BMSR_LSTATUS;
4121                                 else
4122                                         bmsr &= ~BMSR_LSTATUS;
4123                         }
4124                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4125                 }
4126         }
4127
4128         if (bmsr & BMSR_LSTATUS) {
4129                 current_speed = SPEED_1000;
4130                 current_link_up = 1;
4131                 if (bmcr & BMCR_FULLDPLX)
4132                         current_duplex = DUPLEX_FULL;
4133                 else
4134                         current_duplex = DUPLEX_HALF;
4135
4136                 local_adv = 0;
4137                 remote_adv = 0;
4138
4139                 if (bmcr & BMCR_ANENABLE) {
4140                         u32 common;
4141
4142                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4143                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4144                         common = local_adv & remote_adv;
4145                         if (common & (ADVERTISE_1000XHALF |
4146                                       ADVERTISE_1000XFULL)) {
4147                                 if (common & ADVERTISE_1000XFULL)
4148                                         current_duplex = DUPLEX_FULL;
4149                                 else
4150                                         current_duplex = DUPLEX_HALF;
4151                         } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4152                                 /* Link is up via parallel detect */
4153                         } else {
4154                                 current_link_up = 0;
4155                         }
4156                 }
4157         }
4158
4159         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4160                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4161
4162         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4163         if (tp->link_config.active_duplex == DUPLEX_HALF)
4164                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4165
4166         tw32_f(MAC_MODE, tp->mac_mode);
4167         udelay(40);
4168
4169         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4170
4171         tp->link_config.active_speed = current_speed;
4172         tp->link_config.active_duplex = current_duplex;
4173
4174         if (current_link_up != netif_carrier_ok(tp->dev)) {
4175                 if (current_link_up)
4176                         netif_carrier_on(tp->dev);
4177                 else {
4178                         netif_carrier_off(tp->dev);
4179                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4180                 }
4181                 tg3_link_report(tp);
4182         }
4183         return err;
4184 }
4185
4186 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4187 {
4188         if (tp->serdes_counter) {
4189                 /* Give autoneg time to complete. */
4190                 tp->serdes_counter--;
4191                 return;
4192         }
4193
4194         if (!netif_carrier_ok(tp->dev) &&
4195             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4196                 u32 bmcr;
4197
4198                 tg3_readphy(tp, MII_BMCR, &bmcr);
4199                 if (bmcr & BMCR_ANENABLE) {
4200                         u32 phy1, phy2;
4201
4202                         /* Select shadow register 0x1f */
4203                         tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4204                         tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4205
4206                         /* Select expansion interrupt status register */
4207                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4208                                          MII_TG3_DSP_EXP1_INT_STAT);
4209                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4210                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4211
4212                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4213                                 /* We have signal detect and not receiving
4214                                  * config code words, link is up by parallel
4215                                  * detection.
4216                                  */
4217
4218                                 bmcr &= ~BMCR_ANENABLE;
4219                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4220                                 tg3_writephy(tp, MII_BMCR, bmcr);
4221                                 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4222                         }
4223                 }
4224         } else if (netif_carrier_ok(tp->dev) &&
4225                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4226                    (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4227                 u32 phy2;
4228
4229                 /* Select expansion interrupt status register */
4230                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4231                                  MII_TG3_DSP_EXP1_INT_STAT);
4232                 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4233                 if (phy2 & 0x20) {
4234                         u32 bmcr;
4235
4236                         /* Config code words received, turn on autoneg. */
4237                         tg3_readphy(tp, MII_BMCR, &bmcr);
4238                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4239
4240                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4241
4242                 }
4243         }
4244 }
4245
4246 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4247 {
4248         int err;
4249
4250         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4251                 err = tg3_setup_fiber_phy(tp, force_reset);
4252         else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4253                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4254         else
4255                 err = tg3_setup_copper_phy(tp, force_reset);
4256
4257         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4258                 u32 val, scale;
4259
4260                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4261                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4262                         scale = 65;
4263                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4264                         scale = 6;
4265                 else
4266                         scale = 12;
4267
4268                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4269                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4270                 tw32(GRC_MISC_CFG, val);
4271         }
4272
4273         if (tp->link_config.active_speed == SPEED_1000 &&
4274             tp->link_config.active_duplex == DUPLEX_HALF)
4275                 tw32(MAC_TX_LENGTHS,
4276                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4277                       (6 << TX_LENGTHS_IPG_SHIFT) |
4278                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4279         else
4280                 tw32(MAC_TX_LENGTHS,
4281                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4282                       (6 << TX_LENGTHS_IPG_SHIFT) |
4283                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4284
4285         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4286                 if (netif_carrier_ok(tp->dev)) {
4287                         tw32(HOSTCC_STAT_COAL_TICKS,
4288                              tp->coal.stats_block_coalesce_usecs);
4289                 } else {
4290                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4291                 }
4292         }
4293
4294         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4295                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4296                 if (!netif_carrier_ok(tp->dev))
4297                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4298                               tp->pwrmgmt_thresh;
4299                 else
4300                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4301                 tw32(PCIE_PWR_MGMT_THRESH, val);
4302         }
4303
4304         return err;
4305 }
4306
4307 static inline int tg3_irq_sync(struct tg3 *tp)
4308 {
4309         return tp->irq_sync;
4310 }
4311
4312 /* This is called whenever we suspect that the system chipset is re-
4313  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4314  * is bogus tx completions. We try to recover by setting the
4315  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4316  * in the workqueue.
4317  */
4318 static void tg3_tx_recover(struct tg3 *tp)
4319 {
4320         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4321                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4322
4323         netdev_warn(tp->dev,
4324                     "The system may be re-ordering memory-mapped I/O "
4325                     "cycles to the network device, attempting to recover. "
4326                     "Please report the problem to the driver maintainer "
4327                     "and include system chipset information.\n");
4328
4329         spin_lock(&tp->lock);
4330         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4331         spin_unlock(&tp->lock);
4332 }
4333
4334 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4335 {
4336         /* Tell compiler to fetch tx indices from memory. */
4337         barrier();
4338         return tnapi->tx_pending -
4339                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4340 }
4341
4342 /* Tigon3 never reports partial packet sends.  So we do not
4343  * need special logic to handle SKBs that have not had all
4344  * of their frags sent yet, like SunGEM does.
4345  */
4346 static void tg3_tx(struct tg3_napi *tnapi)
4347 {
4348         struct tg3 *tp = tnapi->tp;
4349         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4350         u32 sw_idx = tnapi->tx_cons;
4351         struct netdev_queue *txq;
4352         int index = tnapi - tp->napi;
4353
4354         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4355                 index--;
4356
4357         txq = netdev_get_tx_queue(tp->dev, index);
4358
4359         while (sw_idx != hw_idx) {
4360                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4361                 struct sk_buff *skb = ri->skb;
4362                 int i, tx_bug = 0;
4363
4364                 if (unlikely(skb == NULL)) {
4365                         tg3_tx_recover(tp);
4366                         return;
4367                 }
4368
4369                 pci_unmap_single(tp->pdev,
4370                                  dma_unmap_addr(ri, mapping),
4371                                  skb_headlen(skb),
4372                                  PCI_DMA_TODEVICE);
4373
4374                 ri->skb = NULL;
4375
4376                 sw_idx = NEXT_TX(sw_idx);
4377
4378                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4379                         ri = &tnapi->tx_buffers[sw_idx];
4380                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4381                                 tx_bug = 1;
4382
4383                         pci_unmap_page(tp->pdev,
4384                                        dma_unmap_addr(ri, mapping),
4385                                        skb_shinfo(skb)->frags[i].size,
4386                                        PCI_DMA_TODEVICE);
4387                         sw_idx = NEXT_TX(sw_idx);
4388                 }
4389
4390                 dev_kfree_skb(skb);
4391
4392                 if (unlikely(tx_bug)) {
4393                         tg3_tx_recover(tp);
4394                         return;
4395                 }
4396         }
4397
4398         tnapi->tx_cons = sw_idx;
4399
4400         /* Need to make the tx_cons update visible to tg3_start_xmit()
4401          * before checking for netif_queue_stopped().  Without the
4402          * memory barrier, there is a small possibility that tg3_start_xmit()
4403          * will miss it and cause the queue to be stopped forever.
4404          */
4405         smp_mb();
4406
4407         if (unlikely(netif_tx_queue_stopped(txq) &&
4408                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4409                 __netif_tx_lock(txq, smp_processor_id());
4410                 if (netif_tx_queue_stopped(txq) &&
4411                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4412                         netif_tx_wake_queue(txq);
4413                 __netif_tx_unlock(txq);
4414         }
4415 }
4416
4417 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4418 {
4419         if (!ri->skb)
4420                 return;
4421
4422         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4423                          map_sz, PCI_DMA_FROMDEVICE);
4424         dev_kfree_skb_any(ri->skb);
4425         ri->skb = NULL;
4426 }
4427
4428 /* Returns size of skb allocated or < 0 on error.
4429  *
4430  * We only need to fill in the address because the other members
4431  * of the RX descriptor are invariant, see tg3_init_rings.
4432  *
4433  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4434  * posting buffers we only dirty the first cache line of the RX
4435  * descriptor (containing the address).  Whereas for the RX status
4436  * buffers the cpu only reads the last cacheline of the RX descriptor
4437  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4438  */
4439 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4440                             u32 opaque_key, u32 dest_idx_unmasked)
4441 {
4442         struct tg3_rx_buffer_desc *desc;
4443         struct ring_info *map, *src_map;
4444         struct sk_buff *skb;
4445         dma_addr_t mapping;
4446         int skb_size, dest_idx;
4447
4448         src_map = NULL;
4449         switch (opaque_key) {
4450         case RXD_OPAQUE_RING_STD:
4451                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4452                 desc = &tpr->rx_std[dest_idx];
4453                 map = &tpr->rx_std_buffers[dest_idx];
4454                 skb_size = tp->rx_pkt_map_sz;
4455                 break;
4456
4457         case RXD_OPAQUE_RING_JUMBO:
4458                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4459                 desc = &tpr->rx_jmb[dest_idx].std;
4460                 map = &tpr->rx_jmb_buffers[dest_idx];
4461                 skb_size = TG3_RX_JMB_MAP_SZ;
4462                 break;
4463
4464         default:
4465                 return -EINVAL;
4466         }
4467
4468         /* Do not overwrite any of the map or rp information
4469          * until we are sure we can commit to a new buffer.
4470          *
4471          * Callers depend upon this behavior and assume that
4472          * we leave everything unchanged if we fail.
4473          */
4474         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4475         if (skb == NULL)
4476                 return -ENOMEM;
4477
4478         skb_reserve(skb, tp->rx_offset);
4479
4480         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4481                                  PCI_DMA_FROMDEVICE);
4482         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4483                 dev_kfree_skb(skb);
4484                 return -EIO;
4485         }
4486
4487         map->skb = skb;
4488         dma_unmap_addr_set(map, mapping, mapping);
4489
4490         desc->addr_hi = ((u64)mapping >> 32);
4491         desc->addr_lo = ((u64)mapping & 0xffffffff);
4492
4493         return skb_size;
4494 }
4495
4496 /* We only need to move over in the address because the other
4497  * members of the RX descriptor are invariant.  See notes above
4498  * tg3_alloc_rx_skb for full details.
4499  */
4500 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4501                            struct tg3_rx_prodring_set *dpr,
4502                            u32 opaque_key, int src_idx,
4503                            u32 dest_idx_unmasked)
4504 {
4505         struct tg3 *tp = tnapi->tp;
4506         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4507         struct ring_info *src_map, *dest_map;
4508         struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
4509         int dest_idx;
4510
4511         switch (opaque_key) {
4512         case RXD_OPAQUE_RING_STD:
4513                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4514                 dest_desc = &dpr->rx_std[dest_idx];
4515                 dest_map = &dpr->rx_std_buffers[dest_idx];
4516                 src_desc = &spr->rx_std[src_idx];
4517                 src_map = &spr->rx_std_buffers[src_idx];
4518                 break;
4519
4520         case RXD_OPAQUE_RING_JUMBO:
4521                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4522                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4523                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4524                 src_desc = &spr->rx_jmb[src_idx].std;
4525                 src_map = &spr->rx_jmb_buffers[src_idx];
4526                 break;
4527
4528         default:
4529                 return;
4530         }
4531
4532         dest_map->skb = src_map->skb;
4533         dma_unmap_addr_set(dest_map, mapping,
4534                            dma_unmap_addr(src_map, mapping));
4535         dest_desc->addr_hi = src_desc->addr_hi;
4536         dest_desc->addr_lo = src_desc->addr_lo;
4537
4538         /* Ensure that the update to the skb happens after the physical
4539          * addresses have been transferred to the new BD location.
4540          */
4541         smp_wmb();
4542
4543         src_map->skb = NULL;
4544 }
4545
4546 /* The RX ring scheme is composed of multiple rings which post fresh
4547  * buffers to the chip, and one special ring the chip uses to report
4548  * status back to the host.
4549  *
4550  * The special ring reports the status of received packets to the
4551  * host.  The chip does not write into the original descriptor the
4552  * RX buffer was obtained from.  The chip simply takes the original
4553  * descriptor as provided by the host, updates the status and length
4554  * field, then writes this into the next status ring entry.
4555  *
4556  * Each ring the host uses to post buffers to the chip is described
4557  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4558  * it is first placed into the on-chip ram.  When the packet's length
4559  * is known, it walks down the TG3_BDINFO entries to select the ring.
4560  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4561  * which is within the range of the new packet's length is chosen.
4562  *
4563  * The "separate ring for rx status" scheme may sound queer, but it makes
4564  * sense from a cache coherency perspective.  If only the host writes
4565  * to the buffer post rings, and only the chip writes to the rx status
4566  * rings, then cache lines never move beyond shared-modified state.
4567  * If both the host and chip were to write into the same ring, cache line
4568  * eviction could occur since both entities want it in an exclusive state.
4569  */
4570 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4571 {
4572         struct tg3 *tp = tnapi->tp;
4573         u32 work_mask, rx_std_posted = 0;
4574         u32 std_prod_idx, jmb_prod_idx;
4575         u32 sw_idx = tnapi->rx_rcb_ptr;
4576         u16 hw_idx;
4577         int received;
4578         struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
4579
4580         hw_idx = *(tnapi->rx_rcb_prod_idx);
4581         /*
4582          * We need to order the read of hw_idx and the read of
4583          * the opaque cookie.
4584          */
4585         rmb();
4586         work_mask = 0;
4587         received = 0;
4588         std_prod_idx = tpr->rx_std_prod_idx;
4589         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4590         while (sw_idx != hw_idx && budget > 0) {
4591                 struct ring_info *ri;
4592                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4593                 unsigned int len;
4594                 struct sk_buff *skb;
4595                 dma_addr_t dma_addr;
4596                 u32 opaque_key, desc_idx, *post_ptr;
4597                 bool hw_vlan __maybe_unused = false;
4598                 u16 vtag __maybe_unused = 0;
4599
4600                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4601                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4602                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4603                         ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4604                         dma_addr = dma_unmap_addr(ri, mapping);
4605                         skb = ri->skb;
4606                         post_ptr = &std_prod_idx;
4607                         rx_std_posted++;
4608                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4609                         ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4610                         dma_addr = dma_unmap_addr(ri, mapping);
4611                         skb = ri->skb;
4612                         post_ptr = &jmb_prod_idx;
4613                 } else
4614                         goto next_pkt_nopost;
4615
4616                 work_mask |= opaque_key;
4617
4618                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4619                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4620                 drop_it:
4621                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4622                                        desc_idx, *post_ptr);
4623                 drop_it_no_recycle:
4624                         /* Other statistics kept track of by card. */
4625                         tp->net_stats.rx_dropped++;
4626                         goto next_pkt;
4627                 }
4628
4629                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4630                       ETH_FCS_LEN;
4631
4632                 if (len > TG3_RX_COPY_THRESH(tp)) {
4633                         int skb_size;
4634
4635                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4636                                                     *post_ptr);
4637                         if (skb_size < 0)
4638                                 goto drop_it;
4639
4640                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4641                                          PCI_DMA_FROMDEVICE);
4642
4643                         /* Ensure that the update to the skb happens
4644                          * after the usage of the old DMA mapping.
4645                          */
4646                         smp_wmb();
4647
4648                         ri->skb = NULL;
4649
4650                         skb_put(skb, len);
4651                 } else {
4652                         struct sk_buff *copy_skb;
4653
4654                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4655                                        desc_idx, *post_ptr);
4656
4657                         copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
4658                                                     TG3_RAW_IP_ALIGN);
4659                         if (copy_skb == NULL)
4660                                 goto drop_it_no_recycle;
4661
4662                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
4663                         skb_put(copy_skb, len);
4664                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4665                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4666                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4667
4668                         /* We'll reuse the original ring buffer. */
4669                         skb = copy_skb;
4670                 }
4671
4672                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4673                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4674                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4675                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4676                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4677                 else
4678                         skb_checksum_none_assert(skb);
4679
4680                 skb->protocol = eth_type_trans(skb, tp->dev);
4681
4682                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4683                     skb->protocol != htons(ETH_P_8021Q)) {
4684                         dev_kfree_skb(skb);
4685                         goto next_pkt;
4686                 }
4687
4688                 if (desc->type_flags & RXD_FLAG_VLAN &&
4689                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
4690                         vtag = desc->err_vlan & RXD_VLAN_MASK;
4691 #if TG3_VLAN_TAG_USED
4692                         if (tp->vlgrp)
4693                                 hw_vlan = true;
4694                         else
4695 #endif
4696                         {
4697                                 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
4698                                                     __skb_push(skb, VLAN_HLEN);
4699
4700                                 memmove(ve, skb->data + VLAN_HLEN,
4701                                         ETH_ALEN * 2);
4702                                 ve->h_vlan_proto = htons(ETH_P_8021Q);
4703                                 ve->h_vlan_TCI = htons(vtag);
4704                         }
4705                 }
4706
4707 #if TG3_VLAN_TAG_USED
4708                 if (hw_vlan)
4709                         vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
4710                 else
4711 #endif
4712                         napi_gro_receive(&tnapi->napi, skb);
4713
4714                 received++;
4715                 budget--;
4716
4717 next_pkt:
4718                 (*post_ptr)++;
4719
4720                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4721                         tpr->rx_std_prod_idx = std_prod_idx &
4722                                                tp->rx_std_ring_mask;
4723                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4724                                      tpr->rx_std_prod_idx);
4725                         work_mask &= ~RXD_OPAQUE_RING_STD;
4726                         rx_std_posted = 0;
4727                 }
4728 next_pkt_nopost:
4729                 sw_idx++;
4730                 sw_idx &= tp->rx_ret_ring_mask;
4731
4732                 /* Refresh hw_idx to see if there is new work */
4733                 if (sw_idx == hw_idx) {
4734                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4735                         rmb();
4736                 }
4737         }
4738
4739         /* ACK the status ring. */
4740         tnapi->rx_rcb_ptr = sw_idx;
4741         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4742
4743         /* Refill RX ring(s). */
4744         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4745                 if (work_mask & RXD_OPAQUE_RING_STD) {
4746                         tpr->rx_std_prod_idx = std_prod_idx &
4747                                                tp->rx_std_ring_mask;
4748                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4749                                      tpr->rx_std_prod_idx);
4750                 }
4751                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4752                         tpr->rx_jmb_prod_idx = jmb_prod_idx &
4753                                                tp->rx_jmb_ring_mask;
4754                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4755                                      tpr->rx_jmb_prod_idx);
4756                 }
4757                 mmiowb();
4758         } else if (work_mask) {
4759                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4760                  * updated before the producer indices can be updated.
4761                  */
4762                 smp_wmb();
4763
4764                 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
4765                 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
4766
4767                 if (tnapi != &tp->napi[1])
4768                         napi_schedule(&tp->napi[1].napi);
4769         }
4770
4771         return received;
4772 }
4773
4774 static void tg3_poll_link(struct tg3 *tp)
4775 {
4776         /* handle link change and other phy events */
4777         if (!(tp->tg3_flags &
4778               (TG3_FLAG_USE_LINKCHG_REG |
4779                TG3_FLAG_POLL_SERDES))) {
4780                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4781
4782                 if (sblk->status & SD_STATUS_LINK_CHG) {
4783                         sblk->status = SD_STATUS_UPDATED |
4784                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4785                         spin_lock(&tp->lock);
4786                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4787                                 tw32_f(MAC_STATUS,
4788                                      (MAC_STATUS_SYNC_CHANGED |
4789                                       MAC_STATUS_CFG_CHANGED |
4790                                       MAC_STATUS_MI_COMPLETION |
4791                                       MAC_STATUS_LNKSTATE_CHANGED));
4792                                 udelay(40);
4793                         } else
4794                                 tg3_setup_phy(tp, 0);
4795                         spin_unlock(&tp->lock);
4796                 }
4797         }
4798 }
4799
4800 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4801                                 struct tg3_rx_prodring_set *dpr,
4802                                 struct tg3_rx_prodring_set *spr)
4803 {
4804         u32 si, di, cpycnt, src_prod_idx;
4805         int i, err = 0;
4806
4807         while (1) {
4808                 src_prod_idx = spr->rx_std_prod_idx;
4809
4810                 /* Make sure updates to the rx_std_buffers[] entries and the
4811                  * standard producer index are seen in the correct order.
4812                  */
4813                 smp_rmb();
4814
4815                 if (spr->rx_std_cons_idx == src_prod_idx)
4816                         break;
4817
4818                 if (spr->rx_std_cons_idx < src_prod_idx)
4819                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4820                 else
4821                         cpycnt = tp->rx_std_ring_mask + 1 -
4822                                  spr->rx_std_cons_idx;
4823
4824                 cpycnt = min(cpycnt,
4825                              tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
4826
4827                 si = spr->rx_std_cons_idx;
4828                 di = dpr->rx_std_prod_idx;
4829
4830                 for (i = di; i < di + cpycnt; i++) {
4831                         if (dpr->rx_std_buffers[i].skb) {
4832                                 cpycnt = i - di;
4833                                 err = -ENOSPC;
4834                                 break;
4835                         }
4836                 }
4837
4838                 if (!cpycnt)
4839                         break;
4840
4841                 /* Ensure that updates to the rx_std_buffers ring and the
4842                  * shadowed hardware producer ring from tg3_recycle_skb() are
4843                  * ordered correctly WRT the skb check above.
4844                  */
4845                 smp_rmb();
4846
4847                 memcpy(&dpr->rx_std_buffers[di],
4848                        &spr->rx_std_buffers[si],
4849                        cpycnt * sizeof(struct ring_info));
4850
4851                 for (i = 0; i < cpycnt; i++, di++, si++) {
4852                         struct tg3_rx_buffer_desc *sbd, *dbd;
4853                         sbd = &spr->rx_std[si];
4854                         dbd = &dpr->rx_std[di];
4855                         dbd->addr_hi = sbd->addr_hi;
4856                         dbd->addr_lo = sbd->addr_lo;
4857                 }
4858
4859                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
4860                                        tp->rx_std_ring_mask;
4861                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
4862                                        tp->rx_std_ring_mask;
4863         }
4864
4865         while (1) {
4866                 src_prod_idx = spr->rx_jmb_prod_idx;
4867
4868                 /* Make sure updates to the rx_jmb_buffers[] entries and
4869                  * the jumbo producer index are seen in the correct order.
4870                  */
4871                 smp_rmb();
4872
4873                 if (spr->rx_jmb_cons_idx == src_prod_idx)
4874                         break;
4875
4876                 if (spr->rx_jmb_cons_idx < src_prod_idx)
4877                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4878                 else
4879                         cpycnt = tp->rx_jmb_ring_mask + 1 -
4880                                  spr->rx_jmb_cons_idx;
4881
4882                 cpycnt = min(cpycnt,
4883                              tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
4884
4885                 si = spr->rx_jmb_cons_idx;
4886                 di = dpr->rx_jmb_prod_idx;
4887
4888                 for (i = di; i < di + cpycnt; i++) {
4889                         if (dpr->rx_jmb_buffers[i].skb) {
4890                                 cpycnt = i - di;
4891                                 err = -ENOSPC;
4892                                 break;
4893                         }
4894                 }
4895
4896                 if (!cpycnt)
4897                         break;
4898
4899                 /* Ensure that updates to the rx_jmb_buffers ring and the
4900                  * shadowed hardware producer ring from tg3_recycle_skb() are
4901                  * ordered correctly WRT the skb check above.
4902                  */
4903                 smp_rmb();
4904
4905                 memcpy(&dpr->rx_jmb_buffers[di],
4906                        &spr->rx_jmb_buffers[si],
4907                        cpycnt * sizeof(struct ring_info));
4908
4909                 for (i = 0; i < cpycnt; i++, di++, si++) {
4910                         struct tg3_rx_buffer_desc *sbd, *dbd;
4911                         sbd = &spr->rx_jmb[si].std;
4912                         dbd = &dpr->rx_jmb[di].std;
4913                         dbd->addr_hi = sbd->addr_hi;
4914                         dbd->addr_lo = sbd->addr_lo;
4915                 }
4916
4917                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
4918                                        tp->rx_jmb_ring_mask;
4919                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
4920                                        tp->rx_jmb_ring_mask;
4921         }
4922
4923         return err;
4924 }
4925
4926 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4927 {
4928         struct tg3 *tp = tnapi->tp;
4929
4930         /* run TX completion thread */
4931         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4932                 tg3_tx(tnapi);
4933                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4934                         return work_done;
4935         }
4936
4937         /* run RX thread, within the bounds set by NAPI.
4938          * All RX "locking" is done by ensuring outside
4939          * code synchronizes with tg3->napi.poll()
4940          */
4941         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4942                 work_done += tg3_rx(tnapi, budget - work_done);
4943
4944         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4945                 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
4946                 int i, err = 0;
4947                 u32 std_prod_idx = dpr->rx_std_prod_idx;
4948                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
4949
4950                 for (i = 1; i < tp->irq_cnt; i++)
4951                         err |= tg3_rx_prodring_xfer(tp, dpr,
4952                                                     &tp->napi[i].prodring);
4953
4954                 wmb();
4955
4956                 if (std_prod_idx != dpr->rx_std_prod_idx)
4957                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4958                                      dpr->rx_std_prod_idx);
4959
4960                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
4961                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4962                                      dpr->rx_jmb_prod_idx);
4963
4964                 mmiowb();
4965
4966                 if (err)
4967                         tw32_f(HOSTCC_MODE, tp->coal_now);
4968         }
4969
4970         return work_done;
4971 }
4972
4973 static int tg3_poll_msix(struct napi_struct *napi, int budget)
4974 {
4975         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4976         struct tg3 *tp = tnapi->tp;
4977         int work_done = 0;
4978         struct tg3_hw_status *sblk = tnapi->hw_status;
4979
4980         while (1) {
4981                 work_done = tg3_poll_work(tnapi, work_done, budget);
4982
4983                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4984                         goto tx_recovery;
4985
4986                 if (unlikely(work_done >= budget))
4987                         break;
4988
4989                 /* tp->last_tag is used in tg3_int_reenable() below
4990                  * to tell the hw how much work has been processed,
4991                  * so we must read it before checking for more work.
4992                  */
4993                 tnapi->last_tag = sblk->status_tag;
4994                 tnapi->last_irq_tag = tnapi->last_tag;
4995                 rmb();
4996
4997                 /* check for RX/TX work to do */
4998                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4999                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5000                         napi_complete(napi);
5001                         /* Reenable interrupts. */
5002                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5003                         mmiowb();
5004                         break;
5005                 }
5006         }
5007
5008         return work_done;
5009
5010 tx_recovery:
5011         /* work_done is guaranteed to be less than budget. */
5012         napi_complete(napi);
5013         schedule_work(&tp->reset_task);
5014         return work_done;
5015 }
5016
5017 static int tg3_poll(struct napi_struct *napi, int budget)
5018 {
5019         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5020         struct tg3 *tp = tnapi->tp;
5021         int work_done = 0;
5022         struct tg3_hw_status *sblk = tnapi->hw_status;
5023
5024         while (1) {
5025                 tg3_poll_link(tp);
5026
5027                 work_done = tg3_poll_work(tnapi, work_done, budget);
5028
5029                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5030                         goto tx_recovery;
5031
5032                 if (unlikely(work_done >= budget))
5033                         break;
5034
5035                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5036                         /* tp->last_tag is used in tg3_int_reenable() below
5037                          * to tell the hw how much work has been processed,
5038                          * so we must read it before checking for more work.
5039                          */
5040                         tnapi->last_tag = sblk->status_tag;
5041                         tnapi->last_irq_tag = tnapi->last_tag;
5042                         rmb();
5043                 } else
5044                         sblk->status &= ~SD_STATUS_UPDATED;
5045
5046                 if (likely(!tg3_has_work(tnapi))) {
5047                         napi_complete(napi);
5048                         tg3_int_reenable(tnapi);
5049                         break;
5050                 }
5051         }
5052
5053         return work_done;
5054
5055 tx_recovery:
5056         /* work_done is guaranteed to be less than budget. */
5057         napi_complete(napi);
5058         schedule_work(&tp->reset_task);
5059         return work_done;
5060 }
5061
5062 static void tg3_napi_disable(struct tg3 *tp)
5063 {
5064         int i;
5065
5066         for (i = tp->irq_cnt - 1; i >= 0; i--)
5067                 napi_disable(&tp->napi[i].napi);
5068 }
5069
5070 static void tg3_napi_enable(struct tg3 *tp)
5071 {
5072         int i;
5073
5074         for (i = 0; i < tp->irq_cnt; i++)
5075                 napi_enable(&tp->napi[i].napi);
5076 }
5077
5078 static void tg3_napi_init(struct tg3 *tp)
5079 {
5080         int i;
5081
5082         netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
5083         for (i = 1; i < tp->irq_cnt; i++)
5084                 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
5085 }
5086
5087 static void tg3_napi_fini(struct tg3 *tp)
5088 {
5089         int i;
5090
5091         for (i = 0; i < tp->irq_cnt; i++)
5092                 netif_napi_del(&tp->napi[i].napi);
5093 }
5094
5095 static inline void tg3_netif_stop(struct tg3 *tp)
5096 {
5097         tp->dev->trans_start = jiffies; /* prevent tx timeout */
5098         tg3_napi_disable(tp);
5099         netif_tx_disable(tp->dev);
5100 }
5101
5102 static inline void tg3_netif_start(struct tg3 *tp)
5103 {
5104         /* NOTE: unconditional netif_tx_wake_all_queues is only
5105          * appropriate so long as all callers are assured to
5106          * have free tx slots (such as after tg3_init_hw)
5107          */
5108         netif_tx_wake_all_queues(tp->dev);
5109
5110         tg3_napi_enable(tp);
5111         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
5112         tg3_enable_ints(tp);
5113 }
5114
5115 static void tg3_irq_quiesce(struct tg3 *tp)
5116 {
5117         int i;
5118
5119         BUG_ON(tp->irq_sync);
5120
5121         tp->irq_sync = 1;
5122         smp_mb();
5123
5124         for (i = 0; i < tp->irq_cnt; i++)
5125                 synchronize_irq(tp->napi[i].irq_vec);
5126 }
5127
5128 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5129  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5130  * with as well.  Most of the time, this is not necessary except when
5131  * shutting down the device.
5132  */
5133 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5134 {
5135         spin_lock_bh(&tp->lock);
5136         if (irq_sync)
5137                 tg3_irq_quiesce(tp);
5138 }
5139
5140 static inline void tg3_full_unlock(struct tg3 *tp)
5141 {
5142         spin_unlock_bh(&tp->lock);
5143 }
5144
5145 /* One-shot MSI handler - Chip automatically disables interrupt
5146  * after sending MSI so driver doesn't have to do it.
5147  */
5148 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5149 {
5150         struct tg3_napi *tnapi = dev_id;
5151         struct tg3 *tp = tnapi->tp;
5152
5153         prefetch(tnapi->hw_status);
5154         if (tnapi->rx_rcb)
5155                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5156
5157         if (likely(!tg3_irq_sync(tp)))
5158                 napi_schedule(&tnapi->napi);
5159
5160         return IRQ_HANDLED;
5161 }
5162
5163 /* MSI ISR - No need to check for interrupt sharing and no need to
5164  * flush status block and interrupt mailbox. PCI ordering rules
5165  * guarantee that MSI will arrive after the status block.
5166  */
5167 static irqreturn_t tg3_msi(int irq, void *dev_id)
5168 {
5169         struct tg3_napi *tnapi = dev_id;
5170         struct tg3 *tp = tnapi->tp;
5171
5172         prefetch(tnapi->hw_status);
5173         if (tnapi->rx_rcb)
5174                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5175         /*
5176          * Writing any value to intr-mbox-0 clears PCI INTA# and
5177          * chip-internal interrupt pending events.
5178          * Writing non-zero to intr-mbox-0 additional tells the
5179          * NIC to stop sending us irqs, engaging "in-intr-handler"
5180          * event coalescing.
5181          */
5182         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5183         if (likely(!tg3_irq_sync(tp)))
5184                 napi_schedule(&tnapi->napi);
5185
5186         return IRQ_RETVAL(1);
5187 }
5188
5189 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5190 {
5191         struct tg3_napi *tnapi = dev_id;
5192         struct tg3 *tp = tnapi->tp;
5193         struct tg3_hw_status *sblk = tnapi->hw_status;
5194         unsigned int handled = 1;
5195
5196         /* In INTx mode, it is possible for the interrupt to arrive at
5197          * the CPU before the status block posted prior to the interrupt.
5198          * Reading the PCI State register will confirm whether the
5199          * interrupt is ours and will flush the status block.
5200          */
5201         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5202                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5203                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5204                         handled = 0;
5205                         goto out;
5206                 }
5207         }
5208
5209         /*
5210          * Writing any value to intr-mbox-0 clears PCI INTA# and
5211          * chip-internal interrupt pending events.
5212          * Writing non-zero to intr-mbox-0 additional tells the
5213          * NIC to stop sending us irqs, engaging "in-intr-handler"
5214          * event coalescing.
5215          *
5216          * Flush the mailbox to de-assert the IRQ immediately to prevent
5217          * spurious interrupts.  The flush impacts performance but
5218          * excessive spurious interrupts can be worse in some cases.
5219          */
5220         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5221         if (tg3_irq_sync(tp))
5222                 goto out;
5223         sblk->status &= ~SD_STATUS_UPDATED;
5224         if (likely(tg3_has_work(tnapi))) {
5225                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5226                 napi_schedule(&tnapi->napi);
5227         } else {
5228                 /* No work, shared interrupt perhaps?  re-enable
5229                  * interrupts, and flush that PCI write
5230                  */
5231                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5232                                0x00000000);
5233         }
5234 out:
5235         return IRQ_RETVAL(handled);
5236 }
5237
5238 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5239 {
5240         struct tg3_napi *tnapi = dev_id;
5241         struct tg3 *tp = tnapi->tp;
5242         struct tg3_hw_status *sblk = tnapi->hw_status;
5243         unsigned int handled = 1;
5244
5245         /* In INTx mode, it is possible for the interrupt to arrive at
5246          * the CPU before the status block posted prior to the interrupt.
5247          * Reading the PCI State register will confirm whether the
5248          * interrupt is ours and will flush the status block.
5249          */
5250         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5251                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5252                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5253                         handled = 0;
5254                         goto out;
5255                 }
5256         }
5257
5258         /*
5259          * writing any value to intr-mbox-0 clears PCI INTA# and
5260          * chip-internal interrupt pending events.
5261          * writing non-zero to intr-mbox-0 additional tells the
5262          * NIC to stop sending us irqs, engaging "in-intr-handler"
5263          * event coalescing.
5264          *
5265          * Flush the mailbox to de-assert the IRQ immediately to prevent
5266          * spurious interrupts.  The flush impacts performance but
5267          * excessive spurious interrupts can be worse in some cases.
5268          */
5269         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5270
5271         /*
5272          * In a shared interrupt configuration, sometimes other devices'
5273          * interrupts will scream.  We record the current status tag here
5274          * so that the above check can report that the screaming interrupts
5275          * are unhandled.  Eventually they will be silenced.
5276          */
5277         tnapi->last_irq_tag = sblk->status_tag;
5278
5279         if (tg3_irq_sync(tp))
5280                 goto out;
5281
5282         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5283
5284         napi_schedule(&tnapi->napi);
5285
5286 out:
5287         return IRQ_RETVAL(handled);
5288 }
5289
5290 /* ISR for interrupt test */
5291 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5292 {
5293         struct tg3_napi *tnapi = dev_id;
5294         struct tg3 *tp = tnapi->tp;
5295         struct tg3_hw_status *sblk = tnapi->hw_status;
5296
5297         if ((sblk->status & SD_STATUS_UPDATED) ||
5298             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5299                 tg3_disable_ints(tp);
5300                 return IRQ_RETVAL(1);
5301         }
5302         return IRQ_RETVAL(0);
5303 }
5304
5305 static int tg3_init_hw(struct tg3 *, int);
5306 static int tg3_halt(struct tg3 *, int, int);
5307
5308 /* Restart hardware after configuration changes, self-test, etc.
5309  * Invoked with tp->lock held.
5310  */
5311 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5312         __releases(tp->lock)
5313         __acquires(tp->lock)
5314 {
5315         int err;
5316
5317         err = tg3_init_hw(tp, reset_phy);
5318         if (err) {
5319                 netdev_err(tp->dev,
5320                            "Failed to re-initialize device, aborting\n");
5321                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5322                 tg3_full_unlock(tp);
5323                 del_timer_sync(&tp->timer);
5324                 tp->irq_sync = 0;
5325                 tg3_napi_enable(tp);
5326                 dev_close(tp->dev);
5327                 tg3_full_lock(tp, 0);
5328         }
5329         return err;
5330 }
5331
5332 #ifdef CONFIG_NET_POLL_CONTROLLER
5333 static void tg3_poll_controller(struct net_device *dev)
5334 {
5335         int i;
5336         struct tg3 *tp = netdev_priv(dev);
5337
5338         for (i = 0; i < tp->irq_cnt; i++)
5339                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5340 }
5341 #endif
5342
5343 static void tg3_reset_task(struct work_struct *work)
5344 {
5345         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5346         int err;
5347         unsigned int restart_timer;
5348
5349         tg3_full_lock(tp, 0);
5350
5351         if (!netif_running(tp->dev)) {
5352                 tg3_full_unlock(tp);
5353                 return;
5354         }
5355
5356         tg3_full_unlock(tp);
5357
5358         tg3_phy_stop(tp);
5359
5360         tg3_netif_stop(tp);
5361
5362         tg3_full_lock(tp, 1);
5363
5364         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5365         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5366
5367         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5368                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5369                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5370                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5371                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5372         }
5373
5374         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5375         err = tg3_init_hw(tp, 1);
5376         if (err)
5377                 goto out;
5378
5379         tg3_netif_start(tp);
5380
5381         if (restart_timer)
5382                 mod_timer(&tp->timer, jiffies + 1);
5383
5384 out:
5385         tg3_full_unlock(tp);
5386
5387         if (!err)
5388                 tg3_phy_start(tp);
5389 }
5390
5391 static void tg3_dump_short_state(struct tg3 *tp)
5392 {
5393         netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5394                    tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5395         netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5396                    tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5397 }
5398
5399 static void tg3_tx_timeout(struct net_device *dev)
5400 {
5401         struct tg3 *tp = netdev_priv(dev);
5402
5403         if (netif_msg_tx_err(tp)) {
5404                 netdev_err(dev, "transmit timed out, resetting\n");
5405                 tg3_dump_short_state(tp);
5406         }
5407
5408         schedule_work(&tp->reset_task);
5409 }
5410
5411 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5412 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5413 {
5414         u32 base = (u32) mapping & 0xffffffff;
5415
5416         return (base > 0xffffdcc0) && (base + len + 8 < base);
5417 }
5418
5419 /* Test for DMA addresses > 40-bit */
5420 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5421                                           int len)
5422 {
5423 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5424         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5425                 return ((u64) mapping + len) > DMA_BIT_MASK(40);
5426         return 0;
5427 #else
5428         return 0;
5429 #endif
5430 }
5431
5432 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5433
5434 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5435 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5436                                        struct sk_buff *skb, u32 last_plus_one,
5437                                        u32 *start, u32 base_flags, u32 mss)
5438 {
5439         struct tg3 *tp = tnapi->tp;
5440         struct sk_buff *new_skb;
5441         dma_addr_t new_addr = 0;
5442         u32 entry = *start;
5443         int i, ret = 0;
5444
5445         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5446                 new_skb = skb_copy(skb, GFP_ATOMIC);
5447         else {
5448                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5449
5450                 new_skb = skb_copy_expand(skb,
5451                                           skb_headroom(skb) + more_headroom,
5452                                           skb_tailroom(skb), GFP_ATOMIC);
5453         }
5454
5455         if (!new_skb) {
5456                 ret = -1;
5457         } else {
5458                 /* New SKB is guaranteed to be linear. */
5459                 entry = *start;
5460                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5461                                           PCI_DMA_TODEVICE);
5462                 /* Make sure the mapping succeeded */
5463                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5464                         ret = -1;
5465                         dev_kfree_skb(new_skb);
5466                         new_skb = NULL;
5467
5468                 /* Make sure new skb does not cross any 4G boundaries.
5469                  * Drop the packet if it does.
5470                  */
5471                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5472                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5473                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5474                                          PCI_DMA_TODEVICE);
5475                         ret = -1;
5476                         dev_kfree_skb(new_skb);
5477                         new_skb = NULL;
5478                 } else {
5479                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5480                                     base_flags, 1 | (mss << 1));
5481                         *start = NEXT_TX(entry);
5482                 }
5483         }
5484
5485         /* Now clean up the sw ring entries. */
5486         i = 0;
5487         while (entry != last_plus_one) {
5488                 int len;
5489
5490                 if (i == 0)
5491                         len = skb_headlen(skb);
5492                 else
5493                         len = skb_shinfo(skb)->frags[i-1].size;
5494
5495                 pci_unmap_single(tp->pdev,
5496                                  dma_unmap_addr(&tnapi->tx_buffers[entry],
5497                                                 mapping),
5498                                  len, PCI_DMA_TODEVICE);
5499                 if (i == 0) {
5500                         tnapi->tx_buffers[entry].skb = new_skb;
5501                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5502                                            new_addr);
5503                 } else {
5504                         tnapi->tx_buffers[entry].skb = NULL;
5505                 }
5506                 entry = NEXT_TX(entry);
5507                 i++;
5508         }
5509
5510         dev_kfree_skb(skb);
5511
5512         return ret;
5513 }
5514
5515 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5516                         dma_addr_t mapping, int len, u32 flags,
5517                         u32 mss_and_is_end)
5518 {
5519         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5520         int is_end = (mss_and_is_end & 0x1);
5521         u32 mss = (mss_and_is_end >> 1);
5522         u32 vlan_tag = 0;
5523
5524         if (is_end)
5525                 flags |= TXD_FLAG_END;
5526         if (flags & TXD_FLAG_VLAN) {
5527                 vlan_tag = flags >> 16;
5528                 flags &= 0xffff;
5529         }
5530         vlan_tag |= (mss << TXD_MSS_SHIFT);
5531
5532         txd->addr_hi = ((u64) mapping >> 32);
5533         txd->addr_lo = ((u64) mapping & 0xffffffff);
5534         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5535         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5536 }
5537
5538 /* hard_start_xmit for devices that don't have any bugs and
5539  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5540  */
5541 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5542                                   struct net_device *dev)
5543 {
5544         struct tg3 *tp = netdev_priv(dev);
5545         u32 len, entry, base_flags, mss;
5546         dma_addr_t mapping;
5547         struct tg3_napi *tnapi;
5548         struct netdev_queue *txq;
5549         unsigned int i, last;
5550
5551         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5552         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5553         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5554                 tnapi++;
5555
5556         /* We are running in BH disabled context with netif_tx_lock
5557          * and TX reclaim runs via tp->napi.poll inside of a software
5558          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5559          * no IRQ context deadlocks to worry about either.  Rejoice!
5560          */
5561         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5562                 if (!netif_tx_queue_stopped(txq)) {
5563                         netif_tx_stop_queue(txq);
5564
5565                         /* This is a hard error, log it. */
5566                         netdev_err(dev,
5567                                    "BUG! Tx Ring full when queue awake!\n");
5568                 }
5569                 return NETDEV_TX_BUSY;
5570         }
5571
5572         entry = tnapi->tx_prod;
5573         base_flags = 0;
5574         mss = skb_shinfo(skb)->gso_size;
5575         if (mss) {
5576                 int tcp_opt_len, ip_tcp_len;
5577                 u32 hdrlen;
5578
5579                 if (skb_header_cloned(skb) &&
5580                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5581                         dev_kfree_skb(skb);
5582                         goto out_unlock;
5583                 }
5584
5585                 if (skb_is_gso_v6(skb)) {
5586                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5587                 } else {
5588                         struct iphdr *iph = ip_hdr(skb);
5589
5590                         tcp_opt_len = tcp_optlen(skb);
5591                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5592
5593                         iph->check = 0;
5594                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5595                         hdrlen = ip_tcp_len + tcp_opt_len;
5596                 }
5597
5598                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5599                         mss |= (hdrlen & 0xc) << 12;
5600                         if (hdrlen & 0x10)
5601                                 base_flags |= 0x00000010;
5602                         base_flags |= (hdrlen & 0x3e0) << 5;
5603                 } else
5604                         mss |= hdrlen << 9;
5605
5606                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5607                                TXD_FLAG_CPU_POST_DMA);
5608
5609                 tcp_hdr(skb)->check = 0;
5610
5611         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5612                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5613         }
5614
5615 #if TG3_VLAN_TAG_USED
5616         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5617                 base_flags |= (TXD_FLAG_VLAN |
5618                                (vlan_tx_tag_get(skb) << 16));
5619 #endif
5620
5621         len = skb_headlen(skb);
5622
5623         /* Queue skb data, a.k.a. the main skb fragment. */
5624         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5625         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5626                 dev_kfree_skb(skb);
5627                 goto out_unlock;
5628         }
5629
5630         tnapi->tx_buffers[entry].skb = skb;
5631         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5632
5633         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5634             !mss && skb->len > ETH_DATA_LEN)
5635                 base_flags |= TXD_FLAG_JMB_PKT;
5636
5637         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5638                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5639
5640         entry = NEXT_TX(entry);
5641
5642         /* Now loop through additional data fragments, and queue them. */
5643         if (skb_shinfo(skb)->nr_frags > 0) {
5644                 last = skb_shinfo(skb)->nr_frags - 1;
5645                 for (i = 0; i <= last; i++) {
5646                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5647
5648                         len = frag->size;
5649                         mapping = pci_map_page(tp->pdev,
5650                                                frag->page,
5651                                                frag->page_offset,
5652                                                len, PCI_DMA_TODEVICE);
5653                         if (pci_dma_mapping_error(tp->pdev, mapping))
5654                                 goto dma_error;
5655
5656                         tnapi->tx_buffers[entry].skb = NULL;
5657                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5658                                            mapping);
5659
5660                         tg3_set_txd(tnapi, entry, mapping, len,
5661                                     base_flags, (i == last) | (mss << 1));
5662
5663                         entry = NEXT_TX(entry);
5664                 }
5665         }
5666
5667         /* Packets are ready, update Tx producer idx local and on card. */
5668         tw32_tx_mbox(tnapi->prodmbox, entry);
5669
5670         tnapi->tx_prod = entry;
5671         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5672                 netif_tx_stop_queue(txq);
5673
5674                 /* netif_tx_stop_queue() must be done before checking
5675                  * checking tx index in tg3_tx_avail() below, because in
5676                  * tg3_tx(), we update tx index before checking for
5677                  * netif_tx_queue_stopped().
5678                  */
5679                 smp_mb();
5680                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5681                         netif_tx_wake_queue(txq);
5682         }
5683
5684 out_unlock:
5685         mmiowb();
5686
5687         return NETDEV_TX_OK;
5688
5689 dma_error:
5690         last = i;
5691         entry = tnapi->tx_prod;
5692         tnapi->tx_buffers[entry].skb = NULL;
5693         pci_unmap_single(tp->pdev,
5694                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5695                          skb_headlen(skb),
5696                          PCI_DMA_TODEVICE);
5697         for (i = 0; i <= last; i++) {
5698                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5699                 entry = NEXT_TX(entry);
5700
5701                 pci_unmap_page(tp->pdev,
5702                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5703                                               mapping),
5704                                frag->size, PCI_DMA_TODEVICE);
5705         }
5706
5707         dev_kfree_skb(skb);
5708         return NETDEV_TX_OK;
5709 }
5710
5711 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5712                                           struct net_device *);
5713
5714 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5715  * TSO header is greater than 80 bytes.
5716  */
5717 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5718 {
5719         struct sk_buff *segs, *nskb;
5720         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5721
5722         /* Estimate the number of fragments in the worst case */
5723         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5724                 netif_stop_queue(tp->dev);
5725
5726                 /* netif_tx_stop_queue() must be done before checking
5727                  * checking tx index in tg3_tx_avail() below, because in
5728                  * tg3_tx(), we update tx index before checking for
5729                  * netif_tx_queue_stopped().
5730                  */
5731                 smp_mb();
5732                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5733                         return NETDEV_TX_BUSY;
5734
5735                 netif_wake_queue(tp->dev);
5736         }
5737
5738         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5739         if (IS_ERR(segs))
5740                 goto tg3_tso_bug_end;
5741
5742         do {
5743                 nskb = segs;
5744                 segs = segs->next;
5745                 nskb->next = NULL;
5746                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5747         } while (segs);
5748