tg3: Relax 5717 serdes restriction
[linux-2.6.git] / drivers / net / tg3.c
1 /*
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  * Copyright (C) 2005-2010 Broadcom Corporation.
8  *
9  * Firmware is:
10  *      Derived from proprietary unpublished source code,
11  *      Copyright (C) 2000-2003 Broadcom Corporation.
12  *
13  *      Permission is hereby granted for the distribution of this firmware
14  *      data in hexadecimal or equivalent format, provided this copyright
15  *      notice is accompanying it.
16  */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
26 #include <linux/in.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/phy.h>
36 #include <linux/brcmphy.h>
37 #include <linux/if_vlan.h>
38 #include <linux/ip.h>
39 #include <linux/tcp.h>
40 #include <linux/workqueue.h>
41 #include <linux/prefetch.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/firmware.h>
44
45 #include <net/checksum.h>
46 #include <net/ip.h>
47
48 #include <asm/system.h>
49 #include <asm/io.h>
50 #include <asm/byteorder.h>
51 #include <asm/uaccess.h>
52
53 #ifdef CONFIG_SPARC
54 #include <asm/idprom.h>
55 #include <asm/prom.h>
56 #endif
57
58 #define BAR_0   0
59 #define BAR_2   2
60
61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62 #define TG3_VLAN_TAG_USED 1
63 #else
64 #define TG3_VLAN_TAG_USED 0
65 #endif
66
67 #include "tg3.h"
68
69 #define DRV_MODULE_NAME         "tg3"
70 #define DRV_MODULE_VERSION      "3.111"
71 #define DRV_MODULE_RELDATE      "June 5, 2010"
72
73 #define TG3_DEF_MAC_MODE        0
74 #define TG3_DEF_RX_MODE         0
75 #define TG3_DEF_TX_MODE         0
76 #define TG3_DEF_MSG_ENABLE        \
77         (NETIF_MSG_DRV          | \
78          NETIF_MSG_PROBE        | \
79          NETIF_MSG_LINK         | \
80          NETIF_MSG_TIMER        | \
81          NETIF_MSG_IFDOWN       | \
82          NETIF_MSG_IFUP         | \
83          NETIF_MSG_RX_ERR       | \
84          NETIF_MSG_TX_ERR)
85
86 /* length of time before we decide the hardware is borked,
87  * and dev->tx_timeout() should be called to fix the problem
88  */
89 #define TG3_TX_TIMEOUT                  (5 * HZ)
90
91 /* hardware minimum and maximum for a single frame's data payload */
92 #define TG3_MIN_MTU                     60
93 #define TG3_MAX_MTU(tp) \
94         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
95
96 /* These numbers seem to be hard coded in the NIC firmware somehow.
97  * You can't change the ring sizes, but you can change where you place
98  * them in the NIC onboard memory.
99  */
100 #define TG3_RX_RING_SIZE                512
101 #define TG3_DEF_RX_RING_PENDING         200
102 #define TG3_RX_JUMBO_RING_SIZE          256
103 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
104 #define TG3_RSS_INDIR_TBL_SIZE          128
105
106 /* Do not place this n-ring entries value into the tp struct itself,
107  * we really want to expose these constants to GCC so that modulo et
108  * al.  operations are done with shifts and masks instead of with
109  * hw multiply/modulo instructions.  Another solution would be to
110  * replace things like '% foo' with '& (foo - 1)'.
111  */
112 #define TG3_RX_RCB_RING_SIZE(tp)        \
113         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
114           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
115
116 #define TG3_TX_RING_SIZE                512
117 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
118
119 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
120                                  TG3_RX_RING_SIZE)
121 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
122                                  TG3_RX_JUMBO_RING_SIZE)
123 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
124                                  TG3_RX_RCB_RING_SIZE(tp))
125 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
126                                  TG3_TX_RING_SIZE)
127 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
128
129 #define TG3_RX_DMA_ALIGN                16
130 #define TG3_RX_HEADROOM                 ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
131
132 #define TG3_DMA_BYTE_ENAB               64
133
134 #define TG3_RX_STD_DMA_SZ               1536
135 #define TG3_RX_JMB_DMA_SZ               9046
136
137 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
138
139 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
140 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
141
142 #define TG3_RX_STD_BUFF_RING_SIZE \
143         (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
144
145 #define TG3_RX_JMB_BUFF_RING_SIZE \
146         (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
147
148 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
149  * that are at least dword aligned when used in PCIX mode.  The driver
150  * works around this bug by double copying the packet.  This workaround
151  * is built into the normal double copy length check for efficiency.
152  *
153  * However, the double copy is only necessary on those architectures
154  * where unaligned memory accesses are inefficient.  For those architectures
155  * where unaligned memory accesses incur little penalty, we can reintegrate
156  * the 5701 in the normal rx path.  Doing so saves a device structure
157  * dereference by hardcoding the double copy threshold in place.
158  */
159 #define TG3_RX_COPY_THRESHOLD           256
160 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
161         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
162 #else
163         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
164 #endif
165
166 /* minimum number of free TX descriptors required to wake up TX process */
167 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
168
169 #define TG3_RAW_IP_ALIGN 2
170
171 /* number of ETHTOOL_GSTATS u64's */
172 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
173
174 #define TG3_NUM_TEST            6
175
176 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
177
178 #define FIRMWARE_TG3            "tigon/tg3.bin"
179 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
180 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
181
182 static char version[] __devinitdata =
183         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
184
185 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
186 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
187 MODULE_LICENSE("GPL");
188 MODULE_VERSION(DRV_MODULE_VERSION);
189 MODULE_FIRMWARE(FIRMWARE_TG3);
190 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
191 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
192
193 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
194 module_param(tg3_debug, int, 0);
195 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
196
197 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
268         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
269         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
270         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
271         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
272         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
273         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
274         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
275         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
276         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
277         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
278         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
279         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
280         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
281         {}
282 };
283
284 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
285
286 static const struct {
287         const char string[ETH_GSTRING_LEN];
288 } ethtool_stats_keys[TG3_NUM_STATS] = {
289         { "rx_octets" },
290         { "rx_fragments" },
291         { "rx_ucast_packets" },
292         { "rx_mcast_packets" },
293         { "rx_bcast_packets" },
294         { "rx_fcs_errors" },
295         { "rx_align_errors" },
296         { "rx_xon_pause_rcvd" },
297         { "rx_xoff_pause_rcvd" },
298         { "rx_mac_ctrl_rcvd" },
299         { "rx_xoff_entered" },
300         { "rx_frame_too_long_errors" },
301         { "rx_jabbers" },
302         { "rx_undersize_packets" },
303         { "rx_in_length_errors" },
304         { "rx_out_length_errors" },
305         { "rx_64_or_less_octet_packets" },
306         { "rx_65_to_127_octet_packets" },
307         { "rx_128_to_255_octet_packets" },
308         { "rx_256_to_511_octet_packets" },
309         { "rx_512_to_1023_octet_packets" },
310         { "rx_1024_to_1522_octet_packets" },
311         { "rx_1523_to_2047_octet_packets" },
312         { "rx_2048_to_4095_octet_packets" },
313         { "rx_4096_to_8191_octet_packets" },
314         { "rx_8192_to_9022_octet_packets" },
315
316         { "tx_octets" },
317         { "tx_collisions" },
318
319         { "tx_xon_sent" },
320         { "tx_xoff_sent" },
321         { "tx_flow_control" },
322         { "tx_mac_errors" },
323         { "tx_single_collisions" },
324         { "tx_mult_collisions" },
325         { "tx_deferred" },
326         { "tx_excessive_collisions" },
327         { "tx_late_collisions" },
328         { "tx_collide_2times" },
329         { "tx_collide_3times" },
330         { "tx_collide_4times" },
331         { "tx_collide_5times" },
332         { "tx_collide_6times" },
333         { "tx_collide_7times" },
334         { "tx_collide_8times" },
335         { "tx_collide_9times" },
336         { "tx_collide_10times" },
337         { "tx_collide_11times" },
338         { "tx_collide_12times" },
339         { "tx_collide_13times" },
340         { "tx_collide_14times" },
341         { "tx_collide_15times" },
342         { "tx_ucast_packets" },
343         { "tx_mcast_packets" },
344         { "tx_bcast_packets" },
345         { "tx_carrier_sense_errors" },
346         { "tx_discards" },
347         { "tx_errors" },
348
349         { "dma_writeq_full" },
350         { "dma_write_prioq_full" },
351         { "rxbds_empty" },
352         { "rx_discards" },
353         { "rx_errors" },
354         { "rx_threshold_hit" },
355
356         { "dma_readq_full" },
357         { "dma_read_prioq_full" },
358         { "tx_comp_queue_full" },
359
360         { "ring_set_send_prod_index" },
361         { "ring_status_update" },
362         { "nic_irqs" },
363         { "nic_avoided_irqs" },
364         { "nic_tx_threshold_hit" }
365 };
366
367 static const struct {
368         const char string[ETH_GSTRING_LEN];
369 } ethtool_test_keys[TG3_NUM_TEST] = {
370         { "nvram test     (online) " },
371         { "link test      (online) " },
372         { "register test  (offline)" },
373         { "memory test    (offline)" },
374         { "loopback test  (offline)" },
375         { "interrupt test (offline)" },
376 };
377
378 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
379 {
380         writel(val, tp->regs + off);
381 }
382
383 static u32 tg3_read32(struct tg3 *tp, u32 off)
384 {
385         return readl(tp->regs + off);
386 }
387
388 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
389 {
390         writel(val, tp->aperegs + off);
391 }
392
393 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
394 {
395         return readl(tp->aperegs + off);
396 }
397
398 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
399 {
400         unsigned long flags;
401
402         spin_lock_irqsave(&tp->indirect_lock, flags);
403         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
404         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
405         spin_unlock_irqrestore(&tp->indirect_lock, flags);
406 }
407
408 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
409 {
410         writel(val, tp->regs + off);
411         readl(tp->regs + off);
412 }
413
414 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
415 {
416         unsigned long flags;
417         u32 val;
418
419         spin_lock_irqsave(&tp->indirect_lock, flags);
420         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
421         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
422         spin_unlock_irqrestore(&tp->indirect_lock, flags);
423         return val;
424 }
425
426 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
427 {
428         unsigned long flags;
429
430         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
431                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
432                                        TG3_64BIT_REG_LOW, val);
433                 return;
434         }
435         if (off == TG3_RX_STD_PROD_IDX_REG) {
436                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
437                                        TG3_64BIT_REG_LOW, val);
438                 return;
439         }
440
441         spin_lock_irqsave(&tp->indirect_lock, flags);
442         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
443         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
444         spin_unlock_irqrestore(&tp->indirect_lock, flags);
445
446         /* In indirect mode when disabling interrupts, we also need
447          * to clear the interrupt bit in the GRC local ctrl register.
448          */
449         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
450             (val == 0x1)) {
451                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
452                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
453         }
454 }
455
456 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
457 {
458         unsigned long flags;
459         u32 val;
460
461         spin_lock_irqsave(&tp->indirect_lock, flags);
462         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
463         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
464         spin_unlock_irqrestore(&tp->indirect_lock, flags);
465         return val;
466 }
467
468 /* usec_wait specifies the wait time in usec when writing to certain registers
469  * where it is unsafe to read back the register without some delay.
470  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
471  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
472  */
473 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
474 {
475         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
476             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
477                 /* Non-posted methods */
478                 tp->write32(tp, off, val);
479         else {
480                 /* Posted method */
481                 tg3_write32(tp, off, val);
482                 if (usec_wait)
483                         udelay(usec_wait);
484                 tp->read32(tp, off);
485         }
486         /* Wait again after the read for the posted method to guarantee that
487          * the wait time is met.
488          */
489         if (usec_wait)
490                 udelay(usec_wait);
491 }
492
493 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
494 {
495         tp->write32_mbox(tp, off, val);
496         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
497             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
498                 tp->read32_mbox(tp, off);
499 }
500
501 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
502 {
503         void __iomem *mbox = tp->regs + off;
504         writel(val, mbox);
505         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
506                 writel(val, mbox);
507         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
508                 readl(mbox);
509 }
510
511 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
512 {
513         return readl(tp->regs + off + GRCMBOX_BASE);
514 }
515
516 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
517 {
518         writel(val, tp->regs + off + GRCMBOX_BASE);
519 }
520
521 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
522 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
523 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
524 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
525 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
526
527 #define tw32(reg, val)                  tp->write32(tp, reg, val)
528 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
529 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
530 #define tr32(reg)                       tp->read32(tp, reg)
531
532 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
533 {
534         unsigned long flags;
535
536         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
537             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
538                 return;
539
540         spin_lock_irqsave(&tp->indirect_lock, flags);
541         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
542                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
543                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
544
545                 /* Always leave this as zero. */
546                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
547         } else {
548                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
549                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
550
551                 /* Always leave this as zero. */
552                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
553         }
554         spin_unlock_irqrestore(&tp->indirect_lock, flags);
555 }
556
557 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
558 {
559         unsigned long flags;
560
561         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
562             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
563                 *val = 0;
564                 return;
565         }
566
567         spin_lock_irqsave(&tp->indirect_lock, flags);
568         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
569                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
570                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
571
572                 /* Always leave this as zero. */
573                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
574         } else {
575                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
576                 *val = tr32(TG3PCI_MEM_WIN_DATA);
577
578                 /* Always leave this as zero. */
579                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
580         }
581         spin_unlock_irqrestore(&tp->indirect_lock, flags);
582 }
583
584 static void tg3_ape_lock_init(struct tg3 *tp)
585 {
586         int i;
587         u32 regbase;
588
589         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
590                 regbase = TG3_APE_LOCK_GRANT;
591         else
592                 regbase = TG3_APE_PER_LOCK_GRANT;
593
594         /* Make sure the driver hasn't any stale locks. */
595         for (i = 0; i < 8; i++)
596                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
597 }
598
599 static int tg3_ape_lock(struct tg3 *tp, int locknum)
600 {
601         int i, off;
602         int ret = 0;
603         u32 status, req, gnt;
604
605         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
606                 return 0;
607
608         switch (locknum) {
609         case TG3_APE_LOCK_GRC:
610         case TG3_APE_LOCK_MEM:
611                 break;
612         default:
613                 return -EINVAL;
614         }
615
616         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
617                 req = TG3_APE_LOCK_REQ;
618                 gnt = TG3_APE_LOCK_GRANT;
619         } else {
620                 req = TG3_APE_PER_LOCK_REQ;
621                 gnt = TG3_APE_PER_LOCK_GRANT;
622         }
623
624         off = 4 * locknum;
625
626         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
627
628         /* Wait for up to 1 millisecond to acquire lock. */
629         for (i = 0; i < 100; i++) {
630                 status = tg3_ape_read32(tp, gnt + off);
631                 if (status == APE_LOCK_GRANT_DRIVER)
632                         break;
633                 udelay(10);
634         }
635
636         if (status != APE_LOCK_GRANT_DRIVER) {
637                 /* Revoke the lock request. */
638                 tg3_ape_write32(tp, gnt + off,
639                                 APE_LOCK_GRANT_DRIVER);
640
641                 ret = -EBUSY;
642         }
643
644         return ret;
645 }
646
647 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
648 {
649         u32 gnt;
650
651         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
652                 return;
653
654         switch (locknum) {
655         case TG3_APE_LOCK_GRC:
656         case TG3_APE_LOCK_MEM:
657                 break;
658         default:
659                 return;
660         }
661
662         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
663                 gnt = TG3_APE_LOCK_GRANT;
664         else
665                 gnt = TG3_APE_PER_LOCK_GRANT;
666
667         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
668 }
669
670 static void tg3_disable_ints(struct tg3 *tp)
671 {
672         int i;
673
674         tw32(TG3PCI_MISC_HOST_CTRL,
675              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
676         for (i = 0; i < tp->irq_max; i++)
677                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
678 }
679
680 static void tg3_enable_ints(struct tg3 *tp)
681 {
682         int i;
683
684         tp->irq_sync = 0;
685         wmb();
686
687         tw32(TG3PCI_MISC_HOST_CTRL,
688              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
689
690         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
691         for (i = 0; i < tp->irq_cnt; i++) {
692                 struct tg3_napi *tnapi = &tp->napi[i];
693
694                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
695                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
696                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
697
698                 tp->coal_now |= tnapi->coal_now;
699         }
700
701         /* Force an initial interrupt */
702         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
703             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
704                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
705         else
706                 tw32(HOSTCC_MODE, tp->coal_now);
707
708         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
709 }
710
711 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
712 {
713         struct tg3 *tp = tnapi->tp;
714         struct tg3_hw_status *sblk = tnapi->hw_status;
715         unsigned int work_exists = 0;
716
717         /* check for phy events */
718         if (!(tp->tg3_flags &
719               (TG3_FLAG_USE_LINKCHG_REG |
720                TG3_FLAG_POLL_SERDES))) {
721                 if (sblk->status & SD_STATUS_LINK_CHG)
722                         work_exists = 1;
723         }
724         /* check for RX/TX work to do */
725         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
726             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
727                 work_exists = 1;
728
729         return work_exists;
730 }
731
732 /* tg3_int_reenable
733  *  similar to tg3_enable_ints, but it accurately determines whether there
734  *  is new work pending and can return without flushing the PIO write
735  *  which reenables interrupts
736  */
737 static void tg3_int_reenable(struct tg3_napi *tnapi)
738 {
739         struct tg3 *tp = tnapi->tp;
740
741         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
742         mmiowb();
743
744         /* When doing tagged status, this work check is unnecessary.
745          * The last_tag we write above tells the chip which piece of
746          * work we've completed.
747          */
748         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
749             tg3_has_work(tnapi))
750                 tw32(HOSTCC_MODE, tp->coalesce_mode |
751                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
752 }
753
754 static void tg3_napi_disable(struct tg3 *tp)
755 {
756         int i;
757
758         for (i = tp->irq_cnt - 1; i >= 0; i--)
759                 napi_disable(&tp->napi[i].napi);
760 }
761
762 static void tg3_napi_enable(struct tg3 *tp)
763 {
764         int i;
765
766         for (i = 0; i < tp->irq_cnt; i++)
767                 napi_enable(&tp->napi[i].napi);
768 }
769
770 static inline void tg3_netif_stop(struct tg3 *tp)
771 {
772         tp->dev->trans_start = jiffies; /* prevent tx timeout */
773         tg3_napi_disable(tp);
774         netif_tx_disable(tp->dev);
775 }
776
777 static inline void tg3_netif_start(struct tg3 *tp)
778 {
779         /* NOTE: unconditional netif_tx_wake_all_queues is only
780          * appropriate so long as all callers are assured to
781          * have free tx slots (such as after tg3_init_hw)
782          */
783         netif_tx_wake_all_queues(tp->dev);
784
785         tg3_napi_enable(tp);
786         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
787         tg3_enable_ints(tp);
788 }
789
790 static void tg3_switch_clocks(struct tg3 *tp)
791 {
792         u32 clock_ctrl;
793         u32 orig_clock_ctrl;
794
795         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
796             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
797                 return;
798
799         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
800
801         orig_clock_ctrl = clock_ctrl;
802         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
803                        CLOCK_CTRL_CLKRUN_OENABLE |
804                        0x1f);
805         tp->pci_clock_ctrl = clock_ctrl;
806
807         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
808                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
809                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
810                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
811                 }
812         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
813                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
814                             clock_ctrl |
815                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
816                             40);
817                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
818                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
819                             40);
820         }
821         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
822 }
823
824 #define PHY_BUSY_LOOPS  5000
825
826 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
827 {
828         u32 frame_val;
829         unsigned int loops;
830         int ret;
831
832         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
833                 tw32_f(MAC_MI_MODE,
834                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
835                 udelay(80);
836         }
837
838         *val = 0x0;
839
840         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
841                       MI_COM_PHY_ADDR_MASK);
842         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
843                       MI_COM_REG_ADDR_MASK);
844         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
845
846         tw32_f(MAC_MI_COM, frame_val);
847
848         loops = PHY_BUSY_LOOPS;
849         while (loops != 0) {
850                 udelay(10);
851                 frame_val = tr32(MAC_MI_COM);
852
853                 if ((frame_val & MI_COM_BUSY) == 0) {
854                         udelay(5);
855                         frame_val = tr32(MAC_MI_COM);
856                         break;
857                 }
858                 loops -= 1;
859         }
860
861         ret = -EBUSY;
862         if (loops != 0) {
863                 *val = frame_val & MI_COM_DATA_MASK;
864                 ret = 0;
865         }
866
867         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
868                 tw32_f(MAC_MI_MODE, tp->mi_mode);
869                 udelay(80);
870         }
871
872         return ret;
873 }
874
875 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
876 {
877         u32 frame_val;
878         unsigned int loops;
879         int ret;
880
881         if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
882             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
883                 return 0;
884
885         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
886                 tw32_f(MAC_MI_MODE,
887                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
888                 udelay(80);
889         }
890
891         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
892                       MI_COM_PHY_ADDR_MASK);
893         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
894                       MI_COM_REG_ADDR_MASK);
895         frame_val |= (val & MI_COM_DATA_MASK);
896         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
897
898         tw32_f(MAC_MI_COM, frame_val);
899
900         loops = PHY_BUSY_LOOPS;
901         while (loops != 0) {
902                 udelay(10);
903                 frame_val = tr32(MAC_MI_COM);
904                 if ((frame_val & MI_COM_BUSY) == 0) {
905                         udelay(5);
906                         frame_val = tr32(MAC_MI_COM);
907                         break;
908                 }
909                 loops -= 1;
910         }
911
912         ret = -EBUSY;
913         if (loops != 0)
914                 ret = 0;
915
916         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
917                 tw32_f(MAC_MI_MODE, tp->mi_mode);
918                 udelay(80);
919         }
920
921         return ret;
922 }
923
924 static int tg3_bmcr_reset(struct tg3 *tp)
925 {
926         u32 phy_control;
927         int limit, err;
928
929         /* OK, reset it, and poll the BMCR_RESET bit until it
930          * clears or we time out.
931          */
932         phy_control = BMCR_RESET;
933         err = tg3_writephy(tp, MII_BMCR, phy_control);
934         if (err != 0)
935                 return -EBUSY;
936
937         limit = 5000;
938         while (limit--) {
939                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
940                 if (err != 0)
941                         return -EBUSY;
942
943                 if ((phy_control & BMCR_RESET) == 0) {
944                         udelay(40);
945                         break;
946                 }
947                 udelay(10);
948         }
949         if (limit < 0)
950                 return -EBUSY;
951
952         return 0;
953 }
954
955 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
956 {
957         struct tg3 *tp = bp->priv;
958         u32 val;
959
960         spin_lock_bh(&tp->lock);
961
962         if (tg3_readphy(tp, reg, &val))
963                 val = -EIO;
964
965         spin_unlock_bh(&tp->lock);
966
967         return val;
968 }
969
970 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
971 {
972         struct tg3 *tp = bp->priv;
973         u32 ret = 0;
974
975         spin_lock_bh(&tp->lock);
976
977         if (tg3_writephy(tp, reg, val))
978                 ret = -EIO;
979
980         spin_unlock_bh(&tp->lock);
981
982         return ret;
983 }
984
985 static int tg3_mdio_reset(struct mii_bus *bp)
986 {
987         return 0;
988 }
989
990 static void tg3_mdio_config_5785(struct tg3 *tp)
991 {
992         u32 val;
993         struct phy_device *phydev;
994
995         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
996         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
997         case PHY_ID_BCM50610:
998         case PHY_ID_BCM50610M:
999                 val = MAC_PHYCFG2_50610_LED_MODES;
1000                 break;
1001         case PHY_ID_BCMAC131:
1002                 val = MAC_PHYCFG2_AC131_LED_MODES;
1003                 break;
1004         case PHY_ID_RTL8211C:
1005                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1006                 break;
1007         case PHY_ID_RTL8201E:
1008                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1009                 break;
1010         default:
1011                 return;
1012         }
1013
1014         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1015                 tw32(MAC_PHYCFG2, val);
1016
1017                 val = tr32(MAC_PHYCFG1);
1018                 val &= ~(MAC_PHYCFG1_RGMII_INT |
1019                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1020                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1021                 tw32(MAC_PHYCFG1, val);
1022
1023                 return;
1024         }
1025
1026         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
1027                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1028                        MAC_PHYCFG2_FMODE_MASK_MASK |
1029                        MAC_PHYCFG2_GMODE_MASK_MASK |
1030                        MAC_PHYCFG2_ACT_MASK_MASK   |
1031                        MAC_PHYCFG2_QUAL_MASK_MASK |
1032                        MAC_PHYCFG2_INBAND_ENABLE;
1033
1034         tw32(MAC_PHYCFG2, val);
1035
1036         val = tr32(MAC_PHYCFG1);
1037         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1038                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1039         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1040                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1041                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1042                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1043                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1044         }
1045         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1046                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1047         tw32(MAC_PHYCFG1, val);
1048
1049         val = tr32(MAC_EXT_RGMII_MODE);
1050         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1051                  MAC_RGMII_MODE_RX_QUALITY |
1052                  MAC_RGMII_MODE_RX_ACTIVITY |
1053                  MAC_RGMII_MODE_RX_ENG_DET |
1054                  MAC_RGMII_MODE_TX_ENABLE |
1055                  MAC_RGMII_MODE_TX_LOWPWR |
1056                  MAC_RGMII_MODE_TX_RESET);
1057         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1058                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1059                         val |= MAC_RGMII_MODE_RX_INT_B |
1060                                MAC_RGMII_MODE_RX_QUALITY |
1061                                MAC_RGMII_MODE_RX_ACTIVITY |
1062                                MAC_RGMII_MODE_RX_ENG_DET;
1063                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1064                         val |= MAC_RGMII_MODE_TX_ENABLE |
1065                                MAC_RGMII_MODE_TX_LOWPWR |
1066                                MAC_RGMII_MODE_TX_RESET;
1067         }
1068         tw32(MAC_EXT_RGMII_MODE, val);
1069 }
1070
1071 static void tg3_mdio_start(struct tg3 *tp)
1072 {
1073         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1074         tw32_f(MAC_MI_MODE, tp->mi_mode);
1075         udelay(80);
1076
1077         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1078             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1079                 tg3_mdio_config_5785(tp);
1080 }
1081
1082 static int tg3_mdio_init(struct tg3 *tp)
1083 {
1084         int i;
1085         u32 reg;
1086         struct phy_device *phydev;
1087
1088         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1089             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
1090                 u32 is_serdes;
1091
1092                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1093
1094                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1095                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1096                 else
1097                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1098                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1099                 if (is_serdes)
1100                         tp->phy_addr += 7;
1101         } else
1102                 tp->phy_addr = TG3_PHY_MII_ADDR;
1103
1104         tg3_mdio_start(tp);
1105
1106         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1107             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1108                 return 0;
1109
1110         tp->mdio_bus = mdiobus_alloc();
1111         if (tp->mdio_bus == NULL)
1112                 return -ENOMEM;
1113
1114         tp->mdio_bus->name     = "tg3 mdio bus";
1115         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1116                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1117         tp->mdio_bus->priv     = tp;
1118         tp->mdio_bus->parent   = &tp->pdev->dev;
1119         tp->mdio_bus->read     = &tg3_mdio_read;
1120         tp->mdio_bus->write    = &tg3_mdio_write;
1121         tp->mdio_bus->reset    = &tg3_mdio_reset;
1122         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1123         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1124
1125         for (i = 0; i < PHY_MAX_ADDR; i++)
1126                 tp->mdio_bus->irq[i] = PHY_POLL;
1127
1128         /* The bus registration will look for all the PHYs on the mdio bus.
1129          * Unfortunately, it does not ensure the PHY is powered up before
1130          * accessing the PHY ID registers.  A chip reset is the
1131          * quickest way to bring the device back to an operational state..
1132          */
1133         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1134                 tg3_bmcr_reset(tp);
1135
1136         i = mdiobus_register(tp->mdio_bus);
1137         if (i) {
1138                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1139                 mdiobus_free(tp->mdio_bus);
1140                 return i;
1141         }
1142
1143         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1144
1145         if (!phydev || !phydev->drv) {
1146                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1147                 mdiobus_unregister(tp->mdio_bus);
1148                 mdiobus_free(tp->mdio_bus);
1149                 return -ENODEV;
1150         }
1151
1152         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1153         case PHY_ID_BCM57780:
1154                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1155                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1156                 break;
1157         case PHY_ID_BCM50610:
1158         case PHY_ID_BCM50610M:
1159                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1160                                      PHY_BRCM_RX_REFCLK_UNUSED |
1161                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1162                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1163                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1164                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1165                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1166                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1167                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1168                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1169                 /* fallthru */
1170         case PHY_ID_RTL8211C:
1171                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1172                 break;
1173         case PHY_ID_RTL8201E:
1174         case PHY_ID_BCMAC131:
1175                 phydev->interface = PHY_INTERFACE_MODE_MII;
1176                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1177                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1178                 break;
1179         }
1180
1181         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1182
1183         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1184                 tg3_mdio_config_5785(tp);
1185
1186         return 0;
1187 }
1188
1189 static void tg3_mdio_fini(struct tg3 *tp)
1190 {
1191         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1192                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1193                 mdiobus_unregister(tp->mdio_bus);
1194                 mdiobus_free(tp->mdio_bus);
1195         }
1196 }
1197
1198 /* tp->lock is held. */
1199 static inline void tg3_generate_fw_event(struct tg3 *tp)
1200 {
1201         u32 val;
1202
1203         val = tr32(GRC_RX_CPU_EVENT);
1204         val |= GRC_RX_CPU_DRIVER_EVENT;
1205         tw32_f(GRC_RX_CPU_EVENT, val);
1206
1207         tp->last_event_jiffies = jiffies;
1208 }
1209
1210 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1211
1212 /* tp->lock is held. */
1213 static void tg3_wait_for_event_ack(struct tg3 *tp)
1214 {
1215         int i;
1216         unsigned int delay_cnt;
1217         long time_remain;
1218
1219         /* If enough time has passed, no wait is necessary. */
1220         time_remain = (long)(tp->last_event_jiffies + 1 +
1221                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1222                       (long)jiffies;
1223         if (time_remain < 0)
1224                 return;
1225
1226         /* Check if we can shorten the wait time. */
1227         delay_cnt = jiffies_to_usecs(time_remain);
1228         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1229                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1230         delay_cnt = (delay_cnt >> 3) + 1;
1231
1232         for (i = 0; i < delay_cnt; i++) {
1233                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1234                         break;
1235                 udelay(8);
1236         }
1237 }
1238
1239 /* tp->lock is held. */
1240 static void tg3_ump_link_report(struct tg3 *tp)
1241 {
1242         u32 reg;
1243         u32 val;
1244
1245         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1246             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1247                 return;
1248
1249         tg3_wait_for_event_ack(tp);
1250
1251         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1252
1253         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1254
1255         val = 0;
1256         if (!tg3_readphy(tp, MII_BMCR, &reg))
1257                 val = reg << 16;
1258         if (!tg3_readphy(tp, MII_BMSR, &reg))
1259                 val |= (reg & 0xffff);
1260         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1261
1262         val = 0;
1263         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1264                 val = reg << 16;
1265         if (!tg3_readphy(tp, MII_LPA, &reg))
1266                 val |= (reg & 0xffff);
1267         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1268
1269         val = 0;
1270         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1271                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1272                         val = reg << 16;
1273                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1274                         val |= (reg & 0xffff);
1275         }
1276         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1277
1278         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1279                 val = reg << 16;
1280         else
1281                 val = 0;
1282         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1283
1284         tg3_generate_fw_event(tp);
1285 }
1286
1287 static void tg3_link_report(struct tg3 *tp)
1288 {
1289         if (!netif_carrier_ok(tp->dev)) {
1290                 netif_info(tp, link, tp->dev, "Link is down\n");
1291                 tg3_ump_link_report(tp);
1292         } else if (netif_msg_link(tp)) {
1293                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1294                             (tp->link_config.active_speed == SPEED_1000 ?
1295                              1000 :
1296                              (tp->link_config.active_speed == SPEED_100 ?
1297                               100 : 10)),
1298                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1299                              "full" : "half"));
1300
1301                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1302                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1303                             "on" : "off",
1304                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1305                             "on" : "off");
1306                 tg3_ump_link_report(tp);
1307         }
1308 }
1309
1310 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1311 {
1312         u16 miireg;
1313
1314         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1315                 miireg = ADVERTISE_PAUSE_CAP;
1316         else if (flow_ctrl & FLOW_CTRL_TX)
1317                 miireg = ADVERTISE_PAUSE_ASYM;
1318         else if (flow_ctrl & FLOW_CTRL_RX)
1319                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1320         else
1321                 miireg = 0;
1322
1323         return miireg;
1324 }
1325
1326 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1327 {
1328         u16 miireg;
1329
1330         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1331                 miireg = ADVERTISE_1000XPAUSE;
1332         else if (flow_ctrl & FLOW_CTRL_TX)
1333                 miireg = ADVERTISE_1000XPSE_ASYM;
1334         else if (flow_ctrl & FLOW_CTRL_RX)
1335                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1336         else
1337                 miireg = 0;
1338
1339         return miireg;
1340 }
1341
1342 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1343 {
1344         u8 cap = 0;
1345
1346         if (lcladv & ADVERTISE_1000XPAUSE) {
1347                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1348                         if (rmtadv & LPA_1000XPAUSE)
1349                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1350                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1351                                 cap = FLOW_CTRL_RX;
1352                 } else {
1353                         if (rmtadv & LPA_1000XPAUSE)
1354                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1355                 }
1356         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1357                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1358                         cap = FLOW_CTRL_TX;
1359         }
1360
1361         return cap;
1362 }
1363
1364 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1365 {
1366         u8 autoneg;
1367         u8 flowctrl = 0;
1368         u32 old_rx_mode = tp->rx_mode;
1369         u32 old_tx_mode = tp->tx_mode;
1370
1371         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1372                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1373         else
1374                 autoneg = tp->link_config.autoneg;
1375
1376         if (autoneg == AUTONEG_ENABLE &&
1377             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1378                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1379                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1380                 else
1381                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1382         } else
1383                 flowctrl = tp->link_config.flowctrl;
1384
1385         tp->link_config.active_flowctrl = flowctrl;
1386
1387         if (flowctrl & FLOW_CTRL_RX)
1388                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1389         else
1390                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1391
1392         if (old_rx_mode != tp->rx_mode)
1393                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1394
1395         if (flowctrl & FLOW_CTRL_TX)
1396                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1397         else
1398                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1399
1400         if (old_tx_mode != tp->tx_mode)
1401                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1402 }
1403
1404 static void tg3_adjust_link(struct net_device *dev)
1405 {
1406         u8 oldflowctrl, linkmesg = 0;
1407         u32 mac_mode, lcl_adv, rmt_adv;
1408         struct tg3 *tp = netdev_priv(dev);
1409         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1410
1411         spin_lock_bh(&tp->lock);
1412
1413         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1414                                     MAC_MODE_HALF_DUPLEX);
1415
1416         oldflowctrl = tp->link_config.active_flowctrl;
1417
1418         if (phydev->link) {
1419                 lcl_adv = 0;
1420                 rmt_adv = 0;
1421
1422                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1423                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1424                 else if (phydev->speed == SPEED_1000 ||
1425                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1426                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1427                 else
1428                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1429
1430                 if (phydev->duplex == DUPLEX_HALF)
1431                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1432                 else {
1433                         lcl_adv = tg3_advert_flowctrl_1000T(
1434                                   tp->link_config.flowctrl);
1435
1436                         if (phydev->pause)
1437                                 rmt_adv = LPA_PAUSE_CAP;
1438                         if (phydev->asym_pause)
1439                                 rmt_adv |= LPA_PAUSE_ASYM;
1440                 }
1441
1442                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1443         } else
1444                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1445
1446         if (mac_mode != tp->mac_mode) {
1447                 tp->mac_mode = mac_mode;
1448                 tw32_f(MAC_MODE, tp->mac_mode);
1449                 udelay(40);
1450         }
1451
1452         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1453                 if (phydev->speed == SPEED_10)
1454                         tw32(MAC_MI_STAT,
1455                              MAC_MI_STAT_10MBPS_MODE |
1456                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1457                 else
1458                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1459         }
1460
1461         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1462                 tw32(MAC_TX_LENGTHS,
1463                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1464                       (6 << TX_LENGTHS_IPG_SHIFT) |
1465                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1466         else
1467                 tw32(MAC_TX_LENGTHS,
1468                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1469                       (6 << TX_LENGTHS_IPG_SHIFT) |
1470                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1471
1472         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1473             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1474             phydev->speed != tp->link_config.active_speed ||
1475             phydev->duplex != tp->link_config.active_duplex ||
1476             oldflowctrl != tp->link_config.active_flowctrl)
1477                 linkmesg = 1;
1478
1479         tp->link_config.active_speed = phydev->speed;
1480         tp->link_config.active_duplex = phydev->duplex;
1481
1482         spin_unlock_bh(&tp->lock);
1483
1484         if (linkmesg)
1485                 tg3_link_report(tp);
1486 }
1487
1488 static int tg3_phy_init(struct tg3 *tp)
1489 {
1490         struct phy_device *phydev;
1491
1492         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1493                 return 0;
1494
1495         /* Bring the PHY back to a known state. */
1496         tg3_bmcr_reset(tp);
1497
1498         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1499
1500         /* Attach the MAC to the PHY. */
1501         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1502                              phydev->dev_flags, phydev->interface);
1503         if (IS_ERR(phydev)) {
1504                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1505                 return PTR_ERR(phydev);
1506         }
1507
1508         /* Mask with MAC supported features. */
1509         switch (phydev->interface) {
1510         case PHY_INTERFACE_MODE_GMII:
1511         case PHY_INTERFACE_MODE_RGMII:
1512                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1513                         phydev->supported &= (PHY_GBIT_FEATURES |
1514                                               SUPPORTED_Pause |
1515                                               SUPPORTED_Asym_Pause);
1516                         break;
1517                 }
1518                 /* fallthru */
1519         case PHY_INTERFACE_MODE_MII:
1520                 phydev->supported &= (PHY_BASIC_FEATURES |
1521                                       SUPPORTED_Pause |
1522                                       SUPPORTED_Asym_Pause);
1523                 break;
1524         default:
1525                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1526                 return -EINVAL;
1527         }
1528
1529         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1530
1531         phydev->advertising = phydev->supported;
1532
1533         return 0;
1534 }
1535
1536 static void tg3_phy_start(struct tg3 *tp)
1537 {
1538         struct phy_device *phydev;
1539
1540         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1541                 return;
1542
1543         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1544
1545         if (tp->link_config.phy_is_low_power) {
1546                 tp->link_config.phy_is_low_power = 0;
1547                 phydev->speed = tp->link_config.orig_speed;
1548                 phydev->duplex = tp->link_config.orig_duplex;
1549                 phydev->autoneg = tp->link_config.orig_autoneg;
1550                 phydev->advertising = tp->link_config.orig_advertising;
1551         }
1552
1553         phy_start(phydev);
1554
1555         phy_start_aneg(phydev);
1556 }
1557
1558 static void tg3_phy_stop(struct tg3 *tp)
1559 {
1560         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1561                 return;
1562
1563         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1564 }
1565
1566 static void tg3_phy_fini(struct tg3 *tp)
1567 {
1568         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1569                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1570                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1571         }
1572 }
1573
1574 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1575 {
1576         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1577         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1578 }
1579
1580 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1581 {
1582         u32 phytest;
1583
1584         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1585                 u32 phy;
1586
1587                 tg3_writephy(tp, MII_TG3_FET_TEST,
1588                              phytest | MII_TG3_FET_SHADOW_EN);
1589                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1590                         if (enable)
1591                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1592                         else
1593                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1594                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1595                 }
1596                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1597         }
1598 }
1599
1600 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1601 {
1602         u32 reg;
1603
1604         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1605             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1606               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1607              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1608                 return;
1609
1610         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1611                 tg3_phy_fet_toggle_apd(tp, enable);
1612                 return;
1613         }
1614
1615         reg = MII_TG3_MISC_SHDW_WREN |
1616               MII_TG3_MISC_SHDW_SCR5_SEL |
1617               MII_TG3_MISC_SHDW_SCR5_LPED |
1618               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1619               MII_TG3_MISC_SHDW_SCR5_SDTL |
1620               MII_TG3_MISC_SHDW_SCR5_C125OE;
1621         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1622                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1623
1624         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1625
1626
1627         reg = MII_TG3_MISC_SHDW_WREN |
1628               MII_TG3_MISC_SHDW_APD_SEL |
1629               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1630         if (enable)
1631                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1632
1633         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1634 }
1635
1636 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1637 {
1638         u32 phy;
1639
1640         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1641             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1642                 return;
1643
1644         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1645                 u32 ephy;
1646
1647                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1648                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1649
1650                         tg3_writephy(tp, MII_TG3_FET_TEST,
1651                                      ephy | MII_TG3_FET_SHADOW_EN);
1652                         if (!tg3_readphy(tp, reg, &phy)) {
1653                                 if (enable)
1654                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1655                                 else
1656                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1657                                 tg3_writephy(tp, reg, phy);
1658                         }
1659                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1660                 }
1661         } else {
1662                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1663                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1664                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1665                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1666                         if (enable)
1667                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1668                         else
1669                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1670                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1671                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1672                 }
1673         }
1674 }
1675
1676 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1677 {
1678         u32 val;
1679
1680         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1681                 return;
1682
1683         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1684             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1685                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1686                              (val | (1 << 15) | (1 << 4)));
1687 }
1688
1689 static void tg3_phy_apply_otp(struct tg3 *tp)
1690 {
1691         u32 otp, phy;
1692
1693         if (!tp->phy_otp)
1694                 return;
1695
1696         otp = tp->phy_otp;
1697
1698         /* Enable SM_DSP clock and tx 6dB coding. */
1699         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1700               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1701               MII_TG3_AUXCTL_ACTL_TX_6DB;
1702         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1703
1704         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1705         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1706         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1707
1708         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1709               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1710         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1711
1712         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1713         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1714         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1715
1716         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1717         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1718
1719         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1720         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1721
1722         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1723               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1724         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1725
1726         /* Turn off SM_DSP clock. */
1727         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1728               MII_TG3_AUXCTL_ACTL_TX_6DB;
1729         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1730 }
1731
1732 static int tg3_wait_macro_done(struct tg3 *tp)
1733 {
1734         int limit = 100;
1735
1736         while (limit--) {
1737                 u32 tmp32;
1738
1739                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1740                         if ((tmp32 & 0x1000) == 0)
1741                                 break;
1742                 }
1743         }
1744         if (limit < 0)
1745                 return -EBUSY;
1746
1747         return 0;
1748 }
1749
1750 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1751 {
1752         static const u32 test_pat[4][6] = {
1753         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1754         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1755         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1756         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1757         };
1758         int chan;
1759
1760         for (chan = 0; chan < 4; chan++) {
1761                 int i;
1762
1763                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1764                              (chan * 0x2000) | 0x0200);
1765                 tg3_writephy(tp, 0x16, 0x0002);
1766
1767                 for (i = 0; i < 6; i++)
1768                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1769                                      test_pat[chan][i]);
1770
1771                 tg3_writephy(tp, 0x16, 0x0202);
1772                 if (tg3_wait_macro_done(tp)) {
1773                         *resetp = 1;
1774                         return -EBUSY;
1775                 }
1776
1777                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1778                              (chan * 0x2000) | 0x0200);
1779                 tg3_writephy(tp, 0x16, 0x0082);
1780                 if (tg3_wait_macro_done(tp)) {
1781                         *resetp = 1;
1782                         return -EBUSY;
1783                 }
1784
1785                 tg3_writephy(tp, 0x16, 0x0802);
1786                 if (tg3_wait_macro_done(tp)) {
1787                         *resetp = 1;
1788                         return -EBUSY;
1789                 }
1790
1791                 for (i = 0; i < 6; i += 2) {
1792                         u32 low, high;
1793
1794                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1795                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1796                             tg3_wait_macro_done(tp)) {
1797                                 *resetp = 1;
1798                                 return -EBUSY;
1799                         }
1800                         low &= 0x7fff;
1801                         high &= 0x000f;
1802                         if (low != test_pat[chan][i] ||
1803                             high != test_pat[chan][i+1]) {
1804                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1805                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1806                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1807
1808                                 return -EBUSY;
1809                         }
1810                 }
1811         }
1812
1813         return 0;
1814 }
1815
1816 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1817 {
1818         int chan;
1819
1820         for (chan = 0; chan < 4; chan++) {
1821                 int i;
1822
1823                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1824                              (chan * 0x2000) | 0x0200);
1825                 tg3_writephy(tp, 0x16, 0x0002);
1826                 for (i = 0; i < 6; i++)
1827                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1828                 tg3_writephy(tp, 0x16, 0x0202);
1829                 if (tg3_wait_macro_done(tp))
1830                         return -EBUSY;
1831         }
1832
1833         return 0;
1834 }
1835
1836 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1837 {
1838         u32 reg32, phy9_orig;
1839         int retries, do_phy_reset, err;
1840
1841         retries = 10;
1842         do_phy_reset = 1;
1843         do {
1844                 if (do_phy_reset) {
1845                         err = tg3_bmcr_reset(tp);
1846                         if (err)
1847                                 return err;
1848                         do_phy_reset = 0;
1849                 }
1850
1851                 /* Disable transmitter and interrupt.  */
1852                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1853                         continue;
1854
1855                 reg32 |= 0x3000;
1856                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1857
1858                 /* Set full-duplex, 1000 mbps.  */
1859                 tg3_writephy(tp, MII_BMCR,
1860                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1861
1862                 /* Set to master mode.  */
1863                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1864                         continue;
1865
1866                 tg3_writephy(tp, MII_TG3_CTRL,
1867                              (MII_TG3_CTRL_AS_MASTER |
1868                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1869
1870                 /* Enable SM_DSP_CLOCK and 6dB.  */
1871                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1872
1873                 /* Block the PHY control access.  */
1874                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1875                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1876
1877                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1878                 if (!err)
1879                         break;
1880         } while (--retries);
1881
1882         err = tg3_phy_reset_chanpat(tp);
1883         if (err)
1884                 return err;
1885
1886         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1887         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1888
1889         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1890         tg3_writephy(tp, 0x16, 0x0000);
1891
1892         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1893             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1894                 /* Set Extended packet length bit for jumbo frames */
1895                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1896         } else {
1897                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1898         }
1899
1900         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1901
1902         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1903                 reg32 &= ~0x3000;
1904                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1905         } else if (!err)
1906                 err = -EBUSY;
1907
1908         return err;
1909 }
1910
1911 /* This will reset the tigon3 PHY if there is no valid
1912  * link unless the FORCE argument is non-zero.
1913  */
1914 static int tg3_phy_reset(struct tg3 *tp)
1915 {
1916         u32 cpmuctrl;
1917         u32 phy_status;
1918         int err;
1919
1920         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1921                 u32 val;
1922
1923                 val = tr32(GRC_MISC_CFG);
1924                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1925                 udelay(40);
1926         }
1927         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1928         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1929         if (err != 0)
1930                 return -EBUSY;
1931
1932         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1933                 netif_carrier_off(tp->dev);
1934                 tg3_link_report(tp);
1935         }
1936
1937         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1938             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1939             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1940                 err = tg3_phy_reset_5703_4_5(tp);
1941                 if (err)
1942                         return err;
1943                 goto out;
1944         }
1945
1946         cpmuctrl = 0;
1947         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1948             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1949                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1950                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1951                         tw32(TG3_CPMU_CTRL,
1952                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1953         }
1954
1955         err = tg3_bmcr_reset(tp);
1956         if (err)
1957                 return err;
1958
1959         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1960                 u32 phy;
1961
1962                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1963                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1964
1965                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1966         }
1967
1968         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1969             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1970                 u32 val;
1971
1972                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1973                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1974                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1975                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1976                         udelay(40);
1977                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1978                 }
1979         }
1980
1981         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1982              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1983             (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))
1984                 return 0;
1985
1986         tg3_phy_apply_otp(tp);
1987
1988         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1989                 tg3_phy_toggle_apd(tp, true);
1990         else
1991                 tg3_phy_toggle_apd(tp, false);
1992
1993 out:
1994         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1995                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1996                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1997                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1998                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1999                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
2000                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2001         }
2002         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
2003                 tg3_writephy(tp, 0x1c, 0x8d68);
2004                 tg3_writephy(tp, 0x1c, 0x8d68);
2005         }
2006         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
2007                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2008                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2009                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
2010                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2011                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
2012                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
2013                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
2014                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2015         } else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
2016                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2017                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2018                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
2019                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2020                         tg3_writephy(tp, MII_TG3_TEST1,
2021                                      MII_TG3_TEST1_TRIM_EN | 0x4);
2022                 } else
2023                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2024                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2025         }
2026         /* Set Extended packet length bit (bit 14) on all chips that */
2027         /* support jumbo frames */
2028         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2029                 /* Cannot do read-modify-write on 5401 */
2030                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2031         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2032                 u32 phy_reg;
2033
2034                 /* Set bit 14 with read-modify-write to preserve other bits */
2035                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2036                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
2037                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
2038         }
2039
2040         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2041          * jumbo frames transmission.
2042          */
2043         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2044                 u32 phy_reg;
2045
2046                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2047                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2048                                      phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2049         }
2050
2051         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2052                 /* adjust output voltage */
2053                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2054         }
2055
2056         tg3_phy_toggle_automdix(tp, 1);
2057         tg3_phy_set_wirespeed(tp);
2058         return 0;
2059 }
2060
2061 static void tg3_frob_aux_power(struct tg3 *tp)
2062 {
2063         struct tg3 *tp_peer = tp;
2064
2065         /* The GPIOs do something completely different on 57765. */
2066         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2067             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2068             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2069                 return;
2070
2071         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2072             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2073             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2074                 struct net_device *dev_peer;
2075
2076                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2077                 /* remove_one() may have been run on the peer. */
2078                 if (!dev_peer)
2079                         tp_peer = tp;
2080                 else
2081                         tp_peer = netdev_priv(dev_peer);
2082         }
2083
2084         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2085             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2086             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2087             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2088                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2089                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2090                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2091                                     (GRC_LCLCTRL_GPIO_OE0 |
2092                                      GRC_LCLCTRL_GPIO_OE1 |
2093                                      GRC_LCLCTRL_GPIO_OE2 |
2094                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2095                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2096                                     100);
2097                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2098                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2099                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2100                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2101                                              GRC_LCLCTRL_GPIO_OE1 |
2102                                              GRC_LCLCTRL_GPIO_OE2 |
2103                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2104                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2105                                              tp->grc_local_ctrl;
2106                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2107
2108                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2109                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2110
2111                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2112                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2113                 } else {
2114                         u32 no_gpio2;
2115                         u32 grc_local_ctrl = 0;
2116
2117                         if (tp_peer != tp &&
2118                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2119                                 return;
2120
2121                         /* Workaround to prevent overdrawing Amps. */
2122                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2123                             ASIC_REV_5714) {
2124                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2125                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2126                                             grc_local_ctrl, 100);
2127                         }
2128
2129                         /* On 5753 and variants, GPIO2 cannot be used. */
2130                         no_gpio2 = tp->nic_sram_data_cfg &
2131                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2132
2133                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2134                                          GRC_LCLCTRL_GPIO_OE1 |
2135                                          GRC_LCLCTRL_GPIO_OE2 |
2136                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2137                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2138                         if (no_gpio2) {
2139                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2140                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2141                         }
2142                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2143                                                     grc_local_ctrl, 100);
2144
2145                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2146
2147                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2148                                                     grc_local_ctrl, 100);
2149
2150                         if (!no_gpio2) {
2151                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2152                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2153                                             grc_local_ctrl, 100);
2154                         }
2155                 }
2156         } else {
2157                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2158                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2159                         if (tp_peer != tp &&
2160                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2161                                 return;
2162
2163                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2164                                     (GRC_LCLCTRL_GPIO_OE1 |
2165                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2166
2167                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2168                                     GRC_LCLCTRL_GPIO_OE1, 100);
2169
2170                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2171                                     (GRC_LCLCTRL_GPIO_OE1 |
2172                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2173                 }
2174         }
2175 }
2176
2177 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2178 {
2179         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2180                 return 1;
2181         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2182                 if (speed != SPEED_10)
2183                         return 1;
2184         } else if (speed == SPEED_10)
2185                 return 1;
2186
2187         return 0;
2188 }
2189
2190 static int tg3_setup_phy(struct tg3 *, int);
2191
2192 #define RESET_KIND_SHUTDOWN     0
2193 #define RESET_KIND_INIT         1
2194 #define RESET_KIND_SUSPEND      2
2195
2196 static void tg3_write_sig_post_reset(struct tg3 *, int);
2197 static int tg3_halt_cpu(struct tg3 *, u32);
2198
2199 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2200 {
2201         u32 val;
2202
2203         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2204                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2205                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2206                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2207
2208                         sg_dig_ctrl |=
2209                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2210                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2211                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2212                 }
2213                 return;
2214         }
2215
2216         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2217                 tg3_bmcr_reset(tp);
2218                 val = tr32(GRC_MISC_CFG);
2219                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2220                 udelay(40);
2221                 return;
2222         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2223                 u32 phytest;
2224                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2225                         u32 phy;
2226
2227                         tg3_writephy(tp, MII_ADVERTISE, 0);
2228                         tg3_writephy(tp, MII_BMCR,
2229                                      BMCR_ANENABLE | BMCR_ANRESTART);
2230
2231                         tg3_writephy(tp, MII_TG3_FET_TEST,
2232                                      phytest | MII_TG3_FET_SHADOW_EN);
2233                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2234                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2235                                 tg3_writephy(tp,
2236                                              MII_TG3_FET_SHDW_AUXMODE4,
2237                                              phy);
2238                         }
2239                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2240                 }
2241                 return;
2242         } else if (do_low_power) {
2243                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2244                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2245
2246                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2247                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2248                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2249                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2250                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2251         }
2252
2253         /* The PHY should not be powered down on some chips because
2254          * of bugs.
2255          */
2256         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2257             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2258             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2259              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2260                 return;
2261
2262         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2263             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2264                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2265                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2266                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2267                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2268         }
2269
2270         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2271 }
2272
2273 /* tp->lock is held. */
2274 static int tg3_nvram_lock(struct tg3 *tp)
2275 {
2276         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2277                 int i;
2278
2279                 if (tp->nvram_lock_cnt == 0) {
2280                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2281                         for (i = 0; i < 8000; i++) {
2282                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2283                                         break;
2284                                 udelay(20);
2285                         }
2286                         if (i == 8000) {
2287                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2288                                 return -ENODEV;
2289                         }
2290                 }
2291                 tp->nvram_lock_cnt++;
2292         }
2293         return 0;
2294 }
2295
2296 /* tp->lock is held. */
2297 static void tg3_nvram_unlock(struct tg3 *tp)
2298 {
2299         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2300                 if (tp->nvram_lock_cnt > 0)
2301                         tp->nvram_lock_cnt--;
2302                 if (tp->nvram_lock_cnt == 0)
2303                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2304         }
2305 }
2306
2307 /* tp->lock is held. */
2308 static void tg3_enable_nvram_access(struct tg3 *tp)
2309 {
2310         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2311             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2312                 u32 nvaccess = tr32(NVRAM_ACCESS);
2313
2314                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2315         }
2316 }
2317
2318 /* tp->lock is held. */
2319 static void tg3_disable_nvram_access(struct tg3 *tp)
2320 {
2321         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2322             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2323                 u32 nvaccess = tr32(NVRAM_ACCESS);
2324
2325                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2326         }
2327 }
2328
2329 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2330                                         u32 offset, u32 *val)
2331 {
2332         u32 tmp;
2333         int i;
2334
2335         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2336                 return -EINVAL;
2337
2338         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2339                                         EEPROM_ADDR_DEVID_MASK |
2340                                         EEPROM_ADDR_READ);
2341         tw32(GRC_EEPROM_ADDR,
2342              tmp |
2343              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2344              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2345               EEPROM_ADDR_ADDR_MASK) |
2346              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2347
2348         for (i = 0; i < 1000; i++) {
2349                 tmp = tr32(GRC_EEPROM_ADDR);
2350
2351                 if (tmp & EEPROM_ADDR_COMPLETE)
2352                         break;
2353                 msleep(1);
2354         }
2355         if (!(tmp & EEPROM_ADDR_COMPLETE))
2356                 return -EBUSY;
2357
2358         tmp = tr32(GRC_EEPROM_DATA);
2359
2360         /*
2361          * The data will always be opposite the native endian
2362          * format.  Perform a blind byteswap to compensate.
2363          */
2364         *val = swab32(tmp);
2365
2366         return 0;
2367 }
2368
2369 #define NVRAM_CMD_TIMEOUT 10000
2370
2371 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2372 {
2373         int i;
2374
2375         tw32(NVRAM_CMD, nvram_cmd);
2376         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2377                 udelay(10);
2378                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2379                         udelay(10);
2380                         break;
2381                 }
2382         }
2383
2384         if (i == NVRAM_CMD_TIMEOUT)
2385                 return -EBUSY;
2386
2387         return 0;
2388 }
2389
2390 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2391 {
2392         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2393             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2394             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2395            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2396             (tp->nvram_jedecnum == JEDEC_ATMEL))
2397
2398                 addr = ((addr / tp->nvram_pagesize) <<
2399                         ATMEL_AT45DB0X1B_PAGE_POS) +
2400                        (addr % tp->nvram_pagesize);
2401
2402         return addr;
2403 }
2404
2405 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2406 {
2407         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2408             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2409             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2410            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2411             (tp->nvram_jedecnum == JEDEC_ATMEL))
2412
2413                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2414                         tp->nvram_pagesize) +
2415                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2416
2417         return addr;
2418 }
2419
2420 /* NOTE: Data read in from NVRAM is byteswapped according to
2421  * the byteswapping settings for all other register accesses.
2422  * tg3 devices are BE devices, so on a BE machine, the data
2423  * returned will be exactly as it is seen in NVRAM.  On a LE
2424  * machine, the 32-bit value will be byteswapped.
2425  */
2426 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2427 {
2428         int ret;
2429
2430         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2431                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2432
2433         offset = tg3_nvram_phys_addr(tp, offset);
2434
2435         if (offset > NVRAM_ADDR_MSK)
2436                 return -EINVAL;
2437
2438         ret = tg3_nvram_lock(tp);
2439         if (ret)
2440                 return ret;
2441
2442         tg3_enable_nvram_access(tp);
2443
2444         tw32(NVRAM_ADDR, offset);
2445         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2446                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2447
2448         if (ret == 0)
2449                 *val = tr32(NVRAM_RDDATA);
2450
2451         tg3_disable_nvram_access(tp);
2452
2453         tg3_nvram_unlock(tp);
2454
2455         return ret;
2456 }
2457
2458 /* Ensures NVRAM data is in bytestream format. */
2459 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2460 {
2461         u32 v;
2462         int res = tg3_nvram_read(tp, offset, &v);
2463         if (!res)
2464                 *val = cpu_to_be32(v);
2465         return res;
2466 }
2467
2468 /* tp->lock is held. */
2469 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2470 {
2471         u32 addr_high, addr_low;
2472         int i;
2473
2474         addr_high = ((tp->dev->dev_addr[0] << 8) |
2475                      tp->dev->dev_addr[1]);
2476         addr_low = ((tp->dev->dev_addr[2] << 24) |
2477                     (tp->dev->dev_addr[3] << 16) |
2478                     (tp->dev->dev_addr[4] <<  8) |
2479                     (tp->dev->dev_addr[5] <<  0));
2480         for (i = 0; i < 4; i++) {
2481                 if (i == 1 && skip_mac_1)
2482                         continue;
2483                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2484                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2485         }
2486
2487         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2488             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2489                 for (i = 0; i < 12; i++) {
2490                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2491                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2492                 }
2493         }
2494
2495         addr_high = (tp->dev->dev_addr[0] +
2496                      tp->dev->dev_addr[1] +
2497                      tp->dev->dev_addr[2] +
2498                      tp->dev->dev_addr[3] +
2499                      tp->dev->dev_addr[4] +
2500                      tp->dev->dev_addr[5]) &
2501                 TX_BACKOFF_SEED_MASK;
2502         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2503 }
2504
2505 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2506 {
2507         u32 misc_host_ctrl;
2508         bool device_should_wake, do_low_power;
2509
2510         /* Make sure register accesses (indirect or otherwise)
2511          * will function correctly.
2512          */
2513         pci_write_config_dword(tp->pdev,
2514                                TG3PCI_MISC_HOST_CTRL,
2515                                tp->misc_host_ctrl);
2516
2517         switch (state) {
2518         case PCI_D0:
2519                 pci_enable_wake(tp->pdev, state, false);
2520                 pci_set_power_state(tp->pdev, PCI_D0);
2521
2522                 /* Switch out of Vaux if it is a NIC */
2523                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2524                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2525
2526                 return 0;
2527
2528         case PCI_D1:
2529         case PCI_D2:
2530         case PCI_D3hot:
2531                 break;
2532
2533         default:
2534                 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2535                            state);
2536                 return -EINVAL;
2537         }
2538
2539         /* Restore the CLKREQ setting. */
2540         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2541                 u16 lnkctl;
2542
2543                 pci_read_config_word(tp->pdev,
2544                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2545                                      &lnkctl);
2546                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2547                 pci_write_config_word(tp->pdev,
2548                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2549                                       lnkctl);
2550         }
2551
2552         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2553         tw32(TG3PCI_MISC_HOST_CTRL,
2554              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2555
2556         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2557                              device_may_wakeup(&tp->pdev->dev) &&
2558                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2559
2560         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2561                 do_low_power = false;
2562                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2563                     !tp->link_config.phy_is_low_power) {
2564                         struct phy_device *phydev;
2565                         u32 phyid, advertising;
2566
2567                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2568
2569                         tp->link_config.phy_is_low_power = 1;
2570
2571                         tp->link_config.orig_speed = phydev->speed;
2572                         tp->link_config.orig_duplex = phydev->duplex;
2573                         tp->link_config.orig_autoneg = phydev->autoneg;
2574                         tp->link_config.orig_advertising = phydev->advertising;
2575
2576                         advertising = ADVERTISED_TP |
2577                                       ADVERTISED_Pause |
2578                                       ADVERTISED_Autoneg |
2579                                       ADVERTISED_10baseT_Half;
2580
2581                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2582                             device_should_wake) {
2583                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2584                                         advertising |=
2585                                                 ADVERTISED_100baseT_Half |
2586                                                 ADVERTISED_100baseT_Full |
2587                                                 ADVERTISED_10baseT_Full;
2588                                 else
2589                                         advertising |= ADVERTISED_10baseT_Full;
2590                         }
2591
2592                         phydev->advertising = advertising;
2593
2594                         phy_start_aneg(phydev);
2595
2596                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2597                         if (phyid != PHY_ID_BCMAC131) {
2598                                 phyid &= PHY_BCM_OUI_MASK;
2599                                 if (phyid == PHY_BCM_OUI_1 ||
2600                                     phyid == PHY_BCM_OUI_2 ||
2601                                     phyid == PHY_BCM_OUI_3)
2602                                         do_low_power = true;
2603                         }
2604                 }
2605         } else {
2606                 do_low_power = true;
2607
2608                 if (tp->link_config.phy_is_low_power == 0) {
2609                         tp->link_config.phy_is_low_power = 1;
2610                         tp->link_config.orig_speed = tp->link_config.speed;
2611                         tp->link_config.orig_duplex = tp->link_config.duplex;
2612                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2613                 }
2614
2615                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2616                         tp->link_config.speed = SPEED_10;
2617                         tp->link_config.duplex = DUPLEX_HALF;
2618                         tp->link_config.autoneg = AUTONEG_ENABLE;
2619                         tg3_setup_phy(tp, 0);
2620                 }
2621         }
2622
2623         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2624                 u32 val;
2625
2626                 val = tr32(GRC_VCPU_EXT_CTRL);
2627                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2628         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2629                 int i;
2630                 u32 val;
2631
2632                 for (i = 0; i < 200; i++) {
2633                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2634                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2635                                 break;
2636                         msleep(1);
2637                 }
2638         }
2639         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2640                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2641                                                      WOL_DRV_STATE_SHUTDOWN |
2642                                                      WOL_DRV_WOL |
2643                                                      WOL_SET_MAGIC_PKT);
2644
2645         if (device_should_wake) {
2646                 u32 mac_mode;
2647
2648                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2649                         if (do_low_power) {
2650                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2651                                 udelay(40);
2652                         }
2653
2654                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2655                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2656                         else
2657                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2658
2659                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2660                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2661                             ASIC_REV_5700) {
2662                                 u32 speed = (tp->tg3_flags &
2663                                              TG3_FLAG_WOL_SPEED_100MB) ?
2664                                              SPEED_100 : SPEED_10;
2665                                 if (tg3_5700_link_polarity(tp, speed))
2666                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2667                                 else
2668                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2669                         }
2670                 } else {
2671                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2672                 }
2673
2674                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2675                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2676
2677                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2678                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2679                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2680                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2681                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2682                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2683
2684                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2685                         mac_mode |= tp->mac_mode &
2686                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2687                         if (mac_mode & MAC_MODE_APE_TX_EN)
2688                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2689                 }
2690
2691                 tw32_f(MAC_MODE, mac_mode);
2692                 udelay(100);
2693
2694                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2695                 udelay(10);
2696         }
2697
2698         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2699             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2700              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2701                 u32 base_val;
2702
2703                 base_val = tp->pci_clock_ctrl;
2704                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2705                              CLOCK_CTRL_TXCLK_DISABLE);
2706
2707                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2708                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2709         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2710                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2711                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2712                 /* do nothing */
2713         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2714                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2715                 u32 newbits1, newbits2;
2716
2717                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2718                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2719                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2720                                     CLOCK_CTRL_TXCLK_DISABLE |
2721                                     CLOCK_CTRL_ALTCLK);
2722                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2723                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2724                         newbits1 = CLOCK_CTRL_625_CORE;
2725                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2726                 } else {
2727                         newbits1 = CLOCK_CTRL_ALTCLK;
2728                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2729                 }
2730
2731                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2732                             40);
2733
2734                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2735                             40);
2736
2737                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2738                         u32 newbits3;
2739
2740                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2741                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2742                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2743                                             CLOCK_CTRL_TXCLK_DISABLE |
2744                                             CLOCK_CTRL_44MHZ_CORE);
2745                         } else {
2746                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2747                         }
2748
2749                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2750                                     tp->pci_clock_ctrl | newbits3, 40);
2751                 }
2752         }
2753
2754         if (!(device_should_wake) &&
2755             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2756                 tg3_power_down_phy(tp, do_low_power);
2757
2758         tg3_frob_aux_power(tp);
2759
2760         /* Workaround for unstable PLL clock */
2761         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2762             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2763                 u32 val = tr32(0x7d00);
2764
2765                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2766                 tw32(0x7d00, val);
2767                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2768                         int err;
2769
2770                         err = tg3_nvram_lock(tp);
2771                         tg3_halt_cpu(tp, RX_CPU_BASE);
2772                         if (!err)
2773                                 tg3_nvram_unlock(tp);
2774                 }
2775         }
2776
2777         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2778
2779         if (device_should_wake)
2780                 pci_enable_wake(tp->pdev, state, true);
2781
2782         /* Finally, set the new power state. */
2783         pci_set_power_state(tp->pdev, state);
2784
2785         return 0;
2786 }
2787
2788 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2789 {
2790         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2791         case MII_TG3_AUX_STAT_10HALF:
2792                 *speed = SPEED_10;
2793                 *duplex = DUPLEX_HALF;
2794                 break;
2795
2796         case MII_TG3_AUX_STAT_10FULL:
2797                 *speed = SPEED_10;
2798                 *duplex = DUPLEX_FULL;
2799                 break;
2800
2801         case MII_TG3_AUX_STAT_100HALF:
2802                 *speed = SPEED_100;
2803                 *duplex = DUPLEX_HALF;
2804                 break;
2805
2806         case MII_TG3_AUX_STAT_100FULL:
2807                 *speed = SPEED_100;
2808                 *duplex = DUPLEX_FULL;
2809                 break;
2810
2811         case MII_TG3_AUX_STAT_1000HALF:
2812                 *speed = SPEED_1000;
2813                 *duplex = DUPLEX_HALF;
2814                 break;
2815
2816         case MII_TG3_AUX_STAT_1000FULL:
2817                 *speed = SPEED_1000;
2818                 *duplex = DUPLEX_FULL;
2819                 break;
2820
2821         default:
2822                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2823                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2824                                  SPEED_10;
2825                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2826                                   DUPLEX_HALF;
2827                         break;
2828                 }
2829                 *speed = SPEED_INVALID;
2830                 *duplex = DUPLEX_INVALID;
2831                 break;
2832         }
2833 }
2834
2835 static void tg3_phy_copper_begin(struct tg3 *tp)
2836 {
2837         u32 new_adv;
2838         int i;
2839
2840         if (tp->link_config.phy_is_low_power) {
2841                 /* Entering low power mode.  Disable gigabit and
2842                  * 100baseT advertisements.
2843                  */
2844                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2845
2846                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2847                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2848                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2849                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2850
2851                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2852         } else if (tp->link_config.speed == SPEED_INVALID) {
2853                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2854                         tp->link_config.advertising &=
2855                                 ~(ADVERTISED_1000baseT_Half |
2856                                   ADVERTISED_1000baseT_Full);
2857
2858                 new_adv = ADVERTISE_CSMA;
2859                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2860                         new_adv |= ADVERTISE_10HALF;
2861                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2862                         new_adv |= ADVERTISE_10FULL;
2863                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2864                         new_adv |= ADVERTISE_100HALF;
2865                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2866                         new_adv |= ADVERTISE_100FULL;
2867
2868                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2869
2870                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2871
2872                 if (tp->link_config.advertising &
2873                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2874                         new_adv = 0;
2875                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2876                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2877                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2878                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2879                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2880                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2881                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2882                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2883                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2884                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2885                 } else {
2886                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2887                 }
2888         } else {
2889                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2890                 new_adv |= ADVERTISE_CSMA;
2891
2892                 /* Asking for a specific link mode. */
2893                 if (tp->link_config.speed == SPEED_1000) {
2894                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2895
2896                         if (tp->link_config.duplex == DUPLEX_FULL)
2897                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2898                         else
2899                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2900                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2901                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2902                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2903                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2904                 } else {
2905                         if (tp->link_config.speed == SPEED_100) {
2906                                 if (tp->link_config.duplex == DUPLEX_FULL)
2907                                         new_adv |= ADVERTISE_100FULL;
2908                                 else
2909                                         new_adv |= ADVERTISE_100HALF;
2910                         } else {
2911                                 if (tp->link_config.duplex == DUPLEX_FULL)
2912                                         new_adv |= ADVERTISE_10FULL;
2913                                 else
2914                                         new_adv |= ADVERTISE_10HALF;
2915                         }
2916                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2917
2918                         new_adv = 0;
2919                 }
2920
2921                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2922         }
2923
2924         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2925             tp->link_config.speed != SPEED_INVALID) {
2926                 u32 bmcr, orig_bmcr;
2927
2928                 tp->link_config.active_speed = tp->link_config.speed;
2929                 tp->link_config.active_duplex = tp->link_config.duplex;
2930
2931                 bmcr = 0;
2932                 switch (tp->link_config.speed) {
2933                 default:
2934                 case SPEED_10:
2935                         break;
2936
2937                 case SPEED_100:
2938                         bmcr |= BMCR_SPEED100;
2939                         break;
2940
2941                 case SPEED_1000:
2942                         bmcr |= TG3_BMCR_SPEED1000;
2943                         break;
2944                 }
2945
2946                 if (tp->link_config.duplex == DUPLEX_FULL)
2947                         bmcr |= BMCR_FULLDPLX;
2948
2949                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2950                     (bmcr != orig_bmcr)) {
2951                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2952                         for (i = 0; i < 1500; i++) {
2953                                 u32 tmp;
2954
2955                                 udelay(10);
2956                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2957                                     tg3_readphy(tp, MII_BMSR, &tmp))
2958                                         continue;
2959                                 if (!(tmp & BMSR_LSTATUS)) {
2960                                         udelay(40);
2961                                         break;
2962                                 }
2963                         }
2964                         tg3_writephy(tp, MII_BMCR, bmcr);
2965                         udelay(40);
2966                 }
2967         } else {
2968                 tg3_writephy(tp, MII_BMCR,
2969                              BMCR_ANENABLE | BMCR_ANRESTART);
2970         }
2971 }
2972
2973 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2974 {
2975         int err;
2976
2977         /* Turn off tap power management. */
2978         /* Set Extended packet length bit */
2979         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2980
2981         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2982         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2983
2984         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2985         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2986
2987         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2988         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2989
2990         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2991         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2992
2993         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2994         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2995
2996         udelay(40);
2997
2998         return err;
2999 }
3000
3001 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3002 {
3003         u32 adv_reg, all_mask = 0;
3004
3005         if (mask & ADVERTISED_10baseT_Half)
3006                 all_mask |= ADVERTISE_10HALF;
3007         if (mask & ADVERTISED_10baseT_Full)
3008                 all_mask |= ADVERTISE_10FULL;
3009         if (mask & ADVERTISED_100baseT_Half)
3010                 all_mask |= ADVERTISE_100HALF;
3011         if (mask & ADVERTISED_100baseT_Full)
3012                 all_mask |= ADVERTISE_100FULL;
3013
3014         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3015                 return 0;
3016
3017         if ((adv_reg & all_mask) != all_mask)
3018                 return 0;
3019         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
3020                 u32 tg3_ctrl;
3021
3022                 all_mask = 0;
3023                 if (mask & ADVERTISED_1000baseT_Half)
3024                         all_mask |= ADVERTISE_1000HALF;
3025                 if (mask & ADVERTISED_1000baseT_Full)
3026                         all_mask |= ADVERTISE_1000FULL;
3027
3028                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3029                         return 0;
3030
3031                 if ((tg3_ctrl & all_mask) != all_mask)
3032                         return 0;
3033         }
3034         return 1;
3035 }
3036
3037 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3038 {
3039         u32 curadv, reqadv;
3040
3041         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3042                 return 1;
3043
3044         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3045         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3046
3047         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3048                 if (curadv != reqadv)
3049                         return 0;
3050
3051                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3052                         tg3_readphy(tp, MII_LPA, rmtadv);
3053         } else {
3054                 /* Reprogram the advertisement register, even if it
3055                  * does not affect the current link.  If the link
3056                  * gets renegotiated in the future, we can save an
3057                  * additional renegotiation cycle by advertising
3058                  * it correctly in the first place.
3059                  */
3060                 if (curadv != reqadv) {
3061                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3062                                      ADVERTISE_PAUSE_ASYM);
3063                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3064                 }
3065         }
3066
3067         return 1;
3068 }
3069
3070 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3071 {
3072         int current_link_up;
3073         u32 bmsr, dummy;
3074         u32 lcl_adv, rmt_adv;
3075         u16 current_speed;
3076         u8 current_duplex;
3077         int i, err;
3078
3079         tw32(MAC_EVENT, 0);
3080
3081         tw32_f(MAC_STATUS,
3082              (MAC_STATUS_SYNC_CHANGED |
3083               MAC_STATUS_CFG_CHANGED |
3084               MAC_STATUS_MI_COMPLETION |
3085               MAC_STATUS_LNKSTATE_CHANGED));
3086         udelay(40);
3087
3088         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3089                 tw32_f(MAC_MI_MODE,
3090                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3091                 udelay(80);
3092         }
3093
3094         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3095
3096         /* Some third-party PHYs need to be reset on link going
3097          * down.
3098          */
3099         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3100              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3101              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3102             netif_carrier_ok(tp->dev)) {
3103                 tg3_readphy(tp, MII_BMSR, &bmsr);
3104                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3105                     !(bmsr & BMSR_LSTATUS))
3106                         force_reset = 1;
3107         }
3108         if (force_reset)
3109                 tg3_phy_reset(tp);
3110
3111         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3112                 tg3_readphy(tp, MII_BMSR, &bmsr);
3113                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3114                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3115                         bmsr = 0;
3116
3117                 if (!(bmsr & BMSR_LSTATUS)) {
3118                         err = tg3_init_5401phy_dsp(tp);
3119                         if (err)
3120                                 return err;
3121
3122                         tg3_readphy(tp, MII_BMSR, &bmsr);
3123                         for (i = 0; i < 1000; i++) {
3124                                 udelay(10);
3125                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3126                                     (bmsr & BMSR_LSTATUS)) {
3127                                         udelay(40);
3128                                         break;
3129                                 }
3130                         }
3131
3132                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3133                             TG3_PHY_REV_BCM5401_B0 &&
3134                             !(bmsr & BMSR_LSTATUS) &&
3135                             tp->link_config.active_speed == SPEED_1000) {
3136                                 err = tg3_phy_reset(tp);
3137                                 if (!err)
3138                                         err = tg3_init_5401phy_dsp(tp);
3139                                 if (err)
3140                                         return err;
3141                         }
3142                 }
3143         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3144                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3145                 /* 5701 {A0,B0} CRC bug workaround */
3146                 tg3_writephy(tp, 0x15, 0x0a75);
3147                 tg3_writephy(tp, 0x1c, 0x8c68);
3148                 tg3_writephy(tp, 0x1c, 0x8d68);
3149                 tg3_writephy(tp, 0x1c, 0x8c68);
3150         }
3151
3152         /* Clear pending interrupts... */
3153         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3154         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3155
3156         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3157                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3158         else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3159                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3160
3161         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3162             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3163                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3164                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3165                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3166                 else
3167                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3168         }
3169
3170         current_link_up = 0;
3171         current_speed = SPEED_INVALID;
3172         current_duplex = DUPLEX_INVALID;
3173
3174         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3175                 u32 val;
3176
3177                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3178                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3179                 if (!(val & (1 << 10))) {
3180                         val |= (1 << 10);
3181                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3182                         goto relink;
3183                 }
3184         }
3185
3186         bmsr = 0;
3187         for (i = 0; i < 100; i++) {
3188                 tg3_readphy(tp, MII_BMSR, &bmsr);
3189                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3190                     (bmsr & BMSR_LSTATUS))
3191                         break;
3192                 udelay(40);
3193         }
3194
3195         if (bmsr & BMSR_LSTATUS) {
3196                 u32 aux_stat, bmcr;
3197
3198                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3199                 for (i = 0; i < 2000; i++) {
3200                         udelay(10);
3201                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3202                             aux_stat)
3203                                 break;
3204                 }
3205
3206                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3207                                              &current_speed,
3208                                              &current_duplex);
3209
3210                 bmcr = 0;
3211                 for (i = 0; i < 200; i++) {
3212                         tg3_readphy(tp, MII_BMCR, &bmcr);
3213                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3214                                 continue;
3215                         if (bmcr && bmcr != 0x7fff)
3216                                 break;
3217                         udelay(10);
3218                 }
3219
3220                 lcl_adv = 0;
3221                 rmt_adv = 0;
3222
3223                 tp->link_config.active_speed = current_speed;
3224                 tp->link_config.active_duplex = current_duplex;
3225
3226                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3227                         if ((bmcr & BMCR_ANENABLE) &&
3228                             tg3_copper_is_advertising_all(tp,
3229                                                 tp->link_config.advertising)) {
3230                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3231                                                                   &rmt_adv))
3232                                         current_link_up = 1;
3233                         }
3234                 } else {
3235                         if (!(bmcr & BMCR_ANENABLE) &&
3236                             tp->link_config.speed == current_speed &&
3237                             tp->link_config.duplex == current_duplex &&
3238                             tp->link_config.flowctrl ==
3239                             tp->link_config.active_flowctrl) {
3240                                 current_link_up = 1;
3241                         }
3242                 }
3243
3244                 if (current_link_up == 1 &&
3245                     tp->link_config.active_duplex == DUPLEX_FULL)
3246                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3247         }
3248
3249 relink:
3250         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3251                 u32 tmp;
3252
3253                 tg3_phy_copper_begin(tp);
3254
3255                 tg3_readphy(tp, MII_BMSR, &tmp);
3256                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3257                     (tmp & BMSR_LSTATUS))
3258                         current_link_up = 1;
3259         }
3260
3261         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3262         if (current_link_up == 1) {
3263                 if (tp->link_config.active_speed == SPEED_100 ||
3264                     tp->link_config.active_speed == SPEED_10)
3265                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3266                 else
3267                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3268         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3269                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3270         else
3271                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3272
3273         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3274         if (tp->link_config.active_duplex == DUPLEX_HALF)
3275                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3276
3277         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3278                 if (current_link_up == 1 &&
3279                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3280                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3281                 else
3282                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3283         }
3284
3285         /* ??? Without this setting Netgear GA302T PHY does not
3286          * ??? send/receive packets...
3287          */
3288         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3289             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3290                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3291                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3292                 udelay(80);
3293         }
3294
3295         tw32_f(MAC_MODE, tp->mac_mode);
3296         udelay(40);
3297
3298         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3299                 /* Polled via timer. */
3300                 tw32_f(MAC_EVENT, 0);
3301         } else {
3302                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3303         }
3304         udelay(40);
3305
3306         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3307             current_link_up == 1 &&
3308             tp->link_config.active_speed == SPEED_1000 &&
3309             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3310              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3311                 udelay(120);
3312                 tw32_f(MAC_STATUS,
3313                      (MAC_STATUS_SYNC_CHANGED |
3314                       MAC_STATUS_CFG_CHANGED));
3315                 udelay(40);
3316                 tg3_write_mem(tp,
3317                               NIC_SRAM_FIRMWARE_MBOX,
3318                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3319         }
3320
3321         /* Prevent send BD corruption. */
3322         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3323                 u16 oldlnkctl, newlnkctl;
3324
3325                 pci_read_config_word(tp->pdev,
3326                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3327                                      &oldlnkctl);
3328                 if (tp->link_config.active_speed == SPEED_100 ||
3329                     tp->link_config.active_speed == SPEED_10)
3330                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3331                 else
3332                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3333                 if (newlnkctl != oldlnkctl)
3334                         pci_write_config_word(tp->pdev,
3335                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3336                                               newlnkctl);
3337         }
3338
3339         if (current_link_up != netif_carrier_ok(tp->dev)) {
3340                 if (current_link_up)
3341                         netif_carrier_on(tp->dev);
3342                 else
3343                         netif_carrier_off(tp->dev);
3344                 tg3_link_report(tp);
3345         }
3346
3347         return 0;
3348 }
3349
3350 struct tg3_fiber_aneginfo {
3351         int state;
3352 #define ANEG_STATE_UNKNOWN              0
3353 #define ANEG_STATE_AN_ENABLE            1
3354 #define ANEG_STATE_RESTART_INIT         2
3355 #define ANEG_STATE_RESTART              3
3356 #define ANEG_STATE_DISABLE_LINK_OK      4
3357 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3358 #define ANEG_STATE_ABILITY_DETECT       6
3359 #define ANEG_STATE_ACK_DETECT_INIT      7
3360 #define ANEG_STATE_ACK_DETECT           8
3361 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3362 #define ANEG_STATE_COMPLETE_ACK         10
3363 #define ANEG_STATE_IDLE_DETECT_INIT     11
3364 #define ANEG_STATE_IDLE_DETECT          12
3365 #define ANEG_STATE_LINK_OK              13
3366 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3367 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3368
3369         u32 flags;
3370 #define MR_AN_ENABLE            0x00000001
3371 #define MR_RESTART_AN           0x00000002
3372 #define MR_AN_COMPLETE          0x00000004
3373 #define MR_PAGE_RX              0x00000008
3374 #define MR_NP_LOADED            0x00000010
3375 #define MR_TOGGLE_TX            0x00000020
3376 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3377 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3378 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3379 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3380 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3381 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3382 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3383 #define MR_TOGGLE_RX            0x00002000
3384 #define MR_NP_RX                0x00004000
3385
3386 #define MR_LINK_OK              0x80000000
3387
3388         unsigned long link_time, cur_time;
3389
3390         u32 ability_match_cfg;
3391         int ability_match_count;
3392
3393         char ability_match, idle_match, ack_match;
3394
3395         u32 txconfig, rxconfig;
3396 #define ANEG_CFG_NP             0x00000080
3397 #define ANEG_CFG_ACK            0x00000040
3398 #define ANEG_CFG_RF2            0x00000020
3399 #define ANEG_CFG_RF1            0x00000010
3400 #define ANEG_CFG_PS2            0x00000001
3401 #define ANEG_CFG_PS1            0x00008000
3402 #define ANEG_CFG_HD             0x00004000
3403 #define ANEG_CFG_FD             0x00002000
3404 #define ANEG_CFG_INVAL          0x00001f06
3405
3406 };
3407 #define ANEG_OK         0
3408 #define ANEG_DONE       1
3409 #define ANEG_TIMER_ENAB 2
3410 #define ANEG_FAILED     -1
3411
3412 #define ANEG_STATE_SETTLE_TIME  10000
3413
3414 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3415                                    struct tg3_fiber_aneginfo *ap)
3416 {
3417         u16 flowctrl;
3418         unsigned long delta;
3419         u32 rx_cfg_reg;
3420         int ret;
3421
3422         if (ap->state == ANEG_STATE_UNKNOWN) {
3423                 ap->rxconfig = 0;
3424                 ap->link_time = 0;
3425                 ap->cur_time = 0;
3426                 ap->ability_match_cfg = 0;
3427                 ap->ability_match_count = 0;
3428                 ap->ability_match = 0;
3429                 ap->idle_match = 0;
3430                 ap->ack_match = 0;
3431         }
3432         ap->cur_time++;
3433
3434         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3435                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3436
3437                 if (rx_cfg_reg != ap->ability_match_cfg) {
3438                         ap->ability_match_cfg = rx_cfg_reg;
3439                         ap->ability_match = 0;
3440                         ap->ability_match_count = 0;
3441                 } else {
3442                         if (++ap->ability_match_count > 1) {
3443                                 ap->ability_match = 1;
3444                                 ap->ability_match_cfg = rx_cfg_reg;
3445                         }
3446                 }
3447                 if (rx_cfg_reg & ANEG_CFG_ACK)
3448                         ap->ack_match = 1;
3449                 else
3450                         ap->ack_match = 0;
3451
3452                 ap->idle_match = 0;
3453         } else {
3454                 ap->idle_match = 1;
3455                 ap->ability_match_cfg = 0;
3456                 ap->ability_match_count = 0;
3457                 ap->ability_match = 0;
3458                 ap->ack_match = 0;
3459
3460                 rx_cfg_reg = 0;
3461         }
3462
3463         ap->rxconfig = rx_cfg_reg;
3464         ret = ANEG_OK;
3465
3466         switch (ap->state) {
3467         case ANEG_STATE_UNKNOWN:
3468                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3469                         ap->state = ANEG_STATE_AN_ENABLE;
3470
3471                 /* fallthru */
3472         case ANEG_STATE_AN_ENABLE:
3473                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3474                 if (ap->flags & MR_AN_ENABLE) {
3475                         ap->link_time = 0;
3476                         ap->cur_time = 0;
3477                         ap->ability_match_cfg = 0;
3478                         ap->ability_match_count = 0;
3479                         ap->ability_match = 0;
3480                         ap->idle_match = 0;
3481                         ap->ack_match = 0;
3482
3483                         ap->state = ANEG_STATE_RESTART_INIT;
3484                 } else {
3485                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3486                 }
3487                 break;
3488
3489         case ANEG_STATE_RESTART_INIT:
3490                 ap->link_time = ap->cur_time;
3491                 ap->flags &= ~(MR_NP_LOADED);
3492                 ap->txconfig = 0;
3493                 tw32(MAC_TX_AUTO_NEG, 0);
3494                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3495                 tw32_f(MAC_MODE, tp->mac_mode);
3496                 udelay(40);
3497
3498                 ret = ANEG_TIMER_ENAB;
3499                 ap->state = ANEG_STATE_RESTART;
3500
3501                 /* fallthru */
3502         case ANEG_STATE_RESTART:
3503                 delta = ap->cur_time - ap->link_time;
3504                 if (delta > ANEG_STATE_SETTLE_TIME)
3505                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3506                 else
3507                         ret = ANEG_TIMER_ENAB;
3508                 break;
3509
3510         case ANEG_STATE_DISABLE_LINK_OK:
3511                 ret = ANEG_DONE;
3512                 break;
3513
3514         case ANEG_STATE_ABILITY_DETECT_INIT:
3515                 ap->flags &= ~(MR_TOGGLE_TX);
3516                 ap->txconfig = ANEG_CFG_FD;
3517                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3518                 if (flowctrl & ADVERTISE_1000XPAUSE)
3519                         ap->txconfig |= ANEG_CFG_PS1;
3520                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3521                         ap->txconfig |= ANEG_CFG_PS2;
3522                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3523                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3524                 tw32_f(MAC_MODE, tp->mac_mode);
3525                 udelay(40);
3526
3527                 ap->state = ANEG_STATE_ABILITY_DETECT;
3528                 break;
3529
3530         case ANEG_STATE_ABILITY_DETECT:
3531                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3532                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3533                 break;
3534
3535         case ANEG_STATE_ACK_DETECT_INIT:
3536                 ap->txconfig |= ANEG_CFG_ACK;
3537                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3538                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3539                 tw32_f(MAC_MODE, tp->mac_mode);
3540                 udelay(40);
3541
3542                 ap->state = ANEG_STATE_ACK_DETECT;
3543
3544                 /* fallthru */
3545         case ANEG_STATE_ACK_DETECT:
3546                 if (ap->ack_match != 0) {
3547                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3548                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3549                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3550                         } else {
3551                                 ap->state = ANEG_STATE_AN_ENABLE;
3552                         }
3553                 } else if (ap->ability_match != 0 &&
3554                            ap->rxconfig == 0) {
3555                         ap->state = ANEG_STATE_AN_ENABLE;
3556                 }
3557                 break;
3558
3559         case ANEG_STATE_COMPLETE_ACK_INIT:
3560                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3561                         ret = ANEG_FAILED;
3562                         break;
3563                 }
3564                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3565                                MR_LP_ADV_HALF_DUPLEX |
3566                                MR_LP_ADV_SYM_PAUSE |
3567                                MR_LP_ADV_ASYM_PAUSE |
3568                                MR_LP_ADV_REMOTE_FAULT1 |
3569                                MR_LP_ADV_REMOTE_FAULT2 |
3570                                MR_LP_ADV_NEXT_PAGE |
3571                                MR_TOGGLE_RX |
3572                                MR_NP_RX);
3573                 if (ap->rxconfig & ANEG_CFG_FD)
3574                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3575                 if (ap->rxconfig & ANEG_CFG_HD)
3576                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3577                 if (ap->rxconfig & ANEG_CFG_PS1)
3578                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3579                 if (ap->rxconfig & ANEG_CFG_PS2)
3580                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3581                 if (ap->rxconfig & ANEG_CFG_RF1)
3582                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3583                 if (ap->rxconfig & ANEG_CFG_RF2)
3584                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3585                 if (ap->rxconfig & ANEG_CFG_NP)
3586                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3587
3588                 ap->link_time = ap->cur_time;
3589
3590                 ap->flags ^= (MR_TOGGLE_TX);
3591                 if (ap->rxconfig & 0x0008)
3592                         ap->flags |= MR_TOGGLE_RX;
3593                 if (ap->rxconfig & ANEG_CFG_NP)
3594                         ap->flags |= MR_NP_RX;
3595                 ap->flags |= MR_PAGE_RX;
3596
3597                 ap->state = ANEG_STATE_COMPLETE_ACK;
3598                 ret = ANEG_TIMER_ENAB;
3599                 break;
3600
3601         case ANEG_STATE_COMPLETE_ACK:
3602                 if (ap->ability_match != 0 &&
3603                     ap->rxconfig == 0) {
3604                         ap->state = ANEG_STATE_AN_ENABLE;
3605                         break;
3606                 }
3607                 delta = ap->cur_time - ap->link_time;
3608                 if (delta > ANEG_STATE_SETTLE_TIME) {
3609                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3610                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3611                         } else {
3612                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3613                                     !(ap->flags & MR_NP_RX)) {
3614                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3615                                 } else {
3616                                         ret = ANEG_FAILED;
3617                                 }
3618                         }
3619                 }
3620                 break;
3621
3622         case ANEG_STATE_IDLE_DETECT_INIT:
3623                 ap->link_time = ap->cur_time;
3624                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3625                 tw32_f(MAC_MODE, tp->mac_mode);
3626                 udelay(40);
3627
3628                 ap->state = ANEG_STATE_IDLE_DETECT;
3629                 ret = ANEG_TIMER_ENAB;
3630                 break;
3631
3632         case ANEG_STATE_IDLE_DETECT:
3633                 if (ap->ability_match != 0 &&
3634                     ap->rxconfig == 0) {
3635                         ap->state = ANEG_STATE_AN_ENABLE;
3636                         break;
3637                 }
3638                 delta = ap->cur_time - ap->link_time;
3639                 if (delta > ANEG_STATE_SETTLE_TIME) {
3640                         /* XXX another gem from the Broadcom driver :( */
3641                         ap->state = ANEG_STATE_LINK_OK;
3642                 }
3643                 break;
3644
3645         case ANEG_STATE_LINK_OK:
3646                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3647                 ret = ANEG_DONE;
3648                 break;
3649
3650         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3651                 /* ??? unimplemented */
3652                 break;
3653
3654         case ANEG_STATE_NEXT_PAGE_WAIT:
3655                 /* ??? unimplemented */
3656                 break;
3657
3658         default:
3659                 ret = ANEG_FAILED;
3660                 break;
3661         }
3662
3663         return ret;
3664 }
3665
3666 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3667 {
3668         int res = 0;
3669         struct tg3_fiber_aneginfo aninfo;
3670         int status = ANEG_FAILED;
3671         unsigned int tick;
3672         u32 tmp;
3673
3674         tw32_f(MAC_TX_AUTO_NEG, 0);
3675
3676         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3677         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3678         udelay(40);
3679
3680         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3681         udelay(40);
3682
3683         memset(&aninfo, 0, sizeof(aninfo));
3684         aninfo.flags |= MR_AN_ENABLE;
3685         aninfo.state = ANEG_STATE_UNKNOWN;
3686         aninfo.cur_time = 0;
3687         tick = 0;
3688         while (++tick < 195000) {
3689                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3690                 if (status == ANEG_DONE || status == ANEG_FAILED)
3691                         break;
3692
3693                 udelay(1);
3694         }
3695
3696         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3697         tw32_f(MAC_MODE, tp->mac_mode);
3698         udelay(40);
3699
3700         *txflags = aninfo.txconfig;
3701         *rxflags = aninfo.flags;
3702
3703         if (status == ANEG_DONE &&
3704             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3705                              MR_LP_ADV_FULL_DUPLEX)))
3706                 res = 1;
3707
3708         return res;
3709 }
3710
3711 static void tg3_init_bcm8002(struct tg3 *tp)
3712 {
3713         u32 mac_status = tr32(MAC_STATUS);
3714         int i;
3715
3716         /* Reset when initting first time or we have a link. */
3717         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3718             !(mac_status & MAC_STATUS_PCS_SYNCED))
3719                 return;
3720
3721         /* Set PLL lock range. */
3722         tg3_writephy(tp, 0x16, 0x8007);
3723
3724         /* SW reset */
3725         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3726
3727         /* Wait for reset to complete. */
3728         /* XXX schedule_timeout() ... */
3729         for (i = 0; i < 500; i++)
3730                 udelay(10);
3731
3732         /* Config mode; select PMA/Ch 1 regs. */
3733         tg3_writephy(tp, 0x10, 0x8411);
3734
3735         /* Enable auto-lock and comdet, select txclk for tx. */
3736         tg3_writephy(tp, 0x11, 0x0a10);
3737
3738         tg3_writephy(tp, 0x18, 0x00a0);
3739         tg3_writephy(tp, 0x16, 0x41ff);
3740
3741         /* Assert and deassert POR. */
3742         tg3_writephy(tp, 0x13, 0x0400);
3743         udelay(40);
3744         tg3_writephy(tp, 0x13, 0x0000);
3745
3746         tg3_writephy(tp, 0x11, 0x0a50);
3747         udelay(40);
3748         tg3_writephy(tp, 0x11, 0x0a10);
3749
3750         /* Wait for signal to stabilize */
3751         /* XXX schedule_timeout() ... */
3752         for (i = 0; i < 15000; i++)
3753                 udelay(10);
3754
3755         /* Deselect the channel register so we can read the PHYID
3756          * later.
3757          */
3758         tg3_writephy(tp, 0x10, 0x8011);
3759 }
3760
3761 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3762 {
3763         u16 flowctrl;
3764         u32 sg_dig_ctrl, sg_dig_status;
3765         u32 serdes_cfg, expected_sg_dig_ctrl;
3766         int workaround, port_a;
3767         int current_link_up;
3768
3769         serdes_cfg = 0;
3770         expected_sg_dig_ctrl = 0;
3771         workaround = 0;
3772         port_a = 1;
3773         current_link_up = 0;
3774
3775         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3776             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3777                 workaround = 1;
3778                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3779                         port_a = 0;
3780
3781                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3782                 /* preserve bits 20-23 for voltage regulator */
3783                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3784         }
3785
3786         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3787
3788         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3789                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3790                         if (workaround) {
3791                                 u32 val = serdes_cfg;
3792
3793                                 if (port_a)
3794                                         val |= 0xc010000;
3795                                 else
3796                                         val |= 0x4010000;
3797                                 tw32_f(MAC_SERDES_CFG, val);
3798                         }
3799
3800                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3801                 }
3802                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3803                         tg3_setup_flow_control(tp, 0, 0);
3804                         current_link_up = 1;
3805                 }
3806                 goto out;
3807         }
3808
3809         /* Want auto-negotiation.  */
3810         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3811
3812         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3813         if (flowctrl & ADVERTISE_1000XPAUSE)
3814                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3815         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3816                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3817
3818         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3819                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3820                     tp->serdes_counter &&
3821                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3822                                     MAC_STATUS_RCVD_CFG)) ==
3823                      MAC_STATUS_PCS_SYNCED)) {
3824                         tp->serdes_counter--;
3825                         current_link_up = 1;
3826                         goto out;
3827                 }
3828 restart_autoneg:
3829                 if (workaround)
3830                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3831                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3832                 udelay(5);
3833                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3834
3835                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3836                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3837         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3838                                  MAC_STATUS_SIGNAL_DET)) {
3839                 sg_dig_status = tr32(SG_DIG_STATUS);
3840                 mac_status = tr32(MAC_STATUS);
3841
3842                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3843                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3844                         u32 local_adv = 0, remote_adv = 0;
3845
3846                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3847                                 local_adv |= ADVERTISE_1000XPAUSE;
3848                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3849                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3850
3851                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3852                                 remote_adv |= LPA_1000XPAUSE;
3853                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3854                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3855
3856                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3857                         current_link_up = 1;
3858                         tp->serdes_counter = 0;
3859                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3860                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3861                         if (tp->serdes_counter)
3862                                 tp->serdes_counter--;
3863                         else {
3864                                 if (workaround) {
3865                                         u32 val = serdes_cfg;
3866
3867                                         if (port_a)
3868                                                 val |= 0xc010000;
3869                                         else
3870                                                 val |= 0x4010000;
3871
3872                                         tw32_f(MAC_SERDES_CFG, val);
3873                                 }
3874
3875                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3876                                 udelay(40);
3877
3878                                 /* Link parallel detection - link is up */
3879                                 /* only if we have PCS_SYNC and not */
3880                                 /* receiving config code words */
3881                                 mac_status = tr32(MAC_STATUS);
3882                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3883                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3884                                         tg3_setup_flow_control(tp, 0, 0);
3885                                         current_link_up = 1;
3886                                         tp->tg3_flags2 |=
3887                                                 TG3_FLG2_PARALLEL_DETECT;
3888                                         tp->serdes_counter =
3889                                                 SERDES_PARALLEL_DET_TIMEOUT;
3890                                 } else
3891                                         goto restart_autoneg;
3892                         }
3893                 }
3894         } else {
3895                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3896                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3897         }
3898
3899 out:
3900         return current_link_up;
3901 }
3902
3903 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3904 {
3905         int current_link_up = 0;
3906
3907         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3908                 goto out;
3909
3910         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3911                 u32 txflags, rxflags;
3912                 int i;
3913
3914                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3915                         u32 local_adv = 0, remote_adv = 0;
3916
3917                         if (txflags & ANEG_CFG_PS1)
3918                                 local_adv |= ADVERTISE_1000XPAUSE;
3919                         if (txflags & ANEG_CFG_PS2)
3920                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3921
3922                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3923                                 remote_adv |= LPA_1000XPAUSE;
3924                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3925                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3926
3927                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3928
3929                         current_link_up = 1;
3930                 }
3931                 for (i = 0; i < 30; i++) {
3932                         udelay(20);
3933                         tw32_f(MAC_STATUS,
3934                                (MAC_STATUS_SYNC_CHANGED |
3935                                 MAC_STATUS_CFG_CHANGED));
3936                         udelay(40);
3937                         if ((tr32(MAC_STATUS) &
3938                              (MAC_STATUS_SYNC_CHANGED |
3939                               MAC_STATUS_CFG_CHANGED)) == 0)
3940                                 break;
3941                 }
3942
3943                 mac_status = tr32(MAC_STATUS);
3944                 if (current_link_up == 0 &&
3945                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3946                     !(mac_status & MAC_STATUS_RCVD_CFG))
3947                         current_link_up = 1;
3948         } else {
3949                 tg3_setup_flow_control(tp, 0, 0);
3950
3951                 /* Forcing 1000FD link up. */
3952                 current_link_up = 1;
3953
3954                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3955                 udelay(40);
3956
3957                 tw32_f(MAC_MODE, tp->mac_mode);
3958                 udelay(40);
3959         }
3960
3961 out:
3962         return current_link_up;
3963 }
3964
3965 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3966 {
3967         u32 orig_pause_cfg;
3968         u16 orig_active_speed;
3969         u8 orig_active_duplex;
3970         u32 mac_status;
3971         int current_link_up;
3972         int i;
3973
3974         orig_pause_cfg = tp->link_config.active_flowctrl;
3975         orig_active_speed = tp->link_config.active_speed;
3976         orig_active_duplex = tp->link_config.active_duplex;
3977
3978         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3979             netif_carrier_ok(tp->dev) &&
3980             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3981                 mac_status = tr32(MAC_STATUS);
3982                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3983                                MAC_STATUS_SIGNAL_DET |
3984                                MAC_STATUS_CFG_CHANGED |
3985                                MAC_STATUS_RCVD_CFG);
3986                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3987                                    MAC_STATUS_SIGNAL_DET)) {
3988                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3989                                             MAC_STATUS_CFG_CHANGED));
3990                         return 0;
3991                 }
3992         }
3993
3994         tw32_f(MAC_TX_AUTO_NEG, 0);
3995
3996         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3997         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3998         tw32_f(MAC_MODE, tp->mac_mode);
3999         udelay(40);
4000
4001         if (tp->phy_id == TG3_PHY_ID_BCM8002)
4002                 tg3_init_bcm8002(tp);
4003
4004         /* Enable link change event even when serdes polling.  */
4005         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4006         udelay(40);
4007
4008         current_link_up = 0;
4009         mac_status = tr32(MAC_STATUS);
4010
4011         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
4012                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4013         else
4014                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4015
4016         tp->napi[0].hw_status->status =
4017                 (SD_STATUS_UPDATED |
4018                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4019
4020         for (i = 0; i < 100; i++) {
4021                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4022                                     MAC_STATUS_CFG_CHANGED));
4023                 udelay(5);
4024                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4025                                          MAC_STATUS_CFG_CHANGED |
4026                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4027                         break;
4028         }
4029
4030         mac_status = tr32(MAC_STATUS);
4031         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4032                 current_link_up = 0;
4033                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4034                     tp->serdes_counter == 0) {
4035                         tw32_f(MAC_MODE, (tp->mac_mode |
4036                                           MAC_MODE_SEND_CONFIGS));
4037                         udelay(1);
4038                         tw32_f(MAC_MODE, tp->mac_mode);
4039                 }
4040         }
4041
4042         if (current_link_up == 1) {
4043                 tp->link_config.active_speed = SPEED_1000;
4044                 tp->link_config.active_duplex = DUPLEX_FULL;
4045                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4046                                     LED_CTRL_LNKLED_OVERRIDE |
4047                                     LED_CTRL_1000MBPS_ON));
4048         } else {
4049                 tp->link_config.active_speed = SPEED_INVALID;
4050                 tp->link_config.active_duplex = DUPLEX_INVALID;
4051                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4052                                     LED_CTRL_LNKLED_OVERRIDE |
4053                                     LED_CTRL_TRAFFIC_OVERRIDE));
4054         }
4055
4056         if (current_link_up != netif_carrier_ok(tp->dev)) {
4057                 if (current_link_up)
4058                         netif_carrier_on(tp->dev);
4059                 else
4060                         netif_carrier_off(tp->dev);
4061                 tg3_link_report(tp);
4062         } else {
4063                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4064                 if (orig_pause_cfg != now_pause_cfg ||
4065                     orig_active_speed != tp->link_config.active_speed ||
4066                     orig_active_duplex != tp->link_config.active_duplex)
4067                         tg3_link_report(tp);
4068         }
4069
4070         return 0;
4071 }
4072
4073 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4074 {
4075         int current_link_up, err = 0;
4076         u32 bmsr, bmcr;
4077         u16 current_speed;
4078         u8 current_duplex;
4079         u32 local_adv, remote_adv;
4080
4081         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4082         tw32_f(MAC_MODE, tp->mac_mode);
4083         udelay(40);
4084
4085         tw32(MAC_EVENT, 0);
4086
4087         tw32_f(MAC_STATUS,
4088              (MAC_STATUS_SYNC_CHANGED |
4089               MAC_STATUS_CFG_CHANGED |
4090               MAC_STATUS_MI_COMPLETION |
4091               MAC_STATUS_LNKSTATE_CHANGED));
4092         udelay(40);
4093
4094         if (force_reset)
4095                 tg3_phy_reset(tp);
4096
4097         current_link_up = 0;
4098         current_speed = SPEED_INVALID;
4099         current_duplex = DUPLEX_INVALID;
4100
4101         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4102         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4103         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4104                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4105                         bmsr |= BMSR_LSTATUS;
4106                 else
4107                         bmsr &= ~BMSR_LSTATUS;
4108         }
4109
4110         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4111
4112         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4113             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4114                 /* do nothing, just check for link up at the end */
4115         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4116                 u32 adv, new_adv;
4117
4118                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4119                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4120                                   ADVERTISE_1000XPAUSE |
4121                                   ADVERTISE_1000XPSE_ASYM |
4122                                   ADVERTISE_SLCT);
4123
4124                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4125
4126                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4127                         new_adv |= ADVERTISE_1000XHALF;
4128                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4129                         new_adv |= ADVERTISE_1000XFULL;
4130
4131                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4132                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4133                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4134                         tg3_writephy(tp, MII_BMCR, bmcr);
4135
4136                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4137                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4138                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4139
4140                         return err;
4141                 }
4142         } else {
4143                 u32 new_bmcr;
4144
4145                 bmcr &= ~BMCR_SPEED1000;
4146                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4147
4148                 if (tp->link_config.duplex == DUPLEX_FULL)
4149                         new_bmcr |= BMCR_FULLDPLX;
4150
4151                 if (new_bmcr != bmcr) {
4152                         /* BMCR_SPEED1000 is a reserved bit that needs
4153                          * to be set on write.
4154                          */
4155                         new_bmcr |= BMCR_SPEED1000;
4156
4157                         /* Force a linkdown */
4158                         if (netif_carrier_ok(tp->dev)) {
4159                                 u32 adv;
4160
4161                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4162                                 adv &= ~(ADVERTISE_1000XFULL |
4163                                          ADVERTISE_1000XHALF |
4164                                          ADVERTISE_SLCT);
4165                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4166                                 tg3_writephy(tp, MII_BMCR, bmcr |
4167                                                            BMCR_ANRESTART |
4168                                                            BMCR_ANENABLE);
4169                                 udelay(10);
4170                                 netif_carrier_off(tp->dev);
4171                         }
4172                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4173                         bmcr = new_bmcr;
4174                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4175                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4176                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4177                             ASIC_REV_5714) {
4178                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4179                                         bmsr |= BMSR_LSTATUS;
4180                                 else
4181                                         bmsr &= ~BMSR_LSTATUS;
4182                         }
4183                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4184                 }
4185         }
4186
4187         if (bmsr & BMSR_LSTATUS) {
4188                 current_speed = SPEED_1000;
4189                 current_link_up = 1;
4190                 if (bmcr & BMCR_FULLDPLX)
4191                         current_duplex = DUPLEX_FULL;
4192                 else
4193                         current_duplex = DUPLEX_HALF;
4194
4195                 local_adv = 0;
4196                 remote_adv = 0;
4197
4198                 if (bmcr & BMCR_ANENABLE) {
4199                         u32 common;
4200
4201                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4202                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4203                         common = local_adv & remote_adv;
4204                         if (common & (ADVERTISE_1000XHALF |
4205                                       ADVERTISE_1000XFULL)) {
4206                                 if (common & ADVERTISE_1000XFULL)
4207                                         current_duplex = DUPLEX_FULL;
4208                                 else
4209                                         current_duplex = DUPLEX_HALF;
4210                         } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4211                                 /* Link is up via parallel detect */
4212                         } else {
4213                                 current_link_up = 0;
4214                         }
4215                 }
4216         }
4217
4218         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4219                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4220
4221         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4222         if (tp->link_config.active_duplex == DUPLEX_HALF)
4223                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4224
4225         tw32_f(MAC_MODE, tp->mac_mode);
4226         udelay(40);
4227
4228         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4229
4230         tp->link_config.active_speed = current_speed;
4231         tp->link_config.active_duplex = current_duplex;
4232
4233         if (current_link_up != netif_carrier_ok(tp->dev)) {
4234                 if (current_link_up)
4235                         netif_carrier_on(tp->dev);
4236                 else {
4237                         netif_carrier_off(tp->dev);
4238                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4239                 }
4240                 tg3_link_report(tp);
4241         }
4242         return err;
4243 }
4244
4245 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4246 {
4247         if (tp->serdes_counter) {
4248                 /* Give autoneg time to complete. */
4249                 tp->serdes_counter--;
4250                 return;
4251         }
4252
4253         if (!netif_carrier_ok(tp->dev) &&
4254             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4255                 u32 bmcr;
4256
4257                 tg3_readphy(tp, MII_BMCR, &bmcr);
4258                 if (bmcr & BMCR_ANENABLE) {
4259                         u32 phy1, phy2;
4260
4261                         /* Select shadow register 0x1f */
4262                         tg3_writephy(tp, 0x1c, 0x7c00);
4263                         tg3_readphy(tp, 0x1c, &phy1);
4264
4265                         /* Select expansion interrupt status register */
4266                         tg3_writephy(tp, 0x17, 0x0f01);
4267                         tg3_readphy(tp, 0x15, &phy2);
4268                         tg3_readphy(tp, 0x15, &phy2);
4269
4270                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4271                                 /* We have signal detect and not receiving
4272                                  * config code words, link is up by parallel
4273                                  * detection.
4274                                  */
4275
4276                                 bmcr &= ~BMCR_ANENABLE;
4277                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4278                                 tg3_writephy(tp, MII_BMCR, bmcr);
4279                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4280                         }
4281                 }
4282         } else if (netif_carrier_ok(tp->dev) &&
4283                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4284                    (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4285                 u32 phy2;
4286
4287                 /* Select expansion interrupt status register */
4288                 tg3_writephy(tp, 0x17, 0x0f01);
4289                 tg3_readphy(tp, 0x15, &phy2);
4290                 if (phy2 & 0x20) {
4291                         u32 bmcr;
4292
4293                         /* Config code words received, turn on autoneg. */
4294                         tg3_readphy(tp, MII_BMCR, &bmcr);
4295                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4296
4297                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4298
4299                 }
4300         }
4301 }
4302
4303 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4304 {
4305         int err;
4306
4307         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
4308                 err = tg3_setup_fiber_phy(tp, force_reset);
4309         else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
4310                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4311         else
4312                 err = tg3_setup_copper_phy(tp, force_reset);
4313
4314         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4315                 u32 val, scale;
4316
4317                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4318                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4319                         scale = 65;
4320                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4321                         scale = 6;
4322                 else
4323                         scale = 12;
4324
4325                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4326                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4327                 tw32(GRC_MISC_CFG, val);
4328         }
4329
4330         if (tp->link_config.active_speed == SPEED_1000 &&
4331             tp->link_config.active_duplex == DUPLEX_HALF)
4332                 tw32(MAC_TX_LENGTHS,
4333                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4334                       (6 << TX_LENGTHS_IPG_SHIFT) |
4335                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4336         else
4337                 tw32(MAC_TX_LENGTHS,
4338                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4339                       (6 << TX_LENGTHS_IPG_SHIFT) |
4340                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4341
4342         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4343                 if (netif_carrier_ok(tp->dev)) {
4344                         tw32(HOSTCC_STAT_COAL_TICKS,
4345                              tp->coal.stats_block_coalesce_usecs);
4346                 } else {
4347                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4348                 }
4349         }
4350
4351         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4352                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4353                 if (!netif_carrier_ok(tp->dev))
4354                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4355                               tp->pwrmgmt_thresh;
4356                 else
4357                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4358                 tw32(PCIE_PWR_MGMT_THRESH, val);
4359         }
4360
4361         return err;
4362 }
4363
4364 /* This is called whenever we suspect that the system chipset is re-
4365  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4366  * is bogus tx completions. We try to recover by setting the
4367  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4368  * in the workqueue.
4369  */
4370 static void tg3_tx_recover(struct tg3 *tp)
4371 {
4372         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4373                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4374
4375         netdev_warn(tp->dev,
4376                     "The system may be re-ordering memory-mapped I/O "
4377                     "cycles to the network device, attempting to recover. "
4378                     "Please report the problem to the driver maintainer "
4379                     "and include system chipset information.\n");
4380
4381         spin_lock(&tp->lock);
4382         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4383         spin_unlock(&tp->lock);
4384 }
4385
4386 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4387 {
4388         smp_mb();
4389         return tnapi->tx_pending -
4390                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4391 }
4392
4393 /* Tigon3 never reports partial packet sends.  So we do not
4394  * need special logic to handle SKBs that have not had all
4395  * of their frags sent yet, like SunGEM does.
4396  */
4397 static void tg3_tx(struct tg3_napi *tnapi)
4398 {
4399         struct tg3 *tp = tnapi->tp;
4400         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4401         u32 sw_idx = tnapi->tx_cons;
4402         struct netdev_queue *txq;
4403         int index = tnapi - tp->napi;
4404
4405         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4406                 index--;
4407
4408         txq = netdev_get_tx_queue(tp->dev, index);
4409
4410         while (sw_idx != hw_idx) {
4411                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4412                 struct sk_buff *skb = ri->skb;
4413                 int i, tx_bug = 0;
4414
4415                 if (unlikely(skb == NULL)) {
4416                         tg3_tx_recover(tp);
4417                         return;
4418                 }
4419
4420                 pci_unmap_single(tp->pdev,
4421                                  dma_unmap_addr(ri, mapping),
4422                                  skb_headlen(skb),
4423                                  PCI_DMA_TODEVICE);
4424
4425                 ri->skb = NULL;
4426
4427                 sw_idx = NEXT_TX(sw_idx);
4428
4429                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4430                         ri = &tnapi->tx_buffers[sw_idx];
4431                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4432                                 tx_bug = 1;
4433
4434                         pci_unmap_page(tp->pdev,
4435                                        dma_unmap_addr(ri, mapping),
4436                                        skb_shinfo(skb)->frags[i].size,
4437                                        PCI_DMA_TODEVICE);
4438                         sw_idx = NEXT_TX(sw_idx);
4439                 }
4440
4441                 dev_kfree_skb(skb);
4442
4443                 if (unlikely(tx_bug)) {
4444                         tg3_tx_recover(tp);
4445                         return;
4446                 }
4447         }
4448
4449         tnapi->tx_cons = sw_idx;
4450
4451         /* Need to make the tx_cons update visible to tg3_start_xmit()
4452          * before checking for netif_queue_stopped().  Without the
4453          * memory barrier, there is a small possibility that tg3_start_xmit()
4454          * will miss it and cause the queue to be stopped forever.
4455          */
4456         smp_mb();
4457
4458         if (unlikely(netif_tx_queue_stopped(txq) &&
4459                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4460                 __netif_tx_lock(txq, smp_processor_id());
4461                 if (netif_tx_queue_stopped(txq) &&
4462                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4463                         netif_tx_wake_queue(txq);
4464                 __netif_tx_unlock(txq);
4465         }
4466 }
4467
4468 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4469 {
4470         if (!ri->skb)
4471                 return;
4472
4473         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4474                          map_sz, PCI_DMA_FROMDEVICE);
4475         dev_kfree_skb_any(ri->skb);
4476         ri->skb = NULL;
4477 }
4478
4479 /* Returns size of skb allocated or < 0 on error.
4480  *
4481  * We only need to fill in the address because the other members
4482  * of the RX descriptor are invariant, see tg3_init_rings.
4483  *
4484  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4485  * posting buffers we only dirty the first cache line of the RX
4486  * descriptor (containing the address).  Whereas for the RX status
4487  * buffers the cpu only reads the last cacheline of the RX descriptor
4488  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4489  */
4490 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4491                             u32 opaque_key, u32 dest_idx_unmasked)
4492 {
4493         struct tg3_rx_buffer_desc *desc;
4494         struct ring_info *map, *src_map;
4495         struct sk_buff *skb;
4496         dma_addr_t mapping;
4497         int skb_size, dest_idx;
4498
4499         src_map = NULL;
4500         switch (opaque_key) {
4501         case RXD_OPAQUE_RING_STD:
4502                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4503                 desc = &tpr->rx_std[dest_idx];
4504                 map = &tpr->rx_std_buffers[dest_idx];
4505                 skb_size = tp->rx_pkt_map_sz;
4506                 break;
4507
4508         case RXD_OPAQUE_RING_JUMBO:
4509                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4510                 desc = &tpr->rx_jmb[dest_idx].std;
4511                 map = &tpr->rx_jmb_buffers[dest_idx];
4512                 skb_size = TG3_RX_JMB_MAP_SZ;
4513                 break;
4514
4515         default:
4516                 return -EINVAL;
4517         }
4518
4519         /* Do not overwrite any of the map or rp information
4520          * until we are sure we can commit to a new buffer.
4521          *
4522          * Callers depend upon this behavior and assume that
4523          * we leave everything unchanged if we fail.
4524          */
4525         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4526         if (skb == NULL)
4527                 return -ENOMEM;
4528
4529         skb_reserve(skb, tp->rx_offset);
4530
4531         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4532                                  PCI_DMA_FROMDEVICE);
4533         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4534                 dev_kfree_skb(skb);
4535                 return -EIO;
4536         }
4537
4538         map->skb = skb;
4539         dma_unmap_addr_set(map, mapping, mapping);
4540
4541         desc->addr_hi = ((u64)mapping >> 32);
4542         desc->addr_lo = ((u64)mapping & 0xffffffff);
4543
4544         return skb_size;
4545 }
4546
4547 /* We only need to move over in the address because the other
4548  * members of the RX descriptor are invariant.  See notes above
4549  * tg3_alloc_rx_skb for full details.
4550  */
4551 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4552                            struct tg3_rx_prodring_set *dpr,
4553                            u32 opaque_key, int src_idx,
4554                            u32 dest_idx_unmasked)
4555 {
4556         struct tg3 *tp = tnapi->tp;
4557         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4558         struct ring_info *src_map, *dest_map;
4559         struct tg3_rx_prodring_set *spr = &tp->prodring[0];
4560         int dest_idx;
4561
4562         switch (opaque_key) {
4563         case RXD_OPAQUE_RING_STD:
4564                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4565                 dest_desc = &dpr->rx_std[dest_idx];
4566                 dest_map = &dpr->rx_std_buffers[dest_idx];
4567                 src_desc = &spr->rx_std[src_idx];
4568                 src_map = &spr->rx_std_buffers[src_idx];
4569                 break;
4570
4571         case RXD_OPAQUE_RING_JUMBO:
4572                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4573                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4574                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4575                 src_desc = &spr->rx_jmb[src_idx].std;
4576                 src_map = &spr->rx_jmb_buffers[src_idx];
4577                 break;
4578
4579         default:
4580                 return;
4581         }
4582
4583         dest_map->skb = src_map->skb;
4584         dma_unmap_addr_set(dest_map, mapping,
4585                            dma_unmap_addr(src_map, mapping));
4586         dest_desc->addr_hi = src_desc->addr_hi;
4587         dest_desc->addr_lo = src_desc->addr_lo;
4588
4589         /* Ensure that the update to the skb happens after the physical
4590          * addresses have been transferred to the new BD location.
4591          */
4592         smp_wmb();
4593
4594         src_map->skb = NULL;
4595 }
4596
4597 /* The RX ring scheme is composed of multiple rings which post fresh
4598  * buffers to the chip, and one special ring the chip uses to report
4599  * status back to the host.
4600  *
4601  * The special ring reports the status of received packets to the
4602  * host.  The chip does not write into the original descriptor the
4603  * RX buffer was obtained from.  The chip simply takes the original
4604  * descriptor as provided by the host, updates the status and length
4605  * field, then writes this into the next status ring entry.
4606  *
4607  * Each ring the host uses to post buffers to the chip is described
4608  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4609  * it is first placed into the on-chip ram.  When the packet's length
4610  * is known, it walks down the TG3_BDINFO entries to select the ring.
4611  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4612  * which is within the range of the new packet's length is chosen.
4613  *
4614  * The "separate ring for rx status" scheme may sound queer, but it makes
4615  * sense from a cache coherency perspective.  If only the host writes
4616  * to the buffer post rings, and only the chip writes to the rx status
4617  * rings, then cache lines never move beyond shared-modified state.
4618  * If both the host and chip were to write into the same ring, cache line
4619  * eviction could occur since both entities want it in an exclusive state.
4620  */
4621 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4622 {
4623         struct tg3 *tp = tnapi->tp;
4624         u32 work_mask, rx_std_posted = 0;
4625         u32 std_prod_idx, jmb_prod_idx;
4626         u32 sw_idx = tnapi->rx_rcb_ptr;
4627         u16 hw_idx;
4628         int received;
4629         struct tg3_rx_prodring_set *tpr = tnapi->prodring;
4630
4631         hw_idx = *(tnapi->rx_rcb_prod_idx);
4632         /*
4633          * We need to order the read of hw_idx and the read of
4634          * the opaque cookie.
4635          */
4636         rmb();
4637         work_mask = 0;
4638         received = 0;
4639         std_prod_idx = tpr->rx_std_prod_idx;
4640         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4641         while (sw_idx != hw_idx && budget > 0) {
4642                 struct ring_info *ri;
4643                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4644                 unsigned int len;
4645                 struct sk_buff *skb;
4646                 dma_addr_t dma_addr;
4647                 u32 opaque_key, desc_idx, *post_ptr;
4648                 bool hw_vlan __maybe_unused = false;
4649                 u16 vtag __maybe_unused = 0;
4650
4651                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4652                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4653                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4654                         ri = &tp->prodring[0].rx_std_buffers[desc_idx];
4655                         dma_addr = dma_unmap_addr(ri, mapping);
4656                         skb = ri->skb;
4657                         post_ptr = &std_prod_idx;
4658                         rx_std_posted++;
4659                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4660                         ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
4661                         dma_addr = dma_unmap_addr(ri, mapping);
4662                         skb = ri->skb;
4663                         post_ptr = &jmb_prod_idx;
4664                 } else
4665                         goto next_pkt_nopost;
4666
4667                 work_mask |= opaque_key;
4668
4669                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4670                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4671                 drop_it:
4672                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4673                                        desc_idx, *post_ptr);
4674                 drop_it_no_recycle:
4675                         /* Other statistics kept track of by card. */
4676                         tp->net_stats.rx_dropped++;
4677                         goto next_pkt;
4678                 }
4679
4680                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4681                       ETH_FCS_LEN;
4682
4683                 if (len > TG3_RX_COPY_THRESH(tp)) {
4684                         int skb_size;
4685
4686                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4687                                                     *post_ptr);
4688                         if (skb_size < 0)
4689                                 goto drop_it;
4690
4691                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4692                                          PCI_DMA_FROMDEVICE);
4693
4694                         /* Ensure that the update to the skb happens
4695                          * after the usage of the old DMA mapping.
4696                          */
4697                         smp_wmb();
4698
4699                         ri->skb = NULL;
4700
4701                         skb_put(skb, len);
4702                 } else {
4703                         struct sk_buff *copy_skb;
4704
4705                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4706                                        desc_idx, *post_ptr);
4707
4708                         copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
4709                                                     TG3_RAW_IP_ALIGN);
4710                         if (copy_skb == NULL)
4711                                 goto drop_it_no_recycle;
4712
4713                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
4714                         skb_put(copy_skb, len);
4715                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4716                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4717                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4718
4719                         /* We'll reuse the original ring buffer. */
4720                         skb = copy_skb;
4721                 }
4722
4723                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4724                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4725                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4726                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4727                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4728                 else
4729                         skb->ip_summed = CHECKSUM_NONE;
4730
4731                 skb->protocol = eth_type_trans(skb, tp->dev);
4732
4733                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4734                     skb->protocol != htons(ETH_P_8021Q)) {
4735                         dev_kfree_skb(skb);
4736                         goto next_pkt;
4737                 }
4738
4739                 if (desc->type_flags & RXD_FLAG_VLAN &&
4740                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
4741                         vtag = desc->err_vlan & RXD_VLAN_MASK;
4742 #if TG3_VLAN_TAG_USED
4743                         if (tp->vlgrp)
4744                                 hw_vlan = true;
4745                         else
4746 #endif
4747                         {
4748                                 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
4749                                                     __skb_push(skb, VLAN_HLEN);
4750
4751                                 memmove(ve, skb->data + VLAN_HLEN,
4752                                         ETH_ALEN * 2);
4753                                 ve->h_vlan_proto = htons(ETH_P_8021Q);
4754                                 ve->h_vlan_TCI = htons(vtag);
4755                         }
4756                 }
4757
4758 #if TG3_VLAN_TAG_USED
4759                 if (hw_vlan)
4760                         vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
4761                 else
4762 #endif
4763                         napi_gro_receive(&tnapi->napi, skb);
4764
4765                 received++;
4766                 budget--;
4767
4768 next_pkt:
4769                 (*post_ptr)++;
4770
4771                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4772                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4773                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4774                                      tpr->rx_std_prod_idx);
4775                         work_mask &= ~RXD_OPAQUE_RING_STD;
4776                         rx_std_posted = 0;
4777                 }
4778 next_pkt_nopost:
4779                 sw_idx++;
4780                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4781
4782                 /* Refresh hw_idx to see if there is new work */
4783                 if (sw_idx == hw_idx) {
4784                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4785                         rmb();
4786                 }
4787         }
4788
4789         /* ACK the status ring. */
4790         tnapi->rx_rcb_ptr = sw_idx;
4791         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4792
4793         /* Refill RX ring(s). */
4794         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4795                 if (work_mask & RXD_OPAQUE_RING_STD) {
4796                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4797                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4798                                      tpr->rx_std_prod_idx);
4799                 }
4800                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4801                         tpr->rx_jmb_prod_idx = jmb_prod_idx %
4802                                                TG3_RX_JUMBO_RING_SIZE;
4803                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4804                                      tpr->rx_jmb_prod_idx);
4805                 }
4806                 mmiowb();
4807         } else if (work_mask) {
4808                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4809                  * updated before the producer indices can be updated.
4810                  */
4811                 smp_wmb();
4812
4813                 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4814                 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4815
4816                 if (tnapi != &tp->napi[1])
4817                         napi_schedule(&tp->napi[1].napi);
4818         }
4819
4820         return received;
4821 }
4822
4823 static void tg3_poll_link(struct tg3 *tp)
4824 {
4825         /* handle link change and other phy events */
4826         if (!(tp->tg3_flags &
4827               (TG3_FLAG_USE_LINKCHG_REG |
4828                TG3_FLAG_POLL_SERDES))) {
4829                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4830
4831                 if (sblk->status & SD_STATUS_LINK_CHG) {
4832                         sblk->status = SD_STATUS_UPDATED |
4833                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4834                         spin_lock(&tp->lock);
4835                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4836                                 tw32_f(MAC_STATUS,
4837                                      (MAC_STATUS_SYNC_CHANGED |
4838                                       MAC_STATUS_CFG_CHANGED |
4839                                       MAC_STATUS_MI_COMPLETION |
4840                                       MAC_STATUS_LNKSTATE_CHANGED));
4841                                 udelay(40);
4842                         } else
4843                                 tg3_setup_phy(tp, 0);
4844                         spin_unlock(&tp->lock);
4845                 }
4846         }
4847 }
4848
4849 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4850                                 struct tg3_rx_prodring_set *dpr,
4851                                 struct tg3_rx_prodring_set *spr)
4852 {
4853         u32 si, di, cpycnt, src_prod_idx;
4854         int i, err = 0;
4855
4856         while (1) {
4857                 src_prod_idx = spr->rx_std_prod_idx;
4858
4859                 /* Make sure updates to the rx_std_buffers[] entries and the
4860                  * standard producer index are seen in the correct order.
4861                  */
4862                 smp_rmb();
4863
4864                 if (spr->rx_std_cons_idx == src_prod_idx)
4865                         break;
4866
4867                 if (spr->rx_std_cons_idx < src_prod_idx)
4868                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4869                 else
4870                         cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4871
4872                 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4873
4874                 si = spr->rx_std_cons_idx;
4875                 di = dpr->rx_std_prod_idx;
4876
4877                 for (i = di; i < di + cpycnt; i++) {
4878                         if (dpr->rx_std_buffers[i].skb) {
4879                                 cpycnt = i - di;
4880                                 err = -ENOSPC;
4881                                 break;
4882                         }
4883                 }
4884
4885                 if (!cpycnt)
4886                         break;
4887
4888                 /* Ensure that updates to the rx_std_buffers ring and the
4889                  * shadowed hardware producer ring from tg3_recycle_skb() are
4890                  * ordered correctly WRT the skb check above.
4891                  */
4892                 smp_rmb();
4893
4894                 memcpy(&dpr->rx_std_buffers[di],
4895                        &spr->rx_std_buffers[si],
4896                        cpycnt * sizeof(struct ring_info));
4897
4898                 for (i = 0; i < cpycnt; i++, di++, si++) {
4899                         struct tg3_rx_buffer_desc *sbd, *dbd;
4900                         sbd = &spr->rx_std[si];
4901                         dbd = &dpr->rx_std[di];
4902                         dbd->addr_hi = sbd->addr_hi;
4903                         dbd->addr_lo = sbd->addr_lo;
4904                 }
4905
4906                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4907                                        TG3_RX_RING_SIZE;
4908                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4909                                        TG3_RX_RING_SIZE;
4910         }
4911
4912         while (1) {
4913                 src_prod_idx = spr->rx_jmb_prod_idx;
4914
4915                 /* Make sure updates to the rx_jmb_buffers[] entries and
4916                  * the jumbo producer index are seen in the correct order.
4917                  */
4918                 smp_rmb();
4919
4920                 if (spr->rx_jmb_cons_idx == src_prod_idx)
4921                         break;
4922
4923                 if (spr->rx_jmb_cons_idx < src_prod_idx)
4924                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4925                 else
4926                         cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4927
4928                 cpycnt = min(cpycnt,
4929                              TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4930
4931                 si = spr->rx_jmb_cons_idx;
4932                 di = dpr->rx_jmb_prod_idx;
4933
4934                 for (i = di; i < di + cpycnt; i++) {
4935                         if (dpr->rx_jmb_buffers[i].skb) {
4936                                 cpycnt = i - di;
4937                                 err = -ENOSPC;
4938                                 break;
4939                         }
4940                 }
4941
4942                 if (!cpycnt)
4943                         break;
4944
4945                 /* Ensure that updates to the rx_jmb_buffers ring and the
4946                  * shadowed hardware producer ring from tg3_recycle_skb() are
4947                  * ordered correctly WRT the skb check above.
4948                  */
4949                 smp_rmb();
4950
4951                 memcpy(&dpr->rx_jmb_buffers[di],
4952                        &spr->rx_jmb_buffers[si],
4953                        cpycnt * sizeof(struct ring_info));
4954
4955                 for (i = 0; i < cpycnt; i++, di++, si++) {
4956                         struct tg3_rx_buffer_desc *sbd, *dbd;
4957                         sbd = &spr->rx_jmb[si].std;
4958                         dbd = &dpr->rx_jmb[di].std;
4959                         dbd->addr_hi = sbd->addr_hi;
4960                         dbd->addr_lo = sbd->addr_lo;
4961                 }
4962
4963                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4964                                        TG3_RX_JUMBO_RING_SIZE;
4965                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4966                                        TG3_RX_JUMBO_RING_SIZE;
4967         }
4968
4969         return err;
4970 }
4971
4972 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4973 {
4974         struct tg3 *tp = tnapi->tp;
4975
4976         /* run TX completion thread */
4977         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4978                 tg3_tx(tnapi);
4979                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4980                         return work_done;
4981         }
4982
4983         /* run RX thread, within the bounds set by NAPI.
4984          * All RX "locking" is done by ensuring outside
4985          * code synchronizes with tg3->napi.poll()
4986          */
4987         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4988                 work_done += tg3_rx(tnapi, budget - work_done);
4989
4990         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4991                 struct tg3_rx_prodring_set *dpr = &tp->prodring[0];
4992                 int i, err = 0;
4993                 u32 std_prod_idx = dpr->rx_std_prod_idx;
4994                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
4995
4996                 for (i = 1; i < tp->irq_cnt; i++)
4997                         err |= tg3_rx_prodring_xfer(tp, dpr,
4998                                                     tp->napi[i].prodring);
4999
5000                 wmb();
5001
5002                 if (std_prod_idx != dpr->rx_std_prod_idx)
5003                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5004                                      dpr->rx_std_prod_idx);
5005
5006                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5007                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5008                                      dpr->rx_jmb_prod_idx);
5009
5010                 mmiowb();
5011
5012                 if (err)
5013                         tw32_f(HOSTCC_MODE, tp->coal_now);
5014         }
5015
5016         return work_done;
5017 }
5018
5019 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5020 {
5021         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5022         struct tg3 *tp = tnapi->tp;
5023         int work_done = 0;
5024         struct tg3_hw_status *sblk = tnapi->hw_status;
5025
5026         while (1) {
5027                 work_done = tg3_poll_work(tnapi, work_done, budget);
5028
5029                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5030                         goto tx_recovery;
5031
5032                 if (unlikely(work_done >= budget))
5033                         break;
5034
5035                 /* tp->last_tag is used in tg3_int_reenable() below
5036                  * to tell the hw how much work has been processed,
5037                  * so we must read it before checking for more work.
5038                  */
5039                 tnapi->last_tag = sblk->status_tag;
5040                 tnapi->last_irq_tag = tnapi->last_tag;
5041                 rmb();
5042
5043                 /* check for RX/TX work to do */
5044                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5045                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5046                         napi_complete(napi);
5047                         /* Reenable interrupts. */
5048                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5049                         mmiowb();
5050                         break;
5051                 }
5052         }
5053
5054         return work_done;
5055
5056 tx_recovery:
5057         /* work_done is guaranteed to be less than budget. */
5058         napi_complete(napi);
5059         schedule_work(&tp->reset_task);
5060         return work_done;
5061 }
5062
5063 static int tg3_poll(struct napi_struct *napi, int budget)
5064 {
5065         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5066         struct tg3 *tp = tnapi->tp;
5067         int work_done = 0;
5068         struct tg3_hw_status *sblk = tnapi->hw_status;
5069
5070         while (1) {
5071                 tg3_poll_link(tp);
5072
5073                 work_done = tg3_poll_work(tnapi, work_done, budget);
5074
5075                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5076                         goto tx_recovery;
5077
5078                 if (unlikely(work_done >= budget))
5079                         break;
5080
5081                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5082                         /* tp->last_tag is used in tg3_int_reenable() below
5083                          * to tell the hw how much work has been processed,
5084                          * so we must read it before checking for more work.
5085                          */
5086                         tnapi->last_tag = sblk->status_tag;
5087                         tnapi->last_irq_tag = tnapi->last_tag;
5088                         rmb();
5089                 } else
5090                         sblk->status &= ~SD_STATUS_UPDATED;
5091
5092                 if (likely(!tg3_has_work(tnapi))) {
5093                         napi_complete(napi);
5094                         tg3_int_reenable(tnapi);
5095                         break;
5096                 }
5097         }
5098
5099         return work_done;
5100
5101 tx_recovery:
5102         /* work_done is guaranteed to be less than budget. */
5103         napi_complete(napi);
5104         schedule_work(&tp->reset_task);
5105         return work_done;
5106 }
5107
5108 static void tg3_irq_quiesce(struct tg3 *tp)
5109 {
5110         int i;
5111
5112         BUG_ON(tp->irq_sync);
5113
5114         tp->irq_sync = 1;
5115         smp_mb();
5116
5117         for (i = 0; i < tp->irq_cnt; i++)
5118                 synchronize_irq(tp->napi[i].irq_vec);
5119 }
5120
5121 static inline int tg3_irq_sync(struct tg3 *tp)
5122 {
5123         return tp->irq_sync;
5124 }
5125
5126 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5127  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5128  * with as well.  Most of the time, this is not necessary except when
5129  * shutting down the device.
5130  */
5131 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5132 {
5133         spin_lock_bh(&tp->lock);
5134         if (irq_sync)
5135                 tg3_irq_quiesce(tp);
5136 }
5137
5138 static inline void tg3_full_unlock(struct tg3 *tp)
5139 {
5140         spin_unlock_bh(&tp->lock);
5141 }
5142
5143 /* One-shot MSI handler - Chip automatically disables interrupt
5144  * after sending MSI so driver doesn't have to do it.
5145  */
5146 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5147 {
5148         struct tg3_napi *tnapi = dev_id;
5149         struct tg3 *tp = tnapi->tp;
5150
5151         prefetch(tnapi->hw_status);
5152         if (tnapi->rx_rcb)
5153                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5154
5155         if (likely(!tg3_irq_sync(tp)))
5156                 napi_schedule(&tnapi->napi);
5157
5158         return IRQ_HANDLED;
5159 }
5160
5161 /* MSI ISR - No need to check for interrupt sharing and no need to
5162  * flush status block and interrupt mailbox. PCI ordering rules
5163  * guarantee that MSI will arrive after the status block.
5164  */
5165 static irqreturn_t tg3_msi(int irq, void *dev_id)
5166 {
5167         struct tg3_napi *tnapi = dev_id;
5168         struct tg3 *tp = tnapi->tp;
5169
5170         prefetch(tnapi->hw_status);
5171         if (tnapi->rx_rcb)
5172                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5173         /*
5174          * Writing any value to intr-mbox-0 clears PCI INTA# and
5175          * chip-internal interrupt pending events.
5176          * Writing non-zero to intr-mbox-0 additional tells the
5177          * NIC to stop sending us irqs, engaging "in-intr-handler"
5178          * event coalescing.
5179          */
5180         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5181         if (likely(!tg3_irq_sync(tp)))
5182                 napi_schedule(&tnapi->napi);
5183
5184         return IRQ_RETVAL(1);
5185 }
5186
5187 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5188 {
5189         struct tg3_napi *tnapi = dev_id;
5190         struct tg3 *tp = tnapi->tp;
5191         struct tg3_hw_status *sblk = tnapi->hw_status;
5192         unsigned int handled = 1;
5193
5194         /* In INTx mode, it is possible for the interrupt to arrive at
5195          * the CPU before the status block posted prior to the interrupt.
5196          * Reading the PCI State register will confirm whether the
5197          * interrupt is ours and will flush the status block.
5198          */
5199         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5200                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5201                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5202                         handled = 0;
5203                         goto out;
5204                 }
5205         }
5206
5207         /*
5208          * Writing any value to intr-mbox-0 clears PCI INTA# and
5209          * chip-internal interrupt pending events.
5210          * Writing non-zero to intr-mbox-0 additional tells the
5211          * NIC to stop sending us irqs, engaging "in-intr-handler"
5212          * event coalescing.
5213          *
5214          * Flush the mailbox to de-assert the IRQ immediately to prevent
5215          * spurious interrupts.  The flush impacts performance but
5216          * excessive spurious interrupts can be worse in some cases.
5217          */
5218         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5219         if (tg3_irq_sync(tp))
5220                 goto out;
5221         sblk->status &= ~SD_STATUS_UPDATED;
5222         if (likely(tg3_has_work(tnapi))) {
5223                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5224                 napi_schedule(&tnapi->napi);
5225         } else {
5226                 /* No work, shared interrupt perhaps?  re-enable
5227                  * interrupts, and flush that PCI write
5228                  */
5229                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5230                                0x00000000);
5231         }
5232 out:
5233         return IRQ_RETVAL(handled);
5234 }
5235
5236 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5237 {
5238         struct tg3_napi *tnapi = dev_id;
5239         struct tg3 *tp = tnapi->tp;
5240         struct tg3_hw_status *sblk = tnapi->hw_status;
5241         unsigned int handled = 1;
5242
5243         /* In INTx mode, it is possible for the interrupt to arrive at
5244          * the CPU before the status block posted prior to the interrupt.
5245          * Reading the PCI State register will confirm whether the
5246          * interrupt is ours and will flush the status block.
5247          */
5248         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5249                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5250                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5251                         handled = 0;
5252                         goto out;
5253                 }
5254         }
5255
5256         /*
5257          * writing any value to intr-mbox-0 clears PCI INTA# and
5258          * chip-internal interrupt pending events.
5259          * writing non-zero to intr-mbox-0 additional tells the
5260          * NIC to stop sending us irqs, engaging "in-intr-handler"
5261          * event coalescing.
5262          *
5263          * Flush the mailbox to de-assert the IRQ immediately to prevent
5264          * spurious interrupts.  The flush impacts performance but
5265          * excessive spurious interrupts can be worse in some cases.
5266          */
5267         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5268
5269         /*
5270          * In a shared interrupt configuration, sometimes other devices'
5271          * interrupts will scream.  We record the current status tag here
5272          * so that the above check can report that the screaming interrupts
5273          * are unhandled.  Eventually they will be silenced.
5274          */
5275         tnapi->last_irq_tag = sblk->status_tag;
5276
5277         if (tg3_irq_sync(tp))
5278                 goto out;
5279
5280         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5281
5282         napi_schedule(&tnapi->napi);
5283
5284 out:
5285         return IRQ_RETVAL(handled);
5286 }
5287
5288 /* ISR for interrupt test */
5289 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5290 {
5291         struct tg3_napi *tnapi = dev_id;
5292         struct tg3 *tp = tnapi->tp;
5293         struct tg3_hw_status *sblk = tnapi->hw_status;
5294
5295         if ((sblk->status & SD_STATUS_UPDATED) ||
5296             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5297                 tg3_disable_ints(tp);
5298                 return IRQ_RETVAL(1);
5299         }
5300         return IRQ_RETVAL(0);
5301 }
5302
5303 static int tg3_init_hw(struct tg3 *, int);
5304 static int tg3_halt(struct tg3 *, int, int);
5305
5306 /* Restart hardware after configuration changes, self-test, etc.
5307  * Invoked with tp->lock held.
5308  */
5309 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5310         __releases(tp->lock)
5311         __acquires(tp->lock)
5312 {
5313         int err;
5314
5315         err = tg3_init_hw(tp, reset_phy);
5316         if (err) {
5317                 netdev_err(tp->dev,
5318                            "Failed to re-initialize device, aborting\n");
5319                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5320                 tg3_full_unlock(tp);
5321                 del_timer_sync(&tp->timer);
5322                 tp->irq_sync = 0;
5323                 tg3_napi_enable(tp);
5324                 dev_close(tp->dev);
5325                 tg3_full_lock(tp, 0);
5326         }
5327         return err;
5328 }
5329
5330 #ifdef CONFIG_NET_POLL_CONTROLLER
5331 static void tg3_poll_controller(struct net_device *dev)
5332 {
5333         int i;
5334         struct tg3 *tp = netdev_priv(dev);
5335
5336         for (i = 0; i < tp->irq_cnt; i++)
5337                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5338 }
5339 #endif
5340
5341 static void tg3_reset_task(struct work_struct *work)
5342 {
5343         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5344         int err;
5345         unsigned int restart_timer;
5346
5347         tg3_full_lock(tp, 0);
5348
5349         if (!netif_running(tp->dev)) {
5350                 tg3_full_unlock(tp);
5351                 return;
5352         }
5353
5354         tg3_full_unlock(tp);
5355
5356         tg3_phy_stop(tp);
5357
5358         tg3_netif_stop(tp);
5359
5360         tg3_full_lock(tp, 1);
5361
5362         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5363         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5364
5365         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5366                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5367                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5368                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5369                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5370         }
5371
5372         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5373         err = tg3_init_hw(tp, 1);
5374         if (err)
5375                 goto out;
5376
5377         tg3_netif_start(tp);
5378
5379         if (restart_timer)
5380                 mod_timer(&tp->timer, jiffies + 1);
5381
5382 out:
5383         tg3_full_unlock(tp);
5384
5385         if (!err)
5386                 tg3_phy_start(tp);
5387 }
5388
5389 static void tg3_dump_short_state(struct tg3 *tp)
5390 {
5391         netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5392                    tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5393         netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5394                    tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5395 }
5396
5397 static void tg3_tx_timeout(struct net_device *dev)
5398 {
5399         struct tg3 *tp = netdev_priv(dev);
5400
5401         if (netif_msg_tx_err(tp)) {
5402                 netdev_err(dev, "transmit timed out, resetting\n");
5403                 tg3_dump_short_state(tp);
5404         }
5405
5406         schedule_work(&tp->reset_task);
5407 }
5408
5409 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5410 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5411 {
5412         u32 base = (u32) mapping & 0xffffffff;
5413
5414         return ((base > 0xffffdcc0) &&
5415                 (base + len + 8 < base));
5416 }
5417
5418 /* Test for DMA addresses > 40-bit */
5419 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5420                                           int len)
5421 {
5422 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5423         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5424                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5425         return 0;
5426 #else
5427         return 0;
5428 #endif
5429 }
5430
5431 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5432
5433 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5434 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5435                                        struct sk_buff *skb, u32 last_plus_one,
5436                                        u32 *start, u32 base_flags, u32 mss)
5437 {
5438         struct tg3 *tp = tnapi->tp;
5439         struct sk_buff *new_skb;
5440         dma_addr_t new_addr = 0;
5441         u32 entry = *start;
5442         int i, ret = 0;
5443
5444         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5445                 new_skb = skb_copy(skb, GFP_ATOMIC);
5446         else {
5447                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5448
5449                 new_skb = skb_copy_expand(skb,
5450                                           skb_headroom(skb) + more_headroom,
5451                                           skb_tailroom(skb), GFP_ATOMIC);
5452         }
5453
5454         if (!new_skb) {
5455                 ret = -1;
5456         } else {
5457                 /* New SKB is guaranteed to be linear. */
5458                 entry = *start;
5459                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5460                                           PCI_DMA_TODEVICE);
5461                 /* Make sure the mapping succeeded */
5462                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5463                         ret = -1;
5464                         dev_kfree_skb(new_skb);
5465                         new_skb = NULL;
5466
5467                 /* Make sure new skb does not cross any 4G boundaries.
5468                  * Drop the packet if it does.
5469                  */
5470                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5471                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5472                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5473                                          PCI_DMA_TODEVICE);
5474                         ret = -1;
5475                         dev_kfree_skb(new_skb);
5476                         new_skb = NULL;
5477                 } else {
5478                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5479                                     base_flags, 1 | (mss << 1));
5480                         *start = NEXT_TX(entry);
5481                 }
5482         }
5483
5484         /* Now clean up the sw ring entries. */
5485         i = 0;
5486         while (entry != last_plus_one) {
5487                 int len;
5488
5489                 if (i == 0)
5490                         len = skb_headlen(skb);
5491                 else
5492                         len = skb_shinfo(skb)->frags[i-1].size;
5493
5494                 pci_unmap_single(tp->pdev,
5495                                  dma_unmap_addr(&tnapi->tx_buffers[entry],
5496                                                 mapping),
5497                                  len, PCI_DMA_TODEVICE);
5498                 if (i == 0) {
5499                         tnapi->tx_buffers[entry].skb = new_skb;
5500                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5501                                            new_addr);
5502                 } else {
5503                         tnapi->tx_buffers[entry].skb = NULL;
5504                 }
5505                 entry = NEXT_TX(entry);
5506                 i++;
5507         }
5508
5509         dev_kfree_skb(skb);
5510
5511         return ret;
5512 }
5513
5514 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5515                         dma_addr_t mapping, int len, u32 flags,
5516                         u32 mss_and_is_end)
5517 {
5518         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5519         int is_end = (mss_and_is_end & 0x1);
5520         u32 mss = (mss_and_is_end >> 1);
5521         u32 vlan_tag = 0;
5522
5523         if (is_end)
5524                 flags |= TXD_FLAG_END;
5525         if (flags & TXD_FLAG_VLAN) {
5526                 vlan_tag = flags >> 16;
5527                 flags &= 0xffff;
5528         }
5529         vlan_tag |= (mss << TXD_MSS_SHIFT);
5530
5531         txd->addr_hi = ((u64) mapping >> 32);
5532         txd->addr_lo = ((u64) mapping & 0xffffffff);
5533         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5534         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5535 }
5536
5537 /* hard_start_xmit for devices that don't have any bugs and
5538  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5539  */
5540 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5541                                   struct net_device *dev)
5542 {
5543         struct tg3 *tp = netdev_priv(dev);
5544         u32 len, entry, base_flags, mss;
5545         dma_addr_t mapping;
5546         struct tg3_napi *tnapi;
5547         struct netdev_queue *txq;
5548         unsigned int i, last;
5549
5550         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5551         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5552         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5553                 tnapi++;
5554
5555         /* We are running in BH disabled context with netif_tx_lock
5556          * and TX reclaim runs via tp->napi.poll inside of a software
5557          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5558          * no IRQ context deadlocks to worry about either.  Rejoice!
5559          */
5560         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5561                 if (!netif_tx_queue_stopped(txq)) {
5562                         netif_tx_stop_queue(txq);
5563
5564                         /* This is a hard error, log it. */
5565                         netdev_err(dev,
5566                                    "BUG! Tx Ring full when queue awake!\n");
5567                 }
5568                 return NETDEV_TX_BUSY;
5569         }
5570
5571         entry = tnapi->tx_prod;
5572         base_flags = 0;
5573         mss = 0;
5574         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5575                 int tcp_opt_len, ip_tcp_len;
5576                 u32 hdrlen;
5577
5578                 if (skb_header_cloned(skb) &&
5579                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5580                         dev_kfree_skb(skb);
5581                         goto out_unlock;
5582                 }
5583
5584                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5585                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5586                 else {
5587                         struct iphdr *iph = ip_hdr(skb);
5588
5589                         tcp_opt_len = tcp_optlen(skb);
5590                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5591
5592                         iph->check = 0;
5593                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5594                         hdrlen = ip_tcp_len + tcp_opt_len;
5595                 }
5596
5597                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5598                         mss |= (hdrlen & 0xc) << 12;
5599                         if (hdrlen & 0x10)
5600                                 base_flags |= 0x00000010;
5601                         base_flags |= (hdrlen & 0x3e0) << 5;
5602                 } else
5603                         mss |= hdrlen << 9;
5604
5605                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5606                                TXD_FLAG_CPU_POST_DMA);
5607
5608                 tcp_hdr(skb)->check = 0;
5609
5610         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5611                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5612         }
5613
5614 #if TG3_VLAN_TAG_USED
5615         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5616                 base_flags |= (TXD_FLAG_VLAN |
5617                                (vlan_tx_tag_get(skb) << 16));
5618 #endif
5619
5620         len = skb_headlen(skb);
5621
5622         /* Queue skb data, a.k.a. the main skb fragment. */
5623         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5624         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5625                 dev_kfree_skb(skb);
5626                 goto out_unlock;
5627         }
5628
5629         tnapi->tx_buffers[entry].skb = skb;
5630         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5631
5632         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5633             !mss && skb->len > ETH_DATA_LEN)
5634                 base_flags |= TXD_FLAG_JMB_PKT;
5635
5636         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5637                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5638
5639         entry = NEXT_TX(entry);
5640
5641         /* Now loop through additional data fragments, and queue them. */
5642         if (skb_shinfo(skb)->nr_frags > 0) {
5643                 last = skb_shinfo(skb)->nr_frags - 1;
5644                 for (i = 0; i <= last; i++) {
5645                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5646
5647                         len = frag->size;
5648                         mapping = pci_map_page(tp->pdev,
5649                                                frag->page,
5650                                                frag->page_offset,
5651                                                len, PCI_DMA_TODEVICE);
5652                         if (pci_dma_mapping_error(tp->pdev, mapping))
5653                                 goto dma_error;
5654
5655                         tnapi->tx_buffers[entry].skb = NULL;
5656                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5657                                            mapping);
5658
5659                         tg3_set_txd(tnapi, entry, mapping, len,
5660                                     base_flags, (i == last) | (mss << 1));
5661
5662                         entry = NEXT_TX(entry);
5663                 }
5664         }
5665
5666         /* Packets are ready, update Tx producer idx local and on card. */
5667         tw32_tx_mbox(tnapi->prodmbox, entry);
5668
5669         tnapi->tx_prod = entry;
5670         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5671                 netif_tx_stop_queue(txq);
5672                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5673                         netif_tx_wake_queue(txq);
5674         }
5675
5676 out_unlock:
5677         mmiowb();
5678
5679         return NETDEV_TX_OK;
5680
5681 dma_error:
5682         last = i;
5683         entry = tnapi->tx_prod;
5684         tnapi->tx_buffers[entry].skb = NULL;
5685         pci_unmap_single(tp->pdev,
5686                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5687                          skb_headlen(skb),
5688                          PCI_DMA_TODEVICE);
5689         for (i = 0; i <= last; i++) {
5690                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5691                 entry = NEXT_TX(entry);
5692
5693                 pci_unmap_page(tp->pdev,
5694                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5695                                               mapping),
5696                                frag->size, PCI_DMA_TODEVICE);
5697         }
5698
5699         dev_kfree_skb(skb);
5700         return NETDEV_TX_OK;
5701 }
5702
5703 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5704                                           struct net_device *);
5705
5706 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5707  * TSO header is greater than 80 bytes.
5708  */
5709 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5710 {
5711         struct sk_buff *segs, *nskb;
5712         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5713
5714         /* Estimate the number of fragments in the worst case */
5715         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5716                 netif_stop_queue(tp->dev);
5717                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5718                         return NETDEV_TX_BUSY;
5719
5720                 netif_wake_queue(tp->dev);
5721         }
5722
5723         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5724         if (IS_ERR(segs))
5725                 goto tg3_tso_bug_end;
5726
5727         do {
5728                 nskb = segs;
5729                 segs = segs->next;
5730                 nskb->next = NULL;
5731                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5732         } while (segs);
5733
5734 tg3_tso_bug_end:
5735         dev_kfree_skb(skb);
5736
5737         return NETDEV_TX_OK;
5738 }
5739
5740 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5741  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5742  */
5743 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5744                                           struct net_device *dev)
5745 {
5746         struct tg3 *tp = netdev_priv(dev);
5747         u32 len, entry, base_flags, mss;
5748         int would_hit_hwbug;
5749         dma_addr_t mapping;
5750         struct tg3_napi *tnapi;
5751         struct netdev_queue *txq;
5752         unsigned int i, last;
5753
5754         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5755         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5756         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)