tg3: Futureproof the loopback test
[linux-2.6.git] / drivers / net / tg3.c
1 /*
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  * Copyright (C) 2005-2010 Broadcom Corporation.
8  *
9  * Firmware is:
10  *      Derived from proprietary unpublished source code,
11  *      Copyright (C) 2000-2003 Broadcom Corporation.
12  *
13  *      Permission is hereby granted for the distribution of this firmware
14  *      data in hexadecimal or equivalent format, provided this copyright
15  *      notice is accompanying it.
16  */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/in.h>
28 #include <linux/init.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mii.h>
36 #include <linux/phy.h>
37 #include <linux/brcmphy.h>
38 #include <linux/if_vlan.h>
39 #include <linux/ip.h>
40 #include <linux/tcp.h>
41 #include <linux/workqueue.h>
42 #include <linux/prefetch.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/firmware.h>
45
46 #include <net/checksum.h>
47 #include <net/ip.h>
48
49 #include <asm/system.h>
50 #include <asm/io.h>
51 #include <asm/byteorder.h>
52 #include <asm/uaccess.h>
53
54 #ifdef CONFIG_SPARC
55 #include <asm/idprom.h>
56 #include <asm/prom.h>
57 #endif
58
59 #define BAR_0   0
60 #define BAR_2   2
61
62 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
63 #define TG3_VLAN_TAG_USED 1
64 #else
65 #define TG3_VLAN_TAG_USED 0
66 #endif
67
68 #include "tg3.h"
69
70 #define DRV_MODULE_NAME         "tg3"
71 #define TG3_MAJ_NUM                     3
72 #define TG3_MIN_NUM                     113
73 #define DRV_MODULE_VERSION      \
74         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
75 #define DRV_MODULE_RELDATE      "August 2, 2010"
76
77 #define TG3_DEF_MAC_MODE        0
78 #define TG3_DEF_RX_MODE         0
79 #define TG3_DEF_TX_MODE         0
80 #define TG3_DEF_MSG_ENABLE        \
81         (NETIF_MSG_DRV          | \
82          NETIF_MSG_PROBE        | \
83          NETIF_MSG_LINK         | \
84          NETIF_MSG_TIMER        | \
85          NETIF_MSG_IFDOWN       | \
86          NETIF_MSG_IFUP         | \
87          NETIF_MSG_RX_ERR       | \
88          NETIF_MSG_TX_ERR)
89
90 /* length of time before we decide the hardware is borked,
91  * and dev->tx_timeout() should be called to fix the problem
92  */
93 #define TG3_TX_TIMEOUT                  (5 * HZ)
94
95 /* hardware minimum and maximum for a single frame's data payload */
96 #define TG3_MIN_MTU                     60
97 #define TG3_MAX_MTU(tp) \
98         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
99
100 /* These numbers seem to be hard coded in the NIC firmware somehow.
101  * You can't change the ring sizes, but you can change where you place
102  * them in the NIC onboard memory.
103  */
104 #define TG3_RX_RING_SIZE                512
105 #define TG3_DEF_RX_RING_PENDING         200
106 #define TG3_RX_JUMBO_RING_SIZE          256
107 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
108 #define TG3_RSS_INDIR_TBL_SIZE          128
109
110 /* Do not place this n-ring entries value into the tp struct itself,
111  * we really want to expose these constants to GCC so that modulo et
112  * al.  operations are done with shifts and masks instead of with
113  * hw multiply/modulo instructions.  Another solution would be to
114  * replace things like '% foo' with '& (foo - 1)'.
115  */
116 #define TG3_RX_RCB_RING_SIZE(tp)        \
117         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
118           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
119
120 #define TG3_TX_RING_SIZE                512
121 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
122
123 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
124                                  TG3_RX_RING_SIZE)
125 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
126                                  TG3_RX_JUMBO_RING_SIZE)
127 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
128                                  TG3_RX_RCB_RING_SIZE(tp))
129 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
130                                  TG3_TX_RING_SIZE)
131 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
132
133 #define TG3_RX_DMA_ALIGN                16
134 #define TG3_RX_HEADROOM                 ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
135
136 #define TG3_DMA_BYTE_ENAB               64
137
138 #define TG3_RX_STD_DMA_SZ               1536
139 #define TG3_RX_JMB_DMA_SZ               9046
140
141 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
142
143 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
144 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
145
146 #define TG3_RX_STD_BUFF_RING_SIZE \
147         (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
148
149 #define TG3_RX_JMB_BUFF_RING_SIZE \
150         (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
151
152 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
153  * that are at least dword aligned when used in PCIX mode.  The driver
154  * works around this bug by double copying the packet.  This workaround
155  * is built into the normal double copy length check for efficiency.
156  *
157  * However, the double copy is only necessary on those architectures
158  * where unaligned memory accesses are inefficient.  For those architectures
159  * where unaligned memory accesses incur little penalty, we can reintegrate
160  * the 5701 in the normal rx path.  Doing so saves a device structure
161  * dereference by hardcoding the double copy threshold in place.
162  */
163 #define TG3_RX_COPY_THRESHOLD           256
164 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
165         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
166 #else
167         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
168 #endif
169
170 /* minimum number of free TX descriptors required to wake up TX process */
171 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
172
173 #define TG3_RAW_IP_ALIGN 2
174
175 /* number of ETHTOOL_GSTATS u64's */
176 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
177
178 #define TG3_NUM_TEST            6
179
180 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
181
182 #define FIRMWARE_TG3            "tigon/tg3.bin"
183 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
184 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
185
186 static char version[] __devinitdata =
187         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
188
189 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
190 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
191 MODULE_LICENSE("GPL");
192 MODULE_VERSION(DRV_MODULE_VERSION);
193 MODULE_FIRMWARE(FIRMWARE_TG3);
194 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
195 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
196
197 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
198 module_param(tg3_debug, int, 0);
199 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
200
201 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
268         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
269         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
270         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
271         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
272         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
273         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
274         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
275         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
276         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
277         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
278         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
279         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
280         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
281         {}
282 };
283
284 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
285
286 static const struct {
287         const char string[ETH_GSTRING_LEN];
288 } ethtool_stats_keys[TG3_NUM_STATS] = {
289         { "rx_octets" },
290         { "rx_fragments" },
291         { "rx_ucast_packets" },
292         { "rx_mcast_packets" },
293         { "rx_bcast_packets" },
294         { "rx_fcs_errors" },
295         { "rx_align_errors" },
296         { "rx_xon_pause_rcvd" },
297         { "rx_xoff_pause_rcvd" },
298         { "rx_mac_ctrl_rcvd" },
299         { "rx_xoff_entered" },
300         { "rx_frame_too_long_errors" },
301         { "rx_jabbers" },
302         { "rx_undersize_packets" },
303         { "rx_in_length_errors" },
304         { "rx_out_length_errors" },
305         { "rx_64_or_less_octet_packets" },
306         { "rx_65_to_127_octet_packets" },
307         { "rx_128_to_255_octet_packets" },
308         { "rx_256_to_511_octet_packets" },
309         { "rx_512_to_1023_octet_packets" },
310         { "rx_1024_to_1522_octet_packets" },
311         { "rx_1523_to_2047_octet_packets" },
312         { "rx_2048_to_4095_octet_packets" },
313         { "rx_4096_to_8191_octet_packets" },
314         { "rx_8192_to_9022_octet_packets" },
315
316         { "tx_octets" },
317         { "tx_collisions" },
318
319         { "tx_xon_sent" },
320         { "tx_xoff_sent" },
321         { "tx_flow_control" },
322         { "tx_mac_errors" },
323         { "tx_single_collisions" },
324         { "tx_mult_collisions" },
325         { "tx_deferred" },
326         { "tx_excessive_collisions" },
327         { "tx_late_collisions" },
328         { "tx_collide_2times" },
329         { "tx_collide_3times" },
330         { "tx_collide_4times" },
331         { "tx_collide_5times" },
332         { "tx_collide_6times" },
333         { "tx_collide_7times" },
334         { "tx_collide_8times" },
335         { "tx_collide_9times" },
336         { "tx_collide_10times" },
337         { "tx_collide_11times" },
338         { "tx_collide_12times" },
339         { "tx_collide_13times" },
340         { "tx_collide_14times" },
341         { "tx_collide_15times" },
342         { "tx_ucast_packets" },
343         { "tx_mcast_packets" },
344         { "tx_bcast_packets" },
345         { "tx_carrier_sense_errors" },
346         { "tx_discards" },
347         { "tx_errors" },
348
349         { "dma_writeq_full" },
350         { "dma_write_prioq_full" },
351         { "rxbds_empty" },
352         { "rx_discards" },
353         { "rx_errors" },
354         { "rx_threshold_hit" },
355
356         { "dma_readq_full" },
357         { "dma_read_prioq_full" },
358         { "tx_comp_queue_full" },
359
360         { "ring_set_send_prod_index" },
361         { "ring_status_update" },
362         { "nic_irqs" },
363         { "nic_avoided_irqs" },
364         { "nic_tx_threshold_hit" }
365 };
366
367 static const struct {
368         const char string[ETH_GSTRING_LEN];
369 } ethtool_test_keys[TG3_NUM_TEST] = {
370         { "nvram test     (online) " },
371         { "link test      (online) " },
372         { "register test  (offline)" },
373         { "memory test    (offline)" },
374         { "loopback test  (offline)" },
375         { "interrupt test (offline)" },
376 };
377
378 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
379 {
380         writel(val, tp->regs + off);
381 }
382
383 static u32 tg3_read32(struct tg3 *tp, u32 off)
384 {
385         return readl(tp->regs + off);
386 }
387
388 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
389 {
390         writel(val, tp->aperegs + off);
391 }
392
393 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
394 {
395         return readl(tp->aperegs + off);
396 }
397
398 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
399 {
400         unsigned long flags;
401
402         spin_lock_irqsave(&tp->indirect_lock, flags);
403         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
404         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
405         spin_unlock_irqrestore(&tp->indirect_lock, flags);
406 }
407
408 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
409 {
410         writel(val, tp->regs + off);
411         readl(tp->regs + off);
412 }
413
414 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
415 {
416         unsigned long flags;
417         u32 val;
418
419         spin_lock_irqsave(&tp->indirect_lock, flags);
420         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
421         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
422         spin_unlock_irqrestore(&tp->indirect_lock, flags);
423         return val;
424 }
425
426 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
427 {
428         unsigned long flags;
429
430         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
431                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
432                                        TG3_64BIT_REG_LOW, val);
433                 return;
434         }
435         if (off == TG3_RX_STD_PROD_IDX_REG) {
436                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
437                                        TG3_64BIT_REG_LOW, val);
438                 return;
439         }
440
441         spin_lock_irqsave(&tp->indirect_lock, flags);
442         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
443         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
444         spin_unlock_irqrestore(&tp->indirect_lock, flags);
445
446         /* In indirect mode when disabling interrupts, we also need
447          * to clear the interrupt bit in the GRC local ctrl register.
448          */
449         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
450             (val == 0x1)) {
451                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
452                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
453         }
454 }
455
456 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
457 {
458         unsigned long flags;
459         u32 val;
460
461         spin_lock_irqsave(&tp->indirect_lock, flags);
462         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
463         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
464         spin_unlock_irqrestore(&tp->indirect_lock, flags);
465         return val;
466 }
467
468 /* usec_wait specifies the wait time in usec when writing to certain registers
469  * where it is unsafe to read back the register without some delay.
470  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
471  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
472  */
473 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
474 {
475         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
476             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
477                 /* Non-posted methods */
478                 tp->write32(tp, off, val);
479         else {
480                 /* Posted method */
481                 tg3_write32(tp, off, val);
482                 if (usec_wait)
483                         udelay(usec_wait);
484                 tp->read32(tp, off);
485         }
486         /* Wait again after the read for the posted method to guarantee that
487          * the wait time is met.
488          */
489         if (usec_wait)
490                 udelay(usec_wait);
491 }
492
493 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
494 {
495         tp->write32_mbox(tp, off, val);
496         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
497             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
498                 tp->read32_mbox(tp, off);
499 }
500
501 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
502 {
503         void __iomem *mbox = tp->regs + off;
504         writel(val, mbox);
505         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
506                 writel(val, mbox);
507         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
508                 readl(mbox);
509 }
510
511 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
512 {
513         return readl(tp->regs + off + GRCMBOX_BASE);
514 }
515
516 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
517 {
518         writel(val, tp->regs + off + GRCMBOX_BASE);
519 }
520
521 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
522 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
523 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
524 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
525 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
526
527 #define tw32(reg, val)                  tp->write32(tp, reg, val)
528 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
529 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
530 #define tr32(reg)                       tp->read32(tp, reg)
531
532 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
533 {
534         unsigned long flags;
535
536         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
537             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
538                 return;
539
540         spin_lock_irqsave(&tp->indirect_lock, flags);
541         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
542                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
543                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
544
545                 /* Always leave this as zero. */
546                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
547         } else {
548                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
549                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
550
551                 /* Always leave this as zero. */
552                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
553         }
554         spin_unlock_irqrestore(&tp->indirect_lock, flags);
555 }
556
557 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
558 {
559         unsigned long flags;
560
561         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
562             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
563                 *val = 0;
564                 return;
565         }
566
567         spin_lock_irqsave(&tp->indirect_lock, flags);
568         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
569                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
570                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
571
572                 /* Always leave this as zero. */
573                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
574         } else {
575                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
576                 *val = tr32(TG3PCI_MEM_WIN_DATA);
577
578                 /* Always leave this as zero. */
579                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
580         }
581         spin_unlock_irqrestore(&tp->indirect_lock, flags);
582 }
583
584 static void tg3_ape_lock_init(struct tg3 *tp)
585 {
586         int i;
587         u32 regbase;
588
589         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
590                 regbase = TG3_APE_LOCK_GRANT;
591         else
592                 regbase = TG3_APE_PER_LOCK_GRANT;
593
594         /* Make sure the driver hasn't any stale locks. */
595         for (i = 0; i < 8; i++)
596                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
597 }
598
599 static int tg3_ape_lock(struct tg3 *tp, int locknum)
600 {
601         int i, off;
602         int ret = 0;
603         u32 status, req, gnt;
604
605         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
606                 return 0;
607
608         switch (locknum) {
609         case TG3_APE_LOCK_GRC:
610         case TG3_APE_LOCK_MEM:
611                 break;
612         default:
613                 return -EINVAL;
614         }
615
616         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
617                 req = TG3_APE_LOCK_REQ;
618                 gnt = TG3_APE_LOCK_GRANT;
619         } else {
620                 req = TG3_APE_PER_LOCK_REQ;
621                 gnt = TG3_APE_PER_LOCK_GRANT;
622         }
623
624         off = 4 * locknum;
625
626         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
627
628         /* Wait for up to 1 millisecond to acquire lock. */
629         for (i = 0; i < 100; i++) {
630                 status = tg3_ape_read32(tp, gnt + off);
631                 if (status == APE_LOCK_GRANT_DRIVER)
632                         break;
633                 udelay(10);
634         }
635
636         if (status != APE_LOCK_GRANT_DRIVER) {
637                 /* Revoke the lock request. */
638                 tg3_ape_write32(tp, gnt + off,
639                                 APE_LOCK_GRANT_DRIVER);
640
641                 ret = -EBUSY;
642         }
643
644         return ret;
645 }
646
647 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
648 {
649         u32 gnt;
650
651         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
652                 return;
653
654         switch (locknum) {
655         case TG3_APE_LOCK_GRC:
656         case TG3_APE_LOCK_MEM:
657                 break;
658         default:
659                 return;
660         }
661
662         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
663                 gnt = TG3_APE_LOCK_GRANT;
664         else
665                 gnt = TG3_APE_PER_LOCK_GRANT;
666
667         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
668 }
669
670 static void tg3_disable_ints(struct tg3 *tp)
671 {
672         int i;
673
674         tw32(TG3PCI_MISC_HOST_CTRL,
675              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
676         for (i = 0; i < tp->irq_max; i++)
677                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
678 }
679
680 static void tg3_enable_ints(struct tg3 *tp)
681 {
682         int i;
683
684         tp->irq_sync = 0;
685         wmb();
686
687         tw32(TG3PCI_MISC_HOST_CTRL,
688              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
689
690         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
691         for (i = 0; i < tp->irq_cnt; i++) {
692                 struct tg3_napi *tnapi = &tp->napi[i];
693
694                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
695                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
696                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
697
698                 tp->coal_now |= tnapi->coal_now;
699         }
700
701         /* Force an initial interrupt */
702         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
703             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
704                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
705         else
706                 tw32(HOSTCC_MODE, tp->coal_now);
707
708         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
709 }
710
711 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
712 {
713         struct tg3 *tp = tnapi->tp;
714         struct tg3_hw_status *sblk = tnapi->hw_status;
715         unsigned int work_exists = 0;
716
717         /* check for phy events */
718         if (!(tp->tg3_flags &
719               (TG3_FLAG_USE_LINKCHG_REG |
720                TG3_FLAG_POLL_SERDES))) {
721                 if (sblk->status & SD_STATUS_LINK_CHG)
722                         work_exists = 1;
723         }
724         /* check for RX/TX work to do */
725         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
726             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
727                 work_exists = 1;
728
729         return work_exists;
730 }
731
732 /* tg3_int_reenable
733  *  similar to tg3_enable_ints, but it accurately determines whether there
734  *  is new work pending and can return without flushing the PIO write
735  *  which reenables interrupts
736  */
737 static void tg3_int_reenable(struct tg3_napi *tnapi)
738 {
739         struct tg3 *tp = tnapi->tp;
740
741         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
742         mmiowb();
743
744         /* When doing tagged status, this work check is unnecessary.
745          * The last_tag we write above tells the chip which piece of
746          * work we've completed.
747          */
748         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
749             tg3_has_work(tnapi))
750                 tw32(HOSTCC_MODE, tp->coalesce_mode |
751                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
752 }
753
754 static void tg3_switch_clocks(struct tg3 *tp)
755 {
756         u32 clock_ctrl;
757         u32 orig_clock_ctrl;
758
759         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
760             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
761                 return;
762
763         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
764
765         orig_clock_ctrl = clock_ctrl;
766         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
767                        CLOCK_CTRL_CLKRUN_OENABLE |
768                        0x1f);
769         tp->pci_clock_ctrl = clock_ctrl;
770
771         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
772                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
773                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
774                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
775                 }
776         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
777                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
778                             clock_ctrl |
779                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
780                             40);
781                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
782                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
783                             40);
784         }
785         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
786 }
787
788 #define PHY_BUSY_LOOPS  5000
789
790 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
791 {
792         u32 frame_val;
793         unsigned int loops;
794         int ret;
795
796         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
797                 tw32_f(MAC_MI_MODE,
798                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
799                 udelay(80);
800         }
801
802         *val = 0x0;
803
804         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
805                       MI_COM_PHY_ADDR_MASK);
806         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
807                       MI_COM_REG_ADDR_MASK);
808         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
809
810         tw32_f(MAC_MI_COM, frame_val);
811
812         loops = PHY_BUSY_LOOPS;
813         while (loops != 0) {
814                 udelay(10);
815                 frame_val = tr32(MAC_MI_COM);
816
817                 if ((frame_val & MI_COM_BUSY) == 0) {
818                         udelay(5);
819                         frame_val = tr32(MAC_MI_COM);
820                         break;
821                 }
822                 loops -= 1;
823         }
824
825         ret = -EBUSY;
826         if (loops != 0) {
827                 *val = frame_val & MI_COM_DATA_MASK;
828                 ret = 0;
829         }
830
831         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
832                 tw32_f(MAC_MI_MODE, tp->mi_mode);
833                 udelay(80);
834         }
835
836         return ret;
837 }
838
839 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
840 {
841         u32 frame_val;
842         unsigned int loops;
843         int ret;
844
845         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
846             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
847                 return 0;
848
849         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
850                 tw32_f(MAC_MI_MODE,
851                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
852                 udelay(80);
853         }
854
855         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
856                       MI_COM_PHY_ADDR_MASK);
857         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
858                       MI_COM_REG_ADDR_MASK);
859         frame_val |= (val & MI_COM_DATA_MASK);
860         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
861
862         tw32_f(MAC_MI_COM, frame_val);
863
864         loops = PHY_BUSY_LOOPS;
865         while (loops != 0) {
866                 udelay(10);
867                 frame_val = tr32(MAC_MI_COM);
868                 if ((frame_val & MI_COM_BUSY) == 0) {
869                         udelay(5);
870                         frame_val = tr32(MAC_MI_COM);
871                         break;
872                 }
873                 loops -= 1;
874         }
875
876         ret = -EBUSY;
877         if (loops != 0)
878                 ret = 0;
879
880         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
881                 tw32_f(MAC_MI_MODE, tp->mi_mode);
882                 udelay(80);
883         }
884
885         return ret;
886 }
887
888 static int tg3_bmcr_reset(struct tg3 *tp)
889 {
890         u32 phy_control;
891         int limit, err;
892
893         /* OK, reset it, and poll the BMCR_RESET bit until it
894          * clears or we time out.
895          */
896         phy_control = BMCR_RESET;
897         err = tg3_writephy(tp, MII_BMCR, phy_control);
898         if (err != 0)
899                 return -EBUSY;
900
901         limit = 5000;
902         while (limit--) {
903                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
904                 if (err != 0)
905                         return -EBUSY;
906
907                 if ((phy_control & BMCR_RESET) == 0) {
908                         udelay(40);
909                         break;
910                 }
911                 udelay(10);
912         }
913         if (limit < 0)
914                 return -EBUSY;
915
916         return 0;
917 }
918
919 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
920 {
921         struct tg3 *tp = bp->priv;
922         u32 val;
923
924         spin_lock_bh(&tp->lock);
925
926         if (tg3_readphy(tp, reg, &val))
927                 val = -EIO;
928
929         spin_unlock_bh(&tp->lock);
930
931         return val;
932 }
933
934 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
935 {
936         struct tg3 *tp = bp->priv;
937         u32 ret = 0;
938
939         spin_lock_bh(&tp->lock);
940
941         if (tg3_writephy(tp, reg, val))
942                 ret = -EIO;
943
944         spin_unlock_bh(&tp->lock);
945
946         return ret;
947 }
948
949 static int tg3_mdio_reset(struct mii_bus *bp)
950 {
951         return 0;
952 }
953
954 static void tg3_mdio_config_5785(struct tg3 *tp)
955 {
956         u32 val;
957         struct phy_device *phydev;
958
959         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
960         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
961         case PHY_ID_BCM50610:
962         case PHY_ID_BCM50610M:
963                 val = MAC_PHYCFG2_50610_LED_MODES;
964                 break;
965         case PHY_ID_BCMAC131:
966                 val = MAC_PHYCFG2_AC131_LED_MODES;
967                 break;
968         case PHY_ID_RTL8211C:
969                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
970                 break;
971         case PHY_ID_RTL8201E:
972                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
973                 break;
974         default:
975                 return;
976         }
977
978         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
979                 tw32(MAC_PHYCFG2, val);
980
981                 val = tr32(MAC_PHYCFG1);
982                 val &= ~(MAC_PHYCFG1_RGMII_INT |
983                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
984                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
985                 tw32(MAC_PHYCFG1, val);
986
987                 return;
988         }
989
990         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
991                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
992                        MAC_PHYCFG2_FMODE_MASK_MASK |
993                        MAC_PHYCFG2_GMODE_MASK_MASK |
994                        MAC_PHYCFG2_ACT_MASK_MASK   |
995                        MAC_PHYCFG2_QUAL_MASK_MASK |
996                        MAC_PHYCFG2_INBAND_ENABLE;
997
998         tw32(MAC_PHYCFG2, val);
999
1000         val = tr32(MAC_PHYCFG1);
1001         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1002                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1003         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1004                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1005                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1006                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1007                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1008         }
1009         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1010                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1011         tw32(MAC_PHYCFG1, val);
1012
1013         val = tr32(MAC_EXT_RGMII_MODE);
1014         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1015                  MAC_RGMII_MODE_RX_QUALITY |
1016                  MAC_RGMII_MODE_RX_ACTIVITY |
1017                  MAC_RGMII_MODE_RX_ENG_DET |
1018                  MAC_RGMII_MODE_TX_ENABLE |
1019                  MAC_RGMII_MODE_TX_LOWPWR |
1020                  MAC_RGMII_MODE_TX_RESET);
1021         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1022                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1023                         val |= MAC_RGMII_MODE_RX_INT_B |
1024                                MAC_RGMII_MODE_RX_QUALITY |
1025                                MAC_RGMII_MODE_RX_ACTIVITY |
1026                                MAC_RGMII_MODE_RX_ENG_DET;
1027                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1028                         val |= MAC_RGMII_MODE_TX_ENABLE |
1029                                MAC_RGMII_MODE_TX_LOWPWR |
1030                                MAC_RGMII_MODE_TX_RESET;
1031         }
1032         tw32(MAC_EXT_RGMII_MODE, val);
1033 }
1034
1035 static void tg3_mdio_start(struct tg3 *tp)
1036 {
1037         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1038         tw32_f(MAC_MI_MODE, tp->mi_mode);
1039         udelay(80);
1040
1041         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1042             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1043                 tg3_mdio_config_5785(tp);
1044 }
1045
1046 static int tg3_mdio_init(struct tg3 *tp)
1047 {
1048         int i;
1049         u32 reg;
1050         struct phy_device *phydev;
1051
1052         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1053             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
1054                 u32 is_serdes;
1055
1056                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1057
1058                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1059                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1060                 else
1061                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1062                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1063                 if (is_serdes)
1064                         tp->phy_addr += 7;
1065         } else
1066                 tp->phy_addr = TG3_PHY_MII_ADDR;
1067
1068         tg3_mdio_start(tp);
1069
1070         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1071             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1072                 return 0;
1073
1074         tp->mdio_bus = mdiobus_alloc();
1075         if (tp->mdio_bus == NULL)
1076                 return -ENOMEM;
1077
1078         tp->mdio_bus->name     = "tg3 mdio bus";
1079         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1080                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1081         tp->mdio_bus->priv     = tp;
1082         tp->mdio_bus->parent   = &tp->pdev->dev;
1083         tp->mdio_bus->read     = &tg3_mdio_read;
1084         tp->mdio_bus->write    = &tg3_mdio_write;
1085         tp->mdio_bus->reset    = &tg3_mdio_reset;
1086         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1087         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1088
1089         for (i = 0; i < PHY_MAX_ADDR; i++)
1090                 tp->mdio_bus->irq[i] = PHY_POLL;
1091
1092         /* The bus registration will look for all the PHYs on the mdio bus.
1093          * Unfortunately, it does not ensure the PHY is powered up before
1094          * accessing the PHY ID registers.  A chip reset is the
1095          * quickest way to bring the device back to an operational state..
1096          */
1097         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1098                 tg3_bmcr_reset(tp);
1099
1100         i = mdiobus_register(tp->mdio_bus);
1101         if (i) {
1102                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1103                 mdiobus_free(tp->mdio_bus);
1104                 return i;
1105         }
1106
1107         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1108
1109         if (!phydev || !phydev->drv) {
1110                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1111                 mdiobus_unregister(tp->mdio_bus);
1112                 mdiobus_free(tp->mdio_bus);
1113                 return -ENODEV;
1114         }
1115
1116         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1117         case PHY_ID_BCM57780:
1118                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1119                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1120                 break;
1121         case PHY_ID_BCM50610:
1122         case PHY_ID_BCM50610M:
1123                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1124                                      PHY_BRCM_RX_REFCLK_UNUSED |
1125                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1126                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1127                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1128                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1129                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1130                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1131                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1132                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1133                 /* fallthru */
1134         case PHY_ID_RTL8211C:
1135                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1136                 break;
1137         case PHY_ID_RTL8201E:
1138         case PHY_ID_BCMAC131:
1139                 phydev->interface = PHY_INTERFACE_MODE_MII;
1140                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1141                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1142                 break;
1143         }
1144
1145         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1146
1147         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1148                 tg3_mdio_config_5785(tp);
1149
1150         return 0;
1151 }
1152
1153 static void tg3_mdio_fini(struct tg3 *tp)
1154 {
1155         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1156                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1157                 mdiobus_unregister(tp->mdio_bus);
1158                 mdiobus_free(tp->mdio_bus);
1159         }
1160 }
1161
1162 /* tp->lock is held. */
1163 static inline void tg3_generate_fw_event(struct tg3 *tp)
1164 {
1165         u32 val;
1166
1167         val = tr32(GRC_RX_CPU_EVENT);
1168         val |= GRC_RX_CPU_DRIVER_EVENT;
1169         tw32_f(GRC_RX_CPU_EVENT, val);
1170
1171         tp->last_event_jiffies = jiffies;
1172 }
1173
1174 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1175
1176 /* tp->lock is held. */
1177 static void tg3_wait_for_event_ack(struct tg3 *tp)
1178 {
1179         int i;
1180         unsigned int delay_cnt;
1181         long time_remain;
1182
1183         /* If enough time has passed, no wait is necessary. */
1184         time_remain = (long)(tp->last_event_jiffies + 1 +
1185                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1186                       (long)jiffies;
1187         if (time_remain < 0)
1188                 return;
1189
1190         /* Check if we can shorten the wait time. */
1191         delay_cnt = jiffies_to_usecs(time_remain);
1192         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1193                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1194         delay_cnt = (delay_cnt >> 3) + 1;
1195
1196         for (i = 0; i < delay_cnt; i++) {
1197                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1198                         break;
1199                 udelay(8);
1200         }
1201 }
1202
1203 /* tp->lock is held. */
1204 static void tg3_ump_link_report(struct tg3 *tp)
1205 {
1206         u32 reg;
1207         u32 val;
1208
1209         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1210             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1211                 return;
1212
1213         tg3_wait_for_event_ack(tp);
1214
1215         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1216
1217         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1218
1219         val = 0;
1220         if (!tg3_readphy(tp, MII_BMCR, &reg))
1221                 val = reg << 16;
1222         if (!tg3_readphy(tp, MII_BMSR, &reg))
1223                 val |= (reg & 0xffff);
1224         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1225
1226         val = 0;
1227         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1228                 val = reg << 16;
1229         if (!tg3_readphy(tp, MII_LPA, &reg))
1230                 val |= (reg & 0xffff);
1231         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1232
1233         val = 0;
1234         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1235                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1236                         val = reg << 16;
1237                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1238                         val |= (reg & 0xffff);
1239         }
1240         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1241
1242         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1243                 val = reg << 16;
1244         else
1245                 val = 0;
1246         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1247
1248         tg3_generate_fw_event(tp);
1249 }
1250
1251 static void tg3_link_report(struct tg3 *tp)
1252 {
1253         if (!netif_carrier_ok(tp->dev)) {
1254                 netif_info(tp, link, tp->dev, "Link is down\n");
1255                 tg3_ump_link_report(tp);
1256         } else if (netif_msg_link(tp)) {
1257                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1258                             (tp->link_config.active_speed == SPEED_1000 ?
1259                              1000 :
1260                              (tp->link_config.active_speed == SPEED_100 ?
1261                               100 : 10)),
1262                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1263                              "full" : "half"));
1264
1265                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1266                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1267                             "on" : "off",
1268                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1269                             "on" : "off");
1270                 tg3_ump_link_report(tp);
1271         }
1272 }
1273
1274 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1275 {
1276         u16 miireg;
1277
1278         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1279                 miireg = ADVERTISE_PAUSE_CAP;
1280         else if (flow_ctrl & FLOW_CTRL_TX)
1281                 miireg = ADVERTISE_PAUSE_ASYM;
1282         else if (flow_ctrl & FLOW_CTRL_RX)
1283                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1284         else
1285                 miireg = 0;
1286
1287         return miireg;
1288 }
1289
1290 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1291 {
1292         u16 miireg;
1293
1294         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1295                 miireg = ADVERTISE_1000XPAUSE;
1296         else if (flow_ctrl & FLOW_CTRL_TX)
1297                 miireg = ADVERTISE_1000XPSE_ASYM;
1298         else if (flow_ctrl & FLOW_CTRL_RX)
1299                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1300         else
1301                 miireg = 0;
1302
1303         return miireg;
1304 }
1305
1306 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1307 {
1308         u8 cap = 0;
1309
1310         if (lcladv & ADVERTISE_1000XPAUSE) {
1311                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1312                         if (rmtadv & LPA_1000XPAUSE)
1313                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1314                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1315                                 cap = FLOW_CTRL_RX;
1316                 } else {
1317                         if (rmtadv & LPA_1000XPAUSE)
1318                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1319                 }
1320         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1321                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1322                         cap = FLOW_CTRL_TX;
1323         }
1324
1325         return cap;
1326 }
1327
1328 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1329 {
1330         u8 autoneg;
1331         u8 flowctrl = 0;
1332         u32 old_rx_mode = tp->rx_mode;
1333         u32 old_tx_mode = tp->tx_mode;
1334
1335         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1336                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1337         else
1338                 autoneg = tp->link_config.autoneg;
1339
1340         if (autoneg == AUTONEG_ENABLE &&
1341             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1342                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1343                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1344                 else
1345                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1346         } else
1347                 flowctrl = tp->link_config.flowctrl;
1348
1349         tp->link_config.active_flowctrl = flowctrl;
1350
1351         if (flowctrl & FLOW_CTRL_RX)
1352                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1353         else
1354                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1355
1356         if (old_rx_mode != tp->rx_mode)
1357                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1358
1359         if (flowctrl & FLOW_CTRL_TX)
1360                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1361         else
1362                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1363
1364         if (old_tx_mode != tp->tx_mode)
1365                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1366 }
1367
1368 static void tg3_adjust_link(struct net_device *dev)
1369 {
1370         u8 oldflowctrl, linkmesg = 0;
1371         u32 mac_mode, lcl_adv, rmt_adv;
1372         struct tg3 *tp = netdev_priv(dev);
1373         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1374
1375         spin_lock_bh(&tp->lock);
1376
1377         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1378                                     MAC_MODE_HALF_DUPLEX);
1379
1380         oldflowctrl = tp->link_config.active_flowctrl;
1381
1382         if (phydev->link) {
1383                 lcl_adv = 0;
1384                 rmt_adv = 0;
1385
1386                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1387                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1388                 else if (phydev->speed == SPEED_1000 ||
1389                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1390                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1391                 else
1392                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1393
1394                 if (phydev->duplex == DUPLEX_HALF)
1395                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1396                 else {
1397                         lcl_adv = tg3_advert_flowctrl_1000T(
1398                                   tp->link_config.flowctrl);
1399
1400                         if (phydev->pause)
1401                                 rmt_adv = LPA_PAUSE_CAP;
1402                         if (phydev->asym_pause)
1403                                 rmt_adv |= LPA_PAUSE_ASYM;
1404                 }
1405
1406                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1407         } else
1408                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1409
1410         if (mac_mode != tp->mac_mode) {
1411                 tp->mac_mode = mac_mode;
1412                 tw32_f(MAC_MODE, tp->mac_mode);
1413                 udelay(40);
1414         }
1415
1416         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1417                 if (phydev->speed == SPEED_10)
1418                         tw32(MAC_MI_STAT,
1419                              MAC_MI_STAT_10MBPS_MODE |
1420                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1421                 else
1422                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1423         }
1424
1425         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1426                 tw32(MAC_TX_LENGTHS,
1427                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1428                       (6 << TX_LENGTHS_IPG_SHIFT) |
1429                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1430         else
1431                 tw32(MAC_TX_LENGTHS,
1432                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1433                       (6 << TX_LENGTHS_IPG_SHIFT) |
1434                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1435
1436         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1437             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1438             phydev->speed != tp->link_config.active_speed ||
1439             phydev->duplex != tp->link_config.active_duplex ||
1440             oldflowctrl != tp->link_config.active_flowctrl)
1441                 linkmesg = 1;
1442
1443         tp->link_config.active_speed = phydev->speed;
1444         tp->link_config.active_duplex = phydev->duplex;
1445
1446         spin_unlock_bh(&tp->lock);
1447
1448         if (linkmesg)
1449                 tg3_link_report(tp);
1450 }
1451
1452 static int tg3_phy_init(struct tg3 *tp)
1453 {
1454         struct phy_device *phydev;
1455
1456         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1457                 return 0;
1458
1459         /* Bring the PHY back to a known state. */
1460         tg3_bmcr_reset(tp);
1461
1462         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1463
1464         /* Attach the MAC to the PHY. */
1465         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1466                              phydev->dev_flags, phydev->interface);
1467         if (IS_ERR(phydev)) {
1468                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1469                 return PTR_ERR(phydev);
1470         }
1471
1472         /* Mask with MAC supported features. */
1473         switch (phydev->interface) {
1474         case PHY_INTERFACE_MODE_GMII:
1475         case PHY_INTERFACE_MODE_RGMII:
1476                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1477                         phydev->supported &= (PHY_GBIT_FEATURES |
1478                                               SUPPORTED_Pause |
1479                                               SUPPORTED_Asym_Pause);
1480                         break;
1481                 }
1482                 /* fallthru */
1483         case PHY_INTERFACE_MODE_MII:
1484                 phydev->supported &= (PHY_BASIC_FEATURES |
1485                                       SUPPORTED_Pause |
1486                                       SUPPORTED_Asym_Pause);
1487                 break;
1488         default:
1489                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1490                 return -EINVAL;
1491         }
1492
1493         tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1494
1495         phydev->advertising = phydev->supported;
1496
1497         return 0;
1498 }
1499
1500 static void tg3_phy_start(struct tg3 *tp)
1501 {
1502         struct phy_device *phydev;
1503
1504         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1505                 return;
1506
1507         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1508
1509         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1510                 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1511                 phydev->speed = tp->link_config.orig_speed;
1512                 phydev->duplex = tp->link_config.orig_duplex;
1513                 phydev->autoneg = tp->link_config.orig_autoneg;
1514                 phydev->advertising = tp->link_config.orig_advertising;
1515         }
1516
1517         phy_start(phydev);
1518
1519         phy_start_aneg(phydev);
1520 }
1521
1522 static void tg3_phy_stop(struct tg3 *tp)
1523 {
1524         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1525                 return;
1526
1527         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1528 }
1529
1530 static void tg3_phy_fini(struct tg3 *tp)
1531 {
1532         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1533                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1534                 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1535         }
1536 }
1537
1538 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1539 {
1540         int err;
1541
1542         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1543         if (!err)
1544                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1545
1546         return err;
1547 }
1548
1549 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1550 {
1551         u32 phytest;
1552
1553         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1554                 u32 phy;
1555
1556                 tg3_writephy(tp, MII_TG3_FET_TEST,
1557                              phytest | MII_TG3_FET_SHADOW_EN);
1558                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1559                         if (enable)
1560                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1561                         else
1562                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1563                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1564                 }
1565                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1566         }
1567 }
1568
1569 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1570 {
1571         u32 reg;
1572
1573         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1574             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1575               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1576              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1577                 return;
1578
1579         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1580                 tg3_phy_fet_toggle_apd(tp, enable);
1581                 return;
1582         }
1583
1584         reg = MII_TG3_MISC_SHDW_WREN |
1585               MII_TG3_MISC_SHDW_SCR5_SEL |
1586               MII_TG3_MISC_SHDW_SCR5_LPED |
1587               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1588               MII_TG3_MISC_SHDW_SCR5_SDTL |
1589               MII_TG3_MISC_SHDW_SCR5_C125OE;
1590         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1591                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1592
1593         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1594
1595
1596         reg = MII_TG3_MISC_SHDW_WREN |
1597               MII_TG3_MISC_SHDW_APD_SEL |
1598               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1599         if (enable)
1600                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1601
1602         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1603 }
1604
1605 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1606 {
1607         u32 phy;
1608
1609         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1610             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1611                 return;
1612
1613         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1614                 u32 ephy;
1615
1616                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1617                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1618
1619                         tg3_writephy(tp, MII_TG3_FET_TEST,
1620                                      ephy | MII_TG3_FET_SHADOW_EN);
1621                         if (!tg3_readphy(tp, reg, &phy)) {
1622                                 if (enable)
1623                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1624                                 else
1625                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1626                                 tg3_writephy(tp, reg, phy);
1627                         }
1628                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1629                 }
1630         } else {
1631                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1632                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1633                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1634                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1635                         if (enable)
1636                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1637                         else
1638                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1639                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1640                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1641                 }
1642         }
1643 }
1644
1645 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1646 {
1647         u32 val;
1648
1649         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1650                 return;
1651
1652         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1653             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1654                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1655                              (val | (1 << 15) | (1 << 4)));
1656 }
1657
1658 static void tg3_phy_apply_otp(struct tg3 *tp)
1659 {
1660         u32 otp, phy;
1661
1662         if (!tp->phy_otp)
1663                 return;
1664
1665         otp = tp->phy_otp;
1666
1667         /* Enable SM_DSP clock and tx 6dB coding. */
1668         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1669               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1670               MII_TG3_AUXCTL_ACTL_TX_6DB;
1671         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1672
1673         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1674         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1675         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1676
1677         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1678               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1679         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1680
1681         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1682         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1683         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1684
1685         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1686         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1687
1688         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1689         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1690
1691         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1692               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1693         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1694
1695         /* Turn off SM_DSP clock. */
1696         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1697               MII_TG3_AUXCTL_ACTL_TX_6DB;
1698         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1699 }
1700
1701 static int tg3_wait_macro_done(struct tg3 *tp)
1702 {
1703         int limit = 100;
1704
1705         while (limit--) {
1706                 u32 tmp32;
1707
1708                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1709                         if ((tmp32 & 0x1000) == 0)
1710                                 break;
1711                 }
1712         }
1713         if (limit < 0)
1714                 return -EBUSY;
1715
1716         return 0;
1717 }
1718
1719 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1720 {
1721         static const u32 test_pat[4][6] = {
1722         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1723         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1724         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1725         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1726         };
1727         int chan;
1728
1729         for (chan = 0; chan < 4; chan++) {
1730                 int i;
1731
1732                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1733                              (chan * 0x2000) | 0x0200);
1734                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1735
1736                 for (i = 0; i < 6; i++)
1737                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1738                                      test_pat[chan][i]);
1739
1740                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1741                 if (tg3_wait_macro_done(tp)) {
1742                         *resetp = 1;
1743                         return -EBUSY;
1744                 }
1745
1746                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1747                              (chan * 0x2000) | 0x0200);
1748                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1749                 if (tg3_wait_macro_done(tp)) {
1750                         *resetp = 1;
1751                         return -EBUSY;
1752                 }
1753
1754                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1755                 if (tg3_wait_macro_done(tp)) {
1756                         *resetp = 1;
1757                         return -EBUSY;
1758                 }
1759
1760                 for (i = 0; i < 6; i += 2) {
1761                         u32 low, high;
1762
1763                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1764                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1765                             tg3_wait_macro_done(tp)) {
1766                                 *resetp = 1;
1767                                 return -EBUSY;
1768                         }
1769                         low &= 0x7fff;
1770                         high &= 0x000f;
1771                         if (low != test_pat[chan][i] ||
1772                             high != test_pat[chan][i+1]) {
1773                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1774                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1775                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1776
1777                                 return -EBUSY;
1778                         }
1779                 }
1780         }
1781
1782         return 0;
1783 }
1784
1785 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1786 {
1787         int chan;
1788
1789         for (chan = 0; chan < 4; chan++) {
1790                 int i;
1791
1792                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1793                              (chan * 0x2000) | 0x0200);
1794                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1795                 for (i = 0; i < 6; i++)
1796                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1797                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1798                 if (tg3_wait_macro_done(tp))
1799                         return -EBUSY;
1800         }
1801
1802         return 0;
1803 }
1804
1805 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1806 {
1807         u32 reg32, phy9_orig;
1808         int retries, do_phy_reset, err;
1809
1810         retries = 10;
1811         do_phy_reset = 1;
1812         do {
1813                 if (do_phy_reset) {
1814                         err = tg3_bmcr_reset(tp);
1815                         if (err)
1816                                 return err;
1817                         do_phy_reset = 0;
1818                 }
1819
1820                 /* Disable transmitter and interrupt.  */
1821                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1822                         continue;
1823
1824                 reg32 |= 0x3000;
1825                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1826
1827                 /* Set full-duplex, 1000 mbps.  */
1828                 tg3_writephy(tp, MII_BMCR,
1829                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1830
1831                 /* Set to master mode.  */
1832                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1833                         continue;
1834
1835                 tg3_writephy(tp, MII_TG3_CTRL,
1836                              (MII_TG3_CTRL_AS_MASTER |
1837                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1838
1839                 /* Enable SM_DSP_CLOCK and 6dB.  */
1840                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1841
1842                 /* Block the PHY control access.  */
1843                 tg3_phydsp_write(tp, 0x8005, 0x0800);
1844
1845                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1846                 if (!err)
1847                         break;
1848         } while (--retries);
1849
1850         err = tg3_phy_reset_chanpat(tp);
1851         if (err)
1852                 return err;
1853
1854         tg3_phydsp_write(tp, 0x8005, 0x0000);
1855
1856         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1857         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1858
1859         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1860             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1861                 /* Set Extended packet length bit for jumbo frames */
1862                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1863         } else {
1864                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1865         }
1866
1867         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1868
1869         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1870                 reg32 &= ~0x3000;
1871                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1872         } else if (!err)
1873                 err = -EBUSY;
1874
1875         return err;
1876 }
1877
1878 /* This will reset the tigon3 PHY if there is no valid
1879  * link unless the FORCE argument is non-zero.
1880  */
1881 static int tg3_phy_reset(struct tg3 *tp)
1882 {
1883         u32 val, cpmuctrl;
1884         int err;
1885
1886         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1887                 val = tr32(GRC_MISC_CFG);
1888                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1889                 udelay(40);
1890         }
1891         err  = tg3_readphy(tp, MII_BMSR, &val);
1892         err |= tg3_readphy(tp, MII_BMSR, &val);
1893         if (err != 0)
1894                 return -EBUSY;
1895
1896         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1897                 netif_carrier_off(tp->dev);
1898                 tg3_link_report(tp);
1899         }
1900
1901         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1902             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1903             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1904                 err = tg3_phy_reset_5703_4_5(tp);
1905                 if (err)
1906                         return err;
1907                 goto out;
1908         }
1909
1910         cpmuctrl = 0;
1911         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1912             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1913                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1914                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1915                         tw32(TG3_CPMU_CTRL,
1916                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1917         }
1918
1919         err = tg3_bmcr_reset(tp);
1920         if (err)
1921                 return err;
1922
1923         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1924                 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1925                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
1926
1927                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1928         }
1929
1930         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1931             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1932                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1933                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1934                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1935                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1936                         udelay(40);
1937                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1938                 }
1939         }
1940
1941         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1942              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1943             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
1944                 return 0;
1945
1946         tg3_phy_apply_otp(tp);
1947
1948         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
1949                 tg3_phy_toggle_apd(tp, true);
1950         else
1951                 tg3_phy_toggle_apd(tp, false);
1952
1953 out:
1954         if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
1955                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1956                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
1957                 tg3_phydsp_write(tp, 0x000a, 0x0323);
1958                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1959         }
1960         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
1961                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
1962                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
1963         }
1964         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
1965                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1966                 tg3_phydsp_write(tp, 0x000a, 0x310b);
1967                 tg3_phydsp_write(tp, 0x201f, 0x9506);
1968                 tg3_phydsp_write(tp, 0x401f, 0x14e2);
1969                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1970         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
1971                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1972                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1973                 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
1974                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1975                         tg3_writephy(tp, MII_TG3_TEST1,
1976                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1977                 } else
1978                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1979                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1980         }
1981         /* Set Extended packet length bit (bit 14) on all chips that */
1982         /* support jumbo frames */
1983         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1984                 /* Cannot do read-modify-write on 5401 */
1985                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1986         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1987                 /* Set bit 14 with read-modify-write to preserve other bits */
1988                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1989                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1990                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000);
1991         }
1992
1993         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1994          * jumbo frames transmission.
1995          */
1996         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1997                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
1998                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
1999                                      val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2000         }
2001
2002         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2003                 /* adjust output voltage */
2004                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2005         }
2006
2007         tg3_phy_toggle_automdix(tp, 1);
2008         tg3_phy_set_wirespeed(tp);
2009         return 0;
2010 }
2011
2012 static void tg3_frob_aux_power(struct tg3 *tp)
2013 {
2014         struct tg3 *tp_peer = tp;
2015
2016         /* The GPIOs do something completely different on 57765. */
2017         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2018             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2019             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2020                 return;
2021
2022         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2023             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2024             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2025                 struct net_device *dev_peer;
2026
2027                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2028                 /* remove_one() may have been run on the peer. */
2029                 if (!dev_peer)
2030                         tp_peer = tp;
2031                 else
2032                         tp_peer = netdev_priv(dev_peer);
2033         }
2034
2035         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2036             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2037             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2038             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2039                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2040                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2041                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2042                                     (GRC_LCLCTRL_GPIO_OE0 |
2043                                      GRC_LCLCTRL_GPIO_OE1 |
2044                                      GRC_LCLCTRL_GPIO_OE2 |
2045                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2046                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2047                                     100);
2048                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2049                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2050                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2051                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2052                                              GRC_LCLCTRL_GPIO_OE1 |
2053                                              GRC_LCLCTRL_GPIO_OE2 |
2054                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2055                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2056                                              tp->grc_local_ctrl;
2057                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2058
2059                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2060                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2061
2062                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2063                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2064                 } else {
2065                         u32 no_gpio2;
2066                         u32 grc_local_ctrl = 0;
2067
2068                         if (tp_peer != tp &&
2069                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2070                                 return;
2071
2072                         /* Workaround to prevent overdrawing Amps. */
2073                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2074                             ASIC_REV_5714) {
2075                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2076                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2077                                             grc_local_ctrl, 100);
2078                         }
2079
2080                         /* On 5753 and variants, GPIO2 cannot be used. */
2081                         no_gpio2 = tp->nic_sram_data_cfg &
2082                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2083
2084                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2085                                          GRC_LCLCTRL_GPIO_OE1 |
2086                                          GRC_LCLCTRL_GPIO_OE2 |
2087                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2088                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2089                         if (no_gpio2) {
2090                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2091                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2092                         }
2093                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2094                                                     grc_local_ctrl, 100);
2095
2096                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2097
2098                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2099                                                     grc_local_ctrl, 100);
2100
2101                         if (!no_gpio2) {
2102                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2103                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2104                                             grc_local_ctrl, 100);
2105                         }
2106                 }
2107         } else {
2108                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2109                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2110                         if (tp_peer != tp &&
2111                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2112                                 return;
2113
2114                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2115                                     (GRC_LCLCTRL_GPIO_OE1 |
2116                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2117
2118                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2119                                     GRC_LCLCTRL_GPIO_OE1, 100);
2120
2121                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2122                                     (GRC_LCLCTRL_GPIO_OE1 |
2123                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2124                 }
2125         }
2126 }
2127
2128 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2129 {
2130         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2131                 return 1;
2132         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2133                 if (speed != SPEED_10)
2134                         return 1;
2135         } else if (speed == SPEED_10)
2136                 return 1;
2137
2138         return 0;
2139 }
2140
2141 static int tg3_setup_phy(struct tg3 *, int);
2142
2143 #define RESET_KIND_SHUTDOWN     0
2144 #define RESET_KIND_INIT         1
2145 #define RESET_KIND_SUSPEND      2
2146
2147 static void tg3_write_sig_post_reset(struct tg3 *, int);
2148 static int tg3_halt_cpu(struct tg3 *, u32);
2149
2150 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2151 {
2152         u32 val;
2153
2154         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2155                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2156                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2157                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2158
2159                         sg_dig_ctrl |=
2160                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2161                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2162                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2163                 }
2164                 return;
2165         }
2166
2167         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2168                 tg3_bmcr_reset(tp);
2169                 val = tr32(GRC_MISC_CFG);
2170                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2171                 udelay(40);
2172                 return;
2173         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2174                 u32 phytest;
2175                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2176                         u32 phy;
2177
2178                         tg3_writephy(tp, MII_ADVERTISE, 0);
2179                         tg3_writephy(tp, MII_BMCR,
2180                                      BMCR_ANENABLE | BMCR_ANRESTART);
2181
2182                         tg3_writephy(tp, MII_TG3_FET_TEST,
2183                                      phytest | MII_TG3_FET_SHADOW_EN);
2184                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2185                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2186                                 tg3_writephy(tp,
2187                                              MII_TG3_FET_SHDW_AUXMODE4,
2188                                              phy);
2189                         }
2190                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2191                 }
2192                 return;
2193         } else if (do_low_power) {
2194                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2195                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2196
2197                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2198                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2199                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2200                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2201                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2202         }
2203
2204         /* The PHY should not be powered down on some chips because
2205          * of bugs.
2206          */
2207         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2208             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2209             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2210              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2211                 return;
2212
2213         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2214             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2215                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2216                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2217                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2218                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2219         }
2220
2221         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2222 }
2223
2224 /* tp->lock is held. */
2225 static int tg3_nvram_lock(struct tg3 *tp)
2226 {
2227         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2228                 int i;
2229
2230                 if (tp->nvram_lock_cnt == 0) {
2231                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2232                         for (i = 0; i < 8000; i++) {
2233                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2234                                         break;
2235                                 udelay(20);
2236                         }
2237                         if (i == 8000) {
2238                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2239                                 return -ENODEV;
2240                         }
2241                 }
2242                 tp->nvram_lock_cnt++;
2243         }
2244         return 0;
2245 }
2246
2247 /* tp->lock is held. */
2248 static void tg3_nvram_unlock(struct tg3 *tp)
2249 {
2250         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2251                 if (tp->nvram_lock_cnt > 0)
2252                         tp->nvram_lock_cnt--;
2253                 if (tp->nvram_lock_cnt == 0)
2254                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2255         }
2256 }
2257
2258 /* tp->lock is held. */
2259 static void tg3_enable_nvram_access(struct tg3 *tp)
2260 {
2261         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2262             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2263                 u32 nvaccess = tr32(NVRAM_ACCESS);
2264
2265                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2266         }
2267 }
2268
2269 /* tp->lock is held. */
2270 static void tg3_disable_nvram_access(struct tg3 *tp)
2271 {
2272         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2273             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2274                 u32 nvaccess = tr32(NVRAM_ACCESS);
2275
2276                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2277         }
2278 }
2279
2280 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2281                                         u32 offset, u32 *val)
2282 {
2283         u32 tmp;
2284         int i;
2285
2286         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2287                 return -EINVAL;
2288
2289         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2290                                         EEPROM_ADDR_DEVID_MASK |
2291                                         EEPROM_ADDR_READ);
2292         tw32(GRC_EEPROM_ADDR,
2293              tmp |
2294              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2295              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2296               EEPROM_ADDR_ADDR_MASK) |
2297              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2298
2299         for (i = 0; i < 1000; i++) {
2300                 tmp = tr32(GRC_EEPROM_ADDR);
2301
2302                 if (tmp & EEPROM_ADDR_COMPLETE)
2303                         break;
2304                 msleep(1);
2305         }
2306         if (!(tmp & EEPROM_ADDR_COMPLETE))
2307                 return -EBUSY;
2308
2309         tmp = tr32(GRC_EEPROM_DATA);
2310
2311         /*
2312          * The data will always be opposite the native endian
2313          * format.  Perform a blind byteswap to compensate.
2314          */
2315         *val = swab32(tmp);
2316
2317         return 0;
2318 }
2319
2320 #define NVRAM_CMD_TIMEOUT 10000
2321
2322 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2323 {
2324         int i;
2325
2326         tw32(NVRAM_CMD, nvram_cmd);
2327         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2328                 udelay(10);
2329                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2330                         udelay(10);
2331                         break;
2332                 }
2333         }
2334
2335         if (i == NVRAM_CMD_TIMEOUT)
2336                 return -EBUSY;
2337
2338         return 0;
2339 }
2340
2341 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2342 {
2343         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2344             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2345             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2346            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2347             (tp->nvram_jedecnum == JEDEC_ATMEL))
2348
2349                 addr = ((addr / tp->nvram_pagesize) <<
2350                         ATMEL_AT45DB0X1B_PAGE_POS) +
2351                        (addr % tp->nvram_pagesize);
2352
2353         return addr;
2354 }
2355
2356 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2357 {
2358         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2359             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2360             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2361            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2362             (tp->nvram_jedecnum == JEDEC_ATMEL))
2363
2364                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2365                         tp->nvram_pagesize) +
2366                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2367
2368         return addr;
2369 }
2370
2371 /* NOTE: Data read in from NVRAM is byteswapped according to
2372  * the byteswapping settings for all other register accesses.
2373  * tg3 devices are BE devices, so on a BE machine, the data
2374  * returned will be exactly as it is seen in NVRAM.  On a LE
2375  * machine, the 32-bit value will be byteswapped.
2376  */
2377 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2378 {
2379         int ret;
2380
2381         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2382                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2383
2384         offset = tg3_nvram_phys_addr(tp, offset);
2385
2386         if (offset > NVRAM_ADDR_MSK)
2387                 return -EINVAL;
2388
2389         ret = tg3_nvram_lock(tp);
2390         if (ret)
2391                 return ret;
2392
2393         tg3_enable_nvram_access(tp);
2394
2395         tw32(NVRAM_ADDR, offset);
2396         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2397                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2398
2399         if (ret == 0)
2400                 *val = tr32(NVRAM_RDDATA);
2401
2402         tg3_disable_nvram_access(tp);
2403
2404         tg3_nvram_unlock(tp);
2405
2406         return ret;
2407 }
2408
2409 /* Ensures NVRAM data is in bytestream format. */
2410 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2411 {
2412         u32 v;
2413         int res = tg3_nvram_read(tp, offset, &v);
2414         if (!res)
2415                 *val = cpu_to_be32(v);
2416         return res;
2417 }
2418
2419 /* tp->lock is held. */
2420 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2421 {
2422         u32 addr_high, addr_low;
2423         int i;
2424
2425         addr_high = ((tp->dev->dev_addr[0] << 8) |
2426                      tp->dev->dev_addr[1]);
2427         addr_low = ((tp->dev->dev_addr[2] << 24) |
2428                     (tp->dev->dev_addr[3] << 16) |
2429                     (tp->dev->dev_addr[4] <<  8) |
2430                     (tp->dev->dev_addr[5] <<  0));
2431         for (i = 0; i < 4; i++) {
2432                 if (i == 1 && skip_mac_1)
2433                         continue;
2434                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2435                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2436         }
2437
2438         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2439             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2440                 for (i = 0; i < 12; i++) {
2441                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2442                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2443                 }
2444         }
2445
2446         addr_high = (tp->dev->dev_addr[0] +
2447                      tp->dev->dev_addr[1] +
2448                      tp->dev->dev_addr[2] +
2449                      tp->dev->dev_addr[3] +
2450                      tp->dev->dev_addr[4] +
2451                      tp->dev->dev_addr[5]) &
2452                 TX_BACKOFF_SEED_MASK;
2453         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2454 }
2455
2456 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2457 {
2458         u32 misc_host_ctrl;
2459         bool device_should_wake, do_low_power;
2460
2461         /* Make sure register accesses (indirect or otherwise)
2462          * will function correctly.
2463          */
2464         pci_write_config_dword(tp->pdev,
2465                                TG3PCI_MISC_HOST_CTRL,
2466                                tp->misc_host_ctrl);
2467
2468         switch (state) {
2469         case PCI_D0:
2470                 pci_enable_wake(tp->pdev, state, false);
2471                 pci_set_power_state(tp->pdev, PCI_D0);
2472
2473                 /* Switch out of Vaux if it is a NIC */
2474                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2475                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2476
2477                 return 0;
2478
2479         case PCI_D1:
2480         case PCI_D2:
2481         case PCI_D3hot:
2482                 break;
2483
2484         default:
2485                 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2486                            state);
2487                 return -EINVAL;
2488         }
2489
2490         /* Restore the CLKREQ setting. */
2491         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2492                 u16 lnkctl;
2493
2494                 pci_read_config_word(tp->pdev,
2495                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2496                                      &lnkctl);
2497                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2498                 pci_write_config_word(tp->pdev,
2499                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2500                                       lnkctl);
2501         }
2502
2503         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2504         tw32(TG3PCI_MISC_HOST_CTRL,
2505              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2506
2507         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2508                              device_may_wakeup(&tp->pdev->dev) &&
2509                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2510
2511         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2512                 do_low_power = false;
2513                 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2514                     !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2515                         struct phy_device *phydev;
2516                         u32 phyid, advertising;
2517
2518                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2519
2520                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2521
2522                         tp->link_config.orig_speed = phydev->speed;
2523                         tp->link_config.orig_duplex = phydev->duplex;
2524                         tp->link_config.orig_autoneg = phydev->autoneg;
2525                         tp->link_config.orig_advertising = phydev->advertising;
2526
2527                         advertising = ADVERTISED_TP |
2528                                       ADVERTISED_Pause |
2529                                       ADVERTISED_Autoneg |
2530                                       ADVERTISED_10baseT_Half;
2531
2532                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2533                             device_should_wake) {
2534                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2535                                         advertising |=
2536                                                 ADVERTISED_100baseT_Half |
2537                                                 ADVERTISED_100baseT_Full |
2538                                                 ADVERTISED_10baseT_Full;
2539                                 else
2540                                         advertising |= ADVERTISED_10baseT_Full;
2541                         }
2542
2543                         phydev->advertising = advertising;
2544
2545                         phy_start_aneg(phydev);
2546
2547                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2548                         if (phyid != PHY_ID_BCMAC131) {
2549                                 phyid &= PHY_BCM_OUI_MASK;
2550                                 if (phyid == PHY_BCM_OUI_1 ||
2551                                     phyid == PHY_BCM_OUI_2 ||
2552                                     phyid == PHY_BCM_OUI_3)
2553                                         do_low_power = true;
2554                         }
2555                 }
2556         } else {
2557                 do_low_power = true;
2558
2559                 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2560                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2561                         tp->link_config.orig_speed = tp->link_config.speed;
2562                         tp->link_config.orig_duplex = tp->link_config.duplex;
2563                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2564                 }
2565
2566                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2567                         tp->link_config.speed = SPEED_10;
2568                         tp->link_config.duplex = DUPLEX_HALF;
2569                         tp->link_config.autoneg = AUTONEG_ENABLE;
2570                         tg3_setup_phy(tp, 0);
2571                 }
2572         }
2573
2574         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2575                 u32 val;
2576
2577                 val = tr32(GRC_VCPU_EXT_CTRL);
2578                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2579         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2580                 int i;
2581                 u32 val;
2582
2583                 for (i = 0; i < 200; i++) {
2584                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2585                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2586                                 break;
2587                         msleep(1);
2588                 }
2589         }
2590         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2591                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2592                                                      WOL_DRV_STATE_SHUTDOWN |
2593                                                      WOL_DRV_WOL |
2594                                                      WOL_SET_MAGIC_PKT);
2595
2596         if (device_should_wake) {
2597                 u32 mac_mode;
2598
2599                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2600                         if (do_low_power) {
2601                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2602                                 udelay(40);
2603                         }
2604
2605                         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2606                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2607                         else
2608                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2609
2610                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2611                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2612                             ASIC_REV_5700) {
2613                                 u32 speed = (tp->tg3_flags &
2614                                              TG3_FLAG_WOL_SPEED_100MB) ?
2615                                              SPEED_100 : SPEED_10;
2616                                 if (tg3_5700_link_polarity(tp, speed))
2617                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2618                                 else
2619                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2620                         }
2621                 } else {
2622                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2623                 }
2624
2625                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2626                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2627
2628                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2629                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2630                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2631                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2632                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2633                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2634
2635                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2636                         mac_mode |= tp->mac_mode &
2637                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2638                         if (mac_mode & MAC_MODE_APE_TX_EN)
2639                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2640                 }
2641
2642                 tw32_f(MAC_MODE, mac_mode);
2643                 udelay(100);
2644
2645                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2646                 udelay(10);
2647         }
2648
2649         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2650             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2651              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2652                 u32 base_val;
2653
2654                 base_val = tp->pci_clock_ctrl;
2655                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2656                              CLOCK_CTRL_TXCLK_DISABLE);
2657
2658                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2659                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2660         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2661                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2662                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2663                 /* do nothing */
2664         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2665                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2666                 u32 newbits1, newbits2;
2667
2668                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2669                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2670                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2671                                     CLOCK_CTRL_TXCLK_DISABLE |
2672                                     CLOCK_CTRL_ALTCLK);
2673                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2674                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2675                         newbits1 = CLOCK_CTRL_625_CORE;
2676                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2677                 } else {
2678                         newbits1 = CLOCK_CTRL_ALTCLK;
2679                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2680                 }
2681
2682                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2683                             40);
2684
2685                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2686                             40);
2687
2688                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2689                         u32 newbits3;
2690
2691                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2692                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2693                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2694                                             CLOCK_CTRL_TXCLK_DISABLE |
2695                                             CLOCK_CTRL_44MHZ_CORE);
2696                         } else {
2697                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2698                         }
2699
2700                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2701                                     tp->pci_clock_ctrl | newbits3, 40);
2702                 }
2703         }
2704
2705         if (!(device_should_wake) &&
2706             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2707                 tg3_power_down_phy(tp, do_low_power);
2708
2709         tg3_frob_aux_power(tp);
2710
2711         /* Workaround for unstable PLL clock */
2712         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2713             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2714                 u32 val = tr32(0x7d00);
2715
2716                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2717                 tw32(0x7d00, val);
2718                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2719                         int err;
2720
2721                         err = tg3_nvram_lock(tp);
2722                         tg3_halt_cpu(tp, RX_CPU_BASE);
2723                         if (!err)
2724                                 tg3_nvram_unlock(tp);
2725                 }
2726         }
2727
2728         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2729
2730         if (device_should_wake)
2731                 pci_enable_wake(tp->pdev, state, true);
2732
2733         /* Finally, set the new power state. */
2734         pci_set_power_state(tp->pdev, state);
2735
2736         return 0;
2737 }
2738
2739 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2740 {
2741         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2742         case MII_TG3_AUX_STAT_10HALF:
2743                 *speed = SPEED_10;
2744                 *duplex = DUPLEX_HALF;
2745                 break;
2746
2747         case MII_TG3_AUX_STAT_10FULL:
2748                 *speed = SPEED_10;
2749                 *duplex = DUPLEX_FULL;
2750                 break;
2751
2752         case MII_TG3_AUX_STAT_100HALF:
2753                 *speed = SPEED_100;
2754                 *duplex = DUPLEX_HALF;
2755                 break;
2756
2757         case MII_TG3_AUX_STAT_100FULL:
2758                 *speed = SPEED_100;
2759                 *duplex = DUPLEX_FULL;
2760                 break;
2761
2762         case MII_TG3_AUX_STAT_1000HALF:
2763                 *speed = SPEED_1000;
2764                 *duplex = DUPLEX_HALF;
2765                 break;
2766
2767         case MII_TG3_AUX_STAT_1000FULL:
2768                 *speed = SPEED_1000;
2769                 *duplex = DUPLEX_FULL;
2770                 break;
2771
2772         default:
2773                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2774                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2775                                  SPEED_10;
2776                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2777                                   DUPLEX_HALF;
2778                         break;
2779                 }
2780                 *speed = SPEED_INVALID;
2781                 *duplex = DUPLEX_INVALID;
2782                 break;
2783         }
2784 }
2785
2786 static void tg3_phy_copper_begin(struct tg3 *tp)
2787 {
2788         u32 new_adv;
2789         int i;
2790
2791         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2792                 /* Entering low power mode.  Disable gigabit and
2793                  * 100baseT advertisements.
2794                  */
2795                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2796
2797                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2798                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2799                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2800                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2801
2802                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2803         } else if (tp->link_config.speed == SPEED_INVALID) {
2804                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2805                         tp->link_config.advertising &=
2806                                 ~(ADVERTISED_1000baseT_Half |
2807                                   ADVERTISED_1000baseT_Full);
2808
2809                 new_adv = ADVERTISE_CSMA;
2810                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2811                         new_adv |= ADVERTISE_10HALF;
2812                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2813                         new_adv |= ADVERTISE_10FULL;
2814                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2815                         new_adv |= ADVERTISE_100HALF;
2816                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2817                         new_adv |= ADVERTISE_100FULL;
2818
2819                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2820
2821                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2822
2823                 if (tp->link_config.advertising &
2824                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2825                         new_adv = 0;
2826                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2827                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2828                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2829                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2830                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
2831                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2832                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2833                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2834                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2835                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2836                 } else {
2837                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2838                 }
2839         } else {
2840                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2841                 new_adv |= ADVERTISE_CSMA;
2842
2843                 /* Asking for a specific link mode. */
2844                 if (tp->link_config.speed == SPEED_1000) {
2845                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2846
2847                         if (tp->link_config.duplex == DUPLEX_FULL)
2848                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2849                         else
2850                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2851                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2852                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2853                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2854                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2855                 } else {
2856                         if (tp->link_config.speed == SPEED_100) {
2857                                 if (tp->link_config.duplex == DUPLEX_FULL)
2858                                         new_adv |= ADVERTISE_100FULL;
2859                                 else
2860                                         new_adv |= ADVERTISE_100HALF;
2861                         } else {
2862                                 if (tp->link_config.duplex == DUPLEX_FULL)
2863                                         new_adv |= ADVERTISE_10FULL;
2864                                 else
2865                                         new_adv |= ADVERTISE_10HALF;
2866                         }
2867                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2868
2869                         new_adv = 0;
2870                 }
2871
2872                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2873         }
2874
2875         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2876             tp->link_config.speed != SPEED_INVALID) {
2877                 u32 bmcr, orig_bmcr;
2878
2879                 tp->link_config.active_speed = tp->link_config.speed;
2880                 tp->link_config.active_duplex = tp->link_config.duplex;
2881
2882                 bmcr = 0;
2883                 switch (tp->link_config.speed) {
2884                 default:
2885                 case SPEED_10:
2886                         break;
2887
2888                 case SPEED_100:
2889                         bmcr |= BMCR_SPEED100;
2890                         break;
2891
2892                 case SPEED_1000:
2893                         bmcr |= TG3_BMCR_SPEED1000;
2894                         break;
2895                 }
2896
2897                 if (tp->link_config.duplex == DUPLEX_FULL)
2898                         bmcr |= BMCR_FULLDPLX;
2899
2900                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2901                     (bmcr != orig_bmcr)) {
2902                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2903                         for (i = 0; i < 1500; i++) {
2904                                 u32 tmp;
2905
2906                                 udelay(10);
2907                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2908                                     tg3_readphy(tp, MII_BMSR, &tmp))
2909                                         continue;
2910                                 if (!(tmp & BMSR_LSTATUS)) {
2911                                         udelay(40);
2912                                         break;
2913                                 }
2914                         }
2915                         tg3_writephy(tp, MII_BMCR, bmcr);
2916                         udelay(40);
2917                 }
2918         } else {
2919                 tg3_writephy(tp, MII_BMCR,
2920                              BMCR_ANENABLE | BMCR_ANRESTART);
2921         }
2922 }
2923
2924 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2925 {
2926         int err;
2927
2928         /* Turn off tap power management. */
2929         /* Set Extended packet length bit */
2930         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2931
2932         err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
2933         err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
2934         err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
2935         err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
2936         err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
2937
2938         udelay(40);
2939
2940         return err;
2941 }
2942
2943 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2944 {
2945         u32 adv_reg, all_mask = 0;
2946
2947         if (mask & ADVERTISED_10baseT_Half)
2948                 all_mask |= ADVERTISE_10HALF;
2949         if (mask & ADVERTISED_10baseT_Full)
2950                 all_mask |= ADVERTISE_10FULL;
2951         if (mask & ADVERTISED_100baseT_Half)
2952                 all_mask |= ADVERTISE_100HALF;
2953         if (mask & ADVERTISED_100baseT_Full)
2954                 all_mask |= ADVERTISE_100FULL;
2955
2956         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2957                 return 0;
2958
2959         if ((adv_reg & all_mask) != all_mask)
2960                 return 0;
2961         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
2962                 u32 tg3_ctrl;
2963
2964                 all_mask = 0;
2965                 if (mask & ADVERTISED_1000baseT_Half)
2966                         all_mask |= ADVERTISE_1000HALF;
2967                 if (mask & ADVERTISED_1000baseT_Full)
2968                         all_mask |= ADVERTISE_1000FULL;
2969
2970                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2971                         return 0;
2972
2973                 if ((tg3_ctrl & all_mask) != all_mask)
2974                         return 0;
2975         }
2976         return 1;
2977 }
2978
2979 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2980 {
2981         u32 curadv, reqadv;
2982
2983         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2984                 return 1;
2985
2986         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2987         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2988
2989         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2990                 if (curadv != reqadv)
2991                         return 0;
2992
2993                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2994                         tg3_readphy(tp, MII_LPA, rmtadv);
2995         } else {
2996                 /* Reprogram the advertisement register, even if it
2997                  * does not affect the current link.  If the link
2998                  * gets renegotiated in the future, we can save an
2999                  * additional renegotiation cycle by advertising
3000                  * it correctly in the first place.
3001                  */
3002                 if (curadv != reqadv) {
3003                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3004                                      ADVERTISE_PAUSE_ASYM);
3005                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3006                 }
3007         }
3008
3009         return 1;
3010 }
3011
3012 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3013 {
3014         int current_link_up;
3015         u32 bmsr, val;
3016         u32 lcl_adv, rmt_adv;
3017         u16 current_speed;
3018         u8 current_duplex;
3019         int i, err;
3020
3021         tw32(MAC_EVENT, 0);
3022
3023         tw32_f(MAC_STATUS,
3024              (MAC_STATUS_SYNC_CHANGED |
3025               MAC_STATUS_CFG_CHANGED |
3026               MAC_STATUS_MI_COMPLETION |
3027               MAC_STATUS_LNKSTATE_CHANGED));
3028         udelay(40);
3029
3030         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3031                 tw32_f(MAC_MI_MODE,
3032                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3033                 udelay(80);
3034         }
3035
3036         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3037
3038         /* Some third-party PHYs need to be reset on link going
3039          * down.
3040          */
3041         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3042              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3043              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3044             netif_carrier_ok(tp->dev)) {
3045                 tg3_readphy(tp, MII_BMSR, &bmsr);
3046                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3047                     !(bmsr & BMSR_LSTATUS))
3048                         force_reset = 1;
3049         }
3050         if (force_reset)
3051                 tg3_phy_reset(tp);
3052
3053         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3054                 tg3_readphy(tp, MII_BMSR, &bmsr);
3055                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3056                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3057                         bmsr = 0;
3058
3059                 if (!(bmsr & BMSR_LSTATUS)) {
3060                         err = tg3_init_5401phy_dsp(tp);
3061                         if (err)
3062                                 return err;
3063
3064                         tg3_readphy(tp, MII_BMSR, &bmsr);
3065                         for (i = 0; i < 1000; i++) {
3066                                 udelay(10);
3067                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3068                                     (bmsr & BMSR_LSTATUS)) {
3069                                         udelay(40);
3070                                         break;
3071                                 }
3072                         }
3073
3074                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3075                             TG3_PHY_REV_BCM5401_B0 &&
3076                             !(bmsr & BMSR_LSTATUS) &&
3077                             tp->link_config.active_speed == SPEED_1000) {
3078                                 err = tg3_phy_reset(tp);
3079                                 if (!err)
3080                                         err = tg3_init_5401phy_dsp(tp);
3081                                 if (err)
3082                                         return err;
3083                         }
3084                 }
3085         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3086                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3087                 /* 5701 {A0,B0} CRC bug workaround */
3088                 tg3_writephy(tp, 0x15, 0x0a75);
3089                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3090                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3091                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3092         }
3093
3094         /* Clear pending interrupts... */
3095         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3096         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3097
3098         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3099                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3100         else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3101                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3102
3103         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3104             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3105                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3106                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3107                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3108                 else
3109                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3110         }
3111
3112         current_link_up = 0;
3113         current_speed = SPEED_INVALID;
3114         current_duplex = DUPLEX_INVALID;
3115
3116         if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3117                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3118                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3119                 if (!(val & (1 << 10))) {
3120                         val |= (1 << 10);
3121                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3122                         goto relink;
3123                 }
3124         }
3125
3126         bmsr = 0;
3127         for (i = 0; i < 100; i++) {
3128                 tg3_readphy(tp, MII_BMSR, &bmsr);
3129                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3130                     (bmsr & BMSR_LSTATUS))
3131                         break;
3132                 udelay(40);
3133         }
3134
3135         if (bmsr & BMSR_LSTATUS) {
3136                 u32 aux_stat, bmcr;
3137
3138                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3139                 for (i = 0; i < 2000; i++) {
3140                         udelay(10);
3141                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3142                             aux_stat)
3143                                 break;
3144                 }
3145
3146                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3147                                              &current_speed,
3148                                              &current_duplex);
3149
3150                 bmcr = 0;
3151                 for (i = 0; i < 200; i++) {
3152                         tg3_readphy(tp, MII_BMCR, &bmcr);
3153                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3154                                 continue;
3155                         if (bmcr && bmcr != 0x7fff)
3156                                 break;
3157                         udelay(10);
3158                 }
3159
3160                 lcl_adv = 0;
3161                 rmt_adv = 0;
3162
3163                 tp->link_config.active_speed = current_speed;
3164                 tp->link_config.active_duplex = current_duplex;
3165
3166                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3167                         if ((bmcr & BMCR_ANENABLE) &&
3168                             tg3_copper_is_advertising_all(tp,
3169                                                 tp->link_config.advertising)) {
3170                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3171                                                                   &rmt_adv))
3172                                         current_link_up = 1;
3173                         }
3174                 } else {
3175                         if (!(bmcr & BMCR_ANENABLE) &&
3176                             tp->link_config.speed == current_speed &&
3177                             tp->link_config.duplex == current_duplex &&
3178                             tp->link_config.flowctrl ==
3179                             tp->link_config.active_flowctrl) {
3180                                 current_link_up = 1;
3181                         }
3182                 }
3183
3184                 if (current_link_up == 1 &&
3185                     tp->link_config.active_duplex == DUPLEX_FULL)
3186                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3187         }
3188
3189 relink:
3190         if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3191                 tg3_phy_copper_begin(tp);
3192
3193                 tg3_readphy(tp, MII_BMSR, &bmsr);
3194                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3195                     (bmsr & BMSR_LSTATUS))
3196                         current_link_up = 1;
3197         }
3198
3199         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3200         if (current_link_up == 1) {
3201                 if (tp->link_config.active_speed == SPEED_100 ||
3202                     tp->link_config.active_speed == SPEED_10)
3203                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3204                 else
3205                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3206         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3207                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3208         else
3209                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3210
3211         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3212         if (tp->link_config.active_duplex == DUPLEX_HALF)
3213                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3214
3215         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3216                 if (current_link_up == 1 &&
3217                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3218                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3219                 else
3220                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3221         }
3222
3223         /* ??? Without this setting Netgear GA302T PHY does not
3224          * ??? send/receive packets...
3225          */
3226         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3227             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3228                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3229                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3230                 udelay(80);
3231         }
3232
3233         tw32_f(MAC_MODE, tp->mac_mode);
3234         udelay(40);
3235
3236         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3237                 /* Polled via timer. */
3238                 tw32_f(MAC_EVENT, 0);
3239         } else {
3240                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3241         }
3242         udelay(40);
3243
3244         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3245             current_link_up == 1 &&
3246             tp->link_config.active_speed == SPEED_1000 &&
3247             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3248              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3249                 udelay(120);
3250                 tw32_f(MAC_STATUS,
3251                      (MAC_STATUS_SYNC_CHANGED |
3252                       MAC_STATUS_CFG_CHANGED));
3253                 udelay(40);
3254                 tg3_write_mem(tp,
3255                               NIC_SRAM_FIRMWARE_MBOX,
3256                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3257         }
3258
3259         /* Prevent send BD corruption. */
3260         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3261                 u16 oldlnkctl, newlnkctl;
3262
3263                 pci_read_config_word(tp->pdev,
3264                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3265                                      &oldlnkctl);
3266                 if (tp->link_config.active_speed == SPEED_100 ||
3267                     tp->link_config.active_speed == SPEED_10)
3268                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3269                 else
3270                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3271                 if (newlnkctl != oldlnkctl)
3272                         pci_write_config_word(tp->pdev,
3273                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3274                                               newlnkctl);
3275         }
3276
3277         if (current_link_up != netif_carrier_ok(tp->dev)) {
3278                 if (current_link_up)
3279                         netif_carrier_on(tp->dev);
3280                 else
3281                         netif_carrier_off(tp->dev);
3282                 tg3_link_report(tp);
3283         }
3284
3285         return 0;
3286 }
3287
3288 struct tg3_fiber_aneginfo {
3289         int state;
3290 #define ANEG_STATE_UNKNOWN              0
3291 #define ANEG_STATE_AN_ENABLE            1
3292 #define ANEG_STATE_RESTART_INIT         2
3293 #define ANEG_STATE_RESTART              3
3294 #define ANEG_STATE_DISABLE_LINK_OK      4
3295 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3296 #define ANEG_STATE_ABILITY_DETECT       6
3297 #define ANEG_STATE_ACK_DETECT_INIT      7
3298 #define ANEG_STATE_ACK_DETECT           8
3299 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3300 #define ANEG_STATE_COMPLETE_ACK         10
3301 #define ANEG_STATE_IDLE_DETECT_INIT     11
3302 #define ANEG_STATE_IDLE_DETECT          12
3303 #define ANEG_STATE_LINK_OK              13
3304 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3305 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3306
3307         u32 flags;
3308 #define MR_AN_ENABLE            0x00000001
3309 #define MR_RESTART_AN           0x00000002
3310 #define MR_AN_COMPLETE          0x00000004
3311 #define MR_PAGE_RX              0x00000008
3312 #define MR_NP_LOADED            0x00000010
3313 #define MR_TOGGLE_TX            0x00000020
3314 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3315 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3316 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3317 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3318 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3319 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3320 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3321 #define MR_TOGGLE_RX            0x00002000
3322 #define MR_NP_RX                0x00004000
3323
3324 #define MR_LINK_OK              0x80000000
3325
3326         unsigned long link_time, cur_time;
3327
3328         u32 ability_match_cfg;
3329         int ability_match_count;
3330
3331         char ability_match, idle_match, ack_match;
3332
3333         u32 txconfig, rxconfig;
3334 #define ANEG_CFG_NP             0x00000080
3335 #define ANEG_CFG_ACK            0x00000040
3336 #define ANEG_CFG_RF2            0x00000020
3337 #define ANEG_CFG_RF1            0x00000010
3338 #define ANEG_CFG_PS2            0x00000001
3339 #define ANEG_CFG_PS1            0x00008000
3340 #define ANEG_CFG_HD             0x00004000
3341 #define ANEG_CFG_FD             0x00002000
3342 #define ANEG_CFG_INVAL          0x00001f06
3343
3344 };
3345 #define ANEG_OK         0
3346 #define ANEG_DONE       1
3347 #define ANEG_TIMER_ENAB 2
3348 #define ANEG_FAILED     -1
3349
3350 #define ANEG_STATE_SETTLE_TIME  10000
3351
3352 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3353                                    struct tg3_fiber_aneginfo *ap)
3354 {
3355         u16 flowctrl;
3356         unsigned long delta;
3357         u32 rx_cfg_reg;
3358         int ret;
3359
3360         if (ap->state == ANEG_STATE_UNKNOWN) {
3361                 ap->rxconfig = 0;
3362                 ap->link_time = 0;
3363                 ap->cur_time = 0;
3364                 ap->ability_match_cfg = 0;
3365                 ap->ability_match_count = 0;
3366                 ap->ability_match = 0;
3367                 ap->idle_match = 0;
3368                 ap->ack_match = 0;
3369         }
3370         ap->cur_time++;
3371
3372         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3373                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3374
3375                 if (rx_cfg_reg != ap->ability_match_cfg) {
3376                         ap->ability_match_cfg = rx_cfg_reg;
3377                         ap->ability_match = 0;
3378                         ap->ability_match_count = 0;
3379                 } else {
3380                         if (++ap->ability_match_count > 1) {
3381                                 ap->ability_match = 1;
3382                                 ap->ability_match_cfg = rx_cfg_reg;
3383                         }
3384                 }
3385                 if (rx_cfg_reg & ANEG_CFG_ACK)
3386                         ap->ack_match = 1;
3387                 else
3388                         ap->ack_match = 0;
3389
3390                 ap->idle_match = 0;
3391         } else {
3392                 ap->idle_match = 1;
3393                 ap->ability_match_cfg = 0;
3394                 ap->ability_match_count = 0;
3395                 ap->ability_match = 0;
3396                 ap->ack_match = 0;
3397
3398                 rx_cfg_reg = 0;
3399         }
3400
3401         ap->rxconfig = rx_cfg_reg;
3402         ret = ANEG_OK;
3403
3404         switch (ap->state) {
3405         case ANEG_STATE_UNKNOWN:
3406                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3407                         ap->state = ANEG_STATE_AN_ENABLE;
3408
3409                 /* fallthru */
3410         case ANEG_STATE_AN_ENABLE:
3411                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3412                 if (ap->flags & MR_AN_ENABLE) {
3413                         ap->link_time = 0;
3414                         ap->cur_time = 0;
3415                         ap->ability_match_cfg = 0;
3416                         ap->ability_match_count = 0;
3417                         ap->ability_match = 0;
3418                         ap->idle_match = 0;
3419                         ap->ack_match = 0;
3420
3421                         ap->state = ANEG_STATE_RESTART_INIT;
3422                 } else {
3423                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3424                 }
3425                 break;
3426
3427         case ANEG_STATE_RESTART_INIT:
3428                 ap->link_time = ap->cur_time;
3429                 ap->flags &= ~(MR_NP_LOADED);
3430                 ap->txconfig = 0;
3431                 tw32(MAC_TX_AUTO_NEG, 0);
3432                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3433                 tw32_f(MAC_MODE, tp->mac_mode);
3434                 udelay(40);
3435
3436                 ret = ANEG_TIMER_ENAB;
3437                 ap->state = ANEG_STATE_RESTART;
3438
3439                 /* fallthru */
3440         case ANEG_STATE_RESTART:
3441                 delta = ap->cur_time - ap->link_time;
3442                 if (delta > ANEG_STATE_SETTLE_TIME)
3443                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3444                 else
3445                         ret = ANEG_TIMER_ENAB;
3446                 break;
3447
3448         case ANEG_STATE_DISABLE_LINK_OK:
3449                 ret = ANEG_DONE;
3450                 break;
3451
3452         case ANEG_STATE_ABILITY_DETECT_INIT:
3453                 ap->flags &= ~(MR_TOGGLE_TX);
3454                 ap->txconfig = ANEG_CFG_FD;
3455                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3456                 if (flowctrl & ADVERTISE_1000XPAUSE)
3457                         ap->txconfig |= ANEG_CFG_PS1;
3458                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3459                         ap->txconfig |= ANEG_CFG_PS2;
3460                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3461                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3462                 tw32_f(MAC_MODE, tp->mac_mode);
3463                 udelay(40);
3464
3465                 ap->state = ANEG_STATE_ABILITY_DETECT;
3466                 break;
3467
3468         case ANEG_STATE_ABILITY_DETECT:
3469                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3470                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3471                 break;
3472
3473         case ANEG_STATE_ACK_DETECT_INIT:
3474                 ap->txconfig |= ANEG_CFG_ACK;
3475                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3476                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3477                 tw32_f(MAC_MODE, tp->mac_mode);
3478                 udelay(40);
3479
3480                 ap->state = ANEG_STATE_ACK_DETECT;
3481
3482                 /* fallthru */
3483         case ANEG_STATE_ACK_DETECT:
3484                 if (ap->ack_match != 0) {
3485                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3486                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3487                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3488                         } else {
3489                                 ap->state = ANEG_STATE_AN_ENABLE;
3490                         }
3491                 } else if (ap->ability_match != 0 &&
3492                            ap->rxconfig == 0) {
3493                         ap->state = ANEG_STATE_AN_ENABLE;
3494                 }
3495                 break;
3496
3497         case ANEG_STATE_COMPLETE_ACK_INIT:
3498                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3499                         ret = ANEG_FAILED;
3500                         break;
3501                 }
3502                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3503                                MR_LP_ADV_HALF_DUPLEX |
3504                                MR_LP_ADV_SYM_PAUSE |
3505                                MR_LP_ADV_ASYM_PAUSE |
3506                                MR_LP_ADV_REMOTE_FAULT1 |
3507                                MR_LP_ADV_REMOTE_FAULT2 |
3508                                MR_LP_ADV_NEXT_PAGE |
3509                                MR_TOGGLE_RX |
3510                                MR_NP_RX);
3511                 if (ap->rxconfig & ANEG_CFG_FD)
3512                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3513                 if (ap->rxconfig & ANEG_CFG_HD)
3514                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3515                 if (ap->rxconfig & ANEG_CFG_PS1)
3516                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3517                 if (ap->rxconfig & ANEG_CFG_PS2)
3518                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3519                 if (ap->rxconfig & ANEG_CFG_RF1)
3520                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3521                 if (ap->rxconfig & ANEG_CFG_RF2)
3522                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3523                 if (ap->rxconfig & ANEG_CFG_NP)
3524                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3525
3526                 ap->link_time = ap->cur_time;
3527
3528                 ap->flags ^= (MR_TOGGLE_TX);
3529                 if (ap->rxconfig & 0x0008)
3530                         ap->flags |= MR_TOGGLE_RX;
3531                 if (ap->rxconfig & ANEG_CFG_NP)
3532                         ap->flags |= MR_NP_RX;
3533                 ap->flags |= MR_PAGE_RX;
3534
3535                 ap->state = ANEG_STATE_COMPLETE_ACK;
3536                 ret = ANEG_TIMER_ENAB;
3537                 break;
3538
3539         case ANEG_STATE_COMPLETE_ACK:
3540                 if (ap->ability_match != 0 &&
3541                     ap->rxconfig == 0) {
3542                         ap->state = ANEG_STATE_AN_ENABLE;
3543                         break;
3544                 }
3545                 delta = ap->cur_time - ap->link_time;
3546                 if (delta > ANEG_STATE_SETTLE_TIME) {
3547                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3548                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3549                         } else {
3550                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3551                                     !(ap->flags & MR_NP_RX)) {
3552                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3553                                 } else {
3554                                         ret = ANEG_FAILED;
3555                                 }
3556                         }
3557                 }
3558                 break;
3559
3560         case ANEG_STATE_IDLE_DETECT_INIT:
3561                 ap->link_time = ap->cur_time;
3562                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3563                 tw32_f(MAC_MODE, tp->mac_mode);
3564                 udelay(40);
3565
3566                 ap->state = ANEG_STATE_IDLE_DETECT;
3567                 ret = ANEG_TIMER_ENAB;
3568                 break;
3569
3570         case ANEG_STATE_IDLE_DETECT:
3571                 if (ap->ability_match != 0 &&
3572                     ap->rxconfig == 0) {
3573                         ap->state = ANEG_STATE_AN_ENABLE;
3574                         break;
3575                 }
3576                 delta = ap->cur_time - ap->link_time;
3577                 if (delta > ANEG_STATE_SETTLE_TIME) {
3578                         /* XXX another gem from the Broadcom driver :( */
3579                         ap->state = ANEG_STATE_LINK_OK;
3580                 }
3581                 break;
3582
3583         case ANEG_STATE_LINK_OK:
3584                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3585                 ret = ANEG_DONE;
3586                 break;
3587
3588         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3589                 /* ??? unimplemented */
3590                 break;
3591
3592         case ANEG_STATE_NEXT_PAGE_WAIT:
3593                 /* ??? unimplemented */
3594                 break;
3595
3596         default:
3597                 ret = ANEG_FAILED;
3598                 break;
3599         }
3600
3601         return ret;
3602 }
3603
3604 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3605 {
3606         int res = 0;
3607         struct tg3_fiber_aneginfo aninfo;
3608         int status = ANEG_FAILED;
3609         unsigned int tick;
3610         u32 tmp;
3611
3612         tw32_f(MAC_TX_AUTO_NEG, 0);
3613
3614         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3615         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3616         udelay(40);
3617
3618         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3619         udelay(40);
3620
3621         memset(&aninfo, 0, sizeof(aninfo));
3622         aninfo.flags |= MR_AN_ENABLE;
3623         aninfo.state = ANEG_STATE_UNKNOWN;
3624         aninfo.cur_time = 0;
3625         tick = 0;
3626         while (++tick < 195000) {
3627                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3628                 if (status == ANEG_DONE || status == ANEG_FAILED)
3629                         break;
3630
3631                 udelay(1);
3632         }
3633
3634         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3635         tw32_f(MAC_MODE, tp->mac_mode);
3636         udelay(40);
3637
3638         *txflags = aninfo.txconfig;
3639         *rxflags = aninfo.flags;
3640
3641         if (status == ANEG_DONE &&
3642             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3643                              MR_LP_ADV_FULL_DUPLEX)))
3644                 res = 1;
3645
3646         return res;
3647 }
3648
3649 static void tg3_init_bcm8002(struct tg3 *tp)
3650 {
3651         u32 mac_status = tr32(MAC_STATUS);
3652         int i;
3653
3654         /* Reset when initting first time or we have a link. */
3655         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3656             !(mac_status & MAC_STATUS_PCS_SYNCED))
3657                 return;
3658
3659         /* Set PLL lock range. */
3660         tg3_writephy(tp, 0x16, 0x8007);
3661
3662         /* SW reset */
3663         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3664
3665         /* Wait for reset to complete. */
3666         /* XXX schedule_timeout() ... */
3667         for (i = 0; i < 500; i++)
3668                 udelay(10);
3669
3670         /* Config mode; select PMA/Ch 1 regs. */
3671         tg3_writephy(tp, 0x10, 0x8411);
3672
3673         /* Enable auto-lock and comdet, select txclk for tx. */
3674         tg3_writephy(tp, 0x11, 0x0a10);
3675
3676         tg3_writephy(tp, 0x18, 0x00a0);
3677         tg3_writephy(tp, 0x16, 0x41ff);
3678
3679         /* Assert and deassert POR. */
3680         tg3_writephy(tp, 0x13, 0x0400);
3681         udelay(40);
3682         tg3_writephy(tp, 0x13, 0x0000);
3683
3684         tg3_writephy(tp, 0x11, 0x0a50);
3685         udelay(40);
3686         tg3_writephy(tp, 0x11, 0x0a10);
3687
3688         /* Wait for signal to stabilize */
3689         /* XXX schedule_timeout() ... */
3690         for (i = 0; i < 15000; i++)
3691                 udelay(10);
3692
3693         /* Deselect the channel register so we can read the PHYID
3694          * later.
3695          */
3696         tg3_writephy(tp, 0x10, 0x8011);
3697 }
3698
3699 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3700 {
3701         u16 flowctrl;
3702         u32 sg_dig_ctrl, sg_dig_status;
3703         u32 serdes_cfg, expected_sg_dig_ctrl;
3704         int workaround, port_a;
3705         int current_link_up;
3706
3707         serdes_cfg = 0;
3708         expected_sg_dig_ctrl = 0;
3709         workaround = 0;
3710         port_a = 1;
3711         current_link_up = 0;
3712
3713         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3714             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3715                 workaround = 1;
3716                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3717                         port_a = 0;
3718
3719                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3720                 /* preserve bits 20-23 for voltage regulator */
3721                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3722         }
3723
3724         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3725
3726         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3727                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3728                         if (workaround) {
3729                                 u32 val = serdes_cfg;
3730
3731                                 if (port_a)
3732                                         val |= 0xc010000;
3733                                 else
3734                                         val |= 0x4010000;
3735                                 tw32_f(MAC_SERDES_CFG, val);
3736                         }
3737
3738                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3739                 }
3740                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3741                         tg3_setup_flow_control(tp, 0, 0);
3742                         current_link_up = 1;
3743                 }
3744                 goto out;
3745         }
3746
3747         /* Want auto-negotiation.  */
3748         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3749
3750         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3751         if (flowctrl & ADVERTISE_1000XPAUSE)
3752                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3753         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3754                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3755
3756         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3757                 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3758                     tp->serdes_counter &&
3759                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3760                                     MAC_STATUS_RCVD_CFG)) ==
3761                      MAC_STATUS_PCS_SYNCED)) {
3762                         tp->serdes_counter--;
3763                         current_link_up = 1;
3764                         goto out;
3765                 }
3766 restart_autoneg:
3767                 if (workaround)
3768                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3769                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3770                 udelay(5);
3771                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3772
3773                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3774                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3775         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3776                                  MAC_STATUS_SIGNAL_DET)) {
3777                 sg_dig_status = tr32(SG_DIG_STATUS);
3778                 mac_status = tr32(MAC_STATUS);
3779
3780                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3781                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3782                         u32 local_adv = 0, remote_adv = 0;
3783
3784                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3785                                 local_adv |= ADVERTISE_1000XPAUSE;
3786                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3787                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3788
3789                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3790                                 remote_adv |= LPA_1000XPAUSE;
3791                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3792                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3793
3794                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3795                         current_link_up = 1;
3796                         tp->serdes_counter = 0;
3797                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3798                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3799                         if (tp->serdes_counter)
3800                                 tp->serdes_counter--;
3801                         else {
3802                                 if (workaround) {
3803                                         u32 val = serdes_cfg;
3804
3805                                         if (port_a)
3806                                                 val |= 0xc010000;
3807                                         else
3808                                                 val |= 0x4010000;
3809
3810                                         tw32_f(MAC_SERDES_CFG, val);
3811                                 }
3812
3813                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3814                                 udelay(40);
3815
3816                                 /* Link parallel detection - link is up */
3817                                 /* only if we have PCS_SYNC and not */
3818                                 /* receiving config code words */
3819                                 mac_status = tr32(MAC_STATUS);
3820                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3821                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3822                                         tg3_setup_flow_control(tp, 0, 0);
3823                                         current_link_up = 1;
3824                                         tp->phy_flags |=
3825                                                 TG3_PHYFLG_PARALLEL_DETECT;
3826                                         tp->serdes_counter =
3827                                                 SERDES_PARALLEL_DET_TIMEOUT;
3828                                 } else
3829                                         goto restart_autoneg;
3830                         }
3831                 }
3832         } else {
3833                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3834                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3835         }
3836
3837 out:
3838         return current_link_up;
3839 }
3840
3841 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3842 {
3843         int current_link_up = 0;
3844
3845         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3846                 goto out;
3847
3848         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3849                 u32 txflags, rxflags;
3850                 int i;
3851
3852                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3853                         u32 local_adv = 0, remote_adv = 0;
3854
3855                         if (txflags & ANEG_CFG_PS1)
3856                                 local_adv |= ADVERTISE_1000XPAUSE;
3857                         if (txflags & ANEG_CFG_PS2)
3858                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3859
3860                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3861                                 remote_adv |= LPA_1000XPAUSE;
3862                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3863                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3864
3865                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3866
3867                         current_link_up = 1;
3868                 }
3869                 for (i = 0; i < 30; i++) {
3870                         udelay(20);
3871                         tw32_f(MAC_STATUS,
3872                                (MAC_STATUS_SYNC_CHANGED |
3873                                 MAC_STATUS_CFG_CHANGED));
3874                         udelay(40);
3875                         if ((tr32(MAC_STATUS) &
3876                              (MAC_STATUS_SYNC_CHANGED |
3877                               MAC_STATUS_CFG_CHANGED)) == 0)
3878                                 break;
3879                 }
3880
3881                 mac_status = tr32(MAC_STATUS);
3882                 if (current_link_up == 0 &&
3883                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3884                     !(mac_status & MAC_STATUS_RCVD_CFG))
3885                         current_link_up = 1;
3886         } else {
3887                 tg3_setup_flow_control(tp, 0, 0);
3888
3889                 /* Forcing 1000FD link up. */
3890                 current_link_up = 1;
3891
3892                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3893                 udelay(40);
3894
3895                 tw32_f(MAC_MODE, tp->mac_mode);
3896                 udelay(40);
3897         }
3898
3899 out:
3900         return current_link_up;
3901 }
3902
3903 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3904 {
3905         u32 orig_pause_cfg;
3906         u16 orig_active_speed;
3907         u8 orig_active_duplex;
3908         u32 mac_status;
3909         int current_link_up;
3910         int i;
3911
3912         orig_pause_cfg = tp->link_config.active_flowctrl;
3913         orig_active_speed = tp->link_config.active_speed;
3914         orig_active_duplex = tp->link_config.active_duplex;
3915
3916         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3917             netif_carrier_ok(tp->dev) &&
3918             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3919                 mac_status = tr32(MAC_STATUS);
3920                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3921                                MAC_STATUS_SIGNAL_DET |
3922                                MAC_STATUS_CFG_CHANGED |
3923                                MAC_STATUS_RCVD_CFG);
3924                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3925                                    MAC_STATUS_SIGNAL_DET)) {
3926                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3927                                             MAC_STATUS_CFG_CHANGED));
3928                         return 0;
3929                 }
3930         }
3931
3932         tw32_f(MAC_TX_AUTO_NEG, 0);
3933
3934         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3935         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3936         tw32_f(MAC_MODE, tp->mac_mode);
3937         udelay(40);
3938
3939         if (tp->phy_id == TG3_PHY_ID_BCM8002)
3940                 tg3_init_bcm8002(tp);
3941
3942         /* Enable link change event even when serdes polling.  */
3943         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3944         udelay(40);
3945
3946         current_link_up = 0;
3947         mac_status = tr32(MAC_STATUS);
3948
3949         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3950                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3951         else
3952                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3953
3954         tp->napi[0].hw_status->status =
3955                 (SD_STATUS_UPDATED |
3956                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3957
3958         for (i = 0; i < 100; i++) {
3959                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3960                                     MAC_STATUS_CFG_CHANGED));
3961                 udelay(5);
3962                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3963                                          MAC_STATUS_CFG_CHANGED |
3964                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3965                         break;
3966         }
3967
3968         mac_status = tr32(MAC_STATUS);
3969         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3970                 current_link_up = 0;
3971                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3972                     tp->serdes_counter == 0) {
3973                         tw32_f(MAC_MODE, (tp->mac_mode |
3974                                           MAC_MODE_SEND_CONFIGS));
3975                         udelay(1);
3976                         tw32_f(MAC_MODE, tp->mac_mode);
3977                 }
3978         }
3979
3980         if (current_link_up == 1) {
3981                 tp->link_config.active_speed = SPEED_1000;
3982                 tp->link_config.active_duplex = DUPLEX_FULL;
3983                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3984                                     LED_CTRL_LNKLED_OVERRIDE |
3985                                     LED_CTRL_1000MBPS_ON));
3986         } else {
3987                 tp->link_config.active_speed = SPEED_INVALID;
3988                 tp->link_config.active_duplex = DUPLEX_INVALID;
3989                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3990                                     LED_CTRL_LNKLED_OVERRIDE |
3991                                     LED_CTRL_TRAFFIC_OVERRIDE));
3992         }
3993
3994         if (current_link_up != netif_carrier_ok(tp->dev)) {
3995                 if (current_link_up)
3996                         netif_carrier_on(tp->dev);
3997                 else
3998                         netif_carrier_off(tp->dev);
3999                 tg3_link_report(tp);
4000         } else {
4001                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4002                 if (orig_pause_cfg != now_pause_cfg ||
4003                     orig_active_speed != tp->link_config.active_speed ||
4004                     orig_active_duplex != tp->link_config.active_duplex)
4005                         tg3_link_report(tp);
4006         }
4007
4008         return 0;
4009 }
4010
4011 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4012 {
4013         int current_link_up, err = 0;
4014         u32 bmsr, bmcr;
4015         u16 current_speed;
4016         u8 current_duplex;
4017         u32 local_adv, remote_adv;
4018
4019         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4020         tw32_f(MAC_MODE, tp->mac_mode);
4021         udelay(40);
4022
4023         tw32(MAC_EVENT, 0);
4024
4025         tw32_f(MAC_STATUS,
4026              (MAC_STATUS_SYNC_CHANGED |
4027               MAC_STATUS_CFG_CHANGED |
4028               MAC_STATUS_MI_COMPLETION |
4029               MAC_STATUS_LNKSTATE_CHANGED));
4030         udelay(40);
4031
4032         if (force_reset)
4033                 tg3_phy_reset(tp);
4034
4035         current_link_up = 0;
4036         current_speed = SPEED_INVALID;
4037         current_duplex = DUPLEX_INVALID;
4038
4039         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4040         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4041         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4042                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4043                         bmsr |= BMSR_LSTATUS;
4044                 else
4045                         bmsr &= ~BMSR_LSTATUS;
4046         }
4047
4048         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4049
4050         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4051             (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4052                 /* do nothing, just check for link up at the end */
4053         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4054                 u32 adv, new_adv;
4055
4056                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4057                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4058                                   ADVERTISE_1000XPAUSE |
4059                                   ADVERTISE_1000XPSE_ASYM |
4060                                   ADVERTISE_SLCT);
4061
4062                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4063
4064                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4065                         new_adv |= ADVERTISE_1000XHALF;
4066                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4067                         new_adv |= ADVERTISE_1000XFULL;
4068
4069                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4070                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4071                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4072                         tg3_writephy(tp, MII_BMCR, bmcr);
4073
4074                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4075                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4076                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4077
4078                         return err;
4079                 }
4080         } else {
4081                 u32 new_bmcr;
4082
4083                 bmcr &= ~BMCR_SPEED1000;
4084                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4085
4086                 if (tp->link_config.duplex == DUPLEX_FULL)
4087                         new_bmcr |= BMCR_FULLDPLX;
4088
4089                 if (new_bmcr != bmcr) {
4090                         /* BMCR_SPEED1000 is a reserved bit that needs
4091                          * to be set on write.
4092                          */
4093                         new_bmcr |= BMCR_SPEED1000;
4094
4095                         /* Force a linkdown */
4096                         if (netif_carrier_ok(tp->dev)) {
4097                                 u32 adv;
4098
4099                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4100                                 adv &= ~(ADVERTISE_1000XFULL |
4101                                          ADVERTISE_1000XHALF |
4102                                          ADVERTISE_SLCT);
4103                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4104                                 tg3_writephy(tp, MII_BMCR, bmcr |
4105                                                            BMCR_ANRESTART |
4106                                                            BMCR_ANENABLE);
4107                                 udelay(10);
4108                                 netif_carrier_off(tp->dev);
4109                         }
4110                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4111                         bmcr = new_bmcr;
4112                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4113                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4114                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4115                             ASIC_REV_5714) {
4116                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4117                                         bmsr |= BMSR_LSTATUS;
4118                                 else
4119                                         bmsr &= ~BMSR_LSTATUS;
4120                         }
4121                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4122                 }
4123         }
4124
4125         if (bmsr & BMSR_LSTATUS) {
4126                 current_speed = SPEED_1000;
4127                 current_link_up = 1;
4128                 if (bmcr & BMCR_FULLDPLX)
4129                         current_duplex = DUPLEX_FULL;
4130                 else
4131                         current_duplex = DUPLEX_HALF;
4132
4133                 local_adv = 0;
4134                 remote_adv = 0;
4135
4136                 if (bmcr & BMCR_ANENABLE) {
4137                         u32 common;
4138
4139                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4140                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4141                         common = local_adv & remote_adv;
4142                         if (common & (ADVERTISE_1000XHALF |
4143                                       ADVERTISE_1000XFULL)) {
4144                                 if (common & ADVERTISE_1000XFULL)
4145                                         current_duplex = DUPLEX_FULL;
4146                                 else
4147                                         current_duplex = DUPLEX_HALF;
4148                         } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4149                                 /* Link is up via parallel detect */
4150                         } else {
4151                                 current_link_up = 0;
4152                         }
4153                 }
4154         }
4155
4156         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4157                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4158
4159         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4160         if (tp->link_config.active_duplex == DUPLEX_HALF)
4161                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4162
4163         tw32_f(MAC_MODE, tp->mac_mode);
4164         udelay(40);
4165
4166         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4167
4168         tp->link_config.active_speed = current_speed;
4169         tp->link_config.active_duplex = current_duplex;
4170
4171         if (current_link_up != netif_carrier_ok(tp->dev)) {
4172                 if (current_link_up)
4173                         netif_carrier_on(tp->dev);
4174                 else {
4175                         netif_carrier_off(tp->dev);
4176                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4177                 }
4178                 tg3_link_report(tp);
4179         }
4180         return err;
4181 }
4182
4183 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4184 {
4185         if (tp->serdes_counter) {
4186                 /* Give autoneg time to complete. */
4187                 tp->serdes_counter--;
4188                 return;
4189         }
4190
4191         if (!netif_carrier_ok(tp->dev) &&
4192             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4193                 u32 bmcr;
4194
4195                 tg3_readphy(tp, MII_BMCR, &bmcr);
4196                 if (bmcr & BMCR_ANENABLE) {
4197                         u32 phy1, phy2;
4198
4199                         /* Select shadow register 0x1f */
4200                         tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4201                         tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4202
4203                         /* Select expansion interrupt status register */
4204                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4205                                          MII_TG3_DSP_EXP1_INT_STAT);
4206                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4207                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4208
4209                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4210                                 /* We have signal detect and not receiving
4211                                  * config code words, link is up by parallel
4212                                  * detection.
4213                                  */
4214
4215                                 bmcr &= ~BMCR_ANENABLE;
4216                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4217                                 tg3_writephy(tp, MII_BMCR, bmcr);
4218                                 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4219                         }
4220                 }
4221         } else if (netif_carrier_ok(tp->dev) &&
4222                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4223                    (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4224                 u32 phy2;
4225
4226                 /* Select expansion interrupt status register */
4227                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4228                                  MII_TG3_DSP_EXP1_INT_STAT);
4229                 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4230                 if (phy2 & 0x20) {
4231                         u32 bmcr;
4232
4233                         /* Config code words received, turn on autoneg. */
4234                         tg3_readphy(tp, MII_BMCR, &bmcr);
4235                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4236
4237                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4238
4239                 }
4240         }
4241 }
4242
4243 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4244 {
4245         int err;
4246
4247         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4248                 err = tg3_setup_fiber_phy(tp, force_reset);
4249         else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4250                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4251         else
4252                 err = tg3_setup_copper_phy(tp, force_reset);
4253
4254         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4255                 u32 val, scale;
4256
4257                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4258                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4259                         scale = 65;
4260                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4261                         scale = 6;
4262                 else
4263                         scale = 12;
4264
4265                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4266                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4267                 tw32(GRC_MISC_CFG, val);
4268         }
4269
4270         if (tp->link_config.active_speed == SPEED_1000 &&
4271             tp->link_config.active_duplex == DUPLEX_HALF)
4272                 tw32(MAC_TX_LENGTHS,
4273                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4274                       (6 << TX_LENGTHS_IPG_SHIFT) |
4275                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4276         else
4277                 tw32(MAC_TX_LENGTHS,
4278                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4279                       (6 << TX_LENGTHS_IPG_SHIFT) |
4280                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4281
4282         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4283                 if (netif_carrier_ok(tp->dev)) {
4284                         tw32(HOSTCC_STAT_COAL_TICKS,
4285                              tp->coal.stats_block_coalesce_usecs);
4286                 } else {
4287                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4288                 }
4289         }
4290
4291         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4292                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4293                 if (!netif_carrier_ok(tp->dev))
4294                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4295                               tp->pwrmgmt_thresh;
4296                 else
4297                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4298                 tw32(PCIE_PWR_MGMT_THRESH, val);
4299         }
4300
4301         return err;
4302 }
4303
4304 static inline int tg3_irq_sync(struct tg3 *tp)
4305 {
4306         return tp->irq_sync;
4307 }
4308
4309 /* This is called whenever we suspect that the system chipset is re-
4310  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4311  * is bogus tx completions. We try to recover by setting the
4312  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4313  * in the workqueue.
4314  */
4315 static void tg3_tx_recover(struct tg3 *tp)
4316 {
4317         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4318                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4319
4320         netdev_warn(tp->dev,
4321                     "The system may be re-ordering memory-mapped I/O "
4322                     "cycles to the network device, attempting to recover. "
4323                     "Please report the problem to the driver maintainer "
4324                     "and include system chipset information.\n");
4325
4326         spin_lock(&tp->lock);
4327         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4328         spin_unlock(&tp->lock);
4329 }
4330
4331 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4332 {
4333         /* Tell compiler to fetch tx indices from memory. */
4334         barrier();
4335         return tnapi->tx_pending -
4336                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4337 }
4338
4339 /* Tigon3 never reports partial packet sends.  So we do not
4340  * need special logic to handle SKBs that have not had all
4341  * of their frags sent yet, like SunGEM does.
4342  */
4343 static void tg3_tx(struct tg3_napi *tnapi)
4344 {
4345         struct tg3 *tp = tnapi->tp;
4346         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4347         u32 sw_idx = tnapi->tx_cons;
4348         struct netdev_queue *txq;
4349         int index = tnapi - tp->napi;
4350
4351         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4352                 index--;
4353
4354         txq = netdev_get_tx_queue(tp->dev, index);
4355
4356         while (sw_idx != hw_idx) {
4357                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4358                 struct sk_buff *skb = ri->skb;
4359                 int i, tx_bug = 0;
4360
4361                 if (unlikely(skb == NULL)) {
4362                         tg3_tx_recover(tp);
4363                         return;
4364                 }
4365
4366                 pci_unmap_single(tp->pdev,
4367                                  dma_unmap_addr(ri, mapping),
4368                                  skb_headlen(skb),
4369                                  PCI_DMA_TODEVICE);
4370
4371                 ri->skb = NULL;
4372
4373                 sw_idx = NEXT_TX(sw_idx);
4374
4375                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4376                         ri = &tnapi->tx_buffers[sw_idx];
4377                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4378                                 tx_bug = 1;
4379
4380                         pci_unmap_page(tp->pdev,
4381                                        dma_unmap_addr(ri, mapping),
4382                                        skb_shinfo(skb)->frags[i].size,
4383                                        PCI_DMA_TODEVICE);
4384                         sw_idx = NEXT_TX(sw_idx);
4385                 }
4386
4387                 dev_kfree_skb(skb);
4388
4389                 if (unlikely(tx_bug)) {
4390                         tg3_tx_recover(tp);
4391                         return;
4392                 }
4393         }
4394
4395         tnapi->tx_cons = sw_idx;
4396
4397         /* Need to make the tx_cons update visible to tg3_start_xmit()
4398          * before checking for netif_queue_stopped().  Without the
4399          * memory barrier, there is a small possibility that tg3_start_xmit()
4400          * will miss it and cause the queue to be stopped forever.
4401          */
4402         smp_mb();
4403
4404         if (unlikely(netif_tx_queue_stopped(txq) &&
4405                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4406                 __netif_tx_lock(txq, smp_processor_id());
4407                 if (netif_tx_queue_stopped(txq) &&
4408                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4409                         netif_tx_wake_queue(txq);
4410                 __netif_tx_unlock(txq);
4411         }
4412 }
4413
4414 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4415 {
4416         if (!ri->skb)
4417                 return;
4418
4419         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4420                          map_sz, PCI_DMA_FROMDEVICE);
4421         dev_kfree_skb_any(ri->skb);
4422         ri->skb = NULL;
4423 }
4424
4425 /* Returns size of skb allocated or < 0 on error.
4426  *
4427  * We only need to fill in the address because the other members
4428  * of the RX descriptor are invariant, see tg3_init_rings.
4429  *
4430  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4431  * posting buffers we only dirty the first cache line of the RX
4432  * descriptor (containing the address).  Whereas for the RX status
4433  * buffers the cpu only reads the last cacheline of the RX descriptor
4434  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4435  */
4436 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4437                             u32 opaque_key, u32 dest_idx_unmasked)
4438 {
4439         struct tg3_rx_buffer_desc *desc;
4440         struct ring_info *map, *src_map;
4441         struct sk_buff *skb;
4442         dma_addr_t mapping;
4443         int skb_size, dest_idx;
4444
4445         src_map = NULL;
4446         switch (opaque_key) {
4447         case RXD_OPAQUE_RING_STD:
4448                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4449                 desc = &tpr->rx_std[dest_idx];
4450                 map = &tpr->rx_std_buffers[dest_idx];
4451                 skb_size = tp->rx_pkt_map_sz;
4452                 break;
4453
4454         case RXD_OPAQUE_RING_JUMBO:
4455                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4456                 desc = &tpr->rx_jmb[dest_idx].std;
4457                 map = &tpr->rx_jmb_buffers[dest_idx];
4458                 skb_size = TG3_RX_JMB_MAP_SZ;
4459                 break;
4460
4461         default:
4462                 return -EINVAL;
4463         }
4464
4465         /* Do not overwrite any of the map or rp information
4466          * until we are sure we can commit to a new buffer.
4467          *
4468          * Callers depend upon this behavior and assume that
4469          * we leave everything unchanged if we fail.
4470          */
4471         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4472         if (skb == NULL)
4473                 return -ENOMEM;
4474
4475         skb_reserve(skb, tp->rx_offset);
4476
4477         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4478                                  PCI_DMA_FROMDEVICE);
4479         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4480                 dev_kfree_skb(skb);
4481                 return -EIO;
4482         }
4483
4484         map->skb = skb;
4485         dma_unmap_addr_set(map, mapping, mapping);
4486
4487         desc->addr_hi = ((u64)mapping >> 32);
4488         desc->addr_lo = ((u64)mapping & 0xffffffff);
4489
4490         return skb_size;
4491 }
4492
4493 /* We only need to move over in the address because the other
4494  * members of the RX descriptor are invariant.  See notes above
4495  * tg3_alloc_rx_skb for full details.
4496  */
4497 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4498                            struct tg3_rx_prodring_set *dpr,
4499                            u32 opaque_key, int src_idx,
4500                            u32 dest_idx_unmasked)
4501 {
4502         struct tg3 *tp = tnapi->tp;
4503         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4504         struct ring_info *src_map, *dest_map;
4505         struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
4506         int dest_idx;
4507
4508         switch (opaque_key) {
4509         case RXD_OPAQUE_RING_STD:
4510                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4511                 dest_desc = &dpr->rx_std[dest_idx];
4512                 dest_map = &dpr->rx_std_buffers[dest_idx];
4513                 src_desc = &spr->rx_std[src_idx];
4514                 src_map = &spr->rx_std_buffers[src_idx];
4515                 break;
4516
4517         case RXD_OPAQUE_RING_JUMBO:
4518                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4519                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4520                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4521                 src_desc = &spr->rx_jmb[src_idx].std;
4522                 src_map = &spr->rx_jmb_buffers[src_idx];
4523                 break;
4524
4525         default:
4526                 return;
4527         }
4528
4529         dest_map->skb = src_map->skb;
4530         dma_unmap_addr_set(dest_map, mapping,
4531                            dma_unmap_addr(src_map, mapping));
4532         dest_desc->addr_hi = src_desc->addr_hi;
4533         dest_desc->addr_lo = src_desc->addr_lo;
4534
4535         /* Ensure that the update to the skb happens after the physical
4536          * addresses have been transferred to the new BD location.
4537          */
4538         smp_wmb();
4539
4540         src_map->skb = NULL;
4541 }
4542
4543 /* The RX ring scheme is composed of multiple rings which post fresh
4544  * buffers to the chip, and one special ring the chip uses to report
4545  * status back to the host.
4546  *
4547  * The special ring reports the status of received packets to the
4548  * host.  The chip does not write into the original descriptor the
4549  * RX buffer was obtained from.  The chip simply takes the original
4550  * descriptor as provided by the host, updates the status and length
4551  * field, then writes this into the next status ring entry.
4552  *
4553  * Each ring the host uses to post buffers to the chip is described
4554  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4555  * it is first placed into the on-chip ram.  When the packet's length
4556  * is known, it walks down the TG3_BDINFO entries to select the ring.
4557  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4558  * which is within the range of the new packet's length is chosen.
4559  *
4560  * The "separate ring for rx status" scheme may sound queer, but it makes
4561  * sense from a cache coherency perspective.  If only the host writes
4562  * to the buffer post rings, and only the chip writes to the rx status
4563  * rings, then cache lines never move beyond shared-modified state.
4564  * If both the host and chip were to write into the same ring, cache line
4565  * eviction could occur since both entities want it in an exclusive state.
4566  */
4567 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4568 {
4569         struct tg3 *tp = tnapi->tp;
4570         u32 work_mask, rx_std_posted = 0;
4571         u32 std_prod_idx, jmb_prod_idx;
4572         u32 sw_idx = tnapi->rx_rcb_ptr;
4573         u16 hw_idx;
4574         int received;
4575         struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
4576
4577         hw_idx = *(tnapi->rx_rcb_prod_idx);
4578         /*
4579          * We need to order the read of hw_idx and the read of
4580          * the opaque cookie.
4581          */
4582         rmb();
4583         work_mask = 0;
4584         received = 0;
4585         std_prod_idx = tpr->rx_std_prod_idx;
4586         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4587         while (sw_idx != hw_idx && budget > 0) {
4588                 struct ring_info *ri;
4589                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4590                 unsigned int len;
4591                 struct sk_buff *skb;
4592                 dma_addr_t dma_addr;
4593                 u32 opaque_key, desc_idx, *post_ptr;
4594                 bool hw_vlan __maybe_unused = false;
4595                 u16 vtag __maybe_unused = 0;
4596
4597                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4598                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4599                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4600                         ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4601                         dma_addr = dma_unmap_addr(ri, mapping);
4602                         skb = ri->skb;
4603                         post_ptr = &std_prod_idx;
4604                         rx_std_posted++;
4605                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4606                         ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4607                         dma_addr = dma_unmap_addr(ri, mapping);
4608                         skb = ri->skb;
4609                         post_ptr = &jmb_prod_idx;
4610                 } else
4611                         goto next_pkt_nopost;
4612
4613                 work_mask |= opaque_key;
4614
4615                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4616                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4617                 drop_it:
4618                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4619                                        desc_idx, *post_ptr);
4620                 drop_it_no_recycle:
4621                         /* Other statistics kept track of by card. */
4622                         tp->net_stats.rx_dropped++;
4623                         goto next_pkt;
4624                 }
4625
4626                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4627                       ETH_FCS_LEN;
4628
4629                 if (len > TG3_RX_COPY_THRESH(tp)) {
4630                         int skb_size;
4631
4632                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4633                                                     *post_ptr);
4634                         if (skb_size < 0)
4635                                 goto drop_it;
4636
4637                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4638                                          PCI_DMA_FROMDEVICE);
4639
4640                         /* Ensure that the update to the skb happens
4641                          * after the usage of the old DMA mapping.
4642                          */
4643                         smp_wmb();
4644
4645                         ri->skb = NULL;
4646
4647                         skb_put(skb, len);
4648                 } else {
4649                         struct sk_buff *copy_skb;
4650
4651                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4652                                        desc_idx, *post_ptr);
4653
4654                         copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
4655                                                     TG3_RAW_IP_ALIGN);
4656                         if (copy_skb == NULL)
4657                                 goto drop_it_no_recycle;
4658
4659                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
4660                         skb_put(copy_skb, len);
4661                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4662                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4663                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4664
4665                         /* We'll reuse the original ring buffer. */
4666                         skb = copy_skb;
4667                 }
4668
4669                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4670                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4671                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4672                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4673                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4674                 else
4675                         skb_checksum_none_assert(skb);
4676
4677                 skb->protocol = eth_type_trans(skb, tp->dev);
4678
4679                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4680                     skb->protocol != htons(ETH_P_8021Q)) {
4681                         dev_kfree_skb(skb);
4682                         goto next_pkt;
4683                 }
4684
4685                 if (desc->type_flags & RXD_FLAG_VLAN &&
4686                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
4687                         vtag = desc->err_vlan & RXD_VLAN_MASK;
4688 #if TG3_VLAN_TAG_USED
4689                         if (tp->vlgrp)
4690                                 hw_vlan = true;
4691                         else
4692 #endif
4693                         {
4694                                 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
4695                                                     __skb_push(skb, VLAN_HLEN);
4696
4697                                 memmove(ve, skb->data + VLAN_HLEN,
4698                                         ETH_ALEN * 2);
4699                                 ve->h_vlan_proto = htons(ETH_P_8021Q);
4700                                 ve->h_vlan_TCI = htons(vtag);
4701                         }
4702                 }
4703
4704 #if TG3_VLAN_TAG_USED
4705                 if (hw_vlan)
4706                         vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
4707                 else
4708 #endif
4709                         napi_gro_receive(&tnapi->napi, skb);
4710
4711                 received++;
4712                 budget--;
4713
4714 next_pkt:
4715                 (*post_ptr)++;
4716
4717                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4718                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4719                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4720                                      tpr->rx_std_prod_idx);
4721                         work_mask &= ~RXD_OPAQUE_RING_STD;
4722                         rx_std_posted = 0;
4723                 }
4724 next_pkt_nopost:
4725                 sw_idx++;
4726                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4727
4728                 /* Refresh hw_idx to see if there is new work */
4729                 if (sw_idx == hw_idx) {
4730                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4731                         rmb();
4732                 }
4733         }
4734
4735         /* ACK the status ring. */
4736         tnapi->rx_rcb_ptr = sw_idx;
4737         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4738
4739         /* Refill RX ring(s). */
4740         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4741                 if (work_mask & RXD_OPAQUE_RING_STD) {
4742                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4743                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4744                                      tpr->rx_std_prod_idx);
4745                 }
4746                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4747                         tpr->rx_jmb_prod_idx = jmb_prod_idx %
4748                                                TG3_RX_JUMBO_RING_SIZE;
4749                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4750                                      tpr->rx_jmb_prod_idx);
4751                 }
4752                 mmiowb();
4753         } else if (work_mask) {
4754                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4755                  * updated before the producer indices can be updated.
4756                  */
4757                 smp_wmb();
4758
4759                 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4760                 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4761
4762                 if (tnapi != &tp->napi[1])
4763                         napi_schedule(&tp->napi[1].napi);
4764         }
4765
4766         return received;
4767 }
4768
4769 static void tg3_poll_link(struct tg3 *tp)
4770 {
4771         /* handle link change and other phy events */
4772         if (!(tp->tg3_flags &
4773               (TG3_FLAG_USE_LINKCHG_REG |
4774                TG3_FLAG_POLL_SERDES))) {
4775                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4776
4777                 if (sblk->status & SD_STATUS_LINK_CHG) {
4778                         sblk->status = SD_STATUS_UPDATED |
4779                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4780                         spin_lock(&tp->lock);
4781                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4782                                 tw32_f(MAC_STATUS,
4783                                      (MAC_STATUS_SYNC_CHANGED |
4784                                       MAC_STATUS_CFG_CHANGED |
4785                                       MAC_STATUS_MI_COMPLETION |
4786                                       MAC_STATUS_LNKSTATE_CHANGED));
4787                                 udelay(40);
4788                         } else
4789                                 tg3_setup_phy(tp, 0);
4790                         spin_unlock(&tp->lock);
4791                 }
4792         }
4793 }
4794
4795 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4796                                 struct tg3_rx_prodring_set *dpr,
4797                                 struct tg3_rx_prodring_set *spr)
4798 {
4799         u32 si, di, cpycnt, src_prod_idx;
4800         int i, err = 0;
4801
4802         while (1) {
4803                 src_prod_idx = spr->rx_std_prod_idx;
4804
4805                 /* Make sure updates to the rx_std_buffers[] entries and the
4806                  * standard producer index are seen in the correct order.
4807                  */
4808                 smp_rmb();
4809
4810                 if (spr->rx_std_cons_idx == src_prod_idx)
4811                         break;
4812
4813                 if (spr->rx_std_cons_idx < src_prod_idx)
4814                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4815                 else
4816                         cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4817
4818                 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4819
4820                 si = spr->rx_std_cons_idx;
4821                 di = dpr->rx_std_prod_idx;
4822
4823                 for (i = di; i < di + cpycnt; i++) {
4824                         if (dpr->rx_std_buffers[i].skb) {
4825                                 cpycnt = i - di;
4826                                 err = -ENOSPC;
4827                                 break;
4828                         }
4829                 }
4830
4831                 if (!cpycnt)
4832                         break;
4833
4834                 /* Ensure that updates to the rx_std_buffers ring and the
4835                  * shadowed hardware producer ring from tg3_recycle_skb() are
4836                  * ordered correctly WRT the skb check above.
4837                  */
4838                 smp_rmb();
4839
4840                 memcpy(&dpr->rx_std_buffers[di],
4841                        &spr->rx_std_buffers[si],
4842                        cpycnt * sizeof(struct ring_info));
4843
4844                 for (i = 0; i < cpycnt; i++, di++, si++) {
4845                         struct tg3_rx_buffer_desc *sbd, *dbd;
4846                         sbd = &spr->rx_std[si];
4847                         dbd = &dpr->rx_std[di];
4848                         dbd->addr_hi = sbd->addr_hi;
4849                         dbd->addr_lo = sbd->addr_lo;
4850                 }
4851
4852                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4853                                        TG3_RX_RING_SIZE;
4854                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4855                                        TG3_RX_RING_SIZE;
4856         }
4857
4858         while (1) {
4859                 src_prod_idx = spr->rx_jmb_prod_idx;
4860
4861                 /* Make sure updates to the rx_jmb_buffers[] entries and
4862                  * the jumbo producer index are seen in the correct order.
4863                  */
4864                 smp_rmb();
4865
4866                 if (spr->rx_jmb_cons_idx == src_prod_idx)
4867                         break;
4868
4869                 if (spr->rx_jmb_cons_idx < src_prod_idx)
4870                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4871                 else
4872                         cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4873
4874                 cpycnt = min(cpycnt,
4875                              TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4876
4877                 si = spr->rx_jmb_cons_idx;
4878                 di = dpr->rx_jmb_prod_idx;
4879
4880                 for (i = di; i < di + cpycnt; i++) {
4881                         if (dpr->rx_jmb_buffers[i].skb) {
4882                                 cpycnt = i - di;
4883                                 err = -ENOSPC;
4884                                 break;
4885                         }
4886                 }
4887
4888                 if (!cpycnt)
4889                         break;
4890
4891                 /* Ensure that updates to the rx_jmb_buffers ring and the
4892                  * shadowed hardware producer ring from tg3_recycle_skb() are
4893                  * ordered correctly WRT the skb check above.
4894                  */
4895                 smp_rmb();
4896
4897                 memcpy(&dpr->rx_jmb_buffers[di],
4898                        &spr->rx_jmb_buffers[si],
4899                        cpycnt * sizeof(struct ring_info));
4900
4901                 for (i = 0; i < cpycnt; i++, di++, si++) {
4902                         struct tg3_rx_buffer_desc *sbd, *dbd;
4903                         sbd = &spr->rx_jmb[si].std;
4904                         dbd = &dpr->rx_jmb[di].std;
4905                         dbd->addr_hi = sbd->addr_hi;
4906                         dbd->addr_lo = sbd->addr_lo;
4907                 }
4908
4909                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4910                                        TG3_RX_JUMBO_RING_SIZE;
4911                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4912                                        TG3_RX_JUMBO_RING_SIZE;
4913         }
4914
4915         return err;
4916 }
4917
4918 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4919 {
4920         struct tg3 *tp = tnapi->tp;
4921
4922         /* run TX completion thread */
4923         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4924                 tg3_tx(tnapi);
4925                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4926                         return work_done;
4927         }
4928
4929         /* run RX thread, within the bounds set by NAPI.
4930          * All RX "locking" is done by ensuring outside
4931          * code synchronizes with tg3->napi.poll()
4932          */
4933         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4934                 work_done += tg3_rx(tnapi, budget - work_done);
4935
4936         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4937                 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
4938                 int i, err = 0;
4939                 u32 std_prod_idx = dpr->rx_std_prod_idx;
4940                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
4941
4942                 for (i = 1; i < tp->irq_cnt; i++)
4943                         err |= tg3_rx_prodring_xfer(tp, dpr,
4944                                                     &tp->napi[i].prodring);
4945
4946                 wmb();
4947
4948                 if (std_prod_idx != dpr->rx_std_prod_idx)
4949                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4950                                      dpr->rx_std_prod_idx);
4951
4952                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
4953                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4954                                      dpr->rx_jmb_prod_idx);
4955
4956                 mmiowb();
4957
4958                 if (err)
4959                         tw32_f(HOSTCC_MODE, tp->coal_now);
4960         }
4961
4962         return work_done;
4963 }
4964
4965 static int tg3_poll_msix(struct napi_struct *napi, int budget)
4966 {
4967         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4968         struct tg3 *tp = tnapi->tp;
4969         int work_done = 0;
4970         struct tg3_hw_status *sblk = tnapi->hw_status;
4971
4972         while (1) {
4973                 work_done = tg3_poll_work(tnapi, work_done, budget);
4974
4975                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4976                         goto tx_recovery;
4977
4978                 if (unlikely(work_done >= budget))
4979                         break;
4980
4981                 /* tp->last_tag is used in tg3_int_reenable() below
4982                  * to tell the hw how much work has been processed,
4983                  * so we must read it before checking for more work.
4984                  */
4985                 tnapi->last_tag = sblk->status_tag;
4986                 tnapi->last_irq_tag = tnapi->last_tag;
4987                 rmb();
4988
4989                 /* check for RX/TX work to do */
4990                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4991                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
4992                         napi_complete(napi);
4993                         /* Reenable interrupts. */
4994                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
4995                         mmiowb();
4996                         break;
4997                 }
4998         }
4999
5000         return work_done;
5001
5002 tx_recovery:
5003         /* work_done is guaranteed to be less than budget. */
5004         napi_complete(napi);
5005         schedule_work(&tp->reset_task);
5006         return work_done;
5007 }
5008
5009 static int tg3_poll(struct napi_struct *napi, int budget)
5010 {
5011         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5012         struct tg3 *tp = tnapi->tp;
5013         int work_done = 0;
5014         struct tg3_hw_status *sblk = tnapi->hw_status;
5015
5016         while (1) {
5017                 tg3_poll_link(tp);
5018
5019                 work_done = tg3_poll_work(tnapi, work_done, budget);
5020
5021                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5022                         goto tx_recovery;
5023
5024                 if (unlikely(work_done >= budget))
5025                         break;
5026
5027                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5028                         /* tp->last_tag is used in tg3_int_reenable() below
5029                          * to tell the hw how much work has been processed,
5030                          * so we must read it before checking for more work.
5031                          */
5032                         tnapi->last_tag = sblk->status_tag;
5033                         tnapi->last_irq_tag = tnapi->last_tag;
5034                         rmb();
5035                 } else
5036                         sblk->status &= ~SD_STATUS_UPDATED;
5037
5038                 if (likely(!tg3_has_work(tnapi))) {
5039                         napi_complete(napi);
5040                         tg3_int_reenable(tnapi);
5041                         break;
5042                 }
5043         }
5044
5045         return work_done;
5046
5047 tx_recovery:
5048         /* work_done is guaranteed to be less than budget. */
5049         napi_complete(napi);
5050         schedule_work(&tp->reset_task);
5051         return work_done;
5052 }
5053
5054 static void tg3_napi_disable(struct tg3 *tp)
5055 {
5056         int i;
5057
5058         for (i = tp->irq_cnt - 1; i >= 0; i--)
5059                 napi_disable(&tp->napi[i].napi);
5060 }
5061
5062 static void tg3_napi_enable(struct tg3 *tp)
5063 {
5064         int i;
5065
5066         for (i = 0; i < tp->irq_cnt; i++)
5067                 napi_enable(&tp->napi[i].napi);
5068 }
5069
5070 static void tg3_napi_init(struct tg3 *tp)
5071 {
5072         int i;
5073
5074         netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
5075         for (i = 1; i < tp->irq_cnt; i++)
5076                 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
5077 }
5078
5079 static void tg3_napi_fini(struct tg3 *tp)
5080 {
5081         int i;
5082
5083         for (i = 0; i < tp->irq_cnt; i++)
5084                 netif_napi_del(&tp->napi[i].napi);
5085 }
5086
5087 static inline void tg3_netif_stop(struct tg3 *tp)
5088 {
5089         tp->dev->trans_start = jiffies; /* prevent tx timeout */
5090         tg3_napi_disable(tp);
5091         netif_tx_disable(tp->dev);
5092 }
5093
5094 static inline void tg3_netif_start(struct tg3 *tp)
5095 {
5096         /* NOTE: unconditional netif_tx_wake_all_queues is only
5097          * appropriate so long as all callers are assured to
5098          * have free tx slots (such as after tg3_init_hw)
5099          */
5100         netif_tx_wake_all_queues(tp->dev);
5101
5102         tg3_napi_enable(tp);
5103         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
5104         tg3_enable_ints(tp);
5105 }
5106
5107 static void tg3_irq_quiesce(struct tg3 *tp)
5108 {
5109         int i;
5110
5111         BUG_ON(tp->irq_sync);
5112
5113         tp->irq_sync = 1;
5114         smp_mb();
5115
5116         for (i = 0; i < tp->irq_cnt; i++)
5117                 synchronize_irq(tp->napi[i].irq_vec);
5118 }
5119
5120 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5121  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5122  * with as well.  Most of the time, this is not necessary except when
5123  * shutting down the device.
5124  */
5125 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5126 {
5127         spin_lock_bh(&tp->lock);
5128         if (irq_sync)
5129                 tg3_irq_quiesce(tp);
5130 }
5131
5132 static inline void tg3_full_unlock(struct tg3 *tp)
5133 {
5134         spin_unlock_bh(&tp->lock);
5135 }
5136
5137 /* One-shot MSI handler - Chip automatically disables interrupt
5138  * after sending MSI so driver doesn't have to do it.
5139  */
5140 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5141 {
5142         struct tg3_napi *tnapi = dev_id;
5143         struct tg3 *tp = tnapi->tp;
5144
5145         prefetch(tnapi->hw_status);
5146         if (tnapi->rx_rcb)
5147                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5148
5149         if (likely(!tg3_irq_sync(tp)))
5150                 napi_schedule(&tnapi->napi);
5151
5152         return IRQ_HANDLED;
5153 }
5154
5155 /* MSI ISR - No need to check for interrupt sharing and no need to
5156  * flush status block and interrupt mailbox. PCI ordering rules
5157  * guarantee that MSI will arrive after the status block.
5158  */
5159 static irqreturn_t tg3_msi(int irq, void *dev_id)
5160 {
5161         struct tg3_napi *tnapi = dev_id;
5162         struct tg3 *tp = tnapi->tp;
5163
5164         prefetch(tnapi->hw_status);
5165         if (tnapi->rx_rcb)
5166                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5167         /*
5168          * Writing any value to intr-mbox-0 clears PCI INTA# and
5169          * chip-internal interrupt pending events.
5170          * Writing non-zero to intr-mbox-0 additional tells the
5171          * NIC to stop sending us irqs, engaging "in-intr-handler"
5172          * event coalescing.
5173          */
5174         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5175         if (likely(!tg3_irq_sync(tp)))
5176                 napi_schedule(&tnapi->napi);
5177
5178         return IRQ_RETVAL(1);
5179 }
5180
5181 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5182 {
5183         struct tg3_napi *tnapi = dev_id;
5184         struct tg3 *tp = tnapi->tp;
5185         struct tg3_hw_status *sblk = tnapi->hw_status;
5186         unsigned int handled = 1;
5187
5188         /* In INTx mode, it is possible for the interrupt to arrive at
5189          * the CPU before the status block posted prior to the interrupt.
5190          * Reading the PCI State register will confirm whether the
5191          * interrupt is ours and will flush the status block.
5192          */
5193         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5194                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5195                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5196                         handled = 0;
5197                         goto out;
5198                 }
5199         }
5200
5201         /*
5202          * Writing any value to intr-mbox-0 clears PCI INTA# and
5203          * chip-internal interrupt pending events.
5204          * Writing non-zero to intr-mbox-0 additional tells the
5205          * NIC to stop sending us irqs, engaging "in-intr-handler"
5206          * event coalescing.
5207          *
5208          * Flush the mailbox to de-assert the IRQ immediately to prevent
5209          * spurious interrupts.  The flush impacts performance but
5210          * excessive spurious interrupts can be worse in some cases.
5211          */
5212         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5213         if (tg3_irq_sync(tp))
5214                 goto out;
5215         sblk->status &= ~SD_STATUS_UPDATED;
5216         if (likely(tg3_has_work(tnapi))) {
5217                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5218                 napi_schedule(&tnapi->napi);
5219         } else {
5220                 /* No work, shared interrupt perhaps?  re-enable
5221                  * interrupts, and flush that PCI write
5222                  */
5223                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5224                                0x00000000);
5225         }
5226 out:
5227         return IRQ_RETVAL(handled);
5228 }
5229
5230 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5231 {
5232         struct tg3_napi *tnapi = dev_id;
5233         struct tg3 *tp = tnapi->tp;
5234         struct tg3_hw_status *sblk = tnapi->hw_status;
5235         unsigned int handled = 1;
5236
5237         /* In INTx mode, it is possible for the interrupt to arrive at
5238          * the CPU before the status block posted prior to the interrupt.
5239          * Reading the PCI State register will confirm whether the
5240          * interrupt is ours and will flush the status block.
5241          */
5242         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5243                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5244                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5245                         handled = 0;
5246                         goto out;
5247                 }
5248         }
5249
5250         /*
5251          * writing any value to intr-mbox-0 clears PCI INTA# and
5252          * chip-internal interrupt pending events.
5253          * writing non-zero to intr-mbox-0 additional tells the
5254          * NIC to stop sending us irqs, engaging "in-intr-handler"
5255          * event coalescing.
5256          *
5257          * Flush the mailbox to de-assert the IRQ immediately to prevent
5258          * spurious interrupts.  The flush impacts performance but
5259          * excessive spurious interrupts can be worse in some cases.
5260          */
5261         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5262
5263         /*
5264          * In a shared interrupt configuration, sometimes other devices'
5265          * interrupts will scream.  We record the current status tag here
5266          * so that the above check can report that the screaming interrupts
5267          * are unhandled.  Eventually they will be silenced.
5268          */
5269         tnapi->last_irq_tag = sblk->status_tag;
5270
5271         if (tg3_irq_sync(tp))
5272                 goto out;
5273
5274         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5275
5276         napi_schedule(&tnapi->napi);
5277
5278 out:
5279         return IRQ_RETVAL(handled);
5280 }
5281
5282 /* ISR for interrupt test */
5283 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5284 {
5285         struct tg3_napi *tnapi = dev_id;
5286         struct tg3 *tp = tnapi->tp;
5287         struct tg3_hw_status *sblk = tnapi->hw_status;
5288
5289         if ((sblk->status & SD_STATUS_UPDATED) ||
5290             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5291                 tg3_disable_ints(tp);
5292                 return IRQ_RETVAL(1);
5293         }
5294         return IRQ_RETVAL(0);
5295 }
5296
5297 static int tg3_init_hw(struct tg3 *, int);
5298 static int tg3_halt(struct tg3 *, int, int);
5299
5300 /* Restart hardware after configuration changes, self-test, etc.
5301  * Invoked with tp->lock held.
5302  */
5303 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5304         __releases(tp->lock)
5305         __acquires(tp->lock)
5306 {
5307         int err;
5308
5309         err = tg3_init_hw(tp, reset_phy);
5310         if (err) {
5311                 netdev_err(tp->dev,
5312                            "Failed to re-initialize device, aborting\n");
5313                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5314                 tg3_full_unlock(tp);
5315                 del_timer_sync(&tp->timer);
5316                 tp->irq_sync = 0;
5317                 tg3_napi_enable(tp);
5318                 dev_close(tp->dev);
5319                 tg3_full_lock(tp, 0);
5320         }
5321         return err;
5322 }
5323
5324 #ifdef CONFIG_NET_POLL_CONTROLLER
5325 static void tg3_poll_controller(struct net_device *dev)
5326 {
5327         int i;
5328         struct tg3 *tp = netdev_priv(dev);
5329
5330         for (i = 0; i < tp->irq_cnt; i++)
5331                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5332 }
5333 #endif
5334
5335 static void tg3_reset_task(struct work_struct *work)
5336 {
5337         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5338         int err;
5339         unsigned int restart_timer;
5340
5341         tg3_full_lock(tp, 0);
5342
5343         if (!netif_running(tp->dev)) {
5344                 tg3_full_unlock(tp);
5345                 return;
5346         }
5347
5348         tg3_full_unlock(tp);
5349
5350         tg3_phy_stop(tp);
5351
5352         tg3_netif_stop(tp);
5353
5354         tg3_full_lock(tp, 1);
5355
5356         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5357         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5358
5359         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5360                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5361                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5362                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5363                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5364         }
5365
5366         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5367         err = tg3_init_hw(tp, 1);
5368         if (err)
5369                 goto out;
5370
5371         tg3_netif_start(tp);
5372
5373         if (restart_timer)
5374                 mod_timer(&tp->timer, jiffies + 1);
5375
5376 out:
5377         tg3_full_unlock(tp);
5378
5379         if (!err)
5380                 tg3_phy_start(tp);
5381 }
5382
5383 static void tg3_dump_short_state(struct tg3 *tp)
5384 {
5385         netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5386                    tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5387         netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5388                    tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5389 }
5390
5391 static void tg3_tx_timeout(struct net_device *dev)
5392 {
5393         struct tg3 *tp = netdev_priv(dev);
5394
5395         if (netif_msg_tx_err(tp)) {
5396                 netdev_err(dev, "transmit timed out, resetting\n");
5397                 tg3_dump_short_state(tp);
5398         }
5399
5400         schedule_work(&tp->reset_task);
5401 }
5402
5403 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5404 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5405 {
5406         u32 base = (u32) mapping & 0xffffffff;
5407
5408         return (base > 0xffffdcc0) && (base + len + 8 < base);
5409 }
5410
5411 /* Test for DMA addresses > 40-bit */
5412 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5413                                           int len)
5414 {
5415 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5416         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5417                 return ((u64) mapping + len) > DMA_BIT_MASK(40);
5418         return 0;
5419 #else
5420         return 0;
5421 #endif
5422 }
5423
5424 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5425
5426 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5427 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5428                                        struct sk_buff *skb, u32 last_plus_one,
5429                                        u32 *start, u32 base_flags, u32 mss)
5430 {
5431         struct tg3 *tp = tnapi->tp;
5432         struct sk_buff *new_skb;
5433         dma_addr_t new_addr = 0;
5434         u32 entry = *start;
5435         int i, ret = 0;
5436
5437         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5438                 new_skb = skb_copy(skb, GFP_ATOMIC);
5439         else {
5440                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5441
5442                 new_skb = skb_copy_expand(skb,
5443                                           skb_headroom(skb) + more_headroom,
5444                                           skb_tailroom(skb), GFP_ATOMIC);
5445         }
5446
5447         if (!new_skb) {
5448                 ret = -1;
5449         } else {
5450                 /* New SKB is guaranteed to be linear. */
5451                 entry = *start;
5452                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5453                                           PCI_DMA_TODEVICE);
5454                 /* Make sure the mapping succeeded */
5455                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5456                         ret = -1;
5457                         dev_kfree_skb(new_skb);
5458                         new_skb = NULL;
5459
5460                 /* Make sure new skb does not cross any 4G boundaries.
5461                  * Drop the packet if it does.
5462                  */
5463                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5464                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5465                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5466                                          PCI_DMA_TODEVICE);
5467                         ret = -1;
5468                         dev_kfree_skb(new_skb);
5469                         new_skb = NULL;
5470                 } else {
5471                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5472                                     base_flags, 1 | (mss << 1));
5473                         *start = NEXT_TX(entry);
5474                 }
5475         }
5476
5477         /* Now clean up the sw ring entries. */
5478         i = 0;
5479         while (entry != last_plus_one) {
5480                 int len;
5481
5482                 if (i == 0)
5483                         len = skb_headlen(skb);
5484                 else
5485                         len = skb_shinfo(skb)->frags[i-1].size;
5486
5487                 pci_unmap_single(tp->pdev,
5488                                  dma_unmap_addr(&tnapi->tx_buffers[entry],
5489                                                 mapping),
5490                                  len, PCI_DMA_TODEVICE);
5491                 if (i == 0) {
5492                         tnapi->tx_buffers[entry].skb = new_skb;
5493                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5494                                            new_addr);
5495                 } else {
5496                         tnapi->tx_buffers[entry].skb = NULL;
5497                 }
5498                 entry = NEXT_TX(entry);
5499                 i++;
5500         }
5501
5502         dev_kfree_skb(skb);
5503
5504         return ret;
5505 }
5506
5507 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5508                         dma_addr_t mapping, int len, u32 flags,
5509                         u32 mss_and_is_end)
5510 {
5511         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5512         int is_end = (mss_and_is_end & 0x1);
5513         u32 mss = (mss_and_is_end >> 1);
5514         u32 vlan_tag = 0;
5515
5516         if (is_end)
5517                 flags |= TXD_FLAG_END;
5518         if (flags & TXD_FLAG_VLAN) {
5519                 vlan_tag = flags >> 16;
5520                 flags &= 0xffff;
5521         }
5522         vlan_tag |= (mss << TXD_MSS_SHIFT);
5523
5524         txd->addr_hi = ((u64) mapping >> 32);
5525         txd->addr_lo = ((u64) mapping & 0xffffffff);
5526         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5527         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5528 }
5529
5530 /* hard_start_xmit for devices that don't have any bugs and
5531  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5532  */
5533 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5534                                   struct net_device *dev)
5535 {
5536         struct tg3 *tp = netdev_priv(dev);
5537         u32 len, entry, base_flags, mss;
5538         dma_addr_t mapping;
5539         struct tg3_napi *tnapi;
5540         struct netdev_queue *txq;
5541         unsigned int i, last;
5542
5543         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5544         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5545         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5546                 tnapi++;
5547
5548         /* We are running in BH disabled context with netif_tx_lock
5549          * and TX reclaim runs via tp->napi.poll inside of a software
5550          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5551          * no IRQ context deadlocks to worry about either.  Rejoice!
5552          */
5553         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5554                 if (!netif_tx_queue_stopped(txq)) {
5555                         netif_tx_stop_queue(txq);
5556
5557                         /* This is a hard error, log it. */
5558                         netdev_err(dev,
5559                                    "BUG! Tx Ring full when queue awake!\n");
5560                 }
5561                 return NETDEV_TX_BUSY;
5562         }
5563
5564         entry = tnapi->tx_prod;
5565         base_flags = 0;
5566         mss = skb_shinfo(skb)->gso_size;
5567         if (mss) {
5568                 int tcp_opt_len, ip_tcp_len;
5569                 u32 hdrlen;
5570
5571                 if (skb_header_cloned(skb) &&
5572                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5573                         dev_kfree_skb(skb);
5574                         goto out_unlock;
5575                 }
5576
5577                 if (skb_is_gso_v6(skb)) {
5578                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5579                 } else {
5580                         struct iphdr *iph = ip_hdr(skb);
5581
5582                         tcp_opt_len = tcp_optlen(skb);
5583                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5584
5585                         iph->check = 0;
5586                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5587                         hdrlen = ip_tcp_len + tcp_opt_len;
5588                 }
5589
5590                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5591                         mss |= (hdrlen & 0xc) << 12;
5592                         if (hdrlen & 0x10)
5593                                 base_flags |= 0x00000010;
5594                         base_flags |= (hdrlen & 0x3e0) << 5;
5595                 } else
5596                         mss |= hdrlen << 9;
5597
5598                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5599                                TXD_FLAG_CPU_POST_DMA);
5600
5601                 tcp_hdr(skb)->check = 0;
5602
5603         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5604                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5605         }
5606
5607 #if TG3_VLAN_TAG_USED
5608         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5609                 base_flags |= (TXD_FLAG_VLAN |
5610                                (vlan_tx_tag_get(skb) << 16));
5611 #endif
5612
5613         len = skb_headlen(skb);
5614
5615         /* Queue skb data, a.k.a. the main skb fragment. */
5616         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5617         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5618                 dev_kfree_skb(skb);
5619                 goto out_unlock;
5620         }
5621
5622         tnapi->tx_buffers[entry].skb = skb;
5623         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5624
5625         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5626             !mss && skb->len > ETH_DATA_LEN)
5627                 base_flags |= TXD_FLAG_JMB_PKT;
5628
5629         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5630                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5631
5632         entry = NEXT_TX(entry);
5633
5634         /* Now loop through additional data fragments, and queue them. */
5635         if (skb_shinfo(skb)->nr_frags > 0) {
5636                 last = skb_shinfo(skb)->nr_frags - 1;
5637                 for (i = 0; i <= last; i++) {
5638                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5639
5640                         len = frag->size;
5641                         mapping = pci_map_page(tp->pdev,
5642                                                frag->page,
5643                                                frag->page_offset,
5644                                                len, PCI_DMA_TODEVICE);
5645                         if (pci_dma_mapping_error(tp->pdev, mapping))
5646                                 goto dma_error;
5647
5648                         tnapi->tx_buffers[entry].skb = NULL;
5649                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5650                                            mapping);
5651
5652                         tg3_set_txd(tnapi, entry, mapping, len,
5653                                     base_flags, (i == last) | (mss << 1));
5654
5655                         entry = NEXT_TX(entry);
5656                 }
5657         }
5658
5659         /* Packets are ready, update Tx producer idx local and on card. */
5660         tw32_tx_mbox(tnapi->prodmbox, entry);
5661
5662         tnapi->tx_prod = entry;
5663         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5664                 netif_tx_stop_queue(txq);
5665
5666                 /* netif_tx_stop_queue() must be done before checking
5667                  * checking tx index in tg3_tx_avail() below, because in
5668                  * tg3_tx(), we update tx index before checking for
5669                  * netif_tx_queue_stopped().
5670                  */
5671                 smp_mb();
5672                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5673                         netif_tx_wake_queue(txq);
5674         }
5675
5676 out_unlock:
5677         mmiowb();
5678
5679         return NETDEV_TX_OK;
5680
5681 dma_error:
5682         last = i;
5683         entry = tnapi->tx_prod;
5684         tnapi->tx_buffers[entry].skb = NULL;
5685         pci_unmap_single(tp->pdev,
5686                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5687                          skb_headlen(skb),
5688                          PCI_DMA_TODEVICE);
5689         for (i = 0; i <= last; i++) {
5690                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5691                 entry = NEXT_TX(entry);
5692
5693                 pci_unmap_page(tp->pdev,
5694                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5695                                               mapping),
5696                                frag->size, PCI_DMA_TODEVICE);
5697         }
5698
5699         dev_kfree_skb(skb);
5700         return NETDEV_TX_OK;
5701 }
5702
5703 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5704                                           struct net_device *);
5705
5706 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5707  * TSO header is greater than 80 bytes.
5708  */
5709 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5710 {
5711         struct sk_buff *segs, *nskb;
5712         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5713
5714         /* Estimate the number of fragments in the worst case */
5715         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5716                 netif_stop_queue(tp->dev);
5717
5718                 /* netif_tx_stop_queue() must be done before checking
5719                  * checking tx index in tg3_tx_avail() below, because in
5720                  * tg3_tx(), we update tx index before checking for
5721                  * netif_tx_queue_stopped().
5722                  */
5723                 smp_mb();
5724                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5725                         return NETDEV_TX_BUSY;
5726
5727                 netif_wake_queue(tp->dev);
5728         }
5729
5730         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5731         if (IS_ERR(segs))
5732                 goto tg3_tso_bug_end;
5733
5734         do {
5735                 nskb = segs;
5736                 segs = segs->next;
5737                 nskb->next = NULL;
5738                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5739         } while (segs);
5740
5741 tg3_tso_bug_end:
5742         dev_kfree_skb(skb);
5743
5744         return NETDEV_TX_OK;
5745 }
5746
5747 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5748  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5749  */
5750 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5751                                           struct net_device *dev)
5752 {