tg3: adapt tg3 to use reworked PCI PM code
[linux-2.6.git] / drivers / net / tg3.c
1 /*
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  * Copyright (C) 2005-2007 Broadcom Corporation.
8  *
9  * Firmware is:
10  *      Derived from proprietary unpublished source code,
11  *      Copyright (C) 2000-2003 Broadcom Corporation.
12  *
13  *      Permission is hereby granted for the distribution of this firmware
14  *      data in hexadecimal or equivalent format, provided this copyright
15  *      notice is accompanying it.
16  */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
26 #include <linux/in.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/phy.h>
36 #include <linux/brcmphy.h>
37 #include <linux/if_vlan.h>
38 #include <linux/ip.h>
39 #include <linux/tcp.h>
40 #include <linux/workqueue.h>
41 #include <linux/prefetch.h>
42 #include <linux/dma-mapping.h>
43
44 #include <net/checksum.h>
45 #include <net/ip.h>
46
47 #include <asm/system.h>
48 #include <asm/io.h>
49 #include <asm/byteorder.h>
50 #include <asm/uaccess.h>
51
52 #ifdef CONFIG_SPARC
53 #include <asm/idprom.h>
54 #include <asm/prom.h>
55 #endif
56
57 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
58 #define TG3_VLAN_TAG_USED 1
59 #else
60 #define TG3_VLAN_TAG_USED 0
61 #endif
62
63 #define TG3_TSO_SUPPORT 1
64
65 #include "tg3.h"
66
67 #define DRV_MODULE_NAME         "tg3"
68 #define PFX DRV_MODULE_NAME     ": "
69 #define DRV_MODULE_VERSION      "3.93"
70 #define DRV_MODULE_RELDATE      "May 22, 2008"
71
72 #define TG3_DEF_MAC_MODE        0
73 #define TG3_DEF_RX_MODE         0
74 #define TG3_DEF_TX_MODE         0
75 #define TG3_DEF_MSG_ENABLE        \
76         (NETIF_MSG_DRV          | \
77          NETIF_MSG_PROBE        | \
78          NETIF_MSG_LINK         | \
79          NETIF_MSG_TIMER        | \
80          NETIF_MSG_IFDOWN       | \
81          NETIF_MSG_IFUP         | \
82          NETIF_MSG_RX_ERR       | \
83          NETIF_MSG_TX_ERR)
84
85 /* length of time before we decide the hardware is borked,
86  * and dev->tx_timeout() should be called to fix the problem
87  */
88 #define TG3_TX_TIMEOUT                  (5 * HZ)
89
90 /* hardware minimum and maximum for a single frame's data payload */
91 #define TG3_MIN_MTU                     60
92 #define TG3_MAX_MTU(tp) \
93         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
94
95 /* These numbers seem to be hard coded in the NIC firmware somehow.
96  * You can't change the ring sizes, but you can change where you place
97  * them in the NIC onboard memory.
98  */
99 #define TG3_RX_RING_SIZE                512
100 #define TG3_DEF_RX_RING_PENDING         200
101 #define TG3_RX_JUMBO_RING_SIZE          256
102 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
103
104 /* Do not place this n-ring entries value into the tp struct itself,
105  * we really want to expose these constants to GCC so that modulo et
106  * al.  operations are done with shifts and masks instead of with
107  * hw multiply/modulo instructions.  Another solution would be to
108  * replace things like '% foo' with '& (foo - 1)'.
109  */
110 #define TG3_RX_RCB_RING_SIZE(tp)        \
111         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
112
113 #define TG3_TX_RING_SIZE                512
114 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
115
116 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
117                                  TG3_RX_RING_SIZE)
118 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
119                                  TG3_RX_JUMBO_RING_SIZE)
120 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
121                                    TG3_RX_RCB_RING_SIZE(tp))
122 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
123                                  TG3_TX_RING_SIZE)
124 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
125
126 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
127 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
128
129 /* minimum number of free TX descriptors required to wake up TX process */
130 #define TG3_TX_WAKEUP_THRESH(tp)                ((tp)->tx_pending / 4)
131
132 /* number of ETHTOOL_GSTATS u64's */
133 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
134
135 #define TG3_NUM_TEST            6
136
137 static char version[] __devinitdata =
138         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
139
140 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
141 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
142 MODULE_LICENSE("GPL");
143 MODULE_VERSION(DRV_MODULE_VERSION);
144
145 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
146 module_param(tg3_debug, int, 0);
147 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
148
149 static struct pci_device_id tg3_pci_tbl[] = {
150         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
151         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
152         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
153         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
154         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
155         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
156         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
157         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
158         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
159         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
160         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
161         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
162         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
163         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
164         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
165         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
166         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
167         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
168         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
169         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
170         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
171         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5785)},
209         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
210         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
211         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
212         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
213         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
214         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
215         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
216         {}
217 };
218
219 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
220
221 static const struct {
222         const char string[ETH_GSTRING_LEN];
223 } ethtool_stats_keys[TG3_NUM_STATS] = {
224         { "rx_octets" },
225         { "rx_fragments" },
226         { "rx_ucast_packets" },
227         { "rx_mcast_packets" },
228         { "rx_bcast_packets" },
229         { "rx_fcs_errors" },
230         { "rx_align_errors" },
231         { "rx_xon_pause_rcvd" },
232         { "rx_xoff_pause_rcvd" },
233         { "rx_mac_ctrl_rcvd" },
234         { "rx_xoff_entered" },
235         { "rx_frame_too_long_errors" },
236         { "rx_jabbers" },
237         { "rx_undersize_packets" },
238         { "rx_in_length_errors" },
239         { "rx_out_length_errors" },
240         { "rx_64_or_less_octet_packets" },
241         { "rx_65_to_127_octet_packets" },
242         { "rx_128_to_255_octet_packets" },
243         { "rx_256_to_511_octet_packets" },
244         { "rx_512_to_1023_octet_packets" },
245         { "rx_1024_to_1522_octet_packets" },
246         { "rx_1523_to_2047_octet_packets" },
247         { "rx_2048_to_4095_octet_packets" },
248         { "rx_4096_to_8191_octet_packets" },
249         { "rx_8192_to_9022_octet_packets" },
250
251         { "tx_octets" },
252         { "tx_collisions" },
253
254         { "tx_xon_sent" },
255         { "tx_xoff_sent" },
256         { "tx_flow_control" },
257         { "tx_mac_errors" },
258         { "tx_single_collisions" },
259         { "tx_mult_collisions" },
260         { "tx_deferred" },
261         { "tx_excessive_collisions" },
262         { "tx_late_collisions" },
263         { "tx_collide_2times" },
264         { "tx_collide_3times" },
265         { "tx_collide_4times" },
266         { "tx_collide_5times" },
267         { "tx_collide_6times" },
268         { "tx_collide_7times" },
269         { "tx_collide_8times" },
270         { "tx_collide_9times" },
271         { "tx_collide_10times" },
272         { "tx_collide_11times" },
273         { "tx_collide_12times" },
274         { "tx_collide_13times" },
275         { "tx_collide_14times" },
276         { "tx_collide_15times" },
277         { "tx_ucast_packets" },
278         { "tx_mcast_packets" },
279         { "tx_bcast_packets" },
280         { "tx_carrier_sense_errors" },
281         { "tx_discards" },
282         { "tx_errors" },
283
284         { "dma_writeq_full" },
285         { "dma_write_prioq_full" },
286         { "rxbds_empty" },
287         { "rx_discards" },
288         { "rx_errors" },
289         { "rx_threshold_hit" },
290
291         { "dma_readq_full" },
292         { "dma_read_prioq_full" },
293         { "tx_comp_queue_full" },
294
295         { "ring_set_send_prod_index" },
296         { "ring_status_update" },
297         { "nic_irqs" },
298         { "nic_avoided_irqs" },
299         { "nic_tx_threshold_hit" }
300 };
301
302 static const struct {
303         const char string[ETH_GSTRING_LEN];
304 } ethtool_test_keys[TG3_NUM_TEST] = {
305         { "nvram test     (online) " },
306         { "link test      (online) " },
307         { "register test  (offline)" },
308         { "memory test    (offline)" },
309         { "loopback test  (offline)" },
310         { "interrupt test (offline)" },
311 };
312
313 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
314 {
315         writel(val, tp->regs + off);
316 }
317
318 static u32 tg3_read32(struct tg3 *tp, u32 off)
319 {
320         return (readl(tp->regs + off));
321 }
322
323 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
324 {
325         writel(val, tp->aperegs + off);
326 }
327
328 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
329 {
330         return (readl(tp->aperegs + off));
331 }
332
333 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
334 {
335         unsigned long flags;
336
337         spin_lock_irqsave(&tp->indirect_lock, flags);
338         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
339         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
340         spin_unlock_irqrestore(&tp->indirect_lock, flags);
341 }
342
343 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
344 {
345         writel(val, tp->regs + off);
346         readl(tp->regs + off);
347 }
348
349 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
350 {
351         unsigned long flags;
352         u32 val;
353
354         spin_lock_irqsave(&tp->indirect_lock, flags);
355         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
356         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
357         spin_unlock_irqrestore(&tp->indirect_lock, flags);
358         return val;
359 }
360
361 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
362 {
363         unsigned long flags;
364
365         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
366                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
367                                        TG3_64BIT_REG_LOW, val);
368                 return;
369         }
370         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
371                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
372                                        TG3_64BIT_REG_LOW, val);
373                 return;
374         }
375
376         spin_lock_irqsave(&tp->indirect_lock, flags);
377         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
378         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
379         spin_unlock_irqrestore(&tp->indirect_lock, flags);
380
381         /* In indirect mode when disabling interrupts, we also need
382          * to clear the interrupt bit in the GRC local ctrl register.
383          */
384         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
385             (val == 0x1)) {
386                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
387                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
388         }
389 }
390
391 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
392 {
393         unsigned long flags;
394         u32 val;
395
396         spin_lock_irqsave(&tp->indirect_lock, flags);
397         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
398         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
399         spin_unlock_irqrestore(&tp->indirect_lock, flags);
400         return val;
401 }
402
403 /* usec_wait specifies the wait time in usec when writing to certain registers
404  * where it is unsafe to read back the register without some delay.
405  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
406  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
407  */
408 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
409 {
410         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
411             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
412                 /* Non-posted methods */
413                 tp->write32(tp, off, val);
414         else {
415                 /* Posted method */
416                 tg3_write32(tp, off, val);
417                 if (usec_wait)
418                         udelay(usec_wait);
419                 tp->read32(tp, off);
420         }
421         /* Wait again after the read for the posted method to guarantee that
422          * the wait time is met.
423          */
424         if (usec_wait)
425                 udelay(usec_wait);
426 }
427
428 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
429 {
430         tp->write32_mbox(tp, off, val);
431         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
432             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
433                 tp->read32_mbox(tp, off);
434 }
435
436 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
437 {
438         void __iomem *mbox = tp->regs + off;
439         writel(val, mbox);
440         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
441                 writel(val, mbox);
442         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
443                 readl(mbox);
444 }
445
446 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
447 {
448         return (readl(tp->regs + off + GRCMBOX_BASE));
449 }
450
451 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
452 {
453         writel(val, tp->regs + off + GRCMBOX_BASE);
454 }
455
456 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
457 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
458 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
459 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
460 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
461
462 #define tw32(reg,val)           tp->write32(tp, reg, val)
463 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
464 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
465 #define tr32(reg)               tp->read32(tp, reg)
466
467 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
468 {
469         unsigned long flags;
470
471         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
472             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
473                 return;
474
475         spin_lock_irqsave(&tp->indirect_lock, flags);
476         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
477                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
478                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
479
480                 /* Always leave this as zero. */
481                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
482         } else {
483                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
484                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
485
486                 /* Always leave this as zero. */
487                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
488         }
489         spin_unlock_irqrestore(&tp->indirect_lock, flags);
490 }
491
492 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
493 {
494         unsigned long flags;
495
496         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
497             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
498                 *val = 0;
499                 return;
500         }
501
502         spin_lock_irqsave(&tp->indirect_lock, flags);
503         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
504                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
505                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
506
507                 /* Always leave this as zero. */
508                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
509         } else {
510                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
511                 *val = tr32(TG3PCI_MEM_WIN_DATA);
512
513                 /* Always leave this as zero. */
514                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
515         }
516         spin_unlock_irqrestore(&tp->indirect_lock, flags);
517 }
518
519 static void tg3_ape_lock_init(struct tg3 *tp)
520 {
521         int i;
522
523         /* Make sure the driver hasn't any stale locks. */
524         for (i = 0; i < 8; i++)
525                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
526                                 APE_LOCK_GRANT_DRIVER);
527 }
528
529 static int tg3_ape_lock(struct tg3 *tp, int locknum)
530 {
531         int i, off;
532         int ret = 0;
533         u32 status;
534
535         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
536                 return 0;
537
538         switch (locknum) {
539                 case TG3_APE_LOCK_MEM:
540                         break;
541                 default:
542                         return -EINVAL;
543         }
544
545         off = 4 * locknum;
546
547         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
548
549         /* Wait for up to 1 millisecond to acquire lock. */
550         for (i = 0; i < 100; i++) {
551                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
552                 if (status == APE_LOCK_GRANT_DRIVER)
553                         break;
554                 udelay(10);
555         }
556
557         if (status != APE_LOCK_GRANT_DRIVER) {
558                 /* Revoke the lock request. */
559                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
560                                 APE_LOCK_GRANT_DRIVER);
561
562                 ret = -EBUSY;
563         }
564
565         return ret;
566 }
567
568 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
569 {
570         int off;
571
572         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
573                 return;
574
575         switch (locknum) {
576                 case TG3_APE_LOCK_MEM:
577                         break;
578                 default:
579                         return;
580         }
581
582         off = 4 * locknum;
583         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
584 }
585
586 static void tg3_disable_ints(struct tg3 *tp)
587 {
588         tw32(TG3PCI_MISC_HOST_CTRL,
589              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
590         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
591 }
592
593 static inline void tg3_cond_int(struct tg3 *tp)
594 {
595         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
596             (tp->hw_status->status & SD_STATUS_UPDATED))
597                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
598         else
599                 tw32(HOSTCC_MODE, tp->coalesce_mode |
600                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
601 }
602
603 static void tg3_enable_ints(struct tg3 *tp)
604 {
605         tp->irq_sync = 0;
606         wmb();
607
608         tw32(TG3PCI_MISC_HOST_CTRL,
609              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
610         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
611                        (tp->last_tag << 24));
612         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
613                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
614                                (tp->last_tag << 24));
615         tg3_cond_int(tp);
616 }
617
618 static inline unsigned int tg3_has_work(struct tg3 *tp)
619 {
620         struct tg3_hw_status *sblk = tp->hw_status;
621         unsigned int work_exists = 0;
622
623         /* check for phy events */
624         if (!(tp->tg3_flags &
625               (TG3_FLAG_USE_LINKCHG_REG |
626                TG3_FLAG_POLL_SERDES))) {
627                 if (sblk->status & SD_STATUS_LINK_CHG)
628                         work_exists = 1;
629         }
630         /* check for RX/TX work to do */
631         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
632             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
633                 work_exists = 1;
634
635         return work_exists;
636 }
637
638 /* tg3_restart_ints
639  *  similar to tg3_enable_ints, but it accurately determines whether there
640  *  is new work pending and can return without flushing the PIO write
641  *  which reenables interrupts
642  */
643 static void tg3_restart_ints(struct tg3 *tp)
644 {
645         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
646                      tp->last_tag << 24);
647         mmiowb();
648
649         /* When doing tagged status, this work check is unnecessary.
650          * The last_tag we write above tells the chip which piece of
651          * work we've completed.
652          */
653         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
654             tg3_has_work(tp))
655                 tw32(HOSTCC_MODE, tp->coalesce_mode |
656                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
657 }
658
659 static inline void tg3_netif_stop(struct tg3 *tp)
660 {
661         tp->dev->trans_start = jiffies; /* prevent tx timeout */
662         napi_disable(&tp->napi);
663         netif_tx_disable(tp->dev);
664 }
665
666 static inline void tg3_netif_start(struct tg3 *tp)
667 {
668         netif_wake_queue(tp->dev);
669         /* NOTE: unconditional netif_wake_queue is only appropriate
670          * so long as all callers are assured to have free tx slots
671          * (such as after tg3_init_hw)
672          */
673         napi_enable(&tp->napi);
674         tp->hw_status->status |= SD_STATUS_UPDATED;
675         tg3_enable_ints(tp);
676 }
677
678 static void tg3_switch_clocks(struct tg3 *tp)
679 {
680         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
681         u32 orig_clock_ctrl;
682
683         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
684             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
685                 return;
686
687         orig_clock_ctrl = clock_ctrl;
688         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
689                        CLOCK_CTRL_CLKRUN_OENABLE |
690                        0x1f);
691         tp->pci_clock_ctrl = clock_ctrl;
692
693         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
694                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
695                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
696                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
697                 }
698         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
699                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
700                             clock_ctrl |
701                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
702                             40);
703                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
704                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
705                             40);
706         }
707         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
708 }
709
710 #define PHY_BUSY_LOOPS  5000
711
712 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
713 {
714         u32 frame_val;
715         unsigned int loops;
716         int ret;
717
718         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
719                 tw32_f(MAC_MI_MODE,
720                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
721                 udelay(80);
722         }
723
724         *val = 0x0;
725
726         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
727                       MI_COM_PHY_ADDR_MASK);
728         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
729                       MI_COM_REG_ADDR_MASK);
730         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
731
732         tw32_f(MAC_MI_COM, frame_val);
733
734         loops = PHY_BUSY_LOOPS;
735         while (loops != 0) {
736                 udelay(10);
737                 frame_val = tr32(MAC_MI_COM);
738
739                 if ((frame_val & MI_COM_BUSY) == 0) {
740                         udelay(5);
741                         frame_val = tr32(MAC_MI_COM);
742                         break;
743                 }
744                 loops -= 1;
745         }
746
747         ret = -EBUSY;
748         if (loops != 0) {
749                 *val = frame_val & MI_COM_DATA_MASK;
750                 ret = 0;
751         }
752
753         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
754                 tw32_f(MAC_MI_MODE, tp->mi_mode);
755                 udelay(80);
756         }
757
758         return ret;
759 }
760
761 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
762 {
763         u32 frame_val;
764         unsigned int loops;
765         int ret;
766
767         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
768             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
769                 return 0;
770
771         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
772                 tw32_f(MAC_MI_MODE,
773                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
774                 udelay(80);
775         }
776
777         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
778                       MI_COM_PHY_ADDR_MASK);
779         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
780                       MI_COM_REG_ADDR_MASK);
781         frame_val |= (val & MI_COM_DATA_MASK);
782         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
783
784         tw32_f(MAC_MI_COM, frame_val);
785
786         loops = PHY_BUSY_LOOPS;
787         while (loops != 0) {
788                 udelay(10);
789                 frame_val = tr32(MAC_MI_COM);
790                 if ((frame_val & MI_COM_BUSY) == 0) {
791                         udelay(5);
792                         frame_val = tr32(MAC_MI_COM);
793                         break;
794                 }
795                 loops -= 1;
796         }
797
798         ret = -EBUSY;
799         if (loops != 0)
800                 ret = 0;
801
802         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
803                 tw32_f(MAC_MI_MODE, tp->mi_mode);
804                 udelay(80);
805         }
806
807         return ret;
808 }
809
810 static int tg3_bmcr_reset(struct tg3 *tp)
811 {
812         u32 phy_control;
813         int limit, err;
814
815         /* OK, reset it, and poll the BMCR_RESET bit until it
816          * clears or we time out.
817          */
818         phy_control = BMCR_RESET;
819         err = tg3_writephy(tp, MII_BMCR, phy_control);
820         if (err != 0)
821                 return -EBUSY;
822
823         limit = 5000;
824         while (limit--) {
825                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
826                 if (err != 0)
827                         return -EBUSY;
828
829                 if ((phy_control & BMCR_RESET) == 0) {
830                         udelay(40);
831                         break;
832                 }
833                 udelay(10);
834         }
835         if (limit <= 0)
836                 return -EBUSY;
837
838         return 0;
839 }
840
841 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
842 {
843         struct tg3 *tp = (struct tg3 *)bp->priv;
844         u32 val;
845
846         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
847                 return -EAGAIN;
848
849         if (tg3_readphy(tp, reg, &val))
850                 return -EIO;
851
852         return val;
853 }
854
855 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
856 {
857         struct tg3 *tp = (struct tg3 *)bp->priv;
858
859         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
860                 return -EAGAIN;
861
862         if (tg3_writephy(tp, reg, val))
863                 return -EIO;
864
865         return 0;
866 }
867
868 static int tg3_mdio_reset(struct mii_bus *bp)
869 {
870         return 0;
871 }
872
873 static void tg3_mdio_config(struct tg3 *tp)
874 {
875         u32 val;
876
877         if (tp->mdio_bus.phy_map[PHY_ADDR]->interface !=
878             PHY_INTERFACE_MODE_RGMII)
879                 return;
880
881         val = tr32(MAC_PHYCFG1) & ~(MAC_PHYCFG1_RGMII_EXT_RX_DEC |
882                                     MAC_PHYCFG1_RGMII_SND_STAT_EN);
883         if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {
884                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
885                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
886                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
887                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
888         }
889         tw32(MAC_PHYCFG1, val | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV);
890
891         val = tr32(MAC_PHYCFG2) & ~(MAC_PHYCFG2_INBAND_ENABLE);
892         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
893                 val |= MAC_PHYCFG2_INBAND_ENABLE;
894         tw32(MAC_PHYCFG2, val);
895
896         val = tr32(MAC_EXT_RGMII_MODE);
897         val &= ~(MAC_RGMII_MODE_RX_INT_B |
898                  MAC_RGMII_MODE_RX_QUALITY |
899                  MAC_RGMII_MODE_RX_ACTIVITY |
900                  MAC_RGMII_MODE_RX_ENG_DET |
901                  MAC_RGMII_MODE_TX_ENABLE |
902                  MAC_RGMII_MODE_TX_LOWPWR |
903                  MAC_RGMII_MODE_TX_RESET);
904         if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {
905                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
906                         val |= MAC_RGMII_MODE_RX_INT_B |
907                                MAC_RGMII_MODE_RX_QUALITY |
908                                MAC_RGMII_MODE_RX_ACTIVITY |
909                                MAC_RGMII_MODE_RX_ENG_DET;
910                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
911                         val |= MAC_RGMII_MODE_TX_ENABLE |
912                                MAC_RGMII_MODE_TX_LOWPWR |
913                                MAC_RGMII_MODE_TX_RESET;
914         }
915         tw32(MAC_EXT_RGMII_MODE, val);
916 }
917
918 static void tg3_mdio_start(struct tg3 *tp)
919 {
920         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
921                 mutex_lock(&tp->mdio_bus.mdio_lock);
922                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
923                 mutex_unlock(&tp->mdio_bus.mdio_lock);
924         }
925
926         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
927         tw32_f(MAC_MI_MODE, tp->mi_mode);
928         udelay(80);
929
930         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED)
931                 tg3_mdio_config(tp);
932 }
933
934 static void tg3_mdio_stop(struct tg3 *tp)
935 {
936         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
937                 mutex_lock(&tp->mdio_bus.mdio_lock);
938                 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
939                 mutex_unlock(&tp->mdio_bus.mdio_lock);
940         }
941 }
942
943 static int tg3_mdio_init(struct tg3 *tp)
944 {
945         int i;
946         u32 reg;
947         struct phy_device *phydev;
948         struct mii_bus *mdio_bus = &tp->mdio_bus;
949
950         tg3_mdio_start(tp);
951
952         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
953             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
954                 return 0;
955
956         memset(mdio_bus, 0, sizeof(*mdio_bus));
957
958         mdio_bus->name     = "tg3 mdio bus";
959         snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "%x",
960                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
961         mdio_bus->priv     = tp;
962         mdio_bus->dev      = &tp->pdev->dev;
963         mdio_bus->read     = &tg3_mdio_read;
964         mdio_bus->write    = &tg3_mdio_write;
965         mdio_bus->reset    = &tg3_mdio_reset;
966         mdio_bus->phy_mask = ~(1 << PHY_ADDR);
967         mdio_bus->irq      = &tp->mdio_irq[0];
968
969         for (i = 0; i < PHY_MAX_ADDR; i++)
970                 mdio_bus->irq[i] = PHY_POLL;
971
972         /* The bus registration will look for all the PHYs on the mdio bus.
973          * Unfortunately, it does not ensure the PHY is powered up before
974          * accessing the PHY ID registers.  A chip reset is the
975          * quickest way to bring the device back to an operational state..
976          */
977         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
978                 tg3_bmcr_reset(tp);
979
980         i = mdiobus_register(mdio_bus);
981         if (i) {
982                 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
983                         tp->dev->name, i);
984                 return i;
985         }
986
987         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
988
989         phydev = tp->mdio_bus.phy_map[PHY_ADDR];
990
991         switch (phydev->phy_id) {
992         case TG3_PHY_ID_BCM50610:
993                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
994                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
995                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
996                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
997                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
998                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
999                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1000                 break;
1001         case TG3_PHY_ID_BCMAC131:
1002                 phydev->interface = PHY_INTERFACE_MODE_MII;
1003                 break;
1004         }
1005
1006         tg3_mdio_config(tp);
1007
1008         return 0;
1009 }
1010
1011 static void tg3_mdio_fini(struct tg3 *tp)
1012 {
1013         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1014                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1015                 mdiobus_unregister(&tp->mdio_bus);
1016                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1017         }
1018 }
1019
1020 /* tp->lock is held. */
1021 static void tg3_wait_for_event_ack(struct tg3 *tp)
1022 {
1023         int i;
1024
1025         /* Wait for up to 2.5 milliseconds */
1026         for (i = 0; i < 250000; i++) {
1027                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1028                         break;
1029                 udelay(10);
1030         }
1031 }
1032
1033 /* tp->lock is held. */
1034 static void tg3_ump_link_report(struct tg3 *tp)
1035 {
1036         u32 reg;
1037         u32 val;
1038
1039         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1040             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1041                 return;
1042
1043         tg3_wait_for_event_ack(tp);
1044
1045         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1046
1047         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1048
1049         val = 0;
1050         if (!tg3_readphy(tp, MII_BMCR, &reg))
1051                 val = reg << 16;
1052         if (!tg3_readphy(tp, MII_BMSR, &reg))
1053                 val |= (reg & 0xffff);
1054         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1055
1056         val = 0;
1057         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1058                 val = reg << 16;
1059         if (!tg3_readphy(tp, MII_LPA, &reg))
1060                 val |= (reg & 0xffff);
1061         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1062
1063         val = 0;
1064         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1065                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1066                         val = reg << 16;
1067                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1068                         val |= (reg & 0xffff);
1069         }
1070         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1071
1072         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1073                 val = reg << 16;
1074         else
1075                 val = 0;
1076         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1077
1078         val = tr32(GRC_RX_CPU_EVENT);
1079         val |= GRC_RX_CPU_DRIVER_EVENT;
1080         tw32_f(GRC_RX_CPU_EVENT, val);
1081 }
1082
1083 static void tg3_link_report(struct tg3 *tp)
1084 {
1085         if (!netif_carrier_ok(tp->dev)) {
1086                 if (netif_msg_link(tp))
1087                         printk(KERN_INFO PFX "%s: Link is down.\n",
1088                                tp->dev->name);
1089                 tg3_ump_link_report(tp);
1090         } else if (netif_msg_link(tp)) {
1091                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1092                        tp->dev->name,
1093                        (tp->link_config.active_speed == SPEED_1000 ?
1094                         1000 :
1095                         (tp->link_config.active_speed == SPEED_100 ?
1096                          100 : 10)),
1097                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1098                         "full" : "half"));
1099
1100                 printk(KERN_INFO PFX
1101                        "%s: Flow control is %s for TX and %s for RX.\n",
1102                        tp->dev->name,
1103                        (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_TX) ?
1104                        "on" : "off",
1105                        (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_RX) ?
1106                        "on" : "off");
1107                 tg3_ump_link_report(tp);
1108         }
1109 }
1110
1111 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1112 {
1113         u16 miireg;
1114
1115         if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
1116                 miireg = ADVERTISE_PAUSE_CAP;
1117         else if (flow_ctrl & TG3_FLOW_CTRL_TX)
1118                 miireg = ADVERTISE_PAUSE_ASYM;
1119         else if (flow_ctrl & TG3_FLOW_CTRL_RX)
1120                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1121         else
1122                 miireg = 0;
1123
1124         return miireg;
1125 }
1126
1127 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1128 {
1129         u16 miireg;
1130
1131         if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
1132                 miireg = ADVERTISE_1000XPAUSE;
1133         else if (flow_ctrl & TG3_FLOW_CTRL_TX)
1134                 miireg = ADVERTISE_1000XPSE_ASYM;
1135         else if (flow_ctrl & TG3_FLOW_CTRL_RX)
1136                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1137         else
1138                 miireg = 0;
1139
1140         return miireg;
1141 }
1142
1143 static u8 tg3_resolve_flowctrl_1000T(u16 lcladv, u16 rmtadv)
1144 {
1145         u8 cap = 0;
1146
1147         if (lcladv & ADVERTISE_PAUSE_CAP) {
1148                 if (lcladv & ADVERTISE_PAUSE_ASYM) {
1149                         if (rmtadv & LPA_PAUSE_CAP)
1150                                 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1151                         else if (rmtadv & LPA_PAUSE_ASYM)
1152                                 cap = TG3_FLOW_CTRL_RX;
1153                 } else {
1154                         if (rmtadv & LPA_PAUSE_CAP)
1155                                 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1156                 }
1157         } else if (lcladv & ADVERTISE_PAUSE_ASYM) {
1158                 if ((rmtadv & LPA_PAUSE_CAP) && (rmtadv & LPA_PAUSE_ASYM))
1159                         cap = TG3_FLOW_CTRL_TX;
1160         }
1161
1162         return cap;
1163 }
1164
1165 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1166 {
1167         u8 cap = 0;
1168
1169         if (lcladv & ADVERTISE_1000XPAUSE) {
1170                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1171                         if (rmtadv & LPA_1000XPAUSE)
1172                                 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1173                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1174                                 cap = TG3_FLOW_CTRL_RX;
1175                 } else {
1176                         if (rmtadv & LPA_1000XPAUSE)
1177                                 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1178                 }
1179         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1180                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1181                         cap = TG3_FLOW_CTRL_TX;
1182         }
1183
1184         return cap;
1185 }
1186
1187 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1188 {
1189         u8 autoneg;
1190         u8 flowctrl = 0;
1191         u32 old_rx_mode = tp->rx_mode;
1192         u32 old_tx_mode = tp->tx_mode;
1193
1194         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1195                 autoneg = tp->mdio_bus.phy_map[PHY_ADDR]->autoneg;
1196         else
1197                 autoneg = tp->link_config.autoneg;
1198
1199         if (autoneg == AUTONEG_ENABLE &&
1200             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1201                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1202                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1203                 else
1204                         flowctrl = tg3_resolve_flowctrl_1000T(lcladv, rmtadv);
1205         } else
1206                 flowctrl = tp->link_config.flowctrl;
1207
1208         tp->link_config.active_flowctrl = flowctrl;
1209
1210         if (flowctrl & TG3_FLOW_CTRL_RX)
1211                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1212         else
1213                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1214
1215         if (old_rx_mode != tp->rx_mode)
1216                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1217
1218         if (flowctrl & TG3_FLOW_CTRL_TX)
1219                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1220         else
1221                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1222
1223         if (old_tx_mode != tp->tx_mode)
1224                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1225 }
1226
1227 static void tg3_adjust_link(struct net_device *dev)
1228 {
1229         u8 oldflowctrl, linkmesg = 0;
1230         u32 mac_mode, lcl_adv, rmt_adv;
1231         struct tg3 *tp = netdev_priv(dev);
1232         struct phy_device *phydev = tp->mdio_bus.phy_map[PHY_ADDR];
1233
1234         spin_lock(&tp->lock);
1235
1236         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1237                                     MAC_MODE_HALF_DUPLEX);
1238
1239         oldflowctrl = tp->link_config.active_flowctrl;
1240
1241         if (phydev->link) {
1242                 lcl_adv = 0;
1243                 rmt_adv = 0;
1244
1245                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1246                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1247                 else
1248                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1249
1250                 if (phydev->duplex == DUPLEX_HALF)
1251                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1252                 else {
1253                         lcl_adv = tg3_advert_flowctrl_1000T(
1254                                   tp->link_config.flowctrl);
1255
1256                         if (phydev->pause)
1257                                 rmt_adv = LPA_PAUSE_CAP;
1258                         if (phydev->asym_pause)
1259                                 rmt_adv |= LPA_PAUSE_ASYM;
1260                 }
1261
1262                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1263         } else
1264                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1265
1266         if (mac_mode != tp->mac_mode) {
1267                 tp->mac_mode = mac_mode;
1268                 tw32_f(MAC_MODE, tp->mac_mode);
1269                 udelay(40);
1270         }
1271
1272         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1273                 tw32(MAC_TX_LENGTHS,
1274                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1275                       (6 << TX_LENGTHS_IPG_SHIFT) |
1276                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1277         else
1278                 tw32(MAC_TX_LENGTHS,
1279                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1280                       (6 << TX_LENGTHS_IPG_SHIFT) |
1281                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1282
1283         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1284             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1285             phydev->speed != tp->link_config.active_speed ||
1286             phydev->duplex != tp->link_config.active_duplex ||
1287             oldflowctrl != tp->link_config.active_flowctrl)
1288             linkmesg = 1;
1289
1290         tp->link_config.active_speed = phydev->speed;
1291         tp->link_config.active_duplex = phydev->duplex;
1292
1293         spin_unlock(&tp->lock);
1294
1295         if (linkmesg)
1296                 tg3_link_report(tp);
1297 }
1298
1299 static int tg3_phy_init(struct tg3 *tp)
1300 {
1301         struct phy_device *phydev;
1302
1303         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1304                 return 0;
1305
1306         /* Bring the PHY back to a known state. */
1307         tg3_bmcr_reset(tp);
1308
1309         phydev = tp->mdio_bus.phy_map[PHY_ADDR];
1310
1311         /* Attach the MAC to the PHY. */
1312         phydev = phy_connect(tp->dev, phydev->dev.bus_id, tg3_adjust_link,
1313                              phydev->dev_flags, phydev->interface);
1314         if (IS_ERR(phydev)) {
1315                 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1316                 return PTR_ERR(phydev);
1317         }
1318
1319         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1320
1321         /* Mask with MAC supported features. */
1322         phydev->supported &= (PHY_GBIT_FEATURES |
1323                               SUPPORTED_Pause |
1324                               SUPPORTED_Asym_Pause);
1325
1326         phydev->advertising = phydev->supported;
1327
1328         printk(KERN_INFO
1329                "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
1330                tp->dev->name, phydev->drv->name, phydev->dev.bus_id);
1331
1332         return 0;
1333 }
1334
1335 static void tg3_phy_start(struct tg3 *tp)
1336 {
1337         struct phy_device *phydev;
1338
1339         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1340                 return;
1341
1342         phydev = tp->mdio_bus.phy_map[PHY_ADDR];
1343
1344         if (tp->link_config.phy_is_low_power) {
1345                 tp->link_config.phy_is_low_power = 0;
1346                 phydev->speed = tp->link_config.orig_speed;
1347                 phydev->duplex = tp->link_config.orig_duplex;
1348                 phydev->autoneg = tp->link_config.orig_autoneg;
1349                 phydev->advertising = tp->link_config.orig_advertising;
1350         }
1351
1352         phy_start(phydev);
1353
1354         phy_start_aneg(phydev);
1355 }
1356
1357 static void tg3_phy_stop(struct tg3 *tp)
1358 {
1359         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1360                 return;
1361
1362         phy_stop(tp->mdio_bus.phy_map[PHY_ADDR]);
1363 }
1364
1365 static void tg3_phy_fini(struct tg3 *tp)
1366 {
1367         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1368                 phy_disconnect(tp->mdio_bus.phy_map[PHY_ADDR]);
1369                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1370         }
1371 }
1372
1373 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1374 {
1375         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1376         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1377 }
1378
1379 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1380 {
1381         u32 phy;
1382
1383         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1384             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1385                 return;
1386
1387         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1388                 u32 ephy;
1389
1390                 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
1391                         tg3_writephy(tp, MII_TG3_EPHY_TEST,
1392                                      ephy | MII_TG3_EPHY_SHADOW_EN);
1393                         if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
1394                                 if (enable)
1395                                         phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
1396                                 else
1397                                         phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
1398                                 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
1399                         }
1400                         tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
1401                 }
1402         } else {
1403                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1404                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1405                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1406                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1407                         if (enable)
1408                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1409                         else
1410                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1411                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1412                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1413                 }
1414         }
1415 }
1416
1417 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1418 {
1419         u32 val;
1420
1421         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1422                 return;
1423
1424         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1425             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1426                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1427                              (val | (1 << 15) | (1 << 4)));
1428 }
1429
1430 static void tg3_phy_apply_otp(struct tg3 *tp)
1431 {
1432         u32 otp, phy;
1433
1434         if (!tp->phy_otp)
1435                 return;
1436
1437         otp = tp->phy_otp;
1438
1439         /* Enable SM_DSP clock and tx 6dB coding. */
1440         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1441               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1442               MII_TG3_AUXCTL_ACTL_TX_6DB;
1443         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1444
1445         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1446         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1447         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1448
1449         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1450               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1451         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1452
1453         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1454         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1455         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1456
1457         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1458         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1459
1460         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1461         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1462
1463         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1464               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1465         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1466
1467         /* Turn off SM_DSP clock. */
1468         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1469               MII_TG3_AUXCTL_ACTL_TX_6DB;
1470         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1471 }
1472
1473 static int tg3_wait_macro_done(struct tg3 *tp)
1474 {
1475         int limit = 100;
1476
1477         while (limit--) {
1478                 u32 tmp32;
1479
1480                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1481                         if ((tmp32 & 0x1000) == 0)
1482                                 break;
1483                 }
1484         }
1485         if (limit <= 0)
1486                 return -EBUSY;
1487
1488         return 0;
1489 }
1490
1491 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1492 {
1493         static const u32 test_pat[4][6] = {
1494         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1495         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1496         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1497         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1498         };
1499         int chan;
1500
1501         for (chan = 0; chan < 4; chan++) {
1502                 int i;
1503
1504                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1505                              (chan * 0x2000) | 0x0200);
1506                 tg3_writephy(tp, 0x16, 0x0002);
1507
1508                 for (i = 0; i < 6; i++)
1509                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1510                                      test_pat[chan][i]);
1511
1512                 tg3_writephy(tp, 0x16, 0x0202);
1513                 if (tg3_wait_macro_done(tp)) {
1514                         *resetp = 1;
1515                         return -EBUSY;
1516                 }
1517
1518                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1519                              (chan * 0x2000) | 0x0200);
1520                 tg3_writephy(tp, 0x16, 0x0082);
1521                 if (tg3_wait_macro_done(tp)) {
1522                         *resetp = 1;
1523                         return -EBUSY;
1524                 }
1525
1526                 tg3_writephy(tp, 0x16, 0x0802);
1527                 if (tg3_wait_macro_done(tp)) {
1528                         *resetp = 1;
1529                         return -EBUSY;
1530                 }
1531
1532                 for (i = 0; i < 6; i += 2) {
1533                         u32 low, high;
1534
1535                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1536                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1537                             tg3_wait_macro_done(tp)) {
1538                                 *resetp = 1;
1539                                 return -EBUSY;
1540                         }
1541                         low &= 0x7fff;
1542                         high &= 0x000f;
1543                         if (low != test_pat[chan][i] ||
1544                             high != test_pat[chan][i+1]) {
1545                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1546                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1547                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1548
1549                                 return -EBUSY;
1550                         }
1551                 }
1552         }
1553
1554         return 0;
1555 }
1556
1557 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1558 {
1559         int chan;
1560
1561         for (chan = 0; chan < 4; chan++) {
1562                 int i;
1563
1564                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1565                              (chan * 0x2000) | 0x0200);
1566                 tg3_writephy(tp, 0x16, 0x0002);
1567                 for (i = 0; i < 6; i++)
1568                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1569                 tg3_writephy(tp, 0x16, 0x0202);
1570                 if (tg3_wait_macro_done(tp))
1571                         return -EBUSY;
1572         }
1573
1574         return 0;
1575 }
1576
1577 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1578 {
1579         u32 reg32, phy9_orig;
1580         int retries, do_phy_reset, err;
1581
1582         retries = 10;
1583         do_phy_reset = 1;
1584         do {
1585                 if (do_phy_reset) {
1586                         err = tg3_bmcr_reset(tp);
1587                         if (err)
1588                                 return err;
1589                         do_phy_reset = 0;
1590                 }
1591
1592                 /* Disable transmitter and interrupt.  */
1593                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1594                         continue;
1595
1596                 reg32 |= 0x3000;
1597                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1598
1599                 /* Set full-duplex, 1000 mbps.  */
1600                 tg3_writephy(tp, MII_BMCR,
1601                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1602
1603                 /* Set to master mode.  */
1604                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1605                         continue;
1606
1607                 tg3_writephy(tp, MII_TG3_CTRL,
1608                              (MII_TG3_CTRL_AS_MASTER |
1609                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1610
1611                 /* Enable SM_DSP_CLOCK and 6dB.  */
1612                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1613
1614                 /* Block the PHY control access.  */
1615                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1616                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1617
1618                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1619                 if (!err)
1620                         break;
1621         } while (--retries);
1622
1623         err = tg3_phy_reset_chanpat(tp);
1624         if (err)
1625                 return err;
1626
1627         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1628         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1629
1630         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1631         tg3_writephy(tp, 0x16, 0x0000);
1632
1633         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1634             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1635                 /* Set Extended packet length bit for jumbo frames */
1636                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1637         }
1638         else {
1639                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1640         }
1641
1642         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1643
1644         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1645                 reg32 &= ~0x3000;
1646                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1647         } else if (!err)
1648                 err = -EBUSY;
1649
1650         return err;
1651 }
1652
1653 /* This will reset the tigon3 PHY if there is no valid
1654  * link unless the FORCE argument is non-zero.
1655  */
1656 static int tg3_phy_reset(struct tg3 *tp)
1657 {
1658         u32 cpmuctrl;
1659         u32 phy_status;
1660         int err;
1661
1662         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1663                 u32 val;
1664
1665                 val = tr32(GRC_MISC_CFG);
1666                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1667                 udelay(40);
1668         }
1669         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1670         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1671         if (err != 0)
1672                 return -EBUSY;
1673
1674         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1675                 netif_carrier_off(tp->dev);
1676                 tg3_link_report(tp);
1677         }
1678
1679         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1680             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1681             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1682                 err = tg3_phy_reset_5703_4_5(tp);
1683                 if (err)
1684                         return err;
1685                 goto out;
1686         }
1687
1688         cpmuctrl = 0;
1689         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1690             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1691                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1692                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1693                         tw32(TG3_CPMU_CTRL,
1694                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1695         }
1696
1697         err = tg3_bmcr_reset(tp);
1698         if (err)
1699                 return err;
1700
1701         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1702                 u32 phy;
1703
1704                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1705                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1706
1707                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1708         }
1709
1710         if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
1711                 u32 val;
1712
1713                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1714                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1715                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1716                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1717                         udelay(40);
1718                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1719                 }
1720
1721                 /* Disable GPHY autopowerdown. */
1722                 tg3_writephy(tp, MII_TG3_MISC_SHDW,
1723                              MII_TG3_MISC_SHDW_WREN |
1724                              MII_TG3_MISC_SHDW_APD_SEL |
1725                              MII_TG3_MISC_SHDW_APD_WKTM_84MS);
1726         }
1727
1728         tg3_phy_apply_otp(tp);
1729
1730 out:
1731         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1732                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1733                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1734                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1735                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1736                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1737                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1738         }
1739         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1740                 tg3_writephy(tp, 0x1c, 0x8d68);
1741                 tg3_writephy(tp, 0x1c, 0x8d68);
1742         }
1743         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1744                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1745                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1746                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1747                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1748                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1749                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1750                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1751                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1752         }
1753         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1754                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1755                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1756                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1757                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1758                         tg3_writephy(tp, MII_TG3_TEST1,
1759                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1760                 } else
1761                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1762                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1763         }
1764         /* Set Extended packet length bit (bit 14) on all chips that */
1765         /* support jumbo frames */
1766         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1767                 /* Cannot do read-modify-write on 5401 */
1768                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1769         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1770                 u32 phy_reg;
1771
1772                 /* Set bit 14 with read-modify-write to preserve other bits */
1773                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1774                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1775                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1776         }
1777
1778         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1779          * jumbo frames transmission.
1780          */
1781         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1782                 u32 phy_reg;
1783
1784                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1785                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1786                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1787         }
1788
1789         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1790                 /* adjust output voltage */
1791                 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1792         }
1793
1794         tg3_phy_toggle_automdix(tp, 1);
1795         tg3_phy_set_wirespeed(tp);
1796         return 0;
1797 }
1798
1799 static void tg3_frob_aux_power(struct tg3 *tp)
1800 {
1801         struct tg3 *tp_peer = tp;
1802
1803         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1804                 return;
1805
1806         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1807             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1808                 struct net_device *dev_peer;
1809
1810                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1811                 /* remove_one() may have been run on the peer. */
1812                 if (!dev_peer)
1813                         tp_peer = tp;
1814                 else
1815                         tp_peer = netdev_priv(dev_peer);
1816         }
1817
1818         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1819             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1820             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1821             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1822                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1823                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1824                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1825                                     (GRC_LCLCTRL_GPIO_OE0 |
1826                                      GRC_LCLCTRL_GPIO_OE1 |
1827                                      GRC_LCLCTRL_GPIO_OE2 |
1828                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1829                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1830                                     100);
1831                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) {
1832                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1833                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1834                                              GRC_LCLCTRL_GPIO_OE1 |
1835                                              GRC_LCLCTRL_GPIO_OE2 |
1836                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
1837                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
1838                                              tp->grc_local_ctrl;
1839                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1840
1841                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
1842                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1843
1844                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
1845                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1846                 } else {
1847                         u32 no_gpio2;
1848                         u32 grc_local_ctrl = 0;
1849
1850                         if (tp_peer != tp &&
1851                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1852                                 return;
1853
1854                         /* Workaround to prevent overdrawing Amps. */
1855                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1856                             ASIC_REV_5714) {
1857                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1858                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1859                                             grc_local_ctrl, 100);
1860                         }
1861
1862                         /* On 5753 and variants, GPIO2 cannot be used. */
1863                         no_gpio2 = tp->nic_sram_data_cfg &
1864                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1865
1866                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1867                                          GRC_LCLCTRL_GPIO_OE1 |
1868                                          GRC_LCLCTRL_GPIO_OE2 |
1869                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1870                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1871                         if (no_gpio2) {
1872                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1873                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
1874                         }
1875                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1876                                                     grc_local_ctrl, 100);
1877
1878                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1879
1880                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1881                                                     grc_local_ctrl, 100);
1882
1883                         if (!no_gpio2) {
1884                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1885                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1886                                             grc_local_ctrl, 100);
1887                         }
1888                 }
1889         } else {
1890                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1891                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1892                         if (tp_peer != tp &&
1893                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1894                                 return;
1895
1896                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1897                                     (GRC_LCLCTRL_GPIO_OE1 |
1898                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1899
1900                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1901                                     GRC_LCLCTRL_GPIO_OE1, 100);
1902
1903                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1904                                     (GRC_LCLCTRL_GPIO_OE1 |
1905                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1906                 }
1907         }
1908 }
1909
1910 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
1911 {
1912         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
1913                 return 1;
1914         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
1915                 if (speed != SPEED_10)
1916                         return 1;
1917         } else if (speed == SPEED_10)
1918                 return 1;
1919
1920         return 0;
1921 }
1922
1923 static int tg3_setup_phy(struct tg3 *, int);
1924
1925 #define RESET_KIND_SHUTDOWN     0
1926 #define RESET_KIND_INIT         1
1927 #define RESET_KIND_SUSPEND      2
1928
1929 static void tg3_write_sig_post_reset(struct tg3 *, int);
1930 static int tg3_halt_cpu(struct tg3 *, u32);
1931 static int tg3_nvram_lock(struct tg3 *);
1932 static void tg3_nvram_unlock(struct tg3 *);
1933
1934 static void tg3_power_down_phy(struct tg3 *tp)
1935 {
1936         u32 val;
1937
1938         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1939                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1940                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
1941                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
1942
1943                         sg_dig_ctrl |=
1944                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
1945                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
1946                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
1947                 }
1948                 return;
1949         }
1950
1951         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1952                 tg3_bmcr_reset(tp);
1953                 val = tr32(GRC_MISC_CFG);
1954                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1955                 udelay(40);
1956                 return;
1957         } else if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
1958                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1959                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1960                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1961         }
1962
1963         /* The PHY should not be powered down on some chips because
1964          * of bugs.
1965          */
1966         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1967             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1968             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1969              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1970                 return;
1971
1972         if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
1973                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1974                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1975                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
1976                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1977         }
1978
1979         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1980 }
1981
1982 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1983 {
1984         u32 misc_host_ctrl;
1985
1986         /* Make sure register accesses (indirect or otherwise)
1987          * will function correctly.
1988          */
1989         pci_write_config_dword(tp->pdev,
1990                                TG3PCI_MISC_HOST_CTRL,
1991                                tp->misc_host_ctrl);
1992
1993         switch (state) {
1994         case PCI_D0:
1995                 pci_enable_wake(tp->pdev, state, false);
1996                 pci_set_power_state(tp->pdev, PCI_D0);
1997
1998                 /* Switch out of Vaux if it is a NIC */
1999                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2000                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2001
2002                 return 0;
2003
2004         case PCI_D1:
2005         case PCI_D2:
2006         case PCI_D3hot:
2007                 break;
2008
2009         default:
2010                 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2011                         tp->dev->name, state);
2012                 return -EINVAL;
2013         }
2014         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2015         tw32(TG3PCI_MISC_HOST_CTRL,
2016              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2017
2018         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2019                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2020                     !tp->link_config.phy_is_low_power) {
2021                         struct phy_device *phydev;
2022                         u32 advertising;
2023
2024                         phydev = tp->mdio_bus.phy_map[PHY_ADDR];
2025
2026                         tp->link_config.phy_is_low_power = 1;
2027
2028                         tp->link_config.orig_speed = phydev->speed;
2029                         tp->link_config.orig_duplex = phydev->duplex;
2030                         tp->link_config.orig_autoneg = phydev->autoneg;
2031                         tp->link_config.orig_advertising = phydev->advertising;
2032
2033                         advertising = ADVERTISED_TP |
2034                                       ADVERTISED_Pause |
2035                                       ADVERTISED_Autoneg |
2036                                       ADVERTISED_10baseT_Half;
2037
2038                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2039                             (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
2040                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2041                                         advertising |=
2042                                                 ADVERTISED_100baseT_Half |
2043                                                 ADVERTISED_100baseT_Full |
2044                                                 ADVERTISED_10baseT_Full;
2045                                 else
2046                                         advertising |= ADVERTISED_10baseT_Full;
2047                         }
2048
2049                         phydev->advertising = advertising;
2050
2051                         phy_start_aneg(phydev);
2052                 }
2053         } else {
2054                 if (tp->link_config.phy_is_low_power == 0) {
2055                         tp->link_config.phy_is_low_power = 1;
2056                         tp->link_config.orig_speed = tp->link_config.speed;
2057                         tp->link_config.orig_duplex = tp->link_config.duplex;
2058                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2059                 }
2060
2061                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2062                         tp->link_config.speed = SPEED_10;
2063                         tp->link_config.duplex = DUPLEX_HALF;
2064                         tp->link_config.autoneg = AUTONEG_ENABLE;
2065                         tg3_setup_phy(tp, 0);
2066                 }
2067         }
2068
2069         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2070                 u32 val;
2071
2072                 val = tr32(GRC_VCPU_EXT_CTRL);
2073                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2074         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2075                 int i;
2076                 u32 val;
2077
2078                 for (i = 0; i < 200; i++) {
2079                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2080                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2081                                 break;
2082                         msleep(1);
2083                 }
2084         }
2085         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2086                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2087                                                      WOL_DRV_STATE_SHUTDOWN |
2088                                                      WOL_DRV_WOL |
2089                                                      WOL_SET_MAGIC_PKT);
2090
2091         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
2092                 u32 mac_mode;
2093
2094                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2095                         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
2096                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2097                                 udelay(40);
2098                         }
2099
2100                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2101                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2102                         else
2103                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2104
2105                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2106                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2107                             ASIC_REV_5700) {
2108                                 u32 speed = (tp->tg3_flags &
2109                                              TG3_FLAG_WOL_SPEED_100MB) ?
2110                                              SPEED_100 : SPEED_10;
2111                                 if (tg3_5700_link_polarity(tp, speed))
2112                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2113                                 else
2114                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2115                         }
2116                 } else {
2117                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2118                 }
2119
2120                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2121                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2122
2123                 if (pci_pme_capable(tp->pdev, state) &&
2124                      (tp->tg3_flags & TG3_FLAG_WOL_ENABLE))
2125                         mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2126
2127                 tw32_f(MAC_MODE, mac_mode);
2128                 udelay(100);
2129
2130                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2131                 udelay(10);
2132         }
2133
2134         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2135             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2136              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2137                 u32 base_val;
2138
2139                 base_val = tp->pci_clock_ctrl;
2140                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2141                              CLOCK_CTRL_TXCLK_DISABLE);
2142
2143                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2144                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2145         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2146                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2147                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2148                 /* do nothing */
2149         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2150                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2151                 u32 newbits1, newbits2;
2152
2153                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2154                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2155                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2156                                     CLOCK_CTRL_TXCLK_DISABLE |
2157                                     CLOCK_CTRL_ALTCLK);
2158                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2159                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2160                         newbits1 = CLOCK_CTRL_625_CORE;
2161                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2162                 } else {
2163                         newbits1 = CLOCK_CTRL_ALTCLK;
2164                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2165                 }
2166
2167                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2168                             40);
2169
2170                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2171                             40);
2172
2173                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2174                         u32 newbits3;
2175
2176                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2177                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2178                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2179                                             CLOCK_CTRL_TXCLK_DISABLE |
2180                                             CLOCK_CTRL_44MHZ_CORE);
2181                         } else {
2182                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2183                         }
2184
2185                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2186                                     tp->pci_clock_ctrl | newbits3, 40);
2187                 }
2188         }
2189
2190         if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
2191             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
2192             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
2193                 tg3_power_down_phy(tp);
2194
2195         tg3_frob_aux_power(tp);
2196
2197         /* Workaround for unstable PLL clock */
2198         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2199             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2200                 u32 val = tr32(0x7d00);
2201
2202                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2203                 tw32(0x7d00, val);
2204                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2205                         int err;
2206
2207                         err = tg3_nvram_lock(tp);
2208                         tg3_halt_cpu(tp, RX_CPU_BASE);
2209                         if (!err)
2210                                 tg3_nvram_unlock(tp);
2211                 }
2212         }
2213
2214         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2215
2216         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
2217                 pci_enable_wake(tp->pdev, state, true);
2218
2219         /* Finally, set the new power state. */
2220         pci_set_power_state(tp->pdev, state);
2221
2222         return 0;
2223 }
2224
2225 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2226 {
2227         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2228         case MII_TG3_AUX_STAT_10HALF:
2229                 *speed = SPEED_10;
2230                 *duplex = DUPLEX_HALF;
2231                 break;
2232
2233         case MII_TG3_AUX_STAT_10FULL:
2234                 *speed = SPEED_10;
2235                 *duplex = DUPLEX_FULL;
2236                 break;
2237
2238         case MII_TG3_AUX_STAT_100HALF:
2239                 *speed = SPEED_100;
2240                 *duplex = DUPLEX_HALF;
2241                 break;
2242
2243         case MII_TG3_AUX_STAT_100FULL:
2244                 *speed = SPEED_100;
2245                 *duplex = DUPLEX_FULL;
2246                 break;
2247
2248         case MII_TG3_AUX_STAT_1000HALF:
2249                 *speed = SPEED_1000;
2250                 *duplex = DUPLEX_HALF;
2251                 break;
2252
2253         case MII_TG3_AUX_STAT_1000FULL:
2254                 *speed = SPEED_1000;
2255                 *duplex = DUPLEX_FULL;
2256                 break;
2257
2258         default:
2259                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2260                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2261                                  SPEED_10;
2262                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2263                                   DUPLEX_HALF;
2264                         break;
2265                 }
2266                 *speed = SPEED_INVALID;
2267                 *duplex = DUPLEX_INVALID;
2268                 break;
2269         }
2270 }
2271
2272 static void tg3_phy_copper_begin(struct tg3 *tp)
2273 {
2274         u32 new_adv;
2275         int i;
2276
2277         if (tp->link_config.phy_is_low_power) {
2278                 /* Entering low power mode.  Disable gigabit and
2279                  * 100baseT advertisements.
2280                  */
2281                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2282
2283                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2284                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2285                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2286                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2287
2288                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2289         } else if (tp->link_config.speed == SPEED_INVALID) {
2290                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2291                         tp->link_config.advertising &=
2292                                 ~(ADVERTISED_1000baseT_Half |
2293                                   ADVERTISED_1000baseT_Full);
2294
2295                 new_adv = ADVERTISE_CSMA;
2296                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2297                         new_adv |= ADVERTISE_10HALF;
2298                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2299                         new_adv |= ADVERTISE_10FULL;
2300                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2301                         new_adv |= ADVERTISE_100HALF;
2302                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2303                         new_adv |= ADVERTISE_100FULL;
2304
2305                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2306
2307                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2308
2309                 if (tp->link_config.advertising &
2310                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2311                         new_adv = 0;
2312                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2313                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2314                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2315                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2316                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2317                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2318                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2319                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2320                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2321                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2322                 } else {
2323                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2324                 }
2325         } else {
2326                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2327                 new_adv |= ADVERTISE_CSMA;
2328
2329                 /* Asking for a specific link mode. */
2330                 if (tp->link_config.speed == SPEED_1000) {
2331                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2332
2333                         if (tp->link_config.duplex == DUPLEX_FULL)
2334                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2335                         else
2336                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2337                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2338                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2339                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2340                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2341                 } else {
2342                         if (tp->link_config.speed == SPEED_100) {
2343                                 if (tp->link_config.duplex == DUPLEX_FULL)
2344                                         new_adv |= ADVERTISE_100FULL;
2345                                 else
2346                                         new_adv |= ADVERTISE_100HALF;
2347                         } else {
2348                                 if (tp->link_config.duplex == DUPLEX_FULL)
2349                                         new_adv |= ADVERTISE_10FULL;
2350                                 else
2351                                         new_adv |= ADVERTISE_10HALF;
2352                         }
2353                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2354
2355                         new_adv = 0;
2356                 }
2357
2358                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2359         }
2360
2361         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2362             tp->link_config.speed != SPEED_INVALID) {
2363                 u32 bmcr, orig_bmcr;
2364
2365                 tp->link_config.active_speed = tp->link_config.speed;
2366                 tp->link_config.active_duplex = tp->link_config.duplex;
2367
2368                 bmcr = 0;
2369                 switch (tp->link_config.speed) {
2370                 default:
2371                 case SPEED_10:
2372                         break;
2373
2374                 case SPEED_100:
2375                         bmcr |= BMCR_SPEED100;
2376                         break;
2377
2378                 case SPEED_1000:
2379                         bmcr |= TG3_BMCR_SPEED1000;
2380                         break;
2381                 }
2382
2383                 if (tp->link_config.duplex == DUPLEX_FULL)
2384                         bmcr |= BMCR_FULLDPLX;
2385
2386                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2387                     (bmcr != orig_bmcr)) {
2388                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2389                         for (i = 0; i < 1500; i++) {
2390                                 u32 tmp;
2391
2392                                 udelay(10);
2393                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2394                                     tg3_readphy(tp, MII_BMSR, &tmp))
2395                                         continue;
2396                                 if (!(tmp & BMSR_LSTATUS)) {
2397                                         udelay(40);
2398                                         break;
2399                                 }
2400                         }
2401                         tg3_writephy(tp, MII_BMCR, bmcr);
2402                         udelay(40);
2403                 }
2404         } else {
2405                 tg3_writephy(tp, MII_BMCR,
2406                              BMCR_ANENABLE | BMCR_ANRESTART);
2407         }
2408 }
2409
2410 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2411 {
2412         int err;
2413
2414         /* Turn off tap power management. */
2415         /* Set Extended packet length bit */
2416         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2417
2418         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2419         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2420
2421         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2422         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2423
2424         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2425         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2426
2427         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2428         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2429
2430         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2431         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2432
2433         udelay(40);
2434
2435         return err;
2436 }
2437
2438 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2439 {
2440         u32 adv_reg, all_mask = 0;
2441
2442         if (mask & ADVERTISED_10baseT_Half)
2443                 all_mask |= ADVERTISE_10HALF;
2444         if (mask & ADVERTISED_10baseT_Full)
2445                 all_mask |= ADVERTISE_10FULL;
2446         if (mask & ADVERTISED_100baseT_Half)
2447                 all_mask |= ADVERTISE_100HALF;
2448         if (mask & ADVERTISED_100baseT_Full)
2449                 all_mask |= ADVERTISE_100FULL;
2450
2451         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2452                 return 0;
2453
2454         if ((adv_reg & all_mask) != all_mask)
2455                 return 0;
2456         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2457                 u32 tg3_ctrl;
2458
2459                 all_mask = 0;
2460                 if (mask & ADVERTISED_1000baseT_Half)
2461                         all_mask |= ADVERTISE_1000HALF;
2462                 if (mask & ADVERTISED_1000baseT_Full)
2463                         all_mask |= ADVERTISE_1000FULL;
2464
2465                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2466                         return 0;
2467
2468                 if ((tg3_ctrl & all_mask) != all_mask)
2469                         return 0;
2470         }
2471         return 1;
2472 }
2473
2474 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2475 {
2476         u32 curadv, reqadv;
2477
2478         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2479                 return 1;
2480
2481         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2482         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2483
2484         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2485                 if (curadv != reqadv)
2486                         return 0;
2487
2488                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2489                         tg3_readphy(tp, MII_LPA, rmtadv);
2490         } else {
2491                 /* Reprogram the advertisement register, even if it
2492                  * does not affect the current link.  If the link
2493                  * gets renegotiated in the future, we can save an
2494                  * additional renegotiation cycle by advertising
2495                  * it correctly in the first place.
2496                  */
2497                 if (curadv != reqadv) {
2498                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2499                                      ADVERTISE_PAUSE_ASYM);
2500                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2501                 }
2502         }
2503
2504         return 1;
2505 }
2506
2507 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2508 {
2509         int current_link_up;
2510         u32 bmsr, dummy;
2511         u32 lcl_adv, rmt_adv;
2512         u16 current_speed;
2513         u8 current_duplex;
2514         int i, err;
2515
2516         tw32(MAC_EVENT, 0);
2517
2518         tw32_f(MAC_STATUS,
2519              (MAC_STATUS_SYNC_CHANGED |
2520               MAC_STATUS_CFG_CHANGED |
2521               MAC_STATUS_MI_COMPLETION |
2522               MAC_STATUS_LNKSTATE_CHANGED));
2523         udelay(40);
2524
2525         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2526                 tw32_f(MAC_MI_MODE,
2527                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2528                 udelay(80);
2529         }
2530
2531         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2532
2533         /* Some third-party PHYs need to be reset on link going
2534          * down.
2535          */
2536         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2537              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2538              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2539             netif_carrier_ok(tp->dev)) {
2540                 tg3_readphy(tp, MII_BMSR, &bmsr);
2541                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2542                     !(bmsr & BMSR_LSTATUS))
2543                         force_reset = 1;
2544         }
2545         if (force_reset)
2546                 tg3_phy_reset(tp);
2547
2548         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2549                 tg3_readphy(tp, MII_BMSR, &bmsr);
2550                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2551                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2552                         bmsr = 0;
2553
2554                 if (!(bmsr & BMSR_LSTATUS)) {
2555                         err = tg3_init_5401phy_dsp(tp);
2556                         if (err)
2557                                 return err;
2558
2559                         tg3_readphy(tp, MII_BMSR, &bmsr);
2560                         for (i = 0; i < 1000; i++) {
2561                                 udelay(10);
2562                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2563                                     (bmsr & BMSR_LSTATUS)) {
2564                                         udelay(40);
2565                                         break;
2566                                 }
2567                         }
2568
2569                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
2570                             !(bmsr & BMSR_LSTATUS) &&
2571                             tp->link_config.active_speed == SPEED_1000) {
2572                                 err = tg3_phy_reset(tp);
2573                                 if (!err)
2574                                         err = tg3_init_5401phy_dsp(tp);
2575                                 if (err)
2576                                         return err;
2577                         }
2578                 }
2579         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2580                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2581                 /* 5701 {A0,B0} CRC bug workaround */
2582                 tg3_writephy(tp, 0x15, 0x0a75);
2583                 tg3_writephy(tp, 0x1c, 0x8c68);
2584                 tg3_writephy(tp, 0x1c, 0x8d68);
2585                 tg3_writephy(tp, 0x1c, 0x8c68);
2586         }
2587
2588         /* Clear pending interrupts... */
2589         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2590         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2591
2592         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
2593                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
2594         else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
2595                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
2596
2597         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2598             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2599                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
2600                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2601                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
2602                 else
2603                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
2604         }
2605
2606         current_link_up = 0;
2607         current_speed = SPEED_INVALID;
2608         current_duplex = DUPLEX_INVALID;
2609
2610         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
2611                 u32 val;
2612
2613                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
2614                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
2615                 if (!(val & (1 << 10))) {
2616                         val |= (1 << 10);
2617                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2618                         goto relink;
2619                 }
2620         }
2621
2622         bmsr = 0;
2623         for (i = 0; i < 100; i++) {
2624                 tg3_readphy(tp, MII_BMSR, &bmsr);
2625                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2626                     (bmsr & BMSR_LSTATUS))
2627                         break;
2628                 udelay(40);
2629         }
2630
2631         if (bmsr & BMSR_LSTATUS) {
2632                 u32 aux_stat, bmcr;
2633
2634                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
2635                 for (i = 0; i < 2000; i++) {
2636                         udelay(10);
2637                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
2638                             aux_stat)
2639                                 break;
2640                 }
2641
2642                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
2643                                              &current_speed,
2644                                              &current_duplex);
2645
2646                 bmcr = 0;
2647                 for (i = 0; i < 200; i++) {
2648                         tg3_readphy(tp, MII_BMCR, &bmcr);
2649                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
2650                                 continue;
2651                         if (bmcr && bmcr != 0x7fff)
2652                                 break;
2653                         udelay(10);
2654                 }
2655
2656                 lcl_adv = 0;
2657                 rmt_adv = 0;
2658
2659                 tp->link_config.active_speed = current_speed;
2660                 tp->link_config.active_duplex = current_duplex;
2661
2662                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2663                         if ((bmcr & BMCR_ANENABLE) &&
2664                             tg3_copper_is_advertising_all(tp,
2665                                                 tp->link_config.advertising)) {
2666                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
2667                                                                   &rmt_adv))
2668                                         current_link_up = 1;
2669                         }
2670                 } else {
2671                         if (!(bmcr & BMCR_ANENABLE) &&
2672                             tp->link_config.speed == current_speed &&
2673                             tp->link_config.duplex == current_duplex &&
2674                             tp->link_config.flowctrl ==
2675                             tp->link_config.active_flowctrl) {
2676                                 current_link_up = 1;
2677                         }
2678                 }
2679
2680                 if (current_link_up == 1 &&
2681                     tp->link_config.active_duplex == DUPLEX_FULL)
2682                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2683         }
2684
2685 relink:
2686         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
2687                 u32 tmp;
2688
2689                 tg3_phy_copper_begin(tp);
2690
2691                 tg3_readphy(tp, MII_BMSR, &tmp);
2692                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
2693                     (tmp & BMSR_LSTATUS))
2694                         current_link_up = 1;
2695         }
2696
2697         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
2698         if (current_link_up == 1) {
2699                 if (tp->link_config.active_speed == SPEED_100 ||
2700                     tp->link_config.active_speed == SPEED_10)
2701                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
2702                 else
2703                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2704         } else
2705                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2706
2707         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2708         if (tp->link_config.active_duplex == DUPLEX_HALF)
2709                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2710
2711         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
2712                 if (current_link_up == 1 &&
2713                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
2714                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2715                 else
2716                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2717         }
2718
2719         /* ??? Without this setting Netgear GA302T PHY does not
2720          * ??? send/receive packets...
2721          */
2722         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2723             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2724                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2725                 tw32_f(MAC_MI_MODE, tp->mi_mode);
2726                 udelay(80);
2727         }
2728
2729         tw32_f(MAC_MODE, tp->mac_mode);
2730         udelay(40);
2731
2732         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2733                 /* Polled via timer. */
2734                 tw32_f(MAC_EVENT, 0);
2735         } else {
2736                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2737         }
2738         udelay(40);
2739
2740         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2741             current_link_up == 1 &&
2742             tp->link_config.active_speed == SPEED_1000 &&
2743             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2744              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2745                 udelay(120);
2746                 tw32_f(MAC_STATUS,
2747                      (MAC_STATUS_SYNC_CHANGED |
2748                       MAC_STATUS_CFG_CHANGED));
2749                 udelay(40);
2750                 tg3_write_mem(tp,
2751                               NIC_SRAM_FIRMWARE_MBOX,
2752                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2753         }
2754
2755         if (current_link_up != netif_carrier_ok(tp->dev)) {
2756                 if (current_link_up)
2757                         netif_carrier_on(tp->dev);
2758                 else
2759                         netif_carrier_off(tp->dev);
2760                 tg3_link_report(tp);
2761         }
2762
2763         return 0;
2764 }
2765
2766 struct tg3_fiber_aneginfo {
2767         int state;
2768 #define ANEG_STATE_UNKNOWN              0
2769 #define ANEG_STATE_AN_ENABLE            1
2770 #define ANEG_STATE_RESTART_INIT         2
2771 #define ANEG_STATE_RESTART              3
2772 #define ANEG_STATE_DISABLE_LINK_OK      4
2773 #define ANEG_STATE_ABILITY_DETECT_INIT  5
2774 #define ANEG_STATE_ABILITY_DETECT       6
2775 #define ANEG_STATE_ACK_DETECT_INIT      7
2776 #define ANEG_STATE_ACK_DETECT           8
2777 #define ANEG_STATE_COMPLETE_ACK_INIT    9
2778 #define ANEG_STATE_COMPLETE_ACK         10
2779 #define ANEG_STATE_IDLE_DETECT_INIT     11
2780 #define ANEG_STATE_IDLE_DETECT          12
2781 #define ANEG_STATE_LINK_OK              13
2782 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
2783 #define ANEG_STATE_NEXT_PAGE_WAIT       15
2784
2785         u32 flags;
2786 #define MR_AN_ENABLE            0x00000001
2787 #define MR_RESTART_AN           0x00000002
2788 #define MR_AN_COMPLETE          0x00000004
2789 #define MR_PAGE_RX              0x00000008
2790 #define MR_NP_LOADED            0x00000010
2791 #define MR_TOGGLE_TX            0x00000020
2792 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
2793 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
2794 #define MR_LP_ADV_SYM_PAUSE     0x00000100
2795 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
2796 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2797 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2798 #define MR_LP_ADV_NEXT_PAGE     0x00001000
2799 #define MR_TOGGLE_RX            0x00002000
2800 #define MR_NP_RX                0x00004000
2801
2802 #define MR_LINK_OK              0x80000000
2803
2804         unsigned long link_time, cur_time;
2805
2806         u32 ability_match_cfg;
2807         int ability_match_count;
2808
2809         char ability_match, idle_match, ack_match;
2810
2811         u32 txconfig, rxconfig;
2812 #define ANEG_CFG_NP             0x00000080
2813 #define ANEG_CFG_ACK            0x00000040
2814 #define ANEG_CFG_RF2            0x00000020
2815 #define ANEG_CFG_RF1            0x00000010
2816 #define ANEG_CFG_PS2            0x00000001
2817 #define ANEG_CFG_PS1            0x00008000
2818 #define ANEG_CFG_HD             0x00004000
2819 #define ANEG_CFG_FD             0x00002000
2820 #define ANEG_CFG_INVAL          0x00001f06
2821
2822 };
2823 #define ANEG_OK         0
2824 #define ANEG_DONE       1
2825 #define ANEG_TIMER_ENAB 2
2826 #define ANEG_FAILED     -1
2827
2828 #define ANEG_STATE_SETTLE_TIME  10000
2829
2830 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2831                                    struct tg3_fiber_aneginfo *ap)
2832 {
2833         u16 flowctrl;
2834         unsigned long delta;
2835         u32 rx_cfg_reg;
2836         int ret;
2837
2838         if (ap->state == ANEG_STATE_UNKNOWN) {
2839                 ap->rxconfig = 0;
2840                 ap->link_time = 0;
2841                 ap->cur_time = 0;
2842                 ap->ability_match_cfg = 0;
2843                 ap->ability_match_count = 0;
2844                 ap->ability_match = 0;
2845                 ap->idle_match = 0;
2846                 ap->ack_match = 0;
2847         }
2848         ap->cur_time++;
2849
2850         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2851                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2852
2853                 if (rx_cfg_reg != ap->ability_match_cfg) {
2854                         ap->ability_match_cfg = rx_cfg_reg;
2855                         ap->ability_match = 0;
2856                         ap->ability_match_count = 0;
2857                 } else {
2858                         if (++ap->ability_match_count > 1) {
2859                                 ap->ability_match = 1;
2860                                 ap->ability_match_cfg = rx_cfg_reg;
2861                         }
2862                 }
2863                 if (rx_cfg_reg & ANEG_CFG_ACK)
2864                         ap->ack_match = 1;
2865                 else
2866                         ap->ack_match = 0;
2867
2868                 ap->idle_match = 0;
2869         } else {
2870                 ap->idle_match = 1;
2871                 ap->ability_match_cfg = 0;
2872                 ap->ability_match_count = 0;
2873                 ap->ability_match = 0;
2874                 ap->ack_match = 0;
2875
2876                 rx_cfg_reg = 0;
2877         }
2878
2879         ap->rxconfig = rx_cfg_reg;
2880         ret = ANEG_OK;
2881
2882         switch(ap->state) {
2883         case ANEG_STATE_UNKNOWN:
2884                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2885                         ap->state = ANEG_STATE_AN_ENABLE;
2886
2887                 /* fallthru */
2888         case ANEG_STATE_AN_ENABLE:
2889                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2890                 if (ap->flags & MR_AN_ENABLE) {
2891                         ap->link_time = 0;
2892                         ap->cur_time = 0;
2893                         ap->ability_match_cfg = 0;
2894                         ap->ability_match_count = 0;
2895                         ap->ability_match = 0;
2896                         ap->idle_match = 0;
2897                         ap->ack_match = 0;
2898
2899                         ap->state = ANEG_STATE_RESTART_INIT;
2900                 } else {
2901                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
2902                 }
2903                 break;
2904
2905         case ANEG_STATE_RESTART_INIT:
2906                 ap->link_time = ap->cur_time;
2907                 ap->flags &= ~(MR_NP_LOADED);
2908                 ap->txconfig = 0;
2909                 tw32(MAC_TX_AUTO_NEG, 0);
2910                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2911                 tw32_f(MAC_MODE, tp->mac_mode);
2912                 udelay(40);
2913
2914                 ret = ANEG_TIMER_ENAB;
2915                 ap->state = ANEG_STATE_RESTART;
2916
2917                 /* fallthru */
2918         case ANEG_STATE_RESTART:
2919                 delta = ap->cur_time - ap->link_time;
2920                 if (delta > ANEG_STATE_SETTLE_TIME) {
2921                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2922                 } else {
2923                         ret = ANEG_TIMER_ENAB;
2924                 }
2925                 break;
2926
2927         case ANEG_STATE_DISABLE_LINK_OK:
2928                 ret = ANEG_DONE;
2929                 break;
2930
2931         case ANEG_STATE_ABILITY_DETECT_INIT:
2932                 ap->flags &= ~(MR_TOGGLE_TX);
2933                 ap->txconfig = ANEG_CFG_FD;
2934                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
2935                 if (flowctrl & ADVERTISE_1000XPAUSE)
2936                         ap->txconfig |= ANEG_CFG_PS1;
2937                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
2938                         ap->txconfig |= ANEG_CFG_PS2;
2939                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2940                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2941                 tw32_f(MAC_MODE, tp->mac_mode);
2942                 udelay(40);
2943
2944                 ap->state = ANEG_STATE_ABILITY_DETECT;
2945                 break;
2946
2947         case ANEG_STATE_ABILITY_DETECT:
2948                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2949                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
2950                 }
2951                 break;
2952
2953         case ANEG_STATE_ACK_DETECT_INIT:
2954                 ap->txconfig |= ANEG_CFG_ACK;
2955                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2956                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2957                 tw32_f(MAC_MODE, tp->mac_mode);
2958                 udelay(40);
2959
2960                 ap->state = ANEG_STATE_ACK_DETECT;
2961
2962                 /* fallthru */
2963         case ANEG_STATE_ACK_DETECT:
2964                 if (ap->ack_match != 0) {
2965                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2966                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2967                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2968                         } else {
2969                                 ap->state = ANEG_STATE_AN_ENABLE;
2970                         }
2971                 } else if (ap->ability_match != 0 &&
2972                            ap->rxconfig == 0) {
2973                         ap->state = ANEG_STATE_AN_ENABLE;
2974                 }
2975                 break;
2976
2977         case ANEG_STATE_COMPLETE_ACK_INIT:
2978                 if (ap->rxconfig & ANEG_CFG_INVAL) {
2979                         ret = ANEG_FAILED;
2980                         break;
2981                 }
2982                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2983                                MR_LP_ADV_HALF_DUPLEX |
2984                                MR_LP_ADV_SYM_PAUSE |
2985                                MR_LP_ADV_ASYM_PAUSE |
2986                                MR_LP_ADV_REMOTE_FAULT1 |
2987                                MR_LP_ADV_REMOTE_FAULT2 |
2988                                MR_LP_ADV_NEXT_PAGE |
2989                                MR_TOGGLE_RX |
2990                                MR_NP_RX);
2991                 if (ap->rxconfig & ANEG_CFG_FD)
2992                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2993                 if (ap->rxconfig & ANEG_CFG_HD)
2994                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2995                 if (ap->rxconfig & ANEG_CFG_PS1)
2996                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
2997                 if (ap->rxconfig & ANEG_CFG_PS2)
2998                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2999                 if (ap->rxconfig & ANEG_CFG_RF1)
3000                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3001                 if (ap->rxconfig & ANEG_CFG_RF2)
3002                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3003                 if (ap->rxconfig & ANEG_CFG_NP)
3004                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3005
3006                 ap->link_time = ap->cur_time;
3007
3008                 ap->flags ^= (MR_TOGGLE_TX);
3009                 if (ap->rxconfig & 0x0008)
3010                         ap->flags |= MR_TOGGLE_RX;
3011                 if (ap->rxconfig & ANEG_CFG_NP)
3012                         ap->flags |= MR_NP_RX;
3013                 ap->flags |= MR_PAGE_RX;
3014
3015                 ap->state = ANEG_STATE_COMPLETE_ACK;
3016                 ret = ANEG_TIMER_ENAB;
3017                 break;
3018
3019         case ANEG_STATE_COMPLETE_ACK:
3020                 if (ap->ability_match != 0 &&
3021                     ap->rxconfig == 0) {
3022                         ap->state = ANEG_STATE_AN_ENABLE;
3023                         break;
3024                 }
3025                 delta = ap->cur_time - ap->link_time;
3026                 if (delta > ANEG_STATE_SETTLE_TIME) {
3027                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3028                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3029                         } else {
3030                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3031                                     !(ap->flags & MR_NP_RX)) {
3032                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3033                                 } else {
3034                                         ret = ANEG_FAILED;
3035                                 }
3036                         }
3037                 }
3038                 break;
3039
3040         case ANEG_STATE_IDLE_DETECT_INIT:
3041                 ap->link_time = ap->cur_time;
3042                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3043                 tw32_f(MAC_MODE, tp->mac_mode);
3044                 udelay(40);
3045
3046                 ap->state = ANEG_STATE_IDLE_DETECT;
3047                 ret = ANEG_TIMER_ENAB;
3048                 break;
3049
3050         case ANEG_STATE_IDLE_DETECT:
3051                 if (ap->ability_match != 0 &&
3052                     ap->rxconfig == 0) {
3053                         ap->state = ANEG_STATE_AN_ENABLE;
3054                         break;
3055                 }
3056                 delta = ap->cur_time - ap->link_time;
3057                 if (delta > ANEG_STATE_SETTLE_TIME) {
3058                         /* XXX another gem from the Broadcom driver :( */
3059                         ap->state = ANEG_STATE_LINK_OK;
3060                 }
3061                 break;
3062
3063         case ANEG_STATE_LINK_OK:
3064                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3065                 ret = ANEG_DONE;
3066                 break;
3067
3068         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3069                 /* ??? unimplemented */
3070                 break;
3071
3072         case ANEG_STATE_NEXT_PAGE_WAIT:
3073                 /* ??? unimplemented */
3074                 break;
3075
3076         default:
3077                 ret = ANEG_FAILED;
3078                 break;
3079         }
3080
3081         return ret;
3082 }
3083
3084 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3085 {
3086         int res = 0;
3087         struct tg3_fiber_aneginfo aninfo;
3088         int status = ANEG_FAILED;
3089         unsigned int tick;
3090         u32 tmp;
3091
3092         tw32_f(MAC_TX_AUTO_NEG, 0);
3093
3094         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3095         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3096         udelay(40);
3097
3098         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3099         udelay(40);
3100
3101         memset(&aninfo, 0, sizeof(aninfo));
3102         aninfo.flags |= MR_AN_ENABLE;
3103         aninfo.state = ANEG_STATE_UNKNOWN;
3104         aninfo.cur_time = 0;
3105         tick = 0;
3106         while (++tick < 195000) {
3107                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3108                 if (status == ANEG_DONE || status == ANEG_FAILED)
3109                         break;
3110
3111                 udelay(1);
3112         }
3113
3114         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3115         tw32_f(MAC_MODE, tp->mac_mode);
3116         udelay(40);
3117
3118         *txflags = aninfo.txconfig;
3119         *rxflags = aninfo.flags;
3120
3121         if (status == ANEG_DONE &&
3122             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3123                              MR_LP_ADV_FULL_DUPLEX)))
3124                 res = 1;
3125
3126         return res;
3127 }
3128
3129 static void tg3_init_bcm8002(struct tg3 *tp)
3130 {
3131         u32 mac_status = tr32(MAC_STATUS);
3132         int i;
3133
3134         /* Reset when initting first time or we have a link. */
3135         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3136             !(mac_status & MAC_STATUS_PCS_SYNCED))
3137                 return;
3138
3139         /* Set PLL lock range. */
3140         tg3_writephy(tp, 0x16, 0x8007);
3141
3142         /* SW reset */
3143         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3144
3145         /* Wait for reset to complete. */
3146         /* XXX schedule_timeout() ... */
3147         for (i = 0; i < 500; i++)
3148                 udelay(10);
3149
3150         /* Config mode; select PMA/Ch 1 regs. */
3151         tg3_writephy(tp, 0x10, 0x8411);
3152
3153         /* Enable auto-lock and comdet, select txclk for tx. */
3154         tg3_writephy(tp, 0x11, 0x0a10);
3155
3156         tg3_writephy(tp, 0x18, 0x00a0);
3157         tg3_writephy(tp, 0x16, 0x41ff);
3158
3159         /* Assert and deassert POR. */
3160         tg3_writephy(tp, 0x13, 0x0400);
3161         udelay(40);
3162         tg3_writephy(tp, 0x13, 0x0000);
3163
3164         tg3_writephy(tp, 0x11, 0x0a50);
3165         udelay(40);
3166         tg3_writephy(tp, 0x11, 0x0a10);
3167
3168         /* Wait for signal to stabilize */
3169         /* XXX schedule_timeout() ... */
3170         for (i = 0; i < 15000; i++)
3171                 udelay(10);
3172
3173         /* Deselect the channel register so we can read the PHYID
3174          * later.
3175          */
3176         tg3_writephy(tp, 0x10, 0x8011);
3177 }
3178
3179 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3180 {
3181         u16 flowctrl;
3182         u32 sg_dig_ctrl, sg_dig_status;
3183         u32 serdes_cfg, expected_sg_dig_ctrl;
3184         int workaround, port_a;
3185         int current_link_up;
3186
3187         serdes_cfg = 0;
3188         expected_sg_dig_ctrl = 0;
3189         workaround = 0;
3190         port_a = 1;
3191         current_link_up = 0;
3192
3193         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3194             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3195                 workaround = 1;
3196                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3197                         port_a = 0;
3198
3199                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3200                 /* preserve bits 20-23 for voltage regulator */
3201                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3202         }
3203
3204         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3205
3206         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3207                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3208                         if (workaround) {
3209                                 u32 val = serdes_cfg;
3210
3211                                 if (port_a)
3212                                         val |= 0xc010000;
3213                                 else
3214                                         val |= 0x4010000;
3215                                 tw32_f(MAC_SERDES_CFG, val);
3216                         }
3217
3218                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3219                 }
3220                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3221                         tg3_setup_flow_control(tp, 0, 0);
3222                         current_link_up = 1;
3223                 }
3224                 goto out;
3225         }
3226
3227         /* Want auto-negotiation.  */
3228         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3229
3230         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3231         if (flowctrl & ADVERTISE_1000XPAUSE)
3232                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3233         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3234                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3235
3236         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3237                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3238                     tp->serdes_counter &&
3239                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3240                                     MAC_STATUS_RCVD_CFG)) ==
3241                      MAC_STATUS_PCS_SYNCED)) {
3242                         tp->serdes_counter--;
3243                         current_link_up = 1;
3244                         goto out;
3245                 }
3246 restart_autoneg:
3247                 if (workaround)
3248                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3249                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3250                 udelay(5);
3251                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3252
3253                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3254                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3255         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3256                                  MAC_STATUS_SIGNAL_DET)) {
3257                 sg_dig_status = tr32(SG_DIG_STATUS);
3258                 mac_status = tr32(MAC_STATUS);
3259
3260                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3261                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3262                         u32 local_adv = 0, remote_adv = 0;
3263
3264                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3265                                 local_adv |= ADVERTISE_1000XPAUSE;
3266                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3267                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3268
3269                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3270                                 remote_adv |= LPA_1000XPAUSE;
3271                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3272                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3273
3274                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3275                         current_link_up = 1;
3276                         tp->serdes_counter = 0;
3277                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3278                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3279                         if (tp->serdes_counter)
3280                                 tp->serdes_counter--;
3281                         else {
3282                                 if (workaround) {
3283                                         u32 val = serdes_cfg;
3284
3285                                         if (port_a)
3286                                                 val |= 0xc010000;
3287                                         else
3288                                                 val |= 0x4010000;
3289
3290                                         tw32_f(MAC_SERDES_CFG, val);
3291                                 }
3292
3293                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3294                                 udelay(40);
3295
3296                                 /* Link parallel detection - link is up */
3297                                 /* only if we have PCS_SYNC and not */
3298                                 /* receiving config code words */
3299                                 mac_status = tr32(MAC_STATUS);
3300                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3301                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3302                                         tg3_setup_flow_control(tp, 0, 0);
3303                                         current_link_up = 1;
3304                                         tp->tg3_flags2 |=
3305                                                 TG3_FLG2_PARALLEL_DETECT;
3306                                         tp->serdes_counter =
3307                                                 SERDES_PARALLEL_DET_TIMEOUT;
3308                                 } else
3309                                         goto restart_autoneg;
3310                         }
3311                 }
3312         } else {
3313                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3314                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3315         }
3316
3317 out:
3318         return current_link_up;
3319 }
3320
3321 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3322 {
3323         int current_link_up = 0;
3324
3325         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3326                 goto out;
3327
3328         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3329                 u32 txflags, rxflags;
3330                 int i;
3331
3332                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3333                         u32 local_adv = 0, remote_adv = 0;
3334
3335                         if (txflags & ANEG_CFG_PS1)
3336                                 local_adv |= ADVERTISE_1000XPAUSE;
3337                         if (txflags & ANEG_CFG_PS2)
3338                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3339
3340                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3341                                 remote_adv |= LPA_1000XPAUSE;
3342                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3343                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3344
3345                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3346
3347                         current_link_up = 1;
3348                 }
3349                 for (i = 0; i < 30; i++) {
3350                         udelay(20);
3351                         tw32_f(MAC_STATUS,
3352                                (MAC_STATUS_SYNC_CHANGED |
3353                                 MAC_STATUS_CFG_CHANGED));
3354                         udelay(40);
3355                         if ((tr32(MAC_STATUS) &
3356                              (MAC_STATUS_SYNC_CHANGED |
3357                               MAC_STATUS_CFG_CHANGED)) == 0)
3358                                 break;
3359                 }
3360
3361                 mac_status = tr32(MAC_STATUS);
3362                 if (current_link_up == 0 &&
3363                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3364                     !(mac_status & MAC_STATUS_RCVD_CFG))
3365                         current_link_up = 1;
3366         } else {
3367                 tg3_setup_flow_control(tp, 0, 0);
3368
3369                 /* Forcing 1000FD link up. */
3370                 current_link_up = 1;
3371
3372                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3373                 udelay(40);
3374
3375                 tw32_f(MAC_MODE, tp->mac_mode);
3376                 udelay(40);
3377         }
3378
3379 out:
3380         return current_link_up;
3381 }
3382
3383 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3384 {
3385         u32 orig_pause_cfg;
3386         u16 orig_active_speed;
3387         u8 orig_active_duplex;
3388         u32 mac_status;
3389         int current_link_up;
3390         int i;
3391
3392         orig_pause_cfg = tp->link_config.active_flowctrl;
3393         orig_active_speed = tp->link_config.active_speed;
3394         orig_active_duplex = tp->link_config.active_duplex;
3395
3396         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3397             netif_carrier_ok(tp->dev) &&
3398             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3399                 mac_status = tr32(MAC_STATUS);
3400                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3401                                MAC_STATUS_SIGNAL_DET |
3402                                MAC_STATUS_CFG_CHANGED |
3403                                MAC_STATUS_RCVD_CFG);
3404                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3405                                    MAC_STATUS_SIGNAL_DET)) {
3406                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3407                                             MAC_STATUS_CFG_CHANGED));
3408                         return 0;
3409                 }
3410         }
3411
3412         tw32_f(MAC_TX_AUTO_NEG, 0);
3413
3414         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3415         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3416         tw32_f(MAC_MODE, tp->mac_mode);
3417         udelay(40);
3418
3419         if (tp->phy_id == PHY_ID_BCM8002)
3420                 tg3_init_bcm8002(tp);
3421
3422         /* Enable link change event even when serdes polling.  */
3423         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3424         udelay(40);
3425
3426         current_link_up = 0;
3427         mac_status = tr32(MAC_STATUS);
3428
3429         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3430                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3431         else
3432                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3433
3434         tp->hw_status->status =
3435                 (SD_STATUS_UPDATED |
3436                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3437
3438         for (i = 0; i < 100; i++) {
3439                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3440                                     MAC_STATUS_CFG_CHANGED));
3441                 udelay(5);
3442                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3443                                          MAC_STATUS_CFG_CHANGED |
3444                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3445                         break;
3446         }
3447
3448         mac_status = tr32(MAC_STATUS);
3449         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3450                 current_link_up = 0;
3451                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3452                     tp->serdes_counter == 0) {
3453                         tw32_f(MAC_MODE, (tp->mac_mode |
3454                                           MAC_MODE_SEND_CONFIGS));
3455                         udelay(1);
3456                         tw32_f(MAC_MODE, tp->mac_mode);
3457                 }
3458         }
3459
3460         if (current_link_up == 1) {
3461                 tp->link_config.active_speed = SPEED_1000;
3462                 tp->link_config.active_duplex = DUPLEX_FULL;
3463                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3464                                     LED_CTRL_LNKLED_OVERRIDE |
3465                                     LED_CTRL_1000MBPS_ON));
3466         } else {
3467                 tp->link_config.active_speed = SPEED_INVALID;
3468                 tp->link_config.active_duplex = DUPLEX_INVALID;
3469                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3470                                     LED_CTRL_LNKLED_OVERRIDE |
3471                                     LED_CTRL_TRAFFIC_OVERRIDE));
3472         }
3473
3474         if (current_link_up != netif_carrier_ok(tp->dev)) {
3475                 if (current_link_up)
3476                         netif_carrier_on(tp->dev);
3477                 else
3478                         netif_carrier_off(tp->dev);
3479                 tg3_link_report(tp);
3480         } else {
3481                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
3482                 if (orig_pause_cfg != now_pause_cfg ||
3483                     orig_active_speed != tp->link_config.active_speed ||
3484                     orig_active_duplex != tp->link_config.active_duplex)
3485                         tg3_link_report(tp);
3486         }
3487
3488         return 0;
3489 }
3490
3491 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3492 {
3493         int current_link_up, err = 0;
3494         u32 bmsr, bmcr;
3495         u16 current_speed;
3496         u8 current_duplex;
3497         u32 local_adv, remote_adv;
3498
3499         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3500         tw32_f(MAC_MODE, tp->mac_mode);
3501         udelay(40);
3502
3503         tw32(MAC_EVENT, 0);
3504
3505         tw32_f(MAC_STATUS,
3506              (MAC_STATUS_SYNC_CHANGED |
3507               MAC_STATUS_CFG_CHANGED |
3508               MAC_STATUS_MI_COMPLETION |
3509               MAC_STATUS_LNKSTATE_CHANGED));
3510         udelay(40);
3511
3512         if (force_reset)
3513                 tg3_phy_reset(tp);
3514
3515         current_link_up = 0;
3516         current_speed = SPEED_INVALID;
3517         current_duplex = DUPLEX_INVALID;
3518
3519         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3520         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3521         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3522                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3523                         bmsr |= BMSR_LSTATUS;
3524                 else
3525                         bmsr &= ~BMSR_LSTATUS;
3526         }
3527
3528         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3529
3530         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
3531             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3532                 /* do nothing, just check for link up at the end */
3533         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3534                 u32 adv, new_adv;
3535
3536                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3537                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
3538                                   ADVERTISE_1000XPAUSE |
3539                                   ADVERTISE_1000XPSE_ASYM |
3540                                   ADVERTISE_SLCT);
3541
3542                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3543
3544                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
3545                         new_adv |= ADVERTISE_1000XHALF;
3546                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
3547                         new_adv |= ADVERTISE_1000XFULL;
3548
3549                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
3550                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
3551                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
3552                         tg3_writephy(tp, MII_BMCR, bmcr);
3553
3554                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3555                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
3556                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3557
3558                         return err;
3559                 }
3560         } else {
3561                 u32 new_bmcr;
3562
3563                 bmcr &= ~BMCR_SPEED1000;
3564                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
3565
3566                 if (tp->link_config.duplex == DUPLEX_FULL)
3567                         new_bmcr |= BMCR_FULLDPLX;
3568
3569                 if (new_bmcr != bmcr) {
3570                         /* BMCR_SPEED1000 is a reserved bit that needs
3571                          * to be set on write.
3572                          */
3573                         new_bmcr |= BMCR_SPEED1000;
3574
3575                         /* Force a linkdown */
3576                         if (netif_carrier_ok(tp->dev)) {
3577                                 u32 adv;
3578
3579                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3580                                 adv &= ~(ADVERTISE_1000XFULL |
3581                                          ADVERTISE_1000XHALF |
3582                                          ADVERTISE_SLCT);
3583                                 tg3_writephy(tp, MII_ADVERTISE, adv);
3584                                 tg3_writephy(tp, MII_BMCR, bmcr |
3585                                                            BMCR_ANRESTART |
3586                                                            BMCR_ANENABLE);
3587                                 udelay(10);
3588                                 netif_carrier_off(tp->dev);
3589                         }
3590                         tg3_writephy(tp, MII_BMCR, new_bmcr);
3591                         bmcr = new_bmcr;
3592                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3593                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3594                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
3595                             ASIC_REV_5714) {
3596                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3597                                         bmsr |= BMSR_LSTATUS;
3598                                 else
3599                                         bmsr &= ~BMSR_LSTATUS;
3600                         }
3601                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3602                 }
3603         }
3604
3605         if (bmsr & BMSR_LSTATUS) {
3606                 current_speed = SPEED_1000;
3607                 current_link_up = 1;
3608                 if (bmcr & BMCR_FULLDPLX)
3609                         current_duplex = DUPLEX_FULL;
3610                 else
3611                         current_duplex = DUPLEX_HALF;
3612
3613                 local_adv = 0;
3614                 remote_adv = 0;
3615
3616                 if (bmcr & BMCR_ANENABLE) {
3617                         u32 common;
3618
3619                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
3620                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
3621                         common = local_adv & remote_adv;
3622                         if (common & (ADVERTISE_1000XHALF |
3623                                       ADVERTISE_1000XFULL)) {
3624                                 if (common & ADVERTISE_1000XFULL)
3625                                         current_duplex = DUPLEX_FULL;
3626                                 else
3627                                         current_duplex = DUPLEX_HALF;
3628                         }
3629                         else
3630                                 current_link_up = 0;
3631                 }
3632         }
3633
3634         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
3635                 tg3_setup_flow_control(tp, local_adv, remote_adv);
3636
3637         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3638         if (tp->link_config.active_duplex == DUPLEX_HALF)
3639                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3640
3641         tw32_f(MAC_MODE, tp->mac_mode);
3642         udelay(40);
3643
3644         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3645
3646         tp->link_config.active_speed = current_speed;
3647         tp->link_config.active_duplex = current_duplex;
3648
3649         if (current_link_up != netif_carrier_ok(tp->dev)) {
3650                 if (current_link_up)
3651                         netif_carrier_on(tp->dev);
3652                 else {
3653                         netif_carrier_off(tp->dev);
3654                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3655                 }
3656                 tg3_link_report(tp);
3657         }
3658         return err;
3659 }
3660
3661 static void tg3_serdes_parallel_detect(struct tg3 *tp)
3662 {
3663         if (tp->serdes_counter) {
3664                 /* Give autoneg time to complete. */
3665                 tp->serdes_counter--;
3666                 return;
3667         }
3668         if (!netif_carrier_ok(tp->dev) &&
3669             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
3670                 u32 bmcr;
3671
3672                 tg3_readphy(tp, MII_BMCR, &bmcr);
3673                 if (bmcr & BMCR_ANENABLE) {
3674                         u32 phy1, phy2;
3675
3676                         /* Select shadow register 0x1f */
3677                         tg3_writephy(tp, 0x1c, 0x7c00);
3678                         tg3_readphy(tp, 0x1c, &phy1);
3679
3680                         /* Select expansion interrupt status register */
3681                         tg3_writephy(tp, 0x17, 0x0f01);
3682                         tg3_readphy(tp, 0x15, &phy2);
3683                         tg3_readphy(tp, 0x15, &phy2);
3684
3685                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
3686                                 /* We have signal detect and not receiving
3687                                  * config code words, link is up by parallel
3688                                  * detection.
3689                                  */
3690
3691                                 bmcr &= ~BMCR_ANENABLE;
3692                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
3693                                 tg3_writephy(tp, MII_BMCR, bmcr);
3694                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
3695                         }
3696                 }
3697         }
3698         else if (netif_carrier_ok(tp->dev) &&
3699                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
3700                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3701                 u32 phy2;
3702
3703                 /* Select expansion interrupt status register */
3704                 tg3_writephy(tp, 0x17, 0x0f01);
3705                 tg3_readphy(tp, 0x15, &phy2);
3706                 if (phy2 & 0x20) {
3707                         u32 bmcr;
3708
3709                         /* Config code words received, turn on autoneg. */
3710                         tg3_readphy(tp, MII_BMCR, &bmcr);
3711                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
3712
3713                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3714
3715                 }
3716         }
3717 }
3718
3719 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
3720 {
3721         int err;
3722
3723         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
3724                 err = tg3_setup_fiber_phy(tp, force_reset);
3725         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
3726                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
3727         } else {
3728                 err = tg3_setup_copper_phy(tp, force_reset);
3729         }
3730
3731         if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
3732             tp->pci_chip_rev_id == CHIPREV_ID_5784_A1) {
3733                 u32 val, scale;
3734
3735                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
3736                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
3737                         scale = 65;
3738                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
3739                         scale = 6;
3740                 else
3741                         scale = 12;
3742
3743                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
3744                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
3745                 tw32(GRC_MISC_CFG, val);
3746         }
3747
3748         if (tp->link_config.active_speed == SPEED_1000 &&
3749             tp->link_config.active_duplex == DUPLEX_HALF)
3750                 tw32(MAC_TX_LENGTHS,
3751                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3752                       (6 << TX_LENGTHS_IPG_SHIFT) |
3753                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3754         else
3755                 tw32(MAC_TX_LENGTHS,
3756                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3757                       (6 << TX_LENGTHS_IPG_SHIFT) |
3758                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3759
3760         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3761                 if (netif_carrier_ok(tp->dev)) {
3762                         tw32(HOSTCC_STAT_COAL_TICKS,
3763                              tp->coal.stats_block_coalesce_usecs);
3764                 } else {
3765                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
3766                 }
3767         }
3768
3769         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
3770                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
3771                 if (!netif_carrier_ok(tp->dev))
3772                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
3773                               tp->pwrmgmt_thresh;
3774                 else
3775                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
3776                 tw32(PCIE_PWR_MGMT_THRESH, val);
3777         }
3778
3779         return err;
3780 }
3781
3782 /* This is called whenever we suspect that the system chipset is re-
3783  * ordering the sequence of MMIO to the tx send mailbox. The symptom
3784  * is bogus tx completions. We try to recover by setting the
3785  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3786  * in the workqueue.
3787  */
3788 static void tg3_tx_recover(struct tg3 *tp)
3789 {
3790         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3791                tp->write32_tx_mbox == tg3_write_indirect_mbox);
3792
3793         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3794                "mapped I/O cycles to the network device, attempting to "
3795                "recover. Please report the problem to the driver maintainer "
3796                "and include system chipset information.\n", tp->dev->name);
3797
3798         spin_lock(&tp->lock);
3799         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3800         spin_unlock(&tp->lock);
3801 }
3802
3803 static inline u32 tg3_tx_avail(struct tg3 *tp)
3804 {
3805         smp_mb();
3806         return (tp->tx_pending -
3807                 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3808 }
3809
3810 /* Tigon3 never reports partial packet sends.  So we do not
3811  * need special logic to handle SKBs that have not had all
3812  * of their frags sent yet, like SunGEM does.
3813  */
3814 static void tg3_tx(struct tg3 *tp)
3815 {
3816         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3817         u32 sw_idx = tp->tx_cons;
3818
3819         while (sw_idx != hw_idx) {
3820                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3821                 struct sk_buff *skb = ri->skb;
3822                 int i, tx_bug = 0;
3823
3824                 if (unlikely(skb == NULL)) {
3825                         tg3_tx_recover(tp);
3826                         return;
3827                 }
3828
3829                 pci_unmap_single(tp->pdev,
3830                                  pci_unmap_addr(ri, mapping),
3831                                  skb_headlen(skb),
3832                                  PCI_DMA_TODEVICE);
3833
3834                 ri->skb = NULL;
3835
3836                 sw_idx = NEXT_TX(sw_idx);
3837
3838                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3839                         ri = &tp->tx_buffers[sw_idx];
3840                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3841                                 tx_bug = 1;
3842
3843                         pci_unmap_page(tp->pdev,
3844                                        pci_unmap_addr(ri, mapping),
3845                                        skb_shinfo(skb)->frags[i].size,
3846                                        PCI_DMA_TODEVICE);
3847
3848                         sw_idx = NEXT_TX(sw_idx);
3849                 }
3850
3851                 dev_kfree_skb(skb);
3852
3853                 if (unlikely(tx_bug)) {
3854                         tg3_tx_recover(tp);
3855                         return;
3856                 }
3857         }
3858
3859         tp->tx_cons = sw_idx;
3860
3861         /* Need to make the tx_cons update visible to tg3_start_xmit()
3862          * before checking for netif_queue_stopped().  Without the
3863          * memory barrier, there is a small possibility that tg3_start_xmit()
3864          * will miss it and cause the queue to be stopped forever.
3865          */
3866         smp_mb();
3867
3868         if (unlikely(netif_queue_stopped(tp->dev) &&
3869                      (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3870                 netif_tx_lock(tp->dev);
3871                 if (netif_queue_stopped(tp->dev) &&
3872                     (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3873                         netif_wake_queue(tp->dev);
3874                 netif_tx_unlock(tp->dev);
3875         }
3876 }
3877
3878 /* Returns size of skb allocated or < 0 on error.
3879  *
3880  * We only need to fill in the address because the other members
3881  * of the RX descriptor are invariant, see tg3_init_rings.
3882  *
3883  * Note the purposeful assymetry of cpu vs. chip accesses.  For
3884  * posting buffers we only dirty the first cache line of the RX
3885  * descriptor (containing the address).  Whereas for the RX status
3886  * buffers the cpu only reads the last cacheline of the RX descriptor
3887  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3888  */
3889 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3890                             int src_idx, u32 dest_idx_unmasked)
3891 {
3892         struct tg3_rx_buffer_desc *desc;
3893         struct ring_info *map, *src_map;
3894         struct sk_buff *skb;
3895         dma_addr_t mapping;
3896         int skb_size, dest_idx;
3897
3898         src_map = NULL;
3899         switch (opaque_key) {
3900         case RXD_OPAQUE_RING_STD:
3901                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3902                 desc = &tp->rx_std[dest_idx];
3903                 map = &tp->rx_std_buffers[dest_idx];
3904                 if (src_idx >= 0)
3905                         src_map = &tp->rx_std_buffers[src_idx];
3906                 skb_size = tp->rx_pkt_buf_sz;
3907                 break;
3908
3909         case RXD_OPAQUE_RING_JUMBO:
3910                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3911                 desc = &tp->rx_jumbo[dest_idx];
3912                 map = &tp->rx_jumbo_buffers[dest_idx];
3913                 if (src_idx >= 0)
3914                         src_map = &tp->rx_jumbo_buffers[src_idx];
3915                 skb_size = RX_JUMBO_PKT_BUF_SZ;
3916                 break;
3917
3918         default:
3919                 return -EINVAL;
3920         }
3921
3922         /* Do not overwrite any of the map or rp information
3923          * until we are sure we can commit to a new buffer.
3924          *
3925          * Callers depend upon this behavior and assume that
3926          * we leave everything unchanged if we fail.
3927          */
3928         skb = netdev_alloc_skb(tp->dev, skb_size);
3929         if (skb == NULL)
3930                 return -ENOMEM;
3931
3932         skb_reserve(skb, tp->rx_offset);
3933
3934         mapping = pci_map_single(tp->pdev, skb->data,
3935                                  skb_size - tp->rx_offset,
3936                                  PCI_DMA_FROMDEVICE);
3937
3938         map->skb = skb;
3939         pci_unmap_addr_set(map, mapping, mapping);
3940
3941         if (src_map != NULL)
3942                 src_map->skb = NULL;
3943
3944         desc->addr_hi = ((u64)mapping >> 32);
3945         desc->addr_lo = ((u64)mapping & 0xffffffff);
3946
3947         return skb_size;
3948 }
3949
3950 /* We only need to move over in the address because the other
3951  * members of the RX descriptor are invariant.  See notes above
3952  * tg3_alloc_rx_skb for full details.
3953  */
3954 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3955                            int src_idx, u32 dest_idx_unmasked)
3956 {
3957         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3958         struct ring_info *src_map, *dest_map;
3959         int dest_idx;
3960
3961         switch (opaque_key) {
3962         case RXD_OPAQUE_RING_STD:
3963                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3964                 dest_desc = &tp->rx_std[dest_idx];
3965                 dest_map = &tp->rx_std_buffers[dest_idx];
3966                 src_desc = &tp->rx_std[src_idx];
3967                 src_map = &tp->rx_std_buffers[src_idx];
3968                 break;
3969
3970         case RXD_OPAQUE_RING_JUMBO:
3971                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3972                 dest_desc = &tp->rx_jumbo[dest_idx];
3973                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3974                 src_desc = &tp->rx_jumbo[src_idx];
3975                 src_map = &tp->rx_jumbo_buffers[src_idx];
3976                 break;
3977
3978         default:
3979                 return;
3980         }
3981
3982         dest_map->skb = src_map->skb;
3983         pci_unmap_addr_set(dest_map, mapping,
3984                            pci_unmap_addr(src_map, mapping));
3985         dest_desc->addr_hi = src_desc->addr_hi;
3986         dest_desc->addr_lo = src_desc->addr_lo;
3987
3988         src_map->skb = NULL;
3989 }
3990
3991 #if TG3_VLAN_TAG_USED
3992 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3993 {
3994         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3995 }
3996 #endif
3997
3998 /* The RX ring scheme is composed of multiple rings which post fresh
3999  * buffers to the chip, and one special ring the chip uses to report
4000  * status back to the host.
4001  *
4002  * The special ring reports the status of received packets to the
4003  * host.  The chip does not write into the original descriptor the
4004  * RX buffer was obtained from.  The chip simply takes the original
4005  * descriptor as provided by the host, updates the status and length
4006  * field, then writes this into the next status ring entry.
4007  *
4008  * Each ring the host uses to post buffers to the chip is described
4009  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4010  * it is first placed into the on-chip ram.  When the packet's length
4011  * is known, it walks down the TG3_BDINFO entries to select the ring.
4012  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4013  * which is within the range of the new packet's length is chosen.
4014  *
4015  * The "separate ring for rx status" scheme may sound queer, but it makes
4016  * sense from a cache coherency perspective.  If only the host writes
4017  * to the buffer post rings, and only the chip writes to the rx status
4018  * rings, then cache lines never move beyond shared-modified state.
4019  * If both the host and chip were to write into the same ring, cache line
4020  * eviction could occur since both entities want it in an exclusive state.
4021  */
4022 static int tg3_rx(struct tg3 *tp, int budget)
4023 {
4024         u32 work_mask, rx_std_posted = 0;
4025         u32 sw_idx = tp->rx_rcb_ptr;
4026         u16 hw_idx;
4027         int received;
4028
4029         hw_idx = tp->hw_status->idx[0].rx_producer;
4030         /*
4031          * We need to order the read of hw_idx and the read of
4032          * the opaque cookie.
4033          */
4034         rmb();
4035         work_mask = 0;
4036         received = 0;
4037         while (sw_idx != hw_idx && budget > 0) {
4038                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
4039                 unsigned int len;
4040                 struct sk_buff *skb;
4041                 dma_addr_t dma_addr;
4042                 u32 opaque_key, desc_idx, *post_ptr;
4043
4044                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4045                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4046                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4047                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
4048                                                   mapping);
4049                         skb = tp->rx_std_buffers[desc_idx].skb;
4050                         post_ptr = &tp->rx_std_ptr;
4051                         rx_std_posted++;
4052                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4053                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
4054                                                   mapping);
4055                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
4056                         post_ptr = &tp->rx_jumbo_ptr;
4057                 }
4058                 else {
4059                         goto next_pkt_nopost;
4060                 }
4061
4062                 work_mask |= opaque_key;
4063
4064                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4065                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4066                 drop_it:
4067                         tg3_recycle_rx(tp, opaque_key,
4068                                        desc_idx, *post_ptr);
4069                 drop_it_no_recycle:
4070                         /* Other statistics kept track of by card. */
4071                         tp->net_stats.rx_dropped++;
4072                         goto next_pkt;
4073                 }
4074
4075                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
4076
4077                 if (len > RX_COPY_THRESHOLD
4078                         && tp->rx_offset == 2
4079                         /* rx_offset != 2 iff this is a 5701 card running
4080                          * in PCI-X mode [see tg3_get_invariants()] */
4081                 ) {
4082                         int skb_size;
4083
4084                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
4085                                                     desc_idx, *post_ptr);
4086                         if (skb_size < 0)
4087                                 goto drop_it;
4088
4089                         pci_unmap_single(tp->pdev, dma_addr,
4090                                          skb_size - tp->rx_offset,
4091                                          PCI_DMA_FROMDEVICE);
4092
4093                         skb_put(skb, len);
4094                 } else {
4095                         struct sk_buff *copy_skb;
4096
4097                         tg3_recycle_rx(tp, opaque_key,
4098                                        desc_idx, *post_ptr);
4099
4100                         copy_skb = netdev_alloc_skb(tp->dev, len + 2);
4101                         if (copy_skb == NULL)
4102                                 goto drop_it_no_recycle;
4103
4104                         skb_reserve(copy_skb, 2);
4105                         skb_put(copy_skb, len);
4106                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4107                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4108                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4109
4110                         /* We'll reuse the original ring buffer. */
4111                         skb = copy_skb;
4112                 }
4113
4114                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4115                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4116                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4117                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4118                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4119                 else
4120                         skb->ip_summed = CHECKSUM_NONE;
4121
4122                 skb->protocol = eth_type_trans(skb, tp->dev);
4123 #if TG3_VLAN_TAG_USED
4124                 if (tp->vlgrp != NULL &&
4125                     desc->type_flags & RXD_FLAG_VLAN) {
4126                         tg3_vlan_rx(tp, skb,
4127                                     desc->err_vlan & RXD_VLAN_MASK);
4128                 } else
4129 #endif
4130                         netif_receive_skb(skb);
4131
4132                 tp->dev->last_rx = jiffies;
4133                 received++;
4134                 budget--;
4135
4136 next_pkt:
4137                 (*post_ptr)++;
4138
4139                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4140                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4141
4142                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4143                                      TG3_64BIT_REG_LOW, idx);
4144                         work_mask &= ~RXD_OPAQUE_RING_STD;
4145                         rx_std_posted = 0;
4146                 }
4147 next_pkt_nopost:
4148                 sw_idx++;
4149                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4150
4151                 /* Refresh hw_idx to see if there is new work */
4152                 if (sw_idx == hw_idx) {
4153                         hw_idx = tp->hw_status->idx[0].rx_producer;
4154                         rmb();
4155                 }
4156         }
4157
4158         /* ACK the status ring. */
4159         tp->rx_rcb_ptr = sw_idx;
4160         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
4161
4162         /* Refill RX ring(s). */
4163         if (work_mask & RXD_OPAQUE_RING_STD) {
4164                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
4165                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4166                              sw_idx);
4167         }
4168         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4169                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
4170                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4171                              sw_idx);
4172         }
4173         mmiowb();
4174
4175         return received;
4176 }
4177
4178 static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
4179 {
4180         struct tg3_hw_status *sblk = tp->hw_status;
4181
4182         /* handle link change and other phy events */
4183         if (!(tp->tg3_flags &
4184               (TG3_FLAG_USE_LINKCHG_REG |
4185                TG3_FLAG_POLL_SERDES))) {
4186                 if (sblk->status & SD_STATUS_LINK_CHG) {
4187                         sblk->status = SD_STATUS_UPDATED |
4188                                 (sblk->status & ~SD_STATUS_LINK_CHG);
4189                         spin_lock(&tp->lock);
4190                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4191                                 tw32_f(MAC_STATUS,
4192                                      (MAC_STATUS_SYNC_CHANGED |
4193                                       MAC_STATUS_CFG_CHANGED |
4194                                       MAC_STATUS_MI_COMPLETION |
4195                                       MAC_STATUS_LNKSTATE_CHANGED));
4196                                 udelay(40);
4197                         } else
4198                                 tg3_setup_phy(tp, 0);
4199                         spin_unlock(&tp->lock);
4200                 }
4201         }
4202
4203         /* run TX completion thread */
4204         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
4205                 tg3_tx(tp);
4206                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4207                         return work_done;
4208         }
4209
4210         /* run RX thread, within the bounds set by NAPI.
4211          * All RX "locking" is done by ensuring outside
4212          * code synchronizes with tg3->napi.poll()
4213          */
4214         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
4215                 work_done += tg3_rx(tp, budget - work_done);
4216
4217         return work_done;
4218 }
4219
4220 static int tg3_poll(struct napi_struct *napi, int budget)
4221 {
4222         struct tg3 *tp = container_of(napi, struct tg3, napi);
4223         int work_done = 0;
4224         struct tg3_hw_status *sblk = tp->hw_status;
4225
4226         while (1) {
4227                 work_done = tg3_poll_work(tp, work_done, budget);
4228
4229                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4230                         goto tx_recovery;
4231
4232                 if (unlikely(work_done >= budget))
4233                         break;
4234
4235                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4236                         /* tp->last_tag is used in tg3_restart_ints() below
4237                          * to tell the hw how much work has been processed,
4238                          * so we must read it before checking for more work.
4239                          */
4240                         tp->last_tag = sblk->status_tag;
4241                         rmb();
4242                 } else
4243                         sblk->status &= ~SD_STATUS_UPDATED;
4244
4245                 if (likely(!tg3_has_work(tp))) {
4246                         netif_rx_complete(tp->dev, napi);
4247                         tg3_restart_ints(tp);
4248                         break;
4249                 }
4250         }
4251
4252         return work_done;
4253
4254 tx_recovery:
4255         /* work_done is guaranteed to be less than budget. */
4256         netif_rx_complete(tp->dev, napi);
4257         schedule_work(&tp->reset_task);
4258         return work_done;
4259 }
4260
4261 static void tg3_irq_quiesce(struct tg3 *tp)
4262 {
4263         BUG_ON(tp->irq_sync);
4264
4265         tp->irq_sync = 1;
4266         smp_mb();
4267
4268         synchronize_irq(tp->pdev->irq);
4269 }
4270
4271 static inline int tg3_irq_sync(struct tg3 *tp)
4272 {
4273         return tp->irq_sync;
4274 }
4275
4276 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4277  * If irq_sync is non-zero, then the IRQ handler must be synchronized
4278  * with as well.  Most of the time, this is not necessary except when
4279  * shutting down the device.
4280  */
4281 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4282 {
4283         spin_lock_bh(&tp->lock);
4284         if (irq_sync)
4285                 tg3_irq_quiesce(tp);
4286 }
4287
4288 static inline void tg3_full_unlock(struct tg3 *tp)
4289 {
4290         spin_unlock_bh(&tp->lock);
4291 }
4292
4293 /* One-shot MSI handler - Chip automatically disables interrupt
4294  * after sending MSI so driver doesn't have to do it.
4295  */
4296 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4297 {
4298         struct net_device *dev = dev_id;
4299         struct tg3 *tp = netdev_priv(dev);
4300
4301         prefetch(tp->hw_status);
4302         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4303
4304         if (likely(!tg3_irq_sync(tp)))
4305                 netif_rx_schedule(dev, &tp->napi);
4306
4307         return IRQ_HANDLED;
4308 }
4309
4310 /* MSI ISR - No need to check for interrupt sharing and no need to
4311  * flush status block and interrupt mailbox. PCI ordering rules
4312  * guarantee that MSI will arrive after the status block.
4313  */
4314 static irqreturn_t tg3_msi(int irq, void *dev_id)
4315 {
4316         struct net_device *dev = dev_id;
4317         struct tg3 *tp = netdev_priv(dev);
4318
4319         prefetch(tp->hw_status);
4320         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4321         /*
4322          * Writing any value to intr-mbox-0 clears PCI INTA# and
4323          * chip-internal interrupt pending events.
4324          * Writing non-zero to intr-mbox-0 additional tells the
4325          * NIC to stop sending us irqs, engaging "in-intr-handler"
4326          * event coalescing.
4327          */
4328         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4329         if (likely(!tg3_irq_sync(tp)))
4330                 netif_rx_schedule(dev, &tp->napi);
4331
4332         return IRQ_RETVAL(1);
4333 }
4334
4335 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4336 {
4337         struct net_device *dev = dev_id;
4338         struct tg3 *tp = netdev_priv(dev);
4339         struct tg3_hw_status *sblk = tp->hw_status;
4340         unsigned int handled = 1;
4341
4342         /* In INTx mode, it is possible for the interrupt to arrive at
4343          * the CPU before the status block posted prior to the interrupt.
4344          * Reading the PCI State register will confirm whether the
4345          * interrupt is ours and will flush the status block.
4346          */
4347         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4348                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4349                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4350                         handled = 0;
4351                         goto out;
4352                 }
4353         }
4354
4355         /*
4356          * Writing any value to intr-mbox-0 clears PCI INTA# and
4357          * chip-internal interrupt pending events.
4358          * Writing non-zero to intr-mbox-0 additional tells the
4359          * NIC to stop sending us irqs, engaging "in-intr-handler"
4360          * event coalescing.
4361          *
4362          * Flush the mailbox to de-assert the IRQ immediately to prevent
4363          * spurious interrupts.  The flush impacts performance but
4364          * excessive spurious interrupts can be worse in some cases.
4365          */
4366         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4367         if (tg3_irq_sync(tp))
4368                 goto out;
4369         sblk->status &= ~SD_STATUS_UPDATED;
4370         if (likely(tg3_has_work(tp))) {
4371                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4372                 netif_rx_schedule(dev, &tp->napi);
4373         } else {
4374                 /* No work, shared interrupt perhaps?  re-enable
4375                  * interrupts, and flush that PCI write
4376                  */
4377                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4378                                0x00000000);
4379         }
4380 out:
4381         return IRQ_RETVAL(handled);
4382 }
4383
4384 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4385 {
4386         struct net_device *dev = dev_id;
4387         struct tg3 *tp = netdev_priv(dev);
4388         struct tg3_hw_status *sblk = tp->hw_status;
4389         unsigned int handled = 1;
4390
4391         /* In INTx mode, it is possible for the interrupt to arrive at
4392          * the CPU before the status block posted prior to the interrupt.
4393          * Reading the PCI State register will confirm whether the
4394          * interrupt is ours and will flush the status block.
4395          */
4396         if (unlikely(sblk->status_tag == tp->last_tag)) {
4397                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4398                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4399                         handled = 0;
4400                         goto out;
4401                 }
4402         }
4403
4404         /*
4405          * writing any value to intr-mbox-0 clears PCI INTA# and
4406          * chip-internal interrupt pending events.
4407          * writing non-zero to intr-mbox-0 additional tells the
4408          * NIC to stop sending us irqs, engaging "in-intr-handler"
4409          * event coalescing.
4410          *
4411          * Flush the mailbox to de-assert the IRQ immediately to prevent
4412          * spurious interrupts.  The flush impacts performance but
4413          * excessive spurious interrupts can be worse in some cases.
4414          */
4415         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4416         if (tg3_irq_sync(tp))
4417                 goto out;
4418         if (netif_rx_schedule_prep(dev, &tp->napi)) {
4419                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4420                 /* Update last_tag to mark that this status has been
4421                  * seen. Because interrupt may be shared, we may be
4422                  * racing with tg3_poll(), so only update last_tag
4423                  * if tg3_poll() is not scheduled.
4424                  */
4425                 tp->last_tag = sblk->status_tag;
4426                 __netif_rx_schedule(dev, &tp->napi);
4427         }
4428 out:
4429         return IRQ_RETVAL(handled);
4430 }
4431
4432 /* ISR for interrupt test */
4433 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4434 {
4435         struct net_device *dev = dev_id;
4436         struct tg3 *tp = netdev_priv(dev);
4437         struct tg3_hw_status *sblk = tp->hw_status;
4438
4439         if ((sblk->status & SD_STATUS_UPDATED) ||
4440             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4441                 tg3_disable_ints(tp);
4442                 return IRQ_RETVAL(1);
4443         }
4444         return IRQ_RETVAL(0);
4445 }
4446
4447 static int tg3_init_hw(struct tg3 *, int);
4448 static int tg3_halt(struct tg3 *, int, int);
4449
4450 /* Restart hardware after configuration changes, self-test, etc.
4451  * Invoked with tp->lock held.
4452  */
4453 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4454         __releases(tp->lock)
4455         __acquires(tp->lock)
4456 {
4457         int err;
4458
4459         err = tg3_init_hw(tp, reset_phy);
4460         if (err) {
4461                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4462                        "aborting.\n", tp->dev->name);
4463                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4464                 tg3_full_unlock(tp);
4465                 del_timer_sync(&tp->timer);
4466                 tp->irq_sync = 0;
4467                 napi_enable(&tp->napi);
4468                 dev_close(tp->dev);
4469                 tg3_full_lock(tp, 0);
4470         }
4471         return err;
4472 }
4473
4474 #ifdef CONFIG_NET_POLL_CONTROLLER
4475 static void tg3_poll_controller(struct net_device *dev)
4476 {
4477         struct tg3 *tp = netdev_priv(dev);
4478
4479         tg3_interrupt(tp->pdev->irq, dev);
4480 }
4481 #endif
4482
4483 static void tg3_reset_task(struct work_struct *work)
4484 {
4485         struct tg3 *tp = container_of(work, struct tg3, reset_task);
4486         int err;
4487         unsigned int restart_timer;
4488
4489         tg3_full_lock(tp, 0);
4490
4491         if (!netif_running(tp->dev)) {
4492                 tg3_full_unlock(tp);
4493                 return;
4494         }
4495
4496         tg3_full_unlock(tp);
4497
4498         tg3_phy_stop(tp);
4499
4500         tg3_netif_stop(tp);
4501
4502         tg3_full_lock(tp, 1);
4503
4504         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4505         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4506
4507         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4508                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4509                 tp->write32_rx_mbox = tg3_write_flush_reg32;
4510                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4511                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4512         }
4513
4514         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
4515         err = tg3_init_hw(tp, 1);
4516         if (err)
4517                 goto out;
4518
4519         tg3_netif_start(tp);
4520
4521         if (restart_timer)
4522                 mod_timer(&tp->timer, jiffies + 1);
4523
4524 out:
4525         tg3_full_unlock(tp);
4526
4527         if (!err)
4528                 tg3_phy_start(tp);
4529 }
4530
4531 static void tg3_dump_short_state(struct tg3 *tp)
4532 {
4533         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
4534                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
4535         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
4536                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
4537 }
4538
4539 static void tg3_tx_timeout(struct net_device *dev)
4540 {
4541         struct tg3 *tp = netdev_priv(dev);
4542
4543         if (netif_msg_tx_err(tp)) {
4544                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
4545                        dev->name);
4546                 tg3_dump_short_state(tp);
4547         }
4548
4549         schedule_work(&tp->reset_task);
4550 }
4551
4552 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
4553 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
4554 {
4555         u32 base = (u32) mapping & 0xffffffff;
4556
4557         return ((base > 0xffffdcc0) &&
4558                 (base + len + 8 < base));
4559 }
4560
4561 /* Test for DMA addresses > 40-bit */
4562 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
4563                                           int len)
4564 {
4565 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
4566         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
4567                 return (((u64) mapping + len) > DMA_40BIT_MASK);
4568         return 0;
4569 #else
4570         return 0;
4571 #endif
4572 }
4573
4574 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
4575
4576 /* Workaround 4GB and 40-bit hardware DMA bugs. */
4577 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
4578                                        u32 last_plus_one, u32 *start,
4579                                        u32 base_flags, u32 mss)
4580 {
4581         struct sk_buff *new_skb;
4582         dma_addr_t new_addr = 0;
4583         u32 entry = *start;
4584         int i, ret = 0;
4585
4586         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
4587                 new_skb = skb_copy(skb, GFP_ATOMIC);
4588         else {
4589                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
4590
4591                 new_skb = skb_copy_expand(skb,
4592                                           skb_headroom(skb) + more_headroom,
4593                                           skb_tailroom(skb), GFP_ATOMIC);
4594         }
4595
4596         if (!new_skb) {
4597                 ret = -1;
4598         } else {
4599                 /* New SKB is guaranteed to be linear. */
4600                 entry = *start;
4601                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
4602                                           PCI_DMA_TODEVICE);
4603                 /* Make sure new skb does not cross any 4G boundaries.
4604                  * Drop the packet if it does.
4605                  */
4606                 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
4607                         ret = -1;
4608                         dev_kfree_skb(new_skb);
4609                         new_skb = NULL;
4610                 } else {
4611                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
4612                                     base_flags, 1 | (mss << 1));
4613                         *start = NEXT_TX(entry);
4614                 }
4615         }
4616
4617         /* Now clean up the sw ring entries. */
4618         i = 0;
4619         while (entry != last_plus_one) {
4620                 int len;
4621
4622                 if (i == 0)
4623                         len = skb_headlen(skb);
4624                 else
4625                         len = skb_shinfo(skb)->frags[i-1].size;
4626                 pci_unmap_single(tp->pdev,
4627                                  pci_unmap_addr(&tp->tx_buffers[entry], mapping),
4628                                  len, PCI_DMA_TODEVICE);
4629                 if (i == 0) {
4630                         tp->tx_buffers[entry].skb = new_skb;
4631                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
4632                 } else {
4633                         tp->tx_buffers[entry].skb = NULL;
4634                 }
4635                 entry = NEXT_TX(entry);
4636                 i++;
4637         }
4638
4639         dev_kfree_skb(skb);
4640
4641         return ret;
4642 }
4643
4644 static void tg3_set_txd(struct tg3 *tp, int entry,
4645                         dma_addr_t mapping, int len, u32 flags,
4646                         u32 mss_and_is_end)
4647 {
4648         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
4649         int is_end = (mss_and_is_end & 0x1);
4650         u32 mss = (mss_and_is_end >> 1);
4651         u32 vlan_tag = 0;
4652
4653         if (is_end)
4654                 flags |= TXD_FLAG_END;
4655         if (flags & TXD_FLAG_VLAN) {
4656                 vlan_tag = flags >> 16;
4657                 flags &= 0xffff;
4658         }
4659         vlan_tag |= (mss << TXD_MSS_SHIFT);
4660
4661         txd->addr_hi = ((u64) mapping >> 32);
4662         txd->addr_lo = ((u64) mapping & 0xffffffff);
4663         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
4664         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
4665 }
4666
4667 /* hard_start_xmit for devices that don't have any bugs and
4668  * support TG3_FLG2_HW_TSO_2 only.
4669  */
4670 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
4671 {
4672         struct tg3 *tp = netdev_priv(dev);
4673         dma_addr_t mapping;
4674         u32 len, entry, base_flags, mss;
4675
4676         len = skb_headlen(skb);
4677
4678         /* We are running in BH disabled context with netif_tx_lock
4679          * and TX reclaim runs via tp->napi.poll inside of a software
4680          * interrupt.  Furthermore, IRQ processing runs lockless so we have
4681          * no IRQ context deadlocks to worry about either.  Rejoice!
4682          */
4683         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4684                 if (!netif_queue_stopped(dev)) {
4685                         netif_stop_queue(dev);
4686
4687                         /* This is a hard error, log it. */
4688                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4689                                "queue awake!\n", dev->name);
4690                 }
4691                 return NETDEV_TX_BUSY;
4692         }
4693
4694         entry = tp->tx_prod;
4695         base_flags = 0;
4696         mss = 0;
4697         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4698                 int tcp_opt_len, ip_tcp_len;
4699
4700                 if (skb_header_cloned(skb) &&
4701                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4702                         dev_kfree_skb(skb);
4703                         goto out_unlock;
4704                 }
4705
4706                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
4707                         mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
4708                 else {
4709                         struct iphdr *iph = ip_hdr(skb);
4710
4711                         tcp_opt_len = tcp_optlen(skb);
4712                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4713
4714                         iph->check = 0;
4715                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
4716                         mss |= (ip_tcp_len + tcp_opt_len) << 9;
4717                 }
4718
4719                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4720                                TXD_FLAG_CPU_POST_DMA);
4721
4722                 tcp_hdr(skb)->check = 0;
4723
4724         }
4725         else if (skb->ip_summed == CHECKSUM_PARTIAL)
4726                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4727 #if TG3_VLAN_TAG_USED
4728         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4729                 base_flags |= (TXD_FLAG_VLAN |
4730                                (vlan_tx_tag_get(skb) << 16));
4731 #endif
4732
4733         /* Queue skb data, a.k.a. the main skb fragment. */
4734         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4735
4736         tp->tx_buffers[entry].skb = skb;
4737         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4738
4739         tg3_set_txd(tp, entry, mapping, len, base_flags,
4740                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4741
4742         entry = NEXT_TX(entry);
4743
4744         /* Now loop through additional data fragments, and queue them. */
4745         if (skb_shinfo(skb)->nr_frags > 0) {
4746                 unsigned int i, last;
4747
4748                 last = skb_shinfo(skb)->nr_frags - 1;
4749                 for (i = 0; i <= last; i++) {
4750                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4751
4752                         len = frag->size;
4753                         mapping = pci_map_page(tp->pdev,
4754                                                frag->page,
4755                                                frag->page_offset,
4756                                                len, PCI_DMA_TODEVICE);
4757
4758                         tp->tx_buffers[entry].skb = NULL;
4759                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4760
4761                         tg3_set_txd(tp, entry, mapping, len,
4762                                     base_flags, (i == last) | (mss << 1));
4763
4764                         entry = NEXT_TX(entry);
4765                 }
4766         }
4767
4768         /* Packets are ready, update Tx producer idx local and on card. */
4769         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4770
4771         tp->tx_prod = entry;
4772         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4773                 netif_stop_queue(dev);
4774                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4775                         netif_wake_queue(tp->dev);
4776         }
4777
4778 out_unlock:
4779         mmiowb();
4780
4781         dev->trans_start = jiffies;
4782
4783         return NETDEV_TX_OK;
4784 }
4785
4786 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
4787
4788 /* Use GSO to workaround a rare TSO bug that may be triggered when the
4789  * TSO header is greater than 80 bytes.
4790  */
4791 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
4792 {
4793         struct sk_buff *segs, *nskb;
4794
4795         /* Estimate the number of fragments in the worst case */
4796         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
4797                 netif_stop_queue(tp->dev);
4798                 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
4799                         return NETDEV_TX_BUSY;
4800
4801                 netif_wake_queue(tp->dev);
4802         }
4803
4804         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
4805         if (IS_ERR(segs))
4806                 goto tg3_tso_bug_end;
4807
4808         do {
4809                 nskb = segs;
4810                 segs = segs->next;
4811                 nskb->next = NULL;
4812                 tg3_start_xmit_dma_bug(nskb, tp->dev);
4813         } while (segs);
4814
4815 tg3_tso_bug_end:
4816         dev_kfree_skb(skb);
4817
4818         return NETDEV_TX_OK;
4819 }
4820
4821 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
4822  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
4823  */
4824 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
4825 {
4826         struct tg3 *tp = netdev_priv(dev);
4827         dma_addr_t mapping;
4828         u32 len, entry, base_flags, mss;
4829         int would_hit_hwbug;
4830
4831         len = skb_headlen(skb);
4832
4833         /* We are running in BH disabled context with netif_tx_lock
4834          * and TX reclaim runs via tp->napi.poll inside of a software
4835          * interrupt.  Furthermore, IRQ processing runs lockless so we have
4836          * no IRQ context deadlocks to worry about either.  Rejoice!
4837          */
4838         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4839                 if (!netif_queue_stopped(dev)) {
4840                         netif_stop_queue(dev);
4841
4842                         /* This is a hard error, log it. */
4843                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4844                                "queue awake!\n", dev->name);
4845                 }
4846                 return NETDEV_TX_BUSY;
4847         }
4848
4849         entry = tp->tx_prod;
4850         base_flags = 0;
4851         if (skb->ip_summed == CHECKSUM_PARTIAL)
4852                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4853         mss = 0;
4854         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4855                 struct iphdr *iph;
4856                 int tcp_opt_len, ip_tcp_len, hdr_len;
4857
4858                 if (skb_header_cloned(skb) &&
4859                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4860                         dev_kfree_skb(skb);
4861                         goto out_unlock;
4862                 }
4863
4864                 tcp_opt_len = tcp_optlen(skb);
4865                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4866
4867                 hdr_len = ip_tcp_len + tcp_opt_len;
4868                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4869                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
4870                         return (tg3_tso_bug(tp, skb));
4871
4872                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4873                                TXD_FLAG_CPU_POST_DMA);
4874
4875                 iph = ip_hdr(skb);
4876                 iph->check = 0;
4877                 iph->tot_len = htons(mss + hdr_len);
4878                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4879                         tcp_hdr(skb)->check = 0;
4880                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4881                 } else
4882                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4883                                                                  iph->daddr, 0,
4884                                                                  IPPROTO_TCP,
4885                                                                  0);
4886
4887                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4888                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4889                         if (tcp_opt_len || iph->ihl > 5) {
4890                                 int tsflags;
4891
4892                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4893                                 mss |= (tsflags << 11);
4894                         }
4895                 } else {
4896                         if (tcp_opt_len || iph->ihl > 5) {
4897                                 int tsflags;
4898
4899                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4900                                 base_flags |= tsflags << 12;
4901                         }
4902                 }
4903         }
4904 #if TG3_VLAN_TAG_USED
4905         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4906                 base_flags |= (TXD_FLAG_VLAN |
4907                                (vlan_tx_tag_get(skb) << 16));
4908 #endif
4909
4910         /* Queue skb data, a.k.a. the main skb fragment. */
4911         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4912
4913         tp->tx_buffers[entry].skb = skb;
4914         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4915
4916         would_hit_hwbug = 0;
4917
4918         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
4919                 would_hit_hwbug = 1;
4920         else if (tg3_4g_overflow_test(mapping, len))
4921                 would_hit_hwbug = 1;
4922
4923         tg3_set_txd(tp, entry, mapping, len, base_flags,
4924                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4925
4926         entry = NEXT_TX(entry);
4927
4928         /* Now loop through additional data fragments, and queue them. */
4929         if (skb_shinfo(skb)->nr_frags > 0) {
4930                 unsigned int i, last;
4931
4932                 last = skb_shinfo(skb)->nr_frags - 1;
4933                 for (i = 0; i <= last; i++) {
4934                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4935
4936                         len = frag->size;
4937                         mapping = pci_map_page(tp->pdev,
4938                                                frag->page,
4939                                                frag->page_offset,
4940                                                len, PCI_DMA_TODEVICE);
4941
4942                         tp->tx_buffers[entry].skb = NULL;
4943                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4944
4945                         if (tg3_4g_overflow_test(mapping, len))
4946                                 would_hit_hwbug = 1;
4947
4948                         if (tg3_40bit_overflow_test(tp, mapping, len))
4949                                 would_hit_hwbug = 1;
4950
4951                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4952                                 tg3_set_txd(tp, entry, mapping, len,
4953                                             base_flags, (i == last)|(mss << 1));
4954                         else
4955                                 tg3_set_txd(tp, entry, mapping, len,
4956                                             base_flags, (i == last));
4957
4958                         entry = NEXT_TX(entry);
4959                 }
4960         }
4961
4962         if (would_hit_hwbug) {
4963                 u32 last_plus_one = entry;
4964                 u32 start;
4965
4966                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4967                 start &= (TG3_TX_RING_SIZE - 1);
4968
4969                 /* If the workaround fails due to memory/mapping
4970                  * failure, silently drop this packet.
4971                  */
4972                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
4973                                                 &start, base_flags, mss))
4974                         goto out_unlock;
4975
4976                 entry = start;
4977         }
4978
4979         /* Packets are ready, update Tx producer idx local and on card. */
4980         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4981
4982         tp->tx_prod = entry;
4983         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4984                 netif_stop_queue(dev);
4985                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4986                         netif_wake_queue(tp->dev);
4987         }
4988
4989 out_unlock:
4990         mmiowb();
4991
4992         dev->trans_start = jiffies;
4993
4994         return NETDEV_TX_OK;
4995 }
4996
4997 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4998                                int new_mtu)
4999 {
5000         dev->mtu = new_mtu;
5001
5002         if (new_mtu > ETH_DATA_LEN) {
5003                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5004                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5005                         ethtool_op_set_tso(dev, 0);
5006                 }
5007                 else
5008                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5009         } else {
5010                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5011                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5012                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5013         }
5014 }
5015
5016 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5017 {
5018         struct tg3 *tp = netdev_priv(dev);
5019         int err;
5020
5021         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5022                 return -EINVAL;
5023
5024         if (!netif_running(dev)) {
5025                 /* We'll just catch it later when the
5026                  * device is up'd.
5027                  */
5028                 tg3_set_mtu(dev, tp, new_mtu);
5029                 return 0;
5030         }
5031
5032         tg3_phy_stop(tp);
5033
5034         tg3_netif_stop(tp);
5035
5036         tg3_full_lock(tp, 1);
5037
5038         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5039
5040         tg3_set_mtu(dev, tp, new_mtu);
5041
5042         err = tg3_restart_hw(tp, 0);
5043
5044         if (!err)
5045                 tg3_netif_start(tp);
5046
5047         tg3_full_unlock(tp);
5048
5049         if (!err)
5050                 tg3_phy_start(tp);
5051
5052         return err;
5053 }
5054
5055 /* Free up pending packets in all rx/tx rings.
5056  *
5057  * The chip has been shut down and the driver detached from
5058  * the networking, so no interrupts or new tx packets will
5059  * end up in the driver.  tp->{tx,}lock is not held and we are not
5060  * in an interrupt context and thus may sleep.
5061  */
5062 static void tg3_free_rings(struct tg3 *tp)
5063 {
5064         struct ring_info *rxp;
5065         int i;
5066
5067         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5068                 rxp = &tp->rx_std_buffers[i];
5069
5070                 if (rxp->skb == NULL)
5071                         continue;
5072                 pci_unmap_single(tp->pdev,
5073                                  pci_unmap_addr(rxp, mapping),
5074                                  tp->rx_pkt_buf_sz - tp->rx_offset,
5075                                  PCI_DMA_FROMDEVICE);
5076                 dev_kfree_skb_any(rxp->skb);
5077                 rxp->skb = NULL;
5078         }
5079
5080         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5081                 rxp = &tp->rx_jumbo_buffers[i];
5082
5083                 if (rxp->skb == NULL)
5084                         continue;
5085                 pci_unmap_single(tp->pdev,
5086                                  pci_unmap_addr(rxp, mapping),
5087                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
5088                                  PCI_DMA_FROMDEVICE);
5089                 dev_kfree_skb_any(rxp->skb);
5090                 rxp->skb = NULL;
5091         }
5092
5093         for (i = 0; i < TG3_TX_RING_SIZE; ) {
5094                 struct tx_ring_info *txp;
5095                 struct sk_buff *skb;
5096                 int j;
5097
5098                 txp = &tp->tx_buffers[i];
5099                 skb = txp->skb;
5100
5101                 if (skb == NULL) {
5102                         i++;
5103                         continue;
5104                 }
5105
5106                 pci_unmap_single(tp->pdev,
5107                                  pci_unmap_addr(txp, mapping),
5108                                  skb_headlen(skb),
5109                                  PCI_DMA_TODEVICE);
5110                 txp->skb = NULL;
5111
5112                 i++;
5113
5114                 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
5115                         txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
5116                         pci_unmap_page(tp->pdev,
5117                                        pci_unmap_addr(txp, mapping),
5118                                        skb_shinfo(skb)->frags[j].size,
5119                                        PCI_DMA_TODEVICE);
5120                         i++;
5121                 }
5122
5123                 dev_kfree_skb_any(skb);
5124         }
5125 }
5126
5127 /* Initialize tx/rx rings for packet processing.
5128  *
5129  * The chip has been shut down and the driver detached from
5130  * the networking, so no interrupts or new tx packets will
5131  * end up in the driver.  tp->{tx,}lock are held and thus
5132  * we may not sleep.
5133  */
5134 static int tg3_init_rings(struct tg3 *tp)
5135 {
5136         u32 i;
5137
5138         /* Free up all the SKBs. */
5139         tg3_free_rings(tp);
5140
5141         /* Zero out all descriptors. */
5142         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
5143         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
5144         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5145         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
5146
5147         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
5148         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5149             (tp->dev->mtu > ETH_DATA_LEN))
5150                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
5151
5152         /* Initialize invariants of the rings, we only set this
5153          * stuff once.  This works because the card does not
5154          * write into the rx buffer posting rings.
5155          */
5156         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5157                 struct tg3_rx_buffer_desc *rxd;
5158
5159                 rxd = &tp->rx_std[i];
5160                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
5161                         << RXD_LEN_SHIFT;
5162                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5163                 rxd->opaque = (RXD_OPAQUE_RING_STD |
5164                                (i << RXD_OPAQUE_INDEX_SHIFT));
5165         }
5166
5167         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5168                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5169                         struct tg3_rx_buffer_desc *rxd;
5170
5171                         rxd = &tp->rx_jumbo[i];
5172                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
5173                                 << RXD_LEN_SHIFT;
5174                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5175                                 RXD_FLAG_JUMBO;
5176                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5177                                (i << RXD_OPAQUE_INDEX_SHIFT));
5178                 }
5179         }
5180
5181         /* Now allocate fresh SKBs for each rx ring. */
5182         for (i = 0; i < tp->rx_pending; i++) {
5183                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5184                         printk(KERN_WARNING PFX
5185                                "%s: Using a smaller RX standard ring, "
5186                                "only %d out of %d buffers were allocated "
5187                                "successfully.\n",
5188                                tp->dev->name, i, tp->rx_pending);
5189                         if (i == 0)
5190                                 return -ENOMEM;
5191                         tp->rx_pending = i;
5192                         break;
5193                 }
5194         }
5195
5196         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5197                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5198                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
5199                                              -1, i) < 0) {
5200                                 printk(KERN_WARNING PFX
5201                                        "%s: Using a smaller RX jumbo ring, "
5202                                        "only %d out of %d buffers were "
5203                                        "allocated successfully.\n",
5204                                        tp->dev->name, i, tp->rx_jumbo_pending);
5205                                 if (i == 0) {
5206                                         tg3_free_rings(tp);
5207                                         return -ENOMEM;
5208                                 }
5209                                 tp->rx_jumbo_pending = i;
5210                                 break;
5211                         }
5212                 }
5213         }
5214         return 0;
5215 }
5216
5217 /*
5218  * Must not be invoked with interrupt sources disabled and
5219  * the hardware shutdown down.
5220  */
5221 static void tg3_free_consistent(struct tg3 *tp)
5222 {
5223         kfree(tp->rx_std_buffers);
5224         tp->rx_std_buffers = NULL;
5225         if (tp->rx_std) {
5226                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5227                                     tp->rx_std, tp->rx_std_mapping);
5228                 tp->rx_std = NULL;
5229         }
5230         if (tp->rx_jumbo) {
5231                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5232                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
5233                 tp->rx_jumbo = NULL;
5234         }
5235         if (tp->rx_rcb) {
5236                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5237                                     tp->rx_rcb, tp->rx_rcb_mapping);
5238                 tp->rx_rcb = NULL;
5239         }
5240         if (tp->tx_ring) {
5241                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5242                         tp->tx_ring, tp->tx_desc_mapping);
5243                 tp->tx_ring = NULL;
5244         }
5245         if (tp->hw_status) {
5246                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5247                                     tp->hw_status, tp->status_mapping);
5248                 tp->hw_status = NULL;
5249         }
5250         if (tp->hw_stats) {
5251                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5252                                     tp->hw_stats, tp->stats_mapping);
5253                 tp->hw_stats = NULL;
5254         }
5255 }
5256
5257 /*
5258  * Must not be invoked with interrupt sources disabled and
5259  * the hardware shutdown down.  Can sleep.
5260  */
5261 static int tg3_alloc_consistent(struct tg3 *tp)
5262 {
5263         tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
5264                                       (TG3_RX_RING_SIZE +
5265                                        TG3_RX_JUMBO_RING_SIZE)) +
5266                                      (sizeof(struct tx_ring_info) *
5267                                       TG3_TX_RING_SIZE),
5268                                      GFP_KERNEL);
5269         if (!tp->rx_std_buffers)
5270                 return -ENOMEM;
5271
5272         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
5273         tp->tx_buffers = (struct tx_ring_info *)
5274                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
5275
5276         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5277                                           &tp->rx_std_mapping);
5278         if (!tp->rx_std)
5279                 goto err_out;
5280
5281         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5282                                             &tp->rx_jumbo_mapping);
5283
5284         if (!tp->rx_jumbo)
5285                 goto err_out;
5286
5287         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5288                                           &tp->rx_rcb_mapping);
5289         if (!tp->rx_rcb)
5290                 goto err_out;
5291
5292         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5293                                            &tp->tx_desc_mapping);
5294         if (!tp->tx_ring)
5295                 goto err_out;
5296
5297         tp->hw_status = pci_alloc_consistent(tp->pdev,
5298                                              TG3_HW_STATUS_SIZE,
5299                                              &tp->status_mapping);
5300         if (!tp->hw_status)
5301                 goto err_out;
5302
5303         tp->hw_stats = pci_alloc_consistent(tp->pdev,
5304                                             sizeof(struct tg3_hw_stats),
5305                                             &tp->stats_mapping);
5306         if (!tp->hw_stats)
5307                 goto err_out;
5308
5309         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5310         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5311
5312         return 0;
5313
5314 err_out:
5315         tg3_free_consistent(tp);
5316         return -ENOMEM;
5317 }
5318
5319 #define MAX_WAIT_CNT 1000
5320
5321 /* To stop a block, clear the enable bit and poll till it
5322  * clears.  tp->lock is held.
5323  */
5324 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
5325 {
5326         unsigned int i;
5327         u32 val;
5328
5329         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5330                 switch (ofs) {
5331                 case RCVLSC_MODE:
5332                 case DMAC_MODE:
5333                 case MBFREE_MODE:
5334                 case BUFMGR_MODE:
5335                 case MEMARB_MODE:
5336                         /* We can't enable/disable these bits of the
5337                          * 5705/5750, just say success.
5338                          */
5339                         return 0;
5340
5341                 default:
5342                         break;
5343                 }
5344         }
5345
5346         val = tr32(ofs);
5347         val &= ~enable_bit;
5348         tw32_f(ofs, val);
5349
5350         for (i = 0; i < MAX_WAIT_CNT; i++) {
5351                 udelay(100);
5352                 val = tr32(ofs);
5353                 if ((val & enable_bit) == 0)
5354                         break;
5355         }
5356
5357         if (i == MAX_WAIT_CNT && !silent) {
5358                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5359                        "ofs=%lx enable_bit=%x\n",
5360                        ofs, enable_bit);
5361                 return -ENODEV;
5362         }
5363
5364         return 0;
5365 }
5366
5367 /* tp->lock is held. */
5368 static int tg3_abort_hw(struct tg3 *tp, int silent)
5369 {
5370         int i, err;
5371
5372         tg3_disable_ints(tp);
5373
5374         tp->rx_mode &= ~RX_MODE_ENABLE;
5375         tw32_f(MAC_RX_MODE, tp->rx_mode);
5376         udelay(10);
5377
5378         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5379         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5380         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5381         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5382         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5383         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5384
5385         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5386         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5387         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5388         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5389         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5390         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5391         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
5392
5393         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5394         tw32_f(MAC_MODE, tp->mac_mode);
5395         udelay(40);
5396
5397         tp->tx_mode &= ~TX_MODE_ENABLE;
5398         tw32_f(MAC_TX_MODE, tp->tx_mode);
5399
5400         for (i = 0; i < MAX_WAIT_CNT; i++) {
5401                 udelay(100);
5402                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5403                         break;
5404         }
5405         if (i >= MAX_WAIT_CNT) {
5406                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5407                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5408                        tp->dev->name, tr32(MAC_TX_MODE));
5409                 err |= -ENODEV;
5410         }
5411
5412         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
5413         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5414         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
5415
5416         tw32(FTQ_RESET, 0xffffffff);
5417         tw32(FTQ_RESET, 0x00000000);
5418
5419         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5420         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
5421
5422         if (tp->hw_status)
5423                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5424         if (tp->hw_stats)
5425                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5426
5427         return err;
5428 }
5429
5430 /* tp->lock is held. */
5431 static int tg3_nvram_lock(struct tg3 *tp)
5432 {
5433         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
5434                 int i;
5435
5436                 if (tp->nvram_lock_cnt == 0) {
5437                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
5438                         for (i = 0; i < 8000; i++) {
5439                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
5440                                         break;
5441                                 udelay(20);
5442                         }
5443                         if (i == 8000) {
5444                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
5445                                 return -ENODEV;
5446                         }
5447                 }
5448                 tp->nvram_lock_cnt++;
5449         }
5450         return 0;
5451 }
5452
5453 /* tp->lock is held. */
5454 static void tg3_nvram_unlock(struct tg3 *tp)
5455 {
5456         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
5457                 if (tp->nvram_lock_cnt > 0)
5458                         tp->nvram_lock_cnt--;
5459                 if (tp->nvram_lock_cnt == 0)
5460                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
5461         }
5462 }
5463
5464 /* tp->lock is held. */
5465 static void tg3_enable_nvram_access(struct tg3 *tp)
5466 {
5467         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5468             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5469                 u32 nvaccess = tr32(NVRAM_ACCESS);
5470
5471                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
5472         }
5473 }
5474
5475 /* tp->lock is held. */
5476 static void tg3_disable_nvram_access(struct tg3 *tp)
5477 {
5478         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5479             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5480                 u32 nvaccess = tr32(NVRAM_ACCESS);
5481
5482                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
5483         }
5484 }
5485
5486 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5487 {
5488         int i;
5489         u32 apedata;
5490
5491         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5492         if (apedata != APE_SEG_SIG_MAGIC)
5493                 return;
5494
5495         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
5496         if (apedata != APE_FW_STATUS_READY)
5497                 return;
5498
5499         /* Wait for up to 1 millisecond for APE to service previous event. */
5500         for (i = 0; i < 10; i++) {
5501                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5502                         return;
5503
5504                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5505
5506                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5507                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5508                                         event | APE_EVENT_STATUS_EVENT_PENDING);
5509
5510                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5511
5512                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5513                         break;
5514
5515                 udelay(100);
5516         }
5517
5518         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5519                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5520 }
5521
5522 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5523 {
5524         u32 event;
5525         u32 apedata;
5526
5527         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5528                 return;
5529
5530         switch (kind) {
5531                 case RESET_KIND_INIT:
5532                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5533                                         APE_HOST_SEG_SIG_MAGIC);
5534                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5535                                         APE_HOST_SEG_LEN_MAGIC);
5536                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5537                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5538                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
5539                                         APE_HOST_DRIVER_ID_MAGIC);
5540                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
5541                                         APE_HOST_BEHAV_NO_PHYLOCK);
5542
5543                         event = APE_EVENT_STATUS_STATE_START;
5544                         break;
5545                 case RESET_KIND_SHUTDOWN:
5546                         event = APE_EVENT_STATUS_STATE_UNLOAD;
5547                         break;
5548                 case RESET_KIND_SUSPEND:
5549                         event = APE_EVENT_STATUS_STATE_SUSPEND;
5550                         break;
5551                 default:
5552                         return;
5553         }
5554
5555         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
5556
5557         tg3_ape_send_event(tp, event);
5558 }
5559
5560 /* tp->lock is held. */
5561 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
5562 {
5563         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
5564                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
5565
5566         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5567                 switch (kind) {
5568                 case RESET_KIND_INIT:
5569                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5570                                       DRV_STATE_START);
5571                         break;
5572
5573                 case RESET_KIND_SHUTDOWN:
5574                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5575                                       DRV_STATE_UNLOAD);
5576                         break;
5577
5578                 case RESET_KIND_SUSPEND:
5579                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5580                                       DRV_STATE_SUSPEND);
5581                         break;
5582
5583                 default:
5584                         break;
5585                 }
5586         }
5587
5588         if (kind == RESET_KIND_INIT ||
5589             kind == RESET_KIND_SUSPEND)
5590                 tg3_ape_driver_state_change(tp, kind);
5591 }
5592
5593 /* tp->lock is held. */
5594 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
5595 {
5596         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5597                 switch (kind) {
5598                 case RESET_KIND_INIT:
5599                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5600                                       DRV_STATE_START_DONE);
5601                         break;
5602
5603                 case RESET_KIND_SHUTDOWN:
5604                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5605                                       DRV_STATE_UNLOAD_DONE);
5606                         break;
5607
5608                 default:
5609                         break;
5610                 }
5611         }
5612
5613         if (kind == RESET_KIND_SHUTDOWN)
5614                 tg3_ape_driver_state_change(tp, kind);
5615 }
5616
5617 /* tp->lock is held. */
5618 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
5619 {
5620         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5621                 switch (kind) {
5622                 case RESET_KIND_INIT:
5623                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5624                                       DRV_STATE_START);
5625                         break;
5626
5627                 case RESET_KIND_SHUTDOWN:
5628                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5629                                       DRV_STATE_UNLOAD);
5630                         break;
5631
5632                 case RESET_KIND_SUSPEND:
5633                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5634                                       DRV_STATE_SUSPEND);
5635                         break;
5636
5637                 default:
5638                         break;
5639                 }
5640         }
5641 }
5642
5643 static int tg3_poll_fw(struct tg3 *tp)
5644 {
5645         int i;
5646         u32 val;
5647
5648         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5649                 /* Wait up to 20ms for init done. */
5650                 for (i = 0; i < 200; i++) {
5651                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
5652                                 return 0;
5653                         udelay(100);
5654                 }
5655                 return -ENODEV;
5656         }
5657
5658         /* Wait for firmware initialization to complete. */
5659         for (i = 0; i < 100000; i++) {
5660                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
5661                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
5662                         break;
5663                 udelay(10);
5664         }
5665
5666         /* Chip might not be fitted with firmware.  Some Sun onboard
5667          * parts are configured like that.  So don't signal the timeout
5668          * of the above loop as an error, but do report the lack of
5669          * running firmware once.
5670          */
5671         if (i >= 100000 &&
5672             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
5673                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
5674
5675                 printk(KERN_INFO PFX "%s: No firmware running.\n",
5676                        tp->dev->name);
5677         }
5678
5679         return 0;
5680 }
5681
5682 /* Save PCI command register before chip reset */
5683 static void tg3_save_pci_state(struct tg3 *tp)
5684 {
5685         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
5686 }
5687
5688 /* Restore PCI state after chip reset */
5689 static void tg3_restore_pci_state(struct tg3 *tp)
5690 {
5691         u32 val;
5692
5693         /* Re-enable indirect register accesses. */
5694         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
5695                                tp->misc_host_ctrl);
5696
5697         /* Set MAX PCI retry to zero. */
5698         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
5699         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5700             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
5701                 val |= PCISTATE_RETRY_SAME_DMA;
5702         /* Allow reads and writes to the APE register and memory space. */
5703         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
5704                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
5705                        PCISTATE_ALLOW_APE_SHMEM_WR;
5706         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
5707
5708         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
5709
5710         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
5711                 pcie_set_readrq(tp->pdev, 4096);
5712         else {
5713                 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
5714                                       tp->pci_cacheline_sz);
5715                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
5716                                       tp->pci_lat_timer);
5717         }
5718
5719         /* Make sure PCI-X relaxed ordering bit is clear. */
5720         if (tp->pcix_cap) {
5721                 u16 pcix_cmd;
5722
5723                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5724                                      &pcix_cmd);
5725                 pcix_cmd &= ~PCI_X_CMD_ERO;
5726                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5727                                       pcix_cmd);
5728         }
5729
5730         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5731
5732                 /* Chip reset on 5780 will reset MSI enable bit,
5733                  * so need to restore it.
5734                  */
5735                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
5736                         u16 ctrl;
5737
5738                         pci_read_config_word(tp->pdev,
5739                                              tp->msi_cap + PCI_MSI_FLAGS,
5740                                              &ctrl);
5741                         pci_write_config_word(tp->pdev,
5742                                               tp->msi_cap + PCI_MSI_FLAGS,
5743                                               ctrl | PCI_MSI_FLAGS_ENABLE);
5744                         val = tr32(MSGINT_MODE);
5745                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
5746                 }
5747         }
5748 }
5749
5750 static void tg3_stop_