tg3: Fix a flags typo
[linux-2.6.git] / drivers / net / tg3.c
1 /*
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  * Copyright (C) 2005-2007 Broadcom Corporation.
8  *
9  * Firmware is:
10  *      Derived from proprietary unpublished source code,
11  *      Copyright (C) 2000-2003 Broadcom Corporation.
12  *
13  *      Permission is hereby granted for the distribution of this firmware
14  *      data in hexadecimal or equivalent format, provided this copyright
15  *      notice is accompanying it.
16  */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
26 #include <linux/in.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/if_vlan.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/workqueue.h>
39 #include <linux/prefetch.h>
40 #include <linux/dma-mapping.h>
41
42 #include <net/checksum.h>
43 #include <net/ip.h>
44
45 #include <asm/system.h>
46 #include <asm/io.h>
47 #include <asm/byteorder.h>
48 #include <asm/uaccess.h>
49
50 #ifdef CONFIG_SPARC
51 #include <asm/idprom.h>
52 #include <asm/prom.h>
53 #endif
54
55 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
56 #define TG3_VLAN_TAG_USED 1
57 #else
58 #define TG3_VLAN_TAG_USED 0
59 #endif
60
61 #define TG3_TSO_SUPPORT 1
62
63 #include "tg3.h"
64
65 #define DRV_MODULE_NAME         "tg3"
66 #define PFX DRV_MODULE_NAME     ": "
67 #define DRV_MODULE_VERSION      "3.92"
68 #define DRV_MODULE_RELDATE      "May 2, 2008"
69
70 #define TG3_DEF_MAC_MODE        0
71 #define TG3_DEF_RX_MODE         0
72 #define TG3_DEF_TX_MODE         0
73 #define TG3_DEF_MSG_ENABLE        \
74         (NETIF_MSG_DRV          | \
75          NETIF_MSG_PROBE        | \
76          NETIF_MSG_LINK         | \
77          NETIF_MSG_TIMER        | \
78          NETIF_MSG_IFDOWN       | \
79          NETIF_MSG_IFUP         | \
80          NETIF_MSG_RX_ERR       | \
81          NETIF_MSG_TX_ERR)
82
83 /* length of time before we decide the hardware is borked,
84  * and dev->tx_timeout() should be called to fix the problem
85  */
86 #define TG3_TX_TIMEOUT                  (5 * HZ)
87
88 /* hardware minimum and maximum for a single frame's data payload */
89 #define TG3_MIN_MTU                     60
90 #define TG3_MAX_MTU(tp) \
91         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
92
93 /* These numbers seem to be hard coded in the NIC firmware somehow.
94  * You can't change the ring sizes, but you can change where you place
95  * them in the NIC onboard memory.
96  */
97 #define TG3_RX_RING_SIZE                512
98 #define TG3_DEF_RX_RING_PENDING         200
99 #define TG3_RX_JUMBO_RING_SIZE          256
100 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
101
102 /* Do not place this n-ring entries value into the tp struct itself,
103  * we really want to expose these constants to GCC so that modulo et
104  * al.  operations are done with shifts and masks instead of with
105  * hw multiply/modulo instructions.  Another solution would be to
106  * replace things like '% foo' with '& (foo - 1)'.
107  */
108 #define TG3_RX_RCB_RING_SIZE(tp)        \
109         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
110
111 #define TG3_TX_RING_SIZE                512
112 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
113
114 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
115                                  TG3_RX_RING_SIZE)
116 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
117                                  TG3_RX_JUMBO_RING_SIZE)
118 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
119                                    TG3_RX_RCB_RING_SIZE(tp))
120 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
121                                  TG3_TX_RING_SIZE)
122 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
123
124 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
125 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
126
127 /* minimum number of free TX descriptors required to wake up TX process */
128 #define TG3_TX_WAKEUP_THRESH(tp)                ((tp)->tx_pending / 4)
129
130 /* number of ETHTOOL_GSTATS u64's */
131 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
132
133 #define TG3_NUM_TEST            6
134
135 static char version[] __devinitdata =
136         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
137
138 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
139 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
140 MODULE_LICENSE("GPL");
141 MODULE_VERSION(DRV_MODULE_VERSION);
142
143 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
144 module_param(tg3_debug, int, 0);
145 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
146
147 static struct pci_device_id tg3_pci_tbl[] = {
148         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
149         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
150         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
151         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
152         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
153         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
154         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
155         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
156         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
157         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
158         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
159         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
160         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
161         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
162         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
163         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
164         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
165         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
166         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
167         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
168         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
169         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
170         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
171         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
206         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
207         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
208         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
209         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
210         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
211         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
212         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
213         {}
214 };
215
216 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
217
218 static const struct {
219         const char string[ETH_GSTRING_LEN];
220 } ethtool_stats_keys[TG3_NUM_STATS] = {
221         { "rx_octets" },
222         { "rx_fragments" },
223         { "rx_ucast_packets" },
224         { "rx_mcast_packets" },
225         { "rx_bcast_packets" },
226         { "rx_fcs_errors" },
227         { "rx_align_errors" },
228         { "rx_xon_pause_rcvd" },
229         { "rx_xoff_pause_rcvd" },
230         { "rx_mac_ctrl_rcvd" },
231         { "rx_xoff_entered" },
232         { "rx_frame_too_long_errors" },
233         { "rx_jabbers" },
234         { "rx_undersize_packets" },
235         { "rx_in_length_errors" },
236         { "rx_out_length_errors" },
237         { "rx_64_or_less_octet_packets" },
238         { "rx_65_to_127_octet_packets" },
239         { "rx_128_to_255_octet_packets" },
240         { "rx_256_to_511_octet_packets" },
241         { "rx_512_to_1023_octet_packets" },
242         { "rx_1024_to_1522_octet_packets" },
243         { "rx_1523_to_2047_octet_packets" },
244         { "rx_2048_to_4095_octet_packets" },
245         { "rx_4096_to_8191_octet_packets" },
246         { "rx_8192_to_9022_octet_packets" },
247
248         { "tx_octets" },
249         { "tx_collisions" },
250
251         { "tx_xon_sent" },
252         { "tx_xoff_sent" },
253         { "tx_flow_control" },
254         { "tx_mac_errors" },
255         { "tx_single_collisions" },
256         { "tx_mult_collisions" },
257         { "tx_deferred" },
258         { "tx_excessive_collisions" },
259         { "tx_late_collisions" },
260         { "tx_collide_2times" },
261         { "tx_collide_3times" },
262         { "tx_collide_4times" },
263         { "tx_collide_5times" },
264         { "tx_collide_6times" },
265         { "tx_collide_7times" },
266         { "tx_collide_8times" },
267         { "tx_collide_9times" },
268         { "tx_collide_10times" },
269         { "tx_collide_11times" },
270         { "tx_collide_12times" },
271         { "tx_collide_13times" },
272         { "tx_collide_14times" },
273         { "tx_collide_15times" },
274         { "tx_ucast_packets" },
275         { "tx_mcast_packets" },
276         { "tx_bcast_packets" },
277         { "tx_carrier_sense_errors" },
278         { "tx_discards" },
279         { "tx_errors" },
280
281         { "dma_writeq_full" },
282         { "dma_write_prioq_full" },
283         { "rxbds_empty" },
284         { "rx_discards" },
285         { "rx_errors" },
286         { "rx_threshold_hit" },
287
288         { "dma_readq_full" },
289         { "dma_read_prioq_full" },
290         { "tx_comp_queue_full" },
291
292         { "ring_set_send_prod_index" },
293         { "ring_status_update" },
294         { "nic_irqs" },
295         { "nic_avoided_irqs" },
296         { "nic_tx_threshold_hit" }
297 };
298
299 static const struct {
300         const char string[ETH_GSTRING_LEN];
301 } ethtool_test_keys[TG3_NUM_TEST] = {
302         { "nvram test     (online) " },
303         { "link test      (online) " },
304         { "register test  (offline)" },
305         { "memory test    (offline)" },
306         { "loopback test  (offline)" },
307         { "interrupt test (offline)" },
308 };
309
310 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
311 {
312         writel(val, tp->regs + off);
313 }
314
315 static u32 tg3_read32(struct tg3 *tp, u32 off)
316 {
317         return (readl(tp->regs + off));
318 }
319
320 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
321 {
322         writel(val, tp->aperegs + off);
323 }
324
325 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
326 {
327         return (readl(tp->aperegs + off));
328 }
329
330 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
331 {
332         unsigned long flags;
333
334         spin_lock_irqsave(&tp->indirect_lock, flags);
335         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
336         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
337         spin_unlock_irqrestore(&tp->indirect_lock, flags);
338 }
339
340 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
341 {
342         writel(val, tp->regs + off);
343         readl(tp->regs + off);
344 }
345
346 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
347 {
348         unsigned long flags;
349         u32 val;
350
351         spin_lock_irqsave(&tp->indirect_lock, flags);
352         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
353         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
354         spin_unlock_irqrestore(&tp->indirect_lock, flags);
355         return val;
356 }
357
358 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
359 {
360         unsigned long flags;
361
362         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
363                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
364                                        TG3_64BIT_REG_LOW, val);
365                 return;
366         }
367         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
368                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
369                                        TG3_64BIT_REG_LOW, val);
370                 return;
371         }
372
373         spin_lock_irqsave(&tp->indirect_lock, flags);
374         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
375         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
376         spin_unlock_irqrestore(&tp->indirect_lock, flags);
377
378         /* In indirect mode when disabling interrupts, we also need
379          * to clear the interrupt bit in the GRC local ctrl register.
380          */
381         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
382             (val == 0x1)) {
383                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
384                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
385         }
386 }
387
388 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
389 {
390         unsigned long flags;
391         u32 val;
392
393         spin_lock_irqsave(&tp->indirect_lock, flags);
394         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
395         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
396         spin_unlock_irqrestore(&tp->indirect_lock, flags);
397         return val;
398 }
399
400 /* usec_wait specifies the wait time in usec when writing to certain registers
401  * where it is unsafe to read back the register without some delay.
402  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
403  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
404  */
405 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
406 {
407         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
408             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
409                 /* Non-posted methods */
410                 tp->write32(tp, off, val);
411         else {
412                 /* Posted method */
413                 tg3_write32(tp, off, val);
414                 if (usec_wait)
415                         udelay(usec_wait);
416                 tp->read32(tp, off);
417         }
418         /* Wait again after the read for the posted method to guarantee that
419          * the wait time is met.
420          */
421         if (usec_wait)
422                 udelay(usec_wait);
423 }
424
425 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
426 {
427         tp->write32_mbox(tp, off, val);
428         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
429             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
430                 tp->read32_mbox(tp, off);
431 }
432
433 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
434 {
435         void __iomem *mbox = tp->regs + off;
436         writel(val, mbox);
437         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
438                 writel(val, mbox);
439         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
440                 readl(mbox);
441 }
442
443 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
444 {
445         return (readl(tp->regs + off + GRCMBOX_BASE));
446 }
447
448 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
449 {
450         writel(val, tp->regs + off + GRCMBOX_BASE);
451 }
452
453 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
454 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
455 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
456 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
457 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
458
459 #define tw32(reg,val)           tp->write32(tp, reg, val)
460 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
461 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
462 #define tr32(reg)               tp->read32(tp, reg)
463
464 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
465 {
466         unsigned long flags;
467
468         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
469             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
470                 return;
471
472         spin_lock_irqsave(&tp->indirect_lock, flags);
473         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
474                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
475                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
476
477                 /* Always leave this as zero. */
478                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
479         } else {
480                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
481                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
482
483                 /* Always leave this as zero. */
484                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
485         }
486         spin_unlock_irqrestore(&tp->indirect_lock, flags);
487 }
488
489 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
490 {
491         unsigned long flags;
492
493         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
494             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
495                 *val = 0;
496                 return;
497         }
498
499         spin_lock_irqsave(&tp->indirect_lock, flags);
500         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
501                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
502                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
503
504                 /* Always leave this as zero. */
505                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
506         } else {
507                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
508                 *val = tr32(TG3PCI_MEM_WIN_DATA);
509
510                 /* Always leave this as zero. */
511                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
512         }
513         spin_unlock_irqrestore(&tp->indirect_lock, flags);
514 }
515
516 static void tg3_ape_lock_init(struct tg3 *tp)
517 {
518         int i;
519
520         /* Make sure the driver hasn't any stale locks. */
521         for (i = 0; i < 8; i++)
522                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
523                                 APE_LOCK_GRANT_DRIVER);
524 }
525
526 static int tg3_ape_lock(struct tg3 *tp, int locknum)
527 {
528         int i, off;
529         int ret = 0;
530         u32 status;
531
532         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
533                 return 0;
534
535         switch (locknum) {
536                 case TG3_APE_LOCK_MEM:
537                         break;
538                 default:
539                         return -EINVAL;
540         }
541
542         off = 4 * locknum;
543
544         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
545
546         /* Wait for up to 1 millisecond to acquire lock. */
547         for (i = 0; i < 100; i++) {
548                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
549                 if (status == APE_LOCK_GRANT_DRIVER)
550                         break;
551                 udelay(10);
552         }
553
554         if (status != APE_LOCK_GRANT_DRIVER) {
555                 /* Revoke the lock request. */
556                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
557                                 APE_LOCK_GRANT_DRIVER);
558
559                 ret = -EBUSY;
560         }
561
562         return ret;
563 }
564
565 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
566 {
567         int off;
568
569         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
570                 return;
571
572         switch (locknum) {
573                 case TG3_APE_LOCK_MEM:
574                         break;
575                 default:
576                         return;
577         }
578
579         off = 4 * locknum;
580         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
581 }
582
583 static void tg3_disable_ints(struct tg3 *tp)
584 {
585         tw32(TG3PCI_MISC_HOST_CTRL,
586              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
587         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
588 }
589
590 static inline void tg3_cond_int(struct tg3 *tp)
591 {
592         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
593             (tp->hw_status->status & SD_STATUS_UPDATED))
594                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
595         else
596                 tw32(HOSTCC_MODE, tp->coalesce_mode |
597                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
598 }
599
600 static void tg3_enable_ints(struct tg3 *tp)
601 {
602         tp->irq_sync = 0;
603         wmb();
604
605         tw32(TG3PCI_MISC_HOST_CTRL,
606              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
607         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
608                        (tp->last_tag << 24));
609         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
610                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
611                                (tp->last_tag << 24));
612         tg3_cond_int(tp);
613 }
614
615 static inline unsigned int tg3_has_work(struct tg3 *tp)
616 {
617         struct tg3_hw_status *sblk = tp->hw_status;
618         unsigned int work_exists = 0;
619
620         /* check for phy events */
621         if (!(tp->tg3_flags &
622               (TG3_FLAG_USE_LINKCHG_REG |
623                TG3_FLAG_POLL_SERDES))) {
624                 if (sblk->status & SD_STATUS_LINK_CHG)
625                         work_exists = 1;
626         }
627         /* check for RX/TX work to do */
628         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
629             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
630                 work_exists = 1;
631
632         return work_exists;
633 }
634
635 /* tg3_restart_ints
636  *  similar to tg3_enable_ints, but it accurately determines whether there
637  *  is new work pending and can return without flushing the PIO write
638  *  which reenables interrupts
639  */
640 static void tg3_restart_ints(struct tg3 *tp)
641 {
642         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
643                      tp->last_tag << 24);
644         mmiowb();
645
646         /* When doing tagged status, this work check is unnecessary.
647          * The last_tag we write above tells the chip which piece of
648          * work we've completed.
649          */
650         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
651             tg3_has_work(tp))
652                 tw32(HOSTCC_MODE, tp->coalesce_mode |
653                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
654 }
655
656 static inline void tg3_netif_stop(struct tg3 *tp)
657 {
658         tp->dev->trans_start = jiffies; /* prevent tx timeout */
659         napi_disable(&tp->napi);
660         netif_tx_disable(tp->dev);
661 }
662
663 static inline void tg3_netif_start(struct tg3 *tp)
664 {
665         netif_wake_queue(tp->dev);
666         /* NOTE: unconditional netif_wake_queue is only appropriate
667          * so long as all callers are assured to have free tx slots
668          * (such as after tg3_init_hw)
669          */
670         napi_enable(&tp->napi);
671         tp->hw_status->status |= SD_STATUS_UPDATED;
672         tg3_enable_ints(tp);
673 }
674
675 static void tg3_switch_clocks(struct tg3 *tp)
676 {
677         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
678         u32 orig_clock_ctrl;
679
680         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
681             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
682                 return;
683
684         orig_clock_ctrl = clock_ctrl;
685         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
686                        CLOCK_CTRL_CLKRUN_OENABLE |
687                        0x1f);
688         tp->pci_clock_ctrl = clock_ctrl;
689
690         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
691                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
692                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
693                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
694                 }
695         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
696                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
697                             clock_ctrl |
698                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
699                             40);
700                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
701                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
702                             40);
703         }
704         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
705 }
706
707 #define PHY_BUSY_LOOPS  5000
708
709 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
710 {
711         u32 frame_val;
712         unsigned int loops;
713         int ret;
714
715         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
716                 tw32_f(MAC_MI_MODE,
717                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
718                 udelay(80);
719         }
720
721         *val = 0x0;
722
723         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
724                       MI_COM_PHY_ADDR_MASK);
725         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
726                       MI_COM_REG_ADDR_MASK);
727         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
728
729         tw32_f(MAC_MI_COM, frame_val);
730
731         loops = PHY_BUSY_LOOPS;
732         while (loops != 0) {
733                 udelay(10);
734                 frame_val = tr32(MAC_MI_COM);
735
736                 if ((frame_val & MI_COM_BUSY) == 0) {
737                         udelay(5);
738                         frame_val = tr32(MAC_MI_COM);
739                         break;
740                 }
741                 loops -= 1;
742         }
743
744         ret = -EBUSY;
745         if (loops != 0) {
746                 *val = frame_val & MI_COM_DATA_MASK;
747                 ret = 0;
748         }
749
750         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
751                 tw32_f(MAC_MI_MODE, tp->mi_mode);
752                 udelay(80);
753         }
754
755         return ret;
756 }
757
758 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
759 {
760         u32 frame_val;
761         unsigned int loops;
762         int ret;
763
764         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
765             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
766                 return 0;
767
768         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
769                 tw32_f(MAC_MI_MODE,
770                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
771                 udelay(80);
772         }
773
774         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
775                       MI_COM_PHY_ADDR_MASK);
776         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
777                       MI_COM_REG_ADDR_MASK);
778         frame_val |= (val & MI_COM_DATA_MASK);
779         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
780
781         tw32_f(MAC_MI_COM, frame_val);
782
783         loops = PHY_BUSY_LOOPS;
784         while (loops != 0) {
785                 udelay(10);
786                 frame_val = tr32(MAC_MI_COM);
787                 if ((frame_val & MI_COM_BUSY) == 0) {
788                         udelay(5);
789                         frame_val = tr32(MAC_MI_COM);
790                         break;
791                 }
792                 loops -= 1;
793         }
794
795         ret = -EBUSY;
796         if (loops != 0)
797                 ret = 0;
798
799         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
800                 tw32_f(MAC_MI_MODE, tp->mi_mode);
801                 udelay(80);
802         }
803
804         return ret;
805 }
806
807 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
808 {
809         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
810         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
811 }
812
813 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
814 {
815         u32 phy;
816
817         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
818             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
819                 return;
820
821         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
822                 u32 ephy;
823
824                 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
825                         tg3_writephy(tp, MII_TG3_EPHY_TEST,
826                                      ephy | MII_TG3_EPHY_SHADOW_EN);
827                         if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
828                                 if (enable)
829                                         phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
830                                 else
831                                         phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
832                                 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
833                         }
834                         tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
835                 }
836         } else {
837                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
838                       MII_TG3_AUXCTL_SHDWSEL_MISC;
839                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
840                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
841                         if (enable)
842                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
843                         else
844                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
845                         phy |= MII_TG3_AUXCTL_MISC_WREN;
846                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
847                 }
848         }
849 }
850
851 static void tg3_phy_set_wirespeed(struct tg3 *tp)
852 {
853         u32 val;
854
855         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
856                 return;
857
858         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
859             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
860                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
861                              (val | (1 << 15) | (1 << 4)));
862 }
863
864 static int tg3_bmcr_reset(struct tg3 *tp)
865 {
866         u32 phy_control;
867         int limit, err;
868
869         /* OK, reset it, and poll the BMCR_RESET bit until it
870          * clears or we time out.
871          */
872         phy_control = BMCR_RESET;
873         err = tg3_writephy(tp, MII_BMCR, phy_control);
874         if (err != 0)
875                 return -EBUSY;
876
877         limit = 5000;
878         while (limit--) {
879                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
880                 if (err != 0)
881                         return -EBUSY;
882
883                 if ((phy_control & BMCR_RESET) == 0) {
884                         udelay(40);
885                         break;
886                 }
887                 udelay(10);
888         }
889         if (limit <= 0)
890                 return -EBUSY;
891
892         return 0;
893 }
894
895 static void tg3_phy_apply_otp(struct tg3 *tp)
896 {
897         u32 otp, phy;
898
899         if (!tp->phy_otp)
900                 return;
901
902         otp = tp->phy_otp;
903
904         /* Enable SM_DSP clock and tx 6dB coding. */
905         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
906               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
907               MII_TG3_AUXCTL_ACTL_TX_6DB;
908         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
909
910         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
911         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
912         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
913
914         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
915               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
916         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
917
918         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
919         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
920         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
921
922         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
923         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
924
925         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
926         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
927
928         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
929               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
930         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
931
932         /* Turn off SM_DSP clock. */
933         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
934               MII_TG3_AUXCTL_ACTL_TX_6DB;
935         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
936 }
937
938 static int tg3_wait_macro_done(struct tg3 *tp)
939 {
940         int limit = 100;
941
942         while (limit--) {
943                 u32 tmp32;
944
945                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
946                         if ((tmp32 & 0x1000) == 0)
947                                 break;
948                 }
949         }
950         if (limit <= 0)
951                 return -EBUSY;
952
953         return 0;
954 }
955
956 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
957 {
958         static const u32 test_pat[4][6] = {
959         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
960         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
961         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
962         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
963         };
964         int chan;
965
966         for (chan = 0; chan < 4; chan++) {
967                 int i;
968
969                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
970                              (chan * 0x2000) | 0x0200);
971                 tg3_writephy(tp, 0x16, 0x0002);
972
973                 for (i = 0; i < 6; i++)
974                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
975                                      test_pat[chan][i]);
976
977                 tg3_writephy(tp, 0x16, 0x0202);
978                 if (tg3_wait_macro_done(tp)) {
979                         *resetp = 1;
980                         return -EBUSY;
981                 }
982
983                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
984                              (chan * 0x2000) | 0x0200);
985                 tg3_writephy(tp, 0x16, 0x0082);
986                 if (tg3_wait_macro_done(tp)) {
987                         *resetp = 1;
988                         return -EBUSY;
989                 }
990
991                 tg3_writephy(tp, 0x16, 0x0802);
992                 if (tg3_wait_macro_done(tp)) {
993                         *resetp = 1;
994                         return -EBUSY;
995                 }
996
997                 for (i = 0; i < 6; i += 2) {
998                         u32 low, high;
999
1000                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1001                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1002                             tg3_wait_macro_done(tp)) {
1003                                 *resetp = 1;
1004                                 return -EBUSY;
1005                         }
1006                         low &= 0x7fff;
1007                         high &= 0x000f;
1008                         if (low != test_pat[chan][i] ||
1009                             high != test_pat[chan][i+1]) {
1010                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1011                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1012                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1013
1014                                 return -EBUSY;
1015                         }
1016                 }
1017         }
1018
1019         return 0;
1020 }
1021
1022 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1023 {
1024         int chan;
1025
1026         for (chan = 0; chan < 4; chan++) {
1027                 int i;
1028
1029                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1030                              (chan * 0x2000) | 0x0200);
1031                 tg3_writephy(tp, 0x16, 0x0002);
1032                 for (i = 0; i < 6; i++)
1033                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1034                 tg3_writephy(tp, 0x16, 0x0202);
1035                 if (tg3_wait_macro_done(tp))
1036                         return -EBUSY;
1037         }
1038
1039         return 0;
1040 }
1041
1042 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1043 {
1044         u32 reg32, phy9_orig;
1045         int retries, do_phy_reset, err;
1046
1047         retries = 10;
1048         do_phy_reset = 1;
1049         do {
1050                 if (do_phy_reset) {
1051                         err = tg3_bmcr_reset(tp);
1052                         if (err)
1053                                 return err;
1054                         do_phy_reset = 0;
1055                 }
1056
1057                 /* Disable transmitter and interrupt.  */
1058                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1059                         continue;
1060
1061                 reg32 |= 0x3000;
1062                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1063
1064                 /* Set full-duplex, 1000 mbps.  */
1065                 tg3_writephy(tp, MII_BMCR,
1066                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1067
1068                 /* Set to master mode.  */
1069                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1070                         continue;
1071
1072                 tg3_writephy(tp, MII_TG3_CTRL,
1073                              (MII_TG3_CTRL_AS_MASTER |
1074                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1075
1076                 /* Enable SM_DSP_CLOCK and 6dB.  */
1077                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1078
1079                 /* Block the PHY control access.  */
1080                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1081                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1082
1083                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1084                 if (!err)
1085                         break;
1086         } while (--retries);
1087
1088         err = tg3_phy_reset_chanpat(tp);
1089         if (err)
1090                 return err;
1091
1092         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1093         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1094
1095         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1096         tg3_writephy(tp, 0x16, 0x0000);
1097
1098         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1099             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1100                 /* Set Extended packet length bit for jumbo frames */
1101                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1102         }
1103         else {
1104                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1105         }
1106
1107         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1108
1109         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1110                 reg32 &= ~0x3000;
1111                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1112         } else if (!err)
1113                 err = -EBUSY;
1114
1115         return err;
1116 }
1117
1118 static void tg3_link_report(struct tg3 *);
1119
1120 /* This will reset the tigon3 PHY if there is no valid
1121  * link unless the FORCE argument is non-zero.
1122  */
1123 static int tg3_phy_reset(struct tg3 *tp)
1124 {
1125         u32 cpmuctrl;
1126         u32 phy_status;
1127         int err;
1128
1129         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1130                 u32 val;
1131
1132                 val = tr32(GRC_MISC_CFG);
1133                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1134                 udelay(40);
1135         }
1136         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1137         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1138         if (err != 0)
1139                 return -EBUSY;
1140
1141         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1142                 netif_carrier_off(tp->dev);
1143                 tg3_link_report(tp);
1144         }
1145
1146         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1147             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1148             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1149                 err = tg3_phy_reset_5703_4_5(tp);
1150                 if (err)
1151                         return err;
1152                 goto out;
1153         }
1154
1155         cpmuctrl = 0;
1156         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1157             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1158                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1159                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1160                         tw32(TG3_CPMU_CTRL,
1161                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1162         }
1163
1164         err = tg3_bmcr_reset(tp);
1165         if (err)
1166                 return err;
1167
1168         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1169                 u32 phy;
1170
1171                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1172                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1173
1174                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1175         }
1176
1177         if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
1178                 u32 val;
1179
1180                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1181                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1182                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1183                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1184                         udelay(40);
1185                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1186                 }
1187
1188                 /* Disable GPHY autopowerdown. */
1189                 tg3_writephy(tp, MII_TG3_MISC_SHDW,
1190                              MII_TG3_MISC_SHDW_WREN |
1191                              MII_TG3_MISC_SHDW_APD_SEL |
1192                              MII_TG3_MISC_SHDW_APD_WKTM_84MS);
1193         }
1194
1195         tg3_phy_apply_otp(tp);
1196
1197 out:
1198         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1199                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1200                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1201                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1202                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1203                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1204                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1205         }
1206         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1207                 tg3_writephy(tp, 0x1c, 0x8d68);
1208                 tg3_writephy(tp, 0x1c, 0x8d68);
1209         }
1210         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1211                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1212                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1213                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1214                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1215                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1216                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1217                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1218                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1219         }
1220         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1221                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1222                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1223                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1224                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1225                         tg3_writephy(tp, MII_TG3_TEST1,
1226                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1227                 } else
1228                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1229                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1230         }
1231         /* Set Extended packet length bit (bit 14) on all chips that */
1232         /* support jumbo frames */
1233         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1234                 /* Cannot do read-modify-write on 5401 */
1235                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1236         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1237                 u32 phy_reg;
1238
1239                 /* Set bit 14 with read-modify-write to preserve other bits */
1240                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1241                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1242                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1243         }
1244
1245         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1246          * jumbo frames transmission.
1247          */
1248         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1249                 u32 phy_reg;
1250
1251                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1252                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1253                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1254         }
1255
1256         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1257                 /* adjust output voltage */
1258                 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1259         }
1260
1261         tg3_phy_toggle_automdix(tp, 1);
1262         tg3_phy_set_wirespeed(tp);
1263         return 0;
1264 }
1265
1266 static void tg3_frob_aux_power(struct tg3 *tp)
1267 {
1268         struct tg3 *tp_peer = tp;
1269
1270         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1271                 return;
1272
1273         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1274             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1275                 struct net_device *dev_peer;
1276
1277                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1278                 /* remove_one() may have been run on the peer. */
1279                 if (!dev_peer)
1280                         tp_peer = tp;
1281                 else
1282                         tp_peer = netdev_priv(dev_peer);
1283         }
1284
1285         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1286             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1287             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1288             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1289                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1290                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1291                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1292                                     (GRC_LCLCTRL_GPIO_OE0 |
1293                                      GRC_LCLCTRL_GPIO_OE1 |
1294                                      GRC_LCLCTRL_GPIO_OE2 |
1295                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1296                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1297                                     100);
1298                 } else {
1299                         u32 no_gpio2;
1300                         u32 grc_local_ctrl = 0;
1301
1302                         if (tp_peer != tp &&
1303                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1304                                 return;
1305
1306                         /* Workaround to prevent overdrawing Amps. */
1307                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1308                             ASIC_REV_5714) {
1309                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1310                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1311                                             grc_local_ctrl, 100);
1312                         }
1313
1314                         /* On 5753 and variants, GPIO2 cannot be used. */
1315                         no_gpio2 = tp->nic_sram_data_cfg &
1316                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1317
1318                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1319                                          GRC_LCLCTRL_GPIO_OE1 |
1320                                          GRC_LCLCTRL_GPIO_OE2 |
1321                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1322                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1323                         if (no_gpio2) {
1324                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1325                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
1326                         }
1327                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1328                                                     grc_local_ctrl, 100);
1329
1330                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1331
1332                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1333                                                     grc_local_ctrl, 100);
1334
1335                         if (!no_gpio2) {
1336                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1337                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1338                                             grc_local_ctrl, 100);
1339                         }
1340                 }
1341         } else {
1342                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1343                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1344                         if (tp_peer != tp &&
1345                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1346                                 return;
1347
1348                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1349                                     (GRC_LCLCTRL_GPIO_OE1 |
1350                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1351
1352                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1353                                     GRC_LCLCTRL_GPIO_OE1, 100);
1354
1355                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1356                                     (GRC_LCLCTRL_GPIO_OE1 |
1357                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1358                 }
1359         }
1360 }
1361
1362 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
1363 {
1364         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
1365                 return 1;
1366         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
1367                 if (speed != SPEED_10)
1368                         return 1;
1369         } else if (speed == SPEED_10)
1370                 return 1;
1371
1372         return 0;
1373 }
1374
1375 static int tg3_setup_phy(struct tg3 *, int);
1376
1377 #define RESET_KIND_SHUTDOWN     0
1378 #define RESET_KIND_INIT         1
1379 #define RESET_KIND_SUSPEND      2
1380
1381 static void tg3_write_sig_post_reset(struct tg3 *, int);
1382 static int tg3_halt_cpu(struct tg3 *, u32);
1383 static int tg3_nvram_lock(struct tg3 *);
1384 static void tg3_nvram_unlock(struct tg3 *);
1385
1386 static void tg3_power_down_phy(struct tg3 *tp)
1387 {
1388         u32 val;
1389
1390         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1391                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1392                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
1393                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
1394
1395                         sg_dig_ctrl |=
1396                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
1397                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
1398                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
1399                 }
1400                 return;
1401         }
1402
1403         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1404                 tg3_bmcr_reset(tp);
1405                 val = tr32(GRC_MISC_CFG);
1406                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1407                 udelay(40);
1408                 return;
1409         } else {
1410                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1411                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1412                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1413         }
1414
1415         /* The PHY should not be powered down on some chips because
1416          * of bugs.
1417          */
1418         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1419             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1420             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1421              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1422                 return;
1423
1424         if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
1425                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1426                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1427                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
1428                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1429         }
1430
1431         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1432 }
1433
1434 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1435 {
1436         u32 misc_host_ctrl;
1437         u16 power_control, power_caps;
1438         int pm = tp->pm_cap;
1439
1440         /* Make sure register accesses (indirect or otherwise)
1441          * will function correctly.
1442          */
1443         pci_write_config_dword(tp->pdev,
1444                                TG3PCI_MISC_HOST_CTRL,
1445                                tp->misc_host_ctrl);
1446
1447         pci_read_config_word(tp->pdev,
1448                              pm + PCI_PM_CTRL,
1449                              &power_control);
1450         power_control |= PCI_PM_CTRL_PME_STATUS;
1451         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1452         switch (state) {
1453         case PCI_D0:
1454                 power_control |= 0;
1455                 pci_write_config_word(tp->pdev,
1456                                       pm + PCI_PM_CTRL,
1457                                       power_control);
1458                 udelay(100);    /* Delay after power state change */
1459
1460                 /* Switch out of Vaux if it is a NIC */
1461                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
1462                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1463
1464                 return 0;
1465
1466         case PCI_D1:
1467                 power_control |= 1;
1468                 break;
1469
1470         case PCI_D2:
1471                 power_control |= 2;
1472                 break;
1473
1474         case PCI_D3hot:
1475                 power_control |= 3;
1476                 break;
1477
1478         default:
1479                 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1480                        "requested.\n",
1481                        tp->dev->name, state);
1482                 return -EINVAL;
1483         };
1484
1485         power_control |= PCI_PM_CTRL_PME_ENABLE;
1486
1487         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1488         tw32(TG3PCI_MISC_HOST_CTRL,
1489              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1490
1491         if (tp->link_config.phy_is_low_power == 0) {
1492                 tp->link_config.phy_is_low_power = 1;
1493                 tp->link_config.orig_speed = tp->link_config.speed;
1494                 tp->link_config.orig_duplex = tp->link_config.duplex;
1495                 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1496         }
1497
1498         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1499                 tp->link_config.speed = SPEED_10;
1500                 tp->link_config.duplex = DUPLEX_HALF;
1501                 tp->link_config.autoneg = AUTONEG_ENABLE;
1502                 tg3_setup_phy(tp, 0);
1503         }
1504
1505         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1506                 u32 val;
1507
1508                 val = tr32(GRC_VCPU_EXT_CTRL);
1509                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1510         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1511                 int i;
1512                 u32 val;
1513
1514                 for (i = 0; i < 200; i++) {
1515                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1516                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1517                                 break;
1518                         msleep(1);
1519                 }
1520         }
1521         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
1522                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1523                                                      WOL_DRV_STATE_SHUTDOWN |
1524                                                      WOL_DRV_WOL |
1525                                                      WOL_SET_MAGIC_PKT);
1526
1527         pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1528
1529         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1530                 u32 mac_mode;
1531
1532                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1533                         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1534                         udelay(40);
1535
1536                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1537                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
1538                         else
1539                                 mac_mode = MAC_MODE_PORT_MODE_MII;
1540
1541                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
1542                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1543                             ASIC_REV_5700) {
1544                                 u32 speed = (tp->tg3_flags &
1545                                              TG3_FLAG_WOL_SPEED_100MB) ?
1546                                              SPEED_100 : SPEED_10;
1547                                 if (tg3_5700_link_polarity(tp, speed))
1548                                         mac_mode |= MAC_MODE_LINK_POLARITY;
1549                                 else
1550                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
1551                         }
1552                 } else {
1553                         mac_mode = MAC_MODE_PORT_MODE_TBI;
1554                 }
1555
1556                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1557                         tw32(MAC_LED_CTRL, tp->led_ctrl);
1558
1559                 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1560                      (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1561                         mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1562
1563                 tw32_f(MAC_MODE, mac_mode);
1564                 udelay(100);
1565
1566                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1567                 udelay(10);
1568         }
1569
1570         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1571             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1572              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1573                 u32 base_val;
1574
1575                 base_val = tp->pci_clock_ctrl;
1576                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1577                              CLOCK_CTRL_TXCLK_DISABLE);
1578
1579                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1580                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
1581         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1582                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
1583                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
1584                 /* do nothing */
1585         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1586                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1587                 u32 newbits1, newbits2;
1588
1589                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1590                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1591                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1592                                     CLOCK_CTRL_TXCLK_DISABLE |
1593                                     CLOCK_CTRL_ALTCLK);
1594                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1595                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1596                         newbits1 = CLOCK_CTRL_625_CORE;
1597                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1598                 } else {
1599                         newbits1 = CLOCK_CTRL_ALTCLK;
1600                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1601                 }
1602
1603                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1604                             40);
1605
1606                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1607                             40);
1608
1609                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1610                         u32 newbits3;
1611
1612                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1613                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1614                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1615                                             CLOCK_CTRL_TXCLK_DISABLE |
1616                                             CLOCK_CTRL_44MHZ_CORE);
1617                         } else {
1618                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1619                         }
1620
1621                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
1622                                     tp->pci_clock_ctrl | newbits3, 40);
1623                 }
1624         }
1625
1626         if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1627             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
1628             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
1629                 tg3_power_down_phy(tp);
1630
1631         tg3_frob_aux_power(tp);
1632
1633         /* Workaround for unstable PLL clock */
1634         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1635             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1636                 u32 val = tr32(0x7d00);
1637
1638                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1639                 tw32(0x7d00, val);
1640                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1641                         int err;
1642
1643                         err = tg3_nvram_lock(tp);
1644                         tg3_halt_cpu(tp, RX_CPU_BASE);
1645                         if (!err)
1646                                 tg3_nvram_unlock(tp);
1647                 }
1648         }
1649
1650         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1651
1652         /* Finally, set the new power state. */
1653         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1654         udelay(100);    /* Delay after power state change */
1655
1656         return 0;
1657 }
1658
1659 /* tp->lock is held. */
1660 static void tg3_wait_for_event_ack(struct tg3 *tp)
1661 {
1662         int i;
1663
1664         /* Wait for up to 2.5 milliseconds */
1665         for (i = 0; i < 250000; i++) {
1666                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1667                         break;
1668                 udelay(10);
1669         }
1670 }
1671
1672 /* tp->lock is held. */
1673 static void tg3_ump_link_report(struct tg3 *tp)
1674 {
1675         u32 reg;
1676         u32 val;
1677
1678         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1679             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1680                 return;
1681
1682         tg3_wait_for_event_ack(tp);
1683
1684         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1685
1686         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1687
1688         val = 0;
1689         if (!tg3_readphy(tp, MII_BMCR, &reg))
1690                 val = reg << 16;
1691         if (!tg3_readphy(tp, MII_BMSR, &reg))
1692                 val |= (reg & 0xffff);
1693         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1694
1695         val = 0;
1696         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1697                 val = reg << 16;
1698         if (!tg3_readphy(tp, MII_LPA, &reg))
1699                 val |= (reg & 0xffff);
1700         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1701
1702         val = 0;
1703         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1704                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1705                         val = reg << 16;
1706                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1707                         val |= (reg & 0xffff);
1708         }
1709         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1710
1711         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1712                 val = reg << 16;
1713         else
1714                 val = 0;
1715         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1716
1717         val = tr32(GRC_RX_CPU_EVENT);
1718         val |= GRC_RX_CPU_DRIVER_EVENT;
1719         tw32_f(GRC_RX_CPU_EVENT, val);
1720 }
1721
1722 static void tg3_link_report(struct tg3 *tp)
1723 {
1724         if (!netif_carrier_ok(tp->dev)) {
1725                 if (netif_msg_link(tp))
1726                         printk(KERN_INFO PFX "%s: Link is down.\n",
1727                                tp->dev->name);
1728                 tg3_ump_link_report(tp);
1729         } else if (netif_msg_link(tp)) {
1730                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1731                        tp->dev->name,
1732                        (tp->link_config.active_speed == SPEED_1000 ?
1733                         1000 :
1734                         (tp->link_config.active_speed == SPEED_100 ?
1735                          100 : 10)),
1736                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1737                         "full" : "half"));
1738
1739                 printk(KERN_INFO PFX
1740                        "%s: Flow control is %s for TX and %s for RX.\n",
1741                        tp->dev->name,
1742                        (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_TX) ?
1743                        "on" : "off",
1744                        (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_RX) ?
1745                        "on" : "off");
1746                 tg3_ump_link_report(tp);
1747         }
1748 }
1749
1750 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1751 {
1752         u16 miireg;
1753
1754         if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
1755                 miireg = ADVERTISE_PAUSE_CAP;
1756         else if (flow_ctrl & TG3_FLOW_CTRL_TX)
1757                 miireg = ADVERTISE_PAUSE_ASYM;
1758         else if (flow_ctrl & TG3_FLOW_CTRL_RX)
1759                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1760         else
1761                 miireg = 0;
1762
1763         return miireg;
1764 }
1765
1766 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1767 {
1768         u16 miireg;
1769
1770         if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
1771                 miireg = ADVERTISE_1000XPAUSE;
1772         else if (flow_ctrl & TG3_FLOW_CTRL_TX)
1773                 miireg = ADVERTISE_1000XPSE_ASYM;
1774         else if (flow_ctrl & TG3_FLOW_CTRL_RX)
1775                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1776         else
1777                 miireg = 0;
1778
1779         return miireg;
1780 }
1781
1782 static u8 tg3_resolve_flowctrl_1000T(u16 lcladv, u16 rmtadv)
1783 {
1784         u8 cap = 0;
1785
1786         if (lcladv & ADVERTISE_PAUSE_CAP) {
1787                 if (lcladv & ADVERTISE_PAUSE_ASYM) {
1788                         if (rmtadv & LPA_PAUSE_CAP)
1789                                 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1790                         else if (rmtadv & LPA_PAUSE_ASYM)
1791                                 cap = TG3_FLOW_CTRL_RX;
1792                 } else {
1793                         if (rmtadv & LPA_PAUSE_CAP)
1794                                 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1795                 }
1796         } else if (lcladv & ADVERTISE_PAUSE_ASYM) {
1797                 if ((rmtadv & LPA_PAUSE_CAP) && (rmtadv & LPA_PAUSE_ASYM))
1798                         cap = TG3_FLOW_CTRL_TX;
1799         }
1800
1801         return cap;
1802 }
1803
1804 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1805 {
1806         u8 cap = 0;
1807
1808         if (lcladv & ADVERTISE_1000XPAUSE) {
1809                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1810                         if (rmtadv & LPA_1000XPAUSE)
1811                                 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1812                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1813                                 cap = TG3_FLOW_CTRL_RX;
1814                 } else {
1815                         if (rmtadv & LPA_1000XPAUSE)
1816                                 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1817                 }
1818         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1819                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1820                         cap = TG3_FLOW_CTRL_TX;
1821         }
1822
1823         return cap;
1824 }
1825
1826 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1827 {
1828         u8 new_tg3_flags = 0;
1829         u32 old_rx_mode = tp->rx_mode;
1830         u32 old_tx_mode = tp->tx_mode;
1831
1832         if (tp->link_config.autoneg == AUTONEG_ENABLE &&
1833             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1834                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1835                         new_tg3_flags = tg3_resolve_flowctrl_1000X(local_adv,
1836                                                                    remote_adv);
1837                 else
1838                         new_tg3_flags = tg3_resolve_flowctrl_1000T(local_adv,
1839                                                                    remote_adv);
1840         } else {
1841                 new_tg3_flags = tp->link_config.flowctrl;
1842         }
1843
1844         tp->link_config.active_flowctrl = new_tg3_flags;
1845
1846         if (new_tg3_flags & TG3_FLOW_CTRL_RX)
1847                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1848         else
1849                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1850
1851         if (old_rx_mode != tp->rx_mode) {
1852                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1853         }
1854
1855         if (new_tg3_flags & TG3_FLOW_CTRL_TX)
1856                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1857         else
1858                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1859
1860         if (old_tx_mode != tp->tx_mode) {
1861                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1862         }
1863 }
1864
1865 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1866 {
1867         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1868         case MII_TG3_AUX_STAT_10HALF:
1869                 *speed = SPEED_10;
1870                 *duplex = DUPLEX_HALF;
1871                 break;
1872
1873         case MII_TG3_AUX_STAT_10FULL:
1874                 *speed = SPEED_10;
1875                 *duplex = DUPLEX_FULL;
1876                 break;
1877
1878         case MII_TG3_AUX_STAT_100HALF:
1879                 *speed = SPEED_100;
1880                 *duplex = DUPLEX_HALF;
1881                 break;
1882
1883         case MII_TG3_AUX_STAT_100FULL:
1884                 *speed = SPEED_100;
1885                 *duplex = DUPLEX_FULL;
1886                 break;
1887
1888         case MII_TG3_AUX_STAT_1000HALF:
1889                 *speed = SPEED_1000;
1890                 *duplex = DUPLEX_HALF;
1891                 break;
1892
1893         case MII_TG3_AUX_STAT_1000FULL:
1894                 *speed = SPEED_1000;
1895                 *duplex = DUPLEX_FULL;
1896                 break;
1897
1898         default:
1899                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1900                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1901                                  SPEED_10;
1902                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1903                                   DUPLEX_HALF;
1904                         break;
1905                 }
1906                 *speed = SPEED_INVALID;
1907                 *duplex = DUPLEX_INVALID;
1908                 break;
1909         };
1910 }
1911
1912 static void tg3_phy_copper_begin(struct tg3 *tp)
1913 {
1914         u32 new_adv;
1915         int i;
1916
1917         if (tp->link_config.phy_is_low_power) {
1918                 /* Entering low power mode.  Disable gigabit and
1919                  * 100baseT advertisements.
1920                  */
1921                 tg3_writephy(tp, MII_TG3_CTRL, 0);
1922
1923                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1924                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1925                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1926                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1927
1928                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1929         } else if (tp->link_config.speed == SPEED_INVALID) {
1930                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1931                         tp->link_config.advertising &=
1932                                 ~(ADVERTISED_1000baseT_Half |
1933                                   ADVERTISED_1000baseT_Full);
1934
1935                 new_adv = ADVERTISE_CSMA;
1936                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1937                         new_adv |= ADVERTISE_10HALF;
1938                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1939                         new_adv |= ADVERTISE_10FULL;
1940                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1941                         new_adv |= ADVERTISE_100HALF;
1942                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1943                         new_adv |= ADVERTISE_100FULL;
1944
1945                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
1946
1947                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1948
1949                 if (tp->link_config.advertising &
1950                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1951                         new_adv = 0;
1952                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1953                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1954                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1955                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1956                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1957                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1958                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1959                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1960                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1961                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1962                 } else {
1963                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1964                 }
1965         } else {
1966                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
1967                 new_adv |= ADVERTISE_CSMA;
1968
1969                 /* Asking for a specific link mode. */
1970                 if (tp->link_config.speed == SPEED_1000) {
1971                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1972
1973                         if (tp->link_config.duplex == DUPLEX_FULL)
1974                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1975                         else
1976                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1977                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1978                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1979                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1980                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1981                 } else {
1982                         if (tp->link_config.speed == SPEED_100) {
1983                                 if (tp->link_config.duplex == DUPLEX_FULL)
1984                                         new_adv |= ADVERTISE_100FULL;
1985                                 else
1986                                         new_adv |= ADVERTISE_100HALF;
1987                         } else {
1988                                 if (tp->link_config.duplex == DUPLEX_FULL)
1989                                         new_adv |= ADVERTISE_10FULL;
1990                                 else
1991                                         new_adv |= ADVERTISE_10HALF;
1992                         }
1993                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1994
1995                         new_adv = 0;
1996                 }
1997
1998                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1999         }
2000
2001         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2002             tp->link_config.speed != SPEED_INVALID) {
2003                 u32 bmcr, orig_bmcr;
2004
2005                 tp->link_config.active_speed = tp->link_config.speed;
2006                 tp->link_config.active_duplex = tp->link_config.duplex;
2007
2008                 bmcr = 0;
2009                 switch (tp->link_config.speed) {
2010                 default:
2011                 case SPEED_10:
2012                         break;
2013
2014                 case SPEED_100:
2015                         bmcr |= BMCR_SPEED100;
2016                         break;
2017
2018                 case SPEED_1000:
2019                         bmcr |= TG3_BMCR_SPEED1000;
2020                         break;
2021                 };
2022
2023                 if (tp->link_config.duplex == DUPLEX_FULL)
2024                         bmcr |= BMCR_FULLDPLX;
2025
2026                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2027                     (bmcr != orig_bmcr)) {
2028                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2029                         for (i = 0; i < 1500; i++) {
2030                                 u32 tmp;
2031
2032                                 udelay(10);
2033                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2034                                     tg3_readphy(tp, MII_BMSR, &tmp))
2035                                         continue;
2036                                 if (!(tmp & BMSR_LSTATUS)) {
2037                                         udelay(40);
2038                                         break;
2039                                 }
2040                         }
2041                         tg3_writephy(tp, MII_BMCR, bmcr);
2042                         udelay(40);
2043                 }
2044         } else {
2045                 tg3_writephy(tp, MII_BMCR,
2046                              BMCR_ANENABLE | BMCR_ANRESTART);
2047         }
2048 }
2049
2050 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2051 {
2052         int err;
2053
2054         /* Turn off tap power management. */
2055         /* Set Extended packet length bit */
2056         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2057
2058         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2059         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2060
2061         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2062         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2063
2064         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2065         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2066
2067         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2068         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2069
2070         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2071         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2072
2073         udelay(40);
2074
2075         return err;
2076 }
2077
2078 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2079 {
2080         u32 adv_reg, all_mask = 0;
2081
2082         if (mask & ADVERTISED_10baseT_Half)
2083                 all_mask |= ADVERTISE_10HALF;
2084         if (mask & ADVERTISED_10baseT_Full)
2085                 all_mask |= ADVERTISE_10FULL;
2086         if (mask & ADVERTISED_100baseT_Half)
2087                 all_mask |= ADVERTISE_100HALF;
2088         if (mask & ADVERTISED_100baseT_Full)
2089                 all_mask |= ADVERTISE_100FULL;
2090
2091         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2092                 return 0;
2093
2094         if ((adv_reg & all_mask) != all_mask)
2095                 return 0;
2096         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2097                 u32 tg3_ctrl;
2098
2099                 all_mask = 0;
2100                 if (mask & ADVERTISED_1000baseT_Half)
2101                         all_mask |= ADVERTISE_1000HALF;
2102                 if (mask & ADVERTISED_1000baseT_Full)
2103                         all_mask |= ADVERTISE_1000FULL;
2104
2105                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2106                         return 0;
2107
2108                 if ((tg3_ctrl & all_mask) != all_mask)
2109                         return 0;
2110         }
2111         return 1;
2112 }
2113
2114 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2115 {
2116         u32 curadv, reqadv;
2117
2118         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2119                 return 1;
2120
2121         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2122         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2123
2124         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2125                 if (curadv != reqadv)
2126                         return 0;
2127
2128                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2129                         tg3_readphy(tp, MII_LPA, rmtadv);
2130         } else {
2131                 /* Reprogram the advertisement register, even if it
2132                  * does not affect the current link.  If the link
2133                  * gets renegotiated in the future, we can save an
2134                  * additional renegotiation cycle by advertising
2135                  * it correctly in the first place.
2136                  */
2137                 if (curadv != reqadv) {
2138                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2139                                      ADVERTISE_PAUSE_ASYM);
2140                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2141                 }
2142         }
2143
2144         return 1;
2145 }
2146
2147 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2148 {
2149         int current_link_up;
2150         u32 bmsr, dummy;
2151         u32 lcl_adv, rmt_adv;
2152         u16 current_speed;
2153         u8 current_duplex;
2154         int i, err;
2155
2156         tw32(MAC_EVENT, 0);
2157
2158         tw32_f(MAC_STATUS,
2159              (MAC_STATUS_SYNC_CHANGED |
2160               MAC_STATUS_CFG_CHANGED |
2161               MAC_STATUS_MI_COMPLETION |
2162               MAC_STATUS_LNKSTATE_CHANGED));
2163         udelay(40);
2164
2165         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2166                 tw32_f(MAC_MI_MODE,
2167                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2168                 udelay(80);
2169         }
2170
2171         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2172
2173         /* Some third-party PHYs need to be reset on link going
2174          * down.
2175          */
2176         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2177              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2178              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2179             netif_carrier_ok(tp->dev)) {
2180                 tg3_readphy(tp, MII_BMSR, &bmsr);
2181                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2182                     !(bmsr & BMSR_LSTATUS))
2183                         force_reset = 1;
2184         }
2185         if (force_reset)
2186                 tg3_phy_reset(tp);
2187
2188         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2189                 tg3_readphy(tp, MII_BMSR, &bmsr);
2190                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2191                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2192                         bmsr = 0;
2193
2194                 if (!(bmsr & BMSR_LSTATUS)) {
2195                         err = tg3_init_5401phy_dsp(tp);
2196                         if (err)
2197                                 return err;
2198
2199                         tg3_readphy(tp, MII_BMSR, &bmsr);
2200                         for (i = 0; i < 1000; i++) {
2201                                 udelay(10);
2202                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2203                                     (bmsr & BMSR_LSTATUS)) {
2204                                         udelay(40);
2205                                         break;
2206                                 }
2207                         }
2208
2209                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
2210                             !(bmsr & BMSR_LSTATUS) &&
2211                             tp->link_config.active_speed == SPEED_1000) {
2212                                 err = tg3_phy_reset(tp);
2213                                 if (!err)
2214                                         err = tg3_init_5401phy_dsp(tp);
2215                                 if (err)
2216                                         return err;
2217                         }
2218                 }
2219         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2220                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2221                 /* 5701 {A0,B0} CRC bug workaround */
2222                 tg3_writephy(tp, 0x15, 0x0a75);
2223                 tg3_writephy(tp, 0x1c, 0x8c68);
2224                 tg3_writephy(tp, 0x1c, 0x8d68);
2225                 tg3_writephy(tp, 0x1c, 0x8c68);
2226         }
2227
2228         /* Clear pending interrupts... */
2229         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2230         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2231
2232         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
2233                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
2234         else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
2235                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
2236
2237         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2238             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2239                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
2240                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2241                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
2242                 else
2243                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
2244         }
2245
2246         current_link_up = 0;
2247         current_speed = SPEED_INVALID;
2248         current_duplex = DUPLEX_INVALID;
2249
2250         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
2251                 u32 val;
2252
2253                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
2254                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
2255                 if (!(val & (1 << 10))) {
2256                         val |= (1 << 10);
2257                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2258                         goto relink;
2259                 }
2260         }
2261
2262         bmsr = 0;
2263         for (i = 0; i < 100; i++) {
2264                 tg3_readphy(tp, MII_BMSR, &bmsr);
2265                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2266                     (bmsr & BMSR_LSTATUS))
2267                         break;
2268                 udelay(40);
2269         }
2270
2271         if (bmsr & BMSR_LSTATUS) {
2272                 u32 aux_stat, bmcr;
2273
2274                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
2275                 for (i = 0; i < 2000; i++) {
2276                         udelay(10);
2277                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
2278                             aux_stat)
2279                                 break;
2280                 }
2281
2282                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
2283                                              &current_speed,
2284                                              &current_duplex);
2285
2286                 bmcr = 0;
2287                 for (i = 0; i < 200; i++) {
2288                         tg3_readphy(tp, MII_BMCR, &bmcr);
2289                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
2290                                 continue;
2291                         if (bmcr && bmcr != 0x7fff)
2292                                 break;
2293                         udelay(10);
2294                 }
2295
2296                 lcl_adv = 0;
2297                 rmt_adv = 0;
2298
2299                 tp->link_config.active_speed = current_speed;
2300                 tp->link_config.active_duplex = current_duplex;
2301
2302                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2303                         if ((bmcr & BMCR_ANENABLE) &&
2304                             tg3_copper_is_advertising_all(tp,
2305                                                 tp->link_config.advertising)) {
2306                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
2307                                                                   &rmt_adv))
2308                                         current_link_up = 1;
2309                         }
2310                 } else {
2311                         if (!(bmcr & BMCR_ANENABLE) &&
2312                             tp->link_config.speed == current_speed &&
2313                             tp->link_config.duplex == current_duplex &&
2314                             tp->link_config.flowctrl ==
2315                             tp->link_config.active_flowctrl) {
2316                                 current_link_up = 1;
2317                         }
2318                 }
2319
2320                 if (current_link_up == 1 &&
2321                     tp->link_config.active_duplex == DUPLEX_FULL)
2322                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2323         }
2324
2325 relink:
2326         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
2327                 u32 tmp;
2328
2329                 tg3_phy_copper_begin(tp);
2330
2331                 tg3_readphy(tp, MII_BMSR, &tmp);
2332                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
2333                     (tmp & BMSR_LSTATUS))
2334                         current_link_up = 1;
2335         }
2336
2337         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
2338         if (current_link_up == 1) {
2339                 if (tp->link_config.active_speed == SPEED_100 ||
2340                     tp->link_config.active_speed == SPEED_10)
2341                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
2342                 else
2343                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2344         } else
2345                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2346
2347         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2348         if (tp->link_config.active_duplex == DUPLEX_HALF)
2349                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2350
2351         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
2352                 if (current_link_up == 1 &&
2353                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
2354                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2355                 else
2356                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2357         }
2358
2359         /* ??? Without this setting Netgear GA302T PHY does not
2360          * ??? send/receive packets...
2361          */
2362         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2363             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2364                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2365                 tw32_f(MAC_MI_MODE, tp->mi_mode);
2366                 udelay(80);
2367         }
2368
2369         tw32_f(MAC_MODE, tp->mac_mode);
2370         udelay(40);
2371
2372         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2373                 /* Polled via timer. */
2374                 tw32_f(MAC_EVENT, 0);
2375         } else {
2376                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2377         }
2378         udelay(40);
2379
2380         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2381             current_link_up == 1 &&
2382             tp->link_config.active_speed == SPEED_1000 &&
2383             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2384              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2385                 udelay(120);
2386                 tw32_f(MAC_STATUS,
2387                      (MAC_STATUS_SYNC_CHANGED |
2388                       MAC_STATUS_CFG_CHANGED));
2389                 udelay(40);
2390                 tg3_write_mem(tp,
2391                               NIC_SRAM_FIRMWARE_MBOX,
2392                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2393         }
2394
2395         if (current_link_up != netif_carrier_ok(tp->dev)) {
2396                 if (current_link_up)
2397                         netif_carrier_on(tp->dev);
2398                 else
2399                         netif_carrier_off(tp->dev);
2400                 tg3_link_report(tp);
2401         }
2402
2403         return 0;
2404 }
2405
2406 struct tg3_fiber_aneginfo {
2407         int state;
2408 #define ANEG_STATE_UNKNOWN              0
2409 #define ANEG_STATE_AN_ENABLE            1
2410 #define ANEG_STATE_RESTART_INIT         2
2411 #define ANEG_STATE_RESTART              3
2412 #define ANEG_STATE_DISABLE_LINK_OK      4
2413 #define ANEG_STATE_ABILITY_DETECT_INIT  5
2414 #define ANEG_STATE_ABILITY_DETECT       6
2415 #define ANEG_STATE_ACK_DETECT_INIT      7
2416 #define ANEG_STATE_ACK_DETECT           8
2417 #define ANEG_STATE_COMPLETE_ACK_INIT    9
2418 #define ANEG_STATE_COMPLETE_ACK         10
2419 #define ANEG_STATE_IDLE_DETECT_INIT     11
2420 #define ANEG_STATE_IDLE_DETECT          12
2421 #define ANEG_STATE_LINK_OK              13
2422 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
2423 #define ANEG_STATE_NEXT_PAGE_WAIT       15
2424
2425         u32 flags;
2426 #define MR_AN_ENABLE            0x00000001
2427 #define MR_RESTART_AN           0x00000002
2428 #define MR_AN_COMPLETE          0x00000004
2429 #define MR_PAGE_RX              0x00000008
2430 #define MR_NP_LOADED            0x00000010
2431 #define MR_TOGGLE_TX            0x00000020
2432 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
2433 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
2434 #define MR_LP_ADV_SYM_PAUSE     0x00000100
2435 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
2436 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2437 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2438 #define MR_LP_ADV_NEXT_PAGE     0x00001000
2439 #define MR_TOGGLE_RX            0x00002000
2440 #define MR_NP_RX                0x00004000
2441
2442 #define MR_LINK_OK              0x80000000
2443
2444         unsigned long link_time, cur_time;
2445
2446         u32 ability_match_cfg;
2447         int ability_match_count;
2448
2449         char ability_match, idle_match, ack_match;
2450
2451         u32 txconfig, rxconfig;
2452 #define ANEG_CFG_NP             0x00000080
2453 #define ANEG_CFG_ACK            0x00000040
2454 #define ANEG_CFG_RF2            0x00000020
2455 #define ANEG_CFG_RF1            0x00000010
2456 #define ANEG_CFG_PS2            0x00000001
2457 #define ANEG_CFG_PS1            0x00008000
2458 #define ANEG_CFG_HD             0x00004000
2459 #define ANEG_CFG_FD             0x00002000
2460 #define ANEG_CFG_INVAL          0x00001f06
2461
2462 };
2463 #define ANEG_OK         0
2464 #define ANEG_DONE       1
2465 #define ANEG_TIMER_ENAB 2
2466 #define ANEG_FAILED     -1
2467
2468 #define ANEG_STATE_SETTLE_TIME  10000
2469
2470 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2471                                    struct tg3_fiber_aneginfo *ap)
2472 {
2473         u16 flowctrl;
2474         unsigned long delta;
2475         u32 rx_cfg_reg;
2476         int ret;
2477
2478         if (ap->state == ANEG_STATE_UNKNOWN) {
2479                 ap->rxconfig = 0;
2480                 ap->link_time = 0;
2481                 ap->cur_time = 0;
2482                 ap->ability_match_cfg = 0;
2483                 ap->ability_match_count = 0;
2484                 ap->ability_match = 0;
2485                 ap->idle_match = 0;
2486                 ap->ack_match = 0;
2487         }
2488         ap->cur_time++;
2489
2490         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2491                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2492
2493                 if (rx_cfg_reg != ap->ability_match_cfg) {
2494                         ap->ability_match_cfg = rx_cfg_reg;
2495                         ap->ability_match = 0;
2496                         ap->ability_match_count = 0;
2497                 } else {
2498                         if (++ap->ability_match_count > 1) {
2499                                 ap->ability_match = 1;
2500                                 ap->ability_match_cfg = rx_cfg_reg;
2501                         }
2502                 }
2503                 if (rx_cfg_reg & ANEG_CFG_ACK)
2504                         ap->ack_match = 1;
2505                 else
2506                         ap->ack_match = 0;
2507
2508                 ap->idle_match = 0;
2509         } else {
2510                 ap->idle_match = 1;
2511                 ap->ability_match_cfg = 0;
2512                 ap->ability_match_count = 0;
2513                 ap->ability_match = 0;
2514                 ap->ack_match = 0;
2515
2516                 rx_cfg_reg = 0;
2517         }
2518
2519         ap->rxconfig = rx_cfg_reg;
2520         ret = ANEG_OK;
2521
2522         switch(ap->state) {
2523         case ANEG_STATE_UNKNOWN:
2524                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2525                         ap->state = ANEG_STATE_AN_ENABLE;
2526
2527                 /* fallthru */
2528         case ANEG_STATE_AN_ENABLE:
2529                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2530                 if (ap->flags & MR_AN_ENABLE) {
2531                         ap->link_time = 0;
2532                         ap->cur_time = 0;
2533                         ap->ability_match_cfg = 0;
2534                         ap->ability_match_count = 0;
2535                         ap->ability_match = 0;
2536                         ap->idle_match = 0;
2537                         ap->ack_match = 0;
2538
2539                         ap->state = ANEG_STATE_RESTART_INIT;
2540                 } else {
2541                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
2542                 }
2543                 break;
2544
2545         case ANEG_STATE_RESTART_INIT:
2546                 ap->link_time = ap->cur_time;
2547                 ap->flags &= ~(MR_NP_LOADED);
2548                 ap->txconfig = 0;
2549                 tw32(MAC_TX_AUTO_NEG, 0);
2550                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2551                 tw32_f(MAC_MODE, tp->mac_mode);
2552                 udelay(40);
2553
2554                 ret = ANEG_TIMER_ENAB;
2555                 ap->state = ANEG_STATE_RESTART;
2556
2557                 /* fallthru */
2558         case ANEG_STATE_RESTART:
2559                 delta = ap->cur_time - ap->link_time;
2560                 if (delta > ANEG_STATE_SETTLE_TIME) {
2561                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2562                 } else {
2563                         ret = ANEG_TIMER_ENAB;
2564                 }
2565                 break;
2566
2567         case ANEG_STATE_DISABLE_LINK_OK:
2568                 ret = ANEG_DONE;
2569                 break;
2570
2571         case ANEG_STATE_ABILITY_DETECT_INIT:
2572                 ap->flags &= ~(MR_TOGGLE_TX);
2573                 ap->txconfig = ANEG_CFG_FD;
2574                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
2575                 if (flowctrl & ADVERTISE_1000XPAUSE)
2576                         ap->txconfig |= ANEG_CFG_PS1;
2577                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
2578                         ap->txconfig |= ANEG_CFG_PS2;
2579                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2580                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2581                 tw32_f(MAC_MODE, tp->mac_mode);
2582                 udelay(40);
2583
2584                 ap->state = ANEG_STATE_ABILITY_DETECT;
2585                 break;
2586
2587         case ANEG_STATE_ABILITY_DETECT:
2588                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2589                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
2590                 }
2591                 break;
2592
2593         case ANEG_STATE_ACK_DETECT_INIT:
2594                 ap->txconfig |= ANEG_CFG_ACK;
2595                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2596                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2597                 tw32_f(MAC_MODE, tp->mac_mode);
2598                 udelay(40);
2599
2600                 ap->state = ANEG_STATE_ACK_DETECT;
2601
2602                 /* fallthru */
2603         case ANEG_STATE_ACK_DETECT:
2604                 if (ap->ack_match != 0) {
2605                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2606                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2607                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2608                         } else {
2609                                 ap->state = ANEG_STATE_AN_ENABLE;
2610                         }
2611                 } else if (ap->ability_match != 0 &&
2612                            ap->rxconfig == 0) {
2613                         ap->state = ANEG_STATE_AN_ENABLE;
2614                 }
2615                 break;
2616
2617         case ANEG_STATE_COMPLETE_ACK_INIT:
2618                 if (ap->rxconfig & ANEG_CFG_INVAL) {
2619                         ret = ANEG_FAILED;
2620                         break;
2621                 }
2622                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2623                                MR_LP_ADV_HALF_DUPLEX |
2624                                MR_LP_ADV_SYM_PAUSE |
2625                                MR_LP_ADV_ASYM_PAUSE |
2626                                MR_LP_ADV_REMOTE_FAULT1 |
2627                                MR_LP_ADV_REMOTE_FAULT2 |
2628                                MR_LP_ADV_NEXT_PAGE |
2629                                MR_TOGGLE_RX |
2630                                MR_NP_RX);
2631                 if (ap->rxconfig & ANEG_CFG_FD)
2632                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2633                 if (ap->rxconfig & ANEG_CFG_HD)
2634                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2635                 if (ap->rxconfig & ANEG_CFG_PS1)
2636                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
2637                 if (ap->rxconfig & ANEG_CFG_PS2)
2638                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2639                 if (ap->rxconfig & ANEG_CFG_RF1)
2640                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2641                 if (ap->rxconfig & ANEG_CFG_RF2)
2642                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2643                 if (ap->rxconfig & ANEG_CFG_NP)
2644                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
2645
2646                 ap->link_time = ap->cur_time;
2647
2648                 ap->flags ^= (MR_TOGGLE_TX);
2649                 if (ap->rxconfig & 0x0008)
2650                         ap->flags |= MR_TOGGLE_RX;
2651                 if (ap->rxconfig & ANEG_CFG_NP)
2652                         ap->flags |= MR_NP_RX;
2653                 ap->flags |= MR_PAGE_RX;
2654
2655                 ap->state = ANEG_STATE_COMPLETE_ACK;
2656                 ret = ANEG_TIMER_ENAB;
2657                 break;
2658
2659         case ANEG_STATE_COMPLETE_ACK:
2660                 if (ap->ability_match != 0 &&
2661                     ap->rxconfig == 0) {
2662                         ap->state = ANEG_STATE_AN_ENABLE;
2663                         break;
2664                 }
2665                 delta = ap->cur_time - ap->link_time;
2666                 if (delta > ANEG_STATE_SETTLE_TIME) {
2667                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2668                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2669                         } else {
2670                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2671                                     !(ap->flags & MR_NP_RX)) {
2672                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2673                                 } else {
2674                                         ret = ANEG_FAILED;
2675                                 }
2676                         }
2677                 }
2678                 break;
2679
2680         case ANEG_STATE_IDLE_DETECT_INIT:
2681                 ap->link_time = ap->cur_time;
2682                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2683                 tw32_f(MAC_MODE, tp->mac_mode);
2684                 udelay(40);
2685
2686                 ap->state = ANEG_STATE_IDLE_DETECT;
2687                 ret = ANEG_TIMER_ENAB;
2688                 break;
2689
2690         case ANEG_STATE_IDLE_DETECT:
2691                 if (ap->ability_match != 0 &&
2692                     ap->rxconfig == 0) {
2693                         ap->state = ANEG_STATE_AN_ENABLE;
2694                         break;
2695                 }
2696                 delta = ap->cur_time - ap->link_time;
2697                 if (delta > ANEG_STATE_SETTLE_TIME) {
2698                         /* XXX another gem from the Broadcom driver :( */
2699                         ap->state = ANEG_STATE_LINK_OK;
2700                 }
2701                 break;
2702
2703         case ANEG_STATE_LINK_OK:
2704                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2705                 ret = ANEG_DONE;
2706                 break;
2707
2708         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2709                 /* ??? unimplemented */
2710                 break;
2711
2712         case ANEG_STATE_NEXT_PAGE_WAIT:
2713                 /* ??? unimplemented */
2714                 break;
2715
2716         default:
2717                 ret = ANEG_FAILED;
2718                 break;
2719         };
2720
2721         return ret;
2722 }
2723
2724 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
2725 {
2726         int res = 0;
2727         struct tg3_fiber_aneginfo aninfo;
2728         int status = ANEG_FAILED;
2729         unsigned int tick;
2730         u32 tmp;
2731
2732         tw32_f(MAC_TX_AUTO_NEG, 0);
2733
2734         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2735         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2736         udelay(40);
2737
2738         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2739         udelay(40);
2740
2741         memset(&aninfo, 0, sizeof(aninfo));
2742         aninfo.flags |= MR_AN_ENABLE;
2743         aninfo.state = ANEG_STATE_UNKNOWN;
2744         aninfo.cur_time = 0;
2745         tick = 0;
2746         while (++tick < 195000) {
2747                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2748                 if (status == ANEG_DONE || status == ANEG_FAILED)
2749                         break;
2750
2751                 udelay(1);
2752         }
2753
2754         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2755         tw32_f(MAC_MODE, tp->mac_mode);
2756         udelay(40);
2757
2758         *txflags = aninfo.txconfig;
2759         *rxflags = aninfo.flags;
2760
2761         if (status == ANEG_DONE &&
2762             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2763                              MR_LP_ADV_FULL_DUPLEX)))
2764                 res = 1;
2765
2766         return res;
2767 }
2768
2769 static void tg3_init_bcm8002(struct tg3 *tp)
2770 {
2771         u32 mac_status = tr32(MAC_STATUS);
2772         int i;
2773
2774         /* Reset when initting first time or we have a link. */
2775         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2776             !(mac_status & MAC_STATUS_PCS_SYNCED))
2777                 return;
2778
2779         /* Set PLL lock range. */
2780         tg3_writephy(tp, 0x16, 0x8007);
2781
2782         /* SW reset */
2783         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2784
2785         /* Wait for reset to complete. */
2786         /* XXX schedule_timeout() ... */
2787         for (i = 0; i < 500; i++)
2788                 udelay(10);
2789
2790         /* Config mode; select PMA/Ch 1 regs. */
2791         tg3_writephy(tp, 0x10, 0x8411);
2792
2793         /* Enable auto-lock and comdet, select txclk for tx. */
2794         tg3_writephy(tp, 0x11, 0x0a10);
2795
2796         tg3_writephy(tp, 0x18, 0x00a0);
2797         tg3_writephy(tp, 0x16, 0x41ff);
2798
2799         /* Assert and deassert POR. */
2800         tg3_writephy(tp, 0x13, 0x0400);
2801         udelay(40);
2802         tg3_writephy(tp, 0x13, 0x0000);
2803
2804         tg3_writephy(tp, 0x11, 0x0a50);
2805         udelay(40);
2806         tg3_writephy(tp, 0x11, 0x0a10);
2807
2808         /* Wait for signal to stabilize */
2809         /* XXX schedule_timeout() ... */
2810         for (i = 0; i < 15000; i++)
2811                 udelay(10);
2812
2813         /* Deselect the channel register so we can read the PHYID
2814          * later.
2815          */
2816         tg3_writephy(tp, 0x10, 0x8011);
2817 }
2818
2819 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2820 {
2821         u16 flowctrl;
2822         u32 sg_dig_ctrl, sg_dig_status;
2823         u32 serdes_cfg, expected_sg_dig_ctrl;
2824         int workaround, port_a;
2825         int current_link_up;
2826
2827         serdes_cfg = 0;
2828         expected_sg_dig_ctrl = 0;
2829         workaround = 0;
2830         port_a = 1;
2831         current_link_up = 0;
2832
2833         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2834             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2835                 workaround = 1;
2836                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2837                         port_a = 0;
2838
2839                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2840                 /* preserve bits 20-23 for voltage regulator */
2841                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2842         }
2843
2844         sg_dig_ctrl = tr32(SG_DIG_CTRL);
2845
2846         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2847                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
2848                         if (workaround) {
2849                                 u32 val = serdes_cfg;
2850
2851                                 if (port_a)
2852                                         val |= 0xc010000;
2853                                 else
2854                                         val |= 0x4010000;
2855                                 tw32_f(MAC_SERDES_CFG, val);
2856                         }
2857
2858                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
2859                 }
2860                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2861                         tg3_setup_flow_control(tp, 0, 0);
2862                         current_link_up = 1;
2863                 }
2864                 goto out;
2865         }
2866
2867         /* Want auto-negotiation.  */
2868         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
2869
2870         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
2871         if (flowctrl & ADVERTISE_1000XPAUSE)
2872                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
2873         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
2874                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
2875
2876         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2877                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
2878                     tp->serdes_counter &&
2879                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
2880                                     MAC_STATUS_RCVD_CFG)) ==
2881                      MAC_STATUS_PCS_SYNCED)) {
2882                         tp->serdes_counter--;
2883                         current_link_up = 1;
2884                         goto out;
2885                 }
2886 restart_autoneg:
2887                 if (workaround)
2888                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2889                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
2890                 udelay(5);
2891                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2892
2893                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2894                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2895         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2896                                  MAC_STATUS_SIGNAL_DET)) {
2897                 sg_dig_status = tr32(SG_DIG_STATUS);
2898                 mac_status = tr32(MAC_STATUS);
2899
2900                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
2901                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
2902                         u32 local_adv = 0, remote_adv = 0;
2903
2904                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
2905                                 local_adv |= ADVERTISE_1000XPAUSE;
2906                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
2907                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
2908
2909                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
2910                                 remote_adv |= LPA_1000XPAUSE;
2911                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
2912                                 remote_adv |= LPA_1000XPAUSE_ASYM;
2913
2914                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2915                         current_link_up = 1;
2916                         tp->serdes_counter = 0;
2917                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2918                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
2919                         if (tp->serdes_counter)
2920                                 tp->serdes_counter--;
2921                         else {
2922                                 if (workaround) {
2923                                         u32 val = serdes_cfg;
2924
2925                                         if (port_a)
2926                                                 val |= 0xc010000;
2927                                         else
2928                                                 val |= 0x4010000;
2929
2930                                         tw32_f(MAC_SERDES_CFG, val);
2931                                 }
2932
2933                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
2934                                 udelay(40);
2935
2936                                 /* Link parallel detection - link is up */
2937                                 /* only if we have PCS_SYNC and not */
2938                                 /* receiving config code words */
2939                                 mac_status = tr32(MAC_STATUS);
2940                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2941                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
2942                                         tg3_setup_flow_control(tp, 0, 0);
2943                                         current_link_up = 1;
2944                                         tp->tg3_flags2 |=
2945                                                 TG3_FLG2_PARALLEL_DETECT;
2946                                         tp->serdes_counter =
2947                                                 SERDES_PARALLEL_DET_TIMEOUT;
2948                                 } else
2949                                         goto restart_autoneg;
2950                         }
2951                 }
2952         } else {
2953                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2954                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2955         }
2956
2957 out:
2958         return current_link_up;
2959 }
2960
2961 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2962 {
2963         int current_link_up = 0;
2964
2965         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
2966                 goto out;
2967
2968         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2969                 u32 txflags, rxflags;
2970                 int i;
2971
2972                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
2973                         u32 local_adv = 0, remote_adv = 0;
2974
2975                         if (txflags & ANEG_CFG_PS1)
2976                                 local_adv |= ADVERTISE_1000XPAUSE;
2977                         if (txflags & ANEG_CFG_PS2)
2978                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
2979
2980                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
2981                                 remote_adv |= LPA_1000XPAUSE;
2982                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
2983                                 remote_adv |= LPA_1000XPAUSE_ASYM;
2984
2985                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2986
2987                         current_link_up = 1;
2988                 }
2989                 for (i = 0; i < 30; i++) {
2990                         udelay(20);
2991                         tw32_f(MAC_STATUS,
2992                                (MAC_STATUS_SYNC_CHANGED |
2993                                 MAC_STATUS_CFG_CHANGED));
2994                         udelay(40);
2995                         if ((tr32(MAC_STATUS) &
2996                              (MAC_STATUS_SYNC_CHANGED |
2997                               MAC_STATUS_CFG_CHANGED)) == 0)
2998                                 break;
2999                 }
3000
3001                 mac_status = tr32(MAC_STATUS);
3002                 if (current_link_up == 0 &&
3003                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3004                     !(mac_status & MAC_STATUS_RCVD_CFG))
3005                         current_link_up = 1;
3006         } else {
3007                 tg3_setup_flow_control(tp, 0, 0);
3008
3009                 /* Forcing 1000FD link up. */
3010                 current_link_up = 1;
3011
3012                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3013                 udelay(40);
3014
3015                 tw32_f(MAC_MODE, tp->mac_mode);
3016                 udelay(40);
3017         }
3018
3019 out:
3020         return current_link_up;
3021 }
3022
3023 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3024 {
3025         u32 orig_pause_cfg;
3026         u16 orig_active_speed;
3027         u8 orig_active_duplex;
3028         u32 mac_status;
3029         int current_link_up;
3030         int i;
3031
3032         orig_pause_cfg = tp->link_config.active_flowctrl;
3033         orig_active_speed = tp->link_config.active_speed;
3034         orig_active_duplex = tp->link_config.active_duplex;
3035
3036         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3037             netif_carrier_ok(tp->dev) &&
3038             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3039                 mac_status = tr32(MAC_STATUS);
3040                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3041                                MAC_STATUS_SIGNAL_DET |
3042                                MAC_STATUS_CFG_CHANGED |
3043                                MAC_STATUS_RCVD_CFG);
3044                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3045                                    MAC_STATUS_SIGNAL_DET)) {
3046                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3047                                             MAC_STATUS_CFG_CHANGED));
3048                         return 0;
3049                 }
3050         }
3051
3052         tw32_f(MAC_TX_AUTO_NEG, 0);
3053
3054         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3055         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3056         tw32_f(MAC_MODE, tp->mac_mode);
3057         udelay(40);
3058
3059         if (tp->phy_id == PHY_ID_BCM8002)
3060                 tg3_init_bcm8002(tp);
3061
3062         /* Enable link change event even when serdes polling.  */
3063         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3064         udelay(40);
3065
3066         current_link_up = 0;
3067         mac_status = tr32(MAC_STATUS);
3068
3069         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3070                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3071         else
3072                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3073
3074         tp->hw_status->status =
3075                 (SD_STATUS_UPDATED |
3076                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3077
3078         for (i = 0; i < 100; i++) {
3079                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3080                                     MAC_STATUS_CFG_CHANGED));
3081                 udelay(5);
3082                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3083                                          MAC_STATUS_CFG_CHANGED |
3084                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3085                         break;
3086         }
3087
3088         mac_status = tr32(MAC_STATUS);
3089         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3090                 current_link_up = 0;
3091                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3092                     tp->serdes_counter == 0) {
3093                         tw32_f(MAC_MODE, (tp->mac_mode |
3094                                           MAC_MODE_SEND_CONFIGS));
3095                         udelay(1);
3096                         tw32_f(MAC_MODE, tp->mac_mode);
3097                 }
3098         }
3099
3100         if (current_link_up == 1) {
3101                 tp->link_config.active_speed = SPEED_1000;
3102                 tp->link_config.active_duplex = DUPLEX_FULL;
3103                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3104                                     LED_CTRL_LNKLED_OVERRIDE |
3105                                     LED_CTRL_1000MBPS_ON));
3106         } else {
3107                 tp->link_config.active_speed = SPEED_INVALID;
3108                 tp->link_config.active_duplex = DUPLEX_INVALID;
3109                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3110                                     LED_CTRL_LNKLED_OVERRIDE |
3111                                     LED_CTRL_TRAFFIC_OVERRIDE));
3112         }
3113
3114         if (current_link_up != netif_carrier_ok(tp->dev)) {
3115                 if (current_link_up)
3116                         netif_carrier_on(tp->dev);
3117                 else
3118                         netif_carrier_off(tp->dev);
3119                 tg3_link_report(tp);
3120         } else {
3121                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
3122                 if (orig_pause_cfg != now_pause_cfg ||
3123                     orig_active_speed != tp->link_config.active_speed ||
3124                     orig_active_duplex != tp->link_config.active_duplex)
3125                         tg3_link_report(tp);
3126         }
3127
3128         return 0;
3129 }
3130
3131 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3132 {
3133         int current_link_up, err = 0;
3134         u32 bmsr, bmcr;
3135         u16 current_speed;
3136         u8 current_duplex;
3137         u32 local_adv, remote_adv;
3138
3139         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3140         tw32_f(MAC_MODE, tp->mac_mode);
3141         udelay(40);
3142
3143         tw32(MAC_EVENT, 0);
3144
3145         tw32_f(MAC_STATUS,
3146              (MAC_STATUS_SYNC_CHANGED |
3147               MAC_STATUS_CFG_CHANGED |
3148               MAC_STATUS_MI_COMPLETION |
3149               MAC_STATUS_LNKSTATE_CHANGED));
3150         udelay(40);
3151
3152         if (force_reset)
3153                 tg3_phy_reset(tp);
3154
3155         current_link_up = 0;
3156         current_speed = SPEED_INVALID;
3157         current_duplex = DUPLEX_INVALID;
3158
3159         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3160         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3161         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3162                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3163                         bmsr |= BMSR_LSTATUS;
3164                 else
3165                         bmsr &= ~BMSR_LSTATUS;
3166         }
3167
3168         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3169
3170         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
3171             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3172                 /* do nothing, just check for link up at the end */
3173         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3174                 u32 adv, new_adv;
3175
3176                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3177                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
3178                                   ADVERTISE_1000XPAUSE |
3179                                   ADVERTISE_1000XPSE_ASYM |
3180                                   ADVERTISE_SLCT);
3181
3182                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3183
3184                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
3185                         new_adv |= ADVERTISE_1000XHALF;
3186                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
3187                         new_adv |= ADVERTISE_1000XFULL;
3188
3189                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
3190                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
3191                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
3192                         tg3_writephy(tp, MII_BMCR, bmcr);
3193
3194                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3195                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
3196                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3197
3198                         return err;
3199                 }
3200         } else {
3201                 u32 new_bmcr;
3202
3203                 bmcr &= ~BMCR_SPEED1000;
3204                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
3205
3206                 if (tp->link_config.duplex == DUPLEX_FULL)
3207                         new_bmcr |= BMCR_FULLDPLX;
3208
3209                 if (new_bmcr != bmcr) {
3210                         /* BMCR_SPEED1000 is a reserved bit that needs
3211                          * to be set on write.
3212                          */
3213                         new_bmcr |= BMCR_SPEED1000;
3214
3215                         /* Force a linkdown */
3216                         if (netif_carrier_ok(tp->dev)) {
3217                                 u32 adv;
3218
3219                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3220                                 adv &= ~(ADVERTISE_1000XFULL |
3221                                          ADVERTISE_1000XHALF |
3222                                          ADVERTISE_SLCT);
3223                                 tg3_writephy(tp, MII_ADVERTISE, adv);
3224                                 tg3_writephy(tp, MII_BMCR, bmcr |
3225                                                            BMCR_ANRESTART |
3226                                                            BMCR_ANENABLE);
3227                                 udelay(10);
3228                                 netif_carrier_off(tp->dev);
3229                         }
3230                         tg3_writephy(tp, MII_BMCR, new_bmcr);
3231                         bmcr = new_bmcr;
3232                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3233                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3234                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
3235                             ASIC_REV_5714) {
3236                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3237                                         bmsr |= BMSR_LSTATUS;
3238                                 else
3239                                         bmsr &= ~BMSR_LSTATUS;
3240                         }
3241                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3242                 }
3243         }
3244
3245         if (bmsr & BMSR_LSTATUS) {
3246                 current_speed = SPEED_1000;
3247                 current_link_up = 1;
3248                 if (bmcr & BMCR_FULLDPLX)
3249                         current_duplex = DUPLEX_FULL;
3250                 else
3251                         current_duplex = DUPLEX_HALF;
3252
3253                 local_adv = 0;
3254                 remote_adv = 0;
3255
3256                 if (bmcr & BMCR_ANENABLE) {
3257                         u32 common;
3258
3259                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
3260                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
3261                         common = local_adv & remote_adv;
3262                         if (common & (ADVERTISE_1000XHALF |
3263                                       ADVERTISE_1000XFULL)) {
3264                                 if (common & ADVERTISE_1000XFULL)
3265                                         current_duplex = DUPLEX_FULL;
3266                                 else
3267                                         current_duplex = DUPLEX_HALF;
3268                         }
3269                         else
3270                                 current_link_up = 0;
3271                 }
3272         }
3273
3274         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
3275                 tg3_setup_flow_control(tp, local_adv, remote_adv);
3276
3277         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3278         if (tp->link_config.active_duplex == DUPLEX_HALF)
3279                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3280
3281         tw32_f(MAC_MODE, tp->mac_mode);
3282         udelay(40);
3283
3284         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3285
3286         tp->link_config.active_speed = current_speed;
3287         tp->link_config.active_duplex = current_duplex;
3288
3289         if (current_link_up != netif_carrier_ok(tp->dev)) {
3290                 if (current_link_up)
3291                         netif_carrier_on(tp->dev);
3292                 else {
3293                         netif_carrier_off(tp->dev);
3294                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3295                 }
3296                 tg3_link_report(tp);
3297         }
3298         return err;
3299 }
3300
3301 static void tg3_serdes_parallel_detect(struct tg3 *tp)
3302 {
3303         if (tp->serdes_counter) {
3304                 /* Give autoneg time to complete. */
3305                 tp->serdes_counter--;
3306                 return;
3307         }
3308         if (!netif_carrier_ok(tp->dev) &&
3309             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
3310                 u32 bmcr;
3311
3312                 tg3_readphy(tp, MII_BMCR, &bmcr);
3313                 if (bmcr & BMCR_ANENABLE) {
3314                         u32 phy1, phy2;
3315
3316                         /* Select shadow register 0x1f */
3317                         tg3_writephy(tp, 0x1c, 0x7c00);
3318                         tg3_readphy(tp, 0x1c, &phy1);
3319
3320                         /* Select expansion interrupt status register */
3321                         tg3_writephy(tp, 0x17, 0x0f01);
3322                         tg3_readphy(tp, 0x15, &phy2);
3323                         tg3_readphy(tp, 0x15, &phy2);
3324
3325                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
3326                                 /* We have signal detect and not receiving
3327                                  * config code words, link is up by parallel
3328                                  * detection.
3329                                  */
3330
3331                                 bmcr &= ~BMCR_ANENABLE;
3332                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
3333                                 tg3_writephy(tp, MII_BMCR, bmcr);
3334                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
3335                         }
3336                 }
3337         }
3338         else if (netif_carrier_ok(tp->dev) &&
3339                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
3340                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3341                 u32 phy2;
3342
3343                 /* Select expansion interrupt status register */
3344                 tg3_writephy(tp, 0x17, 0x0f01);
3345                 tg3_readphy(tp, 0x15, &phy2);
3346                 if (phy2 & 0x20) {
3347                         u32 bmcr;
3348
3349                         /* Config code words received, turn on autoneg. */
3350                         tg3_readphy(tp, MII_BMCR, &bmcr);
3351                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
3352
3353                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3354
3355                 }
3356         }
3357 }
3358
3359 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
3360 {
3361         int err;
3362
3363         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
3364                 err = tg3_setup_fiber_phy(tp, force_reset);
3365         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
3366                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
3367         } else {
3368                 err = tg3_setup_copper_phy(tp, force_reset);
3369         }
3370
3371         if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
3372             tp->pci_chip_rev_id == CHIPREV_ID_5784_A1) {
3373                 u32 val, scale;
3374
3375                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
3376                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
3377                         scale = 65;
3378                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
3379                         scale = 6;
3380                 else
3381                         scale = 12;
3382
3383                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
3384                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
3385                 tw32(GRC_MISC_CFG, val);
3386         }
3387
3388         if (tp->link_config.active_speed == SPEED_1000 &&
3389             tp->link_config.active_duplex == DUPLEX_HALF)
3390                 tw32(MAC_TX_LENGTHS,
3391                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3392                       (6 << TX_LENGTHS_IPG_SHIFT) |
3393                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3394         else
3395                 tw32(MAC_TX_LENGTHS,
3396                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3397                       (6 << TX_LENGTHS_IPG_SHIFT) |
3398                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3399
3400         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3401                 if (netif_carrier_ok(tp->dev)) {
3402                         tw32(HOSTCC_STAT_COAL_TICKS,
3403                              tp->coal.stats_block_coalesce_usecs);
3404                 } else {
3405                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
3406                 }
3407         }
3408
3409         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
3410                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
3411                 if (!netif_carrier_ok(tp->dev))
3412                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
3413                               tp->pwrmgmt_thresh;
3414                 else
3415                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
3416                 tw32(PCIE_PWR_MGMT_THRESH, val);
3417         }
3418
3419         return err;
3420 }
3421
3422 /* This is called whenever we suspect that the system chipset is re-
3423  * ordering the sequence of MMIO to the tx send mailbox. The symptom
3424  * is bogus tx completions. We try to recover by setting the
3425  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3426  * in the workqueue.
3427  */
3428 static void tg3_tx_recover(struct tg3 *tp)
3429 {
3430         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3431                tp->write32_tx_mbox == tg3_write_indirect_mbox);
3432
3433         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3434                "mapped I/O cycles to the network device, attempting to "
3435                "recover. Please report the problem to the driver maintainer "
3436                "and include system chipset information.\n", tp->dev->name);
3437
3438         spin_lock(&tp->lock);
3439         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3440         spin_unlock(&tp->lock);
3441 }
3442
3443 static inline u32 tg3_tx_avail(struct tg3 *tp)
3444 {
3445         smp_mb();
3446         return (tp->tx_pending -
3447                 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3448 }
3449
3450 /* Tigon3 never reports partial packet sends.  So we do not
3451  * need special logic to handle SKBs that have not had all
3452  * of their frags sent yet, like SunGEM does.
3453  */
3454 static void tg3_tx(struct tg3 *tp)
3455 {
3456         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3457         u32 sw_idx = tp->tx_cons;
3458
3459         while (sw_idx != hw_idx) {
3460                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3461                 struct sk_buff *skb = ri->skb;
3462                 int i, tx_bug = 0;
3463
3464                 if (unlikely(skb == NULL)) {
3465                         tg3_tx_recover(tp);
3466                         return;
3467                 }
3468
3469                 pci_unmap_single(tp->pdev,
3470                                  pci_unmap_addr(ri, mapping),
3471                                  skb_headlen(skb),
3472                                  PCI_DMA_TODEVICE);
3473
3474                 ri->skb = NULL;
3475
3476                 sw_idx = NEXT_TX(sw_idx);
3477
3478                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3479                         ri = &tp->tx_buffers[sw_idx];
3480                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3481                                 tx_bug = 1;
3482
3483                         pci_unmap_page(tp->pdev,
3484                                        pci_unmap_addr(ri, mapping),
3485                                        skb_shinfo(skb)->frags[i].size,
3486                                        PCI_DMA_TODEVICE);
3487
3488                         sw_idx = NEXT_TX(sw_idx);
3489                 }
3490
3491                 dev_kfree_skb(skb);
3492
3493                 if (unlikely(tx_bug)) {
3494                         tg3_tx_recover(tp);
3495                         return;
3496                 }
3497         }
3498
3499         tp->tx_cons = sw_idx;
3500
3501         /* Need to make the tx_cons update visible to tg3_start_xmit()
3502          * before checking for netif_queue_stopped().  Without the
3503          * memory barrier, there is a small possibility that tg3_start_xmit()
3504          * will miss it and cause the queue to be stopped forever.
3505          */
3506         smp_mb();
3507
3508         if (unlikely(netif_queue_stopped(tp->dev) &&
3509                      (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3510                 netif_tx_lock(tp->dev);
3511                 if (netif_queue_stopped(tp->dev) &&
3512                     (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3513                         netif_wake_queue(tp->dev);
3514                 netif_tx_unlock(tp->dev);
3515         }
3516 }
3517
3518 /* Returns size of skb allocated or < 0 on error.
3519  *
3520  * We only need to fill in the address because the other members
3521  * of the RX descriptor are invariant, see tg3_init_rings.
3522  *
3523  * Note the purposeful assymetry of cpu vs. chip accesses.  For
3524  * posting buffers we only dirty the first cache line of the RX
3525  * descriptor (containing the address).  Whereas for the RX status
3526  * buffers the cpu only reads the last cacheline of the RX descriptor
3527  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3528  */
3529 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3530                             int src_idx, u32 dest_idx_unmasked)
3531 {
3532         struct tg3_rx_buffer_desc *desc;
3533         struct ring_info *map, *src_map;
3534         struct sk_buff *skb;
3535         dma_addr_t mapping;
3536         int skb_size, dest_idx;
3537
3538         src_map = NULL;
3539         switch (opaque_key) {
3540         case RXD_OPAQUE_RING_STD:
3541                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3542                 desc = &tp->rx_std[dest_idx];
3543                 map = &tp->rx_std_buffers[dest_idx];
3544                 if (src_idx >= 0)
3545                         src_map = &tp->rx_std_buffers[src_idx];
3546                 skb_size = tp->rx_pkt_buf_sz;
3547                 break;
3548
3549         case RXD_OPAQUE_RING_JUMBO:
3550                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3551                 desc = &tp->rx_jumbo[dest_idx];
3552                 map = &tp->rx_jumbo_buffers[dest_idx];
3553                 if (src_idx >= 0)
3554                         src_map = &tp->rx_jumbo_buffers[src_idx];
3555                 skb_size = RX_JUMBO_PKT_BUF_SZ;
3556                 break;
3557
3558         default:
3559                 return -EINVAL;
3560         };
3561
3562         /* Do not overwrite any of the map or rp information
3563          * until we are sure we can commit to a new buffer.
3564          *
3565          * Callers depend upon this behavior and assume that
3566          * we leave everything unchanged if we fail.
3567          */
3568         skb = netdev_alloc_skb(tp->dev, skb_size);
3569         if (skb == NULL)
3570                 return -ENOMEM;
3571
3572         skb_reserve(skb, tp->rx_offset);
3573
3574         mapping = pci_map_single(tp->pdev, skb->data,
3575                                  skb_size - tp->rx_offset,
3576                                  PCI_DMA_FROMDEVICE);
3577
3578         map->skb = skb;
3579         pci_unmap_addr_set(map, mapping, mapping);
3580
3581         if (src_map != NULL)
3582                 src_map->skb = NULL;
3583
3584         desc->addr_hi = ((u64)mapping >> 32);
3585         desc->addr_lo = ((u64)mapping & 0xffffffff);
3586
3587         return skb_size;
3588 }
3589
3590 /* We only need to move over in the address because the other
3591  * members of the RX descriptor are invariant.  See notes above
3592  * tg3_alloc_rx_skb for full details.
3593  */
3594 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3595                            int src_idx, u32 dest_idx_unmasked)
3596 {
3597         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3598         struct ring_info *src_map, *dest_map;
3599         int dest_idx;
3600
3601         switch (opaque_key) {
3602         case RXD_OPAQUE_RING_STD:
3603                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3604                 dest_desc = &tp->rx_std[dest_idx];
3605                 dest_map = &tp->rx_std_buffers[dest_idx];
3606                 src_desc = &tp->rx_std[src_idx];
3607                 src_map = &tp->rx_std_buffers[src_idx];
3608                 break;
3609
3610         case RXD_OPAQUE_RING_JUMBO:
3611                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3612                 dest_desc = &tp->rx_jumbo[dest_idx];
3613                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3614                 src_desc = &tp->rx_jumbo[src_idx];
3615                 src_map = &tp->rx_jumbo_buffers[src_idx];
3616                 break;
3617
3618         default:
3619                 return;
3620         };
3621
3622         dest_map->skb = src_map->skb;
3623         pci_unmap_addr_set(dest_map, mapping,
3624                            pci_unmap_addr(src_map, mapping));
3625         dest_desc->addr_hi = src_desc->addr_hi;
3626         dest_desc->addr_lo = src_desc->addr_lo;
3627
3628         src_map->skb = NULL;
3629 }
3630
3631 #if TG3_VLAN_TAG_USED
3632 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3633 {
3634         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3635 }
3636 #endif
3637
3638 /* The RX ring scheme is composed of multiple rings which post fresh
3639  * buffers to the chip, and one special ring the chip uses to report
3640  * status back to the host.
3641  *
3642  * The special ring reports the status of received packets to the
3643  * host.  The chip does not write into the original descriptor the
3644  * RX buffer was obtained from.  The chip simply takes the original
3645  * descriptor as provided by the host, updates the status and length
3646  * field, then writes this into the next status ring entry.
3647  *
3648  * Each ring the host uses to post buffers to the chip is described
3649  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
3650  * it is first placed into the on-chip ram.  When the packet's length
3651  * is known, it walks down the TG3_BDINFO entries to select the ring.
3652  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3653  * which is within the range of the new packet's length is chosen.
3654  *
3655  * The "separate ring for rx status" scheme may sound queer, but it makes
3656  * sense from a cache coherency perspective.  If only the host writes
3657  * to the buffer post rings, and only the chip writes to the rx status
3658  * rings, then cache lines never move beyond shared-modified state.
3659  * If both the host and chip were to write into the same ring, cache line
3660  * eviction could occur since both entities want it in an exclusive state.
3661  */
3662 static int tg3_rx(struct tg3 *tp, int budget)
3663 {
3664         u32 work_mask, rx_std_posted = 0;
3665         u32 sw_idx = tp->rx_rcb_ptr;
3666         u16 hw_idx;
3667         int received;
3668
3669         hw_idx = tp->hw_status->idx[0].rx_producer;
3670         /*
3671          * We need to order the read of hw_idx and the read of
3672          * the opaque cookie.
3673          */
3674         rmb();
3675         work_mask = 0;
3676         received = 0;
3677         while (sw_idx != hw_idx && budget > 0) {
3678                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3679                 unsigned int len;
3680                 struct sk_buff *skb;
3681                 dma_addr_t dma_addr;
3682                 u32 opaque_key, desc_idx, *post_ptr;
3683
3684                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3685                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3686                 if (opaque_key == RXD_OPAQUE_RING_STD) {
3687                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3688                                                   mapping);
3689                         skb = tp->rx_std_buffers[desc_idx].skb;
3690                         post_ptr = &tp->rx_std_ptr;
3691                         rx_std_posted++;
3692                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3693                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3694                                                   mapping);
3695                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
3696                         post_ptr = &tp->rx_jumbo_ptr;
3697                 }
3698                 else {
3699                         goto next_pkt_nopost;
3700                 }
3701
3702                 work_mask |= opaque_key;
3703
3704                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3705                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3706                 drop_it:
3707                         tg3_recycle_rx(tp, opaque_key,
3708                                        desc_idx, *post_ptr);
3709                 drop_it_no_recycle:
3710                         /* Other statistics kept track of by card. */
3711                         tp->net_stats.rx_dropped++;
3712                         goto next_pkt;
3713                 }
3714
3715                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3716
3717                 if (len > RX_COPY_THRESHOLD
3718                         && tp->rx_offset == 2
3719                         /* rx_offset != 2 iff this is a 5701 card running
3720                          * in PCI-X mode [see tg3_get_invariants()] */
3721                 ) {
3722                         int skb_size;
3723
3724                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3725                                                     desc_idx, *post_ptr);
3726                         if (skb_size < 0)
3727                                 goto drop_it;
3728
3729                         pci_unmap_single(tp->pdev, dma_addr,
3730                                          skb_size - tp->rx_offset,
3731                                          PCI_DMA_FROMDEVICE);
3732
3733                         skb_put(skb, len);
3734                 } else {
3735                         struct sk_buff *copy_skb;
3736
3737                         tg3_recycle_rx(tp, opaque_key,
3738                                        desc_idx, *post_ptr);
3739
3740                         copy_skb = netdev_alloc_skb(tp->dev, len + 2);
3741                         if (copy_skb == NULL)
3742                                 goto drop_it_no_recycle;
3743
3744                         skb_reserve(copy_skb, 2);
3745                         skb_put(copy_skb, len);
3746                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3747                         skb_copy_from_linear_data(skb, copy_skb->data, len);
3748                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3749
3750                         /* We'll reuse the original ring buffer. */
3751                         skb = copy_skb;
3752                 }
3753
3754                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3755                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3756                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3757                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
3758                         skb->ip_summed = CHECKSUM_UNNECESSARY;
3759                 else
3760                         skb->ip_summed = CHECKSUM_NONE;
3761
3762                 skb->protocol = eth_type_trans(skb, tp->dev);
3763 #if TG3_VLAN_TAG_USED
3764                 if (tp->vlgrp != NULL &&
3765                     desc->type_flags & RXD_FLAG_VLAN) {
3766                         tg3_vlan_rx(tp, skb,
3767                                     desc->err_vlan & RXD_VLAN_MASK);
3768                 } else
3769 #endif
3770                         netif_receive_skb(skb);
3771
3772                 tp->dev->last_rx = jiffies;
3773                 received++;
3774                 budget--;
3775
3776 next_pkt:
3777                 (*post_ptr)++;
3778
3779                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3780                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3781
3782                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3783                                      TG3_64BIT_REG_LOW, idx);
3784                         work_mask &= ~RXD_OPAQUE_RING_STD;
3785                         rx_std_posted = 0;
3786                 }
3787 next_pkt_nopost:
3788                 sw_idx++;
3789                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
3790
3791                 /* Refresh hw_idx to see if there is new work */
3792                 if (sw_idx == hw_idx) {
3793                         hw_idx = tp->hw_status->idx[0].rx_producer;
3794                         rmb();
3795                 }
3796         }
3797
3798         /* ACK the status ring. */
3799         tp->rx_rcb_ptr = sw_idx;
3800         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3801
3802         /* Refill RX ring(s). */
3803         if (work_mask & RXD_OPAQUE_RING_STD) {
3804                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3805                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3806                              sw_idx);
3807         }
3808         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3809                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3810                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3811                              sw_idx);
3812         }
3813         mmiowb();
3814
3815         return received;
3816 }
3817
3818 static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
3819 {
3820         struct tg3_hw_status *sblk = tp->hw_status;
3821
3822         /* handle link change and other phy events */
3823         if (!(tp->tg3_flags &
3824               (TG3_FLAG_USE_LINKCHG_REG |
3825                TG3_FLAG_POLL_SERDES))) {
3826                 if (sblk->status & SD_STATUS_LINK_CHG) {
3827                         sblk->status = SD_STATUS_UPDATED |
3828                                 (sblk->status & ~SD_STATUS_LINK_CHG);
3829                         spin_lock(&tp->lock);
3830                         tg3_setup_phy(tp, 0);
3831                         spin_unlock(&tp->lock);
3832                 }
3833         }
3834
3835         /* run TX completion thread */
3836         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3837                 tg3_tx(tp);
3838                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
3839                         return work_done;
3840         }
3841
3842         /* run RX thread, within the bounds set by NAPI.
3843          * All RX "locking" is done by ensuring outside
3844          * code synchronizes with tg3->napi.poll()
3845          */
3846         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
3847                 work_done += tg3_rx(tp, budget - work_done);
3848
3849         return work_done;
3850 }
3851
3852 static int tg3_poll(struct napi_struct *napi, int budget)
3853 {
3854         struct tg3 *tp = container_of(napi, struct tg3, napi);
3855         int work_done = 0;
3856         struct tg3_hw_status *sblk = tp->hw_status;
3857
3858         while (1) {
3859                 work_done = tg3_poll_work(tp, work_done, budget);
3860
3861                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
3862                         goto tx_recovery;
3863
3864                 if (unlikely(work_done >= budget))
3865                         break;
3866
3867                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3868                         /* tp->last_tag is used in tg3_restart_ints() below
3869                          * to tell the hw how much work has been processed,
3870                          * so we must read it before checking for more work.
3871                          */
3872                         tp->last_tag = sblk->status_tag;
3873                         rmb();
3874                 } else
3875                         sblk->status &= ~SD_STATUS_UPDATED;
3876
3877                 if (likely(!tg3_has_work(tp))) {
3878                         netif_rx_complete(tp->dev, napi);
3879                         tg3_restart_ints(tp);
3880                         break;
3881                 }
3882         }
3883
3884         return work_done;
3885
3886 tx_recovery:
3887         /* work_done is guaranteed to be less than budget. */
3888         netif_rx_complete(tp->dev, napi);
3889         schedule_work(&tp->reset_task);
3890         return work_done;
3891 }
3892
3893 static void tg3_irq_quiesce(struct tg3 *tp)
3894 {
3895         BUG_ON(tp->irq_sync);
3896
3897         tp->irq_sync = 1;
3898         smp_mb();
3899
3900         synchronize_irq(tp->pdev->irq);
3901 }
3902
3903 static inline int tg3_irq_sync(struct tg3 *tp)
3904 {
3905         return tp->irq_sync;
3906 }
3907
3908 /* Fully shutdown all tg3 driver activity elsewhere in the system.
3909  * If irq_sync is non-zero, then the IRQ handler must be synchronized
3910  * with as well.  Most of the time, this is not necessary except when
3911  * shutting down the device.
3912  */
3913 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3914 {
3915         spin_lock_bh(&tp->lock);
3916         if (irq_sync)
3917                 tg3_irq_quiesce(tp);
3918 }
3919
3920 static inline void tg3_full_unlock(struct tg3 *tp)
3921 {
3922         spin_unlock_bh(&tp->lock);
3923 }
3924
3925 /* One-shot MSI handler - Chip automatically disables interrupt
3926  * after sending MSI so driver doesn't have to do it.
3927  */
3928 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
3929 {
3930         struct net_device *dev = dev_id;
3931         struct tg3 *tp = netdev_priv(dev);
3932
3933         prefetch(tp->hw_status);
3934         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3935
3936         if (likely(!tg3_irq_sync(tp)))
3937                 netif_rx_schedule(dev, &tp->napi);
3938
3939         return IRQ_HANDLED;
3940 }
3941
3942 /* MSI ISR - No need to check for interrupt sharing and no need to
3943  * flush status block and interrupt mailbox. PCI ordering rules
3944  * guarantee that MSI will arrive after the status block.
3945  */
3946 static irqreturn_t tg3_msi(int irq, void *dev_id)
3947 {
3948         struct net_device *dev = dev_id;
3949         struct tg3 *tp = netdev_priv(dev);
3950
3951         prefetch(tp->hw_status);
3952         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3953         /*
3954          * Writing any value to intr-mbox-0 clears PCI INTA# and
3955          * chip-internal interrupt pending events.
3956          * Writing non-zero to intr-mbox-0 additional tells the
3957          * NIC to stop sending us irqs, engaging "in-intr-handler"
3958          * event coalescing.
3959          */
3960         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3961         if (likely(!tg3_irq_sync(tp)))
3962                 netif_rx_schedule(dev, &tp->napi);
3963
3964         return IRQ_RETVAL(1);
3965 }
3966
3967 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
3968 {
3969         struct net_device *dev = dev_id;
3970         struct tg3 *tp = netdev_priv(dev);
3971         struct tg3_hw_status *sblk = tp->hw_status;
3972         unsigned int handled = 1;
3973
3974         /* In INTx mode, it is possible for the interrupt to arrive at
3975          * the CPU before the status block posted prior to the interrupt.
3976          * Reading the PCI State register will confirm whether the
3977          * interrupt is ours and will flush the status block.
3978          */
3979         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
3980                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3981                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3982                         handled = 0;
3983                         goto out;
3984                 }
3985         }
3986
3987         /*
3988          * Writing any value to intr-mbox-0 clears PCI INTA# and
3989          * chip-internal interrupt pending events.
3990          * Writing non-zero to intr-mbox-0 additional tells the
3991          * NIC to stop sending us irqs, engaging "in-intr-handler"
3992          * event coalescing.
3993          *
3994          * Flush the mailbox to de-assert the IRQ immediately to prevent
3995          * spurious interrupts.  The flush impacts performance but
3996          * excessive spurious interrupts can be worse in some cases.
3997          */
3998         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3999         if (tg3_irq_sync(tp))
4000                 goto out;
4001         sblk->status &= ~SD_STATUS_UPDATED;
4002         if (likely(tg3_has_work(tp))) {
4003                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4004                 netif_rx_schedule(dev, &tp->napi);
4005         } else {
4006                 /* No work, shared interrupt perhaps?  re-enable
4007                  * interrupts, and flush that PCI write
4008                  */
4009                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4010                                0x00000000);
4011         }
4012 out:
4013         return IRQ_RETVAL(handled);
4014 }
4015
4016 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4017 {
4018         struct net_device *dev = dev_id;
4019         struct tg3 *tp = netdev_priv(dev);
4020         struct tg3_hw_status *sblk = tp->hw_status;
4021         unsigned int handled = 1;
4022
4023         /* In INTx mode, it is possible for the interrupt to arrive at
4024          * the CPU before the status block posted prior to the interrupt.
4025          * Reading the PCI State register will confirm whether the
4026          * interrupt is ours and will flush the status block.
4027          */
4028         if (unlikely(sblk->status_tag == tp->last_tag)) {
4029                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4030                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4031                         handled = 0;
4032                         goto out;
4033                 }
4034         }
4035
4036         /*
4037          * writing any value to intr-mbox-0 clears PCI INTA# and
4038          * chip-internal interrupt pending events.
4039          * writing non-zero to intr-mbox-0 additional tells the
4040          * NIC to stop sending us irqs, engaging "in-intr-handler"
4041          * event coalescing.
4042          *
4043          * Flush the mailbox to de-assert the IRQ immediately to prevent
4044          * spurious interrupts.  The flush impacts performance but
4045          * excessive spurious interrupts can be worse in some cases.
4046          */
4047         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4048         if (tg3_irq_sync(tp))
4049                 goto out;
4050         if (netif_rx_schedule_prep(dev, &tp->napi)) {
4051                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4052                 /* Update last_tag to mark that this status has been
4053                  * seen. Because interrupt may be shared, we may be
4054                  * racing with tg3_poll(), so only update last_tag
4055                  * if tg3_poll() is not scheduled.
4056                  */
4057                 tp->last_tag = sblk->status_tag;
4058                 __netif_rx_schedule(dev, &tp->napi);
4059         }
4060 out:
4061         return IRQ_RETVAL(handled);
4062 }
4063
4064 /* ISR for interrupt test */
4065 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4066 {
4067         struct net_device *dev = dev_id;
4068         struct tg3 *tp = netdev_priv(dev);
4069         struct tg3_hw_status *sblk = tp->hw_status;
4070
4071         if ((sblk->status & SD_STATUS_UPDATED) ||
4072             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4073                 tg3_disable_ints(tp);
4074                 return IRQ_RETVAL(1);
4075         }
4076         return IRQ_RETVAL(0);
4077 }
4078
4079 static int tg3_init_hw(struct tg3 *, int);
4080 static int tg3_halt(struct tg3 *, int, int);
4081
4082 /* Restart hardware after configuration changes, self-test, etc.
4083  * Invoked with tp->lock held.
4084  */
4085 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4086         __releases(tp->lock)
4087         __acquires(tp->lock)
4088 {
4089         int err;
4090
4091         err = tg3_init_hw(tp, reset_phy);
4092         if (err) {
4093                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4094                        "aborting.\n", tp->dev->name);
4095                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4096                 tg3_full_unlock(tp);
4097                 del_timer_sync(&tp->timer);
4098                 tp->irq_sync = 0;
4099                 napi_enable(&tp->napi);
4100                 dev_close(tp->dev);
4101                 tg3_full_lock(tp, 0);
4102         }
4103         return err;
4104 }
4105
4106 #ifdef CONFIG_NET_POLL_CONTROLLER
4107 static void tg3_poll_controller(struct net_device *dev)
4108 {
4109         struct tg3 *tp = netdev_priv(dev);
4110
4111         tg3_interrupt(tp->pdev->irq, dev);
4112 }
4113 #endif
4114
4115 static void tg3_reset_task(struct work_struct *work)
4116 {
4117         struct tg3 *tp = container_of(work, struct tg3, reset_task);
4118         unsigned int restart_timer;
4119
4120         tg3_full_lock(tp, 0);
4121
4122         if (!netif_running(tp->dev)) {
4123                 tg3_full_unlock(tp);
4124                 return;
4125         }
4126
4127         tg3_full_unlock(tp);
4128
4129         tg3_netif_stop(tp);
4130
4131         tg3_full_lock(tp, 1);
4132
4133         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4134         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4135
4136         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4137                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4138                 tp->write32_rx_mbox = tg3_write_flush_reg32;
4139                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4140                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4141         }
4142
4143         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
4144         if (tg3_init_hw(tp, 1))
4145                 goto out;
4146
4147         tg3_netif_start(tp);
4148
4149         if (restart_timer)
4150                 mod_timer(&tp->timer, jiffies + 1);
4151
4152 out:
4153         tg3_full_unlock(tp);
4154 }
4155
4156 static void tg3_dump_short_state(struct tg3 *tp)
4157 {
4158         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
4159                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
4160         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
4161                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
4162 }
4163
4164 static void tg3_tx_timeout(struct net_device *dev)
4165 {
4166         struct tg3 *tp = netdev_priv(dev);
4167
4168         if (netif_msg_tx_err(tp)) {
4169                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
4170                        dev->name);
4171                 tg3_dump_short_state(tp);
4172         }
4173
4174         schedule_work(&tp->reset_task);
4175 }
4176
4177 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
4178 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
4179 {
4180         u32 base = (u32) mapping & 0xffffffff;
4181
4182         return ((base > 0xffffdcc0) &&
4183                 (base + len + 8 < base));
4184 }
4185
4186 /* Test for DMA addresses > 40-bit */
4187 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
4188                                           int len)
4189 {
4190 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
4191         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
4192                 return (((u64) mapping + len) > DMA_40BIT_MASK);
4193         return 0;
4194 #else
4195         return 0;
4196 #endif
4197 }
4198
4199 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
4200
4201 /* Workaround 4GB and 40-bit hardware DMA bugs. */
4202 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
4203                                        u32 last_plus_one, u32 *start,
4204                                        u32 base_flags, u32 mss)
4205 {
4206         struct sk_buff *new_skb;
4207         dma_addr_t new_addr = 0;
4208         u32 entry = *start;
4209         int i, ret = 0;
4210
4211         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
4212                 new_skb = skb_copy(skb, GFP_ATOMIC);
4213         else {
4214                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
4215
4216                 new_skb = skb_copy_expand(skb,
4217                                           skb_headroom(skb) + more_headroom,
4218                                           skb_tailroom(skb), GFP_ATOMIC);
4219         }
4220
4221         if (!new_skb) {
4222                 ret = -1;
4223         } else {
4224                 /* New SKB is guaranteed to be linear. */
4225                 entry = *start;
4226                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
4227                                           PCI_DMA_TODEVICE);
4228                 /* Make sure new skb does not cross any 4G boundaries.
4229                  * Drop the packet if it does.
4230                  */
4231                 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
4232                         ret = -1;
4233                         dev_kfree_skb(new_skb);
4234                         new_skb = NULL;
4235                 } else {
4236                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
4237                                     base_flags, 1 | (mss << 1));
4238                         *start = NEXT_TX(entry);
4239                 }
4240         }
4241
4242         /* Now clean up the sw ring entries. */
4243         i = 0;
4244         while (entry != last_plus_one) {
4245                 int len;
4246
4247                 if (i == 0)
4248                         len = skb_headlen(skb);
4249                 else
4250                         len = skb_shinfo(skb)->frags[i-1].size;
4251                 pci_unmap_single(tp->pdev,
4252                                  pci_unmap_addr(&tp->tx_buffers[entry], mapping),
4253                                  len, PCI_DMA_TODEVICE);
4254                 if (i == 0) {
4255                         tp->tx_buffers[entry].skb = new_skb;
4256                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
4257                 } else {
4258                         tp->tx_buffers[entry].skb = NULL;
4259                 }
4260                 entry = NEXT_TX(entry);
4261                 i++;
4262         }
4263
4264         dev_kfree_skb(skb);
4265
4266         return ret;
4267 }
4268
4269 static void tg3_set_txd(struct tg3 *tp, int entry,
4270                         dma_addr_t mapping, int len, u32 flags,
4271                         u32 mss_and_is_end)
4272 {
4273         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
4274         int is_end = (mss_and_is_end & 0x1);
4275         u32 mss = (mss_and_is_end >> 1);
4276         u32 vlan_tag = 0;
4277
4278         if (is_end)
4279                 flags |= TXD_FLAG_END;
4280         if (flags & TXD_FLAG_VLAN) {
4281                 vlan_tag = flags >> 16;
4282                 flags &= 0xffff;
4283         }
4284         vlan_tag |= (mss << TXD_MSS_SHIFT);
4285
4286         txd->addr_hi = ((u64) mapping >> 32);
4287         txd->addr_lo = ((u64) mapping & 0xffffffff);
4288         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
4289         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
4290 }
4291
4292 /* hard_start_xmit for devices that don't have any bugs and
4293  * support TG3_FLG2_HW_TSO_2 only.
4294  */
4295 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
4296 {
4297         struct tg3 *tp = netdev_priv(dev);
4298         dma_addr_t mapping;
4299         u32 len, entry, base_flags, mss;
4300
4301         len = skb_headlen(skb);
4302
4303         /* We are running in BH disabled context with netif_tx_lock
4304          * and TX reclaim runs via tp->napi.poll inside of a software
4305          * interrupt.  Furthermore, IRQ processing runs lockless so we have
4306          * no IRQ context deadlocks to worry about either.  Rejoice!
4307          */
4308         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4309                 if (!netif_queue_stopped(dev)) {
4310                         netif_stop_queue(dev);
4311
4312                         /* This is a hard error, log it. */
4313                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4314                                "queue awake!\n", dev->name);
4315                 }
4316                 return NETDEV_TX_BUSY;
4317         }
4318
4319         entry = tp->tx_prod;
4320         base_flags = 0;
4321         mss = 0;
4322         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4323                 int tcp_opt_len, ip_tcp_len;
4324
4325                 if (skb_header_cloned(skb) &&
4326                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4327                         dev_kfree_skb(skb);
4328                         goto out_unlock;
4329                 }
4330
4331                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
4332                         mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
4333                 else {
4334                         struct iphdr *iph = ip_hdr(skb);
4335
4336                         tcp_opt_len = tcp_optlen(skb);
4337                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4338
4339                         iph->check = 0;
4340                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
4341                         mss |= (ip_tcp_len + tcp_opt_len) << 9;
4342                 }
4343
4344                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4345                                TXD_FLAG_CPU_POST_DMA);
4346
4347                 tcp_hdr(skb)->check = 0;
4348
4349         }
4350         else if (skb->ip_summed == CHECKSUM_PARTIAL)
4351                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4352 #if TG3_VLAN_TAG_USED
4353         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4354                 base_flags |= (TXD_FLAG_VLAN |
4355                                (vlan_tx_tag_get(skb) << 16));
4356 #endif
4357
4358         /* Queue skb data, a.k.a. the main skb fragment. */
4359         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4360
4361         tp->tx_buffers[entry].skb = skb;
4362         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4363
4364         tg3_set_txd(tp, entry, mapping, len, base_flags,
4365                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4366
4367         entry = NEXT_TX(entry);
4368
4369         /* Now loop through additional data fragments, and queue them. */
4370         if (skb_shinfo(skb)->nr_frags > 0) {
4371                 unsigned int i, last;
4372
4373                 last = skb_shinfo(skb)->nr_frags - 1;
4374                 for (i = 0; i <= last; i++) {
4375                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4376
4377                         len = frag->size;
4378                         mapping = pci_map_page(tp->pdev,
4379                                                frag->page,
4380                                                frag->page_offset,
4381                                                len, PCI_DMA_TODEVICE);
4382
4383                         tp->tx_buffers[entry].skb = NULL;
4384                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4385
4386                         tg3_set_txd(tp, entry, mapping, len,
4387                                     base_flags, (i == last) | (mss << 1));
4388
4389                         entry = NEXT_TX(entry);
4390                 }
4391         }
4392
4393         /* Packets are ready, update Tx producer idx local and on card. */
4394         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4395
4396         tp->tx_prod = entry;
4397         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4398                 netif_stop_queue(dev);
4399                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4400                         netif_wake_queue(tp->dev);
4401         }
4402
4403 out_unlock:
4404         mmiowb();
4405
4406         dev->trans_start = jiffies;
4407
4408         return NETDEV_TX_OK;
4409 }
4410
4411 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
4412
4413 /* Use GSO to workaround a rare TSO bug that may be triggered when the
4414  * TSO header is greater than 80 bytes.
4415  */
4416 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
4417 {
4418         struct sk_buff *segs, *nskb;
4419
4420         /* Estimate the number of fragments in the worst case */
4421         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
4422                 netif_stop_queue(tp->dev);
4423                 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
4424                         return NETDEV_TX_BUSY;
4425
4426                 netif_wake_queue(tp->dev);
4427         }
4428
4429         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
4430         if (IS_ERR(segs))
4431                 goto tg3_tso_bug_end;
4432
4433         do {
4434                 nskb = segs;
4435                 segs = segs->next;
4436                 nskb->next = NULL;
4437                 tg3_start_xmit_dma_bug(nskb, tp->dev);
4438         } while (segs);
4439
4440 tg3_tso_bug_end:
4441         dev_kfree_skb(skb);
4442
4443         return NETDEV_TX_OK;
4444 }
4445
4446 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
4447  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
4448  */
4449 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
4450 {
4451         struct tg3 *tp = netdev_priv(dev);
4452         dma_addr_t mapping;
4453         u32 len, entry, base_flags, mss;
4454         int would_hit_hwbug;
4455
4456         len = skb_headlen(skb);
4457
4458         /* We are running in BH disabled context with netif_tx_lock
4459          * and TX reclaim runs via tp->napi.poll inside of a software
4460          * interrupt.  Furthermore, IRQ processing runs lockless so we have
4461          * no IRQ context deadlocks to worry about either.  Rejoice!
4462          */
4463         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4464                 if (!netif_queue_stopped(dev)) {
4465                         netif_stop_queue(dev);
4466
4467                         /* This is a hard error, log it. */
4468                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4469                                "queue awake!\n", dev->name);
4470                 }
4471                 return NETDEV_TX_BUSY;
4472         }
4473
4474         entry = tp->tx_prod;
4475         base_flags = 0;
4476         if (skb->ip_summed == CHECKSUM_PARTIAL)
4477                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4478         mss = 0;
4479         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4480                 struct iphdr *iph;
4481                 int tcp_opt_len, ip_tcp_len, hdr_len;
4482
4483                 if (skb_header_cloned(skb) &&
4484                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4485                         dev_kfree_skb(skb);
4486                         goto out_unlock;
4487                 }
4488
4489                 tcp_opt_len = tcp_optlen(skb);
4490                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4491
4492                 hdr_len = ip_tcp_len + tcp_opt_len;
4493                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4494                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
4495                         return (tg3_tso_bug(tp, skb));
4496
4497                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4498                                TXD_FLAG_CPU_POST_DMA);
4499
4500                 iph = ip_hdr(skb);
4501                 iph->check = 0;
4502                 iph->tot_len = htons(mss + hdr_len);
4503                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4504                         tcp_hdr(skb)->check = 0;
4505                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4506                 } else
4507                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4508                                                                  iph->daddr, 0,
4509                                                                  IPPROTO_TCP,
4510                                                                  0);
4511
4512                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4513                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4514                         if (tcp_opt_len || iph->ihl > 5) {
4515                                 int tsflags;
4516
4517                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4518                                 mss |= (tsflags << 11);
4519                         }
4520                 } else {
4521                         if (tcp_opt_len || iph->ihl > 5) {
4522                                 int tsflags;
4523
4524                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4525                                 base_flags |= tsflags << 12;
4526                         }
4527                 }
4528         }
4529 #if TG3_VLAN_TAG_USED
4530         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4531                 base_flags |= (TXD_FLAG_VLAN |
4532                                (vlan_tx_tag_get(skb) << 16));
4533 #endif
4534
4535         /* Queue skb data, a.k.a. the main skb fragment. */
4536         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4537
4538         tp->tx_buffers[entry].skb = skb;
4539         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4540
4541         would_hit_hwbug = 0;
4542
4543         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
4544                 would_hit_hwbug = 1;
4545         else if (tg3_4g_overflow_test(mapping, len))
4546                 would_hit_hwbug = 1;
4547
4548         tg3_set_txd(tp, entry, mapping, len, base_flags,
4549                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4550
4551         entry = NEXT_TX(entry);
4552
4553         /* Now loop through additional data fragments, and queue them. */
4554         if (skb_shinfo(skb)->nr_frags > 0) {
4555                 unsigned int i, last;
4556
4557                 last = skb_shinfo(skb)->nr_frags - 1;
4558                 for (i = 0; i <= last; i++) {
4559                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4560
4561                         len = frag->size;
4562                         mapping = pci_map_page(tp->pdev,
4563                                                frag->page,
4564                                                frag->page_offset,
4565                                                len, PCI_DMA_TODEVICE);
4566
4567                         tp->tx_buffers[entry].skb = NULL;
4568                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4569
4570                         if (tg3_4g_overflow_test(mapping, len))
4571                                 would_hit_hwbug = 1;
4572
4573                         if (tg3_40bit_overflow_test(tp, mapping, len))
4574                                 would_hit_hwbug = 1;
4575
4576                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4577                                 tg3_set_txd(tp, entry, mapping, len,
4578                                             base_flags, (i == last)|(mss << 1));
4579                         else
4580                                 tg3_set_txd(tp, entry, mapping, len,
4581                                             base_flags, (i == last));
4582
4583                         entry = NEXT_TX(entry);
4584                 }
4585         }
4586
4587         if (would_hit_hwbug) {
4588                 u32 last_plus_one = entry;
4589                 u32 start;
4590
4591                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4592                 start &= (TG3_TX_RING_SIZE - 1);
4593
4594                 /* If the workaround fails due to memory/mapping
4595                  * failure, silently drop this packet.
4596                  */
4597                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
4598                                                 &start, base_flags, mss))
4599                         goto out_unlock;
4600
4601                 entry = start;
4602         }
4603
4604         /* Packets are ready, update Tx producer idx local and on card. */
4605         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4606
4607         tp->tx_prod = entry;
4608         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4609                 netif_stop_queue(dev);
4610                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4611                         netif_wake_queue(tp->dev);
4612         }
4613
4614 out_unlock:
4615         mmiowb();
4616
4617         dev->trans_start = jiffies;
4618
4619         return NETDEV_TX_OK;
4620 }
4621
4622 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4623                                int new_mtu)
4624 {
4625         dev->mtu = new_mtu;
4626
4627         if (new_mtu > ETH_DATA_LEN) {
4628                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4629                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4630                         ethtool_op_set_tso(dev, 0);
4631                 }
4632                 else
4633                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4634         } else {
4635                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4636                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4637                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
4638         }
4639 }
4640
4641 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4642 {
4643         struct tg3 *tp = netdev_priv(dev);
4644         int err;
4645
4646         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4647                 return -EINVAL;
4648
4649         if (!netif_running(dev)) {
4650                 /* We'll just catch it later when the
4651                  * device is up'd.
4652                  */
4653                 tg3_set_mtu(dev, tp, new_mtu);
4654                 return 0;
4655         }
4656
4657         tg3_netif_stop(tp);
4658
4659         tg3_full_lock(tp, 1);
4660
4661         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4662
4663         tg3_set_mtu(dev, tp, new_mtu);
4664
4665         err = tg3_restart_hw(tp, 0);
4666
4667         if (!err)
4668                 tg3_netif_start(tp);
4669
4670         tg3_full_unlock(tp);
4671
4672         return err;
4673 }
4674
4675 /* Free up pending packets in all rx/tx rings.
4676  *
4677  * The chip has been shut down and the driver detached from
4678  * the networking, so no interrupts or new tx packets will
4679  * end up in the driver.  tp->{tx,}lock is not held and we are not
4680  * in an interrupt context and thus may sleep.
4681  */
4682 static void tg3_free_rings(struct tg3 *tp)
4683 {
4684         struct ring_info *rxp;
4685         int i;
4686
4687         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4688                 rxp = &tp->rx_std_buffers[i];
4689
4690                 if (rxp->skb == NULL)
4691                         continue;
4692                 pci_unmap_single(tp->pdev,
4693                                  pci_unmap_addr(rxp, mapping),
4694                                  tp->rx_pkt_buf_sz - tp->rx_offset,
4695                                  PCI_DMA_FROMDEVICE);
4696                 dev_kfree_skb_any(rxp->skb);
4697                 rxp->skb = NULL;
4698         }
4699
4700         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4701                 rxp = &tp->rx_jumbo_buffers[i];
4702
4703                 if (rxp->skb == NULL)
4704                         continue;
4705                 pci_unmap_single(tp->pdev,
4706                                  pci_unmap_addr(rxp, mapping),
4707                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4708                                  PCI_DMA_FROMDEVICE);
4709                 dev_kfree_skb_any(rxp->skb);
4710                 rxp->skb = NULL;
4711         }
4712
4713         for (i = 0; i < TG3_TX_RING_SIZE; ) {
4714                 struct tx_ring_info *txp;
4715                 struct sk_buff *skb;
4716                 int j;
4717
4718                 txp = &tp->tx_buffers[i];
4719                 skb = txp->skb;
4720
4721                 if (skb == NULL) {
4722                         i++;
4723                         continue;
4724                 }
4725
4726                 pci_unmap_single(tp->pdev,
4727                                  pci_unmap_addr(txp, mapping),
4728                                  skb_headlen(skb),
4729                                  PCI_DMA_TODEVICE);
4730                 txp->skb = NULL;
4731
4732                 i++;
4733
4734                 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4735                         txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4736                         pci_unmap_page(tp->pdev,
4737                                        pci_unmap_addr(txp, mapping),
4738                                        skb_shinfo(skb)->frags[j].size,
4739                                        PCI_DMA_TODEVICE);
4740                         i++;
4741                 }
4742
4743                 dev_kfree_skb_any(skb);
4744         }
4745 }
4746
4747 /* Initialize tx/rx rings for packet processing.
4748  *
4749  * The chip has been shut down and the driver detached from
4750  * the networking, so no interrupts or new tx packets will
4751  * end up in the driver.  tp->{tx,}lock are held and thus
4752  * we may not sleep.
4753  */
4754 static int tg3_init_rings(struct tg3 *tp)
4755 {
4756         u32 i;
4757
4758         /* Free up all the SKBs. */
4759         tg3_free_rings(tp);
4760
4761         /* Zero out all descriptors. */
4762         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4763         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4764         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4765         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4766
4767         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
4768         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
4769             (tp->dev->mtu > ETH_DATA_LEN))
4770                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4771
4772         /* Initialize invariants of the rings, we only set this
4773          * stuff once.  This works because the card does not
4774          * write into the rx buffer posting rings.
4775          */
4776         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4777                 struct tg3_rx_buffer_desc *rxd;
4778
4779                 rxd = &tp->rx_std[i];
4780                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
4781                         << RXD_LEN_SHIFT;
4782                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4783                 rxd->opaque = (RXD_OPAQUE_RING_STD |
4784                                (i << RXD_OPAQUE_INDEX_SHIFT));
4785         }
4786
4787         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4788                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4789                         struct tg3_rx_buffer_desc *rxd;
4790
4791                         rxd = &tp->rx_jumbo[i];
4792                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4793                                 << RXD_LEN_SHIFT;
4794                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4795                                 RXD_FLAG_JUMBO;
4796                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4797                                (i << RXD_OPAQUE_INDEX_SHIFT));
4798                 }
4799         }
4800
4801         /* Now allocate fresh SKBs for each rx ring. */
4802         for (i = 0; i < tp->rx_pending; i++) {
4803                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4804                         printk(KERN_WARNING PFX
4805                                "%s: Using a smaller RX standard ring, "
4806                                "only %d out of %d buffers were allocated "
4807                                "successfully.\n",
4808                                tp->dev->name, i, tp->rx_pending);
4809                         if (i == 0)
4810                                 return -ENOMEM;
4811                         tp->rx_pending = i;
4812                         break;
4813                 }
4814         }
4815
4816         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4817                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4818                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
4819                                              -1, i) < 0) {
4820                                 printk(KERN_WARNING PFX
4821                                        "%s: Using a smaller RX jumbo ring, "
4822                                        "only %d out of %d buffers were "
4823                                        "allocated successfully.\n",
4824                                        tp->dev->name, i, tp->rx_jumbo_pending);
4825                                 if (i == 0) {
4826                                         tg3_free_rings(tp);
4827                                         return -ENOMEM;
4828                                 }
4829                                 tp->rx_jumbo_pending = i;
4830                                 break;
4831                         }
4832                 }
4833         }
4834         return 0;
4835 }
4836
4837 /*
4838  * Must not be invoked with interrupt sources disabled and
4839  * the hardware shutdown down.
4840  */
4841 static void tg3_free_consistent(struct tg3 *tp)
4842 {
4843         kfree(tp->rx_std_buffers);
4844         tp->rx_std_buffers = NULL;
4845         if (tp->rx_std) {
4846                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4847                                     tp->rx_std, tp->rx_std_mapping);
4848                 tp->rx_std = NULL;
4849         }
4850         if (tp->rx_jumbo) {
4851                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4852                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
4853                 tp->rx_jumbo = NULL;
4854         }
4855         if (tp->rx_rcb) {
4856                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4857                                     tp->rx_rcb, tp->rx_rcb_mapping);
4858                 tp->rx_rcb = NULL;
4859         }
4860         if (tp->tx_ring) {
4861                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4862                         tp->tx_ring, tp->tx_desc_mapping);
4863                 tp->tx_ring = NULL;
4864         }
4865         if (tp->hw_status) {
4866                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4867                                     tp->hw_status, tp->status_mapping);
4868                 tp->hw_status = NULL;
4869         }
4870         if (tp->hw_stats) {
4871                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4872                                     tp->hw_stats, tp->stats_mapping);
4873                 tp->hw_stats = NULL;
4874         }
4875 }
4876
4877 /*
4878  * Must not be invoked with interrupt sources disabled and
4879  * the hardware shutdown down.  Can sleep.
4880  */
4881 static int tg3_alloc_consistent(struct tg3 *tp)
4882 {
4883         tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
4884                                       (TG3_RX_RING_SIZE +
4885                                        TG3_RX_JUMBO_RING_SIZE)) +
4886                                      (sizeof(struct tx_ring_info) *
4887                                       TG3_TX_RING_SIZE),
4888                                      GFP_KERNEL);
4889         if (!tp->rx_std_buffers)
4890                 return -ENOMEM;
4891
4892         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4893         tp->tx_buffers = (struct tx_ring_info *)
4894                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4895
4896         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4897                                           &tp->rx_std_mapping);
4898         if (!tp->rx_std)
4899                 goto err_out;
4900
4901         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4902                                             &tp->rx_jumbo_mapping);
4903
4904         if (!tp->rx_jumbo)
4905                 goto err_out;
4906
4907         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4908                                           &tp->rx_rcb_mapping);
4909         if (!tp->rx_rcb)
4910                 goto err_out;
4911
4912         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4913                                            &tp->tx_desc_mapping);
4914         if (!tp->tx_ring)
4915                 goto err_out;
4916
4917         tp->hw_status = pci_alloc_consistent(tp->pdev,
4918                                              TG3_HW_STATUS_SIZE,
4919                                              &tp->status_mapping);
4920         if (!tp->hw_status)
4921                 goto err_out;
4922
4923         tp->hw_stats = pci_alloc_consistent(tp->pdev,
4924                                             sizeof(struct tg3_hw_stats),
4925                                             &tp->stats_mapping);
4926         if (!tp->hw_stats)
4927                 goto err_out;
4928
4929         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4930         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4931
4932         return 0;
4933
4934 err_out:
4935         tg3_free_consistent(tp);
4936         return -ENOMEM;
4937 }
4938
4939 #define MAX_WAIT_CNT 1000
4940
4941 /* To stop a block, clear the enable bit and poll till it
4942  * clears.  tp->lock is held.
4943  */
4944 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4945 {
4946         unsigned int i;
4947         u32 val;
4948
4949         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4950                 switch (ofs) {
4951                 case RCVLSC_MODE:
4952                 case DMAC_MODE:
4953                 case MBFREE_MODE:
4954                 case BUFMGR_MODE:
4955                 case MEMARB_MODE:
4956                         /* We can't enable/disable these bits of the
4957                          * 5705/5750, just say success.
4958                          */
4959                         return 0;
4960
4961                 default:
4962                         break;
4963                 };
4964         }
4965
4966         val = tr32(ofs);
4967         val &= ~enable_bit;
4968         tw32_f(ofs, val);
4969
4970         for (i = 0; i < MAX_WAIT_CNT; i++) {
4971                 udelay(100);
4972                 val = tr32(ofs);
4973                 if ((val & enable_bit) == 0)
4974                         break;
4975         }
4976
4977         if (i == MAX_WAIT_CNT && !silent) {
4978                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4979                        "ofs=%lx enable_bit=%x\n",
4980                        ofs, enable_bit);
4981                 return -ENODEV;
4982         }
4983
4984         return 0;
4985 }
4986
4987 /* tp->lock is held. */
4988 static int tg3_abort_hw(struct tg3 *tp, int silent)
4989 {
4990         int i, err;
4991
4992         tg3_disable_ints(tp);
4993
4994         tp->rx_mode &= ~RX_MODE_ENABLE;
4995         tw32_f(MAC_RX_MODE, tp->rx_mode);
4996         udelay(10);
4997
4998         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4999         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5000         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5001         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5002         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5003         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5004
5005         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5006         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5007         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5008         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5009         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5010         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5011         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
5012
5013         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5014         tw32_f(MAC_MODE, tp->mac_mode);
5015         udelay(40);
5016
5017         tp->tx_mode &= ~TX_MODE_ENABLE;
5018         tw32_f(MAC_TX_MODE, tp->tx_mode);
5019
5020         for (i = 0; i < MAX_WAIT_CNT; i++) {
5021                 udelay(100);
5022                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5023                         break;
5024         }
5025         if (i >= MAX_WAIT_CNT) {
5026                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5027                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5028                        tp->dev->name, tr32(MAC_TX_MODE));
5029                 err |= -ENODEV;
5030         }
5031
5032         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
5033         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5034         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
5035
5036         tw32(FTQ_RESET, 0xffffffff);
5037         tw32(FTQ_RESET, 0x00000000);
5038
5039         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5040         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
5041
5042         if (tp->hw_status)
5043                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5044         if (tp->hw_stats)
5045                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5046
5047         return err;
5048 }
5049
5050 /* tp->lock is held. */
5051 static int tg3_nvram_lock(struct tg3 *tp)
5052 {
5053         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
5054                 int i;
5055
5056                 if (tp->nvram_lock_cnt == 0) {
5057                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
5058                         for (i = 0; i < 8000; i++) {
5059                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
5060                                         break;
5061                                 udelay(20);
5062                         }
5063                         if (i == 8000) {
5064                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
5065                                 return -ENODEV;
5066                         }
5067                 }
5068                 tp->nvram_lock_cnt++;
5069         }
5070         return 0;
5071 }
5072
5073 /* tp->lock is held. */
5074 static void tg3_nvram_unlock(struct tg3 *tp)
5075 {
5076         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
5077                 if (tp->nvram_lock_cnt > 0)
5078                         tp->nvram_lock_cnt--;
5079                 if (tp->nvram_lock_cnt == 0)
5080                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
5081         }
5082 }
5083
5084 /* tp->lock is held. */
5085 static void tg3_enable_nvram_access(struct tg3 *tp)
5086 {
5087         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5088             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5089                 u32 nvaccess = tr32(NVRAM_ACCESS);
5090
5091                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
5092         }
5093 }
5094
5095 /* tp->lock is held. */
5096 static void tg3_disable_nvram_access(struct tg3 *tp)
5097 {
5098         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5099             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5100                 u32 nvaccess = tr32(NVRAM_ACCESS);
5101
5102                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
5103         }
5104 }
5105
5106 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5107 {
5108         int i;
5109         u32 apedata;
5110
5111         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5112         if (apedata != APE_SEG_SIG_MAGIC)
5113                 return;
5114
5115         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
5116         if (apedata != APE_FW_STATUS_READY)
5117                 return;
5118
5119         /* Wait for up to 1 millisecond for APE to service previous event. */
5120         for (i = 0; i < 10; i++) {
5121                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5122                         return;
5123
5124                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5125
5126                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5127                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5128                                         event | APE_EVENT_STATUS_EVENT_PENDING);
5129
5130                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5131
5132                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5133                         break;
5134
5135                 udelay(100);
5136         }
5137
5138         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5139                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5140 }
5141
5142 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5143 {
5144         u32 event;
5145         u32 apedata;
5146
5147         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5148                 return;
5149
5150         switch (kind) {
5151                 case RESET_KIND_INIT:
5152                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5153                                         APE_HOST_SEG_SIG_MAGIC);
5154                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5155                                         APE_HOST_SEG_LEN_MAGIC);
5156                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5157                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5158                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
5159                                         APE_HOST_DRIVER_ID_MAGIC);
5160                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
5161                                         APE_HOST_BEHAV_NO_PHYLOCK);
5162
5163                         event = APE_EVENT_STATUS_STATE_START;
5164                         break;
5165                 case RESET_KIND_SHUTDOWN:
5166                         event = APE_EVENT_STATUS_STATE_UNLOAD;
5167                         break;
5168                 case RESET_KIND_SUSPEND:
5169                         event = APE_EVENT_STATUS_STATE_SUSPEND;
5170                         break;
5171                 default:
5172                         return;
5173         }
5174
5175         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
5176
5177         tg3_ape_send_event(tp, event);
5178 }
5179
5180 /* tp->lock is held. */
5181 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
5182 {
5183         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
5184                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
5185
5186         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5187                 switch (kind) {
5188                 case RESET_KIND_INIT:
5189                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5190                                       DRV_STATE_START);
5191                         break;
5192
5193                 case RESET_KIND_SHUTDOWN:
5194                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5195                                       DRV_STATE_UNLOAD);
5196                         break;
5197
5198                 case RESET_KIND_SUSPEND:
5199                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5200                                       DRV_STATE_SUSPEND);
5201                         break;
5202
5203                 default:
5204                         break;
5205                 };
5206         }
5207
5208         if (kind == RESET_KIND_INIT ||
5209             kind == RESET_KIND_SUSPEND)
5210                 tg3_ape_driver_state_change(tp, kind);
5211 }
5212
5213 /* tp->lock is held. */
5214 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
5215 {
5216         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5217                 switch (kind) {
5218                 case RESET_KIND_INIT:
5219                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5220                                       DRV_STATE_START_DONE);
5221                         break;
5222
5223                 case RESET_KIND_SHUTDOWN:
5224                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5225                                       DRV_STATE_UNLOAD_DONE);
5226                         break;
5227
5228                 default:
5229                         break;
5230                 };
5231         }
5232
5233         if (kind == RESET_KIND_SHUTDOWN)
5234                 tg3_ape_driver_state_change(tp, kind);
5235 }
5236
5237 /* tp->lock is held. */
5238 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
5239 {
5240         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5241                 switch (kind) {
5242                 case RESET_KIND_INIT:
5243                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5244                                       DRV_STATE_START);
5245                         break;
5246
5247                 case RESET_KIND_SHUTDOWN:
5248                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5249                                       DRV_STATE_UNLOAD);
5250                         break;
5251
5252                 case RESET_KIND_SUSPEND:
5253                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5254                                       DRV_STATE_SUSPEND);
5255                         break;
5256
5257                 default:
5258                         break;
5259                 };
5260         }
5261 }
5262
5263 static int tg3_poll_fw(struct tg3 *tp)
5264 {
5265         int i;
5266         u32 val;
5267
5268         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5269                 /* Wait up to 20ms for init done. */
5270                 for (i = 0; i < 200; i++) {
5271                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
5272                                 return 0;
5273                         udelay(100);
5274                 }
5275                 return -ENODEV;
5276         }
5277
5278         /* Wait for firmware initialization to complete. */
5279         for (i = 0; i < 100000; i++) {
5280                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
5281                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
5282                         break;
5283                 udelay(10);
5284         }
5285
5286         /* Chip might not be fitted with firmware.  Some Sun onboard
5287          * parts are configured like that.  So don't signal the timeout
5288          * of the above loop as an error, but do report the lack of
5289          * running firmware once.
5290          */
5291         if (i >= 100000 &&
5292             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
5293                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
5294
5295                 printk(KERN_INFO PFX "%s: No firmware running.\n",
5296                        tp->dev->name);
5297         }
5298
5299         return 0;
5300 }
5301
5302 /* Save PCI command register before chip reset */
5303 static void tg3_save_pci_state(struct tg3 *tp)
5304 {
5305         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
5306 }
5307
5308 /* Restore PCI state after chip reset */
5309 static void tg3_restore_pci_state(struct tg3 *tp)
5310 {
5311         u32 val;
5312
5313         /* Re-enable indirect register accesses. */
5314         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
5315                                tp->misc_host_ctrl);
5316
5317         /* Set MAX PCI retry to zero. */
5318         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
5319         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5320             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
5321                 val |= PCISTATE_RETRY_SAME_DMA;
5322         /* Allow reads and writes to the APE register and memory space. */
5323         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
5324                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
5325                        PCISTATE_ALLOW_APE_SHMEM_WR;
5326         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
5327
5328         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
5329
5330         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
5331                 pcie_set_readrq(tp->pdev, 4096);
5332         else {
5333                 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
5334                                       tp->pci_cacheline_sz);
5335                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
5336                                       tp->pci_lat_timer);
5337         }
5338
5339         /* Make sure PCI-X relaxed ordering bit is clear. */
5340         if (tp->pcix_cap) {
5341                 u16 pcix_cmd;
5342
5343                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5344                                      &pcix_cmd);
5345                 pcix_cmd &= ~PCI_X_CMD_ERO;
5346                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5347                                       pcix_cmd);
5348         }
5349
5350         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5351
5352                 /* Chip reset on 5780 will reset MSI enable bit,
5353                  * so need to restore it.
5354                  */
5355                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
5356                         u16 ctrl;
5357
5358                         pci_read_config_word(tp->pdev,
5359                                              tp->msi_cap + PCI_MSI_FLAGS,
5360                                              &ctrl);
5361                         pci_write_config_word(tp->pdev,
5362                                               tp->msi_cap + PCI_MSI_FLAGS,
5363                                               ctrl | PCI_MSI_FLAGS_ENABLE);
5364                         val = tr32(MSGINT_MODE);
5365                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
5366                 }
5367         }
5368 }
5369
5370 static void tg3_stop_fw(struct tg3 *);
5371
5372 /* tp->lock is held. */
5373 static int tg3_chip_reset(struct tg3 *tp)
5374 {
5375         u32 val;
5376         void (*write_op)(struct tg3 *, u32, u32);
5377         int err;
5378
5379         tg3_nvram_lock(tp);
5380
5381         /* No matching tg3_nvram_unlock() after this because
5382          * chip reset below will undo the nvram lock.
5383          */
5384         tp->nvram_lock_cnt = 0;
5385
5386         /* GRC_MISC_CFG core clock reset will clear the memory
5387          * enable bit in PCI register 4 and the MSI enable bit
5388          * on some chips, so we save relevant registers here.
5389          */
5390         tg3_save_pci_state(tp);
5391
5392         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
5393             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
5394             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
5395             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
5396             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
5397                 tw32(GRC_FASTBOOT_PC, 0);
5398
5399         /*
5400          * We must avoid the readl() that normally takes place.
5401          * It locks machines, causes machine checks, and other
5402          * fun things.  So, temporarily disable the 5701
5403          * hardware workaround, while we do the reset.
5404          */
5405         write_op = tp->write32;
5406         if (write_op == tg3_write_flush_reg32)
5407                 tp->write32 = tg3_write32;
5408
5409         /* Prevent the irq handler from reading or writing PCI registers
5410          * during chip reset when the memory enable bit in the PCI command
5411          * register may be cleared.  The chip does not generate interrupt
5412          * at this time, but the irq handler may still be called due to irq
5413          * sharing or irqpoll.
5414          */
5415         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
5416         if (tp->hw_status) {
5417                 tp->hw_status->status = 0;
5418                 tp->hw_status->status_tag = 0;
5419         }
5420         tp->last_tag = 0;
5421         smp_mb();
5422         synchronize_irq(tp->pdev->irq);
5423
5424         /* do the reset */
5425         val = GRC_MISC_CFG_CORECLK_RESET;
5426
5427         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
5428                 if (tr32(0x7e2c) == 0x60) {
5429                         tw32(0x7e2c, 0x20);
5430                 }
5431                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
5432                         tw32(GRC_MISC_CFG, (1 << 29));
5433                         val |= (1 << 29);
5434                 }
5435         }
5436
5437         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5438                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
5439                 tw32(GRC_VCPU_EXT_CTRL,
5440                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
5441         }
5442
5443         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5444                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
5445         tw32(GRC_MISC_CFG, val);
5446
5447         /* restore 5701 hardware bug workaround write method */
5448         tp->write32 = write_op;
5449
5450         /* Unfortunately, we have to delay before the PCI read back.
5451          * Some 575X chips even will not respond to a PCI cfg access
5452          * when the reset command is given to the chip.
5453          *
5454          * How do these hardware designers expect things to work
5455          * properly if the PCI write is posted for a long period
5456          * of time?  It is always necessary to have some method by
5457          * which a register read back can occur to push the write
5458          * out which does the reset.
5459          *
5460          * For most tg3 variants the trick below was working.
5461          * Ho hum...
5462          */
5463         udelay(120);
5464
5465         /* Flush PCI posted writes.  The normal MMIO registers
5466          * are inaccessible at this time so this is the only
5467          * way to make this reliably (actually, this is no longer
5468          * the case, see above).  I tried to use indirect
5469          * register read/write but this upset some 5701 variants.
5470          */
5471         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
5472
5473         udelay(120);
5474
5475         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
5476                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
5477                         int i;
5478                         u32 cfg_val;
5479
5480                         /* Wait for link training to complete.  */
5481                         for (i = 0; i < 5000; i++)
5482                                 udelay(100);
5483
5484                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
5485                         pci_write_config_dword(tp->pdev, 0xc4,
5486                                                cfg_val | (1 << 15));
5487                 }
5488                 /* Set PCIE max payload size and clear error status.  */
5489                 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
5490         }
5491
5492         tg3_restore_pci_state(tp);
5493
5494         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
5495
5496         val = 0;
5497         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5498                 val = tr32(MEMARB_MODE);
5499         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
5500
5501         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
5502                 tg3_stop_fw(tp);
5503                 tw32(0x5000, 0x400);
5504         }
5505
5506         tw32(GRC_MODE, tp->grc_mode);
5507
5508         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
5509                 val = tr32(0xc4);
5510
5511                 tw32(0xc4, val | (1 << 15));
5512         }
5513
5514         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
5515             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5516                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
5517                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
5518                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
5519                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5520         }
5521
5522         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5523                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
5524                 tw32_f(MAC_MODE, tp->mac_mode);
5525         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
5526                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
5527                 tw32_f(MAC_MODE, tp->mac_mode);
5528         } else
5529                 tw32_f(MAC_MODE, 0);
5530         udelay(40);
5531
5532         err = tg3_poll_fw(tp);
5533         if (err)
5534                 return err;
5535
5536         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
5537             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
5538                 val = tr32(0x7c00);
5539
5540                 tw32(0x7c00, val | (1 << 25));
5541         }
5542
5543         /* Reprobe ASF enable state.  */
5544         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
5545         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
5546         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
5547         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
5548                 u32 nic_cfg;
5549
5550                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
5551                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
5552                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
5553                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
5554                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
5555                 }
5556         }
5557
5558         return 0;
5559 }
5560
5561 /* tp->lock is held. */
5562 static void tg3_stop_fw(struct tg3 *tp)
5563 {
5564         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
5565            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
5566                 u32 val;
5567
5568                 /* Wait for RX cpu to ACK the previous event. */
5569                 tg3_wait_for_event_ack(tp);
5570
5571                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
5572                 val = tr32(GRC_RX_CPU_EVENT);
5573                 val |= GRC_RX_CPU_DRIVER_EVENT;
5574                 tw32(GRC_RX_CPU_EVENT, val);
5575
5576                 /* Wait for RX cpu to ACK this event. */
5577                 tg3_wait_for_event_ack(tp);
5578         }
5579 }
5580
5581 /* tp->lock is held. */
5582 static int tg3_halt(struct tg3 *tp, int kind, int silent)
5583 {
5584         int err;
5585
5586         tg3_stop_fw(tp);
5587
5588         tg3_write_sig_pre_reset(tp, kind);
5589
5590         tg3_abort_hw(tp, silent);
5591         err = tg3_chip_reset(tp);
5592
5593         tg3_write_sig_legacy(tp, kind);
5594         tg3_write_sig_post_reset(tp, kind);
5595
5596         if (err)
5597                 return err;
5598
5599         return 0;
5600 }
5601
5602 #define TG3_FW_RELEASE_MAJOR    0x0
5603 #define TG3_FW_RELASE_MINOR     0x0
5604 #define TG3_FW_RELEASE_FIX      0x0
5605 #define TG3_FW_START_ADDR       0x08000000
5606 #define TG3_FW_TEXT_ADDR        0x08000000
5607 #define TG3_FW_TEXT_LEN         0x9c0
5608 #define TG3_FW_RODATA_ADDR      0x080009c0
5609 #define TG3_FW_RODATA_LEN       0x60
5610 #define TG3_FW_DATA_ADDR        0x08000a40
5611 #define TG3_FW_DATA_LEN         0x20
5612 #define TG3_FW_SBSS_ADDR        0x08000a60
5613 #define TG3_FW_SBSS_LEN         0xc
5614 #define TG3_FW_BSS_ADDR         0x08000a70
5615 #define TG3_FW_BSS_LEN          0x10
5616
5617 static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
5618         0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5619         0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5620         0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5621         0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
5622         0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
5623         0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
5624         0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
5625         0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
5626         0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
5627         0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
5628         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
5629         0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
5630         0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
5631         0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
5632         0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
5633         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5634         0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
5635         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
5636         0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
5637         0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5638         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
5639         0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
5640         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5641         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5642         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5643         0, 0, 0, 0, 0, 0,
5644         0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
5645         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5646         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5647         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5648         0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
5649         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
5650         0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
5651         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
5652         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5653         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5654         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
5655         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5656         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5657         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5658         0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
5659         0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
5660         0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
5661         0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
5662         0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
5663         0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
5664         0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
5665         0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
5666         0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
5667         0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
5668         0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
5669         0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
5670         0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
5671         0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
5672         0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
5673         0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
5674         0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
5675         0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
5676         0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
5677         0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
5678         0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
5679         0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
5680         0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
5681         0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
5682         0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
5683         0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
5684         0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
5685         0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
5686         0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
5687         0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
5688         0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
5689         0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
5690         0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
5691         0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
5692         0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
5693         0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
5694         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
5695         0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
5696         0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
5697         0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
5698         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
5699         0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
5700         0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
5701         0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
5702         0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
5703         0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
5704         0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
5705         0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
5706         0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
5707         0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
5708         0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
5709 };
5710
5711 static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
5712         0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
5713         0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
5714         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5715         0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
5716         0x00000000
5717 };
5718
5719 #if 0 /* All zeros, don't eat up space with it. */
5720 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
5721         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5722         0x00000000, 0x00000000, 0x00000000, 0x00000000
5723 };
5724 #endif
5725
5726 #define RX_CPU_SCRATCH_BASE     0x30000
5727 #define RX_CPU_SCRATCH_SIZE     0x04000
5728 #define TX_CPU_SCRATCH_BASE     0x34000
5729 #define TX_CPU_SCRATCH_SIZE     0x04000
5730
5731 /* tp->lock is held. */
5732 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
5733 {
5734         int i;
5735
5736         BUG_ON(offset == TX_CPU_BASE &&
5737             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
5738
5739         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5740                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
5741
5742                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
5743                 return 0;
5744         }
5745         if (offset == RX_CPU_BASE) {
5746                 for (i = 0; i < 10000; i++) {
5747                         tw32(offset + CPU_STATE,