f353f69caeb8357fa7f9c04d017b6ad9ede2cb2d
[linux-2.6.git] / drivers / net / tg3.c
1 /*
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  * Copyright (C) 2005-2007 Broadcom Corporation.
8  *
9  * Firmware is:
10  *      Derived from proprietary unpublished source code,
11  *      Copyright (C) 2000-2003 Broadcom Corporation.
12  *
13  *      Permission is hereby granted for the distribution of this firmware
14  *      data in hexadecimal or equivalent format, provided this copyright
15  *      notice is accompanying it.
16  */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
26 #include <linux/in.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/phy.h>
36 #include <linux/brcmphy.h>
37 #include <linux/if_vlan.h>
38 #include <linux/ip.h>
39 #include <linux/tcp.h>
40 #include <linux/workqueue.h>
41 #include <linux/prefetch.h>
42 #include <linux/dma-mapping.h>
43
44 #include <net/checksum.h>
45 #include <net/ip.h>
46
47 #include <asm/system.h>
48 #include <asm/io.h>
49 #include <asm/byteorder.h>
50 #include <asm/uaccess.h>
51
52 #ifdef CONFIG_SPARC
53 #include <asm/idprom.h>
54 #include <asm/prom.h>
55 #endif
56
57 #define BAR_0   0
58 #define BAR_2   2
59
60 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
61 #define TG3_VLAN_TAG_USED 1
62 #else
63 #define TG3_VLAN_TAG_USED 0
64 #endif
65
66 #define TG3_TSO_SUPPORT 1
67
68 #include "tg3.h"
69
70 #define DRV_MODULE_NAME         "tg3"
71 #define PFX DRV_MODULE_NAME     ": "
72 #define DRV_MODULE_VERSION      "3.96"
73 #define DRV_MODULE_RELDATE      "November 21, 2008"
74
75 #define TG3_DEF_MAC_MODE        0
76 #define TG3_DEF_RX_MODE         0
77 #define TG3_DEF_TX_MODE         0
78 #define TG3_DEF_MSG_ENABLE        \
79         (NETIF_MSG_DRV          | \
80          NETIF_MSG_PROBE        | \
81          NETIF_MSG_LINK         | \
82          NETIF_MSG_TIMER        | \
83          NETIF_MSG_IFDOWN       | \
84          NETIF_MSG_IFUP         | \
85          NETIF_MSG_RX_ERR       | \
86          NETIF_MSG_TX_ERR)
87
88 /* length of time before we decide the hardware is borked,
89  * and dev->tx_timeout() should be called to fix the problem
90  */
91 #define TG3_TX_TIMEOUT                  (5 * HZ)
92
93 /* hardware minimum and maximum for a single frame's data payload */
94 #define TG3_MIN_MTU                     60
95 #define TG3_MAX_MTU(tp) \
96         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
97
98 /* These numbers seem to be hard coded in the NIC firmware somehow.
99  * You can't change the ring sizes, but you can change where you place
100  * them in the NIC onboard memory.
101  */
102 #define TG3_RX_RING_SIZE                512
103 #define TG3_DEF_RX_RING_PENDING         200
104 #define TG3_RX_JUMBO_RING_SIZE          256
105 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
106
107 /* Do not place this n-ring entries value into the tp struct itself,
108  * we really want to expose these constants to GCC so that modulo et
109  * al.  operations are done with shifts and masks instead of with
110  * hw multiply/modulo instructions.  Another solution would be to
111  * replace things like '% foo' with '& (foo - 1)'.
112  */
113 #define TG3_RX_RCB_RING_SIZE(tp)        \
114         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
115
116 #define TG3_TX_RING_SIZE                512
117 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
118
119 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
120                                  TG3_RX_RING_SIZE)
121 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
122                                  TG3_RX_JUMBO_RING_SIZE)
123 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
124                                    TG3_RX_RCB_RING_SIZE(tp))
125 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
126                                  TG3_TX_RING_SIZE)
127 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
128
129 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
130 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
131
132 /* minimum number of free TX descriptors required to wake up TX process */
133 #define TG3_TX_WAKEUP_THRESH(tp)                ((tp)->tx_pending / 4)
134
135 #define TG3_RAW_IP_ALIGN 2
136
137 /* number of ETHTOOL_GSTATS u64's */
138 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
139
140 #define TG3_NUM_TEST            6
141
142 static char version[] __devinitdata =
143         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
144
145 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
146 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
147 MODULE_LICENSE("GPL");
148 MODULE_VERSION(DRV_MODULE_VERSION);
149
150 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
151 module_param(tg3_debug, int, 0);
152 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
153
154 static struct pci_device_id tg3_pci_tbl[] = {
155         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
156         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
157         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
158         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
159         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
160         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
161         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
162         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
163         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
164         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
165         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
166         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
167         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
168         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
169         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
170         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
171         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5785)},
216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57720)},
220         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
221         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
222         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
223         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
224         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
225         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
226         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
227         {}
228 };
229
230 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
231
232 static const struct {
233         const char string[ETH_GSTRING_LEN];
234 } ethtool_stats_keys[TG3_NUM_STATS] = {
235         { "rx_octets" },
236         { "rx_fragments" },
237         { "rx_ucast_packets" },
238         { "rx_mcast_packets" },
239         { "rx_bcast_packets" },
240         { "rx_fcs_errors" },
241         { "rx_align_errors" },
242         { "rx_xon_pause_rcvd" },
243         { "rx_xoff_pause_rcvd" },
244         { "rx_mac_ctrl_rcvd" },
245         { "rx_xoff_entered" },
246         { "rx_frame_too_long_errors" },
247         { "rx_jabbers" },
248         { "rx_undersize_packets" },
249         { "rx_in_length_errors" },
250         { "rx_out_length_errors" },
251         { "rx_64_or_less_octet_packets" },
252         { "rx_65_to_127_octet_packets" },
253         { "rx_128_to_255_octet_packets" },
254         { "rx_256_to_511_octet_packets" },
255         { "rx_512_to_1023_octet_packets" },
256         { "rx_1024_to_1522_octet_packets" },
257         { "rx_1523_to_2047_octet_packets" },
258         { "rx_2048_to_4095_octet_packets" },
259         { "rx_4096_to_8191_octet_packets" },
260         { "rx_8192_to_9022_octet_packets" },
261
262         { "tx_octets" },
263         { "tx_collisions" },
264
265         { "tx_xon_sent" },
266         { "tx_xoff_sent" },
267         { "tx_flow_control" },
268         { "tx_mac_errors" },
269         { "tx_single_collisions" },
270         { "tx_mult_collisions" },
271         { "tx_deferred" },
272         { "tx_excessive_collisions" },
273         { "tx_late_collisions" },
274         { "tx_collide_2times" },
275         { "tx_collide_3times" },
276         { "tx_collide_4times" },
277         { "tx_collide_5times" },
278         { "tx_collide_6times" },
279         { "tx_collide_7times" },
280         { "tx_collide_8times" },
281         { "tx_collide_9times" },
282         { "tx_collide_10times" },
283         { "tx_collide_11times" },
284         { "tx_collide_12times" },
285         { "tx_collide_13times" },
286         { "tx_collide_14times" },
287         { "tx_collide_15times" },
288         { "tx_ucast_packets" },
289         { "tx_mcast_packets" },
290         { "tx_bcast_packets" },
291         { "tx_carrier_sense_errors" },
292         { "tx_discards" },
293         { "tx_errors" },
294
295         { "dma_writeq_full" },
296         { "dma_write_prioq_full" },
297         { "rxbds_empty" },
298         { "rx_discards" },
299         { "rx_errors" },
300         { "rx_threshold_hit" },
301
302         { "dma_readq_full" },
303         { "dma_read_prioq_full" },
304         { "tx_comp_queue_full" },
305
306         { "ring_set_send_prod_index" },
307         { "ring_status_update" },
308         { "nic_irqs" },
309         { "nic_avoided_irqs" },
310         { "nic_tx_threshold_hit" }
311 };
312
313 static const struct {
314         const char string[ETH_GSTRING_LEN];
315 } ethtool_test_keys[TG3_NUM_TEST] = {
316         { "nvram test     (online) " },
317         { "link test      (online) " },
318         { "register test  (offline)" },
319         { "memory test    (offline)" },
320         { "loopback test  (offline)" },
321         { "interrupt test (offline)" },
322 };
323
324 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
325 {
326         writel(val, tp->regs + off);
327 }
328
329 static u32 tg3_read32(struct tg3 *tp, u32 off)
330 {
331         return (readl(tp->regs + off));
332 }
333
334 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
335 {
336         writel(val, tp->aperegs + off);
337 }
338
339 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
340 {
341         return (readl(tp->aperegs + off));
342 }
343
344 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
345 {
346         unsigned long flags;
347
348         spin_lock_irqsave(&tp->indirect_lock, flags);
349         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
350         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
351         spin_unlock_irqrestore(&tp->indirect_lock, flags);
352 }
353
354 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
355 {
356         writel(val, tp->regs + off);
357         readl(tp->regs + off);
358 }
359
360 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
361 {
362         unsigned long flags;
363         u32 val;
364
365         spin_lock_irqsave(&tp->indirect_lock, flags);
366         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
367         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
368         spin_unlock_irqrestore(&tp->indirect_lock, flags);
369         return val;
370 }
371
372 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
373 {
374         unsigned long flags;
375
376         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
377                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
378                                        TG3_64BIT_REG_LOW, val);
379                 return;
380         }
381         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
382                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
383                                        TG3_64BIT_REG_LOW, val);
384                 return;
385         }
386
387         spin_lock_irqsave(&tp->indirect_lock, flags);
388         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
389         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
390         spin_unlock_irqrestore(&tp->indirect_lock, flags);
391
392         /* In indirect mode when disabling interrupts, we also need
393          * to clear the interrupt bit in the GRC local ctrl register.
394          */
395         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
396             (val == 0x1)) {
397                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
398                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
399         }
400 }
401
402 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
403 {
404         unsigned long flags;
405         u32 val;
406
407         spin_lock_irqsave(&tp->indirect_lock, flags);
408         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
409         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
410         spin_unlock_irqrestore(&tp->indirect_lock, flags);
411         return val;
412 }
413
414 /* usec_wait specifies the wait time in usec when writing to certain registers
415  * where it is unsafe to read back the register without some delay.
416  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
417  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
418  */
419 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
420 {
421         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
422             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
423                 /* Non-posted methods */
424                 tp->write32(tp, off, val);
425         else {
426                 /* Posted method */
427                 tg3_write32(tp, off, val);
428                 if (usec_wait)
429                         udelay(usec_wait);
430                 tp->read32(tp, off);
431         }
432         /* Wait again after the read for the posted method to guarantee that
433          * the wait time is met.
434          */
435         if (usec_wait)
436                 udelay(usec_wait);
437 }
438
439 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
440 {
441         tp->write32_mbox(tp, off, val);
442         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
443             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
444                 tp->read32_mbox(tp, off);
445 }
446
447 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
448 {
449         void __iomem *mbox = tp->regs + off;
450         writel(val, mbox);
451         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
452                 writel(val, mbox);
453         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
454                 readl(mbox);
455 }
456
457 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
458 {
459         return (readl(tp->regs + off + GRCMBOX_BASE));
460 }
461
462 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
463 {
464         writel(val, tp->regs + off + GRCMBOX_BASE);
465 }
466
467 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
468 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
469 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
470 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
471 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
472
473 #define tw32(reg,val)           tp->write32(tp, reg, val)
474 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
475 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
476 #define tr32(reg)               tp->read32(tp, reg)
477
478 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
479 {
480         unsigned long flags;
481
482         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
483             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
484                 return;
485
486         spin_lock_irqsave(&tp->indirect_lock, flags);
487         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
488                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
489                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
490
491                 /* Always leave this as zero. */
492                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
493         } else {
494                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
495                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
496
497                 /* Always leave this as zero. */
498                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
499         }
500         spin_unlock_irqrestore(&tp->indirect_lock, flags);
501 }
502
503 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
504 {
505         unsigned long flags;
506
507         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
508             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
509                 *val = 0;
510                 return;
511         }
512
513         spin_lock_irqsave(&tp->indirect_lock, flags);
514         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
515                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
516                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
517
518                 /* Always leave this as zero. */
519                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
520         } else {
521                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
522                 *val = tr32(TG3PCI_MEM_WIN_DATA);
523
524                 /* Always leave this as zero. */
525                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
526         }
527         spin_unlock_irqrestore(&tp->indirect_lock, flags);
528 }
529
530 static void tg3_ape_lock_init(struct tg3 *tp)
531 {
532         int i;
533
534         /* Make sure the driver hasn't any stale locks. */
535         for (i = 0; i < 8; i++)
536                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
537                                 APE_LOCK_GRANT_DRIVER);
538 }
539
540 static int tg3_ape_lock(struct tg3 *tp, int locknum)
541 {
542         int i, off;
543         int ret = 0;
544         u32 status;
545
546         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
547                 return 0;
548
549         switch (locknum) {
550                 case TG3_APE_LOCK_GRC:
551                 case TG3_APE_LOCK_MEM:
552                         break;
553                 default:
554                         return -EINVAL;
555         }
556
557         off = 4 * locknum;
558
559         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
560
561         /* Wait for up to 1 millisecond to acquire lock. */
562         for (i = 0; i < 100; i++) {
563                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
564                 if (status == APE_LOCK_GRANT_DRIVER)
565                         break;
566                 udelay(10);
567         }
568
569         if (status != APE_LOCK_GRANT_DRIVER) {
570                 /* Revoke the lock request. */
571                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
572                                 APE_LOCK_GRANT_DRIVER);
573
574                 ret = -EBUSY;
575         }
576
577         return ret;
578 }
579
580 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
581 {
582         int off;
583
584         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
585                 return;
586
587         switch (locknum) {
588                 case TG3_APE_LOCK_GRC:
589                 case TG3_APE_LOCK_MEM:
590                         break;
591                 default:
592                         return;
593         }
594
595         off = 4 * locknum;
596         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
597 }
598
599 static void tg3_disable_ints(struct tg3 *tp)
600 {
601         tw32(TG3PCI_MISC_HOST_CTRL,
602              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
603         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
604 }
605
606 static inline void tg3_cond_int(struct tg3 *tp)
607 {
608         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
609             (tp->hw_status->status & SD_STATUS_UPDATED))
610                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
611         else
612                 tw32(HOSTCC_MODE, tp->coalesce_mode |
613                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
614 }
615
616 static void tg3_enable_ints(struct tg3 *tp)
617 {
618         tp->irq_sync = 0;
619         wmb();
620
621         tw32(TG3PCI_MISC_HOST_CTRL,
622              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
623         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
624                        (tp->last_tag << 24));
625         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
626                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
627                                (tp->last_tag << 24));
628         tg3_cond_int(tp);
629 }
630
631 static inline unsigned int tg3_has_work(struct tg3 *tp)
632 {
633         struct tg3_hw_status *sblk = tp->hw_status;
634         unsigned int work_exists = 0;
635
636         /* check for phy events */
637         if (!(tp->tg3_flags &
638               (TG3_FLAG_USE_LINKCHG_REG |
639                TG3_FLAG_POLL_SERDES))) {
640                 if (sblk->status & SD_STATUS_LINK_CHG)
641                         work_exists = 1;
642         }
643         /* check for RX/TX work to do */
644         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
645             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
646                 work_exists = 1;
647
648         return work_exists;
649 }
650
651 /* tg3_restart_ints
652  *  similar to tg3_enable_ints, but it accurately determines whether there
653  *  is new work pending and can return without flushing the PIO write
654  *  which reenables interrupts
655  */
656 static void tg3_restart_ints(struct tg3 *tp)
657 {
658         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
659                      tp->last_tag << 24);
660         mmiowb();
661
662         /* When doing tagged status, this work check is unnecessary.
663          * The last_tag we write above tells the chip which piece of
664          * work we've completed.
665          */
666         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
667             tg3_has_work(tp))
668                 tw32(HOSTCC_MODE, tp->coalesce_mode |
669                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
670 }
671
672 static inline void tg3_netif_stop(struct tg3 *tp)
673 {
674         tp->dev->trans_start = jiffies; /* prevent tx timeout */
675         napi_disable(&tp->napi);
676         netif_tx_disable(tp->dev);
677 }
678
679 static inline void tg3_netif_start(struct tg3 *tp)
680 {
681         netif_wake_queue(tp->dev);
682         /* NOTE: unconditional netif_wake_queue is only appropriate
683          * so long as all callers are assured to have free tx slots
684          * (such as after tg3_init_hw)
685          */
686         napi_enable(&tp->napi);
687         tp->hw_status->status |= SD_STATUS_UPDATED;
688         tg3_enable_ints(tp);
689 }
690
691 static void tg3_switch_clocks(struct tg3 *tp)
692 {
693         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
694         u32 orig_clock_ctrl;
695
696         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
697             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
698                 return;
699
700         orig_clock_ctrl = clock_ctrl;
701         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
702                        CLOCK_CTRL_CLKRUN_OENABLE |
703                        0x1f);
704         tp->pci_clock_ctrl = clock_ctrl;
705
706         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
707                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
708                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
709                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
710                 }
711         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
712                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
713                             clock_ctrl |
714                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
715                             40);
716                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
717                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
718                             40);
719         }
720         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
721 }
722
723 #define PHY_BUSY_LOOPS  5000
724
725 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
726 {
727         u32 frame_val;
728         unsigned int loops;
729         int ret;
730
731         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
732                 tw32_f(MAC_MI_MODE,
733                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
734                 udelay(80);
735         }
736
737         *val = 0x0;
738
739         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
740                       MI_COM_PHY_ADDR_MASK);
741         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
742                       MI_COM_REG_ADDR_MASK);
743         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
744
745         tw32_f(MAC_MI_COM, frame_val);
746
747         loops = PHY_BUSY_LOOPS;
748         while (loops != 0) {
749                 udelay(10);
750                 frame_val = tr32(MAC_MI_COM);
751
752                 if ((frame_val & MI_COM_BUSY) == 0) {
753                         udelay(5);
754                         frame_val = tr32(MAC_MI_COM);
755                         break;
756                 }
757                 loops -= 1;
758         }
759
760         ret = -EBUSY;
761         if (loops != 0) {
762                 *val = frame_val & MI_COM_DATA_MASK;
763                 ret = 0;
764         }
765
766         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
767                 tw32_f(MAC_MI_MODE, tp->mi_mode);
768                 udelay(80);
769         }
770
771         return ret;
772 }
773
774 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
775 {
776         u32 frame_val;
777         unsigned int loops;
778         int ret;
779
780         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
781             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
782                 return 0;
783
784         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
785                 tw32_f(MAC_MI_MODE,
786                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
787                 udelay(80);
788         }
789
790         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
791                       MI_COM_PHY_ADDR_MASK);
792         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
793                       MI_COM_REG_ADDR_MASK);
794         frame_val |= (val & MI_COM_DATA_MASK);
795         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
796
797         tw32_f(MAC_MI_COM, frame_val);
798
799         loops = PHY_BUSY_LOOPS;
800         while (loops != 0) {
801                 udelay(10);
802                 frame_val = tr32(MAC_MI_COM);
803                 if ((frame_val & MI_COM_BUSY) == 0) {
804                         udelay(5);
805                         frame_val = tr32(MAC_MI_COM);
806                         break;
807                 }
808                 loops -= 1;
809         }
810
811         ret = -EBUSY;
812         if (loops != 0)
813                 ret = 0;
814
815         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
816                 tw32_f(MAC_MI_MODE, tp->mi_mode);
817                 udelay(80);
818         }
819
820         return ret;
821 }
822
823 static int tg3_bmcr_reset(struct tg3 *tp)
824 {
825         u32 phy_control;
826         int limit, err;
827
828         /* OK, reset it, and poll the BMCR_RESET bit until it
829          * clears or we time out.
830          */
831         phy_control = BMCR_RESET;
832         err = tg3_writephy(tp, MII_BMCR, phy_control);
833         if (err != 0)
834                 return -EBUSY;
835
836         limit = 5000;
837         while (limit--) {
838                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
839                 if (err != 0)
840                         return -EBUSY;
841
842                 if ((phy_control & BMCR_RESET) == 0) {
843                         udelay(40);
844                         break;
845                 }
846                 udelay(10);
847         }
848         if (limit <= 0)
849                 return -EBUSY;
850
851         return 0;
852 }
853
854 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
855 {
856         struct tg3 *tp = (struct tg3 *)bp->priv;
857         u32 val;
858
859         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
860                 return -EAGAIN;
861
862         if (tg3_readphy(tp, reg, &val))
863                 return -EIO;
864
865         return val;
866 }
867
868 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
869 {
870         struct tg3 *tp = (struct tg3 *)bp->priv;
871
872         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
873                 return -EAGAIN;
874
875         if (tg3_writephy(tp, reg, val))
876                 return -EIO;
877
878         return 0;
879 }
880
881 static int tg3_mdio_reset(struct mii_bus *bp)
882 {
883         return 0;
884 }
885
886 static void tg3_mdio_config_5785(struct tg3 *tp)
887 {
888         u32 val;
889         struct phy_device *phydev;
890
891         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
892         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
893         case TG3_PHY_ID_BCM50610:
894                 val = MAC_PHYCFG2_50610_LED_MODES;
895                 break;
896         case TG3_PHY_ID_BCMAC131:
897                 val = MAC_PHYCFG2_AC131_LED_MODES;
898                 break;
899         case TG3_PHY_ID_RTL8211C:
900                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
901                 break;
902         case TG3_PHY_ID_RTL8201E:
903                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
904                 break;
905         default:
906                 return;
907         }
908
909         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
910                 tw32(MAC_PHYCFG2, val);
911
912                 val = tr32(MAC_PHYCFG1);
913                 val &= ~MAC_PHYCFG1_RGMII_INT;
914                 tw32(MAC_PHYCFG1, val);
915
916                 return;
917         }
918
919         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
920                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
921                        MAC_PHYCFG2_FMODE_MASK_MASK |
922                        MAC_PHYCFG2_GMODE_MASK_MASK |
923                        MAC_PHYCFG2_ACT_MASK_MASK   |
924                        MAC_PHYCFG2_QUAL_MASK_MASK |
925                        MAC_PHYCFG2_INBAND_ENABLE;
926
927         tw32(MAC_PHYCFG2, val);
928
929         val = tr32(MAC_PHYCFG1) & ~(MAC_PHYCFG1_RGMII_EXT_RX_DEC |
930                                     MAC_PHYCFG1_RGMII_SND_STAT_EN);
931         if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {
932                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
933                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
934                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
935                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
936         }
937         tw32(MAC_PHYCFG1, val | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV);
938
939         val = tr32(MAC_EXT_RGMII_MODE);
940         val &= ~(MAC_RGMII_MODE_RX_INT_B |
941                  MAC_RGMII_MODE_RX_QUALITY |
942                  MAC_RGMII_MODE_RX_ACTIVITY |
943                  MAC_RGMII_MODE_RX_ENG_DET |
944                  MAC_RGMII_MODE_TX_ENABLE |
945                  MAC_RGMII_MODE_TX_LOWPWR |
946                  MAC_RGMII_MODE_TX_RESET);
947         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
948                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
949                         val |= MAC_RGMII_MODE_RX_INT_B |
950                                MAC_RGMII_MODE_RX_QUALITY |
951                                MAC_RGMII_MODE_RX_ACTIVITY |
952                                MAC_RGMII_MODE_RX_ENG_DET;
953                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
954                         val |= MAC_RGMII_MODE_TX_ENABLE |
955                                MAC_RGMII_MODE_TX_LOWPWR |
956                                MAC_RGMII_MODE_TX_RESET;
957         }
958         tw32(MAC_EXT_RGMII_MODE, val);
959 }
960
961 static void tg3_mdio_start(struct tg3 *tp)
962 {
963         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
964                 mutex_lock(&tp->mdio_bus->mdio_lock);
965                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
966                 mutex_unlock(&tp->mdio_bus->mdio_lock);
967         }
968
969         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
970         tw32_f(MAC_MI_MODE, tp->mi_mode);
971         udelay(80);
972
973         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
974             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
975                 tg3_mdio_config_5785(tp);
976 }
977
978 static void tg3_mdio_stop(struct tg3 *tp)
979 {
980         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
981                 mutex_lock(&tp->mdio_bus->mdio_lock);
982                 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
983                 mutex_unlock(&tp->mdio_bus->mdio_lock);
984         }
985 }
986
987 static int tg3_mdio_init(struct tg3 *tp)
988 {
989         int i;
990         u32 reg;
991         struct phy_device *phydev;
992
993         tg3_mdio_start(tp);
994
995         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
996             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
997                 return 0;
998
999         tp->mdio_bus = mdiobus_alloc();
1000         if (tp->mdio_bus == NULL)
1001                 return -ENOMEM;
1002
1003         tp->mdio_bus->name     = "tg3 mdio bus";
1004         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1005                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1006         tp->mdio_bus->priv     = tp;
1007         tp->mdio_bus->parent   = &tp->pdev->dev;
1008         tp->mdio_bus->read     = &tg3_mdio_read;
1009         tp->mdio_bus->write    = &tg3_mdio_write;
1010         tp->mdio_bus->reset    = &tg3_mdio_reset;
1011         tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
1012         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1013
1014         for (i = 0; i < PHY_MAX_ADDR; i++)
1015                 tp->mdio_bus->irq[i] = PHY_POLL;
1016
1017         /* The bus registration will look for all the PHYs on the mdio bus.
1018          * Unfortunately, it does not ensure the PHY is powered up before
1019          * accessing the PHY ID registers.  A chip reset is the
1020          * quickest way to bring the device back to an operational state..
1021          */
1022         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1023                 tg3_bmcr_reset(tp);
1024
1025         i = mdiobus_register(tp->mdio_bus);
1026         if (i) {
1027                 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1028                         tp->dev->name, i);
1029                 mdiobus_free(tp->mdio_bus);
1030                 return i;
1031         }
1032
1033         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1034
1035         if (!phydev || !phydev->drv) {
1036                 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1037                 mdiobus_unregister(tp->mdio_bus);
1038                 mdiobus_free(tp->mdio_bus);
1039                 return -ENODEV;
1040         }
1041
1042         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1043         case TG3_PHY_ID_BCM57780:
1044                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1045                 break;
1046         case TG3_PHY_ID_BCM50610:
1047                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1048                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1049                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1050                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1051                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1052                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1053                 /* fallthru */
1054         case TG3_PHY_ID_RTL8211C:
1055                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1056                 break;
1057         case TG3_PHY_ID_RTL8201E:
1058         case TG3_PHY_ID_BCMAC131:
1059                 phydev->interface = PHY_INTERFACE_MODE_MII;
1060                 break;
1061         }
1062
1063         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1064
1065         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1066                 tg3_mdio_config_5785(tp);
1067
1068         return 0;
1069 }
1070
1071 static void tg3_mdio_fini(struct tg3 *tp)
1072 {
1073         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1074                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1075                 mdiobus_unregister(tp->mdio_bus);
1076                 mdiobus_free(tp->mdio_bus);
1077                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1078         }
1079 }
1080
1081 /* tp->lock is held. */
1082 static inline void tg3_generate_fw_event(struct tg3 *tp)
1083 {
1084         u32 val;
1085
1086         val = tr32(GRC_RX_CPU_EVENT);
1087         val |= GRC_RX_CPU_DRIVER_EVENT;
1088         tw32_f(GRC_RX_CPU_EVENT, val);
1089
1090         tp->last_event_jiffies = jiffies;
1091 }
1092
1093 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1094
1095 /* tp->lock is held. */
1096 static void tg3_wait_for_event_ack(struct tg3 *tp)
1097 {
1098         int i;
1099         unsigned int delay_cnt;
1100         long time_remain;
1101
1102         /* If enough time has passed, no wait is necessary. */
1103         time_remain = (long)(tp->last_event_jiffies + 1 +
1104                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1105                       (long)jiffies;
1106         if (time_remain < 0)
1107                 return;
1108
1109         /* Check if we can shorten the wait time. */
1110         delay_cnt = jiffies_to_usecs(time_remain);
1111         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1112                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1113         delay_cnt = (delay_cnt >> 3) + 1;
1114
1115         for (i = 0; i < delay_cnt; i++) {
1116                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1117                         break;
1118                 udelay(8);
1119         }
1120 }
1121
1122 /* tp->lock is held. */
1123 static void tg3_ump_link_report(struct tg3 *tp)
1124 {
1125         u32 reg;
1126         u32 val;
1127
1128         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1129             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1130                 return;
1131
1132         tg3_wait_for_event_ack(tp);
1133
1134         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1135
1136         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1137
1138         val = 0;
1139         if (!tg3_readphy(tp, MII_BMCR, &reg))
1140                 val = reg << 16;
1141         if (!tg3_readphy(tp, MII_BMSR, &reg))
1142                 val |= (reg & 0xffff);
1143         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1144
1145         val = 0;
1146         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1147                 val = reg << 16;
1148         if (!tg3_readphy(tp, MII_LPA, &reg))
1149                 val |= (reg & 0xffff);
1150         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1151
1152         val = 0;
1153         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1154                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1155                         val = reg << 16;
1156                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1157                         val |= (reg & 0xffff);
1158         }
1159         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1160
1161         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1162                 val = reg << 16;
1163         else
1164                 val = 0;
1165         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1166
1167         tg3_generate_fw_event(tp);
1168 }
1169
1170 static void tg3_link_report(struct tg3 *tp)
1171 {
1172         if (!netif_carrier_ok(tp->dev)) {
1173                 if (netif_msg_link(tp))
1174                         printk(KERN_INFO PFX "%s: Link is down.\n",
1175                                tp->dev->name);
1176                 tg3_ump_link_report(tp);
1177         } else if (netif_msg_link(tp)) {
1178                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1179                        tp->dev->name,
1180                        (tp->link_config.active_speed == SPEED_1000 ?
1181                         1000 :
1182                         (tp->link_config.active_speed == SPEED_100 ?
1183                          100 : 10)),
1184                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1185                         "full" : "half"));
1186
1187                 printk(KERN_INFO PFX
1188                        "%s: Flow control is %s for TX and %s for RX.\n",
1189                        tp->dev->name,
1190                        (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1191                        "on" : "off",
1192                        (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1193                        "on" : "off");
1194                 tg3_ump_link_report(tp);
1195         }
1196 }
1197
1198 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1199 {
1200         u16 miireg;
1201
1202         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1203                 miireg = ADVERTISE_PAUSE_CAP;
1204         else if (flow_ctrl & FLOW_CTRL_TX)
1205                 miireg = ADVERTISE_PAUSE_ASYM;
1206         else if (flow_ctrl & FLOW_CTRL_RX)
1207                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1208         else
1209                 miireg = 0;
1210
1211         return miireg;
1212 }
1213
1214 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1215 {
1216         u16 miireg;
1217
1218         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1219                 miireg = ADVERTISE_1000XPAUSE;
1220         else if (flow_ctrl & FLOW_CTRL_TX)
1221                 miireg = ADVERTISE_1000XPSE_ASYM;
1222         else if (flow_ctrl & FLOW_CTRL_RX)
1223                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1224         else
1225                 miireg = 0;
1226
1227         return miireg;
1228 }
1229
1230 static u8 tg3_resolve_flowctrl_1000T(u16 lcladv, u16 rmtadv)
1231 {
1232         u8 cap = 0;
1233
1234         if (lcladv & ADVERTISE_PAUSE_CAP) {
1235                 if (lcladv & ADVERTISE_PAUSE_ASYM) {
1236                         if (rmtadv & LPA_PAUSE_CAP)
1237                                 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1238                         else if (rmtadv & LPA_PAUSE_ASYM)
1239                                 cap = TG3_FLOW_CTRL_RX;
1240                 } else {
1241                         if (rmtadv & LPA_PAUSE_CAP)
1242                                 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1243                 }
1244         } else if (lcladv & ADVERTISE_PAUSE_ASYM) {
1245                 if ((rmtadv & LPA_PAUSE_CAP) && (rmtadv & LPA_PAUSE_ASYM))
1246                         cap = TG3_FLOW_CTRL_TX;
1247         }
1248
1249         return cap;
1250 }
1251
1252 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1253 {
1254         u8 cap = 0;
1255
1256         if (lcladv & ADVERTISE_1000XPAUSE) {
1257                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1258                         if (rmtadv & LPA_1000XPAUSE)
1259                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1260                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1261                                 cap = FLOW_CTRL_RX;
1262                 } else {
1263                         if (rmtadv & LPA_1000XPAUSE)
1264                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1265                 }
1266         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1267                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1268                         cap = FLOW_CTRL_TX;
1269         }
1270
1271         return cap;
1272 }
1273
1274 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1275 {
1276         u8 autoneg;
1277         u8 flowctrl = 0;
1278         u32 old_rx_mode = tp->rx_mode;
1279         u32 old_tx_mode = tp->tx_mode;
1280
1281         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1282                 autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
1283         else
1284                 autoneg = tp->link_config.autoneg;
1285
1286         if (autoneg == AUTONEG_ENABLE &&
1287             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1288                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1289                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1290                 else
1291                         flowctrl = tg3_resolve_flowctrl_1000T(lcladv, rmtadv);
1292         } else
1293                 flowctrl = tp->link_config.flowctrl;
1294
1295         tp->link_config.active_flowctrl = flowctrl;
1296
1297         if (flowctrl & FLOW_CTRL_RX)
1298                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1299         else
1300                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1301
1302         if (old_rx_mode != tp->rx_mode)
1303                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1304
1305         if (flowctrl & FLOW_CTRL_TX)
1306                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1307         else
1308                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1309
1310         if (old_tx_mode != tp->tx_mode)
1311                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1312 }
1313
1314 static void tg3_adjust_link(struct net_device *dev)
1315 {
1316         u8 oldflowctrl, linkmesg = 0;
1317         u32 mac_mode, lcl_adv, rmt_adv;
1318         struct tg3 *tp = netdev_priv(dev);
1319         struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1320
1321         spin_lock(&tp->lock);
1322
1323         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1324                                     MAC_MODE_HALF_DUPLEX);
1325
1326         oldflowctrl = tp->link_config.active_flowctrl;
1327
1328         if (phydev->link) {
1329                 lcl_adv = 0;
1330                 rmt_adv = 0;
1331
1332                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1333                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1334                 else
1335                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1336
1337                 if (phydev->duplex == DUPLEX_HALF)
1338                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1339                 else {
1340                         lcl_adv = tg3_advert_flowctrl_1000T(
1341                                   tp->link_config.flowctrl);
1342
1343                         if (phydev->pause)
1344                                 rmt_adv = LPA_PAUSE_CAP;
1345                         if (phydev->asym_pause)
1346                                 rmt_adv |= LPA_PAUSE_ASYM;
1347                 }
1348
1349                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1350         } else
1351                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1352
1353         if (mac_mode != tp->mac_mode) {
1354                 tp->mac_mode = mac_mode;
1355                 tw32_f(MAC_MODE, tp->mac_mode);
1356                 udelay(40);
1357         }
1358
1359         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1360                 if (phydev->speed == SPEED_10)
1361                         tw32(MAC_MI_STAT,
1362                              MAC_MI_STAT_10MBPS_MODE |
1363                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1364                 else
1365                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1366         }
1367
1368         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1369                 tw32(MAC_TX_LENGTHS,
1370                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1371                       (6 << TX_LENGTHS_IPG_SHIFT) |
1372                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1373         else
1374                 tw32(MAC_TX_LENGTHS,
1375                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1376                       (6 << TX_LENGTHS_IPG_SHIFT) |
1377                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1378
1379         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1380             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1381             phydev->speed != tp->link_config.active_speed ||
1382             phydev->duplex != tp->link_config.active_duplex ||
1383             oldflowctrl != tp->link_config.active_flowctrl)
1384             linkmesg = 1;
1385
1386         tp->link_config.active_speed = phydev->speed;
1387         tp->link_config.active_duplex = phydev->duplex;
1388
1389         spin_unlock(&tp->lock);
1390
1391         if (linkmesg)
1392                 tg3_link_report(tp);
1393 }
1394
1395 static int tg3_phy_init(struct tg3 *tp)
1396 {
1397         struct phy_device *phydev;
1398
1399         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1400                 return 0;
1401
1402         /* Bring the PHY back to a known state. */
1403         tg3_bmcr_reset(tp);
1404
1405         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1406
1407         /* Attach the MAC to the PHY. */
1408         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1409                              phydev->dev_flags, phydev->interface);
1410         if (IS_ERR(phydev)) {
1411                 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1412                 return PTR_ERR(phydev);
1413         }
1414
1415         /* Mask with MAC supported features. */
1416         switch (phydev->interface) {
1417         case PHY_INTERFACE_MODE_GMII:
1418         case PHY_INTERFACE_MODE_RGMII:
1419                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1420                         phydev->supported &= (PHY_GBIT_FEATURES |
1421                                               SUPPORTED_Pause |
1422                                               SUPPORTED_Asym_Pause);
1423                         break;
1424                 }
1425                 /* fallthru */
1426         case PHY_INTERFACE_MODE_MII:
1427                 phydev->supported &= (PHY_BASIC_FEATURES |
1428                                       SUPPORTED_Pause |
1429                                       SUPPORTED_Asym_Pause);
1430                 break;
1431         default:
1432                 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1433                 return -EINVAL;
1434         }
1435
1436         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1437
1438         phydev->advertising = phydev->supported;
1439
1440         return 0;
1441 }
1442
1443 static void tg3_phy_start(struct tg3 *tp)
1444 {
1445         struct phy_device *phydev;
1446
1447         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1448                 return;
1449
1450         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1451
1452         if (tp->link_config.phy_is_low_power) {
1453                 tp->link_config.phy_is_low_power = 0;
1454                 phydev->speed = tp->link_config.orig_speed;
1455                 phydev->duplex = tp->link_config.orig_duplex;
1456                 phydev->autoneg = tp->link_config.orig_autoneg;
1457                 phydev->advertising = tp->link_config.orig_advertising;
1458         }
1459
1460         phy_start(phydev);
1461
1462         phy_start_aneg(phydev);
1463 }
1464
1465 static void tg3_phy_stop(struct tg3 *tp)
1466 {
1467         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1468                 return;
1469
1470         phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
1471 }
1472
1473 static void tg3_phy_fini(struct tg3 *tp)
1474 {
1475         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1476                 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1477                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1478         }
1479 }
1480
1481 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1482 {
1483         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1484         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1485 }
1486
1487 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1488 {
1489         u32 reg;
1490
1491         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1492                 return;
1493
1494         reg = MII_TG3_MISC_SHDW_WREN |
1495               MII_TG3_MISC_SHDW_SCR5_SEL |
1496               MII_TG3_MISC_SHDW_SCR5_LPED |
1497               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1498               MII_TG3_MISC_SHDW_SCR5_SDTL |
1499               MII_TG3_MISC_SHDW_SCR5_C125OE;
1500         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1501                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1502
1503         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1504
1505
1506         reg = MII_TG3_MISC_SHDW_WREN |
1507               MII_TG3_MISC_SHDW_APD_SEL |
1508               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1509         if (enable)
1510                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1511
1512         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1513 }
1514
1515 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1516 {
1517         u32 phy;
1518
1519         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1520             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1521                 return;
1522
1523         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1524                 u32 ephy;
1525
1526                 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
1527                         tg3_writephy(tp, MII_TG3_EPHY_TEST,
1528                                      ephy | MII_TG3_EPHY_SHADOW_EN);
1529                         if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
1530                                 if (enable)
1531                                         phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
1532                                 else
1533                                         phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
1534                                 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
1535                         }
1536                         tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
1537                 }
1538         } else {
1539                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1540                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1541                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1542                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1543                         if (enable)
1544                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1545                         else
1546                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1547                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1548                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1549                 }
1550         }
1551 }
1552
1553 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1554 {
1555         u32 val;
1556
1557         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1558                 return;
1559
1560         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1561             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1562                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1563                              (val | (1 << 15) | (1 << 4)));
1564 }
1565
1566 static void tg3_phy_apply_otp(struct tg3 *tp)
1567 {
1568         u32 otp, phy;
1569
1570         if (!tp->phy_otp)
1571                 return;
1572
1573         otp = tp->phy_otp;
1574
1575         /* Enable SM_DSP clock and tx 6dB coding. */
1576         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1577               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1578               MII_TG3_AUXCTL_ACTL_TX_6DB;
1579         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1580
1581         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1582         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1583         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1584
1585         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1586               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1587         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1588
1589         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1590         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1591         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1592
1593         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1594         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1595
1596         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1597         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1598
1599         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1600               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1601         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1602
1603         /* Turn off SM_DSP clock. */
1604         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1605               MII_TG3_AUXCTL_ACTL_TX_6DB;
1606         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1607 }
1608
1609 static int tg3_wait_macro_done(struct tg3 *tp)
1610 {
1611         int limit = 100;
1612
1613         while (limit--) {
1614                 u32 tmp32;
1615
1616                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1617                         if ((tmp32 & 0x1000) == 0)
1618                                 break;
1619                 }
1620         }
1621         if (limit <= 0)
1622                 return -EBUSY;
1623
1624         return 0;
1625 }
1626
1627 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1628 {
1629         static const u32 test_pat[4][6] = {
1630         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1631         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1632         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1633         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1634         };
1635         int chan;
1636
1637         for (chan = 0; chan < 4; chan++) {
1638                 int i;
1639
1640                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1641                              (chan * 0x2000) | 0x0200);
1642                 tg3_writephy(tp, 0x16, 0x0002);
1643
1644                 for (i = 0; i < 6; i++)
1645                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1646                                      test_pat[chan][i]);
1647
1648                 tg3_writephy(tp, 0x16, 0x0202);
1649                 if (tg3_wait_macro_done(tp)) {
1650                         *resetp = 1;
1651                         return -EBUSY;
1652                 }
1653
1654                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1655                              (chan * 0x2000) | 0x0200);
1656                 tg3_writephy(tp, 0x16, 0x0082);
1657                 if (tg3_wait_macro_done(tp)) {
1658                         *resetp = 1;
1659                         return -EBUSY;
1660                 }
1661
1662                 tg3_writephy(tp, 0x16, 0x0802);
1663                 if (tg3_wait_macro_done(tp)) {
1664                         *resetp = 1;
1665                         return -EBUSY;
1666                 }
1667
1668                 for (i = 0; i < 6; i += 2) {
1669                         u32 low, high;
1670
1671                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1672                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1673                             tg3_wait_macro_done(tp)) {
1674                                 *resetp = 1;
1675                                 return -EBUSY;
1676                         }
1677                         low &= 0x7fff;
1678                         high &= 0x000f;
1679                         if (low != test_pat[chan][i] ||
1680                             high != test_pat[chan][i+1]) {
1681                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1682                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1683                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1684
1685                                 return -EBUSY;
1686                         }
1687                 }
1688         }
1689
1690         return 0;
1691 }
1692
1693 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1694 {
1695         int chan;
1696
1697         for (chan = 0; chan < 4; chan++) {
1698                 int i;
1699
1700                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1701                              (chan * 0x2000) | 0x0200);
1702                 tg3_writephy(tp, 0x16, 0x0002);
1703                 for (i = 0; i < 6; i++)
1704                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1705                 tg3_writephy(tp, 0x16, 0x0202);
1706                 if (tg3_wait_macro_done(tp))
1707                         return -EBUSY;
1708         }
1709
1710         return 0;
1711 }
1712
1713 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1714 {
1715         u32 reg32, phy9_orig;
1716         int retries, do_phy_reset, err;
1717
1718         retries = 10;
1719         do_phy_reset = 1;
1720         do {
1721                 if (do_phy_reset) {
1722                         err = tg3_bmcr_reset(tp);
1723                         if (err)
1724                                 return err;
1725                         do_phy_reset = 0;
1726                 }
1727
1728                 /* Disable transmitter and interrupt.  */
1729                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1730                         continue;
1731
1732                 reg32 |= 0x3000;
1733                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1734
1735                 /* Set full-duplex, 1000 mbps.  */
1736                 tg3_writephy(tp, MII_BMCR,
1737                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1738
1739                 /* Set to master mode.  */
1740                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1741                         continue;
1742
1743                 tg3_writephy(tp, MII_TG3_CTRL,
1744                              (MII_TG3_CTRL_AS_MASTER |
1745                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1746
1747                 /* Enable SM_DSP_CLOCK and 6dB.  */
1748                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1749
1750                 /* Block the PHY control access.  */
1751                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1752                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1753
1754                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1755                 if (!err)
1756                         break;
1757         } while (--retries);
1758
1759         err = tg3_phy_reset_chanpat(tp);
1760         if (err)
1761                 return err;
1762
1763         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1764         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1765
1766         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1767         tg3_writephy(tp, 0x16, 0x0000);
1768
1769         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1770             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1771                 /* Set Extended packet length bit for jumbo frames */
1772                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1773         }
1774         else {
1775                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1776         }
1777
1778         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1779
1780         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1781                 reg32 &= ~0x3000;
1782                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1783         } else if (!err)
1784                 err = -EBUSY;
1785
1786         return err;
1787 }
1788
1789 /* This will reset the tigon3 PHY if there is no valid
1790  * link unless the FORCE argument is non-zero.
1791  */
1792 static int tg3_phy_reset(struct tg3 *tp)
1793 {
1794         u32 cpmuctrl;
1795         u32 phy_status;
1796         int err;
1797
1798         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1799                 u32 val;
1800
1801                 val = tr32(GRC_MISC_CFG);
1802                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1803                 udelay(40);
1804         }
1805         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1806         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1807         if (err != 0)
1808                 return -EBUSY;
1809
1810         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1811                 netif_carrier_off(tp->dev);
1812                 tg3_link_report(tp);
1813         }
1814
1815         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1816             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1817             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1818                 err = tg3_phy_reset_5703_4_5(tp);
1819                 if (err)
1820                         return err;
1821                 goto out;
1822         }
1823
1824         cpmuctrl = 0;
1825         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1826             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1827                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1828                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1829                         tw32(TG3_CPMU_CTRL,
1830                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1831         }
1832
1833         err = tg3_bmcr_reset(tp);
1834         if (err)
1835                 return err;
1836
1837         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1838                 u32 phy;
1839
1840                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1841                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1842
1843                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1844         }
1845
1846         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1847             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1848                 u32 val;
1849
1850                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1851                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1852                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1853                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1854                         udelay(40);
1855                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1856                 }
1857         }
1858
1859         tg3_phy_apply_otp(tp);
1860
1861         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1862                 tg3_phy_toggle_apd(tp, true);
1863         else
1864                 tg3_phy_toggle_apd(tp, false);
1865
1866 out:
1867         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1868                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1869                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1870                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1871                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1872                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1873                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1874         }
1875         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1876                 tg3_writephy(tp, 0x1c, 0x8d68);
1877                 tg3_writephy(tp, 0x1c, 0x8d68);
1878         }
1879         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1880                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1881                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1882                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1883                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1884                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1885                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1886                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1887                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1888         }
1889         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1890                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1891                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1892                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1893                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1894                         tg3_writephy(tp, MII_TG3_TEST1,
1895                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1896                 } else
1897                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1898                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1899         }
1900         /* Set Extended packet length bit (bit 14) on all chips that */
1901         /* support jumbo frames */
1902         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1903                 /* Cannot do read-modify-write on 5401 */
1904                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1905         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1906                 u32 phy_reg;
1907
1908                 /* Set bit 14 with read-modify-write to preserve other bits */
1909                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1910                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1911                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1912         }
1913
1914         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1915          * jumbo frames transmission.
1916          */
1917         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1918                 u32 phy_reg;
1919
1920                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1921                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1922                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1923         }
1924
1925         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1926                 /* adjust output voltage */
1927                 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1928         }
1929
1930         tg3_phy_toggle_automdix(tp, 1);
1931         tg3_phy_set_wirespeed(tp);
1932         return 0;
1933 }
1934
1935 static void tg3_frob_aux_power(struct tg3 *tp)
1936 {
1937         struct tg3 *tp_peer = tp;
1938
1939         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1940                 return;
1941
1942         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1943             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1944                 struct net_device *dev_peer;
1945
1946                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1947                 /* remove_one() may have been run on the peer. */
1948                 if (!dev_peer)
1949                         tp_peer = tp;
1950                 else
1951                         tp_peer = netdev_priv(dev_peer);
1952         }
1953
1954         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1955             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1956             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1957             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1958                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1959                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1960                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1961                                     (GRC_LCLCTRL_GPIO_OE0 |
1962                                      GRC_LCLCTRL_GPIO_OE1 |
1963                                      GRC_LCLCTRL_GPIO_OE2 |
1964                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1965                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1966                                     100);
1967                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) {
1968                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1969                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1970                                              GRC_LCLCTRL_GPIO_OE1 |
1971                                              GRC_LCLCTRL_GPIO_OE2 |
1972                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
1973                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
1974                                              tp->grc_local_ctrl;
1975                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1976
1977                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
1978                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1979
1980                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
1981                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1982                 } else {
1983                         u32 no_gpio2;
1984                         u32 grc_local_ctrl = 0;
1985
1986                         if (tp_peer != tp &&
1987                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1988                                 return;
1989
1990                         /* Workaround to prevent overdrawing Amps. */
1991                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1992                             ASIC_REV_5714) {
1993                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1994                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1995                                             grc_local_ctrl, 100);
1996                         }
1997
1998                         /* On 5753 and variants, GPIO2 cannot be used. */
1999                         no_gpio2 = tp->nic_sram_data_cfg &
2000                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2001
2002                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2003                                          GRC_LCLCTRL_GPIO_OE1 |
2004                                          GRC_LCLCTRL_GPIO_OE2 |
2005                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2006                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2007                         if (no_gpio2) {
2008                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2009                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2010                         }
2011                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2012                                                     grc_local_ctrl, 100);
2013
2014                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2015
2016                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2017                                                     grc_local_ctrl, 100);
2018
2019                         if (!no_gpio2) {
2020                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2021                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2022                                             grc_local_ctrl, 100);
2023                         }
2024                 }
2025         } else {
2026                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2027                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2028                         if (tp_peer != tp &&
2029                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2030                                 return;
2031
2032                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2033                                     (GRC_LCLCTRL_GPIO_OE1 |
2034                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2035
2036                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2037                                     GRC_LCLCTRL_GPIO_OE1, 100);
2038
2039                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2040                                     (GRC_LCLCTRL_GPIO_OE1 |
2041                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2042                 }
2043         }
2044 }
2045
2046 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2047 {
2048         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2049                 return 1;
2050         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2051                 if (speed != SPEED_10)
2052                         return 1;
2053         } else if (speed == SPEED_10)
2054                 return 1;
2055
2056         return 0;
2057 }
2058
2059 static int tg3_setup_phy(struct tg3 *, int);
2060
2061 #define RESET_KIND_SHUTDOWN     0
2062 #define RESET_KIND_INIT         1
2063 #define RESET_KIND_SUSPEND      2
2064
2065 static void tg3_write_sig_post_reset(struct tg3 *, int);
2066 static int tg3_halt_cpu(struct tg3 *, u32);
2067 static int tg3_nvram_lock(struct tg3 *);
2068 static void tg3_nvram_unlock(struct tg3 *);
2069
2070 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2071 {
2072         u32 val;
2073
2074         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2075                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2076                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2077                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2078
2079                         sg_dig_ctrl |=
2080                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2081                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2082                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2083                 }
2084                 return;
2085         }
2086
2087         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2088                 tg3_bmcr_reset(tp);
2089                 val = tr32(GRC_MISC_CFG);
2090                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2091                 udelay(40);
2092                 return;
2093         } else if (do_low_power) {
2094                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2095                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2096
2097                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2098                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2099                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2100                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2101                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2102         }
2103
2104         /* The PHY should not be powered down on some chips because
2105          * of bugs.
2106          */
2107         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2108             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2109             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2110              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2111                 return;
2112
2113         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2114             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2115                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2116                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2117                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2118                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2119         }
2120
2121         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2122 }
2123
2124 /* tp->lock is held. */
2125 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2126 {
2127         u32 addr_high, addr_low;
2128         int i;
2129
2130         addr_high = ((tp->dev->dev_addr[0] << 8) |
2131                      tp->dev->dev_addr[1]);
2132         addr_low = ((tp->dev->dev_addr[2] << 24) |
2133                     (tp->dev->dev_addr[3] << 16) |
2134                     (tp->dev->dev_addr[4] <<  8) |
2135                     (tp->dev->dev_addr[5] <<  0));
2136         for (i = 0; i < 4; i++) {
2137                 if (i == 1 && skip_mac_1)
2138                         continue;
2139                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2140                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2141         }
2142
2143         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2144             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2145                 for (i = 0; i < 12; i++) {
2146                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2147                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2148                 }
2149         }
2150
2151         addr_high = (tp->dev->dev_addr[0] +
2152                      tp->dev->dev_addr[1] +
2153                      tp->dev->dev_addr[2] +
2154                      tp->dev->dev_addr[3] +
2155                      tp->dev->dev_addr[4] +
2156                      tp->dev->dev_addr[5]) &
2157                 TX_BACKOFF_SEED_MASK;
2158         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2159 }
2160
2161 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2162 {
2163         u32 misc_host_ctrl;
2164         bool device_should_wake, do_low_power;
2165
2166         /* Make sure register accesses (indirect or otherwise)
2167          * will function correctly.
2168          */
2169         pci_write_config_dword(tp->pdev,
2170                                TG3PCI_MISC_HOST_CTRL,
2171                                tp->misc_host_ctrl);
2172
2173         switch (state) {
2174         case PCI_D0:
2175                 pci_enable_wake(tp->pdev, state, false);
2176                 pci_set_power_state(tp->pdev, PCI_D0);
2177
2178                 /* Switch out of Vaux if it is a NIC */
2179                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2180                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2181
2182                 return 0;
2183
2184         case PCI_D1:
2185         case PCI_D2:
2186         case PCI_D3hot:
2187                 break;
2188
2189         default:
2190                 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2191                         tp->dev->name, state);
2192                 return -EINVAL;
2193         }
2194
2195         /* Restore the CLKREQ setting. */
2196         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2197                 u16 lnkctl;
2198
2199                 pci_read_config_word(tp->pdev,
2200                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2201                                      &lnkctl);
2202                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2203                 pci_write_config_word(tp->pdev,
2204                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2205                                       lnkctl);
2206         }
2207
2208         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2209         tw32(TG3PCI_MISC_HOST_CTRL,
2210              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2211
2212         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2213                              device_may_wakeup(&tp->pdev->dev) &&
2214                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2215
2216         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2217                 do_low_power = false;
2218                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2219                     !tp->link_config.phy_is_low_power) {
2220                         struct phy_device *phydev;
2221                         u32 phyid, advertising;
2222
2223                         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
2224
2225                         tp->link_config.phy_is_low_power = 1;
2226
2227                         tp->link_config.orig_speed = phydev->speed;
2228                         tp->link_config.orig_duplex = phydev->duplex;
2229                         tp->link_config.orig_autoneg = phydev->autoneg;
2230                         tp->link_config.orig_advertising = phydev->advertising;
2231
2232                         advertising = ADVERTISED_TP |
2233                                       ADVERTISED_Pause |
2234                                       ADVERTISED_Autoneg |
2235                                       ADVERTISED_10baseT_Half;
2236
2237                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2238                             device_should_wake) {
2239                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2240                                         advertising |=
2241                                                 ADVERTISED_100baseT_Half |
2242                                                 ADVERTISED_100baseT_Full |
2243                                                 ADVERTISED_10baseT_Full;
2244                                 else
2245                                         advertising |= ADVERTISED_10baseT_Full;
2246                         }
2247
2248                         phydev->advertising = advertising;
2249
2250                         phy_start_aneg(phydev);
2251
2252                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2253                         if (phyid != TG3_PHY_ID_BCMAC131) {
2254                                 phyid &= TG3_PHY_OUI_MASK;
2255                                 if (phyid == TG3_PHY_OUI_1 &&
2256                                     phyid == TG3_PHY_OUI_2 &&
2257                                     phyid == TG3_PHY_OUI_3)
2258                                         do_low_power = true;
2259                         }
2260                 }
2261         } else {
2262                 do_low_power = false;
2263
2264                 if (tp->link_config.phy_is_low_power == 0) {
2265                         tp->link_config.phy_is_low_power = 1;
2266                         tp->link_config.orig_speed = tp->link_config.speed;
2267                         tp->link_config.orig_duplex = tp->link_config.duplex;
2268                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2269                 }
2270
2271                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2272                         tp->link_config.speed = SPEED_10;
2273                         tp->link_config.duplex = DUPLEX_HALF;
2274                         tp->link_config.autoneg = AUTONEG_ENABLE;
2275                         tg3_setup_phy(tp, 0);
2276                 }
2277         }
2278
2279         __tg3_set_mac_addr(tp, 0);
2280
2281         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2282                 u32 val;
2283
2284                 val = tr32(GRC_VCPU_EXT_CTRL);
2285                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2286         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2287                 int i;
2288                 u32 val;
2289
2290                 for (i = 0; i < 200; i++) {
2291                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2292                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2293                                 break;
2294                         msleep(1);
2295                 }
2296         }
2297         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2298                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2299                                                      WOL_DRV_STATE_SHUTDOWN |
2300                                                      WOL_DRV_WOL |
2301                                                      WOL_SET_MAGIC_PKT);
2302
2303         if (device_should_wake) {
2304                 u32 mac_mode;
2305
2306                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2307                         if (do_low_power) {
2308                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2309                                 udelay(40);
2310                         }
2311
2312                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2313                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2314                         else
2315                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2316
2317                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2318                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2319                             ASIC_REV_5700) {
2320                                 u32 speed = (tp->tg3_flags &
2321                                              TG3_FLAG_WOL_SPEED_100MB) ?
2322                                              SPEED_100 : SPEED_10;
2323                                 if (tg3_5700_link_polarity(tp, speed))
2324                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2325                                 else
2326                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2327                         }
2328                 } else {
2329                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2330                 }
2331
2332                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2333                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2334
2335                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2336                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2337                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2338                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2339                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2340                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2341
2342                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2343                         mac_mode |= tp->mac_mode &
2344                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2345                         if (mac_mode & MAC_MODE_APE_TX_EN)
2346                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2347                 }
2348
2349                 tw32_f(MAC_MODE, mac_mode);
2350                 udelay(100);
2351
2352                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2353                 udelay(10);
2354         }
2355
2356         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2357             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2358              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2359                 u32 base_val;
2360
2361                 base_val = tp->pci_clock_ctrl;
2362                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2363                              CLOCK_CTRL_TXCLK_DISABLE);
2364
2365                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2366                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2367         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2368                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2369                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2370                 /* do nothing */
2371         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2372                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2373                 u32 newbits1, newbits2;
2374
2375                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2376                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2377                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2378                                     CLOCK_CTRL_TXCLK_DISABLE |
2379                                     CLOCK_CTRL_ALTCLK);
2380                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2381                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2382                         newbits1 = CLOCK_CTRL_625_CORE;
2383                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2384                 } else {
2385                         newbits1 = CLOCK_CTRL_ALTCLK;
2386                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2387                 }
2388
2389                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2390                             40);
2391
2392                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2393                             40);
2394
2395                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2396                         u32 newbits3;
2397
2398                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2399                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2400                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2401                                             CLOCK_CTRL_TXCLK_DISABLE |
2402                                             CLOCK_CTRL_44MHZ_CORE);
2403                         } else {
2404                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2405                         }
2406
2407                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2408                                     tp->pci_clock_ctrl | newbits3, 40);
2409                 }
2410         }
2411
2412         if (!(device_should_wake) &&
2413             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2414                 tg3_power_down_phy(tp, do_low_power);
2415
2416         tg3_frob_aux_power(tp);
2417
2418         /* Workaround for unstable PLL clock */
2419         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2420             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2421                 u32 val = tr32(0x7d00);
2422
2423                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2424                 tw32(0x7d00, val);
2425                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2426                         int err;
2427
2428                         err = tg3_nvram_lock(tp);
2429                         tg3_halt_cpu(tp, RX_CPU_BASE);
2430                         if (!err)
2431                                 tg3_nvram_unlock(tp);
2432                 }
2433         }
2434
2435         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2436
2437         if (device_should_wake)
2438                 pci_enable_wake(tp->pdev, state, true);
2439
2440         /* Finally, set the new power state. */
2441         pci_set_power_state(tp->pdev, state);
2442
2443         return 0;
2444 }
2445
2446 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2447 {
2448         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2449         case MII_TG3_AUX_STAT_10HALF:
2450                 *speed = SPEED_10;
2451                 *duplex = DUPLEX_HALF;
2452                 break;
2453
2454         case MII_TG3_AUX_STAT_10FULL:
2455                 *speed = SPEED_10;
2456                 *duplex = DUPLEX_FULL;
2457                 break;
2458
2459         case MII_TG3_AUX_STAT_100HALF:
2460                 *speed = SPEED_100;
2461                 *duplex = DUPLEX_HALF;
2462                 break;
2463
2464         case MII_TG3_AUX_STAT_100FULL:
2465                 *speed = SPEED_100;
2466                 *duplex = DUPLEX_FULL;
2467                 break;
2468
2469         case MII_TG3_AUX_STAT_1000HALF:
2470                 *speed = SPEED_1000;
2471                 *duplex = DUPLEX_HALF;
2472                 break;
2473
2474         case MII_TG3_AUX_STAT_1000FULL:
2475                 *speed = SPEED_1000;
2476                 *duplex = DUPLEX_FULL;
2477                 break;
2478
2479         default:
2480                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2481                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2482                                  SPEED_10;
2483                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2484                                   DUPLEX_HALF;
2485                         break;
2486                 }
2487                 *speed = SPEED_INVALID;
2488                 *duplex = DUPLEX_INVALID;
2489                 break;
2490         }
2491 }
2492
2493 static void tg3_phy_copper_begin(struct tg3 *tp)
2494 {
2495         u32 new_adv;
2496         int i;
2497
2498         if (tp->link_config.phy_is_low_power) {
2499                 /* Entering low power mode.  Disable gigabit and
2500                  * 100baseT advertisements.
2501                  */
2502                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2503
2504                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2505                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2506                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2507                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2508
2509                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2510         } else if (tp->link_config.speed == SPEED_INVALID) {
2511                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2512                         tp->link_config.advertising &=
2513                                 ~(ADVERTISED_1000baseT_Half |
2514                                   ADVERTISED_1000baseT_Full);
2515
2516                 new_adv = ADVERTISE_CSMA;
2517                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2518                         new_adv |= ADVERTISE_10HALF;
2519                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2520                         new_adv |= ADVERTISE_10FULL;
2521                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2522                         new_adv |= ADVERTISE_100HALF;
2523                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2524                         new_adv |= ADVERTISE_100FULL;
2525
2526                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2527
2528                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2529
2530                 if (tp->link_config.advertising &
2531                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2532                         new_adv = 0;
2533                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2534                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2535                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2536                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2537                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2538                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2539                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2540                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2541                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2542                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2543                 } else {
2544                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2545                 }
2546         } else {
2547                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2548                 new_adv |= ADVERTISE_CSMA;
2549
2550                 /* Asking for a specific link mode. */
2551                 if (tp->link_config.speed == SPEED_1000) {
2552                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2553
2554                         if (tp->link_config.duplex == DUPLEX_FULL)
2555                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2556                         else
2557                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2558                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2559                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2560                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2561                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2562                 } else {
2563                         if (tp->link_config.speed == SPEED_100) {
2564                                 if (tp->link_config.duplex == DUPLEX_FULL)
2565                                         new_adv |= ADVERTISE_100FULL;
2566                                 else
2567                                         new_adv |= ADVERTISE_100HALF;
2568                         } else {
2569                                 if (tp->link_config.duplex == DUPLEX_FULL)
2570                                         new_adv |= ADVERTISE_10FULL;
2571                                 else
2572                                         new_adv |= ADVERTISE_10HALF;
2573                         }
2574                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2575
2576                         new_adv = 0;
2577                 }
2578
2579                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2580         }
2581
2582         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2583             tp->link_config.speed != SPEED_INVALID) {
2584                 u32 bmcr, orig_bmcr;
2585
2586                 tp->link_config.active_speed = tp->link_config.speed;
2587                 tp->link_config.active_duplex = tp->link_config.duplex;
2588
2589                 bmcr = 0;
2590                 switch (tp->link_config.speed) {
2591                 default:
2592                 case SPEED_10:
2593                         break;
2594
2595                 case SPEED_100:
2596                         bmcr |= BMCR_SPEED100;
2597                         break;
2598
2599                 case SPEED_1000:
2600                         bmcr |= TG3_BMCR_SPEED1000;
2601                         break;
2602                 }
2603
2604                 if (tp->link_config.duplex == DUPLEX_FULL)
2605                         bmcr |= BMCR_FULLDPLX;
2606
2607                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2608                     (bmcr != orig_bmcr)) {
2609                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2610                         for (i = 0; i < 1500; i++) {
2611                                 u32 tmp;
2612
2613                                 udelay(10);
2614                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2615                                     tg3_readphy(tp, MII_BMSR, &tmp))
2616                                         continue;
2617                                 if (!(tmp & BMSR_LSTATUS)) {
2618                                         udelay(40);
2619                                         break;
2620                                 }
2621                         }
2622                         tg3_writephy(tp, MII_BMCR, bmcr);
2623                         udelay(40);
2624                 }
2625         } else {
2626                 tg3_writephy(tp, MII_BMCR,
2627                              BMCR_ANENABLE | BMCR_ANRESTART);
2628         }
2629 }
2630
2631 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2632 {
2633         int err;
2634
2635         /* Turn off tap power management. */
2636         /* Set Extended packet length bit */
2637         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2638
2639         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2640         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2641
2642         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2643         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2644
2645         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2646         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2647
2648         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2649         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2650
2651         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2652         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2653
2654         udelay(40);
2655
2656         return err;
2657 }
2658
2659 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2660 {
2661         u32 adv_reg, all_mask = 0;
2662
2663         if (mask & ADVERTISED_10baseT_Half)
2664                 all_mask |= ADVERTISE_10HALF;
2665         if (mask & ADVERTISED_10baseT_Full)
2666                 all_mask |= ADVERTISE_10FULL;
2667         if (mask & ADVERTISED_100baseT_Half)
2668                 all_mask |= ADVERTISE_100HALF;
2669         if (mask & ADVERTISED_100baseT_Full)
2670                 all_mask |= ADVERTISE_100FULL;
2671
2672         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2673                 return 0;
2674
2675         if ((adv_reg & all_mask) != all_mask)
2676                 return 0;
2677         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2678                 u32 tg3_ctrl;
2679
2680                 all_mask = 0;
2681                 if (mask & ADVERTISED_1000baseT_Half)
2682                         all_mask |= ADVERTISE_1000HALF;
2683                 if (mask & ADVERTISED_1000baseT_Full)
2684                         all_mask |= ADVERTISE_1000FULL;
2685
2686                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2687                         return 0;
2688
2689                 if ((tg3_ctrl & all_mask) != all_mask)
2690                         return 0;
2691         }
2692         return 1;
2693 }
2694
2695 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2696 {
2697         u32 curadv, reqadv;
2698
2699         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2700                 return 1;
2701
2702         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2703         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2704
2705         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2706                 if (curadv != reqadv)
2707                         return 0;
2708
2709                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2710                         tg3_readphy(tp, MII_LPA, rmtadv);
2711         } else {
2712                 /* Reprogram the advertisement register, even if it
2713                  * does not affect the current link.  If the link
2714                  * gets renegotiated in the future, we can save an
2715                  * additional renegotiation cycle by advertising
2716                  * it correctly in the first place.
2717                  */
2718                 if (curadv != reqadv) {
2719                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2720                                      ADVERTISE_PAUSE_ASYM);
2721                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2722                 }
2723         }
2724
2725         return 1;
2726 }
2727
2728 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2729 {
2730         int current_link_up;
2731         u32 bmsr, dummy;
2732         u32 lcl_adv, rmt_adv;
2733         u16 current_speed;
2734         u8 current_duplex;
2735         int i, err;
2736
2737         tw32(MAC_EVENT, 0);
2738
2739         tw32_f(MAC_STATUS,
2740              (MAC_STATUS_SYNC_CHANGED |
2741               MAC_STATUS_CFG_CHANGED |
2742               MAC_STATUS_MI_COMPLETION |
2743               MAC_STATUS_LNKSTATE_CHANGED));
2744         udelay(40);
2745
2746         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2747                 tw32_f(MAC_MI_MODE,
2748                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2749                 udelay(80);
2750         }
2751
2752         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2753
2754         /* Some third-party PHYs need to be reset on link going
2755          * down.
2756          */
2757         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2758              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2759              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2760             netif_carrier_ok(tp->dev)) {
2761                 tg3_readphy(tp, MII_BMSR, &bmsr);
2762                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2763                     !(bmsr & BMSR_LSTATUS))
2764                         force_reset = 1;
2765         }
2766         if (force_reset)
2767                 tg3_phy_reset(tp);
2768
2769         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2770                 tg3_readphy(tp, MII_BMSR, &bmsr);
2771                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2772                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2773                         bmsr = 0;
2774
2775                 if (!(bmsr & BMSR_LSTATUS)) {
2776                         err = tg3_init_5401phy_dsp(tp);
2777                         if (err)
2778                                 return err;
2779
2780                         tg3_readphy(tp, MII_BMSR, &bmsr);
2781                         for (i = 0; i < 1000; i++) {
2782                                 udelay(10);
2783                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2784                                     (bmsr & BMSR_LSTATUS)) {
2785                                         udelay(40);
2786                                         break;
2787                                 }
2788                         }
2789
2790                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
2791                             !(bmsr & BMSR_LSTATUS) &&
2792                             tp->link_config.active_speed == SPEED_1000) {
2793                                 err = tg3_phy_reset(tp);
2794                                 if (!err)
2795                                         err = tg3_init_5401phy_dsp(tp);
2796                                 if (err)
2797                                         return err;
2798                         }
2799                 }
2800         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2801                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2802                 /* 5701 {A0,B0} CRC bug workaround */
2803                 tg3_writephy(tp, 0x15, 0x0a75);
2804                 tg3_writephy(tp, 0x1c, 0x8c68);
2805                 tg3_writephy(tp, 0x1c, 0x8d68);
2806                 tg3_writephy(tp, 0x1c, 0x8c68);
2807         }
2808
2809         /* Clear pending interrupts... */
2810         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2811         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2812
2813         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
2814                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
2815         else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
2816                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
2817
2818         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2819             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2820                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
2821                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2822                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
2823                 else
2824                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
2825         }
2826
2827         current_link_up = 0;
2828         current_speed = SPEED_INVALID;
2829         current_duplex = DUPLEX_INVALID;
2830
2831         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
2832                 u32 val;
2833
2834                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
2835                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
2836                 if (!(val & (1 << 10))) {
2837                         val |= (1 << 10);
2838                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2839                         goto relink;
2840                 }
2841         }
2842
2843         bmsr = 0;
2844         for (i = 0; i < 100; i++) {
2845                 tg3_readphy(tp, MII_BMSR, &bmsr);
2846                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2847                     (bmsr & BMSR_LSTATUS))
2848                         break;
2849                 udelay(40);
2850         }
2851
2852         if (bmsr & BMSR_LSTATUS) {
2853                 u32 aux_stat, bmcr;
2854
2855                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
2856                 for (i = 0; i < 2000; i++) {
2857                         udelay(10);
2858                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
2859                             aux_stat)
2860                                 break;
2861                 }
2862
2863                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
2864                                              &current_speed,
2865                                              &current_duplex);
2866
2867                 bmcr = 0;
2868                 for (i = 0; i < 200; i++) {
2869                         tg3_readphy(tp, MII_BMCR, &bmcr);
2870                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
2871                                 continue;
2872                         if (bmcr && bmcr != 0x7fff)
2873                                 break;
2874                         udelay(10);
2875                 }
2876
2877                 lcl_adv = 0;
2878                 rmt_adv = 0;
2879
2880                 tp->link_config.active_speed = current_speed;
2881                 tp->link_config.active_duplex = current_duplex;
2882
2883                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2884                         if ((bmcr & BMCR_ANENABLE) &&
2885                             tg3_copper_is_advertising_all(tp,
2886                                                 tp->link_config.advertising)) {
2887                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
2888                                                                   &rmt_adv))
2889                                         current_link_up = 1;
2890                         }
2891                 } else {
2892                         if (!(bmcr & BMCR_ANENABLE) &&
2893                             tp->link_config.speed == current_speed &&
2894                             tp->link_config.duplex == current_duplex &&
2895                             tp->link_config.flowctrl ==
2896                             tp->link_config.active_flowctrl) {
2897                                 current_link_up = 1;
2898                         }
2899                 }
2900
2901                 if (current_link_up == 1 &&
2902                     tp->link_config.active_duplex == DUPLEX_FULL)
2903                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2904         }
2905
2906 relink:
2907         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
2908                 u32 tmp;
2909
2910                 tg3_phy_copper_begin(tp);
2911
2912                 tg3_readphy(tp, MII_BMSR, &tmp);
2913                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
2914                     (tmp & BMSR_LSTATUS))
2915                         current_link_up = 1;
2916         }
2917
2918         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
2919         if (current_link_up == 1) {
2920                 if (tp->link_config.active_speed == SPEED_100 ||
2921                     tp->link_config.active_speed == SPEED_10)
2922                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
2923                 else
2924                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2925         } else
2926                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2927
2928         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2929         if (tp->link_config.active_duplex == DUPLEX_HALF)
2930                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2931
2932         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
2933                 if (current_link_up == 1 &&
2934                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
2935                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2936                 else
2937                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2938         }
2939
2940         /* ??? Without this setting Netgear GA302T PHY does not
2941          * ??? send/receive packets...
2942          */
2943         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2944             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2945                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2946                 tw32_f(MAC_MI_MODE, tp->mi_mode);
2947                 udelay(80);
2948         }
2949
2950         tw32_f(MAC_MODE, tp->mac_mode);
2951         udelay(40);
2952
2953         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2954                 /* Polled via timer. */
2955                 tw32_f(MAC_EVENT, 0);
2956         } else {
2957                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2958         }
2959         udelay(40);
2960
2961         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2962             current_link_up == 1 &&
2963             tp->link_config.active_speed == SPEED_1000 &&
2964             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2965              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2966                 udelay(120);
2967                 tw32_f(MAC_STATUS,
2968                      (MAC_STATUS_SYNC_CHANGED |
2969                       MAC_STATUS_CFG_CHANGED));
2970                 udelay(40);
2971                 tg3_write_mem(tp,
2972                               NIC_SRAM_FIRMWARE_MBOX,
2973                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2974         }
2975
2976         /* Prevent send BD corruption. */
2977         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2978                 u16 oldlnkctl, newlnkctl;
2979
2980                 pci_read_config_word(tp->pdev,
2981                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2982                                      &oldlnkctl);
2983                 if (tp->link_config.active_speed == SPEED_100 ||
2984                     tp->link_config.active_speed == SPEED_10)
2985                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
2986                 else
2987                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
2988                 if (newlnkctl != oldlnkctl)
2989                         pci_write_config_word(tp->pdev,
2990                                               tp->pcie_cap + PCI_EXP_LNKCTL,
2991                                               newlnkctl);
2992         }
2993
2994         if (current_link_up != netif_carrier_ok(tp->dev)) {
2995                 if (current_link_up)
2996                         netif_carrier_on(tp->dev);
2997                 else
2998                         netif_carrier_off(tp->dev);
2999                 tg3_link_report(tp);
3000         }
3001
3002         return 0;
3003 }
3004
3005 struct tg3_fiber_aneginfo {
3006         int state;
3007 #define ANEG_STATE_UNKNOWN              0
3008 #define ANEG_STATE_AN_ENABLE            1
3009 #define ANEG_STATE_RESTART_INIT         2
3010 #define ANEG_STATE_RESTART              3
3011 #define ANEG_STATE_DISABLE_LINK_OK      4
3012 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3013 #define ANEG_STATE_ABILITY_DETECT       6
3014 #define ANEG_STATE_ACK_DETECT_INIT      7
3015 #define ANEG_STATE_ACK_DETECT           8
3016 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3017 #define ANEG_STATE_COMPLETE_ACK         10
3018 #define ANEG_STATE_IDLE_DETECT_INIT     11
3019 #define ANEG_STATE_IDLE_DETECT          12
3020 #define ANEG_STATE_LINK_OK              13
3021 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3022 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3023
3024         u32 flags;
3025 #define MR_AN_ENABLE            0x00000001
3026 #define MR_RESTART_AN           0x00000002
3027 #define MR_AN_COMPLETE          0x00000004
3028 #define MR_PAGE_RX              0x00000008
3029 #define MR_NP_LOADED            0x00000010
3030 #define MR_TOGGLE_TX            0x00000020
3031 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3032 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3033 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3034 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3035 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3036 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3037 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3038 #define MR_TOGGLE_RX            0x00002000
3039 #define MR_NP_RX                0x00004000
3040
3041 #define MR_LINK_OK              0x80000000
3042
3043         unsigned long link_time, cur_time;
3044
3045         u32 ability_match_cfg;
3046         int ability_match_count;
3047
3048         char ability_match, idle_match, ack_match;
3049
3050         u32 txconfig, rxconfig;
3051 #define ANEG_CFG_NP             0x00000080
3052 #define ANEG_CFG_ACK            0x00000040
3053 #define ANEG_CFG_RF2            0x00000020
3054 #define ANEG_CFG_RF1            0x00000010
3055 #define ANEG_CFG_PS2            0x00000001
3056 #define ANEG_CFG_PS1            0x00008000
3057 #define ANEG_CFG_HD             0x00004000
3058 #define ANEG_CFG_FD             0x00002000
3059 #define ANEG_CFG_INVAL          0x00001f06
3060
3061 };
3062 #define ANEG_OK         0
3063 #define ANEG_DONE       1
3064 #define ANEG_TIMER_ENAB 2
3065 #define ANEG_FAILED     -1
3066
3067 #define ANEG_STATE_SETTLE_TIME  10000
3068
3069 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3070                                    struct tg3_fiber_aneginfo *ap)
3071 {
3072         u16 flowctrl;
3073         unsigned long delta;
3074         u32 rx_cfg_reg;
3075         int ret;
3076
3077         if (ap->state == ANEG_STATE_UNKNOWN) {
3078                 ap->rxconfig = 0;
3079                 ap->link_time = 0;
3080                 ap->cur_time = 0;
3081                 ap->ability_match_cfg = 0;
3082                 ap->ability_match_count = 0;
3083                 ap->ability_match = 0;
3084                 ap->idle_match = 0;
3085                 ap->ack_match = 0;
3086         }
3087         ap->cur_time++;
3088
3089         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3090                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3091
3092                 if (rx_cfg_reg != ap->ability_match_cfg) {
3093                         ap->ability_match_cfg = rx_cfg_reg;
3094                         ap->ability_match = 0;
3095                         ap->ability_match_count = 0;
3096                 } else {
3097                         if (++ap->ability_match_count > 1) {
3098                                 ap->ability_match = 1;
3099                                 ap->ability_match_cfg = rx_cfg_reg;
3100                         }
3101                 }
3102                 if (rx_cfg_reg & ANEG_CFG_ACK)
3103                         ap->ack_match = 1;
3104                 else
3105                         ap->ack_match = 0;
3106
3107                 ap->idle_match = 0;
3108         } else {
3109                 ap->idle_match = 1;
3110                 ap->ability_match_cfg = 0;
3111                 ap->ability_match_count = 0;
3112                 ap->ability_match = 0;
3113                 ap->ack_match = 0;
3114
3115                 rx_cfg_reg = 0;
3116         }
3117
3118         ap->rxconfig = rx_cfg_reg;
3119         ret = ANEG_OK;
3120
3121         switch(ap->state) {
3122         case ANEG_STATE_UNKNOWN:
3123                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3124                         ap->state = ANEG_STATE_AN_ENABLE;
3125
3126                 /* fallthru */
3127         case ANEG_STATE_AN_ENABLE:
3128                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3129                 if (ap->flags & MR_AN_ENABLE) {
3130                         ap->link_time = 0;
3131                         ap->cur_time = 0;
3132                         ap->ability_match_cfg = 0;
3133                         ap->ability_match_count = 0;
3134                         ap->ability_match = 0;
3135                         ap->idle_match = 0;
3136                         ap->ack_match = 0;
3137
3138                         ap->state = ANEG_STATE_RESTART_INIT;
3139                 } else {
3140                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3141                 }
3142                 break;
3143
3144         case ANEG_STATE_RESTART_INIT:
3145                 ap->link_time = ap->cur_time;
3146                 ap->flags &= ~(MR_NP_LOADED);
3147                 ap->txconfig = 0;
3148                 tw32(MAC_TX_AUTO_NEG, 0);
3149                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3150                 tw32_f(MAC_MODE, tp->mac_mode);
3151                 udelay(40);
3152
3153                 ret = ANEG_TIMER_ENAB;
3154                 ap->state = ANEG_STATE_RESTART;
3155
3156                 /* fallthru */
3157         case ANEG_STATE_RESTART:
3158                 delta = ap->cur_time - ap->link_time;
3159                 if (delta > ANEG_STATE_SETTLE_TIME) {
3160                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3161                 } else {
3162                         ret = ANEG_TIMER_ENAB;
3163                 }
3164                 break;
3165
3166         case ANEG_STATE_DISABLE_LINK_OK:
3167                 ret = ANEG_DONE;
3168                 break;
3169
3170         case ANEG_STATE_ABILITY_DETECT_INIT:
3171                 ap->flags &= ~(MR_TOGGLE_TX);
3172                 ap->txconfig = ANEG_CFG_FD;
3173                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3174                 if (flowctrl & ADVERTISE_1000XPAUSE)
3175                         ap->txconfig |= ANEG_CFG_PS1;
3176                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3177                         ap->txconfig |= ANEG_CFG_PS2;
3178                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3179                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3180                 tw32_f(MAC_MODE, tp->mac_mode);
3181                 udelay(40);
3182
3183                 ap->state = ANEG_STATE_ABILITY_DETECT;
3184                 break;
3185
3186         case ANEG_STATE_ABILITY_DETECT:
3187                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3188                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3189                 }
3190                 break;
3191
3192         case ANEG_STATE_ACK_DETECT_INIT:
3193                 ap->txconfig |= ANEG_CFG_ACK;
3194                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3195                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3196                 tw32_f(MAC_MODE, tp->mac_mode);
3197                 udelay(40);
3198
3199                 ap->state = ANEG_STATE_ACK_DETECT;
3200
3201                 /* fallthru */
3202         case ANEG_STATE_ACK_DETECT:
3203                 if (ap->ack_match != 0) {
3204                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3205                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3206                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3207                         } else {
3208                                 ap->state = ANEG_STATE_AN_ENABLE;
3209                         }
3210                 } else if (ap->ability_match != 0 &&
3211                            ap->rxconfig == 0) {
3212                         ap->state = ANEG_STATE_AN_ENABLE;
3213                 }
3214                 break;
3215
3216         case ANEG_STATE_COMPLETE_ACK_INIT:
3217                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3218                         ret = ANEG_FAILED;
3219                         break;
3220                 }
3221                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3222                                MR_LP_ADV_HALF_DUPLEX |
3223                                MR_LP_ADV_SYM_PAUSE |
3224                                MR_LP_ADV_ASYM_PAUSE |
3225                                MR_LP_ADV_REMOTE_FAULT1 |
3226                                MR_LP_ADV_REMOTE_FAULT2 |
3227                                MR_LP_ADV_NEXT_PAGE |
3228                                MR_TOGGLE_RX |
3229                                MR_NP_RX);
3230                 if (ap->rxconfig & ANEG_CFG_FD)
3231                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3232                 if (ap->rxconfig & ANEG_CFG_HD)
3233                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3234                 if (ap->rxconfig & ANEG_CFG_PS1)
3235                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3236                 if (ap->rxconfig & ANEG_CFG_PS2)
3237                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3238                 if (ap->rxconfig & ANEG_CFG_RF1)
3239                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3240                 if (ap->rxconfig & ANEG_CFG_RF2)
3241                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3242                 if (ap->rxconfig & ANEG_CFG_NP)
3243                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3244
3245                 ap->link_time = ap->cur_time;
3246
3247                 ap->flags ^= (MR_TOGGLE_TX);
3248                 if (ap->rxconfig & 0x0008)
3249                         ap->flags |= MR_TOGGLE_RX;
3250                 if (ap->rxconfig & ANEG_CFG_NP)
3251                         ap->flags |= MR_NP_RX;
3252                 ap->flags |= MR_PAGE_RX;
3253
3254                 ap->state = ANEG_STATE_COMPLETE_ACK;
3255                 ret = ANEG_TIMER_ENAB;
3256                 break;
3257
3258         case ANEG_STATE_COMPLETE_ACK:
3259                 if (ap->ability_match != 0 &&
3260                     ap->rxconfig == 0) {
3261                         ap->state = ANEG_STATE_AN_ENABLE;
3262                         break;
3263                 }
3264                 delta = ap->cur_time - ap->link_time;
3265                 if (delta > ANEG_STATE_SETTLE_TIME) {
3266                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3267                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3268                         } else {
3269                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3270                                     !(ap->flags & MR_NP_RX)) {
3271                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3272                                 } else {
3273                                         ret = ANEG_FAILED;
3274                                 }
3275                         }
3276                 }
3277                 break;
3278
3279         case ANEG_STATE_IDLE_DETECT_INIT:
3280                 ap->link_time = ap->cur_time;
3281                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3282                 tw32_f(MAC_MODE, tp->mac_mode);
3283                 udelay(40);
3284
3285                 ap->state = ANEG_STATE_IDLE_DETECT;
3286                 ret = ANEG_TIMER_ENAB;
3287                 break;
3288
3289         case ANEG_STATE_IDLE_DETECT:
3290                 if (ap->ability_match != 0 &&
3291                     ap->rxconfig == 0) {
3292                         ap->state = ANEG_STATE_AN_ENABLE;
3293                         break;
3294                 }
3295                 delta = ap->cur_time - ap->link_time;
3296                 if (delta > ANEG_STATE_SETTLE_TIME) {
3297                         /* XXX another gem from the Broadcom driver :( */
3298                         ap->state = ANEG_STATE_LINK_OK;
3299                 }
3300                 break;
3301
3302         case ANEG_STATE_LINK_OK:
3303                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3304                 ret = ANEG_DONE;
3305                 break;
3306
3307         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3308                 /* ??? unimplemented */
3309                 break;
3310
3311         case ANEG_STATE_NEXT_PAGE_WAIT:
3312                 /* ??? unimplemented */
3313                 break;
3314
3315         default:
3316                 ret = ANEG_FAILED;
3317                 break;
3318         }
3319
3320         return ret;
3321 }
3322
3323 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3324 {
3325         int res = 0;
3326         struct tg3_fiber_aneginfo aninfo;
3327         int status = ANEG_FAILED;
3328         unsigned int tick;
3329         u32 tmp;
3330
3331         tw32_f(MAC_TX_AUTO_NEG, 0);
3332
3333         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3334         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3335         udelay(40);
3336
3337         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3338         udelay(40);
3339
3340         memset(&aninfo, 0, sizeof(aninfo));
3341         aninfo.flags |= MR_AN_ENABLE;
3342         aninfo.state = ANEG_STATE_UNKNOWN;
3343         aninfo.cur_time = 0;
3344         tick = 0;
3345         while (++tick < 195000) {
3346                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3347                 if (status == ANEG_DONE || status == ANEG_FAILED)
3348                         break;
3349
3350                 udelay(1);
3351         }
3352
3353         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3354         tw32_f(MAC_MODE, tp->mac_mode);
3355         udelay(40);
3356
3357         *txflags = aninfo.txconfig;
3358         *rxflags = aninfo.flags;
3359
3360         if (status == ANEG_DONE &&
3361             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3362                              MR_LP_ADV_FULL_DUPLEX)))
3363                 res = 1;
3364
3365         return res;
3366 }
3367
3368 static void tg3_init_bcm8002(struct tg3 *tp)
3369 {
3370         u32 mac_status = tr32(MAC_STATUS);
3371         int i;
3372
3373         /* Reset when initting first time or we have a link. */
3374         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3375             !(mac_status & MAC_STATUS_PCS_SYNCED))
3376                 return;
3377
3378         /* Set PLL lock range. */
3379         tg3_writephy(tp, 0x16, 0x8007);
3380
3381         /* SW reset */
3382         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3383
3384         /* Wait for reset to complete. */
3385         /* XXX schedule_timeout() ... */
3386         for (i = 0; i < 500; i++)
3387                 udelay(10);
3388
3389         /* Config mode; select PMA/Ch 1 regs. */
3390         tg3_writephy(tp, 0x10, 0x8411);
3391
3392         /* Enable auto-lock and comdet, select txclk for tx. */
3393         tg3_writephy(tp, 0x11, 0x0a10);
3394
3395         tg3_writephy(tp, 0x18, 0x00a0);
3396         tg3_writephy(tp, 0x16, 0x41ff);
3397
3398         /* Assert and deassert POR. */
3399         tg3_writephy(tp, 0x13, 0x0400);
3400         udelay(40);
3401         tg3_writephy(tp, 0x13, 0x0000);
3402
3403         tg3_writephy(tp, 0x11, 0x0a50);
3404         udelay(40);
3405         tg3_writephy(tp, 0x11, 0x0a10);
3406
3407         /* Wait for signal to stabilize */
3408         /* XXX schedule_timeout() ... */
3409         for (i = 0; i < 15000; i++)
3410                 udelay(10);
3411
3412         /* Deselect the channel register so we can read the PHYID
3413          * later.
3414          */
3415         tg3_writephy(tp, 0x10, 0x8011);
3416 }
3417
3418 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3419 {
3420         u16 flowctrl;
3421         u32 sg_dig_ctrl, sg_dig_status;
3422         u32 serdes_cfg, expected_sg_dig_ctrl;
3423         int workaround, port_a;
3424         int current_link_up;
3425
3426         serdes_cfg = 0;
3427         expected_sg_dig_ctrl = 0;
3428         workaround = 0;
3429         port_a = 1;
3430         current_link_up = 0;
3431
3432         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3433             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3434                 workaround = 1;
3435                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3436                         port_a = 0;
3437
3438                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3439                 /* preserve bits 20-23 for voltage regulator */
3440                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3441         }
3442
3443         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3444
3445         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3446                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3447                         if (workaround) {
3448                                 u32 val = serdes_cfg;
3449
3450                                 if (port_a)
3451                                         val |= 0xc010000;
3452                                 else
3453                                         val |= 0x4010000;
3454                                 tw32_f(MAC_SERDES_CFG, val);
3455                         }
3456
3457                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3458                 }
3459                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3460                         tg3_setup_flow_control(tp, 0, 0);
3461                         current_link_up = 1;
3462                 }
3463                 goto out;
3464         }
3465
3466         /* Want auto-negotiation.  */
3467         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3468
3469         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3470         if (flowctrl & ADVERTISE_1000XPAUSE)
3471                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3472         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3473                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3474
3475         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3476                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3477                     tp->serdes_counter &&
3478                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3479                                     MAC_STATUS_RCVD_CFG)) ==
3480                      MAC_STATUS_PCS_SYNCED)) {
3481                         tp->serdes_counter--;
3482                         current_link_up = 1;
3483                         goto out;
3484                 }
3485 restart_autoneg:
3486                 if (workaround)
3487                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3488                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3489                 udelay(5);
3490                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3491
3492                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3493                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3494         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3495                                  MAC_STATUS_SIGNAL_DET)) {
3496                 sg_dig_status = tr32(SG_DIG_STATUS);
3497                 mac_status = tr32(MAC_STATUS);
3498
3499                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3500                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3501                         u32 local_adv = 0, remote_adv = 0;
3502
3503                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3504                                 local_adv |= ADVERTISE_1000XPAUSE;
3505                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3506                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3507
3508                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3509                                 remote_adv |= LPA_1000XPAUSE;
3510                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3511                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3512
3513                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3514                         current_link_up = 1;
3515                         tp->serdes_counter = 0;
3516                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3517                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3518                         if (tp->serdes_counter)
3519                                 tp->serdes_counter--;
3520                         else {
3521                                 if (workaround) {
3522                                         u32 val = serdes_cfg;
3523
3524                                         if (port_a)
3525                                                 val |= 0xc010000;
3526                                         else
3527                                                 val |= 0x4010000;
3528
3529                                         tw32_f(MAC_SERDES_CFG, val);
3530                                 }
3531
3532                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3533                                 udelay(40);
3534
3535                                 /* Link parallel detection - link is up */
3536                                 /* only if we have PCS_SYNC and not */
3537                                 /* receiving config code words */
3538                                 mac_status = tr32(MAC_STATUS);
3539                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3540                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3541                                         tg3_setup_flow_control(tp, 0, 0);
3542                                         current_link_up = 1;
3543                                         tp->tg3_flags2 |=
3544                                                 TG3_FLG2_PARALLEL_DETECT;
3545                                         tp->serdes_counter =
3546                                                 SERDES_PARALLEL_DET_TIMEOUT;
3547                                 } else
3548                                         goto restart_autoneg;
3549                         }
3550                 }
3551         } else {
3552                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3553                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3554         }
3555
3556 out:
3557         return current_link_up;
3558 }
3559
3560 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3561 {
3562         int current_link_up = 0;
3563
3564         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3565                 goto out;
3566
3567         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3568                 u32 txflags, rxflags;
3569                 int i;
3570
3571                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3572                         u32 local_adv = 0, remote_adv = 0;
3573
3574                         if (txflags & ANEG_CFG_PS1)
3575                                 local_adv |= ADVERTISE_1000XPAUSE;
3576                         if (txflags & ANEG_CFG_PS2)
3577                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3578
3579                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3580                                 remote_adv |= LPA_1000XPAUSE;
3581                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3582                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3583
3584                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3585
3586                         current_link_up = 1;
3587                 }
3588                 for (i = 0; i < 30; i++) {
3589                         udelay(20);
3590                         tw32_f(MAC_STATUS,
3591                                (MAC_STATUS_SYNC_CHANGED |
3592                                 MAC_STATUS_CFG_CHANGED));
3593                         udelay(40);
3594                         if ((tr32(MAC_STATUS) &
3595                              (MAC_STATUS_SYNC_CHANGED |
3596                               MAC_STATUS_CFG_CHANGED)) == 0)
3597                                 break;
3598                 }
3599
3600                 mac_status = tr32(MAC_STATUS);
3601                 if (current_link_up == 0 &&
3602                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3603                     !(mac_status & MAC_STATUS_RCVD_CFG))
3604                         current_link_up = 1;
3605         } else {
3606                 tg3_setup_flow_control(tp, 0, 0);
3607
3608                 /* Forcing 1000FD link up. */
3609                 current_link_up = 1;
3610
3611                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3612                 udelay(40);
3613
3614                 tw32_f(MAC_MODE, tp->mac_mode);
3615                 udelay(40);
3616         }
3617
3618 out:
3619         return current_link_up;
3620 }
3621
3622 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3623 {
3624         u32 orig_pause_cfg;
3625         u16 orig_active_speed;
3626         u8 orig_active_duplex;
3627         u32 mac_status;
3628         int current_link_up;
3629         int i;
3630
3631         orig_pause_cfg = tp->link_config.active_flowctrl;
3632         orig_active_speed = tp->link_config.active_speed;
3633         orig_active_duplex = tp->link_config.active_duplex;
3634
3635         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3636             netif_carrier_ok(tp->dev) &&
3637             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3638                 mac_status = tr32(MAC_STATUS);
3639                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3640                                MAC_STATUS_SIGNAL_DET |
3641                                MAC_STATUS_CFG_CHANGED |
3642                                MAC_STATUS_RCVD_CFG);
3643                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3644                                    MAC_STATUS_SIGNAL_DET)) {
3645                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3646                                             MAC_STATUS_CFG_CHANGED));
3647                         return 0;
3648                 }
3649         }
3650
3651         tw32_f(MAC_TX_AUTO_NEG, 0);
3652
3653         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3654         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3655         tw32_f(MAC_MODE, tp->mac_mode);
3656         udelay(40);
3657
3658         if (tp->phy_id == PHY_ID_BCM8002)
3659                 tg3_init_bcm8002(tp);
3660
3661         /* Enable link change event even when serdes polling.  */
3662         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3663         udelay(40);
3664
3665         current_link_up = 0;
3666         mac_status = tr32(MAC_STATUS);
3667
3668         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3669                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3670         else
3671                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3672
3673         tp->hw_status->status =
3674                 (SD_STATUS_UPDATED |
3675                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3676
3677         for (i = 0; i < 100; i++) {
3678                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3679                                     MAC_STATUS_CFG_CHANGED));
3680                 udelay(5);
3681                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3682                                          MAC_STATUS_CFG_CHANGED |
3683                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3684                         break;
3685         }
3686
3687         mac_status = tr32(MAC_STATUS);
3688         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3689                 current_link_up = 0;
3690                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3691                     tp->serdes_counter == 0) {
3692                         tw32_f(MAC_MODE, (tp->mac_mode |
3693                                           MAC_MODE_SEND_CONFIGS));
3694                         udelay(1);
3695                         tw32_f(MAC_MODE, tp->mac_mode);
3696                 }
3697         }
3698
3699         if (current_link_up == 1) {
3700                 tp->link_config.active_speed = SPEED_1000;
3701                 tp->link_config.active_duplex = DUPLEX_FULL;
3702                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3703                                     LED_CTRL_LNKLED_OVERRIDE |
3704                                     LED_CTRL_1000MBPS_ON));
3705         } else {
3706                 tp->link_config.active_speed = SPEED_INVALID;
3707                 tp->link_config.active_duplex = DUPLEX_INVALID;
3708                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3709                                     LED_CTRL_LNKLED_OVERRIDE |
3710                                     LED_CTRL_TRAFFIC_OVERRIDE));
3711         }
3712
3713         if (current_link_up != netif_carrier_ok(tp->dev)) {
3714                 if (current_link_up)
3715                         netif_carrier_on(tp->dev);
3716                 else
3717                         netif_carrier_off(tp->dev);
3718                 tg3_link_report(tp);
3719         } else {
3720                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
3721                 if (orig_pause_cfg != now_pause_cfg ||
3722                     orig_active_speed != tp->link_config.active_speed ||
3723                     orig_active_duplex != tp->link_config.active_duplex)
3724                         tg3_link_report(tp);
3725         }
3726
3727         return 0;
3728 }
3729
3730 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3731 {
3732         int current_link_up, err = 0;
3733         u32 bmsr, bmcr;
3734         u16 current_speed;
3735         u8 current_duplex;
3736         u32 local_adv, remote_adv;
3737
3738         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3739         tw32_f(MAC_MODE, tp->mac_mode);
3740         udelay(40);
3741
3742         tw32(MAC_EVENT, 0);
3743
3744         tw32_f(MAC_STATUS,
3745              (MAC_STATUS_SYNC_CHANGED |
3746               MAC_STATUS_CFG_CHANGED |
3747               MAC_STATUS_MI_COMPLETION |
3748               MAC_STATUS_LNKSTATE_CHANGED));
3749         udelay(40);
3750
3751         if (force_reset)
3752                 tg3_phy_reset(tp);
3753
3754         current_link_up = 0;
3755         current_speed = SPEED_INVALID;
3756         current_duplex = DUPLEX_INVALID;
3757
3758         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3759         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3760         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3761                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3762                         bmsr |= BMSR_LSTATUS;
3763                 else
3764                         bmsr &= ~BMSR_LSTATUS;
3765         }
3766
3767         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3768
3769         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
3770             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3771                 /* do nothing, just check for link up at the end */
3772         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3773                 u32 adv, new_adv;
3774
3775                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3776                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
3777                                   ADVERTISE_1000XPAUSE |
3778                                   ADVERTISE_1000XPSE_ASYM |
3779                                   ADVERTISE_SLCT);
3780
3781                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3782
3783                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
3784                         new_adv |= ADVERTISE_1000XHALF;
3785                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
3786                         new_adv |= ADVERTISE_1000XFULL;
3787
3788                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
3789                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
3790                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
3791                         tg3_writephy(tp, MII_BMCR, bmcr);
3792
3793                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3794                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
3795                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3796
3797                         return err;
3798                 }
3799         } else {
3800                 u32 new_bmcr;
3801
3802                 bmcr &= ~BMCR_SPEED1000;
3803                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
3804
3805                 if (tp->link_config.duplex == DUPLEX_FULL)
3806                         new_bmcr |= BMCR_FULLDPLX;
3807
3808                 if (new_bmcr != bmcr) {
3809                         /* BMCR_SPEED1000 is a reserved bit that needs
3810                          * to be set on write.
3811                          */
3812                         new_bmcr |= BMCR_SPEED1000;
3813
3814                         /* Force a linkdown */
3815                         if (netif_carrier_ok(tp->dev)) {
3816                                 u32 adv;
3817
3818                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3819                                 adv &= ~(ADVERTISE_1000XFULL |
3820                                          ADVERTISE_1000XHALF |
3821                                          ADVERTISE_SLCT);
3822                                 tg3_writephy(tp, MII_ADVERTISE, adv);
3823                                 tg3_writephy(tp, MII_BMCR, bmcr |
3824                                                            BMCR_ANRESTART |
3825                                                            BMCR_ANENABLE);
3826                                 udelay(10);
3827                                 netif_carrier_off(tp->dev);
3828                         }
3829                         tg3_writephy(tp, MII_BMCR, new_bmcr);
3830                         bmcr = new_bmcr;
3831                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3832                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3833                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
3834                             ASIC_REV_5714) {
3835                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3836                                         bmsr |= BMSR_LSTATUS;
3837                                 else
3838                                         bmsr &= ~BMSR_LSTATUS;
3839                         }
3840                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3841                 }
3842         }
3843
3844         if (bmsr & BMSR_LSTATUS) {
3845                 current_speed = SPEED_1000;
3846                 current_link_up = 1;
3847                 if (bmcr & BMCR_FULLDPLX)
3848                         current_duplex = DUPLEX_FULL;
3849                 else
3850                         current_duplex = DUPLEX_HALF;
3851
3852                 local_adv = 0;
3853                 remote_adv = 0;
3854
3855                 if (bmcr & BMCR_ANENABLE) {
3856                         u32 common;
3857
3858                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
3859                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
3860                         common = local_adv & remote_adv;
3861                         if (common & (ADVERTISE_1000XHALF |
3862                                       ADVERTISE_1000XFULL)) {
3863                                 if (common & ADVERTISE_1000XFULL)
3864                                         current_duplex = DUPLEX_FULL;
3865                                 else
3866                                         current_duplex = DUPLEX_HALF;
3867                         }
3868                         else
3869                                 current_link_up = 0;
3870                 }
3871         }
3872
3873         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
3874                 tg3_setup_flow_control(tp, local_adv, remote_adv);
3875
3876         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3877         if (tp->link_config.active_duplex == DUPLEX_HALF)
3878                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3879
3880         tw32_f(MAC_MODE, tp->mac_mode);
3881         udelay(40);
3882
3883         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3884
3885         tp->link_config.active_speed = current_speed;
3886         tp->link_config.active_duplex = current_duplex;
3887
3888         if (current_link_up != netif_carrier_ok(tp->dev)) {
3889                 if (current_link_up)
3890                         netif_carrier_on(tp->dev);
3891                 else {
3892                         netif_carrier_off(tp->dev);
3893                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3894                 }
3895                 tg3_link_report(tp);
3896         }
3897         return err;
3898 }
3899
3900 static void tg3_serdes_parallel_detect(struct tg3 *tp)
3901 {
3902         if (tp->serdes_counter) {
3903                 /* Give autoneg time to complete. */
3904                 tp->serdes_counter--;
3905                 return;
3906         }
3907         if (!netif_carrier_ok(tp->dev) &&
3908             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
3909                 u32 bmcr;
3910
3911                 tg3_readphy(tp, MII_BMCR, &bmcr);
3912                 if (bmcr & BMCR_ANENABLE) {
3913                         u32 phy1, phy2;
3914
3915                         /* Select shadow register 0x1f */
3916                         tg3_writephy(tp, 0x1c, 0x7c00);
3917                         tg3_readphy(tp, 0x1c, &phy1);
3918
3919                         /* Select expansion interrupt status register */
3920                         tg3_writephy(tp, 0x17, 0x0f01);
3921                         tg3_readphy(tp, 0x15, &phy2);
3922                         tg3_readphy(tp, 0x15, &phy2);
3923
3924                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
3925                                 /* We have signal detect and not receiving
3926                                  * config code words, link is up by parallel
3927                                  * detection.
3928                                  */
3929
3930                                 bmcr &= ~BMCR_ANENABLE;
3931                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
3932                                 tg3_writephy(tp, MII_BMCR, bmcr);
3933                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
3934                         }
3935                 }
3936         }
3937         else if (netif_carrier_ok(tp->dev) &&
3938                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
3939                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3940                 u32 phy2;
3941
3942                 /* Select expansion interrupt status register */
3943                 tg3_writephy(tp, 0x17, 0x0f01);
3944                 tg3_readphy(tp, 0x15, &phy2);
3945                 if (phy2 & 0x20) {
3946                         u32 bmcr;
3947
3948                         /* Config code words received, turn on autoneg. */
3949                         tg3_readphy(tp, MII_BMCR, &bmcr);
3950                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
3951
3952                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3953
3954                 }
3955         }
3956 }
3957
3958 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
3959 {
3960         int err;
3961
3962         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
3963                 err = tg3_setup_fiber_phy(tp, force_reset);
3964         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
3965                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
3966         } else {
3967                 err = tg3_setup_copper_phy(tp, force_reset);
3968         }
3969
3970         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
3971                 u32 val, scale;
3972
3973                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
3974                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
3975                         scale = 65;
3976                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
3977                         scale = 6;
3978                 else
3979                         scale = 12;
3980
3981                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
3982                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
3983                 tw32(GRC_MISC_CFG, val);
3984         }
3985
3986         if (tp->link_config.active_speed == SPEED_1000 &&
3987             tp->link_config.active_duplex == DUPLEX_HALF)
3988                 tw32(MAC_TX_LENGTHS,
3989                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3990                       (6 << TX_LENGTHS_IPG_SHIFT) |
3991                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3992         else
3993                 tw32(MAC_TX_LENGTHS,
3994                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3995                       (6 << TX_LENGTHS_IPG_SHIFT) |
3996                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3997
3998         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3999                 if (netif_carrier_ok(tp->dev)) {
4000                         tw32(HOSTCC_STAT_COAL_TICKS,
4001                              tp->coal.stats_block_coalesce_usecs);
4002                 } else {
4003                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4004                 }
4005         }
4006
4007         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4008                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4009                 if (!netif_carrier_ok(tp->dev))
4010                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4011                               tp->pwrmgmt_thresh;
4012                 else
4013                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4014                 tw32(PCIE_PWR_MGMT_THRESH, val);
4015         }
4016
4017         return err;
4018 }
4019
4020 /* This is called whenever we suspect that the system chipset is re-
4021  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4022  * is bogus tx completions. We try to recover by setting the
4023  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4024  * in the workqueue.
4025  */
4026 static void tg3_tx_recover(struct tg3 *tp)
4027 {
4028         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4029                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4030
4031         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4032                "mapped I/O cycles to the network device, attempting to "
4033                "recover. Please report the problem to the driver maintainer "
4034                "and include system chipset information.\n", tp->dev->name);
4035
4036         spin_lock(&tp->lock);
4037         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4038         spin_unlock(&tp->lock);
4039 }
4040
4041 static inline u32 tg3_tx_avail(struct tg3 *tp)
4042 {
4043         smp_mb();
4044         return (tp->tx_pending -
4045                 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
4046 }
4047
4048 /* Tigon3 never reports partial packet sends.  So we do not
4049  * need special logic to handle SKBs that have not had all
4050  * of their frags sent yet, like SunGEM does.
4051  */
4052 static void tg3_tx(struct tg3 *tp)
4053 {
4054         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
4055         u32 sw_idx = tp->tx_cons;
4056
4057         while (sw_idx != hw_idx) {
4058                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
4059                 struct sk_buff *skb = ri->skb;
4060                 int i, tx_bug = 0;
4061
4062                 if (unlikely(skb == NULL)) {
4063                         tg3_tx_recover(tp);
4064                         return;
4065                 }
4066
4067                 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
4068
4069                 ri->skb = NULL;
4070
4071                 sw_idx = NEXT_TX(sw_idx);
4072
4073                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4074                         ri = &tp->tx_buffers[sw_idx];
4075                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4076                                 tx_bug = 1;
4077                         sw_idx = NEXT_TX(sw_idx);
4078                 }
4079
4080                 dev_kfree_skb(skb);
4081
4082                 if (unlikely(tx_bug)) {
4083                         tg3_tx_recover(tp);
4084                         return;
4085                 }
4086         }
4087
4088         tp->tx_cons = sw_idx;
4089
4090         /* Need to make the tx_cons update visible to tg3_start_xmit()
4091          * before checking for netif_queue_stopped().  Without the
4092          * memory barrier, there is a small possibility that tg3_start_xmit()
4093          * will miss it and cause the queue to be stopped forever.
4094          */
4095         smp_mb();
4096
4097         if (unlikely(netif_queue_stopped(tp->dev) &&
4098                      (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
4099                 netif_tx_lock(tp->dev);
4100                 if (netif_queue_stopped(tp->dev) &&
4101                     (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
4102                         netif_wake_queue(tp->dev);
4103                 netif_tx_unlock(tp->dev);
4104         }
4105 }
4106
4107 /* Returns size of skb allocated or < 0 on error.
4108  *
4109  * We only need to fill in the address because the other members
4110  * of the RX descriptor are invariant, see tg3_init_rings.
4111  *
4112  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4113  * posting buffers we only dirty the first cache line of the RX
4114  * descriptor (containing the address).  Whereas for the RX status
4115  * buffers the cpu only reads the last cacheline of the RX descriptor
4116  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4117  */
4118 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
4119                             int src_idx, u32 dest_idx_unmasked)
4120 {
4121         struct tg3_rx_buffer_desc *desc;
4122         struct ring_info *map, *src_map;
4123         struct sk_buff *skb;
4124         dma_addr_t mapping;
4125         int skb_size, dest_idx;
4126
4127         src_map = NULL;
4128         switch (opaque_key) {
4129         case RXD_OPAQUE_RING_STD:
4130                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4131                 desc = &tp->rx_std[dest_idx];
4132                 map = &tp->rx_std_buffers[dest_idx];
4133                 if (src_idx >= 0)
4134                         src_map = &tp->rx_std_buffers[src_idx];
4135                 skb_size = tp->rx_pkt_buf_sz;
4136                 break;
4137
4138         case RXD_OPAQUE_RING_JUMBO:
4139                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4140                 desc = &tp->rx_jumbo[dest_idx];
4141                 map = &tp->rx_jumbo_buffers[dest_idx];
4142                 if (src_idx >= 0)
4143                         src_map = &tp->rx_jumbo_buffers[src_idx];
4144                 skb_size = RX_JUMBO_PKT_BUF_SZ;
4145                 break;
4146
4147         default:
4148                 return -EINVAL;
4149         }
4150
4151         /* Do not overwrite any of the map or rp information
4152          * until we are sure we can commit to a new buffer.
4153          *
4154          * Callers depend upon this behavior and assume that
4155          * we leave everything unchanged if we fail.
4156          */
4157         skb = netdev_alloc_skb(tp->dev, skb_size);
4158         if (skb == NULL)
4159                 return -ENOMEM;
4160
4161         skb_reserve(skb, tp->rx_offset);
4162
4163         mapping = pci_map_single(tp->pdev, skb->data,
4164                                  skb_size - tp->rx_offset,
4165                                  PCI_DMA_FROMDEVICE);
4166
4167         map->skb = skb;
4168         pci_unmap_addr_set(map, mapping, mapping);
4169
4170         if (src_map != NULL)
4171                 src_map->skb = NULL;
4172
4173         desc->addr_hi = ((u64)mapping >> 32);
4174         desc->addr_lo = ((u64)mapping & 0xffffffff);
4175
4176         return skb_size;
4177 }
4178
4179 /* We only need to move over in the address because the other
4180  * members of the RX descriptor are invariant.  See notes above
4181  * tg3_alloc_rx_skb for full details.
4182  */
4183 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
4184                            int src_idx, u32 dest_idx_unmasked)
4185 {
4186         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4187         struct ring_info *src_map, *dest_map;
4188         int dest_idx;
4189
4190         switch (opaque_key) {
4191         case RXD_OPAQUE_RING_STD:
4192                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4193                 dest_desc = &tp->rx_std[dest_idx];
4194                 dest_map = &tp->rx_std_buffers[dest_idx];
4195                 src_desc = &tp->rx_std[src_idx];
4196                 src_map = &tp->rx_std_buffers[src_idx];
4197                 break;
4198
4199         case RXD_OPAQUE_RING_JUMBO:
4200                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4201                 dest_desc = &tp->rx_jumbo[dest_idx];
4202                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
4203                 src_desc = &tp->rx_jumbo[src_idx];
4204                 src_map = &tp->rx_jumbo_buffers[src_idx];
4205                 break;
4206
4207         default:
4208                 return;
4209         }
4210
4211         dest_map->skb = src_map->skb;
4212         pci_unmap_addr_set(dest_map, mapping,
4213                            pci_unmap_addr(src_map, mapping));
4214         dest_desc->addr_hi = src_desc->addr_hi;
4215         dest_desc->addr_lo = src_desc->addr_lo;
4216
4217         src_map->skb = NULL;
4218 }
4219
4220 #if TG3_VLAN_TAG_USED
4221 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
4222 {
4223         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
4224 }
4225 #endif
4226
4227 /* The RX ring scheme is composed of multiple rings which post fresh
4228  * buffers to the chip, and one special ring the chip uses to report
4229  * status back to the host.
4230  *
4231  * The special ring reports the status of received packets to the
4232  * host.  The chip does not write into the original descriptor the
4233  * RX buffer was obtained from.  The chip simply takes the original
4234  * descriptor as provided by the host, updates the status and length
4235  * field, then writes this into the next status ring entry.
4236  *
4237  * Each ring the host uses to post buffers to the chip is described
4238  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4239  * it is first placed into the on-chip ram.  When the packet's length
4240  * is known, it walks down the TG3_BDINFO entries to select the ring.
4241  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4242  * which is within the range of the new packet's length is chosen.
4243  *
4244  * The "separate ring for rx status" scheme may sound queer, but it makes
4245  * sense from a cache coherency perspective.  If only the host writes
4246  * to the buffer post rings, and only the chip writes to the rx status
4247  * rings, then cache lines never move beyond shared-modified state.
4248  * If both the host and chip were to write into the same ring, cache line
4249  * eviction could occur since both entities want it in an exclusive state.
4250  */
4251 static int tg3_rx(struct tg3 *tp, int budget)
4252 {
4253         u32 work_mask, rx_std_posted = 0;
4254         u32 sw_idx = tp->rx_rcb_ptr;
4255         u16 hw_idx;
4256         int received;
4257
4258         hw_idx = tp->hw_status->idx[0].rx_producer;
4259         /*
4260          * We need to order the read of hw_idx and the read of
4261          * the opaque cookie.
4262          */
4263         rmb();
4264         work_mask = 0;
4265         received = 0;
4266         while (sw_idx != hw_idx && budget > 0) {
4267                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
4268                 unsigned int len;
4269                 struct sk_buff *skb;
4270                 dma_addr_t dma_addr;
4271                 u32 opaque_key, desc_idx, *post_ptr;
4272
4273                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4274                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4275                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4276                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
4277                                                   mapping);
4278                         skb = tp->rx_std_buffers[desc_idx].skb;
4279                         post_ptr = &tp->rx_std_ptr;
4280                         rx_std_posted++;
4281                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4282                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
4283                                                   mapping);
4284                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
4285                         post_ptr = &tp->rx_jumbo_ptr;
4286                 }
4287                 else {
4288                         goto next_pkt_nopost;
4289                 }
4290
4291                 work_mask |= opaque_key;
4292
4293                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4294                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4295                 drop_it:
4296                         tg3_recycle_rx(tp, opaque_key,
4297                                        desc_idx, *post_ptr);
4298                 drop_it_no_recycle:
4299                         /* Other statistics kept track of by card. */
4300                         tp->net_stats.rx_dropped++;
4301                         goto next_pkt;
4302                 }
4303
4304                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4305                       ETH_FCS_LEN;
4306
4307                 if (len > RX_COPY_THRESHOLD
4308                         && tp->rx_offset == NET_IP_ALIGN
4309                         /* rx_offset will likely not equal NET_IP_ALIGN
4310                          * if this is a 5701 card running in PCI-X mode
4311                          * [see tg3_get_invariants()]
4312                          */
4313                 ) {
4314                         int skb_size;
4315
4316                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
4317                                                     desc_idx, *post_ptr);
4318                         if (skb_size < 0)
4319                                 goto drop_it;
4320
4321                         pci_unmap_single(tp->pdev, dma_addr,
4322                                          skb_size - tp->rx_offset,
4323                                          PCI_DMA_FROMDEVICE);
4324
4325                         skb_put(skb, len);
4326                 } else {
4327                         struct sk_buff *copy_skb;
4328
4329                         tg3_recycle_rx(tp, opaque_key,
4330                                        desc_idx, *post_ptr);
4331
4332                         copy_skb = netdev_alloc_skb(tp->dev,
4333                                                     len + TG3_RAW_IP_ALIGN);
4334                         if (copy_skb == NULL)
4335                                 goto drop_it_no_recycle;
4336
4337                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4338                         skb_put(copy_skb, len);
4339                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4340                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4341                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4342
4343                         /* We'll reuse the original ring buffer. */
4344                         skb = copy_skb;
4345                 }
4346
4347                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4348                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4349                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4350                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4351                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4352                 else
4353                         skb->ip_summed = CHECKSUM_NONE;
4354
4355                 skb->protocol = eth_type_trans(skb, tp->dev);
4356 #if TG3_VLAN_TAG_USED
4357                 if (tp->vlgrp != NULL &&
4358                     desc->type_flags & RXD_FLAG_VLAN) {
4359                         tg3_vlan_rx(tp, skb,
4360                                     desc->err_vlan & RXD_VLAN_MASK);
4361                 } else
4362 #endif
4363                         netif_receive_skb(skb);
4364
4365                 received++;
4366                 budget--;
4367
4368 next_pkt:
4369                 (*post_ptr)++;
4370
4371                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4372                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4373
4374                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4375                                      TG3_64BIT_REG_LOW, idx);
4376                         work_mask &= ~RXD_OPAQUE_RING_STD;
4377                         rx_std_posted = 0;
4378                 }
4379 next_pkt_nopost:
4380                 sw_idx++;
4381                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4382
4383                 /* Refresh hw_idx to see if there is new work */
4384                 if (sw_idx == hw_idx) {
4385                         hw_idx = tp->hw_status->idx[0].rx_producer;
4386                         rmb();
4387                 }
4388         }
4389
4390         /* ACK the status ring. */
4391         tp->rx_rcb_ptr = sw_idx;
4392         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
4393
4394         /* Refill RX ring(s). */
4395         if (work_mask & RXD_OPAQUE_RING_STD) {
4396                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
4397                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4398                              sw_idx);
4399         }
4400         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4401                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
4402                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4403                              sw_idx);
4404         }
4405         mmiowb();
4406
4407         return received;
4408 }
4409
4410 static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
4411 {
4412         struct tg3_hw_status *sblk = tp->hw_status;
4413
4414         /* handle link change and other phy events */
4415         if (!(tp->tg3_flags &
4416               (TG3_FLAG_USE_LINKCHG_REG |
4417                TG3_FLAG_POLL_SERDES))) {
4418                 if (sblk->status & SD_STATUS_LINK_CHG) {
4419                         sblk->status = SD_STATUS_UPDATED |
4420                                 (sblk->status & ~SD_STATUS_LINK_CHG);
4421                         spin_lock(&tp->lock);
4422                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4423                                 tw32_f(MAC_STATUS,
4424                                      (MAC_STATUS_SYNC_CHANGED |
4425                                       MAC_STATUS_CFG_CHANGED |
4426                                       MAC_STATUS_MI_COMPLETION |
4427                                       MAC_STATUS_LNKSTATE_CHANGED));
4428                                 udelay(40);
4429                         } else
4430                                 tg3_setup_phy(tp, 0);
4431                         spin_unlock(&tp->lock);
4432                 }
4433         }
4434
4435         /* run TX completion thread */
4436         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
4437                 tg3_tx(tp);
4438                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4439                         return work_done;
4440         }
4441
4442         /* run RX thread, within the bounds set by NAPI.
4443          * All RX "locking" is done by ensuring outside
4444          * code synchronizes with tg3->napi.poll()
4445          */
4446         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
4447                 work_done += tg3_rx(tp, budget - work_done);
4448
4449         return work_done;
4450 }
4451
4452 static int tg3_poll(struct napi_struct *napi, int budget)
4453 {
4454         struct tg3 *tp = container_of(napi, struct tg3, napi);
4455         int work_done = 0;
4456         struct tg3_hw_status *sblk = tp->hw_status;
4457
4458         while (1) {
4459                 work_done = tg3_poll_work(tp, work_done, budget);
4460
4461                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4462                         goto tx_recovery;
4463
4464                 if (unlikely(work_done >= budget))
4465                         break;
4466
4467                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4468                         /* tp->last_tag is used in tg3_restart_ints() below
4469                          * to tell the hw how much work has been processed,
4470                          * so we must read it before checking for more work.
4471                          */
4472                         tp->last_tag = sblk->status_tag;
4473                         rmb();
4474                 } else
4475                         sblk->status &= ~SD_STATUS_UPDATED;
4476
4477                 if (likely(!tg3_has_work(tp))) {
4478                         netif_rx_complete(tp->dev, napi);
4479                         tg3_restart_ints(tp);
4480                         break;
4481                 }
4482         }
4483
4484         return work_done;
4485
4486 tx_recovery:
4487         /* work_done is guaranteed to be less than budget. */
4488         netif_rx_complete(tp->dev, napi);
4489         schedule_work(&tp->reset_task);
4490         return work_done;
4491 }
4492
4493 static void tg3_irq_quiesce(struct tg3 *tp)
4494 {
4495         BUG_ON(tp->irq_sync);
4496
4497         tp->irq_sync = 1;
4498         smp_mb();
4499
4500         synchronize_irq(tp->pdev->irq);
4501 }
4502
4503 static inline int tg3_irq_sync(struct tg3 *tp)
4504 {
4505         return tp->irq_sync;
4506 }
4507
4508 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4509  * If irq_sync is non-zero, then the IRQ handler must be synchronized
4510  * with as well.  Most of the time, this is not necessary except when
4511  * shutting down the device.
4512  */
4513 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4514 {
4515         spin_lock_bh(&tp->lock);
4516         if (irq_sync)
4517                 tg3_irq_quiesce(tp);
4518 }
4519
4520 static inline void tg3_full_unlock(struct tg3 *tp)
4521 {
4522         spin_unlock_bh(&tp->lock);
4523 }
4524
4525 /* One-shot MSI handler - Chip automatically disables interrupt
4526  * after sending MSI so driver doesn't have to do it.
4527  */
4528 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4529 {
4530         struct net_device *dev = dev_id;
4531         struct tg3 *tp = netdev_priv(dev);
4532
4533         prefetch(tp->hw_status);
4534         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4535
4536         if (likely(!tg3_irq_sync(tp)))
4537                 netif_rx_schedule(dev, &tp->napi);
4538
4539         return IRQ_HANDLED;
4540 }
4541
4542 /* MSI ISR - No need to check for interrupt sharing and no need to
4543  * flush status block and interrupt mailbox. PCI ordering rules
4544  * guarantee that MSI will arrive after the status block.
4545  */
4546 static irqreturn_t tg3_msi(int irq, void *dev_id)
4547 {
4548         struct net_device *dev = dev_id;
4549         struct tg3 *tp = netdev_priv(dev);
4550
4551         prefetch(tp->hw_status);
4552         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4553         /*
4554          * Writing any value to intr-mbox-0 clears PCI INTA# and
4555          * chip-internal interrupt pending events.
4556          * Writing non-zero to intr-mbox-0 additional tells the
4557          * NIC to stop sending us irqs, engaging "in-intr-handler"
4558          * event coalescing.
4559          */
4560         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4561         if (likely(!tg3_irq_sync(tp)))
4562                 netif_rx_schedule(dev, &tp->napi);
4563
4564         return IRQ_RETVAL(1);
4565 }
4566
4567 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4568 {
4569         struct net_device *dev = dev_id;
4570         struct tg3 *tp = netdev_priv(dev);
4571         struct tg3_hw_status *sblk = tp->hw_status;
4572         unsigned int handled = 1;
4573
4574         /* In INTx mode, it is possible for the interrupt to arrive at
4575          * the CPU before the status block posted prior to the interrupt.
4576          * Reading the PCI State register will confirm whether the
4577          * interrupt is ours and will flush the status block.
4578          */
4579         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4580                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4581                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4582                         handled = 0;
4583                         goto out;
4584                 }
4585         }
4586
4587         /*
4588          * Writing any value to intr-mbox-0 clears PCI INTA# and
4589          * chip-internal interrupt pending events.
4590          * Writing non-zero to intr-mbox-0 additional tells the
4591          * NIC to stop sending us irqs, engaging "in-intr-handler"
4592          * event coalescing.
4593          *
4594          * Flush the mailbox to de-assert the IRQ immediately to prevent
4595          * spurious interrupts.  The flush impacts performance but
4596          * excessive spurious interrupts can be worse in some cases.
4597          */
4598         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4599         if (tg3_irq_sync(tp))
4600                 goto out;
4601         sblk->status &= ~SD_STATUS_UPDATED;
4602         if (likely(tg3_has_work(tp))) {
4603                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4604                 netif_rx_schedule(dev, &tp->napi);
4605         } else {
4606                 /* No work, shared interrupt perhaps?  re-enable
4607                  * interrupts, and flush that PCI write
4608                  */
4609                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4610                                0x00000000);
4611         }
4612 out:
4613         return IRQ_RETVAL(handled);
4614 }
4615
4616 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4617 {
4618         struct net_device *dev = dev_id;
4619         struct tg3 *tp = netdev_priv(dev);
4620         struct tg3_hw_status *sblk = tp->hw_status;
4621         unsigned int handled = 1;
4622
4623         /* In INTx mode, it is possible for the interrupt to arrive at
4624          * the CPU before the status block posted prior to the interrupt.
4625          * Reading the PCI State register will confirm whether the
4626          * interrupt is ours and will flush the status block.
4627          */
4628         if (unlikely(sblk->status_tag == tp->last_tag)) {
4629                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4630                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4631                         handled = 0;
4632                         goto out;
4633                 }
4634         }
4635
4636         /*
4637          * writing any value to intr-mbox-0 clears PCI INTA# and
4638          * chip-internal interrupt pending events.
4639          * writing non-zero to intr-mbox-0 additional tells the
4640          * NIC to stop sending us irqs, engaging "in-intr-handler"
4641          * event coalescing.
4642          *
4643          * Flush the mailbox to de-assert the IRQ immediately to prevent
4644          * spurious interrupts.  The flush impacts performance but
4645          * excessive spurious interrupts can be worse in some cases.
4646          */
4647         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4648         if (tg3_irq_sync(tp))
4649                 goto out;
4650         if (netif_rx_schedule_prep(dev, &tp->napi)) {
4651                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4652                 /* Update last_tag to mark that this status has been
4653                  * seen. Because interrupt may be shared, we may be
4654                  * racing with tg3_poll(), so only update last_tag
4655                  * if tg3_poll() is not scheduled.
4656                  */
4657                 tp->last_tag = sblk->status_tag;
4658                 __netif_rx_schedule(dev, &tp->napi);
4659         }
4660 out:
4661         return IRQ_RETVAL(handled);
4662 }
4663
4664 /* ISR for interrupt test */
4665 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4666 {
4667         struct net_device *dev = dev_id;
4668         struct tg3 *tp = netdev_priv(dev);
4669         struct tg3_hw_status *sblk = tp->hw_status;
4670
4671         if ((sblk->status & SD_STATUS_UPDATED) ||
4672             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4673                 tg3_disable_ints(tp);
4674                 return IRQ_RETVAL(1);
4675         }
4676         return IRQ_RETVAL(0);
4677 }
4678
4679 static int tg3_init_hw(struct tg3 *, int);
4680 static int tg3_halt(struct tg3 *, int, int);
4681
4682 /* Restart hardware after configuration changes, self-test, etc.
4683  * Invoked with tp->lock held.
4684  */
4685 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4686         __releases(tp->lock)
4687         __acquires(tp->lock)
4688 {
4689         int err;
4690
4691         err = tg3_init_hw(tp, reset_phy);
4692         if (err) {
4693                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4694                        "aborting.\n", tp->dev->name);
4695                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4696                 tg3_full_unlock(tp);
4697                 del_timer_sync(&tp->timer);
4698                 tp->irq_sync = 0;
4699                 napi_enable(&tp->napi);
4700                 dev_close(tp->dev);
4701                 tg3_full_lock(tp, 0);
4702         }
4703         return err;
4704 }
4705
4706 #ifdef CONFIG_NET_POLL_CONTROLLER
4707 static void tg3_poll_controller(struct net_device *dev)
4708 {
4709         struct tg3 *tp = netdev_priv(dev);
4710
4711         tg3_interrupt(tp->pdev->irq, dev);
4712 }
4713 #endif
4714
4715 static void tg3_reset_task(struct work_struct *work)
4716 {
4717         struct tg3 *tp = container_of(work, struct tg3, reset_task);
4718         int err;
4719         unsigned int restart_timer;
4720
4721         tg3_full_lock(tp, 0);
4722
4723         if (!netif_running(tp->dev)) {
4724                 tg3_full_unlock(tp);
4725                 return;
4726         }
4727
4728         tg3_full_unlock(tp);
4729
4730         tg3_phy_stop(tp);
4731
4732         tg3_netif_stop(tp);
4733
4734         tg3_full_lock(tp, 1);
4735
4736         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4737         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4738
4739         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4740                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4741                 tp->write32_rx_mbox = tg3_write_flush_reg32;
4742                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4743                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4744         }
4745
4746         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
4747         err = tg3_init_hw(tp, 1);
4748         if (err)
4749                 goto out;
4750
4751         tg3_netif_start(tp);
4752
4753         if (restart_timer)
4754                 mod_timer(&tp->timer, jiffies + 1);
4755
4756 out:
4757         tg3_full_unlock(tp);
4758
4759         if (!err)
4760                 tg3_phy_start(tp);
4761 }
4762
4763 static void tg3_dump_short_state(struct tg3 *tp)
4764 {
4765         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
4766                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
4767         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
4768                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
4769 }
4770
4771 static void tg3_tx_timeout(struct net_device *dev)
4772 {
4773         struct tg3 *tp = netdev_priv(dev);
4774
4775         if (netif_msg_tx_err(tp)) {
4776                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
4777                        dev->name);
4778                 tg3_dump_short_state(tp);
4779         }
4780
4781         schedule_work(&tp->reset_task);
4782 }
4783
4784 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
4785 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
4786 {
4787         u32 base = (u32) mapping & 0xffffffff;
4788
4789         return ((base > 0xffffdcc0) &&
4790                 (base + len + 8 < base));
4791 }
4792
4793 /* Test for DMA addresses > 40-bit */
4794 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
4795                                           int len)
4796 {
4797 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
4798         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
4799                 return (((u64) mapping + len) > DMA_40BIT_MASK);
4800         return 0;
4801 #else
4802         return 0;
4803 #endif
4804 }
4805
4806 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
4807
4808 /* Workaround 4GB and 40-bit hardware DMA bugs. */
4809 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
4810                                        u32 last_plus_one, u32 *start,
4811                                        u32 base_flags, u32 mss)
4812 {
4813         struct sk_buff *new_skb;
4814         dma_addr_t new_addr = 0;
4815         u32 entry = *start;
4816         int i, ret = 0;
4817
4818         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
4819                 new_skb = skb_copy(skb, GFP_ATOMIC);
4820         else {
4821                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
4822
4823                 new_skb = skb_copy_expand(skb,
4824                                           skb_headroom(skb) + more_headroom,
4825                                           skb_tailroom(skb), GFP_ATOMIC);
4826         }
4827
4828         if (!new_skb) {
4829                 ret = -1;
4830         } else {
4831                 /* New SKB is guaranteed to be linear. */
4832                 entry = *start;
4833                 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
4834                 new_addr = skb_shinfo(new_skb)->dma_maps[0];
4835
4836                 /* Make sure new skb does not cross any 4G boundaries.
4837                  * Drop the packet if it does.
4838                  */
4839                 if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) {
4840                         if (!ret)
4841                                 skb_dma_unmap(&tp->pdev->dev, new_skb,
4842                                               DMA_TO_DEVICE);
4843                         ret = -1;
4844                         dev_kfree_skb(new_skb);
4845                         new_skb = NULL;
4846                 } else {
4847                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
4848                                     base_flags, 1 | (mss << 1));
4849                         *start = NEXT_TX(entry);
4850                 }
4851         }
4852
4853         /* Now clean up the sw ring entries. */
4854         i = 0;
4855         while (entry != last_plus_one) {
4856                 if (i == 0) {
4857                         tp->tx_buffers[entry].skb = new_skb;
4858                 } else {
4859                         tp->tx_buffers[entry].skb = NULL;
4860                 }
4861                 entry = NEXT_TX(entry);
4862                 i++;
4863         }
4864
4865         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
4866         dev_kfree_skb(skb);
4867
4868         return ret;
4869 }
4870
4871 static void tg3_set_txd(struct tg3 *tp, int entry,
4872                         dma_addr_t mapping, int len, u32 flags,
4873                         u32 mss_and_is_end)
4874 {
4875         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
4876         int is_end = (mss_and_is_end & 0x1);
4877         u32 mss = (mss_and_is_end >> 1);
4878         u32 vlan_tag = 0;
4879
4880         if (is_end)
4881                 flags |= TXD_FLAG_END;
4882         if (flags & TXD_FLAG_VLAN) {
4883                 vlan_tag = flags >> 16;
4884                 flags &= 0xffff;
4885         }
4886         vlan_tag |= (mss << TXD_MSS_SHIFT);
4887
4888         txd->addr_hi = ((u64) mapping >> 32);
4889         txd->addr_lo = ((u64) mapping & 0xffffffff);
4890         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
4891         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
4892 }
4893
4894 /* hard_start_xmit for devices that don't have any bugs and
4895  * support TG3_FLG2_HW_TSO_2 only.
4896  */
4897 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
4898 {
4899         struct tg3 *tp = netdev_priv(dev);
4900         u32 len, entry, base_flags, mss;
4901         struct skb_shared_info *sp;
4902         dma_addr_t mapping;
4903
4904         len = skb_headlen(skb);
4905
4906         /* We are running in BH disabled context with netif_tx_lock
4907          * and TX reclaim runs via tp->napi.poll inside of a software
4908          * interrupt.  Furthermore, IRQ processing runs lockless so we have
4909          * no IRQ context deadlocks to worry about either.  Rejoice!
4910          */
4911         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4912                 if (!netif_queue_stopped(dev)) {
4913                         netif_stop_queue(dev);
4914
4915                         /* This is a hard error, log it. */
4916                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4917                                "queue awake!\n", dev->name);
4918                 }
4919                 return NETDEV_TX_BUSY;
4920         }
4921
4922         entry = tp->tx_prod;
4923         base_flags = 0;
4924         mss = 0;
4925         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4926                 int tcp_opt_len, ip_tcp_len;
4927
4928                 if (skb_header_cloned(skb) &&
4929                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4930                         dev_kfree_skb(skb);
4931                         goto out_unlock;
4932                 }
4933
4934                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
4935                         mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
4936                 else {
4937                         struct iphdr *iph = ip_hdr(skb);
4938
4939                         tcp_opt_len = tcp_optlen(skb);
4940                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4941
4942                         iph->check = 0;
4943                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
4944                         mss |= (ip_tcp_len + tcp_opt_len) << 9;
4945                 }
4946
4947                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4948                                TXD_FLAG_CPU_POST_DMA);
4949
4950                 tcp_hdr(skb)->check = 0;
4951
4952         }
4953         else if (skb->ip_summed == CHECKSUM_PARTIAL)
4954                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4955 #if TG3_VLAN_TAG_USED
4956         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4957                 base_flags |= (TXD_FLAG_VLAN |
4958                                (vlan_tx_tag_get(skb) << 16));
4959 #endif
4960
4961         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
4962                 dev_kfree_skb(skb);
4963                 goto out_unlock;
4964         }
4965
4966         sp = skb_shinfo(skb);
4967
4968         mapping = sp->dma_maps[0];
4969
4970         tp->tx_buffers[entry].skb = skb;
4971
4972         tg3_set_txd(tp, entry, mapping, len, base_flags,
4973                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4974
4975         entry = NEXT_TX(entry);
4976
4977         /* Now loop through additional data fragments, and queue them. */
4978         if (skb_shinfo(skb)->nr_frags > 0) {
4979                 unsigned int i, last;
4980
4981                 last = skb_shinfo(skb)->nr_frags - 1;
4982                 for (i = 0; i <= last; i++) {
4983                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4984
4985                         len = frag->size;
4986                         mapping = sp->dma_maps[i + 1];
4987                         tp->tx_buffers[entry].skb = NULL;
4988
4989                         tg3_set_txd(tp, entry, mapping, len,
4990                                     base_flags, (i == last) | (mss << 1));
4991
4992                         entry = NEXT_TX(entry);
4993                 }
4994         }
4995
4996         /* Packets are ready, update Tx producer idx local and on card. */
4997         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4998
4999         tp->tx_prod = entry;
5000         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5001                 netif_stop_queue(dev);
5002                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5003                         netif_wake_queue(tp->dev);
5004         }
5005
5006 out_unlock:
5007         mmiowb();
5008
5009         dev->trans_start = jiffies;
5010
5011         return NETDEV_TX_OK;
5012 }
5013
5014 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
5015
5016 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5017  * TSO header is greater than 80 bytes.
5018  */
5019 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5020 {
5021         struct sk_buff *segs, *nskb;
5022
5023         /* Estimate the number of fragments in the worst case */
5024         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
5025                 netif_stop_queue(tp->dev);
5026                 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
5027                         return NETDEV_TX_BUSY;
5028
5029                 netif_wake_queue(tp->dev);
5030         }
5031
5032         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5033         if (IS_ERR(segs))
5034                 goto tg3_tso_bug_end;
5035
5036         do {
5037                 nskb = segs;
5038                 segs = segs->next;
5039                 nskb->next = NULL;
5040                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5041         } while (segs);
5042
5043 tg3_tso_bug_end:
5044         dev_kfree_skb(skb);
5045
5046         return NETDEV_TX_OK;
5047 }
5048
5049 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5050  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5051  */
5052 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
5053 {
5054         struct tg3 *tp = netdev_priv(dev);
5055         u32 len, entry, base_flags, mss;
5056         struct skb_shared_info *sp;
5057         int would_hit_hwbug;
5058         dma_addr_t mapping;
5059
5060         len = skb_headlen(skb);
5061
5062         /* We are running in BH disabled context with netif_tx_lock
5063          * and TX reclaim runs via tp->napi.poll inside of a software
5064          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5065          * no IRQ context deadlocks to worry about either.  Rejoice!
5066          */
5067         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5068                 if (!netif_queue_stopped(dev)) {
5069                         netif_stop_queue(dev);
5070
5071                         /* This is a hard error, log it. */
5072                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5073                                "queue awake!\n", dev->name);
5074                 }
5075                 return NETDEV_TX_BUSY;
5076         }
5077
5078         entry = tp->tx_prod;
5079         base_flags = 0;
5080         if (skb->ip_summed == CHECKSUM_PARTIAL)
5081                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5082         mss = 0;
5083         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5084                 struct iphdr *iph;
5085                 int tcp_opt_len, ip_tcp_len, hdr_len;
5086
5087                 if (skb_header_cloned(skb) &&
5088                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5089                         dev_kfree_skb(skb);
5090                         goto out_unlock;
5091                 }
5092
5093                 tcp_opt_len = tcp_optlen(skb);
5094                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5095
5096                 hdr_len = ip_tcp_len + tcp_opt_len;
5097                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5098                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5099                         return (tg3_tso_bug(tp, skb));
5100
5101                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5102                                TXD_FLAG_CPU_POST_DMA);
5103
5104                 iph = ip_hdr(skb);
5105                 iph->check = 0;
5106                 iph->tot_len = htons(mss + hdr_len);
5107                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5108                         tcp_hdr(skb)->check = 0;
5109                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5110                 } else
5111                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5112                                                                  iph->daddr, 0,
5113                                                                  IPPROTO_TCP,
5114                                                                  0);
5115
5116                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
5117                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
5118                         if (tcp_opt_len || iph->ihl > 5) {
5119                                 int tsflags;
5120
5121                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5122                                 mss |= (tsflags << 11);
5123                         }
5124                 } else {
5125                         if (tcp_opt_len || iph->ihl > 5) {
5126                                 int tsflags;
5127
5128                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5129                                 base_flags |= tsflags << 12;
5130                         }
5131                 }
5132         }
5133 #if TG3_VLAN_TAG_USED
5134         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5135                 base_flags |= (TXD_FLAG_VLAN |
5136                                (vlan_tx_tag_get(skb) << 16));
5137 #endif
5138
5139         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5140                 dev_kfree_skb(skb);
5141                 goto out_unlock;
5142         }
5143
5144         sp = skb_shinfo(skb);
5145
5146         mapping = sp->dma_maps[0];
5147
5148         tp->tx_buffers[entry].skb = skb;
5149
5150         would_hit_hwbug = 0;
5151
5152         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5153                 would_hit_hwbug = 1;
5154         else if (tg3_4g_overflow_test(mapping, len))
5155                 would_hit_hwbug = 1;
5156
5157         tg3_set_txd(tp, entry, mapping, len, base_flags,
5158                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5159
5160         entry = NEXT_TX(entry);
5161
5162         /* Now loop through additional data fragments, and queue them. */
5163         if (skb_shinfo(skb)->nr_frags > 0) {
5164                 unsigned int i, last;
5165
5166                 last = skb_shinfo(skb)->nr_frags - 1;
5167                 for (i = 0; i <= last; i++) {
5168                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5169
5170                         len = frag->size;
5171                         mapping = sp->dma_maps[i + 1];
5172
5173                         tp->tx_buffers[entry].skb = NULL;
5174
5175                         if (tg3_4g_overflow_test(mapping, len))
5176                                 would_hit_hwbug = 1;
5177
5178                         if (tg3_40bit_overflow_test(tp, mapping, len))
5179                                 would_hit_hwbug = 1;
5180
5181                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5182                                 tg3_set_txd(tp, entry, mapping, len,
5183                                             base_flags, (i == last)|(mss << 1));
5184                         else
5185                                 tg3_set_txd(tp, entry, mapping, len,
5186                                             base_flags, (i == last));
5187
5188                         entry = NEXT_TX(entry);
5189                 }
5190         }
5191
5192         if (would_hit_hwbug) {
5193                 u32 last_plus_one = entry;
5194                 u32 start;
5195
5196                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5197                 start &= (TG3_TX_RING_SIZE - 1);
5198
5199                 /* If the workaround fails due to memory/mapping
5200                  * failure, silently drop this packet.
5201                  */
5202                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
5203                                                 &start, base_flags, mss))
5204                         goto out_unlock;
5205
5206                 entry = start;
5207         }
5208
5209         /* Packets are ready, update Tx producer idx local and on card. */
5210         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5211
5212         tp->tx_prod = entry;
5213         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5214                 netif_stop_queue(dev);
5215                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5216                         netif_wake_queue(tp->dev);
5217         }
5218
5219 out_unlock:
5220         mmiowb();
5221
5222         dev->trans_start = jiffies;
5223
5224         return NETDEV_TX_OK;
5225 }
5226
5227 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5228                                int new_mtu)
5229 {
5230         dev->mtu = new_mtu;
5231
5232         if (new_mtu > ETH_DATA_LEN) {
5233                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5234                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5235                         ethtool_op_set_tso(dev, 0);
5236                 }
5237                 else
5238                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5239         } else {
5240                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5241                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5242                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5243         }
5244 }
5245
5246 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5247 {
5248         struct tg3 *tp = netdev_priv(dev);
5249         int err;
5250
5251         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5252                 return -EINVAL;
5253
5254         if (!netif_running(dev)) {
5255                 /* We'll just catch it later when the
5256                  * device is up'd.
5257                  */
5258                 tg3_set_mtu(dev, tp, new_mtu);
5259                 return 0;
5260         }
5261
5262         tg3_phy_stop(tp);
5263
5264         tg3_netif_stop(tp);
5265
5266         tg3_full_lock(tp, 1);
5267
5268         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5269
5270         tg3_set_mtu(dev, tp, new_mtu);
5271
5272         err = tg3_restart_hw(tp, 0);
5273
5274         if (!err)
5275                 tg3_netif_start(tp);
5276
5277         tg3_full_unlock(tp);
5278
5279         if (!err)
5280                 tg3_phy_start(tp);
5281
5282         return err;
5283 }
5284
5285 /* Free up pending packets in all rx/tx rings.
5286  *
5287  * The chip has been shut down and the driver detached from
5288  * the networking, so no interrupts or new tx packets will
5289  * end up in the driver.  tp->{tx,}lock is not held and we are not
5290  * in an interrupt context and thus may sleep.
5291  */
5292 static void tg3_free_rings(struct tg3 *tp)
5293 {
5294         struct ring_info *rxp;
5295         int i;
5296
5297         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5298                 rxp = &tp->rx_std_buffers[i];
5299
5300                 if (rxp->skb == NULL)
5301                         continue;
5302                 pci_unmap_single(tp->pdev,
5303                                  pci_unmap_addr(rxp, mapping),
5304                                  tp->rx_pkt_buf_sz - tp->rx_offset,
5305                                  PCI_DMA_FROMDEVICE);
5306                 dev_kfree_skb_any(rxp->skb);
5307                 rxp->skb = NULL;
5308         }
5309
5310         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5311                 rxp = &tp->rx_jumbo_buffers[i];
5312
5313                 if (rxp->skb == NULL)
5314                         continue;
5315                 pci_unmap_single(tp->pdev,
5316                                  pci_unmap_addr(rxp, mapping),
5317                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
5318                                  PCI_DMA_FROMDEVICE);
5319                 dev_kfree_skb_any(rxp->skb);
5320                 rxp->skb = NULL;
5321         }
5322
5323         for (i = 0; i < TG3_TX_RING_SIZE; ) {
5324                 struct tx_ring_info *txp;
5325                 struct sk_buff *skb;
5326
5327                 txp = &tp->tx_buffers[i];
5328                 skb = txp->skb;
5329
5330                 if (skb == NULL) {
5331                         i++;
5332                         continue;
5333                 }
5334
5335                 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5336
5337                 txp->skb = NULL;
5338
5339                 i += skb_shinfo(skb)->nr_frags + 1;
5340
5341                 dev_kfree_skb_any(skb);
5342         }
5343 }
5344
5345 /* Initialize tx/rx rings for packet processing.
5346  *
5347  * The chip has been shut down and the driver detached from
5348  * the networking, so no interrupts or new tx packets will
5349  * end up in the driver.  tp->{tx,}lock are held and thus
5350  * we may not sleep.
5351  */
5352 static int tg3_init_rings(struct tg3 *tp)
5353 {
5354         u32 i;
5355
5356         /* Free up all the SKBs. */
5357         tg3_free_rings(tp);
5358
5359         /* Zero out all descriptors. */
5360         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
5361         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
5362         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5363         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
5364
5365         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
5366         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5367             (tp->dev->mtu > ETH_DATA_LEN))
5368                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
5369
5370         /* Initialize invariants of the rings, we only set this
5371          * stuff once.  This works because the card does not
5372          * write into the rx buffer posting rings.
5373          */
5374         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5375                 struct tg3_rx_buffer_desc *rxd;
5376
5377                 rxd = &tp->rx_std[i];
5378                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
5379                         << RXD_LEN_SHIFT;
5380                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5381                 rxd->opaque = (RXD_OPAQUE_RING_STD |
5382                                (i << RXD_OPAQUE_INDEX_SHIFT));
5383         }
5384
5385         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5386                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5387                         struct tg3_rx_buffer_desc *rxd;
5388
5389                         rxd = &tp->rx_jumbo[i];
5390                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
5391                                 << RXD_LEN_SHIFT;
5392                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5393                                 RXD_FLAG_JUMBO;
5394                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5395                                (i << RXD_OPAQUE_INDEX_SHIFT));
5396                 }
5397         }
5398
5399         /* Now allocate fresh SKBs for each rx ring. */
5400         for (i = 0; i < tp->rx_pending; i++) {
5401                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5402                         printk(KERN_WARNING PFX
5403                                "%s: Using a smaller RX standard ring, "
5404                                "only %d out of %d buffers were allocated "
5405                                "successfully.\n",
5406                                tp->dev->name, i, tp->rx_pending);
5407                         if (i == 0)
5408                                 return -ENOMEM;
5409                         tp->rx_pending = i;
5410                         break;
5411                 }
5412         }
5413
5414         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5415                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5416                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
5417                                              -1, i) < 0) {
5418                                 printk(KERN_WARNING PFX
5419                                        "%s: Using a smaller RX jumbo ring, "
5420                                        "only %d out of %d buffers were "
5421                                        "allocated successfully.\n",
5422                                        tp->dev->name, i, tp->rx_jumbo_pending);
5423                                 if (i == 0) {
5424                                         tg3_free_rings(tp);
5425                                         return -ENOMEM;
5426                                 }
5427                                 tp->rx_jumbo_pending = i;
5428                                 break;
5429                         }
5430                 }
5431         }
5432         return 0;
5433 }
5434
5435 /*
5436  * Must not be invoked with interrupt sources disabled and
5437  * the hardware shutdown down.
5438  */
5439 static void tg3_free_consistent(struct tg3 *tp)
5440 {
5441         kfree(tp->rx_std_buffers);
5442         tp->rx_std_buffers = NULL;
5443         if (tp->rx_std) {
5444                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5445                                     tp->rx_std, tp->rx_std_mapping);
5446                 tp->rx_std = NULL;
5447         }
5448         if (tp->rx_jumbo) {
5449                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5450                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
5451                 tp->rx_jumbo = NULL;
5452         }
5453         if (tp->rx_rcb) {
5454                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5455                                     tp->rx_rcb, tp->rx_rcb_mapping);
5456                 tp->rx_rcb = NULL;
5457         }
5458         if (tp->tx_ring) {
5459                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5460                         tp->tx_ring, tp->tx_desc_mapping);
5461                 tp->tx_ring = NULL;
5462         }
5463         if (tp->hw_status) {
5464                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5465                                     tp->hw_status, tp->status_mapping);
5466                 tp->hw_status = NULL;
5467         }
5468         if (tp->hw_stats) {
5469                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5470                                     tp->hw_stats, tp->stats_mapping);
5471                 tp->hw_stats = NULL;
5472         }
5473 }
5474
5475 /*
5476  * Must not be invoked with interrupt sources disabled and
5477  * the hardware shutdown down.  Can sleep.
5478  */
5479 static int tg3_alloc_consistent(struct tg3 *tp)
5480 {
5481         tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
5482                                       (TG3_RX_RING_SIZE +
5483                                        TG3_RX_JUMBO_RING_SIZE)) +
5484                                      (sizeof(struct tx_ring_info) *
5485                                       TG3_TX_RING_SIZE),
5486                                      GFP_KERNEL);
5487         if (!tp->rx_std_buffers)
5488                 return -ENOMEM;
5489
5490         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
5491         tp->tx_buffers = (struct tx_ring_info *)
5492                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
5493
5494         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5495                                           &tp->rx_std_mapping);
5496         if (!tp->rx_std)
5497                 goto err_out;
5498
5499         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5500                                             &tp->rx_jumbo_mapping);
5501
5502         if (!tp->rx_jumbo)
5503                 goto err_out;
5504
5505         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5506                                           &tp->rx_rcb_mapping);
5507         if (!tp->rx_rcb)
5508                 goto err_out;
5509
5510         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5511                                            &tp->tx_desc_mapping);
5512         if (!tp->tx_ring)
5513                 goto err_out;
5514
5515         tp->hw_status = pci_alloc_consistent(tp->pdev,
5516                                              TG3_HW_STATUS_SIZE,
5517                                              &tp->status_mapping);
5518         if (!tp->hw_status)
5519                 goto err_out;
5520
5521         tp->hw_stats = pci_alloc_consistent(tp->pdev,
5522                                             sizeof(struct tg3_hw_stats),
5523                                             &tp->stats_mapping);
5524         if (!tp->hw_stats)
5525                 goto err_out;
5526
5527         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5528         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5529
5530         return 0;
5531
5532 err_out:
5533         tg3_free_consistent(tp);
5534         return -ENOMEM;
5535 }
5536
5537 #define MAX_WAIT_CNT 1000
5538
5539 /* To stop a block, clear the enable bit and poll till it
5540  * clears.  tp->lock is held.
5541  */
5542 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
5543 {
5544         unsigned int i;
5545         u32 val;
5546
5547         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5548                 switch (ofs) {
5549                 case RCVLSC_MODE:
5550                 case DMAC_MODE:
5551                 case MBFREE_MODE:
5552                 case BUFMGR_MODE:
5553                 case MEMARB_MODE:
5554                         /* We can't enable/disable these bits of the
5555                          * 5705/5750, just say success.
5556                          */
5557                         return 0;
5558
5559                 default:
5560                         break;
5561                 }
5562         }
5563
5564         val = tr32(ofs);
5565         val &= ~enable_bit;
5566         tw32_f(ofs, val);
5567
5568         for (i = 0; i < MAX_WAIT_CNT; i++) {
5569                 udelay(100);
5570                 val = tr32(ofs);
5571                 if ((val & enable_bit) == 0)
5572                         break;
5573         }
5574
5575         if (i == MAX_WAIT_CNT && !silent) {
5576                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5577                        "ofs=%lx enable_bit=%x\n",
5578                        ofs, enable_bit);
5579                 return -ENODEV;
5580         }
5581
5582         return 0;
5583 }
5584
5585 /* tp->lock is held. */
5586 static int tg3_abort_hw(struct tg3 *tp, int silent)
5587 {
5588         int i, err;
5589
5590         tg3_disable_ints(tp);
5591
5592         tp->rx_mode &= ~RX_MODE_ENABLE;
5593         tw32_f(MAC_RX_MODE, tp->rx_mode);
5594         udelay(10);
5595
5596         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5597         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5598         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5599         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5600         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5601         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5602
5603         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5604         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5605         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5606         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5607         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5608         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5609         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
5610
5611         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5612         tw32_f(MAC_MODE, tp->mac_mode);
5613         udelay(40);
5614
5615         tp->tx_mode &= ~TX_MODE_ENABLE;
5616         tw32_f(MAC_TX_MODE, tp->tx_mode);
5617
5618         for (i = 0; i < MAX_WAIT_CNT; i++) {
5619                 udelay(100);
5620                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5621                         break;
5622         }
5623         if (i >= MAX_WAIT_CNT) {
5624                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5625                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5626                        tp->dev->name, tr32(MAC_TX_MODE));
5627                 err |= -ENODEV;
5628         }
5629
5630         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
5631         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5632         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
5633
5634         tw32(FTQ_RESET, 0xffffffff);
5635         tw32(FTQ_RESET, 0x00000000);
5636
5637         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5638         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
5639
5640         if (tp->hw_status)
5641                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5642         if (tp->hw_stats)
5643                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5644
5645         return err;
5646 }
5647
5648 /* tp->lock is held. */
5649 static int tg3_nvram_lock(struct tg3 *tp)
5650 {
5651         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
5652                 int i;
5653
5654                 if (tp->nvram_lock_cnt == 0) {
5655                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
5656                         for (i = 0; i < 8000; i++) {
5657                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
5658                                         break;
5659                                 udelay(20);
5660                         }
5661                         if (i == 8000) {
5662                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
5663                                 return -ENODEV;
5664                         }
5665                 }
5666                 tp->nvram_lock_cnt++;
5667         }
5668         return 0;
5669 }
5670
5671 /* tp->lock is held. */
5672 static void tg3_nvram_unlock(struct tg3 *tp)
5673 {
5674         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
5675                 if (tp->nvram_lock_cnt > 0)
5676                         tp->nvram_lock_cnt--;
5677                 if (tp->nvram_lock_cnt == 0)
5678                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
5679         }
5680 }
5681
5682 /* tp->lock is held. */
5683 static void tg3_enable_nvram_access(struct tg3 *tp)
5684 {
5685         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5686             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5687                 u32 nvaccess = tr32(NVRAM_ACCESS);
5688
5689                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
5690         }
5691 }
5692
5693 /* tp->lock is held. */
5694 static void tg3_disable_nvram_access(struct tg3 *tp)
5695 {
5696         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5697             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5698                 u32 nvaccess = tr32(NVRAM_ACCESS);
5699
5700                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
5701         }
5702 }
5703
5704 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5705 {
5706         int i;
5707         u32 apedata;
5708
5709         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5710         if (apedata != APE_SEG_SIG_MAGIC)
5711                 return;
5712
5713         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
5714         if (!(apedata & APE_FW_STATUS_READY))
5715                 return;
5716
5717         /* Wait for up to 1 millisecond for APE to service previous event. */
5718         for (i = 0; i < 10; i++) {
5719                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5720                         return;
5721
5722                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5723
5724                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5725                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5726                                         event | APE_EVENT_STATUS_EVENT_PENDING);
5727
5728                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5729
5730                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5731                         break;
5732
5733                 udelay(100);
5734         }
5735
5736         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5737                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5738 }
5739
5740 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5741 {
5742         u32 event;
5743         u32 apedata;
5744
5745         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5746                 return;
5747
5748         switch (kind) {
5749                 case RESET_KIND_INIT:
5750                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5751                                         APE_HOST_SEG_SIG_MAGIC);
5752                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5753                                         APE_HOST_SEG_LEN_MAGIC);
5754                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5755                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5756                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
5757                                         APE_HOST_DRIVER_ID_MAGIC);
5758                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
5759                                         APE_HOST_BEHAV_NO_PHYLOCK);
5760
5761                         event = APE_EVENT_STATUS_STATE_START;
5762                         break;
5763                 case RESET_KIND_SHUTDOWN:
5764                         /* With the interface we are currently using,
5765                          * APE does not track driver state.  Wiping
5766                          * out the HOST SEGMENT SIGNATURE forces
5767                          * the APE to assume OS absent status.
5768