tg3 / broadcom: Add PHY_BRCM_CLEAR_RGMII_MODE flag
[linux-2.6.git] / drivers / net / tg3.c
1 /*
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  * Copyright (C) 2005-2009 Broadcom Corporation.
8  *
9  * Firmware is:
10  *      Derived from proprietary unpublished source code,
11  *      Copyright (C) 2000-2003 Broadcom Corporation.
12  *
13  *      Permission is hereby granted for the distribution of this firmware
14  *      data in hexadecimal or equivalent format, provided this copyright
15  *      notice is accompanying it.
16  */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
26 #include <linux/in.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/phy.h>
36 #include <linux/brcmphy.h>
37 #include <linux/if_vlan.h>
38 #include <linux/ip.h>
39 #include <linux/tcp.h>
40 #include <linux/workqueue.h>
41 #include <linux/prefetch.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/firmware.h>
44
45 #include <net/checksum.h>
46 #include <net/ip.h>
47
48 #include <asm/system.h>
49 #include <asm/io.h>
50 #include <asm/byteorder.h>
51 #include <asm/uaccess.h>
52
53 #ifdef CONFIG_SPARC
54 #include <asm/idprom.h>
55 #include <asm/prom.h>
56 #endif
57
58 #define BAR_0   0
59 #define BAR_2   2
60
61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62 #define TG3_VLAN_TAG_USED 1
63 #else
64 #define TG3_VLAN_TAG_USED 0
65 #endif
66
67 #include "tg3.h"
68
69 #define DRV_MODULE_NAME         "tg3"
70 #define PFX DRV_MODULE_NAME     ": "
71 #define DRV_MODULE_VERSION      "3.102"
72 #define DRV_MODULE_RELDATE      "September 1, 2009"
73
74 #define TG3_DEF_MAC_MODE        0
75 #define TG3_DEF_RX_MODE         0
76 #define TG3_DEF_TX_MODE         0
77 #define TG3_DEF_MSG_ENABLE        \
78         (NETIF_MSG_DRV          | \
79          NETIF_MSG_PROBE        | \
80          NETIF_MSG_LINK         | \
81          NETIF_MSG_TIMER        | \
82          NETIF_MSG_IFDOWN       | \
83          NETIF_MSG_IFUP         | \
84          NETIF_MSG_RX_ERR       | \
85          NETIF_MSG_TX_ERR)
86
87 /* length of time before we decide the hardware is borked,
88  * and dev->tx_timeout() should be called to fix the problem
89  */
90 #define TG3_TX_TIMEOUT                  (5 * HZ)
91
92 /* hardware minimum and maximum for a single frame's data payload */
93 #define TG3_MIN_MTU                     60
94 #define TG3_MAX_MTU(tp) \
95         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
96
97 /* These numbers seem to be hard coded in the NIC firmware somehow.
98  * You can't change the ring sizes, but you can change where you place
99  * them in the NIC onboard memory.
100  */
101 #define TG3_RX_RING_SIZE                512
102 #define TG3_DEF_RX_RING_PENDING         200
103 #define TG3_RX_JUMBO_RING_SIZE          256
104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
105 #define TG3_RSS_INDIR_TBL_SIZE 128
106
107 /* Do not place this n-ring entries value into the tp struct itself,
108  * we really want to expose these constants to GCC so that modulo et
109  * al.  operations are done with shifts and masks instead of with
110  * hw multiply/modulo instructions.  Another solution would be to
111  * replace things like '% foo' with '& (foo - 1)'.
112  */
113 #define TG3_RX_RCB_RING_SIZE(tp)        \
114         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
115           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
116
117 #define TG3_TX_RING_SIZE                512
118 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
119
120 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
121                                  TG3_RX_RING_SIZE)
122 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
123                                  TG3_RX_JUMBO_RING_SIZE)
124 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
125                                  TG3_RX_RCB_RING_SIZE(tp))
126 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
127                                  TG3_TX_RING_SIZE)
128 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
129
130 #define TG3_DMA_BYTE_ENAB               64
131
132 #define TG3_RX_STD_DMA_SZ               1536
133 #define TG3_RX_JMB_DMA_SZ               9046
134
135 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
136
137 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
138 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
139
140 /* minimum number of free TX descriptors required to wake up TX process */
141 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
142
143 #define TG3_RAW_IP_ALIGN 2
144
145 /* number of ETHTOOL_GSTATS u64's */
146 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
147
148 #define TG3_NUM_TEST            6
149
150 #define FIRMWARE_TG3            "tigon/tg3.bin"
151 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
152 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
153
154 static char version[] __devinitdata =
155         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
156
157 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
158 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
159 MODULE_LICENSE("GPL");
160 MODULE_VERSION(DRV_MODULE_VERSION);
161 MODULE_FIRMWARE(FIRMWARE_TG3);
162 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
163 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
164
165 #define TG3_RSS_MIN_NUM_MSIX_VECS       2
166
167 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
168 module_param(tg3_debug, int, 0);
169 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
170
171 static struct pci_device_id tg3_pci_tbl[] = {
172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
238         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
239         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
240         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
241         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
242         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
243         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
244         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
245         {}
246 };
247
248 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
249
250 static const struct {
251         const char string[ETH_GSTRING_LEN];
252 } ethtool_stats_keys[TG3_NUM_STATS] = {
253         { "rx_octets" },
254         { "rx_fragments" },
255         { "rx_ucast_packets" },
256         { "rx_mcast_packets" },
257         { "rx_bcast_packets" },
258         { "rx_fcs_errors" },
259         { "rx_align_errors" },
260         { "rx_xon_pause_rcvd" },
261         { "rx_xoff_pause_rcvd" },
262         { "rx_mac_ctrl_rcvd" },
263         { "rx_xoff_entered" },
264         { "rx_frame_too_long_errors" },
265         { "rx_jabbers" },
266         { "rx_undersize_packets" },
267         { "rx_in_length_errors" },
268         { "rx_out_length_errors" },
269         { "rx_64_or_less_octet_packets" },
270         { "rx_65_to_127_octet_packets" },
271         { "rx_128_to_255_octet_packets" },
272         { "rx_256_to_511_octet_packets" },
273         { "rx_512_to_1023_octet_packets" },
274         { "rx_1024_to_1522_octet_packets" },
275         { "rx_1523_to_2047_octet_packets" },
276         { "rx_2048_to_4095_octet_packets" },
277         { "rx_4096_to_8191_octet_packets" },
278         { "rx_8192_to_9022_octet_packets" },
279
280         { "tx_octets" },
281         { "tx_collisions" },
282
283         { "tx_xon_sent" },
284         { "tx_xoff_sent" },
285         { "tx_flow_control" },
286         { "tx_mac_errors" },
287         { "tx_single_collisions" },
288         { "tx_mult_collisions" },
289         { "tx_deferred" },
290         { "tx_excessive_collisions" },
291         { "tx_late_collisions" },
292         { "tx_collide_2times" },
293         { "tx_collide_3times" },
294         { "tx_collide_4times" },
295         { "tx_collide_5times" },
296         { "tx_collide_6times" },
297         { "tx_collide_7times" },
298         { "tx_collide_8times" },
299         { "tx_collide_9times" },
300         { "tx_collide_10times" },
301         { "tx_collide_11times" },
302         { "tx_collide_12times" },
303         { "tx_collide_13times" },
304         { "tx_collide_14times" },
305         { "tx_collide_15times" },
306         { "tx_ucast_packets" },
307         { "tx_mcast_packets" },
308         { "tx_bcast_packets" },
309         { "tx_carrier_sense_errors" },
310         { "tx_discards" },
311         { "tx_errors" },
312
313         { "dma_writeq_full" },
314         { "dma_write_prioq_full" },
315         { "rxbds_empty" },
316         { "rx_discards" },
317         { "rx_errors" },
318         { "rx_threshold_hit" },
319
320         { "dma_readq_full" },
321         { "dma_read_prioq_full" },
322         { "tx_comp_queue_full" },
323
324         { "ring_set_send_prod_index" },
325         { "ring_status_update" },
326         { "nic_irqs" },
327         { "nic_avoided_irqs" },
328         { "nic_tx_threshold_hit" }
329 };
330
331 static const struct {
332         const char string[ETH_GSTRING_LEN];
333 } ethtool_test_keys[TG3_NUM_TEST] = {
334         { "nvram test     (online) " },
335         { "link test      (online) " },
336         { "register test  (offline)" },
337         { "memory test    (offline)" },
338         { "loopback test  (offline)" },
339         { "interrupt test (offline)" },
340 };
341
342 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
343 {
344         writel(val, tp->regs + off);
345 }
346
347 static u32 tg3_read32(struct tg3 *tp, u32 off)
348 {
349         return (readl(tp->regs + off));
350 }
351
352 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
353 {
354         writel(val, tp->aperegs + off);
355 }
356
357 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
358 {
359         return (readl(tp->aperegs + off));
360 }
361
362 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
363 {
364         unsigned long flags;
365
366         spin_lock_irqsave(&tp->indirect_lock, flags);
367         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
368         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
369         spin_unlock_irqrestore(&tp->indirect_lock, flags);
370 }
371
372 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
373 {
374         writel(val, tp->regs + off);
375         readl(tp->regs + off);
376 }
377
378 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
379 {
380         unsigned long flags;
381         u32 val;
382
383         spin_lock_irqsave(&tp->indirect_lock, flags);
384         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
385         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
386         spin_unlock_irqrestore(&tp->indirect_lock, flags);
387         return val;
388 }
389
390 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
391 {
392         unsigned long flags;
393
394         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
395                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
396                                        TG3_64BIT_REG_LOW, val);
397                 return;
398         }
399         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
400                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
401                                        TG3_64BIT_REG_LOW, val);
402                 return;
403         }
404
405         spin_lock_irqsave(&tp->indirect_lock, flags);
406         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
407         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
408         spin_unlock_irqrestore(&tp->indirect_lock, flags);
409
410         /* In indirect mode when disabling interrupts, we also need
411          * to clear the interrupt bit in the GRC local ctrl register.
412          */
413         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
414             (val == 0x1)) {
415                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
416                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
417         }
418 }
419
420 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
421 {
422         unsigned long flags;
423         u32 val;
424
425         spin_lock_irqsave(&tp->indirect_lock, flags);
426         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
427         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
428         spin_unlock_irqrestore(&tp->indirect_lock, flags);
429         return val;
430 }
431
432 /* usec_wait specifies the wait time in usec when writing to certain registers
433  * where it is unsafe to read back the register without some delay.
434  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
435  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
436  */
437 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
438 {
439         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
440             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
441                 /* Non-posted methods */
442                 tp->write32(tp, off, val);
443         else {
444                 /* Posted method */
445                 tg3_write32(tp, off, val);
446                 if (usec_wait)
447                         udelay(usec_wait);
448                 tp->read32(tp, off);
449         }
450         /* Wait again after the read for the posted method to guarantee that
451          * the wait time is met.
452          */
453         if (usec_wait)
454                 udelay(usec_wait);
455 }
456
457 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
458 {
459         tp->write32_mbox(tp, off, val);
460         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
461             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
462                 tp->read32_mbox(tp, off);
463 }
464
465 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
466 {
467         void __iomem *mbox = tp->regs + off;
468         writel(val, mbox);
469         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
470                 writel(val, mbox);
471         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
472                 readl(mbox);
473 }
474
475 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
476 {
477         return (readl(tp->regs + off + GRCMBOX_BASE));
478 }
479
480 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
481 {
482         writel(val, tp->regs + off + GRCMBOX_BASE);
483 }
484
485 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
486 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
487 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
488 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
489 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
490
491 #define tw32(reg,val)           tp->write32(tp, reg, val)
492 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
493 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
494 #define tr32(reg)               tp->read32(tp, reg)
495
496 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
497 {
498         unsigned long flags;
499
500         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
501             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
502                 return;
503
504         spin_lock_irqsave(&tp->indirect_lock, flags);
505         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
506                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
507                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
508
509                 /* Always leave this as zero. */
510                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
511         } else {
512                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
513                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
514
515                 /* Always leave this as zero. */
516                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
517         }
518         spin_unlock_irqrestore(&tp->indirect_lock, flags);
519 }
520
521 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
522 {
523         unsigned long flags;
524
525         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
526             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
527                 *val = 0;
528                 return;
529         }
530
531         spin_lock_irqsave(&tp->indirect_lock, flags);
532         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
533                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
534                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
535
536                 /* Always leave this as zero. */
537                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
538         } else {
539                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
540                 *val = tr32(TG3PCI_MEM_WIN_DATA);
541
542                 /* Always leave this as zero. */
543                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
544         }
545         spin_unlock_irqrestore(&tp->indirect_lock, flags);
546 }
547
548 static void tg3_ape_lock_init(struct tg3 *tp)
549 {
550         int i;
551
552         /* Make sure the driver hasn't any stale locks. */
553         for (i = 0; i < 8; i++)
554                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
555                                 APE_LOCK_GRANT_DRIVER);
556 }
557
558 static int tg3_ape_lock(struct tg3 *tp, int locknum)
559 {
560         int i, off;
561         int ret = 0;
562         u32 status;
563
564         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
565                 return 0;
566
567         switch (locknum) {
568                 case TG3_APE_LOCK_GRC:
569                 case TG3_APE_LOCK_MEM:
570                         break;
571                 default:
572                         return -EINVAL;
573         }
574
575         off = 4 * locknum;
576
577         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
578
579         /* Wait for up to 1 millisecond to acquire lock. */
580         for (i = 0; i < 100; i++) {
581                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
582                 if (status == APE_LOCK_GRANT_DRIVER)
583                         break;
584                 udelay(10);
585         }
586
587         if (status != APE_LOCK_GRANT_DRIVER) {
588                 /* Revoke the lock request. */
589                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
590                                 APE_LOCK_GRANT_DRIVER);
591
592                 ret = -EBUSY;
593         }
594
595         return ret;
596 }
597
598 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
599 {
600         int off;
601
602         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
603                 return;
604
605         switch (locknum) {
606                 case TG3_APE_LOCK_GRC:
607                 case TG3_APE_LOCK_MEM:
608                         break;
609                 default:
610                         return;
611         }
612
613         off = 4 * locknum;
614         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
615 }
616
617 static void tg3_disable_ints(struct tg3 *tp)
618 {
619         int i;
620
621         tw32(TG3PCI_MISC_HOST_CTRL,
622              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
623         for (i = 0; i < tp->irq_max; i++)
624                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
625 }
626
627 static void tg3_enable_ints(struct tg3 *tp)
628 {
629         int i;
630         u32 coal_now = 0;
631
632         tp->irq_sync = 0;
633         wmb();
634
635         tw32(TG3PCI_MISC_HOST_CTRL,
636              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
637
638         for (i = 0; i < tp->irq_cnt; i++) {
639                 struct tg3_napi *tnapi = &tp->napi[i];
640                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
641                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
642                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
643
644                 coal_now |= tnapi->coal_now;
645         }
646
647         /* Force an initial interrupt */
648         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
649             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
650                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
651         else
652                 tw32(HOSTCC_MODE, tp->coalesce_mode |
653                      HOSTCC_MODE_ENABLE | coal_now);
654 }
655
656 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
657 {
658         struct tg3 *tp = tnapi->tp;
659         struct tg3_hw_status *sblk = tnapi->hw_status;
660         unsigned int work_exists = 0;
661
662         /* check for phy events */
663         if (!(tp->tg3_flags &
664               (TG3_FLAG_USE_LINKCHG_REG |
665                TG3_FLAG_POLL_SERDES))) {
666                 if (sblk->status & SD_STATUS_LINK_CHG)
667                         work_exists = 1;
668         }
669         /* check for RX/TX work to do */
670         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
671             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
672                 work_exists = 1;
673
674         return work_exists;
675 }
676
677 /* tg3_int_reenable
678  *  similar to tg3_enable_ints, but it accurately determines whether there
679  *  is new work pending and can return without flushing the PIO write
680  *  which reenables interrupts
681  */
682 static void tg3_int_reenable(struct tg3_napi *tnapi)
683 {
684         struct tg3 *tp = tnapi->tp;
685
686         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
687         mmiowb();
688
689         /* When doing tagged status, this work check is unnecessary.
690          * The last_tag we write above tells the chip which piece of
691          * work we've completed.
692          */
693         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
694             tg3_has_work(tnapi))
695                 tw32(HOSTCC_MODE, tp->coalesce_mode |
696                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
697 }
698
699 static void tg3_napi_disable(struct tg3 *tp)
700 {
701         int i;
702
703         for (i = tp->irq_cnt - 1; i >= 0; i--)
704                 napi_disable(&tp->napi[i].napi);
705 }
706
707 static void tg3_napi_enable(struct tg3 *tp)
708 {
709         int i;
710
711         for (i = 0; i < tp->irq_cnt; i++)
712                 napi_enable(&tp->napi[i].napi);
713 }
714
715 static inline void tg3_netif_stop(struct tg3 *tp)
716 {
717         tp->dev->trans_start = jiffies; /* prevent tx timeout */
718         tg3_napi_disable(tp);
719         netif_tx_disable(tp->dev);
720 }
721
722 static inline void tg3_netif_start(struct tg3 *tp)
723 {
724         /* NOTE: unconditional netif_tx_wake_all_queues is only
725          * appropriate so long as all callers are assured to
726          * have free tx slots (such as after tg3_init_hw)
727          */
728         netif_tx_wake_all_queues(tp->dev);
729
730         tg3_napi_enable(tp);
731         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
732         tg3_enable_ints(tp);
733 }
734
735 static void tg3_switch_clocks(struct tg3 *tp)
736 {
737         u32 clock_ctrl;
738         u32 orig_clock_ctrl;
739
740         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
741             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
742                 return;
743
744         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
745
746         orig_clock_ctrl = clock_ctrl;
747         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
748                        CLOCK_CTRL_CLKRUN_OENABLE |
749                        0x1f);
750         tp->pci_clock_ctrl = clock_ctrl;
751
752         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
753                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
754                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
755                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
756                 }
757         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
758                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
759                             clock_ctrl |
760                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
761                             40);
762                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
763                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
764                             40);
765         }
766         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
767 }
768
769 #define PHY_BUSY_LOOPS  5000
770
771 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
772 {
773         u32 frame_val;
774         unsigned int loops;
775         int ret;
776
777         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
778                 tw32_f(MAC_MI_MODE,
779                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
780                 udelay(80);
781         }
782
783         *val = 0x0;
784
785         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
786                       MI_COM_PHY_ADDR_MASK);
787         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
788                       MI_COM_REG_ADDR_MASK);
789         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
790
791         tw32_f(MAC_MI_COM, frame_val);
792
793         loops = PHY_BUSY_LOOPS;
794         while (loops != 0) {
795                 udelay(10);
796                 frame_val = tr32(MAC_MI_COM);
797
798                 if ((frame_val & MI_COM_BUSY) == 0) {
799                         udelay(5);
800                         frame_val = tr32(MAC_MI_COM);
801                         break;
802                 }
803                 loops -= 1;
804         }
805
806         ret = -EBUSY;
807         if (loops != 0) {
808                 *val = frame_val & MI_COM_DATA_MASK;
809                 ret = 0;
810         }
811
812         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
813                 tw32_f(MAC_MI_MODE, tp->mi_mode);
814                 udelay(80);
815         }
816
817         return ret;
818 }
819
820 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
821 {
822         u32 frame_val;
823         unsigned int loops;
824         int ret;
825
826         if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
827             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
828                 return 0;
829
830         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
831                 tw32_f(MAC_MI_MODE,
832                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
833                 udelay(80);
834         }
835
836         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
837                       MI_COM_PHY_ADDR_MASK);
838         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
839                       MI_COM_REG_ADDR_MASK);
840         frame_val |= (val & MI_COM_DATA_MASK);
841         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
842
843         tw32_f(MAC_MI_COM, frame_val);
844
845         loops = PHY_BUSY_LOOPS;
846         while (loops != 0) {
847                 udelay(10);
848                 frame_val = tr32(MAC_MI_COM);
849                 if ((frame_val & MI_COM_BUSY) == 0) {
850                         udelay(5);
851                         frame_val = tr32(MAC_MI_COM);
852                         break;
853                 }
854                 loops -= 1;
855         }
856
857         ret = -EBUSY;
858         if (loops != 0)
859                 ret = 0;
860
861         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
862                 tw32_f(MAC_MI_MODE, tp->mi_mode);
863                 udelay(80);
864         }
865
866         return ret;
867 }
868
869 static int tg3_bmcr_reset(struct tg3 *tp)
870 {
871         u32 phy_control;
872         int limit, err;
873
874         /* OK, reset it, and poll the BMCR_RESET bit until it
875          * clears or we time out.
876          */
877         phy_control = BMCR_RESET;
878         err = tg3_writephy(tp, MII_BMCR, phy_control);
879         if (err != 0)
880                 return -EBUSY;
881
882         limit = 5000;
883         while (limit--) {
884                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
885                 if (err != 0)
886                         return -EBUSY;
887
888                 if ((phy_control & BMCR_RESET) == 0) {
889                         udelay(40);
890                         break;
891                 }
892                 udelay(10);
893         }
894         if (limit < 0)
895                 return -EBUSY;
896
897         return 0;
898 }
899
900 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
901 {
902         struct tg3 *tp = bp->priv;
903         u32 val;
904
905         spin_lock_bh(&tp->lock);
906
907         if (tg3_readphy(tp, reg, &val))
908                 val = -EIO;
909
910         spin_unlock_bh(&tp->lock);
911
912         return val;
913 }
914
915 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
916 {
917         struct tg3 *tp = bp->priv;
918         u32 ret = 0;
919
920         spin_lock_bh(&tp->lock);
921
922         if (tg3_writephy(tp, reg, val))
923                 ret = -EIO;
924
925         spin_unlock_bh(&tp->lock);
926
927         return ret;
928 }
929
930 static int tg3_mdio_reset(struct mii_bus *bp)
931 {
932         return 0;
933 }
934
935 static void tg3_mdio_config_5785(struct tg3 *tp)
936 {
937         u32 val;
938         struct phy_device *phydev;
939
940         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
941         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
942         case TG3_PHY_ID_BCM50610:
943         case TG3_PHY_ID_BCM50610M:
944                 val = MAC_PHYCFG2_50610_LED_MODES;
945                 break;
946         case TG3_PHY_ID_BCMAC131:
947                 val = MAC_PHYCFG2_AC131_LED_MODES;
948                 break;
949         case TG3_PHY_ID_RTL8211C:
950                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
951                 break;
952         case TG3_PHY_ID_RTL8201E:
953                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
954                 break;
955         default:
956                 return;
957         }
958
959         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
960                 tw32(MAC_PHYCFG2, val);
961
962                 val = tr32(MAC_PHYCFG1);
963                 val &= ~(MAC_PHYCFG1_RGMII_INT |
964                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
965                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
966                 tw32(MAC_PHYCFG1, val);
967
968                 return;
969         }
970
971         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
972                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
973                        MAC_PHYCFG2_FMODE_MASK_MASK |
974                        MAC_PHYCFG2_GMODE_MASK_MASK |
975                        MAC_PHYCFG2_ACT_MASK_MASK   |
976                        MAC_PHYCFG2_QUAL_MASK_MASK |
977                        MAC_PHYCFG2_INBAND_ENABLE;
978
979         tw32(MAC_PHYCFG2, val);
980
981         val = tr32(MAC_PHYCFG1);
982         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
983                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
984         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
985                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
986                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
987                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
988                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
989         }
990         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
991                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
992         tw32(MAC_PHYCFG1, val);
993
994         val = tr32(MAC_EXT_RGMII_MODE);
995         val &= ~(MAC_RGMII_MODE_RX_INT_B |
996                  MAC_RGMII_MODE_RX_QUALITY |
997                  MAC_RGMII_MODE_RX_ACTIVITY |
998                  MAC_RGMII_MODE_RX_ENG_DET |
999                  MAC_RGMII_MODE_TX_ENABLE |
1000                  MAC_RGMII_MODE_TX_LOWPWR |
1001                  MAC_RGMII_MODE_TX_RESET);
1002         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
1003                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1004                         val |= MAC_RGMII_MODE_RX_INT_B |
1005                                MAC_RGMII_MODE_RX_QUALITY |
1006                                MAC_RGMII_MODE_RX_ACTIVITY |
1007                                MAC_RGMII_MODE_RX_ENG_DET;
1008                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1009                         val |= MAC_RGMII_MODE_TX_ENABLE |
1010                                MAC_RGMII_MODE_TX_LOWPWR |
1011                                MAC_RGMII_MODE_TX_RESET;
1012         }
1013         tw32(MAC_EXT_RGMII_MODE, val);
1014 }
1015
1016 static void tg3_mdio_start(struct tg3 *tp)
1017 {
1018         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1019         tw32_f(MAC_MI_MODE, tp->mi_mode);
1020         udelay(80);
1021
1022         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1023                 u32 funcnum, is_serdes;
1024
1025                 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1026                 if (funcnum)
1027                         tp->phy_addr = 2;
1028                 else
1029                         tp->phy_addr = 1;
1030
1031                 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1032                 if (is_serdes)
1033                         tp->phy_addr += 7;
1034         } else
1035                 tp->phy_addr = TG3_PHY_MII_ADDR;
1036
1037         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1038             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1039                 tg3_mdio_config_5785(tp);
1040 }
1041
1042 static int tg3_mdio_init(struct tg3 *tp)
1043 {
1044         int i;
1045         u32 reg;
1046         struct phy_device *phydev;
1047
1048         tg3_mdio_start(tp);
1049
1050         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1051             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1052                 return 0;
1053
1054         tp->mdio_bus = mdiobus_alloc();
1055         if (tp->mdio_bus == NULL)
1056                 return -ENOMEM;
1057
1058         tp->mdio_bus->name     = "tg3 mdio bus";
1059         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1060                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1061         tp->mdio_bus->priv     = tp;
1062         tp->mdio_bus->parent   = &tp->pdev->dev;
1063         tp->mdio_bus->read     = &tg3_mdio_read;
1064         tp->mdio_bus->write    = &tg3_mdio_write;
1065         tp->mdio_bus->reset    = &tg3_mdio_reset;
1066         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1067         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1068
1069         for (i = 0; i < PHY_MAX_ADDR; i++)
1070                 tp->mdio_bus->irq[i] = PHY_POLL;
1071
1072         /* The bus registration will look for all the PHYs on the mdio bus.
1073          * Unfortunately, it does not ensure the PHY is powered up before
1074          * accessing the PHY ID registers.  A chip reset is the
1075          * quickest way to bring the device back to an operational state..
1076          */
1077         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1078                 tg3_bmcr_reset(tp);
1079
1080         i = mdiobus_register(tp->mdio_bus);
1081         if (i) {
1082                 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1083                         tp->dev->name, i);
1084                 mdiobus_free(tp->mdio_bus);
1085                 return i;
1086         }
1087
1088         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1089
1090         if (!phydev || !phydev->drv) {
1091                 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1092                 mdiobus_unregister(tp->mdio_bus);
1093                 mdiobus_free(tp->mdio_bus);
1094                 return -ENODEV;
1095         }
1096
1097         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1098         case TG3_PHY_ID_BCM57780:
1099                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1100                 break;
1101         case TG3_PHY_ID_BCM50610:
1102         case TG3_PHY_ID_BCM50610M:
1103                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE;
1104                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1105                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1106                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1107                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1108                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1109                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1110                 /* fallthru */
1111         case TG3_PHY_ID_RTL8211C:
1112                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1113                 break;
1114         case TG3_PHY_ID_RTL8201E:
1115         case TG3_PHY_ID_BCMAC131:
1116                 phydev->interface = PHY_INTERFACE_MODE_MII;
1117                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1118                 break;
1119         }
1120
1121         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1122
1123         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1124                 tg3_mdio_config_5785(tp);
1125
1126         return 0;
1127 }
1128
1129 static void tg3_mdio_fini(struct tg3 *tp)
1130 {
1131         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1132                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1133                 mdiobus_unregister(tp->mdio_bus);
1134                 mdiobus_free(tp->mdio_bus);
1135         }
1136 }
1137
1138 /* tp->lock is held. */
1139 static inline void tg3_generate_fw_event(struct tg3 *tp)
1140 {
1141         u32 val;
1142
1143         val = tr32(GRC_RX_CPU_EVENT);
1144         val |= GRC_RX_CPU_DRIVER_EVENT;
1145         tw32_f(GRC_RX_CPU_EVENT, val);
1146
1147         tp->last_event_jiffies = jiffies;
1148 }
1149
1150 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1151
1152 /* tp->lock is held. */
1153 static void tg3_wait_for_event_ack(struct tg3 *tp)
1154 {
1155         int i;
1156         unsigned int delay_cnt;
1157         long time_remain;
1158
1159         /* If enough time has passed, no wait is necessary. */
1160         time_remain = (long)(tp->last_event_jiffies + 1 +
1161                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1162                       (long)jiffies;
1163         if (time_remain < 0)
1164                 return;
1165
1166         /* Check if we can shorten the wait time. */
1167         delay_cnt = jiffies_to_usecs(time_remain);
1168         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1169                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1170         delay_cnt = (delay_cnt >> 3) + 1;
1171
1172         for (i = 0; i < delay_cnt; i++) {
1173                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1174                         break;
1175                 udelay(8);
1176         }
1177 }
1178
1179 /* tp->lock is held. */
1180 static void tg3_ump_link_report(struct tg3 *tp)
1181 {
1182         u32 reg;
1183         u32 val;
1184
1185         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1186             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1187                 return;
1188
1189         tg3_wait_for_event_ack(tp);
1190
1191         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1192
1193         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1194
1195         val = 0;
1196         if (!tg3_readphy(tp, MII_BMCR, &reg))
1197                 val = reg << 16;
1198         if (!tg3_readphy(tp, MII_BMSR, &reg))
1199                 val |= (reg & 0xffff);
1200         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1201
1202         val = 0;
1203         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1204                 val = reg << 16;
1205         if (!tg3_readphy(tp, MII_LPA, &reg))
1206                 val |= (reg & 0xffff);
1207         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1208
1209         val = 0;
1210         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1211                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1212                         val = reg << 16;
1213                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1214                         val |= (reg & 0xffff);
1215         }
1216         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1217
1218         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1219                 val = reg << 16;
1220         else
1221                 val = 0;
1222         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1223
1224         tg3_generate_fw_event(tp);
1225 }
1226
1227 static void tg3_link_report(struct tg3 *tp)
1228 {
1229         if (!netif_carrier_ok(tp->dev)) {
1230                 if (netif_msg_link(tp))
1231                         printk(KERN_INFO PFX "%s: Link is down.\n",
1232                                tp->dev->name);
1233                 tg3_ump_link_report(tp);
1234         } else if (netif_msg_link(tp)) {
1235                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1236                        tp->dev->name,
1237                        (tp->link_config.active_speed == SPEED_1000 ?
1238                         1000 :
1239                         (tp->link_config.active_speed == SPEED_100 ?
1240                          100 : 10)),
1241                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1242                         "full" : "half"));
1243
1244                 printk(KERN_INFO PFX
1245                        "%s: Flow control is %s for TX and %s for RX.\n",
1246                        tp->dev->name,
1247                        (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1248                        "on" : "off",
1249                        (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1250                        "on" : "off");
1251                 tg3_ump_link_report(tp);
1252         }
1253 }
1254
1255 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1256 {
1257         u16 miireg;
1258
1259         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1260                 miireg = ADVERTISE_PAUSE_CAP;
1261         else if (flow_ctrl & FLOW_CTRL_TX)
1262                 miireg = ADVERTISE_PAUSE_ASYM;
1263         else if (flow_ctrl & FLOW_CTRL_RX)
1264                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1265         else
1266                 miireg = 0;
1267
1268         return miireg;
1269 }
1270
1271 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1272 {
1273         u16 miireg;
1274
1275         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1276                 miireg = ADVERTISE_1000XPAUSE;
1277         else if (flow_ctrl & FLOW_CTRL_TX)
1278                 miireg = ADVERTISE_1000XPSE_ASYM;
1279         else if (flow_ctrl & FLOW_CTRL_RX)
1280                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1281         else
1282                 miireg = 0;
1283
1284         return miireg;
1285 }
1286
1287 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1288 {
1289         u8 cap = 0;
1290
1291         if (lcladv & ADVERTISE_1000XPAUSE) {
1292                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1293                         if (rmtadv & LPA_1000XPAUSE)
1294                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1295                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1296                                 cap = FLOW_CTRL_RX;
1297                 } else {
1298                         if (rmtadv & LPA_1000XPAUSE)
1299                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1300                 }
1301         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1302                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1303                         cap = FLOW_CTRL_TX;
1304         }
1305
1306         return cap;
1307 }
1308
1309 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1310 {
1311         u8 autoneg;
1312         u8 flowctrl = 0;
1313         u32 old_rx_mode = tp->rx_mode;
1314         u32 old_tx_mode = tp->tx_mode;
1315
1316         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1317                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1318         else
1319                 autoneg = tp->link_config.autoneg;
1320
1321         if (autoneg == AUTONEG_ENABLE &&
1322             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1323                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1324                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1325                 else
1326                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1327         } else
1328                 flowctrl = tp->link_config.flowctrl;
1329
1330         tp->link_config.active_flowctrl = flowctrl;
1331
1332         if (flowctrl & FLOW_CTRL_RX)
1333                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1334         else
1335                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1336
1337         if (old_rx_mode != tp->rx_mode)
1338                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1339
1340         if (flowctrl & FLOW_CTRL_TX)
1341                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1342         else
1343                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1344
1345         if (old_tx_mode != tp->tx_mode)
1346                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1347 }
1348
1349 static void tg3_adjust_link(struct net_device *dev)
1350 {
1351         u8 oldflowctrl, linkmesg = 0;
1352         u32 mac_mode, lcl_adv, rmt_adv;
1353         struct tg3 *tp = netdev_priv(dev);
1354         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1355
1356         spin_lock_bh(&tp->lock);
1357
1358         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1359                                     MAC_MODE_HALF_DUPLEX);
1360
1361         oldflowctrl = tp->link_config.active_flowctrl;
1362
1363         if (phydev->link) {
1364                 lcl_adv = 0;
1365                 rmt_adv = 0;
1366
1367                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1368                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1369                 else if (phydev->speed == SPEED_1000 ||
1370                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1371                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1372                 else
1373                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1374
1375                 if (phydev->duplex == DUPLEX_HALF)
1376                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1377                 else {
1378                         lcl_adv = tg3_advert_flowctrl_1000T(
1379                                   tp->link_config.flowctrl);
1380
1381                         if (phydev->pause)
1382                                 rmt_adv = LPA_PAUSE_CAP;
1383                         if (phydev->asym_pause)
1384                                 rmt_adv |= LPA_PAUSE_ASYM;
1385                 }
1386
1387                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1388         } else
1389                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1390
1391         if (mac_mode != tp->mac_mode) {
1392                 tp->mac_mode = mac_mode;
1393                 tw32_f(MAC_MODE, tp->mac_mode);
1394                 udelay(40);
1395         }
1396
1397         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1398                 if (phydev->speed == SPEED_10)
1399                         tw32(MAC_MI_STAT,
1400                              MAC_MI_STAT_10MBPS_MODE |
1401                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1402                 else
1403                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1404         }
1405
1406         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1407                 tw32(MAC_TX_LENGTHS,
1408                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1409                       (6 << TX_LENGTHS_IPG_SHIFT) |
1410                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1411         else
1412                 tw32(MAC_TX_LENGTHS,
1413                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1414                       (6 << TX_LENGTHS_IPG_SHIFT) |
1415                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1416
1417         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1418             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1419             phydev->speed != tp->link_config.active_speed ||
1420             phydev->duplex != tp->link_config.active_duplex ||
1421             oldflowctrl != tp->link_config.active_flowctrl)
1422             linkmesg = 1;
1423
1424         tp->link_config.active_speed = phydev->speed;
1425         tp->link_config.active_duplex = phydev->duplex;
1426
1427         spin_unlock_bh(&tp->lock);
1428
1429         if (linkmesg)
1430                 tg3_link_report(tp);
1431 }
1432
1433 static int tg3_phy_init(struct tg3 *tp)
1434 {
1435         struct phy_device *phydev;
1436
1437         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1438                 return 0;
1439
1440         /* Bring the PHY back to a known state. */
1441         tg3_bmcr_reset(tp);
1442
1443         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1444
1445         /* Attach the MAC to the PHY. */
1446         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1447                              phydev->dev_flags, phydev->interface);
1448         if (IS_ERR(phydev)) {
1449                 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1450                 return PTR_ERR(phydev);
1451         }
1452
1453         /* Mask with MAC supported features. */
1454         switch (phydev->interface) {
1455         case PHY_INTERFACE_MODE_GMII:
1456         case PHY_INTERFACE_MODE_RGMII:
1457                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1458                         phydev->supported &= (PHY_GBIT_FEATURES |
1459                                               SUPPORTED_Pause |
1460                                               SUPPORTED_Asym_Pause);
1461                         break;
1462                 }
1463                 /* fallthru */
1464         case PHY_INTERFACE_MODE_MII:
1465                 phydev->supported &= (PHY_BASIC_FEATURES |
1466                                       SUPPORTED_Pause |
1467                                       SUPPORTED_Asym_Pause);
1468                 break;
1469         default:
1470                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1471                 return -EINVAL;
1472         }
1473
1474         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1475
1476         phydev->advertising = phydev->supported;
1477
1478         return 0;
1479 }
1480
1481 static void tg3_phy_start(struct tg3 *tp)
1482 {
1483         struct phy_device *phydev;
1484
1485         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1486                 return;
1487
1488         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1489
1490         if (tp->link_config.phy_is_low_power) {
1491                 tp->link_config.phy_is_low_power = 0;
1492                 phydev->speed = tp->link_config.orig_speed;
1493                 phydev->duplex = tp->link_config.orig_duplex;
1494                 phydev->autoneg = tp->link_config.orig_autoneg;
1495                 phydev->advertising = tp->link_config.orig_advertising;
1496         }
1497
1498         phy_start(phydev);
1499
1500         phy_start_aneg(phydev);
1501 }
1502
1503 static void tg3_phy_stop(struct tg3 *tp)
1504 {
1505         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1506                 return;
1507
1508         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1509 }
1510
1511 static void tg3_phy_fini(struct tg3 *tp)
1512 {
1513         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1514                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1515                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1516         }
1517 }
1518
1519 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1520 {
1521         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1522         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1523 }
1524
1525 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1526 {
1527         u32 phytest;
1528
1529         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1530                 u32 phy;
1531
1532                 tg3_writephy(tp, MII_TG3_FET_TEST,
1533                              phytest | MII_TG3_FET_SHADOW_EN);
1534                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1535                         if (enable)
1536                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1537                         else
1538                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1539                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1540                 }
1541                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1542         }
1543 }
1544
1545 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1546 {
1547         u32 reg;
1548
1549         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1550                 return;
1551
1552         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1553                 tg3_phy_fet_toggle_apd(tp, enable);
1554                 return;
1555         }
1556
1557         reg = MII_TG3_MISC_SHDW_WREN |
1558               MII_TG3_MISC_SHDW_SCR5_SEL |
1559               MII_TG3_MISC_SHDW_SCR5_LPED |
1560               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1561               MII_TG3_MISC_SHDW_SCR5_SDTL |
1562               MII_TG3_MISC_SHDW_SCR5_C125OE;
1563         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1564                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1565
1566         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1567
1568
1569         reg = MII_TG3_MISC_SHDW_WREN |
1570               MII_TG3_MISC_SHDW_APD_SEL |
1571               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1572         if (enable)
1573                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1574
1575         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1576 }
1577
1578 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1579 {
1580         u32 phy;
1581
1582         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1583             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1584                 return;
1585
1586         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1587                 u32 ephy;
1588
1589                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1590                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1591
1592                         tg3_writephy(tp, MII_TG3_FET_TEST,
1593                                      ephy | MII_TG3_FET_SHADOW_EN);
1594                         if (!tg3_readphy(tp, reg, &phy)) {
1595                                 if (enable)
1596                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1597                                 else
1598                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1599                                 tg3_writephy(tp, reg, phy);
1600                         }
1601                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1602                 }
1603         } else {
1604                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1605                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1606                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1607                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1608                         if (enable)
1609                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1610                         else
1611                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1612                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1613                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1614                 }
1615         }
1616 }
1617
1618 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1619 {
1620         u32 val;
1621
1622         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1623                 return;
1624
1625         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1626             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1627                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1628                              (val | (1 << 15) | (1 << 4)));
1629 }
1630
1631 static void tg3_phy_apply_otp(struct tg3 *tp)
1632 {
1633         u32 otp, phy;
1634
1635         if (!tp->phy_otp)
1636                 return;
1637
1638         otp = tp->phy_otp;
1639
1640         /* Enable SM_DSP clock and tx 6dB coding. */
1641         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1642               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1643               MII_TG3_AUXCTL_ACTL_TX_6DB;
1644         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1645
1646         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1647         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1648         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1649
1650         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1651               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1652         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1653
1654         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1655         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1656         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1657
1658         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1659         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1660
1661         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1662         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1663
1664         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1665               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1666         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1667
1668         /* Turn off SM_DSP clock. */
1669         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1670               MII_TG3_AUXCTL_ACTL_TX_6DB;
1671         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1672 }
1673
1674 static int tg3_wait_macro_done(struct tg3 *tp)
1675 {
1676         int limit = 100;
1677
1678         while (limit--) {
1679                 u32 tmp32;
1680
1681                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1682                         if ((tmp32 & 0x1000) == 0)
1683                                 break;
1684                 }
1685         }
1686         if (limit < 0)
1687                 return -EBUSY;
1688
1689         return 0;
1690 }
1691
1692 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1693 {
1694         static const u32 test_pat[4][6] = {
1695         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1696         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1697         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1698         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1699         };
1700         int chan;
1701
1702         for (chan = 0; chan < 4; chan++) {
1703                 int i;
1704
1705                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1706                              (chan * 0x2000) | 0x0200);
1707                 tg3_writephy(tp, 0x16, 0x0002);
1708
1709                 for (i = 0; i < 6; i++)
1710                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1711                                      test_pat[chan][i]);
1712
1713                 tg3_writephy(tp, 0x16, 0x0202);
1714                 if (tg3_wait_macro_done(tp)) {
1715                         *resetp = 1;
1716                         return -EBUSY;
1717                 }
1718
1719                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1720                              (chan * 0x2000) | 0x0200);
1721                 tg3_writephy(tp, 0x16, 0x0082);
1722                 if (tg3_wait_macro_done(tp)) {
1723                         *resetp = 1;
1724                         return -EBUSY;
1725                 }
1726
1727                 tg3_writephy(tp, 0x16, 0x0802);
1728                 if (tg3_wait_macro_done(tp)) {
1729                         *resetp = 1;
1730                         return -EBUSY;
1731                 }
1732
1733                 for (i = 0; i < 6; i += 2) {
1734                         u32 low, high;
1735
1736                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1737                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1738                             tg3_wait_macro_done(tp)) {
1739                                 *resetp = 1;
1740                                 return -EBUSY;
1741                         }
1742                         low &= 0x7fff;
1743                         high &= 0x000f;
1744                         if (low != test_pat[chan][i] ||
1745                             high != test_pat[chan][i+1]) {
1746                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1747                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1748                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1749
1750                                 return -EBUSY;
1751                         }
1752                 }
1753         }
1754
1755         return 0;
1756 }
1757
1758 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1759 {
1760         int chan;
1761
1762         for (chan = 0; chan < 4; chan++) {
1763                 int i;
1764
1765                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1766                              (chan * 0x2000) | 0x0200);
1767                 tg3_writephy(tp, 0x16, 0x0002);
1768                 for (i = 0; i < 6; i++)
1769                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1770                 tg3_writephy(tp, 0x16, 0x0202);
1771                 if (tg3_wait_macro_done(tp))
1772                         return -EBUSY;
1773         }
1774
1775         return 0;
1776 }
1777
1778 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1779 {
1780         u32 reg32, phy9_orig;
1781         int retries, do_phy_reset, err;
1782
1783         retries = 10;
1784         do_phy_reset = 1;
1785         do {
1786                 if (do_phy_reset) {
1787                         err = tg3_bmcr_reset(tp);
1788                         if (err)
1789                                 return err;
1790                         do_phy_reset = 0;
1791                 }
1792
1793                 /* Disable transmitter and interrupt.  */
1794                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1795                         continue;
1796
1797                 reg32 |= 0x3000;
1798                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1799
1800                 /* Set full-duplex, 1000 mbps.  */
1801                 tg3_writephy(tp, MII_BMCR,
1802                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1803
1804                 /* Set to master mode.  */
1805                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1806                         continue;
1807
1808                 tg3_writephy(tp, MII_TG3_CTRL,
1809                              (MII_TG3_CTRL_AS_MASTER |
1810                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1811
1812                 /* Enable SM_DSP_CLOCK and 6dB.  */
1813                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1814
1815                 /* Block the PHY control access.  */
1816                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1817                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1818
1819                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1820                 if (!err)
1821                         break;
1822         } while (--retries);
1823
1824         err = tg3_phy_reset_chanpat(tp);
1825         if (err)
1826                 return err;
1827
1828         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1829         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1830
1831         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1832         tg3_writephy(tp, 0x16, 0x0000);
1833
1834         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1835             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1836                 /* Set Extended packet length bit for jumbo frames */
1837                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1838         }
1839         else {
1840                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1841         }
1842
1843         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1844
1845         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1846                 reg32 &= ~0x3000;
1847                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1848         } else if (!err)
1849                 err = -EBUSY;
1850
1851         return err;
1852 }
1853
1854 /* This will reset the tigon3 PHY if there is no valid
1855  * link unless the FORCE argument is non-zero.
1856  */
1857 static int tg3_phy_reset(struct tg3 *tp)
1858 {
1859         u32 cpmuctrl;
1860         u32 phy_status;
1861         int err;
1862
1863         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1864                 u32 val;
1865
1866                 val = tr32(GRC_MISC_CFG);
1867                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1868                 udelay(40);
1869         }
1870         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1871         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1872         if (err != 0)
1873                 return -EBUSY;
1874
1875         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1876                 netif_carrier_off(tp->dev);
1877                 tg3_link_report(tp);
1878         }
1879
1880         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1881             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1882             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1883                 err = tg3_phy_reset_5703_4_5(tp);
1884                 if (err)
1885                         return err;
1886                 goto out;
1887         }
1888
1889         cpmuctrl = 0;
1890         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1891             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1892                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1893                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1894                         tw32(TG3_CPMU_CTRL,
1895                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1896         }
1897
1898         err = tg3_bmcr_reset(tp);
1899         if (err)
1900                 return err;
1901
1902         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1903                 u32 phy;
1904
1905                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1906                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1907
1908                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1909         }
1910
1911         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1912             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1913                 u32 val;
1914
1915                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1916                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1917                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1918                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1919                         udelay(40);
1920                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1921                 }
1922         }
1923
1924         tg3_phy_apply_otp(tp);
1925
1926         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1927                 tg3_phy_toggle_apd(tp, true);
1928         else
1929                 tg3_phy_toggle_apd(tp, false);
1930
1931 out:
1932         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1933                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1934                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1935                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1936                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1937                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1938                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1939         }
1940         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1941                 tg3_writephy(tp, 0x1c, 0x8d68);
1942                 tg3_writephy(tp, 0x1c, 0x8d68);
1943         }
1944         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1945                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1946                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1947                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1948                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1949                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1950                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1951                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1952                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1953         }
1954         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1955                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1956                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1957                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1958                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1959                         tg3_writephy(tp, MII_TG3_TEST1,
1960                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1961                 } else
1962                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1963                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1964         }
1965         /* Set Extended packet length bit (bit 14) on all chips that */
1966         /* support jumbo frames */
1967         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1968                 /* Cannot do read-modify-write on 5401 */
1969                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1970         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1971                 u32 phy_reg;
1972
1973                 /* Set bit 14 with read-modify-write to preserve other bits */
1974                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1975                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1976                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1977         }
1978
1979         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1980          * jumbo frames transmission.
1981          */
1982         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1983                 u32 phy_reg;
1984
1985                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1986                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1987                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1988         }
1989
1990         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1991                 /* adjust output voltage */
1992                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
1993         }
1994
1995         tg3_phy_toggle_automdix(tp, 1);
1996         tg3_phy_set_wirespeed(tp);
1997         return 0;
1998 }
1999
2000 static void tg3_frob_aux_power(struct tg3 *tp)
2001 {
2002         struct tg3 *tp_peer = tp;
2003
2004         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
2005                 return;
2006
2007         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2008             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2009             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2010                 struct net_device *dev_peer;
2011
2012                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2013                 /* remove_one() may have been run on the peer. */
2014                 if (!dev_peer)
2015                         tp_peer = tp;
2016                 else
2017                         tp_peer = netdev_priv(dev_peer);
2018         }
2019
2020         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2021             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2022             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2023             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2024                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2025                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2026                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2027                                     (GRC_LCLCTRL_GPIO_OE0 |
2028                                      GRC_LCLCTRL_GPIO_OE1 |
2029                                      GRC_LCLCTRL_GPIO_OE2 |
2030                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2031                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2032                                     100);
2033                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2034                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2035                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2036                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2037                                              GRC_LCLCTRL_GPIO_OE1 |
2038                                              GRC_LCLCTRL_GPIO_OE2 |
2039                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2040                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2041                                              tp->grc_local_ctrl;
2042                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2043
2044                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2045                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2046
2047                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2048                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2049                 } else {
2050                         u32 no_gpio2;
2051                         u32 grc_local_ctrl = 0;
2052
2053                         if (tp_peer != tp &&
2054                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2055                                 return;
2056
2057                         /* Workaround to prevent overdrawing Amps. */
2058                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2059                             ASIC_REV_5714) {
2060                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2061                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2062                                             grc_local_ctrl, 100);
2063                         }
2064
2065                         /* On 5753 and variants, GPIO2 cannot be used. */
2066                         no_gpio2 = tp->nic_sram_data_cfg &
2067                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2068
2069                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2070                                          GRC_LCLCTRL_GPIO_OE1 |
2071                                          GRC_LCLCTRL_GPIO_OE2 |
2072                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2073                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2074                         if (no_gpio2) {
2075                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2076                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2077                         }
2078                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2079                                                     grc_local_ctrl, 100);
2080
2081                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2082
2083                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2084                                                     grc_local_ctrl, 100);
2085
2086                         if (!no_gpio2) {
2087                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2088                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2089                                             grc_local_ctrl, 100);
2090                         }
2091                 }
2092         } else {
2093                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2094                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2095                         if (tp_peer != tp &&
2096                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2097                                 return;
2098
2099                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2100                                     (GRC_LCLCTRL_GPIO_OE1 |
2101                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2102
2103                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2104                                     GRC_LCLCTRL_GPIO_OE1, 100);
2105
2106                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2107                                     (GRC_LCLCTRL_GPIO_OE1 |
2108                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2109                 }
2110         }
2111 }
2112
2113 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2114 {
2115         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2116                 return 1;
2117         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2118                 if (speed != SPEED_10)
2119                         return 1;
2120         } else if (speed == SPEED_10)
2121                 return 1;
2122
2123         return 0;
2124 }
2125
2126 static int tg3_setup_phy(struct tg3 *, int);
2127
2128 #define RESET_KIND_SHUTDOWN     0
2129 #define RESET_KIND_INIT         1
2130 #define RESET_KIND_SUSPEND      2
2131
2132 static void tg3_write_sig_post_reset(struct tg3 *, int);
2133 static int tg3_halt_cpu(struct tg3 *, u32);
2134
2135 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2136 {
2137         u32 val;
2138
2139         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2140                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2141                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2142                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2143
2144                         sg_dig_ctrl |=
2145                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2146                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2147                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2148                 }
2149                 return;
2150         }
2151
2152         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2153                 tg3_bmcr_reset(tp);
2154                 val = tr32(GRC_MISC_CFG);
2155                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2156                 udelay(40);
2157                 return;
2158         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2159                 u32 phytest;
2160                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2161                         u32 phy;
2162
2163                         tg3_writephy(tp, MII_ADVERTISE, 0);
2164                         tg3_writephy(tp, MII_BMCR,
2165                                      BMCR_ANENABLE | BMCR_ANRESTART);
2166
2167                         tg3_writephy(tp, MII_TG3_FET_TEST,
2168                                      phytest | MII_TG3_FET_SHADOW_EN);
2169                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2170                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2171                                 tg3_writephy(tp,
2172                                              MII_TG3_FET_SHDW_AUXMODE4,
2173                                              phy);
2174                         }
2175                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2176                 }
2177                 return;
2178         } else if (do_low_power) {
2179                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2180                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2181
2182                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2183                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2184                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2185                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2186                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2187         }
2188
2189         /* The PHY should not be powered down on some chips because
2190          * of bugs.
2191          */
2192         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2193             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2194             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2195              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2196                 return;
2197
2198         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2199             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2200                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2201                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2202                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2203                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2204         }
2205
2206         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2207 }
2208
2209 /* tp->lock is held. */
2210 static int tg3_nvram_lock(struct tg3 *tp)
2211 {
2212         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2213                 int i;
2214
2215                 if (tp->nvram_lock_cnt == 0) {
2216                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2217                         for (i = 0; i < 8000; i++) {
2218                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2219                                         break;
2220                                 udelay(20);
2221                         }
2222                         if (i == 8000) {
2223                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2224                                 return -ENODEV;
2225                         }
2226                 }
2227                 tp->nvram_lock_cnt++;
2228         }
2229         return 0;
2230 }
2231
2232 /* tp->lock is held. */
2233 static void tg3_nvram_unlock(struct tg3 *tp)
2234 {
2235         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2236                 if (tp->nvram_lock_cnt > 0)
2237                         tp->nvram_lock_cnt--;
2238                 if (tp->nvram_lock_cnt == 0)
2239                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2240         }
2241 }
2242
2243 /* tp->lock is held. */
2244 static void tg3_enable_nvram_access(struct tg3 *tp)
2245 {
2246         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2247             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2248                 u32 nvaccess = tr32(NVRAM_ACCESS);
2249
2250                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2251         }
2252 }
2253
2254 /* tp->lock is held. */
2255 static void tg3_disable_nvram_access(struct tg3 *tp)
2256 {
2257         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2258             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2259                 u32 nvaccess = tr32(NVRAM_ACCESS);
2260
2261                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2262         }
2263 }
2264
2265 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2266                                         u32 offset, u32 *val)
2267 {
2268         u32 tmp;
2269         int i;
2270
2271         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2272                 return -EINVAL;
2273
2274         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2275                                         EEPROM_ADDR_DEVID_MASK |
2276                                         EEPROM_ADDR_READ);
2277         tw32(GRC_EEPROM_ADDR,
2278              tmp |
2279              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2280              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2281               EEPROM_ADDR_ADDR_MASK) |
2282              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2283
2284         for (i = 0; i < 1000; i++) {
2285                 tmp = tr32(GRC_EEPROM_ADDR);
2286
2287                 if (tmp & EEPROM_ADDR_COMPLETE)
2288                         break;
2289                 msleep(1);
2290         }
2291         if (!(tmp & EEPROM_ADDR_COMPLETE))
2292                 return -EBUSY;
2293
2294         tmp = tr32(GRC_EEPROM_DATA);
2295
2296         /*
2297          * The data will always be opposite the native endian
2298          * format.  Perform a blind byteswap to compensate.
2299          */
2300         *val = swab32(tmp);
2301
2302         return 0;
2303 }
2304
2305 #define NVRAM_CMD_TIMEOUT 10000
2306
2307 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2308 {
2309         int i;
2310
2311         tw32(NVRAM_CMD, nvram_cmd);
2312         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2313                 udelay(10);
2314                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2315                         udelay(10);
2316                         break;
2317                 }
2318         }
2319
2320         if (i == NVRAM_CMD_TIMEOUT)
2321                 return -EBUSY;
2322
2323         return 0;
2324 }
2325
2326 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2327 {
2328         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2329             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2330             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2331            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2332             (tp->nvram_jedecnum == JEDEC_ATMEL))
2333
2334                 addr = ((addr / tp->nvram_pagesize) <<
2335                         ATMEL_AT45DB0X1B_PAGE_POS) +
2336                        (addr % tp->nvram_pagesize);
2337
2338         return addr;
2339 }
2340
2341 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2342 {
2343         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2344             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2345             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2346            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2347             (tp->nvram_jedecnum == JEDEC_ATMEL))
2348
2349                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2350                         tp->nvram_pagesize) +
2351                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2352
2353         return addr;
2354 }
2355
2356 /* NOTE: Data read in from NVRAM is byteswapped according to
2357  * the byteswapping settings for all other register accesses.
2358  * tg3 devices are BE devices, so on a BE machine, the data
2359  * returned will be exactly as it is seen in NVRAM.  On a LE
2360  * machine, the 32-bit value will be byteswapped.
2361  */
2362 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2363 {
2364         int ret;
2365
2366         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2367                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2368
2369         offset = tg3_nvram_phys_addr(tp, offset);
2370
2371         if (offset > NVRAM_ADDR_MSK)
2372                 return -EINVAL;
2373
2374         ret = tg3_nvram_lock(tp);
2375         if (ret)
2376                 return ret;
2377
2378         tg3_enable_nvram_access(tp);
2379
2380         tw32(NVRAM_ADDR, offset);
2381         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2382                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2383
2384         if (ret == 0)
2385                 *val = tr32(NVRAM_RDDATA);
2386
2387         tg3_disable_nvram_access(tp);
2388
2389         tg3_nvram_unlock(tp);
2390
2391         return ret;
2392 }
2393
2394 /* Ensures NVRAM data is in bytestream format. */
2395 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2396 {
2397         u32 v;
2398         int res = tg3_nvram_read(tp, offset, &v);
2399         if (!res)
2400                 *val = cpu_to_be32(v);
2401         return res;
2402 }
2403
2404 /* tp->lock is held. */
2405 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2406 {
2407         u32 addr_high, addr_low;
2408         int i;
2409
2410         addr_high = ((tp->dev->dev_addr[0] << 8) |
2411                      tp->dev->dev_addr[1]);
2412         addr_low = ((tp->dev->dev_addr[2] << 24) |
2413                     (tp->dev->dev_addr[3] << 16) |
2414                     (tp->dev->dev_addr[4] <<  8) |
2415                     (tp->dev->dev_addr[5] <<  0));
2416         for (i = 0; i < 4; i++) {
2417                 if (i == 1 && skip_mac_1)
2418                         continue;
2419                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2420                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2421         }
2422
2423         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2424             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2425                 for (i = 0; i < 12; i++) {
2426                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2427                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2428                 }
2429         }
2430
2431         addr_high = (tp->dev->dev_addr[0] +
2432                      tp->dev->dev_addr[1] +
2433                      tp->dev->dev_addr[2] +
2434                      tp->dev->dev_addr[3] +
2435                      tp->dev->dev_addr[4] +
2436                      tp->dev->dev_addr[5]) &
2437                 TX_BACKOFF_SEED_MASK;
2438         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2439 }
2440
2441 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2442 {
2443         u32 misc_host_ctrl;
2444         bool device_should_wake, do_low_power;
2445
2446         /* Make sure register accesses (indirect or otherwise)
2447          * will function correctly.
2448          */
2449         pci_write_config_dword(tp->pdev,
2450                                TG3PCI_MISC_HOST_CTRL,
2451                                tp->misc_host_ctrl);
2452
2453         switch (state) {
2454         case PCI_D0:
2455                 pci_enable_wake(tp->pdev, state, false);
2456                 pci_set_power_state(tp->pdev, PCI_D0);
2457
2458                 /* Switch out of Vaux if it is a NIC */
2459                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2460                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2461
2462                 return 0;
2463
2464         case PCI_D1:
2465         case PCI_D2:
2466         case PCI_D3hot:
2467                 break;
2468
2469         default:
2470                 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2471                         tp->dev->name, state);
2472                 return -EINVAL;
2473         }
2474
2475         /* Restore the CLKREQ setting. */
2476         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2477                 u16 lnkctl;
2478
2479                 pci_read_config_word(tp->pdev,
2480                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2481                                      &lnkctl);
2482                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2483                 pci_write_config_word(tp->pdev,
2484                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2485                                       lnkctl);
2486         }
2487
2488         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2489         tw32(TG3PCI_MISC_HOST_CTRL,
2490              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2491
2492         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2493                              device_may_wakeup(&tp->pdev->dev) &&
2494                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2495
2496         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2497                 do_low_power = false;
2498                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2499                     !tp->link_config.phy_is_low_power) {
2500                         struct phy_device *phydev;
2501                         u32 phyid, advertising;
2502
2503                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2504
2505                         tp->link_config.phy_is_low_power = 1;
2506
2507                         tp->link_config.orig_speed = phydev->speed;
2508                         tp->link_config.orig_duplex = phydev->duplex;
2509                         tp->link_config.orig_autoneg = phydev->autoneg;
2510                         tp->link_config.orig_advertising = phydev->advertising;
2511
2512                         advertising = ADVERTISED_TP |
2513                                       ADVERTISED_Pause |
2514                                       ADVERTISED_Autoneg |
2515                                       ADVERTISED_10baseT_Half;
2516
2517                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2518                             device_should_wake) {
2519                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2520                                         advertising |=
2521                                                 ADVERTISED_100baseT_Half |
2522                                                 ADVERTISED_100baseT_Full |
2523                                                 ADVERTISED_10baseT_Full;
2524                                 else
2525                                         advertising |= ADVERTISED_10baseT_Full;
2526                         }
2527
2528                         phydev->advertising = advertising;
2529
2530                         phy_start_aneg(phydev);
2531
2532                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2533                         if (phyid != TG3_PHY_ID_BCMAC131) {
2534                                 phyid &= TG3_PHY_OUI_MASK;
2535                                 if (phyid == TG3_PHY_OUI_1 ||
2536                                     phyid == TG3_PHY_OUI_2 ||
2537                                     phyid == TG3_PHY_OUI_3)
2538                                         do_low_power = true;
2539                         }
2540                 }
2541         } else {
2542                 do_low_power = true;
2543
2544                 if (tp->link_config.phy_is_low_power == 0) {
2545                         tp->link_config.phy_is_low_power = 1;
2546                         tp->link_config.orig_speed = tp->link_config.speed;
2547                         tp->link_config.orig_duplex = tp->link_config.duplex;
2548                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2549                 }
2550
2551                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2552                         tp->link_config.speed = SPEED_10;
2553                         tp->link_config.duplex = DUPLEX_HALF;
2554                         tp->link_config.autoneg = AUTONEG_ENABLE;
2555                         tg3_setup_phy(tp, 0);
2556                 }
2557         }
2558
2559         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2560                 u32 val;
2561
2562                 val = tr32(GRC_VCPU_EXT_CTRL);
2563                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2564         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2565                 int i;
2566                 u32 val;
2567
2568                 for (i = 0; i < 200; i++) {
2569                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2570                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2571                                 break;
2572                         msleep(1);
2573                 }
2574         }
2575         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2576                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2577                                                      WOL_DRV_STATE_SHUTDOWN |
2578                                                      WOL_DRV_WOL |
2579                                                      WOL_SET_MAGIC_PKT);
2580
2581         if (device_should_wake) {
2582                 u32 mac_mode;
2583
2584                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2585                         if (do_low_power) {
2586                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2587                                 udelay(40);
2588                         }
2589
2590                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2591                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2592                         else
2593                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2594
2595                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2596                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2597                             ASIC_REV_5700) {
2598                                 u32 speed = (tp->tg3_flags &
2599                                              TG3_FLAG_WOL_SPEED_100MB) ?
2600                                              SPEED_100 : SPEED_10;
2601                                 if (tg3_5700_link_polarity(tp, speed))
2602                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2603                                 else
2604                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2605                         }
2606                 } else {
2607                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2608                 }
2609
2610                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2611                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2612
2613                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2614                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2615                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2616                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2617                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2618                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2619
2620                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2621                         mac_mode |= tp->mac_mode &
2622                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2623                         if (mac_mode & MAC_MODE_APE_TX_EN)
2624                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2625                 }
2626
2627                 tw32_f(MAC_MODE, mac_mode);
2628                 udelay(100);
2629
2630                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2631                 udelay(10);
2632         }
2633
2634         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2635             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2636              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2637                 u32 base_val;
2638
2639                 base_val = tp->pci_clock_ctrl;
2640                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2641                              CLOCK_CTRL_TXCLK_DISABLE);
2642
2643                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2644                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2645         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2646                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2647                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2648                 /* do nothing */
2649         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2650                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2651                 u32 newbits1, newbits2;
2652
2653                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2654                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2655                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2656                                     CLOCK_CTRL_TXCLK_DISABLE |
2657                                     CLOCK_CTRL_ALTCLK);
2658                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2659                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2660                         newbits1 = CLOCK_CTRL_625_CORE;
2661                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2662                 } else {
2663                         newbits1 = CLOCK_CTRL_ALTCLK;
2664                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2665                 }
2666
2667                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2668                             40);
2669
2670                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2671                             40);
2672
2673                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2674                         u32 newbits3;
2675
2676                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2677                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2678                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2679                                             CLOCK_CTRL_TXCLK_DISABLE |
2680                                             CLOCK_CTRL_44MHZ_CORE);
2681                         } else {
2682                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2683                         }
2684
2685                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2686                                     tp->pci_clock_ctrl | newbits3, 40);
2687                 }
2688         }
2689
2690         if (!(device_should_wake) &&
2691             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2692                 tg3_power_down_phy(tp, do_low_power);
2693
2694         tg3_frob_aux_power(tp);
2695
2696         /* Workaround for unstable PLL clock */
2697         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2698             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2699                 u32 val = tr32(0x7d00);
2700
2701                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2702                 tw32(0x7d00, val);
2703                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2704                         int err;
2705
2706                         err = tg3_nvram_lock(tp);
2707                         tg3_halt_cpu(tp, RX_CPU_BASE);
2708                         if (!err)
2709                                 tg3_nvram_unlock(tp);
2710                 }
2711         }
2712
2713         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2714
2715         if (device_should_wake)
2716                 pci_enable_wake(tp->pdev, state, true);
2717
2718         /* Finally, set the new power state. */
2719         pci_set_power_state(tp->pdev, state);
2720
2721         return 0;
2722 }
2723
2724 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2725 {
2726         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2727         case MII_TG3_AUX_STAT_10HALF:
2728                 *speed = SPEED_10;
2729                 *duplex = DUPLEX_HALF;
2730                 break;
2731
2732         case MII_TG3_AUX_STAT_10FULL:
2733                 *speed = SPEED_10;
2734                 *duplex = DUPLEX_FULL;
2735                 break;
2736
2737         case MII_TG3_AUX_STAT_100HALF:
2738                 *speed = SPEED_100;
2739                 *duplex = DUPLEX_HALF;
2740                 break;
2741
2742         case MII_TG3_AUX_STAT_100FULL:
2743                 *speed = SPEED_100;
2744                 *duplex = DUPLEX_FULL;
2745                 break;
2746
2747         case MII_TG3_AUX_STAT_1000HALF:
2748                 *speed = SPEED_1000;
2749                 *duplex = DUPLEX_HALF;
2750                 break;
2751
2752         case MII_TG3_AUX_STAT_1000FULL:
2753                 *speed = SPEED_1000;
2754                 *duplex = DUPLEX_FULL;
2755                 break;
2756
2757         default:
2758                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2759                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2760                                  SPEED_10;
2761                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2762                                   DUPLEX_HALF;
2763                         break;
2764                 }
2765                 *speed = SPEED_INVALID;
2766                 *duplex = DUPLEX_INVALID;
2767                 break;
2768         }
2769 }
2770
2771 static void tg3_phy_copper_begin(struct tg3 *tp)
2772 {
2773         u32 new_adv;
2774         int i;
2775
2776         if (tp->link_config.phy_is_low_power) {
2777                 /* Entering low power mode.  Disable gigabit and
2778                  * 100baseT advertisements.
2779                  */
2780                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2781
2782                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2783                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2784                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2785                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2786
2787                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2788         } else if (tp->link_config.speed == SPEED_INVALID) {
2789                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2790                         tp->link_config.advertising &=
2791                                 ~(ADVERTISED_1000baseT_Half |
2792                                   ADVERTISED_1000baseT_Full);
2793
2794                 new_adv = ADVERTISE_CSMA;
2795                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2796                         new_adv |= ADVERTISE_10HALF;
2797                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2798                         new_adv |= ADVERTISE_10FULL;
2799                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2800                         new_adv |= ADVERTISE_100HALF;
2801                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2802                         new_adv |= ADVERTISE_100FULL;
2803
2804                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2805
2806                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2807
2808                 if (tp->link_config.advertising &
2809                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2810                         new_adv = 0;
2811                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2812                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2813                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2814                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2815                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2816                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2817                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2818                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2819                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2820                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2821                 } else {
2822                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2823                 }
2824         } else {
2825                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2826                 new_adv |= ADVERTISE_CSMA;
2827
2828                 /* Asking for a specific link mode. */
2829                 if (tp->link_config.speed == SPEED_1000) {
2830                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2831
2832                         if (tp->link_config.duplex == DUPLEX_FULL)
2833                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2834                         else
2835                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2836                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2837                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2838                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2839                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2840                 } else {
2841                         if (tp->link_config.speed == SPEED_100) {
2842                                 if (tp->link_config.duplex == DUPLEX_FULL)
2843                                         new_adv |= ADVERTISE_100FULL;
2844                                 else
2845                                         new_adv |= ADVERTISE_100HALF;
2846                         } else {
2847                                 if (tp->link_config.duplex == DUPLEX_FULL)
2848                                         new_adv |= ADVERTISE_10FULL;
2849                                 else
2850                                         new_adv |= ADVERTISE_10HALF;
2851                         }
2852                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2853
2854                         new_adv = 0;
2855                 }
2856
2857                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2858         }
2859
2860         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2861             tp->link_config.speed != SPEED_INVALID) {
2862                 u32 bmcr, orig_bmcr;
2863
2864                 tp->link_config.active_speed = tp->link_config.speed;
2865                 tp->link_config.active_duplex = tp->link_config.duplex;
2866
2867                 bmcr = 0;
2868                 switch (tp->link_config.speed) {
2869                 default:
2870                 case SPEED_10:
2871                         break;
2872
2873                 case SPEED_100:
2874                         bmcr |= BMCR_SPEED100;
2875                         break;
2876
2877                 case SPEED_1000:
2878                         bmcr |= TG3_BMCR_SPEED1000;
2879                         break;
2880                 }
2881
2882                 if (tp->link_config.duplex == DUPLEX_FULL)
2883                         bmcr |= BMCR_FULLDPLX;
2884
2885                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2886                     (bmcr != orig_bmcr)) {
2887                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2888                         for (i = 0; i < 1500; i++) {
2889                                 u32 tmp;
2890
2891                                 udelay(10);
2892                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2893                                     tg3_readphy(tp, MII_BMSR, &tmp))
2894                                         continue;
2895                                 if (!(tmp & BMSR_LSTATUS)) {
2896                                         udelay(40);
2897                                         break;
2898                                 }
2899                         }
2900                         tg3_writephy(tp, MII_BMCR, bmcr);
2901                         udelay(40);
2902                 }
2903         } else {
2904                 tg3_writephy(tp, MII_BMCR,
2905                              BMCR_ANENABLE | BMCR_ANRESTART);
2906         }
2907 }
2908
2909 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2910 {
2911         int err;
2912
2913         /* Turn off tap power management. */
2914         /* Set Extended packet length bit */
2915         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2916
2917         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2918         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2919
2920         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2921         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2922
2923         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2924         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2925
2926         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2927         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2928
2929         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2930         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2931
2932         udelay(40);
2933
2934         return err;
2935 }
2936
2937 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2938 {
2939         u32 adv_reg, all_mask = 0;
2940
2941         if (mask & ADVERTISED_10baseT_Half)
2942                 all_mask |= ADVERTISE_10HALF;
2943         if (mask & ADVERTISED_10baseT_Full)
2944                 all_mask |= ADVERTISE_10FULL;
2945         if (mask & ADVERTISED_100baseT_Half)
2946                 all_mask |= ADVERTISE_100HALF;
2947         if (mask & ADVERTISED_100baseT_Full)
2948                 all_mask |= ADVERTISE_100FULL;
2949
2950         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2951                 return 0;
2952
2953         if ((adv_reg & all_mask) != all_mask)
2954                 return 0;
2955         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2956                 u32 tg3_ctrl;
2957
2958                 all_mask = 0;
2959                 if (mask & ADVERTISED_1000baseT_Half)
2960                         all_mask |= ADVERTISE_1000HALF;
2961                 if (mask & ADVERTISED_1000baseT_Full)
2962                         all_mask |= ADVERTISE_1000FULL;
2963
2964                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2965                         return 0;
2966
2967                 if ((tg3_ctrl & all_mask) != all_mask)
2968                         return 0;
2969         }
2970         return 1;
2971 }
2972
2973 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2974 {
2975         u32 curadv, reqadv;
2976
2977         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2978                 return 1;
2979
2980         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2981         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2982
2983         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2984                 if (curadv != reqadv)
2985                         return 0;
2986
2987                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2988                         tg3_readphy(tp, MII_LPA, rmtadv);
2989         } else {
2990                 /* Reprogram the advertisement register, even if it
2991                  * does not affect the current link.  If the link
2992                  * gets renegotiated in the future, we can save an
2993                  * additional renegotiation cycle by advertising
2994                  * it correctly in the first place.
2995                  */
2996                 if (curadv != reqadv) {
2997                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2998                                      ADVERTISE_PAUSE_ASYM);
2999                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3000                 }
3001         }
3002
3003         return 1;
3004 }
3005
3006 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3007 {
3008         int current_link_up;
3009         u32 bmsr, dummy;
3010         u32 lcl_adv, rmt_adv;
3011         u16 current_speed;
3012         u8 current_duplex;
3013         int i, err;
3014
3015         tw32(MAC_EVENT, 0);
3016
3017         tw32_f(MAC_STATUS,
3018              (MAC_STATUS_SYNC_CHANGED |
3019               MAC_STATUS_CFG_CHANGED |
3020               MAC_STATUS_MI_COMPLETION |
3021               MAC_STATUS_LNKSTATE_CHANGED));
3022         udelay(40);
3023
3024         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3025                 tw32_f(MAC_MI_MODE,
3026                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3027                 udelay(80);
3028         }
3029
3030         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3031
3032         /* Some third-party PHYs need to be reset on link going
3033          * down.
3034          */
3035         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3036              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3037              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3038             netif_carrier_ok(tp->dev)) {
3039                 tg3_readphy(tp, MII_BMSR, &bmsr);
3040                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3041                     !(bmsr & BMSR_LSTATUS))
3042                         force_reset = 1;
3043         }
3044         if (force_reset)
3045                 tg3_phy_reset(tp);
3046
3047         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3048                 tg3_readphy(tp, MII_BMSR, &bmsr);
3049                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3050                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3051                         bmsr = 0;
3052
3053                 if (!(bmsr & BMSR_LSTATUS)) {
3054                         err = tg3_init_5401phy_dsp(tp);
3055                         if (err)
3056                                 return err;
3057
3058                         tg3_readphy(tp, MII_BMSR, &bmsr);
3059                         for (i = 0; i < 1000; i++) {
3060                                 udelay(10);
3061                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3062                                     (bmsr & BMSR_LSTATUS)) {
3063                                         udelay(40);
3064                                         break;
3065                                 }
3066                         }
3067
3068                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3069                             !(bmsr & BMSR_LSTATUS) &&
3070                             tp->link_config.active_speed == SPEED_1000) {
3071                                 err = tg3_phy_reset(tp);
3072                                 if (!err)
3073                                         err = tg3_init_5401phy_dsp(tp);
3074                                 if (err)
3075                                         return err;
3076                         }
3077                 }
3078         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3079                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3080                 /* 5701 {A0,B0} CRC bug workaround */
3081                 tg3_writephy(tp, 0x15, 0x0a75);
3082                 tg3_writephy(tp, 0x1c, 0x8c68);
3083                 tg3_writephy(tp, 0x1c, 0x8d68);
3084                 tg3_writephy(tp, 0x1c, 0x8c68);
3085         }
3086
3087         /* Clear pending interrupts... */
3088         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3089         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3090
3091         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3092                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3093         else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3094                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3095
3096         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3097             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3098                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3099                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3100                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3101                 else
3102                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3103         }
3104
3105         current_link_up = 0;
3106         current_speed = SPEED_INVALID;
3107         current_duplex = DUPLEX_INVALID;
3108
3109         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3110                 u32 val;
3111
3112                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3113                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3114                 if (!(val & (1 << 10))) {
3115                         val |= (1 << 10);
3116                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3117                         goto relink;
3118                 }
3119         }
3120
3121         bmsr = 0;
3122         for (i = 0; i < 100; i++) {
3123                 tg3_readphy(tp, MII_BMSR, &bmsr);
3124                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3125                     (bmsr & BMSR_LSTATUS))
3126                         break;
3127                 udelay(40);
3128         }
3129
3130         if (bmsr & BMSR_LSTATUS) {
3131                 u32 aux_stat, bmcr;
3132
3133                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3134                 for (i = 0; i < 2000; i++) {
3135                         udelay(10);
3136                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3137                             aux_stat)
3138                                 break;
3139                 }
3140
3141                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3142                                              &current_speed,
3143                                              &current_duplex);
3144
3145                 bmcr = 0;
3146                 for (i = 0; i < 200; i++) {
3147                         tg3_readphy(tp, MII_BMCR, &bmcr);
3148                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3149                                 continue;
3150                         if (bmcr && bmcr != 0x7fff)
3151                                 break;
3152                         udelay(10);
3153                 }
3154
3155                 lcl_adv = 0;
3156                 rmt_adv = 0;
3157
3158                 tp->link_config.active_speed = current_speed;
3159                 tp->link_config.active_duplex = current_duplex;
3160
3161                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3162                         if ((bmcr & BMCR_ANENABLE) &&
3163                             tg3_copper_is_advertising_all(tp,
3164                                                 tp->link_config.advertising)) {
3165                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3166                                                                   &rmt_adv))
3167                                         current_link_up = 1;
3168                         }
3169                 } else {
3170                         if (!(bmcr & BMCR_ANENABLE) &&
3171                             tp->link_config.speed == current_speed &&
3172                             tp->link_config.duplex == current_duplex &&
3173                             tp->link_config.flowctrl ==
3174                             tp->link_config.active_flowctrl) {
3175                                 current_link_up = 1;
3176                         }
3177                 }
3178
3179                 if (current_link_up == 1 &&
3180                     tp->link_config.active_duplex == DUPLEX_FULL)
3181                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3182         }
3183
3184 relink:
3185         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3186                 u32 tmp;
3187
3188                 tg3_phy_copper_begin(tp);
3189
3190                 tg3_readphy(tp, MII_BMSR, &tmp);
3191                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3192                     (tmp & BMSR_LSTATUS))
3193                         current_link_up = 1;
3194         }
3195
3196         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3197         if (current_link_up == 1) {
3198                 if (tp->link_config.active_speed == SPEED_100 ||
3199                     tp->link_config.active_speed == SPEED_10)
3200                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3201                 else
3202                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3203         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3204                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3205         else
3206                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3207
3208         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3209         if (tp->link_config.active_duplex == DUPLEX_HALF)
3210                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3211
3212         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3213                 if (current_link_up == 1 &&
3214                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3215                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3216                 else
3217                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3218         }
3219
3220         /* ??? Without this setting Netgear GA302T PHY does not
3221          * ??? send/receive packets...
3222          */
3223         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3224             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3225                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3226                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3227                 udelay(80);
3228         }
3229
3230         tw32_f(MAC_MODE, tp->mac_mode);
3231         udelay(40);
3232
3233         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3234                 /* Polled via timer. */
3235                 tw32_f(MAC_EVENT, 0);
3236         } else {
3237                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3238         }
3239         udelay(40);
3240
3241         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3242             current_link_up == 1 &&
3243             tp->link_config.active_speed == SPEED_1000 &&
3244             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3245              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3246                 udelay(120);
3247                 tw32_f(MAC_STATUS,
3248                      (MAC_STATUS_SYNC_CHANGED |
3249                       MAC_STATUS_CFG_CHANGED));
3250                 udelay(40);
3251                 tg3_write_mem(tp,
3252                               NIC_SRAM_FIRMWARE_MBOX,
3253                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3254         }
3255
3256         /* Prevent send BD corruption. */
3257         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3258                 u16 oldlnkctl, newlnkctl;
3259
3260                 pci_read_config_word(tp->pdev,
3261                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3262                                      &oldlnkctl);
3263                 if (tp->link_config.active_speed == SPEED_100 ||
3264                     tp->link_config.active_speed == SPEED_10)
3265                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3266                 else
3267                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3268                 if (newlnkctl != oldlnkctl)
3269                         pci_write_config_word(tp->pdev,
3270                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3271                                               newlnkctl);
3272         }
3273
3274         if (current_link_up != netif_carrier_ok(tp->dev)) {
3275                 if (current_link_up)
3276                         netif_carrier_on(tp->dev);
3277                 else
3278                         netif_carrier_off(tp->dev);
3279                 tg3_link_report(tp);
3280         }
3281
3282         return 0;
3283 }
3284
3285 struct tg3_fiber_aneginfo {
3286         int state;
3287 #define ANEG_STATE_UNKNOWN              0
3288 #define ANEG_STATE_AN_ENABLE            1
3289 #define ANEG_STATE_RESTART_INIT         2
3290 #define ANEG_STATE_RESTART              3
3291 #define ANEG_STATE_DISABLE_LINK_OK      4
3292 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3293 #define ANEG_STATE_ABILITY_DETECT       6
3294 #define ANEG_STATE_ACK_DETECT_INIT      7
3295 #define ANEG_STATE_ACK_DETECT           8
3296 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3297 #define ANEG_STATE_COMPLETE_ACK         10
3298 #define ANEG_STATE_IDLE_DETECT_INIT     11
3299 #define ANEG_STATE_IDLE_DETECT          12
3300 #define ANEG_STATE_LINK_OK              13
3301 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3302 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3303
3304         u32 flags;
3305 #define MR_AN_ENABLE            0x00000001
3306 #define MR_RESTART_AN           0x00000002
3307 #define MR_AN_COMPLETE          0x00000004
3308 #define MR_PAGE_RX              0x00000008
3309 #define MR_NP_LOADED            0x00000010
3310 #define MR_TOGGLE_TX            0x00000020
3311 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3312 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3313 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3314 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3315 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3316 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3317 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3318 #define MR_TOGGLE_RX            0x00002000
3319 #define MR_NP_RX                0x00004000
3320
3321 #define MR_LINK_OK              0x80000000
3322
3323         unsigned long link_time, cur_time;
3324
3325         u32 ability_match_cfg;
3326         int ability_match_count;
3327
3328         char ability_match, idle_match, ack_match;
3329
3330         u32 txconfig, rxconfig;
3331 #define ANEG_CFG_NP             0x00000080
3332 #define ANEG_CFG_ACK            0x00000040
3333 #define ANEG_CFG_RF2            0x00000020
3334 #define ANEG_CFG_RF1            0x00000010
3335 #define ANEG_CFG_PS2            0x00000001
3336 #define ANEG_CFG_PS1            0x00008000
3337 #define ANEG_CFG_HD             0x00004000
3338 #define ANEG_CFG_FD             0x00002000
3339 #define ANEG_CFG_INVAL          0x00001f06
3340
3341 };
3342 #define ANEG_OK         0
3343 #define ANEG_DONE       1
3344 #define ANEG_TIMER_ENAB 2
3345 #define ANEG_FAILED     -1
3346
3347 #define ANEG_STATE_SETTLE_TIME  10000
3348
3349 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3350                                    struct tg3_fiber_aneginfo *ap)
3351 {
3352         u16 flowctrl;
3353         unsigned long delta;
3354         u32 rx_cfg_reg;
3355         int ret;
3356
3357         if (ap->state == ANEG_STATE_UNKNOWN) {
3358                 ap->rxconfig = 0;
3359                 ap->link_time = 0;
3360                 ap->cur_time = 0;
3361                 ap->ability_match_cfg = 0;
3362                 ap->ability_match_count = 0;
3363                 ap->ability_match = 0;
3364                 ap->idle_match = 0;
3365                 ap->ack_match = 0;
3366         }
3367         ap->cur_time++;
3368
3369         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3370                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3371
3372                 if (rx_cfg_reg != ap->ability_match_cfg) {
3373                         ap->ability_match_cfg = rx_cfg_reg;
3374                         ap->ability_match = 0;
3375                         ap->ability_match_count = 0;
3376                 } else {
3377                         if (++ap->ability_match_count > 1) {
3378                                 ap->ability_match = 1;
3379                                 ap->ability_match_cfg = rx_cfg_reg;
3380                         }
3381                 }
3382                 if (rx_cfg_reg & ANEG_CFG_ACK)
3383                         ap->ack_match = 1;
3384                 else
3385                         ap->ack_match = 0;
3386
3387                 ap->idle_match = 0;
3388         } else {
3389                 ap->idle_match = 1;
3390                 ap->ability_match_cfg = 0;
3391                 ap->ability_match_count = 0;
3392                 ap->ability_match = 0;
3393                 ap->ack_match = 0;
3394
3395                 rx_cfg_reg = 0;
3396         }
3397
3398         ap->rxconfig = rx_cfg_reg;
3399         ret = ANEG_OK;
3400
3401         switch(ap->state) {
3402         case ANEG_STATE_UNKNOWN:
3403                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3404                         ap->state = ANEG_STATE_AN_ENABLE;
3405
3406                 /* fallthru */
3407         case ANEG_STATE_AN_ENABLE:
3408                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3409                 if (ap->flags & MR_AN_ENABLE) {
3410                         ap->link_time = 0;
3411                         ap->cur_time = 0;
3412                         ap->ability_match_cfg = 0;
3413                         ap->ability_match_count = 0;
3414                         ap->ability_match = 0;
3415                         ap->idle_match = 0;
3416                         ap->ack_match = 0;
3417
3418                         ap->state = ANEG_STATE_RESTART_INIT;
3419                 } else {
3420                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3421                 }
3422                 break;
3423
3424         case ANEG_STATE_RESTART_INIT:
3425                 ap->link_time = ap->cur_time;
3426                 ap->flags &= ~(MR_NP_LOADED);
3427                 ap->txconfig = 0;
3428                 tw32(MAC_TX_AUTO_NEG, 0);
3429                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3430                 tw32_f(MAC_MODE, tp->mac_mode);
3431                 udelay(40);
3432
3433                 ret = ANEG_TIMER_ENAB;
3434                 ap->state = ANEG_STATE_RESTART;
3435
3436                 /* fallthru */
3437         case ANEG_STATE_RESTART:
3438                 delta = ap->cur_time - ap->link_time;
3439                 if (delta > ANEG_STATE_SETTLE_TIME) {
3440                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3441                 } else {
3442                         ret = ANEG_TIMER_ENAB;
3443                 }
3444                 break;
3445
3446         case ANEG_STATE_DISABLE_LINK_OK:
3447                 ret = ANEG_DONE;
3448                 break;
3449
3450         case ANEG_STATE_ABILITY_DETECT_INIT:
3451                 ap->flags &= ~(MR_TOGGLE_TX);
3452                 ap->txconfig = ANEG_CFG_FD;
3453                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3454                 if (flowctrl & ADVERTISE_1000XPAUSE)
3455                         ap->txconfig |= ANEG_CFG_PS1;
3456                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3457                         ap->txconfig |= ANEG_CFG_PS2;
3458                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3459                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3460                 tw32_f(MAC_MODE, tp->mac_mode);
3461                 udelay(40);
3462
3463                 ap->state = ANEG_STATE_ABILITY_DETECT;
3464                 break;
3465
3466         case ANEG_STATE_ABILITY_DETECT:
3467                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3468                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3469                 }
3470                 break;
3471
3472         case ANEG_STATE_ACK_DETECT_INIT:
3473                 ap->txconfig |= ANEG_CFG_ACK;
3474                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3475                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3476                 tw32_f(MAC_MODE, tp->mac_mode);
3477                 udelay(40);
3478
3479                 ap->state = ANEG_STATE_ACK_DETECT;
3480
3481                 /* fallthru */
3482         case ANEG_STATE_ACK_DETECT:
3483                 if (ap->ack_match != 0) {
3484                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3485                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3486                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3487                         } else {
3488                                 ap->state = ANEG_STATE_AN_ENABLE;
3489                         }
3490                 } else if (ap->ability_match != 0 &&
3491                            ap->rxconfig == 0) {
3492                         ap->state = ANEG_STATE_AN_ENABLE;
3493                 }
3494                 break;
3495
3496         case ANEG_STATE_COMPLETE_ACK_INIT:
3497                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3498                         ret = ANEG_FAILED;
3499                         break;
3500                 }
3501                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3502                                MR_LP_ADV_HALF_DUPLEX |
3503                                MR_LP_ADV_SYM_PAUSE |
3504                                MR_LP_ADV_ASYM_PAUSE |
3505                                MR_LP_ADV_REMOTE_FAULT1 |
3506                                MR_LP_ADV_REMOTE_FAULT2 |
3507                                MR_LP_ADV_NEXT_PAGE |
3508                                MR_TOGGLE_RX |
3509                                MR_NP_RX);
3510                 if (ap->rxconfig & ANEG_CFG_FD)
3511                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3512                 if (ap->rxconfig & ANEG_CFG_HD)
3513                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3514                 if (ap->rxconfig & ANEG_CFG_PS1)
3515                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3516                 if (ap->rxconfig & ANEG_CFG_PS2)
3517                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3518                 if (ap->rxconfig & ANEG_CFG_RF1)
3519                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3520                 if (ap->rxconfig & ANEG_CFG_RF2)
3521                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3522                 if (ap->rxconfig & ANEG_CFG_NP)
3523                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3524
3525                 ap->link_time = ap->cur_time;
3526
3527                 ap->flags ^= (MR_TOGGLE_TX);
3528                 if (ap->rxconfig & 0x0008)
3529                         ap->flags |= MR_TOGGLE_RX;
3530                 if (ap->rxconfig & ANEG_CFG_NP)
3531                         ap->flags |= MR_NP_RX;
3532                 ap->flags |= MR_PAGE_RX;
3533
3534                 ap->state = ANEG_STATE_COMPLETE_ACK;
3535                 ret = ANEG_TIMER_ENAB;
3536                 break;
3537
3538         case ANEG_STATE_COMPLETE_ACK:
3539                 if (ap->ability_match != 0 &&
3540                     ap->rxconfig == 0) {
3541                         ap->state = ANEG_STATE_AN_ENABLE;
3542                         break;
3543                 }
3544                 delta = ap->cur_time - ap->link_time;
3545                 if (delta > ANEG_STATE_SETTLE_TIME) {
3546                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3547                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3548                         } else {
3549                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3550                                     !(ap->flags & MR_NP_RX)) {
3551                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3552                                 } else {
3553                                         ret = ANEG_FAILED;
3554                                 }
3555                         }
3556                 }
3557                 break;
3558
3559         case ANEG_STATE_IDLE_DETECT_INIT:
3560                 ap->link_time = ap->cur_time;
3561                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3562                 tw32_f(MAC_MODE, tp->mac_mode);
3563                 udelay(40);
3564
3565                 ap->state = ANEG_STATE_IDLE_DETECT;
3566                 ret = ANEG_TIMER_ENAB;
3567                 break;
3568
3569         case ANEG_STATE_IDLE_DETECT:
3570                 if (ap->ability_match != 0 &&
3571                     ap->rxconfig == 0) {
3572                         ap->state = ANEG_STATE_AN_ENABLE;
3573                         break;
3574                 }
3575                 delta = ap->cur_time - ap->link_time;
3576                 if (delta > ANEG_STATE_SETTLE_TIME) {
3577                         /* XXX another gem from the Broadcom driver :( */
3578                         ap->state = ANEG_STATE_LINK_OK;
3579                 }
3580                 break;
3581
3582         case ANEG_STATE_LINK_OK:
3583                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3584                 ret = ANEG_DONE;
3585                 break;
3586
3587         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3588                 /* ??? unimplemented */
3589                 break;
3590
3591         case ANEG_STATE_NEXT_PAGE_WAIT:
3592                 /* ??? unimplemented */
3593                 break;
3594
3595         default:
3596                 ret = ANEG_FAILED;
3597                 break;
3598         }
3599
3600         return ret;
3601 }
3602
3603 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3604 {
3605         int res = 0;
3606         struct tg3_fiber_aneginfo aninfo;
3607         int status = ANEG_FAILED;
3608         unsigned int tick;
3609         u32 tmp;
3610
3611         tw32_f(MAC_TX_AUTO_NEG, 0);
3612
3613         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3614         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3615         udelay(40);
3616
3617         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3618         udelay(40);
3619
3620         memset(&aninfo, 0, sizeof(aninfo));
3621         aninfo.flags |= MR_AN_ENABLE;
3622         aninfo.state = ANEG_STATE_UNKNOWN;
3623         aninfo.cur_time = 0;
3624         tick = 0;
3625         while (++tick < 195000) {
3626                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3627                 if (status == ANEG_DONE || status == ANEG_FAILED)
3628                         break;
3629
3630                 udelay(1);
3631         }
3632
3633         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3634         tw32_f(MAC_MODE, tp->mac_mode);
3635         udelay(40);
3636
3637         *txflags = aninfo.txconfig;
3638         *rxflags = aninfo.flags;
3639
3640         if (status == ANEG_DONE &&
3641             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3642                              MR_LP_ADV_FULL_DUPLEX)))
3643                 res = 1;
3644
3645         return res;
3646 }
3647
3648 static void tg3_init_bcm8002(struct tg3 *tp)
3649 {
3650         u32 mac_status = tr32(MAC_STATUS);
3651         int i;
3652
3653         /* Reset when initting first time or we have a link. */
3654         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3655             !(mac_status & MAC_STATUS_PCS_SYNCED))
3656                 return;
3657
3658         /* Set PLL lock range. */
3659         tg3_writephy(tp, 0x16, 0x8007);
3660
3661         /* SW reset */
3662         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3663
3664         /* Wait for reset to complete. */
3665         /* XXX schedule_timeout() ... */
3666         for (i = 0; i < 500; i++)
3667                 udelay(10);
3668
3669         /* Config mode; select PMA/Ch 1 regs. */
3670         tg3_writephy(tp, 0x10, 0x8411);
3671
3672         /* Enable auto-lock and comdet, select txclk for tx. */
3673         tg3_writephy(tp, 0x11, 0x0a10);
3674
3675         tg3_writephy(tp, 0x18, 0x00a0);
3676         tg3_writephy(tp, 0x16, 0x41ff);
3677
3678         /* Assert and deassert POR. */
3679         tg3_writephy(tp, 0x13, 0x0400);
3680         udelay(40);
3681         tg3_writephy(tp, 0x13, 0x0000);
3682
3683         tg3_writephy(tp, 0x11, 0x0a50);
3684         udelay(40);
3685         tg3_writephy(tp, 0x11, 0x0a10);
3686
3687         /* Wait for signal to stabilize */
3688         /* XXX schedule_timeout() ... */
3689         for (i = 0; i < 15000; i++)
3690                 udelay(10);
3691
3692         /* Deselect the channel register so we can read the PHYID
3693          * later.
3694          */
3695         tg3_writephy(tp, 0x10, 0x8011);
3696 }
3697
3698 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3699 {
3700         u16 flowctrl;
3701         u32 sg_dig_ctrl, sg_dig_status;
3702         u32 serdes_cfg, expected_sg_dig_ctrl;
3703         int workaround, port_a;
3704         int current_link_up;
3705
3706         serdes_cfg = 0;
3707         expected_sg_dig_ctrl = 0;
3708         workaround = 0;
3709         port_a = 1;
3710         current_link_up = 0;
3711
3712         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3713             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3714                 workaround = 1;
3715                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3716                         port_a = 0;
3717
3718                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3719                 /* preserve bits 20-23 for voltage regulator */
3720                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3721         }
3722
3723         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3724
3725         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3726                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3727                         if (workaround) {
3728                                 u32 val = serdes_cfg;
3729
3730                                 if (port_a)
3731                                         val |= 0xc010000;
3732                                 else
3733                                         val |= 0x4010000;
3734                                 tw32_f(MAC_SERDES_CFG, val);
3735                         }
3736
3737                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3738                 }
3739                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3740                         tg3_setup_flow_control(tp, 0, 0);
3741                         current_link_up = 1;
3742                 }
3743                 goto out;
3744         }
3745
3746         /* Want auto-negotiation.  */
3747         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3748
3749         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3750         if (flowctrl & ADVERTISE_1000XPAUSE)
3751                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3752         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3753                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3754
3755         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3756                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3757                     tp->serdes_counter &&
3758                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3759                                     MAC_STATUS_RCVD_CFG)) ==
3760                      MAC_STATUS_PCS_SYNCED)) {
3761                         tp->serdes_counter--;
3762                         current_link_up = 1;
3763                         goto out;
3764                 }
3765 restart_autoneg:
3766                 if (workaround)
3767                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3768                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3769                 udelay(5);
3770                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3771
3772                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3773                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3774         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3775                                  MAC_STATUS_SIGNAL_DET)) {
3776                 sg_dig_status = tr32(SG_DIG_STATUS);
3777                 mac_status = tr32(MAC_STATUS);
3778
3779                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3780                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3781                         u32 local_adv = 0, remote_adv = 0;
3782
3783                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3784                                 local_adv |= ADVERTISE_1000XPAUSE;
3785                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3786                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3787
3788                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3789                                 remote_adv |= LPA_1000XPAUSE;
3790                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3791                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3792
3793                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3794                         current_link_up = 1;
3795                         tp->serdes_counter = 0;
3796                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3797                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3798                         if (tp->serdes_counter)
3799                                 tp->serdes_counter--;
3800                         else {
3801                                 if (workaround) {
3802                                         u32 val = serdes_cfg;
3803
3804                                         if (port_a)
3805                                                 val |= 0xc010000;
3806                                         else
3807                                                 val |= 0x4010000;
3808
3809                                         tw32_f(MAC_SERDES_CFG, val);
3810                                 }
3811
3812                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3813                                 udelay(40);
3814
3815                                 /* Link parallel detection - link is up */
3816                                 /* only if we have PCS_SYNC and not */
3817                                 /* receiving config code words */
3818                                 mac_status = tr32(MAC_STATUS);
3819                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3820                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3821                                         tg3_setup_flow_control(tp, 0, 0);
3822                                         current_link_up = 1;
3823                                         tp->tg3_flags2 |=
3824                                                 TG3_FLG2_PARALLEL_DETECT;
3825                                         tp->serdes_counter =
3826                                                 SERDES_PARALLEL_DET_TIMEOUT;
3827                                 } else
3828                                         goto restart_autoneg;
3829                         }
3830                 }
3831         } else {
3832                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3833                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3834         }
3835
3836 out:
3837         return current_link_up;
3838 }
3839
3840 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3841 {
3842         int current_link_up = 0;
3843
3844         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3845                 goto out;
3846
3847         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3848                 u32 txflags, rxflags;
3849                 int i;
3850
3851                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3852                         u32 local_adv = 0, remote_adv = 0;
3853
3854                         if (txflags & ANEG_CFG_PS1)
3855                                 local_adv |= ADVERTISE_1000XPAUSE;
3856                         if (txflags & ANEG_CFG_PS2)
3857                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3858
3859                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3860                                 remote_adv |= LPA_1000XPAUSE;
3861                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3862                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3863
3864                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3865
3866                         current_link_up = 1;
3867                 }
3868                 for (i = 0; i < 30; i++) {
3869                         udelay(20);
3870                         tw32_f(MAC_STATUS,
3871                                (MAC_STATUS_SYNC_CHANGED |
3872                                 MAC_STATUS_CFG_CHANGED));
3873                         udelay(40);
3874                         if ((tr32(MAC_STATUS) &
3875                              (MAC_STATUS_SYNC_CHANGED |
3876                               MAC_STATUS_CFG_CHANGED)) == 0)
3877                                 break;
3878                 }
3879
3880                 mac_status = tr32(MAC_STATUS);
3881                 if (current_link_up == 0 &&
3882                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3883                     !(mac_status & MAC_STATUS_RCVD_CFG))
3884                         current_link_up = 1;
3885         } else {
3886                 tg3_setup_flow_control(tp, 0, 0);
3887
3888                 /* Forcing 1000FD link up. */
3889                 current_link_up = 1;
3890
3891                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3892                 udelay(40);
3893
3894                 tw32_f(MAC_MODE, tp->mac_mode);
3895                 udelay(40);
3896         }
3897
3898 out:
3899         return current_link_up;
3900 }
3901
3902 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3903 {
3904         u32 orig_pause_cfg;
3905         u16 orig_active_speed;
3906         u8 orig_active_duplex;
3907         u32 mac_status;
3908         int current_link_up;
3909         int i;
3910
3911         orig_pause_cfg = tp->link_config.active_flowctrl;
3912         orig_active_speed = tp->link_config.active_speed;
3913         orig_active_duplex = tp->link_config.active_duplex;
3914
3915         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3916             netif_carrier_ok(tp->dev) &&
3917             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3918                 mac_status = tr32(MAC_STATUS);
3919                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3920                                MAC_STATUS_SIGNAL_DET |
3921                                MAC_STATUS_CFG_CHANGED |
3922                                MAC_STATUS_RCVD_CFG);
3923                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3924                                    MAC_STATUS_SIGNAL_DET)) {
3925                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3926                                             MAC_STATUS_CFG_CHANGED));
3927                         return 0;
3928                 }
3929         }
3930
3931         tw32_f(MAC_TX_AUTO_NEG, 0);
3932
3933         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3934         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3935         tw32_f(MAC_MODE, tp->mac_mode);
3936         udelay(40);
3937
3938         if (tp->phy_id == PHY_ID_BCM8002)
3939                 tg3_init_bcm8002(tp);
3940
3941         /* Enable link change event even when serdes polling.  */
3942         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3943         udelay(40);
3944
3945         current_link_up = 0;
3946         mac_status = tr32(MAC_STATUS);
3947
3948         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3949                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3950         else
3951                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3952
3953         tp->napi[0].hw_status->status =
3954                 (SD_STATUS_UPDATED |
3955                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3956
3957         for (i = 0; i < 100; i++) {
3958                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3959                                     MAC_STATUS_CFG_CHANGED));
3960                 udelay(5);
3961                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3962                                          MAC_STATUS_CFG_CHANGED |
3963                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3964                         break;
3965         }
3966
3967         mac_status = tr32(MAC_STATUS);
3968         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3969                 current_link_up = 0;
3970                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3971                     tp->serdes_counter == 0) {
3972                         tw32_f(MAC_MODE, (tp->mac_mode |
3973                                           MAC_MODE_SEND_CONFIGS));
3974                         udelay(1);
3975                         tw32_f(MAC_MODE, tp->mac_mode);
3976                 }
3977         }
3978
3979         if (current_link_up == 1) {
3980                 tp->link_config.active_speed = SPEED_1000;
3981                 tp->link_config.active_duplex = DUPLEX_FULL;
3982                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3983                                     LED_CTRL_LNKLED_OVERRIDE |
3984                                     LED_CTRL_1000MBPS_ON));
3985         } else {
3986                 tp->link_config.active_speed = SPEED_INVALID;
3987                 tp->link_config.active_duplex = DUPLEX_INVALID;
3988                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3989                                     LED_CTRL_LNKLED_OVERRIDE |
3990                                     LED_CTRL_TRAFFIC_OVERRIDE));
3991         }
3992
3993         if (current_link_up != netif_carrier_ok(tp->dev)) {
3994                 if (current_link_up)
3995                         netif_carrier_on(tp->dev);
3996                 else
3997                         netif_carrier_off(tp->dev);
3998                 tg3_link_report(tp);
3999         } else {
4000                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4001                 if (orig_pause_cfg != now_pause_cfg ||
4002                     orig_active_speed != tp->link_config.active_speed ||
4003                     orig_active_duplex != tp->link_config.active_duplex)
4004                         tg3_link_report(tp);
4005         }
4006
4007         return 0;
4008 }
4009
4010 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4011 {
4012         int current_link_up, err = 0;
4013         u32 bmsr, bmcr;
4014         u16 current_speed;
4015         u8 current_duplex;
4016         u32 local_adv, remote_adv;
4017
4018         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4019         tw32_f(MAC_MODE, tp->mac_mode);
4020         udelay(40);
4021
4022         tw32(MAC_EVENT, 0);
4023
4024         tw32_f(MAC_STATUS,
4025              (MAC_STATUS_SYNC_CHANGED |
4026               MAC_STATUS_CFG_CHANGED |
4027               MAC_STATUS_MI_COMPLETION |
4028               MAC_STATUS_LNKSTATE_CHANGED));
4029         udelay(40);
4030
4031         if (force_reset)
4032                 tg3_phy_reset(tp);
4033
4034         current_link_up = 0;
4035         current_speed = SPEED_INVALID;
4036         current_duplex = DUPLEX_INVALID;
4037
4038         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4039         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4040         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4041                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4042                         bmsr |= BMSR_LSTATUS;
4043                 else
4044                         bmsr &= ~BMSR_LSTATUS;
4045         }
4046
4047         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4048
4049         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4050             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4051                 /* do nothing, just check for link up at the end */
4052         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4053                 u32 adv, new_adv;
4054
4055                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4056                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4057                                   ADVERTISE_1000XPAUSE |
4058                                   ADVERTISE_1000XPSE_ASYM |
4059                                   ADVERTISE_SLCT);
4060
4061                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4062
4063                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4064                         new_adv |= ADVERTISE_1000XHALF;
4065                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4066                         new_adv |= ADVERTISE_1000XFULL;
4067
4068                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4069                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4070                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4071                         tg3_writephy(tp, MII_BMCR, bmcr);
4072
4073                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4074                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4075                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4076
4077                         return err;
4078                 }
4079         } else {
4080                 u32 new_bmcr;
4081
4082                 bmcr &= ~BMCR_SPEED1000;
4083                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4084
4085                 if (tp->link_config.duplex == DUPLEX_FULL)
4086                         new_bmcr |= BMCR_FULLDPLX;
4087
4088                 if (new_bmcr != bmcr) {
4089                         /* BMCR_SPEED1000 is a reserved bit that needs
4090                          * to be set on write.
4091                          */
4092                         new_bmcr |= BMCR_SPEED1000;
4093
4094                         /* Force a linkdown */
4095                         if (netif_carrier_ok(tp->dev)) {
4096                                 u32 adv;
4097
4098                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4099                                 adv &= ~(ADVERTISE_1000XFULL |
4100                                          ADVERTISE_1000XHALF |
4101                                          ADVERTISE_SLCT);
4102                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4103                                 tg3_writephy(tp, MII_BMCR, bmcr |
4104                                                            BMCR_ANRESTART |
4105                                                            BMCR_ANENABLE);
4106                                 udelay(10);
4107                                 netif_carrier_off(tp->dev);
4108                         }
4109                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4110                         bmcr = new_bmcr;
4111                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4112                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4113                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4114                             ASIC_REV_5714) {
4115                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4116                                         bmsr |= BMSR_LSTATUS;
4117                                 else
4118                                         bmsr &= ~BMSR_LSTATUS;
4119                         }
4120                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4121                 }
4122         }
4123
4124         if (bmsr & BMSR_LSTATUS) {
4125                 current_speed = SPEED_1000;
4126                 current_link_up = 1;
4127                 if (bmcr & BMCR_FULLDPLX)
4128                         current_duplex = DUPLEX_FULL;
4129                 else
4130                         current_duplex = DUPLEX_HALF;
4131
4132                 local_adv = 0;
4133                 remote_adv = 0;
4134
4135                 if (bmcr & BMCR_ANENABLE) {
4136                         u32 common;
4137
4138                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4139                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4140                         common = local_adv & remote_adv;
4141                         if (common & (ADVERTISE_1000XHALF |
4142                                       ADVERTISE_1000XFULL)) {
4143                                 if (common & ADVERTISE_1000XFULL)
4144                                         current_duplex = DUPLEX_FULL;
4145                                 else
4146                                         current_duplex = DUPLEX_HALF;
4147                         }
4148                         else
4149                                 current_link_up = 0;
4150                 }
4151         }
4152
4153         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4154                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4155
4156         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4157         if (tp->link_config.active_duplex == DUPLEX_HALF)
4158                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4159
4160         tw32_f(MAC_MODE, tp->mac_mode);
4161         udelay(40);
4162
4163         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4164
4165         tp->link_config.active_speed = current_speed;
4166         tp->link_config.active_duplex = current_duplex;
4167
4168         if (current_link_up != netif_carrier_ok(tp->dev)) {
4169                 if (current_link_up)
4170                         netif_carrier_on(tp->dev);
4171                 else {
4172                         netif_carrier_off(tp->dev);
4173                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4174                 }
4175                 tg3_link_report(tp);
4176         }
4177         return err;
4178 }
4179
4180 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4181 {
4182         if (tp->serdes_counter) {
4183                 /* Give autoneg time to complete. */
4184                 tp->serdes_counter--;
4185                 return;
4186         }
4187         if (!netif_carrier_ok(tp->dev) &&
4188             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4189                 u32 bmcr;
4190
4191                 tg3_readphy(tp, MII_BMCR, &bmcr);
4192                 if (bmcr & BMCR_ANENABLE) {
4193                         u32 phy1, phy2;
4194
4195                         /* Select shadow register 0x1f */
4196                         tg3_writephy(tp, 0x1c, 0x7c00);
4197                         tg3_readphy(tp, 0x1c, &phy1);
4198
4199                         /* Select expansion interrupt status register */
4200                         tg3_writephy(tp, 0x17, 0x0f01);
4201                         tg3_readphy(tp, 0x15, &phy2);
4202                         tg3_readphy(tp, 0x15, &phy2);
4203
4204                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4205                                 /* We have signal detect and not receiving
4206                                  * config code words, link is up by parallel
4207                                  * detection.
4208                                  */
4209
4210                                 bmcr &= ~BMCR_ANENABLE;
4211                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4212                                 tg3_writephy(tp, MII_BMCR, bmcr);
4213                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4214                         }
4215                 }
4216         }
4217         else if (netif_carrier_ok(tp->dev) &&
4218                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4219                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4220                 u32 phy2;
4221
4222                 /* Select expansion interrupt status register */
4223                 tg3_writephy(tp, 0x17, 0x0f01);
4224                 tg3_readphy(tp, 0x15, &phy2);
4225                 if (phy2 & 0x20) {
4226                         u32 bmcr;
4227
4228                         /* Config code words received, turn on autoneg. */
4229                         tg3_readphy(tp, MII_BMCR, &bmcr);
4230                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4231
4232                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4233
4234                 }
4235         }
4236 }
4237
4238 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4239 {
4240         int err;
4241
4242         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4243                 err = tg3_setup_fiber_phy(tp, force_reset);
4244         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4245                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4246         } else {
4247                 err = tg3_setup_copper_phy(tp, force_reset);
4248         }
4249
4250         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4251                 u32 val, scale;
4252
4253                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4254                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4255                         scale = 65;
4256                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4257                         scale = 6;
4258                 else
4259                         scale = 12;
4260
4261                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4262                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4263                 tw32(GRC_MISC_CFG, val);
4264         }
4265
4266         if (tp->link_config.active_speed == SPEED_1000 &&
4267             tp->link_config.active_duplex == DUPLEX_HALF)
4268                 tw32(MAC_TX_LENGTHS,
4269                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4270                       (6 << TX_LENGTHS_IPG_SHIFT) |
4271                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4272         else
4273                 tw32(MAC_TX_LENGTHS,
4274                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4275                       (6 << TX_LENGTHS_IPG_SHIFT) |
4276                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4277
4278         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4279                 if (netif_carrier_ok(tp->dev)) {
4280                         tw32(HOSTCC_STAT_COAL_TICKS,
4281                              tp->coal.stats_block_coalesce_usecs);
4282                 } else {
4283                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4284                 }
4285         }
4286
4287         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4288                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4289                 if (!netif_carrier_ok(tp->dev))
4290                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4291                               tp->pwrmgmt_thresh;
4292                 else
4293                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4294                 tw32(PCIE_PWR_MGMT_THRESH, val);
4295         }
4296
4297         return err;
4298 }
4299
4300 /* This is called whenever we suspect that the system chipset is re-
4301  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4302  * is bogus tx completions. We try to recover by setting the
4303  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4304  * in the workqueue.
4305  */
4306 static void tg3_tx_recover(struct tg3 *tp)
4307 {
4308         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4309                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4310
4311         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4312                "mapped I/O cycles to the network device, attempting to "
4313                "recover. Please report the problem to the driver maintainer "
4314                "and include system chipset information.\n", tp->dev->name);
4315
4316         spin_lock(&tp->lock);
4317         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4318         spin_unlock(&tp->lock);
4319 }
4320
4321 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4322 {
4323         smp_mb();
4324         return tnapi->tx_pending -
4325                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4326 }
4327
4328 /* Tigon3 never reports partial packet sends.  So we do not
4329  * need special logic to handle SKBs that have not had all
4330  * of their frags sent yet, like SunGEM does.
4331  */
4332 static void tg3_tx(struct tg3_napi *tnapi)
4333 {
4334         struct tg3 *tp = tnapi->tp;
4335         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4336         u32 sw_idx = tnapi->tx_cons;
4337         struct netdev_queue *txq;
4338         int index = tnapi - tp->napi;
4339
4340         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
4341                 index--;
4342
4343         txq = netdev_get_tx_queue(tp->dev, index);
4344
4345         while (sw_idx != hw_idx) {
4346                 struct tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
4347                 struct sk_buff *skb = ri->skb;
4348                 int i, tx_bug = 0;
4349
4350                 if (unlikely(skb == NULL)) {
4351                         tg3_tx_recover(tp);
4352                         return;
4353                 }
4354
4355                 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
4356
4357                 ri->skb = NULL;
4358
4359                 sw_idx = NEXT_TX(sw_idx);
4360
4361                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4362                         ri = &tnapi->tx_buffers[sw_idx];
4363                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4364                                 tx_bug = 1;
4365                         sw_idx = NEXT_TX(sw_idx);
4366                 }
4367
4368                 dev_kfree_skb(skb);
4369
4370                 if (unlikely(tx_bug)) {
4371                         tg3_tx_recover(tp);
4372                         return;
4373                 }
4374         }
4375
4376         tnapi->tx_cons = sw_idx;
4377
4378         /* Need to make the tx_cons update visible to tg3_start_xmit()
4379          * before checking for netif_queue_stopped().  Without the
4380          * memory barrier, there is a small possibility that tg3_start_xmit()
4381          * will miss it and cause the queue to be stopped forever.
4382          */
4383         smp_mb();
4384
4385         if (unlikely(netif_tx_queue_stopped(txq) &&
4386                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4387                 __netif_tx_lock(txq, smp_processor_id());
4388                 if (netif_tx_queue_stopped(txq) &&
4389                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4390                         netif_tx_wake_queue(txq);
4391                 __netif_tx_unlock(txq);
4392         }
4393 }
4394
4395 /* Returns size of skb allocated or < 0 on error.
4396  *
4397  * We only need to fill in the address because the other members
4398  * of the RX descriptor are invariant, see tg3_init_rings.
4399  *
4400  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4401  * posting buffers we only dirty the first cache line of the RX
4402  * descriptor (containing the address).  Whereas for the RX status
4403  * buffers the cpu only reads the last cacheline of the RX descriptor
4404  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4405  */
4406 static int tg3_alloc_rx_skb(struct tg3_napi *tnapi, u32 opaque_key,
4407                             int src_idx, u32 dest_idx_unmasked)
4408 {
4409         struct tg3 *tp = tnapi->tp;
4410         struct tg3_rx_buffer_desc *desc;
4411         struct ring_info *map, *src_map;
4412         struct sk_buff *skb;
4413         dma_addr_t mapping;
4414         int skb_size, dest_idx;
4415         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4416
4417         src_map = NULL;
4418         switch (opaque_key) {
4419         case RXD_OPAQUE_RING_STD:
4420                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4421                 desc = &tpr->rx_std[dest_idx];
4422                 map = &tpr->rx_std_buffers[dest_idx];
4423                 if (src_idx >= 0)
4424                         src_map = &tpr->rx_std_buffers[src_idx];
4425                 skb_size = tp->rx_pkt_map_sz;
4426                 break;
4427
4428         case RXD_OPAQUE_RING_JUMBO:
4429                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4430                 desc = &tpr->rx_jmb[dest_idx].std;
4431                 map = &tpr->rx_jmb_buffers[dest_idx];
4432                 if (src_idx >= 0)
4433                         src_map = &tpr->rx_jmb_buffers[src_idx];
4434                 skb_size = TG3_RX_JMB_MAP_SZ;
4435                 break;
4436
4437         default:
4438                 return -EINVAL;
4439         }
4440
4441         /* Do not overwrite any of the map or rp information
4442          * until we are sure we can commit to a new buffer.
4443          *
4444          * Callers depend upon this behavior and assume that
4445          * we leave everything unchanged if we fail.
4446          */
4447         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4448         if (skb == NULL)
4449                 return -ENOMEM;
4450
4451         skb_reserve(skb, tp->rx_offset);
4452
4453         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4454                                  PCI_DMA_FROMDEVICE);
4455         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4456                 dev_kfree_skb(skb);
4457                 return -EIO;
4458         }
4459
4460         map->skb = skb;
4461         pci_unmap_addr_set(map, mapping, mapping);
4462
4463         if (src_map != NULL)
4464                 src_map->skb = NULL;
4465
4466         desc->addr_hi = ((u64)mapping >> 32);
4467         desc->addr_lo = ((u64)mapping & 0xffffffff);
4468
4469         return skb_size;
4470 }
4471
4472 /* We only need to move over in the address because the other
4473  * members of the RX descriptor are invariant.  See notes above
4474  * tg3_alloc_rx_skb for full details.
4475  */
4476 static void tg3_recycle_rx(struct tg3_napi *tnapi, u32 opaque_key,
4477                            int src_idx, u32 dest_idx_unmasked)
4478 {
4479         struct tg3 *tp = tnapi->tp;
4480         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4481         struct ring_info *src_map, *dest_map;
4482         int dest_idx;
4483         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4484
4485         switch (opaque_key) {
4486         case RXD_OPAQUE_RING_STD:
4487                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4488                 dest_desc = &tpr->rx_std[dest_idx];
4489                 dest_map = &tpr->rx_std_buffers[dest_idx];
4490                 src_desc = &tpr->rx_std[src_idx];
4491                 src_map = &tpr->rx_std_buffers[src_idx];
4492                 break;
4493
4494         case RXD_OPAQUE_RING_JUMBO:
4495                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4496                 dest_desc = &tpr->rx_jmb[dest_idx].std;
4497                 dest_map = &tpr->rx_jmb_buffers[dest_idx];
4498                 src_desc = &tpr->rx_jmb[src_idx].std;
4499                 src_map = &tpr->rx_jmb_buffers[src_idx];
4500                 break;
4501
4502         default:
4503                 return;
4504         }
4505
4506         dest_map->skb = src_map->skb;
4507         pci_unmap_addr_set(dest_map, mapping,
4508                            pci_unmap_addr(src_map, mapping));
4509         dest_desc->addr_hi = src_desc->addr_hi;
4510         dest_desc->addr_lo = src_desc->addr_lo;
4511
4512         src_map->skb = NULL;
4513 }
4514
4515 /* The RX ring scheme is composed of multiple rings which post fresh
4516  * buffers to the chip, and one special ring the chip uses to report
4517  * status back to the host.
4518  *
4519  * The special ring reports the status of received packets to the
4520  * host.  The chip does not write into the original descriptor the
4521  * RX buffer was obtained from.  The chip simply takes the original
4522  * descriptor as provided by the host, updates the status and length
4523  * field, then writes this into the next status ring entry.
4524  *
4525  * Each ring the host uses to post buffers to the chip is described
4526  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4527  * it is first placed into the on-chip ram.  When the packet's length
4528  * is known, it walks down the TG3_BDINFO entries to select the ring.
4529  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4530  * which is within the range of the new packet's length is chosen.
4531  *
4532  * The "separate ring for rx status" scheme may sound queer, but it makes
4533  * sense from a cache coherency perspective.  If only the host writes
4534  * to the buffer post rings, and only the chip writes to the rx status
4535  * rings, then cache lines never move beyond shared-modified state.
4536  * If both the host and chip were to write into the same ring, cache line
4537  * eviction could occur since both entities want it in an exclusive state.
4538  */
4539 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4540 {
4541         struct tg3 *tp = tnapi->tp;
4542         u32 work_mask, rx_std_posted = 0;
4543         u32 sw_idx = tnapi->rx_rcb_ptr;
4544         u16 hw_idx;
4545         int received;
4546         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4547
4548         hw_idx = *(tnapi->rx_rcb_prod_idx);
4549         /*
4550          * We need to order the read of hw_idx and the read of
4551          * the opaque cookie.
4552          */
4553         rmb();
4554         work_mask = 0;
4555         received = 0;
4556         while (sw_idx != hw_idx && budget > 0) {
4557                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4558                 unsigned int len;
4559                 struct sk_buff *skb;
4560                 dma_addr_t dma_addr;
4561                 u32 opaque_key, desc_idx, *post_ptr;
4562
4563                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4564                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4565                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4566                         struct ring_info *ri = &tpr->rx_std_buffers[desc_idx];
4567                         dma_addr = pci_unmap_addr(ri, mapping);
4568                         skb = ri->skb;
4569                         post_ptr = &tpr->rx_std_ptr;
4570                         rx_std_posted++;
4571                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4572                         struct ring_info *ri = &tpr->rx_jmb_buffers[desc_idx];
4573                         dma_addr = pci_unmap_addr(ri, mapping);
4574                         skb = ri->skb;
4575                         post_ptr = &tpr->rx_jmb_ptr;
4576                 } else
4577                         goto next_pkt_nopost;
4578
4579                 work_mask |= opaque_key;
4580
4581                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4582                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4583                 drop_it:
4584                         tg3_recycle_rx(tnapi, opaque_key,
4585                                        desc_idx, *post_ptr);
4586                 drop_it_no_recycle:
4587                         /* Other statistics kept track of by card. */
4588                         tp->net_stats.rx_dropped++;
4589                         goto next_pkt;
4590                 }
4591
4592                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4593                       ETH_FCS_LEN;
4594
4595                 if (len > RX_COPY_THRESHOLD
4596                         && tp->rx_offset == NET_IP_ALIGN
4597                         /* rx_offset will likely not equal NET_IP_ALIGN
4598                          * if this is a 5701 card running in PCI-X mode
4599                          * [see tg3_get_invariants()]
4600                          */
4601                 ) {
4602                         int skb_size;
4603
4604                         skb_size = tg3_alloc_rx_skb(tnapi, opaque_key,
4605                                                     desc_idx, *post_ptr);
4606                         if (skb_size < 0)
4607                                 goto drop_it;
4608
4609                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4610                                          PCI_DMA_FROMDEVICE);
4611
4612                         skb_put(skb, len);
4613                 } else {
4614                         struct sk_buff *copy_skb;
4615
4616                         tg3_recycle_rx(tnapi, opaque_key,
4617                                        desc_idx, *post_ptr);
4618
4619                         copy_skb = netdev_alloc_skb(tp->dev,
4620                                                     len + TG3_RAW_IP_ALIGN);
4621                         if (copy_skb == NULL)
4622                                 goto drop_it_no_recycle;
4623
4624                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4625                         skb_put(copy_skb, len);
4626                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4627                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4628                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4629
4630                         /* We'll reuse the original ring buffer. */
4631                         skb = copy_skb;
4632                 }
4633
4634                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4635                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4636                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4637                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4638                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4639                 else
4640                         skb->ip_summed = CHECKSUM_NONE;
4641
4642                 skb->protocol = eth_type_trans(skb, tp->dev);
4643
4644                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4645                     skb->protocol != htons(ETH_P_8021Q)) {
4646                         dev_kfree_skb(skb);
4647                         goto next_pkt;
4648                 }
4649
4650 #if TG3_VLAN_TAG_USED
4651                 if (tp->vlgrp != NULL &&
4652                     desc->type_flags & RXD_FLAG_VLAN) {
4653                         vlan_gro_receive(&tnapi->napi, tp->vlgrp,
4654                                          desc->err_vlan & RXD_VLAN_MASK, skb);
4655                 } else
4656 #endif
4657                         napi_gro_receive(&tnapi->napi, skb);
4658
4659                 received++;
4660                 budget--;
4661
4662 next_pkt:
4663                 (*post_ptr)++;
4664
4665                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4666                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4667
4668                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4669                                      TG3_64BIT_REG_LOW, idx);
4670                         work_mask &= ~RXD_OPAQUE_RING_STD;
4671                         rx_std_posted = 0;
4672                 }
4673 next_pkt_nopost:
4674                 sw_idx++;
4675                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4676
4677                 /* Refresh hw_idx to see if there is new work */
4678                 if (sw_idx == hw_idx) {
4679                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4680                         rmb();
4681                 }
4682         }
4683
4684         /* ACK the status ring. */
4685         tnapi->rx_rcb_ptr = sw_idx;
4686         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4687
4688         /* Refill RX ring(s). */
4689         if (work_mask & RXD_OPAQUE_RING_STD) {
4690                 sw_idx = tpr->rx_std_ptr % TG3_RX_RING_SIZE;
4691                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4692                              sw_idx);
4693         }
4694         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4695                 sw_idx = tpr->rx_jmb_ptr % TG3_RX_JUMBO_RING_SIZE;
4696                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4697                              sw_idx);
4698         }
4699         mmiowb();
4700
4701         return received;
4702 }
4703
4704 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4705 {
4706         struct tg3 *tp = tnapi->tp;
4707         struct tg3_hw_status *sblk = tnapi->hw_status;
4708
4709         /* handle link change and other phy events */
4710         if (!(tp->tg3_flags &
4711               (TG3_FLAG_USE_LINKCHG_REG |
4712                TG3_FLAG_POLL_SERDES))) {
4713                 if (sblk->status & SD_STATUS_LINK_CHG) {
4714                         sblk->status = SD_STATUS_UPDATED |
4715                                 (sblk->status & ~SD_STATUS_LINK_CHG);
4716                         spin_lock(&tp->lock);
4717                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4718                                 tw32_f(MAC_STATUS,
4719                                      (MAC_STATUS_SYNC_CHANGED |
4720                                       MAC_STATUS_CFG_CHANGED |
4721                                       MAC_STATUS_MI_COMPLETION |
4722                                       MAC_STATUS_LNKSTATE_CHANGED));
4723                                 udelay(40);
4724                         } else
4725                                 tg3_setup_phy(tp, 0);
4726                         spin_unlock(&tp->lock);
4727                 }
4728         }
4729
4730         /* run TX completion thread */
4731         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4732                 tg3_tx(tnapi);
4733                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4734                         return work_done;
4735         }
4736
4737         /* run RX thread, within the bounds set by NAPI.
4738          * All RX "locking" is done by ensuring outside
4739          * code synchronizes with tg3->napi.poll()
4740          */
4741         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4742                 work_done += tg3_rx(tnapi, budget - work_done);
4743
4744         return work_done;
4745 }
4746
4747 static int tg3_poll(struct napi_struct *napi, int budget)
4748 {
4749         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4750         struct tg3 *tp = tnapi->tp;
4751         int work_done = 0;
4752         struct tg3_hw_status *sblk = tnapi->hw_status;
4753
4754         while (1) {
4755                 work_done = tg3_poll_work(tnapi, work_done, budget);
4756
4757                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4758                         goto tx_recovery;
4759
4760                 if (unlikely(work_done >= budget))
4761                         break;
4762
4763                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4764                         /* tp->last_tag is used in tg3_int_reenable() below
4765                          * to tell the hw how much work has been processed,
4766                          * so we must read it before checking for more work.
4767                          */
4768                         tnapi->last_tag = sblk->status_tag;
4769                         tnapi->last_irq_tag = tnapi->last_tag;
4770                         rmb();
4771                 } else
4772                         sblk->status &= ~SD_STATUS_UPDATED;
4773
4774                 if (likely(!tg3_has_work(tnapi))) {
4775                         napi_complete(napi);
4776                         tg3_int_reenable(tnapi);
4777                         break;
4778                 }
4779         }
4780
4781         return work_done;
4782
4783 tx_recovery:
4784         /* work_done is guaranteed to be less than budget. */
4785         napi_complete(napi);
4786         schedule_work(&tp->reset_task);
4787         return work_done;
4788 }
4789
4790 static void tg3_irq_quiesce(struct tg3 *tp)
4791 {
4792         int i;
4793
4794         BUG_ON(tp->irq_sync);
4795
4796         tp->irq_sync = 1;
4797         smp_mb();
4798
4799         for (i = 0; i < tp->irq_cnt; i++)
4800                 synchronize_irq(tp->napi[i].irq_vec);
4801 }
4802
4803 static inline int tg3_irq_sync(struct tg3 *tp)
4804 {
4805         return tp->irq_sync;
4806 }
4807
4808 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4809  * If irq_sync is non-zero, then the IRQ handler must be synchronized
4810  * with as well.  Most of the time, this is not necessary except when
4811  * shutting down the device.
4812  */
4813 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4814 {
4815         spin_lock_bh(&tp->lock);
4816         if (irq_sync)
4817                 tg3_irq_quiesce(tp);
4818 }
4819
4820 static inline void tg3_full_unlock(struct tg3 *tp)
4821 {
4822         spin_unlock_bh(&tp->lock);
4823 }
4824
4825 /* One-shot MSI handler - Chip automatically disables interrupt
4826  * after sending MSI so driver doesn't have to do it.
4827  */
4828 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4829 {
4830         struct tg3_napi *tnapi = dev_id;
4831         struct tg3 *tp = tnapi->tp;
4832
4833         prefetch(tnapi->hw_status);
4834         if (tnapi->rx_rcb)
4835                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4836
4837         if (likely(!tg3_irq_sync(tp)))
4838                 napi_schedule(&tnapi->napi);
4839
4840         return IRQ_HANDLED;
4841 }
4842
4843 /* MSI ISR - No need to check for interrupt sharing and no need to
4844  * flush status block and interrupt mailbox. PCI ordering rules
4845  * guarantee that MSI will arrive after the status block.
4846  */
4847 static irqreturn_t tg3_msi(int irq, void *dev_id)
4848 {
4849         struct tg3_napi *tnapi = dev_id;
4850         struct tg3 *tp = tnapi->tp;
4851
4852         prefetch(tnapi->hw_status);
4853         if (tnapi->rx_rcb)
4854                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4855         /*
4856          * Writing any value to intr-mbox-0 clears PCI INTA# and
4857          * chip-internal interrupt pending events.
4858          * Writing non-zero to intr-mbox-0 additional tells the
4859          * NIC to stop sending us irqs, engaging "in-intr-handler"
4860          * event coalescing.
4861          */
4862         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4863         if (likely(!tg3_irq_sync(tp)))
4864                 napi_schedule(&tnapi->napi);
4865
4866         return IRQ_RETVAL(1);
4867 }
4868
4869 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4870 {
4871         struct tg3_napi *tnapi = dev_id;
4872         struct tg3 *tp = tnapi->tp;
4873         struct tg3_hw_status *sblk = tnapi->hw_status;
4874         unsigned int handled = 1;
4875
4876         /* In INTx mode, it is possible for the interrupt to arrive at
4877          * the CPU before the status block posted prior to the interrupt.
4878          * Reading the PCI State register will confirm whether the
4879          * interrupt is ours and will flush the status block.
4880          */
4881         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4882                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4883                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4884                         handled = 0;
4885                         goto out;
4886                 }
4887         }
4888
4889         /*
4890          * Writing any value to intr-mbox-0 clears PCI INTA# and
4891          * chip-internal interrupt pending events.
4892          * Writing non-zero to intr-mbox-0 additional tells the
4893          * NIC to stop sending us irqs, engaging "in-intr-handler"
4894          * event coalescing.
4895          *
4896          * Flush the mailbox to de-assert the IRQ immediately to prevent
4897          * spurious interrupts.  The flush impacts performance but
4898          * excessive spurious interrupts can be worse in some cases.
4899          */
4900         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4901         if (tg3_irq_sync(tp))
4902                 goto out;
4903         sblk->status &= ~SD_STATUS_UPDATED;
4904         if (likely(tg3_has_work(tnapi))) {
4905                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4906                 napi_schedule(&tnapi->napi);
4907         } else {
4908                 /* No work, shared interrupt perhaps?  re-enable
4909                  * interrupts, and flush that PCI write
4910                  */
4911                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4912                                0x00000000);
4913         }
4914 out:
4915         return IRQ_RETVAL(handled);
4916 }
4917
4918 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4919 {
4920         struct tg3_napi *tnapi = dev_id;
4921         struct tg3 *tp = tnapi->tp;
4922         struct tg3_hw_status *sblk = tnapi->hw_status;
4923         unsigned int handled = 1;
4924
4925         /* In INTx mode, it is possible for the interrupt to arrive at
4926          * the CPU before the status block posted prior to the interrupt.
4927          * Reading the PCI State register will confirm whether the
4928          * interrupt is ours and will flush the status block.
4929          */
4930         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
4931                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4932                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4933                         handled = 0;
4934                         goto out;
4935                 }
4936         }
4937
4938         /*
4939          * writing any value to intr-mbox-0 clears PCI INTA# and
4940          * chip-internal interrupt pending events.
4941          * writing non-zero to intr-mbox-0 additional tells the
4942          * NIC to stop sending us irqs, engaging "in-intr-handler"
4943          * event coalescing.
4944          *
4945          * Flush the mailbox to de-assert the IRQ immediately to prevent
4946          * spurious interrupts.  The flush impacts performance but
4947          * excessive spurious interrupts can be worse in some cases.
4948          */
4949         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4950
4951         /*
4952          * In a shared interrupt configuration, sometimes other devices'
4953          * interrupts will scream.  We record the current status tag here
4954          * so that the above check can report that the screaming interrupts
4955          * are unhandled.  Eventually they will be silenced.
4956          */
4957         tnapi->last_irq_tag = sblk->status_tag;
4958
4959         if (tg3_irq_sync(tp))
4960                 goto out;
4961
4962         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4963
4964         napi_schedule(&tnapi->napi);
4965
4966 out:
4967         return IRQ_RETVAL(handled);
4968 }
4969
4970 /* ISR for interrupt test */
4971 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4972 {
4973         struct tg3_napi *tnapi = dev_id;
4974         struct tg3 *tp = tnapi->tp;
4975         struct tg3_hw_status *sblk = tnapi->hw_status;
4976
4977         if ((sblk->status & SD_STATUS_UPDATED) ||
4978             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4979                 tg3_disable_ints(tp);
4980                 return IRQ_RETVAL(1);
4981         }
4982         return IRQ_RETVAL(0);
4983 }
4984
4985 static int tg3_init_hw(struct tg3 *, int);
4986 static int tg3_halt(struct tg3 *, int, int);
4987
4988 /* Restart hardware after configuration changes, self-test, etc.
4989  * Invoked with tp->lock held.
4990  */
4991 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4992         __releases(tp->lock)
4993         __acquires(tp->lock)
4994 {
4995         int err;
4996
4997         err = tg3_init_hw(tp, reset_phy);
4998         if (err) {
4999                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
5000                        "aborting.\n", tp->dev->name);
5001                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5002                 tg3_full_unlock(tp);
5003                 del_timer_sync(&tp->timer);
5004                 tp->irq_sync = 0;
5005                 tg3_napi_enable(tp);
5006                 dev_close(tp->dev);
5007                 tg3_full_lock(tp, 0);
5008         }
5009         return err;
5010 }
5011
5012 #ifdef CONFIG_NET_POLL_CONTROLLER
5013 static void tg3_poll_controller(struct net_device *dev)
5014 {
5015         int i;
5016         struct tg3 *tp = netdev_priv(dev);
5017
5018         for (i = 0; i < tp->irq_cnt; i++)
5019                 tg3_interrupt(tp->napi[i].irq_vec, dev);
5020 }
5021 #endif
5022
5023 static void tg3_reset_task(struct work_struct *work)
5024 {
5025         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5026         int err;
5027         unsigned int restart_timer;
5028
5029         tg3_full_lock(tp, 0);
5030
5031         if (!netif_running(tp->dev)) {
5032                 tg3_full_unlock(tp);
5033                 return;
5034         }
5035
5036         tg3_full_unlock(tp);
5037
5038         tg3_phy_stop(tp);
5039
5040         tg3_netif_stop(tp);
5041
5042         tg3_full_lock(tp, 1);
5043
5044         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5045         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5046
5047         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5048                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5049                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5050                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5051                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5052         }
5053
5054         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5055         err = tg3_init_hw(tp, 1);
5056         if (err)
5057                 goto out;
5058
5059         tg3_netif_start(tp);
5060
5061         if (restart_timer)
5062                 mod_timer(&tp->timer, jiffies + 1);
5063
5064 out:
5065         tg3_full_unlock(tp);
5066
5067         if (!err)
5068                 tg3_phy_start(tp);
5069 }
5070
5071 static void tg3_dump_short_state(struct tg3 *tp)
5072 {
5073         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5074                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5075         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5076                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5077 }
5078
5079 static void tg3_tx_timeout(struct net_device *dev)
5080 {
5081         struct tg3 *tp = netdev_priv(dev);
5082
5083         if (netif_msg_tx_err(tp)) {
5084                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5085                        dev->name);
5086                 tg3_dump_short_state(tp);
5087         }
5088
5089         schedule_work(&tp->reset_task);
5090 }
5091
5092 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5093 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5094 {
5095         u32 base = (u32) mapping & 0xffffffff;
5096
5097         return ((base > 0xffffdcc0) &&
5098                 (base + len + 8 < base));
5099 }
5100
5101 /* Test for DMA addresses > 40-bit */
5102 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5103                                           int len)
5104 {
5105 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5106         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5107                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5108         return 0;
5109 #else
5110         return 0;
5111 #endif
5112 }
5113
5114 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5115
5116 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5117 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
5118                                        u32 last_plus_one, u32 *start,
5119                                        u32 base_flags, u32 mss)
5120 {
5121         struct tg3_napi *tnapi = &tp->napi[0];
5122         struct sk_buff *new_skb;
5123         dma_addr_t new_addr = 0;
5124         u32 entry = *start;
5125         int i, ret = 0;
5126
5127         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5128                 new_skb = skb_copy(skb, GFP_ATOMIC);
5129         else {
5130                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5131
5132                 new_skb = skb_copy_expand(skb,
5133                                           skb_headroom(skb) + more_headroom,
5134                                           skb_tailroom(skb), GFP_ATOMIC);
5135         }
5136
5137         if (!new_skb) {
5138                 ret = -1;
5139         } else {
5140                 /* New SKB is guaranteed to be linear. */
5141                 entry = *start;
5142                 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
5143                 new_addr = skb_shinfo(new_skb)->dma_head;
5144
5145                 /* Make sure new skb does not cross any 4G boundaries.
5146                  * Drop the packet if it does.
5147                  */
5148                 if (ret || ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5149                             tg3_4g_overflow_test(new_addr, new_skb->len))) {
5150                         if (!ret)
5151                                 skb_dma_unmap(&tp->pdev->dev, new_skb,
5152                                               DMA_TO_DEVICE);
5153                         ret = -1;
5154                         dev_kfree_skb(new_skb);
5155                         new_skb = NULL;
5156                 } else {
5157                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5158                                     base_flags, 1 | (mss << 1));
5159                         *start = NEXT_TX(entry);
5160                 }
5161         }
5162
5163         /* Now clean up the sw ring entries. */
5164         i = 0;
5165         while (entry != last_plus_one) {
5166                 if (i == 0)
5167                         tnapi->tx_buffers[entry].skb = new_skb;
5168                 else
5169                         tnapi->tx_buffers[entry].skb = NULL;
5170                 entry = NEXT_TX(entry);
5171                 i++;
5172         }
5173
5174         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5175         dev_kfree_skb(skb);
5176
5177         return ret;
5178 }
5179
5180 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5181                         dma_addr_t mapping, int len, u32 flags,
5182                         u32 mss_and_is_end)
5183 {
5184         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5185         int is_end = (mss_and_is_end & 0x1);
5186         u32 mss = (mss_and_is_end >> 1);
5187         u32 vlan_tag = 0;
5188
5189         if (is_end)
5190                 flags |= TXD_FLAG_END;
5191         if (flags & TXD_FLAG_VLAN) {
5192                 vlan_tag = flags >> 16;
5193                 flags &= 0xffff;
5194         }
5195         vlan_tag |= (mss << TXD_MSS_SHIFT);
5196
5197         txd->addr_hi = ((u64) mapping >> 32);
5198         txd->addr_lo = ((u64) mapping & 0xffffffff);
5199         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5200         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5201 }
5202
5203 /* hard_start_xmit for devices that don't have any bugs and
5204  * support TG3_FLG2_HW_TSO_2 only.
5205  */
5206 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5207                                   struct net_device *dev)
5208 {
5209         struct tg3 *tp = netdev_priv(dev);
5210         u32 len, entry, base_flags, mss;
5211         struct skb_shared_info *sp;
5212         dma_addr_t mapping;
5213         struct tg3_napi *tnapi;
5214         struct netdev_queue *txq;
5215
5216         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5217         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5218         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5219                 tnapi++;
5220
5221         /* We are running in BH disabled context with netif_tx_lock
5222          * and TX reclaim runs via tp->napi.poll inside of a software
5223          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5224          * no IRQ context deadlocks to worry about either.  Rejoice!
5225          */
5226         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5227                 if (!netif_tx_queue_stopped(txq)) {
5228                         netif_tx_stop_queue(txq);
5229
5230                         /* This is a hard error, log it. */
5231                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5232                                "queue awake!\n", dev->name);
5233                 }
5234                 return NETDEV_TX_BUSY;
5235         }
5236
5237         entry = tnapi->tx_prod;
5238         base_flags = 0;
5239         mss = 0;
5240         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5241                 int tcp_opt_len, ip_tcp_len;
5242                 u32 hdrlen;
5243
5244                 if (skb_header_cloned(skb) &&
5245                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5246                         dev_kfree_skb(skb);
5247                         goto out_unlock;
5248                 }
5249
5250                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5251                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5252                 else {
5253                         struct iphdr *iph = ip_hdr(skb);
5254
5255                         tcp_opt_len = tcp_optlen(skb);
5256                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5257
5258                         iph->check = 0;
5259                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5260                         hdrlen = ip_tcp_len + tcp_opt_len;
5261                 }
5262
5263                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
5264                         mss |= (hdrlen & 0xc) << 12;
5265                         if (hdrlen & 0x10)
5266                                 base_flags |= 0x00000010;
5267                         base_flags |= (hdrlen & 0x3e0) << 5;
5268                 } else
5269                         mss |= hdrlen << 9;
5270
5271                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5272                                TXD_FLAG_CPU_POST_DMA);
5273
5274                 tcp_hdr(skb)->check = 0;
5275
5276         }
5277         else if (skb->ip_summed == CHECKSUM_PARTIAL)
5278                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5279 #if TG3_VLAN_TAG_USED
5280         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5281                 base_flags |= (TXD_FLAG_VLAN |
5282                                (vlan_tx_tag_get(skb) << 16));
5283 #endif
5284
5285         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5286                 dev_kfree_skb(skb);
5287                 goto out_unlock;
5288         }
5289
5290         sp = skb_shinfo(skb);
5291
5292         mapping = sp->dma_head;
5293
5294         tnapi->tx_buffers[entry].skb = skb;
5295
5296         len = skb_headlen(skb);
5297
5298         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
5299             !mss && skb->len > ETH_DATA_LEN)
5300                 base_flags |= TXD_FLAG_JMB_PKT;
5301
5302         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5303                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5304
5305         entry = NEXT_TX(entry);
5306
5307         /* Now loop through additional data fragments, and queue them. */
5308         if (skb_shinfo(skb)->nr_frags > 0) {
5309                 unsigned int i, last;
5310
5311                 last = skb_shinfo(skb)->nr_frags - 1;
5312                 for (i = 0; i <= last; i++) {
5313                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5314
5315                         len = frag->size;
5316                         mapping = sp->dma_maps[i];
5317                         tnapi->tx_buffers[entry].skb = NULL;
5318
5319                         tg3_set_txd(tnapi, entry, mapping, len,
5320                                     base_flags, (i == last) | (mss << 1));
5321
5322                         entry = NEXT_TX(entry);
5323                 }
5324         }
5325
5326         /* Packets are ready, update Tx producer idx local and on card. */
5327         tw32_tx_mbox(tnapi->prodmbox, entry);
5328
5329         tnapi->tx_prod = entry;
5330         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5331                 netif_tx_stop_queue(txq);
5332                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5333                         netif_tx_wake_queue(txq);
5334         }
5335
5336 out_unlock:
5337         mmiowb();
5338
5339         return NETDEV_TX_OK;
5340 }
5341
5342 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5343                                           struct net_device *);
5344
5345 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5346  * TSO header is greater than 80 bytes.
5347  */
5348 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5349 {
5350         struct sk_buff *segs, *nskb;
5351         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5352
5353         /* Estimate the number of fragments in the worst case */
5354         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5355                 netif_stop_queue(tp->dev);
5356                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5357                         return NETDEV_TX_BUSY;
5358
5359                 netif_wake_queue(tp->dev);
5360         }
5361
5362         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5363         if (IS_ERR(segs))
5364                 goto tg3_tso_bug_end;
5365
5366         do {
5367                 nskb = segs;
5368                 segs = segs->next;
5369                 nskb->next = NULL;
5370                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5371         } while (segs);
5372
5373 tg3_tso_bug_end:
5374         dev_kfree_skb(skb);
5375
5376         return NETDEV_TX_OK;
5377 }
5378
5379 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5380  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5381  */
5382 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5383                                           struct net_device *dev)
5384 {
5385         struct tg3 *tp = netdev_priv(dev);
5386         u32 len, entry, base_flags, mss;
5387         struct skb_shared_info *sp;
5388         int would_hit_hwbug;
5389         dma_addr_t mapping;
5390         struct tg3_napi *tnapi = &tp->napi[0];
5391
5392         len = skb_headlen(skb);
5393
5394         /* We are running in BH disabled context with netif_tx_lock
5395          * and TX reclaim runs via tp->napi.poll inside of a software
5396          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5397          * no IRQ context deadlocks to worry about either.  Rejoice!
5398          */
5399         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5400                 if (!netif_queue_stopped(dev)) {
5401                         netif_stop_queue(dev);
5402
5403                         /* This is a hard error, log it. */
5404                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5405                                "queue awake!\n", dev->name);
5406                 }
5407                 return NETDEV_TX_BUSY;
5408         }
5409
5410         entry = tnapi->tx_prod;
5411         base_flags = 0;
5412         if (skb->ip_summed == CHECKSUM_PARTIAL)
5413                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5414         mss = 0;
5415         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5416                 struct iphdr *iph;
5417                 u32 tcp_opt_len, ip_tcp_len, hdr_len;
5418
5419                 if (skb_header_cloned(skb) &&
5420                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5421                         dev_kfree_skb(skb);
5422                         goto out_unlock;
5423                 }
5424
5425                 tcp_opt_len = tcp_optlen(skb);
5426                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5427
5428                 hdr_len = ip_tcp_len + tcp_opt_len;
5429                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5430                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5431                         return (tg3_tso_bug(tp, skb));
5432
5433                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5434                                TXD_FLAG_CPU_POST_DMA);
5435
5436                 iph = ip_hdr(skb);
5437                 iph->check = 0;
5438                 iph->tot_len = htons(mss + hdr_len);
5439                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5440                         tcp_hdr(skb)->check = 0;
5441                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5442                 } else
5443                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5444                                                                  iph->daddr, 0,
5445                                                                  IPPROTO_TCP,
5446                                                                  0);
5447
5448                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5449                         mss |= hdr_len << 9;
5450                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5451                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5452                         if (tcp_opt_len || iph->ihl > 5) {
5453                                 int tsflags;
5454
5455                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5456                                 mss |= (tsflags << 11);
5457                         }
5458                 } else {
5459                         if (tcp_opt_len || iph->ihl > 5) {
5460                                 int tsflags;
5461
5462                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5463                                 base_flags |= tsflags << 12;
5464                         }
5465                 }
5466         }
5467 #if TG3_VLAN_TAG_USED
5468         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5469                 base_flags |= (TXD_FLAG_VLAN |
5470                                (vlan_tx_tag_get(skb) << 16));
5471 #endif
5472
5473         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5474                 dev_kfree_skb(skb);
5475                 goto out_unlock;
5476         }
5477
5478         sp = skb_shinfo(skb);
5479
5480         mapping = sp->dma_head;
5481
5482         tnapi->tx_buffers[entry].skb = skb;
5483
5484         would_hit_hwbug = 0;
5485
5486         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5487                 would_hit_hwbug = 1;
5488
5489         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5490             tg3_4g_overflow_test(mapping, len))
5491                 would_hit_hwbug = 1;
5492
5493         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5494             tg3_40bit_overflow_test(tp, mapping, len))
5495                 would_hit_hwbug = 1;
5496
5497         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5498                 would_hit_hwbug = 1;
5499
5500         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5501                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5502
5503         entry = NEXT_TX(entry);
5504
5505         /* Now loop through additional data fragments, and queue them. */
5506         if (skb_shinfo(skb)->nr_frags > 0) {
5507                 unsigned int i, last;
5508
5509                 last = skb_shinfo(skb)->nr_frags - 1;
5510                 for (i = 0; i <= last; i++) {
5511                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5512
5513                         len = frag->size;
5514                         mapping = sp->dma_maps[i];
5515
5516                         tnapi->tx_buffers[entry].skb = NULL;
5517
5518                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5519                             len <= 8)
5520                                 would_hit_hwbug = 1;
5521
5522                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5523                             tg3_4g_overflow_test(mapping, len))
5524                                 would_hit_hwbug = 1;
5525
5526                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5527                             tg3_40bit_overflow_test(tp, mapping, len))
5528                                 would_hit_hwbug = 1;
5529
5530                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5531                                 tg3_set_txd(tnapi, entry, mapping, len,
5532                                             base_flags, (i == last)|(mss << 1));
5533                         else
5534                                 tg3_set_txd(tnapi, entry, mapping, len,
5535                                             base_flags, (i == last));
5536
5537                         entry = NEXT_TX(entry);
5538                 }
5539         }
5540
5541         if (would_hit_hwbug) {
5542                 u32 last_plus_one = entry;
5543                 u32 start;
5544
5545                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5546                 start &= (TG3_TX_RING_SIZE - 1);
5547
5548                 /* If the workaround fails due to memory/mapping
5549                  * failure, silently drop this packet.
5550                  */
5551                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
5552                                                 &start, base_flags, mss))
5553                         goto out_unlock;
5554
5555                 entry = start;
5556         }
5557
5558         /* Packets are ready, update Tx producer idx local and on card. */
5559         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, entry);
5560
5561         tnapi->tx_prod = entry;
5562         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5563                 netif_stop_queue(dev);
5564                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5565                         netif_wake_queue(tp->dev);
5566         }
5567
5568 out_unlock:
5569         mmiowb();
5570
5571         return NETDEV_TX_OK;
5572 }
5573
5574 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5575                                int new_mtu)
5576 {
5577         dev->mtu = new_mtu;
5578
5579         if (new_mtu > ETH_DATA_LEN) {
5580                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5581                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5582                         ethtool_op_set_tso(dev, 0);
5583                 }
5584                 else
5585                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5586         } else {
5587                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5588                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5589                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5590         }
5591 }
5592
5593 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5594 {
5595         struct tg3 *tp = netdev_priv(dev);
5596         int err;
5597
5598         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5599                 return -EINVAL;
5600
5601         if (!netif_running(dev)) {
5602                 /* We'll just catch it later when the
5603                  * device is up'd.
5604                  */
5605                 tg3_set_mtu(dev, tp, new_mtu);
5606                 return 0;
5607         }
5608
5609         tg3_phy_stop(tp);
5610
5611         tg3_netif_stop(tp);
5612
5613         tg3_full_lock(tp, 1);
5614
5615         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5616
5617         tg3_set_mtu(dev, tp, new_mtu);
5618
5619         err = tg3_restart_hw(tp, 0);
5620
5621         if (!err)
5622                 tg3_netif_start(tp);
5623
5624         tg3_full_unlock(tp);
5625
5626         if (!err)
5627                 tg3_phy_start(tp);
5628
5629         return err;
5630 }
5631
5632 static void tg3_rx_prodring_free(struct tg3 *tp,
5633                                  struct tg3_rx_prodring_set *tpr)
5634 {
5635         int i;
5636         struct ring_info *rxp;
5637
5638         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5639                 rxp = &tpr->rx_std_buffers[i];
5640
5641                 if (rxp->skb == NULL)
5642                         continue;
5643
5644                 pci_unmap_single(tp->pdev,
5645                                  pci_unmap_addr(rxp, mapping),
5646                                  tp->rx_pkt_map_sz,
5647                                  PCI_DMA_FROMDEVICE);
5648                 dev_kfree_skb_any(rxp->skb);
5649                 rxp->skb = NULL;
5650         }
5651
5652         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5653                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5654                         rxp = &tpr->rx_jmb_buffers[i];
5655
5656                         if (rxp->skb == NULL)
5657                                 continue;
5658
5659                         pci_unmap_single(tp->pdev,
5660                                          pci_unmap_addr(rxp, mapping),
5661                                          TG3_RX_JMB_MAP_SZ,
5662                                          PCI_DMA_FROMDEVICE);
5663                         dev_kfree_skb_any(rxp->skb);
5664                         rxp->skb = NULL;
5665                 }
5666         }
5667 }
5668
5669 /* Initialize tx/rx rings for packet processing.
5670  *
5671  * The chip has been shut down and the driver detached from
5672  * the networking, so no interrupts or new tx packets will
5673  * end up in the driver.  tp->{tx,}lock are held and thus
5674  * we may not sleep.
5675  */
5676 static int tg3_rx_prodring_alloc(struct tg3 *tp,
5677                                  struct tg3_rx_prodring_set *tpr)
5678 {
5679         u32 i, rx_pkt_dma_sz;
5680         struct tg3_napi *tnapi = &tp->napi[0];
5681
5682         /* Zero out all descriptors. */
5683         memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
5684
5685         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
5686         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5687             tp->dev->mtu > ETH_DATA_LEN)
5688                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5689         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
5690
5691         /* Initialize invariants of the rings, we only set this
5692          * stuff once.  This works because the card does not
5693          * write into the rx buffer posting rings.
5694          */
5695         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5696                 struct tg3_rx_buffer_desc *rxd;
5697
5698                 rxd = &tpr->rx_std[i];
5699                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
5700                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5701                 rxd->opaque = (RXD_OPAQUE_RING_STD |
5702                                (i << RXD_OPAQUE_INDEX_SHIFT));
5703         }
5704
5705         /* Now allocate fresh SKBs for each rx ring. */
5706         for (i = 0; i < tp->rx_pending; i++) {
5707                 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5708                         printk(KERN_WARNING PFX
5709                                "%s: Using a smaller RX standard ring, "
5710                                "only %d out of %d buffers were allocated "
5711                                "successfully.\n",
5712                                tp->dev->name, i, tp->rx_pending);
5713                         if (i == 0)
5714                                 goto initfail;
5715                         tp->rx_pending = i;
5716                         break;
5717                 }
5718         }
5719
5720         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
5721                 goto done;
5722
5723         memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
5724
5725         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5726                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5727                         struct tg3_rx_buffer_desc *rxd;
5728
5729                         rxd = &tpr->rx_jmb[i].std;
5730                         rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
5731                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5732                                 RXD_FLAG_JUMBO;
5733                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5734                                (i << RXD_OPAQUE_INDEX_SHIFT));
5735                 }
5736
5737                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5738                         if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_JUMBO,
5739                                              -1, i) < 0) {
5740                                 printk(KERN_WARNING PFX
5741                                        "%s: Using a smaller RX jumbo ring, "
5742                                        "only %d out of %d buffers were "
5743                                        "allocated successfully.\n",
5744                                        tp->dev->name, i, tp->rx_jumbo_pending);
5745                                 if (i == 0)
5746                                         goto initfail;
5747                                 tp->rx_jumbo_pending = i;
5748                                 break;
5749                         }
5750                 }
5751         }
5752
5753 done:
5754         return 0;
5755
5756 initfail:
5757         tg3_rx_prodring_free(tp, tpr);
5758         return -ENOMEM;
5759 }
5760
5761 static void tg3_rx_prodring_fini(struct tg3 *tp,
5762                                  struct tg3_rx_prodring_set *tpr)
5763 {
5764         kfree(tpr->rx_std_buffers);
5765         tpr->rx_std_buffers = NULL;
5766         kfree(tpr->rx_jmb_buffers);
5767         tpr->rx_jmb_buffers = NULL;
5768         if (tpr->rx_std) {
5769                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5770                                     tpr->rx_std, tpr->rx_std_mapping);
5771                 tpr->rx_std = NULL;
5772         }
5773         if (tpr->rx_jmb) {
5774