bc3af78a869ff52881077b89cf6e5e544b6e8a91
[linux-2.6.git] / drivers / net / tg3.c
1 /*
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  * Copyright (C) 2005-2010 Broadcom Corporation.
8  *
9  * Firmware is:
10  *      Derived from proprietary unpublished source code,
11  *      Copyright (C) 2000-2003 Broadcom Corporation.
12  *
13  *      Permission is hereby granted for the distribution of this firmware
14  *      data in hexadecimal or equivalent format, provided this copyright
15  *      notice is accompanying it.
16  */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/in.h>
28 #include <linux/init.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mii.h>
36 #include <linux/phy.h>
37 #include <linux/brcmphy.h>
38 #include <linux/if_vlan.h>
39 #include <linux/ip.h>
40 #include <linux/tcp.h>
41 #include <linux/workqueue.h>
42 #include <linux/prefetch.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/firmware.h>
45
46 #include <net/checksum.h>
47 #include <net/ip.h>
48
49 #include <asm/system.h>
50 #include <asm/io.h>
51 #include <asm/byteorder.h>
52 #include <asm/uaccess.h>
53
54 #ifdef CONFIG_SPARC
55 #include <asm/idprom.h>
56 #include <asm/prom.h>
57 #endif
58
59 #define BAR_0   0
60 #define BAR_2   2
61
62 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
63 #define TG3_VLAN_TAG_USED 1
64 #else
65 #define TG3_VLAN_TAG_USED 0
66 #endif
67
68 #include "tg3.h"
69
70 #define DRV_MODULE_NAME         "tg3"
71 #define TG3_MAJ_NUM                     3
72 #define TG3_MIN_NUM                     113
73 #define DRV_MODULE_VERSION      \
74         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
75 #define DRV_MODULE_RELDATE      "August 2, 2010"
76
77 #define TG3_DEF_MAC_MODE        0
78 #define TG3_DEF_RX_MODE         0
79 #define TG3_DEF_TX_MODE         0
80 #define TG3_DEF_MSG_ENABLE        \
81         (NETIF_MSG_DRV          | \
82          NETIF_MSG_PROBE        | \
83          NETIF_MSG_LINK         | \
84          NETIF_MSG_TIMER        | \
85          NETIF_MSG_IFDOWN       | \
86          NETIF_MSG_IFUP         | \
87          NETIF_MSG_RX_ERR       | \
88          NETIF_MSG_TX_ERR)
89
90 /* length of time before we decide the hardware is borked,
91  * and dev->tx_timeout() should be called to fix the problem
92  */
93 #define TG3_TX_TIMEOUT                  (5 * HZ)
94
95 /* hardware minimum and maximum for a single frame's data payload */
96 #define TG3_MIN_MTU                     60
97 #define TG3_MAX_MTU(tp) \
98         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
99
100 /* These numbers seem to be hard coded in the NIC firmware somehow.
101  * You can't change the ring sizes, but you can change where you place
102  * them in the NIC onboard memory.
103  */
104 #define TG3_RX_RING_SIZE                512
105 #define TG3_DEF_RX_RING_PENDING         200
106 #define TG3_RX_JUMBO_RING_SIZE          256
107 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
108 #define TG3_RSS_INDIR_TBL_SIZE          128
109
110 /* Do not place this n-ring entries value into the tp struct itself,
111  * we really want to expose these constants to GCC so that modulo et
112  * al.  operations are done with shifts and masks instead of with
113  * hw multiply/modulo instructions.  Another solution would be to
114  * replace things like '% foo' with '& (foo - 1)'.
115  */
116 #define TG3_RX_RCB_RING_SIZE(tp)        \
117         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
118           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
119
120 #define TG3_TX_RING_SIZE                512
121 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
122
123 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
124                                  TG3_RX_RING_SIZE)
125 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
126                                  TG3_RX_JUMBO_RING_SIZE)
127 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
128                                  TG3_RX_RCB_RING_SIZE(tp))
129 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
130                                  TG3_TX_RING_SIZE)
131 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
132
133 #define TG3_RX_DMA_ALIGN                16
134 #define TG3_RX_HEADROOM                 ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
135
136 #define TG3_DMA_BYTE_ENAB               64
137
138 #define TG3_RX_STD_DMA_SZ               1536
139 #define TG3_RX_JMB_DMA_SZ               9046
140
141 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
142
143 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
144 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
145
146 #define TG3_RX_STD_BUFF_RING_SIZE \
147         (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
148
149 #define TG3_RX_JMB_BUFF_RING_SIZE \
150         (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
151
152 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
153  * that are at least dword aligned when used in PCIX mode.  The driver
154  * works around this bug by double copying the packet.  This workaround
155  * is built into the normal double copy length check for efficiency.
156  *
157  * However, the double copy is only necessary on those architectures
158  * where unaligned memory accesses are inefficient.  For those architectures
159  * where unaligned memory accesses incur little penalty, we can reintegrate
160  * the 5701 in the normal rx path.  Doing so saves a device structure
161  * dereference by hardcoding the double copy threshold in place.
162  */
163 #define TG3_RX_COPY_THRESHOLD           256
164 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
165         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
166 #else
167         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
168 #endif
169
170 /* minimum number of free TX descriptors required to wake up TX process */
171 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
172
173 #define TG3_RAW_IP_ALIGN 2
174
175 /* number of ETHTOOL_GSTATS u64's */
176 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
177
178 #define TG3_NUM_TEST            6
179
180 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
181
182 #define FIRMWARE_TG3            "tigon/tg3.bin"
183 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
184 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
185
186 static char version[] __devinitdata =
187         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
188
189 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
190 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
191 MODULE_LICENSE("GPL");
192 MODULE_VERSION(DRV_MODULE_VERSION);
193 MODULE_FIRMWARE(FIRMWARE_TG3);
194 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
195 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
196
197 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
198 module_param(tg3_debug, int, 0);
199 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
200
201 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
268         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
269         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
270         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
271         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
272         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
273         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
274         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
275         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
276         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
277         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
278         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
279         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
280         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
281         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
282         {}
283 };
284
285 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
286
287 static const struct {
288         const char string[ETH_GSTRING_LEN];
289 } ethtool_stats_keys[TG3_NUM_STATS] = {
290         { "rx_octets" },
291         { "rx_fragments" },
292         { "rx_ucast_packets" },
293         { "rx_mcast_packets" },
294         { "rx_bcast_packets" },
295         { "rx_fcs_errors" },
296         { "rx_align_errors" },
297         { "rx_xon_pause_rcvd" },
298         { "rx_xoff_pause_rcvd" },
299         { "rx_mac_ctrl_rcvd" },
300         { "rx_xoff_entered" },
301         { "rx_frame_too_long_errors" },
302         { "rx_jabbers" },
303         { "rx_undersize_packets" },
304         { "rx_in_length_errors" },
305         { "rx_out_length_errors" },
306         { "rx_64_or_less_octet_packets" },
307         { "rx_65_to_127_octet_packets" },
308         { "rx_128_to_255_octet_packets" },
309         { "rx_256_to_511_octet_packets" },
310         { "rx_512_to_1023_octet_packets" },
311         { "rx_1024_to_1522_octet_packets" },
312         { "rx_1523_to_2047_octet_packets" },
313         { "rx_2048_to_4095_octet_packets" },
314         { "rx_4096_to_8191_octet_packets" },
315         { "rx_8192_to_9022_octet_packets" },
316
317         { "tx_octets" },
318         { "tx_collisions" },
319
320         { "tx_xon_sent" },
321         { "tx_xoff_sent" },
322         { "tx_flow_control" },
323         { "tx_mac_errors" },
324         { "tx_single_collisions" },
325         { "tx_mult_collisions" },
326         { "tx_deferred" },
327         { "tx_excessive_collisions" },
328         { "tx_late_collisions" },
329         { "tx_collide_2times" },
330         { "tx_collide_3times" },
331         { "tx_collide_4times" },
332         { "tx_collide_5times" },
333         { "tx_collide_6times" },
334         { "tx_collide_7times" },
335         { "tx_collide_8times" },
336         { "tx_collide_9times" },
337         { "tx_collide_10times" },
338         { "tx_collide_11times" },
339         { "tx_collide_12times" },
340         { "tx_collide_13times" },
341         { "tx_collide_14times" },
342         { "tx_collide_15times" },
343         { "tx_ucast_packets" },
344         { "tx_mcast_packets" },
345         { "tx_bcast_packets" },
346         { "tx_carrier_sense_errors" },
347         { "tx_discards" },
348         { "tx_errors" },
349
350         { "dma_writeq_full" },
351         { "dma_write_prioq_full" },
352         { "rxbds_empty" },
353         { "rx_discards" },
354         { "rx_errors" },
355         { "rx_threshold_hit" },
356
357         { "dma_readq_full" },
358         { "dma_read_prioq_full" },
359         { "tx_comp_queue_full" },
360
361         { "ring_set_send_prod_index" },
362         { "ring_status_update" },
363         { "nic_irqs" },
364         { "nic_avoided_irqs" },
365         { "nic_tx_threshold_hit" }
366 };
367
368 static const struct {
369         const char string[ETH_GSTRING_LEN];
370 } ethtool_test_keys[TG3_NUM_TEST] = {
371         { "nvram test     (online) " },
372         { "link test      (online) " },
373         { "register test  (offline)" },
374         { "memory test    (offline)" },
375         { "loopback test  (offline)" },
376         { "interrupt test (offline)" },
377 };
378
379 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
380 {
381         writel(val, tp->regs + off);
382 }
383
384 static u32 tg3_read32(struct tg3 *tp, u32 off)
385 {
386         return readl(tp->regs + off);
387 }
388
389 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
390 {
391         writel(val, tp->aperegs + off);
392 }
393
394 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
395 {
396         return readl(tp->aperegs + off);
397 }
398
399 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
400 {
401         unsigned long flags;
402
403         spin_lock_irqsave(&tp->indirect_lock, flags);
404         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
405         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
406         spin_unlock_irqrestore(&tp->indirect_lock, flags);
407 }
408
409 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
410 {
411         writel(val, tp->regs + off);
412         readl(tp->regs + off);
413 }
414
415 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
416 {
417         unsigned long flags;
418         u32 val;
419
420         spin_lock_irqsave(&tp->indirect_lock, flags);
421         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
422         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
423         spin_unlock_irqrestore(&tp->indirect_lock, flags);
424         return val;
425 }
426
427 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
428 {
429         unsigned long flags;
430
431         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
432                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
433                                        TG3_64BIT_REG_LOW, val);
434                 return;
435         }
436         if (off == TG3_RX_STD_PROD_IDX_REG) {
437                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
438                                        TG3_64BIT_REG_LOW, val);
439                 return;
440         }
441
442         spin_lock_irqsave(&tp->indirect_lock, flags);
443         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
444         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
445         spin_unlock_irqrestore(&tp->indirect_lock, flags);
446
447         /* In indirect mode when disabling interrupts, we also need
448          * to clear the interrupt bit in the GRC local ctrl register.
449          */
450         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
451             (val == 0x1)) {
452                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
453                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
454         }
455 }
456
457 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
458 {
459         unsigned long flags;
460         u32 val;
461
462         spin_lock_irqsave(&tp->indirect_lock, flags);
463         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
464         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
465         spin_unlock_irqrestore(&tp->indirect_lock, flags);
466         return val;
467 }
468
469 /* usec_wait specifies the wait time in usec when writing to certain registers
470  * where it is unsafe to read back the register without some delay.
471  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
472  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
473  */
474 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
475 {
476         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
477             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
478                 /* Non-posted methods */
479                 tp->write32(tp, off, val);
480         else {
481                 /* Posted method */
482                 tg3_write32(tp, off, val);
483                 if (usec_wait)
484                         udelay(usec_wait);
485                 tp->read32(tp, off);
486         }
487         /* Wait again after the read for the posted method to guarantee that
488          * the wait time is met.
489          */
490         if (usec_wait)
491                 udelay(usec_wait);
492 }
493
494 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
495 {
496         tp->write32_mbox(tp, off, val);
497         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
498             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
499                 tp->read32_mbox(tp, off);
500 }
501
502 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
503 {
504         void __iomem *mbox = tp->regs + off;
505         writel(val, mbox);
506         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
507                 writel(val, mbox);
508         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
509                 readl(mbox);
510 }
511
512 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
513 {
514         return readl(tp->regs + off + GRCMBOX_BASE);
515 }
516
517 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
518 {
519         writel(val, tp->regs + off + GRCMBOX_BASE);
520 }
521
522 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
523 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
524 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
525 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
526 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
527
528 #define tw32(reg, val)                  tp->write32(tp, reg, val)
529 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
530 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
531 #define tr32(reg)                       tp->read32(tp, reg)
532
533 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
534 {
535         unsigned long flags;
536
537         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
538             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
539                 return;
540
541         spin_lock_irqsave(&tp->indirect_lock, flags);
542         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
543                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
544                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
545
546                 /* Always leave this as zero. */
547                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
548         } else {
549                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
550                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
551
552                 /* Always leave this as zero. */
553                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
554         }
555         spin_unlock_irqrestore(&tp->indirect_lock, flags);
556 }
557
558 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
559 {
560         unsigned long flags;
561
562         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
563             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
564                 *val = 0;
565                 return;
566         }
567
568         spin_lock_irqsave(&tp->indirect_lock, flags);
569         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
570                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
571                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
572
573                 /* Always leave this as zero. */
574                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
575         } else {
576                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
577                 *val = tr32(TG3PCI_MEM_WIN_DATA);
578
579                 /* Always leave this as zero. */
580                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
581         }
582         spin_unlock_irqrestore(&tp->indirect_lock, flags);
583 }
584
585 static void tg3_ape_lock_init(struct tg3 *tp)
586 {
587         int i;
588         u32 regbase;
589
590         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
591                 regbase = TG3_APE_LOCK_GRANT;
592         else
593                 regbase = TG3_APE_PER_LOCK_GRANT;
594
595         /* Make sure the driver hasn't any stale locks. */
596         for (i = 0; i < 8; i++)
597                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
598 }
599
600 static int tg3_ape_lock(struct tg3 *tp, int locknum)
601 {
602         int i, off;
603         int ret = 0;
604         u32 status, req, gnt;
605
606         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
607                 return 0;
608
609         switch (locknum) {
610         case TG3_APE_LOCK_GRC:
611         case TG3_APE_LOCK_MEM:
612                 break;
613         default:
614                 return -EINVAL;
615         }
616
617         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
618                 req = TG3_APE_LOCK_REQ;
619                 gnt = TG3_APE_LOCK_GRANT;
620         } else {
621                 req = TG3_APE_PER_LOCK_REQ;
622                 gnt = TG3_APE_PER_LOCK_GRANT;
623         }
624
625         off = 4 * locknum;
626
627         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
628
629         /* Wait for up to 1 millisecond to acquire lock. */
630         for (i = 0; i < 100; i++) {
631                 status = tg3_ape_read32(tp, gnt + off);
632                 if (status == APE_LOCK_GRANT_DRIVER)
633                         break;
634                 udelay(10);
635         }
636
637         if (status != APE_LOCK_GRANT_DRIVER) {
638                 /* Revoke the lock request. */
639                 tg3_ape_write32(tp, gnt + off,
640                                 APE_LOCK_GRANT_DRIVER);
641
642                 ret = -EBUSY;
643         }
644
645         return ret;
646 }
647
648 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
649 {
650         u32 gnt;
651
652         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
653                 return;
654
655         switch (locknum) {
656         case TG3_APE_LOCK_GRC:
657         case TG3_APE_LOCK_MEM:
658                 break;
659         default:
660                 return;
661         }
662
663         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
664                 gnt = TG3_APE_LOCK_GRANT;
665         else
666                 gnt = TG3_APE_PER_LOCK_GRANT;
667
668         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
669 }
670
671 static void tg3_disable_ints(struct tg3 *tp)
672 {
673         int i;
674
675         tw32(TG3PCI_MISC_HOST_CTRL,
676              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
677         for (i = 0; i < tp->irq_max; i++)
678                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
679 }
680
681 static void tg3_enable_ints(struct tg3 *tp)
682 {
683         int i;
684
685         tp->irq_sync = 0;
686         wmb();
687
688         tw32(TG3PCI_MISC_HOST_CTRL,
689              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
690
691         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
692         for (i = 0; i < tp->irq_cnt; i++) {
693                 struct tg3_napi *tnapi = &tp->napi[i];
694
695                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
696                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
697                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
698
699                 tp->coal_now |= tnapi->coal_now;
700         }
701
702         /* Force an initial interrupt */
703         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
704             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
705                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
706         else
707                 tw32(HOSTCC_MODE, tp->coal_now);
708
709         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
710 }
711
712 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
713 {
714         struct tg3 *tp = tnapi->tp;
715         struct tg3_hw_status *sblk = tnapi->hw_status;
716         unsigned int work_exists = 0;
717
718         /* check for phy events */
719         if (!(tp->tg3_flags &
720               (TG3_FLAG_USE_LINKCHG_REG |
721                TG3_FLAG_POLL_SERDES))) {
722                 if (sblk->status & SD_STATUS_LINK_CHG)
723                         work_exists = 1;
724         }
725         /* check for RX/TX work to do */
726         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
727             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
728                 work_exists = 1;
729
730         return work_exists;
731 }
732
733 /* tg3_int_reenable
734  *  similar to tg3_enable_ints, but it accurately determines whether there
735  *  is new work pending and can return without flushing the PIO write
736  *  which reenables interrupts
737  */
738 static void tg3_int_reenable(struct tg3_napi *tnapi)
739 {
740         struct tg3 *tp = tnapi->tp;
741
742         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
743         mmiowb();
744
745         /* When doing tagged status, this work check is unnecessary.
746          * The last_tag we write above tells the chip which piece of
747          * work we've completed.
748          */
749         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
750             tg3_has_work(tnapi))
751                 tw32(HOSTCC_MODE, tp->coalesce_mode |
752                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
753 }
754
755 static void tg3_napi_disable(struct tg3 *tp)
756 {
757         int i;
758
759         for (i = tp->irq_cnt - 1; i >= 0; i--)
760                 napi_disable(&tp->napi[i].napi);
761 }
762
763 static void tg3_napi_enable(struct tg3 *tp)
764 {
765         int i;
766
767         for (i = 0; i < tp->irq_cnt; i++)
768                 napi_enable(&tp->napi[i].napi);
769 }
770
771 static inline void tg3_netif_stop(struct tg3 *tp)
772 {
773         tp->dev->trans_start = jiffies; /* prevent tx timeout */
774         tg3_napi_disable(tp);
775         netif_tx_disable(tp->dev);
776 }
777
778 static inline void tg3_netif_start(struct tg3 *tp)
779 {
780         /* NOTE: unconditional netif_tx_wake_all_queues is only
781          * appropriate so long as all callers are assured to
782          * have free tx slots (such as after tg3_init_hw)
783          */
784         netif_tx_wake_all_queues(tp->dev);
785
786         tg3_napi_enable(tp);
787         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
788         tg3_enable_ints(tp);
789 }
790
791 static void tg3_switch_clocks(struct tg3 *tp)
792 {
793         u32 clock_ctrl;
794         u32 orig_clock_ctrl;
795
796         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
797             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
798                 return;
799
800         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
801
802         orig_clock_ctrl = clock_ctrl;
803         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
804                        CLOCK_CTRL_CLKRUN_OENABLE |
805                        0x1f);
806         tp->pci_clock_ctrl = clock_ctrl;
807
808         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
809                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
810                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
811                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
812                 }
813         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
814                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
815                             clock_ctrl |
816                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
817                             40);
818                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
819                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
820                             40);
821         }
822         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
823 }
824
825 #define PHY_BUSY_LOOPS  5000
826
827 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
828 {
829         u32 frame_val;
830         unsigned int loops;
831         int ret;
832
833         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
834                 tw32_f(MAC_MI_MODE,
835                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
836                 udelay(80);
837         }
838
839         *val = 0x0;
840
841         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
842                       MI_COM_PHY_ADDR_MASK);
843         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
844                       MI_COM_REG_ADDR_MASK);
845         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
846
847         tw32_f(MAC_MI_COM, frame_val);
848
849         loops = PHY_BUSY_LOOPS;
850         while (loops != 0) {
851                 udelay(10);
852                 frame_val = tr32(MAC_MI_COM);
853
854                 if ((frame_val & MI_COM_BUSY) == 0) {
855                         udelay(5);
856                         frame_val = tr32(MAC_MI_COM);
857                         break;
858                 }
859                 loops -= 1;
860         }
861
862         ret = -EBUSY;
863         if (loops != 0) {
864                 *val = frame_val & MI_COM_DATA_MASK;
865                 ret = 0;
866         }
867
868         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
869                 tw32_f(MAC_MI_MODE, tp->mi_mode);
870                 udelay(80);
871         }
872
873         return ret;
874 }
875
876 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
877 {
878         u32 frame_val;
879         unsigned int loops;
880         int ret;
881
882         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
883             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
884                 return 0;
885
886         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
887                 tw32_f(MAC_MI_MODE,
888                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
889                 udelay(80);
890         }
891
892         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
893                       MI_COM_PHY_ADDR_MASK);
894         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
895                       MI_COM_REG_ADDR_MASK);
896         frame_val |= (val & MI_COM_DATA_MASK);
897         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
898
899         tw32_f(MAC_MI_COM, frame_val);
900
901         loops = PHY_BUSY_LOOPS;
902         while (loops != 0) {
903                 udelay(10);
904                 frame_val = tr32(MAC_MI_COM);
905                 if ((frame_val & MI_COM_BUSY) == 0) {
906                         udelay(5);
907                         frame_val = tr32(MAC_MI_COM);
908                         break;
909                 }
910                 loops -= 1;
911         }
912
913         ret = -EBUSY;
914         if (loops != 0)
915                 ret = 0;
916
917         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
918                 tw32_f(MAC_MI_MODE, tp->mi_mode);
919                 udelay(80);
920         }
921
922         return ret;
923 }
924
925 static int tg3_bmcr_reset(struct tg3 *tp)
926 {
927         u32 phy_control;
928         int limit, err;
929
930         /* OK, reset it, and poll the BMCR_RESET bit until it
931          * clears or we time out.
932          */
933         phy_control = BMCR_RESET;
934         err = tg3_writephy(tp, MII_BMCR, phy_control);
935         if (err != 0)
936                 return -EBUSY;
937
938         limit = 5000;
939         while (limit--) {
940                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
941                 if (err != 0)
942                         return -EBUSY;
943
944                 if ((phy_control & BMCR_RESET) == 0) {
945                         udelay(40);
946                         break;
947                 }
948                 udelay(10);
949         }
950         if (limit < 0)
951                 return -EBUSY;
952
953         return 0;
954 }
955
956 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
957 {
958         struct tg3 *tp = bp->priv;
959         u32 val;
960
961         spin_lock_bh(&tp->lock);
962
963         if (tg3_readphy(tp, reg, &val))
964                 val = -EIO;
965
966         spin_unlock_bh(&tp->lock);
967
968         return val;
969 }
970
971 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
972 {
973         struct tg3 *tp = bp->priv;
974         u32 ret = 0;
975
976         spin_lock_bh(&tp->lock);
977
978         if (tg3_writephy(tp, reg, val))
979                 ret = -EIO;
980
981         spin_unlock_bh(&tp->lock);
982
983         return ret;
984 }
985
986 static int tg3_mdio_reset(struct mii_bus *bp)
987 {
988         return 0;
989 }
990
991 static void tg3_mdio_config_5785(struct tg3 *tp)
992 {
993         u32 val;
994         struct phy_device *phydev;
995
996         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
997         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
998         case PHY_ID_BCM50610:
999         case PHY_ID_BCM50610M:
1000                 val = MAC_PHYCFG2_50610_LED_MODES;
1001                 break;
1002         case PHY_ID_BCMAC131:
1003                 val = MAC_PHYCFG2_AC131_LED_MODES;
1004                 break;
1005         case PHY_ID_RTL8211C:
1006                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1007                 break;
1008         case PHY_ID_RTL8201E:
1009                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1010                 break;
1011         default:
1012                 return;
1013         }
1014
1015         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1016                 tw32(MAC_PHYCFG2, val);
1017
1018                 val = tr32(MAC_PHYCFG1);
1019                 val &= ~(MAC_PHYCFG1_RGMII_INT |
1020                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1021                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1022                 tw32(MAC_PHYCFG1, val);
1023
1024                 return;
1025         }
1026
1027         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
1028                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1029                        MAC_PHYCFG2_FMODE_MASK_MASK |
1030                        MAC_PHYCFG2_GMODE_MASK_MASK |
1031                        MAC_PHYCFG2_ACT_MASK_MASK   |
1032                        MAC_PHYCFG2_QUAL_MASK_MASK |
1033                        MAC_PHYCFG2_INBAND_ENABLE;
1034
1035         tw32(MAC_PHYCFG2, val);
1036
1037         val = tr32(MAC_PHYCFG1);
1038         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1039                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1040         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1041                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1042                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1043                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1044                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1045         }
1046         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1047                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1048         tw32(MAC_PHYCFG1, val);
1049
1050         val = tr32(MAC_EXT_RGMII_MODE);
1051         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1052                  MAC_RGMII_MODE_RX_QUALITY |
1053                  MAC_RGMII_MODE_RX_ACTIVITY |
1054                  MAC_RGMII_MODE_RX_ENG_DET |
1055                  MAC_RGMII_MODE_TX_ENABLE |
1056                  MAC_RGMII_MODE_TX_LOWPWR |
1057                  MAC_RGMII_MODE_TX_RESET);
1058         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1059                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1060                         val |= MAC_RGMII_MODE_RX_INT_B |
1061                                MAC_RGMII_MODE_RX_QUALITY |
1062                                MAC_RGMII_MODE_RX_ACTIVITY |
1063                                MAC_RGMII_MODE_RX_ENG_DET;
1064                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1065                         val |= MAC_RGMII_MODE_TX_ENABLE |
1066                                MAC_RGMII_MODE_TX_LOWPWR |
1067                                MAC_RGMII_MODE_TX_RESET;
1068         }
1069         tw32(MAC_EXT_RGMII_MODE, val);
1070 }
1071
1072 static void tg3_mdio_start(struct tg3 *tp)
1073 {
1074         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1075         tw32_f(MAC_MI_MODE, tp->mi_mode);
1076         udelay(80);
1077
1078         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1079             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1080                 tg3_mdio_config_5785(tp);
1081 }
1082
1083 static int tg3_mdio_init(struct tg3 *tp)
1084 {
1085         int i;
1086         u32 reg;
1087         struct phy_device *phydev;
1088
1089         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1090             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
1091                 u32 is_serdes;
1092
1093                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1094
1095                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1096                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1097                 else
1098                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1099                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1100                 if (is_serdes)
1101                         tp->phy_addr += 7;
1102         } else
1103                 tp->phy_addr = TG3_PHY_MII_ADDR;
1104
1105         tg3_mdio_start(tp);
1106
1107         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1108             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1109                 return 0;
1110
1111         tp->mdio_bus = mdiobus_alloc();
1112         if (tp->mdio_bus == NULL)
1113                 return -ENOMEM;
1114
1115         tp->mdio_bus->name     = "tg3 mdio bus";
1116         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1117                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1118         tp->mdio_bus->priv     = tp;
1119         tp->mdio_bus->parent   = &tp->pdev->dev;
1120         tp->mdio_bus->read     = &tg3_mdio_read;
1121         tp->mdio_bus->write    = &tg3_mdio_write;
1122         tp->mdio_bus->reset    = &tg3_mdio_reset;
1123         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1124         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1125
1126         for (i = 0; i < PHY_MAX_ADDR; i++)
1127                 tp->mdio_bus->irq[i] = PHY_POLL;
1128
1129         /* The bus registration will look for all the PHYs on the mdio bus.
1130          * Unfortunately, it does not ensure the PHY is powered up before
1131          * accessing the PHY ID registers.  A chip reset is the
1132          * quickest way to bring the device back to an operational state..
1133          */
1134         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1135                 tg3_bmcr_reset(tp);
1136
1137         i = mdiobus_register(tp->mdio_bus);
1138         if (i) {
1139                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1140                 mdiobus_free(tp->mdio_bus);
1141                 return i;
1142         }
1143
1144         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1145
1146         if (!phydev || !phydev->drv) {
1147                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1148                 mdiobus_unregister(tp->mdio_bus);
1149                 mdiobus_free(tp->mdio_bus);
1150                 return -ENODEV;
1151         }
1152
1153         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1154         case PHY_ID_BCM57780:
1155                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1156                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1157                 break;
1158         case PHY_ID_BCM50610:
1159         case PHY_ID_BCM50610M:
1160                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1161                                      PHY_BRCM_RX_REFCLK_UNUSED |
1162                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1163                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1164                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1165                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1166                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1167                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1168                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1169                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1170                 /* fallthru */
1171         case PHY_ID_RTL8211C:
1172                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1173                 break;
1174         case PHY_ID_RTL8201E:
1175         case PHY_ID_BCMAC131:
1176                 phydev->interface = PHY_INTERFACE_MODE_MII;
1177                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1178                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1179                 break;
1180         }
1181
1182         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1183
1184         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1185                 tg3_mdio_config_5785(tp);
1186
1187         return 0;
1188 }
1189
1190 static void tg3_mdio_fini(struct tg3 *tp)
1191 {
1192         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1193                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1194                 mdiobus_unregister(tp->mdio_bus);
1195                 mdiobus_free(tp->mdio_bus);
1196         }
1197 }
1198
1199 /* tp->lock is held. */
1200 static inline void tg3_generate_fw_event(struct tg3 *tp)
1201 {
1202         u32 val;
1203
1204         val = tr32(GRC_RX_CPU_EVENT);
1205         val |= GRC_RX_CPU_DRIVER_EVENT;
1206         tw32_f(GRC_RX_CPU_EVENT, val);
1207
1208         tp->last_event_jiffies = jiffies;
1209 }
1210
1211 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1212
1213 /* tp->lock is held. */
1214 static void tg3_wait_for_event_ack(struct tg3 *tp)
1215 {
1216         int i;
1217         unsigned int delay_cnt;
1218         long time_remain;
1219
1220         /* If enough time has passed, no wait is necessary. */
1221         time_remain = (long)(tp->last_event_jiffies + 1 +
1222                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1223                       (long)jiffies;
1224         if (time_remain < 0)
1225                 return;
1226
1227         /* Check if we can shorten the wait time. */
1228         delay_cnt = jiffies_to_usecs(time_remain);
1229         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1230                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1231         delay_cnt = (delay_cnt >> 3) + 1;
1232
1233         for (i = 0; i < delay_cnt; i++) {
1234                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1235                         break;
1236                 udelay(8);
1237         }
1238 }
1239
1240 /* tp->lock is held. */
1241 static void tg3_ump_link_report(struct tg3 *tp)
1242 {
1243         u32 reg;
1244         u32 val;
1245
1246         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1247             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1248                 return;
1249
1250         tg3_wait_for_event_ack(tp);
1251
1252         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1253
1254         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1255
1256         val = 0;
1257         if (!tg3_readphy(tp, MII_BMCR, &reg))
1258                 val = reg << 16;
1259         if (!tg3_readphy(tp, MII_BMSR, &reg))
1260                 val |= (reg & 0xffff);
1261         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1262
1263         val = 0;
1264         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1265                 val = reg << 16;
1266         if (!tg3_readphy(tp, MII_LPA, &reg))
1267                 val |= (reg & 0xffff);
1268         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1269
1270         val = 0;
1271         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1272                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1273                         val = reg << 16;
1274                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1275                         val |= (reg & 0xffff);
1276         }
1277         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1278
1279         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1280                 val = reg << 16;
1281         else
1282                 val = 0;
1283         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1284
1285         tg3_generate_fw_event(tp);
1286 }
1287
1288 static void tg3_link_report(struct tg3 *tp)
1289 {
1290         if (!netif_carrier_ok(tp->dev)) {
1291                 netif_info(tp, link, tp->dev, "Link is down\n");
1292                 tg3_ump_link_report(tp);
1293         } else if (netif_msg_link(tp)) {
1294                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1295                             (tp->link_config.active_speed == SPEED_1000 ?
1296                              1000 :
1297                              (tp->link_config.active_speed == SPEED_100 ?
1298                               100 : 10)),
1299                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1300                              "full" : "half"));
1301
1302                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1303                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1304                             "on" : "off",
1305                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1306                             "on" : "off");
1307                 tg3_ump_link_report(tp);
1308         }
1309 }
1310
1311 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1312 {
1313         u16 miireg;
1314
1315         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1316                 miireg = ADVERTISE_PAUSE_CAP;
1317         else if (flow_ctrl & FLOW_CTRL_TX)
1318                 miireg = ADVERTISE_PAUSE_ASYM;
1319         else if (flow_ctrl & FLOW_CTRL_RX)
1320                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1321         else
1322                 miireg = 0;
1323
1324         return miireg;
1325 }
1326
1327 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1328 {
1329         u16 miireg;
1330
1331         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1332                 miireg = ADVERTISE_1000XPAUSE;
1333         else if (flow_ctrl & FLOW_CTRL_TX)
1334                 miireg = ADVERTISE_1000XPSE_ASYM;
1335         else if (flow_ctrl & FLOW_CTRL_RX)
1336                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1337         else
1338                 miireg = 0;
1339
1340         return miireg;
1341 }
1342
1343 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1344 {
1345         u8 cap = 0;
1346
1347         if (lcladv & ADVERTISE_1000XPAUSE) {
1348                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1349                         if (rmtadv & LPA_1000XPAUSE)
1350                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1351                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1352                                 cap = FLOW_CTRL_RX;
1353                 } else {
1354                         if (rmtadv & LPA_1000XPAUSE)
1355                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1356                 }
1357         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1358                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1359                         cap = FLOW_CTRL_TX;
1360         }
1361
1362         return cap;
1363 }
1364
1365 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1366 {
1367         u8 autoneg;
1368         u8 flowctrl = 0;
1369         u32 old_rx_mode = tp->rx_mode;
1370         u32 old_tx_mode = tp->tx_mode;
1371
1372         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1373                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1374         else
1375                 autoneg = tp->link_config.autoneg;
1376
1377         if (autoneg == AUTONEG_ENABLE &&
1378             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1379                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1380                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1381                 else
1382                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1383         } else
1384                 flowctrl = tp->link_config.flowctrl;
1385
1386         tp->link_config.active_flowctrl = flowctrl;
1387
1388         if (flowctrl & FLOW_CTRL_RX)
1389                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1390         else
1391                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1392
1393         if (old_rx_mode != tp->rx_mode)
1394                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1395
1396         if (flowctrl & FLOW_CTRL_TX)
1397                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1398         else
1399                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1400
1401         if (old_tx_mode != tp->tx_mode)
1402                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1403 }
1404
1405 static void tg3_adjust_link(struct net_device *dev)
1406 {
1407         u8 oldflowctrl, linkmesg = 0;
1408         u32 mac_mode, lcl_adv, rmt_adv;
1409         struct tg3 *tp = netdev_priv(dev);
1410         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1411
1412         spin_lock_bh(&tp->lock);
1413
1414         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1415                                     MAC_MODE_HALF_DUPLEX);
1416
1417         oldflowctrl = tp->link_config.active_flowctrl;
1418
1419         if (phydev->link) {
1420                 lcl_adv = 0;
1421                 rmt_adv = 0;
1422
1423                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1424                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1425                 else if (phydev->speed == SPEED_1000 ||
1426                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1427                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1428                 else
1429                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1430
1431                 if (phydev->duplex == DUPLEX_HALF)
1432                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1433                 else {
1434                         lcl_adv = tg3_advert_flowctrl_1000T(
1435                                   tp->link_config.flowctrl);
1436
1437                         if (phydev->pause)
1438                                 rmt_adv = LPA_PAUSE_CAP;
1439                         if (phydev->asym_pause)
1440                                 rmt_adv |= LPA_PAUSE_ASYM;
1441                 }
1442
1443                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1444         } else
1445                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1446
1447         if (mac_mode != tp->mac_mode) {
1448                 tp->mac_mode = mac_mode;
1449                 tw32_f(MAC_MODE, tp->mac_mode);
1450                 udelay(40);
1451         }
1452
1453         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1454                 if (phydev->speed == SPEED_10)
1455                         tw32(MAC_MI_STAT,
1456                              MAC_MI_STAT_10MBPS_MODE |
1457                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1458                 else
1459                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1460         }
1461
1462         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1463                 tw32(MAC_TX_LENGTHS,
1464                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1465                       (6 << TX_LENGTHS_IPG_SHIFT) |
1466                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1467         else
1468                 tw32(MAC_TX_LENGTHS,
1469                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1470                       (6 << TX_LENGTHS_IPG_SHIFT) |
1471                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1472
1473         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1474             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1475             phydev->speed != tp->link_config.active_speed ||
1476             phydev->duplex != tp->link_config.active_duplex ||
1477             oldflowctrl != tp->link_config.active_flowctrl)
1478                 linkmesg = 1;
1479
1480         tp->link_config.active_speed = phydev->speed;
1481         tp->link_config.active_duplex = phydev->duplex;
1482
1483         spin_unlock_bh(&tp->lock);
1484
1485         if (linkmesg)
1486                 tg3_link_report(tp);
1487 }
1488
1489 static int tg3_phy_init(struct tg3 *tp)
1490 {
1491         struct phy_device *phydev;
1492
1493         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1494                 return 0;
1495
1496         /* Bring the PHY back to a known state. */
1497         tg3_bmcr_reset(tp);
1498
1499         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1500
1501         /* Attach the MAC to the PHY. */
1502         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1503                              phydev->dev_flags, phydev->interface);
1504         if (IS_ERR(phydev)) {
1505                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1506                 return PTR_ERR(phydev);
1507         }
1508
1509         /* Mask with MAC supported features. */
1510         switch (phydev->interface) {
1511         case PHY_INTERFACE_MODE_GMII:
1512         case PHY_INTERFACE_MODE_RGMII:
1513                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1514                         phydev->supported &= (PHY_GBIT_FEATURES |
1515                                               SUPPORTED_Pause |
1516                                               SUPPORTED_Asym_Pause);
1517                         break;
1518                 }
1519                 /* fallthru */
1520         case PHY_INTERFACE_MODE_MII:
1521                 phydev->supported &= (PHY_BASIC_FEATURES |
1522                                       SUPPORTED_Pause |
1523                                       SUPPORTED_Asym_Pause);
1524                 break;
1525         default:
1526                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1527                 return -EINVAL;
1528         }
1529
1530         tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1531
1532         phydev->advertising = phydev->supported;
1533
1534         return 0;
1535 }
1536
1537 static void tg3_phy_start(struct tg3 *tp)
1538 {
1539         struct phy_device *phydev;
1540
1541         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1542                 return;
1543
1544         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1545
1546         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1547                 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1548                 phydev->speed = tp->link_config.orig_speed;
1549                 phydev->duplex = tp->link_config.orig_duplex;
1550                 phydev->autoneg = tp->link_config.orig_autoneg;
1551                 phydev->advertising = tp->link_config.orig_advertising;
1552         }
1553
1554         phy_start(phydev);
1555
1556         phy_start_aneg(phydev);
1557 }
1558
1559 static void tg3_phy_stop(struct tg3 *tp)
1560 {
1561         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1562                 return;
1563
1564         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1565 }
1566
1567 static void tg3_phy_fini(struct tg3 *tp)
1568 {
1569         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1570                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1571                 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1572         }
1573 }
1574
1575 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1576 {
1577         int err;
1578
1579         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1580         if (!err)
1581                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1582
1583         return err;
1584 }
1585
1586 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1587 {
1588         u32 phytest;
1589
1590         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1591                 u32 phy;
1592
1593                 tg3_writephy(tp, MII_TG3_FET_TEST,
1594                              phytest | MII_TG3_FET_SHADOW_EN);
1595                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1596                         if (enable)
1597                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1598                         else
1599                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1600                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1601                 }
1602                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1603         }
1604 }
1605
1606 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1607 {
1608         u32 reg;
1609
1610         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1611             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1612               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1613              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1614                 return;
1615
1616         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1617                 tg3_phy_fet_toggle_apd(tp, enable);
1618                 return;
1619         }
1620
1621         reg = MII_TG3_MISC_SHDW_WREN |
1622               MII_TG3_MISC_SHDW_SCR5_SEL |
1623               MII_TG3_MISC_SHDW_SCR5_LPED |
1624               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1625               MII_TG3_MISC_SHDW_SCR5_SDTL |
1626               MII_TG3_MISC_SHDW_SCR5_C125OE;
1627         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1628                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1629
1630         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1631
1632
1633         reg = MII_TG3_MISC_SHDW_WREN |
1634               MII_TG3_MISC_SHDW_APD_SEL |
1635               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1636         if (enable)
1637                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1638
1639         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1640 }
1641
1642 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1643 {
1644         u32 phy;
1645
1646         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1647             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1648                 return;
1649
1650         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1651                 u32 ephy;
1652
1653                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1654                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1655
1656                         tg3_writephy(tp, MII_TG3_FET_TEST,
1657                                      ephy | MII_TG3_FET_SHADOW_EN);
1658                         if (!tg3_readphy(tp, reg, &phy)) {
1659                                 if (enable)
1660                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1661                                 else
1662                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1663                                 tg3_writephy(tp, reg, phy);
1664                         }
1665                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1666                 }
1667         } else {
1668                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1669                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1670                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1671                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1672                         if (enable)
1673                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1674                         else
1675                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1676                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1677                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1678                 }
1679         }
1680 }
1681
1682 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1683 {
1684         u32 val;
1685
1686         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1687                 return;
1688
1689         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1690             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1691                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1692                              (val | (1 << 15) | (1 << 4)));
1693 }
1694
1695 static void tg3_phy_apply_otp(struct tg3 *tp)
1696 {
1697         u32 otp, phy;
1698
1699         if (!tp->phy_otp)
1700                 return;
1701
1702         otp = tp->phy_otp;
1703
1704         /* Enable SM_DSP clock and tx 6dB coding. */
1705         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1706               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1707               MII_TG3_AUXCTL_ACTL_TX_6DB;
1708         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1709
1710         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1711         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1712         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1713
1714         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1715               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1716         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1717
1718         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1719         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1720         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1721
1722         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1723         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1724
1725         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1726         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1727
1728         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1729               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1730         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1731
1732         /* Turn off SM_DSP clock. */
1733         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1734               MII_TG3_AUXCTL_ACTL_TX_6DB;
1735         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1736 }
1737
1738 static int tg3_wait_macro_done(struct tg3 *tp)
1739 {
1740         int limit = 100;
1741
1742         while (limit--) {
1743                 u32 tmp32;
1744
1745                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1746                         if ((tmp32 & 0x1000) == 0)
1747                                 break;
1748                 }
1749         }
1750         if (limit < 0)
1751                 return -EBUSY;
1752
1753         return 0;
1754 }
1755
1756 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1757 {
1758         static const u32 test_pat[4][6] = {
1759         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1760         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1761         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1762         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1763         };
1764         int chan;
1765
1766         for (chan = 0; chan < 4; chan++) {
1767                 int i;
1768
1769                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1770                              (chan * 0x2000) | 0x0200);
1771                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1772
1773                 for (i = 0; i < 6; i++)
1774                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1775                                      test_pat[chan][i]);
1776
1777                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1778                 if (tg3_wait_macro_done(tp)) {
1779                         *resetp = 1;
1780                         return -EBUSY;
1781                 }
1782
1783                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1784                              (chan * 0x2000) | 0x0200);
1785                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1786                 if (tg3_wait_macro_done(tp)) {
1787                         *resetp = 1;
1788                         return -EBUSY;
1789                 }
1790
1791                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1792                 if (tg3_wait_macro_done(tp)) {
1793                         *resetp = 1;
1794                         return -EBUSY;
1795                 }
1796
1797                 for (i = 0; i < 6; i += 2) {
1798                         u32 low, high;
1799
1800                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1801                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1802                             tg3_wait_macro_done(tp)) {
1803                                 *resetp = 1;
1804                                 return -EBUSY;
1805                         }
1806                         low &= 0x7fff;
1807                         high &= 0x000f;
1808                         if (low != test_pat[chan][i] ||
1809                             high != test_pat[chan][i+1]) {
1810                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1811                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1812                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1813
1814                                 return -EBUSY;
1815                         }
1816                 }
1817         }
1818
1819         return 0;
1820 }
1821
1822 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1823 {
1824         int chan;
1825
1826         for (chan = 0; chan < 4; chan++) {
1827                 int i;
1828
1829                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1830                              (chan * 0x2000) | 0x0200);
1831                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1832                 for (i = 0; i < 6; i++)
1833                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1834                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1835                 if (tg3_wait_macro_done(tp))
1836                         return -EBUSY;
1837         }
1838
1839         return 0;
1840 }
1841
1842 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1843 {
1844         u32 reg32, phy9_orig;
1845         int retries, do_phy_reset, err;
1846
1847         retries = 10;
1848         do_phy_reset = 1;
1849         do {
1850                 if (do_phy_reset) {
1851                         err = tg3_bmcr_reset(tp);
1852                         if (err)
1853                                 return err;
1854                         do_phy_reset = 0;
1855                 }
1856
1857                 /* Disable transmitter and interrupt.  */
1858                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1859                         continue;
1860
1861                 reg32 |= 0x3000;
1862                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1863
1864                 /* Set full-duplex, 1000 mbps.  */
1865                 tg3_writephy(tp, MII_BMCR,
1866                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1867
1868                 /* Set to master mode.  */
1869                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1870                         continue;
1871
1872                 tg3_writephy(tp, MII_TG3_CTRL,
1873                              (MII_TG3_CTRL_AS_MASTER |
1874                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1875
1876                 /* Enable SM_DSP_CLOCK and 6dB.  */
1877                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1878
1879                 /* Block the PHY control access.  */
1880                 tg3_phydsp_write(tp, 0x8005, 0x0800);
1881
1882                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1883                 if (!err)
1884                         break;
1885         } while (--retries);
1886
1887         err = tg3_phy_reset_chanpat(tp);
1888         if (err)
1889                 return err;
1890
1891         tg3_phydsp_write(tp, 0x8005, 0x0000);
1892
1893         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1894         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1895
1896         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1897             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1898                 /* Set Extended packet length bit for jumbo frames */
1899                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1900         } else {
1901                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1902         }
1903
1904         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1905
1906         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1907                 reg32 &= ~0x3000;
1908                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1909         } else if (!err)
1910                 err = -EBUSY;
1911
1912         return err;
1913 }
1914
1915 /* This will reset the tigon3 PHY if there is no valid
1916  * link unless the FORCE argument is non-zero.
1917  */
1918 static int tg3_phy_reset(struct tg3 *tp)
1919 {
1920         u32 cpmuctrl;
1921         u32 phy_status;
1922         int err;
1923
1924         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1925                 u32 val;
1926
1927                 val = tr32(GRC_MISC_CFG);
1928                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1929                 udelay(40);
1930         }
1931         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1932         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1933         if (err != 0)
1934                 return -EBUSY;
1935
1936         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1937                 netif_carrier_off(tp->dev);
1938                 tg3_link_report(tp);
1939         }
1940
1941         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1942             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1943             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1944                 err = tg3_phy_reset_5703_4_5(tp);
1945                 if (err)
1946                         return err;
1947                 goto out;
1948         }
1949
1950         cpmuctrl = 0;
1951         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1952             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1953                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1954                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1955                         tw32(TG3_CPMU_CTRL,
1956                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1957         }
1958
1959         err = tg3_bmcr_reset(tp);
1960         if (err)
1961                 return err;
1962
1963         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1964                 u32 phy;
1965
1966                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1967                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1968
1969                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1970         }
1971
1972         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1973             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1974                 u32 val;
1975
1976                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1977                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1978                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1979                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1980                         udelay(40);
1981                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1982                 }
1983         }
1984
1985         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1986              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1987             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
1988                 return 0;
1989
1990         tg3_phy_apply_otp(tp);
1991
1992         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
1993                 tg3_phy_toggle_apd(tp, true);
1994         else
1995                 tg3_phy_toggle_apd(tp, false);
1996
1997 out:
1998         if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
1999                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2000                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2001                 tg3_phydsp_write(tp, 0x000a, 0x0323);
2002                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2003         }
2004         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2005                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2006                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2007         }
2008         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2009                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2010                 tg3_phydsp_write(tp, 0x000a, 0x310b);
2011                 tg3_phydsp_write(tp, 0x201f, 0x9506);
2012                 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2013                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2014         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2015                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2016                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2017                 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2018                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2019                         tg3_writephy(tp, MII_TG3_TEST1,
2020                                      MII_TG3_TEST1_TRIM_EN | 0x4);
2021                 } else
2022                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2023                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2024         }
2025         /* Set Extended packet length bit (bit 14) on all chips that */
2026         /* support jumbo frames */
2027         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2028                 /* Cannot do read-modify-write on 5401 */
2029                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2030         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2031                 u32 phy_reg;
2032
2033                 /* Set bit 14 with read-modify-write to preserve other bits */
2034                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2035                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
2036                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
2037         }
2038
2039         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2040          * jumbo frames transmission.
2041          */
2042         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2043                 u32 phy_reg;
2044
2045                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2046                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2047                                      phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2048         }
2049
2050         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2051                 /* adjust output voltage */
2052                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2053         }
2054
2055         tg3_phy_toggle_automdix(tp, 1);
2056         tg3_phy_set_wirespeed(tp);
2057         return 0;
2058 }
2059
2060 static void tg3_frob_aux_power(struct tg3 *tp)
2061 {
2062         struct tg3 *tp_peer = tp;
2063
2064         /* The GPIOs do something completely different on 57765. */
2065         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2066             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2067             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2068                 return;
2069
2070         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2071             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2072             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2073                 struct net_device *dev_peer;
2074
2075                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2076                 /* remove_one() may have been run on the peer. */
2077                 if (!dev_peer)
2078                         tp_peer = tp;
2079                 else
2080                         tp_peer = netdev_priv(dev_peer);
2081         }
2082
2083         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2084             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2085             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2086             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2087                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2088                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2089                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2090                                     (GRC_LCLCTRL_GPIO_OE0 |
2091                                      GRC_LCLCTRL_GPIO_OE1 |
2092                                      GRC_LCLCTRL_GPIO_OE2 |
2093                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2094                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2095                                     100);
2096                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2097                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2098                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2099                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2100                                              GRC_LCLCTRL_GPIO_OE1 |
2101                                              GRC_LCLCTRL_GPIO_OE2 |
2102                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2103                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2104                                              tp->grc_local_ctrl;
2105                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2106
2107                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2108                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2109
2110                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2111                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2112                 } else {
2113                         u32 no_gpio2;
2114                         u32 grc_local_ctrl = 0;
2115
2116                         if (tp_peer != tp &&
2117                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2118                                 return;
2119
2120                         /* Workaround to prevent overdrawing Amps. */
2121                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2122                             ASIC_REV_5714) {
2123                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2124                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2125                                             grc_local_ctrl, 100);
2126                         }
2127
2128                         /* On 5753 and variants, GPIO2 cannot be used. */
2129                         no_gpio2 = tp->nic_sram_data_cfg &
2130                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2131
2132                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2133                                          GRC_LCLCTRL_GPIO_OE1 |
2134                                          GRC_LCLCTRL_GPIO_OE2 |
2135                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2136                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2137                         if (no_gpio2) {
2138                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2139                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2140                         }
2141                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2142                                                     grc_local_ctrl, 100);
2143
2144                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2145
2146                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2147                                                     grc_local_ctrl, 100);
2148
2149                         if (!no_gpio2) {
2150                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2151                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2152                                             grc_local_ctrl, 100);
2153                         }
2154                 }
2155         } else {
2156                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2157                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2158                         if (tp_peer != tp &&
2159                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2160                                 return;
2161
2162                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2163                                     (GRC_LCLCTRL_GPIO_OE1 |
2164                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2165
2166                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2167                                     GRC_LCLCTRL_GPIO_OE1, 100);
2168
2169                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2170                                     (GRC_LCLCTRL_GPIO_OE1 |
2171                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2172                 }
2173         }
2174 }
2175
2176 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2177 {
2178         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2179                 return 1;
2180         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2181                 if (speed != SPEED_10)
2182                         return 1;
2183         } else if (speed == SPEED_10)
2184                 return 1;
2185
2186         return 0;
2187 }
2188
2189 static int tg3_setup_phy(struct tg3 *, int);
2190
2191 #define RESET_KIND_SHUTDOWN     0
2192 #define RESET_KIND_INIT         1
2193 #define RESET_KIND_SUSPEND      2
2194
2195 static void tg3_write_sig_post_reset(struct tg3 *, int);
2196 static int tg3_halt_cpu(struct tg3 *, u32);
2197
2198 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2199 {
2200         u32 val;
2201
2202         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2203                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2204                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2205                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2206
2207                         sg_dig_ctrl |=
2208                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2209                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2210                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2211                 }
2212                 return;
2213         }
2214
2215         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2216                 tg3_bmcr_reset(tp);
2217                 val = tr32(GRC_MISC_CFG);
2218                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2219                 udelay(40);
2220                 return;
2221         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2222                 u32 phytest;
2223                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2224                         u32 phy;
2225
2226                         tg3_writephy(tp, MII_ADVERTISE, 0);
2227                         tg3_writephy(tp, MII_BMCR,
2228                                      BMCR_ANENABLE | BMCR_ANRESTART);
2229
2230                         tg3_writephy(tp, MII_TG3_FET_TEST,
2231                                      phytest | MII_TG3_FET_SHADOW_EN);
2232                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2233                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2234                                 tg3_writephy(tp,
2235                                              MII_TG3_FET_SHDW_AUXMODE4,
2236                                              phy);
2237                         }
2238                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2239                 }
2240                 return;
2241         } else if (do_low_power) {
2242                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2243                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2244
2245                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2246                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2247                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2248                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2249                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2250         }
2251
2252         /* The PHY should not be powered down on some chips because
2253          * of bugs.
2254          */
2255         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2256             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2257             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2258              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2259                 return;
2260
2261         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2262             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2263                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2264                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2265                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2266                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2267         }
2268
2269         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2270 }
2271
2272 /* tp->lock is held. */
2273 static int tg3_nvram_lock(struct tg3 *tp)
2274 {
2275         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2276                 int i;
2277
2278                 if (tp->nvram_lock_cnt == 0) {
2279                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2280                         for (i = 0; i < 8000; i++) {
2281                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2282                                         break;
2283                                 udelay(20);
2284                         }
2285                         if (i == 8000) {
2286                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2287                                 return -ENODEV;
2288                         }
2289                 }
2290                 tp->nvram_lock_cnt++;
2291         }
2292         return 0;
2293 }
2294
2295 /* tp->lock is held. */
2296 static void tg3_nvram_unlock(struct tg3 *tp)
2297 {
2298         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2299                 if (tp->nvram_lock_cnt > 0)
2300                         tp->nvram_lock_cnt--;
2301                 if (tp->nvram_lock_cnt == 0)
2302                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2303         }
2304 }
2305
2306 /* tp->lock is held. */
2307 static void tg3_enable_nvram_access(struct tg3 *tp)
2308 {
2309         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2310             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2311                 u32 nvaccess = tr32(NVRAM_ACCESS);
2312
2313                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2314         }
2315 }
2316
2317 /* tp->lock is held. */
2318 static void tg3_disable_nvram_access(struct tg3 *tp)
2319 {
2320         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2321             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2322                 u32 nvaccess = tr32(NVRAM_ACCESS);
2323
2324                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2325         }
2326 }
2327
2328 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2329                                         u32 offset, u32 *val)
2330 {
2331         u32 tmp;
2332         int i;
2333
2334         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2335                 return -EINVAL;
2336
2337         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2338                                         EEPROM_ADDR_DEVID_MASK |
2339                                         EEPROM_ADDR_READ);
2340         tw32(GRC_EEPROM_ADDR,
2341              tmp |
2342              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2343              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2344               EEPROM_ADDR_ADDR_MASK) |
2345              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2346
2347         for (i = 0; i < 1000; i++) {
2348                 tmp = tr32(GRC_EEPROM_ADDR);
2349
2350                 if (tmp & EEPROM_ADDR_COMPLETE)
2351                         break;
2352                 msleep(1);
2353         }
2354         if (!(tmp & EEPROM_ADDR_COMPLETE))
2355                 return -EBUSY;
2356
2357         tmp = tr32(GRC_EEPROM_DATA);
2358
2359         /*
2360          * The data will always be opposite the native endian
2361          * format.  Perform a blind byteswap to compensate.
2362          */
2363         *val = swab32(tmp);
2364
2365         return 0;
2366 }
2367
2368 #define NVRAM_CMD_TIMEOUT 10000
2369
2370 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2371 {
2372         int i;
2373
2374         tw32(NVRAM_CMD, nvram_cmd);
2375         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2376                 udelay(10);
2377                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2378                         udelay(10);
2379                         break;
2380                 }
2381         }
2382
2383         if (i == NVRAM_CMD_TIMEOUT)
2384                 return -EBUSY;
2385
2386         return 0;
2387 }
2388
2389 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2390 {
2391         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2392             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2393             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2394            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2395             (tp->nvram_jedecnum == JEDEC_ATMEL))
2396
2397                 addr = ((addr / tp->nvram_pagesize) <<
2398                         ATMEL_AT45DB0X1B_PAGE_POS) +
2399                        (addr % tp->nvram_pagesize);
2400
2401         return addr;
2402 }
2403
2404 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2405 {
2406         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2407             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2408             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2409            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2410             (tp->nvram_jedecnum == JEDEC_ATMEL))
2411
2412                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2413                         tp->nvram_pagesize) +
2414                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2415
2416         return addr;
2417 }
2418
2419 /* NOTE: Data read in from NVRAM is byteswapped according to
2420  * the byteswapping settings for all other register accesses.
2421  * tg3 devices are BE devices, so on a BE machine, the data
2422  * returned will be exactly as it is seen in NVRAM.  On a LE
2423  * machine, the 32-bit value will be byteswapped.
2424  */
2425 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2426 {
2427         int ret;
2428
2429         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2430                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2431
2432         offset = tg3_nvram_phys_addr(tp, offset);
2433
2434         if (offset > NVRAM_ADDR_MSK)
2435                 return -EINVAL;
2436
2437         ret = tg3_nvram_lock(tp);
2438         if (ret)
2439                 return ret;
2440
2441         tg3_enable_nvram_access(tp);
2442
2443         tw32(NVRAM_ADDR, offset);
2444         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2445                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2446
2447         if (ret == 0)
2448                 *val = tr32(NVRAM_RDDATA);
2449
2450         tg3_disable_nvram_access(tp);
2451
2452         tg3_nvram_unlock(tp);
2453
2454         return ret;
2455 }
2456
2457 /* Ensures NVRAM data is in bytestream format. */
2458 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2459 {
2460         u32 v;
2461         int res = tg3_nvram_read(tp, offset, &v);
2462         if (!res)
2463                 *val = cpu_to_be32(v);
2464         return res;
2465 }
2466
2467 /* tp->lock is held. */
2468 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2469 {
2470         u32 addr_high, addr_low;
2471         int i;
2472
2473         addr_high = ((tp->dev->dev_addr[0] << 8) |
2474                      tp->dev->dev_addr[1]);
2475         addr_low = ((tp->dev->dev_addr[2] << 24) |
2476                     (tp->dev->dev_addr[3] << 16) |
2477                     (tp->dev->dev_addr[4] <<  8) |
2478                     (tp->dev->dev_addr[5] <<  0));
2479         for (i = 0; i < 4; i++) {
2480                 if (i == 1 && skip_mac_1)
2481                         continue;
2482                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2483                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2484         }
2485
2486         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2487             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2488                 for (i = 0; i < 12; i++) {
2489                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2490                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2491                 }
2492         }
2493
2494         addr_high = (tp->dev->dev_addr[0] +
2495                      tp->dev->dev_addr[1] +
2496                      tp->dev->dev_addr[2] +
2497                      tp->dev->dev_addr[3] +
2498                      tp->dev->dev_addr[4] +
2499                      tp->dev->dev_addr[5]) &
2500                 TX_BACKOFF_SEED_MASK;
2501         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2502 }
2503
2504 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2505 {
2506         u32 misc_host_ctrl;
2507         bool device_should_wake, do_low_power;
2508
2509         /* Make sure register accesses (indirect or otherwise)
2510          * will function correctly.
2511          */
2512         pci_write_config_dword(tp->pdev,
2513                                TG3PCI_MISC_HOST_CTRL,
2514                                tp->misc_host_ctrl);
2515
2516         switch (state) {
2517         case PCI_D0:
2518                 pci_enable_wake(tp->pdev, state, false);
2519                 pci_set_power_state(tp->pdev, PCI_D0);
2520
2521                 /* Switch out of Vaux if it is a NIC */
2522                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2523                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2524
2525                 return 0;
2526
2527         case PCI_D1:
2528         case PCI_D2:
2529         case PCI_D3hot:
2530                 break;
2531
2532         default:
2533                 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2534                            state);
2535                 return -EINVAL;
2536         }
2537
2538         /* Restore the CLKREQ setting. */
2539         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2540                 u16 lnkctl;
2541
2542                 pci_read_config_word(tp->pdev,
2543                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2544                                      &lnkctl);
2545                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2546                 pci_write_config_word(tp->pdev,
2547                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2548                                       lnkctl);
2549         }
2550
2551         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2552         tw32(TG3PCI_MISC_HOST_CTRL,
2553              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2554
2555         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2556                              device_may_wakeup(&tp->pdev->dev) &&
2557                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2558
2559         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2560                 do_low_power = false;
2561                 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2562                     !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2563                         struct phy_device *phydev;
2564                         u32 phyid, advertising;
2565
2566                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2567
2568                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2569
2570                         tp->link_config.orig_speed = phydev->speed;
2571                         tp->link_config.orig_duplex = phydev->duplex;
2572                         tp->link_config.orig_autoneg = phydev->autoneg;
2573                         tp->link_config.orig_advertising = phydev->advertising;
2574
2575                         advertising = ADVERTISED_TP |
2576                                       ADVERTISED_Pause |
2577                                       ADVERTISED_Autoneg |
2578                                       ADVERTISED_10baseT_Half;
2579
2580                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2581                             device_should_wake) {
2582                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2583                                         advertising |=
2584                                                 ADVERTISED_100baseT_Half |
2585                                                 ADVERTISED_100baseT_Full |
2586                                                 ADVERTISED_10baseT_Full;
2587                                 else
2588                                         advertising |= ADVERTISED_10baseT_Full;
2589                         }
2590
2591                         phydev->advertising = advertising;
2592
2593                         phy_start_aneg(phydev);
2594
2595                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2596                         if (phyid != PHY_ID_BCMAC131) {
2597                                 phyid &= PHY_BCM_OUI_MASK;
2598                                 if (phyid == PHY_BCM_OUI_1 ||
2599                                     phyid == PHY_BCM_OUI_2 ||
2600                                     phyid == PHY_BCM_OUI_3)
2601                                         do_low_power = true;
2602                         }
2603                 }
2604         } else {
2605                 do_low_power = true;
2606
2607                 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2608                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2609                         tp->link_config.orig_speed = tp->link_config.speed;
2610                         tp->link_config.orig_duplex = tp->link_config.duplex;
2611                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2612                 }
2613
2614                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2615                         tp->link_config.speed = SPEED_10;
2616                         tp->link_config.duplex = DUPLEX_HALF;
2617                         tp->link_config.autoneg = AUTONEG_ENABLE;
2618                         tg3_setup_phy(tp, 0);
2619                 }
2620         }
2621
2622         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2623                 u32 val;
2624
2625                 val = tr32(GRC_VCPU_EXT_CTRL);
2626                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2627         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2628                 int i;
2629                 u32 val;
2630
2631                 for (i = 0; i < 200; i++) {
2632                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2633                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2634                                 break;
2635                         msleep(1);
2636                 }
2637         }
2638         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2639                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2640                                                      WOL_DRV_STATE_SHUTDOWN |
2641                                                      WOL_DRV_WOL |
2642                                                      WOL_SET_MAGIC_PKT);
2643
2644         if (device_should_wake) {
2645                 u32 mac_mode;
2646
2647                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2648                         if (do_low_power) {
2649                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2650                                 udelay(40);
2651                         }
2652
2653                         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2654                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2655                         else
2656                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2657
2658                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2659                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2660                             ASIC_REV_5700) {
2661                                 u32 speed = (tp->tg3_flags &
2662                                              TG3_FLAG_WOL_SPEED_100MB) ?
2663                                              SPEED_100 : SPEED_10;
2664                                 if (tg3_5700_link_polarity(tp, speed))
2665                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2666                                 else
2667                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2668                         }
2669                 } else {
2670                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2671                 }
2672
2673                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2674                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2675
2676                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2677                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2678                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2679                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2680                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2681                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2682
2683                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2684                         mac_mode |= tp->mac_mode &
2685                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2686                         if (mac_mode & MAC_MODE_APE_TX_EN)
2687                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2688                 }
2689
2690                 tw32_f(MAC_MODE, mac_mode);
2691                 udelay(100);
2692
2693                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2694                 udelay(10);
2695         }
2696
2697         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2698             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2699              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2700                 u32 base_val;
2701
2702                 base_val = tp->pci_clock_ctrl;
2703                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2704                              CLOCK_CTRL_TXCLK_DISABLE);
2705
2706                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2707                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2708         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2709                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2710                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2711                 /* do nothing */
2712         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2713                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2714                 u32 newbits1, newbits2;
2715
2716                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2717                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2718                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2719                                     CLOCK_CTRL_TXCLK_DISABLE |
2720                                     CLOCK_CTRL_ALTCLK);
2721                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2722                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2723                         newbits1 = CLOCK_CTRL_625_CORE;
2724                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2725                 } else {
2726                         newbits1 = CLOCK_CTRL_ALTCLK;
2727                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2728                 }
2729
2730                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2731                             40);
2732
2733                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2734                             40);
2735
2736                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2737                         u32 newbits3;
2738
2739                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2740                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2741                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2742                                             CLOCK_CTRL_TXCLK_DISABLE |
2743                                             CLOCK_CTRL_44MHZ_CORE);
2744                         } else {
2745                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2746                         }
2747
2748                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2749                                     tp->pci_clock_ctrl | newbits3, 40);
2750                 }
2751         }
2752
2753         if (!(device_should_wake) &&
2754             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2755                 tg3_power_down_phy(tp, do_low_power);
2756
2757         tg3_frob_aux_power(tp);
2758
2759         /* Workaround for unstable PLL clock */
2760         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2761             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2762                 u32 val = tr32(0x7d00);
2763
2764                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2765                 tw32(0x7d00, val);
2766                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2767                         int err;
2768
2769                         err = tg3_nvram_lock(tp);
2770                         tg3_halt_cpu(tp, RX_CPU_BASE);
2771                         if (!err)
2772                                 tg3_nvram_unlock(tp);
2773                 }
2774         }
2775
2776         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2777
2778         if (device_should_wake)
2779                 pci_enable_wake(tp->pdev, state, true);
2780
2781         /* Finally, set the new power state. */
2782         pci_set_power_state(tp->pdev, state);
2783
2784         return 0;
2785 }
2786
2787 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2788 {
2789         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2790         case MII_TG3_AUX_STAT_10HALF:
2791                 *speed = SPEED_10;
2792                 *duplex = DUPLEX_HALF;
2793                 break;
2794
2795         case MII_TG3_AUX_STAT_10FULL:
2796                 *speed = SPEED_10;
2797                 *duplex = DUPLEX_FULL;
2798                 break;
2799
2800         case MII_TG3_AUX_STAT_100HALF:
2801                 *speed = SPEED_100;
2802                 *duplex = DUPLEX_HALF;
2803                 break;
2804
2805         case MII_TG3_AUX_STAT_100FULL:
2806                 *speed = SPEED_100;
2807                 *duplex = DUPLEX_FULL;
2808                 break;
2809
2810         case MII_TG3_AUX_STAT_1000HALF:
2811                 *speed = SPEED_1000;
2812                 *duplex = DUPLEX_HALF;
2813                 break;
2814
2815         case MII_TG3_AUX_STAT_1000FULL:
2816                 *speed = SPEED_1000;
2817                 *duplex = DUPLEX_FULL;
2818                 break;
2819
2820         default:
2821                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2822                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2823                                  SPEED_10;
2824                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2825                                   DUPLEX_HALF;
2826                         break;
2827                 }
2828                 *speed = SPEED_INVALID;
2829                 *duplex = DUPLEX_INVALID;
2830                 break;
2831         }
2832 }
2833
2834 static void tg3_phy_copper_begin(struct tg3 *tp)
2835 {
2836         u32 new_adv;
2837         int i;
2838
2839         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2840                 /* Entering low power mode.  Disable gigabit and
2841                  * 100baseT advertisements.
2842                  */
2843                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2844
2845                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2846                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2847                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2848                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2849
2850                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2851         } else if (tp->link_config.speed == SPEED_INVALID) {
2852                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2853                         tp->link_config.advertising &=
2854                                 ~(ADVERTISED_1000baseT_Half |
2855                                   ADVERTISED_1000baseT_Full);
2856
2857                 new_adv = ADVERTISE_CSMA;
2858                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2859                         new_adv |= ADVERTISE_10HALF;
2860                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2861                         new_adv |= ADVERTISE_10FULL;
2862                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2863                         new_adv |= ADVERTISE_100HALF;
2864                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2865                         new_adv |= ADVERTISE_100FULL;
2866
2867                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2868
2869                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2870
2871                 if (tp->link_config.advertising &
2872                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2873                         new_adv = 0;
2874                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2875                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2876                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2877                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2878                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
2879                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2880                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2881                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2882                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2883                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2884                 } else {
2885                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2886                 }
2887         } else {
2888                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2889                 new_adv |= ADVERTISE_CSMA;
2890
2891                 /* Asking for a specific link mode. */
2892                 if (tp->link_config.speed == SPEED_1000) {
2893                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2894
2895                         if (tp->link_config.duplex == DUPLEX_FULL)
2896                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2897                         else
2898                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2899                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2900                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2901                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2902                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2903                 } else {
2904                         if (tp->link_config.speed == SPEED_100) {
2905                                 if (tp->link_config.duplex == DUPLEX_FULL)
2906                                         new_adv |= ADVERTISE_100FULL;
2907                                 else
2908                                         new_adv |= ADVERTISE_100HALF;
2909                         } else {
2910                                 if (tp->link_config.duplex == DUPLEX_FULL)
2911                                         new_adv |= ADVERTISE_10FULL;
2912                                 else
2913                                         new_adv |= ADVERTISE_10HALF;
2914                         }
2915                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2916
2917                         new_adv = 0;
2918                 }
2919
2920                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2921         }
2922
2923         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2924             tp->link_config.speed != SPEED_INVALID) {
2925                 u32 bmcr, orig_bmcr;
2926
2927                 tp->link_config.active_speed = tp->link_config.speed;
2928                 tp->link_config.active_duplex = tp->link_config.duplex;
2929
2930                 bmcr = 0;
2931                 switch (tp->link_config.speed) {
2932                 default:
2933                 case SPEED_10:
2934                         break;
2935
2936                 case SPEED_100:
2937                         bmcr |= BMCR_SPEED100;
2938                         break;
2939
2940                 case SPEED_1000:
2941                         bmcr |= TG3_BMCR_SPEED1000;
2942                         break;
2943                 }
2944
2945                 if (tp->link_config.duplex == DUPLEX_FULL)
2946                         bmcr |= BMCR_FULLDPLX;
2947
2948                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2949                     (bmcr != orig_bmcr)) {
2950                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2951                         for (i = 0; i < 1500; i++) {
2952                                 u32 tmp;
2953
2954                                 udelay(10);
2955                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2956                                     tg3_readphy(tp, MII_BMSR, &tmp))
2957                                         continue;
2958                                 if (!(tmp & BMSR_LSTATUS)) {
2959                                         udelay(40);
2960                                         break;
2961                                 }
2962                         }
2963                         tg3_writephy(tp, MII_BMCR, bmcr);
2964                         udelay(40);
2965                 }
2966         } else {
2967                 tg3_writephy(tp, MII_BMCR,
2968                              BMCR_ANENABLE | BMCR_ANRESTART);
2969         }
2970 }
2971
2972 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2973 {
2974         int err;
2975
2976         /* Turn off tap power management. */
2977         /* Set Extended packet length bit */
2978         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2979
2980         err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
2981         err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
2982         err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
2983         err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
2984         err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
2985
2986         udelay(40);
2987
2988         return err;
2989 }
2990
2991 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2992 {
2993         u32 adv_reg, all_mask = 0;
2994
2995         if (mask & ADVERTISED_10baseT_Half)
2996                 all_mask |= ADVERTISE_10HALF;
2997         if (mask & ADVERTISED_10baseT_Full)
2998                 all_mask |= ADVERTISE_10FULL;
2999         if (mask & ADVERTISED_100baseT_Half)
3000                 all_mask |= ADVERTISE_100HALF;
3001         if (mask & ADVERTISED_100baseT_Full)
3002                 all_mask |= ADVERTISE_100FULL;
3003
3004         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3005                 return 0;
3006
3007         if ((adv_reg & all_mask) != all_mask)
3008                 return 0;
3009         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3010                 u32 tg3_ctrl;
3011
3012                 all_mask = 0;
3013                 if (mask & ADVERTISED_1000baseT_Half)
3014                         all_mask |= ADVERTISE_1000HALF;
3015                 if (mask & ADVERTISED_1000baseT_Full)
3016                         all_mask |= ADVERTISE_1000FULL;
3017
3018                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3019                         return 0;
3020
3021                 if ((tg3_ctrl & all_mask) != all_mask)
3022                         return 0;
3023         }
3024         return 1;
3025 }
3026
3027 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3028 {
3029         u32 curadv, reqadv;
3030
3031         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3032                 return 1;
3033
3034         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3035         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3036
3037         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3038                 if (curadv != reqadv)
3039                         return 0;
3040
3041                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3042                         tg3_readphy(tp, MII_LPA, rmtadv);
3043         } else {
3044                 /* Reprogram the advertisement register, even if it
3045                  * does not affect the current link.  If the link
3046                  * gets renegotiated in the future, we can save an
3047                  * additional renegotiation cycle by advertising
3048                  * it correctly in the first place.
3049                  */
3050                 if (curadv != reqadv) {
3051                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3052                                      ADVERTISE_PAUSE_ASYM);
3053                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3054                 }
3055         }
3056
3057         return 1;
3058 }
3059
3060 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3061 {
3062         int current_link_up;
3063         u32 bmsr, dummy;
3064         u32 lcl_adv, rmt_adv;
3065         u16 current_speed;
3066         u8 current_duplex;
3067         int i, err;
3068
3069         tw32(MAC_EVENT, 0);
3070
3071         tw32_f(MAC_STATUS,
3072              (MAC_STATUS_SYNC_CHANGED |
3073               MAC_STATUS_CFG_CHANGED |
3074               MAC_STATUS_MI_COMPLETION |
3075               MAC_STATUS_LNKSTATE_CHANGED));
3076         udelay(40);
3077
3078         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3079                 tw32_f(MAC_MI_MODE,
3080                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3081                 udelay(80);
3082         }
3083
3084         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3085
3086         /* Some third-party PHYs need to be reset on link going
3087          * down.
3088          */
3089         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3090              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3091              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3092             netif_carrier_ok(tp->dev)) {
3093                 tg3_readphy(tp, MII_BMSR, &bmsr);
3094                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3095                     !(bmsr & BMSR_LSTATUS))
3096                         force_reset = 1;
3097         }
3098         if (force_reset)
3099                 tg3_phy_reset(tp);
3100
3101         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3102                 tg3_readphy(tp, MII_BMSR, &bmsr);
3103                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3104                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3105                         bmsr = 0;
3106
3107                 if (!(bmsr & BMSR_LSTATUS)) {
3108                         err = tg3_init_5401phy_dsp(tp);
3109                         if (err)
3110                                 return err;
3111
3112                         tg3_readphy(tp, MII_BMSR, &bmsr);
3113                         for (i = 0; i < 1000; i++) {
3114                                 udelay(10);
3115                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3116                                     (bmsr & BMSR_LSTATUS)) {
3117                                         udelay(40);
3118                                         break;
3119                                 }
3120                         }
3121
3122                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3123                             TG3_PHY_REV_BCM5401_B0 &&
3124                             !(bmsr & BMSR_LSTATUS) &&
3125                             tp->link_config.active_speed == SPEED_1000) {
3126                                 err = tg3_phy_reset(tp);
3127                                 if (!err)
3128                                         err = tg3_init_5401phy_dsp(tp);
3129                                 if (err)
3130                                         return err;
3131                         }
3132                 }
3133         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3134                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3135                 /* 5701 {A0,B0} CRC bug workaround */
3136                 tg3_writephy(tp, 0x15, 0x0a75);
3137                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3138                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3139                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3140         }
3141
3142         /* Clear pending interrupts... */
3143         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3144         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3145
3146         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3147                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3148         else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3149                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3150
3151         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3152             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3153                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3154                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3155                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3156                 else
3157                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3158         }
3159
3160         current_link_up = 0;
3161         current_speed = SPEED_INVALID;
3162         current_duplex = DUPLEX_INVALID;
3163
3164         if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3165                 u32 val;
3166
3167                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3168                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3169                 if (!(val & (1 << 10))) {
3170                         val |= (1 << 10);
3171                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3172                         goto relink;
3173                 }
3174         }
3175
3176         bmsr = 0;
3177         for (i = 0; i < 100; i++) {
3178                 tg3_readphy(tp, MII_BMSR, &bmsr);
3179                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3180                     (bmsr & BMSR_LSTATUS))
3181                         break;
3182                 udelay(40);
3183         }
3184
3185         if (bmsr & BMSR_LSTATUS) {
3186                 u32 aux_stat, bmcr;
3187
3188                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3189                 for (i = 0; i < 2000; i++) {
3190                         udelay(10);
3191                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3192                             aux_stat)
3193                                 break;
3194                 }
3195
3196                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3197                                              &current_speed,
3198                                              &current_duplex);
3199
3200                 bmcr = 0;
3201                 for (i = 0; i < 200; i++) {
3202                         tg3_readphy(tp, MII_BMCR, &bmcr);
3203                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3204                                 continue;
3205                         if (bmcr && bmcr != 0x7fff)
3206                                 break;
3207                         udelay(10);
3208                 }
3209
3210                 lcl_adv = 0;
3211                 rmt_adv = 0;
3212
3213                 tp->link_config.active_speed = current_speed;
3214                 tp->link_config.active_duplex = current_duplex;
3215
3216                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3217                         if ((bmcr & BMCR_ANENABLE) &&
3218                             tg3_copper_is_advertising_all(tp,
3219                                                 tp->link_config.advertising)) {
3220                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3221                                                                   &rmt_adv))
3222                                         current_link_up = 1;
3223                         }
3224                 } else {
3225                         if (!(bmcr & BMCR_ANENABLE) &&
3226                             tp->link_config.speed == current_speed &&
3227                             tp->link_config.duplex == current_duplex &&
3228                             tp->link_config.flowctrl ==
3229                             tp->link_config.active_flowctrl) {
3230                                 current_link_up = 1;
3231                         }
3232                 }
3233
3234                 if (current_link_up == 1 &&
3235                     tp->link_config.active_duplex == DUPLEX_FULL)
3236                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3237         }
3238
3239 relink:
3240         if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3241                 u32 tmp;
3242
3243                 tg3_phy_copper_begin(tp);
3244
3245                 tg3_readphy(tp, MII_BMSR, &tmp);
3246                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3247                     (tmp & BMSR_LSTATUS))
3248                         current_link_up = 1;
3249         }
3250
3251         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3252         if (current_link_up == 1) {
3253                 if (tp->link_config.active_speed == SPEED_100 ||
3254                     tp->link_config.active_speed == SPEED_10)
3255                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3256                 else
3257                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3258         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3259                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3260         else
3261                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3262
3263         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3264         if (tp->link_config.active_duplex == DUPLEX_HALF)
3265                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3266
3267         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3268                 if (current_link_up == 1 &&
3269                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3270                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3271                 else
3272                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3273         }
3274
3275         /* ??? Without this setting Netgear GA302T PHY does not
3276          * ??? send/receive packets...
3277          */
3278         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3279             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3280                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3281                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3282                 udelay(80);
3283         }
3284
3285         tw32_f(MAC_MODE, tp->mac_mode);
3286         udelay(40);
3287
3288         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3289                 /* Polled via timer. */
3290                 tw32_f(MAC_EVENT, 0);
3291         } else {
3292                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3293         }
3294         udelay(40);
3295
3296         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3297             current_link_up == 1 &&
3298             tp->link_config.active_speed == SPEED_1000 &&
3299             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3300              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3301                 udelay(120);
3302                 tw32_f(MAC_STATUS,
3303                      (MAC_STATUS_SYNC_CHANGED |
3304                       MAC_STATUS_CFG_CHANGED));
3305                 udelay(40);
3306                 tg3_write_mem(tp,
3307                               NIC_SRAM_FIRMWARE_MBOX,
3308                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3309         }
3310
3311         /* Prevent send BD corruption. */
3312         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3313                 u16 oldlnkctl, newlnkctl;
3314
3315                 pci_read_config_word(tp->pdev,
3316                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3317                                      &oldlnkctl);
3318                 if (tp->link_config.active_speed == SPEED_100 ||
3319                     tp->link_config.active_speed == SPEED_10)
3320                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3321                 else
3322                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3323                 if (newlnkctl != oldlnkctl)
3324                         pci_write_config_word(tp->pdev,
3325                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3326                                               newlnkctl);
3327         }
3328
3329         if (current_link_up != netif_carrier_ok(tp->dev)) {
3330                 if (current_link_up)
3331                         netif_carrier_on(tp->dev);
3332                 else
3333                         netif_carrier_off(tp->dev);
3334                 tg3_link_report(tp);
3335         }
3336
3337         return 0;
3338 }
3339
3340 struct tg3_fiber_aneginfo {
3341         int state;
3342 #define ANEG_STATE_UNKNOWN              0
3343 #define ANEG_STATE_AN_ENABLE            1
3344 #define ANEG_STATE_RESTART_INIT         2
3345 #define ANEG_STATE_RESTART              3
3346 #define ANEG_STATE_DISABLE_LINK_OK      4
3347 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3348 #define ANEG_STATE_ABILITY_DETECT       6
3349 #define ANEG_STATE_ACK_DETECT_INIT      7
3350 #define ANEG_STATE_ACK_DETECT           8
3351 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3352 #define ANEG_STATE_COMPLETE_ACK         10
3353 #define ANEG_STATE_IDLE_DETECT_INIT     11
3354 #define ANEG_STATE_IDLE_DETECT          12
3355 #define ANEG_STATE_LINK_OK              13
3356 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3357 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3358
3359         u32 flags;
3360 #define MR_AN_ENABLE            0x00000001
3361 #define MR_RESTART_AN           0x00000002
3362 #define MR_AN_COMPLETE          0x00000004
3363 #define MR_PAGE_RX              0x00000008
3364 #define MR_NP_LOADED            0x00000010
3365 #define MR_TOGGLE_TX            0x00000020
3366 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3367 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3368 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3369 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3370 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3371 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3372 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3373 #define MR_TOGGLE_RX            0x00002000
3374 #define MR_NP_RX                0x00004000
3375
3376 #define MR_LINK_OK              0x80000000
3377
3378         unsigned long link_time, cur_time;
3379
3380         u32 ability_match_cfg;
3381         int ability_match_count;
3382
3383         char ability_match, idle_match, ack_match;
3384
3385         u32 txconfig, rxconfig;
3386 #define ANEG_CFG_NP             0x00000080
3387 #define ANEG_CFG_ACK            0x00000040
3388 #define ANEG_CFG_RF2            0x00000020
3389 #define ANEG_CFG_RF1            0x00000010
3390 #define ANEG_CFG_PS2            0x00000001
3391 #define ANEG_CFG_PS1            0x00008000
3392 #define ANEG_CFG_HD             0x00004000
3393 #define ANEG_CFG_FD             0x00002000
3394 #define ANEG_CFG_INVAL          0x00001f06
3395
3396 };
3397 #define ANEG_OK         0
3398 #define ANEG_DONE       1
3399 #define ANEG_TIMER_ENAB 2
3400 #define ANEG_FAILED     -1
3401
3402 #define ANEG_STATE_SETTLE_TIME  10000
3403
3404 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3405                                    struct tg3_fiber_aneginfo *ap)
3406 {
3407         u16 flowctrl;
3408         unsigned long delta;
3409         u32 rx_cfg_reg;
3410         int ret;
3411
3412         if (ap->state == ANEG_STATE_UNKNOWN) {
3413                 ap->rxconfig = 0;
3414                 ap->link_time = 0;
3415                 ap->cur_time = 0;
3416                 ap->ability_match_cfg = 0;
3417                 ap->ability_match_count = 0;
3418                 ap->ability_match = 0;
3419                 ap->idle_match = 0;
3420                 ap->ack_match = 0;
3421         }
3422         ap->cur_time++;
3423
3424         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3425                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3426
3427                 if (rx_cfg_reg != ap->ability_match_cfg) {
3428                         ap->ability_match_cfg = rx_cfg_reg;
3429                         ap->ability_match = 0;
3430                         ap->ability_match_count = 0;
3431                 } else {
3432                         if (++ap->ability_match_count > 1) {
3433                                 ap->ability_match = 1;
3434                                 ap->ability_match_cfg = rx_cfg_reg;
3435                         }
3436                 }
3437                 if (rx_cfg_reg & ANEG_CFG_ACK)
3438                         ap->ack_match = 1;
3439                 else
3440                         ap->ack_match = 0;
3441
3442                 ap->idle_match = 0;
3443         } else {
3444                 ap->idle_match = 1;
3445                 ap->ability_match_cfg = 0;
3446                 ap->ability_match_count = 0;
3447                 ap->ability_match = 0;
3448                 ap->ack_match = 0;
3449
3450                 rx_cfg_reg = 0;
3451         }
3452
3453         ap->rxconfig = rx_cfg_reg;
3454         ret = ANEG_OK;
3455
3456         switch (ap->state) {
3457         case ANEG_STATE_UNKNOWN:
3458                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3459                         ap->state = ANEG_STATE_AN_ENABLE;
3460
3461                 /* fallthru */
3462         case ANEG_STATE_AN_ENABLE:
3463                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3464                 if (ap->flags & MR_AN_ENABLE) {
3465                         ap->link_time = 0;
3466                         ap->cur_time = 0;
3467                         ap->ability_match_cfg = 0;
3468                         ap->ability_match_count = 0;
3469                         ap->ability_match = 0;
3470                         ap->idle_match = 0;
3471                         ap->ack_match = 0;
3472
3473                         ap->state = ANEG_STATE_RESTART_INIT;
3474                 } else {
3475                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3476                 }
3477                 break;
3478
3479         case ANEG_STATE_RESTART_INIT:
3480                 ap->link_time = ap->cur_time;
3481                 ap->flags &= ~(MR_NP_LOADED);
3482                 ap->txconfig = 0;
3483                 tw32(MAC_TX_AUTO_NEG, 0);
3484                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3485                 tw32_f(MAC_MODE, tp->mac_mode);
3486                 udelay(40);
3487
3488                 ret = ANEG_TIMER_ENAB;
3489                 ap->state = ANEG_STATE_RESTART;
3490
3491                 /* fallthru */
3492         case ANEG_STATE_RESTART:
3493                 delta = ap->cur_time - ap->link_time;
3494                 if (delta > ANEG_STATE_SETTLE_TIME)
3495                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3496                 else
3497                         ret = ANEG_TIMER_ENAB;
3498                 break;
3499
3500         case ANEG_STATE_DISABLE_LINK_OK:
3501                 ret = ANEG_DONE;
3502                 break;
3503
3504         case ANEG_STATE_ABILITY_DETECT_INIT:
3505                 ap->flags &= ~(MR_TOGGLE_TX);
3506                 ap->txconfig = ANEG_CFG_FD;
3507                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3508                 if (flowctrl & ADVERTISE_1000XPAUSE)
3509                         ap->txconfig |= ANEG_CFG_PS1;
3510                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3511                         ap->txconfig |= ANEG_CFG_PS2;
3512                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3513                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3514                 tw32_f(MAC_MODE, tp->mac_mode);
3515                 udelay(40);
3516
3517                 ap->state = ANEG_STATE_ABILITY_DETECT;
3518                 break;
3519
3520         case ANEG_STATE_ABILITY_DETECT:
3521                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3522                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3523                 break;
3524
3525         case ANEG_STATE_ACK_DETECT_INIT:
3526                 ap->txconfig |= ANEG_CFG_ACK;
3527                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3528                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3529                 tw32_f(MAC_MODE, tp->mac_mode);
3530                 udelay(40);
3531
3532                 ap->state = ANEG_STATE_ACK_DETECT;
3533
3534                 /* fallthru */
3535         case ANEG_STATE_ACK_DETECT:
3536                 if (ap->ack_match != 0) {
3537                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3538                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3539                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3540                         } else {
3541                                 ap->state = ANEG_STATE_AN_ENABLE;
3542                         }
3543                 } else if (ap->ability_match != 0 &&
3544                            ap->rxconfig == 0) {
3545                         ap->state = ANEG_STATE_AN_ENABLE;
3546                 }
3547                 break;
3548
3549         case ANEG_STATE_COMPLETE_ACK_INIT:
3550                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3551                         ret = ANEG_FAILED;
3552                         break;
3553                 }
3554                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3555                                MR_LP_ADV_HALF_DUPLEX |
3556                                MR_LP_ADV_SYM_PAUSE |
3557                                MR_LP_ADV_ASYM_PAUSE |
3558                                MR_LP_ADV_REMOTE_FAULT1 |
3559                                MR_LP_ADV_REMOTE_FAULT2 |
3560                                MR_LP_ADV_NEXT_PAGE |
3561                                MR_TOGGLE_RX |
3562                                MR_NP_RX);
3563                 if (ap->rxconfig & ANEG_CFG_FD)
3564                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3565                 if (ap->rxconfig & ANEG_CFG_HD)
3566                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3567                 if (ap->rxconfig & ANEG_CFG_PS1)
3568                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3569                 if (ap->rxconfig & ANEG_CFG_PS2)
3570                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3571                 if (ap->rxconfig & ANEG_CFG_RF1)
3572                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3573                 if (ap->rxconfig & ANEG_CFG_RF2)
3574                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3575                 if (ap->rxconfig & ANEG_CFG_NP)
3576                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3577
3578                 ap->link_time = ap->cur_time;
3579
3580                 ap->flags ^= (MR_TOGGLE_TX);
3581                 if (ap->rxconfig & 0x0008)
3582                         ap->flags |= MR_TOGGLE_RX;
3583                 if (ap->rxconfig & ANEG_CFG_NP)
3584                         ap->flags |= MR_NP_RX;
3585                 ap->flags |= MR_PAGE_RX;
3586
3587                 ap->state = ANEG_STATE_COMPLETE_ACK;
3588                 ret = ANEG_TIMER_ENAB;
3589                 break;
3590
3591         case ANEG_STATE_COMPLETE_ACK:
3592                 if (ap->ability_match != 0 &&
3593                     ap->rxconfig == 0) {
3594                         ap->state = ANEG_STATE_AN_ENABLE;
3595                         break;
3596                 }
3597                 delta = ap->cur_time - ap->link_time;
3598                 if (delta > ANEG_STATE_SETTLE_TIME) {
3599                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3600                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3601                         } else {
3602                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3603                                     !(ap->flags & MR_NP_RX)) {
3604                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3605                                 } else {
3606                                         ret = ANEG_FAILED;
3607                                 }
3608                         }
3609                 }
3610                 break;
3611
3612         case ANEG_STATE_IDLE_DETECT_INIT:
3613                 ap->link_time = ap->cur_time;
3614                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3615                 tw32_f(MAC_MODE, tp->mac_mode);
3616                 udelay(40);
3617
3618                 ap->state = ANEG_STATE_IDLE_DETECT;
3619                 ret = ANEG_TIMER_ENAB;
3620                 break;
3621
3622         case ANEG_STATE_IDLE_DETECT:
3623                 if (ap->ability_match != 0 &&
3624                     ap->rxconfig == 0) {
3625                         ap->state = ANEG_STATE_AN_ENABLE;
3626                         break;
3627                 }
3628                 delta = ap->cur_time - ap->link_time;
3629                 if (delta > ANEG_STATE_SETTLE_TIME) {
3630                         /* XXX another gem from the Broadcom driver :( */
3631                         ap->state = ANEG_STATE_LINK_OK;
3632                 }
3633                 break;
3634
3635         case ANEG_STATE_LINK_OK:
3636                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3637                 ret = ANEG_DONE;
3638                 break;
3639
3640         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3641                 /* ??? unimplemented */
3642                 break;
3643
3644         case ANEG_STATE_NEXT_PAGE_WAIT:
3645                 /* ??? unimplemented */
3646                 break;
3647
3648         default:
3649                 ret = ANEG_FAILED;
3650                 break;
3651         }
3652
3653         return ret;
3654 }
3655
3656 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3657 {
3658         int res = 0;
3659         struct tg3_fiber_aneginfo aninfo;
3660         int status = ANEG_FAILED;
3661         unsigned int tick;
3662         u32 tmp;
3663
3664         tw32_f(MAC_TX_AUTO_NEG, 0);
3665
3666         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3667         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3668         udelay(40);
3669
3670         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3671         udelay(40);
3672
3673         memset(&aninfo, 0, sizeof(aninfo));
3674         aninfo.flags |= MR_AN_ENABLE;
3675         aninfo.state = ANEG_STATE_UNKNOWN;
3676         aninfo.cur_time = 0;
3677         tick = 0;
3678         while (++tick < 195000) {
3679                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3680                 if (status == ANEG_DONE || status == ANEG_FAILED)
3681                         break;
3682
3683                 udelay(1);
3684         }
3685
3686         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3687         tw32_f(MAC_MODE, tp->mac_mode);
3688         udelay(40);
3689
3690         *txflags = aninfo.txconfig;
3691         *rxflags = aninfo.flags;
3692
3693         if (status == ANEG_DONE &&
3694             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3695                              MR_LP_ADV_FULL_DUPLEX)))
3696                 res = 1;
3697
3698         return res;
3699 }
3700
3701 static void tg3_init_bcm8002(struct tg3 *tp)
3702 {
3703         u32 mac_status = tr32(MAC_STATUS);
3704         int i;
3705
3706         /* Reset when initting first time or we have a link. */
3707         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3708             !(mac_status & MAC_STATUS_PCS_SYNCED))
3709                 return;
3710
3711         /* Set PLL lock range. */
3712         tg3_writephy(tp, 0x16, 0x8007);
3713
3714         /* SW reset */
3715         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3716
3717         /* Wait for reset to complete. */
3718         /* XXX schedule_timeout() ... */
3719         for (i = 0; i < 500; i++)
3720                 udelay(10);
3721
3722         /* Config mode; select PMA/Ch 1 regs. */
3723         tg3_writephy(tp, 0x10, 0x8411);
3724
3725         /* Enable auto-lock and comdet, select txclk for tx. */
3726         tg3_writephy(tp, 0x11, 0x0a10);
3727
3728         tg3_writephy(tp, 0x18, 0x00a0);
3729         tg3_writephy(tp, 0x16, 0x41ff);
3730
3731         /* Assert and deassert POR. */
3732         tg3_writephy(tp, 0x13, 0x0400);
3733         udelay(40);
3734         tg3_writephy(tp, 0x13, 0x0000);
3735
3736         tg3_writephy(tp, 0x11, 0x0a50);
3737         udelay(40);
3738         tg3_writephy(tp, 0x11, 0x0a10);
3739
3740         /* Wait for signal to stabilize */
3741         /* XXX schedule_timeout() ... */
3742         for (i = 0; i < 15000; i++)
3743                 udelay(10);
3744
3745         /* Deselect the channel register so we can read the PHYID
3746          * later.
3747          */
3748         tg3_writephy(tp, 0x10, 0x8011);
3749 }
3750
3751 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3752 {
3753         u16 flowctrl;
3754         u32 sg_dig_ctrl, sg_dig_status;
3755         u32 serdes_cfg, expected_sg_dig_ctrl;
3756         int workaround, port_a;
3757         int current_link_up;
3758
3759         serdes_cfg = 0;
3760         expected_sg_dig_ctrl = 0;
3761         workaround = 0;
3762         port_a = 1;
3763         current_link_up = 0;
3764
3765         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3766             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3767                 workaround = 1;
3768                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3769                         port_a = 0;
3770
3771                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3772                 /* preserve bits 20-23 for voltage regulator */
3773                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3774         }
3775
3776         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3777
3778         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3779                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3780                         if (workaround) {
3781                                 u32 val = serdes_cfg;
3782
3783                                 if (port_a)
3784                                         val |= 0xc010000;
3785                                 else
3786                                         val |= 0x4010000;
3787                                 tw32_f(MAC_SERDES_CFG, val);
3788                         }
3789
3790                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3791                 }
3792                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3793                         tg3_setup_flow_control(tp, 0, 0);
3794                         current_link_up = 1;
3795                 }
3796                 goto out;
3797         }
3798
3799         /* Want auto-negotiation.  */
3800         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3801
3802         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3803         if (flowctrl & ADVERTISE_1000XPAUSE)
3804                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3805         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3806                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3807
3808         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3809                 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3810                     tp->serdes_counter &&
3811                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3812                                     MAC_STATUS_RCVD_CFG)) ==
3813                      MAC_STATUS_PCS_SYNCED)) {
3814                         tp->serdes_counter--;
3815                         current_link_up = 1;
3816                         goto out;
3817                 }
3818 restart_autoneg:
3819                 if (workaround)
3820                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3821                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3822                 udelay(5);
3823                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3824
3825                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3826                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3827         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3828                                  MAC_STATUS_SIGNAL_DET)) {
3829                 sg_dig_status = tr32(SG_DIG_STATUS);
3830                 mac_status = tr32(MAC_STATUS);
3831
3832                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3833                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3834                         u32 local_adv = 0, remote_adv = 0;
3835
3836                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3837                                 local_adv |= ADVERTISE_1000XPAUSE;
3838                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3839                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3840
3841                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3842                                 remote_adv |= LPA_1000XPAUSE;
3843                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3844                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3845
3846                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3847                         current_link_up = 1;
3848                         tp->serdes_counter = 0;
3849                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3850                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3851                         if (tp->serdes_counter)
3852                                 tp->serdes_counter--;
3853                         else {
3854                                 if (workaround) {
3855                                         u32 val = serdes_cfg;
3856
3857                                         if (port_a)
3858                                                 val |= 0xc010000;
3859                                         else
3860                                                 val |= 0x4010000;
3861
3862                                         tw32_f(MAC_SERDES_CFG, val);
3863                                 }
3864
3865                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3866                                 udelay(40);
3867
3868                                 /* Link parallel detection - link is up */
3869                                 /* only if we have PCS_SYNC and not */
3870                                 /* receiving config code words */
3871                                 mac_status = tr32(MAC_STATUS);
3872                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3873                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3874                                         tg3_setup_flow_control(tp, 0, 0);
3875                                         current_link_up = 1;
3876                                         tp->phy_flags |=
3877                                                 TG3_PHYFLG_PARALLEL_DETECT;
3878                                         tp->serdes_counter =
3879                                                 SERDES_PARALLEL_DET_TIMEOUT;
3880                                 } else
3881                                         goto restart_autoneg;
3882                         }
3883                 }
3884         } else {
3885                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3886                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3887         }
3888
3889 out:
3890         return current_link_up;
3891 }
3892
3893 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3894 {
3895         int current_link_up = 0;
3896
3897         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3898                 goto out;
3899
3900         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3901                 u32 txflags, rxflags;
3902                 int i;
3903
3904                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3905                         u32 local_adv = 0, remote_adv = 0;
3906
3907                         if (txflags & ANEG_CFG_PS1)
3908                                 local_adv |= ADVERTISE_1000XPAUSE;
3909                         if (txflags & ANEG_CFG_PS2)
3910                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3911
3912                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3913                                 remote_adv |= LPA_1000XPAUSE;
3914                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3915                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3916
3917                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3918
3919                         current_link_up = 1;
3920                 }
3921                 for (i = 0; i < 30; i++) {
3922                         udelay(20);
3923                         tw32_f(MAC_STATUS,
3924                                (MAC_STATUS_SYNC_CHANGED |
3925                                 MAC_STATUS_CFG_CHANGED));
3926                         udelay(40);
3927                         if ((tr32(MAC_STATUS) &
3928                              (MAC_STATUS_SYNC_CHANGED |
3929                               MAC_STATUS_CFG_CHANGED)) == 0)
3930                                 break;
3931                 }
3932
3933                 mac_status = tr32(MAC_STATUS);
3934                 if (current_link_up == 0 &&
3935                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3936                     !(mac_status & MAC_STATUS_RCVD_CFG))
3937                         current_link_up = 1;
3938         } else {
3939                 tg3_setup_flow_control(tp, 0, 0);
3940
3941                 /* Forcing 1000FD link up. */
3942                 current_link_up = 1;
3943
3944                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3945                 udelay(40);
3946
3947                 tw32_f(MAC_MODE, tp->mac_mode);
3948                 udelay(40);
3949         }
3950
3951 out:
3952         return current_link_up;
3953 }
3954
3955 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3956 {
3957         u32 orig_pause_cfg;
3958         u16 orig_active_speed;
3959         u8 orig_active_duplex;
3960         u32 mac_status;
3961         int current_link_up;
3962         int i;
3963
3964         orig_pause_cfg = tp->link_config.active_flowctrl;
3965         orig_active_speed = tp->link_config.active_speed;
3966         orig_active_duplex = tp->link_config.active_duplex;
3967
3968         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3969             netif_carrier_ok(tp->dev) &&
3970             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3971                 mac_status = tr32(MAC_STATUS);
3972                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3973                                MAC_STATUS_SIGNAL_DET |
3974                                MAC_STATUS_CFG_CHANGED |
3975                                MAC_STATUS_RCVD_CFG);
3976                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3977                                    MAC_STATUS_SIGNAL_DET)) {
3978                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3979                                             MAC_STATUS_CFG_CHANGED));
3980                         return 0;
3981                 }
3982         }
3983
3984         tw32_f(MAC_TX_AUTO_NEG, 0);
3985
3986         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3987         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3988         tw32_f(MAC_MODE, tp->mac_mode);
3989         udelay(40);
3990
3991         if (tp->phy_id == TG3_PHY_ID_BCM8002)
3992                 tg3_init_bcm8002(tp);
3993
3994         /* Enable link change event even when serdes polling.  */
3995         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3996         udelay(40);
3997
3998         current_link_up = 0;
3999         mac_status = tr32(MAC_STATUS);
4000
4001         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
4002                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4003         else
4004                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4005
4006         tp->napi[0].hw_status->status =
4007                 (SD_STATUS_UPDATED |
4008                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4009
4010         for (i = 0; i < 100; i++) {
4011                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4012                                     MAC_STATUS_CFG_CHANGED));
4013                 udelay(5);
4014                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4015                                          MAC_STATUS_CFG_CHANGED |
4016                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4017                         break;
4018         }
4019
4020         mac_status = tr32(MAC_STATUS);
4021         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4022                 current_link_up = 0;
4023                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4024                     tp->serdes_counter == 0) {
4025                         tw32_f(MAC_MODE, (tp->mac_mode |
4026                                           MAC_MODE_SEND_CONFIGS));
4027                         udelay(1);
4028                         tw32_f(MAC_MODE, tp->mac_mode);
4029                 }
4030         }
4031
4032         if (current_link_up == 1) {
4033                 tp->link_config.active_speed = SPEED_1000;
4034                 tp->link_config.active_duplex = DUPLEX_FULL;
4035                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4036                                     LED_CTRL_LNKLED_OVERRIDE |
4037                                     LED_CTRL_1000MBPS_ON));
4038         } else {
4039                 tp->link_config.active_speed = SPEED_INVALID;
4040                 tp->link_config.active_duplex = DUPLEX_INVALID;
4041                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4042                                     LED_CTRL_LNKLED_OVERRIDE |
4043                                     LED_CTRL_TRAFFIC_OVERRIDE));
4044         }
4045
4046         if (current_link_up != netif_carrier_ok(tp->dev)) {
4047                 if (current_link_up)
4048                         netif_carrier_on(tp->dev);
4049                 else
4050                         netif_carrier_off(tp->dev);
4051                 tg3_link_report(tp);
4052         } else {
4053                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4054                 if (orig_pause_cfg != now_pause_cfg ||
4055                     orig_active_speed != tp->link_config.active_speed ||
4056                     orig_active_duplex != tp->link_config.active_duplex)
4057                         tg3_link_report(tp);
4058         }
4059
4060         return 0;
4061 }
4062
4063 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4064 {
4065         int current_link_up, err = 0;
4066         u32 bmsr, bmcr;
4067         u16 current_speed;
4068         u8 current_duplex;
4069         u32 local_adv, remote_adv;
4070
4071         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4072         tw32_f(MAC_MODE, tp->mac_mode);
4073         udelay(40);
4074
4075         tw32(MAC_EVENT, 0);
4076
4077         tw32_f(MAC_STATUS,
4078              (MAC_STATUS_SYNC_CHANGED |
4079               MAC_STATUS_CFG_CHANGED |
4080               MAC_STATUS_MI_COMPLETION |
4081               MAC_STATUS_LNKSTATE_CHANGED));
4082         udelay(40);
4083
4084         if (force_reset)
4085                 tg3_phy_reset(tp);
4086
4087         current_link_up = 0;
4088         current_speed = SPEED_INVALID;
4089         current_duplex = DUPLEX_INVALID;
4090
4091         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4092         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4093         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4094                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4095                         bmsr |= BMSR_LSTATUS;
4096                 else
4097                         bmsr &= ~BMSR_LSTATUS;
4098         }
4099
4100         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4101
4102         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4103             (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4104                 /* do nothing, just check for link up at the end */
4105         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4106                 u32 adv, new_adv;
4107
4108                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4109                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4110                                   ADVERTISE_1000XPAUSE |
4111                                   ADVERTISE_1000XPSE_ASYM |
4112                                   ADVERTISE_SLCT);
4113
4114                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4115
4116                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4117                         new_adv |= ADVERTISE_1000XHALF;
4118                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4119                         new_adv |= ADVERTISE_1000XFULL;
4120
4121                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4122                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4123                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4124                         tg3_writephy(tp, MII_BMCR, bmcr);
4125
4126                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4127                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4128                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4129
4130                         return err;
4131                 }
4132         } else {
4133                 u32 new_bmcr;
4134
4135                 bmcr &= ~BMCR_SPEED1000;
4136                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4137
4138                 if (tp->link_config.duplex == DUPLEX_FULL)
4139                         new_bmcr |= BMCR_FULLDPLX;
4140
4141                 if (new_bmcr != bmcr) {
4142                         /* BMCR_SPEED1000 is a reserved bit that needs
4143                          * to be set on write.
4144                          */
4145                         new_bmcr |= BMCR_SPEED1000;
4146
4147                         /* Force a linkdown */
4148                         if (netif_carrier_ok(tp->dev)) {
4149                                 u32 adv;
4150
4151                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4152                                 adv &= ~(ADVERTISE_1000XFULL |
4153                                          ADVERTISE_1000XHALF |
4154                                          ADVERTISE_SLCT);
4155                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4156                                 tg3_writephy(tp, MII_BMCR, bmcr |
4157                                                            BMCR_ANRESTART |
4158                                                            BMCR_ANENABLE);
4159                                 udelay(10);
4160                                 netif_carrier_off(tp->dev);
4161                         }
4162                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4163                         bmcr = new_bmcr;
4164                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4165                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4166                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4167                             ASIC_REV_5714) {
4168                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4169                                         bmsr |= BMSR_LSTATUS;
4170                                 else
4171                                         bmsr &= ~BMSR_LSTATUS;
4172                         }
4173                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4174                 }
4175         }
4176
4177         if (bmsr & BMSR_LSTATUS) {
4178                 current_speed = SPEED_1000;
4179                 current_link_up = 1;
4180                 if (bmcr & BMCR_FULLDPLX)
4181                         current_duplex = DUPLEX_FULL;
4182                 else
4183                         current_duplex = DUPLEX_HALF;
4184
4185                 local_adv = 0;
4186                 remote_adv = 0;
4187
4188                 if (bmcr & BMCR_ANENABLE) {
4189                         u32 common;
4190
4191                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4192                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4193                         common = local_adv & remote_adv;
4194                         if (common & (ADVERTISE_1000XHALF |
4195                                       ADVERTISE_1000XFULL)) {
4196                                 if (common & ADVERTISE_1000XFULL)
4197                                         current_duplex = DUPLEX_FULL;
4198                                 else
4199                                         current_duplex = DUPLEX_HALF;
4200                         } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4201                                 /* Link is up via parallel detect */
4202                         } else {
4203                                 current_link_up = 0;
4204                         }
4205                 }
4206         }
4207
4208         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4209                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4210
4211         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4212         if (tp->link_config.active_duplex == DUPLEX_HALF)
4213                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4214
4215         tw32_f(MAC_MODE, tp->mac_mode);
4216         udelay(40);
4217
4218         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4219
4220         tp->link_config.active_speed = current_speed;
4221         tp->link_config.active_duplex = current_duplex;
4222
4223         if (current_link_up != netif_carrier_ok(tp->dev)) {
4224                 if (current_link_up)
4225                         netif_carrier_on(tp->dev);
4226                 else {
4227                         netif_carrier_off(tp->dev);
4228                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4229                 }
4230                 tg3_link_report(tp);
4231         }
4232         return err;
4233 }
4234
4235 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4236 {
4237         if (tp->serdes_counter) {
4238                 /* Give autoneg time to complete. */
4239                 tp->serdes_counter--;
4240                 return;
4241         }
4242
4243         if (!netif_carrier_ok(tp->dev) &&
4244             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4245                 u32 bmcr;
4246
4247                 tg3_readphy(tp, MII_BMCR, &bmcr);
4248                 if (bmcr & BMCR_ANENABLE) {
4249                         u32 phy1, phy2;
4250
4251                         /* Select shadow register 0x1f */
4252                         tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4253                         tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4254
4255                         /* Select expansion interrupt status register */
4256                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4257                                          MII_TG3_DSP_EXP1_INT_STAT);
4258                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4259                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4260
4261                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4262                                 /* We have signal detect and not receiving
4263                                  * config code words, link is up by parallel
4264                                  * detection.
4265                                  */
4266
4267                                 bmcr &= ~BMCR_ANENABLE;
4268                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4269                                 tg3_writephy(tp, MII_BMCR, bmcr);
4270                                 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4271                         }
4272                 }
4273         } else if (netif_carrier_ok(tp->dev) &&
4274                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4275                    (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4276                 u32 phy2;
4277
4278                 /* Select expansion interrupt status register */
4279                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4280                                  MII_TG3_DSP_EXP1_INT_STAT);
4281                 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4282                 if (phy2 & 0x20) {
4283                         u32 bmcr;
4284
4285                         /* Config code words received, turn on autoneg. */
4286                         tg3_readphy(tp, MII_BMCR, &bmcr);
4287                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4288
4289                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4290
4291                 }
4292         }
4293 }
4294
4295 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4296 {
4297         int err;
4298
4299         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4300                 err = tg3_setup_fiber_phy(tp, force_reset);
4301         else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4302                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4303         else
4304                 err = tg3_setup_copper_phy(tp, force_reset);
4305
4306         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4307                 u32 val, scale;
4308
4309                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4310                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4311                         scale = 65;
4312                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4313                         scale = 6;
4314                 else
4315                         scale = 12;
4316
4317                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4318                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4319                 tw32(GRC_MISC_CFG, val);
4320         }
4321
4322         if (tp->link_config.active_speed == SPEED_1000 &&
4323             tp->link_config.active_duplex == DUPLEX_HALF)
4324                 tw32(MAC_TX_LENGTHS,
4325                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4326                       (6 << TX_LENGTHS_IPG_SHIFT) |
4327                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4328         else
4329                 tw32(MAC_TX_LENGTHS,
4330                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4331                       (6 << TX_LENGTHS_IPG_SHIFT) |
4332                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4333
4334         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4335                 if (netif_carrier_ok(tp->dev)) {
4336                         tw32(HOSTCC_STAT_COAL_TICKS,
4337                              tp->coal.stats_block_coalesce_usecs);
4338                 } else {
4339                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4340                 }
4341         }
4342
4343         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4344                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4345                 if (!netif_carrier_ok(tp->dev))
4346                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4347                               tp->pwrmgmt_thresh;
4348                 else
4349                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4350                 tw32(PCIE_PWR_MGMT_THRESH, val);
4351         }
4352
4353         return err;
4354 }
4355
4356 /* This is called whenever we suspect that the system chipset is re-
4357  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4358  * is bogus tx completions. We try to recover by setting the
4359  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4360  * in the workqueue.
4361  */
4362 static void tg3_tx_recover(struct tg3 *tp)
4363 {
4364         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4365                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4366
4367         netdev_warn(tp->dev,
4368                     "The system may be re-ordering memory-mapped I/O "
4369                     "cycles to the network device, attempting to recover. "
4370                     "Please report the problem to the driver maintainer "
4371                     "and include system chipset information.\n");
4372
4373         spin_lock(&tp->lock);
4374         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4375         spin_unlock(&tp->lock);
4376 }
4377
4378 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4379 {
4380         /* Tell compiler to fetch tx indices from memory. */
4381         barrier();
4382         return tnapi->tx_pending -
4383                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4384 }
4385
4386 /* Tigon3 never reports partial packet sends.  So we do not
4387  * need special logic to handle SKBs that have not had all
4388  * of their frags sent yet, like SunGEM does.
4389  */
4390 static void tg3_tx(struct tg3_napi *tnapi)
4391 {
4392         struct tg3 *tp = tnapi->tp;
4393         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4394         u32 sw_idx = tnapi->tx_cons;
4395         struct netdev_queue *txq;
4396         int index = tnapi - tp->napi;
4397
4398         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4399                 index--;
4400
4401         txq = netdev_get_tx_queue(tp->dev, index);
4402
4403         while (sw_idx != hw_idx) {
4404                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4405                 struct sk_buff *skb = ri->skb;
4406                 int i, tx_bug = 0;
4407
4408                 if (unlikely(skb == NULL)) {
4409                         tg3_tx_recover(tp);
4410                         return;
4411                 }
4412
4413                 pci_unmap_single(tp->pdev,
4414                                  dma_unmap_addr(ri, mapping),
4415                                  skb_headlen(skb),
4416                                  PCI_DMA_TODEVICE);
4417
4418                 ri->skb = NULL;
4419
4420                 sw_idx = NEXT_TX(sw_idx);
4421
4422                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4423                         ri = &tnapi->tx_buffers[sw_idx];
4424                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4425                                 tx_bug = 1;
4426
4427                         pci_unmap_page(tp->pdev,
4428                                        dma_unmap_addr(ri, mapping),
4429                                        skb_shinfo(skb)->frags[i].size,
4430                                        PCI_DMA_TODEVICE);
4431                         sw_idx = NEXT_TX(sw_idx);
4432                 }
4433
4434                 dev_kfree_skb(skb);
4435
4436                 if (unlikely(tx_bug)) {
4437                         tg3_tx_recover(tp);
4438                         return;
4439                 }
4440         }
4441
4442         tnapi->tx_cons = sw_idx;
4443
4444         /* Need to make the tx_cons update visible to tg3_start_xmit()
4445          * before checking for netif_queue_stopped().  Without the
4446          * memory barrier, there is a small possibility that tg3_start_xmit()
4447          * will miss it and cause the queue to be stopped forever.
4448          */
4449         smp_mb();
4450
4451         if (unlikely(netif_tx_queue_stopped(txq) &&
4452                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4453                 __netif_tx_lock(txq, smp_processor_id());
4454                 if (netif_tx_queue_stopped(txq) &&
4455                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4456                         netif_tx_wake_queue(txq);
4457                 __netif_tx_unlock(txq);
4458         }
4459 }
4460
4461 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4462 {
4463         if (!ri->skb)
4464                 return;
4465
4466         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4467                          map_sz, PCI_DMA_FROMDEVICE);
4468         dev_kfree_skb_any(ri->skb);
4469         ri->skb = NULL;
4470 }
4471
4472 /* Returns size of skb allocated or < 0 on error.
4473  *
4474  * We only need to fill in the address because the other members
4475  * of the RX descriptor are invariant, see tg3_init_rings.
4476  *
4477  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4478  * posting buffers we only dirty the first cache line of the RX
4479  * descriptor (containing the address).  Whereas for the RX status
4480  * buffers the cpu only reads the last cacheline of the RX descriptor
4481  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4482  */
4483 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4484                             u32 opaque_key, u32 dest_idx_unmasked)
4485 {
4486         struct tg3_rx_buffer_desc *desc;
4487         struct ring_info *map, *src_map;
4488         struct sk_buff *skb;
4489         dma_addr_t mapping;
4490         int skb_size, dest_idx;
4491
4492         src_map = NULL;
4493         switch (opaque_key) {
4494         case RXD_OPAQUE_RING_STD:
4495                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4496                 desc = &tpr->rx_std[dest_idx];
4497                 map = &tpr->rx_std_buffers[dest_idx];
4498                 skb_size = tp->rx_pkt_map_sz;
4499                 break;
4500
4501         case RXD_OPAQUE_RING_JUMBO:
4502                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4503                 desc = &tpr->rx_jmb[dest_idx].std;
4504                 map = &tpr->rx_jmb_buffers[dest_idx];
4505                 skb_size = TG3_RX_JMB_MAP_SZ;
4506                 break;
4507
4508         default:
4509                 return -EINVAL;
4510         }
4511
4512         /* Do not overwrite any of the map or rp information
4513          * until we are sure we can commit to a new buffer.
4514          *
4515          * Callers depend upon this behavior and assume that
4516          * we leave everything unchanged if we fail.
4517          */
4518         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4519         if (skb == NULL)
4520                 return -ENOMEM;
4521
4522         skb_reserve(skb, tp->rx_offset);
4523
4524         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4525                                  PCI_DMA_FROMDEVICE);
4526         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4527                 dev_kfree_skb(skb);
4528                 return -EIO;
4529         }
4530
4531         map->skb = skb;
4532         dma_unmap_addr_set(map, mapping, mapping);
4533
4534         desc->addr_hi = ((u64)mapping >> 32);
4535         desc->addr_lo = ((u64)mapping & 0xffffffff);
4536
4537         return skb_size;
4538 }
4539
4540 /* We only need to move over in the address because the other
4541  * members of the RX descriptor are invariant.  See notes above
4542  * tg3_alloc_rx_skb for full details.
4543  */
4544 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4545                            struct tg3_rx_prodring_set *dpr,
4546                            u32 opaque_key, int src_idx,
4547                            u32 dest_idx_unmasked)
4548 {
4549         struct tg3 *tp = tnapi->tp;
4550         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4551         struct ring_info *src_map, *dest_map;
4552         struct tg3_rx_prodring_set *spr = &tp->prodring[0];
4553         int dest_idx;
4554
4555         switch (opaque_key) {
4556         case RXD_OPAQUE_RING_STD:
4557                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4558                 dest_desc = &dpr->rx_std[dest_idx];
4559                 dest_map = &dpr->rx_std_buffers[dest_idx];
4560                 src_desc = &spr->rx_std[src_idx];
4561                 src_map = &spr->rx_std_buffers[src_idx];
4562                 break;
4563
4564         case RXD_OPAQUE_RING_JUMBO:
4565                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4566                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4567                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4568                 src_desc = &spr->rx_jmb[src_idx].std;
4569                 src_map = &spr->rx_jmb_buffers[src_idx];
4570                 break;
4571
4572         default:
4573                 return;
4574         }
4575
4576         dest_map->skb = src_map->skb;
4577         dma_unmap_addr_set(dest_map, mapping,
4578                            dma_unmap_addr(src_map, mapping));
4579         dest_desc->addr_hi = src_desc->addr_hi;
4580         dest_desc->addr_lo = src_desc->addr_lo;
4581
4582         /* Ensure that the update to the skb happens after the physical
4583          * addresses have been transferred to the new BD location.
4584          */
4585         smp_wmb();
4586
4587         src_map->skb = NULL;
4588 }
4589
4590 /* The RX ring scheme is composed of multiple rings which post fresh
4591  * buffers to the chip, and one special ring the chip uses to report
4592  * status back to the host.
4593  *
4594  * The special ring reports the status of received packets to the
4595  * host.  The chip does not write into the original descriptor the
4596  * RX buffer was obtained from.  The chip simply takes the original
4597  * descriptor as provided by the host, updates the status and length
4598  * field, then writes this into the next status ring entry.
4599  *
4600  * Each ring the host uses to post buffers to the chip is described
4601  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4602  * it is first placed into the on-chip ram.  When the packet's length
4603  * is known, it walks down the TG3_BDINFO entries to select the ring.
4604  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4605  * which is within the range of the new packet's length is chosen.
4606  *
4607  * The "separate ring for rx status" scheme may sound queer, but it makes
4608  * sense from a cache coherency perspective.  If only the host writes
4609  * to the buffer post rings, and only the chip writes to the rx status
4610  * rings, then cache lines never move beyond shared-modified state.
4611  * If both the host and chip were to write into the same ring, cache line
4612  * eviction could occur since both entities want it in an exclusive state.
4613  */
4614 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4615 {
4616         struct tg3 *tp = tnapi->tp;
4617         u32 work_mask, rx_std_posted = 0;
4618         u32 std_prod_idx, jmb_prod_idx;
4619         u32 sw_idx = tnapi->rx_rcb_ptr;
4620         u16 hw_idx;
4621         int received;
4622         struct tg3_rx_prodring_set *tpr = tnapi->prodring;
4623
4624         hw_idx = *(tnapi->rx_rcb_prod_idx);
4625         /*
4626          * We need to order the read of hw_idx and the read of
4627          * the opaque cookie.
4628          */
4629         rmb();
4630         work_mask = 0;
4631         received = 0;
4632         std_prod_idx = tpr->rx_std_prod_idx;
4633         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4634         while (sw_idx != hw_idx && budget > 0) {
4635                 struct ring_info *ri;
4636                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4637                 unsigned int len;
4638                 struct sk_buff *skb;
4639                 dma_addr_t dma_addr;
4640                 u32 opaque_key, desc_idx, *post_ptr;
4641                 bool hw_vlan __maybe_unused = false;
4642                 u16 vtag __maybe_unused = 0;
4643
4644                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4645                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4646                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4647                         ri = &tp->prodring[0].rx_std_buffers[desc_idx];
4648                         dma_addr = dma_unmap_addr(ri, mapping);
4649                         skb = ri->skb;
4650                         post_ptr = &std_prod_idx;
4651                         rx_std_posted++;
4652                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4653                         ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
4654                         dma_addr = dma_unmap_addr(ri, mapping);
4655                         skb = ri->skb;
4656                         post_ptr = &jmb_prod_idx;
4657                 } else
4658                         goto next_pkt_nopost;
4659
4660                 work_mask |= opaque_key;
4661
4662                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4663                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4664                 drop_it:
4665                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4666                                        desc_idx, *post_ptr);
4667                 drop_it_no_recycle:
4668                         /* Other statistics kept track of by card. */
4669                         tp->net_stats.rx_dropped++;
4670                         goto next_pkt;
4671                 }
4672
4673                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4674                       ETH_FCS_LEN;
4675
4676                 if (len > TG3_RX_COPY_THRESH(tp)) {
4677                         int skb_size;
4678
4679                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4680                                                     *post_ptr);
4681                         if (skb_size < 0)
4682                                 goto drop_it;
4683
4684                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4685                                          PCI_DMA_FROMDEVICE);
4686
4687                         /* Ensure that the update to the skb happens
4688                          * after the usage of the old DMA mapping.
4689                          */
4690                         smp_wmb();
4691
4692                         ri->skb = NULL;
4693
4694                         skb_put(skb, len);
4695                 } else {
4696                         struct sk_buff *copy_skb;
4697
4698                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4699                                        desc_idx, *post_ptr);
4700
4701                         copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
4702                                                     TG3_RAW_IP_ALIGN);
4703                         if (copy_skb == NULL)
4704                                 goto drop_it_no_recycle;
4705
4706                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
4707                         skb_put(copy_skb, len);
4708                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4709                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4710                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4711
4712                         /* We'll reuse the original ring buffer. */
4713                         skb = copy_skb;
4714                 }
4715
4716                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4717                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4718                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4719                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4720                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4721                 else
4722                         skb->ip_summed = CHECKSUM_NONE;
4723
4724                 skb->protocol = eth_type_trans(skb, tp->dev);
4725
4726                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4727                     skb->protocol != htons(ETH_P_8021Q)) {
4728                         dev_kfree_skb(skb);
4729                         goto next_pkt;
4730                 }
4731
4732                 if (desc->type_flags & RXD_FLAG_VLAN &&
4733                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
4734                         vtag = desc->err_vlan & RXD_VLAN_MASK;
4735 #if TG3_VLAN_TAG_USED
4736                         if (tp->vlgrp)
4737                                 hw_vlan = true;
4738                         else
4739 #endif
4740                         {
4741                                 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
4742                                                     __skb_push(skb, VLAN_HLEN);
4743
4744                                 memmove(ve, skb->data + VLAN_HLEN,
4745                                         ETH_ALEN * 2);
4746                                 ve->h_vlan_proto = htons(ETH_P_8021Q);
4747                                 ve->h_vlan_TCI = htons(vtag);
4748                         }
4749                 }
4750
4751 #if TG3_VLAN_TAG_USED
4752                 if (hw_vlan)
4753                         vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
4754                 else
4755 #endif
4756                         napi_gro_receive(&tnapi->napi, skb);
4757
4758                 received++;
4759                 budget--;
4760
4761 next_pkt:
4762                 (*post_ptr)++;
4763
4764                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4765                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4766                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4767                                      tpr->rx_std_prod_idx);
4768                         work_mask &= ~RXD_OPAQUE_RING_STD;
4769                         rx_std_posted = 0;
4770                 }
4771 next_pkt_nopost:
4772                 sw_idx++;
4773                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4774
4775                 /* Refresh hw_idx to see if there is new work */
4776                 if (sw_idx == hw_idx) {
4777                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4778                         rmb();
4779                 }
4780         }
4781
4782         /* ACK the status ring. */
4783         tnapi->rx_rcb_ptr = sw_idx;
4784         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4785
4786         /* Refill RX ring(s). */
4787         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4788                 if (work_mask & RXD_OPAQUE_RING_STD) {
4789                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4790                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4791                                      tpr->rx_std_prod_idx);
4792                 }
4793                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4794                         tpr->rx_jmb_prod_idx = jmb_prod_idx %
4795                                                TG3_RX_JUMBO_RING_SIZE;
4796                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4797                                      tpr->rx_jmb_prod_idx);
4798                 }
4799                 mmiowb();
4800         } else if (work_mask) {
4801                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4802                  * updated before the producer indices can be updated.
4803                  */
4804                 smp_wmb();
4805
4806                 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4807                 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4808
4809                 if (tnapi != &tp->napi[1])
4810                         napi_schedule(&tp->napi[1].napi);
4811         }
4812
4813         return received;
4814 }
4815
4816 static void tg3_poll_link(struct tg3 *tp)
4817 {
4818         /* handle link change and other phy events */
4819         if (!(tp->tg3_flags &
4820               (TG3_FLAG_USE_LINKCHG_REG |
4821                TG3_FLAG_POLL_SERDES))) {
4822                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4823
4824                 if (sblk->status & SD_STATUS_LINK_CHG) {
4825                         sblk->status = SD_STATUS_UPDATED |
4826                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4827                         spin_lock(&tp->lock);
4828                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4829                                 tw32_f(MAC_STATUS,
4830                                      (MAC_STATUS_SYNC_CHANGED |
4831                                       MAC_STATUS_CFG_CHANGED |
4832                                       MAC_STATUS_MI_COMPLETION |
4833                                       MAC_STATUS_LNKSTATE_CHANGED));
4834                                 udelay(40);
4835                         } else
4836                                 tg3_setup_phy(tp, 0);
4837                         spin_unlock(&tp->lock);
4838                 }
4839         }
4840 }
4841
4842 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4843                                 struct tg3_rx_prodring_set *dpr,
4844                                 struct tg3_rx_prodring_set *spr)
4845 {
4846         u32 si, di, cpycnt, src_prod_idx;
4847         int i, err = 0;
4848
4849         while (1) {
4850                 src_prod_idx = spr->rx_std_prod_idx;
4851
4852                 /* Make sure updates to the rx_std_buffers[] entries and the
4853                  * standard producer index are seen in the correct order.
4854                  */
4855                 smp_rmb();
4856
4857                 if (spr->rx_std_cons_idx == src_prod_idx)
4858                         break;
4859
4860                 if (spr->rx_std_cons_idx < src_prod_idx)
4861                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4862                 else
4863                         cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4864
4865                 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4866
4867                 si = spr->rx_std_cons_idx;
4868                 di = dpr->rx_std_prod_idx;
4869
4870                 for (i = di; i < di + cpycnt; i++) {
4871                         if (dpr->rx_std_buffers[i].skb) {
4872                                 cpycnt = i - di;
4873                                 err = -ENOSPC;
4874                                 break;
4875                         }
4876                 }
4877
4878                 if (!cpycnt)
4879                         break;
4880
4881                 /* Ensure that updates to the rx_std_buffers ring and the
4882                  * shadowed hardware producer ring from tg3_recycle_skb() are
4883                  * ordered correctly WRT the skb check above.
4884                  */
4885                 smp_rmb();
4886
4887                 memcpy(&dpr->rx_std_buffers[di],
4888                        &spr->rx_std_buffers[si],
4889                        cpycnt * sizeof(struct ring_info));
4890
4891                 for (i = 0; i < cpycnt; i++, di++, si++) {
4892                         struct tg3_rx_buffer_desc *sbd, *dbd;
4893                         sbd = &spr->rx_std[si];
4894                         dbd = &dpr->rx_std[di];
4895                         dbd->addr_hi = sbd->addr_hi;
4896                         dbd->addr_lo = sbd->addr_lo;
4897                 }
4898
4899                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4900                                        TG3_RX_RING_SIZE;
4901                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4902                                        TG3_RX_RING_SIZE;
4903         }
4904
4905         while (1) {
4906                 src_prod_idx = spr->rx_jmb_prod_idx;
4907
4908                 /* Make sure updates to the rx_jmb_buffers[] entries and
4909                  * the jumbo producer index are seen in the correct order.
4910                  */
4911                 smp_rmb();
4912
4913                 if (spr->rx_jmb_cons_idx == src_prod_idx)
4914                         break;
4915
4916                 if (spr->rx_jmb_cons_idx < src_prod_idx)
4917                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4918                 else
4919                         cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4920
4921                 cpycnt = min(cpycnt,
4922                              TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4923
4924                 si = spr->rx_jmb_cons_idx;
4925                 di = dpr->rx_jmb_prod_idx;
4926
4927                 for (i = di; i < di + cpycnt; i++) {
4928                         if (dpr->rx_jmb_buffers[i].skb) {
4929                                 cpycnt = i - di;
4930                                 err = -ENOSPC;
4931                                 break;
4932                         }
4933                 }
4934
4935                 if (!cpycnt)
4936                         break;
4937
4938                 /* Ensure that updates to the rx_jmb_buffers ring and the
4939                  * shadowed hardware producer ring from tg3_recycle_skb() are
4940                  * ordered correctly WRT the skb check above.
4941                  */
4942                 smp_rmb();
4943
4944                 memcpy(&dpr->rx_jmb_buffers[di],
4945                        &spr->rx_jmb_buffers[si],
4946                        cpycnt * sizeof(struct ring_info));
4947
4948                 for (i = 0; i < cpycnt; i++, di++, si++) {
4949                         struct tg3_rx_buffer_desc *sbd, *dbd;
4950                         sbd = &spr->rx_jmb[si].std;
4951                         dbd = &dpr->rx_jmb[di].std;
4952                         dbd->addr_hi = sbd->addr_hi;
4953                         dbd->addr_lo = sbd->addr_lo;
4954                 }
4955
4956                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4957                                        TG3_RX_JUMBO_RING_SIZE;
4958                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4959                                        TG3_RX_JUMBO_RING_SIZE;
4960         }
4961
4962         return err;
4963 }
4964
4965 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4966 {
4967         struct tg3 *tp = tnapi->tp;
4968
4969         /* run TX completion thread */
4970         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4971                 tg3_tx(tnapi);
4972                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4973                         return work_done;
4974         }
4975
4976         /* run RX thread, within the bounds set by NAPI.
4977          * All RX "locking" is done by ensuring outside
4978          * code synchronizes with tg3->napi.poll()
4979          */
4980         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4981                 work_done += tg3_rx(tnapi, budget - work_done);
4982
4983         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4984                 struct tg3_rx_prodring_set *dpr = &tp->prodring[0];
4985                 int i, err = 0;
4986                 u32 std_prod_idx = dpr->rx_std_prod_idx;
4987                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
4988
4989                 for (i = 1; i < tp->irq_cnt; i++)
4990                         err |= tg3_rx_prodring_xfer(tp, dpr,
4991                                                     tp->napi[i].prodring);
4992
4993                 wmb();
4994
4995                 if (std_prod_idx != dpr->rx_std_prod_idx)
4996                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4997                                      dpr->rx_std_prod_idx);
4998
4999                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5000                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5001                                      dpr->rx_jmb_prod_idx);
5002
5003                 mmiowb();
5004
5005                 if (err)
5006                         tw32_f(HOSTCC_MODE, tp->coal_now);
5007         }
5008
5009         return work_done;
5010 }
5011
5012 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5013 {
5014         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5015         struct tg3 *tp = tnapi->tp;
5016         int work_done = 0;
5017         struct tg3_hw_status *sblk = tnapi->hw_status;
5018
5019         while (1) {
5020                 work_done = tg3_poll_work(tnapi, work_done, budget);
5021
5022                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5023                         goto tx_recovery;
5024
5025                 if (unlikely(work_done >= budget))
5026                         break;
5027
5028                 /* tp->last_tag is used in tg3_int_reenable() below
5029                  * to tell the hw how much work has been processed,
5030                  * so we must read it before checking for more work.
5031                  */
5032                 tnapi->last_tag = sblk->status_tag;
5033                 tnapi->last_irq_tag = tnapi->last_tag;
5034                 rmb();
5035
5036                 /* check for RX/TX work to do */
5037                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5038                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5039                         napi_complete(napi);
5040                         /* Reenable interrupts. */
5041                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5042                         mmiowb();
5043                         break;
5044                 }
5045         }
5046
5047         return work_done;
5048
5049 tx_recovery:
5050         /* work_done is guaranteed to be less than budget. */
5051         napi_complete(napi);
5052         schedule_work(&tp->reset_task);
5053         return work_done;
5054 }
5055
5056 static int tg3_poll(struct napi_struct *napi, int budget)
5057 {
5058         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5059         struct tg3 *tp = tnapi->tp;
5060         int work_done = 0;
5061         struct tg3_hw_status *sblk = tnapi->hw_status;
5062
5063         while (1) {
5064                 tg3_poll_link(tp);
5065
5066                 work_done = tg3_poll_work(tnapi, work_done, budget);
5067
5068                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5069                         goto tx_recovery;
5070
5071                 if (unlikely(work_done >= budget))
5072                         break;
5073
5074                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5075                         /* tp->last_tag is used in tg3_int_reenable() below
5076                          * to tell the hw how much work has been processed,
5077                          * so we must read it before checking for more work.
5078                          */
5079                         tnapi->last_tag = sblk->status_tag;
5080                         tnapi->last_irq_tag = tnapi->last_tag;
5081                         rmb();
5082                 } else
5083                         sblk->status &= ~SD_STATUS_UPDATED;
5084
5085                 if (likely(!tg3_has_work(tnapi))) {
5086                         napi_complete(napi);
5087                         tg3_int_reenable(tnapi);
5088                         break;
5089                 }
5090         }
5091
5092         return work_done;
5093
5094 tx_recovery:
5095         /* work_done is guaranteed to be less than budget. */
5096         napi_complete(napi);
5097         schedule_work(&tp->reset_task);
5098         return work_done;
5099 }
5100
5101 static void tg3_irq_quiesce(struct tg3 *tp)
5102 {
5103         int i;
5104
5105         BUG_ON(tp->irq_sync);
5106
5107         tp->irq_sync = 1;
5108         smp_mb();
5109
5110         for (i = 0; i < tp->irq_cnt; i++)
5111                 synchronize_irq(tp->napi[i].irq_vec);
5112 }
5113
5114 static inline int tg3_irq_sync(struct tg3 *tp)
5115 {
5116         return tp->irq_sync;
5117 }
5118
5119 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5120  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5121  * with as well.  Most of the time, this is not necessary except when
5122  * shutting down the device.
5123  */
5124 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5125 {
5126         spin_lock_bh(&tp->lock);
5127         if (irq_sync)
5128                 tg3_irq_quiesce(tp);
5129 }
5130
5131 static inline void tg3_full_unlock(struct tg3 *tp)
5132 {
5133         spin_unlock_bh(&tp->lock);
5134 }
5135
5136 /* One-shot MSI handler - Chip automatically disables interrupt
5137  * after sending MSI so driver doesn't have to do it.
5138  */
5139 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5140 {
5141         struct tg3_napi *tnapi = dev_id;
5142         struct tg3 *tp = tnapi->tp;
5143
5144         prefetch(tnapi->hw_status);
5145         if (tnapi->rx_rcb)
5146                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5147
5148         if (likely(!tg3_irq_sync(tp)))
5149                 napi_schedule(&tnapi->napi);
5150
5151         return IRQ_HANDLED;
5152 }
5153
5154 /* MSI ISR - No need to check for interrupt sharing and no need to
5155  * flush status block and interrupt mailbox. PCI ordering rules
5156  * guarantee that MSI will arrive after the status block.
5157  */
5158 static irqreturn_t tg3_msi(int irq, void *dev_id)
5159 {
5160         struct tg3_napi *tnapi = dev_id;
5161         struct tg3 *tp = tnapi->tp;
5162
5163         prefetch(tnapi->hw_status);
5164         if (tnapi->rx_rcb)
5165                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5166         /*
5167          * Writing any value to intr-mbox-0 clears PCI INTA# and
5168          * chip-internal interrupt pending events.
5169          * Writing non-zero to intr-mbox-0 additional tells the
5170          * NIC to stop sending us irqs, engaging "in-intr-handler"
5171          * event coalescing.
5172          */
5173         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5174         if (likely(!tg3_irq_sync(tp)))
5175                 napi_schedule(&tnapi->napi);
5176
5177         return IRQ_RETVAL(1);
5178 }
5179
5180 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5181 {
5182         struct tg3_napi *tnapi = dev_id;
5183         struct tg3 *tp = tnapi->tp;
5184         struct tg3_hw_status *sblk = tnapi->hw_status;
5185         unsigned int handled = 1;
5186
5187         /* In INTx mode, it is possible for the interrupt to arrive at
5188          * the CPU before the status block posted prior to the interrupt.
5189          * Reading the PCI State register will confirm whether the
5190          * interrupt is ours and will flush the status block.
5191          */
5192         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5193                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5194                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5195                         handled = 0;
5196                         goto out;
5197                 }
5198         }
5199
5200         /*
5201          * Writing any value to intr-mbox-0 clears PCI INTA# and
5202          * chip-internal interrupt pending events.
5203          * Writing non-zero to intr-mbox-0 additional tells the
5204          * NIC to stop sending us irqs, engaging "in-intr-handler"
5205          * event coalescing.
5206          *
5207          * Flush the mailbox to de-assert the IRQ immediately to prevent
5208          * spurious interrupts.  The flush impacts performance but
5209          * excessive spurious interrupts can be worse in some cases.
5210          */
5211         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5212         if (tg3_irq_sync(tp))
5213                 goto out;
5214         sblk->status &= ~SD_STATUS_UPDATED;
5215         if (likely(tg3_has_work(tnapi))) {
5216                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5217                 napi_schedule(&tnapi->napi);
5218         } else {
5219                 /* No work, shared interrupt perhaps?  re-enable
5220                  * interrupts, and flush that PCI write
5221                  */
5222                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5223                                0x00000000);
5224         }
5225 out:
5226         return IRQ_RETVAL(handled);
5227 }
5228
5229 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5230 {
5231         struct tg3_napi *tnapi = dev_id;
5232         struct tg3 *tp = tnapi->tp;
5233         struct tg3_hw_status *sblk = tnapi->hw_status;
5234         unsigned int handled = 1;
5235
5236         /* In INTx mode, it is possible for the interrupt to arrive at
5237          * the CPU before the status block posted prior to the interrupt.
5238          * Reading the PCI State register will confirm whether the
5239          * interrupt is ours and will flush the status block.
5240          */
5241         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5242                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5243                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5244                         handled = 0;
5245                         goto out;
5246                 }
5247         }
5248
5249         /*
5250          * writing any value to intr-mbox-0 clears PCI INTA# and
5251          * chip-internal interrupt pending events.
5252          * writing non-zero to intr-mbox-0 additional tells the
5253          * NIC to stop sending us irqs, engaging "in-intr-handler"
5254          * event coalescing.
5255          *
5256          * Flush the mailbox to de-assert the IRQ immediately to prevent
5257          * spurious interrupts.  The flush impacts performance but
5258          * excessive spurious interrupts can be worse in some cases.
5259          */
5260         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5261
5262         /*
5263          * In a shared interrupt configuration, sometimes other devices'
5264          * interrupts will scream.  We record the current status tag here
5265          * so that the above check can report that the screaming interrupts
5266          * are unhandled.  Eventually they will be silenced.
5267          */
5268         tnapi->last_irq_tag = sblk->status_tag;
5269
5270         if (tg3_irq_sync(tp))
5271                 goto out;
5272
5273         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5274
5275         napi_schedule(&tnapi->napi);
5276
5277 out:
5278         return IRQ_RETVAL(handled);
5279 }
5280
5281 /* ISR for interrupt test */
5282 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5283 {
5284         struct tg3_napi *tnapi = dev_id;
5285         struct tg3 *tp = tnapi->tp;
5286         struct tg3_hw_status *sblk = tnapi->hw_status;
5287
5288         if ((sblk->status & SD_STATUS_UPDATED) ||
5289             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5290                 tg3_disable_ints(tp);
5291                 return IRQ_RETVAL(1);
5292         }
5293         return IRQ_RETVAL(0);
5294 }
5295
5296 static int tg3_init_hw(struct tg3 *, int);
5297 static int tg3_halt(struct tg3 *, int, int);
5298
5299 /* Restart hardware after configuration changes, self-test, etc.
5300  * Invoked with tp->lock held.
5301  */
5302 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5303         __releases(tp->lock)
5304         __acquires(tp->lock)
5305 {
5306         int err;
5307
5308         err = tg3_init_hw(tp, reset_phy);
5309         if (err) {
5310                 netdev_err(tp->dev,
5311                            "Failed to re-initialize device, aborting\n");
5312                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5313                 tg3_full_unlock(tp);
5314                 del_timer_sync(&tp->timer);
5315                 tp->irq_sync = 0;
5316                 tg3_napi_enable(tp);
5317                 dev_close(tp->dev);
5318                 tg3_full_lock(tp, 0);
5319         }
5320         return err;
5321 }
5322
5323 #ifdef CONFIG_NET_POLL_CONTROLLER
5324 static void tg3_poll_controller(struct net_device *dev)
5325 {
5326         int i;
5327         struct tg3 *tp = netdev_priv(dev);
5328
5329         for (i = 0; i < tp->irq_cnt; i++)
5330                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5331 }
5332 #endif
5333
5334 static void tg3_reset_task(struct work_struct *work)
5335 {
5336         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5337         int err;
5338         unsigned int restart_timer;
5339
5340         tg3_full_lock(tp, 0);
5341
5342         if (!netif_running(tp->dev)) {
5343                 tg3_full_unlock(tp);
5344                 return;
5345         }
5346
5347         tg3_full_unlock(tp);
5348
5349         tg3_phy_stop(tp);
5350
5351         tg3_netif_stop(tp);
5352
5353         tg3_full_lock(tp, 1);
5354
5355         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5356         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5357
5358         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5359                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5360                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5361                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5362                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5363         }
5364
5365         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5366         err = tg3_init_hw(tp, 1);
5367         if (err)
5368                 goto out;
5369
5370         tg3_netif_start(tp);
5371
5372         if (restart_timer)
5373                 mod_timer(&tp->timer, jiffies + 1);
5374
5375 out:
5376         tg3_full_unlock(tp);
5377
5378         if (!err)
5379                 tg3_phy_start(tp);
5380 }
5381
5382 static void tg3_dump_short_state(struct tg3 *tp)
5383 {
5384         netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5385                    tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5386         netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5387                    tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5388 }
5389
5390 static void tg3_tx_timeout(struct net_device *dev)
5391 {
5392         struct tg3 *tp = netdev_priv(dev);
5393
5394         if (netif_msg_tx_err(tp)) {
5395                 netdev_err(dev, "transmit timed out, resetting\n");
5396                 tg3_dump_short_state(tp);
5397         }
5398
5399         schedule_work(&tp->reset_task);
5400 }
5401
5402 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5403 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5404 {
5405         u32 base = (u32) mapping & 0xffffffff;
5406
5407         return ((base > 0xffffdcc0) &&
5408                 (base + len + 8 < base));
5409 }
5410
5411 /* Test for DMA addresses > 40-bit */
5412 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5413                                           int len)
5414 {
5415 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5416         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5417                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5418         return 0;
5419 #else
5420         return 0;
5421 #endif
5422 }
5423
5424 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5425
5426 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5427 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5428                                        struct sk_buff *skb, u32 last_plus_one,
5429                                        u32 *start, u32 base_flags, u32 mss)
5430 {
5431         struct tg3 *tp = tnapi->tp;
5432         struct sk_buff *new_skb;
5433         dma_addr_t new_addr = 0;
5434         u32 entry = *start;
5435         int i, ret = 0;
5436
5437         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5438                 new_skb = skb_copy(skb, GFP_ATOMIC);
5439         else {
5440                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5441
5442                 new_skb = skb_copy_expand(skb,
5443                                           skb_headroom(skb) + more_headroom,
5444                                           skb_tailroom(skb), GFP_ATOMIC);
5445         }
5446
5447         if (!new_skb) {
5448                 ret = -1;
5449         } else {
5450                 /* New SKB is guaranteed to be linear. */
5451                 entry = *start;
5452                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5453                                           PCI_DMA_TODEVICE);
5454                 /* Make sure the mapping succeeded */
5455                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5456                         ret = -1;
5457                         dev_kfree_skb(new_skb);
5458                         new_skb = NULL;
5459
5460                 /* Make sure new skb does not cross any 4G boundaries.
5461                  * Drop the packet if it does.
5462                  */
5463                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5464                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5465                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5466                                          PCI_DMA_TODEVICE);
5467                         ret = -1;
5468                         dev_kfree_skb(new_skb);
5469                         new_skb = NULL;
5470                 } else {
5471                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5472                                     base_flags, 1 | (mss << 1));
5473                         *start = NEXT_TX(entry);
5474                 }
5475         }
5476
5477         /* Now clean up the sw ring entries. */
5478         i = 0;
5479         while (entry != last_plus_one) {
5480                 int len;
5481
5482                 if (i == 0)
5483                         len = skb_headlen(skb);
5484                 else
5485                         len = skb_shinfo(skb)->frags[i-1].size;
5486
5487                 pci_unmap_single(tp->pdev,
5488                                  dma_unmap_addr(&tnapi->tx_buffers[entry],
5489                                                 mapping),
5490                                  len, PCI_DMA_TODEVICE);
5491                 if (i == 0) {
5492                         tnapi->tx_buffers[entry].skb = new_skb;
5493                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5494                                            new_addr);
5495                 } else {
5496                         tnapi->tx_buffers[entry].skb = NULL;
5497                 }
5498                 entry = NEXT_TX(entry);
5499                 i++;
5500         }
5501
5502         dev_kfree_skb(skb);
5503
5504         return ret;
5505 }
5506
5507 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5508                         dma_addr_t mapping, int len, u32 flags,
5509                         u32 mss_and_is_end)
5510 {
5511         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5512         int is_end = (mss_and_is_end & 0x1);
5513         u32 mss = (mss_and_is_end >> 1);
5514         u32 vlan_tag = 0;
5515
5516         if (is_end)
5517                 flags |= TXD_FLAG_END;
5518         if (flags & TXD_FLAG_VLAN) {
5519                 vlan_tag = flags >> 16;
5520                 flags &= 0xffff;
5521         }
5522         vlan_tag |= (mss << TXD_MSS_SHIFT);
5523
5524         txd->addr_hi = ((u64) mapping >> 32);
5525         txd->addr_lo = ((u64) mapping & 0xffffffff);
5526         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5527         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5528 }
5529
5530 /* hard_start_xmit for devices that don't have any bugs and
5531  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5532  */
5533 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5534                                   struct net_device *dev)
5535 {
5536         struct tg3 *tp = netdev_priv(dev);
5537         u32 len, entry, base_flags, mss;
5538         dma_addr_t mapping;
5539         struct tg3_napi *tnapi;
5540         struct netdev_queue *txq;
5541         unsigned int i, last;
5542
5543         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5544         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5545         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5546                 tnapi++;
5547
5548         /* We are running in BH disabled context with netif_tx_lock
5549          * and TX reclaim runs via tp->napi.poll inside of a software
5550          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5551          * no IRQ context deadlocks to worry about either.  Rejoice!
5552          */
5553         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5554                 if (!netif_tx_queue_stopped(txq)) {
5555                         netif_tx_stop_queue(txq);
5556
5557                         /* This is a hard error, log it. */
5558                         netdev_err(dev,
5559                                    "BUG! Tx Ring full when queue awake!\n");
5560                 }
5561                 return NETDEV_TX_BUSY;
5562         }
5563
5564         entry = tnapi->tx_prod;
5565         base_flags = 0;
5566         mss = skb_shinfo(skb)->gso_size;
5567         if (mss) {
5568                 int tcp_opt_len, ip_tcp_len;
5569                 u32 hdrlen;
5570
5571                 if (skb_header_cloned(skb) &&
5572                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5573                         dev_kfree_skb(skb);
5574                         goto out_unlock;
5575                 }
5576
5577                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5578                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5579                 else {
5580                         struct iphdr *iph = ip_hdr(skb);
5581
5582                         tcp_opt_len = tcp_optlen(skb);
5583                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5584
5585                         iph->check = 0;
5586                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5587                         hdrlen = ip_tcp_len + tcp_opt_len;
5588                 }
5589
5590                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5591                         mss |= (hdrlen & 0xc) << 12;
5592                         if (hdrlen & 0x10)
5593                                 base_flags |= 0x00000010;
5594                         base_flags |= (hdrlen & 0x3e0) << 5;
5595                 } else
5596                         mss |= hdrlen << 9;
5597
5598                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5599                                TXD_FLAG_CPU_POST_DMA);
5600
5601                 tcp_hdr(skb)->check = 0;
5602
5603         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5604                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5605         }
5606
5607 #if TG3_VLAN_TAG_USED
5608         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5609                 base_flags |= (TXD_FLAG_VLAN |
5610                                (vlan_tx_tag_get(skb) << 16));
5611 #endif
5612
5613         len = skb_headlen(skb);
5614
5615         /* Queue skb data, a.k.a. the main skb fragment. */
5616         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5617         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5618                 dev_kfree_skb(skb);
5619                 goto out_unlock;
5620         }
5621
5622         tnapi->tx_buffers[entry].skb = skb;
5623         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5624
5625         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5626             !mss && skb->len > ETH_DATA_LEN)
5627                 base_flags |= TXD_FLAG_JMB_PKT;
5628
5629         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5630                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5631
5632         entry = NEXT_TX(entry);
5633
5634         /* Now loop through additional data fragments, and queue them. */
5635         if (skb_shinfo(skb)->nr_frags > 0) {
5636                 last = skb_shinfo(skb)->nr_frags - 1;
5637                 for (i = 0; i <= last; i++) {
5638                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5639
5640                         len = frag->size;
5641                         mapping = pci_map_page(tp->pdev,
5642                                                frag->page,
5643                                                frag->page_offset,
5644                                                len, PCI_DMA_TODEVICE);
5645                         if (pci_dma_mapping_error(tp->pdev, mapping))
5646                                 goto dma_error;
5647
5648                         tnapi->tx_buffers[entry].skb = NULL;
5649                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5650                                            mapping);
5651
5652                         tg3_set_txd(tnapi, entry, mapping, len,
5653                                     base_flags, (i == last) | (mss << 1));
5654
5655                         entry = NEXT_TX(entry);
5656                 }
5657         }
5658
5659         /* Packets are ready, update Tx producer idx local and on card. */
5660         tw32_tx_mbox(tnapi->prodmbox, entry);
5661
5662         tnapi->tx_prod = entry;
5663         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5664                 netif_tx_stop_queue(txq);
5665
5666                 /* netif_tx_stop_queue() must be done before checking
5667                  * checking tx index in tg3_tx_avail() below, because in
5668                  * tg3_tx(), we update tx index before checking for
5669                  * netif_tx_queue_stopped().
5670                  */
5671                 smp_mb();
5672                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5673                         netif_tx_wake_queue(txq);
5674         }
5675
5676 out_unlock:
5677         mmiowb();
5678
5679         return NETDEV_TX_OK;
5680
5681 dma_error:
5682         last = i;
5683         entry = tnapi->tx_prod;
5684         tnapi->tx_buffers[entry].skb = NULL;
5685         pci_unmap_single(tp->pdev,
5686                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5687                          skb_headlen(skb),
5688                          PCI_DMA_TODEVICE);
5689         for (i = 0; i <= last; i++) {
5690                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5691                 entry = NEXT_TX(entry);
5692
5693                 pci_unmap_page(tp->pdev,
5694                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5695                                               mapping),
5696                                frag->size, PCI_DMA_TODEVICE);
5697         }
5698
5699         dev_kfree_skb(skb);
5700         return NETDEV_TX_OK;
5701 }
5702
5703 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5704                                           struct net_device *);
5705
5706 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5707  * TSO header is greater than 80 bytes.
5708  */
5709 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5710 {
5711         struct sk_buff *segs, *nskb;
5712         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5713
5714         /* Estimate the number of fragments in the worst case */
5715         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5716                 netif_stop_queue(tp->dev);
5717
5718                 /* netif_tx_stop_queue() must be done before checking
5719                  * checking tx index in tg3_tx_avail() below, because in
5720                  * tg3_tx(), we update tx index before checking for
5721                  * netif_tx_queue_stopped().
5722                  */
5723                 smp_mb();
5724                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5725                         return NETDEV_TX_BUSY;
5726
5727                 netif_wake_queue(tp->dev);
5728         }
5729
5730         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5731         if (IS_ERR(segs))
5732                 goto tg3_tso_bug_end;
5733
5734         do {
5735                 nskb = segs;
5736                 segs = segs->next;
5737                 nskb->next = NULL;
5738                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5739         } while (segs);
5740
5741 tg3_tso_bug_end:
5742         dev_kfree_skb(skb);
5743
5744         return NETDEV_TX_OK;
5745 }
5746
5747 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5748  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5749  */
5750 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5751                                           struct net_device *dev)
5752 {
5753         struct tg3 *tp = netdev_priv(dev);
5754         u32 len, entry, base_flags, mss;
5755         int would_hit_hwbug;
5756         dma_addr_t mapping;
5757         struct tg3_napi *tnapi;
5758