afcc593108cef1465b4c61228f8a853632be8662
[linux-2.6.git] / drivers / net / tg3.c
1 /*
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  * Copyright (C) 2005-2010 Broadcom Corporation.
8  *
9  * Firmware is:
10  *      Derived from proprietary unpublished source code,
11  *      Copyright (C) 2000-2003 Broadcom Corporation.
12  *
13  *      Permission is hereby granted for the distribution of this firmware
14  *      data in hexadecimal or equivalent format, provided this copyright
15  *      notice is accompanying it.
16  */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/in.h>
28 #include <linux/init.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mii.h>
36 #include <linux/phy.h>
37 #include <linux/brcmphy.h>
38 #include <linux/if_vlan.h>
39 #include <linux/ip.h>
40 #include <linux/tcp.h>
41 #include <linux/workqueue.h>
42 #include <linux/prefetch.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/firmware.h>
45
46 #include <net/checksum.h>
47 #include <net/ip.h>
48
49 #include <asm/system.h>
50 #include <asm/io.h>
51 #include <asm/byteorder.h>
52 #include <asm/uaccess.h>
53
54 #ifdef CONFIG_SPARC
55 #include <asm/idprom.h>
56 #include <asm/prom.h>
57 #endif
58
59 #define BAR_0   0
60 #define BAR_2   2
61
62 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
63 #define TG3_VLAN_TAG_USED 1
64 #else
65 #define TG3_VLAN_TAG_USED 0
66 #endif
67
68 #include "tg3.h"
69
70 #define DRV_MODULE_NAME         "tg3"
71 #define TG3_MAJ_NUM                     3
72 #define TG3_MIN_NUM                     114
73 #define DRV_MODULE_VERSION      \
74         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
75 #define DRV_MODULE_RELDATE      "September 30, 2010"
76
77 #define TG3_DEF_MAC_MODE        0
78 #define TG3_DEF_RX_MODE         0
79 #define TG3_DEF_TX_MODE         0
80 #define TG3_DEF_MSG_ENABLE        \
81         (NETIF_MSG_DRV          | \
82          NETIF_MSG_PROBE        | \
83          NETIF_MSG_LINK         | \
84          NETIF_MSG_TIMER        | \
85          NETIF_MSG_IFDOWN       | \
86          NETIF_MSG_IFUP         | \
87          NETIF_MSG_RX_ERR       | \
88          NETIF_MSG_TX_ERR)
89
90 /* length of time before we decide the hardware is borked,
91  * and dev->tx_timeout() should be called to fix the problem
92  */
93 #define TG3_TX_TIMEOUT                  (5 * HZ)
94
95 /* hardware minimum and maximum for a single frame's data payload */
96 #define TG3_MIN_MTU                     60
97 #define TG3_MAX_MTU(tp) \
98         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
99
100 /* These numbers seem to be hard coded in the NIC firmware somehow.
101  * You can't change the ring sizes, but you can change where you place
102  * them in the NIC onboard memory.
103  */
104 #define TG3_RX_STD_RING_SIZE(tp) \
105         ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
106           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
107          RX_STD_MAX_SIZE_5717 : 512)
108 #define TG3_DEF_RX_RING_PENDING         200
109 #define TG3_RX_JMB_RING_SIZE(tp) \
110         ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
111           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
112          1024 : 256)
113 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
114 #define TG3_RSS_INDIR_TBL_SIZE          128
115
116 /* Do not place this n-ring entries value into the tp struct itself,
117  * we really want to expose these constants to GCC so that modulo et
118  * al.  operations are done with shifts and masks instead of with
119  * hw multiply/modulo instructions.  Another solution would be to
120  * replace things like '% foo' with '& (foo - 1)'.
121  */
122
123 #define TG3_TX_RING_SIZE                512
124 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
125
126 #define TG3_RX_STD_RING_BYTES(tp) \
127         (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
128 #define TG3_RX_JMB_RING_BYTES(tp) \
129         (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
130 #define TG3_RX_RCB_RING_BYTES(tp) \
131         (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
132 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
133                                  TG3_TX_RING_SIZE)
134 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
135
136 #define TG3_RX_DMA_ALIGN                16
137 #define TG3_RX_HEADROOM                 ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
138
139 #define TG3_DMA_BYTE_ENAB               64
140
141 #define TG3_RX_STD_DMA_SZ               1536
142 #define TG3_RX_JMB_DMA_SZ               9046
143
144 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
145
146 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
147 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
148
149 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
150         (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
151
152 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
153         (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
154
155 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
156  * that are at least dword aligned when used in PCIX mode.  The driver
157  * works around this bug by double copying the packet.  This workaround
158  * is built into the normal double copy length check for efficiency.
159  *
160  * However, the double copy is only necessary on those architectures
161  * where unaligned memory accesses are inefficient.  For those architectures
162  * where unaligned memory accesses incur little penalty, we can reintegrate
163  * the 5701 in the normal rx path.  Doing so saves a device structure
164  * dereference by hardcoding the double copy threshold in place.
165  */
166 #define TG3_RX_COPY_THRESHOLD           256
167 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
168         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
169 #else
170         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
171 #endif
172
173 /* minimum number of free TX descriptors required to wake up TX process */
174 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
175
176 #define TG3_RAW_IP_ALIGN 2
177
178 /* number of ETHTOOL_GSTATS u64's */
179 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
180
181 #define TG3_NUM_TEST            6
182
183 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
184
185 #define FIRMWARE_TG3            "tigon/tg3.bin"
186 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
187 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
188
189 static char version[] __devinitdata =
190         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
191
192 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
193 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
194 MODULE_LICENSE("GPL");
195 MODULE_VERSION(DRV_MODULE_VERSION);
196 MODULE_FIRMWARE(FIRMWARE_TG3);
197 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
198 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
199
200 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
201 module_param(tg3_debug, int, 0);
202 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
203
204 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
268         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
269         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
270         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
271         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
272         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
273         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
274         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
275         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
276         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
277         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
278         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
279         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
280         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
281         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
282         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
283         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
284         {}
285 };
286
287 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
288
289 static const struct {
290         const char string[ETH_GSTRING_LEN];
291 } ethtool_stats_keys[TG3_NUM_STATS] = {
292         { "rx_octets" },
293         { "rx_fragments" },
294         { "rx_ucast_packets" },
295         { "rx_mcast_packets" },
296         { "rx_bcast_packets" },
297         { "rx_fcs_errors" },
298         { "rx_align_errors" },
299         { "rx_xon_pause_rcvd" },
300         { "rx_xoff_pause_rcvd" },
301         { "rx_mac_ctrl_rcvd" },
302         { "rx_xoff_entered" },
303         { "rx_frame_too_long_errors" },
304         { "rx_jabbers" },
305         { "rx_undersize_packets" },
306         { "rx_in_length_errors" },
307         { "rx_out_length_errors" },
308         { "rx_64_or_less_octet_packets" },
309         { "rx_65_to_127_octet_packets" },
310         { "rx_128_to_255_octet_packets" },
311         { "rx_256_to_511_octet_packets" },
312         { "rx_512_to_1023_octet_packets" },
313         { "rx_1024_to_1522_octet_packets" },
314         { "rx_1523_to_2047_octet_packets" },
315         { "rx_2048_to_4095_octet_packets" },
316         { "rx_4096_to_8191_octet_packets" },
317         { "rx_8192_to_9022_octet_packets" },
318
319         { "tx_octets" },
320         { "tx_collisions" },
321
322         { "tx_xon_sent" },
323         { "tx_xoff_sent" },
324         { "tx_flow_control" },
325         { "tx_mac_errors" },
326         { "tx_single_collisions" },
327         { "tx_mult_collisions" },
328         { "tx_deferred" },
329         { "tx_excessive_collisions" },
330         { "tx_late_collisions" },
331         { "tx_collide_2times" },
332         { "tx_collide_3times" },
333         { "tx_collide_4times" },
334         { "tx_collide_5times" },
335         { "tx_collide_6times" },
336         { "tx_collide_7times" },
337         { "tx_collide_8times" },
338         { "tx_collide_9times" },
339         { "tx_collide_10times" },
340         { "tx_collide_11times" },
341         { "tx_collide_12times" },
342         { "tx_collide_13times" },
343         { "tx_collide_14times" },
344         { "tx_collide_15times" },
345         { "tx_ucast_packets" },
346         { "tx_mcast_packets" },
347         { "tx_bcast_packets" },
348         { "tx_carrier_sense_errors" },
349         { "tx_discards" },
350         { "tx_errors" },
351
352         { "dma_writeq_full" },
353         { "dma_write_prioq_full" },
354         { "rxbds_empty" },
355         { "rx_discards" },
356         { "rx_errors" },
357         { "rx_threshold_hit" },
358
359         { "dma_readq_full" },
360         { "dma_read_prioq_full" },
361         { "tx_comp_queue_full" },
362
363         { "ring_set_send_prod_index" },
364         { "ring_status_update" },
365         { "nic_irqs" },
366         { "nic_avoided_irqs" },
367         { "nic_tx_threshold_hit" }
368 };
369
370 static const struct {
371         const char string[ETH_GSTRING_LEN];
372 } ethtool_test_keys[TG3_NUM_TEST] = {
373         { "nvram test     (online) " },
374         { "link test      (online) " },
375         { "register test  (offline)" },
376         { "memory test    (offline)" },
377         { "loopback test  (offline)" },
378         { "interrupt test (offline)" },
379 };
380
381 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
382 {
383         writel(val, tp->regs + off);
384 }
385
386 static u32 tg3_read32(struct tg3 *tp, u32 off)
387 {
388         return readl(tp->regs + off);
389 }
390
391 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
392 {
393         writel(val, tp->aperegs + off);
394 }
395
396 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
397 {
398         return readl(tp->aperegs + off);
399 }
400
401 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
402 {
403         unsigned long flags;
404
405         spin_lock_irqsave(&tp->indirect_lock, flags);
406         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
407         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
408         spin_unlock_irqrestore(&tp->indirect_lock, flags);
409 }
410
411 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
412 {
413         writel(val, tp->regs + off);
414         readl(tp->regs + off);
415 }
416
417 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
418 {
419         unsigned long flags;
420         u32 val;
421
422         spin_lock_irqsave(&tp->indirect_lock, flags);
423         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
424         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
425         spin_unlock_irqrestore(&tp->indirect_lock, flags);
426         return val;
427 }
428
429 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
430 {
431         unsigned long flags;
432
433         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
434                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
435                                        TG3_64BIT_REG_LOW, val);
436                 return;
437         }
438         if (off == TG3_RX_STD_PROD_IDX_REG) {
439                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
440                                        TG3_64BIT_REG_LOW, val);
441                 return;
442         }
443
444         spin_lock_irqsave(&tp->indirect_lock, flags);
445         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
446         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
447         spin_unlock_irqrestore(&tp->indirect_lock, flags);
448
449         /* In indirect mode when disabling interrupts, we also need
450          * to clear the interrupt bit in the GRC local ctrl register.
451          */
452         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
453             (val == 0x1)) {
454                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
455                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
456         }
457 }
458
459 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
460 {
461         unsigned long flags;
462         u32 val;
463
464         spin_lock_irqsave(&tp->indirect_lock, flags);
465         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
466         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
467         spin_unlock_irqrestore(&tp->indirect_lock, flags);
468         return val;
469 }
470
471 /* usec_wait specifies the wait time in usec when writing to certain registers
472  * where it is unsafe to read back the register without some delay.
473  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
474  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
475  */
476 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
477 {
478         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
479             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
480                 /* Non-posted methods */
481                 tp->write32(tp, off, val);
482         else {
483                 /* Posted method */
484                 tg3_write32(tp, off, val);
485                 if (usec_wait)
486                         udelay(usec_wait);
487                 tp->read32(tp, off);
488         }
489         /* Wait again after the read for the posted method to guarantee that
490          * the wait time is met.
491          */
492         if (usec_wait)
493                 udelay(usec_wait);
494 }
495
496 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
497 {
498         tp->write32_mbox(tp, off, val);
499         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
500             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
501                 tp->read32_mbox(tp, off);
502 }
503
504 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
505 {
506         void __iomem *mbox = tp->regs + off;
507         writel(val, mbox);
508         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
509                 writel(val, mbox);
510         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
511                 readl(mbox);
512 }
513
514 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
515 {
516         return readl(tp->regs + off + GRCMBOX_BASE);
517 }
518
519 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
520 {
521         writel(val, tp->regs + off + GRCMBOX_BASE);
522 }
523
524 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
525 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
526 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
527 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
528 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
529
530 #define tw32(reg, val)                  tp->write32(tp, reg, val)
531 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
532 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
533 #define tr32(reg)                       tp->read32(tp, reg)
534
535 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
536 {
537         unsigned long flags;
538
539         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
540             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
541                 return;
542
543         spin_lock_irqsave(&tp->indirect_lock, flags);
544         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
545                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
546                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
547
548                 /* Always leave this as zero. */
549                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
550         } else {
551                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
552                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
553
554                 /* Always leave this as zero. */
555                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
556         }
557         spin_unlock_irqrestore(&tp->indirect_lock, flags);
558 }
559
560 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
561 {
562         unsigned long flags;
563
564         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
565             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
566                 *val = 0;
567                 return;
568         }
569
570         spin_lock_irqsave(&tp->indirect_lock, flags);
571         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
572                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
573                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
574
575                 /* Always leave this as zero. */
576                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
577         } else {
578                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
579                 *val = tr32(TG3PCI_MEM_WIN_DATA);
580
581                 /* Always leave this as zero. */
582                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
583         }
584         spin_unlock_irqrestore(&tp->indirect_lock, flags);
585 }
586
587 static void tg3_ape_lock_init(struct tg3 *tp)
588 {
589         int i;
590         u32 regbase;
591
592         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
593                 regbase = TG3_APE_LOCK_GRANT;
594         else
595                 regbase = TG3_APE_PER_LOCK_GRANT;
596
597         /* Make sure the driver hasn't any stale locks. */
598         for (i = 0; i < 8; i++)
599                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
600 }
601
602 static int tg3_ape_lock(struct tg3 *tp, int locknum)
603 {
604         int i, off;
605         int ret = 0;
606         u32 status, req, gnt;
607
608         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
609                 return 0;
610
611         switch (locknum) {
612         case TG3_APE_LOCK_GRC:
613         case TG3_APE_LOCK_MEM:
614                 break;
615         default:
616                 return -EINVAL;
617         }
618
619         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
620                 req = TG3_APE_LOCK_REQ;
621                 gnt = TG3_APE_LOCK_GRANT;
622         } else {
623                 req = TG3_APE_PER_LOCK_REQ;
624                 gnt = TG3_APE_PER_LOCK_GRANT;
625         }
626
627         off = 4 * locknum;
628
629         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
630
631         /* Wait for up to 1 millisecond to acquire lock. */
632         for (i = 0; i < 100; i++) {
633                 status = tg3_ape_read32(tp, gnt + off);
634                 if (status == APE_LOCK_GRANT_DRIVER)
635                         break;
636                 udelay(10);
637         }
638
639         if (status != APE_LOCK_GRANT_DRIVER) {
640                 /* Revoke the lock request. */
641                 tg3_ape_write32(tp, gnt + off,
642                                 APE_LOCK_GRANT_DRIVER);
643
644                 ret = -EBUSY;
645         }
646
647         return ret;
648 }
649
650 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
651 {
652         u32 gnt;
653
654         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
655                 return;
656
657         switch (locknum) {
658         case TG3_APE_LOCK_GRC:
659         case TG3_APE_LOCK_MEM:
660                 break;
661         default:
662                 return;
663         }
664
665         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
666                 gnt = TG3_APE_LOCK_GRANT;
667         else
668                 gnt = TG3_APE_PER_LOCK_GRANT;
669
670         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
671 }
672
673 static void tg3_disable_ints(struct tg3 *tp)
674 {
675         int i;
676
677         tw32(TG3PCI_MISC_HOST_CTRL,
678              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
679         for (i = 0; i < tp->irq_max; i++)
680                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
681 }
682
683 static void tg3_enable_ints(struct tg3 *tp)
684 {
685         int i;
686
687         tp->irq_sync = 0;
688         wmb();
689
690         tw32(TG3PCI_MISC_HOST_CTRL,
691              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
692
693         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
694         for (i = 0; i < tp->irq_cnt; i++) {
695                 struct tg3_napi *tnapi = &tp->napi[i];
696
697                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
698                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
699                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
700
701                 tp->coal_now |= tnapi->coal_now;
702         }
703
704         /* Force an initial interrupt */
705         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
706             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
707                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
708         else
709                 tw32(HOSTCC_MODE, tp->coal_now);
710
711         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
712 }
713
714 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
715 {
716         struct tg3 *tp = tnapi->tp;
717         struct tg3_hw_status *sblk = tnapi->hw_status;
718         unsigned int work_exists = 0;
719
720         /* check for phy events */
721         if (!(tp->tg3_flags &
722               (TG3_FLAG_USE_LINKCHG_REG |
723                TG3_FLAG_POLL_SERDES))) {
724                 if (sblk->status & SD_STATUS_LINK_CHG)
725                         work_exists = 1;
726         }
727         /* check for RX/TX work to do */
728         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
729             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
730                 work_exists = 1;
731
732         return work_exists;
733 }
734
735 /* tg3_int_reenable
736  *  similar to tg3_enable_ints, but it accurately determines whether there
737  *  is new work pending and can return without flushing the PIO write
738  *  which reenables interrupts
739  */
740 static void tg3_int_reenable(struct tg3_napi *tnapi)
741 {
742         struct tg3 *tp = tnapi->tp;
743
744         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
745         mmiowb();
746
747         /* When doing tagged status, this work check is unnecessary.
748          * The last_tag we write above tells the chip which piece of
749          * work we've completed.
750          */
751         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
752             tg3_has_work(tnapi))
753                 tw32(HOSTCC_MODE, tp->coalesce_mode |
754                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
755 }
756
757 static void tg3_switch_clocks(struct tg3 *tp)
758 {
759         u32 clock_ctrl;
760         u32 orig_clock_ctrl;
761
762         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
763             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
764                 return;
765
766         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
767
768         orig_clock_ctrl = clock_ctrl;
769         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
770                        CLOCK_CTRL_CLKRUN_OENABLE |
771                        0x1f);
772         tp->pci_clock_ctrl = clock_ctrl;
773
774         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
775                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
776                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
777                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
778                 }
779         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
780                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
781                             clock_ctrl |
782                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
783                             40);
784                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
785                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
786                             40);
787         }
788         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
789 }
790
791 #define PHY_BUSY_LOOPS  5000
792
793 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
794 {
795         u32 frame_val;
796         unsigned int loops;
797         int ret;
798
799         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
800                 tw32_f(MAC_MI_MODE,
801                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
802                 udelay(80);
803         }
804
805         *val = 0x0;
806
807         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
808                       MI_COM_PHY_ADDR_MASK);
809         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
810                       MI_COM_REG_ADDR_MASK);
811         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
812
813         tw32_f(MAC_MI_COM, frame_val);
814
815         loops = PHY_BUSY_LOOPS;
816         while (loops != 0) {
817                 udelay(10);
818                 frame_val = tr32(MAC_MI_COM);
819
820                 if ((frame_val & MI_COM_BUSY) == 0) {
821                         udelay(5);
822                         frame_val = tr32(MAC_MI_COM);
823                         break;
824                 }
825                 loops -= 1;
826         }
827
828         ret = -EBUSY;
829         if (loops != 0) {
830                 *val = frame_val & MI_COM_DATA_MASK;
831                 ret = 0;
832         }
833
834         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
835                 tw32_f(MAC_MI_MODE, tp->mi_mode);
836                 udelay(80);
837         }
838
839         return ret;
840 }
841
842 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
843 {
844         u32 frame_val;
845         unsigned int loops;
846         int ret;
847
848         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
849             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
850                 return 0;
851
852         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
853                 tw32_f(MAC_MI_MODE,
854                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
855                 udelay(80);
856         }
857
858         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
859                       MI_COM_PHY_ADDR_MASK);
860         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
861                       MI_COM_REG_ADDR_MASK);
862         frame_val |= (val & MI_COM_DATA_MASK);
863         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
864
865         tw32_f(MAC_MI_COM, frame_val);
866
867         loops = PHY_BUSY_LOOPS;
868         while (loops != 0) {
869                 udelay(10);
870                 frame_val = tr32(MAC_MI_COM);
871                 if ((frame_val & MI_COM_BUSY) == 0) {
872                         udelay(5);
873                         frame_val = tr32(MAC_MI_COM);
874                         break;
875                 }
876                 loops -= 1;
877         }
878
879         ret = -EBUSY;
880         if (loops != 0)
881                 ret = 0;
882
883         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
884                 tw32_f(MAC_MI_MODE, tp->mi_mode);
885                 udelay(80);
886         }
887
888         return ret;
889 }
890
891 static int tg3_bmcr_reset(struct tg3 *tp)
892 {
893         u32 phy_control;
894         int limit, err;
895
896         /* OK, reset it, and poll the BMCR_RESET bit until it
897          * clears or we time out.
898          */
899         phy_control = BMCR_RESET;
900         err = tg3_writephy(tp, MII_BMCR, phy_control);
901         if (err != 0)
902                 return -EBUSY;
903
904         limit = 5000;
905         while (limit--) {
906                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
907                 if (err != 0)
908                         return -EBUSY;
909
910                 if ((phy_control & BMCR_RESET) == 0) {
911                         udelay(40);
912                         break;
913                 }
914                 udelay(10);
915         }
916         if (limit < 0)
917                 return -EBUSY;
918
919         return 0;
920 }
921
922 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
923 {
924         struct tg3 *tp = bp->priv;
925         u32 val;
926
927         spin_lock_bh(&tp->lock);
928
929         if (tg3_readphy(tp, reg, &val))
930                 val = -EIO;
931
932         spin_unlock_bh(&tp->lock);
933
934         return val;
935 }
936
937 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
938 {
939         struct tg3 *tp = bp->priv;
940         u32 ret = 0;
941
942         spin_lock_bh(&tp->lock);
943
944         if (tg3_writephy(tp, reg, val))
945                 ret = -EIO;
946
947         spin_unlock_bh(&tp->lock);
948
949         return ret;
950 }
951
952 static int tg3_mdio_reset(struct mii_bus *bp)
953 {
954         return 0;
955 }
956
957 static void tg3_mdio_config_5785(struct tg3 *tp)
958 {
959         u32 val;
960         struct phy_device *phydev;
961
962         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
963         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
964         case PHY_ID_BCM50610:
965         case PHY_ID_BCM50610M:
966                 val = MAC_PHYCFG2_50610_LED_MODES;
967                 break;
968         case PHY_ID_BCMAC131:
969                 val = MAC_PHYCFG2_AC131_LED_MODES;
970                 break;
971         case PHY_ID_RTL8211C:
972                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
973                 break;
974         case PHY_ID_RTL8201E:
975                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
976                 break;
977         default:
978                 return;
979         }
980
981         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
982                 tw32(MAC_PHYCFG2, val);
983
984                 val = tr32(MAC_PHYCFG1);
985                 val &= ~(MAC_PHYCFG1_RGMII_INT |
986                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
987                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
988                 tw32(MAC_PHYCFG1, val);
989
990                 return;
991         }
992
993         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
994                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
995                        MAC_PHYCFG2_FMODE_MASK_MASK |
996                        MAC_PHYCFG2_GMODE_MASK_MASK |
997                        MAC_PHYCFG2_ACT_MASK_MASK   |
998                        MAC_PHYCFG2_QUAL_MASK_MASK |
999                        MAC_PHYCFG2_INBAND_ENABLE;
1000
1001         tw32(MAC_PHYCFG2, val);
1002
1003         val = tr32(MAC_PHYCFG1);
1004         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1005                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1006         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1007                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1008                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1009                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1010                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1011         }
1012         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1013                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1014         tw32(MAC_PHYCFG1, val);
1015
1016         val = tr32(MAC_EXT_RGMII_MODE);
1017         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1018                  MAC_RGMII_MODE_RX_QUALITY |
1019                  MAC_RGMII_MODE_RX_ACTIVITY |
1020                  MAC_RGMII_MODE_RX_ENG_DET |
1021                  MAC_RGMII_MODE_TX_ENABLE |
1022                  MAC_RGMII_MODE_TX_LOWPWR |
1023                  MAC_RGMII_MODE_TX_RESET);
1024         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1025                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1026                         val |= MAC_RGMII_MODE_RX_INT_B |
1027                                MAC_RGMII_MODE_RX_QUALITY |
1028                                MAC_RGMII_MODE_RX_ACTIVITY |
1029                                MAC_RGMII_MODE_RX_ENG_DET;
1030                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1031                         val |= MAC_RGMII_MODE_TX_ENABLE |
1032                                MAC_RGMII_MODE_TX_LOWPWR |
1033                                MAC_RGMII_MODE_TX_RESET;
1034         }
1035         tw32(MAC_EXT_RGMII_MODE, val);
1036 }
1037
1038 static void tg3_mdio_start(struct tg3 *tp)
1039 {
1040         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1041         tw32_f(MAC_MI_MODE, tp->mi_mode);
1042         udelay(80);
1043
1044         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1045             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1046                 tg3_mdio_config_5785(tp);
1047 }
1048
1049 static int tg3_mdio_init(struct tg3 *tp)
1050 {
1051         int i;
1052         u32 reg;
1053         struct phy_device *phydev;
1054
1055         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1056             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
1057                 u32 is_serdes;
1058
1059                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1060
1061                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1062                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1063                 else
1064                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1065                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1066                 if (is_serdes)
1067                         tp->phy_addr += 7;
1068         } else
1069                 tp->phy_addr = TG3_PHY_MII_ADDR;
1070
1071         tg3_mdio_start(tp);
1072
1073         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1074             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1075                 return 0;
1076
1077         tp->mdio_bus = mdiobus_alloc();
1078         if (tp->mdio_bus == NULL)
1079                 return -ENOMEM;
1080
1081         tp->mdio_bus->name     = "tg3 mdio bus";
1082         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1083                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1084         tp->mdio_bus->priv     = tp;
1085         tp->mdio_bus->parent   = &tp->pdev->dev;
1086         tp->mdio_bus->read     = &tg3_mdio_read;
1087         tp->mdio_bus->write    = &tg3_mdio_write;
1088         tp->mdio_bus->reset    = &tg3_mdio_reset;
1089         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1090         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1091
1092         for (i = 0; i < PHY_MAX_ADDR; i++)
1093                 tp->mdio_bus->irq[i] = PHY_POLL;
1094
1095         /* The bus registration will look for all the PHYs on the mdio bus.
1096          * Unfortunately, it does not ensure the PHY is powered up before
1097          * accessing the PHY ID registers.  A chip reset is the
1098          * quickest way to bring the device back to an operational state..
1099          */
1100         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1101                 tg3_bmcr_reset(tp);
1102
1103         i = mdiobus_register(tp->mdio_bus);
1104         if (i) {
1105                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1106                 mdiobus_free(tp->mdio_bus);
1107                 return i;
1108         }
1109
1110         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1111
1112         if (!phydev || !phydev->drv) {
1113                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1114                 mdiobus_unregister(tp->mdio_bus);
1115                 mdiobus_free(tp->mdio_bus);
1116                 return -ENODEV;
1117         }
1118
1119         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1120         case PHY_ID_BCM57780:
1121                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1122                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1123                 break;
1124         case PHY_ID_BCM50610:
1125         case PHY_ID_BCM50610M:
1126                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1127                                      PHY_BRCM_RX_REFCLK_UNUSED |
1128                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1129                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1130                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1131                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1132                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1133                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1134                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1135                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1136                 /* fallthru */
1137         case PHY_ID_RTL8211C:
1138                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1139                 break;
1140         case PHY_ID_RTL8201E:
1141         case PHY_ID_BCMAC131:
1142                 phydev->interface = PHY_INTERFACE_MODE_MII;
1143                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1144                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1145                 break;
1146         }
1147
1148         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1149
1150         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1151                 tg3_mdio_config_5785(tp);
1152
1153         return 0;
1154 }
1155
1156 static void tg3_mdio_fini(struct tg3 *tp)
1157 {
1158         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1159                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1160                 mdiobus_unregister(tp->mdio_bus);
1161                 mdiobus_free(tp->mdio_bus);
1162         }
1163 }
1164
1165 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1166 {
1167         int err;
1168
1169         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1170         if (err)
1171                 goto done;
1172
1173         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1174         if (err)
1175                 goto done;
1176
1177         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1178                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1179         if (err)
1180                 goto done;
1181
1182         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1183
1184 done:
1185         return err;
1186 }
1187
1188 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1189 {
1190         int err;
1191
1192         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1193         if (err)
1194                 goto done;
1195
1196         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1197         if (err)
1198                 goto done;
1199
1200         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1201                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1202         if (err)
1203                 goto done;
1204
1205         err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1206
1207 done:
1208         return err;
1209 }
1210
1211 /* tp->lock is held. */
1212 static inline void tg3_generate_fw_event(struct tg3 *tp)
1213 {
1214         u32 val;
1215
1216         val = tr32(GRC_RX_CPU_EVENT);
1217         val |= GRC_RX_CPU_DRIVER_EVENT;
1218         tw32_f(GRC_RX_CPU_EVENT, val);
1219
1220         tp->last_event_jiffies = jiffies;
1221 }
1222
1223 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1224
1225 /* tp->lock is held. */
1226 static void tg3_wait_for_event_ack(struct tg3 *tp)
1227 {
1228         int i;
1229         unsigned int delay_cnt;
1230         long time_remain;
1231
1232         /* If enough time has passed, no wait is necessary. */
1233         time_remain = (long)(tp->last_event_jiffies + 1 +
1234                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1235                       (long)jiffies;
1236         if (time_remain < 0)
1237                 return;
1238
1239         /* Check if we can shorten the wait time. */
1240         delay_cnt = jiffies_to_usecs(time_remain);
1241         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1242                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1243         delay_cnt = (delay_cnt >> 3) + 1;
1244
1245         for (i = 0; i < delay_cnt; i++) {
1246                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1247                         break;
1248                 udelay(8);
1249         }
1250 }
1251
1252 /* tp->lock is held. */
1253 static void tg3_ump_link_report(struct tg3 *tp)
1254 {
1255         u32 reg;
1256         u32 val;
1257
1258         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1259             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1260                 return;
1261
1262         tg3_wait_for_event_ack(tp);
1263
1264         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1265
1266         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1267
1268         val = 0;
1269         if (!tg3_readphy(tp, MII_BMCR, &reg))
1270                 val = reg << 16;
1271         if (!tg3_readphy(tp, MII_BMSR, &reg))
1272                 val |= (reg & 0xffff);
1273         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1274
1275         val = 0;
1276         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1277                 val = reg << 16;
1278         if (!tg3_readphy(tp, MII_LPA, &reg))
1279                 val |= (reg & 0xffff);
1280         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1281
1282         val = 0;
1283         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1284                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1285                         val = reg << 16;
1286                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1287                         val |= (reg & 0xffff);
1288         }
1289         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1290
1291         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1292                 val = reg << 16;
1293         else
1294                 val = 0;
1295         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1296
1297         tg3_generate_fw_event(tp);
1298 }
1299
1300 static void tg3_link_report(struct tg3 *tp)
1301 {
1302         if (!netif_carrier_ok(tp->dev)) {
1303                 netif_info(tp, link, tp->dev, "Link is down\n");
1304                 tg3_ump_link_report(tp);
1305         } else if (netif_msg_link(tp)) {
1306                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1307                             (tp->link_config.active_speed == SPEED_1000 ?
1308                              1000 :
1309                              (tp->link_config.active_speed == SPEED_100 ?
1310                               100 : 10)),
1311                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1312                              "full" : "half"));
1313
1314                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1315                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1316                             "on" : "off",
1317                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1318                             "on" : "off");
1319                 tg3_ump_link_report(tp);
1320         }
1321 }
1322
1323 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1324 {
1325         u16 miireg;
1326
1327         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1328                 miireg = ADVERTISE_PAUSE_CAP;
1329         else if (flow_ctrl & FLOW_CTRL_TX)
1330                 miireg = ADVERTISE_PAUSE_ASYM;
1331         else if (flow_ctrl & FLOW_CTRL_RX)
1332                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1333         else
1334                 miireg = 0;
1335
1336         return miireg;
1337 }
1338
1339 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1340 {
1341         u16 miireg;
1342
1343         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1344                 miireg = ADVERTISE_1000XPAUSE;
1345         else if (flow_ctrl & FLOW_CTRL_TX)
1346                 miireg = ADVERTISE_1000XPSE_ASYM;
1347         else if (flow_ctrl & FLOW_CTRL_RX)
1348                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1349         else
1350                 miireg = 0;
1351
1352         return miireg;
1353 }
1354
1355 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1356 {
1357         u8 cap = 0;
1358
1359         if (lcladv & ADVERTISE_1000XPAUSE) {
1360                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1361                         if (rmtadv & LPA_1000XPAUSE)
1362                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1363                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1364                                 cap = FLOW_CTRL_RX;
1365                 } else {
1366                         if (rmtadv & LPA_1000XPAUSE)
1367                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1368                 }
1369         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1370                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1371                         cap = FLOW_CTRL_TX;
1372         }
1373
1374         return cap;
1375 }
1376
1377 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1378 {
1379         u8 autoneg;
1380         u8 flowctrl = 0;
1381         u32 old_rx_mode = tp->rx_mode;
1382         u32 old_tx_mode = tp->tx_mode;
1383
1384         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1385                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1386         else
1387                 autoneg = tp->link_config.autoneg;
1388
1389         if (autoneg == AUTONEG_ENABLE &&
1390             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1391                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1392                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1393                 else
1394                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1395         } else
1396                 flowctrl = tp->link_config.flowctrl;
1397
1398         tp->link_config.active_flowctrl = flowctrl;
1399
1400         if (flowctrl & FLOW_CTRL_RX)
1401                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1402         else
1403                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1404
1405         if (old_rx_mode != tp->rx_mode)
1406                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1407
1408         if (flowctrl & FLOW_CTRL_TX)
1409                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1410         else
1411                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1412
1413         if (old_tx_mode != tp->tx_mode)
1414                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1415 }
1416
1417 static void tg3_adjust_link(struct net_device *dev)
1418 {
1419         u8 oldflowctrl, linkmesg = 0;
1420         u32 mac_mode, lcl_adv, rmt_adv;
1421         struct tg3 *tp = netdev_priv(dev);
1422         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1423
1424         spin_lock_bh(&tp->lock);
1425
1426         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1427                                     MAC_MODE_HALF_DUPLEX);
1428
1429         oldflowctrl = tp->link_config.active_flowctrl;
1430
1431         if (phydev->link) {
1432                 lcl_adv = 0;
1433                 rmt_adv = 0;
1434
1435                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1436                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1437                 else if (phydev->speed == SPEED_1000 ||
1438                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1439                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1440                 else
1441                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1442
1443                 if (phydev->duplex == DUPLEX_HALF)
1444                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1445                 else {
1446                         lcl_adv = tg3_advert_flowctrl_1000T(
1447                                   tp->link_config.flowctrl);
1448
1449                         if (phydev->pause)
1450                                 rmt_adv = LPA_PAUSE_CAP;
1451                         if (phydev->asym_pause)
1452                                 rmt_adv |= LPA_PAUSE_ASYM;
1453                 }
1454
1455                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1456         } else
1457                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1458
1459         if (mac_mode != tp->mac_mode) {
1460                 tp->mac_mode = mac_mode;
1461                 tw32_f(MAC_MODE, tp->mac_mode);
1462                 udelay(40);
1463         }
1464
1465         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1466                 if (phydev->speed == SPEED_10)
1467                         tw32(MAC_MI_STAT,
1468                              MAC_MI_STAT_10MBPS_MODE |
1469                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1470                 else
1471                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1472         }
1473
1474         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1475                 tw32(MAC_TX_LENGTHS,
1476                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1477                       (6 << TX_LENGTHS_IPG_SHIFT) |
1478                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1479         else
1480                 tw32(MAC_TX_LENGTHS,
1481                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1482                       (6 << TX_LENGTHS_IPG_SHIFT) |
1483                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1484
1485         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1486             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1487             phydev->speed != tp->link_config.active_speed ||
1488             phydev->duplex != tp->link_config.active_duplex ||
1489             oldflowctrl != tp->link_config.active_flowctrl)
1490                 linkmesg = 1;
1491
1492         tp->link_config.active_speed = phydev->speed;
1493         tp->link_config.active_duplex = phydev->duplex;
1494
1495         spin_unlock_bh(&tp->lock);
1496
1497         if (linkmesg)
1498                 tg3_link_report(tp);
1499 }
1500
1501 static int tg3_phy_init(struct tg3 *tp)
1502 {
1503         struct phy_device *phydev;
1504
1505         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1506                 return 0;
1507
1508         /* Bring the PHY back to a known state. */
1509         tg3_bmcr_reset(tp);
1510
1511         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1512
1513         /* Attach the MAC to the PHY. */
1514         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1515                              phydev->dev_flags, phydev->interface);
1516         if (IS_ERR(phydev)) {
1517                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1518                 return PTR_ERR(phydev);
1519         }
1520
1521         /* Mask with MAC supported features. */
1522         switch (phydev->interface) {
1523         case PHY_INTERFACE_MODE_GMII:
1524         case PHY_INTERFACE_MODE_RGMII:
1525                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1526                         phydev->supported &= (PHY_GBIT_FEATURES |
1527                                               SUPPORTED_Pause |
1528                                               SUPPORTED_Asym_Pause);
1529                         break;
1530                 }
1531                 /* fallthru */
1532         case PHY_INTERFACE_MODE_MII:
1533                 phydev->supported &= (PHY_BASIC_FEATURES |
1534                                       SUPPORTED_Pause |
1535                                       SUPPORTED_Asym_Pause);
1536                 break;
1537         default:
1538                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1539                 return -EINVAL;
1540         }
1541
1542         tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1543
1544         phydev->advertising = phydev->supported;
1545
1546         return 0;
1547 }
1548
1549 static void tg3_phy_start(struct tg3 *tp)
1550 {
1551         struct phy_device *phydev;
1552
1553         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1554                 return;
1555
1556         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1557
1558         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1559                 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1560                 phydev->speed = tp->link_config.orig_speed;
1561                 phydev->duplex = tp->link_config.orig_duplex;
1562                 phydev->autoneg = tp->link_config.orig_autoneg;
1563                 phydev->advertising = tp->link_config.orig_advertising;
1564         }
1565
1566         phy_start(phydev);
1567
1568         phy_start_aneg(phydev);
1569 }
1570
1571 static void tg3_phy_stop(struct tg3 *tp)
1572 {
1573         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1574                 return;
1575
1576         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1577 }
1578
1579 static void tg3_phy_fini(struct tg3 *tp)
1580 {
1581         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1582                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1583                 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1584         }
1585 }
1586
1587 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1588 {
1589         int err;
1590
1591         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1592         if (!err)
1593                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1594
1595         return err;
1596 }
1597
1598 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1599 {
1600         u32 phytest;
1601
1602         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1603                 u32 phy;
1604
1605                 tg3_writephy(tp, MII_TG3_FET_TEST,
1606                              phytest | MII_TG3_FET_SHADOW_EN);
1607                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1608                         if (enable)
1609                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1610                         else
1611                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1612                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1613                 }
1614                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1615         }
1616 }
1617
1618 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1619 {
1620         u32 reg;
1621
1622         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1623             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1624               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1625              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1626                 return;
1627
1628         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1629                 tg3_phy_fet_toggle_apd(tp, enable);
1630                 return;
1631         }
1632
1633         reg = MII_TG3_MISC_SHDW_WREN |
1634               MII_TG3_MISC_SHDW_SCR5_SEL |
1635               MII_TG3_MISC_SHDW_SCR5_LPED |
1636               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1637               MII_TG3_MISC_SHDW_SCR5_SDTL |
1638               MII_TG3_MISC_SHDW_SCR5_C125OE;
1639         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1640                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1641
1642         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1643
1644
1645         reg = MII_TG3_MISC_SHDW_WREN |
1646               MII_TG3_MISC_SHDW_APD_SEL |
1647               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1648         if (enable)
1649                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1650
1651         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1652 }
1653
1654 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1655 {
1656         u32 phy;
1657
1658         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1659             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1660                 return;
1661
1662         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1663                 u32 ephy;
1664
1665                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1666                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1667
1668                         tg3_writephy(tp, MII_TG3_FET_TEST,
1669                                      ephy | MII_TG3_FET_SHADOW_EN);
1670                         if (!tg3_readphy(tp, reg, &phy)) {
1671                                 if (enable)
1672                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1673                                 else
1674                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1675                                 tg3_writephy(tp, reg, phy);
1676                         }
1677                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1678                 }
1679         } else {
1680                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1681                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1682                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1683                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1684                         if (enable)
1685                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1686                         else
1687                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1688                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1689                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1690                 }
1691         }
1692 }
1693
1694 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1695 {
1696         u32 val;
1697
1698         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1699                 return;
1700
1701         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1702             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1703                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1704                              (val | (1 << 15) | (1 << 4)));
1705 }
1706
1707 static void tg3_phy_apply_otp(struct tg3 *tp)
1708 {
1709         u32 otp, phy;
1710
1711         if (!tp->phy_otp)
1712                 return;
1713
1714         otp = tp->phy_otp;
1715
1716         /* Enable SM_DSP clock and tx 6dB coding. */
1717         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1718               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1719               MII_TG3_AUXCTL_ACTL_TX_6DB;
1720         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1721
1722         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1723         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1724         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1725
1726         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1727               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1728         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1729
1730         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1731         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1732         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1733
1734         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1735         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1736
1737         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1738         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1739
1740         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1741               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1742         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1743
1744         /* Turn off SM_DSP clock. */
1745         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1746               MII_TG3_AUXCTL_ACTL_TX_6DB;
1747         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1748 }
1749
1750 static int tg3_wait_macro_done(struct tg3 *tp)
1751 {
1752         int limit = 100;
1753
1754         while (limit--) {
1755                 u32 tmp32;
1756
1757                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1758                         if ((tmp32 & 0x1000) == 0)
1759                                 break;
1760                 }
1761         }
1762         if (limit < 0)
1763                 return -EBUSY;
1764
1765         return 0;
1766 }
1767
1768 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1769 {
1770         static const u32 test_pat[4][6] = {
1771         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1772         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1773         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1774         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1775         };
1776         int chan;
1777
1778         for (chan = 0; chan < 4; chan++) {
1779                 int i;
1780
1781                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1782                              (chan * 0x2000) | 0x0200);
1783                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1784
1785                 for (i = 0; i < 6; i++)
1786                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1787                                      test_pat[chan][i]);
1788
1789                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1790                 if (tg3_wait_macro_done(tp)) {
1791                         *resetp = 1;
1792                         return -EBUSY;
1793                 }
1794
1795                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1796                              (chan * 0x2000) | 0x0200);
1797                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1798                 if (tg3_wait_macro_done(tp)) {
1799                         *resetp = 1;
1800                         return -EBUSY;
1801                 }
1802
1803                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1804                 if (tg3_wait_macro_done(tp)) {
1805                         *resetp = 1;
1806                         return -EBUSY;
1807                 }
1808
1809                 for (i = 0; i < 6; i += 2) {
1810                         u32 low, high;
1811
1812                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1813                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1814                             tg3_wait_macro_done(tp)) {
1815                                 *resetp = 1;
1816                                 return -EBUSY;
1817                         }
1818                         low &= 0x7fff;
1819                         high &= 0x000f;
1820                         if (low != test_pat[chan][i] ||
1821                             high != test_pat[chan][i+1]) {
1822                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1823                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1824                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1825
1826                                 return -EBUSY;
1827                         }
1828                 }
1829         }
1830
1831         return 0;
1832 }
1833
1834 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1835 {
1836         int chan;
1837
1838         for (chan = 0; chan < 4; chan++) {
1839                 int i;
1840
1841                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1842                              (chan * 0x2000) | 0x0200);
1843                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1844                 for (i = 0; i < 6; i++)
1845                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1846                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1847                 if (tg3_wait_macro_done(tp))
1848                         return -EBUSY;
1849         }
1850
1851         return 0;
1852 }
1853
1854 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1855 {
1856         u32 reg32, phy9_orig;
1857         int retries, do_phy_reset, err;
1858
1859         retries = 10;
1860         do_phy_reset = 1;
1861         do {
1862                 if (do_phy_reset) {
1863                         err = tg3_bmcr_reset(tp);
1864                         if (err)
1865                                 return err;
1866                         do_phy_reset = 0;
1867                 }
1868
1869                 /* Disable transmitter and interrupt.  */
1870                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1871                         continue;
1872
1873                 reg32 |= 0x3000;
1874                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1875
1876                 /* Set full-duplex, 1000 mbps.  */
1877                 tg3_writephy(tp, MII_BMCR,
1878                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1879
1880                 /* Set to master mode.  */
1881                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1882                         continue;
1883
1884                 tg3_writephy(tp, MII_TG3_CTRL,
1885                              (MII_TG3_CTRL_AS_MASTER |
1886                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1887
1888                 /* Enable SM_DSP_CLOCK and 6dB.  */
1889                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1890
1891                 /* Block the PHY control access.  */
1892                 tg3_phydsp_write(tp, 0x8005, 0x0800);
1893
1894                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1895                 if (!err)
1896                         break;
1897         } while (--retries);
1898
1899         err = tg3_phy_reset_chanpat(tp);
1900         if (err)
1901                 return err;
1902
1903         tg3_phydsp_write(tp, 0x8005, 0x0000);
1904
1905         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1906         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1907
1908         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1909             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1910                 /* Set Extended packet length bit for jumbo frames */
1911                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1912         } else {
1913                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1914         }
1915
1916         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1917
1918         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1919                 reg32 &= ~0x3000;
1920                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1921         } else if (!err)
1922                 err = -EBUSY;
1923
1924         return err;
1925 }
1926
1927 /* This will reset the tigon3 PHY if there is no valid
1928  * link unless the FORCE argument is non-zero.
1929  */
1930 static int tg3_phy_reset(struct tg3 *tp)
1931 {
1932         u32 val, cpmuctrl;
1933         int err;
1934
1935         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1936                 val = tr32(GRC_MISC_CFG);
1937                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1938                 udelay(40);
1939         }
1940         err  = tg3_readphy(tp, MII_BMSR, &val);
1941         err |= tg3_readphy(tp, MII_BMSR, &val);
1942         if (err != 0)
1943                 return -EBUSY;
1944
1945         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1946                 netif_carrier_off(tp->dev);
1947                 tg3_link_report(tp);
1948         }
1949
1950         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1951             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1952             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1953                 err = tg3_phy_reset_5703_4_5(tp);
1954                 if (err)
1955                         return err;
1956                 goto out;
1957         }
1958
1959         cpmuctrl = 0;
1960         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1961             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1962                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1963                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1964                         tw32(TG3_CPMU_CTRL,
1965                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1966         }
1967
1968         err = tg3_bmcr_reset(tp);
1969         if (err)
1970                 return err;
1971
1972         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1973                 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1974                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
1975
1976                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1977         }
1978
1979         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1980             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1981                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1982                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1983                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1984                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1985                         udelay(40);
1986                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1987                 }
1988         }
1989
1990         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1991              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1992             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
1993                 return 0;
1994
1995         tg3_phy_apply_otp(tp);
1996
1997         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
1998                 tg3_phy_toggle_apd(tp, true);
1999         else
2000                 tg3_phy_toggle_apd(tp, false);
2001
2002 out:
2003         if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
2004                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2005                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2006                 tg3_phydsp_write(tp, 0x000a, 0x0323);
2007                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2008         }
2009         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2010                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2011                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2012         }
2013         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2014                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2015                 tg3_phydsp_write(tp, 0x000a, 0x310b);
2016                 tg3_phydsp_write(tp, 0x201f, 0x9506);
2017                 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2018                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2019         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2020                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2021                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2022                 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2023                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2024                         tg3_writephy(tp, MII_TG3_TEST1,
2025                                      MII_TG3_TEST1_TRIM_EN | 0x4);
2026                 } else
2027                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2028                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2029         }
2030         /* Set Extended packet length bit (bit 14) on all chips that */
2031         /* support jumbo frames */
2032         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2033                 /* Cannot do read-modify-write on 5401 */
2034                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2035         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2036                 /* Set bit 14 with read-modify-write to preserve other bits */
2037                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2038                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
2039                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000);
2040         }
2041
2042         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2043          * jumbo frames transmission.
2044          */
2045         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2046                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2047                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2048                                      val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2049         }
2050
2051         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2052                 /* adjust output voltage */
2053                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2054         }
2055
2056         tg3_phy_toggle_automdix(tp, 1);
2057         tg3_phy_set_wirespeed(tp);
2058         return 0;
2059 }
2060
2061 static void tg3_frob_aux_power(struct tg3 *tp)
2062 {
2063         struct tg3 *tp_peer = tp;
2064
2065         /* The GPIOs do something completely different on 57765. */
2066         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2067             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2068             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2069                 return;
2070
2071         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2072             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2073             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2074                 struct net_device *dev_peer;
2075
2076                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2077                 /* remove_one() may have been run on the peer. */
2078                 if (!dev_peer)
2079                         tp_peer = tp;
2080                 else
2081                         tp_peer = netdev_priv(dev_peer);
2082         }
2083
2084         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2085             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2086             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2087             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2088                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2089                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2090                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2091                                     (GRC_LCLCTRL_GPIO_OE0 |
2092                                      GRC_LCLCTRL_GPIO_OE1 |
2093                                      GRC_LCLCTRL_GPIO_OE2 |
2094                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2095                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2096                                     100);
2097                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2098                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2099                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2100                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2101                                              GRC_LCLCTRL_GPIO_OE1 |
2102                                              GRC_LCLCTRL_GPIO_OE2 |
2103                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2104                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2105                                              tp->grc_local_ctrl;
2106                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2107
2108                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2109                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2110
2111                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2112                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2113                 } else {
2114                         u32 no_gpio2;
2115                         u32 grc_local_ctrl = 0;
2116
2117                         if (tp_peer != tp &&
2118                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2119                                 return;
2120
2121                         /* Workaround to prevent overdrawing Amps. */
2122                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2123                             ASIC_REV_5714) {
2124                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2125                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2126                                             grc_local_ctrl, 100);
2127                         }
2128
2129                         /* On 5753 and variants, GPIO2 cannot be used. */
2130                         no_gpio2 = tp->nic_sram_data_cfg &
2131                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2132
2133                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2134                                          GRC_LCLCTRL_GPIO_OE1 |
2135                                          GRC_LCLCTRL_GPIO_OE2 |
2136                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2137                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2138                         if (no_gpio2) {
2139                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2140                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2141                         }
2142                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2143                                                     grc_local_ctrl, 100);
2144
2145                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2146
2147                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2148                                                     grc_local_ctrl, 100);
2149
2150                         if (!no_gpio2) {
2151                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2152                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2153                                             grc_local_ctrl, 100);
2154                         }
2155                 }
2156         } else {
2157                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2158                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2159                         if (tp_peer != tp &&
2160                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2161                                 return;
2162
2163                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2164                                     (GRC_LCLCTRL_GPIO_OE1 |
2165                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2166
2167                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2168                                     GRC_LCLCTRL_GPIO_OE1, 100);
2169
2170                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2171                                     (GRC_LCLCTRL_GPIO_OE1 |
2172                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2173                 }
2174         }
2175 }
2176
2177 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2178 {
2179         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2180                 return 1;
2181         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2182                 if (speed != SPEED_10)
2183                         return 1;
2184         } else if (speed == SPEED_10)
2185                 return 1;
2186
2187         return 0;
2188 }
2189
2190 static int tg3_setup_phy(struct tg3 *, int);
2191
2192 #define RESET_KIND_SHUTDOWN     0
2193 #define RESET_KIND_INIT         1
2194 #define RESET_KIND_SUSPEND      2
2195
2196 static void tg3_write_sig_post_reset(struct tg3 *, int);
2197 static int tg3_halt_cpu(struct tg3 *, u32);
2198
2199 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2200 {
2201         u32 val;
2202
2203         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2204                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2205                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2206                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2207
2208                         sg_dig_ctrl |=
2209                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2210                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2211                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2212                 }
2213                 return;
2214         }
2215
2216         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2217                 tg3_bmcr_reset(tp);
2218                 val = tr32(GRC_MISC_CFG);
2219                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2220                 udelay(40);
2221                 return;
2222         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2223                 u32 phytest;
2224                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2225                         u32 phy;
2226
2227                         tg3_writephy(tp, MII_ADVERTISE, 0);
2228                         tg3_writephy(tp, MII_BMCR,
2229                                      BMCR_ANENABLE | BMCR_ANRESTART);
2230
2231                         tg3_writephy(tp, MII_TG3_FET_TEST,
2232                                      phytest | MII_TG3_FET_SHADOW_EN);
2233                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2234                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2235                                 tg3_writephy(tp,
2236                                              MII_TG3_FET_SHDW_AUXMODE4,
2237                                              phy);
2238                         }
2239                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2240                 }
2241                 return;
2242         } else if (do_low_power) {
2243                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2244                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2245
2246                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2247                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2248                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2249                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2250                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2251         }
2252
2253         /* The PHY should not be powered down on some chips because
2254          * of bugs.
2255          */
2256         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2257             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2258             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2259              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2260                 return;
2261
2262         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2263             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2264                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2265                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2266                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2267                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2268         }
2269
2270         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2271 }
2272
2273 /* tp->lock is held. */
2274 static int tg3_nvram_lock(struct tg3 *tp)
2275 {
2276         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2277                 int i;
2278
2279                 if (tp->nvram_lock_cnt == 0) {
2280                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2281                         for (i = 0; i < 8000; i++) {
2282                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2283                                         break;
2284                                 udelay(20);
2285                         }
2286                         if (i == 8000) {
2287                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2288                                 return -ENODEV;
2289                         }
2290                 }
2291                 tp->nvram_lock_cnt++;
2292         }
2293         return 0;
2294 }
2295
2296 /* tp->lock is held. */
2297 static void tg3_nvram_unlock(struct tg3 *tp)
2298 {
2299         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2300                 if (tp->nvram_lock_cnt > 0)
2301                         tp->nvram_lock_cnt--;
2302                 if (tp->nvram_lock_cnt == 0)
2303                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2304         }
2305 }
2306
2307 /* tp->lock is held. */
2308 static void tg3_enable_nvram_access(struct tg3 *tp)
2309 {
2310         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2311             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2312                 u32 nvaccess = tr32(NVRAM_ACCESS);
2313
2314                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2315         }
2316 }
2317
2318 /* tp->lock is held. */
2319 static void tg3_disable_nvram_access(struct tg3 *tp)
2320 {
2321         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2322             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2323                 u32 nvaccess = tr32(NVRAM_ACCESS);
2324
2325                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2326         }
2327 }
2328
2329 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2330                                         u32 offset, u32 *val)
2331 {
2332         u32 tmp;
2333         int i;
2334
2335         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2336                 return -EINVAL;
2337
2338         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2339                                         EEPROM_ADDR_DEVID_MASK |
2340                                         EEPROM_ADDR_READ);
2341         tw32(GRC_EEPROM_ADDR,
2342              tmp |
2343              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2344              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2345               EEPROM_ADDR_ADDR_MASK) |
2346              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2347
2348         for (i = 0; i < 1000; i++) {
2349                 tmp = tr32(GRC_EEPROM_ADDR);
2350
2351                 if (tmp & EEPROM_ADDR_COMPLETE)
2352                         break;
2353                 msleep(1);
2354         }
2355         if (!(tmp & EEPROM_ADDR_COMPLETE))
2356                 return -EBUSY;
2357
2358         tmp = tr32(GRC_EEPROM_DATA);
2359
2360         /*
2361          * The data will always be opposite the native endian
2362          * format.  Perform a blind byteswap to compensate.
2363          */
2364         *val = swab32(tmp);
2365
2366         return 0;
2367 }
2368
2369 #define NVRAM_CMD_TIMEOUT 10000
2370
2371 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2372 {
2373         int i;
2374
2375         tw32(NVRAM_CMD, nvram_cmd);
2376         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2377                 udelay(10);
2378                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2379                         udelay(10);
2380                         break;
2381                 }
2382         }
2383
2384         if (i == NVRAM_CMD_TIMEOUT)
2385                 return -EBUSY;
2386
2387         return 0;
2388 }
2389
2390 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2391 {
2392         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2393             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2394             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2395            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2396             (tp->nvram_jedecnum == JEDEC_ATMEL))
2397
2398                 addr = ((addr / tp->nvram_pagesize) <<
2399                         ATMEL_AT45DB0X1B_PAGE_POS) +
2400                        (addr % tp->nvram_pagesize);
2401
2402         return addr;
2403 }
2404
2405 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2406 {
2407         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2408             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2409             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2410            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2411             (tp->nvram_jedecnum == JEDEC_ATMEL))
2412
2413                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2414                         tp->nvram_pagesize) +
2415                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2416
2417         return addr;
2418 }
2419
2420 /* NOTE: Data read in from NVRAM is byteswapped according to
2421  * the byteswapping settings for all other register accesses.
2422  * tg3 devices are BE devices, so on a BE machine, the data
2423  * returned will be exactly as it is seen in NVRAM.  On a LE
2424  * machine, the 32-bit value will be byteswapped.
2425  */
2426 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2427 {
2428         int ret;
2429
2430         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2431                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2432
2433         offset = tg3_nvram_phys_addr(tp, offset);
2434
2435         if (offset > NVRAM_ADDR_MSK)
2436                 return -EINVAL;
2437
2438         ret = tg3_nvram_lock(tp);
2439         if (ret)
2440                 return ret;
2441
2442         tg3_enable_nvram_access(tp);
2443
2444         tw32(NVRAM_ADDR, offset);
2445         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2446                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2447
2448         if (ret == 0)
2449                 *val = tr32(NVRAM_RDDATA);
2450
2451         tg3_disable_nvram_access(tp);
2452
2453         tg3_nvram_unlock(tp);
2454
2455         return ret;
2456 }
2457
2458 /* Ensures NVRAM data is in bytestream format. */
2459 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2460 {
2461         u32 v;
2462         int res = tg3_nvram_read(tp, offset, &v);
2463         if (!res)
2464                 *val = cpu_to_be32(v);
2465         return res;
2466 }
2467
2468 /* tp->lock is held. */
2469 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2470 {
2471         u32 addr_high, addr_low;
2472         int i;
2473
2474         addr_high = ((tp->dev->dev_addr[0] << 8) |
2475                      tp->dev->dev_addr[1]);
2476         addr_low = ((tp->dev->dev_addr[2] << 24) |
2477                     (tp->dev->dev_addr[3] << 16) |
2478                     (tp->dev->dev_addr[4] <<  8) |
2479                     (tp->dev->dev_addr[5] <<  0));
2480         for (i = 0; i < 4; i++) {
2481                 if (i == 1 && skip_mac_1)
2482                         continue;
2483                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2484                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2485         }
2486
2487         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2488             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2489                 for (i = 0; i < 12; i++) {
2490                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2491                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2492                 }
2493         }
2494
2495         addr_high = (tp->dev->dev_addr[0] +
2496                      tp->dev->dev_addr[1] +
2497                      tp->dev->dev_addr[2] +
2498                      tp->dev->dev_addr[3] +
2499                      tp->dev->dev_addr[4] +
2500                      tp->dev->dev_addr[5]) &
2501                 TX_BACKOFF_SEED_MASK;
2502         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2503 }
2504
2505 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2506 {
2507         u32 misc_host_ctrl;
2508         bool device_should_wake, do_low_power;
2509
2510         /* Make sure register accesses (indirect or otherwise)
2511          * will function correctly.
2512          */
2513         pci_write_config_dword(tp->pdev,
2514                                TG3PCI_MISC_HOST_CTRL,
2515                                tp->misc_host_ctrl);
2516
2517         switch (state) {
2518         case PCI_D0:
2519                 pci_enable_wake(tp->pdev, state, false);
2520                 pci_set_power_state(tp->pdev, PCI_D0);
2521
2522                 /* Switch out of Vaux if it is a NIC */
2523                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2524                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2525
2526                 return 0;
2527
2528         case PCI_D1:
2529         case PCI_D2:
2530         case PCI_D3hot:
2531                 break;
2532
2533         default:
2534                 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2535                            state);
2536                 return -EINVAL;
2537         }
2538
2539         /* Restore the CLKREQ setting. */
2540         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2541                 u16 lnkctl;
2542
2543                 pci_read_config_word(tp->pdev,
2544                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2545                                      &lnkctl);
2546                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2547                 pci_write_config_word(tp->pdev,
2548                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2549                                       lnkctl);
2550         }
2551
2552         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2553         tw32(TG3PCI_MISC_HOST_CTRL,
2554              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2555
2556         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2557                              device_may_wakeup(&tp->pdev->dev) &&
2558                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2559
2560         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2561                 do_low_power = false;
2562                 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2563                     !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2564                         struct phy_device *phydev;
2565                         u32 phyid, advertising;
2566
2567                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2568
2569                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2570
2571                         tp->link_config.orig_speed = phydev->speed;
2572                         tp->link_config.orig_duplex = phydev->duplex;
2573                         tp->link_config.orig_autoneg = phydev->autoneg;
2574                         tp->link_config.orig_advertising = phydev->advertising;
2575
2576                         advertising = ADVERTISED_TP |
2577                                       ADVERTISED_Pause |
2578                                       ADVERTISED_Autoneg |
2579                                       ADVERTISED_10baseT_Half;
2580
2581                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2582                             device_should_wake) {
2583                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2584                                         advertising |=
2585                                                 ADVERTISED_100baseT_Half |
2586                                                 ADVERTISED_100baseT_Full |
2587                                                 ADVERTISED_10baseT_Full;
2588                                 else
2589                                         advertising |= ADVERTISED_10baseT_Full;
2590                         }
2591
2592                         phydev->advertising = advertising;
2593
2594                         phy_start_aneg(phydev);
2595
2596                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2597                         if (phyid != PHY_ID_BCMAC131) {
2598                                 phyid &= PHY_BCM_OUI_MASK;
2599                                 if (phyid == PHY_BCM_OUI_1 ||
2600                                     phyid == PHY_BCM_OUI_2 ||
2601                                     phyid == PHY_BCM_OUI_3)
2602                                         do_low_power = true;
2603                         }
2604                 }
2605         } else {
2606                 do_low_power = true;
2607
2608                 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2609                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2610                         tp->link_config.orig_speed = tp->link_config.speed;
2611                         tp->link_config.orig_duplex = tp->link_config.duplex;
2612                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2613                 }
2614
2615                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2616                         tp->link_config.speed = SPEED_10;
2617                         tp->link_config.duplex = DUPLEX_HALF;
2618                         tp->link_config.autoneg = AUTONEG_ENABLE;
2619                         tg3_setup_phy(tp, 0);
2620                 }
2621         }
2622
2623         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2624                 u32 val;
2625
2626                 val = tr32(GRC_VCPU_EXT_CTRL);
2627                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2628         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2629                 int i;
2630                 u32 val;
2631
2632                 for (i = 0; i < 200; i++) {
2633                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2634                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2635                                 break;
2636                         msleep(1);
2637                 }
2638         }
2639         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2640                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2641                                                      WOL_DRV_STATE_SHUTDOWN |
2642                                                      WOL_DRV_WOL |
2643                                                      WOL_SET_MAGIC_PKT);
2644
2645         if (device_should_wake) {
2646                 u32 mac_mode;
2647
2648                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2649                         if (do_low_power) {
2650                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2651                                 udelay(40);
2652                         }
2653
2654                         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2655                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2656                         else
2657                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2658
2659                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2660                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2661                             ASIC_REV_5700) {
2662                                 u32 speed = (tp->tg3_flags &
2663                                              TG3_FLAG_WOL_SPEED_100MB) ?
2664                                              SPEED_100 : SPEED_10;
2665                                 if (tg3_5700_link_polarity(tp, speed))
2666                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2667                                 else
2668                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2669                         }
2670                 } else {
2671                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2672                 }
2673
2674                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2675                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2676
2677                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2678                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2679                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2680                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2681                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2682                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2683
2684                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2685                         mac_mode |= tp->mac_mode &
2686                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2687                         if (mac_mode & MAC_MODE_APE_TX_EN)
2688                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2689                 }
2690
2691                 tw32_f(MAC_MODE, mac_mode);
2692                 udelay(100);
2693
2694                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2695                 udelay(10);
2696         }
2697
2698         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2699             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2700              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2701                 u32 base_val;
2702
2703                 base_val = tp->pci_clock_ctrl;
2704                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2705                              CLOCK_CTRL_TXCLK_DISABLE);
2706
2707                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2708                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2709         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2710                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2711                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2712                 /* do nothing */
2713         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2714                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2715                 u32 newbits1, newbits2;
2716
2717                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2718                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2719                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2720                                     CLOCK_CTRL_TXCLK_DISABLE |
2721                                     CLOCK_CTRL_ALTCLK);
2722                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2723                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2724                         newbits1 = CLOCK_CTRL_625_CORE;
2725                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2726                 } else {
2727                         newbits1 = CLOCK_CTRL_ALTCLK;
2728                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2729                 }
2730
2731                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2732                             40);
2733
2734                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2735                             40);
2736
2737                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2738                         u32 newbits3;
2739
2740                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2741                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2742                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2743                                             CLOCK_CTRL_TXCLK_DISABLE |
2744                                             CLOCK_CTRL_44MHZ_CORE);
2745                         } else {
2746                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2747                         }
2748
2749                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2750                                     tp->pci_clock_ctrl | newbits3, 40);
2751                 }
2752         }
2753
2754         if (!(device_should_wake) &&
2755             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2756                 tg3_power_down_phy(tp, do_low_power);
2757
2758         tg3_frob_aux_power(tp);
2759
2760         /* Workaround for unstable PLL clock */
2761         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2762             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2763                 u32 val = tr32(0x7d00);
2764
2765                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2766                 tw32(0x7d00, val);
2767                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2768                         int err;
2769
2770                         err = tg3_nvram_lock(tp);
2771                         tg3_halt_cpu(tp, RX_CPU_BASE);
2772                         if (!err)
2773                                 tg3_nvram_unlock(tp);
2774                 }
2775         }
2776
2777         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2778
2779         if (device_should_wake)
2780                 pci_enable_wake(tp->pdev, state, true);
2781
2782         /* Finally, set the new power state. */
2783         pci_set_power_state(tp->pdev, state);
2784
2785         return 0;
2786 }
2787
2788 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2789 {
2790         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2791         case MII_TG3_AUX_STAT_10HALF:
2792                 *speed = SPEED_10;
2793                 *duplex = DUPLEX_HALF;
2794                 break;
2795
2796         case MII_TG3_AUX_STAT_10FULL:
2797                 *speed = SPEED_10;
2798                 *duplex = DUPLEX_FULL;
2799                 break;
2800
2801         case MII_TG3_AUX_STAT_100HALF:
2802                 *speed = SPEED_100;
2803                 *duplex = DUPLEX_HALF;
2804                 break;
2805
2806         case MII_TG3_AUX_STAT_100FULL:
2807                 *speed = SPEED_100;
2808                 *duplex = DUPLEX_FULL;
2809                 break;
2810
2811         case MII_TG3_AUX_STAT_1000HALF:
2812                 *speed = SPEED_1000;
2813                 *duplex = DUPLEX_HALF;
2814                 break;
2815
2816         case MII_TG3_AUX_STAT_1000FULL:
2817                 *speed = SPEED_1000;
2818                 *duplex = DUPLEX_FULL;
2819                 break;
2820
2821         default:
2822                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2823                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2824                                  SPEED_10;
2825                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2826                                   DUPLEX_HALF;
2827                         break;
2828                 }
2829                 *speed = SPEED_INVALID;
2830                 *duplex = DUPLEX_INVALID;
2831                 break;
2832         }
2833 }
2834
2835 static void tg3_phy_copper_begin(struct tg3 *tp)
2836 {
2837         u32 new_adv;
2838         int i;
2839
2840         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2841                 /* Entering low power mode.  Disable gigabit and
2842                  * 100baseT advertisements.
2843                  */
2844                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2845
2846                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2847                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2848                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2849                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2850
2851                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2852         } else if (tp->link_config.speed == SPEED_INVALID) {
2853                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2854                         tp->link_config.advertising &=
2855                                 ~(ADVERTISED_1000baseT_Half |
2856                                   ADVERTISED_1000baseT_Full);
2857
2858                 new_adv = ADVERTISE_CSMA;
2859                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2860                         new_adv |= ADVERTISE_10HALF;
2861                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2862                         new_adv |= ADVERTISE_10FULL;
2863                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2864                         new_adv |= ADVERTISE_100HALF;
2865                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2866                         new_adv |= ADVERTISE_100FULL;
2867
2868                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2869
2870                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2871
2872                 if (tp->link_config.advertising &
2873                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2874                         new_adv = 0;
2875                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2876                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2877                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2878                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2879                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
2880                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2881                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2882                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2883                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2884                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2885                 } else {
2886                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2887                 }
2888         } else {
2889                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2890                 new_adv |= ADVERTISE_CSMA;
2891
2892                 /* Asking for a specific link mode. */
2893                 if (tp->link_config.speed == SPEED_1000) {
2894                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2895
2896                         if (tp->link_config.duplex == DUPLEX_FULL)
2897                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2898                         else
2899                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2900                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2901                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2902                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2903                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2904                 } else {
2905                         if (tp->link_config.speed == SPEED_100) {
2906                                 if (tp->link_config.duplex == DUPLEX_FULL)
2907                                         new_adv |= ADVERTISE_100FULL;
2908                                 else
2909                                         new_adv |= ADVERTISE_100HALF;
2910                         } else {
2911                                 if (tp->link_config.duplex == DUPLEX_FULL)
2912                                         new_adv |= ADVERTISE_10FULL;
2913                                 else
2914                                         new_adv |= ADVERTISE_10HALF;
2915                         }
2916                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2917
2918                         new_adv = 0;
2919                 }
2920
2921                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2922         }
2923
2924         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2925             tp->link_config.speed != SPEED_INVALID) {
2926                 u32 bmcr, orig_bmcr;
2927
2928                 tp->link_config.active_speed = tp->link_config.speed;
2929                 tp->link_config.active_duplex = tp->link_config.duplex;
2930
2931                 bmcr = 0;
2932                 switch (tp->link_config.speed) {
2933                 default:
2934                 case SPEED_10:
2935                         break;
2936
2937                 case SPEED_100:
2938                         bmcr |= BMCR_SPEED100;
2939                         break;
2940
2941                 case SPEED_1000:
2942                         bmcr |= TG3_BMCR_SPEED1000;
2943                         break;
2944                 }
2945
2946                 if (tp->link_config.duplex == DUPLEX_FULL)
2947                         bmcr |= BMCR_FULLDPLX;
2948
2949                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2950                     (bmcr != orig_bmcr)) {
2951                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2952                         for (i = 0; i < 1500; i++) {
2953                                 u32 tmp;
2954
2955                                 udelay(10);
2956                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2957                                     tg3_readphy(tp, MII_BMSR, &tmp))
2958                                         continue;
2959                                 if (!(tmp & BMSR_LSTATUS)) {
2960                                         udelay(40);
2961                                         break;
2962                                 }
2963                         }
2964                         tg3_writephy(tp, MII_BMCR, bmcr);
2965                         udelay(40);
2966                 }
2967         } else {
2968                 tg3_writephy(tp, MII_BMCR,
2969                              BMCR_ANENABLE | BMCR_ANRESTART);
2970         }
2971 }
2972
2973 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2974 {
2975         int err;
2976
2977         /* Turn off tap power management. */
2978         /* Set Extended packet length bit */
2979         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2980
2981         err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
2982         err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
2983         err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
2984         err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
2985         err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
2986
2987         udelay(40);
2988
2989         return err;
2990 }
2991
2992 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2993 {
2994         u32 adv_reg, all_mask = 0;
2995
2996         if (mask & ADVERTISED_10baseT_Half)
2997                 all_mask |= ADVERTISE_10HALF;
2998         if (mask & ADVERTISED_10baseT_Full)
2999                 all_mask |= ADVERTISE_10FULL;
3000         if (mask & ADVERTISED_100baseT_Half)
3001                 all_mask |= ADVERTISE_100HALF;
3002         if (mask & ADVERTISED_100baseT_Full)
3003                 all_mask |= ADVERTISE_100FULL;
3004
3005         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3006                 return 0;
3007
3008         if ((adv_reg & all_mask) != all_mask)
3009                 return 0;
3010         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3011                 u32 tg3_ctrl;
3012
3013                 all_mask = 0;
3014                 if (mask & ADVERTISED_1000baseT_Half)
3015                         all_mask |= ADVERTISE_1000HALF;
3016                 if (mask & ADVERTISED_1000baseT_Full)
3017                         all_mask |= ADVERTISE_1000FULL;
3018
3019                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3020                         return 0;
3021
3022                 if ((tg3_ctrl & all_mask) != all_mask)
3023                         return 0;
3024         }
3025         return 1;
3026 }
3027
3028 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3029 {
3030         u32 curadv, reqadv;
3031
3032         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3033                 return 1;
3034
3035         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3036         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3037
3038         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3039                 if (curadv != reqadv)
3040                         return 0;
3041
3042                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3043                         tg3_readphy(tp, MII_LPA, rmtadv);
3044         } else {
3045                 /* Reprogram the advertisement register, even if it
3046                  * does not affect the current link.  If the link
3047                  * gets renegotiated in the future, we can save an
3048                  * additional renegotiation cycle by advertising
3049                  * it correctly in the first place.
3050                  */
3051                 if (curadv != reqadv) {
3052                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3053                                      ADVERTISE_PAUSE_ASYM);
3054                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3055                 }
3056         }
3057
3058         return 1;
3059 }
3060
3061 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3062 {
3063         int current_link_up;
3064         u32 bmsr, val;
3065         u32 lcl_adv, rmt_adv;
3066         u16 current_speed;
3067         u8 current_duplex;
3068         int i, err;
3069
3070         tw32(MAC_EVENT, 0);
3071
3072         tw32_f(MAC_STATUS,
3073              (MAC_STATUS_SYNC_CHANGED |
3074               MAC_STATUS_CFG_CHANGED |
3075               MAC_STATUS_MI_COMPLETION |
3076               MAC_STATUS_LNKSTATE_CHANGED));
3077         udelay(40);
3078
3079         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3080                 tw32_f(MAC_MI_MODE,
3081                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3082                 udelay(80);
3083         }
3084
3085         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3086
3087         /* Some third-party PHYs need to be reset on link going
3088          * down.
3089          */
3090         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3091              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3092              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3093             netif_carrier_ok(tp->dev)) {
3094                 tg3_readphy(tp, MII_BMSR, &bmsr);
3095                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3096                     !(bmsr & BMSR_LSTATUS))
3097                         force_reset = 1;
3098         }
3099         if (force_reset)
3100                 tg3_phy_reset(tp);
3101
3102         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3103                 tg3_readphy(tp, MII_BMSR, &bmsr);
3104                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3105                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3106                         bmsr = 0;
3107
3108                 if (!(bmsr & BMSR_LSTATUS)) {
3109                         err = tg3_init_5401phy_dsp(tp);
3110                         if (err)
3111                                 return err;
3112
3113                         tg3_readphy(tp, MII_BMSR, &bmsr);
3114                         for (i = 0; i < 1000; i++) {
3115                                 udelay(10);
3116                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3117                                     (bmsr & BMSR_LSTATUS)) {
3118                                         udelay(40);
3119                                         break;
3120                                 }
3121                         }
3122
3123                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3124                             TG3_PHY_REV_BCM5401_B0 &&
3125                             !(bmsr & BMSR_LSTATUS) &&
3126                             tp->link_config.active_speed == SPEED_1000) {
3127                                 err = tg3_phy_reset(tp);
3128                                 if (!err)
3129                                         err = tg3_init_5401phy_dsp(tp);
3130                                 if (err)
3131                                         return err;
3132                         }
3133                 }
3134         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3135                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3136                 /* 5701 {A0,B0} CRC bug workaround */
3137                 tg3_writephy(tp, 0x15, 0x0a75);
3138                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3139                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3140                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3141         }
3142
3143         /* Clear pending interrupts... */
3144         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3145         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3146
3147         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3148                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3149         else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3150                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3151
3152         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3153             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3154                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3155                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3156                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3157                 else
3158                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3159         }
3160
3161         current_link_up = 0;
3162         current_speed = SPEED_INVALID;
3163         current_duplex = DUPLEX_INVALID;
3164
3165         if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3166                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3167                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3168                 if (!(val & (1 << 10))) {
3169                         val |= (1 << 10);
3170                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3171                         goto relink;
3172                 }
3173         }
3174
3175         bmsr = 0;
3176         for (i = 0; i < 100; i++) {
3177                 tg3_readphy(tp, MII_BMSR, &bmsr);
3178                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3179                     (bmsr & BMSR_LSTATUS))
3180                         break;
3181                 udelay(40);
3182         }
3183
3184         if (bmsr & BMSR_LSTATUS) {
3185                 u32 aux_stat, bmcr;
3186
3187                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3188                 for (i = 0; i < 2000; i++) {
3189                         udelay(10);
3190                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3191                             aux_stat)
3192                                 break;
3193                 }
3194
3195                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3196                                              &current_speed,
3197                                              &current_duplex);
3198
3199                 bmcr = 0;
3200                 for (i = 0; i < 200; i++) {
3201                         tg3_readphy(tp, MII_BMCR, &bmcr);
3202                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3203                                 continue;
3204                         if (bmcr && bmcr != 0x7fff)
3205                                 break;
3206                         udelay(10);
3207                 }
3208
3209                 lcl_adv = 0;
3210                 rmt_adv = 0;
3211
3212                 tp->link_config.active_speed = current_speed;
3213                 tp->link_config.active_duplex = current_duplex;
3214
3215                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3216                         if ((bmcr & BMCR_ANENABLE) &&
3217                             tg3_copper_is_advertising_all(tp,
3218                                                 tp->link_config.advertising)) {
3219                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3220                                                                   &rmt_adv))
3221                                         current_link_up = 1;
3222                         }
3223                 } else {
3224                         if (!(bmcr & BMCR_ANENABLE) &&
3225                             tp->link_config.speed == current_speed &&
3226                             tp->link_config.duplex == current_duplex &&
3227                             tp->link_config.flowctrl ==
3228                             tp->link_config.active_flowctrl) {
3229                                 current_link_up = 1;
3230                         }
3231                 }
3232
3233                 if (current_link_up == 1 &&
3234                     tp->link_config.active_duplex == DUPLEX_FULL)
3235                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3236         }
3237
3238 relink:
3239         if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3240                 tg3_phy_copper_begin(tp);
3241
3242                 tg3_readphy(tp, MII_BMSR, &bmsr);
3243                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3244                     (bmsr & BMSR_LSTATUS))
3245                         current_link_up = 1;
3246         }
3247
3248         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3249         if (current_link_up == 1) {
3250                 if (tp->link_config.active_speed == SPEED_100 ||
3251                     tp->link_config.active_speed == SPEED_10)
3252                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3253                 else
3254                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3255         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3256                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3257         else
3258                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3259
3260         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3261         if (tp->link_config.active_duplex == DUPLEX_HALF)
3262                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3263
3264         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3265                 if (current_link_up == 1 &&
3266                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3267                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3268                 else
3269                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3270         }
3271
3272         /* ??? Without this setting Netgear GA302T PHY does not
3273          * ??? send/receive packets...
3274          */
3275         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3276             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3277                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3278                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3279                 udelay(80);
3280         }
3281
3282         tw32_f(MAC_MODE, tp->mac_mode);
3283         udelay(40);
3284
3285         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3286                 /* Polled via timer. */
3287                 tw32_f(MAC_EVENT, 0);
3288         } else {
3289                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3290         }
3291         udelay(40);
3292
3293         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3294             current_link_up == 1 &&
3295             tp->link_config.active_speed == SPEED_1000 &&
3296             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3297              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3298                 udelay(120);
3299                 tw32_f(MAC_STATUS,
3300                      (MAC_STATUS_SYNC_CHANGED |
3301                       MAC_STATUS_CFG_CHANGED));
3302                 udelay(40);
3303                 tg3_write_mem(tp,
3304                               NIC_SRAM_FIRMWARE_MBOX,
3305                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3306         }
3307
3308         /* Prevent send BD corruption. */
3309         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3310                 u16 oldlnkctl, newlnkctl;
3311
3312                 pci_read_config_word(tp->pdev,
3313                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3314                                      &oldlnkctl);
3315                 if (tp->link_config.active_speed == SPEED_100 ||
3316                     tp->link_config.active_speed == SPEED_10)
3317                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3318                 else
3319                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3320                 if (newlnkctl != oldlnkctl)
3321                         pci_write_config_word(tp->pdev,
3322                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3323                                               newlnkctl);
3324         }
3325
3326         if (current_link_up != netif_carrier_ok(tp->dev)) {
3327                 if (current_link_up)
3328                         netif_carrier_on(tp->dev);
3329                 else
3330                         netif_carrier_off(tp->dev);
3331                 tg3_link_report(tp);
3332         }
3333
3334         return 0;
3335 }
3336
3337 struct tg3_fiber_aneginfo {
3338         int state;
3339 #define ANEG_STATE_UNKNOWN              0
3340 #define ANEG_STATE_AN_ENABLE            1
3341 #define ANEG_STATE_RESTART_INIT         2
3342 #define ANEG_STATE_RESTART              3
3343 #define ANEG_STATE_DISABLE_LINK_OK      4
3344 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3345 #define ANEG_STATE_ABILITY_DETECT       6
3346 #define ANEG_STATE_ACK_DETECT_INIT      7
3347 #define ANEG_STATE_ACK_DETECT           8
3348 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3349 #define ANEG_STATE_COMPLETE_ACK         10
3350 #define ANEG_STATE_IDLE_DETECT_INIT     11
3351 #define ANEG_STATE_IDLE_DETECT          12
3352 #define ANEG_STATE_LINK_OK              13
3353 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3354 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3355
3356         u32 flags;
3357 #define MR_AN_ENABLE            0x00000001
3358 #define MR_RESTART_AN           0x00000002
3359 #define MR_AN_COMPLETE          0x00000004
3360 #define MR_PAGE_RX              0x00000008
3361 #define MR_NP_LOADED            0x00000010
3362 #define MR_TOGGLE_TX            0x00000020
3363 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3364 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3365 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3366 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3367 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3368 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3369 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3370 #define MR_TOGGLE_RX            0x00002000
3371 #define MR_NP_RX                0x00004000
3372
3373 #define MR_LINK_OK              0x80000000
3374
3375         unsigned long link_time, cur_time;
3376
3377         u32 ability_match_cfg;
3378         int ability_match_count;
3379
3380         char ability_match, idle_match, ack_match;
3381
3382         u32 txconfig, rxconfig;
3383 #define ANEG_CFG_NP             0x00000080
3384 #define ANEG_CFG_ACK            0x00000040
3385 #define ANEG_CFG_RF2            0x00000020
3386 #define ANEG_CFG_RF1            0x00000010
3387 #define ANEG_CFG_PS2            0x00000001
3388 #define ANEG_CFG_PS1            0x00008000
3389 #define ANEG_CFG_HD             0x00004000
3390 #define ANEG_CFG_FD             0x00002000
3391 #define ANEG_CFG_INVAL          0x00001f06
3392
3393 };
3394 #define ANEG_OK         0
3395 #define ANEG_DONE       1
3396 #define ANEG_TIMER_ENAB 2
3397 #define ANEG_FAILED     -1
3398
3399 #define ANEG_STATE_SETTLE_TIME  10000
3400
3401 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3402                                    struct tg3_fiber_aneginfo *ap)
3403 {
3404         u16 flowctrl;
3405         unsigned long delta;
3406         u32 rx_cfg_reg;
3407         int ret;
3408
3409         if (ap->state == ANEG_STATE_UNKNOWN) {
3410                 ap->rxconfig = 0;
3411                 ap->link_time = 0;
3412                 ap->cur_time = 0;
3413                 ap->ability_match_cfg = 0;
3414                 ap->ability_match_count = 0;
3415                 ap->ability_match = 0;
3416                 ap->idle_match = 0;
3417                 ap->ack_match = 0;
3418         }
3419         ap->cur_time++;
3420
3421         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3422                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3423
3424                 if (rx_cfg_reg != ap->ability_match_cfg) {
3425                         ap->ability_match_cfg = rx_cfg_reg;
3426                         ap->ability_match = 0;
3427                         ap->ability_match_count = 0;
3428                 } else {
3429                         if (++ap->ability_match_count > 1) {
3430                                 ap->ability_match = 1;
3431                                 ap->ability_match_cfg = rx_cfg_reg;
3432                         }
3433                 }
3434                 if (rx_cfg_reg & ANEG_CFG_ACK)
3435                         ap->ack_match = 1;
3436                 else
3437                         ap->ack_match = 0;
3438
3439                 ap->idle_match = 0;
3440         } else {
3441                 ap->idle_match = 1;
3442                 ap->ability_match_cfg = 0;
3443                 ap->ability_match_count = 0;
3444                 ap->ability_match = 0;
3445                 ap->ack_match = 0;
3446
3447                 rx_cfg_reg = 0;
3448         }
3449
3450         ap->rxconfig = rx_cfg_reg;
3451         ret = ANEG_OK;
3452
3453         switch (ap->state) {
3454         case ANEG_STATE_UNKNOWN:
3455                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3456                         ap->state = ANEG_STATE_AN_ENABLE;
3457
3458                 /* fallthru */
3459         case ANEG_STATE_AN_ENABLE:
3460                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3461                 if (ap->flags & MR_AN_ENABLE) {
3462                         ap->link_time = 0;
3463                         ap->cur_time = 0;
3464                         ap->ability_match_cfg = 0;
3465                         ap->ability_match_count = 0;
3466                         ap->ability_match = 0;
3467                         ap->idle_match = 0;
3468                         ap->ack_match = 0;
3469
3470                         ap->state = ANEG_STATE_RESTART_INIT;
3471                 } else {
3472                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3473                 }
3474                 break;
3475
3476         case ANEG_STATE_RESTART_INIT:
3477                 ap->link_time = ap->cur_time;
3478                 ap->flags &= ~(MR_NP_LOADED);
3479                 ap->txconfig = 0;
3480                 tw32(MAC_TX_AUTO_NEG, 0);
3481                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3482                 tw32_f(MAC_MODE, tp->mac_mode);
3483                 udelay(40);
3484
3485                 ret = ANEG_TIMER_ENAB;
3486                 ap->state = ANEG_STATE_RESTART;
3487
3488                 /* fallthru */
3489         case ANEG_STATE_RESTART:
3490                 delta = ap->cur_time - ap->link_time;
3491                 if (delta > ANEG_STATE_SETTLE_TIME)
3492                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3493                 else
3494                         ret = ANEG_TIMER_ENAB;
3495                 break;
3496
3497         case ANEG_STATE_DISABLE_LINK_OK:
3498                 ret = ANEG_DONE;
3499                 break;
3500
3501         case ANEG_STATE_ABILITY_DETECT_INIT:
3502                 ap->flags &= ~(MR_TOGGLE_TX);
3503                 ap->txconfig = ANEG_CFG_FD;
3504                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3505                 if (flowctrl & ADVERTISE_1000XPAUSE)
3506                         ap->txconfig |= ANEG_CFG_PS1;
3507                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3508                         ap->txconfig |= ANEG_CFG_PS2;
3509                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3510                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3511                 tw32_f(MAC_MODE, tp->mac_mode);
3512                 udelay(40);
3513
3514                 ap->state = ANEG_STATE_ABILITY_DETECT;
3515                 break;
3516
3517         case ANEG_STATE_ABILITY_DETECT:
3518                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3519                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3520                 break;
3521
3522         case ANEG_STATE_ACK_DETECT_INIT:
3523                 ap->txconfig |= ANEG_CFG_ACK;
3524                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3525                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3526                 tw32_f(MAC_MODE, tp->mac_mode);
3527                 udelay(40);
3528
3529                 ap->state = ANEG_STATE_ACK_DETECT;
3530
3531                 /* fallthru */
3532         case ANEG_STATE_ACK_DETECT:
3533                 if (ap->ack_match != 0) {
3534                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3535                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3536                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3537                         } else {
3538                                 ap->state = ANEG_STATE_AN_ENABLE;
3539                         }
3540                 } else if (ap->ability_match != 0 &&
3541                            ap->rxconfig == 0) {
3542                         ap->state = ANEG_STATE_AN_ENABLE;
3543                 }
3544                 break;
3545
3546         case ANEG_STATE_COMPLETE_ACK_INIT:
3547                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3548                         ret = ANEG_FAILED;
3549                         break;
3550                 }
3551                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3552                                MR_LP_ADV_HALF_DUPLEX |
3553                                MR_LP_ADV_SYM_PAUSE |
3554                                MR_LP_ADV_ASYM_PAUSE |
3555                                MR_LP_ADV_REMOTE_FAULT1 |
3556                                MR_LP_ADV_REMOTE_FAULT2 |
3557                                MR_LP_ADV_NEXT_PAGE |
3558                                MR_TOGGLE_RX |
3559                                MR_NP_RX);
3560                 if (ap->rxconfig & ANEG_CFG_FD)
3561                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3562                 if (ap->rxconfig & ANEG_CFG_HD)
3563                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3564                 if (ap->rxconfig & ANEG_CFG_PS1)
3565                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3566                 if (ap->rxconfig & ANEG_CFG_PS2)
3567                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3568                 if (ap->rxconfig & ANEG_CFG_RF1)
3569                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3570                 if (ap->rxconfig & ANEG_CFG_RF2)
3571                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3572                 if (ap->rxconfig & ANEG_CFG_NP)
3573                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3574
3575                 ap->link_time = ap->cur_time;
3576
3577                 ap->flags ^= (MR_TOGGLE_TX);
3578                 if (ap->rxconfig & 0x0008)
3579                         ap->flags |= MR_TOGGLE_RX;
3580                 if (ap->rxconfig & ANEG_CFG_NP)
3581                         ap->flags |= MR_NP_RX;
3582                 ap->flags |= MR_PAGE_RX;
3583
3584                 ap->state = ANEG_STATE_COMPLETE_ACK;
3585                 ret = ANEG_TIMER_ENAB;
3586                 break;
3587
3588         case ANEG_STATE_COMPLETE_ACK:
3589                 if (ap->ability_match != 0 &&
3590                     ap->rxconfig == 0) {
3591                         ap->state = ANEG_STATE_AN_ENABLE;
3592                         break;
3593                 }
3594                 delta = ap->cur_time - ap->link_time;
3595                 if (delta > ANEG_STATE_SETTLE_TIME) {
3596                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3597                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3598                         } else {
3599                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3600                                     !(ap->flags & MR_NP_RX)) {
3601                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3602                                 } else {
3603                                         ret = ANEG_FAILED;
3604                                 }
3605                         }
3606                 }
3607                 break;
3608
3609         case ANEG_STATE_IDLE_DETECT_INIT:
3610                 ap->link_time = ap->cur_time;
3611                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3612                 tw32_f(MAC_MODE, tp->mac_mode);
3613                 udelay(40);
3614
3615                 ap->state = ANEG_STATE_IDLE_DETECT;
3616                 ret = ANEG_TIMER_ENAB;
3617                 break;
3618
3619         case ANEG_STATE_IDLE_DETECT:
3620                 if (ap->ability_match != 0 &&
3621                     ap->rxconfig == 0) {
3622                         ap->state = ANEG_STATE_AN_ENABLE;
3623                         break;
3624                 }
3625                 delta = ap->cur_time - ap->link_time;
3626                 if (delta > ANEG_STATE_SETTLE_TIME) {
3627                         /* XXX another gem from the Broadcom driver :( */
3628                         ap->state = ANEG_STATE_LINK_OK;
3629                 }
3630                 break;
3631
3632         case ANEG_STATE_LINK_OK:
3633                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3634                 ret = ANEG_DONE;
3635                 break;
3636
3637         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3638                 /* ??? unimplemented */
3639                 break;
3640
3641         case ANEG_STATE_NEXT_PAGE_WAIT:
3642                 /* ??? unimplemented */
3643                 break;
3644
3645         default:
3646                 ret = ANEG_FAILED;
3647                 break;
3648         }
3649
3650         return ret;
3651 }
3652
3653 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3654 {
3655         int res = 0;
3656         struct tg3_fiber_aneginfo aninfo;
3657         int status = ANEG_FAILED;
3658         unsigned int tick;
3659         u32 tmp;
3660
3661         tw32_f(MAC_TX_AUTO_NEG, 0);
3662
3663         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3664         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3665         udelay(40);
3666
3667         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3668         udelay(40);
3669
3670         memset(&aninfo, 0, sizeof(aninfo));
3671         aninfo.flags |= MR_AN_ENABLE;
3672         aninfo.state = ANEG_STATE_UNKNOWN;
3673         aninfo.cur_time = 0;
3674         tick = 0;
3675         while (++tick < 195000) {
3676                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3677                 if (status == ANEG_DONE || status == ANEG_FAILED)
3678                         break;
3679
3680                 udelay(1);
3681         }
3682
3683         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3684         tw32_f(MAC_MODE, tp->mac_mode);
3685         udelay(40);
3686
3687         *txflags = aninfo.txconfig;
3688         *rxflags = aninfo.flags;
3689
3690         if (status == ANEG_DONE &&
3691             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3692                              MR_LP_ADV_FULL_DUPLEX)))
3693                 res = 1;
3694
3695         return res;
3696 }
3697
3698 static void tg3_init_bcm8002(struct tg3 *tp)
3699 {
3700         u32 mac_status = tr32(MAC_STATUS);
3701         int i;
3702
3703         /* Reset when initting first time or we have a link. */
3704         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3705             !(mac_status & MAC_STATUS_PCS_SYNCED))
3706                 return;
3707
3708         /* Set PLL lock range. */
3709         tg3_writephy(tp, 0x16, 0x8007);
3710
3711         /* SW reset */
3712         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3713
3714         /* Wait for reset to complete. */
3715         /* XXX schedule_timeout() ... */
3716         for (i = 0; i < 500; i++)
3717                 udelay(10);
3718
3719         /* Config mode; select PMA/Ch 1 regs. */
3720         tg3_writephy(tp, 0x10, 0x8411);
3721
3722         /* Enable auto-lock and comdet, select txclk for tx. */
3723         tg3_writephy(tp, 0x11, 0x0a10);
3724
3725         tg3_writephy(tp, 0x18, 0x00a0);
3726         tg3_writephy(tp, 0x16, 0x41ff);
3727
3728         /* Assert and deassert POR. */
3729         tg3_writephy(tp, 0x13, 0x0400);
3730         udelay(40);
3731         tg3_writephy(tp, 0x13, 0x0000);
3732
3733         tg3_writephy(tp, 0x11, 0x0a50);
3734         udelay(40);
3735         tg3_writephy(tp, 0x11, 0x0a10);
3736
3737         /* Wait for signal to stabilize */
3738         /* XXX schedule_timeout() ... */
3739         for (i = 0; i < 15000; i++)
3740                 udelay(10);
3741
3742         /* Deselect the channel register so we can read the PHYID
3743          * later.
3744          */
3745         tg3_writephy(tp, 0x10, 0x8011);
3746 }
3747
3748 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3749 {
3750         u16 flowctrl;
3751         u32 sg_dig_ctrl, sg_dig_status;
3752         u32 serdes_cfg, expected_sg_dig_ctrl;
3753         int workaround, port_a;
3754         int current_link_up;
3755
3756         serdes_cfg = 0;
3757         expected_sg_dig_ctrl = 0;
3758         workaround = 0;
3759         port_a = 1;
3760         current_link_up = 0;
3761
3762         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3763             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3764                 workaround = 1;
3765                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3766                         port_a = 0;
3767
3768                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3769                 /* preserve bits 20-23 for voltage regulator */
3770                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3771         }
3772
3773         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3774
3775         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3776                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3777                         if (workaround) {
3778                                 u32 val = serdes_cfg;
3779
3780                                 if (port_a)
3781                                         val |= 0xc010000;
3782                                 else
3783                                         val |= 0x4010000;
3784                                 tw32_f(MAC_SERDES_CFG, val);
3785                         }
3786
3787                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3788                 }
3789                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3790                         tg3_setup_flow_control(tp, 0, 0);
3791                         current_link_up = 1;
3792                 }
3793                 goto out;
3794         }
3795
3796         /* Want auto-negotiation.  */
3797         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3798
3799         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3800         if (flowctrl & ADVERTISE_1000XPAUSE)
3801                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3802         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3803                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3804
3805         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3806                 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3807                     tp->serdes_counter &&
3808                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3809                                     MAC_STATUS_RCVD_CFG)) ==
3810                      MAC_STATUS_PCS_SYNCED)) {
3811                         tp->serdes_counter--;
3812                         current_link_up = 1;
3813                         goto out;
3814                 }
3815 restart_autoneg:
3816                 if (workaround)
3817                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3818                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3819                 udelay(5);
3820                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3821
3822                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3823                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3824         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3825                                  MAC_STATUS_SIGNAL_DET)) {
3826                 sg_dig_status = tr32(SG_DIG_STATUS);
3827                 mac_status = tr32(MAC_STATUS);
3828
3829                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3830                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3831                         u32 local_adv = 0, remote_adv = 0;
3832
3833                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3834                                 local_adv |= ADVERTISE_1000XPAUSE;
3835                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3836                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3837
3838                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3839                                 remote_adv |= LPA_1000XPAUSE;
3840                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3841                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3842
3843                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3844                         current_link_up = 1;
3845                         tp->serdes_counter = 0;
3846                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3847                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3848                         if (tp->serdes_counter)
3849                                 tp->serdes_counter--;
3850                         else {
3851                                 if (workaround) {
3852                                         u32 val = serdes_cfg;
3853
3854                                         if (port_a)
3855                                                 val |= 0xc010000;
3856                                         else
3857                                                 val |= 0x4010000;
3858
3859                                         tw32_f(MAC_SERDES_CFG, val);
3860                                 }
3861
3862                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3863                                 udelay(40);
3864
3865                                 /* Link parallel detection - link is up */
3866                                 /* only if we have PCS_SYNC and not */
3867                                 /* receiving config code words */
3868                                 mac_status = tr32(MAC_STATUS);
3869                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3870                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3871                                         tg3_setup_flow_control(tp, 0, 0);
3872                                         current_link_up = 1;
3873                                         tp->phy_flags |=
3874                                                 TG3_PHYFLG_PARALLEL_DETECT;
3875                                         tp->serdes_counter =
3876                                                 SERDES_PARALLEL_DET_TIMEOUT;
3877                                 } else
3878                                         goto restart_autoneg;
3879                         }
3880                 }
3881         } else {
3882                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3883                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3884         }
3885
3886 out:
3887         return current_link_up;
3888 }
3889
3890 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3891 {
3892         int current_link_up = 0;
3893
3894         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3895                 goto out;
3896
3897         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3898                 u32 txflags, rxflags;
3899                 int i;
3900
3901                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3902                         u32 local_adv = 0, remote_adv = 0;
3903
3904                         if (txflags & ANEG_CFG_PS1)
3905                                 local_adv |= ADVERTISE_1000XPAUSE;
3906                         if (txflags & ANEG_CFG_PS2)
3907                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3908
3909                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3910                                 remote_adv |= LPA_1000XPAUSE;
3911                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3912                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3913
3914                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3915
3916                         current_link_up = 1;
3917                 }
3918                 for (i = 0; i < 30; i++) {
3919                         udelay(20);
3920                         tw32_f(MAC_STATUS,
3921                                (MAC_STATUS_SYNC_CHANGED |
3922                                 MAC_STATUS_CFG_CHANGED));
3923                         udelay(40);
3924                         if ((tr32(MAC_STATUS) &
3925                              (MAC_STATUS_SYNC_CHANGED |
3926                               MAC_STATUS_CFG_CHANGED)) == 0)
3927                                 break;
3928                 }
3929
3930                 mac_status = tr32(MAC_STATUS);
3931                 if (current_link_up == 0 &&
3932                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3933                     !(mac_status & MAC_STATUS_RCVD_CFG))
3934                         current_link_up = 1;
3935         } else {
3936                 tg3_setup_flow_control(tp, 0, 0);
3937
3938                 /* Forcing 1000FD link up. */
3939                 current_link_up = 1;
3940
3941                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3942                 udelay(40);
3943
3944                 tw32_f(MAC_MODE, tp->mac_mode);
3945                 udelay(40);
3946         }
3947
3948 out:
3949         return current_link_up;
3950 }
3951
3952 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3953 {
3954         u32 orig_pause_cfg;
3955         u16 orig_active_speed;
3956         u8 orig_active_duplex;
3957         u32 mac_status;
3958         int current_link_up;
3959         int i;
3960
3961         orig_pause_cfg = tp->link_config.active_flowctrl;
3962         orig_active_speed = tp->link_config.active_speed;
3963         orig_active_duplex = tp->link_config.active_duplex;
3964
3965         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3966             netif_carrier_ok(tp->dev) &&
3967             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3968                 mac_status = tr32(MAC_STATUS);
3969                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3970                                MAC_STATUS_SIGNAL_DET |
3971                                MAC_STATUS_CFG_CHANGED |
3972                                MAC_STATUS_RCVD_CFG);
3973                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3974                                    MAC_STATUS_SIGNAL_DET)) {
3975                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3976                                             MAC_STATUS_CFG_CHANGED));
3977                         return 0;
3978                 }
3979         }
3980
3981         tw32_f(MAC_TX_AUTO_NEG, 0);
3982
3983         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3984         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3985         tw32_f(MAC_MODE, tp->mac_mode);
3986         udelay(40);
3987
3988         if (tp->phy_id == TG3_PHY_ID_BCM8002)
3989                 tg3_init_bcm8002(tp);
3990
3991         /* Enable link change event even when serdes polling.  */
3992         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3993         udelay(40);
3994
3995         current_link_up = 0;
3996         mac_status = tr32(MAC_STATUS);
3997
3998         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3999                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4000         else
4001                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4002
4003         tp->napi[0].hw_status->status =
4004                 (SD_STATUS_UPDATED |
4005                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4006
4007         for (i = 0; i < 100; i++) {
4008                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4009                                     MAC_STATUS_CFG_CHANGED));
4010                 udelay(5);
4011                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4012                                          MAC_STATUS_CFG_CHANGED |
4013                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4014                         break;
4015         }
4016
4017         mac_status = tr32(MAC_STATUS);
4018         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4019                 current_link_up = 0;
4020                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4021                     tp->serdes_counter == 0) {
4022                         tw32_f(MAC_MODE, (tp->mac_mode |
4023                                           MAC_MODE_SEND_CONFIGS));
4024                         udelay(1);
4025                         tw32_f(MAC_MODE, tp->mac_mode);
4026                 }
4027         }
4028
4029         if (current_link_up == 1) {
4030                 tp->link_config.active_speed = SPEED_1000;
4031                 tp->link_config.active_duplex = DUPLEX_FULL;
4032                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4033                                     LED_CTRL_LNKLED_OVERRIDE |
4034                                     LED_CTRL_1000MBPS_ON));
4035         } else {
4036                 tp->link_config.active_speed = SPEED_INVALID;
4037                 tp->link_config.active_duplex = DUPLEX_INVALID;
4038                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4039                                     LED_CTRL_LNKLED_OVERRIDE |
4040                                     LED_CTRL_TRAFFIC_OVERRIDE));
4041         }
4042
4043         if (current_link_up != netif_carrier_ok(tp->dev)) {
4044                 if (current_link_up)
4045                         netif_carrier_on(tp->dev);
4046                 else
4047                         netif_carrier_off(tp->dev);
4048                 tg3_link_report(tp);
4049         } else {
4050                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4051                 if (orig_pause_cfg != now_pause_cfg ||
4052                     orig_active_speed != tp->link_config.active_speed ||
4053                     orig_active_duplex != tp->link_config.active_duplex)
4054                         tg3_link_report(tp);
4055         }
4056
4057         return 0;
4058 }
4059
4060 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4061 {
4062         int current_link_up, err = 0;
4063         u32 bmsr, bmcr;
4064         u16 current_speed;
4065         u8 current_duplex;
4066         u32 local_adv, remote_adv;
4067
4068         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4069         tw32_f(MAC_MODE, tp->mac_mode);
4070         udelay(40);
4071
4072         tw32(MAC_EVENT, 0);
4073
4074         tw32_f(MAC_STATUS,
4075              (MAC_STATUS_SYNC_CHANGED |
4076               MAC_STATUS_CFG_CHANGED |
4077               MAC_STATUS_MI_COMPLETION |
4078               MAC_STATUS_LNKSTATE_CHANGED));
4079         udelay(40);
4080
4081         if (force_reset)
4082                 tg3_phy_reset(tp);
4083
4084         current_link_up = 0;
4085         current_speed = SPEED_INVALID;
4086         current_duplex = DUPLEX_INVALID;
4087
4088         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4089         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4090         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4091                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4092                         bmsr |= BMSR_LSTATUS;
4093                 else
4094                         bmsr &= ~BMSR_LSTATUS;
4095         }
4096
4097         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4098
4099         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4100             (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4101                 /* do nothing, just check for link up at the end */
4102         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4103                 u32 adv, new_adv;
4104
4105                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4106                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4107                                   ADVERTISE_1000XPAUSE |
4108                                   ADVERTISE_1000XPSE_ASYM |
4109                                   ADVERTISE_SLCT);
4110
4111                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4112
4113                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4114                         new_adv |= ADVERTISE_1000XHALF;
4115                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4116                         new_adv |= ADVERTISE_1000XFULL;
4117
4118                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4119                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4120                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4121                         tg3_writephy(tp, MII_BMCR, bmcr);
4122
4123                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4124                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4125                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4126
4127                         return err;
4128                 }
4129         } else {
4130                 u32 new_bmcr;
4131
4132                 bmcr &= ~BMCR_SPEED1000;
4133                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4134
4135                 if (tp->link_config.duplex == DUPLEX_FULL)
4136                         new_bmcr |= BMCR_FULLDPLX;
4137
4138                 if (new_bmcr != bmcr) {
4139                         /* BMCR_SPEED1000 is a reserved bit that needs
4140                          * to be set on write.
4141                          */
4142                         new_bmcr |= BMCR_SPEED1000;
4143
4144                         /* Force a linkdown */
4145                         if (netif_carrier_ok(tp->dev)) {
4146                                 u32 adv;
4147
4148                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4149                                 adv &= ~(ADVERTISE_1000XFULL |
4150                                          ADVERTISE_1000XHALF |
4151                                          ADVERTISE_SLCT);
4152                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4153                                 tg3_writephy(tp, MII_BMCR, bmcr |
4154                                                            BMCR_ANRESTART |
4155                                                            BMCR_ANENABLE);
4156                                 udelay(10);
4157                                 netif_carrier_off(tp->dev);
4158                         }
4159                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4160                         bmcr = new_bmcr;
4161                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4162                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4163                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4164                             ASIC_REV_5714) {
4165                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4166                                         bmsr |= BMSR_LSTATUS;
4167                                 else
4168                                         bmsr &= ~BMSR_LSTATUS;
4169                         }
4170                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4171                 }
4172         }
4173
4174         if (bmsr & BMSR_LSTATUS) {
4175                 current_speed = SPEED_1000;
4176                 current_link_up = 1;
4177                 if (bmcr & BMCR_FULLDPLX)
4178                         current_duplex = DUPLEX_FULL;
4179                 else
4180                         current_duplex = DUPLEX_HALF;
4181
4182                 local_adv = 0;
4183                 remote_adv = 0;
4184
4185                 if (bmcr & BMCR_ANENABLE) {
4186                         u32 common;
4187
4188                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4189                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4190                         common = local_adv & remote_adv;
4191                         if (common & (ADVERTISE_1000XHALF |
4192                                       ADVERTISE_1000XFULL)) {
4193                                 if (common & ADVERTISE_1000XFULL)
4194                                         current_duplex = DUPLEX_FULL;
4195                                 else
4196                                         current_duplex = DUPLEX_HALF;
4197                         } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4198                                 /* Link is up via parallel detect */
4199                         } else {
4200                                 current_link_up = 0;
4201                         }
4202                 }
4203         }
4204
4205         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4206                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4207
4208         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4209         if (tp->link_config.active_duplex == DUPLEX_HALF)
4210                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4211
4212         tw32_f(MAC_MODE, tp->mac_mode);
4213         udelay(40);
4214
4215         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4216
4217         tp->link_config.active_speed = current_speed;
4218         tp->link_config.active_duplex = current_duplex;
4219
4220         if (current_link_up != netif_carrier_ok(tp->dev)) {
4221                 if (current_link_up)
4222                         netif_carrier_on(tp->dev);
4223                 else {
4224                         netif_carrier_off(tp->dev);
4225                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4226                 }
4227                 tg3_link_report(tp);
4228         }
4229         return err;
4230 }
4231
4232 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4233 {
4234         if (tp->serdes_counter) {
4235                 /* Give autoneg time to complete. */
4236                 tp->serdes_counter--;
4237                 return;
4238         }
4239
4240         if (!netif_carrier_ok(tp->dev) &&
4241             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4242                 u32 bmcr;
4243
4244                 tg3_readphy(tp, MII_BMCR, &bmcr);
4245                 if (bmcr & BMCR_ANENABLE) {
4246                         u32 phy1, phy2;
4247
4248                         /* Select shadow register 0x1f */
4249                         tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4250                         tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4251
4252                         /* Select expansion interrupt status register */
4253                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4254                                          MII_TG3_DSP_EXP1_INT_STAT);
4255                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4256                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4257
4258                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4259                                 /* We have signal detect and not receiving
4260                                  * config code words, link is up by parallel
4261                                  * detection.
4262                                  */
4263
4264                                 bmcr &= ~BMCR_ANENABLE;
4265                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4266                                 tg3_writephy(tp, MII_BMCR, bmcr);
4267                                 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4268                         }
4269                 }
4270         } else if (netif_carrier_ok(tp->dev) &&
4271                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4272                    (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4273                 u32 phy2;
4274
4275                 /* Select expansion interrupt status register */
4276                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4277                                  MII_TG3_DSP_EXP1_INT_STAT);
4278                 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4279                 if (phy2 & 0x20) {
4280                         u32 bmcr;
4281
4282                         /* Config code words received, turn on autoneg. */
4283                         tg3_readphy(tp, MII_BMCR, &bmcr);
4284                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4285
4286                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4287
4288                 }
4289         }
4290 }
4291
4292 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4293 {
4294         int err;
4295
4296         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4297                 err = tg3_setup_fiber_phy(tp, force_reset);
4298         else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4299                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4300         else
4301                 err = tg3_setup_copper_phy(tp, force_reset);
4302
4303         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4304                 u32 val, scale;
4305
4306                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4307                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4308                         scale = 65;
4309                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4310                         scale = 6;
4311                 else
4312                         scale = 12;
4313
4314                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4315                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4316                 tw32(GRC_MISC_CFG, val);
4317         }
4318
4319         if (tp->link_config.active_speed == SPEED_1000 &&
4320             tp->link_config.active_duplex == DUPLEX_HALF)
4321                 tw32(MAC_TX_LENGTHS,
4322                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4323                       (6 << TX_LENGTHS_IPG_SHIFT) |
4324                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4325         else
4326                 tw32(MAC_TX_LENGTHS,
4327                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4328                       (6 << TX_LENGTHS_IPG_SHIFT) |
4329                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4330
4331         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4332                 if (netif_carrier_ok(tp->dev)) {
4333                         tw32(HOSTCC_STAT_COAL_TICKS,
4334                              tp->coal.stats_block_coalesce_usecs);
4335                 } else {
4336                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4337                 }
4338         }
4339
4340         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4341                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4342                 if (!netif_carrier_ok(tp->dev))
4343                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4344                               tp->pwrmgmt_thresh;
4345                 else
4346                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4347                 tw32(PCIE_PWR_MGMT_THRESH, val);
4348         }
4349
4350         return err;
4351 }
4352
4353 static inline int tg3_irq_sync(struct tg3 *tp)
4354 {
4355         return tp->irq_sync;
4356 }
4357
4358 /* This is called whenever we suspect that the system chipset is re-
4359  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4360  * is bogus tx completions. We try to recover by setting the
4361  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4362  * in the workqueue.
4363  */
4364 static void tg3_tx_recover(struct tg3 *tp)
4365 {
4366         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4367                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4368
4369         netdev_warn(tp->dev,
4370                     "The system may be re-ordering memory-mapped I/O "
4371                     "cycles to the network device, attempting to recover. "
4372                     "Please report the problem to the driver maintainer "
4373                     "and include system chipset information.\n");
4374
4375         spin_lock(&tp->lock);
4376         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4377         spin_unlock(&tp->lock);
4378 }
4379
4380 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4381 {
4382         /* Tell compiler to fetch tx indices from memory. */
4383         barrier();
4384         return tnapi->tx_pending -
4385                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4386 }
4387
4388 /* Tigon3 never reports partial packet sends.  So we do not
4389  * need special logic to handle SKBs that have not had all
4390  * of their frags sent yet, like SunGEM does.
4391  */
4392 static void tg3_tx(struct tg3_napi *tnapi)
4393 {
4394         struct tg3 *tp = tnapi->tp;
4395         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4396         u32 sw_idx = tnapi->tx_cons;
4397         struct netdev_queue *txq;
4398         int index = tnapi - tp->napi;
4399
4400         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4401                 index--;
4402
4403         txq = netdev_get_tx_queue(tp->dev, index);
4404
4405         while (sw_idx != hw_idx) {
4406                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4407                 struct sk_buff *skb = ri->skb;
4408                 int i, tx_bug = 0;
4409
4410                 if (unlikely(skb == NULL)) {
4411                         tg3_tx_recover(tp);
4412                         return;
4413                 }
4414
4415                 pci_unmap_single(tp->pdev,
4416                                  dma_unmap_addr(ri, mapping),
4417                                  skb_headlen(skb),
4418                                  PCI_DMA_TODEVICE);
4419
4420                 ri->skb = NULL;
4421
4422                 sw_idx = NEXT_TX(sw_idx);
4423
4424                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4425                         ri = &tnapi->tx_buffers[sw_idx];
4426                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4427                                 tx_bug = 1;
4428
4429                         pci_unmap_page(tp->pdev,
4430                                        dma_unmap_addr(ri, mapping),
4431                                        skb_shinfo(skb)->frags[i].size,
4432                                        PCI_DMA_TODEVICE);
4433                         sw_idx = NEXT_TX(sw_idx);
4434                 }
4435
4436                 dev_kfree_skb(skb);
4437
4438                 if (unlikely(tx_bug)) {
4439                         tg3_tx_recover(tp);
4440                         return;
4441                 }
4442         }
4443
4444         tnapi->tx_cons = sw_idx;
4445
4446         /* Need to make the tx_cons update visible to tg3_start_xmit()
4447          * before checking for netif_queue_stopped().  Without the
4448          * memory barrier, there is a small possibility that tg3_start_xmit()
4449          * will miss it and cause the queue to be stopped forever.
4450          */
4451         smp_mb();
4452
4453         if (unlikely(netif_tx_queue_stopped(txq) &&
4454                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4455                 __netif_tx_lock(txq, smp_processor_id());
4456                 if (netif_tx_queue_stopped(txq) &&
4457                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4458                         netif_tx_wake_queue(txq);
4459                 __netif_tx_unlock(txq);
4460         }
4461 }
4462
4463 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4464 {
4465         if (!ri->skb)
4466                 return;
4467
4468         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4469                          map_sz, PCI_DMA_FROMDEVICE);
4470         dev_kfree_skb_any(ri->skb);
4471         ri->skb = NULL;
4472 }
4473
4474 /* Returns size of skb allocated or < 0 on error.
4475  *
4476  * We only need to fill in the address because the other members
4477  * of the RX descriptor are invariant, see tg3_init_rings.
4478  *
4479  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4480  * posting buffers we only dirty the first cache line of the RX
4481  * descriptor (containing the address).  Whereas for the RX status
4482  * buffers the cpu only reads the last cacheline of the RX descriptor
4483  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4484  */
4485 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4486                             u32 opaque_key, u32 dest_idx_unmasked)
4487 {
4488         struct tg3_rx_buffer_desc *desc;
4489         struct ring_info *map, *src_map;
4490         struct sk_buff *skb;
4491         dma_addr_t mapping;
4492         int skb_size, dest_idx;
4493
4494         src_map = NULL;
4495         switch (opaque_key) {
4496         case RXD_OPAQUE_RING_STD:
4497                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4498                 desc = &tpr->rx_std[dest_idx];
4499                 map = &tpr->rx_std_buffers[dest_idx];
4500                 skb_size = tp->rx_pkt_map_sz;
4501                 break;
4502
4503         case RXD_OPAQUE_RING_JUMBO:
4504                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4505                 desc = &tpr->rx_jmb[dest_idx].std;
4506                 map = &tpr->rx_jmb_buffers[dest_idx];
4507                 skb_size = TG3_RX_JMB_MAP_SZ;
4508                 break;
4509
4510         default:
4511                 return -EINVAL;
4512         }
4513
4514         /* Do not overwrite any of the map or rp information
4515          * until we are sure we can commit to a new buffer.
4516          *
4517          * Callers depend upon this behavior and assume that
4518          * we leave everything unchanged if we fail.
4519          */
4520         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4521         if (skb == NULL)
4522                 return -ENOMEM;
4523
4524         skb_reserve(skb, tp->rx_offset);
4525
4526         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4527                                  PCI_DMA_FROMDEVICE);
4528         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4529                 dev_kfree_skb(skb);
4530                 return -EIO;
4531         }
4532
4533         map->skb = skb;
4534         dma_unmap_addr_set(map, mapping, mapping);
4535
4536         desc->addr_hi = ((u64)mapping >> 32);
4537         desc->addr_lo = ((u64)mapping & 0xffffffff);
4538
4539         return skb_size;
4540 }
4541
4542 /* We only need to move over in the address because the other
4543  * members of the RX descriptor are invariant.  See notes above
4544  * tg3_alloc_rx_skb for full details.
4545  */
4546 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4547                            struct tg3_rx_prodring_set *dpr,
4548                            u32 opaque_key, int src_idx,
4549                            u32 dest_idx_unmasked)
4550 {
4551         struct tg3 *tp = tnapi->tp;
4552         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4553         struct ring_info *src_map, *dest_map;
4554         struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
4555         int dest_idx;
4556
4557         switch (opaque_key) {
4558         case RXD_OPAQUE_RING_STD:
4559                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4560                 dest_desc = &dpr->rx_std[dest_idx];
4561                 dest_map = &dpr->rx_std_buffers[dest_idx];
4562                 src_desc = &spr->rx_std[src_idx];
4563                 src_map = &spr->rx_std_buffers[src_idx];
4564                 break;
4565
4566         case RXD_OPAQUE_RING_JUMBO:
4567                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4568                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4569                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4570                 src_desc = &spr->rx_jmb[src_idx].std;
4571                 src_map = &spr->rx_jmb_buffers[src_idx];
4572                 break;
4573
4574         default:
4575                 return;
4576         }
4577
4578         dest_map->skb = src_map->skb;
4579         dma_unmap_addr_set(dest_map, mapping,
4580                            dma_unmap_addr(src_map, mapping));
4581         dest_desc->addr_hi = src_desc->addr_hi;
4582         dest_desc->addr_lo = src_desc->addr_lo;
4583
4584         /* Ensure that the update to the skb happens after the physical
4585          * addresses have been transferred to the new BD location.
4586          */
4587         smp_wmb();
4588
4589         src_map->skb = NULL;
4590 }
4591
4592 /* The RX ring scheme is composed of multiple rings which post fresh
4593  * buffers to the chip, and one special ring the chip uses to report
4594  * status back to the host.
4595  *
4596  * The special ring reports the status of received packets to the
4597  * host.  The chip does not write into the original descriptor the
4598  * RX buffer was obtained from.  The chip simply takes the original
4599  * descriptor as provided by the host, updates the status and length
4600  * field, then writes this into the next status ring entry.
4601  *
4602  * Each ring the host uses to post buffers to the chip is described
4603  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4604  * it is first placed into the on-chip ram.  When the packet's length
4605  * is known, it walks down the TG3_BDINFO entries to select the ring.
4606  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4607  * which is within the range of the new packet's length is chosen.
4608  *
4609  * The "separate ring for rx status" scheme may sound queer, but it makes
4610  * sense from a cache coherency perspective.  If only the host writes
4611  * to the buffer post rings, and only the chip writes to the rx status
4612  * rings, then cache lines never move beyond shared-modified state.
4613  * If both the host and chip were to write into the same ring, cache line
4614  * eviction could occur since both entities want it in an exclusive state.
4615  */
4616 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4617 {
4618         struct tg3 *tp = tnapi->tp;
4619         u32 work_mask, rx_std_posted = 0;
4620         u32 std_prod_idx, jmb_prod_idx;
4621         u32 sw_idx = tnapi->rx_rcb_ptr;
4622         u16 hw_idx;
4623         int received;
4624         struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
4625
4626         hw_idx = *(tnapi->rx_rcb_prod_idx);
4627         /*
4628          * We need to order the read of hw_idx and the read of
4629          * the opaque cookie.
4630          */
4631         rmb();
4632         work_mask = 0;
4633         received = 0;
4634         std_prod_idx = tpr->rx_std_prod_idx;
4635         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4636         while (sw_idx != hw_idx && budget > 0) {
4637                 struct ring_info *ri;
4638                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4639                 unsigned int len;
4640                 struct sk_buff *skb;
4641                 dma_addr_t dma_addr;
4642                 u32 opaque_key, desc_idx, *post_ptr;
4643                 bool hw_vlan __maybe_unused = false;
4644                 u16 vtag __maybe_unused = 0;
4645
4646                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4647                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4648                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4649                         ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4650                         dma_addr = dma_unmap_addr(ri, mapping);
4651                         skb = ri->skb;
4652                         post_ptr = &std_prod_idx;
4653                         rx_std_posted++;
4654                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4655                         ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4656                         dma_addr = dma_unmap_addr(ri, mapping);
4657                         skb = ri->skb;
4658                         post_ptr = &jmb_prod_idx;
4659                 } else
4660                         goto next_pkt_nopost;
4661
4662                 work_mask |= opaque_key;
4663
4664                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4665                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4666                 drop_it:
4667                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4668                                        desc_idx, *post_ptr);
4669                 drop_it_no_recycle:
4670                         /* Other statistics kept track of by card. */
4671                         tp->net_stats.rx_dropped++;
4672                         goto next_pkt;
4673                 }
4674
4675                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4676                       ETH_FCS_LEN;
4677
4678                 if (len > TG3_RX_COPY_THRESH(tp)) {
4679                         int skb_size;
4680
4681                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4682                                                     *post_ptr);
4683                         if (skb_size < 0)
4684                                 goto drop_it;
4685
4686                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4687                                          PCI_DMA_FROMDEVICE);
4688
4689                         /* Ensure that the update to the skb happens
4690                          * after the usage of the old DMA mapping.
4691                          */
4692                         smp_wmb();
4693
4694                         ri->skb = NULL;
4695
4696                         skb_put(skb, len);
4697                 } else {
4698                         struct sk_buff *copy_skb;
4699
4700                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4701                                        desc_idx, *post_ptr);
4702
4703                         copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
4704                                                     TG3_RAW_IP_ALIGN);
4705                         if (copy_skb == NULL)
4706                                 goto drop_it_no_recycle;
4707
4708                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
4709                         skb_put(copy_skb, len);
4710                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4711                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4712                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4713
4714                         /* We'll reuse the original ring buffer. */
4715                         skb = copy_skb;
4716                 }
4717
4718                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4719                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4720                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4721                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4722                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4723                 else
4724                         skb_checksum_none_assert(skb);
4725
4726                 skb->protocol = eth_type_trans(skb, tp->dev);
4727
4728                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4729                     skb->protocol != htons(ETH_P_8021Q)) {
4730                         dev_kfree_skb(skb);
4731                         goto next_pkt;
4732                 }
4733
4734                 if (desc->type_flags & RXD_FLAG_VLAN &&
4735                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
4736                         vtag = desc->err_vlan & RXD_VLAN_MASK;
4737 #if TG3_VLAN_TAG_USED
4738                         if (tp->vlgrp)
4739                                 hw_vlan = true;
4740                         else
4741 #endif
4742                         {
4743                                 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
4744                                                     __skb_push(skb, VLAN_HLEN);
4745
4746                                 memmove(ve, skb->data + VLAN_HLEN,
4747                                         ETH_ALEN * 2);
4748                                 ve->h_vlan_proto = htons(ETH_P_8021Q);
4749                                 ve->h_vlan_TCI = htons(vtag);
4750                         }
4751                 }
4752
4753 #if TG3_VLAN_TAG_USED
4754                 if (hw_vlan)
4755                         vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
4756                 else
4757 #endif
4758                         napi_gro_receive(&tnapi->napi, skb);
4759
4760                 received++;
4761                 budget--;
4762
4763 next_pkt:
4764                 (*post_ptr)++;
4765
4766                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4767                         tpr->rx_std_prod_idx = std_prod_idx &
4768                                                tp->rx_std_ring_mask;
4769                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4770                                      tpr->rx_std_prod_idx);
4771                         work_mask &= ~RXD_OPAQUE_RING_STD;
4772                         rx_std_posted = 0;
4773                 }
4774 next_pkt_nopost:
4775                 sw_idx++;
4776                 sw_idx &= tp->rx_ret_ring_mask;
4777
4778                 /* Refresh hw_idx to see if there is new work */
4779                 if (sw_idx == hw_idx) {
4780                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4781                         rmb();
4782                 }
4783         }
4784
4785         /* ACK the status ring. */
4786         tnapi->rx_rcb_ptr = sw_idx;
4787         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4788
4789         /* Refill RX ring(s). */
4790         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4791                 if (work_mask & RXD_OPAQUE_RING_STD) {
4792                         tpr->rx_std_prod_idx = std_prod_idx &
4793                                                tp->rx_std_ring_mask;
4794                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4795                                      tpr->rx_std_prod_idx);
4796                 }
4797                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4798                         tpr->rx_jmb_prod_idx = jmb_prod_idx &
4799                                                tp->rx_jmb_ring_mask;
4800                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4801                                      tpr->rx_jmb_prod_idx);
4802                 }
4803                 mmiowb();
4804         } else if (work_mask) {
4805                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4806                  * updated before the producer indices can be updated.
4807                  */
4808                 smp_wmb();
4809
4810                 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
4811                 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
4812
4813                 if (tnapi != &tp->napi[1])
4814                         napi_schedule(&tp->napi[1].napi);
4815         }
4816
4817         return received;
4818 }
4819
4820 static void tg3_poll_link(struct tg3 *tp)
4821 {
4822         /* handle link change and other phy events */
4823         if (!(tp->tg3_flags &
4824               (TG3_FLAG_USE_LINKCHG_REG |
4825                TG3_FLAG_POLL_SERDES))) {
4826                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4827
4828                 if (sblk->status & SD_STATUS_LINK_CHG) {
4829                         sblk->status = SD_STATUS_UPDATED |
4830                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4831                         spin_lock(&tp->lock);
4832                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4833                                 tw32_f(MAC_STATUS,
4834                                      (MAC_STATUS_SYNC_CHANGED |
4835                                       MAC_STATUS_CFG_CHANGED |
4836                                       MAC_STATUS_MI_COMPLETION |
4837                                       MAC_STATUS_LNKSTATE_CHANGED));
4838                                 udelay(40);
4839                         } else
4840                                 tg3_setup_phy(tp, 0);
4841                         spin_unlock(&tp->lock);
4842                 }
4843         }
4844 }
4845
4846 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4847                                 struct tg3_rx_prodring_set *dpr,
4848                                 struct tg3_rx_prodring_set *spr)
4849 {
4850         u32 si, di, cpycnt, src_prod_idx;
4851         int i, err = 0;
4852
4853         while (1) {
4854                 src_prod_idx = spr->rx_std_prod_idx;
4855
4856                 /* Make sure updates to the rx_std_buffers[] entries and the
4857                  * standard producer index are seen in the correct order.
4858                  */
4859                 smp_rmb();
4860
4861                 if (spr->rx_std_cons_idx == src_prod_idx)
4862                         break;
4863
4864                 if (spr->rx_std_cons_idx < src_prod_idx)
4865                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4866                 else
4867                         cpycnt = tp->rx_std_ring_mask + 1 -
4868                                  spr->rx_std_cons_idx;
4869
4870                 cpycnt = min(cpycnt,
4871                              tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
4872
4873                 si = spr->rx_std_cons_idx;
4874                 di = dpr->rx_std_prod_idx;
4875
4876                 for (i = di; i < di + cpycnt; i++) {
4877                         if (dpr->rx_std_buffers[i].skb) {
4878                                 cpycnt = i - di;
4879                                 err = -ENOSPC;
4880                                 break;
4881                         }
4882                 }
4883
4884                 if (!cpycnt)
4885                         break;
4886
4887                 /* Ensure that updates to the rx_std_buffers ring and the
4888                  * shadowed hardware producer ring from tg3_recycle_skb() are
4889                  * ordered correctly WRT the skb check above.
4890                  */
4891                 smp_rmb();
4892
4893                 memcpy(&dpr->rx_std_buffers[di],
4894                        &spr->rx_std_buffers[si],
4895                        cpycnt * sizeof(struct ring_info));
4896
4897                 for (i = 0; i < cpycnt; i++, di++, si++) {
4898                         struct tg3_rx_buffer_desc *sbd, *dbd;
4899                         sbd = &spr->rx_std[si];
4900                         dbd = &dpr->rx_std[di];
4901                         dbd->addr_hi = sbd->addr_hi;
4902                         dbd->addr_lo = sbd->addr_lo;
4903                 }
4904
4905                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
4906                                        tp->rx_std_ring_mask;
4907                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
4908                                        tp->rx_std_ring_mask;
4909         }
4910
4911         while (1) {
4912                 src_prod_idx = spr->rx_jmb_prod_idx;
4913
4914                 /* Make sure updates to the rx_jmb_buffers[] entries and
4915                  * the jumbo producer index are seen in the correct order.
4916                  */
4917                 smp_rmb();
4918
4919                 if (spr->rx_jmb_cons_idx == src_prod_idx)
4920                         break;
4921
4922                 if (spr->rx_jmb_cons_idx < src_prod_idx)
4923                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4924                 else
4925                         cpycnt = tp->rx_jmb_ring_mask + 1 -
4926                                  spr->rx_jmb_cons_idx;
4927
4928                 cpycnt = min(cpycnt,
4929                              tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
4930
4931                 si = spr->rx_jmb_cons_idx;
4932                 di = dpr->rx_jmb_prod_idx;
4933
4934                 for (i = di; i < di + cpycnt; i++) {
4935                         if (dpr->rx_jmb_buffers[i].skb) {
4936                                 cpycnt = i - di;
4937                                 err = -ENOSPC;
4938                                 break;
4939                         }
4940                 }
4941
4942                 if (!cpycnt)
4943                         break;
4944
4945                 /* Ensure that updates to the rx_jmb_buffers ring and the
4946                  * shadowed hardware producer ring from tg3_recycle_skb() are
4947                  * ordered correctly WRT the skb check above.
4948                  */
4949                 smp_rmb();
4950
4951                 memcpy(&dpr->rx_jmb_buffers[di],
4952                        &spr->rx_jmb_buffers[si],
4953                        cpycnt * sizeof(struct ring_info));
4954
4955                 for (i = 0; i < cpycnt; i++, di++, si++) {
4956                         struct tg3_rx_buffer_desc *sbd, *dbd;
4957                         sbd = &spr->rx_jmb[si].std;
4958                         dbd = &dpr->rx_jmb[di].std;
4959                         dbd->addr_hi = sbd->addr_hi;
4960                         dbd->addr_lo = sbd->addr_lo;
4961                 }
4962
4963                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
4964                                        tp->rx_jmb_ring_mask;
4965                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
4966                                        tp->rx_jmb_ring_mask;
4967         }
4968
4969         return err;
4970 }
4971
4972 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4973 {
4974         struct tg3 *tp = tnapi->tp;
4975
4976         /* run TX completion thread */
4977         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4978                 tg3_tx(tnapi);
4979                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4980                         return work_done;
4981         }
4982
4983         /* run RX thread, within the bounds set by NAPI.
4984          * All RX "locking" is done by ensuring outside
4985          * code synchronizes with tg3->napi.poll()
4986          */
4987         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4988                 work_done += tg3_rx(tnapi, budget - work_done);
4989
4990         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4991                 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
4992                 int i, err = 0;
4993                 u32 std_prod_idx = dpr->rx_std_prod_idx;
4994                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
4995
4996                 for (i = 1; i < tp->irq_cnt; i++)
4997                         err |= tg3_rx_prodring_xfer(tp, dpr,
4998                                                     &tp->napi[i].prodring);
4999
5000                 wmb();
5001
5002                 if (std_prod_idx != dpr->rx_std_prod_idx)
5003                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5004                                      dpr->rx_std_prod_idx);
5005
5006                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5007                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5008                                      dpr->rx_jmb_prod_idx);
5009
5010                 mmiowb();
5011
5012                 if (err)
5013                         tw32_f(HOSTCC_MODE, tp->coal_now);
5014         }
5015
5016         return work_done;
5017 }
5018
5019 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5020 {
5021         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5022         struct tg3 *tp = tnapi->tp;
5023         int work_done = 0;
5024         struct tg3_hw_status *sblk = tnapi->hw_status;
5025
5026         while (1) {
5027                 work_done = tg3_poll_work(tnapi, work_done, budget);
5028
5029                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5030                         goto tx_recovery;
5031
5032                 if (unlikely(work_done >= budget))
5033                         break;
5034
5035                 /* tp->last_tag is used in tg3_int_reenable() below
5036                  * to tell the hw how much work has been processed,
5037                  * so we must read it before checking for more work.
5038                  */
5039                 tnapi->last_tag = sblk->status_tag;
5040                 tnapi->last_irq_tag = tnapi->last_tag;
5041                 rmb();
5042
5043                 /* check for RX/TX work to do */
5044                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5045                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5046                         napi_complete(napi);
5047                         /* Reenable interrupts. */
5048                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5049                         mmiowb();
5050                         break;
5051                 }
5052         }
5053
5054         return work_done;
5055
5056 tx_recovery:
5057         /* work_done is guaranteed to be less than budget. */
5058         napi_complete(napi);
5059         schedule_work(&tp->reset_task);
5060         return work_done;
5061 }
5062
5063 static int tg3_poll(struct napi_struct *napi, int budget)
5064 {
5065         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5066         struct tg3 *tp = tnapi->tp;
5067         int work_done = 0;
5068         struct tg3_hw_status *sblk = tnapi->hw_status;
5069
5070         while (1) {
5071                 tg3_poll_link(tp);
5072
5073                 work_done = tg3_poll_work(tnapi, work_done, budget);
5074
5075                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5076                         goto tx_recovery;
5077
5078                 if (unlikely(work_done >= budget))
5079                         break;
5080
5081                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5082                         /* tp->last_tag is used in tg3_int_reenable() below
5083                          * to tell the hw how much work has been processed,
5084                          * so we must read it before checking for more work.
5085                          */
5086                         tnapi->last_tag = sblk->status_tag;
5087                         tnapi->last_irq_tag = tnapi->last_tag;
5088                         rmb();
5089                 } else
5090                         sblk->status &= ~SD_STATUS_UPDATED;
5091
5092                 if (likely(!tg3_has_work(tnapi))) {
5093                         napi_complete(napi);
5094                         tg3_int_reenable(tnapi);
5095                         break;
5096                 }
5097         }
5098
5099         return work_done;
5100
5101 tx_recovery:
5102         /* work_done is guaranteed to be less than budget. */
5103         napi_complete(napi);
5104         schedule_work(&tp->reset_task);
5105         return work_done;
5106 }
5107
5108 static void tg3_napi_disable(struct tg3 *tp)
5109 {
5110         int i;
5111
5112         for (i = tp->irq_cnt - 1; i >= 0; i--)
5113                 napi_disable(&tp->napi[i].napi);
5114 }
5115
5116 static void tg3_napi_enable(struct tg3 *tp)
5117 {
5118         int i;
5119
5120         for (i = 0; i < tp->irq_cnt; i++)
5121                 napi_enable(&tp->napi[i].napi);
5122 }
5123
5124 static void tg3_napi_init(struct tg3 *tp)
5125 {
5126         int i;
5127
5128         netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
5129         for (i = 1; i < tp->irq_cnt; i++)
5130                 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
5131 }
5132
5133 static void tg3_napi_fini(struct tg3 *tp)
5134 {
5135         int i;
5136
5137         for (i = 0; i < tp->irq_cnt; i++)
5138                 netif_napi_del(&tp->napi[i].napi);
5139 }
5140
5141 static inline void tg3_netif_stop(struct tg3 *tp)
5142 {
5143         tp->dev->trans_start = jiffies; /* prevent tx timeout */
5144         tg3_napi_disable(tp);
5145         netif_tx_disable(tp->dev);
5146 }
5147
5148 static inline void tg3_netif_start(struct tg3 *tp)
5149 {
5150         /* NOTE: unconditional netif_tx_wake_all_queues is only
5151          * appropriate so long as all callers are assured to
5152          * have free tx slots (such as after tg3_init_hw)
5153          */
5154         netif_tx_wake_all_queues(tp->dev);
5155
5156         tg3_napi_enable(tp);
5157         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
5158         tg3_enable_ints(tp);
5159 }
5160
5161 static void tg3_irq_quiesce(struct tg3 *tp)
5162 {
5163         int i;
5164
5165         BUG_ON(tp->irq_sync);
5166
5167         tp->irq_sync = 1;
5168         smp_mb();
5169
5170         for (i = 0; i < tp->irq_cnt; i++)
5171                 synchronize_irq(tp->napi[i].irq_vec);
5172 }
5173
5174 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5175  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5176  * with as well.  Most of the time, this is not necessary except when
5177  * shutting down the device.
5178  */
5179 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5180 {
5181         spin_lock_bh(&tp->lock);
5182         if (irq_sync)
5183                 tg3_irq_quiesce(tp);
5184 }
5185
5186 static inline void tg3_full_unlock(struct tg3 *tp)
5187 {
5188         spin_unlock_bh(&tp->lock);
5189 }
5190
5191 /* One-shot MSI handler - Chip automatically disables interrupt
5192  * after sending MSI so driver doesn't have to do it.
5193  */
5194 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5195 {
5196         struct tg3_napi *tnapi = dev_id;
5197         struct tg3 *tp = tnapi->tp;
5198
5199         prefetch(tnapi->hw_status);
5200         if (tnapi->rx_rcb)
5201                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5202
5203         if (likely(!tg3_irq_sync(tp)))
5204                 napi_schedule(&tnapi->napi);
5205
5206         return IRQ_HANDLED;
5207 }
5208
5209 /* MSI ISR - No need to check for interrupt sharing and no need to
5210  * flush status block and interrupt mailbox. PCI ordering rules
5211  * guarantee that MSI will arrive after the status block.
5212  */
5213 static irqreturn_t tg3_msi(int irq, void *dev_id)
5214 {
5215         struct tg3_napi *tnapi = dev_id;
5216         struct tg3 *tp = tnapi->tp;
5217
5218         prefetch(tnapi->hw_status);
5219         if (tnapi->rx_rcb)
5220                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5221         /*
5222          * Writing any value to intr-mbox-0 clears PCI INTA# and
5223          * chip-internal interrupt pending events.
5224          * Writing non-zero to intr-mbox-0 additional tells the
5225          * NIC to stop sending us irqs, engaging "in-intr-handler"
5226          * event coalescing.
5227          */
5228         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5229         if (likely(!tg3_irq_sync(tp)))
5230                 napi_schedule(&tnapi->napi);
5231
5232         return IRQ_RETVAL(1);
5233 }
5234
5235 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5236 {
5237         struct tg3_napi *tnapi = dev_id;
5238         struct tg3 *tp = tnapi->tp;
5239         struct tg3_hw_status *sblk = tnapi->hw_status;
5240         unsigned int handled = 1;
5241
5242         /* In INTx mode, it is possible for the interrupt to arrive at
5243          * the CPU before the status block posted prior to the interrupt.
5244          * Reading the PCI State register will confirm whether the
5245          * interrupt is ours and will flush the status block.
5246          */
5247         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5248                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5249                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5250                         handled = 0;
5251                         goto out;
5252                 }
5253         }
5254
5255         /*
5256          * Writing any value to intr-mbox-0 clears PCI INTA# and
5257          * chip-internal interrupt pending events.
5258          * Writing non-zero to intr-mbox-0 additional tells the
5259          * NIC to stop sending us irqs, engaging "in-intr-handler"
5260          * event coalescing.
5261          *
5262          * Flush the mailbox to de-assert the IRQ immediately to prevent
5263          * spurious interrupts.  The flush impacts performance but
5264          * excessive spurious interrupts can be worse in some cases.
5265          */
5266         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5267         if (tg3_irq_sync(tp))
5268                 goto out;
5269         sblk->status &= ~SD_STATUS_UPDATED;
5270         if (likely(tg3_has_work(tnapi))) {
5271                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5272                 napi_schedule(&tnapi->napi);
5273         } else {
5274                 /* No work, shared interrupt perhaps?  re-enable
5275                  * interrupts, and flush that PCI write
5276                  */
5277                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5278                                0x00000000);
5279         }
5280 out:
5281         return IRQ_RETVAL(handled);
5282 }
5283
5284 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5285 {
5286         struct tg3_napi *tnapi = dev_id;
5287         struct tg3 *tp = tnapi->tp;
5288         struct tg3_hw_status *sblk = tnapi->hw_status;
5289         unsigned int handled = 1;
5290
5291         /* In INTx mode, it is possible for the interrupt to arrive at
5292          * the CPU before the status block posted prior to the interrupt.
5293          * Reading the PCI State register will confirm whether the
5294          * interrupt is ours and will flush the status block.
5295          */
5296         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5297                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5298                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5299                         handled = 0;
5300                         goto out;
5301                 }
5302         }
5303
5304         /*
5305          * writing any value to intr-mbox-0 clears PCI INTA# and
5306          * chip-internal interrupt pending events.
5307          * writing non-zero to intr-mbox-0 additional tells the
5308          * NIC to stop sending us irqs, engaging "in-intr-handler"
5309          * event coalescing.
5310          *
5311          * Flush the mailbox to de-assert the IRQ immediately to prevent
5312          * spurious interrupts.  The flush impacts performance but
5313          * excessive spurious interrupts can be worse in some cases.
5314          */
5315         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5316
5317         /*
5318          * In a shared interrupt configuration, sometimes other devices'
5319          * interrupts will scream.  We record the current status tag here
5320          * so that the above check can report that the screaming interrupts
5321          * are unhandled.  Eventually they will be silenced.
5322          */
5323         tnapi->last_irq_tag = sblk->status_tag;
5324
5325         if (tg3_irq_sync(tp))
5326                 goto out;
5327
5328         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5329
5330         napi_schedule(&tnapi->napi);
5331
5332 out:
5333         return IRQ_RETVAL(handled);
5334 }
5335
5336 /* ISR for interrupt test */
5337 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5338 {
5339         struct tg3_napi *tnapi = dev_id;
5340         struct tg3 *tp = tnapi->tp;
5341         struct tg3_hw_status *sblk = tnapi->hw_status;
5342
5343         if ((sblk->status & SD_STATUS_UPDATED) ||
5344             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5345                 tg3_disable_ints(tp);
5346                 return IRQ_RETVAL(1);
5347         }
5348         return IRQ_RETVAL(0);
5349 }
5350
5351 static int tg3_init_hw(struct tg3 *, int);
5352 static int tg3_halt(struct tg3 *, int, int);
5353
5354 /* Restart hardware after configuration changes, self-test, etc.
5355  * Invoked with tp->lock held.
5356  */
5357 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5358         __releases(tp->lock)
5359         __acquires(tp->lock)
5360 {
5361         int err;
5362
5363         err = tg3_init_hw(tp, reset_phy);
5364         if (err) {
5365                 netdev_err(tp->dev,
5366                            "Failed to re-initialize device, aborting\n");
5367                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5368                 tg3_full_unlock(tp);
5369                 del_timer_sync(&tp->timer);
5370                 tp->irq_sync = 0;
5371                 tg3_napi_enable(tp);
5372                 dev_close(tp->dev);
5373                 tg3_full_lock(tp, 0);
5374         }
5375         return err;
5376 }
5377
5378 #ifdef CONFIG_NET_POLL_CONTROLLER
5379 static void tg3_poll_controller(struct net_device *dev)
5380 {
5381         int i;
5382         struct tg3 *tp = netdev_priv(dev);
5383
5384         for (i = 0; i < tp->irq_cnt; i++)
5385                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5386 }
5387 #endif
5388
5389 static void tg3_reset_task(struct work_struct *work)
5390 {
5391         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5392         int err;
5393         unsigned int restart_timer;
5394
5395         tg3_full_lock(tp, 0);
5396
5397         if (!netif_running(tp->dev)) {
5398                 tg3_full_unlock(tp);
5399                 return;
5400         }
5401
5402         tg3_full_unlock(tp);
5403
5404         tg3_phy_stop(tp);
5405
5406         tg3_netif_stop(tp);
5407
5408         tg3_full_lock(tp, 1);
5409
5410         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5411         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5412
5413         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5414                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5415                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5416                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5417                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5418         }
5419
5420         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5421         err = tg3_init_hw(tp, 1);
5422         if (err)
5423                 goto out;
5424
5425         tg3_netif_start(tp);
5426
5427         if (restart_timer)
5428                 mod_timer(&tp->timer, jiffies + 1);
5429
5430 out:
5431         tg3_full_unlock(tp);
5432
5433         if (!err)
5434                 tg3_phy_start(tp);
5435 }
5436
5437 static void tg3_dump_short_state(struct tg3 *tp)
5438 {
5439         netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5440                    tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5441         netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5442                    tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5443 }
5444
5445 static void tg3_tx_timeout(struct net_device *dev)
5446 {
5447         struct tg3 *tp = netdev_priv(dev);
5448
5449         if (netif_msg_tx_err(tp)) {
5450                 netdev_err(dev, "transmit timed out, resetting\n");
5451                 tg3_dump_short_state(tp);
5452         }
5453
5454         schedule_work(&tp->reset_task);
5455 }
5456
5457 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5458 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5459 {
5460         u32 base = (u32) mapping & 0xffffffff;
5461
5462         return (base > 0xffffdcc0) && (base + len + 8 < base);
5463 }
5464
5465 /* Test for DMA addresses > 40-bit */
5466 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5467                                           int len)
5468 {
5469 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5470         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5471                 return ((u64) mapping + len) > DMA_BIT_MASK(40);
5472         return 0;
5473 #else
5474         return 0;
5475 #endif
5476 }
5477
5478 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5479
5480 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5481 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5482                                        struct sk_buff *skb, u32 last_plus_one,
5483                                        u32 *start, u32 base_flags, u32 mss)
5484 {
5485         struct tg3 *tp = tnapi->tp;
5486         struct sk_buff *new_skb;
5487         dma_addr_t new_addr = 0;
5488         u32 entry = *start;
5489         int i, ret = 0;
5490
5491         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5492                 new_skb = skb_copy(skb, GFP_ATOMIC);
5493         else {
5494                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5495
5496                 new_skb = skb_copy_expand(skb,
5497                                           skb_headroom(skb) + more_headroom,
5498                                           skb_tailroom(skb), GFP_ATOMIC);
5499         }
5500
5501         if (!new_skb) {
5502                 ret = -1;
5503         } else {
5504                 /* New SKB is guaranteed to be linear. */
5505                 entry = *start;
5506                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5507                                           PCI_DMA_TODEVICE);
5508                 /* Make sure the mapping succeeded */
5509                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5510                         ret = -1;
5511                         dev_kfree_skb(new_skb);
5512                         new_skb = NULL;
5513
5514                 /* Make sure new skb does not cross any 4G boundaries.
5515                  * Drop the packet if it does.
5516                  */
5517                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5518                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5519                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5520                                          PCI_DMA_TODEVICE);
5521                         ret = -1;
5522                         dev_kfree_skb(new_skb);
5523                         new_skb = NULL;
5524                 } else {
5525                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5526                                     base_flags, 1 | (mss << 1));
5527                         *start = NEXT_TX(entry);
5528                 }
5529         }
5530
5531         /* Now clean up the sw ring entries. */
5532         i = 0;
5533         while (entry != last_plus_one) {
5534                 int len;
5535
5536                 if (i == 0)
5537                         len = skb_headlen(skb);
5538                 else
5539                         len = skb_shinfo(skb)->frags[i-1].size;
5540
5541                 pci_unmap_single(tp->pdev,
5542                                  dma_unmap_addr(&tnapi->tx_buffers[entry],
5543                                                 mapping),
5544                                  len, PCI_DMA_TODEVICE);
5545                 if (i == 0) {
5546                         tnapi->tx_buffers[entry].skb = new_skb;
5547                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5548                                            new_addr);
5549                 } else {
5550                         tnapi->tx_buffers[entry].skb = NULL;
5551                 }
5552                 entry = NEXT_TX(entry);
5553                 i++;
5554         }
5555
5556         dev_kfree_skb(skb);
5557
5558         return ret;
5559 }
5560
5561 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5562                         dma_addr_t mapping, int len, u32 flags,
5563                         u32 mss_and_is_end)
5564 {
5565         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5566         int is_end = (mss_and_is_end & 0x1);
5567         u32 mss = (mss_and_is_end >> 1);
5568         u32 vlan_tag = 0;
5569
5570         if (is_end)
5571                 flags |= TXD_FLAG_END;
5572         if (flags & TXD_FLAG_VLAN) {
5573                 vlan_tag = flags >> 16;
5574                 flags &= 0xffff;
5575         }
5576         vlan_tag |= (mss << TXD_MSS_SHIFT);
5577
5578         txd->addr_hi = ((u64) mapping >> 32);
5579         txd->addr_lo = ((u64) mapping & 0xffffffff);
5580         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5581         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5582 }
5583
5584 /* hard_start_xmit for devices that don't have any bugs and
5585  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5586  */
5587 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5588                                   struct net_device *dev)
5589 {
5590         struct tg3 *tp = netdev_priv(dev);
5591         u32 len, entry, base_flags, mss;
5592         dma_addr_t mapping;
5593         struct tg3_napi *tnapi;
5594         struct netdev_queue *txq;
5595         unsigned int i, last;
5596
5597         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5598         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5599         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5600                 tnapi++;
5601
5602         /* We are running in BH disabled context with netif_tx_lock
5603          * and TX reclaim runs via tp->napi.poll inside of a software
5604          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5605          * no IRQ context deadlocks to worry about either.  Rejoice!
5606          */
5607         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5608                 if (!netif_tx_queue_stopped(txq)) {
5609                         netif_tx_stop_queue(txq);
5610
5611                         /* This is a hard error, log it. */
5612                         netdev_err(dev,
5613                                    "BUG! Tx Ring full when queue awake!\n");
5614                 }
5615                 return NETDEV_TX_BUSY;
5616         }
5617
5618         entry = tnapi->tx_prod;
5619         base_flags = 0;
5620         mss = skb_shinfo(skb)->gso_size;
5621         if (mss) {
5622                 int tcp_opt_len, ip_tcp_len;
5623                 u32 hdrlen;
5624
5625                 if (skb_header_cloned(skb) &&
5626                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5627                         dev_kfree_skb(skb);
5628                         goto out_unlock;
5629                 }
5630
5631                 if (skb_is_gso_v6(skb)) {
5632                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5633                 } else {
5634                         struct iphdr *iph = ip_hdr(skb);
5635
5636                         tcp_opt_len = tcp_optlen(skb);
5637                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5638
5639                         iph->check = 0;
5640                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5641                         hdrlen = ip_tcp_len + tcp_opt_len;
5642                 }
5643
5644                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5645                         mss |= (hdrlen & 0xc) << 12;
5646                         if (hdrlen & 0x10)
5647                                 base_flags |= 0x00000010;
5648                         base_flags |= (hdrlen & 0x3e0) << 5;
5649                 } else
5650                         mss |= hdrlen << 9;
5651
5652                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5653                                TXD_FLAG_CPU_POST_DMA);
5654
5655                 tcp_hdr(skb)->check = 0;
5656
5657         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5658                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5659         }
5660
5661 #if TG3_VLAN_TAG_USED
5662         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5663                 base_flags |= (TXD_FLAG_VLAN |
5664                                (vlan_tx_tag_get(skb) << 16));
5665 #endif
5666
5667         len = skb_headlen(skb);
5668
5669         /* Queue skb data, a.k.a. the main skb fragment. */
5670         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5671         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5672                 dev_kfree_skb(skb);
5673                 goto out_unlock;
5674         }
5675
5676         tnapi->tx_buffers[entry].skb = skb;
5677         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5678
5679         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5680             !mss && skb->len > ETH_DATA_LEN)
5681                 base_flags |= TXD_FLAG_JMB_PKT;
5682
5683         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5684                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5685
5686         entry = NEXT_TX(entry);
5687
5688         /* Now loop through additional data fragments, and queue them. */
5689         if (skb_shinfo(skb)->nr_frags > 0) {
5690                 last = skb_shinfo(skb)->nr_frags - 1;
5691                 for (i = 0; i <= last; i++) {
5692                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5693
5694                         len = frag->size;
5695                         mapping = pci_map_page(tp->pdev,
5696                                                frag->page,
5697                                                frag->page_offset,
5698                                                len, PCI_DMA_TODEVICE);
5699                         if (pci_dma_mapping_error(tp->pdev, mapping))
5700                                 goto dma_error;
5701
5702                         tnapi->tx_buffers[entry].skb = NULL;
5703                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5704                                            mapping);
5705
5706                         tg3_set_txd(tnapi, entry, mapping, len,
5707                                     base_flags, (i == last) | (mss << 1));
5708
5709                         entry = NEXT_TX(entry);
5710                 }
5711         }
5712
5713         /* Packets are ready, update Tx producer idx local and on card. */
5714         tw32_tx_mbox(tnapi->prodmbox, entry);
5715
5716         tnapi->tx_prod = entry;
5717         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5718                 netif_tx_stop_queue(txq);
5719
5720                 /* netif_tx_stop_queue() must be done before checking
5721                  * checking tx index in tg3_tx_avail() below, because in
5722                  * tg3_tx(), we update tx index before checking for
5723                  * netif_tx_queue_stopped().
5724                  */
5725                 smp_mb();
5726                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5727                         netif_tx_wake_queue(txq);
5728         }
5729
5730 out_unlock:
5731         mmiowb();
5732
5733         return NETDEV_TX_OK;
5734
5735 dma_error:
5736         last = i;
5737         entry = tnapi->tx_prod;
5738         tnapi->tx_buffers[entry].skb = NULL;
5739         pci_unmap_single(tp->pdev,
5740                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5741                          skb_headlen(skb),
5742                          PCI_DMA_TODEVICE);
5743         for (i = 0; i <= last; i++) {
5744                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5745                 entry = NEXT_TX(entry);
5746
5747                 pci_unmap_page(tp->pdev,
5748                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5749                                               mapping),
5750                                frag->size, PCI_DMA_TODEVICE);
5751         }
5752
5753         dev_kfree_skb(skb);
5754         return NETDEV_TX_OK;
5755 }
5756
5757 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5758                                           struct net_device *);
5759
5760 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5761  * TSO header is greater than 80 bytes.
5762  */
5763 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5764 {
5765         struct sk_buff *segs, *nskb;
<