pch_can: fix 800k comms issue
[linux-2.6.git] / drivers / net / tg3.c
1 /*
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  * Copyright (C) 2005-2010 Broadcom Corporation.
8  *
9  * Firmware is:
10  *      Derived from proprietary unpublished source code,
11  *      Copyright (C) 2000-2003 Broadcom Corporation.
12  *
13  *      Permission is hereby granted for the distribution of this firmware
14  *      data in hexadecimal or equivalent format, provided this copyright
15  *      notice is accompanying it.
16  */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/in.h>
28 #include <linux/init.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mdio.h>
36 #include <linux/mii.h>
37 #include <linux/phy.h>
38 #include <linux/brcmphy.h>
39 #include <linux/if_vlan.h>
40 #include <linux/ip.h>
41 #include <linux/tcp.h>
42 #include <linux/workqueue.h>
43 #include <linux/prefetch.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/firmware.h>
46
47 #include <net/checksum.h>
48 #include <net/ip.h>
49
50 #include <asm/system.h>
51 #include <asm/io.h>
52 #include <asm/byteorder.h>
53 #include <asm/uaccess.h>
54
55 #ifdef CONFIG_SPARC
56 #include <asm/idprom.h>
57 #include <asm/prom.h>
58 #endif
59
60 #define BAR_0   0
61 #define BAR_2   2
62
63 #include "tg3.h"
64
65 #define DRV_MODULE_NAME         "tg3"
66 #define TG3_MAJ_NUM                     3
67 #define TG3_MIN_NUM                     116
68 #define DRV_MODULE_VERSION      \
69         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
70 #define DRV_MODULE_RELDATE      "December 3, 2010"
71
72 #define TG3_DEF_MAC_MODE        0
73 #define TG3_DEF_RX_MODE         0
74 #define TG3_DEF_TX_MODE         0
75 #define TG3_DEF_MSG_ENABLE        \
76         (NETIF_MSG_DRV          | \
77          NETIF_MSG_PROBE        | \
78          NETIF_MSG_LINK         | \
79          NETIF_MSG_TIMER        | \
80          NETIF_MSG_IFDOWN       | \
81          NETIF_MSG_IFUP         | \
82          NETIF_MSG_RX_ERR       | \
83          NETIF_MSG_TX_ERR)
84
85 /* length of time before we decide the hardware is borked,
86  * and dev->tx_timeout() should be called to fix the problem
87  */
88 #define TG3_TX_TIMEOUT                  (5 * HZ)
89
90 /* hardware minimum and maximum for a single frame's data payload */
91 #define TG3_MIN_MTU                     60
92 #define TG3_MAX_MTU(tp) \
93         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
94
95 /* These numbers seem to be hard coded in the NIC firmware somehow.
96  * You can't change the ring sizes, but you can change where you place
97  * them in the NIC onboard memory.
98  */
99 #define TG3_RX_STD_RING_SIZE(tp) \
100         ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
101           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
102          RX_STD_MAX_SIZE_5717 : 512)
103 #define TG3_DEF_RX_RING_PENDING         200
104 #define TG3_RX_JMB_RING_SIZE(tp) \
105         ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
106           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
107          1024 : 256)
108 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
109 #define TG3_RSS_INDIR_TBL_SIZE          128
110
111 /* Do not place this n-ring entries value into the tp struct itself,
112  * we really want to expose these constants to GCC so that modulo et
113  * al.  operations are done with shifts and masks instead of with
114  * hw multiply/modulo instructions.  Another solution would be to
115  * replace things like '% foo' with '& (foo - 1)'.
116  */
117
118 #define TG3_TX_RING_SIZE                512
119 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
120
121 #define TG3_RX_STD_RING_BYTES(tp) \
122         (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
123 #define TG3_RX_JMB_RING_BYTES(tp) \
124         (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
125 #define TG3_RX_RCB_RING_BYTES(tp) \
126         (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
127 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
128                                  TG3_TX_RING_SIZE)
129 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
130
131 #define TG3_DMA_BYTE_ENAB               64
132
133 #define TG3_RX_STD_DMA_SZ               1536
134 #define TG3_RX_JMB_DMA_SZ               9046
135
136 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
137
138 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
139 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
140
141 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
142         (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
143
144 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
145         (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
146
147 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
148  * that are at least dword aligned when used in PCIX mode.  The driver
149  * works around this bug by double copying the packet.  This workaround
150  * is built into the normal double copy length check for efficiency.
151  *
152  * However, the double copy is only necessary on those architectures
153  * where unaligned memory accesses are inefficient.  For those architectures
154  * where unaligned memory accesses incur little penalty, we can reintegrate
155  * the 5701 in the normal rx path.  Doing so saves a device structure
156  * dereference by hardcoding the double copy threshold in place.
157  */
158 #define TG3_RX_COPY_THRESHOLD           256
159 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
160         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
161 #else
162         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
163 #endif
164
165 /* minimum number of free TX descriptors required to wake up TX process */
166 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
167
168 #define TG3_RAW_IP_ALIGN 2
169
170 /* number of ETHTOOL_GSTATS u64's */
171 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
172
173 #define TG3_NUM_TEST            6
174
175 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
176
177 #define FIRMWARE_TG3            "tigon/tg3.bin"
178 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
179 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
180
181 static char version[] __devinitdata =
182         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
183
184 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
185 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
186 MODULE_LICENSE("GPL");
187 MODULE_VERSION(DRV_MODULE_VERSION);
188 MODULE_FIRMWARE(FIRMWARE_TG3);
189 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
190 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
191
192 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
193 module_param(tg3_debug, int, 0);
194 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
195
196 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
268         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
269         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
270         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
271         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
272         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
273         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
274         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
275         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
276         {}
277 };
278
279 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
280
281 static const struct {
282         const char string[ETH_GSTRING_LEN];
283 } ethtool_stats_keys[TG3_NUM_STATS] = {
284         { "rx_octets" },
285         { "rx_fragments" },
286         { "rx_ucast_packets" },
287         { "rx_mcast_packets" },
288         { "rx_bcast_packets" },
289         { "rx_fcs_errors" },
290         { "rx_align_errors" },
291         { "rx_xon_pause_rcvd" },
292         { "rx_xoff_pause_rcvd" },
293         { "rx_mac_ctrl_rcvd" },
294         { "rx_xoff_entered" },
295         { "rx_frame_too_long_errors" },
296         { "rx_jabbers" },
297         { "rx_undersize_packets" },
298         { "rx_in_length_errors" },
299         { "rx_out_length_errors" },
300         { "rx_64_or_less_octet_packets" },
301         { "rx_65_to_127_octet_packets" },
302         { "rx_128_to_255_octet_packets" },
303         { "rx_256_to_511_octet_packets" },
304         { "rx_512_to_1023_octet_packets" },
305         { "rx_1024_to_1522_octet_packets" },
306         { "rx_1523_to_2047_octet_packets" },
307         { "rx_2048_to_4095_octet_packets" },
308         { "rx_4096_to_8191_octet_packets" },
309         { "rx_8192_to_9022_octet_packets" },
310
311         { "tx_octets" },
312         { "tx_collisions" },
313
314         { "tx_xon_sent" },
315         { "tx_xoff_sent" },
316         { "tx_flow_control" },
317         { "tx_mac_errors" },
318         { "tx_single_collisions" },
319         { "tx_mult_collisions" },
320         { "tx_deferred" },
321         { "tx_excessive_collisions" },
322         { "tx_late_collisions" },
323         { "tx_collide_2times" },
324         { "tx_collide_3times" },
325         { "tx_collide_4times" },
326         { "tx_collide_5times" },
327         { "tx_collide_6times" },
328         { "tx_collide_7times" },
329         { "tx_collide_8times" },
330         { "tx_collide_9times" },
331         { "tx_collide_10times" },
332         { "tx_collide_11times" },
333         { "tx_collide_12times" },
334         { "tx_collide_13times" },
335         { "tx_collide_14times" },
336         { "tx_collide_15times" },
337         { "tx_ucast_packets" },
338         { "tx_mcast_packets" },
339         { "tx_bcast_packets" },
340         { "tx_carrier_sense_errors" },
341         { "tx_discards" },
342         { "tx_errors" },
343
344         { "dma_writeq_full" },
345         { "dma_write_prioq_full" },
346         { "rxbds_empty" },
347         { "rx_discards" },
348         { "rx_errors" },
349         { "rx_threshold_hit" },
350
351         { "dma_readq_full" },
352         { "dma_read_prioq_full" },
353         { "tx_comp_queue_full" },
354
355         { "ring_set_send_prod_index" },
356         { "ring_status_update" },
357         { "nic_irqs" },
358         { "nic_avoided_irqs" },
359         { "nic_tx_threshold_hit" }
360 };
361
362 static const struct {
363         const char string[ETH_GSTRING_LEN];
364 } ethtool_test_keys[TG3_NUM_TEST] = {
365         { "nvram test     (online) " },
366         { "link test      (online) " },
367         { "register test  (offline)" },
368         { "memory test    (offline)" },
369         { "loopback test  (offline)" },
370         { "interrupt test (offline)" },
371 };
372
373 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
374 {
375         writel(val, tp->regs + off);
376 }
377
378 static u32 tg3_read32(struct tg3 *tp, u32 off)
379 {
380         return readl(tp->regs + off);
381 }
382
383 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
384 {
385         writel(val, tp->aperegs + off);
386 }
387
388 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
389 {
390         return readl(tp->aperegs + off);
391 }
392
393 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
394 {
395         unsigned long flags;
396
397         spin_lock_irqsave(&tp->indirect_lock, flags);
398         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
399         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
400         spin_unlock_irqrestore(&tp->indirect_lock, flags);
401 }
402
403 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
404 {
405         writel(val, tp->regs + off);
406         readl(tp->regs + off);
407 }
408
409 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
410 {
411         unsigned long flags;
412         u32 val;
413
414         spin_lock_irqsave(&tp->indirect_lock, flags);
415         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
416         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
417         spin_unlock_irqrestore(&tp->indirect_lock, flags);
418         return val;
419 }
420
421 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
422 {
423         unsigned long flags;
424
425         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
426                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
427                                        TG3_64BIT_REG_LOW, val);
428                 return;
429         }
430         if (off == TG3_RX_STD_PROD_IDX_REG) {
431                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
432                                        TG3_64BIT_REG_LOW, val);
433                 return;
434         }
435
436         spin_lock_irqsave(&tp->indirect_lock, flags);
437         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
438         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
439         spin_unlock_irqrestore(&tp->indirect_lock, flags);
440
441         /* In indirect mode when disabling interrupts, we also need
442          * to clear the interrupt bit in the GRC local ctrl register.
443          */
444         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
445             (val == 0x1)) {
446                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
447                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
448         }
449 }
450
451 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
452 {
453         unsigned long flags;
454         u32 val;
455
456         spin_lock_irqsave(&tp->indirect_lock, flags);
457         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
458         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
459         spin_unlock_irqrestore(&tp->indirect_lock, flags);
460         return val;
461 }
462
463 /* usec_wait specifies the wait time in usec when writing to certain registers
464  * where it is unsafe to read back the register without some delay.
465  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
466  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
467  */
468 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
469 {
470         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
471             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
472                 /* Non-posted methods */
473                 tp->write32(tp, off, val);
474         else {
475                 /* Posted method */
476                 tg3_write32(tp, off, val);
477                 if (usec_wait)
478                         udelay(usec_wait);
479                 tp->read32(tp, off);
480         }
481         /* Wait again after the read for the posted method to guarantee that
482          * the wait time is met.
483          */
484         if (usec_wait)
485                 udelay(usec_wait);
486 }
487
488 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
489 {
490         tp->write32_mbox(tp, off, val);
491         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
492             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
493                 tp->read32_mbox(tp, off);
494 }
495
496 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
497 {
498         void __iomem *mbox = tp->regs + off;
499         writel(val, mbox);
500         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
501                 writel(val, mbox);
502         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
503                 readl(mbox);
504 }
505
506 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
507 {
508         return readl(tp->regs + off + GRCMBOX_BASE);
509 }
510
511 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
512 {
513         writel(val, tp->regs + off + GRCMBOX_BASE);
514 }
515
516 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
517 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
518 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
519 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
520 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
521
522 #define tw32(reg, val)                  tp->write32(tp, reg, val)
523 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
524 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
525 #define tr32(reg)                       tp->read32(tp, reg)
526
527 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
528 {
529         unsigned long flags;
530
531         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
532             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
533                 return;
534
535         spin_lock_irqsave(&tp->indirect_lock, flags);
536         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
537                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
538                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
539
540                 /* Always leave this as zero. */
541                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
542         } else {
543                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
544                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
545
546                 /* Always leave this as zero. */
547                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
548         }
549         spin_unlock_irqrestore(&tp->indirect_lock, flags);
550 }
551
552 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
553 {
554         unsigned long flags;
555
556         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
557             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
558                 *val = 0;
559                 return;
560         }
561
562         spin_lock_irqsave(&tp->indirect_lock, flags);
563         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
564                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
565                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
566
567                 /* Always leave this as zero. */
568                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
569         } else {
570                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
571                 *val = tr32(TG3PCI_MEM_WIN_DATA);
572
573                 /* Always leave this as zero. */
574                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
575         }
576         spin_unlock_irqrestore(&tp->indirect_lock, flags);
577 }
578
579 static void tg3_ape_lock_init(struct tg3 *tp)
580 {
581         int i;
582         u32 regbase;
583
584         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
585                 regbase = TG3_APE_LOCK_GRANT;
586         else
587                 regbase = TG3_APE_PER_LOCK_GRANT;
588
589         /* Make sure the driver hasn't any stale locks. */
590         for (i = 0; i < 8; i++)
591                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
592 }
593
594 static int tg3_ape_lock(struct tg3 *tp, int locknum)
595 {
596         int i, off;
597         int ret = 0;
598         u32 status, req, gnt;
599
600         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
601                 return 0;
602
603         switch (locknum) {
604         case TG3_APE_LOCK_GRC:
605         case TG3_APE_LOCK_MEM:
606                 break;
607         default:
608                 return -EINVAL;
609         }
610
611         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
612                 req = TG3_APE_LOCK_REQ;
613                 gnt = TG3_APE_LOCK_GRANT;
614         } else {
615                 req = TG3_APE_PER_LOCK_REQ;
616                 gnt = TG3_APE_PER_LOCK_GRANT;
617         }
618
619         off = 4 * locknum;
620
621         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
622
623         /* Wait for up to 1 millisecond to acquire lock. */
624         for (i = 0; i < 100; i++) {
625                 status = tg3_ape_read32(tp, gnt + off);
626                 if (status == APE_LOCK_GRANT_DRIVER)
627                         break;
628                 udelay(10);
629         }
630
631         if (status != APE_LOCK_GRANT_DRIVER) {
632                 /* Revoke the lock request. */
633                 tg3_ape_write32(tp, gnt + off,
634                                 APE_LOCK_GRANT_DRIVER);
635
636                 ret = -EBUSY;
637         }
638
639         return ret;
640 }
641
642 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
643 {
644         u32 gnt;
645
646         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
647                 return;
648
649         switch (locknum) {
650         case TG3_APE_LOCK_GRC:
651         case TG3_APE_LOCK_MEM:
652                 break;
653         default:
654                 return;
655         }
656
657         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
658                 gnt = TG3_APE_LOCK_GRANT;
659         else
660                 gnt = TG3_APE_PER_LOCK_GRANT;
661
662         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
663 }
664
665 static void tg3_disable_ints(struct tg3 *tp)
666 {
667         int i;
668
669         tw32(TG3PCI_MISC_HOST_CTRL,
670              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
671         for (i = 0; i < tp->irq_max; i++)
672                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
673 }
674
675 static void tg3_enable_ints(struct tg3 *tp)
676 {
677         int i;
678
679         tp->irq_sync = 0;
680         wmb();
681
682         tw32(TG3PCI_MISC_HOST_CTRL,
683              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
684
685         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
686         for (i = 0; i < tp->irq_cnt; i++) {
687                 struct tg3_napi *tnapi = &tp->napi[i];
688
689                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
690                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
691                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
692
693                 tp->coal_now |= tnapi->coal_now;
694         }
695
696         /* Force an initial interrupt */
697         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
698             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
699                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
700         else
701                 tw32(HOSTCC_MODE, tp->coal_now);
702
703         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
704 }
705
706 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
707 {
708         struct tg3 *tp = tnapi->tp;
709         struct tg3_hw_status *sblk = tnapi->hw_status;
710         unsigned int work_exists = 0;
711
712         /* check for phy events */
713         if (!(tp->tg3_flags &
714               (TG3_FLAG_USE_LINKCHG_REG |
715                TG3_FLAG_POLL_SERDES))) {
716                 if (sblk->status & SD_STATUS_LINK_CHG)
717                         work_exists = 1;
718         }
719         /* check for RX/TX work to do */
720         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
721             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
722                 work_exists = 1;
723
724         return work_exists;
725 }
726
727 /* tg3_int_reenable
728  *  similar to tg3_enable_ints, but it accurately determines whether there
729  *  is new work pending and can return without flushing the PIO write
730  *  which reenables interrupts
731  */
732 static void tg3_int_reenable(struct tg3_napi *tnapi)
733 {
734         struct tg3 *tp = tnapi->tp;
735
736         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
737         mmiowb();
738
739         /* When doing tagged status, this work check is unnecessary.
740          * The last_tag we write above tells the chip which piece of
741          * work we've completed.
742          */
743         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
744             tg3_has_work(tnapi))
745                 tw32(HOSTCC_MODE, tp->coalesce_mode |
746                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
747 }
748
749 static void tg3_switch_clocks(struct tg3 *tp)
750 {
751         u32 clock_ctrl;
752         u32 orig_clock_ctrl;
753
754         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
755             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
756                 return;
757
758         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
759
760         orig_clock_ctrl = clock_ctrl;
761         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
762                        CLOCK_CTRL_CLKRUN_OENABLE |
763                        0x1f);
764         tp->pci_clock_ctrl = clock_ctrl;
765
766         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
767                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
768                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
769                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
770                 }
771         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
772                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
773                             clock_ctrl |
774                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
775                             40);
776                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
777                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
778                             40);
779         }
780         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
781 }
782
783 #define PHY_BUSY_LOOPS  5000
784
785 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
786 {
787         u32 frame_val;
788         unsigned int loops;
789         int ret;
790
791         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
792                 tw32_f(MAC_MI_MODE,
793                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
794                 udelay(80);
795         }
796
797         *val = 0x0;
798
799         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
800                       MI_COM_PHY_ADDR_MASK);
801         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
802                       MI_COM_REG_ADDR_MASK);
803         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
804
805         tw32_f(MAC_MI_COM, frame_val);
806
807         loops = PHY_BUSY_LOOPS;
808         while (loops != 0) {
809                 udelay(10);
810                 frame_val = tr32(MAC_MI_COM);
811
812                 if ((frame_val & MI_COM_BUSY) == 0) {
813                         udelay(5);
814                         frame_val = tr32(MAC_MI_COM);
815                         break;
816                 }
817                 loops -= 1;
818         }
819
820         ret = -EBUSY;
821         if (loops != 0) {
822                 *val = frame_val & MI_COM_DATA_MASK;
823                 ret = 0;
824         }
825
826         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
827                 tw32_f(MAC_MI_MODE, tp->mi_mode);
828                 udelay(80);
829         }
830
831         return ret;
832 }
833
834 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
835 {
836         u32 frame_val;
837         unsigned int loops;
838         int ret;
839
840         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
841             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
842                 return 0;
843
844         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
845                 tw32_f(MAC_MI_MODE,
846                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
847                 udelay(80);
848         }
849
850         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
851                       MI_COM_PHY_ADDR_MASK);
852         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
853                       MI_COM_REG_ADDR_MASK);
854         frame_val |= (val & MI_COM_DATA_MASK);
855         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
856
857         tw32_f(MAC_MI_COM, frame_val);
858
859         loops = PHY_BUSY_LOOPS;
860         while (loops != 0) {
861                 udelay(10);
862                 frame_val = tr32(MAC_MI_COM);
863                 if ((frame_val & MI_COM_BUSY) == 0) {
864                         udelay(5);
865                         frame_val = tr32(MAC_MI_COM);
866                         break;
867                 }
868                 loops -= 1;
869         }
870
871         ret = -EBUSY;
872         if (loops != 0)
873                 ret = 0;
874
875         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
876                 tw32_f(MAC_MI_MODE, tp->mi_mode);
877                 udelay(80);
878         }
879
880         return ret;
881 }
882
883 static int tg3_bmcr_reset(struct tg3 *tp)
884 {
885         u32 phy_control;
886         int limit, err;
887
888         /* OK, reset it, and poll the BMCR_RESET bit until it
889          * clears or we time out.
890          */
891         phy_control = BMCR_RESET;
892         err = tg3_writephy(tp, MII_BMCR, phy_control);
893         if (err != 0)
894                 return -EBUSY;
895
896         limit = 5000;
897         while (limit--) {
898                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
899                 if (err != 0)
900                         return -EBUSY;
901
902                 if ((phy_control & BMCR_RESET) == 0) {
903                         udelay(40);
904                         break;
905                 }
906                 udelay(10);
907         }
908         if (limit < 0)
909                 return -EBUSY;
910
911         return 0;
912 }
913
914 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
915 {
916         struct tg3 *tp = bp->priv;
917         u32 val;
918
919         spin_lock_bh(&tp->lock);
920
921         if (tg3_readphy(tp, reg, &val))
922                 val = -EIO;
923
924         spin_unlock_bh(&tp->lock);
925
926         return val;
927 }
928
929 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
930 {
931         struct tg3 *tp = bp->priv;
932         u32 ret = 0;
933
934         spin_lock_bh(&tp->lock);
935
936         if (tg3_writephy(tp, reg, val))
937                 ret = -EIO;
938
939         spin_unlock_bh(&tp->lock);
940
941         return ret;
942 }
943
944 static int tg3_mdio_reset(struct mii_bus *bp)
945 {
946         return 0;
947 }
948
949 static void tg3_mdio_config_5785(struct tg3 *tp)
950 {
951         u32 val;
952         struct phy_device *phydev;
953
954         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
955         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
956         case PHY_ID_BCM50610:
957         case PHY_ID_BCM50610M:
958                 val = MAC_PHYCFG2_50610_LED_MODES;
959                 break;
960         case PHY_ID_BCMAC131:
961                 val = MAC_PHYCFG2_AC131_LED_MODES;
962                 break;
963         case PHY_ID_RTL8211C:
964                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
965                 break;
966         case PHY_ID_RTL8201E:
967                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
968                 break;
969         default:
970                 return;
971         }
972
973         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
974                 tw32(MAC_PHYCFG2, val);
975
976                 val = tr32(MAC_PHYCFG1);
977                 val &= ~(MAC_PHYCFG1_RGMII_INT |
978                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
979                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
980                 tw32(MAC_PHYCFG1, val);
981
982                 return;
983         }
984
985         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
986                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
987                        MAC_PHYCFG2_FMODE_MASK_MASK |
988                        MAC_PHYCFG2_GMODE_MASK_MASK |
989                        MAC_PHYCFG2_ACT_MASK_MASK   |
990                        MAC_PHYCFG2_QUAL_MASK_MASK |
991                        MAC_PHYCFG2_INBAND_ENABLE;
992
993         tw32(MAC_PHYCFG2, val);
994
995         val = tr32(MAC_PHYCFG1);
996         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
997                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
998         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
999                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1000                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1001                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1002                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1003         }
1004         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1005                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1006         tw32(MAC_PHYCFG1, val);
1007
1008         val = tr32(MAC_EXT_RGMII_MODE);
1009         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1010                  MAC_RGMII_MODE_RX_QUALITY |
1011                  MAC_RGMII_MODE_RX_ACTIVITY |
1012                  MAC_RGMII_MODE_RX_ENG_DET |
1013                  MAC_RGMII_MODE_TX_ENABLE |
1014                  MAC_RGMII_MODE_TX_LOWPWR |
1015                  MAC_RGMII_MODE_TX_RESET);
1016         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1017                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1018                         val |= MAC_RGMII_MODE_RX_INT_B |
1019                                MAC_RGMII_MODE_RX_QUALITY |
1020                                MAC_RGMII_MODE_RX_ACTIVITY |
1021                                MAC_RGMII_MODE_RX_ENG_DET;
1022                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1023                         val |= MAC_RGMII_MODE_TX_ENABLE |
1024                                MAC_RGMII_MODE_TX_LOWPWR |
1025                                MAC_RGMII_MODE_TX_RESET;
1026         }
1027         tw32(MAC_EXT_RGMII_MODE, val);
1028 }
1029
1030 static void tg3_mdio_start(struct tg3 *tp)
1031 {
1032         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1033         tw32_f(MAC_MI_MODE, tp->mi_mode);
1034         udelay(80);
1035
1036         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1037             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1038                 tg3_mdio_config_5785(tp);
1039 }
1040
1041 static int tg3_mdio_init(struct tg3 *tp)
1042 {
1043         int i;
1044         u32 reg;
1045         struct phy_device *phydev;
1046
1047         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1048             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
1049                 u32 is_serdes;
1050
1051                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1052
1053                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1054                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1055                 else
1056                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1057                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1058                 if (is_serdes)
1059                         tp->phy_addr += 7;
1060         } else
1061                 tp->phy_addr = TG3_PHY_MII_ADDR;
1062
1063         tg3_mdio_start(tp);
1064
1065         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1066             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1067                 return 0;
1068
1069         tp->mdio_bus = mdiobus_alloc();
1070         if (tp->mdio_bus == NULL)
1071                 return -ENOMEM;
1072
1073         tp->mdio_bus->name     = "tg3 mdio bus";
1074         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1075                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1076         tp->mdio_bus->priv     = tp;
1077         tp->mdio_bus->parent   = &tp->pdev->dev;
1078         tp->mdio_bus->read     = &tg3_mdio_read;
1079         tp->mdio_bus->write    = &tg3_mdio_write;
1080         tp->mdio_bus->reset    = &tg3_mdio_reset;
1081         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1082         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1083
1084         for (i = 0; i < PHY_MAX_ADDR; i++)
1085                 tp->mdio_bus->irq[i] = PHY_POLL;
1086
1087         /* The bus registration will look for all the PHYs on the mdio bus.
1088          * Unfortunately, it does not ensure the PHY is powered up before
1089          * accessing the PHY ID registers.  A chip reset is the
1090          * quickest way to bring the device back to an operational state..
1091          */
1092         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1093                 tg3_bmcr_reset(tp);
1094
1095         i = mdiobus_register(tp->mdio_bus);
1096         if (i) {
1097                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1098                 mdiobus_free(tp->mdio_bus);
1099                 return i;
1100         }
1101
1102         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1103
1104         if (!phydev || !phydev->drv) {
1105                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1106                 mdiobus_unregister(tp->mdio_bus);
1107                 mdiobus_free(tp->mdio_bus);
1108                 return -ENODEV;
1109         }
1110
1111         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1112         case PHY_ID_BCM57780:
1113                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1114                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1115                 break;
1116         case PHY_ID_BCM50610:
1117         case PHY_ID_BCM50610M:
1118                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1119                                      PHY_BRCM_RX_REFCLK_UNUSED |
1120                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1121                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1122                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1123                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1124                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1125                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1126                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1127                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1128                 /* fallthru */
1129         case PHY_ID_RTL8211C:
1130                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1131                 break;
1132         case PHY_ID_RTL8201E:
1133         case PHY_ID_BCMAC131:
1134                 phydev->interface = PHY_INTERFACE_MODE_MII;
1135                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1136                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1137                 break;
1138         }
1139
1140         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1141
1142         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1143                 tg3_mdio_config_5785(tp);
1144
1145         return 0;
1146 }
1147
1148 static void tg3_mdio_fini(struct tg3 *tp)
1149 {
1150         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1151                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1152                 mdiobus_unregister(tp->mdio_bus);
1153                 mdiobus_free(tp->mdio_bus);
1154         }
1155 }
1156
1157 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1158 {
1159         int err;
1160
1161         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1162         if (err)
1163                 goto done;
1164
1165         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1166         if (err)
1167                 goto done;
1168
1169         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1170                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1171         if (err)
1172                 goto done;
1173
1174         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1175
1176 done:
1177         return err;
1178 }
1179
1180 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1181 {
1182         int err;
1183
1184         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1185         if (err)
1186                 goto done;
1187
1188         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1189         if (err)
1190                 goto done;
1191
1192         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1193                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1194         if (err)
1195                 goto done;
1196
1197         err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1198
1199 done:
1200         return err;
1201 }
1202
1203 /* tp->lock is held. */
1204 static inline void tg3_generate_fw_event(struct tg3 *tp)
1205 {
1206         u32 val;
1207
1208         val = tr32(GRC_RX_CPU_EVENT);
1209         val |= GRC_RX_CPU_DRIVER_EVENT;
1210         tw32_f(GRC_RX_CPU_EVENT, val);
1211
1212         tp->last_event_jiffies = jiffies;
1213 }
1214
1215 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1216
1217 /* tp->lock is held. */
1218 static void tg3_wait_for_event_ack(struct tg3 *tp)
1219 {
1220         int i;
1221         unsigned int delay_cnt;
1222         long time_remain;
1223
1224         /* If enough time has passed, no wait is necessary. */
1225         time_remain = (long)(tp->last_event_jiffies + 1 +
1226                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1227                       (long)jiffies;
1228         if (time_remain < 0)
1229                 return;
1230
1231         /* Check if we can shorten the wait time. */
1232         delay_cnt = jiffies_to_usecs(time_remain);
1233         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1234                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1235         delay_cnt = (delay_cnt >> 3) + 1;
1236
1237         for (i = 0; i < delay_cnt; i++) {
1238                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1239                         break;
1240                 udelay(8);
1241         }
1242 }
1243
1244 /* tp->lock is held. */
1245 static void tg3_ump_link_report(struct tg3 *tp)
1246 {
1247         u32 reg;
1248         u32 val;
1249
1250         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1251             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1252                 return;
1253
1254         tg3_wait_for_event_ack(tp);
1255
1256         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1257
1258         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1259
1260         val = 0;
1261         if (!tg3_readphy(tp, MII_BMCR, &reg))
1262                 val = reg << 16;
1263         if (!tg3_readphy(tp, MII_BMSR, &reg))
1264                 val |= (reg & 0xffff);
1265         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1266
1267         val = 0;
1268         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1269                 val = reg << 16;
1270         if (!tg3_readphy(tp, MII_LPA, &reg))
1271                 val |= (reg & 0xffff);
1272         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1273
1274         val = 0;
1275         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1276                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1277                         val = reg << 16;
1278                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1279                         val |= (reg & 0xffff);
1280         }
1281         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1282
1283         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1284                 val = reg << 16;
1285         else
1286                 val = 0;
1287         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1288
1289         tg3_generate_fw_event(tp);
1290 }
1291
1292 static void tg3_link_report(struct tg3 *tp)
1293 {
1294         if (!netif_carrier_ok(tp->dev)) {
1295                 netif_info(tp, link, tp->dev, "Link is down\n");
1296                 tg3_ump_link_report(tp);
1297         } else if (netif_msg_link(tp)) {
1298                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1299                             (tp->link_config.active_speed == SPEED_1000 ?
1300                              1000 :
1301                              (tp->link_config.active_speed == SPEED_100 ?
1302                               100 : 10)),
1303                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1304                              "full" : "half"));
1305
1306                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1307                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1308                             "on" : "off",
1309                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1310                             "on" : "off");
1311                 tg3_ump_link_report(tp);
1312         }
1313 }
1314
1315 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1316 {
1317         u16 miireg;
1318
1319         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1320                 miireg = ADVERTISE_PAUSE_CAP;
1321         else if (flow_ctrl & FLOW_CTRL_TX)
1322                 miireg = ADVERTISE_PAUSE_ASYM;
1323         else if (flow_ctrl & FLOW_CTRL_RX)
1324                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1325         else
1326                 miireg = 0;
1327
1328         return miireg;
1329 }
1330
1331 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1332 {
1333         u16 miireg;
1334
1335         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1336                 miireg = ADVERTISE_1000XPAUSE;
1337         else if (flow_ctrl & FLOW_CTRL_TX)
1338                 miireg = ADVERTISE_1000XPSE_ASYM;
1339         else if (flow_ctrl & FLOW_CTRL_RX)
1340                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1341         else
1342                 miireg = 0;
1343
1344         return miireg;
1345 }
1346
1347 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1348 {
1349         u8 cap = 0;
1350
1351         if (lcladv & ADVERTISE_1000XPAUSE) {
1352                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1353                         if (rmtadv & LPA_1000XPAUSE)
1354                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1355                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1356                                 cap = FLOW_CTRL_RX;
1357                 } else {
1358                         if (rmtadv & LPA_1000XPAUSE)
1359                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1360                 }
1361         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1362                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1363                         cap = FLOW_CTRL_TX;
1364         }
1365
1366         return cap;
1367 }
1368
1369 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1370 {
1371         u8 autoneg;
1372         u8 flowctrl = 0;
1373         u32 old_rx_mode = tp->rx_mode;
1374         u32 old_tx_mode = tp->tx_mode;
1375
1376         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1377                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1378         else
1379                 autoneg = tp->link_config.autoneg;
1380
1381         if (autoneg == AUTONEG_ENABLE &&
1382             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1383                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1384                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1385                 else
1386                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1387         } else
1388                 flowctrl = tp->link_config.flowctrl;
1389
1390         tp->link_config.active_flowctrl = flowctrl;
1391
1392         if (flowctrl & FLOW_CTRL_RX)
1393                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1394         else
1395                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1396
1397         if (old_rx_mode != tp->rx_mode)
1398                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1399
1400         if (flowctrl & FLOW_CTRL_TX)
1401                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1402         else
1403                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1404
1405         if (old_tx_mode != tp->tx_mode)
1406                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1407 }
1408
1409 static void tg3_adjust_link(struct net_device *dev)
1410 {
1411         u8 oldflowctrl, linkmesg = 0;
1412         u32 mac_mode, lcl_adv, rmt_adv;
1413         struct tg3 *tp = netdev_priv(dev);
1414         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1415
1416         spin_lock_bh(&tp->lock);
1417
1418         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1419                                     MAC_MODE_HALF_DUPLEX);
1420
1421         oldflowctrl = tp->link_config.active_flowctrl;
1422
1423         if (phydev->link) {
1424                 lcl_adv = 0;
1425                 rmt_adv = 0;
1426
1427                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1428                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1429                 else if (phydev->speed == SPEED_1000 ||
1430                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1431                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1432                 else
1433                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1434
1435                 if (phydev->duplex == DUPLEX_HALF)
1436                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1437                 else {
1438                         lcl_adv = tg3_advert_flowctrl_1000T(
1439                                   tp->link_config.flowctrl);
1440
1441                         if (phydev->pause)
1442                                 rmt_adv = LPA_PAUSE_CAP;
1443                         if (phydev->asym_pause)
1444                                 rmt_adv |= LPA_PAUSE_ASYM;
1445                 }
1446
1447                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1448         } else
1449                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1450
1451         if (mac_mode != tp->mac_mode) {
1452                 tp->mac_mode = mac_mode;
1453                 tw32_f(MAC_MODE, tp->mac_mode);
1454                 udelay(40);
1455         }
1456
1457         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1458                 if (phydev->speed == SPEED_10)
1459                         tw32(MAC_MI_STAT,
1460                              MAC_MI_STAT_10MBPS_MODE |
1461                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1462                 else
1463                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1464         }
1465
1466         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1467                 tw32(MAC_TX_LENGTHS,
1468                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1469                       (6 << TX_LENGTHS_IPG_SHIFT) |
1470                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1471         else
1472                 tw32(MAC_TX_LENGTHS,
1473                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1474                       (6 << TX_LENGTHS_IPG_SHIFT) |
1475                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1476
1477         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1478             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1479             phydev->speed != tp->link_config.active_speed ||
1480             phydev->duplex != tp->link_config.active_duplex ||
1481             oldflowctrl != tp->link_config.active_flowctrl)
1482                 linkmesg = 1;
1483
1484         tp->link_config.active_speed = phydev->speed;
1485         tp->link_config.active_duplex = phydev->duplex;
1486
1487         spin_unlock_bh(&tp->lock);
1488
1489         if (linkmesg)
1490                 tg3_link_report(tp);
1491 }
1492
1493 static int tg3_phy_init(struct tg3 *tp)
1494 {
1495         struct phy_device *phydev;
1496
1497         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1498                 return 0;
1499
1500         /* Bring the PHY back to a known state. */
1501         tg3_bmcr_reset(tp);
1502
1503         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1504
1505         /* Attach the MAC to the PHY. */
1506         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1507                              phydev->dev_flags, phydev->interface);
1508         if (IS_ERR(phydev)) {
1509                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1510                 return PTR_ERR(phydev);
1511         }
1512
1513         /* Mask with MAC supported features. */
1514         switch (phydev->interface) {
1515         case PHY_INTERFACE_MODE_GMII:
1516         case PHY_INTERFACE_MODE_RGMII:
1517                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1518                         phydev->supported &= (PHY_GBIT_FEATURES |
1519                                               SUPPORTED_Pause |
1520                                               SUPPORTED_Asym_Pause);
1521                         break;
1522                 }
1523                 /* fallthru */
1524         case PHY_INTERFACE_MODE_MII:
1525                 phydev->supported &= (PHY_BASIC_FEATURES |
1526                                       SUPPORTED_Pause |
1527                                       SUPPORTED_Asym_Pause);
1528                 break;
1529         default:
1530                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1531                 return -EINVAL;
1532         }
1533
1534         tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1535
1536         phydev->advertising = phydev->supported;
1537
1538         return 0;
1539 }
1540
1541 static void tg3_phy_start(struct tg3 *tp)
1542 {
1543         struct phy_device *phydev;
1544
1545         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1546                 return;
1547
1548         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1549
1550         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1551                 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1552                 phydev->speed = tp->link_config.orig_speed;
1553                 phydev->duplex = tp->link_config.orig_duplex;
1554                 phydev->autoneg = tp->link_config.orig_autoneg;
1555                 phydev->advertising = tp->link_config.orig_advertising;
1556         }
1557
1558         phy_start(phydev);
1559
1560         phy_start_aneg(phydev);
1561 }
1562
1563 static void tg3_phy_stop(struct tg3 *tp)
1564 {
1565         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1566                 return;
1567
1568         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1569 }
1570
1571 static void tg3_phy_fini(struct tg3 *tp)
1572 {
1573         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1574                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1575                 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1576         }
1577 }
1578
1579 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1580 {
1581         int err;
1582
1583         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1584         if (!err)
1585                 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1586
1587         return err;
1588 }
1589
1590 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1591 {
1592         int err;
1593
1594         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1595         if (!err)
1596                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1597
1598         return err;
1599 }
1600
1601 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1602 {
1603         u32 phytest;
1604
1605         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1606                 u32 phy;
1607
1608                 tg3_writephy(tp, MII_TG3_FET_TEST,
1609                              phytest | MII_TG3_FET_SHADOW_EN);
1610                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1611                         if (enable)
1612                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1613                         else
1614                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1615                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1616                 }
1617                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1618         }
1619 }
1620
1621 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1622 {
1623         u32 reg;
1624
1625         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1626             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1627               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1628              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1629                 return;
1630
1631         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1632                 tg3_phy_fet_toggle_apd(tp, enable);
1633                 return;
1634         }
1635
1636         reg = MII_TG3_MISC_SHDW_WREN |
1637               MII_TG3_MISC_SHDW_SCR5_SEL |
1638               MII_TG3_MISC_SHDW_SCR5_LPED |
1639               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1640               MII_TG3_MISC_SHDW_SCR5_SDTL |
1641               MII_TG3_MISC_SHDW_SCR5_C125OE;
1642         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1643                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1644
1645         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1646
1647
1648         reg = MII_TG3_MISC_SHDW_WREN |
1649               MII_TG3_MISC_SHDW_APD_SEL |
1650               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1651         if (enable)
1652                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1653
1654         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1655 }
1656
1657 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1658 {
1659         u32 phy;
1660
1661         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1662             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1663                 return;
1664
1665         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1666                 u32 ephy;
1667
1668                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1669                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1670
1671                         tg3_writephy(tp, MII_TG3_FET_TEST,
1672                                      ephy | MII_TG3_FET_SHADOW_EN);
1673                         if (!tg3_readphy(tp, reg, &phy)) {
1674                                 if (enable)
1675                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1676                                 else
1677                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1678                                 tg3_writephy(tp, reg, phy);
1679                         }
1680                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1681                 }
1682         } else {
1683                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1684                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1685                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1686                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1687                         if (enable)
1688                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1689                         else
1690                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1691                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1692                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1693                 }
1694         }
1695 }
1696
1697 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1698 {
1699         u32 val;
1700
1701         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1702                 return;
1703
1704         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1705             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1706                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1707                              (val | (1 << 15) | (1 << 4)));
1708 }
1709
1710 static void tg3_phy_apply_otp(struct tg3 *tp)
1711 {
1712         u32 otp, phy;
1713
1714         if (!tp->phy_otp)
1715                 return;
1716
1717         otp = tp->phy_otp;
1718
1719         /* Enable SM_DSP clock and tx 6dB coding. */
1720         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1721               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1722               MII_TG3_AUXCTL_ACTL_TX_6DB;
1723         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1724
1725         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1726         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1727         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1728
1729         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1730               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1731         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1732
1733         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1734         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1735         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1736
1737         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1738         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1739
1740         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1741         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1742
1743         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1744               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1745         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1746
1747         /* Turn off SM_DSP clock. */
1748         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1749               MII_TG3_AUXCTL_ACTL_TX_6DB;
1750         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1751 }
1752
1753 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
1754 {
1755         u32 val;
1756
1757         if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
1758                 return;
1759
1760         tp->setlpicnt = 0;
1761
1762         if (tp->link_config.autoneg == AUTONEG_ENABLE &&
1763             current_link_up == 1 &&
1764             tp->link_config.active_duplex == DUPLEX_FULL &&
1765             (tp->link_config.active_speed == SPEED_100 ||
1766              tp->link_config.active_speed == SPEED_1000)) {
1767                 u32 eeectl;
1768
1769                 if (tp->link_config.active_speed == SPEED_1000)
1770                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
1771                 else
1772                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
1773
1774                 tw32(TG3_CPMU_EEE_CTRL, eeectl);
1775
1776                 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
1777                                   TG3_CL45_D7_EEERES_STAT, &val);
1778
1779                 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
1780                     val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
1781                         tp->setlpicnt = 2;
1782         }
1783
1784         if (!tp->setlpicnt) {
1785                 val = tr32(TG3_CPMU_EEE_MODE);
1786                 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
1787         }
1788 }
1789
1790 static int tg3_wait_macro_done(struct tg3 *tp)
1791 {
1792         int limit = 100;
1793
1794         while (limit--) {
1795                 u32 tmp32;
1796
1797                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1798                         if ((tmp32 & 0x1000) == 0)
1799                                 break;
1800                 }
1801         }
1802         if (limit < 0)
1803                 return -EBUSY;
1804
1805         return 0;
1806 }
1807
1808 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1809 {
1810         static const u32 test_pat[4][6] = {
1811         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1812         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1813         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1814         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1815         };
1816         int chan;
1817
1818         for (chan = 0; chan < 4; chan++) {
1819                 int i;
1820
1821                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1822                              (chan * 0x2000) | 0x0200);
1823                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1824
1825                 for (i = 0; i < 6; i++)
1826                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1827                                      test_pat[chan][i]);
1828
1829                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1830                 if (tg3_wait_macro_done(tp)) {
1831                         *resetp = 1;
1832                         return -EBUSY;
1833                 }
1834
1835                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1836                              (chan * 0x2000) | 0x0200);
1837                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1838                 if (tg3_wait_macro_done(tp)) {
1839                         *resetp = 1;
1840                         return -EBUSY;
1841                 }
1842
1843                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1844                 if (tg3_wait_macro_done(tp)) {
1845                         *resetp = 1;
1846                         return -EBUSY;
1847                 }
1848
1849                 for (i = 0; i < 6; i += 2) {
1850                         u32 low, high;
1851
1852                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1853                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1854                             tg3_wait_macro_done(tp)) {
1855                                 *resetp = 1;
1856                                 return -EBUSY;
1857                         }
1858                         low &= 0x7fff;
1859                         high &= 0x000f;
1860                         if (low != test_pat[chan][i] ||
1861                             high != test_pat[chan][i+1]) {
1862                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1863                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1864                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1865
1866                                 return -EBUSY;
1867                         }
1868                 }
1869         }
1870
1871         return 0;
1872 }
1873
1874 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1875 {
1876         int chan;
1877
1878         for (chan = 0; chan < 4; chan++) {
1879                 int i;
1880
1881                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1882                              (chan * 0x2000) | 0x0200);
1883                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1884                 for (i = 0; i < 6; i++)
1885                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1886                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1887                 if (tg3_wait_macro_done(tp))
1888                         return -EBUSY;
1889         }
1890
1891         return 0;
1892 }
1893
1894 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1895 {
1896         u32 reg32, phy9_orig;
1897         int retries, do_phy_reset, err;
1898
1899         retries = 10;
1900         do_phy_reset = 1;
1901         do {
1902                 if (do_phy_reset) {
1903                         err = tg3_bmcr_reset(tp);
1904                         if (err)
1905                                 return err;
1906                         do_phy_reset = 0;
1907                 }
1908
1909                 /* Disable transmitter and interrupt.  */
1910                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1911                         continue;
1912
1913                 reg32 |= 0x3000;
1914                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1915
1916                 /* Set full-duplex, 1000 mbps.  */
1917                 tg3_writephy(tp, MII_BMCR,
1918                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1919
1920                 /* Set to master mode.  */
1921                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1922                         continue;
1923
1924                 tg3_writephy(tp, MII_TG3_CTRL,
1925                              (MII_TG3_CTRL_AS_MASTER |
1926                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1927
1928                 /* Enable SM_DSP_CLOCK and 6dB.  */
1929                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1930
1931                 /* Block the PHY control access.  */
1932                 tg3_phydsp_write(tp, 0x8005, 0x0800);
1933
1934                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1935                 if (!err)
1936                         break;
1937         } while (--retries);
1938
1939         err = tg3_phy_reset_chanpat(tp);
1940         if (err)
1941                 return err;
1942
1943         tg3_phydsp_write(tp, 0x8005, 0x0000);
1944
1945         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1946         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1947
1948         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1949             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1950                 /* Set Extended packet length bit for jumbo frames */
1951                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1952         } else {
1953                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1954         }
1955
1956         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1957
1958         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1959                 reg32 &= ~0x3000;
1960                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1961         } else if (!err)
1962                 err = -EBUSY;
1963
1964         return err;
1965 }
1966
1967 /* This will reset the tigon3 PHY if there is no valid
1968  * link unless the FORCE argument is non-zero.
1969  */
1970 static int tg3_phy_reset(struct tg3 *tp)
1971 {
1972         u32 val, cpmuctrl;
1973         int err;
1974
1975         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1976                 val = tr32(GRC_MISC_CFG);
1977                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1978                 udelay(40);
1979         }
1980         err  = tg3_readphy(tp, MII_BMSR, &val);
1981         err |= tg3_readphy(tp, MII_BMSR, &val);
1982         if (err != 0)
1983                 return -EBUSY;
1984
1985         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1986                 netif_carrier_off(tp->dev);
1987                 tg3_link_report(tp);
1988         }
1989
1990         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1991             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1992             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1993                 err = tg3_phy_reset_5703_4_5(tp);
1994                 if (err)
1995                         return err;
1996                 goto out;
1997         }
1998
1999         cpmuctrl = 0;
2000         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2001             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2002                 cpmuctrl = tr32(TG3_CPMU_CTRL);
2003                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2004                         tw32(TG3_CPMU_CTRL,
2005                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2006         }
2007
2008         err = tg3_bmcr_reset(tp);
2009         if (err)
2010                 return err;
2011
2012         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2013                 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2014                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2015
2016                 tw32(TG3_CPMU_CTRL, cpmuctrl);
2017         }
2018
2019         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2020             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2021                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2022                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2023                     CPMU_LSPD_1000MB_MACCLK_12_5) {
2024                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2025                         udelay(40);
2026                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2027                 }
2028         }
2029
2030         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2031              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
2032             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2033                 return 0;
2034
2035         tg3_phy_apply_otp(tp);
2036
2037         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2038                 tg3_phy_toggle_apd(tp, true);
2039         else
2040                 tg3_phy_toggle_apd(tp, false);
2041
2042 out:
2043         if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
2044                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2045                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2046                 tg3_phydsp_write(tp, 0x000a, 0x0323);
2047                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2048         }
2049         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2050                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2051                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2052         }
2053         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2054                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2055                 tg3_phydsp_write(tp, 0x000a, 0x310b);
2056                 tg3_phydsp_write(tp, 0x201f, 0x9506);
2057                 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2058                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2059         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2060                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2061                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2062                 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2063                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2064                         tg3_writephy(tp, MII_TG3_TEST1,
2065                                      MII_TG3_TEST1_TRIM_EN | 0x4);
2066                 } else
2067                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2068                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2069         }
2070         /* Set Extended packet length bit (bit 14) on all chips that */
2071         /* support jumbo frames */
2072         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2073                 /* Cannot do read-modify-write on 5401 */
2074                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2075         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2076                 /* Set bit 14 with read-modify-write to preserve other bits */
2077                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2078                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
2079                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000);
2080         }
2081
2082         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2083          * jumbo frames transmission.
2084          */
2085         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2086                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2087                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2088                                      val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2089         }
2090
2091         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2092                 /* adjust output voltage */
2093                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2094         }
2095
2096         tg3_phy_toggle_automdix(tp, 1);
2097         tg3_phy_set_wirespeed(tp);
2098         return 0;
2099 }
2100
2101 static void tg3_frob_aux_power(struct tg3 *tp)
2102 {
2103         struct tg3 *tp_peer = tp;
2104
2105         /* The GPIOs do something completely different on 57765. */
2106         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2107             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2108             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2109                 return;
2110
2111         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2112             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2113             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2114                 struct net_device *dev_peer;
2115
2116                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2117                 /* remove_one() may have been run on the peer. */
2118                 if (!dev_peer)
2119                         tp_peer = tp;
2120                 else
2121                         tp_peer = netdev_priv(dev_peer);
2122         }
2123
2124         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2125             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2126             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2127             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2128                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2129                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2130                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2131                                     (GRC_LCLCTRL_GPIO_OE0 |
2132                                      GRC_LCLCTRL_GPIO_OE1 |
2133                                      GRC_LCLCTRL_GPIO_OE2 |
2134                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2135                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2136                                     100);
2137                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2138                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2139                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2140                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2141                                              GRC_LCLCTRL_GPIO_OE1 |
2142                                              GRC_LCLCTRL_GPIO_OE2 |
2143                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2144                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2145                                              tp->grc_local_ctrl;
2146                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2147
2148                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2149                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2150
2151                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2152                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2153                 } else {
2154                         u32 no_gpio2;
2155                         u32 grc_local_ctrl = 0;
2156
2157                         if (tp_peer != tp &&
2158                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2159                                 return;
2160
2161                         /* Workaround to prevent overdrawing Amps. */
2162                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2163                             ASIC_REV_5714) {
2164                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2165                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2166                                             grc_local_ctrl, 100);
2167                         }
2168
2169                         /* On 5753 and variants, GPIO2 cannot be used. */
2170                         no_gpio2 = tp->nic_sram_data_cfg &
2171                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2172
2173                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2174                                          GRC_LCLCTRL_GPIO_OE1 |
2175                                          GRC_LCLCTRL_GPIO_OE2 |
2176                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2177                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2178                         if (no_gpio2) {
2179                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2180                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2181                         }
2182                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2183                                                     grc_local_ctrl, 100);
2184
2185                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2186
2187                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2188                                                     grc_local_ctrl, 100);
2189
2190                         if (!no_gpio2) {
2191                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2192                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2193                                             grc_local_ctrl, 100);
2194                         }
2195                 }
2196         } else {
2197                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2198                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2199                         if (tp_peer != tp &&
2200                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2201                                 return;
2202
2203                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2204                                     (GRC_LCLCTRL_GPIO_OE1 |
2205                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2206
2207                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2208                                     GRC_LCLCTRL_GPIO_OE1, 100);
2209
2210                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2211                                     (GRC_LCLCTRL_GPIO_OE1 |
2212                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2213                 }
2214         }
2215 }
2216
2217 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2218 {
2219         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2220                 return 1;
2221         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2222                 if (speed != SPEED_10)
2223                         return 1;
2224         } else if (speed == SPEED_10)
2225                 return 1;
2226
2227         return 0;
2228 }
2229
2230 static int tg3_setup_phy(struct tg3 *, int);
2231
2232 #define RESET_KIND_SHUTDOWN     0
2233 #define RESET_KIND_INIT         1
2234 #define RESET_KIND_SUSPEND      2
2235
2236 static void tg3_write_sig_post_reset(struct tg3 *, int);
2237 static int tg3_halt_cpu(struct tg3 *, u32);
2238
2239 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2240 {
2241         u32 val;
2242
2243         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2244                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2245                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2246                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2247
2248                         sg_dig_ctrl |=
2249                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2250                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2251                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2252                 }
2253                 return;
2254         }
2255
2256         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2257                 tg3_bmcr_reset(tp);
2258                 val = tr32(GRC_MISC_CFG);
2259                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2260                 udelay(40);
2261                 return;
2262         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2263                 u32 phytest;
2264                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2265                         u32 phy;
2266
2267                         tg3_writephy(tp, MII_ADVERTISE, 0);
2268                         tg3_writephy(tp, MII_BMCR,
2269                                      BMCR_ANENABLE | BMCR_ANRESTART);
2270
2271                         tg3_writephy(tp, MII_TG3_FET_TEST,
2272                                      phytest | MII_TG3_FET_SHADOW_EN);
2273                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2274                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2275                                 tg3_writephy(tp,
2276                                              MII_TG3_FET_SHDW_AUXMODE4,
2277                                              phy);
2278                         }
2279                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2280                 }
2281                 return;
2282         } else if (do_low_power) {
2283                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2284                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2285
2286                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2287                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2288                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2289                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2290                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2291         }
2292
2293         /* The PHY should not be powered down on some chips because
2294          * of bugs.
2295          */
2296         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2297             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2298             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2299              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2300                 return;
2301
2302         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2303             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2304                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2305                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2306                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2307                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2308         }
2309
2310         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2311 }
2312
2313 /* tp->lock is held. */
2314 static int tg3_nvram_lock(struct tg3 *tp)
2315 {
2316         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2317                 int i;
2318
2319                 if (tp->nvram_lock_cnt == 0) {
2320                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2321                         for (i = 0; i < 8000; i++) {
2322                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2323                                         break;
2324                                 udelay(20);
2325                         }
2326                         if (i == 8000) {
2327                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2328                                 return -ENODEV;
2329                         }
2330                 }
2331                 tp->nvram_lock_cnt++;
2332         }
2333         return 0;
2334 }
2335
2336 /* tp->lock is held. */
2337 static void tg3_nvram_unlock(struct tg3 *tp)
2338 {
2339         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2340                 if (tp->nvram_lock_cnt > 0)
2341                         tp->nvram_lock_cnt--;
2342                 if (tp->nvram_lock_cnt == 0)
2343                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2344         }
2345 }
2346
2347 /* tp->lock is held. */
2348 static void tg3_enable_nvram_access(struct tg3 *tp)
2349 {
2350         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2351             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2352                 u32 nvaccess = tr32(NVRAM_ACCESS);
2353
2354                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2355         }
2356 }
2357
2358 /* tp->lock is held. */
2359 static void tg3_disable_nvram_access(struct tg3 *tp)
2360 {
2361         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2362             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2363                 u32 nvaccess = tr32(NVRAM_ACCESS);
2364
2365                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2366         }
2367 }
2368
2369 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2370                                         u32 offset, u32 *val)
2371 {
2372         u32 tmp;
2373         int i;
2374
2375         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2376                 return -EINVAL;
2377
2378         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2379                                         EEPROM_ADDR_DEVID_MASK |
2380                                         EEPROM_ADDR_READ);
2381         tw32(GRC_EEPROM_ADDR,
2382              tmp |
2383              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2384              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2385               EEPROM_ADDR_ADDR_MASK) |
2386              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2387
2388         for (i = 0; i < 1000; i++) {
2389                 tmp = tr32(GRC_EEPROM_ADDR);
2390
2391                 if (tmp & EEPROM_ADDR_COMPLETE)
2392                         break;
2393                 msleep(1);
2394         }
2395         if (!(tmp & EEPROM_ADDR_COMPLETE))
2396                 return -EBUSY;
2397
2398         tmp = tr32(GRC_EEPROM_DATA);
2399
2400         /*
2401          * The data will always be opposite the native endian
2402          * format.  Perform a blind byteswap to compensate.
2403          */
2404         *val = swab32(tmp);
2405
2406         return 0;
2407 }
2408
2409 #define NVRAM_CMD_TIMEOUT 10000
2410
2411 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2412 {
2413         int i;
2414
2415         tw32(NVRAM_CMD, nvram_cmd);
2416         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2417                 udelay(10);
2418                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2419                         udelay(10);
2420                         break;
2421                 }
2422         }
2423
2424         if (i == NVRAM_CMD_TIMEOUT)
2425                 return -EBUSY;
2426
2427         return 0;
2428 }
2429
2430 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2431 {
2432         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2433             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2434             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2435            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2436             (tp->nvram_jedecnum == JEDEC_ATMEL))
2437
2438                 addr = ((addr / tp->nvram_pagesize) <<
2439                         ATMEL_AT45DB0X1B_PAGE_POS) +
2440                        (addr % tp->nvram_pagesize);
2441
2442         return addr;
2443 }
2444
2445 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2446 {
2447         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2448             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2449             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2450            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2451             (tp->nvram_jedecnum == JEDEC_ATMEL))
2452
2453                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2454                         tp->nvram_pagesize) +
2455                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2456
2457         return addr;
2458 }
2459
2460 /* NOTE: Data read in from NVRAM is byteswapped according to
2461  * the byteswapping settings for all other register accesses.
2462  * tg3 devices are BE devices, so on a BE machine, the data
2463  * returned will be exactly as it is seen in NVRAM.  On a LE
2464  * machine, the 32-bit value will be byteswapped.
2465  */
2466 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2467 {
2468         int ret;
2469
2470         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2471                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2472
2473         offset = tg3_nvram_phys_addr(tp, offset);
2474
2475         if (offset > NVRAM_ADDR_MSK)
2476                 return -EINVAL;
2477
2478         ret = tg3_nvram_lock(tp);
2479         if (ret)
2480                 return ret;
2481
2482         tg3_enable_nvram_access(tp);
2483
2484         tw32(NVRAM_ADDR, offset);
2485         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2486                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2487
2488         if (ret == 0)
2489                 *val = tr32(NVRAM_RDDATA);
2490
2491         tg3_disable_nvram_access(tp);
2492
2493         tg3_nvram_unlock(tp);
2494
2495         return ret;
2496 }
2497
2498 /* Ensures NVRAM data is in bytestream format. */
2499 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2500 {
2501         u32 v;
2502         int res = tg3_nvram_read(tp, offset, &v);
2503         if (!res)
2504                 *val = cpu_to_be32(v);
2505         return res;
2506 }
2507
2508 /* tp->lock is held. */
2509 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2510 {
2511         u32 addr_high, addr_low;
2512         int i;
2513
2514         addr_high = ((tp->dev->dev_addr[0] << 8) |
2515                      tp->dev->dev_addr[1]);
2516         addr_low = ((tp->dev->dev_addr[2] << 24) |
2517                     (tp->dev->dev_addr[3] << 16) |
2518                     (tp->dev->dev_addr[4] <<  8) |
2519                     (tp->dev->dev_addr[5] <<  0));
2520         for (i = 0; i < 4; i++) {
2521                 if (i == 1 && skip_mac_1)
2522                         continue;
2523                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2524                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2525         }
2526
2527         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2528             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2529                 for (i = 0; i < 12; i++) {
2530                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2531                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2532                 }
2533         }
2534
2535         addr_high = (tp->dev->dev_addr[0] +
2536                      tp->dev->dev_addr[1] +
2537                      tp->dev->dev_addr[2] +
2538                      tp->dev->dev_addr[3] +
2539                      tp->dev->dev_addr[4] +
2540                      tp->dev->dev_addr[5]) &
2541                 TX_BACKOFF_SEED_MASK;
2542         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2543 }
2544
2545 static void tg3_enable_register_access(struct tg3 *tp)
2546 {
2547         /*
2548          * Make sure register accesses (indirect or otherwise) will function
2549          * correctly.
2550          */
2551         pci_write_config_dword(tp->pdev,
2552                                TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
2553 }
2554
2555 static int tg3_power_up(struct tg3 *tp)
2556 {
2557         tg3_enable_register_access(tp);
2558
2559         pci_set_power_state(tp->pdev, PCI_D0);
2560
2561         /* Switch out of Vaux if it is a NIC */
2562         if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2563                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2564
2565         return 0;
2566 }
2567
2568 static int tg3_power_down_prepare(struct tg3 *tp)
2569 {
2570         u32 misc_host_ctrl;
2571         bool device_should_wake, do_low_power;
2572
2573         tg3_enable_register_access(tp);
2574
2575         /* Restore the CLKREQ setting. */
2576         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2577                 u16 lnkctl;
2578
2579                 pci_read_config_word(tp->pdev,
2580                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2581                                      &lnkctl);
2582                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2583                 pci_write_config_word(tp->pdev,
2584                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2585                                       lnkctl);
2586         }
2587
2588         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2589         tw32(TG3PCI_MISC_HOST_CTRL,
2590              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2591
2592         device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
2593                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2594
2595         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2596                 do_low_power = false;
2597                 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2598                     !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2599                         struct phy_device *phydev;
2600                         u32 phyid, advertising;
2601
2602                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2603
2604                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2605
2606                         tp->link_config.orig_speed = phydev->speed;
2607                         tp->link_config.orig_duplex = phydev->duplex;
2608                         tp->link_config.orig_autoneg = phydev->autoneg;
2609                         tp->link_config.orig_advertising = phydev->advertising;
2610
2611                         advertising = ADVERTISED_TP |
2612                                       ADVERTISED_Pause |
2613                                       ADVERTISED_Autoneg |
2614                                       ADVERTISED_10baseT_Half;
2615
2616                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2617                             device_should_wake) {
2618                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2619                                         advertising |=
2620                                                 ADVERTISED_100baseT_Half |
2621                                                 ADVERTISED_100baseT_Full |
2622                                                 ADVERTISED_10baseT_Full;
2623                                 else
2624                                         advertising |= ADVERTISED_10baseT_Full;
2625                         }
2626
2627                         phydev->advertising = advertising;
2628
2629                         phy_start_aneg(phydev);
2630
2631                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2632                         if (phyid != PHY_ID_BCMAC131) {
2633                                 phyid &= PHY_BCM_OUI_MASK;
2634                                 if (phyid == PHY_BCM_OUI_1 ||
2635                                     phyid == PHY_BCM_OUI_2 ||
2636                                     phyid == PHY_BCM_OUI_3)
2637                                         do_low_power = true;
2638                         }
2639                 }
2640         } else {
2641                 do_low_power = true;
2642
2643                 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2644                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2645                         tp->link_config.orig_speed = tp->link_config.speed;
2646                         tp->link_config.orig_duplex = tp->link_config.duplex;
2647                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2648                 }
2649
2650                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2651                         tp->link_config.speed = SPEED_10;
2652                         tp->link_config.duplex = DUPLEX_HALF;
2653                         tp->link_config.autoneg = AUTONEG_ENABLE;
2654                         tg3_setup_phy(tp, 0);
2655                 }
2656         }
2657
2658         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2659                 u32 val;
2660
2661                 val = tr32(GRC_VCPU_EXT_CTRL);
2662                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2663         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2664                 int i;
2665                 u32 val;
2666
2667                 for (i = 0; i < 200; i++) {
2668                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2669                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2670                                 break;
2671                         msleep(1);
2672                 }
2673         }
2674         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2675                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2676                                                      WOL_DRV_STATE_SHUTDOWN |
2677                                                      WOL_DRV_WOL |
2678                                                      WOL_SET_MAGIC_PKT);
2679
2680         if (device_should_wake) {
2681                 u32 mac_mode;
2682
2683                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2684                         if (do_low_power) {
2685                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2686                                 udelay(40);
2687                         }
2688
2689                         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2690                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2691                         else
2692                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2693
2694                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2695                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2696                             ASIC_REV_5700) {
2697                                 u32 speed = (tp->tg3_flags &
2698                                              TG3_FLAG_WOL_SPEED_100MB) ?
2699                                              SPEED_100 : SPEED_10;
2700                                 if (tg3_5700_link_polarity(tp, speed))
2701                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2702                                 else
2703                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2704                         }
2705                 } else {
2706                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2707                 }
2708
2709                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2710                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2711
2712                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2713                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2714                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2715                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2716                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2717                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2718
2719                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
2720                         mac_mode |= MAC_MODE_APE_TX_EN |
2721                                     MAC_MODE_APE_RX_EN |
2722                                     MAC_MODE_TDE_ENABLE;
2723
2724                 tw32_f(MAC_MODE, mac_mode);
2725                 udelay(100);
2726
2727                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2728                 udelay(10);
2729         }
2730
2731         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2732             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2733              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2734                 u32 base_val;
2735
2736                 base_val = tp->pci_clock_ctrl;
2737                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2738                              CLOCK_CTRL_TXCLK_DISABLE);
2739
2740                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2741                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2742         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2743                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2744                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2745                 /* do nothing */
2746         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2747                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2748                 u32 newbits1, newbits2;
2749
2750                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2751                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2752                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2753                                     CLOCK_CTRL_TXCLK_DISABLE |
2754                                     CLOCK_CTRL_ALTCLK);
2755                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2756                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2757                         newbits1 = CLOCK_CTRL_625_CORE;
2758                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2759                 } else {
2760                         newbits1 = CLOCK_CTRL_ALTCLK;
2761                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2762                 }
2763
2764                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2765                             40);
2766
2767                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2768                             40);
2769
2770                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2771                         u32 newbits3;
2772
2773                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2774                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2775                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2776                                             CLOCK_CTRL_TXCLK_DISABLE |
2777                                             CLOCK_CTRL_44MHZ_CORE);
2778                         } else {
2779                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2780                         }
2781
2782                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2783                                     tp->pci_clock_ctrl | newbits3, 40);
2784                 }
2785         }
2786
2787         if (!(device_should_wake) &&
2788             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2789                 tg3_power_down_phy(tp, do_low_power);
2790
2791         tg3_frob_aux_power(tp);
2792
2793         /* Workaround for unstable PLL clock */
2794         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2795             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2796                 u32 val = tr32(0x7d00);
2797
2798                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2799                 tw32(0x7d00, val);
2800                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2801                         int err;
2802
2803                         err = tg3_nvram_lock(tp);
2804                         tg3_halt_cpu(tp, RX_CPU_BASE);
2805                         if (!err)
2806                                 tg3_nvram_unlock(tp);
2807                 }
2808         }
2809
2810         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2811
2812         return 0;
2813 }
2814
2815 static void tg3_power_down(struct tg3 *tp)
2816 {
2817         tg3_power_down_prepare(tp);
2818
2819         pci_wake_from_d3(tp->pdev, tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2820         pci_set_power_state(tp->pdev, PCI_D3hot);
2821 }
2822
2823 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2824 {
2825         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2826         case MII_TG3_AUX_STAT_10HALF:
2827                 *speed = SPEED_10;
2828                 *duplex = DUPLEX_HALF;
2829                 break;
2830
2831         case MII_TG3_AUX_STAT_10FULL:
2832                 *speed = SPEED_10;
2833                 *duplex = DUPLEX_FULL;
2834                 break;
2835
2836         case MII_TG3_AUX_STAT_100HALF:
2837                 *speed = SPEED_100;
2838                 *duplex = DUPLEX_HALF;
2839                 break;
2840
2841         case MII_TG3_AUX_STAT_100FULL:
2842                 *speed = SPEED_100;
2843                 *duplex = DUPLEX_FULL;
2844                 break;
2845
2846         case MII_TG3_AUX_STAT_1000HALF:
2847                 *speed = SPEED_1000;
2848                 *duplex = DUPLEX_HALF;
2849                 break;
2850
2851         case MII_TG3_AUX_STAT_1000FULL:
2852                 *speed = SPEED_1000;
2853                 *duplex = DUPLEX_FULL;
2854                 break;
2855
2856         default:
2857                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2858                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2859                                  SPEED_10;
2860                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2861                                   DUPLEX_HALF;
2862                         break;
2863                 }
2864                 *speed = SPEED_INVALID;
2865                 *duplex = DUPLEX_INVALID;
2866                 break;
2867         }
2868 }
2869
2870 static void tg3_phy_copper_begin(struct tg3 *tp)
2871 {
2872         u32 new_adv;
2873         int i;
2874
2875         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2876                 /* Entering low power mode.  Disable gigabit and
2877                  * 100baseT advertisements.
2878                  */
2879                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2880
2881                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2882                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2883                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2884                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2885
2886                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2887         } else if (tp->link_config.speed == SPEED_INVALID) {
2888                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2889                         tp->link_config.advertising &=
2890                                 ~(ADVERTISED_1000baseT_Half |
2891                                   ADVERTISED_1000baseT_Full);
2892
2893                 new_adv = ADVERTISE_CSMA;
2894                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2895                         new_adv |= ADVERTISE_10HALF;
2896                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2897                         new_adv |= ADVERTISE_10FULL;
2898                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2899                         new_adv |= ADVERTISE_100HALF;
2900                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2901                         new_adv |= ADVERTISE_100FULL;
2902
2903                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2904
2905                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2906
2907                 if (tp->link_config.advertising &
2908                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2909                         new_adv = 0;
2910                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2911                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2912                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2913                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2914                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
2915                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2916                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2917                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2918                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2919                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2920                 } else {
2921                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2922                 }
2923         } else {
2924                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2925                 new_adv |= ADVERTISE_CSMA;
2926
2927                 /* Asking for a specific link mode. */
2928                 if (tp->link_config.speed == SPEED_1000) {
2929                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2930
2931                         if (tp->link_config.duplex == DUPLEX_FULL)
2932                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2933                         else
2934                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2935                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2936                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2937                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2938                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2939                 } else {
2940                         if (tp->link_config.speed == SPEED_100) {
2941                                 if (tp->link_config.duplex == DUPLEX_FULL)
2942                                         new_adv |= ADVERTISE_100FULL;
2943                                 else
2944                                         new_adv |= ADVERTISE_100HALF;
2945                         } else {
2946                                 if (tp->link_config.duplex == DUPLEX_FULL)
2947                                         new_adv |= ADVERTISE_10FULL;
2948                                 else
2949                                         new_adv |= ADVERTISE_10HALF;
2950                         }
2951                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2952
2953                         new_adv = 0;
2954                 }
2955
2956                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2957         }
2958
2959         if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
2960                 u32 val;
2961
2962                 tw32(TG3_CPMU_EEE_MODE,
2963                      tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2964
2965                 /* Enable SM_DSP clock and tx 6dB coding. */
2966                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
2967                       MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
2968                       MII_TG3_AUXCTL_ACTL_TX_6DB;
2969                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2970
2971                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2972                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
2973                     !tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
2974                         tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2,
2975                                          val | MII_TG3_DSP_CH34TP2_HIBW01);
2976
2977                 val = 0;
2978                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2979                         /* Advertise 100-BaseTX EEE ability */
2980                         if (tp->link_config.advertising &
2981                             ADVERTISED_100baseT_Full)
2982                                 val |= MDIO_AN_EEE_ADV_100TX;
2983                         /* Advertise 1000-BaseT EEE ability */
2984                         if (tp->link_config.advertising &
2985                             ADVERTISED_1000baseT_Full)
2986                                 val |= MDIO_AN_EEE_ADV_1000T;
2987                 }
2988                 tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
2989
2990                 /* Turn off SM_DSP clock. */
2991                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
2992                       MII_TG3_AUXCTL_ACTL_TX_6DB;
2993                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2994         }
2995
2996         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2997             tp->link_config.speed != SPEED_INVALID) {
2998                 u32 bmcr, orig_bmcr;
2999
3000                 tp->link_config.active_speed = tp->link_config.speed;
3001                 tp->link_config.active_duplex = tp->link_config.duplex;
3002
3003                 bmcr = 0;
3004                 switch (tp->link_config.speed) {
3005                 default:
3006                 case SPEED_10:
3007                         break;
3008
3009                 case SPEED_100:
3010                         bmcr |= BMCR_SPEED100;
3011                         break;
3012
3013                 case SPEED_1000:
3014                         bmcr |= TG3_BMCR_SPEED1000;
3015                         break;
3016                 }
3017
3018                 if (tp->link_config.duplex == DUPLEX_FULL)
3019                         bmcr |= BMCR_FULLDPLX;
3020
3021                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
3022                     (bmcr != orig_bmcr)) {
3023                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
3024                         for (i = 0; i < 1500; i++) {
3025                                 u32 tmp;
3026
3027                                 udelay(10);
3028                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
3029                                     tg3_readphy(tp, MII_BMSR, &tmp))
3030                                         continue;
3031                                 if (!(tmp & BMSR_LSTATUS)) {
3032                                         udelay(40);
3033                                         break;
3034                                 }
3035                         }
3036                         tg3_writephy(tp, MII_BMCR, bmcr);
3037                         udelay(40);
3038                 }
3039         } else {
3040                 tg3_writephy(tp, MII_BMCR,
3041                              BMCR_ANENABLE | BMCR_ANRESTART);
3042         }
3043 }
3044
3045 static int tg3_init_5401phy_dsp(struct tg3 *tp)
3046 {
3047         int err;
3048
3049         /* Turn off tap power management. */
3050         /* Set Extended packet length bit */
3051         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
3052
3053         err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
3054         err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
3055         err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
3056         err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
3057         err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
3058
3059         udelay(40);
3060
3061         return err;
3062 }
3063
3064 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3065 {
3066         u32 adv_reg, all_mask = 0;
3067
3068         if (mask & ADVERTISED_10baseT_Half)
3069                 all_mask |= ADVERTISE_10HALF;
3070         if (mask & ADVERTISED_10baseT_Full)
3071                 all_mask |= ADVERTISE_10FULL;
3072         if (mask & ADVERTISED_100baseT_Half)
3073                 all_mask |= ADVERTISE_100HALF;
3074         if (mask & ADVERTISED_100baseT_Full)
3075                 all_mask |= ADVERTISE_100FULL;
3076
3077         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3078                 return 0;
3079
3080         if ((adv_reg & all_mask) != all_mask)
3081                 return 0;
3082         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3083                 u32 tg3_ctrl;
3084
3085                 all_mask = 0;
3086                 if (mask & ADVERTISED_1000baseT_Half)
3087                         all_mask |= ADVERTISE_1000HALF;
3088                 if (mask & ADVERTISED_1000baseT_Full)
3089                         all_mask |= ADVERTISE_1000FULL;
3090
3091                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3092                         return 0;
3093
3094                 if ((tg3_ctrl & all_mask) != all_mask)
3095                         return 0;
3096         }
3097         return 1;
3098 }
3099
3100 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3101 {
3102         u32 curadv, reqadv;
3103
3104         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3105                 return 1;
3106
3107         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3108         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3109
3110         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3111                 if (curadv != reqadv)
3112                         return 0;
3113
3114                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3115                         tg3_readphy(tp, MII_LPA, rmtadv);
3116         } else {
3117                 /* Reprogram the advertisement register, even if it
3118                  * does not affect the current link.  If the link
3119                  * gets renegotiated in the future, we can save an
3120                  * additional renegotiation cycle by advertising
3121                  * it correctly in the first place.
3122                  */
3123                 if (curadv != reqadv) {
3124                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3125                                      ADVERTISE_PAUSE_ASYM);
3126                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3127                 }
3128         }
3129
3130         return 1;
3131 }
3132
3133 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3134 {
3135         int current_link_up;
3136         u32 bmsr, val;
3137         u32 lcl_adv, rmt_adv;
3138         u16 current_speed;
3139         u8 current_duplex;
3140         int i, err;
3141
3142         tw32(MAC_EVENT, 0);
3143
3144         tw32_f(MAC_STATUS,
3145              (MAC_STATUS_SYNC_CHANGED |
3146               MAC_STATUS_CFG_CHANGED |
3147               MAC_STATUS_MI_COMPLETION |
3148               MAC_STATUS_LNKSTATE_CHANGED));
3149         udelay(40);
3150
3151         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3152                 tw32_f(MAC_MI_MODE,
3153                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3154                 udelay(80);
3155         }
3156
3157         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3158
3159         /* Some third-party PHYs need to be reset on link going
3160          * down.
3161          */
3162         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3163              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3164              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3165             netif_carrier_ok(tp->dev)) {
3166                 tg3_readphy(tp, MII_BMSR, &bmsr);
3167                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3168                     !(bmsr & BMSR_LSTATUS))
3169                         force_reset = 1;
3170         }
3171         if (force_reset)
3172                 tg3_phy_reset(tp);
3173
3174         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3175                 tg3_readphy(tp, MII_BMSR, &bmsr);
3176                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3177                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3178                         bmsr = 0;
3179
3180                 if (!(bmsr & BMSR_LSTATUS)) {
3181                         err = tg3_init_5401phy_dsp(tp);
3182                         if (err)
3183                                 return err;
3184
3185                         tg3_readphy(tp, MII_BMSR, &bmsr);
3186                         for (i = 0; i < 1000; i++) {
3187                                 udelay(10);
3188                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3189                                     (bmsr & BMSR_LSTATUS)) {
3190                                         udelay(40);
3191                                         break;
3192                                 }
3193                         }
3194
3195                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3196                             TG3_PHY_REV_BCM5401_B0 &&
3197                             !(bmsr & BMSR_LSTATUS) &&
3198                             tp->link_config.active_speed == SPEED_1000) {
3199                                 err = tg3_phy_reset(tp);
3200                                 if (!err)
3201                                         err = tg3_init_5401phy_dsp(tp);
3202                                 if (err)
3203                                         return err;
3204                         }
3205                 }
3206         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3207                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3208                 /* 5701 {A0,B0} CRC bug workaround */
3209                 tg3_writephy(tp, 0x15, 0x0a75);
3210                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3211                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3212                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3213         }
3214
3215         /* Clear pending interrupts... */
3216         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3217         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3218
3219         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3220                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3221         else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3222                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3223
3224         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3225             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3226                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3227                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3228                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3229                 else
3230                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3231         }
3232
3233         current_link_up = 0;
3234         current_speed = SPEED_INVALID;
3235         current_duplex = DUPLEX_INVALID;
3236
3237         if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3238                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3239                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3240                 if (!(val & (1 << 10))) {
3241                         val |= (1 << 10);
3242                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3243                         goto relink;
3244                 }
3245         }
3246
3247         bmsr = 0;
3248         for (i = 0; i < 100; i++) {
3249                 tg3_readphy(tp, MII_BMSR, &bmsr);
3250                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3251                     (bmsr & BMSR_LSTATUS))
3252                         break;
3253                 udelay(40);
3254         }
3255
3256         if (bmsr & BMSR_LSTATUS) {
3257                 u32 aux_stat, bmcr;
3258
3259                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3260                 for (i = 0; i < 2000; i++) {
3261                         udelay(10);
3262                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3263                             aux_stat)
3264                                 break;
3265                 }
3266
3267                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3268                                              &current_speed,
3269                                              &current_duplex);
3270
3271                 bmcr = 0;
3272                 for (i = 0; i < 200; i++) {
3273                         tg3_readphy(tp, MII_BMCR, &bmcr);
3274                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3275                                 continue;
3276                         if (bmcr && bmcr != 0x7fff)
3277                                 break;
3278                         udelay(10);
3279                 }
3280
3281                 lcl_adv = 0;
3282                 rmt_adv = 0;
3283
3284                 tp->link_config.active_speed = current_speed;
3285                 tp->link_config.active_duplex = current_duplex;
3286
3287                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3288                         if ((bmcr & BMCR_ANENABLE) &&
3289                             tg3_copper_is_advertising_all(tp,
3290                                                 tp->link_config.advertising)) {
3291                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3292                                                                   &rmt_adv))
3293                                         current_link_up = 1;
3294                         }
3295                 } else {
3296                         if (!(bmcr & BMCR_ANENABLE) &&
3297                             tp->link_config.speed == current_speed &&
3298                             tp->link_config.duplex == current_duplex &&
3299                             tp->link_config.flowctrl ==
3300                             tp->link_config.active_flowctrl) {
3301                                 current_link_up = 1;
3302                         }
3303                 }
3304
3305                 if (current_link_up == 1 &&
3306                     tp->link_config.active_duplex == DUPLEX_FULL)
3307                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3308         }
3309
3310 relink:
3311         if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3312                 tg3_phy_copper_begin(tp);
3313
3314                 tg3_readphy(tp, MII_BMSR, &bmsr);
3315                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3316                     (bmsr & BMSR_LSTATUS))
3317                         current_link_up = 1;
3318         }
3319
3320         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3321         if (current_link_up == 1) {
3322                 if (tp->link_config.active_speed == SPEED_100 ||
3323                     tp->link_config.active_speed == SPEED_10)
3324                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3325                 else
3326                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3327         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3328                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3329         else
3330                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3331
3332         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3333         if (tp->link_config.active_duplex == DUPLEX_HALF)
3334                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3335
3336         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3337                 if (current_link_up == 1 &&
3338                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3339                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3340                 else
3341                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3342         }
3343
3344         /* ??? Without this setting Netgear GA302T PHY does not
3345          * ??? send/receive packets...
3346          */
3347         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3348             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3349                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3350                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3351                 udelay(80);
3352         }
3353
3354         tw32_f(MAC_MODE, tp->mac_mode);
3355         udelay(40);
3356
3357         tg3_phy_eee_adjust(tp, current_link_up);
3358
3359         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3360                 /* Polled via timer. */
3361                 tw32_f(MAC_EVENT, 0);
3362         } else {
3363                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3364         }
3365         udelay(40);
3366
3367         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3368             current_link_up == 1 &&
3369             tp->link_config.active_speed == SPEED_1000 &&
3370             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3371              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3372                 udelay(120);
3373                 tw32_f(MAC_STATUS,
3374                      (MAC_STATUS_SYNC_CHANGED |
3375                       MAC_STATUS_CFG_CHANGED));
3376                 udelay(40);
3377                 tg3_write_mem(tp,
3378                               NIC_SRAM_FIRMWARE_MBOX,
3379                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3380         }
3381
3382         /* Prevent send BD corruption. */
3383         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3384                 u16 oldlnkctl, newlnkctl;
3385
3386                 pci_read_config_word(tp->pdev,
3387                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3388                                      &oldlnkctl);
3389                 if (tp->link_config.active_speed == SPEED_100 ||
3390                     tp->link_config.active_speed == SPEED_10)
3391                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3392                 else
3393                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3394                 if (newlnkctl != oldlnkctl)
3395                         pci_write_config_word(tp->pdev,
3396                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3397                                               newlnkctl);
3398         }
3399
3400         if (current_link_up != netif_carrier_ok(tp->dev)) {
3401                 if (current_link_up)
3402                         netif_carrier_on(tp->dev);
3403                 else
3404                         netif_carrier_off(tp->dev);
3405                 tg3_link_report(tp);
3406         }
3407
3408         return 0;
3409 }
3410
3411 struct tg3_fiber_aneginfo {
3412         int state;
3413 #define ANEG_STATE_UNKNOWN              0
3414 #define ANEG_STATE_AN_ENABLE            1
3415 #define ANEG_STATE_RESTART_INIT         2
3416 #define ANEG_STATE_RESTART              3
3417 #define ANEG_STATE_DISABLE_LINK_OK      4
3418 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3419 #define ANEG_STATE_ABILITY_DETECT       6
3420 #define ANEG_STATE_ACK_DETECT_INIT      7
3421 #define ANEG_STATE_ACK_DETECT           8
3422 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3423 #define ANEG_STATE_COMPLETE_ACK         10
3424 #define ANEG_STATE_IDLE_DETECT_INIT     11
3425 #define ANEG_STATE_IDLE_DETECT          12
3426 #define ANEG_STATE_LINK_OK              13
3427 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3428 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3429
3430         u32 flags;
3431 #define MR_AN_ENABLE            0x00000001
3432 #define MR_RESTART_AN           0x00000002
3433 #define MR_AN_COMPLETE          0x00000004
3434 #define MR_PAGE_RX              0x00000008
3435 #define MR_NP_LOADED            0x00000010
3436 #define MR_TOGGLE_TX            0x00000020
3437 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3438 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3439 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3440 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3441 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3442 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3443 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3444 #define MR_TOGGLE_RX            0x00002000
3445 #define MR_NP_RX                0x00004000
3446
3447 #define MR_LINK_OK              0x80000000
3448
3449         unsigned long link_time, cur_time;
3450
3451         u32 ability_match_cfg;
3452         int ability_match_count;
3453
3454         char ability_match, idle_match, ack_match;
3455
3456         u32 txconfig, rxconfig;
3457 #define ANEG_CFG_NP             0x00000080
3458 #define ANEG_CFG_ACK            0x00000040
3459 #define ANEG_CFG_RF2            0x00000020
3460 #define ANEG_CFG_RF1            0x00000010
3461 #define ANEG_CFG_PS2            0x00000001
3462 #define ANEG_CFG_PS1            0x00008000
3463 #define ANEG_CFG_HD             0x00004000
3464 #define ANEG_CFG_FD             0x00002000
3465 #define ANEG_CFG_INVAL          0x00001f06
3466
3467 };
3468 #define ANEG_OK         0
3469 #define ANEG_DONE       1
3470 #define ANEG_TIMER_ENAB 2
3471 #define ANEG_FAILED     -1
3472
3473 #define ANEG_STATE_SETTLE_TIME  10000
3474
3475 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3476                                    struct tg3_fiber_aneginfo *ap)
3477 {
3478         u16 flowctrl;
3479         unsigned long delta;
3480         u32 rx_cfg_reg;
3481         int ret;
3482
3483         if (ap->state == ANEG_STATE_UNKNOWN) {
3484                 ap->rxconfig = 0;
3485                 ap->link_time = 0;
3486                 ap->cur_time = 0;
3487                 ap->ability_match_cfg = 0;
3488                 ap->ability_match_count = 0;
3489                 ap->ability_match = 0;
3490                 ap->idle_match = 0;
3491                 ap->ack_match = 0;
3492         }
3493         ap->cur_time++;
3494
3495         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3496                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3497
3498                 if (rx_cfg_reg != ap->ability_match_cfg) {
3499                         ap->ability_match_cfg = rx_cfg_reg;
3500                         ap->ability_match = 0;
3501                         ap->ability_match_count = 0;
3502                 } else {
3503                         if (++ap->ability_match_count > 1) {
3504                                 ap->ability_match = 1;
3505                                 ap->ability_match_cfg = rx_cfg_reg;
3506                         }
3507                 }
3508                 if (rx_cfg_reg & ANEG_CFG_ACK)
3509                         ap->ack_match = 1;
3510                 else
3511                         ap->ack_match = 0;
3512
3513                 ap->idle_match = 0;
3514         } else {
3515                 ap->idle_match = 1;
3516                 ap->ability_match_cfg = 0;
3517                 ap->ability_match_count = 0;
3518                 ap->ability_match = 0;
3519                 ap->ack_match = 0;
3520
3521                 rx_cfg_reg = 0;
3522         }
3523
3524         ap->rxconfig = rx_cfg_reg;
3525         ret = ANEG_OK;
3526
3527         switch (ap->state) {
3528         case ANEG_STATE_UNKNOWN:
3529                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3530                         ap->state = ANEG_STATE_AN_ENABLE;
3531
3532                 /* fallthru */
3533         case ANEG_STATE_AN_ENABLE:
3534                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3535                 if (ap->flags & MR_AN_ENABLE) {
3536                         ap->link_time = 0;
3537                         ap->cur_time = 0;
3538                         ap->ability_match_cfg = 0;
3539                         ap->ability_match_count = 0;
3540                         ap->ability_match = 0;
3541                         ap->idle_match = 0;
3542                         ap->ack_match = 0;
3543
3544                         ap->state = ANEG_STATE_RESTART_INIT;
3545                 } else {
3546                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3547                 }
3548                 break;
3549
3550         case ANEG_STATE_RESTART_INIT:
3551                 ap->link_time = ap->cur_time;
3552                 ap->flags &= ~(MR_NP_LOADED);
3553                 ap->txconfig = 0;
3554                 tw32(MAC_TX_AUTO_NEG, 0);
3555                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3556                 tw32_f(MAC_MODE, tp->mac_mode);
3557                 udelay(40);
3558
3559                 ret = ANEG_TIMER_ENAB;
3560                 ap->state = ANEG_STATE_RESTART;
3561
3562                 /* fallthru */
3563         case ANEG_STATE_RESTART:
3564                 delta = ap->cur_time - ap->link_time;
3565                 if (delta > ANEG_STATE_SETTLE_TIME)
3566                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3567                 else
3568                         ret = ANEG_TIMER_ENAB;
3569                 break;
3570
3571         case ANEG_STATE_DISABLE_LINK_OK:
3572                 ret = ANEG_DONE;
3573                 break;
3574
3575         case ANEG_STATE_ABILITY_DETECT_INIT:
3576                 ap->flags &= ~(MR_TOGGLE_TX);
3577                 ap->txconfig = ANEG_CFG_FD;
3578                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3579                 if (flowctrl & ADVERTISE_1000XPAUSE)
3580                         ap->txconfig |= ANEG_CFG_PS1;
3581                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3582                         ap->txconfig |= ANEG_CFG_PS2;
3583                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3584                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3585                 tw32_f(MAC_MODE, tp->mac_mode);
3586                 udelay(40);
3587
3588                 ap->state = ANEG_STATE_ABILITY_DETECT;
3589                 break;
3590
3591         case ANEG_STATE_ABILITY_DETECT:
3592                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3593                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3594                 break;
3595
3596         case ANEG_STATE_ACK_DETECT_INIT:
3597                 ap->txconfig |= ANEG_CFG_ACK;
3598                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3599                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3600                 tw32_f(MAC_MODE, tp->mac_mode);
3601                 udelay(40);
3602
3603                 ap->state = ANEG_STATE_ACK_DETECT;
3604
3605                 /* fallthru */
3606         case ANEG_STATE_ACK_DETECT:
3607                 if (ap->ack_match != 0) {
3608                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3609                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3610                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3611                         } else {
3612                                 ap->state = ANEG_STATE_AN_ENABLE;
3613                         }
3614                 } else if (ap->ability_match != 0 &&
3615                            ap->rxconfig == 0) {
3616                         ap->state = ANEG_STATE_AN_ENABLE;
3617                 }
3618                 break;
3619
3620         case ANEG_STATE_COMPLETE_ACK_INIT:
3621                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3622                         ret = ANEG_FAILED;
3623                         break;
3624                 }
3625                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3626                                MR_LP_ADV_HALF_DUPLEX |
3627                                MR_LP_ADV_SYM_PAUSE |
3628                                MR_LP_ADV_ASYM_PAUSE |
3629                                MR_LP_ADV_REMOTE_FAULT1 |
3630                                MR_LP_ADV_REMOTE_FAULT2 |
3631                                MR_LP_ADV_NEXT_PAGE |
3632                                MR_TOGGLE_RX |
3633                                MR_NP_RX);
3634                 if (ap->rxconfig & ANEG_CFG_FD)
3635                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3636                 if (ap->rxconfig & ANEG_CFG_HD)
3637                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3638                 if (ap->rxconfig & ANEG_CFG_PS1)
3639                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3640                 if (ap->rxconfig & ANEG_CFG_PS2)
3641                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3642                 if (ap->rxconfig & ANEG_CFG_RF1)
3643                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3644                 if (ap->rxconfig & ANEG_CFG_RF2)
3645                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3646                 if (ap->rxconfig & ANEG_CFG_NP)
3647                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3648
3649                 ap->link_time = ap->cur_time;
3650
3651                 ap->flags ^= (MR_TOGGLE_TX);
3652                 if (ap->rxconfig & 0x0008)
3653                         ap->flags |= MR_TOGGLE_RX;
3654                 if (ap->rxconfig & ANEG_CFG_NP)
3655                         ap->flags |= MR_NP_RX;
3656                 ap->flags |= MR_PAGE_RX;
3657
3658                 ap->state = ANEG_STATE_COMPLETE_ACK;
3659                 ret = ANEG_TIMER_ENAB;
3660                 break;
3661
3662         case ANEG_STATE_COMPLETE_ACK:
3663                 if (ap->ability_match != 0 &&
3664                     ap->rxconfig == 0) {
3665                         ap->state = ANEG_STATE_AN_ENABLE;
3666                         break;
3667                 }
3668                 delta = ap->cur_time - ap->link_time;
3669                 if (delta > ANEG_STATE_SETTLE_TIME) {
3670                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3671                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3672                         } else {
3673                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3674                                     !(ap->flags & MR_NP_RX)) {
3675                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3676                                 } else {
3677                                         ret = ANEG_FAILED;
3678                                 }
3679                         }
3680                 }
3681                 break;
3682
3683         case ANEG_STATE_IDLE_DETECT_INIT:
3684                 ap->link_time = ap->cur_time;
3685                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3686                 tw32_f(MAC_MODE, tp->mac_mode);
3687                 udelay(40);
3688
3689                 ap->state = ANEG_STATE_IDLE_DETECT;
3690                 ret = ANEG_TIMER_ENAB;
3691                 break;
3692
3693         case ANEG_STATE_IDLE_DETECT:
3694                 if (ap->ability_match != 0 &&
3695                     ap->rxconfig == 0) {
3696                         ap->state = ANEG_STATE_AN_ENABLE;
3697                         break;
3698                 }
3699                 delta = ap->cur_time - ap->link_time;
3700                 if (delta > ANEG_STATE_SETTLE_TIME) {
3701                         /* XXX another gem from the Broadcom driver :( */
3702                         ap->state = ANEG_STATE_LINK_OK;
3703                 }
3704                 break;
3705
3706         case ANEG_STATE_LINK_OK:
3707                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3708                 ret = ANEG_DONE;
3709                 break;
3710
3711         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3712                 /* ??? unimplemented */
3713                 break;
3714
3715         case ANEG_STATE_NEXT_PAGE_WAIT:
3716                 /* ??? unimplemented */
3717                 break;
3718
3719         default:
3720                 ret = ANEG_FAILED;
3721                 break;
3722         }
3723
3724         return ret;
3725 }
3726
3727 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3728 {
3729         int res = 0;
3730         struct tg3_fiber_aneginfo aninfo;
3731         int status = ANEG_FAILED;
3732         unsigned int tick;
3733         u32 tmp;
3734
3735         tw32_f(MAC_TX_AUTO_NEG, 0);
3736
3737         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3738         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3739         udelay(40);
3740
3741         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3742         udelay(40);
3743
3744         memset(&aninfo, 0, sizeof(aninfo));
3745         aninfo.flags |= MR_AN_ENABLE;
3746         aninfo.state = ANEG_STATE_UNKNOWN;
3747         aninfo.cur_time = 0;
3748         tick = 0;
3749         while (++tick < 195000) {
3750                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3751                 if (status == ANEG_DONE || status == ANEG_FAILED)
3752                         break;
3753
3754                 udelay(1);
3755         }
3756
3757         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3758         tw32_f(MAC_MODE, tp->mac_mode);
3759         udelay(40);
3760
3761         *txflags = aninfo.txconfig;
3762         *rxflags = aninfo.flags;
3763
3764         if (status == ANEG_DONE &&
3765             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3766                              MR_LP_ADV_FULL_DUPLEX)))
3767                 res = 1;
3768
3769         return res;
3770 }
3771
3772 static void tg3_init_bcm8002(struct tg3 *tp)
3773 {
3774         u32 mac_status = tr32(MAC_STATUS);
3775         int i;
3776
3777         /* Reset when initting first time or we have a link. */
3778         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3779             !(mac_status & MAC_STATUS_PCS_SYNCED))
3780                 return;
3781
3782         /* Set PLL lock range. */
3783         tg3_writephy(tp, 0x16, 0x8007);
3784
3785         /* SW reset */
3786         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3787
3788         /* Wait for reset to complete. */
3789         /* XXX schedule_timeout() ... */
3790         for (i = 0; i < 500; i++)
3791                 udelay(10);
3792
3793         /* Config mode; select PMA/Ch 1 regs. */
3794         tg3_writephy(tp, 0x10, 0x8411);
3795
3796         /* Enable auto-lock and comdet, select txclk for tx. */
3797         tg3_writephy(tp, 0x11, 0x0a10);
3798
3799         tg3_writephy(tp, 0x18, 0x00a0);
3800         tg3_writephy(tp, 0x16, 0x41ff);
3801
3802         /* Assert and deassert POR. */
3803         tg3_writephy(tp, 0x13, 0x0400);
3804         udelay(40);
3805         tg3_writephy(tp, 0x13, 0x0000);
3806
3807         tg3_writephy(tp, 0x11, 0x0a50);
3808         udelay(40);
3809         tg3_writephy(tp, 0x11, 0x0a10);
3810
3811         /* Wait for signal to stabilize */
3812         /* XXX schedule_timeout() ... */
3813         for (i = 0; i < 15000; i++)
3814                 udelay(10);
3815
3816         /* Deselect the channel register so we can read the PHYID
3817          * later.
3818          */
3819         tg3_writephy(tp, 0x10, 0x8011);
3820 }
3821
3822 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3823 {
3824         u16 flowctrl;
3825         u32 sg_dig_ctrl, sg_dig_status;
3826         u32 serdes_cfg, expected_sg_dig_ctrl;
3827         int workaround, port_a;
3828         int current_link_up;
3829
3830         serdes_cfg = 0;
3831         expected_sg_dig_ctrl = 0;
3832         workaround = 0;
3833         port_a = 1;
3834         current_link_up = 0;
3835
3836         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3837             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3838                 workaround = 1;
3839                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3840                         port_a = 0;
3841
3842                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3843                 /* preserve bits 20-23 for voltage regulator */
3844                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3845         }
3846
3847         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3848
3849         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3850                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3851                         if (workaround) {
3852                                 u32 val = serdes_cfg;
3853
3854                                 if (port_a)
3855                                         val |= 0xc010000;
3856                                 else
3857                                         val |= 0x4010000;
3858                                 tw32_f(MAC_SERDES_CFG, val);
3859                         }
3860
3861                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3862                 }
3863                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3864                         tg3_setup_flow_control(tp, 0, 0);
3865                         current_link_up = 1;
3866                 }
3867                 goto out;
3868         }
3869
3870         /* Want auto-negotiation.  */
3871         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3872
3873         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3874         if (flowctrl & ADVERTISE_1000XPAUSE)
3875                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3876         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3877                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3878
3879         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3880                 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3881                     tp->serdes_counter &&
3882                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3883                                     MAC_STATUS_RCVD_CFG)) ==
3884                      MAC_STATUS_PCS_SYNCED)) {
3885                         tp->serdes_counter--;
3886                         current_link_up = 1;
3887                         goto out;
3888                 }
3889 restart_autoneg:
3890                 if (workaround)
3891                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3892                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3893                 udelay(5);
3894                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3895
3896                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3897                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3898         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3899                                  MAC_STATUS_SIGNAL_DET)) {
3900                 sg_dig_status = tr32(SG_DIG_STATUS);
3901                 mac_status = tr32(MAC_STATUS);
3902
3903                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3904                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3905                         u32 local_adv = 0, remote_adv = 0;
3906
3907                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3908                                 local_adv |= ADVERTISE_1000XPAUSE;
3909                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3910                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3911
3912                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3913                                 remote_adv |= LPA_1000XPAUSE;
3914                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3915                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3916
3917                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3918                         current_link_up = 1;
3919                         tp->serdes_counter = 0;
3920                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3921                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3922                         if (tp->serdes_counter)
3923                                 tp->serdes_counter--;
3924                         else {
3925                                 if (workaround) {
3926                                         u32 val = serdes_cfg;
3927
3928                                         if (port_a)
3929                                                 val |= 0xc010000;
3930                                         else
3931                                                 val |= 0x4010000;
3932
3933                                         tw32_f(MAC_SERDES_CFG, val);
3934                                 }
3935
3936                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3937                                 udelay(40);
3938
3939                                 /* Link parallel detection - link is up */
3940                                 /* only if we have PCS_SYNC and not */
3941                                 /* receiving config code words */
3942                                 mac_status = tr32(MAC_STATUS);
3943                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3944                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3945                                         tg3_setup_flow_control(tp, 0, 0);
3946                                         current_link_up = 1;
3947                                         tp->phy_flags |=
3948                                                 TG3_PHYFLG_PARALLEL_DETECT;
3949                                         tp->serdes_counter =
3950                                                 SERDES_PARALLEL_DET_TIMEOUT;
3951                                 } else
3952                                         goto restart_autoneg;
3953                         }
3954                 }
3955         } else {
3956                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3957                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3958         }
3959
3960 out:
3961         return current_link_up;
3962 }
3963
3964 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3965 {
3966         int current_link_up = 0;
3967
3968         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3969                 goto out;
3970
3971         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3972                 u32 txflags, rxflags;
3973                 int i;
3974
3975                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3976                         u32 local_adv = 0, remote_adv = 0;
3977
3978                         if (txflags & ANEG_CFG_PS1)
3979                                 local_adv |= ADVERTISE_1000XPAUSE;
3980                         if (txflags & ANEG_CFG_PS2)
3981                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3982
3983                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3984                                 remote_adv |= LPA_1000XPAUSE;
3985                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3986                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3987
3988                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3989
3990                         current_link_up = 1;
3991                 }
3992                 for (i = 0; i < 30; i++) {
3993                         udelay(20);
3994                         tw32_f(MAC_STATUS,
3995                                (MAC_STATUS_SYNC_CHANGED |
3996                                 MAC_STATUS_CFG_CHANGED));
3997                         udelay(40);
3998                         if ((tr32(MAC_STATUS) &
3999                              (MAC_STATUS_SYNC_CHANGED |
4000                               MAC_STATUS_CFG_CHANGED)) == 0)
4001                                 break;
4002                 }
4003
4004                 mac_status = tr32(MAC_STATUS);
4005                 if (current_link_up == 0 &&
4006                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
4007                     !(mac_status & MAC_STATUS_RCVD_CFG))
4008                         current_link_up = 1;
4009         } else {
4010                 tg3_setup_flow_control(tp, 0, 0);
4011
4012                 /* Forcing 1000FD link up. */
4013                 current_link_up = 1;
4014
4015                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
4016                 udelay(40);
4017
4018                 tw32_f(MAC_MODE, tp->mac_mode);
4019                 udelay(40);
4020         }
4021
4022 out:
4023         return current_link_up;
4024 }
4025
4026 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4027 {
4028         u32 orig_pause_cfg;
4029         u16 orig_active_speed;
4030         u8 orig_active_duplex;
4031         u32 mac_status;
4032         int current_link_up;
4033         int i;
4034
4035         orig_pause_cfg = tp->link_config.active_flowctrl;
4036         orig_active_speed = tp->link_config.active_speed;
4037         orig_active_duplex = tp->link_config.active_duplex;
4038
4039         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
4040             netif_carrier_ok(tp->dev) &&
4041             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
4042                 mac_status = tr32(MAC_STATUS);
4043                 mac_status &= (MAC_STATUS_PCS_SYNCED |
4044                                MAC_STATUS_SIGNAL_DET |
4045                                MAC_STATUS_CFG_CHANGED |
4046                                MAC_STATUS_RCVD_CFG);
4047                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
4048                                    MAC_STATUS_SIGNAL_DET)) {
4049                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4050                                             MAC_STATUS_CFG_CHANGED));
4051                         return 0;
4052                 }
4053         }
4054
4055         tw32_f(MAC_TX_AUTO_NEG, 0);
4056
4057         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
4058         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
4059         tw32_f(MAC_MODE, tp->mac_mode);
4060         udelay(40);
4061
4062         if (tp->phy_id == TG3_PHY_ID_BCM8002)
4063                 tg3_init_bcm8002(tp);
4064
4065         /* Enable link change event even when serdes polling.  */
4066         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4067         udelay(40);
4068
4069         current_link_up = 0;
4070         mac_status = tr32(MAC_STATUS);
4071
4072         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
4073                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4074         else
4075                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4076
4077         tp->napi[0].hw_status->status =
4078                 (SD_STATUS_UPDATED |
4079                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4080
4081         for (i = 0; i < 100; i++) {
4082                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4083                                     MAC_STATUS_CFG_CHANGED));
4084                 udelay(5);
4085                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4086                                          MAC_STATUS_CFG_CHANGED |
4087                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4088                         break;
4089         }
4090
4091         mac_status = tr32(MAC_STATUS);
4092         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4093                 current_link_up = 0;
4094                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4095                     tp->serdes_counter == 0) {
4096                         tw32_f(MAC_MODE, (tp->mac_mode |
4097                                           MAC_MODE_SEND_CONFIGS));
4098                         udelay(1);
4099                         tw32_f(MAC_MODE, tp->mac_mode);
4100                 }
4101         }
4102
4103         if (current_link_up == 1) {
4104                 tp->link_config.active_speed = SPEED_1000;
4105                 tp->link_config.active_duplex = DUPLEX_FULL;
4106                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4107                                     LED_CTRL_LNKLED_OVERRIDE |
4108                                     LED_CTRL_1000MBPS_ON));
4109         } else {
4110                 tp->link_config.active_speed = SPEED_INVALID;
4111                 tp->link_config.active_duplex = DUPLEX_INVALID;
4112                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4113                                     LED_CTRL_LNKLED_OVERRIDE |
4114                                     LED_CTRL_TRAFFIC_OVERRIDE));
4115         }
4116
4117         if (current_link_up != netif_carrier_ok(tp->dev)) {
4118                 if (current_link_up)
4119                         netif_carrier_on(tp->dev);
4120                 else
4121                         netif_carrier_off(tp->dev);
4122                 tg3_link_report(tp);
4123         } else {
4124                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4125                 if (orig_pause_cfg != now_pause_cfg ||
4126                     orig_active_speed != tp->link_config.active_speed ||
4127                     orig_active_duplex != tp->link_config.active_duplex)
4128                         tg3_link_report(tp);
4129         }
4130
4131         return 0;
4132 }
4133
4134 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4135 {
4136         int current_link_up, err = 0;
4137         u32 bmsr, bmcr;
4138         u16 current_speed;
4139         u8 current_duplex;
4140         u32 local_adv, remote_adv;
4141
4142         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4143         tw32_f(MAC_MODE, tp->mac_mode);
4144         udelay(40);
4145
4146         tw32(MAC_EVENT, 0);
4147
4148         tw32_f(MAC_STATUS,
4149              (MAC_STATUS_SYNC_CHANGED |
4150               MAC_STATUS_CFG_CHANGED |
4151               MAC_STATUS_MI_COMPLETION |
4152               MAC_STATUS_LNKSTATE_CHANGED));
4153         udelay(40);
4154
4155         if (force_reset)
4156                 tg3_phy_reset(tp);
4157
4158         current_link_up = 0;
4159         current_speed = SPEED_INVALID;
4160         current_duplex = DUPLEX_INVALID;
4161
4162         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4163         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4164         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4165                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4166                         bmsr |= BMSR_LSTATUS;
4167                 else
4168                         bmsr &= ~BMSR_LSTATUS;
4169         }
4170
4171         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4172
4173         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4174             (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4175                 /* do nothing, just check for link up at the end */
4176         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4177                 u32 adv, new_adv;
4178
4179                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4180                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4181                                   ADVERTISE_1000XPAUSE |
4182                                   ADVERTISE_1000XPSE_ASYM |
4183                                   ADVERTISE_SLCT);
4184
4185                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4186
4187                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4188                         new_adv |= ADVERTISE_1000XHALF;
4189                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4190                         new_adv |= ADVERTISE_1000XFULL;
4191
4192                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4193                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4194                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4195                         tg3_writephy(tp, MII_BMCR, bmcr);
4196
4197                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4198                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4199                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4200
4201                         return err;
4202                 }
4203         } else {
4204                 u32 new_bmcr;
4205
4206                 bmcr &= ~BMCR_SPEED1000;
4207                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4208
4209                 if (tp->link_config.duplex == DUPLEX_FULL)
4210                         new_bmcr |= BMCR_FULLDPLX;
4211
4212                 if (new_bmcr != bmcr) {
4213                         /* BMCR_SPEED1000 is a reserved bit that needs
4214                          * to be set on write.
4215                          */
4216                         new_bmcr |= BMCR_SPEED1000;
4217
4218                         /* Force a linkdown */
4219                         if (netif_carrier_ok(tp->dev)) {
4220                                 u32 adv;
4221
4222                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4223                                 adv &= ~(ADVERTISE_1000XFULL |
4224                                          ADVERTISE_1000XHALF |
4225                                          ADVERTISE_SLCT);
4226                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4227                                 tg3_writephy(tp, MII_BMCR, bmcr |
4228                                                            BMCR_ANRESTART |
4229                                                            BMCR_ANENABLE);
4230                                 udelay(10);
4231                                 netif_carrier_off(tp->dev);
4232                         }
4233                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4234                         bmcr = new_bmcr;
4235                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4236                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4237                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4238                             ASIC_REV_5714) {
4239                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4240                                         bmsr |= BMSR_LSTATUS;
4241                                 else
4242                                         bmsr &= ~BMSR_LSTATUS;
4243                         }
4244                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4245                 }
4246         }
4247
4248         if (bmsr & BMSR_LSTATUS) {
4249                 current_speed = SPEED_1000;
4250                 current_link_up = 1;
4251                 if (bmcr & BMCR_FULLDPLX)
4252                         current_duplex = DUPLEX_FULL;
4253                 else
4254                         current_duplex = DUPLEX_HALF;
4255
4256                 local_adv = 0;
4257                 remote_adv = 0;
4258
4259                 if (bmcr & BMCR_ANENABLE) {
4260                         u32 common;
4261
4262                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4263                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4264                         common = local_adv & remote_adv;
4265                         if (common & (ADVERTISE_1000XHALF |
4266                                       ADVERTISE_1000XFULL)) {
4267                                 if (common & ADVERTISE_1000XFULL)
4268                                         current_duplex = DUPLEX_FULL;
4269                                 else
4270                                         current_duplex = DUPLEX_HALF;
4271                         } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4272                                 /* Link is up via parallel detect */
4273                         } else {
4274                                 current_link_up = 0;
4275                         }
4276                 }
4277         }
4278
4279         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4280                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4281
4282         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4283         if (tp->link_config.active_duplex == DUPLEX_HALF)
4284                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4285
4286         tw32_f(MAC_MODE, tp->mac_mode);
4287         udelay(40);
4288
4289         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4290
4291         tp->link_config.active_speed = current_speed;
4292         tp->link_config.active_duplex = current_duplex;
4293
4294         if (current_link_up != netif_carrier_ok(tp->dev)) {
4295                 if (current_link_up)
4296                         netif_carrier_on(tp->dev);
4297                 else {
4298                         netif_carrier_off(tp->dev);
4299                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4300                 }
4301                 tg3_link_report(tp);
4302         }
4303         return err;
4304 }
4305
4306 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4307 {
4308         if (tp->serdes_counter) {
4309                 /* Give autoneg time to complete. */
4310                 tp->serdes_counter--;
4311                 return;
4312         }
4313
4314         if (!netif_carrier_ok(tp->dev) &&
4315             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4316                 u32 bmcr;
4317
4318                 tg3_readphy(tp, MII_BMCR, &bmcr);
4319                 if (bmcr & BMCR_ANENABLE) {
4320                         u32 phy1, phy2;
4321
4322                         /* Select shadow register 0x1f */
4323                         tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4324                         tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4325
4326                         /* Select expansion interrupt status register */
4327                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4328                                          MII_TG3_DSP_EXP1_INT_STAT);
4329                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4330                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4331
4332                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4333                                 /* We have signal detect and not receiving
4334                                  * config code words, link is up by parallel
4335                                  * detection.
4336                                  */
4337
4338                                 bmcr &= ~BMCR_ANENABLE;
4339                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4340                                 tg3_writephy(tp, MII_BMCR, bmcr);
4341                                 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4342                         }
4343                 }
4344         } else if (netif_carrier_ok(tp->dev) &&
4345                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4346                    (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4347                 u32 phy2;
4348
4349                 /* Select expansion interrupt status register */
4350                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4351                                  MII_TG3_DSP_EXP1_INT_STAT);
4352                 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4353                 if (phy2 & 0x20) {
4354                         u32 bmcr;
4355
4356                         /* Config code words received, turn on autoneg. */
4357                         tg3_readphy(tp, MII_BMCR, &bmcr);
4358                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4359
4360                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4361
4362                 }
4363         }
4364 }
4365
4366 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4367 {
4368         int err;
4369
4370         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4371                 err = tg3_setup_fiber_phy(tp, force_reset);
4372         else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4373                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4374         else
4375                 err = tg3_setup_copper_phy(tp, force_reset);
4376
4377         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4378                 u32 val, scale;
4379
4380                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4381                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4382                         scale = 65;
4383                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4384                         scale = 6;
4385                 else
4386                         scale = 12;
4387
4388                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4389                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4390                 tw32(GRC_MISC_CFG, val);
4391         }
4392
4393         if (tp->link_config.active_speed == SPEED_1000 &&
4394             tp->link_config.active_duplex == DUPLEX_HALF)
4395                 tw32(MAC_TX_LENGTHS,
4396                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4397                       (6 << TX_LENGTHS_IPG_SHIFT) |
4398                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4399         else
4400                 tw32(MAC_TX_LENGTHS,
4401                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4402                       (6 << TX_LENGTHS_IPG_SHIFT) |
4403                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4404
4405         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4406                 if (netif_carrier_ok(tp->dev)) {
4407                         tw32(HOSTCC_STAT_COAL_TICKS,
4408                              tp->coal.stats_block_coalesce_usecs);
4409                 } else {
4410                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4411                 }
4412         }
4413
4414         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4415                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4416                 if (!netif_carrier_ok(tp->dev))
4417                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4418                               tp->pwrmgmt_thresh;
4419                 else
4420                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4421                 tw32(PCIE_PWR_MGMT_THRESH, val);
4422         }
4423
4424         return err;
4425 }
4426
4427 static inline int tg3_irq_sync(struct tg3 *tp)
4428 {
4429         return tp->irq_sync;
4430 }
4431
4432 /* This is called whenever we suspect that the system chipset is re-
4433  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4434  * is bogus tx completions. We try to recover by setting the
4435  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4436  * in the workqueue.
4437  */
4438 static void tg3_tx_recover(struct tg3 *tp)
4439 {
4440         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4441                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4442
4443         netdev_warn(tp->dev,
4444                     "The system may be re-ordering memory-mapped I/O "
4445                     "cycles to the network device, attempting to recover. "
4446                     "Please report the problem to the driver maintainer "
4447                     "and include system chipset information.\n");
4448
4449         spin_lock(&tp->lock);
4450         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4451         spin_unlock(&tp->lock);
4452 }
4453
4454 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4455 {
4456         /* Tell compiler to fetch tx indices from memory. */
4457         barrier();
4458         return tnapi->tx_pending -
4459                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4460 }
4461
4462 /* Tigon3 never reports partial packet sends.  So we do not
4463  * need special logic to handle SKBs that have not had all
4464  * of their frags sent yet, like SunGEM does.
4465  */
4466 static void tg3_tx(struct tg3_napi *tnapi)
4467 {
4468         struct tg3 *tp = tnapi->tp;
4469         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4470         u32 sw_idx = tnapi->tx_cons;
4471         struct netdev_queue *txq;
4472         int index = tnapi - tp->napi;
4473
4474         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4475                 index--;
4476
4477         txq = netdev_get_tx_queue(tp->dev, index);
4478
4479         while (sw_idx != hw_idx) {
4480                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4481                 struct sk_buff *skb = ri->skb;
4482                 int i, tx_bug = 0;
4483
4484                 if (unlikely(skb == NULL)) {
4485                         tg3_tx_recover(tp);
4486                         return;
4487                 }
4488
4489                 pci_unmap_single(tp->pdev,
4490                                  dma_unmap_addr(ri, mapping),
4491                                  skb_headlen(skb),
4492                                  PCI_DMA_TODEVICE);
4493
4494                 ri->skb = NULL;
4495
4496                 sw_idx = NEXT_TX(sw_idx);
4497
4498                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4499                         ri = &tnapi->tx_buffers[sw_idx];
4500                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4501                                 tx_bug = 1;
4502
4503                         pci_unmap_page(tp->pdev,
4504                                        dma_unmap_addr(ri, mapping),
4505                                        skb_shinfo(skb)->frags[i].size,
4506                                        PCI_DMA_TODEVICE);
4507                         sw_idx = NEXT_TX(sw_idx);
4508                 }
4509
4510                 dev_kfree_skb(skb);
4511
4512                 if (unlikely(tx_bug)) {
4513                         tg3_tx_recover(tp);
4514                         return;
4515                 }
4516         }
4517
4518         tnapi->tx_cons = sw_idx;
4519
4520         /* Need to make the tx_cons update visible to tg3_start_xmit()
4521          * before checking for netif_queue_stopped().  Without the
4522          * memory barrier, there is a small possibility that tg3_start_xmit()
4523          * will miss it and cause the queue to be stopped forever.
4524          */
4525         smp_mb();
4526
4527         if (unlikely(netif_tx_queue_stopped(txq) &&
4528                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4529                 __netif_tx_lock(txq, smp_processor_id());
4530                 if (netif_tx_queue_stopped(txq) &&
4531                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4532                         netif_tx_wake_queue(txq);
4533                 __netif_tx_unlock(txq);
4534         }
4535 }
4536
4537 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4538 {
4539         if (!ri->skb)
4540                 return;
4541
4542         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4543                          map_sz, PCI_DMA_FROMDEVICE);
4544         dev_kfree_skb_any(ri->skb);
4545         ri->skb = NULL;
4546 }
4547
4548 /* Returns size of skb allocated or < 0 on error.
4549  *
4550  * We only need to fill in the address because the other members
4551  * of the RX descriptor are invariant, see tg3_init_rings.
4552  *
4553  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4554  * posting buffers we only dirty the first cache line of the RX
4555  * descriptor (containing the address).  Whereas for the RX status
4556  * buffers the cpu only reads the last cacheline of the RX descriptor
4557  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4558  */
4559 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4560                             u32 opaque_key, u32 dest_idx_unmasked)
4561 {
4562         struct tg3_rx_buffer_desc *desc;
4563         struct ring_info *map;
4564         struct sk_buff *skb;
4565         dma_addr_t mapping;
4566         int skb_size, dest_idx;
4567
4568         switch (opaque_key) {
4569         case RXD_OPAQUE_RING_STD:
4570                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4571                 desc = &tpr->rx_std[dest_idx];
4572                 map = &tpr->rx_std_buffers[dest_idx];
4573                 skb_size = tp->rx_pkt_map_sz;
4574                 break;
4575
4576         case RXD_OPAQUE_RING_JUMBO:
4577                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4578                 desc = &tpr->rx_jmb[dest_idx].std;
4579                 map = &tpr->rx_jmb_buffers[dest_idx];
4580                 skb_size = TG3_RX_JMB_MAP_SZ;
4581                 break;
4582
4583         default:
4584                 return -EINVAL;
4585         }
4586
4587         /* Do not overwrite any of the map or rp information
4588          * until we are sure we can commit to a new buffer.
4589          *
4590          * Callers depend upon this behavior and assume that
4591          * we leave everything unchanged if we fail.
4592          */
4593         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4594         if (skb == NULL)
4595                 return -ENOMEM;
4596
4597         skb_reserve(skb, tp->rx_offset);
4598
4599         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4600                                  PCI_DMA_FROMDEVICE);
4601         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4602                 dev_kfree_skb(skb);
4603                 return -EIO;
4604         }
4605
4606         map->skb = skb;
4607         dma_unmap_addr_set(map, mapping, mapping);
4608
4609         desc->addr_hi = ((u64)mapping >> 32);
4610         desc->addr_lo = ((u64)mapping & 0xffffffff);
4611
4612         return skb_size;
4613 }
4614
4615 /* We only need to move over in the address because the other
4616  * members of the RX descriptor are invariant.  See notes above
4617  * tg3_alloc_rx_skb for full details.
4618  */
4619 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4620                            struct tg3_rx_prodring_set *dpr,
4621                            u32 opaque_key, int src_idx,
4622                            u32 dest_idx_unmasked)
4623 {
4624         struct tg3 *tp = tnapi->tp;
4625         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4626         struct ring_info *src_map, *dest_map;
4627         struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
4628         int dest_idx;
4629
4630         switch (opaque_key) {
4631         case RXD_OPAQUE_RING_STD:
4632                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4633                 dest_desc = &dpr->rx_std[dest_idx];
4634                 dest_map = &dpr->rx_std_buffers[dest_idx];
4635                 src_desc = &spr->rx_std[src_idx];
4636                 src_map = &spr->rx_std_buffers[src_idx];
4637                 break;
4638
4639         case RXD_OPAQUE_RING_JUMBO:
4640                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4641                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4642                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4643                 src_desc = &spr->rx_jmb[src_idx].std;
4644                 src_map = &spr->rx_jmb_buffers[src_idx];
4645                 break;
4646
4647         default:
4648                 return;
4649         }
4650
4651         dest_map->skb = src_map->skb;
4652         dma_unmap_addr_set(dest_map, mapping,
4653                            dma_unmap_addr(src_map, mapping));
4654         dest_desc->addr_hi = src_desc->addr_hi;
4655         dest_desc->addr_lo = src_desc->addr_lo;
4656
4657         /* Ensure that the update to the skb happens after the physical
4658          * addresses have been transferred to the new BD location.
4659          */
4660         smp_wmb();
4661
4662         src_map->skb = NULL;
4663 }
4664
4665 /* The RX ring scheme is composed of multiple rings which post fresh
4666  * buffers to the chip, and one special ring the chip uses to report
4667  * status back to the host.
4668  *
4669  * The special ring reports the status of received packets to the
4670  * host.  The chip does not write into the original descriptor the
4671  * RX buffer was obtained from.  The chip simply takes the original
4672  * descriptor as provided by the host, updates the status and length
4673  * field, then writes this into the next status ring entry.
4674  *
4675  * Each ring the host uses to post buffers to the chip is described
4676  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4677  * it is first placed into the on-chip ram.  When the packet's length
4678  * is known, it walks down the TG3_BDINFO entries to select the ring.
4679  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4680  * which is within the range of the new packet's length is chosen.
4681  *
4682  * The "separate ring for rx status" scheme may sound queer, but it makes
4683  * sense from a cache coherency perspective.  If only the host writes
4684  * to the buffer post rings, and only the chip writes to the rx status
4685  * rings, then cache lines never move beyond shared-modified state.
4686  * If both the host and chip were to write into the same ring, cache line
4687  * eviction could occur since both entities want it in an exclusive state.
4688  */
4689 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4690 {
4691         struct tg3 *tp = tnapi->tp;
4692         u32 work_mask, rx_std_posted = 0;
4693         u32 std_prod_idx, jmb_prod_idx;
4694         u32 sw_idx = tnapi->rx_rcb_ptr;
4695         u16 hw_idx;
4696         int received;
4697         struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
4698
4699         hw_idx = *(tnapi->rx_rcb_prod_idx);
4700         /*
4701          * We need to order the read of hw_idx and the read of
4702          * the opaque cookie.
4703          */
4704         rmb();
4705         work_mask = 0;
4706         received = 0;
4707         std_prod_idx = tpr->rx_std_prod_idx;
4708         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4709         while (sw_idx != hw_idx && budget > 0) {
4710                 struct ring_info *ri;
4711                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4712                 unsigned int len;
4713                 struct sk_buff *skb;
4714                 dma_addr_t dma_addr;
4715                 u32 opaque_key, desc_idx, *post_ptr;
4716
4717                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4718                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4719                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4720                         ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4721                         dma_addr = dma_unmap_addr(ri, mapping);
4722                         skb = ri->skb;
4723                         post_ptr = &std_prod_idx;
4724                         rx_std_posted++;
4725                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4726                         ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4727                         dma_addr = dma_unmap_addr(ri, mapping);
4728                         skb = ri->skb;
4729                         post_ptr = &jmb_prod_idx;
4730                 } else
4731                         goto next_pkt_nopost;
4732
4733                 work_mask |= opaque_key;
4734
4735                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4736                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4737                 drop_it:
4738                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4739                                        desc_idx, *post_ptr);
4740                 drop_it_no_recycle:
4741                         /* Other statistics kept track of by card. */
4742                         tp->rx_dropped++;
4743                         goto next_pkt;
4744                 }
4745
4746                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4747                       ETH_FCS_LEN;
4748
4749                 if (len > TG3_RX_COPY_THRESH(tp)) {
4750                         int skb_size;
4751
4752                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4753                                                     *post_ptr);
4754                         if (skb_size < 0)
4755                                 goto drop_it;
4756
4757                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4758                                          PCI_DMA_FROMDEVICE);
4759
4760                         /* Ensure that the update to the skb happens
4761                          * after the usage of the old DMA mapping.
4762                          */
4763                         smp_wmb();
4764
4765                         ri->skb = NULL;
4766
4767                         skb_put(skb, len);
4768                 } else {
4769                         struct sk_buff *copy_skb;
4770
4771                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4772                                        desc_idx, *post_ptr);
4773
4774                         copy_skb = netdev_alloc_skb(tp->dev, len +
4775                                                     TG3_RAW_IP_ALIGN);
4776                         if (copy_skb == NULL)
4777                                 goto drop_it_no_recycle;
4778
4779                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4780                         skb_put(copy_skb, len);
4781                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4782                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4783                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4784
4785                         /* We'll reuse the original ring buffer. */
4786                         skb = copy_skb;
4787                 }
4788
4789                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4790                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4791                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4792                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4793                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4794                 else
4795                         skb_checksum_none_assert(skb);
4796
4797                 skb->protocol = eth_type_trans(skb, tp->dev);
4798
4799                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4800                     skb->protocol != htons(ETH_P_8021Q)) {
4801                         dev_kfree_skb(skb);
4802                         goto drop_it_no_recycle;
4803                 }
4804
4805                 if (desc->type_flags & RXD_FLAG_VLAN &&
4806                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
4807                         __vlan_hwaccel_put_tag(skb,
4808                                                desc->err_vlan & RXD_VLAN_MASK);
4809
4810                 napi_gro_receive(&tnapi->napi, skb);
4811
4812                 received++;
4813                 budget--;
4814
4815 next_pkt:
4816                 (*post_ptr)++;
4817
4818                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4819                         tpr->rx_std_prod_idx = std_prod_idx &
4820                                                tp->rx_std_ring_mask;
4821                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4822                                      tpr->rx_std_prod_idx);
4823                         work_mask &= ~RXD_OPAQUE_RING_STD;
4824                         rx_std_posted = 0;
4825                 }
4826 next_pkt_nopost:
4827                 sw_idx++;
4828                 sw_idx &= tp->rx_ret_ring_mask;
4829
4830                 /* Refresh hw_idx to see if there is new work */
4831                 if (sw_idx == hw_idx) {
4832                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4833                         rmb();
4834                 }
4835         }
4836
4837         /* ACK the status ring. */
4838         tnapi->rx_rcb_ptr = sw_idx;
4839         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4840
4841         /* Refill RX ring(s). */
4842         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4843                 if (work_mask & RXD_OPAQUE_RING_STD) {
4844                         tpr->rx_std_prod_idx = std_prod_idx &
4845                                                tp->rx_std_ring_mask;
4846                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4847                                      tpr->rx_std_prod_idx);
4848                 }
4849                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4850                         tpr->rx_jmb_prod_idx = jmb_prod_idx &
4851                                                tp->rx_jmb_ring_mask;
4852                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4853                                      tpr->rx_jmb_prod_idx);
4854                 }
4855                 mmiowb();
4856         } else if (work_mask) {
4857                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4858                  * updated before the producer indices can be updated.
4859                  */
4860                 smp_wmb();
4861
4862                 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
4863                 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
4864
4865                 if (tnapi != &tp->napi[1])
4866                         napi_schedule(&tp->napi[1].napi);
4867         }
4868
4869         return received;
4870 }
4871
4872 static void tg3_poll_link(struct tg3 *tp)
4873 {
4874         /* handle link change and other phy events */
4875         if (!(tp->tg3_flags &
4876               (TG3_FLAG_USE_LINKCHG_REG |
4877                TG3_FLAG_POLL_SERDES))) {
4878                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4879
4880                 if (sblk->status & SD_STATUS_LINK_CHG) {
4881                         sblk->status = SD_STATUS_UPDATED |
4882                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4883                         spin_lock(&tp->lock);
4884                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4885                                 tw32_f(MAC_STATUS,
4886                                      (MAC_STATUS_SYNC_CHANGED |
4887                                       MAC_STATUS_CFG_CHANGED |
4888                                       MAC_STATUS_MI_COMPLETION |
4889                                       MAC_STATUS_LNKSTATE_CHANGED));
4890                                 udelay(40);
4891                         } else
4892                                 tg3_setup_phy(tp, 0);
4893                         spin_unlock(&tp->lock);
4894                 }
4895         }
4896 }
4897
4898 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4899                                 struct tg3_rx_prodring_set *dpr,
4900                                 struct tg3_rx_prodring_set *spr)
4901 {
4902         u32 si, di, cpycnt, src_prod_idx;
4903         int i, err = 0;
4904
4905         while (1) {
4906                 src_prod_idx = spr->rx_std_prod_idx;
4907
4908                 /* Make sure updates to the rx_std_buffers[] entries and the
4909                  * standard producer index are seen in the correct order.
4910                  */
4911                 smp_rmb();
4912
4913                 if (spr->rx_std_cons_idx == src_prod_idx)
4914                         break;
4915
4916                 if (spr->rx_std_cons_idx < src_prod_idx)
4917                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4918                 else
4919                         cpycnt = tp->rx_std_ring_mask + 1 -
4920                                  spr->rx_std_cons_idx;
4921
4922                 cpycnt = min(cpycnt,
4923                              tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
4924
4925                 si = spr->rx_std_cons_idx;
4926                 di = dpr->rx_std_prod_idx;
4927
4928                 for (i = di; i < di + cpycnt; i++) {
4929                         if (dpr->rx_std_buffers[i].skb) {
4930                                 cpycnt = i - di;
4931                                 err = -ENOSPC;
4932                                 break;
4933                         }
4934                 }
4935
4936                 if (!cpycnt)
4937                         break;
4938
4939                 /* Ensure that updates to the rx_std_buffers ring and the
4940                  * shadowed hardware producer ring from tg3_recycle_skb() are
4941                  * ordered correctly WRT the skb check above.
4942                  */
4943                 smp_rmb();
4944
4945                 memcpy(&dpr->rx_std_buffers[di],
4946                        &spr->rx_std_buffers[si],
4947                        cpycnt * sizeof(struct ring_info));
4948
4949                 for (i = 0; i < cpycnt; i++, di++, si++) {
4950                         struct tg3_rx_buffer_desc *sbd, *dbd;
4951                         sbd = &spr->rx_std[si];
4952                         dbd = &dpr->rx_std[di];
4953                         dbd->addr_hi = sbd->addr_hi;
4954                         dbd->addr_lo = sbd->addr_lo;
4955                 }
4956
4957                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
4958                                        tp->rx_std_ring_mask;
4959                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
4960                                        tp->rx_std_ring_mask;
4961         }
4962
4963         while (1) {
4964                 src_prod_idx = spr->rx_jmb_prod_idx;
4965
4966                 /* Make sure updates to the rx_jmb_buffers[] entries and
4967                  * the jumbo producer index are seen in the correct order.
4968                  */
4969                 smp_rmb();
4970
4971                 if (spr->rx_jmb_cons_idx == src_prod_idx)
4972                         break;
4973
4974                 if (spr->rx_jmb_cons_idx < src_prod_idx)
4975                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4976                 else
4977                         cpycnt = tp->rx_jmb_ring_mask + 1 -
4978                                  spr->rx_jmb_cons_idx;
4979
4980                 cpycnt = min(cpycnt,
4981                              tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
4982
4983                 si = spr->rx_jmb_cons_idx;
4984                 di = dpr->rx_jmb_prod_idx;
4985
4986                 for (i = di; i < di + cpycnt; i++) {
4987                         if (dpr->rx_jmb_buffers[i].skb) {
4988                                 cpycnt = i - di;
4989                                 err = -ENOSPC;
4990                                 break;
4991                         }
4992                 }
4993
4994                 if (!cpycnt)
4995                         break;
4996
4997                 /* Ensure that updates to the rx_jmb_buffers ring and the
4998                  * shadowed hardware producer ring from tg3_recycle_skb() are
4999                  * ordered correctly WRT the skb check above.
5000                  */
5001                 smp_rmb();
5002
5003                 memcpy(&dpr->rx_jmb_buffers[di],
5004                        &spr->rx_jmb_buffers[si],
5005                        cpycnt * sizeof(struct ring_info));
5006
5007                 for (i = 0; i < cpycnt; i++, di++, si++) {
5008                         struct tg3_rx_buffer_desc *sbd, *dbd;
5009                         sbd = &spr->rx_jmb[si].std;
5010                         dbd = &dpr->rx_jmb[di].std;
5011                         dbd->addr_hi = sbd->addr_hi;
5012                         dbd->addr_lo = sbd->addr_lo;
5013                 }
5014
5015                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
5016                                        tp->rx_jmb_ring_mask;
5017                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
5018                                        tp->rx_jmb_ring_mask;
5019         }
5020
5021         return err;
5022 }
5023
5024 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
5025 {
5026         struct tg3 *tp = tnapi->tp;
5027
5028         /* run TX completion thread */
5029         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
5030                 tg3_tx(tnapi);
5031                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5032                         return work_done;
5033         }
5034
5035         /* run RX thread, within the bounds set by NAPI.
5036          * All RX "locking" is done by ensuring outside
5037          * code synchronizes with tg3->napi.poll()
5038          */
5039         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
5040                 work_done += tg3_rx(tnapi, budget - work_done);
5041
5042         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
5043                 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
5044                 int i, err = 0;
5045                 u32 std_prod_idx = dpr->rx_std_prod_idx;
5046                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
5047
5048                 for (i = 1; i < tp->irq_cnt; i++)
5049                         err |= tg3_rx_prodring_xfer(tp, dpr,
5050                                                     &tp->napi[i].prodring);
5051
5052                 wmb();
5053
5054                 if (std_prod_idx != dpr->rx_std_prod_idx)
5055                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5056                                      dpr->rx_std_prod_idx);
5057
5058                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5059                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5060                                      dpr->rx_jmb_prod_idx);
5061
5062                 mmiowb();
5063
5064                 if (err)
5065                         tw32_f(HOSTCC_MODE, tp->coal_now);
5066         }
5067
5068         return work_done;
5069 }
5070
5071 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5072 {
5073         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5074         struct tg3 *tp = tnapi->tp;
5075         int work_done = 0;
5076         struct tg3_hw_status *sblk = tnapi->hw_status;
5077
5078         while (1) {
5079                 work_done = tg3_poll_work(tnapi, work_done, budget);
5080
5081                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5082                         goto tx_recovery;
5083
5084                 if (unlikely(work_done >= budget))
5085                         break;
5086
5087                 /* tp->last_tag is used in tg3_int_reenable() below
5088                  * to tell the hw how much work has been processed,
5089                  * so we must read it before checking for more work.
5090                  */
5091                 tnapi->last_tag = sblk->status_tag;
5092                 tnapi->last_irq_tag = tnapi->last_tag;
5093                 rmb();
5094
5095                 /* check for RX/TX work to do */
5096                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5097                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5098                         napi_complete(napi);
5099                         /* Reenable interrupts. */
5100                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5101                         mmiowb();
5102                         break;
5103                 }
5104         }
5105
5106         return work_done;
5107
5108 tx_recovery:
5109         /* work_done is guaranteed to be less than budget. */
5110         napi_complete(napi);
5111         schedule_work(&tp->reset_task);
5112         return work_done;
5113 }
5114
5115 static int tg3_poll(struct napi_struct *napi, int budget)
5116 {
5117         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5118         struct tg3 *tp = tnapi->tp;
5119         int work_done = 0;
5120         struct tg3_hw_status *sblk = tnapi->hw_status;
5121
5122         while (1) {
5123                 tg3_poll_link(tp);
5124
5125                 work_done = tg3_poll_work(tnapi, work_done, budget);
5126
5127                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5128                         goto tx_recovery;
5129
5130                 if (unlikely(work_done >= budget))
5131                         break;
5132
5133                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5134                         /* tp->last_tag is used in tg3_int_reenable() below
5135                          * to tell the hw how much work has been processed,
5136                          * so we must read it before checking for more work.
5137                          */
5138                         tnapi->last_tag = sblk->status_tag;
5139                         tnapi->last_irq_tag = tnapi->last_tag;
5140                         rmb();
5141                 } else
5142                         sblk->status &= ~SD_STATUS_UPDATED;
5143
5144                 if (likely(!tg3_has_work(tnapi))) {
5145                         napi_complete(napi);
5146                         tg3_int_reenable(tnapi);
5147                         break;
5148                 }
5149         }
5150
5151         return work_done;
5152
5153 tx_recovery:
5154         /* work_done is guaranteed to be less than budget. */
5155         napi_complete(napi);
5156         schedule_work(&tp->reset_task);
5157         return work_done;
5158 }
5159
5160 static void tg3_napi_disable(struct tg3 *tp)
5161 {
5162         int i;
5163
5164         for (i = tp->irq_cnt - 1; i >= 0; i--)
5165                 napi_disable(&tp->napi[i].napi);
5166 }
5167
5168 static void tg3_napi_enable(struct tg3 *tp)
5169 {
5170         int i;
5171
5172         for (i = 0; i < tp->irq_cnt; i++)
5173                 napi_enable(&tp->napi[i].napi);
5174 }
5175
5176 static void tg3_napi_init(struct tg3 *tp)
5177 {
5178         int i;
5179
5180         netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
5181         for (i = 1; i < tp->irq_cnt; i++)
5182                 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
5183 }
5184
5185 static void tg3_napi_fini(struct tg3 *tp)
5186 {
5187         int i;
5188
5189         for (i = 0; i < tp->irq_cnt; i++)
5190                 netif_napi_del(&tp->napi[i].napi);
5191 }
5192
5193 static inline void tg3_netif_stop(struct tg3 *tp)
5194 {
5195         tp->dev->trans_start = jiffies; /* prevent tx timeout */
5196         tg3_napi_disable(tp);
5197         netif_tx_disable(tp->dev);
5198 }
5199
5200 static inline void tg3_netif_start(struct tg3 *tp)
5201 {
5202         /* NOTE: unconditional netif_tx_wake_all_queues is only
5203          * appropriate so long as all callers are assured to
5204          * have free tx slots (such as after tg3_init_hw)
5205          */
5206         netif_tx_wake_all_queues(tp->dev);
5207
5208         tg3_napi_enable(tp);
5209         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
5210         tg3_enable_ints(tp);
5211 }
5212
5213 static void tg3_irq_quiesce(struct tg3 *tp)
5214 {
5215         int i;
5216
5217         BUG_ON(tp->irq_sync);
5218
5219         tp->irq_sync = 1;
5220         smp_mb();
5221
5222         for (i = 0; i < tp->irq_cnt; i++)
5223                 synchronize_irq(tp->napi[i].irq_vec);
5224 }
5225
5226 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5227  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5228  * with as well.  Most of the time, this is not necessary except when
5229  * shutting down the device.
5230  */
5231 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5232 {
5233         spin_lock_bh(&tp->lock);
5234         if (irq_sync)
5235                 tg3_irq_quiesce(tp);
5236 }
5237
5238 static inline void tg3_full_unlock(struct tg3 *tp)
5239 {
5240         spin_unlock_bh(&tp->lock);
5241 }
5242
5243 /* One-shot MSI handler - Chip automatically disables interrupt
5244  * after sending MSI so driver doesn't have to do it.
5245  */
5246 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5247 {
5248         struct tg3_napi *tnapi = dev_id;
5249         struct tg3 *tp = tnapi->tp;
5250
5251         prefetch(tnapi->hw_status);
5252         if (tnapi->rx_rcb)
5253                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5254
5255         if (likely(!tg3_irq_sync(tp)))
5256                 napi_schedule(&tnapi->napi);
5257
5258         return IRQ_HANDLED;
5259 }
5260
5261 /* MSI ISR - No need to check for interrupt sharing and no need to
5262  * flush status block and interrupt mailbox. PCI ordering rules
5263  * guarantee that MSI will arrive after the status block.
5264  */
5265 static irqreturn_t tg3_msi(int irq, void *dev_id)
5266 {
5267         struct tg3_napi *tnapi = dev_id;
5268         struct tg3 *tp = tnapi->tp;
5269
5270         prefetch(tnapi->hw_status);
5271         if (tnapi->rx_rcb)
5272                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5273         /*
5274          * Writing any value to intr-mbox-0 clears PCI INTA# and
5275          * chip-internal interrupt pending events.
5276          * Writing non-zero to intr-mbox-0 additional tells the
5277          * NIC to stop sending us irqs, engaging "in-intr-handler"
5278          * event coalescing.
5279          */
5280         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5281         if (likely(!tg3_irq_sync(tp)))
5282                 napi_schedule(&tnapi->napi);
5283
5284         return IRQ_RETVAL(1);
5285 }
5286
5287 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5288 {
5289         struct tg3_napi *tnapi = dev_id;
5290         struct tg3 *tp = tnapi->tp;
5291         struct tg3_hw_status *sblk = tnapi->hw_status;
5292         unsigned int handled = 1;
5293
5294         /* In INTx mode, it is possible for the interrupt to arrive at
5295          * the CPU before the status block posted prior to the interrupt.
5296          * Reading the PCI State register will confirm whether the
5297          * interrupt is ours and will flush the status block.
5298          */
5299         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5300                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5301                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5302                         handled = 0;
5303                         goto out;
5304                 }
5305         }
5306
5307         /*
5308          * Writing any value to intr-mbox-0 clears PCI INTA# and
5309          * chip-internal interrupt pending events.
5310          * Writing non-zero to intr-mbox-0 additional tells the
5311          * NIC to stop sending us irqs, engaging "in-intr-handler"
5312          * event coalescing.
5313          *
5314          * Flush the mailbox to de-assert the IRQ immediately to prevent
5315          * spurious interrupts.  The flush impacts performance but
5316          * excessive spurious interrupts can be worse in some cases.
5317          */
5318         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5319         if (tg3_irq_sync(tp))
5320                 goto out;
5321         sblk->status &= ~SD_STATUS_UPDATED;
5322         if (likely(tg3_has_work(tnapi))) {
5323                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5324                 napi_schedule(&tnapi->napi);
5325         } else {
5326                 /* No work, shared interrupt perhaps?  re-enable
5327                  * interrupts, and flush that PCI write
5328                  */
5329                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5330                                0x00000000);
5331         }
5332 out:
5333         return IRQ_RETVAL(handled);
5334 }
5335
5336 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5337 {
5338         struct tg3_napi *tnapi = dev_id;
5339         struct tg3 *tp = tnapi->tp;
5340         struct tg3_hw_status *sblk = tnapi->hw_status;
5341         unsigned int handled = 1;
5342
5343         /* In INTx mode, it is possible for the interrupt to arrive at
5344          * the CPU before the status block posted prior to the interrupt.
5345          * Reading the PCI State register will confirm whether the
5346          * interrupt is ours and will flush the status block.
5347          */
5348         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5349                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5350                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5351                         handled = 0;
5352                         goto out;
5353                 }
5354         }
5355
5356         /*
5357          * writing any value to intr-mbox-0 clears PCI INTA# and
5358          * chip-internal interrupt pending events.
5359          * writing non-zero to intr-mbox-0 additional tells the
5360          * NIC to stop sending us irqs, engaging "in-intr-handler"
5361          * event coalescing.
5362          *
5363          * Flush the mailbox to de-assert the IRQ immediately to prevent
5364          * spurious interrupts.  The flush impacts performance but
5365          * excessive spurious interrupts can be worse in some cases.
5366          */
5367         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5368
5369         /*
5370          * In a shared interrupt configuration, sometimes other devices'
5371          * interrupts will scream.  We record the current status tag here
5372          * so that the above check can report that the screaming interrupts
5373          * are unhandled.  Eventually they will be silenced.
5374          */
5375         tnapi->last_irq_tag = sblk->status_tag;
5376
5377         if (tg3_irq_sync(tp))
5378                 goto out;
5379
5380         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5381
5382         napi_schedule(&tnapi->napi);
5383
5384 out:
5385         return IRQ_RETVAL(handled);
5386 }
5387
5388 /* ISR for interrupt test */
5389 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5390 {
5391         struct tg3_napi *tnapi = dev_id;
5392         struct tg3 *tp = tnapi->tp;
5393         struct tg3_hw_status *sblk = tnapi->hw_status;
5394
5395         if ((sblk->status & SD_STATUS_UPDATED) ||
5396             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5397                 tg3_disable_ints(tp);
5398                 return IRQ_RETVAL(1);
5399         }
5400         return IRQ_RETVAL(0);
5401 }
5402
5403 static int tg3_init_hw(struct tg3 *, int);
5404 static int tg3_halt(struct tg3 *, int, int);
5405
5406 /* Restart hardware after configuration changes, self-test, etc.
5407  * Invoked with tp->lock held.
5408  */
5409 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5410         __releases(tp->lock)
5411         __acquires(tp->lock)
5412 {
5413         int err;
5414
5415         err = tg3_init_hw(tp, reset_phy);
5416         if (err) {
5417                 netdev_err(tp->dev,
5418                            "Failed to re-initialize device, aborting\n");
5419                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5420                 tg3_full_unlock(tp);
5421                 del_timer_sync(&tp->timer);
5422                 tp->irq_sync = 0;
5423                 tg3_napi_enable(tp);
5424                 dev_close(tp->dev);
5425                 tg3_full_lock(tp, 0);
5426         }
5427         return err;
5428 }
5429
5430 #ifdef CONFIG_NET_POLL_CONTROLLER
5431 static void tg3_poll_controller(struct net_device *dev)
5432 {
5433         int i;
5434         struct tg3 *tp = netdev_priv(dev);
5435
5436         for (i = 0; i < tp->irq_cnt; i++)
5437                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5438 }
5439 #endif
5440
5441 static void tg3_reset_task(struct work_struct *work)
5442 {
5443         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5444         int err;
5445         unsigned int restart_timer;
5446
5447         tg3_full_lock(tp, 0);
5448
5449         if (!netif_running(tp->dev)) {
5450                 tg3_full_unlock(tp);
5451                 return;
5452         }
5453
5454         tg3_full_unlock(tp);
5455
5456         tg3_phy_stop(tp);
5457
5458         tg3_netif_stop(tp);
5459
5460         tg3_full_lock(tp, 1);
5461
5462         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5463         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5464
5465         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5466                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5467                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5468                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5469                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5470         }
5471
5472         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5473         err = tg3_init_hw(tp, 1);
5474         if (err)
5475                 goto out;
5476
5477         tg3_netif_start(tp);
5478
5479         if (restart_timer)
5480                 mod_timer(&tp->timer, jiffies + 1);
5481
5482 out:
5483         tg3_full_unlock(tp);
5484
5485         if (!err)
5486                 tg3_phy_start(tp);
5487 }
5488
5489 static void tg3_dump_short_state(struct tg3 *tp)
5490 {
5491         netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5492                    tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5493         netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5494                    tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5495 }
5496
5497 static void tg3_tx_timeout(struct net_device *dev)
5498 {
5499         struct tg3 *tp = netdev_priv(dev);
5500
5501         if (netif_msg_tx_err(tp)) {
5502                 netdev_err(dev, "transmit timed out, resetting\n");
5503                 tg3_dump_short_state(tp);
5504         }
5505
5506         schedule_work(&tp->reset_task);
5507 }
5508
5509 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5510 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5511 {
5512         u32 base = (u32) mapping & 0xffffffff;
5513
5514         return (base > 0xffffdcc0) && (base + len + 8 < base);
5515 }
5516
5517 /* Test for DMA addresses > 40-bit */
5518 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5519                                           int len)
5520 {
5521 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5522         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5523                 return ((u64) mapping + len) > DMA_BIT_MASK(40);
5524         return 0;
5525 #else
5526         return 0;
5527 #endif
5528 }
5529
5530 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5531
5532 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5533 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5534                                        struct sk_buff *skb, u32 last_plus_one,
5535                                        u32 *start, u32 base_flags, u32 mss)
5536 {
5537         struct tg3 *tp = tnapi->tp;
5538         struct sk_buff *new_skb;
5539         dma_addr_t new_addr = 0;
5540         u32 entry = *start;
5541         int i, ret = 0;
5542
5543         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5544                 new_skb = skb_copy(skb, GFP_ATOMIC);
5545         else {
5546                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5547
5548                 new_skb = skb_copy_expand(skb,
5549                                           skb_headroom(skb) + more_headroom,
5550                                           skb_tailroom(skb), GFP_ATOMIC);
5551         }
5552
5553         if (!new_skb) {
5554                 ret = -1;
5555         } else {
5556                 /* New SKB is guaranteed to be linear. */
5557                 entry = *start;
5558                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5559                                           PCI_DMA_TODEVICE);
5560                 /* Make sure the mapping succeeded */
5561                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5562                         ret = -1;
5563                         dev_kfree_skb(new_skb);
5564                         new_skb = NULL;
5565
5566                 /* Make sure new skb does not cross any 4G boundaries.
5567                  * Drop the packet if it does.
5568                  */
5569                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5570                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5571                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5572                                          PCI_DMA_TODEVICE);
5573                         ret = -1;
5574                         dev_kfree_skb(new_skb);
5575                         new_skb = NULL;
5576                 } else {
5577                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5578                                     base_flags, 1 | (mss << 1));
5579                         *start = NEXT_TX(entry);
5580                 }
5581         }
5582
5583         /* Now clean up the sw ring entries. */
5584         i = 0;
5585         while (entry != last_plus_one) {
5586                 int len;
5587
5588                 if (i == 0)
5589                         len = skb_headlen(skb);
5590                 else
5591                         len = skb_shinfo(skb)->frags[i-1].size;
5592
5593                 pci_unmap_single(tp->pdev,
5594                                  dma_unmap_addr(&tnapi->tx_buffers[entry],
5595                                                 mapping),
5596                                  len, PCI_DMA_TODEVICE);
5597                 if (i == 0) {
5598                         tnapi->tx_buffers[entry].skb = new_skb;
5599                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5600                                            new_addr);
5601                 } else {
5602                         tnapi->tx_buffers[entry].skb = NULL;
5603                 }
5604                 entry = NEXT_TX(entry);
5605                 i++;
5606         }
5607
5608         dev_kfree_skb(skb);
5609
5610         return ret;
5611 }
5612
5613 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5614                         dma_addr_t mapping, int len, u32 flags,
5615                         u32 mss_and_is_end)
5616 {
5617         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5618         int is_end = (mss_and_is_end & 0x1);
5619         u32 mss = (mss_and_is_end >> 1);
5620         u32 vlan_tag = 0;
5621
5622         if (is_end)
5623                 flags |= TXD_FLAG_END;
5624         if (flags & TXD_FLAG_VLAN) {
5625                 vlan_tag = flags >> 16;
5626                 flags &= 0xffff;
5627         }
5628         vlan_tag |= (mss << TXD_MSS_SHIFT);
5629
5630         txd->addr_hi = ((u64) mapping >> 32);
5631         txd->addr_lo = ((u64) mapping & 0xffffffff);
5632         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5633         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5634 }
5635
5636 /* hard_start_xmit for devices that don't have any bugs and
5637  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5638  */
5639 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5640                                   struct net_device *dev)
5641 {
5642         struct tg3 *tp = netdev_priv(dev);
5643         u32 len, entry, base_flags, mss;
5644         dma_addr_t mapping;
5645         struct tg3_napi *tnapi;
5646         struct netdev_queue *txq;
5647         unsigned int i, last;
5648
5649         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5650         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5651         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5652                 tnapi++;
5653
5654         /* We are running in BH disabled context with netif_tx_lock
5655          * and TX reclaim runs via tp->napi.poll inside of a software
5656          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5657          * no IRQ context deadlocks to worry about either.  Rejoice!
5658          */
5659         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5660                 if (!netif_tx_queue_stopped(txq)) {
5661                         netif_tx_stop_queue(txq);
5662
5663                         /* This is a hard error, log it. */
5664                         netdev_err(dev,
5665                                    "BUG! Tx Ring full when queue awake!\n");
5666                 }
5667                 return NETDEV_TX_BUSY;
5668         }
5669
5670         entry = tnapi->tx_prod;
5671         base_flags = 0;
5672         mss = skb_shinfo(skb)->gso_size;
5673         if (mss) {
5674                 int tcp_opt_len, ip_tcp_len;
5675                 u32 hdrlen;
5676
5677                 if (skb_header_cloned(skb) &&
5678                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5679                         dev_kfree_skb(skb);
5680                         goto out_unlock;
5681                 }
5682
5683                 if (skb_is_gso_v6(skb)) {
5684                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5685                 } else {
5686                         struct iphdr *iph = ip_hdr(skb);
5687
5688                         tcp_opt_len = tcp_optlen(skb);
5689                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5690
5691                         iph->check = 0;
5692                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5693                         hdrlen = ip_tcp_len + tcp_opt_len;
5694                 }
5695
5696                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5697                         mss |= (hdrlen & 0xc) << 12;
5698                         if (hdrlen & 0x10)
5699                                 base_flags |= 0x00000010;
5700                         base_flags |= (hdrlen & 0x3e0) << 5;
5701                 } else
5702                         mss |= hdrlen << 9;
5703
5704                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5705                                TXD_FLAG_CPU_POST_DMA);
5706
5707                 tcp_hdr(skb)->check = 0;
5708
5709         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5710                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5711         }
5712
5713         if (vlan_tx_tag_present(skb))
5714                 base_flags |= (TXD_FLAG_VLAN |
5715                                (vlan_tx_tag_get(skb) << 16));
5716
5717         len = skb_headlen(skb);
5718
5719         /* Queue skb data, a.k.a. the main skb fragment. */
5720         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5721         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5722                 dev_kfree_skb(skb);
5723                 goto out_unlock;
5724         }
5725
5726         tnapi->tx_buffers[entry].skb = skb;
5727         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5728
5729         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5730             !mss && skb->len > VLAN_ETH_FRAME_LEN)
5731                 base_flags |= TXD_FLAG_JMB_PKT;
5732
5733         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5734                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5735
5736         entry = NEXT_TX(entry);
5737
5738         /* Now loop through additional data fragments, and queue them. */
5739         if (skb_shinfo(skb)->nr_frags > 0) {
5740                 last = skb_shinfo(skb)->nr_frags - 1;
5741                 for (i = 0; i <= last; i++) {
5742                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5743
5744                         len = frag->size;
5745                         mapping = pci_map_page(tp->pdev,
5746                                                frag->page,
5747                                                frag->page_offset,
5748                                                len, PCI_DMA_TODEVICE);
5749                         if (pci_dma_mapping_error(tp->pdev, mapping))
5750                                 goto dma_error;
5751
5752                         tnapi->tx_buffers[entry].skb = NULL;
5753                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5754                                            mapping);
5755
5756                         tg3_set_txd(tnapi, entry, mapping, len,
5757                                     base_flags, (i == last) | (mss << 1));
5758
5759                         entry = NEXT_TX(entry);
5760                 }
5761         }
5762
5763         /* Packets are ready, update Tx producer idx local and on card. */
5764         tw32_tx_mbox(tnapi->prodmbox, entry);
5765