852e917778f8a51643096f648d9020c2a7963725
[linux-2.6.git] / drivers / net / tg3.c
1 /*
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  * Copyright (C) 2005-2010 Broadcom Corporation.
8  *
9  * Firmware is:
10  *      Derived from proprietary unpublished source code,
11  *      Copyright (C) 2000-2003 Broadcom Corporation.
12  *
13  *      Permission is hereby granted for the distribution of this firmware
14  *      data in hexadecimal or equivalent format, provided this copyright
15  *      notice is accompanying it.
16  */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/in.h>
28 #include <linux/init.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mii.h>
36 #include <linux/phy.h>
37 #include <linux/brcmphy.h>
38 #include <linux/if_vlan.h>
39 #include <linux/ip.h>
40 #include <linux/tcp.h>
41 #include <linux/workqueue.h>
42 #include <linux/prefetch.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/firmware.h>
45
46 #include <net/checksum.h>
47 #include <net/ip.h>
48
49 #include <asm/system.h>
50 #include <asm/io.h>
51 #include <asm/byteorder.h>
52 #include <asm/uaccess.h>
53
54 #ifdef CONFIG_SPARC
55 #include <asm/idprom.h>
56 #include <asm/prom.h>
57 #endif
58
59 #define BAR_0   0
60 #define BAR_2   2
61
62 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
63 #define TG3_VLAN_TAG_USED 1
64 #else
65 #define TG3_VLAN_TAG_USED 0
66 #endif
67
68 #include "tg3.h"
69
70 #define DRV_MODULE_NAME         "tg3"
71 #define TG3_MAJ_NUM                     3
72 #define TG3_MIN_NUM                     115
73 #define DRV_MODULE_VERSION      \
74         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
75 #define DRV_MODULE_RELDATE      "October 14, 2010"
76
77 #define TG3_DEF_MAC_MODE        0
78 #define TG3_DEF_RX_MODE         0
79 #define TG3_DEF_TX_MODE         0
80 #define TG3_DEF_MSG_ENABLE        \
81         (NETIF_MSG_DRV          | \
82          NETIF_MSG_PROBE        | \
83          NETIF_MSG_LINK         | \
84          NETIF_MSG_TIMER        | \
85          NETIF_MSG_IFDOWN       | \
86          NETIF_MSG_IFUP         | \
87          NETIF_MSG_RX_ERR       | \
88          NETIF_MSG_TX_ERR)
89
90 /* length of time before we decide the hardware is borked,
91  * and dev->tx_timeout() should be called to fix the problem
92  */
93 #define TG3_TX_TIMEOUT                  (5 * HZ)
94
95 /* hardware minimum and maximum for a single frame's data payload */
96 #define TG3_MIN_MTU                     60
97 #define TG3_MAX_MTU(tp) \
98         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
99
100 /* These numbers seem to be hard coded in the NIC firmware somehow.
101  * You can't change the ring sizes, but you can change where you place
102  * them in the NIC onboard memory.
103  */
104 #define TG3_RX_STD_RING_SIZE(tp) \
105         ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
106           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
107          RX_STD_MAX_SIZE_5717 : 512)
108 #define TG3_DEF_RX_RING_PENDING         200
109 #define TG3_RX_JMB_RING_SIZE(tp) \
110         ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
111           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
112          1024 : 256)
113 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
114 #define TG3_RSS_INDIR_TBL_SIZE          128
115
116 /* Do not place this n-ring entries value into the tp struct itself,
117  * we really want to expose these constants to GCC so that modulo et
118  * al.  operations are done with shifts and masks instead of with
119  * hw multiply/modulo instructions.  Another solution would be to
120  * replace things like '% foo' with '& (foo - 1)'.
121  */
122
123 #define TG3_TX_RING_SIZE                512
124 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
125
126 #define TG3_RX_STD_RING_BYTES(tp) \
127         (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
128 #define TG3_RX_JMB_RING_BYTES(tp) \
129         (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
130 #define TG3_RX_RCB_RING_BYTES(tp) \
131         (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
132 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
133                                  TG3_TX_RING_SIZE)
134 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
135
136 #define TG3_RX_DMA_ALIGN                16
137 #define TG3_RX_HEADROOM                 ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
138
139 #define TG3_DMA_BYTE_ENAB               64
140
141 #define TG3_RX_STD_DMA_SZ               1536
142 #define TG3_RX_JMB_DMA_SZ               9046
143
144 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
145
146 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
147 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
148
149 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
150         (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
151
152 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
153         (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
154
155 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
156  * that are at least dword aligned when used in PCIX mode.  The driver
157  * works around this bug by double copying the packet.  This workaround
158  * is built into the normal double copy length check for efficiency.
159  *
160  * However, the double copy is only necessary on those architectures
161  * where unaligned memory accesses are inefficient.  For those architectures
162  * where unaligned memory accesses incur little penalty, we can reintegrate
163  * the 5701 in the normal rx path.  Doing so saves a device structure
164  * dereference by hardcoding the double copy threshold in place.
165  */
166 #define TG3_RX_COPY_THRESHOLD           256
167 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
168         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
169 #else
170         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
171 #endif
172
173 /* minimum number of free TX descriptors required to wake up TX process */
174 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
175
176 #define TG3_RAW_IP_ALIGN 2
177
178 /* number of ETHTOOL_GSTATS u64's */
179 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
180
181 #define TG3_NUM_TEST            6
182
183 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
184
185 #define FIRMWARE_TG3            "tigon/tg3.bin"
186 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
187 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
188
189 static char version[] __devinitdata =
190         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
191
192 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
193 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
194 MODULE_LICENSE("GPL");
195 MODULE_VERSION(DRV_MODULE_VERSION);
196 MODULE_FIRMWARE(FIRMWARE_TG3);
197 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
198 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
199
200 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
201 module_param(tg3_debug, int, 0);
202 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
203
204 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
268         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
269         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
270         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
271         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
272         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
273         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
274         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
275         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
276         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
277         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
278         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
279         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
280         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
281         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
282         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
283         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
284         {}
285 };
286
287 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
288
289 static const struct {
290         const char string[ETH_GSTRING_LEN];
291 } ethtool_stats_keys[TG3_NUM_STATS] = {
292         { "rx_octets" },
293         { "rx_fragments" },
294         { "rx_ucast_packets" },
295         { "rx_mcast_packets" },
296         { "rx_bcast_packets" },
297         { "rx_fcs_errors" },
298         { "rx_align_errors" },
299         { "rx_xon_pause_rcvd" },
300         { "rx_xoff_pause_rcvd" },
301         { "rx_mac_ctrl_rcvd" },
302         { "rx_xoff_entered" },
303         { "rx_frame_too_long_errors" },
304         { "rx_jabbers" },
305         { "rx_undersize_packets" },
306         { "rx_in_length_errors" },
307         { "rx_out_length_errors" },
308         { "rx_64_or_less_octet_packets" },
309         { "rx_65_to_127_octet_packets" },
310         { "rx_128_to_255_octet_packets" },
311         { "rx_256_to_511_octet_packets" },
312         { "rx_512_to_1023_octet_packets" },
313         { "rx_1024_to_1522_octet_packets" },
314         { "rx_1523_to_2047_octet_packets" },
315         { "rx_2048_to_4095_octet_packets" },
316         { "rx_4096_to_8191_octet_packets" },
317         { "rx_8192_to_9022_octet_packets" },
318
319         { "tx_octets" },
320         { "tx_collisions" },
321
322         { "tx_xon_sent" },
323         { "tx_xoff_sent" },
324         { "tx_flow_control" },
325         { "tx_mac_errors" },
326         { "tx_single_collisions" },
327         { "tx_mult_collisions" },
328         { "tx_deferred" },
329         { "tx_excessive_collisions" },
330         { "tx_late_collisions" },
331         { "tx_collide_2times" },
332         { "tx_collide_3times" },
333         { "tx_collide_4times" },
334         { "tx_collide_5times" },
335         { "tx_collide_6times" },
336         { "tx_collide_7times" },
337         { "tx_collide_8times" },
338         { "tx_collide_9times" },
339         { "tx_collide_10times" },
340         { "tx_collide_11times" },
341         { "tx_collide_12times" },
342         { "tx_collide_13times" },
343         { "tx_collide_14times" },
344         { "tx_collide_15times" },
345         { "tx_ucast_packets" },
346         { "tx_mcast_packets" },
347         { "tx_bcast_packets" },
348         { "tx_carrier_sense_errors" },
349         { "tx_discards" },
350         { "tx_errors" },
351
352         { "dma_writeq_full" },
353         { "dma_write_prioq_full" },
354         { "rxbds_empty" },
355         { "rx_discards" },
356         { "rx_errors" },
357         { "rx_threshold_hit" },
358
359         { "dma_readq_full" },
360         { "dma_read_prioq_full" },
361         { "tx_comp_queue_full" },
362
363         { "ring_set_send_prod_index" },
364         { "ring_status_update" },
365         { "nic_irqs" },
366         { "nic_avoided_irqs" },
367         { "nic_tx_threshold_hit" }
368 };
369
370 static const struct {
371         const char string[ETH_GSTRING_LEN];
372 } ethtool_test_keys[TG3_NUM_TEST] = {
373         { "nvram test     (online) " },
374         { "link test      (online) " },
375         { "register test  (offline)" },
376         { "memory test    (offline)" },
377         { "loopback test  (offline)" },
378         { "interrupt test (offline)" },
379 };
380
381 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
382 {
383         writel(val, tp->regs + off);
384 }
385
386 static u32 tg3_read32(struct tg3 *tp, u32 off)
387 {
388         return readl(tp->regs + off);
389 }
390
391 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
392 {
393         writel(val, tp->aperegs + off);
394 }
395
396 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
397 {
398         return readl(tp->aperegs + off);
399 }
400
401 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
402 {
403         unsigned long flags;
404
405         spin_lock_irqsave(&tp->indirect_lock, flags);
406         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
407         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
408         spin_unlock_irqrestore(&tp->indirect_lock, flags);
409 }
410
411 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
412 {
413         writel(val, tp->regs + off);
414         readl(tp->regs + off);
415 }
416
417 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
418 {
419         unsigned long flags;
420         u32 val;
421
422         spin_lock_irqsave(&tp->indirect_lock, flags);
423         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
424         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
425         spin_unlock_irqrestore(&tp->indirect_lock, flags);
426         return val;
427 }
428
429 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
430 {
431         unsigned long flags;
432
433         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
434                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
435                                        TG3_64BIT_REG_LOW, val);
436                 return;
437         }
438         if (off == TG3_RX_STD_PROD_IDX_REG) {
439                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
440                                        TG3_64BIT_REG_LOW, val);
441                 return;
442         }
443
444         spin_lock_irqsave(&tp->indirect_lock, flags);
445         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
446         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
447         spin_unlock_irqrestore(&tp->indirect_lock, flags);
448
449         /* In indirect mode when disabling interrupts, we also need
450          * to clear the interrupt bit in the GRC local ctrl register.
451          */
452         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
453             (val == 0x1)) {
454                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
455                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
456         }
457 }
458
459 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
460 {
461         unsigned long flags;
462         u32 val;
463
464         spin_lock_irqsave(&tp->indirect_lock, flags);
465         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
466         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
467         spin_unlock_irqrestore(&tp->indirect_lock, flags);
468         return val;
469 }
470
471 /* usec_wait specifies the wait time in usec when writing to certain registers
472  * where it is unsafe to read back the register without some delay.
473  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
474  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
475  */
476 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
477 {
478         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
479             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
480                 /* Non-posted methods */
481                 tp->write32(tp, off, val);
482         else {
483                 /* Posted method */
484                 tg3_write32(tp, off, val);
485                 if (usec_wait)
486                         udelay(usec_wait);
487                 tp->read32(tp, off);
488         }
489         /* Wait again after the read for the posted method to guarantee that
490          * the wait time is met.
491          */
492         if (usec_wait)
493                 udelay(usec_wait);
494 }
495
496 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
497 {
498         tp->write32_mbox(tp, off, val);
499         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
500             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
501                 tp->read32_mbox(tp, off);
502 }
503
504 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
505 {
506         void __iomem *mbox = tp->regs + off;
507         writel(val, mbox);
508         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
509                 writel(val, mbox);
510         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
511                 readl(mbox);
512 }
513
514 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
515 {
516         return readl(tp->regs + off + GRCMBOX_BASE);
517 }
518
519 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
520 {
521         writel(val, tp->regs + off + GRCMBOX_BASE);
522 }
523
524 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
525 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
526 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
527 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
528 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
529
530 #define tw32(reg, val)                  tp->write32(tp, reg, val)
531 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
532 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
533 #define tr32(reg)                       tp->read32(tp, reg)
534
535 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
536 {
537         unsigned long flags;
538
539         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
540             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
541                 return;
542
543         spin_lock_irqsave(&tp->indirect_lock, flags);
544         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
545                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
546                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
547
548                 /* Always leave this as zero. */
549                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
550         } else {
551                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
552                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
553
554                 /* Always leave this as zero. */
555                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
556         }
557         spin_unlock_irqrestore(&tp->indirect_lock, flags);
558 }
559
560 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
561 {
562         unsigned long flags;
563
564         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
565             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
566                 *val = 0;
567                 return;
568         }
569
570         spin_lock_irqsave(&tp->indirect_lock, flags);
571         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
572                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
573                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
574
575                 /* Always leave this as zero. */
576                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
577         } else {
578                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
579                 *val = tr32(TG3PCI_MEM_WIN_DATA);
580
581                 /* Always leave this as zero. */
582                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
583         }
584         spin_unlock_irqrestore(&tp->indirect_lock, flags);
585 }
586
587 static void tg3_ape_lock_init(struct tg3 *tp)
588 {
589         int i;
590         u32 regbase;
591
592         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
593                 regbase = TG3_APE_LOCK_GRANT;
594         else
595                 regbase = TG3_APE_PER_LOCK_GRANT;
596
597         /* Make sure the driver hasn't any stale locks. */
598         for (i = 0; i < 8; i++)
599                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
600 }
601
602 static int tg3_ape_lock(struct tg3 *tp, int locknum)
603 {
604         int i, off;
605         int ret = 0;
606         u32 status, req, gnt;
607
608         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
609                 return 0;
610
611         switch (locknum) {
612         case TG3_APE_LOCK_GRC:
613         case TG3_APE_LOCK_MEM:
614                 break;
615         default:
616                 return -EINVAL;
617         }
618
619         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
620                 req = TG3_APE_LOCK_REQ;
621                 gnt = TG3_APE_LOCK_GRANT;
622         } else {
623                 req = TG3_APE_PER_LOCK_REQ;
624                 gnt = TG3_APE_PER_LOCK_GRANT;
625         }
626
627         off = 4 * locknum;
628
629         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
630
631         /* Wait for up to 1 millisecond to acquire lock. */
632         for (i = 0; i < 100; i++) {
633                 status = tg3_ape_read32(tp, gnt + off);
634                 if (status == APE_LOCK_GRANT_DRIVER)
635                         break;
636                 udelay(10);
637         }
638
639         if (status != APE_LOCK_GRANT_DRIVER) {
640                 /* Revoke the lock request. */
641                 tg3_ape_write32(tp, gnt + off,
642                                 APE_LOCK_GRANT_DRIVER);
643
644                 ret = -EBUSY;
645         }
646
647         return ret;
648 }
649
650 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
651 {
652         u32 gnt;
653
654         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
655                 return;
656
657         switch (locknum) {
658         case TG3_APE_LOCK_GRC:
659         case TG3_APE_LOCK_MEM:
660                 break;
661         default:
662                 return;
663         }
664
665         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
666                 gnt = TG3_APE_LOCK_GRANT;
667         else
668                 gnt = TG3_APE_PER_LOCK_GRANT;
669
670         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
671 }
672
673 static void tg3_disable_ints(struct tg3 *tp)
674 {
675         int i;
676
677         tw32(TG3PCI_MISC_HOST_CTRL,
678              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
679         for (i = 0; i < tp->irq_max; i++)
680                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
681 }
682
683 static void tg3_enable_ints(struct tg3 *tp)
684 {
685         int i;
686
687         tp->irq_sync = 0;
688         wmb();
689
690         tw32(TG3PCI_MISC_HOST_CTRL,
691              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
692
693         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
694         for (i = 0; i < tp->irq_cnt; i++) {
695                 struct tg3_napi *tnapi = &tp->napi[i];
696
697                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
698                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
699                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
700
701                 tp->coal_now |= tnapi->coal_now;
702         }
703
704         /* Force an initial interrupt */
705         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
706             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
707                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
708         else
709                 tw32(HOSTCC_MODE, tp->coal_now);
710
711         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
712 }
713
714 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
715 {
716         struct tg3 *tp = tnapi->tp;
717         struct tg3_hw_status *sblk = tnapi->hw_status;
718         unsigned int work_exists = 0;
719
720         /* check for phy events */
721         if (!(tp->tg3_flags &
722               (TG3_FLAG_USE_LINKCHG_REG |
723                TG3_FLAG_POLL_SERDES))) {
724                 if (sblk->status & SD_STATUS_LINK_CHG)
725                         work_exists = 1;
726         }
727         /* check for RX/TX work to do */
728         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
729             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
730                 work_exists = 1;
731
732         return work_exists;
733 }
734
735 /* tg3_int_reenable
736  *  similar to tg3_enable_ints, but it accurately determines whether there
737  *  is new work pending and can return without flushing the PIO write
738  *  which reenables interrupts
739  */
740 static void tg3_int_reenable(struct tg3_napi *tnapi)
741 {
742         struct tg3 *tp = tnapi->tp;
743
744         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
745         mmiowb();
746
747         /* When doing tagged status, this work check is unnecessary.
748          * The last_tag we write above tells the chip which piece of
749          * work we've completed.
750          */
751         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
752             tg3_has_work(tnapi))
753                 tw32(HOSTCC_MODE, tp->coalesce_mode |
754                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
755 }
756
757 static void tg3_switch_clocks(struct tg3 *tp)
758 {
759         u32 clock_ctrl;
760         u32 orig_clock_ctrl;
761
762         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
763             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
764                 return;
765
766         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
767
768         orig_clock_ctrl = clock_ctrl;
769         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
770                        CLOCK_CTRL_CLKRUN_OENABLE |
771                        0x1f);
772         tp->pci_clock_ctrl = clock_ctrl;
773
774         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
775                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
776                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
777                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
778                 }
779         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
780                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
781                             clock_ctrl |
782                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
783                             40);
784                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
785                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
786                             40);
787         }
788         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
789 }
790
791 #define PHY_BUSY_LOOPS  5000
792
793 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
794 {
795         u32 frame_val;
796         unsigned int loops;
797         int ret;
798
799         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
800                 tw32_f(MAC_MI_MODE,
801                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
802                 udelay(80);
803         }
804
805         *val = 0x0;
806
807         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
808                       MI_COM_PHY_ADDR_MASK);
809         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
810                       MI_COM_REG_ADDR_MASK);
811         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
812
813         tw32_f(MAC_MI_COM, frame_val);
814
815         loops = PHY_BUSY_LOOPS;
816         while (loops != 0) {
817                 udelay(10);
818                 frame_val = tr32(MAC_MI_COM);
819
820                 if ((frame_val & MI_COM_BUSY) == 0) {
821                         udelay(5);
822                         frame_val = tr32(MAC_MI_COM);
823                         break;
824                 }
825                 loops -= 1;
826         }
827
828         ret = -EBUSY;
829         if (loops != 0) {
830                 *val = frame_val & MI_COM_DATA_MASK;
831                 ret = 0;
832         }
833
834         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
835                 tw32_f(MAC_MI_MODE, tp->mi_mode);
836                 udelay(80);
837         }
838
839         return ret;
840 }
841
842 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
843 {
844         u32 frame_val;
845         unsigned int loops;
846         int ret;
847
848         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
849             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
850                 return 0;
851
852         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
853                 tw32_f(MAC_MI_MODE,
854                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
855                 udelay(80);
856         }
857
858         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
859                       MI_COM_PHY_ADDR_MASK);
860         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
861                       MI_COM_REG_ADDR_MASK);
862         frame_val |= (val & MI_COM_DATA_MASK);
863         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
864
865         tw32_f(MAC_MI_COM, frame_val);
866
867         loops = PHY_BUSY_LOOPS;
868         while (loops != 0) {
869                 udelay(10);
870                 frame_val = tr32(MAC_MI_COM);
871                 if ((frame_val & MI_COM_BUSY) == 0) {
872                         udelay(5);
873                         frame_val = tr32(MAC_MI_COM);
874                         break;
875                 }
876                 loops -= 1;
877         }
878
879         ret = -EBUSY;
880         if (loops != 0)
881                 ret = 0;
882
883         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
884                 tw32_f(MAC_MI_MODE, tp->mi_mode);
885                 udelay(80);
886         }
887
888         return ret;
889 }
890
891 static int tg3_bmcr_reset(struct tg3 *tp)
892 {
893         u32 phy_control;
894         int limit, err;
895
896         /* OK, reset it, and poll the BMCR_RESET bit until it
897          * clears or we time out.
898          */
899         phy_control = BMCR_RESET;
900         err = tg3_writephy(tp, MII_BMCR, phy_control);
901         if (err != 0)
902                 return -EBUSY;
903
904         limit = 5000;
905         while (limit--) {
906                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
907                 if (err != 0)
908                         return -EBUSY;
909
910                 if ((phy_control & BMCR_RESET) == 0) {
911                         udelay(40);
912                         break;
913                 }
914                 udelay(10);
915         }
916         if (limit < 0)
917                 return -EBUSY;
918
919         return 0;
920 }
921
922 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
923 {
924         struct tg3 *tp = bp->priv;
925         u32 val;
926
927         spin_lock_bh(&tp->lock);
928
929         if (tg3_readphy(tp, reg, &val))
930                 val = -EIO;
931
932         spin_unlock_bh(&tp->lock);
933
934         return val;
935 }
936
937 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
938 {
939         struct tg3 *tp = bp->priv;
940         u32 ret = 0;
941
942         spin_lock_bh(&tp->lock);
943
944         if (tg3_writephy(tp, reg, val))
945                 ret = -EIO;
946
947         spin_unlock_bh(&tp->lock);
948
949         return ret;
950 }
951
952 static int tg3_mdio_reset(struct mii_bus *bp)
953 {
954         return 0;
955 }
956
957 static void tg3_mdio_config_5785(struct tg3 *tp)
958 {
959         u32 val;
960         struct phy_device *phydev;
961
962         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
963         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
964         case PHY_ID_BCM50610:
965         case PHY_ID_BCM50610M:
966                 val = MAC_PHYCFG2_50610_LED_MODES;
967                 break;
968         case PHY_ID_BCMAC131:
969                 val = MAC_PHYCFG2_AC131_LED_MODES;
970                 break;
971         case PHY_ID_RTL8211C:
972                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
973                 break;
974         case PHY_ID_RTL8201E:
975                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
976                 break;
977         default:
978                 return;
979         }
980
981         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
982                 tw32(MAC_PHYCFG2, val);
983
984                 val = tr32(MAC_PHYCFG1);
985                 val &= ~(MAC_PHYCFG1_RGMII_INT |
986                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
987                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
988                 tw32(MAC_PHYCFG1, val);
989
990                 return;
991         }
992
993         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
994                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
995                        MAC_PHYCFG2_FMODE_MASK_MASK |
996                        MAC_PHYCFG2_GMODE_MASK_MASK |
997                        MAC_PHYCFG2_ACT_MASK_MASK   |
998                        MAC_PHYCFG2_QUAL_MASK_MASK |
999                        MAC_PHYCFG2_INBAND_ENABLE;
1000
1001         tw32(MAC_PHYCFG2, val);
1002
1003         val = tr32(MAC_PHYCFG1);
1004         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1005                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1006         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1007                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1008                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1009                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1010                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1011         }
1012         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1013                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1014         tw32(MAC_PHYCFG1, val);
1015
1016         val = tr32(MAC_EXT_RGMII_MODE);
1017         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1018                  MAC_RGMII_MODE_RX_QUALITY |
1019                  MAC_RGMII_MODE_RX_ACTIVITY |
1020                  MAC_RGMII_MODE_RX_ENG_DET |
1021                  MAC_RGMII_MODE_TX_ENABLE |
1022                  MAC_RGMII_MODE_TX_LOWPWR |
1023                  MAC_RGMII_MODE_TX_RESET);
1024         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1025                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1026                         val |= MAC_RGMII_MODE_RX_INT_B |
1027                                MAC_RGMII_MODE_RX_QUALITY |
1028                                MAC_RGMII_MODE_RX_ACTIVITY |
1029                                MAC_RGMII_MODE_RX_ENG_DET;
1030                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1031                         val |= MAC_RGMII_MODE_TX_ENABLE |
1032                                MAC_RGMII_MODE_TX_LOWPWR |
1033                                MAC_RGMII_MODE_TX_RESET;
1034         }
1035         tw32(MAC_EXT_RGMII_MODE, val);
1036 }
1037
1038 static void tg3_mdio_start(struct tg3 *tp)
1039 {
1040         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1041         tw32_f(MAC_MI_MODE, tp->mi_mode);
1042         udelay(80);
1043
1044         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1045             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1046                 tg3_mdio_config_5785(tp);
1047 }
1048
1049 static int tg3_mdio_init(struct tg3 *tp)
1050 {
1051         int i;
1052         u32 reg;
1053         struct phy_device *phydev;
1054
1055         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1056             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
1057                 u32 is_serdes;
1058
1059                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1060
1061                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1062                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1063                 else
1064                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1065                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1066                 if (is_serdes)
1067                         tp->phy_addr += 7;
1068         } else
1069                 tp->phy_addr = TG3_PHY_MII_ADDR;
1070
1071         tg3_mdio_start(tp);
1072
1073         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1074             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1075                 return 0;
1076
1077         tp->mdio_bus = mdiobus_alloc();
1078         if (tp->mdio_bus == NULL)
1079                 return -ENOMEM;
1080
1081         tp->mdio_bus->name     = "tg3 mdio bus";
1082         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1083                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1084         tp->mdio_bus->priv     = tp;
1085         tp->mdio_bus->parent   = &tp->pdev->dev;
1086         tp->mdio_bus->read     = &tg3_mdio_read;
1087         tp->mdio_bus->write    = &tg3_mdio_write;
1088         tp->mdio_bus->reset    = &tg3_mdio_reset;
1089         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1090         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1091
1092         for (i = 0; i < PHY_MAX_ADDR; i++)
1093                 tp->mdio_bus->irq[i] = PHY_POLL;
1094
1095         /* The bus registration will look for all the PHYs on the mdio bus.
1096          * Unfortunately, it does not ensure the PHY is powered up before
1097          * accessing the PHY ID registers.  A chip reset is the
1098          * quickest way to bring the device back to an operational state..
1099          */
1100         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1101                 tg3_bmcr_reset(tp);
1102
1103         i = mdiobus_register(tp->mdio_bus);
1104         if (i) {
1105                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1106                 mdiobus_free(tp->mdio_bus);
1107                 return i;
1108         }
1109
1110         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1111
1112         if (!phydev || !phydev->drv) {
1113                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1114                 mdiobus_unregister(tp->mdio_bus);
1115                 mdiobus_free(tp->mdio_bus);
1116                 return -ENODEV;
1117         }
1118
1119         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1120         case PHY_ID_BCM57780:
1121                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1122                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1123                 break;
1124         case PHY_ID_BCM50610:
1125         case PHY_ID_BCM50610M:
1126                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1127                                      PHY_BRCM_RX_REFCLK_UNUSED |
1128                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1129                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1130                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1131                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1132                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1133                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1134                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1135                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1136                 /* fallthru */
1137         case PHY_ID_RTL8211C:
1138                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1139                 break;
1140         case PHY_ID_RTL8201E:
1141         case PHY_ID_BCMAC131:
1142                 phydev->interface = PHY_INTERFACE_MODE_MII;
1143                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1144                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1145                 break;
1146         }
1147
1148         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1149
1150         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1151                 tg3_mdio_config_5785(tp);
1152
1153         return 0;
1154 }
1155
1156 static void tg3_mdio_fini(struct tg3 *tp)
1157 {
1158         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1159                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1160                 mdiobus_unregister(tp->mdio_bus);
1161                 mdiobus_free(tp->mdio_bus);
1162         }
1163 }
1164
1165 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1166 {
1167         int err;
1168
1169         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1170         if (err)
1171                 goto done;
1172
1173         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1174         if (err)
1175                 goto done;
1176
1177         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1178                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1179         if (err)
1180                 goto done;
1181
1182         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1183
1184 done:
1185         return err;
1186 }
1187
1188 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1189 {
1190         int err;
1191
1192         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1193         if (err)
1194                 goto done;
1195
1196         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1197         if (err)
1198                 goto done;
1199
1200         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1201                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1202         if (err)
1203                 goto done;
1204
1205         err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1206
1207 done:
1208         return err;
1209 }
1210
1211 /* tp->lock is held. */
1212 static inline void tg3_generate_fw_event(struct tg3 *tp)
1213 {
1214         u32 val;
1215
1216         val = tr32(GRC_RX_CPU_EVENT);
1217         val |= GRC_RX_CPU_DRIVER_EVENT;
1218         tw32_f(GRC_RX_CPU_EVENT, val);
1219
1220         tp->last_event_jiffies = jiffies;
1221 }
1222
1223 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1224
1225 /* tp->lock is held. */
1226 static void tg3_wait_for_event_ack(struct tg3 *tp)
1227 {
1228         int i;
1229         unsigned int delay_cnt;
1230         long time_remain;
1231
1232         /* If enough time has passed, no wait is necessary. */
1233         time_remain = (long)(tp->last_event_jiffies + 1 +
1234                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1235                       (long)jiffies;
1236         if (time_remain < 0)
1237                 return;
1238
1239         /* Check if we can shorten the wait time. */
1240         delay_cnt = jiffies_to_usecs(time_remain);
1241         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1242                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1243         delay_cnt = (delay_cnt >> 3) + 1;
1244
1245         for (i = 0; i < delay_cnt; i++) {
1246                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1247                         break;
1248                 udelay(8);
1249         }
1250 }
1251
1252 /* tp->lock is held. */
1253 static void tg3_ump_link_report(struct tg3 *tp)
1254 {
1255         u32 reg;
1256         u32 val;
1257
1258         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1259             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1260                 return;
1261
1262         tg3_wait_for_event_ack(tp);
1263
1264         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1265
1266         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1267
1268         val = 0;
1269         if (!tg3_readphy(tp, MII_BMCR, &reg))
1270                 val = reg << 16;
1271         if (!tg3_readphy(tp, MII_BMSR, &reg))
1272                 val |= (reg & 0xffff);
1273         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1274
1275         val = 0;
1276         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1277                 val = reg << 16;
1278         if (!tg3_readphy(tp, MII_LPA, &reg))
1279                 val |= (reg & 0xffff);
1280         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1281
1282         val = 0;
1283         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1284                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1285                         val = reg << 16;
1286                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1287                         val |= (reg & 0xffff);
1288         }
1289         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1290
1291         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1292                 val = reg << 16;
1293         else
1294                 val = 0;
1295         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1296
1297         tg3_generate_fw_event(tp);
1298 }
1299
1300 static void tg3_link_report(struct tg3 *tp)
1301 {
1302         if (!netif_carrier_ok(tp->dev)) {
1303                 netif_info(tp, link, tp->dev, "Link is down\n");
1304                 tg3_ump_link_report(tp);
1305         } else if (netif_msg_link(tp)) {
1306                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1307                             (tp->link_config.active_speed == SPEED_1000 ?
1308                              1000 :
1309                              (tp->link_config.active_speed == SPEED_100 ?
1310                               100 : 10)),
1311                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1312                              "full" : "half"));
1313
1314                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1315                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1316                             "on" : "off",
1317                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1318                             "on" : "off");
1319                 tg3_ump_link_report(tp);
1320         }
1321 }
1322
1323 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1324 {
1325         u16 miireg;
1326
1327         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1328                 miireg = ADVERTISE_PAUSE_CAP;
1329         else if (flow_ctrl & FLOW_CTRL_TX)
1330                 miireg = ADVERTISE_PAUSE_ASYM;
1331         else if (flow_ctrl & FLOW_CTRL_RX)
1332                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1333         else
1334                 miireg = 0;
1335
1336         return miireg;
1337 }
1338
1339 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1340 {
1341         u16 miireg;
1342
1343         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1344                 miireg = ADVERTISE_1000XPAUSE;
1345         else if (flow_ctrl & FLOW_CTRL_TX)
1346                 miireg = ADVERTISE_1000XPSE_ASYM;
1347         else if (flow_ctrl & FLOW_CTRL_RX)
1348                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1349         else
1350                 miireg = 0;
1351
1352         return miireg;
1353 }
1354
1355 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1356 {
1357         u8 cap = 0;
1358
1359         if (lcladv & ADVERTISE_1000XPAUSE) {
1360                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1361                         if (rmtadv & LPA_1000XPAUSE)
1362                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1363                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1364                                 cap = FLOW_CTRL_RX;
1365                 } else {
1366                         if (rmtadv & LPA_1000XPAUSE)
1367                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1368                 }
1369         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1370                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1371                         cap = FLOW_CTRL_TX;
1372         }
1373
1374         return cap;
1375 }
1376
1377 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1378 {
1379         u8 autoneg;
1380         u8 flowctrl = 0;
1381         u32 old_rx_mode = tp->rx_mode;
1382         u32 old_tx_mode = tp->tx_mode;
1383
1384         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1385                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1386         else
1387                 autoneg = tp->link_config.autoneg;
1388
1389         if (autoneg == AUTONEG_ENABLE &&
1390             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1391                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1392                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1393                 else
1394                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1395         } else
1396                 flowctrl = tp->link_config.flowctrl;
1397
1398         tp->link_config.active_flowctrl = flowctrl;
1399
1400         if (flowctrl & FLOW_CTRL_RX)
1401                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1402         else
1403                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1404
1405         if (old_rx_mode != tp->rx_mode)
1406                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1407
1408         if (flowctrl & FLOW_CTRL_TX)
1409                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1410         else
1411                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1412
1413         if (old_tx_mode != tp->tx_mode)
1414                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1415 }
1416
1417 static void tg3_adjust_link(struct net_device *dev)
1418 {
1419         u8 oldflowctrl, linkmesg = 0;
1420         u32 mac_mode, lcl_adv, rmt_adv;
1421         struct tg3 *tp = netdev_priv(dev);
1422         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1423
1424         spin_lock_bh(&tp->lock);
1425
1426         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1427                                     MAC_MODE_HALF_DUPLEX);
1428
1429         oldflowctrl = tp->link_config.active_flowctrl;
1430
1431         if (phydev->link) {
1432                 lcl_adv = 0;
1433                 rmt_adv = 0;
1434
1435                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1436                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1437                 else if (phydev->speed == SPEED_1000 ||
1438                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1439                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1440                 else
1441                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1442
1443                 if (phydev->duplex == DUPLEX_HALF)
1444                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1445                 else {
1446                         lcl_adv = tg3_advert_flowctrl_1000T(
1447                                   tp->link_config.flowctrl);
1448
1449                         if (phydev->pause)
1450                                 rmt_adv = LPA_PAUSE_CAP;
1451                         if (phydev->asym_pause)
1452                                 rmt_adv |= LPA_PAUSE_ASYM;
1453                 }
1454
1455                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1456         } else
1457                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1458
1459         if (mac_mode != tp->mac_mode) {
1460                 tp->mac_mode = mac_mode;
1461                 tw32_f(MAC_MODE, tp->mac_mode);
1462                 udelay(40);
1463         }
1464
1465         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1466                 if (phydev->speed == SPEED_10)
1467                         tw32(MAC_MI_STAT,
1468                              MAC_MI_STAT_10MBPS_MODE |
1469                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1470                 else
1471                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1472         }
1473
1474         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1475                 tw32(MAC_TX_LENGTHS,
1476                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1477                       (6 << TX_LENGTHS_IPG_SHIFT) |
1478                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1479         else
1480                 tw32(MAC_TX_LENGTHS,
1481                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1482                       (6 << TX_LENGTHS_IPG_SHIFT) |
1483                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1484
1485         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1486             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1487             phydev->speed != tp->link_config.active_speed ||
1488             phydev->duplex != tp->link_config.active_duplex ||
1489             oldflowctrl != tp->link_config.active_flowctrl)
1490                 linkmesg = 1;
1491
1492         tp->link_config.active_speed = phydev->speed;
1493         tp->link_config.active_duplex = phydev->duplex;
1494
1495         spin_unlock_bh(&tp->lock);
1496
1497         if (linkmesg)
1498                 tg3_link_report(tp);
1499 }
1500
1501 static int tg3_phy_init(struct tg3 *tp)
1502 {
1503         struct phy_device *phydev;
1504
1505         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1506                 return 0;
1507
1508         /* Bring the PHY back to a known state. */
1509         tg3_bmcr_reset(tp);
1510
1511         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1512
1513         /* Attach the MAC to the PHY. */
1514         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1515                              phydev->dev_flags, phydev->interface);
1516         if (IS_ERR(phydev)) {
1517                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1518                 return PTR_ERR(phydev);
1519         }
1520
1521         /* Mask with MAC supported features. */
1522         switch (phydev->interface) {
1523         case PHY_INTERFACE_MODE_GMII:
1524         case PHY_INTERFACE_MODE_RGMII:
1525                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1526                         phydev->supported &= (PHY_GBIT_FEATURES |
1527                                               SUPPORTED_Pause |
1528                                               SUPPORTED_Asym_Pause);
1529                         break;
1530                 }
1531                 /* fallthru */
1532         case PHY_INTERFACE_MODE_MII:
1533                 phydev->supported &= (PHY_BASIC_FEATURES |
1534                                       SUPPORTED_Pause |
1535                                       SUPPORTED_Asym_Pause);
1536                 break;
1537         default:
1538                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1539                 return -EINVAL;
1540         }
1541
1542         tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1543
1544         phydev->advertising = phydev->supported;
1545
1546         return 0;
1547 }
1548
1549 static void tg3_phy_start(struct tg3 *tp)
1550 {
1551         struct phy_device *phydev;
1552
1553         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1554                 return;
1555
1556         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1557
1558         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1559                 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1560                 phydev->speed = tp->link_config.orig_speed;
1561                 phydev->duplex = tp->link_config.orig_duplex;
1562                 phydev->autoneg = tp->link_config.orig_autoneg;
1563                 phydev->advertising = tp->link_config.orig_advertising;
1564         }
1565
1566         phy_start(phydev);
1567
1568         phy_start_aneg(phydev);
1569 }
1570
1571 static void tg3_phy_stop(struct tg3 *tp)
1572 {
1573         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1574                 return;
1575
1576         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1577 }
1578
1579 static void tg3_phy_fini(struct tg3 *tp)
1580 {
1581         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1582                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1583                 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1584         }
1585 }
1586
1587 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1588 {
1589         int err;
1590
1591         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1592         if (!err)
1593                 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1594
1595         return err;
1596 }
1597
1598 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1599 {
1600         int err;
1601
1602         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1603         if (!err)
1604                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1605
1606         return err;
1607 }
1608
1609 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1610 {
1611         u32 phytest;
1612
1613         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1614                 u32 phy;
1615
1616                 tg3_writephy(tp, MII_TG3_FET_TEST,
1617                              phytest | MII_TG3_FET_SHADOW_EN);
1618                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1619                         if (enable)
1620                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1621                         else
1622                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1623                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1624                 }
1625                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1626         }
1627 }
1628
1629 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1630 {
1631         u32 reg;
1632
1633         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1634             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1635               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1636              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1637                 return;
1638
1639         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1640                 tg3_phy_fet_toggle_apd(tp, enable);
1641                 return;
1642         }
1643
1644         reg = MII_TG3_MISC_SHDW_WREN |
1645               MII_TG3_MISC_SHDW_SCR5_SEL |
1646               MII_TG3_MISC_SHDW_SCR5_LPED |
1647               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1648               MII_TG3_MISC_SHDW_SCR5_SDTL |
1649               MII_TG3_MISC_SHDW_SCR5_C125OE;
1650         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1651                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1652
1653         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1654
1655
1656         reg = MII_TG3_MISC_SHDW_WREN |
1657               MII_TG3_MISC_SHDW_APD_SEL |
1658               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1659         if (enable)
1660                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1661
1662         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1663 }
1664
1665 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1666 {
1667         u32 phy;
1668
1669         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1670             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1671                 return;
1672
1673         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1674                 u32 ephy;
1675
1676                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1677                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1678
1679                         tg3_writephy(tp, MII_TG3_FET_TEST,
1680                                      ephy | MII_TG3_FET_SHADOW_EN);
1681                         if (!tg3_readphy(tp, reg, &phy)) {
1682                                 if (enable)
1683                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1684                                 else
1685                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1686                                 tg3_writephy(tp, reg, phy);
1687                         }
1688                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1689                 }
1690         } else {
1691                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1692                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1693                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1694                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1695                         if (enable)
1696                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1697                         else
1698                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1699                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1700                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1701                 }
1702         }
1703 }
1704
1705 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1706 {
1707         u32 val;
1708
1709         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1710                 return;
1711
1712         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1713             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1714                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1715                              (val | (1 << 15) | (1 << 4)));
1716 }
1717
1718 static void tg3_phy_apply_otp(struct tg3 *tp)
1719 {
1720         u32 otp, phy;
1721
1722         if (!tp->phy_otp)
1723                 return;
1724
1725         otp = tp->phy_otp;
1726
1727         /* Enable SM_DSP clock and tx 6dB coding. */
1728         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1729               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1730               MII_TG3_AUXCTL_ACTL_TX_6DB;
1731         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1732
1733         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1734         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1735         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1736
1737         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1738               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1739         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1740
1741         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1742         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1743         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1744
1745         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1746         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1747
1748         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1749         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1750
1751         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1752               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1753         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1754
1755         /* Turn off SM_DSP clock. */
1756         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1757               MII_TG3_AUXCTL_ACTL_TX_6DB;
1758         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1759 }
1760
1761 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
1762 {
1763         u32 val;
1764
1765         if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
1766                 return;
1767
1768         tp->setlpicnt = 0;
1769
1770         if (tp->link_config.autoneg == AUTONEG_ENABLE &&
1771             current_link_up == 1 &&
1772             (tp->link_config.active_speed == SPEED_1000 ||
1773              (tp->link_config.active_speed == SPEED_100 &&
1774               tp->link_config.active_duplex == DUPLEX_FULL))) {
1775                 u32 eeectl;
1776
1777                 if (tp->link_config.active_speed == SPEED_1000)
1778                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
1779                 else
1780                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
1781
1782                 tw32(TG3_CPMU_EEE_CTRL, eeectl);
1783
1784                 tg3_phy_cl45_read(tp, 0x7, TG3_CL45_D7_EEERES_STAT, &val);
1785
1786                 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
1787                     val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
1788                         tp->setlpicnt = 2;
1789         }
1790
1791         if (!tp->setlpicnt) {
1792                 val = tr32(TG3_CPMU_EEE_MODE);
1793                 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
1794         }
1795 }
1796
1797 static int tg3_wait_macro_done(struct tg3 *tp)
1798 {
1799         int limit = 100;
1800
1801         while (limit--) {
1802                 u32 tmp32;
1803
1804                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1805                         if ((tmp32 & 0x1000) == 0)
1806                                 break;
1807                 }
1808         }
1809         if (limit < 0)
1810                 return -EBUSY;
1811
1812         return 0;
1813 }
1814
1815 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1816 {
1817         static const u32 test_pat[4][6] = {
1818         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1819         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1820         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1821         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1822         };
1823         int chan;
1824
1825         for (chan = 0; chan < 4; chan++) {
1826                 int i;
1827
1828                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1829                              (chan * 0x2000) | 0x0200);
1830                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1831
1832                 for (i = 0; i < 6; i++)
1833                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1834                                      test_pat[chan][i]);
1835
1836                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1837                 if (tg3_wait_macro_done(tp)) {
1838                         *resetp = 1;
1839                         return -EBUSY;
1840                 }
1841
1842                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1843                              (chan * 0x2000) | 0x0200);
1844                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1845                 if (tg3_wait_macro_done(tp)) {
1846                         *resetp = 1;
1847                         return -EBUSY;
1848                 }
1849
1850                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1851                 if (tg3_wait_macro_done(tp)) {
1852                         *resetp = 1;
1853                         return -EBUSY;
1854                 }
1855
1856                 for (i = 0; i < 6; i += 2) {
1857                         u32 low, high;
1858
1859                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1860                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1861                             tg3_wait_macro_done(tp)) {
1862                                 *resetp = 1;
1863                                 return -EBUSY;
1864                         }
1865                         low &= 0x7fff;
1866                         high &= 0x000f;
1867                         if (low != test_pat[chan][i] ||
1868                             high != test_pat[chan][i+1]) {
1869                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1870                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1871                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1872
1873                                 return -EBUSY;
1874                         }
1875                 }
1876         }
1877
1878         return 0;
1879 }
1880
1881 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1882 {
1883         int chan;
1884
1885         for (chan = 0; chan < 4; chan++) {
1886                 int i;
1887
1888                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1889                              (chan * 0x2000) | 0x0200);
1890                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1891                 for (i = 0; i < 6; i++)
1892                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1893                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1894                 if (tg3_wait_macro_done(tp))
1895                         return -EBUSY;
1896         }
1897
1898         return 0;
1899 }
1900
1901 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1902 {
1903         u32 reg32, phy9_orig;
1904         int retries, do_phy_reset, err;
1905
1906         retries = 10;
1907         do_phy_reset = 1;
1908         do {
1909                 if (do_phy_reset) {
1910                         err = tg3_bmcr_reset(tp);
1911                         if (err)
1912                                 return err;
1913                         do_phy_reset = 0;
1914                 }
1915
1916                 /* Disable transmitter and interrupt.  */
1917                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1918                         continue;
1919
1920                 reg32 |= 0x3000;
1921                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1922
1923                 /* Set full-duplex, 1000 mbps.  */
1924                 tg3_writephy(tp, MII_BMCR,
1925                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1926
1927                 /* Set to master mode.  */
1928                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1929                         continue;
1930
1931                 tg3_writephy(tp, MII_TG3_CTRL,
1932                              (MII_TG3_CTRL_AS_MASTER |
1933                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1934
1935                 /* Enable SM_DSP_CLOCK and 6dB.  */
1936                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1937
1938                 /* Block the PHY control access.  */
1939                 tg3_phydsp_write(tp, 0x8005, 0x0800);
1940
1941                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1942                 if (!err)
1943                         break;
1944         } while (--retries);
1945
1946         err = tg3_phy_reset_chanpat(tp);
1947         if (err)
1948                 return err;
1949
1950         tg3_phydsp_write(tp, 0x8005, 0x0000);
1951
1952         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1953         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1954
1955         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1956             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1957                 /* Set Extended packet length bit for jumbo frames */
1958                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1959         } else {
1960                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1961         }
1962
1963         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1964
1965         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1966                 reg32 &= ~0x3000;
1967                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1968         } else if (!err)
1969                 err = -EBUSY;
1970
1971         return err;
1972 }
1973
1974 /* This will reset the tigon3 PHY if there is no valid
1975  * link unless the FORCE argument is non-zero.
1976  */
1977 static int tg3_phy_reset(struct tg3 *tp)
1978 {
1979         u32 val, cpmuctrl;
1980         int err;
1981
1982         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1983                 val = tr32(GRC_MISC_CFG);
1984                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1985                 udelay(40);
1986         }
1987         err  = tg3_readphy(tp, MII_BMSR, &val);
1988         err |= tg3_readphy(tp, MII_BMSR, &val);
1989         if (err != 0)
1990                 return -EBUSY;
1991
1992         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1993                 netif_carrier_off(tp->dev);
1994                 tg3_link_report(tp);
1995         }
1996
1997         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1998             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1999             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2000                 err = tg3_phy_reset_5703_4_5(tp);
2001                 if (err)
2002                         return err;
2003                 goto out;
2004         }
2005
2006         cpmuctrl = 0;
2007         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2008             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2009                 cpmuctrl = tr32(TG3_CPMU_CTRL);
2010                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2011                         tw32(TG3_CPMU_CTRL,
2012                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2013         }
2014
2015         err = tg3_bmcr_reset(tp);
2016         if (err)
2017                 return err;
2018
2019         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2020                 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2021                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2022
2023                 tw32(TG3_CPMU_CTRL, cpmuctrl);
2024         }
2025
2026         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2027             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2028                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2029                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2030                     CPMU_LSPD_1000MB_MACCLK_12_5) {
2031                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2032                         udelay(40);
2033                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2034                 }
2035         }
2036
2037         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2038              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
2039             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2040                 return 0;
2041
2042         tg3_phy_apply_otp(tp);
2043
2044         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2045                 tg3_phy_toggle_apd(tp, true);
2046         else
2047                 tg3_phy_toggle_apd(tp, false);
2048
2049 out:
2050         if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
2051                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2052                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2053                 tg3_phydsp_write(tp, 0x000a, 0x0323);
2054                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2055         }
2056         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2057                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2058                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2059         }
2060         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2061                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2062                 tg3_phydsp_write(tp, 0x000a, 0x310b);
2063                 tg3_phydsp_write(tp, 0x201f, 0x9506);
2064                 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2065                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2066         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2067                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2068                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2069                 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2070                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2071                         tg3_writephy(tp, MII_TG3_TEST1,
2072                                      MII_TG3_TEST1_TRIM_EN | 0x4);
2073                 } else
2074                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2075                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2076         }
2077         /* Set Extended packet length bit (bit 14) on all chips that */
2078         /* support jumbo frames */
2079         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2080                 /* Cannot do read-modify-write on 5401 */
2081                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2082         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2083                 /* Set bit 14 with read-modify-write to preserve other bits */
2084                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2085                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
2086                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000);
2087         }
2088
2089         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2090          * jumbo frames transmission.
2091          */
2092         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2093                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2094                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2095                                      val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2096         }
2097
2098         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2099                 /* adjust output voltage */
2100                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2101         }
2102
2103         tg3_phy_toggle_automdix(tp, 1);
2104         tg3_phy_set_wirespeed(tp);
2105         return 0;
2106 }
2107
2108 static void tg3_frob_aux_power(struct tg3 *tp)
2109 {
2110         struct tg3 *tp_peer = tp;
2111
2112         /* The GPIOs do something completely different on 57765. */
2113         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2114             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2115             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2116                 return;
2117
2118         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2119             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2120             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2121                 struct net_device *dev_peer;
2122
2123                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2124                 /* remove_one() may have been run on the peer. */
2125                 if (!dev_peer)
2126                         tp_peer = tp;
2127                 else
2128                         tp_peer = netdev_priv(dev_peer);
2129         }
2130
2131         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2132             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2133             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2134             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2135                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2136                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2137                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2138                                     (GRC_LCLCTRL_GPIO_OE0 |
2139                                      GRC_LCLCTRL_GPIO_OE1 |
2140                                      GRC_LCLCTRL_GPIO_OE2 |
2141                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2142                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2143                                     100);
2144                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2145                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2146                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2147                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2148                                              GRC_LCLCTRL_GPIO_OE1 |
2149                                              GRC_LCLCTRL_GPIO_OE2 |
2150                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2151                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2152                                              tp->grc_local_ctrl;
2153                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2154
2155                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2156                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2157
2158                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2159                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2160                 } else {
2161                         u32 no_gpio2;
2162                         u32 grc_local_ctrl = 0;
2163
2164                         if (tp_peer != tp &&
2165                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2166                                 return;
2167
2168                         /* Workaround to prevent overdrawing Amps. */
2169                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2170                             ASIC_REV_5714) {
2171                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2172                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2173                                             grc_local_ctrl, 100);
2174                         }
2175
2176                         /* On 5753 and variants, GPIO2 cannot be used. */
2177                         no_gpio2 = tp->nic_sram_data_cfg &
2178                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2179
2180                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2181                                          GRC_LCLCTRL_GPIO_OE1 |
2182                                          GRC_LCLCTRL_GPIO_OE2 |
2183                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2184                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2185                         if (no_gpio2) {
2186                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2187                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2188                         }
2189                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2190                                                     grc_local_ctrl, 100);
2191
2192                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2193
2194                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2195                                                     grc_local_ctrl, 100);
2196
2197                         if (!no_gpio2) {
2198                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2199                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2200                                             grc_local_ctrl, 100);
2201                         }
2202                 }
2203         } else {
2204                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2205                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2206                         if (tp_peer != tp &&
2207                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2208                                 return;
2209
2210                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2211                                     (GRC_LCLCTRL_GPIO_OE1 |
2212                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2213
2214                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2215                                     GRC_LCLCTRL_GPIO_OE1, 100);
2216
2217                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2218                                     (GRC_LCLCTRL_GPIO_OE1 |
2219                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2220                 }
2221         }
2222 }
2223
2224 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2225 {
2226         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2227                 return 1;
2228         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2229                 if (speed != SPEED_10)
2230                         return 1;
2231         } else if (speed == SPEED_10)
2232                 return 1;
2233
2234         return 0;
2235 }
2236
2237 static int tg3_setup_phy(struct tg3 *, int);
2238
2239 #define RESET_KIND_SHUTDOWN     0
2240 #define RESET_KIND_INIT         1
2241 #define RESET_KIND_SUSPEND      2
2242
2243 static void tg3_write_sig_post_reset(struct tg3 *, int);
2244 static int tg3_halt_cpu(struct tg3 *, u32);
2245
2246 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2247 {
2248         u32 val;
2249
2250         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2251                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2252                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2253                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2254
2255                         sg_dig_ctrl |=
2256                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2257                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2258                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2259                 }
2260                 return;
2261         }
2262
2263         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2264                 tg3_bmcr_reset(tp);
2265                 val = tr32(GRC_MISC_CFG);
2266                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2267                 udelay(40);
2268                 return;
2269         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2270                 u32 phytest;
2271                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2272                         u32 phy;
2273
2274                         tg3_writephy(tp, MII_ADVERTISE, 0);
2275                         tg3_writephy(tp, MII_BMCR,
2276                                      BMCR_ANENABLE | BMCR_ANRESTART);
2277
2278                         tg3_writephy(tp, MII_TG3_FET_TEST,
2279                                      phytest | MII_TG3_FET_SHADOW_EN);
2280                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2281                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2282                                 tg3_writephy(tp,
2283                                              MII_TG3_FET_SHDW_AUXMODE4,
2284                                              phy);
2285                         }
2286                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2287                 }
2288                 return;
2289         } else if (do_low_power) {
2290                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2291                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2292
2293                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2294                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2295                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2296                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2297                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2298         }
2299
2300         /* The PHY should not be powered down on some chips because
2301          * of bugs.
2302          */
2303         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2304             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2305             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2306              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2307                 return;
2308
2309         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2310             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2311                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2312                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2313                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2314                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2315         }
2316
2317         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2318 }
2319
2320 /* tp->lock is held. */
2321 static int tg3_nvram_lock(struct tg3 *tp)
2322 {
2323         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2324                 int i;
2325
2326                 if (tp->nvram_lock_cnt == 0) {
2327                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2328                         for (i = 0; i < 8000; i++) {
2329                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2330                                         break;
2331                                 udelay(20);
2332                         }
2333                         if (i == 8000) {
2334                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2335                                 return -ENODEV;
2336                         }
2337                 }
2338                 tp->nvram_lock_cnt++;
2339         }
2340         return 0;
2341 }
2342
2343 /* tp->lock is held. */
2344 static void tg3_nvram_unlock(struct tg3 *tp)
2345 {
2346         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2347                 if (tp->nvram_lock_cnt > 0)
2348                         tp->nvram_lock_cnt--;
2349                 if (tp->nvram_lock_cnt == 0)
2350                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2351         }
2352 }
2353
2354 /* tp->lock is held. */
2355 static void tg3_enable_nvram_access(struct tg3 *tp)
2356 {
2357         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2358             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2359                 u32 nvaccess = tr32(NVRAM_ACCESS);
2360
2361                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2362         }
2363 }
2364
2365 /* tp->lock is held. */
2366 static void tg3_disable_nvram_access(struct tg3 *tp)
2367 {
2368         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2369             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2370                 u32 nvaccess = tr32(NVRAM_ACCESS);
2371
2372                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2373         }
2374 }
2375
2376 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2377                                         u32 offset, u32 *val)
2378 {
2379         u32 tmp;
2380         int i;
2381
2382         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2383                 return -EINVAL;
2384
2385         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2386                                         EEPROM_ADDR_DEVID_MASK |
2387                                         EEPROM_ADDR_READ);
2388         tw32(GRC_EEPROM_ADDR,
2389              tmp |
2390              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2391              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2392               EEPROM_ADDR_ADDR_MASK) |
2393              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2394
2395         for (i = 0; i < 1000; i++) {
2396                 tmp = tr32(GRC_EEPROM_ADDR);
2397
2398                 if (tmp & EEPROM_ADDR_COMPLETE)
2399                         break;
2400                 msleep(1);
2401         }
2402         if (!(tmp & EEPROM_ADDR_COMPLETE))
2403                 return -EBUSY;
2404
2405         tmp = tr32(GRC_EEPROM_DATA);
2406
2407         /*
2408          * The data will always be opposite the native endian
2409          * format.  Perform a blind byteswap to compensate.
2410          */
2411         *val = swab32(tmp);
2412
2413         return 0;
2414 }
2415
2416 #define NVRAM_CMD_TIMEOUT 10000
2417
2418 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2419 {
2420         int i;
2421
2422         tw32(NVRAM_CMD, nvram_cmd);
2423         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2424                 udelay(10);
2425                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2426                         udelay(10);
2427                         break;
2428                 }
2429         }
2430
2431         if (i == NVRAM_CMD_TIMEOUT)
2432                 return -EBUSY;
2433
2434         return 0;
2435 }
2436
2437 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2438 {
2439         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2440             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2441             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2442            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2443             (tp->nvram_jedecnum == JEDEC_ATMEL))
2444
2445                 addr = ((addr / tp->nvram_pagesize) <<
2446                         ATMEL_AT45DB0X1B_PAGE_POS) +
2447                        (addr % tp->nvram_pagesize);
2448
2449         return addr;
2450 }
2451
2452 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2453 {
2454         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2455             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2456             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2457            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2458             (tp->nvram_jedecnum == JEDEC_ATMEL))
2459
2460                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2461                         tp->nvram_pagesize) +
2462                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2463
2464         return addr;
2465 }
2466
2467 /* NOTE: Data read in from NVRAM is byteswapped according to
2468  * the byteswapping settings for all other register accesses.
2469  * tg3 devices are BE devices, so on a BE machine, the data
2470  * returned will be exactly as it is seen in NVRAM.  On a LE
2471  * machine, the 32-bit value will be byteswapped.
2472  */
2473 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2474 {
2475         int ret;
2476
2477         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2478                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2479
2480         offset = tg3_nvram_phys_addr(tp, offset);
2481
2482         if (offset > NVRAM_ADDR_MSK)
2483                 return -EINVAL;
2484
2485         ret = tg3_nvram_lock(tp);
2486         if (ret)
2487                 return ret;
2488
2489         tg3_enable_nvram_access(tp);
2490
2491         tw32(NVRAM_ADDR, offset);
2492         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2493                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2494
2495         if (ret == 0)
2496                 *val = tr32(NVRAM_RDDATA);
2497
2498         tg3_disable_nvram_access(tp);
2499
2500         tg3_nvram_unlock(tp);
2501
2502         return ret;
2503 }
2504
2505 /* Ensures NVRAM data is in bytestream format. */
2506 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2507 {
2508         u32 v;
2509         int res = tg3_nvram_read(tp, offset, &v);
2510         if (!res)
2511                 *val = cpu_to_be32(v);
2512         return res;
2513 }
2514
2515 /* tp->lock is held. */
2516 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2517 {
2518         u32 addr_high, addr_low;
2519         int i;
2520
2521         addr_high = ((tp->dev->dev_addr[0] << 8) |
2522                      tp->dev->dev_addr[1]);
2523         addr_low = ((tp->dev->dev_addr[2] << 24) |
2524                     (tp->dev->dev_addr[3] << 16) |
2525                     (tp->dev->dev_addr[4] <<  8) |
2526                     (tp->dev->dev_addr[5] <<  0));
2527         for (i = 0; i < 4; i++) {
2528                 if (i == 1 && skip_mac_1)
2529                         continue;
2530                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2531                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2532         }
2533
2534         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2535             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2536                 for (i = 0; i < 12; i++) {
2537                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2538                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2539                 }
2540         }
2541
2542         addr_high = (tp->dev->dev_addr[0] +
2543                      tp->dev->dev_addr[1] +
2544                      tp->dev->dev_addr[2] +
2545                      tp->dev->dev_addr[3] +
2546                      tp->dev->dev_addr[4] +
2547                      tp->dev->dev_addr[5]) &
2548                 TX_BACKOFF_SEED_MASK;
2549         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2550 }
2551
2552 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2553 {
2554         u32 misc_host_ctrl;
2555         bool device_should_wake, do_low_power;
2556
2557         /* Make sure register accesses (indirect or otherwise)
2558          * will function correctly.
2559          */
2560         pci_write_config_dword(tp->pdev,
2561                                TG3PCI_MISC_HOST_CTRL,
2562                                tp->misc_host_ctrl);
2563
2564         switch (state) {
2565         case PCI_D0:
2566                 pci_enable_wake(tp->pdev, state, false);
2567                 pci_set_power_state(tp->pdev, PCI_D0);
2568
2569                 /* Switch out of Vaux if it is a NIC */
2570                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2571                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2572
2573                 return 0;
2574
2575         case PCI_D1:
2576         case PCI_D2:
2577         case PCI_D3hot:
2578                 break;
2579
2580         default:
2581                 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2582                            state);
2583                 return -EINVAL;
2584         }
2585
2586         /* Restore the CLKREQ setting. */
2587         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2588                 u16 lnkctl;
2589
2590                 pci_read_config_word(tp->pdev,
2591                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2592                                      &lnkctl);
2593                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2594                 pci_write_config_word(tp->pdev,
2595                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2596                                       lnkctl);
2597         }
2598
2599         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2600         tw32(TG3PCI_MISC_HOST_CTRL,
2601              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2602
2603         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2604                              device_may_wakeup(&tp->pdev->dev) &&
2605                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2606
2607         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2608                 do_low_power = false;
2609                 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2610                     !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2611                         struct phy_device *phydev;
2612                         u32 phyid, advertising;
2613
2614                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2615
2616                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2617
2618                         tp->link_config.orig_speed = phydev->speed;
2619                         tp->link_config.orig_duplex = phydev->duplex;
2620                         tp->link_config.orig_autoneg = phydev->autoneg;
2621                         tp->link_config.orig_advertising = phydev->advertising;
2622
2623                         advertising = ADVERTISED_TP |
2624                                       ADVERTISED_Pause |
2625                                       ADVERTISED_Autoneg |
2626                                       ADVERTISED_10baseT_Half;
2627
2628                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2629                             device_should_wake) {
2630                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2631                                         advertising |=
2632                                                 ADVERTISED_100baseT_Half |
2633                                                 ADVERTISED_100baseT_Full |
2634                                                 ADVERTISED_10baseT_Full;
2635                                 else
2636                                         advertising |= ADVERTISED_10baseT_Full;
2637                         }
2638
2639                         phydev->advertising = advertising;
2640
2641                         phy_start_aneg(phydev);
2642
2643                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2644                         if (phyid != PHY_ID_BCMAC131) {
2645                                 phyid &= PHY_BCM_OUI_MASK;
2646                                 if (phyid == PHY_BCM_OUI_1 ||
2647                                     phyid == PHY_BCM_OUI_2 ||
2648                                     phyid == PHY_BCM_OUI_3)
2649                                         do_low_power = true;
2650                         }
2651                 }
2652         } else {
2653                 do_low_power = true;
2654
2655                 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2656                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2657                         tp->link_config.orig_speed = tp->link_config.speed;
2658                         tp->link_config.orig_duplex = tp->link_config.duplex;
2659                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2660                 }
2661
2662                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2663                         tp->link_config.speed = SPEED_10;
2664                         tp->link_config.duplex = DUPLEX_HALF;
2665                         tp->link_config.autoneg = AUTONEG_ENABLE;
2666                         tg3_setup_phy(tp, 0);
2667                 }
2668         }
2669
2670         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2671                 u32 val;
2672
2673                 val = tr32(GRC_VCPU_EXT_CTRL);
2674                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2675         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2676                 int i;
2677                 u32 val;
2678
2679                 for (i = 0; i < 200; i++) {
2680                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2681                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2682                                 break;
2683                         msleep(1);
2684                 }
2685         }
2686         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2687                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2688                                                      WOL_DRV_STATE_SHUTDOWN |
2689                                                      WOL_DRV_WOL |
2690                                                      WOL_SET_MAGIC_PKT);
2691
2692         if (device_should_wake) {
2693                 u32 mac_mode;
2694
2695                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2696                         if (do_low_power) {
2697                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2698                                 udelay(40);
2699                         }
2700
2701                         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2702                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2703                         else
2704                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2705
2706                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2707                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2708                             ASIC_REV_5700) {
2709                                 u32 speed = (tp->tg3_flags &
2710                                              TG3_FLAG_WOL_SPEED_100MB) ?
2711                                              SPEED_100 : SPEED_10;
2712                                 if (tg3_5700_link_polarity(tp, speed))
2713                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2714                                 else
2715                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2716                         }
2717                 } else {
2718                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2719                 }
2720
2721                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2722                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2723
2724                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2725                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2726                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2727                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2728                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2729                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2730
2731                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2732                         mac_mode |= tp->mac_mode &
2733                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2734                         if (mac_mode & MAC_MODE_APE_TX_EN)
2735                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2736                 }
2737
2738                 tw32_f(MAC_MODE, mac_mode);
2739                 udelay(100);
2740
2741                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2742                 udelay(10);
2743         }
2744
2745         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2746             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2747              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2748                 u32 base_val;
2749
2750                 base_val = tp->pci_clock_ctrl;
2751                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2752                              CLOCK_CTRL_TXCLK_DISABLE);
2753
2754                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2755                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2756         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2757                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2758                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2759                 /* do nothing */
2760         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2761                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2762                 u32 newbits1, newbits2;
2763
2764                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2765                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2766                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2767                                     CLOCK_CTRL_TXCLK_DISABLE |
2768                                     CLOCK_CTRL_ALTCLK);
2769                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2770                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2771                         newbits1 = CLOCK_CTRL_625_CORE;
2772                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2773                 } else {
2774                         newbits1 = CLOCK_CTRL_ALTCLK;
2775                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2776                 }
2777
2778                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2779                             40);
2780
2781                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2782                             40);
2783
2784                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2785                         u32 newbits3;
2786
2787                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2788                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2789                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2790                                             CLOCK_CTRL_TXCLK_DISABLE |
2791                                             CLOCK_CTRL_44MHZ_CORE);
2792                         } else {
2793                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2794                         }
2795
2796                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2797                                     tp->pci_clock_ctrl | newbits3, 40);
2798                 }
2799         }
2800
2801         if (!(device_should_wake) &&
2802             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2803                 tg3_power_down_phy(tp, do_low_power);
2804
2805         tg3_frob_aux_power(tp);
2806
2807         /* Workaround for unstable PLL clock */
2808         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2809             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2810                 u32 val = tr32(0x7d00);
2811
2812                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2813                 tw32(0x7d00, val);
2814                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2815                         int err;
2816
2817                         err = tg3_nvram_lock(tp);
2818                         tg3_halt_cpu(tp, RX_CPU_BASE);
2819                         if (!err)
2820                                 tg3_nvram_unlock(tp);
2821                 }
2822         }
2823
2824         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2825
2826         if (device_should_wake)
2827                 pci_enable_wake(tp->pdev, state, true);
2828
2829         /* Finally, set the new power state. */
2830         pci_set_power_state(tp->pdev, state);
2831
2832         return 0;
2833 }
2834
2835 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2836 {
2837         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2838         case MII_TG3_AUX_STAT_10HALF:
2839                 *speed = SPEED_10;
2840                 *duplex = DUPLEX_HALF;
2841                 break;
2842
2843         case MII_TG3_AUX_STAT_10FULL:
2844                 *speed = SPEED_10;
2845                 *duplex = DUPLEX_FULL;
2846                 break;
2847
2848         case MII_TG3_AUX_STAT_100HALF:
2849                 *speed = SPEED_100;
2850                 *duplex = DUPLEX_HALF;
2851                 break;
2852
2853         case MII_TG3_AUX_STAT_100FULL:
2854                 *speed = SPEED_100;
2855                 *duplex = DUPLEX_FULL;
2856                 break;
2857
2858         case MII_TG3_AUX_STAT_1000HALF:
2859                 *speed = SPEED_1000;
2860                 *duplex = DUPLEX_HALF;
2861                 break;
2862
2863         case MII_TG3_AUX_STAT_1000FULL:
2864                 *speed = SPEED_1000;
2865                 *duplex = DUPLEX_FULL;
2866                 break;
2867
2868         default:
2869                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2870                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2871                                  SPEED_10;
2872                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2873                                   DUPLEX_HALF;
2874                         break;
2875                 }
2876                 *speed = SPEED_INVALID;
2877                 *duplex = DUPLEX_INVALID;
2878                 break;
2879         }
2880 }
2881
2882 static void tg3_phy_copper_begin(struct tg3 *tp)
2883 {
2884         u32 new_adv;
2885         int i;
2886
2887         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2888                 /* Entering low power mode.  Disable gigabit and
2889                  * 100baseT advertisements.
2890                  */
2891                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2892
2893                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2894                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2895                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2896                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2897
2898                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2899         } else if (tp->link_config.speed == SPEED_INVALID) {
2900                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2901                         tp->link_config.advertising &=
2902                                 ~(ADVERTISED_1000baseT_Half |
2903                                   ADVERTISED_1000baseT_Full);
2904
2905                 new_adv = ADVERTISE_CSMA;
2906                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2907                         new_adv |= ADVERTISE_10HALF;
2908                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2909                         new_adv |= ADVERTISE_10FULL;
2910                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2911                         new_adv |= ADVERTISE_100HALF;
2912                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2913                         new_adv |= ADVERTISE_100FULL;
2914
2915                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2916
2917                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2918
2919                 if (tp->link_config.advertising &
2920                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2921                         new_adv = 0;
2922                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2923                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2924                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2925                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2926                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
2927                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2928                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2929                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2930                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2931                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2932                 } else {
2933                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2934                 }
2935         } else {
2936                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2937                 new_adv |= ADVERTISE_CSMA;
2938
2939                 /* Asking for a specific link mode. */
2940                 if (tp->link_config.speed == SPEED_1000) {
2941                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2942
2943                         if (tp->link_config.duplex == DUPLEX_FULL)
2944                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2945                         else
2946                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2947                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2948                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2949                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2950                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2951                 } else {
2952                         if (tp->link_config.speed == SPEED_100) {
2953                                 if (tp->link_config.duplex == DUPLEX_FULL)
2954                                         new_adv |= ADVERTISE_100FULL;
2955                                 else
2956                                         new_adv |= ADVERTISE_100HALF;
2957                         } else {
2958                                 if (tp->link_config.duplex == DUPLEX_FULL)
2959                                         new_adv |= ADVERTISE_10FULL;
2960                                 else
2961                                         new_adv |= ADVERTISE_10HALF;
2962                         }
2963                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2964
2965                         new_adv = 0;
2966                 }
2967
2968                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2969         }
2970
2971         if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
2972                 u32 val = 0;
2973
2974                 tw32(TG3_CPMU_EEE_MODE,
2975                      tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2976
2977                 /* Enable SM_DSP clock and tx 6dB coding. */
2978                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
2979                       MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
2980                       MII_TG3_AUXCTL_ACTL_TX_6DB;
2981                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2982
2983                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2984                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
2985                     !tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
2986                         tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2,
2987                                          val | MII_TG3_DSP_CH34TP2_HIBW01);
2988
2989                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2990                         /* Advertise 100-BaseTX EEE ability */
2991                         if (tp->link_config.advertising &
2992                             (ADVERTISED_100baseT_Half |
2993                              ADVERTISED_100baseT_Full))
2994                                 val |= TG3_CL45_D7_EEEADV_CAP_100TX;
2995                         /* Advertise 1000-BaseT EEE ability */
2996                         if (tp->link_config.advertising &
2997                             (ADVERTISED_1000baseT_Half |
2998                              ADVERTISED_1000baseT_Full))
2999                                 val |= TG3_CL45_D7_EEEADV_CAP_1000T;
3000                 }
3001                 tg3_phy_cl45_write(tp, 0x7, TG3_CL45_D7_EEEADV_CAP, val);
3002
3003                 /* Turn off SM_DSP clock. */
3004                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
3005                       MII_TG3_AUXCTL_ACTL_TX_6DB;
3006                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3007         }
3008
3009         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
3010             tp->link_config.speed != SPEED_INVALID) {
3011                 u32 bmcr, orig_bmcr;
3012
3013                 tp->link_config.active_speed = tp->link_config.speed;
3014                 tp->link_config.active_duplex = tp->link_config.duplex;
3015
3016                 bmcr = 0;
3017                 switch (tp->link_config.speed) {
3018                 default:
3019                 case SPEED_10:
3020                         break;
3021
3022                 case SPEED_100:
3023                         bmcr |= BMCR_SPEED100;
3024                         break;
3025
3026                 case SPEED_1000:
3027                         bmcr |= TG3_BMCR_SPEED1000;
3028                         break;
3029                 }
3030
3031                 if (tp->link_config.duplex == DUPLEX_FULL)
3032                         bmcr |= BMCR_FULLDPLX;
3033
3034                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
3035                     (bmcr != orig_bmcr)) {
3036                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
3037                         for (i = 0; i < 1500; i++) {
3038                                 u32 tmp;
3039
3040                                 udelay(10);
3041                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
3042                                     tg3_readphy(tp, MII_BMSR, &tmp))
3043                                         continue;
3044                                 if (!(tmp & BMSR_LSTATUS)) {
3045                                         udelay(40);
3046                                         break;
3047                                 }
3048                         }
3049                         tg3_writephy(tp, MII_BMCR, bmcr);
3050                         udelay(40);
3051                 }
3052         } else {
3053                 tg3_writephy(tp, MII_BMCR,
3054                              BMCR_ANENABLE | BMCR_ANRESTART);
3055         }
3056 }
3057
3058 static int tg3_init_5401phy_dsp(struct tg3 *tp)
3059 {
3060         int err;
3061
3062         /* Turn off tap power management. */
3063         /* Set Extended packet length bit */
3064         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
3065
3066         err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
3067         err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
3068         err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
3069         err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
3070         err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
3071
3072         udelay(40);
3073
3074         return err;
3075 }
3076
3077 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3078 {
3079         u32 adv_reg, all_mask = 0;
3080
3081         if (mask & ADVERTISED_10baseT_Half)
3082                 all_mask |= ADVERTISE_10HALF;
3083         if (mask & ADVERTISED_10baseT_Full)
3084                 all_mask |= ADVERTISE_10FULL;
3085         if (mask & ADVERTISED_100baseT_Half)
3086                 all_mask |= ADVERTISE_100HALF;
3087         if (mask & ADVERTISED_100baseT_Full)
3088                 all_mask |= ADVERTISE_100FULL;
3089
3090         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3091                 return 0;
3092
3093         if ((adv_reg & all_mask) != all_mask)
3094                 return 0;
3095         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3096                 u32 tg3_ctrl;
3097
3098                 all_mask = 0;
3099                 if (mask & ADVERTISED_1000baseT_Half)
3100                         all_mask |= ADVERTISE_1000HALF;
3101                 if (mask & ADVERTISED_1000baseT_Full)
3102                         all_mask |= ADVERTISE_1000FULL;
3103
3104                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3105                         return 0;
3106
3107                 if ((tg3_ctrl & all_mask) != all_mask)
3108                         return 0;
3109         }
3110         return 1;
3111 }
3112
3113 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3114 {
3115         u32 curadv, reqadv;
3116
3117         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3118                 return 1;
3119
3120         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3121         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3122
3123         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3124                 if (curadv != reqadv)
3125                         return 0;
3126
3127                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3128                         tg3_readphy(tp, MII_LPA, rmtadv);
3129         } else {
3130                 /* Reprogram the advertisement register, even if it
3131                  * does not affect the current link.  If the link
3132                  * gets renegotiated in the future, we can save an
3133                  * additional renegotiation cycle by advertising
3134                  * it correctly in the first place.
3135                  */
3136                 if (curadv != reqadv) {
3137                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3138                                      ADVERTISE_PAUSE_ASYM);
3139                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3140                 }
3141         }
3142
3143         return 1;
3144 }
3145
3146 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3147 {
3148         int current_link_up;
3149         u32 bmsr, val;
3150         u32 lcl_adv, rmt_adv;
3151         u16 current_speed;
3152         u8 current_duplex;
3153         int i, err;
3154
3155         tw32(MAC_EVENT, 0);
3156
3157         tw32_f(MAC_STATUS,
3158              (MAC_STATUS_SYNC_CHANGED |
3159               MAC_STATUS_CFG_CHANGED |
3160               MAC_STATUS_MI_COMPLETION |
3161               MAC_STATUS_LNKSTATE_CHANGED));
3162         udelay(40);
3163
3164         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3165                 tw32_f(MAC_MI_MODE,
3166                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3167                 udelay(80);
3168         }
3169
3170         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3171
3172         /* Some third-party PHYs need to be reset on link going
3173          * down.
3174          */
3175         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3176              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3177              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3178             netif_carrier_ok(tp->dev)) {
3179                 tg3_readphy(tp, MII_BMSR, &bmsr);
3180                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3181                     !(bmsr & BMSR_LSTATUS))
3182                         force_reset = 1;
3183         }
3184         if (force_reset)
3185                 tg3_phy_reset(tp);
3186
3187         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3188                 tg3_readphy(tp, MII_BMSR, &bmsr);
3189                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3190                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3191                         bmsr = 0;
3192
3193                 if (!(bmsr & BMSR_LSTATUS)) {
3194                         err = tg3_init_5401phy_dsp(tp);
3195                         if (err)
3196                                 return err;
3197
3198                         tg3_readphy(tp, MII_BMSR, &bmsr);
3199                         for (i = 0; i < 1000; i++) {
3200                                 udelay(10);
3201                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3202                                     (bmsr & BMSR_LSTATUS)) {
3203                                         udelay(40);
3204                                         break;
3205                                 }
3206                         }
3207
3208                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3209                             TG3_PHY_REV_BCM5401_B0 &&
3210                             !(bmsr & BMSR_LSTATUS) &&
3211                             tp->link_config.active_speed == SPEED_1000) {
3212                                 err = tg3_phy_reset(tp);
3213                                 if (!err)
3214                                         err = tg3_init_5401phy_dsp(tp);
3215                                 if (err)
3216                                         return err;
3217                         }
3218                 }
3219         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3220                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3221                 /* 5701 {A0,B0} CRC bug workaround */
3222                 tg3_writephy(tp, 0x15, 0x0a75);
3223                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3224                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3225                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3226         }
3227
3228         /* Clear pending interrupts... */
3229         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3230         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3231
3232         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3233                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3234         else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3235                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3236
3237         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3238             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3239                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3240                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3241                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3242                 else
3243                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3244         }
3245
3246         current_link_up = 0;
3247         current_speed = SPEED_INVALID;
3248         current_duplex = DUPLEX_INVALID;
3249
3250         if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3251                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3252                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3253                 if (!(val & (1 << 10))) {
3254                         val |= (1 << 10);
3255                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3256                         goto relink;
3257                 }
3258         }
3259
3260         bmsr = 0;
3261         for (i = 0; i < 100; i++) {
3262                 tg3_readphy(tp, MII_BMSR, &bmsr);
3263                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3264                     (bmsr & BMSR_LSTATUS))
3265                         break;
3266                 udelay(40);
3267         }
3268
3269         if (bmsr & BMSR_LSTATUS) {
3270                 u32 aux_stat, bmcr;
3271
3272                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3273                 for (i = 0; i < 2000; i++) {
3274                         udelay(10);
3275                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3276                             aux_stat)
3277                                 break;
3278                 }
3279
3280                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3281                                              &current_speed,
3282                                              &current_duplex);
3283
3284                 bmcr = 0;
3285                 for (i = 0; i < 200; i++) {
3286                         tg3_readphy(tp, MII_BMCR, &bmcr);
3287                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3288                                 continue;
3289                         if (bmcr && bmcr != 0x7fff)
3290                                 break;
3291                         udelay(10);
3292                 }
3293
3294                 lcl_adv = 0;
3295                 rmt_adv = 0;
3296
3297                 tp->link_config.active_speed = current_speed;
3298                 tp->link_config.active_duplex = current_duplex;
3299
3300                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3301                         if ((bmcr & BMCR_ANENABLE) &&
3302                             tg3_copper_is_advertising_all(tp,
3303                                                 tp->link_config.advertising)) {
3304                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3305                                                                   &rmt_adv))
3306                                         current_link_up = 1;
3307                         }
3308                 } else {
3309                         if (!(bmcr & BMCR_ANENABLE) &&
3310                             tp->link_config.speed == current_speed &&
3311                             tp->link_config.duplex == current_duplex &&
3312                             tp->link_config.flowctrl ==
3313                             tp->link_config.active_flowctrl) {
3314                                 current_link_up = 1;
3315                         }
3316                 }
3317
3318                 if (current_link_up == 1 &&
3319                     tp->link_config.active_duplex == DUPLEX_FULL)
3320                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3321         }
3322
3323 relink:
3324         if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3325                 tg3_phy_copper_begin(tp);
3326
3327                 tg3_readphy(tp, MII_BMSR, &bmsr);
3328                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3329                     (bmsr & BMSR_LSTATUS))
3330                         current_link_up = 1;
3331         }
3332
3333         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3334         if (current_link_up == 1) {
3335                 if (tp->link_config.active_speed == SPEED_100 ||
3336                     tp->link_config.active_speed == SPEED_10)
3337                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3338                 else
3339                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3340         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3341                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3342         else
3343                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3344
3345         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3346         if (tp->link_config.active_duplex == DUPLEX_HALF)
3347                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3348
3349         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3350                 if (current_link_up == 1 &&
3351                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3352                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3353                 else
3354                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3355         }
3356
3357         /* ??? Without this setting Netgear GA302T PHY does not
3358          * ??? send/receive packets...
3359          */
3360         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3361             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3362                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3363                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3364                 udelay(80);
3365         }
3366
3367         tw32_f(MAC_MODE, tp->mac_mode);
3368         udelay(40);
3369
3370         tg3_phy_eee_adjust(tp, current_link_up);
3371
3372         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3373                 /* Polled via timer. */
3374                 tw32_f(MAC_EVENT, 0);
3375         } else {
3376                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3377         }
3378         udelay(40);
3379
3380         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3381             current_link_up == 1 &&
3382             tp->link_config.active_speed == SPEED_1000 &&
3383             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3384              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3385                 udelay(120);
3386                 tw32_f(MAC_STATUS,
3387                      (MAC_STATUS_SYNC_CHANGED |
3388                       MAC_STATUS_CFG_CHANGED));
3389                 udelay(40);
3390                 tg3_write_mem(tp,
3391                               NIC_SRAM_FIRMWARE_MBOX,
3392                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3393         }
3394
3395         /* Prevent send BD corruption. */
3396         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3397                 u16 oldlnkctl, newlnkctl;
3398
3399                 pci_read_config_word(tp->pdev,
3400                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3401                                      &oldlnkctl);
3402                 if (tp->link_config.active_speed == SPEED_100 ||
3403                     tp->link_config.active_speed == SPEED_10)
3404                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3405                 else
3406                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3407                 if (newlnkctl != oldlnkctl)
3408                         pci_write_config_word(tp->pdev,
3409                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3410                                               newlnkctl);
3411         }
3412
3413         if (current_link_up != netif_carrier_ok(tp->dev)) {
3414                 if (current_link_up)
3415                         netif_carrier_on(tp->dev);
3416                 else
3417                         netif_carrier_off(tp->dev);
3418                 tg3_link_report(tp);
3419         }
3420
3421         return 0;
3422 }
3423
3424 struct tg3_fiber_aneginfo {
3425         int state;
3426 #define ANEG_STATE_UNKNOWN              0
3427 #define ANEG_STATE_AN_ENABLE            1
3428 #define ANEG_STATE_RESTART_INIT         2
3429 #define ANEG_STATE_RESTART              3
3430 #define ANEG_STATE_DISABLE_LINK_OK      4
3431 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3432 #define ANEG_STATE_ABILITY_DETECT       6
3433 #define ANEG_STATE_ACK_DETECT_INIT      7
3434 #define ANEG_STATE_ACK_DETECT           8
3435 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3436 #define ANEG_STATE_COMPLETE_ACK         10
3437 #define ANEG_STATE_IDLE_DETECT_INIT     11
3438 #define ANEG_STATE_IDLE_DETECT          12
3439 #define ANEG_STATE_LINK_OK              13
3440 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3441 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3442
3443         u32 flags;
3444 #define MR_AN_ENABLE            0x00000001
3445 #define MR_RESTART_AN           0x00000002
3446 #define MR_AN_COMPLETE          0x00000004
3447 #define MR_PAGE_RX              0x00000008
3448 #define MR_NP_LOADED            0x00000010
3449 #define MR_TOGGLE_TX            0x00000020
3450 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3451 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3452 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3453 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3454 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3455 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3456 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3457 #define MR_TOGGLE_RX            0x00002000
3458 #define MR_NP_RX                0x00004000
3459
3460 #define MR_LINK_OK              0x80000000
3461
3462         unsigned long link_time, cur_time;
3463
3464         u32 ability_match_cfg;
3465         int ability_match_count;
3466
3467         char ability_match, idle_match, ack_match;
3468
3469         u32 txconfig, rxconfig;
3470 #define ANEG_CFG_NP             0x00000080
3471 #define ANEG_CFG_ACK            0x00000040
3472 #define ANEG_CFG_RF2            0x00000020
3473 #define ANEG_CFG_RF1            0x00000010
3474 #define ANEG_CFG_PS2            0x00000001
3475 #define ANEG_CFG_PS1            0x00008000
3476 #define ANEG_CFG_HD             0x00004000
3477 #define ANEG_CFG_FD             0x00002000
3478 #define ANEG_CFG_INVAL          0x00001f06
3479
3480 };
3481 #define ANEG_OK         0
3482 #define ANEG_DONE       1
3483 #define ANEG_TIMER_ENAB 2
3484 #define ANEG_FAILED     -1
3485
3486 #define ANEG_STATE_SETTLE_TIME  10000
3487
3488 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3489                                    struct tg3_fiber_aneginfo *ap)
3490 {
3491         u16 flowctrl;
3492         unsigned long delta;
3493         u32 rx_cfg_reg;
3494         int ret;
3495
3496         if (ap->state == ANEG_STATE_UNKNOWN) {
3497                 ap->rxconfig = 0;
3498                 ap->link_time = 0;
3499                 ap->cur_time = 0;
3500                 ap->ability_match_cfg = 0;
3501                 ap->ability_match_count = 0;
3502                 ap->ability_match = 0;
3503                 ap->idle_match = 0;
3504                 ap->ack_match = 0;
3505         }
3506         ap->cur_time++;
3507
3508         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3509                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3510
3511                 if (rx_cfg_reg != ap->ability_match_cfg) {
3512                         ap->ability_match_cfg = rx_cfg_reg;
3513                         ap->ability_match = 0;
3514                         ap->ability_match_count = 0;
3515                 } else {
3516                         if (++ap->ability_match_count > 1) {
3517                                 ap->ability_match = 1;
3518                                 ap->ability_match_cfg = rx_cfg_reg;
3519                         }
3520                 }
3521                 if (rx_cfg_reg & ANEG_CFG_ACK)
3522                         ap->ack_match = 1;
3523                 else
3524                         ap->ack_match = 0;
3525
3526                 ap->idle_match = 0;
3527         } else {
3528                 ap->idle_match = 1;
3529                 ap->ability_match_cfg = 0;
3530                 ap->ability_match_count = 0;
3531                 ap->ability_match = 0;
3532                 ap->ack_match = 0;
3533
3534                 rx_cfg_reg = 0;
3535         }
3536
3537         ap->rxconfig = rx_cfg_reg;
3538         ret = ANEG_OK;
3539
3540         switch (ap->state) {
3541         case ANEG_STATE_UNKNOWN:
3542                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3543                         ap->state = ANEG_STATE_AN_ENABLE;
3544
3545                 /* fallthru */
3546         case ANEG_STATE_AN_ENABLE:
3547                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3548                 if (ap->flags & MR_AN_ENABLE) {
3549                         ap->link_time = 0;
3550                         ap->cur_time = 0;
3551                         ap->ability_match_cfg = 0;
3552                         ap->ability_match_count = 0;
3553                         ap->ability_match = 0;
3554                         ap->idle_match = 0;
3555                         ap->ack_match = 0;
3556
3557                         ap->state = ANEG_STATE_RESTART_INIT;
3558                 } else {
3559                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3560                 }
3561                 break;
3562
3563         case ANEG_STATE_RESTART_INIT:
3564                 ap->link_time = ap->cur_time;
3565                 ap->flags &= ~(MR_NP_LOADED);
3566                 ap->txconfig = 0;
3567                 tw32(MAC_TX_AUTO_NEG, 0);
3568                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3569                 tw32_f(MAC_MODE, tp->mac_mode);
3570                 udelay(40);
3571
3572                 ret = ANEG_TIMER_ENAB;
3573                 ap->state = ANEG_STATE_RESTART;
3574
3575                 /* fallthru */
3576         case ANEG_STATE_RESTART:
3577                 delta = ap->cur_time - ap->link_time;
3578                 if (delta > ANEG_STATE_SETTLE_TIME)
3579                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3580                 else
3581                         ret = ANEG_TIMER_ENAB;
3582                 break;
3583
3584         case ANEG_STATE_DISABLE_LINK_OK:
3585                 ret = ANEG_DONE;
3586                 break;
3587
3588         case ANEG_STATE_ABILITY_DETECT_INIT:
3589                 ap->flags &= ~(MR_TOGGLE_TX);
3590                 ap->txconfig = ANEG_CFG_FD;
3591                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3592                 if (flowctrl & ADVERTISE_1000XPAUSE)
3593                         ap->txconfig |= ANEG_CFG_PS1;
3594                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3595                         ap->txconfig |= ANEG_CFG_PS2;
3596                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3597                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3598                 tw32_f(MAC_MODE, tp->mac_mode);
3599                 udelay(40);
3600
3601                 ap->state = ANEG_STATE_ABILITY_DETECT;
3602                 break;
3603
3604         case ANEG_STATE_ABILITY_DETECT:
3605                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3606                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3607                 break;
3608
3609         case ANEG_STATE_ACK_DETECT_INIT:
3610                 ap->txconfig |= ANEG_CFG_ACK;
3611                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3612                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3613                 tw32_f(MAC_MODE, tp->mac_mode);
3614                 udelay(40);
3615
3616                 ap->state = ANEG_STATE_ACK_DETECT;
3617
3618                 /* fallthru */
3619         case ANEG_STATE_ACK_DETECT:
3620                 if (ap->ack_match != 0) {
3621                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3622                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3623                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3624                         } else {
3625                                 ap->state = ANEG_STATE_AN_ENABLE;
3626                         }
3627                 } else if (ap->ability_match != 0 &&
3628                            ap->rxconfig == 0) {
3629                         ap->state = ANEG_STATE_AN_ENABLE;
3630                 }
3631                 break;
3632
3633         case ANEG_STATE_COMPLETE_ACK_INIT:
3634                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3635                         ret = ANEG_FAILED;
3636                         break;
3637                 }
3638                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3639                                MR_LP_ADV_HALF_DUPLEX |
3640                                MR_LP_ADV_SYM_PAUSE |
3641                                MR_LP_ADV_ASYM_PAUSE |
3642                                MR_LP_ADV_REMOTE_FAULT1 |
3643                                MR_LP_ADV_REMOTE_FAULT2 |
3644                                MR_LP_ADV_NEXT_PAGE |
3645                                MR_TOGGLE_RX |
3646                                MR_NP_RX);
3647                 if (ap->rxconfig & ANEG_CFG_FD)
3648                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3649                 if (ap->rxconfig & ANEG_CFG_HD)
3650                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3651                 if (ap->rxconfig & ANEG_CFG_PS1)
3652                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3653                 if (ap->rxconfig & ANEG_CFG_PS2)
3654                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3655                 if (ap->rxconfig & ANEG_CFG_RF1)
3656                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3657                 if (ap->rxconfig & ANEG_CFG_RF2)
3658                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3659                 if (ap->rxconfig & ANEG_CFG_NP)
3660                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3661
3662                 ap->link_time = ap->cur_time;
3663
3664                 ap->flags ^= (MR_TOGGLE_TX);
3665                 if (ap->rxconfig & 0x0008)
3666                         ap->flags |= MR_TOGGLE_RX;
3667                 if (ap->rxconfig & ANEG_CFG_NP)
3668                         ap->flags |= MR_NP_RX;
3669                 ap->flags |= MR_PAGE_RX;
3670
3671                 ap->state = ANEG_STATE_COMPLETE_ACK;
3672                 ret = ANEG_TIMER_ENAB;
3673                 break;
3674
3675         case ANEG_STATE_COMPLETE_ACK:
3676                 if (ap->ability_match != 0 &&
3677                     ap->rxconfig == 0) {
3678                         ap->state = ANEG_STATE_AN_ENABLE;
3679                         break;
3680                 }
3681                 delta = ap->cur_time - ap->link_time;
3682                 if (delta > ANEG_STATE_SETTLE_TIME) {
3683                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3684                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3685                         } else {
3686                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3687                                     !(ap->flags & MR_NP_RX)) {
3688                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3689                                 } else {
3690                                         ret = ANEG_FAILED;
3691                                 }
3692                         }
3693                 }
3694                 break;
3695
3696         case ANEG_STATE_IDLE_DETECT_INIT:
3697                 ap->link_time = ap->cur_time;
3698                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3699                 tw32_f(MAC_MODE, tp->mac_mode);
3700                 udelay(40);
3701
3702                 ap->state = ANEG_STATE_IDLE_DETECT;
3703                 ret = ANEG_TIMER_ENAB;
3704                 break;
3705
3706         case ANEG_STATE_IDLE_DETECT:
3707                 if (ap->ability_match != 0 &&
3708                     ap->rxconfig == 0) {
3709                         ap->state = ANEG_STATE_AN_ENABLE;
3710                         break;
3711                 }
3712                 delta = ap->cur_time - ap->link_time;
3713                 if (delta > ANEG_STATE_SETTLE_TIME) {
3714                         /* XXX another gem from the Broadcom driver :( */
3715                         ap->state = ANEG_STATE_LINK_OK;
3716                 }
3717                 break;
3718
3719         case ANEG_STATE_LINK_OK:
3720                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3721                 ret = ANEG_DONE;
3722                 break;
3723
3724         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3725                 /* ??? unimplemented */
3726                 break;
3727
3728         case ANEG_STATE_NEXT_PAGE_WAIT:
3729                 /* ??? unimplemented */
3730                 break;
3731
3732         default:
3733                 ret = ANEG_FAILED;
3734                 break;
3735         }
3736
3737         return ret;
3738 }
3739
3740 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3741 {
3742         int res = 0;
3743         struct tg3_fiber_aneginfo aninfo;
3744         int status = ANEG_FAILED;
3745         unsigned int tick;
3746         u32 tmp;
3747
3748         tw32_f(MAC_TX_AUTO_NEG, 0);
3749
3750         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3751         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3752         udelay(40);
3753
3754         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3755         udelay(40);
3756
3757         memset(&aninfo, 0, sizeof(aninfo));
3758         aninfo.flags |= MR_AN_ENABLE;
3759         aninfo.state = ANEG_STATE_UNKNOWN;
3760         aninfo.cur_time = 0;
3761         tick = 0;
3762         while (++tick < 195000) {
3763                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3764                 if (status == ANEG_DONE || status == ANEG_FAILED)
3765                         break;
3766
3767                 udelay(1);
3768         }
3769
3770         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3771         tw32_f(MAC_MODE, tp->mac_mode);
3772         udelay(40);
3773
3774         *txflags = aninfo.txconfig;
3775         *rxflags = aninfo.flags;
3776
3777         if (status == ANEG_DONE &&
3778             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3779                              MR_LP_ADV_FULL_DUPLEX)))
3780                 res = 1;
3781
3782         return res;
3783 }
3784
3785 static void tg3_init_bcm8002(struct tg3 *tp)
3786 {
3787         u32 mac_status = tr32(MAC_STATUS);
3788         int i;
3789
3790         /* Reset when initting first time or we have a link. */
3791         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3792             !(mac_status & MAC_STATUS_PCS_SYNCED))
3793                 return;
3794
3795         /* Set PLL lock range. */
3796         tg3_writephy(tp, 0x16, 0x8007);
3797
3798         /* SW reset */
3799         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3800
3801         /* Wait for reset to complete. */
3802         /* XXX schedule_timeout() ... */
3803         for (i = 0; i < 500; i++)
3804                 udelay(10);
3805
3806         /* Config mode; select PMA/Ch 1 regs. */
3807         tg3_writephy(tp, 0x10, 0x8411);
3808
3809         /* Enable auto-lock and comdet, select txclk for tx. */
3810         tg3_writephy(tp, 0x11, 0x0a10);
3811
3812         tg3_writephy(tp, 0x18, 0x00a0);
3813         tg3_writephy(tp, 0x16, 0x41ff);
3814
3815         /* Assert and deassert POR. */
3816         tg3_writephy(tp, 0x13, 0x0400);
3817         udelay(40);
3818         tg3_writephy(tp, 0x13, 0x0000);
3819
3820         tg3_writephy(tp, 0x11, 0x0a50);
3821         udelay(40);
3822         tg3_writephy(tp, 0x11, 0x0a10);
3823
3824         /* Wait for signal to stabilize */
3825         /* XXX schedule_timeout() ... */
3826         for (i = 0; i < 15000; i++)
3827                 udelay(10);
3828
3829         /* Deselect the channel register so we can read the PHYID
3830          * later.
3831          */
3832         tg3_writephy(tp, 0x10, 0x8011);
3833 }
3834
3835 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3836 {
3837         u16 flowctrl;
3838         u32 sg_dig_ctrl, sg_dig_status;
3839         u32 serdes_cfg, expected_sg_dig_ctrl;
3840         int workaround, port_a;
3841         int current_link_up;
3842
3843         serdes_cfg = 0;
3844         expected_sg_dig_ctrl = 0;
3845         workaround = 0;
3846         port_a = 1;
3847         current_link_up = 0;
3848
3849         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3850             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3851                 workaround = 1;
3852                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3853                         port_a = 0;
3854
3855                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3856                 /* preserve bits 20-23 for voltage regulator */
3857                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3858         }
3859
3860         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3861
3862         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3863                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3864                         if (workaround) {
3865                                 u32 val = serdes_cfg;
3866
3867                                 if (port_a)
3868                                         val |= 0xc010000;
3869                                 else
3870                                         val |= 0x4010000;
3871                                 tw32_f(MAC_SERDES_CFG, val);
3872                         }
3873
3874                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3875                 }
3876                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3877                         tg3_setup_flow_control(tp, 0, 0);
3878                         current_link_up = 1;
3879                 }
3880                 goto out;
3881         }
3882
3883         /* Want auto-negotiation.  */
3884         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3885
3886         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3887         if (flowctrl & ADVERTISE_1000XPAUSE)
3888                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3889         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3890                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3891
3892         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3893                 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3894                     tp->serdes_counter &&
3895                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3896                                     MAC_STATUS_RCVD_CFG)) ==
3897                      MAC_STATUS_PCS_SYNCED)) {
3898                         tp->serdes_counter--;
3899                         current_link_up = 1;
3900                         goto out;
3901                 }
3902 restart_autoneg:
3903                 if (workaround)
3904                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3905                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3906                 udelay(5);
3907                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3908
3909                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3910                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3911         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3912                                  MAC_STATUS_SIGNAL_DET)) {
3913                 sg_dig_status = tr32(SG_DIG_STATUS);
3914                 mac_status = tr32(MAC_STATUS);
3915
3916                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3917                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3918                         u32 local_adv = 0, remote_adv = 0;
3919
3920                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3921                                 local_adv |= ADVERTISE_1000XPAUSE;
3922                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3923                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3924
3925                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3926                                 remote_adv |= LPA_1000XPAUSE;
3927                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3928                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3929
3930                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3931                         current_link_up = 1;
3932                         tp->serdes_counter = 0;
3933                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3934                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3935                         if (tp->serdes_counter)
3936                                 tp->serdes_counter--;
3937                         else {
3938                                 if (workaround) {
3939                                         u32 val = serdes_cfg;
3940
3941                                         if (port_a)
3942                                                 val |= 0xc010000;
3943                                         else
3944                                                 val |= 0x4010000;
3945
3946                                         tw32_f(MAC_SERDES_CFG, val);
3947                                 }
3948
3949                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3950                                 udelay(40);
3951
3952                                 /* Link parallel detection - link is up */
3953                                 /* only if we have PCS_SYNC and not */
3954                                 /* receiving config code words */
3955                                 mac_status = tr32(MAC_STATUS);
3956                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3957                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3958                                         tg3_setup_flow_control(tp, 0, 0);
3959                                         current_link_up = 1;
3960                                         tp->phy_flags |=
3961                                                 TG3_PHYFLG_PARALLEL_DETECT;
3962                                         tp->serdes_counter =
3963                                                 SERDES_PARALLEL_DET_TIMEOUT;
3964                                 } else
3965                                         goto restart_autoneg;
3966                         }
3967                 }
3968         } else {
3969                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3970                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3971         }
3972
3973 out:
3974         return current_link_up;
3975 }
3976
3977 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3978 {
3979         int current_link_up = 0;
3980
3981         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3982                 goto out;
3983
3984         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3985                 u32 txflags, rxflags;
3986                 int i;
3987
3988                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3989                         u32 local_adv = 0, remote_adv = 0;
3990
3991                         if (txflags & ANEG_CFG_PS1)
3992                                 local_adv |= ADVERTISE_1000XPAUSE;
3993                         if (txflags & ANEG_CFG_PS2)
3994                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3995
3996                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3997                                 remote_adv |= LPA_1000XPAUSE;
3998                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3999                                 remote_adv |= LPA_1000XPAUSE_ASYM;
4000
4001                         tg3_setup_flow_control(tp, local_adv, remote_adv);
4002
4003                         current_link_up = 1;
4004                 }
4005                 for (i = 0; i < 30; i++) {
4006                         udelay(20);
4007                         tw32_f(MAC_STATUS,
4008                                (MAC_STATUS_SYNC_CHANGED |
4009                                 MAC_STATUS_CFG_CHANGED));
4010                         udelay(40);
4011                         if ((tr32(MAC_STATUS) &
4012                              (MAC_STATUS_SYNC_CHANGED |
4013                               MAC_STATUS_CFG_CHANGED)) == 0)
4014                                 break;
4015                 }
4016
4017                 mac_status = tr32(MAC_STATUS);
4018                 if (current_link_up == 0 &&
4019                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
4020                     !(mac_status & MAC_STATUS_RCVD_CFG))
4021                         current_link_up = 1;
4022         } else {
4023                 tg3_setup_flow_control(tp, 0, 0);
4024
4025                 /* Forcing 1000FD link up. */
4026                 current_link_up = 1;
4027
4028                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
4029                 udelay(40);
4030
4031                 tw32_f(MAC_MODE, tp->mac_mode);
4032                 udelay(40);
4033         }
4034
4035 out:
4036         return current_link_up;
4037 }
4038
4039 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4040 {
4041         u32 orig_pause_cfg;
4042         u16 orig_active_speed;
4043         u8 orig_active_duplex;
4044         u32 mac_status;
4045         int current_link_up;
4046         int i;
4047
4048         orig_pause_cfg = tp->link_config.active_flowctrl;
4049         orig_active_speed = tp->link_config.active_speed;
4050         orig_active_duplex = tp->link_config.active_duplex;
4051
4052         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
4053             netif_carrier_ok(tp->dev) &&
4054             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
4055                 mac_status = tr32(MAC_STATUS);
4056                 mac_status &= (MAC_STATUS_PCS_SYNCED |
4057                                MAC_STATUS_SIGNAL_DET |
4058                                MAC_STATUS_CFG_CHANGED |
4059                                MAC_STATUS_RCVD_CFG);
4060                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
4061                                    MAC_STATUS_SIGNAL_DET)) {
4062                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4063                                             MAC_STATUS_CFG_CHANGED));
4064                         return 0;
4065                 }
4066         }
4067
4068         tw32_f(MAC_TX_AUTO_NEG, 0);
4069
4070         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
4071         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
4072         tw32_f(MAC_MODE, tp->mac_mode);
4073         udelay(40);
4074
4075         if (tp->phy_id == TG3_PHY_ID_BCM8002)
4076                 tg3_init_bcm8002(tp);
4077
4078         /* Enable link change event even when serdes polling.  */
4079         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4080         udelay(40);
4081
4082         current_link_up = 0;
4083         mac_status = tr32(MAC_STATUS);
4084
4085         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
4086                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4087         else
4088                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4089
4090         tp->napi[0].hw_status->status =
4091                 (SD_STATUS_UPDATED |
4092                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4093
4094         for (i = 0; i < 100; i++) {
4095                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4096                                     MAC_STATUS_CFG_CHANGED));
4097                 udelay(5);
4098                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4099                                          MAC_STATUS_CFG_CHANGED |
4100                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4101                         break;
4102         }
4103
4104         mac_status = tr32(MAC_STATUS);
4105         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4106                 current_link_up = 0;
4107                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4108                     tp->serdes_counter == 0) {
4109                         tw32_f(MAC_MODE, (tp->mac_mode |
4110                                           MAC_MODE_SEND_CONFIGS));
4111                         udelay(1);
4112                         tw32_f(MAC_MODE, tp->mac_mode);
4113                 }
4114         }
4115
4116         if (current_link_up == 1) {
4117                 tp->link_config.active_speed = SPEED_1000;
4118                 tp->link_config.active_duplex = DUPLEX_FULL;
4119                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4120                                     LED_CTRL_LNKLED_OVERRIDE |
4121                                     LED_CTRL_1000MBPS_ON));
4122         } else {
4123                 tp->link_config.active_speed = SPEED_INVALID;
4124                 tp->link_config.active_duplex = DUPLEX_INVALID;
4125                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4126                                     LED_CTRL_LNKLED_OVERRIDE |
4127                                     LED_CTRL_TRAFFIC_OVERRIDE));
4128         }
4129
4130         if (current_link_up != netif_carrier_ok(tp->dev)) {
4131                 if (current_link_up)
4132                         netif_carrier_on(tp->dev);
4133                 else
4134                         netif_carrier_off(tp->dev);
4135                 tg3_link_report(tp);
4136         } else {
4137                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4138                 if (orig_pause_cfg != now_pause_cfg ||
4139                     orig_active_speed != tp->link_config.active_speed ||
4140                     orig_active_duplex != tp->link_config.active_duplex)
4141                         tg3_link_report(tp);
4142         }
4143
4144         return 0;
4145 }
4146
4147 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4148 {
4149         int current_link_up, err = 0;
4150         u32 bmsr, bmcr;
4151         u16 current_speed;
4152         u8 current_duplex;
4153         u32 local_adv, remote_adv;
4154
4155         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4156         tw32_f(MAC_MODE, tp->mac_mode);
4157         udelay(40);
4158
4159         tw32(MAC_EVENT, 0);
4160
4161         tw32_f(MAC_STATUS,
4162              (MAC_STATUS_SYNC_CHANGED |
4163               MAC_STATUS_CFG_CHANGED |
4164               MAC_STATUS_MI_COMPLETION |
4165               MAC_STATUS_LNKSTATE_CHANGED));
4166         udelay(40);
4167
4168         if (force_reset)
4169                 tg3_phy_reset(tp);
4170
4171         current_link_up = 0;
4172         current_speed = SPEED_INVALID;
4173         current_duplex = DUPLEX_INVALID;
4174
4175         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4176         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4177         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4178                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4179                         bmsr |= BMSR_LSTATUS;
4180                 else
4181                         bmsr &= ~BMSR_LSTATUS;
4182         }
4183
4184         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4185
4186         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4187             (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4188                 /* do nothing, just check for link up at the end */
4189         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4190                 u32 adv, new_adv;
4191
4192                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4193                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4194                                   ADVERTISE_1000XPAUSE |
4195                                   ADVERTISE_1000XPSE_ASYM |
4196                                   ADVERTISE_SLCT);
4197
4198                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4199
4200                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4201                         new_adv |= ADVERTISE_1000XHALF;
4202                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4203                         new_adv |= ADVERTISE_1000XFULL;
4204
4205                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4206                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4207                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4208                         tg3_writephy(tp, MII_BMCR, bmcr);
4209
4210                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4211                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4212                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4213
4214                         return err;
4215                 }
4216         } else {
4217                 u32 new_bmcr;
4218
4219                 bmcr &= ~BMCR_SPEED1000;
4220                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4221
4222                 if (tp->link_config.duplex == DUPLEX_FULL)
4223                         new_bmcr |= BMCR_FULLDPLX;
4224
4225                 if (new_bmcr != bmcr) {
4226                         /* BMCR_SPEED1000 is a reserved bit that needs
4227                          * to be set on write.
4228                          */
4229                         new_bmcr |= BMCR_SPEED1000;
4230
4231                         /* Force a linkdown */
4232                         if (netif_carrier_ok(tp->dev)) {
4233                                 u32 adv;
4234
4235                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4236                                 adv &= ~(ADVERTISE_1000XFULL |
4237                                          ADVERTISE_1000XHALF |
4238                                          ADVERTISE_SLCT);
4239                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4240                                 tg3_writephy(tp, MII_BMCR, bmcr |
4241                                                            BMCR_ANRESTART |
4242                                                            BMCR_ANENABLE);
4243                                 udelay(10);
4244                                 netif_carrier_off(tp->dev);
4245                         }
4246                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4247                         bmcr = new_bmcr;
4248                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4249                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4250                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4251                             ASIC_REV_5714) {
4252                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4253                                         bmsr |= BMSR_LSTATUS;
4254                                 else
4255                                         bmsr &= ~BMSR_LSTATUS;
4256                         }
4257                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4258                 }
4259         }
4260
4261         if (bmsr & BMSR_LSTATUS) {
4262                 current_speed = SPEED_1000;
4263                 current_link_up = 1;
4264                 if (bmcr & BMCR_FULLDPLX)
4265                         current_duplex = DUPLEX_FULL;
4266                 else
4267                         current_duplex = DUPLEX_HALF;
4268
4269                 local_adv = 0;
4270                 remote_adv = 0;
4271
4272                 if (bmcr & BMCR_ANENABLE) {
4273                         u32 common;
4274
4275                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4276                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4277                         common = local_adv & remote_adv;
4278                         if (common & (ADVERTISE_1000XHALF |
4279                                       ADVERTISE_1000XFULL)) {
4280                                 if (common & ADVERTISE_1000XFULL)
4281                                         current_duplex = DUPLEX_FULL;
4282                                 else
4283                                         current_duplex = DUPLEX_HALF;
4284                         } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4285                                 /* Link is up via parallel detect */
4286                         } else {
4287                                 current_link_up = 0;
4288                         }
4289                 }
4290         }
4291
4292         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4293                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4294
4295         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4296         if (tp->link_config.active_duplex == DUPLEX_HALF)
4297                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4298
4299         tw32_f(MAC_MODE, tp->mac_mode);
4300         udelay(40);
4301
4302         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4303
4304         tp->link_config.active_speed = current_speed;
4305         tp->link_config.active_duplex = current_duplex;
4306
4307         if (current_link_up != netif_carrier_ok(tp->dev)) {
4308                 if (current_link_up)
4309                         netif_carrier_on(tp->dev);
4310                 else {
4311                         netif_carrier_off(tp->dev);
4312                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4313                 }
4314                 tg3_link_report(tp);
4315         }
4316         return err;
4317 }
4318
4319 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4320 {
4321         if (tp->serdes_counter) {
4322                 /* Give autoneg time to complete. */
4323                 tp->serdes_counter--;
4324                 return;
4325         }
4326
4327         if (!netif_carrier_ok(tp->dev) &&
4328             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4329                 u32 bmcr;
4330
4331                 tg3_readphy(tp, MII_BMCR, &bmcr);
4332                 if (bmcr & BMCR_ANENABLE) {
4333                         u32 phy1, phy2;
4334
4335                         /* Select shadow register 0x1f */
4336                         tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4337                         tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4338
4339                         /* Select expansion interrupt status register */
4340                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4341                                          MII_TG3_DSP_EXP1_INT_STAT);
4342                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4343                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4344
4345                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4346                                 /* We have signal detect and not receiving
4347                                  * config code words, link is up by parallel
4348                                  * detection.
4349                                  */
4350
4351                                 bmcr &= ~BMCR_ANENABLE;
4352                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4353                                 tg3_writephy(tp, MII_BMCR, bmcr);
4354                                 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4355                         }
4356                 }
4357         } else if (netif_carrier_ok(tp->dev) &&
4358                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4359                    (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4360                 u32 phy2;
4361
4362                 /* Select expansion interrupt status register */
4363                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4364                                  MII_TG3_DSP_EXP1_INT_STAT);
4365                 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4366                 if (phy2 & 0x20) {
4367                         u32 bmcr;
4368
4369                         /* Config code words received, turn on autoneg. */
4370                         tg3_readphy(tp, MII_BMCR, &bmcr);
4371                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4372
4373                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4374
4375                 }
4376         }
4377 }
4378
4379 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4380 {
4381         int err;
4382
4383         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4384                 err = tg3_setup_fiber_phy(tp, force_reset);
4385         else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4386                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4387         else
4388                 err = tg3_setup_copper_phy(tp, force_reset);
4389
4390         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4391                 u32 val, scale;
4392
4393                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4394                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4395                         scale = 65;
4396                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4397                         scale = 6;
4398                 else
4399                         scale = 12;
4400
4401                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4402                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4403                 tw32(GRC_MISC_CFG, val);
4404         }
4405
4406         if (tp->link_config.active_speed == SPEED_1000 &&
4407             tp->link_config.active_duplex == DUPLEX_HALF)
4408                 tw32(MAC_TX_LENGTHS,
4409                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4410                       (6 << TX_LENGTHS_IPG_SHIFT) |
4411                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4412         else
4413                 tw32(MAC_TX_LENGTHS,
4414                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4415                       (6 << TX_LENGTHS_IPG_SHIFT) |
4416                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4417
4418         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4419                 if (netif_carrier_ok(tp->dev)) {
4420                         tw32(HOSTCC_STAT_COAL_TICKS,
4421                              tp->coal.stats_block_coalesce_usecs);
4422                 } else {
4423                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4424                 }
4425         }
4426
4427         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4428                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4429                 if (!netif_carrier_ok(tp->dev))
4430                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4431                               tp->pwrmgmt_thresh;
4432                 else
4433                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4434                 tw32(PCIE_PWR_MGMT_THRESH, val);
4435         }
4436
4437         return err;
4438 }
4439
4440 static inline int tg3_irq_sync(struct tg3 *tp)
4441 {
4442         return tp->irq_sync;
4443 }
4444
4445 /* This is called whenever we suspect that the system chipset is re-
4446  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4447  * is bogus tx completions. We try to recover by setting the
4448  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4449  * in the workqueue.
4450  */
4451 static void tg3_tx_recover(struct tg3 *tp)
4452 {
4453         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4454                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4455
4456         netdev_warn(tp->dev,
4457                     "The system may be re-ordering memory-mapped I/O "
4458                     "cycles to the network device, attempting to recover. "
4459                     "Please report the problem to the driver maintainer "
4460                     "and include system chipset information.\n");
4461
4462         spin_lock(&tp->lock);
4463         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4464         spin_unlock(&tp->lock);
4465 }
4466
4467 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4468 {
4469         /* Tell compiler to fetch tx indices from memory. */
4470         barrier();
4471         return tnapi->tx_pending -
4472                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4473 }
4474
4475 /* Tigon3 never reports partial packet sends.  So we do not
4476  * need special logic to handle SKBs that have not had all
4477  * of their frags sent yet, like SunGEM does.
4478  */
4479 static void tg3_tx(struct tg3_napi *tnapi)
4480 {
4481         struct tg3 *tp = tnapi->tp;
4482         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4483         u32 sw_idx = tnapi->tx_cons;
4484         struct netdev_queue *txq;
4485         int index = tnapi - tp->napi;
4486
4487         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4488                 index--;
4489
4490         txq = netdev_get_tx_queue(tp->dev, index);
4491
4492         while (sw_idx != hw_idx) {
4493                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4494                 struct sk_buff *skb = ri->skb;
4495                 int i, tx_bug = 0;
4496
4497                 if (unlikely(skb == NULL)) {
4498                         tg3_tx_recover(tp);
4499                         return;
4500                 }
4501
4502                 pci_unmap_single(tp->pdev,
4503                                  dma_unmap_addr(ri, mapping),
4504                                  skb_headlen(skb),
4505                                  PCI_DMA_TODEVICE);
4506
4507                 ri->skb = NULL;
4508
4509                 sw_idx = NEXT_TX(sw_idx);
4510
4511                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4512                         ri = &tnapi->tx_buffers[sw_idx];
4513                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4514                                 tx_bug = 1;
4515
4516                         pci_unmap_page(tp->pdev,
4517                                        dma_unmap_addr(ri, mapping),
4518                                        skb_shinfo(skb)->frags[i].size,
4519                                        PCI_DMA_TODEVICE);
4520                         sw_idx = NEXT_TX(sw_idx);
4521                 }
4522
4523                 dev_kfree_skb(skb);
4524
4525                 if (unlikely(tx_bug)) {
4526                         tg3_tx_recover(tp);
4527                         return;
4528                 }
4529         }
4530
4531         tnapi->tx_cons = sw_idx;
4532
4533         /* Need to make the tx_cons update visible to tg3_start_xmit()
4534          * before checking for netif_queue_stopped().  Without the
4535          * memory barrier, there is a small possibility that tg3_start_xmit()
4536          * will miss it and cause the queue to be stopped forever.
4537          */
4538         smp_mb();
4539
4540         if (unlikely(netif_tx_queue_stopped(txq) &&
4541                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4542                 __netif_tx_lock(txq, smp_processor_id());
4543                 if (netif_tx_queue_stopped(txq) &&
4544                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4545                         netif_tx_wake_queue(txq);
4546                 __netif_tx_unlock(txq);
4547         }
4548 }
4549
4550 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4551 {
4552         if (!ri->skb)
4553                 return;
4554
4555         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4556                          map_sz, PCI_DMA_FROMDEVICE);
4557         dev_kfree_skb_any(ri->skb);
4558         ri->skb = NULL;
4559 }
4560
4561 /* Returns size of skb allocated or < 0 on error.
4562  *
4563  * We only need to fill in the address because the other members
4564  * of the RX descriptor are invariant, see tg3_init_rings.
4565  *
4566  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4567  * posting buffers we only dirty the first cache line of the RX
4568  * descriptor (containing the address).  Whereas for the RX status
4569  * buffers the cpu only reads the last cacheline of the RX descriptor
4570  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4571  */
4572 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4573                             u32 opaque_key, u32 dest_idx_unmasked)
4574 {
4575         struct tg3_rx_buffer_desc *desc;
4576         struct ring_info *map;
4577         struct sk_buff *skb;
4578         dma_addr_t mapping;
4579         int skb_size, dest_idx;
4580
4581         switch (opaque_key) {
4582         case RXD_OPAQUE_RING_STD:
4583                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4584                 desc = &tpr->rx_std[dest_idx];
4585                 map = &tpr->rx_std_buffers[dest_idx];
4586                 skb_size = tp->rx_pkt_map_sz;
4587                 break;
4588
4589         case RXD_OPAQUE_RING_JUMBO:
4590                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4591                 desc = &tpr->rx_jmb[dest_idx].std;
4592                 map = &tpr->rx_jmb_buffers[dest_idx];
4593                 skb_size = TG3_RX_JMB_MAP_SZ;
4594                 break;
4595
4596         default:
4597                 return -EINVAL;
4598         }
4599
4600         /* Do not overwrite any of the map or rp information
4601          * until we are sure we can commit to a new buffer.
4602          *
4603          * Callers depend upon this behavior and assume that
4604          * we leave everything unchanged if we fail.
4605          */
4606         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4607         if (skb == NULL)
4608                 return -ENOMEM;
4609
4610         skb_reserve(skb, tp->rx_offset);
4611
4612         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4613                                  PCI_DMA_FROMDEVICE);
4614         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4615                 dev_kfree_skb(skb);
4616                 return -EIO;
4617         }
4618
4619         map->skb = skb;
4620         dma_unmap_addr_set(map, mapping, mapping);
4621
4622         desc->addr_hi = ((u64)mapping >> 32);
4623         desc->addr_lo = ((u64)mapping & 0xffffffff);
4624
4625         return skb_size;
4626 }
4627
4628 /* We only need to move over in the address because the other
4629  * members of the RX descriptor are invariant.  See notes above
4630  * tg3_alloc_rx_skb for full details.
4631  */
4632 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4633                            struct tg3_rx_prodring_set *dpr,
4634                            u32 opaque_key, int src_idx,
4635                            u32 dest_idx_unmasked)
4636 {
4637         struct tg3 *tp = tnapi->tp;
4638         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4639         struct ring_info *src_map, *dest_map;
4640         struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
4641         int dest_idx;
4642
4643         switch (opaque_key) {
4644         case RXD_OPAQUE_RING_STD:
4645                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4646                 dest_desc = &dpr->rx_std[dest_idx];
4647                 dest_map = &dpr->rx_std_buffers[dest_idx];
4648                 src_desc = &spr->rx_std[src_idx];
4649                 src_map = &spr->rx_std_buffers[src_idx];
4650                 break;
4651
4652         case RXD_OPAQUE_RING_JUMBO:
4653                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4654                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4655                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4656                 src_desc = &spr->rx_jmb[src_idx].std;
4657                 src_map = &spr->rx_jmb_buffers[src_idx];
4658                 break;
4659
4660         default:
4661                 return;
4662         }
4663
4664         dest_map->skb = src_map->skb;
4665         dma_unmap_addr_set(dest_map, mapping,
4666                            dma_unmap_addr(src_map, mapping));
4667         dest_desc->addr_hi = src_desc->addr_hi;
4668         dest_desc->addr_lo = src_desc->addr_lo;
4669
4670         /* Ensure that the update to the skb happens after the physical
4671          * addresses have been transferred to the new BD location.
4672          */
4673         smp_wmb();
4674
4675         src_map->skb = NULL;
4676 }
4677
4678 /* The RX ring scheme is composed of multiple rings which post fresh
4679  * buffers to the chip, and one special ring the chip uses to report
4680  * status back to the host.
4681  *
4682  * The special ring reports the status of received packets to the
4683  * host.  The chip does not write into the original descriptor the
4684  * RX buffer was obtained from.  The chip simply takes the original
4685  * descriptor as provided by the host, updates the status and length
4686  * field, then writes this into the next status ring entry.
4687  *
4688  * Each ring the host uses to post buffers to the chip is described
4689  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4690  * it is first placed into the on-chip ram.  When the packet's length
4691  * is known, it walks down the TG3_BDINFO entries to select the ring.
4692  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4693  * which is within the range of the new packet's length is chosen.
4694  *
4695  * The "separate ring for rx status" scheme may sound queer, but it makes
4696  * sense from a cache coherency perspective.  If only the host writes
4697  * to the buffer post rings, and only the chip writes to the rx status
4698  * rings, then cache lines never move beyond shared-modified state.
4699  * If both the host and chip were to write into the same ring, cache line
4700  * eviction could occur since both entities want it in an exclusive state.
4701  */
4702 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4703 {
4704         struct tg3 *tp = tnapi->tp;
4705         u32 work_mask, rx_std_posted = 0;
4706         u32 std_prod_idx, jmb_prod_idx;
4707         u32 sw_idx = tnapi->rx_rcb_ptr;
4708         u16 hw_idx;
4709         int received;
4710         struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
4711
4712         hw_idx = *(tnapi->rx_rcb_prod_idx);
4713         /*
4714          * We need to order the read of hw_idx and the read of
4715          * the opaque cookie.
4716          */
4717         rmb();
4718         work_mask = 0;
4719         received = 0;
4720         std_prod_idx = tpr->rx_std_prod_idx;
4721         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4722         while (sw_idx != hw_idx && budget > 0) {
4723                 struct ring_info *ri;
4724                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4725                 unsigned int len;
4726                 struct sk_buff *skb;
4727                 dma_addr_t dma_addr;
4728                 u32 opaque_key, desc_idx, *post_ptr;
4729                 bool hw_vlan __maybe_unused = false;
4730                 u16 vtag __maybe_unused = 0;
4731
4732                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4733                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4734                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4735                         ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4736                         dma_addr = dma_unmap_addr(ri, mapping);
4737                         skb = ri->skb;
4738                         post_ptr = &std_prod_idx;
4739                         rx_std_posted++;
4740                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4741                         ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4742                         dma_addr = dma_unmap_addr(ri, mapping);
4743                         skb = ri->skb;
4744                         post_ptr = &jmb_prod_idx;
4745                 } else
4746                         goto next_pkt_nopost;
4747
4748                 work_mask |= opaque_key;
4749
4750                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4751                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4752                 drop_it:
4753                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4754                                        desc_idx, *post_ptr);
4755                 drop_it_no_recycle:
4756                         /* Other statistics kept track of by card. */
4757                         tp->rx_dropped++;
4758                         goto next_pkt;
4759                 }
4760
4761                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4762                       ETH_FCS_LEN;
4763
4764                 if (len > TG3_RX_COPY_THRESH(tp)) {
4765                         int skb_size;
4766
4767                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4768                                                     *post_ptr);
4769                         if (skb_size < 0)
4770                                 goto drop_it;
4771
4772                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4773                                          PCI_DMA_FROMDEVICE);
4774
4775                         /* Ensure that the update to the skb happens
4776                          * after the usage of the old DMA mapping.
4777                          */
4778                         smp_wmb();
4779
4780                         ri->skb = NULL;
4781
4782                         skb_put(skb, len);
4783                 } else {
4784                         struct sk_buff *copy_skb;
4785
4786                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4787                                        desc_idx, *post_ptr);
4788
4789                         copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
4790                                                     TG3_RAW_IP_ALIGN);
4791                         if (copy_skb == NULL)
4792                                 goto drop_it_no_recycle;
4793
4794                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
4795                         skb_put(copy_skb, len);
4796                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4797                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4798                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4799
4800                         /* We'll reuse the original ring buffer. */
4801                         skb = copy_skb;
4802                 }
4803
4804                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4805                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4806                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4807                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4808                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4809                 else
4810                         skb_checksum_none_assert(skb);
4811
4812                 skb->protocol = eth_type_trans(skb, tp->dev);
4813
4814                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4815                     skb->protocol != htons(ETH_P_8021Q)) {
4816                         dev_kfree_skb(skb);
4817                         goto drop_it_no_recycle;
4818                 }
4819
4820                 if (desc->type_flags & RXD_FLAG_VLAN &&
4821                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
4822                         vtag = desc->err_vlan & RXD_VLAN_MASK;
4823 #if TG3_VLAN_TAG_USED
4824                         if (tp->vlgrp)
4825                                 hw_vlan = true;
4826                         else
4827 #endif
4828                         {
4829                                 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
4830                                                     __skb_push(skb, VLAN_HLEN);
4831
4832                                 memmove(ve, skb->data + VLAN_HLEN,
4833                                         ETH_ALEN * 2);
4834                                 ve->h_vlan_proto = htons(ETH_P_8021Q);
4835                                 ve->h_vlan_TCI = htons(vtag);
4836                         }
4837                 }
4838
4839 #if TG3_VLAN_TAG_USED
4840                 if (hw_vlan)
4841                         vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
4842                 else
4843 #endif
4844                         napi_gro_receive(&tnapi->napi, skb);
4845
4846                 received++;
4847                 budget--;
4848
4849 next_pkt:
4850                 (*post_ptr)++;
4851
4852                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4853                         tpr->rx_std_prod_idx = std_prod_idx &
4854                                                tp->rx_std_ring_mask;
4855                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4856                                      tpr->rx_std_prod_idx);
4857                         work_mask &= ~RXD_OPAQUE_RING_STD;
4858                         rx_std_posted = 0;
4859                 }
4860 next_pkt_nopost:
4861                 sw_idx++;
4862                 sw_idx &= tp->rx_ret_ring_mask;
4863
4864                 /* Refresh hw_idx to see if there is new work */
4865                 if (sw_idx == hw_idx) {
4866                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4867                         rmb();
4868                 }
4869         }
4870
4871         /* ACK the status ring. */
4872         tnapi->rx_rcb_ptr = sw_idx;
4873         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4874
4875         /* Refill RX ring(s). */
4876         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4877                 if (work_mask & RXD_OPAQUE_RING_STD) {
4878                         tpr->rx_std_prod_idx = std_prod_idx &
4879                                                tp->rx_std_ring_mask;
4880                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4881                                      tpr->rx_std_prod_idx);
4882                 }
4883                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4884                         tpr->rx_jmb_prod_idx = jmb_prod_idx &
4885                                                tp->rx_jmb_ring_mask;
4886                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4887                                      tpr->rx_jmb_prod_idx);
4888                 }
4889                 mmiowb();
4890         } else if (work_mask) {
4891                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4892                  * updated before the producer indices can be updated.
4893                  */
4894                 smp_wmb();
4895
4896                 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
4897                 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
4898
4899                 if (tnapi != &tp->napi[1])
4900                         napi_schedule(&tp->napi[1].napi);
4901         }
4902
4903         return received;
4904 }
4905
4906 static void tg3_poll_link(struct tg3 *tp)
4907 {
4908         /* handle link change and other phy events */
4909         if (!(tp->tg3_flags &
4910               (TG3_FLAG_USE_LINKCHG_REG |
4911                TG3_FLAG_POLL_SERDES))) {
4912                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4913
4914                 if (sblk->status & SD_STATUS_LINK_CHG) {
4915                         sblk->status = SD_STATUS_UPDATED |
4916                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4917                         spin_lock(&tp->lock);
4918                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4919                                 tw32_f(MAC_STATUS,
4920                                      (MAC_STATUS_SYNC_CHANGED |
4921                                       MAC_STATUS_CFG_CHANGED |
4922                                       MAC_STATUS_MI_COMPLETION |
4923                                       MAC_STATUS_LNKSTATE_CHANGED));
4924                                 udelay(40);
4925                         } else
4926                                 tg3_setup_phy(tp, 0);
4927                         spin_unlock(&tp->lock);
4928                 }
4929         }
4930 }
4931
4932 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4933                                 struct tg3_rx_prodring_set *dpr,
4934                                 struct tg3_rx_prodring_set *spr)
4935 {
4936         u32 si, di, cpycnt, src_prod_idx;
4937         int i, err = 0;
4938
4939         while (1) {
4940                 src_prod_idx = spr->rx_std_prod_idx;
4941
4942                 /* Make sure updates to the rx_std_buffers[] entries and the
4943                  * standard producer index are seen in the correct order.
4944                  */
4945                 smp_rmb();
4946
4947                 if (spr->rx_std_cons_idx == src_prod_idx)
4948                         break;
4949
4950                 if (spr->rx_std_cons_idx < src_prod_idx)
4951                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4952                 else
4953                         cpycnt = tp->rx_std_ring_mask + 1 -
4954                                  spr->rx_std_cons_idx;
4955
4956                 cpycnt = min(cpycnt,
4957                              tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
4958
4959                 si = spr->rx_std_cons_idx;
4960                 di = dpr->rx_std_prod_idx;
4961
4962                 for (i = di; i < di + cpycnt; i++) {
4963                         if (dpr->rx_std_buffers[i].skb) {
4964                                 cpycnt = i - di;
4965                                 err = -ENOSPC;
4966                                 break;
4967                         }
4968                 }
4969
4970                 if (!cpycnt)
4971                         break;
4972
4973                 /* Ensure that updates to the rx_std_buffers ring and the
4974                  * shadowed hardware producer ring from tg3_recycle_skb() are
4975                  * ordered correctly WRT the skb check above.
4976                  */
4977                 smp_rmb();
4978
4979                 memcpy(&dpr->rx_std_buffers[di],
4980                        &spr->rx_std_buffers[si],
4981                        cpycnt * sizeof(struct ring_info));
4982
4983                 for (i = 0; i < cpycnt; i++, di++, si++) {
4984                         struct tg3_rx_buffer_desc *sbd, *dbd;
4985                         sbd = &spr->rx_std[si];
4986                         dbd = &dpr->rx_std[di];
4987                         dbd->addr_hi = sbd->addr_hi;
4988                         dbd->addr_lo = sbd->addr_lo;
4989                 }
4990
4991                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
4992                                        tp->rx_std_ring_mask;
4993                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
4994                                        tp->rx_std_ring_mask;
4995         }
4996
4997         while (1) {
4998                 src_prod_idx = spr->rx_jmb_prod_idx;
4999
5000                 /* Make sure updates to the rx_jmb_buffers[] entries and
5001                  * the jumbo producer index are seen in the correct order.
5002                  */
5003                 smp_rmb();
5004
5005                 if (spr->rx_jmb_cons_idx == src_prod_idx)
5006                         break;
5007
5008                 if (spr->rx_jmb_cons_idx < src_prod_idx)
5009                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
5010                 else
5011                         cpycnt = tp->rx_jmb_ring_mask + 1 -
5012                                  spr->rx_jmb_cons_idx;
5013
5014                 cpycnt = min(cpycnt,
5015                              tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
5016
5017                 si = spr->rx_jmb_cons_idx;
5018                 di = dpr->rx_jmb_prod_idx;
5019
5020                 for (i = di; i < di + cpycnt; i++) {
5021                         if (dpr->rx_jmb_buffers[i].skb) {
5022                                 cpycnt = i - di;
5023                                 err = -ENOSPC;
5024                                 break;
5025                         }
5026                 }
5027
5028                 if (!cpycnt)
5029                         break;
5030
5031                 /* Ensure that updates to the rx_jmb_buffers ring and the
5032                  * shadowed hardware producer ring from tg3_recycle_skb() are
5033                  * ordered correctly WRT the skb check above.
5034                  */
5035                 smp_rmb();
5036
5037                 memcpy(&dpr->rx_jmb_buffers[di],
5038                        &spr->rx_jmb_buffers[si],
5039                        cpycnt * sizeof(struct ring_info));
5040
5041                 for (i = 0; i < cpycnt; i++, di++, si++) {
5042                         struct tg3_rx_buffer_desc *sbd, *dbd;
5043                         sbd = &spr->rx_jmb[si].std;
5044                         dbd = &dpr->rx_jmb[di].std;
5045                         dbd->addr_hi = sbd->addr_hi;
5046                         dbd->addr_lo = sbd->addr_lo;
5047                 }
5048
5049                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
5050                                        tp->rx_jmb_ring_mask;
5051                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
5052                                        tp->rx_jmb_ring_mask;
5053         }
5054
5055         return err;
5056 }
5057
5058 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
5059 {
5060         struct tg3 *tp = tnapi->tp;
5061
5062         /* run TX completion thread */
5063         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
5064                 tg3_tx(tnapi);
5065                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5066                         return work_done;
5067         }
5068
5069         /* run RX thread, within the bounds set by NAPI.
5070          * All RX "locking" is done by ensuring outside
5071          * code synchronizes with tg3->napi.poll()
5072          */
5073         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
5074                 work_done += tg3_rx(tnapi, budget - work_done);
5075
5076         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
5077                 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
5078                 int i, err = 0;
5079                 u32 std_prod_idx = dpr->rx_std_prod_idx;
5080                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
5081
5082                 for (i = 1; i < tp->irq_cnt; i++)
5083                         err |= tg3_rx_prodring_xfer(tp, dpr,
5084                                                     &tp->napi[i].prodring);
5085
5086                 wmb();
5087
5088                 if (std_prod_idx != dpr->rx_std_prod_idx)
5089                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5090                                      dpr->rx_std_prod_idx);
5091
5092                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5093                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5094                                      dpr->rx_jmb_prod_idx);
5095
5096                 mmiowb();
5097
5098                 if (err)
5099                         tw32_f(HOSTCC_MODE, tp->coal_now);
5100         }
5101
5102         return work_done;
5103 }
5104
5105 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5106 {
5107         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5108         struct tg3 *tp = tnapi->tp;
5109         int work_done = 0;
5110         struct tg3_hw_status *sblk = tnapi->hw_status;
5111
5112         while (1) {
5113                 work_done = tg3_poll_work(tnapi, work_done, budget);
5114
5115                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5116                         goto tx_recovery;
5117
5118                 if (unlikely(work_done >= budget))
5119                         break;
5120
5121                 /* tp->last_tag is used in tg3_int_reenable() below
5122                  * to tell the hw how much work has been processed,
5123                  * so we must read it before checking for more work.
5124                  */
5125                 tnapi->last_tag = sblk->status_tag;
5126                 tnapi->last_irq_tag = tnapi->last_tag;
5127                 rmb();
5128
5129                 /* check for RX/TX work to do */
5130                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5131                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5132                         napi_complete(napi);
5133                         /* Reenable interrupts. */
5134                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5135                         mmiowb();
5136                         break;
5137                 }
5138         }
5139
5140         return work_done;
5141
5142 tx_recovery:
5143         /* work_done is guaranteed to be less than budget. */
5144         napi_complete(napi);
5145         schedule_work(&tp->reset_task);
5146         return work_done;
5147 }
5148
5149 static int tg3_poll(struct napi_struct *napi, int budget)
5150 {
5151         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5152         struct tg3 *tp = tnapi->tp;
5153         int work_done = 0;
5154         struct tg3_hw_status *sblk = tnapi->hw_status;
5155
5156         while (1) {
5157                 tg3_poll_link(tp);
5158
5159                 work_done = tg3_poll_work(tnapi, work_done, budget);
5160
5161                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5162                         goto tx_recovery;
5163
5164                 if (unlikely(work_done >= budget))
5165                         break;
5166
5167                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5168                         /* tp->last_tag is used in tg3_int_reenable() below
5169                          * to tell the hw how much work has been processed,
5170                          * so we must read it before checking for more work.
5171                          */
5172                         tnapi->last_tag = sblk->status_tag;
5173                         tnapi->last_irq_tag = tnapi->last_tag;
5174                         rmb();
5175                 } else
5176                         sblk->status &= ~SD_STATUS_UPDATED;
5177
5178                 if (likely(!tg3_has_work(tnapi))) {
5179                         napi_complete(napi);
5180                         tg3_int_reenable(tnapi);
5181                         break;
5182                 }
5183         }
5184
5185         return work_done;
5186
5187 tx_recovery:
5188         /* work_done is guaranteed to be less than budget. */
5189         napi_complete(napi);
5190         schedule_work(&tp->reset_task);
5191         return work_done;
5192 }
5193
5194 static void tg3_napi_disable(struct tg3 *tp)
5195 {
5196         int i;
5197
5198         for (i = tp->irq_cnt - 1; i >= 0; i--)
5199                 napi_disable(&tp->napi[i].napi);
5200 }
5201
5202 static void tg3_napi_enable(struct tg3 *tp)
5203 {
5204         int i;
5205
5206         for (i = 0; i < tp->irq_cnt; i++)
5207                 napi_enable(&tp->napi[i].napi);
5208 }
5209
5210 static void tg3_napi_init(struct tg3 *tp)
5211 {
5212         int i;
5213
5214         netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
5215         for (i = 1; i < tp->irq_cnt; i++)
5216                 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
5217 }
5218
5219 static void tg3_napi_fini(struct tg3 *tp)
5220 {
5221         int i;
5222
5223         for (i = 0; i < tp->irq_cnt; i++)
5224                 netif_napi_del(&tp->napi[i].napi);
5225 }
5226
5227 static inline void tg3_netif_stop(struct tg3 *tp)
5228 {
5229         tp->dev->trans_start = jiffies; /* prevent tx timeout */
5230         tg3_napi_disable(tp);
5231         netif_tx_disable(tp->dev);
5232 }
5233
5234 static inline void tg3_netif_start(struct tg3 *tp)
5235 {
5236         /* NOTE: unconditional netif_tx_wake_all_queues is only
5237          * appropriate so long as all callers are assured to
5238          * have free tx slots (such as after tg3_init_hw)
5239          */
5240         netif_tx_wake_all_queues(tp->dev);
5241
5242         tg3_napi_enable(tp);
5243         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
5244         tg3_enable_ints(tp);
5245 }
5246
5247 static void tg3_irq_quiesce(struct tg3 *tp)
5248 {
5249         int i;
5250
5251         BUG_ON(tp->irq_sync);
5252
5253         tp->irq_sync = 1;
5254         smp_mb();
5255
5256         for (i = 0; i < tp->irq_cnt; i++)
5257                 synchronize_irq(tp->napi[i].irq_vec);
5258 }
5259
5260 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5261  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5262  * with as well.  Most of the time, this is not necessary except when
5263  * shutting down the device.
5264  */
5265 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5266 {
5267         spin_lock_bh(&tp->lock);
5268         if (irq_sync)
5269                 tg3_irq_quiesce(tp);
5270 }
5271
5272 static inline void tg3_full_unlock(struct tg3 *tp)
5273 {
5274         spin_unlock_bh(&tp->lock);
5275 }
5276
5277 /* One-shot MSI handler - Chip automatically disables interrupt
5278  * after sending MSI so driver doesn't have to do it.
5279  */
5280 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5281 {
5282         struct tg3_napi *tnapi = dev_id;
5283         struct tg3 *tp = tnapi->tp;
5284
5285         prefetch(tnapi->hw_status);
5286         if (tnapi->rx_rcb)
5287                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5288
5289         if (likely(!tg3_irq_sync(tp)))
5290                 napi_schedule(&tnapi->napi);
5291
5292         return IRQ_HANDLED;
5293 }
5294
5295 /* MSI ISR - No need to check for interrupt sharing and no need to
5296  * flush status block and interrupt mailbox. PCI ordering rules
5297  * guarantee that MSI will arrive after the status block.
5298  */
5299 static irqreturn_t tg3_msi(int irq, void *dev_id)
5300 {
5301         struct tg3_napi *tnapi = dev_id;
5302         struct tg3 *tp = tnapi->tp;
5303
5304         prefetch(tnapi->hw_status);
5305         if (tnapi->rx_rcb)
5306                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5307         /*
5308          * Writing any value to intr-mbox-0 clears PCI INTA# and
5309          * chip-internal interrupt pending events.
5310          * Writing non-zero to intr-mbox-0 additional tells the
5311          * NIC to stop sending us irqs, engaging "in-intr-handler"
5312          * event coalescing.
5313          */
5314         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5315         if (likely(!tg3_irq_sync(tp)))
5316                 napi_schedule(&tnapi->napi);
5317
5318         return IRQ_RETVAL(1);
5319 }
5320
5321 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5322 {
5323         struct tg3_napi *tnapi = dev_id;
5324         struct tg3 *tp = tnapi->tp;
5325         struct tg3_hw_status *sblk = tnapi->hw_status;
5326         unsigned int handled = 1;
5327
5328         /* In INTx mode, it is possible for the interrupt to arrive at
5329          * the CPU before the status block posted prior to the interrupt.
5330          * Reading the PCI State register will confirm whether the
5331          * interrupt is ours and will flush the status block.
5332          */
5333         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5334                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5335                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5336                         handled = 0;
5337                         goto out;
5338                 }
5339         }
5340
5341         /*
5342          * Writing any value to intr-mbox-0 clears PCI INTA# and
5343          * chip-internal interrupt pending events.
5344          * Writing non-zero to intr-mbox-0 additional tells the
5345          * NIC to stop sending us irqs, engaging "in-intr-handler"
5346          * event coalescing.
5347          *
5348          * Flush the mailbox to de-assert the IRQ immediately to prevent
5349          * spurious interrupts.  The flush impacts performance but
5350          * excessive spurious interrupts can be worse in some cases.
5351          */
5352         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5353         if (tg3_irq_sync(tp))
5354                 goto out;
5355         sblk->status &= ~SD_STATUS_UPDATED;
5356         if (likely(tg3_has_work(tnapi))) {
5357                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5358                 napi_schedule(&tnapi->napi);
5359         } else {
5360                 /* No work, shared interrupt perhaps?  re-enable
5361                  * interrupts, and flush that PCI write
5362                  */
5363                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5364                                0x00000000);
5365         }
5366 out:
5367         return IRQ_RETVAL(handled);
5368 }
5369
5370 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5371 {
5372         struct tg3_napi *tnapi = dev_id;
5373         struct tg3 *tp = tnapi->tp;
5374         struct tg3_hw_status *sblk = tnapi->hw_status;
5375         unsigned int handled = 1;
5376
5377         /* In INTx mode, it is possible for the interrupt to arrive at
5378          * the CPU before the status block posted prior to the interrupt.
5379          * Reading the PCI State register will confirm whether the
5380          * interrupt is ours and will flush the status block.
5381          */
5382         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5383                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5384                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5385                         handled = 0;
5386                         goto out;
5387                 }
5388         }
5389
5390         /*
5391          * writing any value to intr-mbox-0 clears PCI INTA# and
5392          * chip-internal interrupt pending events.
5393          * writing non-zero to intr-mbox-0 additional tells the
5394          * NIC to stop sending us irqs, engaging "in-intr-handler"
5395          * event coalescing.
5396          *
5397          * Flush the mailbox to de-assert the IRQ immediately to prevent
5398          * spurious interrupts.  The flush impacts performance but
5399          * excessive spurious interrupts can be worse in some cases.
5400          */
5401         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5402
5403         /*
5404          * In a shared interrupt configuration, sometimes other devices'
5405          * interrupts will scream.  We record the current status tag here
5406          * so that the above check can report that the screaming interrupts
5407          * are unhandled.  Eventually they will be silenced.
5408          */
5409         tnapi->last_irq_tag = sblk->status_tag;
5410
5411         if (tg3_irq_sync(tp))
5412                 goto out;
5413
5414         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5415
5416         napi_schedule(&tnapi->napi);
5417
5418 out:
5419         return IRQ_RETVAL(handled);
5420 }
5421
5422 /* ISR for interrupt test */
5423 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5424 {
5425         struct tg3_napi *tnapi = dev_id;
5426         struct tg3 *tp = tnapi->tp;
5427         struct tg3_hw_status *sblk = tnapi->hw_status;
5428
5429         if ((sblk->status & SD_STATUS_UPDATED) ||
5430             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5431                 tg3_disable_ints(tp);
5432                 return IRQ_RETVAL(1);
5433         }
5434         return IRQ_RETVAL(0);
5435 }
5436
5437 static int tg3_init_hw(struct tg3 *, int);
5438 static int tg3_halt(struct tg3 *, int, int);
5439
5440 /* Restart hardware after configuration changes, self-test, etc.
5441  * Invoked with tp->lock held.
5442  */
5443 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5444         __releases(tp->lock)
5445         __acquires(tp->lock)
5446 {
5447         int err;
5448
5449         err = tg3_init_hw(tp, reset_phy);
5450         if (err) {
5451                 netdev_err(tp->dev,
5452                            "Failed to re-initialize device, aborting\n");
5453                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5454                 tg3_full_unlock(tp);
5455                 del_timer_sync(&tp->timer);
5456                 tp->irq_sync = 0;
5457                 tg3_napi_enable(tp);
5458                 dev_close(tp->dev);
5459                 tg3_full_lock(tp, 0);
5460         }
5461         return err;
5462 }
5463
5464 #ifdef CONFIG_NET_POLL_CONTROLLER
5465 static void tg3_poll_controller(struct net_device *dev)
5466 {
5467         int i;
5468         struct tg3 *tp = netdev_priv(dev);
5469
5470         for (i = 0; i < tp->irq_cnt; i++)
5471                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5472 }
5473 #endif
5474
5475 static void tg3_reset_task(struct work_struct *work)
5476 {
5477         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5478         int err;
5479         unsigned int restart_timer;
5480
5481         tg3_full_lock(tp, 0);
5482
5483         if (!netif_running(tp->dev)) {
5484                 tg3_full_unlock(tp);
5485                 return;
5486         }
5487
5488         tg3_full_unlock(tp);
5489
5490         tg3_phy_stop(tp);
5491
5492         tg3_netif_stop(tp);
5493
5494         tg3_full_lock(tp, 1);
5495
5496         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5497         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5498
5499         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5500                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5501                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5502                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5503                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5504         }
5505
5506         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5507         err = tg3_init_hw(tp, 1);
5508         if (err)
5509                 goto out;
5510
5511         tg3_netif_start(tp);
5512
5513         if (restart_timer)
5514                 mod_timer(&tp->timer, jiffies + 1);
5515
5516 out:
5517         tg3_full_unlock(tp);
5518
5519         if (!err)
5520                 tg3_phy_start(tp);
5521 }
5522
5523 static void tg3_dump_short_state(struct tg3 *tp)
5524 {
5525         netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5526                    tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5527         netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5528                    tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5529 }
5530
5531 static void tg3_tx_timeout(struct net_device *dev)
5532 {
5533         struct tg3 *tp = netdev_priv(dev);
5534
5535         if (netif_msg_tx_err(tp)) {
5536                 netdev_err(dev, "transmit timed out, resetting\n");
5537                 tg3_dump_short_state(tp);
5538         }
5539
5540         schedule_work(&tp->reset_task);
5541 }
5542
5543 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5544 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5545 {
5546         u32 base = (u32) mapping & 0xffffffff;
5547
5548         return (base > 0xffffdcc0) && (base + len + 8 < base);
5549 }
5550
5551 /* Test for DMA addresses > 40-bit */
5552 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5553                                           int len)
5554 {
5555 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5556         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5557                 return ((u64) mapping + len) > DMA_BIT_MASK(40);
5558         return 0;
5559 #else
5560         return 0;
5561 #endif
5562 }
5563
5564 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5565
5566 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5567 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5568                                        struct sk_buff *skb, u32 last_plus_one,
5569                                        u32 *start, u32 base_flags, u32 mss)
5570 {
5571         struct tg3 *tp = tnapi->tp;
5572         struct sk_buff *new_skb;
5573         dma_addr_t new_addr = 0;
5574         u32 entry = *start;
5575         int i, ret = 0;
5576
5577         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5578                 new_skb = skb_copy(skb, GFP_ATOMIC);
5579         else {
5580                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5581
5582                 new_skb = skb_copy_expand(skb,
5583                                           skb_headroom(skb) + more_headroom,
5584                                           skb_tailroom(skb), GFP_ATOMIC);
5585         }
5586
5587         if (!new_skb) {
5588                 ret = -1;
5589         } else {
5590                 /* New SKB is guaranteed to be linear. */
5591                 entry = *start;
5592                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5593                                           PCI_DMA_TODEVICE);
5594                 /* Make sure the mapping succeeded */
5595                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5596                         ret = -1;
5597                         dev_kfree_skb(new_skb);
5598                         new_skb = NULL;
5599
5600                 /* Make sure new skb does not cross any 4G boundaries.
5601                  * Drop the packet if it does.
5602                  */
5603                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5604                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5605                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5606                                          PCI_DMA_TODEVICE);
5607                         ret = -1;
5608                         dev_kfree_skb(new_skb);
5609                         new_skb = NULL;
5610                 } else {
5611                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5612                                     base_flags, 1 | (mss << 1));
5613                         *start = NEXT_TX(entry);
5614                 }
5615         }
5616
5617         /* Now clean up the sw ring entries. */
5618         i = 0;
5619         while (entry != last_plus_one) {
5620                 int len;
5621
5622                 if (i == 0)
5623                         len = skb_headlen(skb);
5624                 else
5625                         len = skb_shinfo(skb)->frags[i-1].size;
5626
5627                 pci_unmap_single(tp->pdev,
5628                                  dma_unmap_addr(&tnapi->tx_buffers[entry],
5629                                                 mapping),
5630                                  len, PCI_DMA_TODEVICE);
5631                 if (i == 0) {
5632                         tnapi->tx_buffers[entry].skb = new_skb;
5633                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5634                                            new_addr);
5635                 } else {
5636                         tnapi->tx_buffers[entry].skb = NULL;
5637                 }
5638                 entry = NEXT_TX(entry);
5639                 i++;
5640         }
5641
5642         dev_kfree_skb(skb);
5643
5644         return ret;
5645 }
5646
5647 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5648                         dma_addr_t mapping, int len, u32 flags,
5649                         u32 mss_and_is_end)
5650 {
5651         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5652         int is_end = (mss_and_is_end & 0x1);
5653         u32 mss = (mss_and_is_end >> 1);
5654         u32 vlan_tag = 0;
5655
5656         if (is_end)
5657                 flags |= TXD_FLAG_END;
5658         if (flags & TXD_FLAG_VLAN) {
5659                 vlan_tag = flags >> 16;
5660                 flags &= 0xffff;
5661         }
5662         vlan_tag |= (mss << TXD_MSS_SHIFT);
5663
5664         txd->addr_hi = ((u64) mapping >> 32);
5665         txd->addr_lo = ((u64) mapping & 0xffffffff);
5666         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5667         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5668 }
5669
5670 /* hard_start_xmit for devices that don't have any bugs and
5671  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5672  */
5673 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5674                                   struct net_device *dev)
5675 {
5676         struct tg3 *tp = netdev_priv(dev);
5677         u32 len, entry, base_flags, mss;
5678         dma_addr_t mapping;
5679         struct tg3_napi *tnapi;
5680         struct netdev_queue *txq;
5681         unsigned int i, last;
5682
5683         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5684         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5685         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5686                 tnapi++;
5687
5688         /* We are running in BH disabled context with netif_tx_lock
5689          * and TX reclaim runs via tp->napi.poll inside of a software
5690          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5691          * no IRQ context deadlocks to worry about either.  Rejoice!
5692          */
5693         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5694                 if (!netif_tx_queue_stopped(txq)) {
5695                         netif_tx_stop_queue(txq);
5696
5697                         /* This is a hard error, log it. */
5698                         netdev_err(dev,
5699                                    "BUG! Tx Ring full when queue awake!\n");
5700                 }
5701                 return NETDEV_TX_BUSY;
5702         }
5703
5704         entry = tnapi->tx_prod;
5705         base_flags = 0;
5706         mss = skb_shinfo(skb)->gso_size;
5707         if (mss) {
5708                 int tcp_opt_len, ip_tcp_len;
5709                 u32 hdrlen;
5710
5711                 if (skb_header_cloned(skb) &&
5712                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5713                         dev_kfree_skb(skb);
5714                         goto out_unlock;
5715                 }
5716
5717                 if (skb_is_gso_v6(skb)) {
5718                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5719                 } else {
5720                         struct iphdr *iph = ip_hdr(skb);
5721
5722                         tcp_opt_len = tcp_optlen(skb);
5723                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5724
5725                         iph->check = 0;
5726                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5727                         hdrlen = ip_tcp_len + tcp_opt_len;
5728                 }
5729
5730                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5731                         mss |= (hdrlen & 0xc) << 12;
5732                         if (hdrlen & 0x10)
5733                                 base_flags |= 0x00000010;
5734                         base_flags |= (hdrlen & 0x3e0) << 5;
5735                 } else
5736                         mss |= hdrlen << 9;
5737
5738                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5739                                TXD_FLAG_CPU_POST_DMA);
5740
5741                 tcp_hdr(skb)->check = 0;
5742
5743         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5744                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5745         }
5746
5747 #if TG3_VLAN_TAG_USED
5748         if (vlan_tx_tag_present(skb))
5749                 base_flags |= (TXD_FLAG_VLAN |
5750                                (vlan_tx_tag_get(skb) << 16));
5751 #endif
5752
5753         len = skb_headlen(skb);
5754
5755         /* Queue skb data, a.k.a. the main skb fragment. */
5756         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5757         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5758                 dev_kfree_skb(skb);
5759                 goto out_unlock;
5760         }
5761
5762         tnapi->tx_buffers[entry].skb = skb;
5763         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5764
5765         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5766             !mss && skb->len > ETH_DATA_LEN)
5767                 base_flags |= TXD_FLAG_JMB_PKT;
5768
5769