tg3: cleanup pci device table vars
[linux-2.6.git] / drivers / net / tg3.c
1 /*
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  * Copyright (C) 2005-2011 Broadcom Corporation.
8  *
9  * Firmware is:
10  *      Derived from proprietary unpublished source code,
11  *      Copyright (C) 2000-2003 Broadcom Corporation.
12  *
13  *      Permission is hereby granted for the distribution of this firmware
14  *      data in hexadecimal or equivalent format, provided this copyright
15  *      notice is accompanying it.
16  */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/in.h>
28 #include <linux/init.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mdio.h>
36 #include <linux/mii.h>
37 #include <linux/phy.h>
38 #include <linux/brcmphy.h>
39 #include <linux/if_vlan.h>
40 #include <linux/ip.h>
41 #include <linux/tcp.h>
42 #include <linux/workqueue.h>
43 #include <linux/prefetch.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/firmware.h>
46
47 #include <net/checksum.h>
48 #include <net/ip.h>
49
50 #include <asm/system.h>
51 #include <asm/io.h>
52 #include <asm/byteorder.h>
53 #include <asm/uaccess.h>
54
55 #ifdef CONFIG_SPARC
56 #include <asm/idprom.h>
57 #include <asm/prom.h>
58 #endif
59
60 #define BAR_0   0
61 #define BAR_2   2
62
63 #include "tg3.h"
64
65 #define DRV_MODULE_NAME         "tg3"
66 #define TG3_MAJ_NUM                     3
67 #define TG3_MIN_NUM                     117
68 #define DRV_MODULE_VERSION      \
69         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
70 #define DRV_MODULE_RELDATE      "January 25, 2011"
71
72 #define TG3_DEF_MAC_MODE        0
73 #define TG3_DEF_RX_MODE         0
74 #define TG3_DEF_TX_MODE         0
75 #define TG3_DEF_MSG_ENABLE        \
76         (NETIF_MSG_DRV          | \
77          NETIF_MSG_PROBE        | \
78          NETIF_MSG_LINK         | \
79          NETIF_MSG_TIMER        | \
80          NETIF_MSG_IFDOWN       | \
81          NETIF_MSG_IFUP         | \
82          NETIF_MSG_RX_ERR       | \
83          NETIF_MSG_TX_ERR)
84
85 /* length of time before we decide the hardware is borked,
86  * and dev->tx_timeout() should be called to fix the problem
87  */
88 #define TG3_TX_TIMEOUT                  (5 * HZ)
89
90 /* hardware minimum and maximum for a single frame's data payload */
91 #define TG3_MIN_MTU                     60
92 #define TG3_MAX_MTU(tp) \
93         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
94
95 /* These numbers seem to be hard coded in the NIC firmware somehow.
96  * You can't change the ring sizes, but you can change where you place
97  * them in the NIC onboard memory.
98  */
99 #define TG3_RX_STD_RING_SIZE(tp) \
100         ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
101           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
102          RX_STD_MAX_SIZE_5717 : 512)
103 #define TG3_DEF_RX_RING_PENDING         200
104 #define TG3_RX_JMB_RING_SIZE(tp) \
105         ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
106           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
107          1024 : 256)
108 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
109 #define TG3_RSS_INDIR_TBL_SIZE          128
110
111 /* Do not place this n-ring entries value into the tp struct itself,
112  * we really want to expose these constants to GCC so that modulo et
113  * al.  operations are done with shifts and masks instead of with
114  * hw multiply/modulo instructions.  Another solution would be to
115  * replace things like '% foo' with '& (foo - 1)'.
116  */
117
118 #define TG3_TX_RING_SIZE                512
119 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
120
121 #define TG3_RX_STD_RING_BYTES(tp) \
122         (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
123 #define TG3_RX_JMB_RING_BYTES(tp) \
124         (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
125 #define TG3_RX_RCB_RING_BYTES(tp) \
126         (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
127 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
128                                  TG3_TX_RING_SIZE)
129 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
130
131 #define TG3_DMA_BYTE_ENAB               64
132
133 #define TG3_RX_STD_DMA_SZ               1536
134 #define TG3_RX_JMB_DMA_SZ               9046
135
136 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
137
138 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
139 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
140
141 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
142         (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
143
144 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
145         (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
146
147 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
148  * that are at least dword aligned when used in PCIX mode.  The driver
149  * works around this bug by double copying the packet.  This workaround
150  * is built into the normal double copy length check for efficiency.
151  *
152  * However, the double copy is only necessary on those architectures
153  * where unaligned memory accesses are inefficient.  For those architectures
154  * where unaligned memory accesses incur little penalty, we can reintegrate
155  * the 5701 in the normal rx path.  Doing so saves a device structure
156  * dereference by hardcoding the double copy threshold in place.
157  */
158 #define TG3_RX_COPY_THRESHOLD           256
159 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
160         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
161 #else
162         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
163 #endif
164
165 /* minimum number of free TX descriptors required to wake up TX process */
166 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
167
168 #define TG3_RAW_IP_ALIGN 2
169
170 /* number of ETHTOOL_GSTATS u64's */
171 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
172
173 #define TG3_NUM_TEST            6
174
175 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
176
177 #define FIRMWARE_TG3            "tigon/tg3.bin"
178 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
179 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
180
181 static char version[] __devinitdata =
182         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
183
184 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
185 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
186 MODULE_LICENSE("GPL");
187 MODULE_VERSION(DRV_MODULE_VERSION);
188 MODULE_FIRMWARE(FIRMWARE_TG3);
189 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
190 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
191
192 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
193 module_param(tg3_debug, int, 0);
194 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
195
196 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
268         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
269         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
270         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
271         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
272         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
273         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
274         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
275         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
276         {}
277 };
278
279 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
280
281 static const struct {
282         const char string[ETH_GSTRING_LEN];
283 } ethtool_stats_keys[TG3_NUM_STATS] = {
284         { "rx_octets" },
285         { "rx_fragments" },
286         { "rx_ucast_packets" },
287         { "rx_mcast_packets" },
288         { "rx_bcast_packets" },
289         { "rx_fcs_errors" },
290         { "rx_align_errors" },
291         { "rx_xon_pause_rcvd" },
292         { "rx_xoff_pause_rcvd" },
293         { "rx_mac_ctrl_rcvd" },
294         { "rx_xoff_entered" },
295         { "rx_frame_too_long_errors" },
296         { "rx_jabbers" },
297         { "rx_undersize_packets" },
298         { "rx_in_length_errors" },
299         { "rx_out_length_errors" },
300         { "rx_64_or_less_octet_packets" },
301         { "rx_65_to_127_octet_packets" },
302         { "rx_128_to_255_octet_packets" },
303         { "rx_256_to_511_octet_packets" },
304         { "rx_512_to_1023_octet_packets" },
305         { "rx_1024_to_1522_octet_packets" },
306         { "rx_1523_to_2047_octet_packets" },
307         { "rx_2048_to_4095_octet_packets" },
308         { "rx_4096_to_8191_octet_packets" },
309         { "rx_8192_to_9022_octet_packets" },
310
311         { "tx_octets" },
312         { "tx_collisions" },
313
314         { "tx_xon_sent" },
315         { "tx_xoff_sent" },
316         { "tx_flow_control" },
317         { "tx_mac_errors" },
318         { "tx_single_collisions" },
319         { "tx_mult_collisions" },
320         { "tx_deferred" },
321         { "tx_excessive_collisions" },
322         { "tx_late_collisions" },
323         { "tx_collide_2times" },
324         { "tx_collide_3times" },
325         { "tx_collide_4times" },
326         { "tx_collide_5times" },
327         { "tx_collide_6times" },
328         { "tx_collide_7times" },
329         { "tx_collide_8times" },
330         { "tx_collide_9times" },
331         { "tx_collide_10times" },
332         { "tx_collide_11times" },
333         { "tx_collide_12times" },
334         { "tx_collide_13times" },
335         { "tx_collide_14times" },
336         { "tx_collide_15times" },
337         { "tx_ucast_packets" },
338         { "tx_mcast_packets" },
339         { "tx_bcast_packets" },
340         { "tx_carrier_sense_errors" },
341         { "tx_discards" },
342         { "tx_errors" },
343
344         { "dma_writeq_full" },
345         { "dma_write_prioq_full" },
346         { "rxbds_empty" },
347         { "rx_discards" },
348         { "rx_errors" },
349         { "rx_threshold_hit" },
350
351         { "dma_readq_full" },
352         { "dma_read_prioq_full" },
353         { "tx_comp_queue_full" },
354
355         { "ring_set_send_prod_index" },
356         { "ring_status_update" },
357         { "nic_irqs" },
358         { "nic_avoided_irqs" },
359         { "nic_tx_threshold_hit" }
360 };
361
362 static const struct {
363         const char string[ETH_GSTRING_LEN];
364 } ethtool_test_keys[TG3_NUM_TEST] = {
365         { "nvram test     (online) " },
366         { "link test      (online) " },
367         { "register test  (offline)" },
368         { "memory test    (offline)" },
369         { "loopback test  (offline)" },
370         { "interrupt test (offline)" },
371 };
372
373 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
374 {
375         writel(val, tp->regs + off);
376 }
377
378 static u32 tg3_read32(struct tg3 *tp, u32 off)
379 {
380         return readl(tp->regs + off);
381 }
382
383 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
384 {
385         writel(val, tp->aperegs + off);
386 }
387
388 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
389 {
390         return readl(tp->aperegs + off);
391 }
392
393 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
394 {
395         unsigned long flags;
396
397         spin_lock_irqsave(&tp->indirect_lock, flags);
398         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
399         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
400         spin_unlock_irqrestore(&tp->indirect_lock, flags);
401 }
402
403 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
404 {
405         writel(val, tp->regs + off);
406         readl(tp->regs + off);
407 }
408
409 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
410 {
411         unsigned long flags;
412         u32 val;
413
414         spin_lock_irqsave(&tp->indirect_lock, flags);
415         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
416         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
417         spin_unlock_irqrestore(&tp->indirect_lock, flags);
418         return val;
419 }
420
421 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
422 {
423         unsigned long flags;
424
425         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
426                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
427                                        TG3_64BIT_REG_LOW, val);
428                 return;
429         }
430         if (off == TG3_RX_STD_PROD_IDX_REG) {
431                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
432                                        TG3_64BIT_REG_LOW, val);
433                 return;
434         }
435
436         spin_lock_irqsave(&tp->indirect_lock, flags);
437         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
438         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
439         spin_unlock_irqrestore(&tp->indirect_lock, flags);
440
441         /* In indirect mode when disabling interrupts, we also need
442          * to clear the interrupt bit in the GRC local ctrl register.
443          */
444         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
445             (val == 0x1)) {
446                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
447                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
448         }
449 }
450
451 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
452 {
453         unsigned long flags;
454         u32 val;
455
456         spin_lock_irqsave(&tp->indirect_lock, flags);
457         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
458         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
459         spin_unlock_irqrestore(&tp->indirect_lock, flags);
460         return val;
461 }
462
463 /* usec_wait specifies the wait time in usec when writing to certain registers
464  * where it is unsafe to read back the register without some delay.
465  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
466  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
467  */
468 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
469 {
470         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
471             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
472                 /* Non-posted methods */
473                 tp->write32(tp, off, val);
474         else {
475                 /* Posted method */
476                 tg3_write32(tp, off, val);
477                 if (usec_wait)
478                         udelay(usec_wait);
479                 tp->read32(tp, off);
480         }
481         /* Wait again after the read for the posted method to guarantee that
482          * the wait time is met.
483          */
484         if (usec_wait)
485                 udelay(usec_wait);
486 }
487
488 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
489 {
490         tp->write32_mbox(tp, off, val);
491         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
492             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
493                 tp->read32_mbox(tp, off);
494 }
495
496 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
497 {
498         void __iomem *mbox = tp->regs + off;
499         writel(val, mbox);
500         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
501                 writel(val, mbox);
502         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
503                 readl(mbox);
504 }
505
506 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
507 {
508         return readl(tp->regs + off + GRCMBOX_BASE);
509 }
510
511 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
512 {
513         writel(val, tp->regs + off + GRCMBOX_BASE);
514 }
515
516 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
517 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
518 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
519 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
520 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
521
522 #define tw32(reg, val)                  tp->write32(tp, reg, val)
523 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
524 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
525 #define tr32(reg)                       tp->read32(tp, reg)
526
527 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
528 {
529         unsigned long flags;
530
531         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
532             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
533                 return;
534
535         spin_lock_irqsave(&tp->indirect_lock, flags);
536         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
537                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
538                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
539
540                 /* Always leave this as zero. */
541                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
542         } else {
543                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
544                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
545
546                 /* Always leave this as zero. */
547                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
548         }
549         spin_unlock_irqrestore(&tp->indirect_lock, flags);
550 }
551
552 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
553 {
554         unsigned long flags;
555
556         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
557             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
558                 *val = 0;
559                 return;
560         }
561
562         spin_lock_irqsave(&tp->indirect_lock, flags);
563         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
564                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
565                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
566
567                 /* Always leave this as zero. */
568                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
569         } else {
570                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
571                 *val = tr32(TG3PCI_MEM_WIN_DATA);
572
573                 /* Always leave this as zero. */
574                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
575         }
576         spin_unlock_irqrestore(&tp->indirect_lock, flags);
577 }
578
579 static void tg3_ape_lock_init(struct tg3 *tp)
580 {
581         int i;
582         u32 regbase;
583
584         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
585                 regbase = TG3_APE_LOCK_GRANT;
586         else
587                 regbase = TG3_APE_PER_LOCK_GRANT;
588
589         /* Make sure the driver hasn't any stale locks. */
590         for (i = 0; i < 8; i++)
591                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
592 }
593
594 static int tg3_ape_lock(struct tg3 *tp, int locknum)
595 {
596         int i, off;
597         int ret = 0;
598         u32 status, req, gnt;
599
600         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
601                 return 0;
602
603         switch (locknum) {
604         case TG3_APE_LOCK_GRC:
605         case TG3_APE_LOCK_MEM:
606                 break;
607         default:
608                 return -EINVAL;
609         }
610
611         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
612                 req = TG3_APE_LOCK_REQ;
613                 gnt = TG3_APE_LOCK_GRANT;
614         } else {
615                 req = TG3_APE_PER_LOCK_REQ;
616                 gnt = TG3_APE_PER_LOCK_GRANT;
617         }
618
619         off = 4 * locknum;
620
621         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
622
623         /* Wait for up to 1 millisecond to acquire lock. */
624         for (i = 0; i < 100; i++) {
625                 status = tg3_ape_read32(tp, gnt + off);
626                 if (status == APE_LOCK_GRANT_DRIVER)
627                         break;
628                 udelay(10);
629         }
630
631         if (status != APE_LOCK_GRANT_DRIVER) {
632                 /* Revoke the lock request. */
633                 tg3_ape_write32(tp, gnt + off,
634                                 APE_LOCK_GRANT_DRIVER);
635
636                 ret = -EBUSY;
637         }
638
639         return ret;
640 }
641
642 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
643 {
644         u32 gnt;
645
646         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
647                 return;
648
649         switch (locknum) {
650         case TG3_APE_LOCK_GRC:
651         case TG3_APE_LOCK_MEM:
652                 break;
653         default:
654                 return;
655         }
656
657         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
658                 gnt = TG3_APE_LOCK_GRANT;
659         else
660                 gnt = TG3_APE_PER_LOCK_GRANT;
661
662         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
663 }
664
665 static void tg3_disable_ints(struct tg3 *tp)
666 {
667         int i;
668
669         tw32(TG3PCI_MISC_HOST_CTRL,
670              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
671         for (i = 0; i < tp->irq_max; i++)
672                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
673 }
674
675 static void tg3_enable_ints(struct tg3 *tp)
676 {
677         int i;
678
679         tp->irq_sync = 0;
680         wmb();
681
682         tw32(TG3PCI_MISC_HOST_CTRL,
683              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
684
685         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
686         for (i = 0; i < tp->irq_cnt; i++) {
687                 struct tg3_napi *tnapi = &tp->napi[i];
688
689                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
690                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
691                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
692
693                 tp->coal_now |= tnapi->coal_now;
694         }
695
696         /* Force an initial interrupt */
697         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
698             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
699                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
700         else
701                 tw32(HOSTCC_MODE, tp->coal_now);
702
703         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
704 }
705
706 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
707 {
708         struct tg3 *tp = tnapi->tp;
709         struct tg3_hw_status *sblk = tnapi->hw_status;
710         unsigned int work_exists = 0;
711
712         /* check for phy events */
713         if (!(tp->tg3_flags &
714               (TG3_FLAG_USE_LINKCHG_REG |
715                TG3_FLAG_POLL_SERDES))) {
716                 if (sblk->status & SD_STATUS_LINK_CHG)
717                         work_exists = 1;
718         }
719         /* check for RX/TX work to do */
720         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
721             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
722                 work_exists = 1;
723
724         return work_exists;
725 }
726
727 /* tg3_int_reenable
728  *  similar to tg3_enable_ints, but it accurately determines whether there
729  *  is new work pending and can return without flushing the PIO write
730  *  which reenables interrupts
731  */
732 static void tg3_int_reenable(struct tg3_napi *tnapi)
733 {
734         struct tg3 *tp = tnapi->tp;
735
736         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
737         mmiowb();
738
739         /* When doing tagged status, this work check is unnecessary.
740          * The last_tag we write above tells the chip which piece of
741          * work we've completed.
742          */
743         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
744             tg3_has_work(tnapi))
745                 tw32(HOSTCC_MODE, tp->coalesce_mode |
746                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
747 }
748
749 static void tg3_switch_clocks(struct tg3 *tp)
750 {
751         u32 clock_ctrl;
752         u32 orig_clock_ctrl;
753
754         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
755             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
756                 return;
757
758         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
759
760         orig_clock_ctrl = clock_ctrl;
761         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
762                        CLOCK_CTRL_CLKRUN_OENABLE |
763                        0x1f);
764         tp->pci_clock_ctrl = clock_ctrl;
765
766         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
767                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
768                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
769                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
770                 }
771         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
772                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
773                             clock_ctrl |
774                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
775                             40);
776                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
777                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
778                             40);
779         }
780         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
781 }
782
783 #define PHY_BUSY_LOOPS  5000
784
785 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
786 {
787         u32 frame_val;
788         unsigned int loops;
789         int ret;
790
791         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
792                 tw32_f(MAC_MI_MODE,
793                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
794                 udelay(80);
795         }
796
797         *val = 0x0;
798
799         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
800                       MI_COM_PHY_ADDR_MASK);
801         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
802                       MI_COM_REG_ADDR_MASK);
803         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
804
805         tw32_f(MAC_MI_COM, frame_val);
806
807         loops = PHY_BUSY_LOOPS;
808         while (loops != 0) {
809                 udelay(10);
810                 frame_val = tr32(MAC_MI_COM);
811
812                 if ((frame_val & MI_COM_BUSY) == 0) {
813                         udelay(5);
814                         frame_val = tr32(MAC_MI_COM);
815                         break;
816                 }
817                 loops -= 1;
818         }
819
820         ret = -EBUSY;
821         if (loops != 0) {
822                 *val = frame_val & MI_COM_DATA_MASK;
823                 ret = 0;
824         }
825
826         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
827                 tw32_f(MAC_MI_MODE, tp->mi_mode);
828                 udelay(80);
829         }
830
831         return ret;
832 }
833
834 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
835 {
836         u32 frame_val;
837         unsigned int loops;
838         int ret;
839
840         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
841             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
842                 return 0;
843
844         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
845                 tw32_f(MAC_MI_MODE,
846                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
847                 udelay(80);
848         }
849
850         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
851                       MI_COM_PHY_ADDR_MASK);
852         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
853                       MI_COM_REG_ADDR_MASK);
854         frame_val |= (val & MI_COM_DATA_MASK);
855         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
856
857         tw32_f(MAC_MI_COM, frame_val);
858
859         loops = PHY_BUSY_LOOPS;
860         while (loops != 0) {
861                 udelay(10);
862                 frame_val = tr32(MAC_MI_COM);
863                 if ((frame_val & MI_COM_BUSY) == 0) {
864                         udelay(5);
865                         frame_val = tr32(MAC_MI_COM);
866                         break;
867                 }
868                 loops -= 1;
869         }
870
871         ret = -EBUSY;
872         if (loops != 0)
873                 ret = 0;
874
875         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
876                 tw32_f(MAC_MI_MODE, tp->mi_mode);
877                 udelay(80);
878         }
879
880         return ret;
881 }
882
883 static int tg3_bmcr_reset(struct tg3 *tp)
884 {
885         u32 phy_control;
886         int limit, err;
887
888         /* OK, reset it, and poll the BMCR_RESET bit until it
889          * clears or we time out.
890          */
891         phy_control = BMCR_RESET;
892         err = tg3_writephy(tp, MII_BMCR, phy_control);
893         if (err != 0)
894                 return -EBUSY;
895
896         limit = 5000;
897         while (limit--) {
898                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
899                 if (err != 0)
900                         return -EBUSY;
901
902                 if ((phy_control & BMCR_RESET) == 0) {
903                         udelay(40);
904                         break;
905                 }
906                 udelay(10);
907         }
908         if (limit < 0)
909                 return -EBUSY;
910
911         return 0;
912 }
913
914 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
915 {
916         struct tg3 *tp = bp->priv;
917         u32 val;
918
919         spin_lock_bh(&tp->lock);
920
921         if (tg3_readphy(tp, reg, &val))
922                 val = -EIO;
923
924         spin_unlock_bh(&tp->lock);
925
926         return val;
927 }
928
929 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
930 {
931         struct tg3 *tp = bp->priv;
932         u32 ret = 0;
933
934         spin_lock_bh(&tp->lock);
935
936         if (tg3_writephy(tp, reg, val))
937                 ret = -EIO;
938
939         spin_unlock_bh(&tp->lock);
940
941         return ret;
942 }
943
944 static int tg3_mdio_reset(struct mii_bus *bp)
945 {
946         return 0;
947 }
948
949 static void tg3_mdio_config_5785(struct tg3 *tp)
950 {
951         u32 val;
952         struct phy_device *phydev;
953
954         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
955         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
956         case PHY_ID_BCM50610:
957         case PHY_ID_BCM50610M:
958                 val = MAC_PHYCFG2_50610_LED_MODES;
959                 break;
960         case PHY_ID_BCMAC131:
961                 val = MAC_PHYCFG2_AC131_LED_MODES;
962                 break;
963         case PHY_ID_RTL8211C:
964                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
965                 break;
966         case PHY_ID_RTL8201E:
967                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
968                 break;
969         default:
970                 return;
971         }
972
973         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
974                 tw32(MAC_PHYCFG2, val);
975
976                 val = tr32(MAC_PHYCFG1);
977                 val &= ~(MAC_PHYCFG1_RGMII_INT |
978                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
979                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
980                 tw32(MAC_PHYCFG1, val);
981
982                 return;
983         }
984
985         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
986                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
987                        MAC_PHYCFG2_FMODE_MASK_MASK |
988                        MAC_PHYCFG2_GMODE_MASK_MASK |
989                        MAC_PHYCFG2_ACT_MASK_MASK   |
990                        MAC_PHYCFG2_QUAL_MASK_MASK |
991                        MAC_PHYCFG2_INBAND_ENABLE;
992
993         tw32(MAC_PHYCFG2, val);
994
995         val = tr32(MAC_PHYCFG1);
996         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
997                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
998         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
999                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1000                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1001                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1002                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1003         }
1004         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1005                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1006         tw32(MAC_PHYCFG1, val);
1007
1008         val = tr32(MAC_EXT_RGMII_MODE);
1009         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1010                  MAC_RGMII_MODE_RX_QUALITY |
1011                  MAC_RGMII_MODE_RX_ACTIVITY |
1012                  MAC_RGMII_MODE_RX_ENG_DET |
1013                  MAC_RGMII_MODE_TX_ENABLE |
1014                  MAC_RGMII_MODE_TX_LOWPWR |
1015                  MAC_RGMII_MODE_TX_RESET);
1016         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1017                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1018                         val |= MAC_RGMII_MODE_RX_INT_B |
1019                                MAC_RGMII_MODE_RX_QUALITY |
1020                                MAC_RGMII_MODE_RX_ACTIVITY |
1021                                MAC_RGMII_MODE_RX_ENG_DET;
1022                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1023                         val |= MAC_RGMII_MODE_TX_ENABLE |
1024                                MAC_RGMII_MODE_TX_LOWPWR |
1025                                MAC_RGMII_MODE_TX_RESET;
1026         }
1027         tw32(MAC_EXT_RGMII_MODE, val);
1028 }
1029
1030 static void tg3_mdio_start(struct tg3 *tp)
1031 {
1032         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1033         tw32_f(MAC_MI_MODE, tp->mi_mode);
1034         udelay(80);
1035
1036         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1037             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1038                 tg3_mdio_config_5785(tp);
1039 }
1040
1041 static int tg3_mdio_init(struct tg3 *tp)
1042 {
1043         int i;
1044         u32 reg;
1045         struct phy_device *phydev;
1046
1047         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1048             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
1049                 u32 is_serdes;
1050
1051                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1052
1053                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1054                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1055                 else
1056                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1057                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1058                 if (is_serdes)
1059                         tp->phy_addr += 7;
1060         } else
1061                 tp->phy_addr = TG3_PHY_MII_ADDR;
1062
1063         tg3_mdio_start(tp);
1064
1065         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1066             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1067                 return 0;
1068
1069         tp->mdio_bus = mdiobus_alloc();
1070         if (tp->mdio_bus == NULL)
1071                 return -ENOMEM;
1072
1073         tp->mdio_bus->name     = "tg3 mdio bus";
1074         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1075                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1076         tp->mdio_bus->priv     = tp;
1077         tp->mdio_bus->parent   = &tp->pdev->dev;
1078         tp->mdio_bus->read     = &tg3_mdio_read;
1079         tp->mdio_bus->write    = &tg3_mdio_write;
1080         tp->mdio_bus->reset    = &tg3_mdio_reset;
1081         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1082         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1083
1084         for (i = 0; i < PHY_MAX_ADDR; i++)
1085                 tp->mdio_bus->irq[i] = PHY_POLL;
1086
1087         /* The bus registration will look for all the PHYs on the mdio bus.
1088          * Unfortunately, it does not ensure the PHY is powered up before
1089          * accessing the PHY ID registers.  A chip reset is the
1090          * quickest way to bring the device back to an operational state..
1091          */
1092         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1093                 tg3_bmcr_reset(tp);
1094
1095         i = mdiobus_register(tp->mdio_bus);
1096         if (i) {
1097                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1098                 mdiobus_free(tp->mdio_bus);
1099                 return i;
1100         }
1101
1102         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1103
1104         if (!phydev || !phydev->drv) {
1105                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1106                 mdiobus_unregister(tp->mdio_bus);
1107                 mdiobus_free(tp->mdio_bus);
1108                 return -ENODEV;
1109         }
1110
1111         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1112         case PHY_ID_BCM57780:
1113                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1114                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1115                 break;
1116         case PHY_ID_BCM50610:
1117         case PHY_ID_BCM50610M:
1118                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1119                                      PHY_BRCM_RX_REFCLK_UNUSED |
1120                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1121                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1122                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1123                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1124                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1125                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1126                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1127                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1128                 /* fallthru */
1129         case PHY_ID_RTL8211C:
1130                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1131                 break;
1132         case PHY_ID_RTL8201E:
1133         case PHY_ID_BCMAC131:
1134                 phydev->interface = PHY_INTERFACE_MODE_MII;
1135                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1136                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1137                 break;
1138         }
1139
1140         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1141
1142         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1143                 tg3_mdio_config_5785(tp);
1144
1145         return 0;
1146 }
1147
1148 static void tg3_mdio_fini(struct tg3 *tp)
1149 {
1150         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1151                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1152                 mdiobus_unregister(tp->mdio_bus);
1153                 mdiobus_free(tp->mdio_bus);
1154         }
1155 }
1156
1157 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1158 {
1159         int err;
1160
1161         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1162         if (err)
1163                 goto done;
1164
1165         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1166         if (err)
1167                 goto done;
1168
1169         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1170                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1171         if (err)
1172                 goto done;
1173
1174         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1175
1176 done:
1177         return err;
1178 }
1179
1180 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1181 {
1182         int err;
1183
1184         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1185         if (err)
1186                 goto done;
1187
1188         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1189         if (err)
1190                 goto done;
1191
1192         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1193                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1194         if (err)
1195                 goto done;
1196
1197         err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1198
1199 done:
1200         return err;
1201 }
1202
1203 /* tp->lock is held. */
1204 static inline void tg3_generate_fw_event(struct tg3 *tp)
1205 {
1206         u32 val;
1207
1208         val = tr32(GRC_RX_CPU_EVENT);
1209         val |= GRC_RX_CPU_DRIVER_EVENT;
1210         tw32_f(GRC_RX_CPU_EVENT, val);
1211
1212         tp->last_event_jiffies = jiffies;
1213 }
1214
1215 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1216
1217 /* tp->lock is held. */
1218 static void tg3_wait_for_event_ack(struct tg3 *tp)
1219 {
1220         int i;
1221         unsigned int delay_cnt;
1222         long time_remain;
1223
1224         /* If enough time has passed, no wait is necessary. */
1225         time_remain = (long)(tp->last_event_jiffies + 1 +
1226                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1227                       (long)jiffies;
1228         if (time_remain < 0)
1229                 return;
1230
1231         /* Check if we can shorten the wait time. */
1232         delay_cnt = jiffies_to_usecs(time_remain);
1233         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1234                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1235         delay_cnt = (delay_cnt >> 3) + 1;
1236
1237         for (i = 0; i < delay_cnt; i++) {
1238                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1239                         break;
1240                 udelay(8);
1241         }
1242 }
1243
1244 /* tp->lock is held. */
1245 static void tg3_ump_link_report(struct tg3 *tp)
1246 {
1247         u32 reg;
1248         u32 val;
1249
1250         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1251             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1252                 return;
1253
1254         tg3_wait_for_event_ack(tp);
1255
1256         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1257
1258         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1259
1260         val = 0;
1261         if (!tg3_readphy(tp, MII_BMCR, &reg))
1262                 val = reg << 16;
1263         if (!tg3_readphy(tp, MII_BMSR, &reg))
1264                 val |= (reg & 0xffff);
1265         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1266
1267         val = 0;
1268         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1269                 val = reg << 16;
1270         if (!tg3_readphy(tp, MII_LPA, &reg))
1271                 val |= (reg & 0xffff);
1272         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1273
1274         val = 0;
1275         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1276                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1277                         val = reg << 16;
1278                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1279                         val |= (reg & 0xffff);
1280         }
1281         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1282
1283         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1284                 val = reg << 16;
1285         else
1286                 val = 0;
1287         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1288
1289         tg3_generate_fw_event(tp);
1290 }
1291
1292 static void tg3_link_report(struct tg3 *tp)
1293 {
1294         if (!netif_carrier_ok(tp->dev)) {
1295                 netif_info(tp, link, tp->dev, "Link is down\n");
1296                 tg3_ump_link_report(tp);
1297         } else if (netif_msg_link(tp)) {
1298                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1299                             (tp->link_config.active_speed == SPEED_1000 ?
1300                              1000 :
1301                              (tp->link_config.active_speed == SPEED_100 ?
1302                               100 : 10)),
1303                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1304                              "full" : "half"));
1305
1306                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1307                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1308                             "on" : "off",
1309                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1310                             "on" : "off");
1311                 tg3_ump_link_report(tp);
1312         }
1313 }
1314
1315 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1316 {
1317         u16 miireg;
1318
1319         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1320                 miireg = ADVERTISE_PAUSE_CAP;
1321         else if (flow_ctrl & FLOW_CTRL_TX)
1322                 miireg = ADVERTISE_PAUSE_ASYM;
1323         else if (flow_ctrl & FLOW_CTRL_RX)
1324                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1325         else
1326                 miireg = 0;
1327
1328         return miireg;
1329 }
1330
1331 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1332 {
1333         u16 miireg;
1334
1335         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1336                 miireg = ADVERTISE_1000XPAUSE;
1337         else if (flow_ctrl & FLOW_CTRL_TX)
1338                 miireg = ADVERTISE_1000XPSE_ASYM;
1339         else if (flow_ctrl & FLOW_CTRL_RX)
1340                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1341         else
1342                 miireg = 0;
1343
1344         return miireg;
1345 }
1346
1347 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1348 {
1349         u8 cap = 0;
1350
1351         if (lcladv & ADVERTISE_1000XPAUSE) {
1352                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1353                         if (rmtadv & LPA_1000XPAUSE)
1354                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1355                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1356                                 cap = FLOW_CTRL_RX;
1357                 } else {
1358                         if (rmtadv & LPA_1000XPAUSE)
1359                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1360                 }
1361         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1362                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1363                         cap = FLOW_CTRL_TX;
1364         }
1365
1366         return cap;
1367 }
1368
1369 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1370 {
1371         u8 autoneg;
1372         u8 flowctrl = 0;
1373         u32 old_rx_mode = tp->rx_mode;
1374         u32 old_tx_mode = tp->tx_mode;
1375
1376         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1377                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1378         else
1379                 autoneg = tp->link_config.autoneg;
1380
1381         if (autoneg == AUTONEG_ENABLE &&
1382             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1383                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1384                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1385                 else
1386                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1387         } else
1388                 flowctrl = tp->link_config.flowctrl;
1389
1390         tp->link_config.active_flowctrl = flowctrl;
1391
1392         if (flowctrl & FLOW_CTRL_RX)
1393                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1394         else
1395                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1396
1397         if (old_rx_mode != tp->rx_mode)
1398                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1399
1400         if (flowctrl & FLOW_CTRL_TX)
1401                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1402         else
1403                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1404
1405         if (old_tx_mode != tp->tx_mode)
1406                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1407 }
1408
1409 static void tg3_adjust_link(struct net_device *dev)
1410 {
1411         u8 oldflowctrl, linkmesg = 0;
1412         u32 mac_mode, lcl_adv, rmt_adv;
1413         struct tg3 *tp = netdev_priv(dev);
1414         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1415
1416         spin_lock_bh(&tp->lock);
1417
1418         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1419                                     MAC_MODE_HALF_DUPLEX);
1420
1421         oldflowctrl = tp->link_config.active_flowctrl;
1422
1423         if (phydev->link) {
1424                 lcl_adv = 0;
1425                 rmt_adv = 0;
1426
1427                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1428                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1429                 else if (phydev->speed == SPEED_1000 ||
1430                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1431                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1432                 else
1433                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1434
1435                 if (phydev->duplex == DUPLEX_HALF)
1436                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1437                 else {
1438                         lcl_adv = tg3_advert_flowctrl_1000T(
1439                                   tp->link_config.flowctrl);
1440
1441                         if (phydev->pause)
1442                                 rmt_adv = LPA_PAUSE_CAP;
1443                         if (phydev->asym_pause)
1444                                 rmt_adv |= LPA_PAUSE_ASYM;
1445                 }
1446
1447                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1448         } else
1449                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1450
1451         if (mac_mode != tp->mac_mode) {
1452                 tp->mac_mode = mac_mode;
1453                 tw32_f(MAC_MODE, tp->mac_mode);
1454                 udelay(40);
1455         }
1456
1457         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1458                 if (phydev->speed == SPEED_10)
1459                         tw32(MAC_MI_STAT,
1460                              MAC_MI_STAT_10MBPS_MODE |
1461                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1462                 else
1463                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1464         }
1465
1466         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1467                 tw32(MAC_TX_LENGTHS,
1468                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1469                       (6 << TX_LENGTHS_IPG_SHIFT) |
1470                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1471         else
1472                 tw32(MAC_TX_LENGTHS,
1473                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1474                       (6 << TX_LENGTHS_IPG_SHIFT) |
1475                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1476
1477         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1478             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1479             phydev->speed != tp->link_config.active_speed ||
1480             phydev->duplex != tp->link_config.active_duplex ||
1481             oldflowctrl != tp->link_config.active_flowctrl)
1482                 linkmesg = 1;
1483
1484         tp->link_config.active_speed = phydev->speed;
1485         tp->link_config.active_duplex = phydev->duplex;
1486
1487         spin_unlock_bh(&tp->lock);
1488
1489         if (linkmesg)
1490                 tg3_link_report(tp);
1491 }
1492
1493 static int tg3_phy_init(struct tg3 *tp)
1494 {
1495         struct phy_device *phydev;
1496
1497         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1498                 return 0;
1499
1500         /* Bring the PHY back to a known state. */
1501         tg3_bmcr_reset(tp);
1502
1503         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1504
1505         /* Attach the MAC to the PHY. */
1506         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1507                              phydev->dev_flags, phydev->interface);
1508         if (IS_ERR(phydev)) {
1509                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1510                 return PTR_ERR(phydev);
1511         }
1512
1513         /* Mask with MAC supported features. */
1514         switch (phydev->interface) {
1515         case PHY_INTERFACE_MODE_GMII:
1516         case PHY_INTERFACE_MODE_RGMII:
1517                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1518                         phydev->supported &= (PHY_GBIT_FEATURES |
1519                                               SUPPORTED_Pause |
1520                                               SUPPORTED_Asym_Pause);
1521                         break;
1522                 }
1523                 /* fallthru */
1524         case PHY_INTERFACE_MODE_MII:
1525                 phydev->supported &= (PHY_BASIC_FEATURES |
1526                                       SUPPORTED_Pause |
1527                                       SUPPORTED_Asym_Pause);
1528                 break;
1529         default:
1530                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1531                 return -EINVAL;
1532         }
1533
1534         tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1535
1536         phydev->advertising = phydev->supported;
1537
1538         return 0;
1539 }
1540
1541 static void tg3_phy_start(struct tg3 *tp)
1542 {
1543         struct phy_device *phydev;
1544
1545         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1546                 return;
1547
1548         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1549
1550         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1551                 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1552                 phydev->speed = tp->link_config.orig_speed;
1553                 phydev->duplex = tp->link_config.orig_duplex;
1554                 phydev->autoneg = tp->link_config.orig_autoneg;
1555                 phydev->advertising = tp->link_config.orig_advertising;
1556         }
1557
1558         phy_start(phydev);
1559
1560         phy_start_aneg(phydev);
1561 }
1562
1563 static void tg3_phy_stop(struct tg3 *tp)
1564 {
1565         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1566                 return;
1567
1568         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1569 }
1570
1571 static void tg3_phy_fini(struct tg3 *tp)
1572 {
1573         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1574                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1575                 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1576         }
1577 }
1578
1579 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1580 {
1581         int err;
1582
1583         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1584         if (!err)
1585                 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1586
1587         return err;
1588 }
1589
1590 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1591 {
1592         int err;
1593
1594         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1595         if (!err)
1596                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1597
1598         return err;
1599 }
1600
1601 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1602 {
1603         u32 phytest;
1604
1605         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1606                 u32 phy;
1607
1608                 tg3_writephy(tp, MII_TG3_FET_TEST,
1609                              phytest | MII_TG3_FET_SHADOW_EN);
1610                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1611                         if (enable)
1612                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1613                         else
1614                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1615                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1616                 }
1617                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1618         }
1619 }
1620
1621 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1622 {
1623         u32 reg;
1624
1625         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1626             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1627               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1628              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1629                 return;
1630
1631         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1632                 tg3_phy_fet_toggle_apd(tp, enable);
1633                 return;
1634         }
1635
1636         reg = MII_TG3_MISC_SHDW_WREN |
1637               MII_TG3_MISC_SHDW_SCR5_SEL |
1638               MII_TG3_MISC_SHDW_SCR5_LPED |
1639               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1640               MII_TG3_MISC_SHDW_SCR5_SDTL |
1641               MII_TG3_MISC_SHDW_SCR5_C125OE;
1642         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1643                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1644
1645         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1646
1647
1648         reg = MII_TG3_MISC_SHDW_WREN |
1649               MII_TG3_MISC_SHDW_APD_SEL |
1650               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1651         if (enable)
1652                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1653
1654         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1655 }
1656
1657 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1658 {
1659         u32 phy;
1660
1661         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1662             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1663                 return;
1664
1665         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1666                 u32 ephy;
1667
1668                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1669                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1670
1671                         tg3_writephy(tp, MII_TG3_FET_TEST,
1672                                      ephy | MII_TG3_FET_SHADOW_EN);
1673                         if (!tg3_readphy(tp, reg, &phy)) {
1674                                 if (enable)
1675                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1676                                 else
1677                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1678                                 tg3_writephy(tp, reg, phy);
1679                         }
1680                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1681                 }
1682         } else {
1683                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1684                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1685                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1686                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1687                         if (enable)
1688                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1689                         else
1690                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1691                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1692                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1693                 }
1694         }
1695 }
1696
1697 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1698 {
1699         u32 val;
1700
1701         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1702                 return;
1703
1704         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1705             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1706                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1707                              (val | (1 << 15) | (1 << 4)));
1708 }
1709
1710 static void tg3_phy_apply_otp(struct tg3 *tp)
1711 {
1712         u32 otp, phy;
1713
1714         if (!tp->phy_otp)
1715                 return;
1716
1717         otp = tp->phy_otp;
1718
1719         /* Enable SM_DSP clock and tx 6dB coding. */
1720         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1721               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1722               MII_TG3_AUXCTL_ACTL_TX_6DB;
1723         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1724
1725         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1726         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1727         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1728
1729         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1730               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1731         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1732
1733         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1734         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1735         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1736
1737         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1738         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1739
1740         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1741         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1742
1743         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1744               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1745         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1746
1747         /* Turn off SM_DSP clock. */
1748         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1749               MII_TG3_AUXCTL_ACTL_TX_6DB;
1750         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1751 }
1752
1753 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
1754 {
1755         u32 val;
1756
1757         if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
1758                 return;
1759
1760         tp->setlpicnt = 0;
1761
1762         if (tp->link_config.autoneg == AUTONEG_ENABLE &&
1763             current_link_up == 1 &&
1764             tp->link_config.active_duplex == DUPLEX_FULL &&
1765             (tp->link_config.active_speed == SPEED_100 ||
1766              tp->link_config.active_speed == SPEED_1000)) {
1767                 u32 eeectl;
1768
1769                 if (tp->link_config.active_speed == SPEED_1000)
1770                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
1771                 else
1772                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
1773
1774                 tw32(TG3_CPMU_EEE_CTRL, eeectl);
1775
1776                 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
1777                                   TG3_CL45_D7_EEERES_STAT, &val);
1778
1779                 switch (val) {
1780                 case TG3_CL45_D7_EEERES_STAT_LP_1000T:
1781                         switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
1782                         case ASIC_REV_5717:
1783                         case ASIC_REV_5719:
1784                         case ASIC_REV_57765:
1785                                 /* Enable SM_DSP clock and tx 6dB coding. */
1786                                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1787                                       MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1788                                       MII_TG3_AUXCTL_ACTL_TX_6DB;
1789                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1790
1791                                 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
1792
1793                                 /* Turn off SM_DSP clock. */
1794                                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1795                                       MII_TG3_AUXCTL_ACTL_TX_6DB;
1796                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1797                         }
1798                         /* Fallthrough */
1799                 case TG3_CL45_D7_EEERES_STAT_LP_100TX:
1800                         tp->setlpicnt = 2;
1801                 }
1802         }
1803
1804         if (!tp->setlpicnt) {
1805                 val = tr32(TG3_CPMU_EEE_MODE);
1806                 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
1807         }
1808 }
1809
1810 static int tg3_wait_macro_done(struct tg3 *tp)
1811 {
1812         int limit = 100;
1813
1814         while (limit--) {
1815                 u32 tmp32;
1816
1817                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1818                         if ((tmp32 & 0x1000) == 0)
1819                                 break;
1820                 }
1821         }
1822         if (limit < 0)
1823                 return -EBUSY;
1824
1825         return 0;
1826 }
1827
1828 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1829 {
1830         static const u32 test_pat[4][6] = {
1831         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1832         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1833         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1834         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1835         };
1836         int chan;
1837
1838         for (chan = 0; chan < 4; chan++) {
1839                 int i;
1840
1841                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1842                              (chan * 0x2000) | 0x0200);
1843                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1844
1845                 for (i = 0; i < 6; i++)
1846                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1847                                      test_pat[chan][i]);
1848
1849                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1850                 if (tg3_wait_macro_done(tp)) {
1851                         *resetp = 1;
1852                         return -EBUSY;
1853                 }
1854
1855                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1856                              (chan * 0x2000) | 0x0200);
1857                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1858                 if (tg3_wait_macro_done(tp)) {
1859                         *resetp = 1;
1860                         return -EBUSY;
1861                 }
1862
1863                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1864                 if (tg3_wait_macro_done(tp)) {
1865                         *resetp = 1;
1866                         return -EBUSY;
1867                 }
1868
1869                 for (i = 0; i < 6; i += 2) {
1870                         u32 low, high;
1871
1872                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1873                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1874                             tg3_wait_macro_done(tp)) {
1875                                 *resetp = 1;
1876                                 return -EBUSY;
1877                         }
1878                         low &= 0x7fff;
1879                         high &= 0x000f;
1880                         if (low != test_pat[chan][i] ||
1881                             high != test_pat[chan][i+1]) {
1882                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1883                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1884                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1885
1886                                 return -EBUSY;
1887                         }
1888                 }
1889         }
1890
1891         return 0;
1892 }
1893
1894 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1895 {
1896         int chan;
1897
1898         for (chan = 0; chan < 4; chan++) {
1899                 int i;
1900
1901                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1902                              (chan * 0x2000) | 0x0200);
1903                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1904                 for (i = 0; i < 6; i++)
1905                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1906                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1907                 if (tg3_wait_macro_done(tp))
1908                         return -EBUSY;
1909         }
1910
1911         return 0;
1912 }
1913
1914 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1915 {
1916         u32 reg32, phy9_orig;
1917         int retries, do_phy_reset, err;
1918
1919         retries = 10;
1920         do_phy_reset = 1;
1921         do {
1922                 if (do_phy_reset) {
1923                         err = tg3_bmcr_reset(tp);
1924                         if (err)
1925                                 return err;
1926                         do_phy_reset = 0;
1927                 }
1928
1929                 /* Disable transmitter and interrupt.  */
1930                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1931                         continue;
1932
1933                 reg32 |= 0x3000;
1934                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1935
1936                 /* Set full-duplex, 1000 mbps.  */
1937                 tg3_writephy(tp, MII_BMCR,
1938                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1939
1940                 /* Set to master mode.  */
1941                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1942                         continue;
1943
1944                 tg3_writephy(tp, MII_TG3_CTRL,
1945                              (MII_TG3_CTRL_AS_MASTER |
1946                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1947
1948                 /* Enable SM_DSP_CLOCK and 6dB.  */
1949                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1950
1951                 /* Block the PHY control access.  */
1952                 tg3_phydsp_write(tp, 0x8005, 0x0800);
1953
1954                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1955                 if (!err)
1956                         break;
1957         } while (--retries);
1958
1959         err = tg3_phy_reset_chanpat(tp);
1960         if (err)
1961                 return err;
1962
1963         tg3_phydsp_write(tp, 0x8005, 0x0000);
1964
1965         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1966         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1967
1968         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1969             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1970                 /* Set Extended packet length bit for jumbo frames */
1971                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1972         } else {
1973                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1974         }
1975
1976         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1977
1978         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1979                 reg32 &= ~0x3000;
1980                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1981         } else if (!err)
1982                 err = -EBUSY;
1983
1984         return err;
1985 }
1986
1987 /* This will reset the tigon3 PHY if there is no valid
1988  * link unless the FORCE argument is non-zero.
1989  */
1990 static int tg3_phy_reset(struct tg3 *tp)
1991 {
1992         u32 val, cpmuctrl;
1993         int err;
1994
1995         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1996                 val = tr32(GRC_MISC_CFG);
1997                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1998                 udelay(40);
1999         }
2000         err  = tg3_readphy(tp, MII_BMSR, &val);
2001         err |= tg3_readphy(tp, MII_BMSR, &val);
2002         if (err != 0)
2003                 return -EBUSY;
2004
2005         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
2006                 netif_carrier_off(tp->dev);
2007                 tg3_link_report(tp);
2008         }
2009
2010         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2011             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2012             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2013                 err = tg3_phy_reset_5703_4_5(tp);
2014                 if (err)
2015                         return err;
2016                 goto out;
2017         }
2018
2019         cpmuctrl = 0;
2020         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2021             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2022                 cpmuctrl = tr32(TG3_CPMU_CTRL);
2023                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2024                         tw32(TG3_CPMU_CTRL,
2025                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2026         }
2027
2028         err = tg3_bmcr_reset(tp);
2029         if (err)
2030                 return err;
2031
2032         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2033                 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2034                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2035
2036                 tw32(TG3_CPMU_CTRL, cpmuctrl);
2037         }
2038
2039         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2040             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2041                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2042                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2043                     CPMU_LSPD_1000MB_MACCLK_12_5) {
2044                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2045                         udelay(40);
2046                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2047                 }
2048         }
2049
2050         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2051              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
2052             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2053                 return 0;
2054
2055         tg3_phy_apply_otp(tp);
2056
2057         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2058                 tg3_phy_toggle_apd(tp, true);
2059         else
2060                 tg3_phy_toggle_apd(tp, false);
2061
2062 out:
2063         if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
2064                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2065                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2066                 tg3_phydsp_write(tp, 0x000a, 0x0323);
2067                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2068         }
2069         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2070                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2071                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2072         }
2073         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2074                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2075                 tg3_phydsp_write(tp, 0x000a, 0x310b);
2076                 tg3_phydsp_write(tp, 0x201f, 0x9506);
2077                 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2078                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2079         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2080                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2081                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2082                 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2083                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2084                         tg3_writephy(tp, MII_TG3_TEST1,
2085                                      MII_TG3_TEST1_TRIM_EN | 0x4);
2086                 } else
2087                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2088                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2089         }
2090         /* Set Extended packet length bit (bit 14) on all chips that */
2091         /* support jumbo frames */
2092         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2093                 /* Cannot do read-modify-write on 5401 */
2094                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2095         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2096                 /* Set bit 14 with read-modify-write to preserve other bits */
2097                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2098                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
2099                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000);
2100         }
2101
2102         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2103          * jumbo frames transmission.
2104          */
2105         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2106                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2107                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2108                                      val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2109         }
2110
2111         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2112                 /* adjust output voltage */
2113                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2114         }
2115
2116         tg3_phy_toggle_automdix(tp, 1);
2117         tg3_phy_set_wirespeed(tp);
2118         return 0;
2119 }
2120
2121 static void tg3_frob_aux_power(struct tg3 *tp)
2122 {
2123         struct tg3 *tp_peer = tp;
2124
2125         /* The GPIOs do something completely different on 57765. */
2126         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2127             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2128             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2129                 return;
2130
2131         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2132             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2133             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2134                 struct net_device *dev_peer;
2135
2136                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2137                 /* remove_one() may have been run on the peer. */
2138                 if (!dev_peer)
2139                         tp_peer = tp;
2140                 else
2141                         tp_peer = netdev_priv(dev_peer);
2142         }
2143
2144         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2145             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2146             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2147             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2148                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2149                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2150                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2151                                     (GRC_LCLCTRL_GPIO_OE0 |
2152                                      GRC_LCLCTRL_GPIO_OE1 |
2153                                      GRC_LCLCTRL_GPIO_OE2 |
2154                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2155                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2156                                     100);
2157                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2158                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2159                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2160                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2161                                              GRC_LCLCTRL_GPIO_OE1 |
2162                                              GRC_LCLCTRL_GPIO_OE2 |
2163                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2164                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2165                                              tp->grc_local_ctrl;
2166                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2167
2168                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2169                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2170
2171                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2172                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2173                 } else {
2174                         u32 no_gpio2;
2175                         u32 grc_local_ctrl = 0;
2176
2177                         if (tp_peer != tp &&
2178                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2179                                 return;
2180
2181                         /* Workaround to prevent overdrawing Amps. */
2182                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2183                             ASIC_REV_5714) {
2184                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2185                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2186                                             grc_local_ctrl, 100);
2187                         }
2188
2189                         /* On 5753 and variants, GPIO2 cannot be used. */
2190                         no_gpio2 = tp->nic_sram_data_cfg &
2191                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2192
2193                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2194                                          GRC_LCLCTRL_GPIO_OE1 |
2195                                          GRC_LCLCTRL_GPIO_OE2 |
2196                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2197                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2198                         if (no_gpio2) {
2199                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2200                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2201                         }
2202                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2203                                                     grc_local_ctrl, 100);
2204
2205                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2206
2207                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2208                                                     grc_local_ctrl, 100);
2209
2210                         if (!no_gpio2) {
2211                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2212                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2213                                             grc_local_ctrl, 100);
2214                         }
2215                 }
2216         } else {
2217                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2218                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2219                         if (tp_peer != tp &&
2220                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2221                                 return;
2222
2223                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2224                                     (GRC_LCLCTRL_GPIO_OE1 |
2225                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2226
2227                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2228                                     GRC_LCLCTRL_GPIO_OE1, 100);
2229
2230                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2231                                     (GRC_LCLCTRL_GPIO_OE1 |
2232                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2233                 }
2234         }
2235 }
2236
2237 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2238 {
2239         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2240                 return 1;
2241         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2242                 if (speed != SPEED_10)
2243                         return 1;
2244         } else if (speed == SPEED_10)
2245                 return 1;
2246
2247         return 0;
2248 }
2249
2250 static int tg3_setup_phy(struct tg3 *, int);
2251
2252 #define RESET_KIND_SHUTDOWN     0
2253 #define RESET_KIND_INIT         1
2254 #define RESET_KIND_SUSPEND      2
2255
2256 static void tg3_write_sig_post_reset(struct tg3 *, int);
2257 static int tg3_halt_cpu(struct tg3 *, u32);
2258
2259 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2260 {
2261         u32 val;
2262
2263         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2264                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2265                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2266                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2267
2268                         sg_dig_ctrl |=
2269                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2270                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2271                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2272                 }
2273                 return;
2274         }
2275
2276         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2277                 tg3_bmcr_reset(tp);
2278                 val = tr32(GRC_MISC_CFG);
2279                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2280                 udelay(40);
2281                 return;
2282         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2283                 u32 phytest;
2284                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2285                         u32 phy;
2286
2287                         tg3_writephy(tp, MII_ADVERTISE, 0);
2288                         tg3_writephy(tp, MII_BMCR,
2289                                      BMCR_ANENABLE | BMCR_ANRESTART);
2290
2291                         tg3_writephy(tp, MII_TG3_FET_TEST,
2292                                      phytest | MII_TG3_FET_SHADOW_EN);
2293                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2294                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2295                                 tg3_writephy(tp,
2296                                              MII_TG3_FET_SHDW_AUXMODE4,
2297                                              phy);
2298                         }
2299                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2300                 }
2301                 return;
2302         } else if (do_low_power) {
2303                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2304                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2305
2306                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2307                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2308                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2309                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2310                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2311         }
2312
2313         /* The PHY should not be powered down on some chips because
2314          * of bugs.
2315          */
2316         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2317             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2318             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2319              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2320                 return;
2321
2322         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2323             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2324                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2325                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2326                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2327                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2328         }
2329
2330         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2331 }
2332
2333 /* tp->lock is held. */
2334 static int tg3_nvram_lock(struct tg3 *tp)
2335 {
2336         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2337                 int i;
2338
2339                 if (tp->nvram_lock_cnt == 0) {
2340                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2341                         for (i = 0; i < 8000; i++) {
2342                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2343                                         break;
2344                                 udelay(20);
2345                         }
2346                         if (i == 8000) {
2347                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2348                                 return -ENODEV;
2349                         }
2350                 }
2351                 tp->nvram_lock_cnt++;
2352         }
2353         return 0;
2354 }
2355
2356 /* tp->lock is held. */
2357 static void tg3_nvram_unlock(struct tg3 *tp)
2358 {
2359         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2360                 if (tp->nvram_lock_cnt > 0)
2361                         tp->nvram_lock_cnt--;
2362                 if (tp->nvram_lock_cnt == 0)
2363                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2364         }
2365 }
2366
2367 /* tp->lock is held. */
2368 static void tg3_enable_nvram_access(struct tg3 *tp)
2369 {
2370         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2371             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2372                 u32 nvaccess = tr32(NVRAM_ACCESS);
2373
2374                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2375         }
2376 }
2377
2378 /* tp->lock is held. */
2379 static void tg3_disable_nvram_access(struct tg3 *tp)
2380 {
2381         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2382             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2383                 u32 nvaccess = tr32(NVRAM_ACCESS);
2384
2385                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2386         }
2387 }
2388
2389 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2390                                         u32 offset, u32 *val)
2391 {
2392         u32 tmp;
2393         int i;
2394
2395         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2396                 return -EINVAL;
2397
2398         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2399                                         EEPROM_ADDR_DEVID_MASK |
2400                                         EEPROM_ADDR_READ);
2401         tw32(GRC_EEPROM_ADDR,
2402              tmp |
2403              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2404              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2405               EEPROM_ADDR_ADDR_MASK) |
2406              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2407
2408         for (i = 0; i < 1000; i++) {
2409                 tmp = tr32(GRC_EEPROM_ADDR);
2410
2411                 if (tmp & EEPROM_ADDR_COMPLETE)
2412                         break;
2413                 msleep(1);
2414         }
2415         if (!(tmp & EEPROM_ADDR_COMPLETE))
2416                 return -EBUSY;
2417
2418         tmp = tr32(GRC_EEPROM_DATA);
2419
2420         /*
2421          * The data will always be opposite the native endian
2422          * format.  Perform a blind byteswap to compensate.
2423          */
2424         *val = swab32(tmp);
2425
2426         return 0;
2427 }
2428
2429 #define NVRAM_CMD_TIMEOUT 10000
2430
2431 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2432 {
2433         int i;
2434
2435         tw32(NVRAM_CMD, nvram_cmd);
2436         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2437                 udelay(10);
2438                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2439                         udelay(10);
2440                         break;
2441                 }
2442         }
2443
2444         if (i == NVRAM_CMD_TIMEOUT)
2445                 return -EBUSY;
2446
2447         return 0;
2448 }
2449
2450 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2451 {
2452         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2453             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2454             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2455            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2456             (tp->nvram_jedecnum == JEDEC_ATMEL))
2457
2458                 addr = ((addr / tp->nvram_pagesize) <<
2459                         ATMEL_AT45DB0X1B_PAGE_POS) +
2460                        (addr % tp->nvram_pagesize);
2461
2462         return addr;
2463 }
2464
2465 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2466 {
2467         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2468             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2469             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2470            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2471             (tp->nvram_jedecnum == JEDEC_ATMEL))
2472
2473                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2474                         tp->nvram_pagesize) +
2475                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2476
2477         return addr;
2478 }
2479
2480 /* NOTE: Data read in from NVRAM is byteswapped according to
2481  * the byteswapping settings for all other register accesses.
2482  * tg3 devices are BE devices, so on a BE machine, the data
2483  * returned will be exactly as it is seen in NVRAM.  On a LE
2484  * machine, the 32-bit value will be byteswapped.
2485  */
2486 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2487 {
2488         int ret;
2489
2490         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2491                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2492
2493         offset = tg3_nvram_phys_addr(tp, offset);
2494
2495         if (offset > NVRAM_ADDR_MSK)
2496                 return -EINVAL;
2497
2498         ret = tg3_nvram_lock(tp);
2499         if (ret)
2500                 return ret;
2501
2502         tg3_enable_nvram_access(tp);
2503
2504         tw32(NVRAM_ADDR, offset);
2505         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2506                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2507
2508         if (ret == 0)
2509                 *val = tr32(NVRAM_RDDATA);
2510
2511         tg3_disable_nvram_access(tp);
2512
2513         tg3_nvram_unlock(tp);
2514
2515         return ret;
2516 }
2517
2518 /* Ensures NVRAM data is in bytestream format. */
2519 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2520 {
2521         u32 v;
2522         int res = tg3_nvram_read(tp, offset, &v);
2523         if (!res)
2524                 *val = cpu_to_be32(v);
2525         return res;
2526 }
2527
2528 /* tp->lock is held. */
2529 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2530 {
2531         u32 addr_high, addr_low;
2532         int i;
2533
2534         addr_high = ((tp->dev->dev_addr[0] << 8) |
2535                      tp->dev->dev_addr[1]);
2536         addr_low = ((tp->dev->dev_addr[2] << 24) |
2537                     (tp->dev->dev_addr[3] << 16) |
2538                     (tp->dev->dev_addr[4] <<  8) |
2539                     (tp->dev->dev_addr[5] <<  0));
2540         for (i = 0; i < 4; i++) {
2541                 if (i == 1 && skip_mac_1)
2542                         continue;
2543                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2544                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2545         }
2546
2547         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2548             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2549                 for (i = 0; i < 12; i++) {
2550                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2551                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2552                 }
2553         }
2554
2555         addr_high = (tp->dev->dev_addr[0] +
2556                      tp->dev->dev_addr[1] +
2557                      tp->dev->dev_addr[2] +
2558                      tp->dev->dev_addr[3] +
2559                      tp->dev->dev_addr[4] +
2560                      tp->dev->dev_addr[5]) &
2561                 TX_BACKOFF_SEED_MASK;
2562         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2563 }
2564
2565 static void tg3_enable_register_access(struct tg3 *tp)
2566 {
2567         /*
2568          * Make sure register accesses (indirect or otherwise) will function
2569          * correctly.
2570          */
2571         pci_write_config_dword(tp->pdev,
2572                                TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
2573 }
2574
2575 static int tg3_power_up(struct tg3 *tp)
2576 {
2577         tg3_enable_register_access(tp);
2578
2579         pci_set_power_state(tp->pdev, PCI_D0);
2580
2581         /* Switch out of Vaux if it is a NIC */
2582         if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2583                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2584
2585         return 0;
2586 }
2587
2588 static int tg3_power_down_prepare(struct tg3 *tp)
2589 {
2590         u32 misc_host_ctrl;
2591         bool device_should_wake, do_low_power;
2592
2593         tg3_enable_register_access(tp);
2594
2595         /* Restore the CLKREQ setting. */
2596         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2597                 u16 lnkctl;
2598
2599                 pci_read_config_word(tp->pdev,
2600                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2601                                      &lnkctl);
2602                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2603                 pci_write_config_word(tp->pdev,
2604                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2605                                       lnkctl);
2606         }
2607
2608         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2609         tw32(TG3PCI_MISC_HOST_CTRL,
2610              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2611
2612         device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
2613                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2614
2615         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2616                 do_low_power = false;
2617                 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2618                     !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2619                         struct phy_device *phydev;
2620                         u32 phyid, advertising;
2621
2622                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2623
2624                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2625
2626                         tp->link_config.orig_speed = phydev->speed;
2627                         tp->link_config.orig_duplex = phydev->duplex;
2628                         tp->link_config.orig_autoneg = phydev->autoneg;
2629                         tp->link_config.orig_advertising = phydev->advertising;
2630
2631                         advertising = ADVERTISED_TP |
2632                                       ADVERTISED_Pause |
2633                                       ADVERTISED_Autoneg |
2634                                       ADVERTISED_10baseT_Half;
2635
2636                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2637                             device_should_wake) {
2638                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2639                                         advertising |=
2640                                                 ADVERTISED_100baseT_Half |
2641                                                 ADVERTISED_100baseT_Full |
2642                                                 ADVERTISED_10baseT_Full;
2643                                 else
2644                                         advertising |= ADVERTISED_10baseT_Full;
2645                         }
2646
2647                         phydev->advertising = advertising;
2648
2649                         phy_start_aneg(phydev);
2650
2651                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2652                         if (phyid != PHY_ID_BCMAC131) {
2653                                 phyid &= PHY_BCM_OUI_MASK;
2654                                 if (phyid == PHY_BCM_OUI_1 ||
2655                                     phyid == PHY_BCM_OUI_2 ||
2656                                     phyid == PHY_BCM_OUI_3)
2657                                         do_low_power = true;
2658                         }
2659                 }
2660         } else {
2661                 do_low_power = true;
2662
2663                 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2664                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2665                         tp->link_config.orig_speed = tp->link_config.speed;
2666                         tp->link_config.orig_duplex = tp->link_config.duplex;
2667                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2668                 }
2669
2670                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2671                         tp->link_config.speed = SPEED_10;
2672                         tp->link_config.duplex = DUPLEX_HALF;
2673                         tp->link_config.autoneg = AUTONEG_ENABLE;
2674                         tg3_setup_phy(tp, 0);
2675                 }
2676         }
2677
2678         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2679                 u32 val;
2680
2681                 val = tr32(GRC_VCPU_EXT_CTRL);
2682                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2683         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2684                 int i;
2685                 u32 val;
2686
2687                 for (i = 0; i < 200; i++) {
2688                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2689                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2690                                 break;
2691                         msleep(1);
2692                 }
2693         }
2694         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2695                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2696                                                      WOL_DRV_STATE_SHUTDOWN |
2697                                                      WOL_DRV_WOL |
2698                                                      WOL_SET_MAGIC_PKT);
2699
2700         if (device_should_wake) {
2701                 u32 mac_mode;
2702
2703                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2704                         if (do_low_power) {
2705                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2706                                 udelay(40);
2707                         }
2708
2709                         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2710                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2711                         else
2712                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2713
2714                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2715                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2716                             ASIC_REV_5700) {
2717                                 u32 speed = (tp->tg3_flags &
2718                                              TG3_FLAG_WOL_SPEED_100MB) ?
2719                                              SPEED_100 : SPEED_10;
2720                                 if (tg3_5700_link_polarity(tp, speed))
2721                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2722                                 else
2723                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2724                         }
2725                 } else {
2726                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2727                 }
2728
2729                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2730                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2731
2732                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2733                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2734                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2735                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2736                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2737                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2738
2739                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
2740                         mac_mode |= MAC_MODE_APE_TX_EN |
2741                                     MAC_MODE_APE_RX_EN |
2742                                     MAC_MODE_TDE_ENABLE;
2743
2744                 tw32_f(MAC_MODE, mac_mode);
2745                 udelay(100);
2746
2747                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2748                 udelay(10);
2749         }
2750
2751         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2752             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2753              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2754                 u32 base_val;
2755
2756                 base_val = tp->pci_clock_ctrl;
2757                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2758                              CLOCK_CTRL_TXCLK_DISABLE);
2759
2760                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2761                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2762         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2763                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2764                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2765                 /* do nothing */
2766         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2767                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2768                 u32 newbits1, newbits2;
2769
2770                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2771                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2772                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2773                                     CLOCK_CTRL_TXCLK_DISABLE |
2774                                     CLOCK_CTRL_ALTCLK);
2775                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2776                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2777                         newbits1 = CLOCK_CTRL_625_CORE;
2778                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2779                 } else {
2780                         newbits1 = CLOCK_CTRL_ALTCLK;
2781                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2782                 }
2783
2784                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2785                             40);
2786
2787                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2788                             40);
2789
2790                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2791                         u32 newbits3;
2792
2793                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2794                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2795                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2796                                             CLOCK_CTRL_TXCLK_DISABLE |
2797                                             CLOCK_CTRL_44MHZ_CORE);
2798                         } else {
2799                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2800                         }
2801
2802                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2803                                     tp->pci_clock_ctrl | newbits3, 40);
2804                 }
2805         }
2806
2807         if (!(device_should_wake) &&
2808             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2809                 tg3_power_down_phy(tp, do_low_power);
2810
2811         tg3_frob_aux_power(tp);
2812
2813         /* Workaround for unstable PLL clock */
2814         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2815             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2816                 u32 val = tr32(0x7d00);
2817
2818                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2819                 tw32(0x7d00, val);
2820                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2821                         int err;
2822
2823                         err = tg3_nvram_lock(tp);
2824                         tg3_halt_cpu(tp, RX_CPU_BASE);
2825                         if (!err)
2826                                 tg3_nvram_unlock(tp);
2827                 }
2828         }
2829
2830         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2831
2832         return 0;
2833 }
2834
2835 static void tg3_power_down(struct tg3 *tp)
2836 {
2837         tg3_power_down_prepare(tp);
2838
2839         pci_wake_from_d3(tp->pdev, tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2840         pci_set_power_state(tp->pdev, PCI_D3hot);
2841 }
2842
2843 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2844 {
2845         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2846         case MII_TG3_AUX_STAT_10HALF:
2847                 *speed = SPEED_10;
2848                 *duplex = DUPLEX_HALF;
2849                 break;
2850
2851         case MII_TG3_AUX_STAT_10FULL:
2852                 *speed = SPEED_10;
2853                 *duplex = DUPLEX_FULL;
2854                 break;
2855
2856         case MII_TG3_AUX_STAT_100HALF:
2857                 *speed = SPEED_100;
2858                 *duplex = DUPLEX_HALF;
2859                 break;
2860
2861         case MII_TG3_AUX_STAT_100FULL:
2862                 *speed = SPEED_100;
2863                 *duplex = DUPLEX_FULL;
2864                 break;
2865
2866         case MII_TG3_AUX_STAT_1000HALF:
2867                 *speed = SPEED_1000;
2868                 *duplex = DUPLEX_HALF;
2869                 break;
2870
2871         case MII_TG3_AUX_STAT_1000FULL:
2872                 *speed = SPEED_1000;
2873                 *duplex = DUPLEX_FULL;
2874                 break;
2875
2876         default:
2877                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2878                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2879                                  SPEED_10;
2880                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2881                                   DUPLEX_HALF;
2882                         break;
2883                 }
2884                 *speed = SPEED_INVALID;
2885                 *duplex = DUPLEX_INVALID;
2886                 break;
2887         }
2888 }
2889
2890 static void tg3_phy_copper_begin(struct tg3 *tp)
2891 {
2892         u32 new_adv;
2893         int i;
2894
2895         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2896                 /* Entering low power mode.  Disable gigabit and
2897                  * 100baseT advertisements.
2898                  */
2899                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2900
2901                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2902                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2903                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2904                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2905
2906                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2907         } else if (tp->link_config.speed == SPEED_INVALID) {
2908                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2909                         tp->link_config.advertising &=
2910                                 ~(ADVERTISED_1000baseT_Half |
2911                                   ADVERTISED_1000baseT_Full);
2912
2913                 new_adv = ADVERTISE_CSMA;
2914                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2915                         new_adv |= ADVERTISE_10HALF;
2916                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2917                         new_adv |= ADVERTISE_10FULL;
2918                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2919                         new_adv |= ADVERTISE_100HALF;
2920                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2921                         new_adv |= ADVERTISE_100FULL;
2922
2923                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2924
2925                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2926
2927                 if (tp->link_config.advertising &
2928                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2929                         new_adv = 0;
2930                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2931                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2932                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2933                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2934                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
2935                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2936                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2937                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2938                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2939                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2940                 } else {
2941                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2942                 }
2943         } else {
2944                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2945                 new_adv |= ADVERTISE_CSMA;
2946
2947                 /* Asking for a specific link mode. */
2948                 if (tp->link_config.speed == SPEED_1000) {
2949                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2950
2951                         if (tp->link_config.duplex == DUPLEX_FULL)
2952                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2953                         else
2954                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2955                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2956                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2957                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2958                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2959                 } else {
2960                         if (tp->link_config.speed == SPEED_100) {
2961                                 if (tp->link_config.duplex == DUPLEX_FULL)
2962                                         new_adv |= ADVERTISE_100FULL;
2963                                 else
2964                                         new_adv |= ADVERTISE_100HALF;
2965                         } else {
2966                                 if (tp->link_config.duplex == DUPLEX_FULL)
2967                                         new_adv |= ADVERTISE_10FULL;
2968                                 else
2969                                         new_adv |= ADVERTISE_10HALF;
2970                         }
2971                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2972
2973                         new_adv = 0;
2974                 }
2975
2976                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2977         }
2978
2979         if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
2980                 u32 val;
2981
2982                 tw32(TG3_CPMU_EEE_MODE,
2983                      tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2984
2985                 /* Enable SM_DSP clock and tx 6dB coding. */
2986                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
2987                       MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
2988                       MII_TG3_AUXCTL_ACTL_TX_6DB;
2989                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2990
2991                 switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
2992                 case ASIC_REV_5717:
2993                 case ASIC_REV_57765:
2994                         if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
2995                                 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
2996                                                  MII_TG3_DSP_CH34TP2_HIBW01);
2997                         /* Fall through */
2998                 case ASIC_REV_5719:
2999                         val = MII_TG3_DSP_TAP26_ALNOKO |
3000                               MII_TG3_DSP_TAP26_RMRXSTO |
3001                               MII_TG3_DSP_TAP26_OPCSINPT;
3002                         tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
3003                 }
3004
3005                 val = 0;
3006                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3007                         /* Advertise 100-BaseTX EEE ability */
3008                         if (tp->link_config.advertising &
3009                             ADVERTISED_100baseT_Full)
3010                                 val |= MDIO_AN_EEE_ADV_100TX;
3011                         /* Advertise 1000-BaseT EEE ability */
3012                         if (tp->link_config.advertising &
3013                             ADVERTISED_1000baseT_Full)
3014                                 val |= MDIO_AN_EEE_ADV_1000T;
3015                 }
3016                 tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3017
3018                 /* Turn off SM_DSP clock. */
3019                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
3020                       MII_TG3_AUXCTL_ACTL_TX_6DB;
3021                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3022         }
3023
3024         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
3025             tp->link_config.speed != SPEED_INVALID) {
3026                 u32 bmcr, orig_bmcr;
3027
3028                 tp->link_config.active_speed = tp->link_config.speed;
3029                 tp->link_config.active_duplex = tp->link_config.duplex;
3030
3031                 bmcr = 0;
3032                 switch (tp->link_config.speed) {
3033                 default:
3034                 case SPEED_10:
3035                         break;
3036
3037                 case SPEED_100:
3038                         bmcr |= BMCR_SPEED100;
3039                         break;
3040
3041                 case SPEED_1000:
3042                         bmcr |= TG3_BMCR_SPEED1000;
3043                         break;
3044                 }
3045
3046                 if (tp->link_config.duplex == DUPLEX_FULL)
3047                         bmcr |= BMCR_FULLDPLX;
3048
3049                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
3050                     (bmcr != orig_bmcr)) {
3051                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
3052                         for (i = 0; i < 1500; i++) {
3053                                 u32 tmp;
3054
3055                                 udelay(10);
3056                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
3057                                     tg3_readphy(tp, MII_BMSR, &tmp))
3058                                         continue;
3059                                 if (!(tmp & BMSR_LSTATUS)) {
3060                                         udelay(40);
3061                                         break;
3062                                 }
3063                         }
3064                         tg3_writephy(tp, MII_BMCR, bmcr);
3065                         udelay(40);
3066                 }
3067         } else {
3068                 tg3_writephy(tp, MII_BMCR,
3069                              BMCR_ANENABLE | BMCR_ANRESTART);
3070         }
3071 }
3072
3073 static int tg3_init_5401phy_dsp(struct tg3 *tp)
3074 {
3075         int err;
3076
3077         /* Turn off tap power management. */
3078         /* Set Extended packet length bit */
3079         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
3080
3081         err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
3082         err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
3083         err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
3084         err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
3085         err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
3086
3087         udelay(40);
3088
3089         return err;
3090 }
3091
3092 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3093 {
3094         u32 adv_reg, all_mask = 0;
3095
3096         if (mask & ADVERTISED_10baseT_Half)
3097                 all_mask |= ADVERTISE_10HALF;
3098         if (mask & ADVERTISED_10baseT_Full)
3099                 all_mask |= ADVERTISE_10FULL;
3100         if (mask & ADVERTISED_100baseT_Half)
3101                 all_mask |= ADVERTISE_100HALF;
3102         if (mask & ADVERTISED_100baseT_Full)
3103                 all_mask |= ADVERTISE_100FULL;
3104
3105         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3106                 return 0;
3107
3108         if ((adv_reg & all_mask) != all_mask)
3109                 return 0;
3110         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3111                 u32 tg3_ctrl;
3112
3113                 all_mask = 0;
3114                 if (mask & ADVERTISED_1000baseT_Half)
3115                         all_mask |= ADVERTISE_1000HALF;
3116                 if (mask & ADVERTISED_1000baseT_Full)
3117                         all_mask |= ADVERTISE_1000FULL;
3118
3119                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3120                         return 0;
3121
3122                 if ((tg3_ctrl & all_mask) != all_mask)
3123                         return 0;
3124         }
3125         return 1;
3126 }
3127
3128 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3129 {
3130         u32 curadv, reqadv;
3131
3132         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3133                 return 1;
3134
3135         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3136         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3137
3138         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3139                 if (curadv != reqadv)
3140                         return 0;
3141
3142                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3143                         tg3_readphy(tp, MII_LPA, rmtadv);
3144         } else {
3145                 /* Reprogram the advertisement register, even if it
3146                  * does not affect the current link.  If the link
3147                  * gets renegotiated in the future, we can save an
3148                  * additional renegotiation cycle by advertising
3149                  * it correctly in the first place.
3150                  */
3151                 if (curadv != reqadv) {
3152                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3153                                      ADVERTISE_PAUSE_ASYM);
3154                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3155                 }
3156         }
3157
3158         return 1;
3159 }
3160
3161 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3162 {
3163         int current_link_up;
3164         u32 bmsr, val;
3165         u32 lcl_adv, rmt_adv;
3166         u16 current_speed;
3167         u8 current_duplex;
3168         int i, err;
3169
3170         tw32(MAC_EVENT, 0);
3171
3172         tw32_f(MAC_STATUS,
3173              (MAC_STATUS_SYNC_CHANGED |
3174               MAC_STATUS_CFG_CHANGED |
3175               MAC_STATUS_MI_COMPLETION |
3176               MAC_STATUS_LNKSTATE_CHANGED));
3177         udelay(40);
3178
3179         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3180                 tw32_f(MAC_MI_MODE,
3181                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3182                 udelay(80);
3183         }
3184
3185         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3186
3187         /* Some third-party PHYs need to be reset on link going
3188          * down.
3189          */
3190         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3191              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3192              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3193             netif_carrier_ok(tp->dev)) {
3194                 tg3_readphy(tp, MII_BMSR, &bmsr);
3195                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3196                     !(bmsr & BMSR_LSTATUS))
3197                         force_reset = 1;
3198         }
3199         if (force_reset)
3200                 tg3_phy_reset(tp);
3201
3202         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3203                 tg3_readphy(tp, MII_BMSR, &bmsr);
3204                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3205                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3206                         bmsr = 0;
3207
3208                 if (!(bmsr & BMSR_LSTATUS)) {
3209                         err = tg3_init_5401phy_dsp(tp);
3210                         if (err)
3211                                 return err;
3212
3213                         tg3_readphy(tp, MII_BMSR, &bmsr);
3214                         for (i = 0; i < 1000; i++) {
3215                                 udelay(10);
3216                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3217                                     (bmsr & BMSR_LSTATUS)) {
3218                                         udelay(40);
3219                                         break;
3220                                 }
3221                         }
3222
3223                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3224                             TG3_PHY_REV_BCM5401_B0 &&
3225                             !(bmsr & BMSR_LSTATUS) &&
3226                             tp->link_config.active_speed == SPEED_1000) {
3227                                 err = tg3_phy_reset(tp);
3228                                 if (!err)
3229                                         err = tg3_init_5401phy_dsp(tp);
3230                                 if (err)
3231                                         return err;
3232                         }
3233                 }
3234         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3235                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3236                 /* 5701 {A0,B0} CRC bug workaround */
3237                 tg3_writephy(tp, 0x15, 0x0a75);
3238                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3239                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3240                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3241         }
3242
3243         /* Clear pending interrupts... */
3244         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3245         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3246
3247         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3248                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3249         else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3250                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3251
3252         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3253             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3254                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3255                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3256                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3257                 else
3258                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3259         }
3260
3261         current_link_up = 0;
3262         current_speed = SPEED_INVALID;
3263         current_duplex = DUPLEX_INVALID;
3264
3265         if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3266                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3267                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3268                 if (!(val & (1 << 10))) {
3269                         val |= (1 << 10);
3270                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3271                         goto relink;
3272                 }
3273         }
3274
3275         bmsr = 0;
3276         for (i = 0; i < 100; i++) {
3277                 tg3_readphy(tp, MII_BMSR, &bmsr);
3278                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3279                     (bmsr & BMSR_LSTATUS))
3280                         break;
3281                 udelay(40);
3282         }
3283
3284         if (bmsr & BMSR_LSTATUS) {
3285                 u32 aux_stat, bmcr;
3286
3287                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3288                 for (i = 0; i < 2000; i++) {
3289                         udelay(10);
3290                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3291                             aux_stat)
3292                                 break;
3293                 }
3294
3295                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3296                                              &current_speed,
3297                                              &current_duplex);
3298
3299                 bmcr = 0;
3300                 for (i = 0; i < 200; i++) {
3301                         tg3_readphy(tp, MII_BMCR, &bmcr);
3302                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3303                                 continue;
3304                         if (bmcr && bmcr != 0x7fff)
3305                                 break;
3306                         udelay(10);
3307                 }
3308
3309                 lcl_adv = 0;
3310                 rmt_adv = 0;
3311
3312                 tp->link_config.active_speed = current_speed;
3313                 tp->link_config.active_duplex = current_duplex;
3314
3315                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3316                         if ((bmcr & BMCR_ANENABLE) &&
3317                             tg3_copper_is_advertising_all(tp,
3318                                                 tp->link_config.advertising)) {
3319                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3320                                                                   &rmt_adv))
3321                                         current_link_up = 1;
3322                         }
3323                 } else {
3324                         if (!(bmcr & BMCR_ANENABLE) &&
3325                             tp->link_config.speed == current_speed &&
3326                             tp->link_config.duplex == current_duplex &&
3327                             tp->link_config.flowctrl ==
3328                             tp->link_config.active_flowctrl) {
3329                                 current_link_up = 1;
3330                         }
3331                 }
3332
3333                 if (current_link_up == 1 &&
3334                     tp->link_config.active_duplex == DUPLEX_FULL)
3335                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3336         }
3337
3338 relink:
3339         if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3340                 tg3_phy_copper_begin(tp);
3341
3342                 tg3_readphy(tp, MII_BMSR, &bmsr);
3343                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3344                     (bmsr & BMSR_LSTATUS))
3345                         current_link_up = 1;
3346         }
3347
3348         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3349         if (current_link_up == 1) {
3350                 if (tp->link_config.active_speed == SPEED_100 ||
3351                     tp->link_config.active_speed == SPEED_10)
3352                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3353                 else
3354                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3355         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3356                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3357         else
3358                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3359
3360         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3361         if (tp->link_config.active_duplex == DUPLEX_HALF)
3362                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3363
3364         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3365                 if (current_link_up == 1 &&
3366                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3367                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3368                 else
3369                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3370         }
3371
3372         /* ??? Without this setting Netgear GA302T PHY does not
3373          * ??? send/receive packets...
3374          */
3375         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3376             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3377                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3378                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3379                 udelay(80);
3380         }
3381
3382         tw32_f(MAC_MODE, tp->mac_mode);
3383         udelay(40);
3384
3385         tg3_phy_eee_adjust(tp, current_link_up);
3386
3387         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3388                 /* Polled via timer. */
3389                 tw32_f(MAC_EVENT, 0);
3390         } else {
3391                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3392         }
3393         udelay(40);
3394
3395         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3396             current_link_up == 1 &&
3397             tp->link_config.active_speed == SPEED_1000 &&
3398             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3399              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3400                 udelay(120);
3401                 tw32_f(MAC_STATUS,
3402                      (MAC_STATUS_SYNC_CHANGED |
3403                       MAC_STATUS_CFG_CHANGED));
3404                 udelay(40);
3405                 tg3_write_mem(tp,
3406                               NIC_SRAM_FIRMWARE_MBOX,
3407                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3408         }
3409
3410         /* Prevent send BD corruption. */
3411         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3412                 u16 oldlnkctl, newlnkctl;
3413
3414                 pci_read_config_word(tp->pdev,
3415                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3416                                      &oldlnkctl);
3417                 if (tp->link_config.active_speed == SPEED_100 ||
3418                     tp->link_config.active_speed == SPEED_10)
3419                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3420                 else
3421                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3422                 if (newlnkctl != oldlnkctl)
3423                         pci_write_config_word(tp->pdev,
3424                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3425                                               newlnkctl);
3426         }
3427
3428         if (current_link_up != netif_carrier_ok(tp->dev)) {
3429                 if (current_link_up)
3430                         netif_carrier_on(tp->dev);
3431                 else
3432                         netif_carrier_off(tp->dev);
3433                 tg3_link_report(tp);
3434         }
3435
3436         return 0;
3437 }
3438
3439 struct tg3_fiber_aneginfo {
3440         int state;
3441 #define ANEG_STATE_UNKNOWN              0
3442 #define ANEG_STATE_AN_ENABLE            1
3443 #define ANEG_STATE_RESTART_INIT         2
3444 #define ANEG_STATE_RESTART              3
3445 #define ANEG_STATE_DISABLE_LINK_OK      4
3446 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3447 #define ANEG_STATE_ABILITY_DETECT       6
3448 #define ANEG_STATE_ACK_DETECT_INIT      7
3449 #define ANEG_STATE_ACK_DETECT           8
3450 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3451 #define ANEG_STATE_COMPLETE_ACK         10
3452 #define ANEG_STATE_IDLE_DETECT_INIT     11
3453 #define ANEG_STATE_IDLE_DETECT          12
3454 #define ANEG_STATE_LINK_OK              13
3455 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3456 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3457
3458         u32 flags;
3459 #define MR_AN_ENABLE            0x00000001
3460 #define MR_RESTART_AN           0x00000002
3461 #define MR_AN_COMPLETE          0x00000004
3462 #define MR_PAGE_RX              0x00000008
3463 #define MR_NP_LOADED            0x00000010
3464 #define MR_TOGGLE_TX            0x00000020
3465 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3466 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3467 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3468 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3469 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3470 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3471 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3472 #define MR_TOGGLE_RX            0x00002000
3473 #define MR_NP_RX                0x00004000
3474
3475 #define MR_LINK_OK              0x80000000
3476
3477         unsigned long link_time, cur_time;
3478
3479         u32 ability_match_cfg;
3480         int ability_match_count;
3481
3482         char ability_match, idle_match, ack_match;
3483
3484         u32 txconfig, rxconfig;
3485 #define ANEG_CFG_NP             0x00000080
3486 #define ANEG_CFG_ACK            0x00000040
3487 #define ANEG_CFG_RF2            0x00000020
3488 #define ANEG_CFG_RF1            0x00000010
3489 #define ANEG_CFG_PS2            0x00000001
3490 #define ANEG_CFG_PS1            0x00008000
3491 #define ANEG_CFG_HD             0x00004000
3492 #define ANEG_CFG_FD             0x00002000
3493 #define ANEG_CFG_INVAL          0x00001f06
3494
3495 };
3496 #define ANEG_OK         0
3497 #define ANEG_DONE       1
3498 #define ANEG_TIMER_ENAB 2
3499 #define ANEG_FAILED     -1
3500
3501 #define ANEG_STATE_SETTLE_TIME  10000
3502
3503 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3504                                    struct tg3_fiber_aneginfo *ap)
3505 {
3506         u16 flowctrl;
3507         unsigned long delta;
3508         u32 rx_cfg_reg;
3509         int ret;
3510
3511         if (ap->state == ANEG_STATE_UNKNOWN) {
3512                 ap->rxconfig = 0;
3513                 ap->link_time = 0;
3514                 ap->cur_time = 0;
3515                 ap->ability_match_cfg = 0;
3516                 ap->ability_match_count = 0;
3517                 ap->ability_match = 0;
3518                 ap->idle_match = 0;
3519                 ap->ack_match = 0;
3520         }
3521         ap->cur_time++;
3522
3523         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3524                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3525
3526                 if (rx_cfg_reg != ap->ability_match_cfg) {
3527                         ap->ability_match_cfg = rx_cfg_reg;
3528                         ap->ability_match = 0;
3529                         ap->ability_match_count = 0;
3530                 } else {
3531                         if (++ap->ability_match_count > 1) {
3532                                 ap->ability_match = 1;
3533                                 ap->ability_match_cfg = rx_cfg_reg;
3534                         }
3535                 }
3536                 if (rx_cfg_reg & ANEG_CFG_ACK)
3537                         ap->ack_match = 1;
3538                 else
3539                         ap->ack_match = 0;
3540
3541                 ap->idle_match = 0;
3542         } else {
3543                 ap->idle_match = 1;
3544                 ap->ability_match_cfg = 0;
3545                 ap->ability_match_count = 0;
3546                 ap->ability_match = 0;
3547                 ap->ack_match = 0;
3548
3549                 rx_cfg_reg = 0;
3550         }
3551
3552         ap->rxconfig = rx_cfg_reg;
3553         ret = ANEG_OK;
3554
3555         switch (ap->state) {
3556         case ANEG_STATE_UNKNOWN:
3557                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3558                         ap->state = ANEG_STATE_AN_ENABLE;
3559
3560                 /* fallthru */
3561         case ANEG_STATE_AN_ENABLE:
3562                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3563                 if (ap->flags & MR_AN_ENABLE) {
3564                         ap->link_time = 0;
3565                         ap->cur_time = 0;
3566                         ap->ability_match_cfg = 0;
3567                         ap->ability_match_count = 0;
3568                         ap->ability_match = 0;
3569                         ap->idle_match = 0;
3570                         ap->ack_match = 0;
3571
3572                         ap->state = ANEG_STATE_RESTART_INIT;
3573                 } else {
3574                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3575                 }
3576                 break;
3577
3578         case ANEG_STATE_RESTART_INIT:
3579                 ap->link_time = ap->cur_time;
3580                 ap->flags &= ~(MR_NP_LOADED);
3581                 ap->txconfig = 0;
3582                 tw32(MAC_TX_AUTO_NEG, 0);
3583                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3584                 tw32_f(MAC_MODE, tp->mac_mode);
3585                 udelay(40);
3586
3587                 ret = ANEG_TIMER_ENAB;
3588                 ap->state = ANEG_STATE_RESTART;
3589
3590                 /* fallthru */
3591         case ANEG_STATE_RESTART:
3592                 delta = ap->cur_time - ap->link_time;
3593                 if (delta > ANEG_STATE_SETTLE_TIME)
3594                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3595                 else
3596                         ret = ANEG_TIMER_ENAB;
3597                 break;
3598
3599         case ANEG_STATE_DISABLE_LINK_OK:
3600                 ret = ANEG_DONE;
3601                 break;
3602
3603         case ANEG_STATE_ABILITY_DETECT_INIT:
3604                 ap->flags &= ~(MR_TOGGLE_TX);
3605                 ap->txconfig = ANEG_CFG_FD;
3606                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3607                 if (flowctrl & ADVERTISE_1000XPAUSE)
3608                         ap->txconfig |= ANEG_CFG_PS1;
3609                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3610                         ap->txconfig |= ANEG_CFG_PS2;
3611                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3612                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3613                 tw32_f(MAC_MODE, tp->mac_mode);
3614                 udelay(40);
3615
3616                 ap->state = ANEG_STATE_ABILITY_DETECT;
3617                 break;
3618
3619         case ANEG_STATE_ABILITY_DETECT:
3620                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3621                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3622                 break;
3623
3624         case ANEG_STATE_ACK_DETECT_INIT:
3625                 ap->txconfig |= ANEG_CFG_ACK;
3626                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3627                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3628                 tw32_f(MAC_MODE, tp->mac_mode);
3629                 udelay(40);
3630
3631                 ap->state = ANEG_STATE_ACK_DETECT;
3632
3633                 /* fallthru */
3634         case ANEG_STATE_ACK_DETECT:
3635                 if (ap->ack_match != 0) {
3636                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3637                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3638                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3639                         } else {
3640                                 ap->state = ANEG_STATE_AN_ENABLE;
3641                         }
3642                 } else if (ap->ability_match != 0 &&
3643                            ap->rxconfig == 0) {
3644                         ap->state = ANEG_STATE_AN_ENABLE;
3645                 }
3646                 break;
3647
3648         case ANEG_STATE_COMPLETE_ACK_INIT:
3649                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3650                         ret = ANEG_FAILED;
3651                         break;
3652                 }
3653                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3654                                MR_LP_ADV_HALF_DUPLEX |
3655                                MR_LP_ADV_SYM_PAUSE |
3656                                MR_LP_ADV_ASYM_PAUSE |
3657                                MR_LP_ADV_REMOTE_FAULT1 |
3658                                MR_LP_ADV_REMOTE_FAULT2 |
3659                                MR_LP_ADV_NEXT_PAGE |
3660                                MR_TOGGLE_RX |
3661                                MR_NP_RX);
3662                 if (ap->rxconfig & ANEG_CFG_FD)
3663                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3664                 if (ap->rxconfig & ANEG_CFG_HD)
3665                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3666                 if (ap->rxconfig & ANEG_CFG_PS1)
3667                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3668                 if (ap->rxconfig & ANEG_CFG_PS2)
3669                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3670                 if (ap->rxconfig & ANEG_CFG_RF1)
3671                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3672                 if (ap->rxconfig & ANEG_CFG_RF2)
3673                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3674                 if (ap->rxconfig & ANEG_CFG_NP)
3675                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3676
3677                 ap->link_time = ap->cur_time;
3678
3679                 ap->flags ^= (MR_TOGGLE_TX);
3680                 if (ap->rxconfig & 0x0008)
3681                         ap->flags |= MR_TOGGLE_RX;
3682                 if (ap->rxconfig & ANEG_CFG_NP)
3683                         ap->flags |= MR_NP_RX;
3684                 ap->flags |= MR_PAGE_RX;
3685
3686                 ap->state = ANEG_STATE_COMPLETE_ACK;
3687                 ret = ANEG_TIMER_ENAB;
3688                 break;
3689
3690         case ANEG_STATE_COMPLETE_ACK:
3691                 if (ap->ability_match != 0 &&
3692                     ap->rxconfig == 0) {
3693                         ap->state = ANEG_STATE_AN_ENABLE;
3694                         break;
3695                 }
3696                 delta = ap->cur_time - ap->link_time;
3697                 if (delta > ANEG_STATE_SETTLE_TIME) {
3698                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3699                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3700                         } else {
3701                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3702                                     !(ap->flags & MR_NP_RX)) {
3703                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3704                                 } else {
3705                                         ret = ANEG_FAILED;
3706                                 }
3707                         }
3708                 }
3709                 break;
3710
3711         case ANEG_STATE_IDLE_DETECT_INIT:
3712                 ap->link_time = ap->cur_time;
3713                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3714                 tw32_f(MAC_MODE, tp->mac_mode);
3715                 udelay(40);
3716
3717                 ap->state = ANEG_STATE_IDLE_DETECT;
3718                 ret = ANEG_TIMER_ENAB;
3719                 break;
3720
3721         case ANEG_STATE_IDLE_DETECT:
3722                 if (ap->ability_match != 0 &&
3723                     ap->rxconfig == 0) {
3724                         ap->state = ANEG_STATE_AN_ENABLE;
3725                         break;
3726                 }
3727                 delta = ap->cur_time - ap->link_time;
3728                 if (delta > ANEG_STATE_SETTLE_TIME) {
3729                         /* XXX another gem from the Broadcom driver :( */
3730                         ap->state = ANEG_STATE_LINK_OK;
3731                 }
3732                 break;
3733
3734         case ANEG_STATE_LINK_OK:
3735                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3736                 ret = ANEG_DONE;
3737                 break;
3738
3739         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3740                 /* ??? unimplemented */
3741                 break;
3742
3743         case ANEG_STATE_NEXT_PAGE_WAIT:
3744                 /* ??? unimplemented */
3745                 break;
3746
3747         default:
3748                 ret = ANEG_FAILED;
3749                 break;
3750         }
3751
3752         return ret;
3753 }
3754
3755 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3756 {
3757         int res = 0;
3758         struct tg3_fiber_aneginfo aninfo;
3759         int status = ANEG_FAILED;
3760         unsigned int tick;
3761         u32 tmp;
3762
3763         tw32_f(MAC_TX_AUTO_NEG, 0);
3764
3765         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3766         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3767         udelay(40);
3768
3769         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3770         udelay(40);
3771
3772         memset(&aninfo, 0, sizeof(aninfo));
3773         aninfo.flags |= MR_AN_ENABLE;
3774         aninfo.state = ANEG_STATE_UNKNOWN;
3775         aninfo.cur_time = 0;
3776         tick = 0;
3777         while (++tick < 195000) {
3778                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3779                 if (status == ANEG_DONE || status == ANEG_FAILED)
3780                         break;
3781
3782                 udelay(1);
3783         }
3784
3785         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3786         tw32_f(MAC_MODE, tp->mac_mode);
3787         udelay(40);
3788
3789         *txflags = aninfo.txconfig;
3790         *rxflags = aninfo.flags;
3791
3792         if (status == ANEG_DONE &&
3793             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3794                              MR_LP_ADV_FULL_DUPLEX)))
3795                 res = 1;
3796
3797         return res;
3798 }
3799
3800 static void tg3_init_bcm8002(struct tg3 *tp)
3801 {
3802         u32 mac_status = tr32(MAC_STATUS);
3803         int i;
3804
3805         /* Reset when initting first time or we have a link. */
3806         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3807             !(mac_status & MAC_STATUS_PCS_SYNCED))
3808                 return;
3809
3810         /* Set PLL lock range. */
3811         tg3_writephy(tp, 0x16, 0x8007);
3812
3813         /* SW reset */
3814         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3815
3816         /* Wait for reset to complete. */
3817         /* XXX schedule_timeout() ... */
3818         for (i = 0; i < 500; i++)
3819                 udelay(10);
3820
3821         /* Config mode; select PMA/Ch 1 regs. */
3822         tg3_writephy(tp, 0x10, 0x8411);
3823
3824         /* Enable auto-lock and comdet, select txclk for tx. */
3825         tg3_writephy(tp, 0x11, 0x0a10);
3826
3827         tg3_writephy(tp, 0x18, 0x00a0);
3828         tg3_writephy(tp, 0x16, 0x41ff);
3829
3830         /* Assert and deassert POR. */
3831         tg3_writephy(tp, 0x13, 0x0400);
3832         udelay(40);
3833         tg3_writephy(tp, 0x13, 0x0000);
3834
3835         tg3_writephy(tp, 0x11, 0x0a50);
3836         udelay(40);
3837         tg3_writephy(tp, 0x11, 0x0a10);
3838
3839         /* Wait for signal to stabilize */
3840         /* XXX schedule_timeout() ... */
3841         for (i = 0; i < 15000; i++)
3842                 udelay(10);
3843
3844         /* Deselect the channel register so we can read the PHYID
3845          * later.
3846          */
3847         tg3_writephy(tp, 0x10, 0x8011);
3848 }
3849
3850 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3851 {
3852         u16 flowctrl;
3853         u32 sg_dig_ctrl, sg_dig_status;
3854         u32 serdes_cfg, expected_sg_dig_ctrl;
3855         int workaround, port_a;
3856         int current_link_up;
3857
3858         serdes_cfg = 0;
3859         expected_sg_dig_ctrl = 0;
3860         workaround = 0;
3861         port_a = 1;
3862         current_link_up = 0;
3863
3864         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3865             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3866                 workaround = 1;
3867                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3868                         port_a = 0;
3869
3870                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3871                 /* preserve bits 20-23 for voltage regulator */
3872                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3873         }
3874
3875         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3876
3877         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3878                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3879                         if (workaround) {
3880                                 u32 val = serdes_cfg;
3881
3882                                 if (port_a)
3883                                         val |= 0xc010000;
3884                                 else
3885                                         val |= 0x4010000;
3886                                 tw32_f(MAC_SERDES_CFG, val);
3887                         }
3888
3889                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3890                 }
3891                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3892                         tg3_setup_flow_control(tp, 0, 0);
3893                         current_link_up = 1;
3894                 }
3895                 goto out;
3896         }
3897
3898         /* Want auto-negotiation.  */
3899         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3900
3901         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3902         if (flowctrl & ADVERTISE_1000XPAUSE)
3903                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3904         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3905                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3906
3907         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3908                 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3909                     tp->serdes_counter &&
3910                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3911                                     MAC_STATUS_RCVD_CFG)) ==
3912                      MAC_STATUS_PCS_SYNCED)) {
3913                         tp->serdes_counter--;
3914                         current_link_up = 1;
3915                         goto out;
3916                 }
3917 restart_autoneg:
3918                 if (workaround)
3919                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3920                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3921                 udelay(5);
3922                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3923
3924                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3925                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3926         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3927                                  MAC_STATUS_SIGNAL_DET)) {
3928                 sg_dig_status = tr32(SG_DIG_STATUS);
3929                 mac_status = tr32(MAC_STATUS);
3930
3931                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3932                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3933                         u32 local_adv = 0, remote_adv = 0;
3934
3935                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3936                                 local_adv |= ADVERTISE_1000XPAUSE;
3937                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3938                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3939
3940                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3941                                 remote_adv |= LPA_1000XPAUSE;
3942                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3943                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3944
3945                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3946                         current_link_up = 1;
3947                         tp->serdes_counter = 0;
3948                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3949                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3950                         if (tp->serdes_counter)
3951                                 tp->serdes_counter--;
3952                         else {
3953                                 if (workaround) {
3954                                         u32 val = serdes_cfg;
3955
3956                                         if (port_a)
3957                                                 val |= 0xc010000;
3958                                         else
3959                                                 val |= 0x4010000;
3960
3961                                         tw32_f(MAC_SERDES_CFG, val);
3962                                 }
3963
3964                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3965                                 udelay(40);
3966
3967                                 /* Link parallel detection - link is up */
3968                                 /* only if we have PCS_SYNC and not */
3969                                 /* receiving config code words */
3970                                 mac_status = tr32(MAC_STATUS);
3971                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3972                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3973                                         tg3_setup_flow_control(tp, 0, 0);
3974                                         current_link_up = 1;
3975                                         tp->phy_flags |=
3976                                                 TG3_PHYFLG_PARALLEL_DETECT;
3977                                         tp->serdes_counter =
3978                                                 SERDES_PARALLEL_DET_TIMEOUT;
3979                                 } else
3980                                         goto restart_autoneg;
3981                         }
3982                 }
3983         } else {
3984                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3985                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3986         }
3987
3988 out:
3989         return current_link_up;
3990 }
3991
3992 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3993 {
3994         int current_link_up = 0;
3995
3996         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3997                 goto out;
3998
3999         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4000                 u32 txflags, rxflags;
4001                 int i;
4002
4003                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
4004                         u32 local_adv = 0, remote_adv = 0;
4005
4006                         if (txflags & ANEG_CFG_PS1)
4007                                 local_adv |= ADVERTISE_1000XPAUSE;
4008                         if (txflags & ANEG_CFG_PS2)
4009                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
4010
4011                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
4012                                 remote_adv |= LPA_1000XPAUSE;
4013                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
4014                                 remote_adv |= LPA_1000XPAUSE_ASYM;
4015
4016                         tg3_setup_flow_control(tp, local_adv, remote_adv);
4017
4018                         current_link_up = 1;
4019                 }
4020                 for (i = 0; i < 30; i++) {
4021                         udelay(20);
4022                         tw32_f(MAC_STATUS,
4023                                (MAC_STATUS_SYNC_CHANGED |
4024                                 MAC_STATUS_CFG_CHANGED));
4025                         udelay(40);
4026                         if ((tr32(MAC_STATUS) &
4027                              (MAC_STATUS_SYNC_CHANGED |
4028                               MAC_STATUS_CFG_CHANGED)) == 0)
4029                                 break;
4030                 }
4031
4032                 mac_status = tr32(MAC_STATUS);
4033                 if (current_link_up == 0 &&
4034                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
4035                     !(mac_status & MAC_STATUS_RCVD_CFG))
4036                         current_link_up = 1;
4037         } else {
4038                 tg3_setup_flow_control(tp, 0, 0);
4039
4040                 /* Forcing 1000FD link up. */
4041                 current_link_up = 1;
4042
4043                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
4044                 udelay(40);
4045
4046                 tw32_f(MAC_MODE, tp->mac_mode);
4047                 udelay(40);
4048         }
4049
4050 out:
4051         return current_link_up;
4052 }
4053
4054 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4055 {
4056         u32 orig_pause_cfg;
4057         u16 orig_active_speed;
4058         u8 orig_active_duplex;
4059         u32 mac_status;
4060         int current_link_up;
4061         int i;
4062
4063         orig_pause_cfg = tp->link_config.active_flowctrl;
4064         orig_active_speed = tp->link_config.active_speed;
4065         orig_active_duplex = tp->link_config.active_duplex;
4066
4067         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
4068             netif_carrier_ok(tp->dev) &&
4069             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
4070                 mac_status = tr32(MAC_STATUS);
4071                 mac_status &= (MAC_STATUS_PCS_SYNCED |
4072                                MAC_STATUS_SIGNAL_DET |
4073                                MAC_STATUS_CFG_CHANGED |
4074                                MAC_STATUS_RCVD_CFG);
4075                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
4076                                    MAC_STATUS_SIGNAL_DET)) {
4077                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4078                                             MAC_STATUS_CFG_CHANGED));
4079                         return 0;
4080                 }
4081         }
4082
4083         tw32_f(MAC_TX_AUTO_NEG, 0);
4084
4085         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
4086         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
4087         tw32_f(MAC_MODE, tp->mac_mode);
4088         udelay(40);
4089
4090         if (tp->phy_id == TG3_PHY_ID_BCM8002)
4091                 tg3_init_bcm8002(tp);
4092
4093         /* Enable link change event even when serdes polling.  */
4094         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4095         udelay(40);
4096
4097         current_link_up = 0;
4098         mac_status = tr32(MAC_STATUS);
4099
4100         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
4101                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4102         else
4103                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4104
4105         tp->napi[0].hw_status->status =
4106                 (SD_STATUS_UPDATED |
4107                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4108
4109         for (i = 0; i < 100; i++) {
4110                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4111                                     MAC_STATUS_CFG_CHANGED));
4112                 udelay(5);
4113                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4114                                          MAC_STATUS_CFG_CHANGED |
4115                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4116                         break;
4117         }
4118
4119         mac_status = tr32(MAC_STATUS);
4120         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4121                 current_link_up = 0;
4122                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4123                     tp->serdes_counter == 0) {
4124                         tw32_f(MAC_MODE, (tp->mac_mode |
4125                                           MAC_MODE_SEND_CONFIGS));
4126                         udelay(1);
4127                         tw32_f(MAC_MODE, tp->mac_mode);
4128                 }
4129         }
4130
4131         if (current_link_up == 1) {
4132                 tp->link_config.active_speed = SPEED_1000;
4133                 tp->link_config.active_duplex = DUPLEX_FULL;
4134                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4135                                     LED_CTRL_LNKLED_OVERRIDE |
4136                                     LED_CTRL_1000MBPS_ON));
4137         } else {
4138                 tp->link_config.active_speed = SPEED_INVALID;
4139                 tp->link_config.active_duplex = DUPLEX_INVALID;
4140                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4141                                     LED_CTRL_LNKLED_OVERRIDE |
4142                                     LED_CTRL_TRAFFIC_OVERRIDE));
4143         }
4144
4145         if (current_link_up != netif_carrier_ok(tp->dev)) {
4146                 if (current_link_up)
4147                         netif_carrier_on(tp->dev);
4148                 else
4149                         netif_carrier_off(tp->dev);
4150                 tg3_link_report(tp);
4151         } else {
4152                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4153                 if (orig_pause_cfg != now_pause_cfg ||
4154                     orig_active_speed != tp->link_config.active_speed ||
4155                     orig_active_duplex != tp->link_config.active_duplex)
4156                         tg3_link_report(tp);
4157         }
4158
4159         return 0;
4160 }
4161
4162 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4163 {
4164         int current_link_up, err = 0;
4165         u32 bmsr, bmcr;
4166         u16 current_speed;
4167         u8 current_duplex;
4168         u32 local_adv, remote_adv;
4169
4170         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4171         tw32_f(MAC_MODE, tp->mac_mode);
4172         udelay(40);
4173
4174         tw32(MAC_EVENT, 0);
4175
4176         tw32_f(MAC_STATUS,
4177              (MAC_STATUS_SYNC_CHANGED |
4178               MAC_STATUS_CFG_CHANGED |
4179               MAC_STATUS_MI_COMPLETION |
4180               MAC_STATUS_LNKSTATE_CHANGED));
4181         udelay(40);
4182
4183         if (force_reset)
4184                 tg3_phy_reset(tp);
4185
4186         current_link_up = 0;
4187         current_speed = SPEED_INVALID;
4188         current_duplex = DUPLEX_INVALID;
4189
4190         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4191         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4192         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4193                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4194                         bmsr |= BMSR_LSTATUS;
4195                 else
4196                         bmsr &= ~BMSR_LSTATUS;
4197         }
4198
4199         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4200
4201         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4202             (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4203                 /* do nothing, just check for link up at the end */
4204         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4205                 u32 adv, new_adv;
4206
4207                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4208                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4209                                   ADVERTISE_1000XPAUSE |
4210                                   ADVERTISE_1000XPSE_ASYM |
4211                                   ADVERTISE_SLCT);
4212
4213                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4214
4215                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4216                         new_adv |= ADVERTISE_1000XHALF;
4217                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4218                         new_adv |= ADVERTISE_1000XFULL;
4219
4220                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4221                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4222                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4223                         tg3_writephy(tp, MII_BMCR, bmcr);
4224
4225                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4226                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4227                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4228
4229                         return err;
4230                 }
4231         } else {
4232                 u32 new_bmcr;
4233
4234                 bmcr &= ~BMCR_SPEED1000;
4235                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4236
4237                 if (tp->link_config.duplex == DUPLEX_FULL)
4238                         new_bmcr |= BMCR_FULLDPLX;
4239
4240                 if (new_bmcr != bmcr) {
4241                         /* BMCR_SPEED1000 is a reserved bit that needs
4242                          * to be set on write.
4243                          */
4244                         new_bmcr |= BMCR_SPEED1000;
4245
4246                         /* Force a linkdown */
4247                         if (netif_carrier_ok(tp->dev)) {
4248                                 u32 adv;
4249
4250                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4251                                 adv &= ~(ADVERTISE_1000XFULL |
4252                                          ADVERTISE_1000XHALF |
4253                                          ADVERTISE_SLCT);
4254                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4255                                 tg3_writephy(tp, MII_BMCR, bmcr |
4256                                                            BMCR_ANRESTART |
4257                                                            BMCR_ANENABLE);
4258                                 udelay(10);
4259                                 netif_carrier_off(tp->dev);
4260                         }
4261                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4262                         bmcr = new_bmcr;
4263                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4264                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4265                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4266                             ASIC_REV_5714) {
4267                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4268                                         bmsr |= BMSR_LSTATUS;
4269                                 else
4270                                         bmsr &= ~BMSR_LSTATUS;
4271                         }
4272                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4273                 }
4274         }
4275
4276         if (bmsr & BMSR_LSTATUS) {
4277                 current_speed = SPEED_1000;
4278                 current_link_up = 1;
4279                 if (bmcr & BMCR_FULLDPLX)
4280                         current_duplex = DUPLEX_FULL;
4281                 else
4282                         current_duplex = DUPLEX_HALF;
4283
4284                 local_adv = 0;
4285                 remote_adv = 0;
4286
4287                 if (bmcr & BMCR_ANENABLE) {
4288                         u32 common;
4289
4290                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4291                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4292                         common = local_adv & remote_adv;
4293                         if (common & (ADVERTISE_1000XHALF |
4294                                       ADVERTISE_1000XFULL)) {
4295                                 if (common & ADVERTISE_1000XFULL)
4296                                         current_duplex = DUPLEX_FULL;
4297                                 else
4298                                         current_duplex = DUPLEX_HALF;
4299                         } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4300                                 /* Link is up via parallel detect */
4301                         } else {
4302                                 current_link_up = 0;
4303                         }
4304                 }
4305         }
4306
4307         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4308                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4309
4310         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4311         if (tp->link_config.active_duplex == DUPLEX_HALF)
4312                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4313
4314         tw32_f(MAC_MODE, tp->mac_mode);
4315         udelay(40);
4316
4317         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4318
4319         tp->link_config.active_speed = current_speed;
4320         tp->link_config.active_duplex = current_duplex;
4321
4322         if (current_link_up != netif_carrier_ok(tp->dev)) {
4323                 if (current_link_up)
4324                         netif_carrier_on(tp->dev);
4325                 else {
4326                         netif_carrier_off(tp->dev);
4327                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4328                 }
4329                 tg3_link_report(tp);
4330         }
4331         return err;
4332 }
4333
4334 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4335 {
4336         if (tp->serdes_counter) {
4337                 /* Give autoneg time to complete. */
4338                 tp->serdes_counter--;
4339                 return;
4340         }
4341
4342         if (!netif_carrier_ok(tp->dev) &&
4343             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4344                 u32 bmcr;
4345
4346                 tg3_readphy(tp, MII_BMCR, &bmcr);
4347                 if (bmcr & BMCR_ANENABLE) {
4348                         u32 phy1, phy2;
4349
4350                         /* Select shadow register 0x1f */
4351                         tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4352                         tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4353
4354                         /* Select expansion interrupt status register */
4355                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4356                                          MII_TG3_DSP_EXP1_INT_STAT);
4357                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4358                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4359
4360                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4361                                 /* We have signal detect and not receiving
4362                                  * config code words, link is up by parallel
4363                                  * detection.
4364                                  */
4365
4366                                 bmcr &= ~BMCR_ANENABLE;
4367                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4368                                 tg3_writephy(tp, MII_BMCR, bmcr);
4369                                 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4370                         }
4371                 }
4372         } else if (netif_carrier_ok(tp->dev) &&
4373                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4374                    (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4375                 u32 phy2;
4376
4377                 /* Select expansion interrupt status register */
4378                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4379                                  MII_TG3_DSP_EXP1_INT_STAT);
4380                 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4381                 if (phy2 & 0x20) {
4382                         u32 bmcr;
4383
4384                         /* Config code words received, turn on autoneg. */
4385                         tg3_readphy(tp, MII_BMCR, &bmcr);
4386                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4387
4388                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4389
4390                 }
4391         }
4392 }
4393
4394 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4395 {
4396         int err;
4397
4398         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4399                 err = tg3_setup_fiber_phy(tp, force_reset);
4400         else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4401                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4402         else
4403                 err = tg3_setup_copper_phy(tp, force_reset);
4404
4405         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4406                 u32 val, scale;
4407
4408                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4409                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4410                         scale = 65;
4411                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4412                         scale = 6;
4413                 else
4414                         scale = 12;
4415
4416                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4417                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4418                 tw32(GRC_MISC_CFG, val);
4419         }
4420
4421         if (tp->link_config.active_speed == SPEED_1000 &&
4422             tp->link_config.active_duplex == DUPLEX_HALF)
4423                 tw32(MAC_TX_LENGTHS,
4424                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4425                       (6 << TX_LENGTHS_IPG_SHIFT) |
4426                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4427         else
4428                 tw32(MAC_TX_LENGTHS,
4429                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4430                       (6 << TX_LENGTHS_IPG_SHIFT) |
4431                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4432
4433         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4434                 if (netif_carrier_ok(tp->dev)) {
4435                         tw32(HOSTCC_STAT_COAL_TICKS,
4436                              tp->coal.stats_block_coalesce_usecs);
4437                 } else {
4438                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4439                 }
4440         }
4441
4442         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4443                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4444                 if (!netif_carrier_ok(tp->dev))
4445                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4446                               tp->pwrmgmt_thresh;
4447                 else
4448                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4449                 tw32(PCIE_PWR_MGMT_THRESH, val);
4450         }
4451
4452         return err;
4453 }
4454
4455 static inline int tg3_irq_sync(struct tg3 *tp)
4456 {
4457         return tp->irq_sync;
4458 }
4459
4460 /* This is called whenever we suspect that the system chipset is re-
4461  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4462  * is bogus tx completions. We try to recover by setting the
4463  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4464  * in the workqueue.
4465  */
4466 static void tg3_tx_recover(struct tg3 *tp)
4467 {
4468         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4469                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4470
4471         netdev_warn(tp->dev,
4472                     "The system may be re-ordering memory-mapped I/O "
4473                     "cycles to the network device, attempting to recover. "
4474                     "Please report the problem to the driver maintainer "
4475                     "and include system chipset information.\n");
4476
4477         spin_lock(&tp->lock);
4478         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4479         spin_unlock(&tp->lock);
4480 }
4481
4482 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4483 {
4484         /* Tell compiler to fetch tx indices from memory. */
4485         barrier();
4486         return tnapi->tx_pending -
4487                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4488 }
4489
4490 /* Tigon3 never reports partial packet sends.  So we do not
4491  * need special logic to handle SKBs that have not had all
4492  * of their frags sent yet, like SunGEM does.
4493  */
4494 static void tg3_tx(struct tg3_napi *tnapi)
4495 {
4496         struct tg3 *tp = tnapi->tp;
4497         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4498         u32 sw_idx = tnapi->tx_cons;
4499         struct netdev_queue *txq;
4500         int index = tnapi - tp->napi;
4501
4502         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4503                 index--;
4504
4505         txq = netdev_get_tx_queue(tp->dev, index);
4506
4507         while (sw_idx != hw_idx) {
4508                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4509                 struct sk_buff *skb = ri->skb;
4510                 int i, tx_bug = 0;
4511
4512                 if (unlikely(skb == NULL)) {
4513                         tg3_tx_recover(tp);
4514                         return;
4515                 }
4516
4517                 pci_unmap_single(tp->pdev,
4518                                  dma_unmap_addr(ri, mapping),
4519                                  skb_headlen(skb),
4520                                  PCI_DMA_TODEVICE);
4521
4522                 ri->skb = NULL;
4523
4524                 sw_idx = NEXT_TX(sw_idx);
4525
4526                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4527                         ri = &tnapi->tx_buffers[sw_idx];
4528                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4529                                 tx_bug = 1;
4530
4531                         pci_unmap_page(tp->pdev,
4532                                        dma_unmap_addr(ri, mapping),
4533                                        skb_shinfo(skb)->frags[i].size,
4534                                        PCI_DMA_TODEVICE);
4535                         sw_idx = NEXT_TX(sw_idx);
4536                 }
4537
4538                 dev_kfree_skb(skb);
4539
4540                 if (unlikely(tx_bug)) {
4541                         tg3_tx_recover(tp);
4542                         return;
4543                 }
4544         }
4545
4546         tnapi->tx_cons = sw_idx;
4547
4548         /* Need to make the tx_cons update visible to tg3_start_xmit()
4549          * before checking for netif_queue_stopped().  Without the
4550          * memory barrier, there is a small possibility that tg3_start_xmit()
4551          * will miss it and cause the queue to be stopped forever.
4552          */
4553         smp_mb();
4554
4555         if (unlikely(netif_tx_queue_stopped(txq) &&
4556                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4557                 __netif_tx_lock(txq, smp_processor_id());
4558                 if (netif_tx_queue_stopped(txq) &&
4559                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4560                         netif_tx_wake_queue(txq);
4561                 __netif_tx_unlock(txq);
4562         }
4563 }
4564
4565 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4566 {
4567         if (!ri->skb)
4568                 return;
4569
4570         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4571                          map_sz, PCI_DMA_FROMDEVICE);
4572         dev_kfree_skb_any(ri->skb);
4573         ri->skb = NULL;
4574 }
4575
4576 /* Returns size of skb allocated or < 0 on error.
4577  *
4578  * We only need to fill in the address because the other members
4579  * of the RX descriptor are invariant, see tg3_init_rings.
4580  *
4581  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4582  * posting buffers we only dirty the first cache line of the RX
4583  * descriptor (containing the address).  Whereas for the RX status
4584  * buffers the cpu only reads the last cacheline of the RX descriptor
4585  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4586  */
4587 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4588                             u32 opaque_key, u32 dest_idx_unmasked)
4589 {
4590         struct tg3_rx_buffer_desc *desc;
4591         struct ring_info *map;
4592         struct sk_buff *skb;
4593         dma_addr_t mapping;
4594         int skb_size, dest_idx;
4595
4596         switch (opaque_key) {
4597         case RXD_OPAQUE_RING_STD:
4598                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4599                 desc = &tpr->rx_std[dest_idx];
4600                 map = &tpr->rx_std_buffers[dest_idx];
4601                 skb_size = tp->rx_pkt_map_sz;
4602                 break;
4603
4604         case RXD_OPAQUE_RING_JUMBO:
4605                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4606                 desc = &tpr->rx_jmb[dest_idx].std;
4607                 map = &tpr->rx_jmb_buffers[dest_idx];
4608                 skb_size = TG3_RX_JMB_MAP_SZ;
4609                 break;
4610
4611         default:
4612                 return -EINVAL;
4613         }
4614
4615         /* Do not overwrite any of the map or rp information
4616          * until we are sure we can commit to a new buffer.
4617          *
4618          * Callers depend upon this behavior and assume that
4619          * we leave everything unchanged if we fail.
4620          */
4621         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4622         if (skb == NULL)
4623                 return -ENOMEM;
4624
4625         skb_reserve(skb, tp->rx_offset);
4626
4627         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4628                                  PCI_DMA_FROMDEVICE);
4629         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4630                 dev_kfree_skb(skb);
4631                 return -EIO;
4632         }
4633
4634         map->skb = skb;
4635         dma_unmap_addr_set(map, mapping, mapping);
4636
4637         desc->addr_hi = ((u64)mapping >> 32);
4638         desc->addr_lo = ((u64)mapping & 0xffffffff);
4639
4640         return skb_size;
4641 }
4642
4643 /* We only need to move over in the address because the other
4644  * members of the RX descriptor are invariant.  See notes above
4645  * tg3_alloc_rx_skb for full details.
4646  */
4647 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4648                            struct tg3_rx_prodring_set *dpr,
4649                            u32 opaque_key, int src_idx,
4650                            u32 dest_idx_unmasked)
4651 {
4652         struct tg3 *tp = tnapi->tp;
4653         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4654         struct ring_info *src_map, *dest_map;
4655         struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
4656         int dest_idx;
4657
4658         switch (opaque_key) {
4659         case RXD_OPAQUE_RING_STD:
4660                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4661                 dest_desc = &dpr->rx_std[dest_idx];
4662                 dest_map = &dpr->rx_std_buffers[dest_idx];
4663                 src_desc = &spr->rx_std[src_idx];
4664                 src_map = &spr->rx_std_buffers[src_idx];
4665                 break;
4666
4667         case RXD_OPAQUE_RING_JUMBO:
4668                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4669                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4670                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4671                 src_desc = &spr->rx_jmb[src_idx].std;
4672                 src_map = &spr->rx_jmb_buffers[src_idx];
4673                 break;
4674
4675         default:
4676                 return;
4677         }
4678
4679         dest_map->skb = src_map->skb;
4680         dma_unmap_addr_set(dest_map, mapping,
4681                            dma_unmap_addr(src_map, mapping));
4682         dest_desc->addr_hi = src_desc->addr_hi;
4683         dest_desc->addr_lo = src_desc->addr_lo;
4684
4685         /* Ensure that the update to the skb happens after the physical
4686          * addresses have been transferred to the new BD location.
4687          */
4688         smp_wmb();
4689
4690         src_map->skb = NULL;
4691 }
4692
4693 /* The RX ring scheme is composed of multiple rings which post fresh
4694  * buffers to the chip, and one special ring the chip uses to report
4695  * status back to the host.
4696  *
4697  * The special ring reports the status of received packets to the
4698  * host.  The chip does not write into the original descriptor the
4699  * RX buffer was obtained from.  The chip simply takes the original
4700  * descriptor as provided by the host, updates the status and length
4701  * field, then writes this into the next status ring entry.
4702  *
4703  * Each ring the host uses to post buffers to the chip is described
4704  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4705  * it is first placed into the on-chip ram.  When the packet's length
4706  * is known, it walks down the TG3_BDINFO entries to select the ring.
4707  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4708  * which is within the range of the new packet's length is chosen.
4709  *
4710  * The "separate ring for rx status" scheme may sound queer, but it makes
4711  * sense from a cache coherency perspective.  If only the host writes
4712  * to the buffer post rings, and only the chip writes to the rx status
4713  * rings, then cache lines never move beyond shared-modified state.
4714  * If both the host and chip were to write into the same ring, cache line
4715  * eviction could occur since both entities want it in an exclusive state.
4716  */
4717 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4718 {
4719         struct tg3 *tp = tnapi->tp;
4720         u32 work_mask, rx_std_posted = 0;
4721         u32 std_prod_idx, jmb_prod_idx;
4722         u32 sw_idx = tnapi->rx_rcb_ptr;
4723         u16 hw_idx;
4724         int received;
4725         struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
4726
4727         hw_idx = *(tnapi->rx_rcb_prod_idx);
4728         /*
4729          * We need to order the read of hw_idx and the read of
4730          * the opaque cookie.
4731          */
4732         rmb();
4733         work_mask = 0;
4734         received = 0;
4735         std_prod_idx = tpr->rx_std_prod_idx;
4736         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4737         while (sw_idx != hw_idx && budget > 0) {
4738                 struct ring_info *ri;
4739                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4740                 unsigned int len;
4741                 struct sk_buff *skb;
4742                 dma_addr_t dma_addr;
4743                 u32 opaque_key, desc_idx, *post_ptr;
4744
4745                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4746                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4747                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4748                         ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4749                         dma_addr = dma_unmap_addr(ri, mapping);
4750                         skb = ri->skb;
4751                         post_ptr = &std_prod_idx;
4752                         rx_std_posted++;
4753                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4754                         ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4755                         dma_addr = dma_unmap_addr(ri, mapping);
4756                         skb = ri->skb;
4757                         post_ptr = &jmb_prod_idx;
4758                 } else
4759                         goto next_pkt_nopost;
4760
4761                 work_mask |= opaque_key;
4762
4763                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4764                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4765                 drop_it:
4766                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4767                                        desc_idx, *post_ptr);
4768                 drop_it_no_recycle:
4769                         /* Other statistics kept track of by card. */
4770                         tp->rx_dropped++;
4771                         goto next_pkt;
4772                 }
4773
4774                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4775                       ETH_FCS_LEN;
4776
4777                 if (len > TG3_RX_COPY_THRESH(tp)) {
4778                         int skb_size;
4779
4780                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4781                                                     *post_ptr);
4782                         if (skb_size < 0)
4783                                 goto drop_it;
4784
4785                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4786                                          PCI_DMA_FROMDEVICE);
4787
4788                         /* Ensure that the update to the skb happens
4789                          * after the usage of the old DMA mapping.
4790                          */
4791                         smp_wmb();
4792
4793                         ri->skb = NULL;
4794
4795                         skb_put(skb, len);
4796                 } else {
4797                         struct sk_buff *copy_skb;
4798
4799                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4800                                        desc_idx, *post_ptr);
4801
4802                         copy_skb = netdev_alloc_skb(tp->dev, len +
4803                                                     TG3_RAW_IP_ALIGN);
4804                         if (copy_skb == NULL)
4805                                 goto drop_it_no_recycle;
4806
4807                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4808                         skb_put(copy_skb, len);
4809                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4810                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4811                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4812
4813                         /* We'll reuse the original ring buffer. */
4814                         skb = copy_skb;
4815                 }
4816
4817                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4818                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4819                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4820                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4821                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4822                 else
4823                         skb_checksum_none_assert(skb);
4824
4825                 skb->protocol = eth_type_trans(skb, tp->dev);
4826
4827                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4828                     skb->protocol != htons(ETH_P_8021Q)) {
4829                         dev_kfree_skb(skb);
4830                         goto drop_it_no_recycle;
4831                 }
4832
4833                 if (desc->type_flags & RXD_FLAG_VLAN &&
4834                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
4835                         __vlan_hwaccel_put_tag(skb,
4836                                                desc->err_vlan & RXD_VLAN_MASK);
4837
4838                 napi_gro_receive(&tnapi->napi, skb);
4839
4840                 received++;
4841                 budget--;
4842
4843 next_pkt:
4844                 (*post_ptr)++;
4845
4846                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4847                         tpr->rx_std_prod_idx = std_prod_idx &
4848                                                tp->rx_std_ring_mask;
4849                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4850                                      tpr->rx_std_prod_idx);
4851                         work_mask &= ~RXD_OPAQUE_RING_STD;
4852                         rx_std_posted = 0;
4853                 }
4854 next_pkt_nopost:
4855                 sw_idx++;
4856                 sw_idx &= tp->rx_ret_ring_mask;
4857
4858                 /* Refresh hw_idx to see if there is new work */
4859                 if (sw_idx == hw_idx) {
4860                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4861                         rmb();
4862                 }
4863         }
4864
4865         /* ACK the status ring. */
4866         tnapi->rx_rcb_ptr = sw_idx;
4867         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4868
4869         /* Refill RX ring(s). */
4870         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4871                 if (work_mask & RXD_OPAQUE_RING_STD) {
4872                         tpr->rx_std_prod_idx = std_prod_idx &
4873                                                tp->rx_std_ring_mask;
4874                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4875                                      tpr->rx_std_prod_idx);
4876                 }
4877                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4878                         tpr->rx_jmb_prod_idx = jmb_prod_idx &
4879                                                tp->rx_jmb_ring_mask;
4880                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4881                                      tpr->rx_jmb_prod_idx);
4882                 }
4883                 mmiowb();
4884         } else if (work_mask) {
4885                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4886                  * updated before the producer indices can be updated.
4887                  */
4888                 smp_wmb();
4889
4890                 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
4891                 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
4892
4893                 if (tnapi != &tp->napi[1])
4894                         napi_schedule(&tp->napi[1].napi);
4895         }
4896
4897         return received;
4898 }
4899
4900 static void tg3_poll_link(struct tg3 *tp)
4901 {
4902         /* handle link change and other phy events */
4903         if (!(tp->tg3_flags &
4904               (TG3_FLAG_USE_LINKCHG_REG |
4905                TG3_FLAG_POLL_SERDES))) {
4906                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4907
4908                 if (sblk->status & SD_STATUS_LINK_CHG) {
4909                         sblk->status = SD_STATUS_UPDATED |
4910                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4911                         spin_lock(&tp->lock);
4912                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4913                                 tw32_f(MAC_STATUS,
4914                                      (MAC_STATUS_SYNC_CHANGED |
4915                                       MAC_STATUS_CFG_CHANGED |
4916                                       MAC_STATUS_MI_COMPLETION |
4917                                       MAC_STATUS_LNKSTATE_CHANGED));
4918                                 udelay(40);
4919                         } else
4920                                 tg3_setup_phy(tp, 0);
4921                         spin_unlock(&tp->lock);
4922                 }
4923         }
4924 }
4925
4926 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4927                                 struct tg3_rx_prodring_set *dpr,
4928                                 struct tg3_rx_prodring_set *spr)
4929 {
4930         u32 si, di, cpycnt, src_prod_idx;
4931         int i, err = 0;
4932
4933         while (1) {
4934                 src_prod_idx = spr->rx_std_prod_idx;
4935
4936                 /* Make sure updates to the rx_std_buffers[] entries and the
4937                  * standard producer index are seen in the correct order.
4938                  */
4939                 smp_rmb();
4940
4941                 if (spr->rx_std_cons_idx == src_prod_idx)
4942                         break;
4943
4944                 if (spr->rx_std_cons_idx < src_prod_idx)
4945                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4946                 else
4947                         cpycnt = tp->rx_std_ring_mask + 1 -
4948                                  spr->rx_std_cons_idx;
4949
4950                 cpycnt = min(cpycnt,
4951                              tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
4952
4953                 si = spr->rx_std_cons_idx;
4954                 di = dpr->rx_std_prod_idx;
4955
4956                 for (i = di; i < di + cpycnt; i++) {
4957                         if (dpr->rx_std_buffers[i].skb) {
4958                                 cpycnt = i - di;
4959                                 err = -ENOSPC;
4960                                 break;
4961                         }
4962                 }
4963
4964                 if (!cpycnt)
4965                         break;
4966
4967                 /* Ensure that updates to the rx_std_buffers ring and the
4968                  * shadowed hardware producer ring from tg3_recycle_skb() are
4969                  * ordered correctly WRT the skb check above.
4970                  */
4971                 smp_rmb();
4972
4973                 memcpy(&dpr->rx_std_buffers[di],
4974                        &spr->rx_std_buffers[si],
4975                        cpycnt * sizeof(struct ring_info));
4976
4977                 for (i = 0; i < cpycnt; i++, di++, si++) {
4978                         struct tg3_rx_buffer_desc *sbd, *dbd;
4979                         sbd = &spr->rx_std[si];
4980                         dbd = &dpr->rx_std[di];
4981                         dbd->addr_hi = sbd->addr_hi;
4982                         dbd->addr_lo = sbd->addr_lo;
4983                 }
4984
4985                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
4986                                        tp->rx_std_ring_mask;
4987                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
4988                                        tp->rx_std_ring_mask;
4989         }
4990
4991         while (1) {
4992                 src_prod_idx = spr->rx_jmb_prod_idx;
4993
4994                 /* Make sure updates to the rx_jmb_buffers[] entries and
4995                  * the jumbo producer index are seen in the correct order.
4996                  */
4997                 smp_rmb();
4998
4999                 if (spr->rx_jmb_cons_idx == src_prod_idx)
5000                         break;
5001
5002                 if (spr->rx_jmb_cons_idx < src_prod_idx)
5003                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
5004                 else
5005                         cpycnt = tp->rx_jmb_ring_mask + 1 -
5006                                  spr->rx_jmb_cons_idx;
5007
5008                 cpycnt = min(cpycnt,
5009                              tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
5010
5011                 si = spr->rx_jmb_cons_idx;
5012                 di = dpr->rx_jmb_prod_idx;
5013
5014                 for (i = di; i < di + cpycnt; i++) {
5015                         if (dpr->rx_jmb_buffers[i].skb) {
5016                                 cpycnt = i - di;
5017                                 err = -ENOSPC;
5018                                 break;
5019                         }
5020                 }
5021
5022                 if (!cpycnt)
5023                         break;
5024
5025                 /* Ensure that updates to the rx_jmb_buffers ring and the
5026                  * shadowed hardware producer ring from tg3_recycle_skb() are
5027                  * ordered correctly WRT the skb check above.
5028                  */
5029                 smp_rmb();
5030
5031                 memcpy(&dpr->rx_jmb_buffers[di],
5032                        &spr->rx_jmb_buffers[si],
5033                        cpycnt * sizeof(struct ring_info));
5034
5035                 for (i = 0; i < cpycnt; i++, di++, si++) {
5036                         struct tg3_rx_buffer_desc *sbd, *dbd;
5037                         sbd = &spr->rx_jmb[si].std;
5038                         dbd = &dpr->rx_jmb[di].std;
5039                         dbd->addr_hi = sbd->addr_hi;
5040                         dbd->addr_lo = sbd->addr_lo;
5041                 }
5042
5043                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
5044                                        tp->rx_jmb_ring_mask;
5045                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
5046                                        tp->rx_jmb_ring_mask;
5047         }
5048
5049         return err;
5050 }
5051
5052 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
5053 {
5054         struct tg3 *tp = tnapi->tp;
5055
5056         /* run TX completion thread */
5057         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
5058                 tg3_tx(tnapi);
5059                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5060                         return work_done;
5061         }
5062
5063         /* run RX thread, within the bounds set by NAPI.
5064          * All RX "locking" is done by ensuring outside
5065          * code synchronizes with tg3->napi.poll()
5066          */
5067         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
5068                 work_done += tg3_rx(tnapi, budget - work_done);
5069
5070         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
5071                 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
5072                 int i, err = 0;
5073                 u32 std_prod_idx = dpr->rx_std_prod_idx;
5074                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
5075
5076                 for (i = 1; i < tp->irq_cnt; i++)
5077                         err |= tg3_rx_prodring_xfer(tp, dpr,
5078                                                     &tp->napi[i].prodring);
5079
5080                 wmb();
5081
5082                 if (std_prod_idx != dpr->rx_std_prod_idx)
5083                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5084                                      dpr->rx_std_prod_idx);
5085
5086                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5087                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5088                                      dpr->rx_jmb_prod_idx);
5089
5090                 mmiowb();
5091
5092                 if (err)
5093                         tw32_f(HOSTCC_MODE, tp->coal_now);
5094         }
5095
5096         return work_done;
5097 }
5098
5099 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5100 {
5101         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5102         struct tg3 *tp = tnapi->tp;
5103         int work_done = 0;
5104         struct tg3_hw_status *sblk = tnapi->hw_status;
5105
5106         while (1) {
5107                 work_done = tg3_poll_work(tnapi, work_done, budget);
5108
5109                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5110                         goto tx_recovery;
5111
5112                 if (unlikely(work_done >= budget))
5113                         break;
5114
5115                 /* tp->last_tag is used in tg3_int_reenable() below
5116                  * to tell the hw how much work has been processed,
5117                  * so we must read it before checking for more work.
5118                  */
5119                 tnapi->last_tag = sblk->status_tag;
5120                 tnapi->last_irq_tag = tnapi->last_tag;
5121                 rmb();
5122
5123                 /* check for RX/TX work to do */
5124                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5125                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5126                         napi_complete(napi);
5127                         /* Reenable interrupts. */
5128                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5129                         mmiowb();
5130                         break;
5131                 }
5132         }
5133
5134         return work_done;
5135
5136 tx_recovery:
5137         /* work_done is guaranteed to be less than budget. */
5138         napi_complete(napi);
5139         schedule_work(&tp->reset_task);
5140         return work_done;
5141 }
5142
5143 static int tg3_poll(struct napi_struct *napi, int budget)
5144 {
5145         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5146         struct tg3 *tp = tnapi->tp;
5147         int work_done = 0;
5148         struct tg3_hw_status *sblk = tnapi->hw_status;
5149
5150         while (1) {
5151                 tg3_poll_link(tp);
5152
5153                 work_done = tg3_poll_work(tnapi, work_done, budget);
5154
5155                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5156                         goto tx_recovery;
5157
5158                 if (unlikely(work_done >= budget))
5159                         break;
5160
5161                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5162                         /* tp->last_tag is used in tg3_int_reenable() below
5163                          * to tell the hw how much work has been processed,
5164                          * so we must read it before checking for more work.
5165                          */
5166                         tnapi->last_tag = sblk->status_tag;
5167                         tnapi->last_irq_tag = tnapi->last_tag;
5168                         rmb();
5169                 } else
5170                         sblk->status &= ~SD_STATUS_UPDATED;
5171
5172                 if (likely(!tg3_has_work(tnapi))) {
5173                         napi_complete(napi);
5174                         tg3_int_reenable(tnapi);
5175                         break;
5176                 }
5177         }
5178
5179         return work_done;
5180
5181 tx_recovery:
5182         /* work_done is guaranteed to be less than budget. */
5183         napi_complete(napi);
5184         schedule_work(&tp->reset_task);
5185         return work_done;
5186 }
5187
5188 static void tg3_napi_disable(struct tg3 *tp)
5189 {
5190         int i;
5191
5192         for (i = tp->irq_cnt - 1; i >= 0; i--)
5193                 napi_disable(&tp->napi[i].napi);
5194 }
5195
5196 static void tg3_napi_enable(struct tg3 *tp)
5197 {
5198         int i;
5199
5200         for (i = 0; i < tp->irq_cnt; i++)
5201                 napi_enable(&tp->napi[i].napi);
5202 }
5203
5204 static void tg3_napi_init(struct tg3 *tp)
5205 {
5206         int i;
5207
5208         netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
5209         for (i = 1; i < tp->irq_cnt; i++)
5210                 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
5211 }
5212
5213 static void tg3_napi_fini(struct tg3 *tp)
5214 {
5215         int i;
5216
5217         for (i = 0; i < tp->irq_cnt; i++)
5218                 netif_napi_del(&tp->napi[i].napi);
5219 }
5220
5221 static inline void tg3_netif_stop(struct tg3 *tp)
5222 {
5223         tp->dev->trans_start = jiffies; /* prevent tx timeout */
5224         tg3_napi_disable(tp);
5225         netif_tx_disable(tp->dev);
5226 }
5227
5228 static inline void tg3_netif_start(struct tg3 *tp)
5229 {
5230         /* NOTE: unconditional netif_tx_wake_all_queues is only
5231          * appropriate so long as all callers are assured to
5232          * have free tx slots (such as after tg3_init_hw)
5233          */
5234         netif_tx_wake_all_queues(tp->dev);
5235
5236         tg3_napi_enable(tp);
5237         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
5238         tg3_enable_ints(tp);
5239 }
5240
5241 static void tg3_irq_quiesce(struct tg3 *tp)
5242 {
5243         int i;
5244
5245         BUG_ON(tp->irq_sync);
5246
5247         tp->irq_sync = 1;
5248         smp_mb();
5249
5250         for (i = 0; i < tp->irq_cnt; i++)
5251                 synchronize_irq(tp->napi[i].irq_vec);
5252 }
5253
5254 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5255  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5256  * with as well.  Most of the time, this is not necessary except when
5257  * shutting down the device.
5258  */
5259 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5260 {
5261         spin_lock_bh(&tp->lock);
5262         if (irq_sync)
5263                 tg3_irq_quiesce(tp);
5264 }
5265
5266 static inline void tg3_full_unlock(struct tg3 *tp)
5267 {
5268         spin_unlock_bh(&tp->lock);
5269 }
5270
5271 /* One-shot MSI handler - Chip automatically disables interrupt
5272  * after sending MSI so driver doesn't have to do it.
5273  */
5274 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5275 {
5276         struct tg3_napi *tnapi = dev_id;
5277         struct tg3 *tp = tnapi->tp;
5278
5279         prefetch(tnapi->hw_status);
5280         if (tnapi->rx_rcb)
5281                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5282
5283         if (likely(!tg3_irq_sync(tp)))
5284                 napi_schedule(&tnapi->napi);
5285
5286         return IRQ_HANDLED;
5287 }
5288
5289 /* MSI ISR - No need to check for interrupt sharing and no need to
5290  * flush status block and interrupt mailbox. PCI ordering rules
5291  * guarantee that MSI will arrive after the status block.
5292  */
5293 static irqreturn_t tg3_msi(int irq, void *dev_id)
5294 {
5295         struct tg3_napi *tnapi = dev_id;
5296         struct tg3 *tp = tnapi->tp;
5297
5298         prefetch(tnapi->hw_status);
5299         if (tnapi->rx_rcb)
5300                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5301         /*
5302          * Writing any value to intr-mbox-0 clears PCI INTA# and
5303          * chip-internal interrupt pending events.
5304          * Writing non-zero to intr-mbox-0 additional tells the
5305          * NIC to stop sending us irqs, engaging "in-intr-handler"
5306          * event coalescing.
5307          */
5308         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5309         if (likely(!tg3_irq_sync(tp)))
5310                 napi_schedule(&tnapi->napi);
5311
5312         return IRQ_RETVAL(1);
5313 }
5314
5315 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5316 {
5317         struct tg3_napi *tnapi = dev_id;
5318         struct tg3 *tp = tnapi->tp;
5319         struct tg3_hw_status *sblk = tnapi->hw_status;
5320         unsigned int handled = 1;
5321
5322         /* In INTx mode, it is possible for the interrupt to arrive at
5323          * the CPU before the status block posted prior to the interrupt.
5324          * Reading the PCI State register will confirm whether the
5325          * interrupt is ours and will flush the status block.
5326          */
5327         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5328                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5329                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5330                         handled = 0;
5331                         goto out;
5332                 }
5333         }
5334
5335         /*
5336          * Writing any value to intr-mbox-0 clears PCI INTA# and
5337          * chip-internal interrupt pending events.
5338          * Writing non-zero to intr-mbox-0 additional tells the
5339          * NIC to stop sending us irqs, engaging "in-intr-handler"
5340          * event coalescing.
5341          *
5342          * Flush the mailbox to de-assert the IRQ immediately to prevent
5343          * spurious interrupts.  The flush impacts performance but
5344          * excessive spurious interrupts can be worse in some cases.
5345          */
5346         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5347         if (tg3_irq_sync(tp))
5348                 goto out;
5349         sblk->status &= ~SD_STATUS_UPDATED;
5350         if (likely(tg3_has_work(tnapi))) {
5351                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5352                 napi_schedule(&tnapi->napi);
5353         } else {
5354                 /* No work, shared interrupt perhaps?  re-enable
5355                  * interrupts, and flush that PCI write
5356                  */
5357                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5358                                0x00000000);
5359         }
5360 out:
5361         return IRQ_RETVAL(handled);
5362 }
5363
5364 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5365 {
5366         struct tg3_napi *tnapi = dev_id;
5367         struct tg3 *tp = tnapi->tp;
5368         struct tg3_hw_status *sblk = tnapi->hw_status;
5369         unsigned int handled = 1;
5370
5371         /* In INTx mode, it is possible for the interrupt to arrive at
5372          * the CPU before the status block posted prior to the interrupt.
5373          * Reading the PCI State register will confirm whether the
5374          * interrupt is ours and will flush the status block.
5375          */
5376         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5377                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5378                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5379                         handled = 0;
5380                         goto out;
5381                 }
5382         }
5383
5384         /*
5385          * writing any value to intr-mbox-0 clears PCI INTA# and
5386          * chip-internal interrupt pending events.
5387          * writing non-zero to intr-mbox-0 additional tells the
5388          * NIC to stop sending us irqs, engaging "in-intr-handler"
5389          * event coalescing.
5390          *
5391          * Flush the mailbox to de-assert the IRQ immediately to prevent
5392          * spurious interrupts.  The flush impacts performance but
5393          * excessive spurious interrupts can be worse in some cases.
5394          */
5395         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5396
5397         /*
5398          * In a shared interrupt configuration, sometimes other devices'
5399          * interrupts will scream.  We record the current status tag here
5400          * so that the above check can report that the screaming interrupts
5401          * are unhandled.  Eventually they will be silenced.
5402          */
5403         tnapi->last_irq_tag = sblk->status_tag;
5404
5405         if (tg3_irq_sync(tp))
5406                 goto out;
5407
5408         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5409
5410         napi_schedule(&tnapi->napi);
5411
5412 out:
5413         return IRQ_RETVAL(handled);
5414 }
5415
5416 /* ISR for interrupt test */
5417 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5418 {
5419         struct tg3_napi *tnapi = dev_id;
5420         struct tg3 *tp = tnapi->tp;
5421         struct tg3_hw_status *sblk = tnapi->hw_status;
5422
5423         if ((sblk->status & SD_STATUS_UPDATED) ||
5424             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5425                 tg3_disable_ints(tp);
5426                 return IRQ_RETVAL(1);
5427         }
5428         return IRQ_RETVAL(0);
5429 }
5430
5431 static int tg3_init_hw(struct tg3 *, int);
5432 static int tg3_halt(struct tg3 *, int, int);
5433
5434 /* Restart hardware after configuration changes, self-test, etc.
5435  * Invoked with tp->lock held.
5436  */
5437 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5438         __releases(tp->lock)
5439         __acquires(tp->lock)
5440 {
5441         int err;
5442
5443         err = tg3_init_hw(tp, reset_phy);
5444         if (err) {
5445                 netdev_err(tp->dev,
5446                            "Failed to re-initialize device, aborting\n");
5447                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5448                 tg3_full_unlock(tp);
5449                 del_timer_sync(&tp->timer);
5450                 tp->irq_sync = 0;
5451                 tg3_napi_enable(tp);
5452                 dev_close(tp->dev);
5453                 tg3_full_lock(tp, 0);
5454         }
5455         return err;
5456 }
5457
5458 #ifdef CONFIG_NET_POLL_CONTROLLER
5459 static void tg3_poll_controller(struct net_device *dev)
5460 {
5461         int i;
5462         struct tg3 *tp = netdev_priv(dev);
5463
5464         for (i = 0; i < tp->irq_cnt; i++)
5465                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5466 }
5467 #endif
5468
5469 static void tg3_reset_task(struct work_struct *work)
5470 {
5471         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5472         int err;
5473         unsigned int restart_timer;
5474
5475         tg3_full_lock(tp, 0);
5476
5477         if (!netif_running(tp->dev)) {
5478                 tg3_full_unlock(tp);
5479                 return;
5480         }
5481
5482         tg3_full_unlock(tp);
5483
5484         tg3_phy_stop(tp);
5485
5486         tg3_netif_stop(tp);
5487
5488         tg3_full_lock(tp, 1);
5489
5490         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5491         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5492
5493         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5494                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5495                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5496                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5497                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5498         }
5499
5500         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5501         err = tg3_init_hw(tp, 1);
5502         if (err)
5503                 goto out;
5504
5505         tg3_netif_start(tp);
5506
5507         if (restart_timer)
5508                 mod_timer(&tp->timer, jiffies + 1);
5509
5510 out:
5511         tg3_full_unlock(tp);
5512
5513         if (!err)
5514                 tg3_phy_start(tp);
5515 }
5516
5517 static void tg3_dump_short_state(struct tg3 *tp)
5518 {
5519         netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5520                    tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5521         netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5522                    tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5523 }
5524
5525 static void tg3_tx_timeout(struct net_device *dev)
5526 {
5527         struct tg3 *tp = netdev_priv(dev);
5528
5529         if (netif_msg_tx_err(tp)) {
5530                 netdev_err(dev, "transmit timed out, resetting\n");
5531                 tg3_dump_short_state(tp);
5532         }
5533
5534         schedule_work(&tp->reset_task);
5535 }
5536
5537 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5538 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5539 {
5540         u32 base = (u32) mapping & 0xffffffff;
5541
5542         return (base > 0xffffdcc0) && (base + len + 8 < base);
5543 }
5544
5545 /* Test for DMA addresses > 40-bit */
5546 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5547                                           int len)
5548 {
5549 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5550         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5551                 return ((u64) mapping + len) > DMA_BIT_MASK(40);
5552         return 0;
5553 #else
5554         return 0;
5555 #endif
5556 }
5557
5558 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5559
5560 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5561 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5562                                        struct sk_buff *skb, u32 last_plus_one,
5563                                        u32 *start, u32 base_flags, u32 mss)
5564 {
5565         struct tg3 *tp = tnapi->tp;
5566         struct sk_buff *new_skb;
5567         dma_addr_t new_addr = 0;
5568         u32 entry = *start;
5569         int i, ret = 0;
5570
5571         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5572                 new_skb = skb_copy(skb, GFP_ATOMIC);
5573         else {
5574                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5575
5576                 new_skb = skb_copy_expand(skb,
5577                                           skb_headroom(skb) + more_headroom,
5578                                           skb_tailroom(skb), GFP_ATOMIC);
5579         }
5580
5581         if (!new_skb) {
5582                 ret = -1;
5583         } else {
5584                 /* New SKB is guaranteed to be linear. */
5585                 entry = *start;
5586                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5587                                           PCI_DMA_TODEVICE);
5588                 /* Make sure the mapping succeeded */
5589                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5590                         ret = -1;
5591                         dev_kfree_skb(new_skb);
5592                         new_skb = NULL;
5593
5594                 /* Make sure new skb does not cross any 4G boundaries.
5595                  * Drop the packet if it does.
5596                  */
5597                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5598                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5599                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5600                                          PCI_DMA_TODEVICE);
5601                         ret = -1;
5602                         dev_kfree_skb(new_skb);
5603                         new_skb = NULL;
5604                 } else {
5605                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5606                                     base_flags, 1 | (mss << 1));
5607                         *start = NEXT_TX(entry);
5608                 }
5609         }
5610
5611         /* Now clean up the sw ring entries. */
5612         i = 0;
5613         while (entry != last_plus_one) {
5614                 int len;
5615
5616                 if (i == 0)
5617                         len = skb_headlen(skb);
5618                 else
5619                         len = skb_shinfo(skb)->frags[i-1].size;
5620
5621                 pci_unmap_single(tp->pdev,
5622                                  dma_unmap_addr(&tnapi->tx_buffers[entry],
5623                                                 mapping),
5624                                  len, PCI_DMA_TODEVICE);
5625                 if (i == 0) {
5626                         tnapi->tx_buffers[entry].skb = new_skb;
5627                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5628                                            new_addr);
5629                 } else {
5630                         tnapi->tx_buffers[entry].skb = NULL;
5631                 }
5632                 entry = NEXT_TX(entry);
5633                 i++;
5634         }
5635
5636         dev_kfree_skb(skb);
5637
5638         return ret;
5639 }
5640
5641 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5642                         dma_addr_t mapping, int len, u32 flags,
5643                         u32 mss_and_is_end)
5644 {
5645         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5646         int is_end = (mss_and_is_end & 0x1);
5647         u32 mss = (mss_and_is_end >> 1);
5648         u32 vlan_tag = 0;
5649
5650         if (is_end)
5651                 flags |= TXD_FLAG_END;
5652         if (flags & TXD_FLAG_VLAN) {
5653                 vlan_tag = flags >> 16;
5654                 flags &= 0xffff;
5655         }
5656         vlan_tag |= (mss << TXD_MSS_SHIFT);
5657
5658         txd->addr_hi = ((u64) mapping >> 32);
5659         txd->addr_lo = ((u64) mapping & 0xffffffff);
5660         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5661         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5662 }
5663
5664 /* hard_start_xmit for devices that don't have any bugs and
5665  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5666  */
5667 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5668                                   struct net_device *dev)
5669 {
5670         struct tg3 *tp = netdev_priv(dev);
5671         u32 len, entry, base_flags, mss;
5672         dma_addr_t mapping;
5673         struct tg3_napi *tnapi;
5674         struct netdev_queue *txq;
5675         unsigned int i, last;
5676
5677         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5678         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5679         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5680                 tnapi++;
5681
5682         /* We are running in BH disabled context with netif_tx_lock
5683          * and TX reclaim runs via tp->napi.poll inside of a software
5684          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5685          * no IRQ context deadlocks to worry about either.  Rejoice!
5686          */
5687         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5688                 if (!netif_tx_queue_stopped(txq)) {
5689                         netif_tx_stop_queue(txq);
5690
5691                         /* This is a hard error, log it. */
5692                         netdev_err(dev,
5693                                    "BUG! Tx Ring full when queue awake!\n");
5694                 }
5695                 return NETDEV_TX_BUSY;
5696         }
5697
5698         entry = tnapi->tx_prod;
5699         base_flags = 0;
5700         mss = skb_shinfo(skb)->gso_size;
5701         if (mss) {
5702                 int tcp_opt_len, ip_tcp_len;
5703                 u32 hdrlen;
5704
5705                 if (skb_header_cloned(skb) &&
5706                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5707                         dev_kfree_skb(skb);
5708                         goto out_unlock;
5709                 }
5710
5711                 if (skb_is_gso_v6(skb)) {
5712                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5713                 } else {
5714                         struct iphdr *iph = ip_hdr(skb);
5715
5716                         tcp_opt_len = tcp_optlen(skb);
5717                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5718
5719                         iph->check = 0;
5720                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5721                         hdrlen = ip_tcp_len + tcp_opt_len;
5722                 }
5723
5724                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5725                         mss |= (hdrlen & 0xc) << 12;
5726                         if (hdrlen & 0x10)
5727                                 base_flags |= 0x00000010;
5728                         base_flags |= (hdrlen & 0x3e0) << 5;
5729                 } else
5730                         mss |= hdrlen << 9;
5731
5732                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5733                                TXD_FLAG_CPU_POST_DMA);
5734
5735                 tcp_hdr(skb)->check = 0;
5736
5737         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5738                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5739         }
5740
5741         if (vlan_tx_tag_present(skb))
5742                 base_flags |= (TXD_FLAG_VLAN |
5743                                (vlan_tx_tag_get(skb) << 16));
5744
5745         len = skb_headlen(skb);
5746
5747         /* Queue skb data, a.k.a. the main skb fragment. */
5748         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5749         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5750                 dev_kfree_skb(skb);
5751                 goto out_unlock;
5752         }
5753
5754         tnapi->tx_buffers[entry].skb = skb;
5755         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5756
5757         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5758             !mss && skb->len > VLAN_ETH_FRAME_LEN)
5759                 base_flags |= TXD_FLAG_JMB_PKT;
5760