firmware: convert tg3 driver to request_firmware()
[linux-2.6.git] / drivers / net / tg3.c
1 /*
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  * Copyright (C) 2005-2007 Broadcom Corporation.
8  *
9  * Firmware is:
10  *      Derived from proprietary unpublished source code,
11  *      Copyright (C) 2000-2003 Broadcom Corporation.
12  *
13  *      Permission is hereby granted for the distribution of this firmware
14  *      data in hexadecimal or equivalent format, provided this copyright
15  *      notice is accompanying it.
16  */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
26 #include <linux/in.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/phy.h>
36 #include <linux/brcmphy.h>
37 #include <linux/if_vlan.h>
38 #include <linux/ip.h>
39 #include <linux/tcp.h>
40 #include <linux/workqueue.h>
41 #include <linux/prefetch.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/firmware.h>
44
45 #include <net/checksum.h>
46 #include <net/ip.h>
47
48 #include <asm/system.h>
49 #include <asm/io.h>
50 #include <asm/byteorder.h>
51 #include <asm/uaccess.h>
52
53 #ifdef CONFIG_SPARC
54 #include <asm/idprom.h>
55 #include <asm/prom.h>
56 #endif
57
58 #define BAR_0   0
59 #define BAR_2   2
60
61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62 #define TG3_VLAN_TAG_USED 1
63 #else
64 #define TG3_VLAN_TAG_USED 0
65 #endif
66
67 #include "tg3.h"
68
69 #define DRV_MODULE_NAME         "tg3"
70 #define PFX DRV_MODULE_NAME     ": "
71 #define DRV_MODULE_VERSION      "3.97"
72 #define DRV_MODULE_RELDATE      "December 10, 2008"
73
74 #define TG3_DEF_MAC_MODE        0
75 #define TG3_DEF_RX_MODE         0
76 #define TG3_DEF_TX_MODE         0
77 #define TG3_DEF_MSG_ENABLE        \
78         (NETIF_MSG_DRV          | \
79          NETIF_MSG_PROBE        | \
80          NETIF_MSG_LINK         | \
81          NETIF_MSG_TIMER        | \
82          NETIF_MSG_IFDOWN       | \
83          NETIF_MSG_IFUP         | \
84          NETIF_MSG_RX_ERR       | \
85          NETIF_MSG_TX_ERR)
86
87 /* length of time before we decide the hardware is borked,
88  * and dev->tx_timeout() should be called to fix the problem
89  */
90 #define TG3_TX_TIMEOUT                  (5 * HZ)
91
92 /* hardware minimum and maximum for a single frame's data payload */
93 #define TG3_MIN_MTU                     60
94 #define TG3_MAX_MTU(tp) \
95         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
96
97 /* These numbers seem to be hard coded in the NIC firmware somehow.
98  * You can't change the ring sizes, but you can change where you place
99  * them in the NIC onboard memory.
100  */
101 #define TG3_RX_RING_SIZE                512
102 #define TG3_DEF_RX_RING_PENDING         200
103 #define TG3_RX_JUMBO_RING_SIZE          256
104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
105
106 /* Do not place this n-ring entries value into the tp struct itself,
107  * we really want to expose these constants to GCC so that modulo et
108  * al.  operations are done with shifts and masks instead of with
109  * hw multiply/modulo instructions.  Another solution would be to
110  * replace things like '% foo' with '& (foo - 1)'.
111  */
112 #define TG3_RX_RCB_RING_SIZE(tp)        \
113         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
114
115 #define TG3_TX_RING_SIZE                512
116 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
117
118 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
119                                  TG3_RX_RING_SIZE)
120 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121                                  TG3_RX_JUMBO_RING_SIZE)
122 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
123                                    TG3_RX_RCB_RING_SIZE(tp))
124 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
125                                  TG3_TX_RING_SIZE)
126 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
127
128 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
129 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
130
131 /* minimum number of free TX descriptors required to wake up TX process */
132 #define TG3_TX_WAKEUP_THRESH(tp)                ((tp)->tx_pending / 4)
133
134 #define TG3_RAW_IP_ALIGN 2
135
136 /* number of ETHTOOL_GSTATS u64's */
137 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
138
139 #define TG3_NUM_TEST            6
140
141 #define FIRMWARE_TG3            "tigon/tg3.bin"
142 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
143 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
144
145 static char version[] __devinitdata =
146         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
147
148 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
149 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
150 MODULE_LICENSE("GPL");
151 MODULE_VERSION(DRV_MODULE_VERSION);
152 MODULE_FIRMWARE(FIRMWARE_TG3);
153 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
154 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
155
156
157 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
158 module_param(tg3_debug, int, 0);
159 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
160
161 static struct pci_device_id tg3_pci_tbl[] = {
162         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
163         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
164         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
165         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
166         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
167         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
168         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
169         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
170         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
171         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5785)},
223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57720)},
227         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
228         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
229         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
230         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
231         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
232         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
233         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
234         {}
235 };
236
237 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
238
239 static const struct {
240         const char string[ETH_GSTRING_LEN];
241 } ethtool_stats_keys[TG3_NUM_STATS] = {
242         { "rx_octets" },
243         { "rx_fragments" },
244         { "rx_ucast_packets" },
245         { "rx_mcast_packets" },
246         { "rx_bcast_packets" },
247         { "rx_fcs_errors" },
248         { "rx_align_errors" },
249         { "rx_xon_pause_rcvd" },
250         { "rx_xoff_pause_rcvd" },
251         { "rx_mac_ctrl_rcvd" },
252         { "rx_xoff_entered" },
253         { "rx_frame_too_long_errors" },
254         { "rx_jabbers" },
255         { "rx_undersize_packets" },
256         { "rx_in_length_errors" },
257         { "rx_out_length_errors" },
258         { "rx_64_or_less_octet_packets" },
259         { "rx_65_to_127_octet_packets" },
260         { "rx_128_to_255_octet_packets" },
261         { "rx_256_to_511_octet_packets" },
262         { "rx_512_to_1023_octet_packets" },
263         { "rx_1024_to_1522_octet_packets" },
264         { "rx_1523_to_2047_octet_packets" },
265         { "rx_2048_to_4095_octet_packets" },
266         { "rx_4096_to_8191_octet_packets" },
267         { "rx_8192_to_9022_octet_packets" },
268
269         { "tx_octets" },
270         { "tx_collisions" },
271
272         { "tx_xon_sent" },
273         { "tx_xoff_sent" },
274         { "tx_flow_control" },
275         { "tx_mac_errors" },
276         { "tx_single_collisions" },
277         { "tx_mult_collisions" },
278         { "tx_deferred" },
279         { "tx_excessive_collisions" },
280         { "tx_late_collisions" },
281         { "tx_collide_2times" },
282         { "tx_collide_3times" },
283         { "tx_collide_4times" },
284         { "tx_collide_5times" },
285         { "tx_collide_6times" },
286         { "tx_collide_7times" },
287         { "tx_collide_8times" },
288         { "tx_collide_9times" },
289         { "tx_collide_10times" },
290         { "tx_collide_11times" },
291         { "tx_collide_12times" },
292         { "tx_collide_13times" },
293         { "tx_collide_14times" },
294         { "tx_collide_15times" },
295         { "tx_ucast_packets" },
296         { "tx_mcast_packets" },
297         { "tx_bcast_packets" },
298         { "tx_carrier_sense_errors" },
299         { "tx_discards" },
300         { "tx_errors" },
301
302         { "dma_writeq_full" },
303         { "dma_write_prioq_full" },
304         { "rxbds_empty" },
305         { "rx_discards" },
306         { "rx_errors" },
307         { "rx_threshold_hit" },
308
309         { "dma_readq_full" },
310         { "dma_read_prioq_full" },
311         { "tx_comp_queue_full" },
312
313         { "ring_set_send_prod_index" },
314         { "ring_status_update" },
315         { "nic_irqs" },
316         { "nic_avoided_irqs" },
317         { "nic_tx_threshold_hit" }
318 };
319
320 static const struct {
321         const char string[ETH_GSTRING_LEN];
322 } ethtool_test_keys[TG3_NUM_TEST] = {
323         { "nvram test     (online) " },
324         { "link test      (online) " },
325         { "register test  (offline)" },
326         { "memory test    (offline)" },
327         { "loopback test  (offline)" },
328         { "interrupt test (offline)" },
329 };
330
331 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
332 {
333         writel(val, tp->regs + off);
334 }
335
336 static u32 tg3_read32(struct tg3 *tp, u32 off)
337 {
338         return (readl(tp->regs + off));
339 }
340
341 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
342 {
343         writel(val, tp->aperegs + off);
344 }
345
346 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
347 {
348         return (readl(tp->aperegs + off));
349 }
350
351 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
352 {
353         unsigned long flags;
354
355         spin_lock_irqsave(&tp->indirect_lock, flags);
356         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
357         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
358         spin_unlock_irqrestore(&tp->indirect_lock, flags);
359 }
360
361 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
362 {
363         writel(val, tp->regs + off);
364         readl(tp->regs + off);
365 }
366
367 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
368 {
369         unsigned long flags;
370         u32 val;
371
372         spin_lock_irqsave(&tp->indirect_lock, flags);
373         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
374         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
375         spin_unlock_irqrestore(&tp->indirect_lock, flags);
376         return val;
377 }
378
379 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
380 {
381         unsigned long flags;
382
383         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
384                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
385                                        TG3_64BIT_REG_LOW, val);
386                 return;
387         }
388         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
389                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
390                                        TG3_64BIT_REG_LOW, val);
391                 return;
392         }
393
394         spin_lock_irqsave(&tp->indirect_lock, flags);
395         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
396         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
397         spin_unlock_irqrestore(&tp->indirect_lock, flags);
398
399         /* In indirect mode when disabling interrupts, we also need
400          * to clear the interrupt bit in the GRC local ctrl register.
401          */
402         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
403             (val == 0x1)) {
404                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
405                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
406         }
407 }
408
409 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
410 {
411         unsigned long flags;
412         u32 val;
413
414         spin_lock_irqsave(&tp->indirect_lock, flags);
415         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
416         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
417         spin_unlock_irqrestore(&tp->indirect_lock, flags);
418         return val;
419 }
420
421 /* usec_wait specifies the wait time in usec when writing to certain registers
422  * where it is unsafe to read back the register without some delay.
423  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
424  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
425  */
426 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
427 {
428         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
429             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
430                 /* Non-posted methods */
431                 tp->write32(tp, off, val);
432         else {
433                 /* Posted method */
434                 tg3_write32(tp, off, val);
435                 if (usec_wait)
436                         udelay(usec_wait);
437                 tp->read32(tp, off);
438         }
439         /* Wait again after the read for the posted method to guarantee that
440          * the wait time is met.
441          */
442         if (usec_wait)
443                 udelay(usec_wait);
444 }
445
446 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
447 {
448         tp->write32_mbox(tp, off, val);
449         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
450             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
451                 tp->read32_mbox(tp, off);
452 }
453
454 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
455 {
456         void __iomem *mbox = tp->regs + off;
457         writel(val, mbox);
458         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
459                 writel(val, mbox);
460         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
461                 readl(mbox);
462 }
463
464 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
465 {
466         return (readl(tp->regs + off + GRCMBOX_BASE));
467 }
468
469 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
470 {
471         writel(val, tp->regs + off + GRCMBOX_BASE);
472 }
473
474 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
475 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
476 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
477 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
478 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
479
480 #define tw32(reg,val)           tp->write32(tp, reg, val)
481 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
482 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
483 #define tr32(reg)               tp->read32(tp, reg)
484
485 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
486 {
487         unsigned long flags;
488
489         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
490             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
491                 return;
492
493         spin_lock_irqsave(&tp->indirect_lock, flags);
494         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
495                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
496                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
497
498                 /* Always leave this as zero. */
499                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
500         } else {
501                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
502                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
503
504                 /* Always leave this as zero. */
505                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
506         }
507         spin_unlock_irqrestore(&tp->indirect_lock, flags);
508 }
509
510 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
511 {
512         unsigned long flags;
513
514         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
515             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
516                 *val = 0;
517                 return;
518         }
519
520         spin_lock_irqsave(&tp->indirect_lock, flags);
521         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
522                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
523                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
524
525                 /* Always leave this as zero. */
526                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
527         } else {
528                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
529                 *val = tr32(TG3PCI_MEM_WIN_DATA);
530
531                 /* Always leave this as zero. */
532                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
533         }
534         spin_unlock_irqrestore(&tp->indirect_lock, flags);
535 }
536
537 static void tg3_ape_lock_init(struct tg3 *tp)
538 {
539         int i;
540
541         /* Make sure the driver hasn't any stale locks. */
542         for (i = 0; i < 8; i++)
543                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
544                                 APE_LOCK_GRANT_DRIVER);
545 }
546
547 static int tg3_ape_lock(struct tg3 *tp, int locknum)
548 {
549         int i, off;
550         int ret = 0;
551         u32 status;
552
553         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
554                 return 0;
555
556         switch (locknum) {
557                 case TG3_APE_LOCK_GRC:
558                 case TG3_APE_LOCK_MEM:
559                         break;
560                 default:
561                         return -EINVAL;
562         }
563
564         off = 4 * locknum;
565
566         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
567
568         /* Wait for up to 1 millisecond to acquire lock. */
569         for (i = 0; i < 100; i++) {
570                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
571                 if (status == APE_LOCK_GRANT_DRIVER)
572                         break;
573                 udelay(10);
574         }
575
576         if (status != APE_LOCK_GRANT_DRIVER) {
577                 /* Revoke the lock request. */
578                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
579                                 APE_LOCK_GRANT_DRIVER);
580
581                 ret = -EBUSY;
582         }
583
584         return ret;
585 }
586
587 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
588 {
589         int off;
590
591         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
592                 return;
593
594         switch (locknum) {
595                 case TG3_APE_LOCK_GRC:
596                 case TG3_APE_LOCK_MEM:
597                         break;
598                 default:
599                         return;
600         }
601
602         off = 4 * locknum;
603         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
604 }
605
606 static void tg3_disable_ints(struct tg3 *tp)
607 {
608         tw32(TG3PCI_MISC_HOST_CTRL,
609              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
610         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
611 }
612
613 static inline void tg3_cond_int(struct tg3 *tp)
614 {
615         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
616             (tp->hw_status->status & SD_STATUS_UPDATED))
617                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
618         else
619                 tw32(HOSTCC_MODE, tp->coalesce_mode |
620                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
621 }
622
623 static void tg3_enable_ints(struct tg3 *tp)
624 {
625         tp->irq_sync = 0;
626         wmb();
627
628         tw32(TG3PCI_MISC_HOST_CTRL,
629              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
630         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
631                        (tp->last_tag << 24));
632         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
633                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
634                                (tp->last_tag << 24));
635         tg3_cond_int(tp);
636 }
637
638 static inline unsigned int tg3_has_work(struct tg3 *tp)
639 {
640         struct tg3_hw_status *sblk = tp->hw_status;
641         unsigned int work_exists = 0;
642
643         /* check for phy events */
644         if (!(tp->tg3_flags &
645               (TG3_FLAG_USE_LINKCHG_REG |
646                TG3_FLAG_POLL_SERDES))) {
647                 if (sblk->status & SD_STATUS_LINK_CHG)
648                         work_exists = 1;
649         }
650         /* check for RX/TX work to do */
651         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
652             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
653                 work_exists = 1;
654
655         return work_exists;
656 }
657
658 /* tg3_restart_ints
659  *  similar to tg3_enable_ints, but it accurately determines whether there
660  *  is new work pending and can return without flushing the PIO write
661  *  which reenables interrupts
662  */
663 static void tg3_restart_ints(struct tg3 *tp)
664 {
665         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
666                      tp->last_tag << 24);
667         mmiowb();
668
669         /* When doing tagged status, this work check is unnecessary.
670          * The last_tag we write above tells the chip which piece of
671          * work we've completed.
672          */
673         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
674             tg3_has_work(tp))
675                 tw32(HOSTCC_MODE, tp->coalesce_mode |
676                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
677 }
678
679 static inline void tg3_netif_stop(struct tg3 *tp)
680 {
681         tp->dev->trans_start = jiffies; /* prevent tx timeout */
682         napi_disable(&tp->napi);
683         netif_tx_disable(tp->dev);
684 }
685
686 static inline void tg3_netif_start(struct tg3 *tp)
687 {
688         netif_wake_queue(tp->dev);
689         /* NOTE: unconditional netif_wake_queue is only appropriate
690          * so long as all callers are assured to have free tx slots
691          * (such as after tg3_init_hw)
692          */
693         napi_enable(&tp->napi);
694         tp->hw_status->status |= SD_STATUS_UPDATED;
695         tg3_enable_ints(tp);
696 }
697
698 static void tg3_switch_clocks(struct tg3 *tp)
699 {
700         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
701         u32 orig_clock_ctrl;
702
703         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
704             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
705                 return;
706
707         orig_clock_ctrl = clock_ctrl;
708         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
709                        CLOCK_CTRL_CLKRUN_OENABLE |
710                        0x1f);
711         tp->pci_clock_ctrl = clock_ctrl;
712
713         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
714                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
715                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
716                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
717                 }
718         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
719                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
720                             clock_ctrl |
721                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
722                             40);
723                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
724                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
725                             40);
726         }
727         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
728 }
729
730 #define PHY_BUSY_LOOPS  5000
731
732 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
733 {
734         u32 frame_val;
735         unsigned int loops;
736         int ret;
737
738         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
739                 tw32_f(MAC_MI_MODE,
740                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
741                 udelay(80);
742         }
743
744         *val = 0x0;
745
746         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
747                       MI_COM_PHY_ADDR_MASK);
748         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
749                       MI_COM_REG_ADDR_MASK);
750         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
751
752         tw32_f(MAC_MI_COM, frame_val);
753
754         loops = PHY_BUSY_LOOPS;
755         while (loops != 0) {
756                 udelay(10);
757                 frame_val = tr32(MAC_MI_COM);
758
759                 if ((frame_val & MI_COM_BUSY) == 0) {
760                         udelay(5);
761                         frame_val = tr32(MAC_MI_COM);
762                         break;
763                 }
764                 loops -= 1;
765         }
766
767         ret = -EBUSY;
768         if (loops != 0) {
769                 *val = frame_val & MI_COM_DATA_MASK;
770                 ret = 0;
771         }
772
773         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
774                 tw32_f(MAC_MI_MODE, tp->mi_mode);
775                 udelay(80);
776         }
777
778         return ret;
779 }
780
781 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
782 {
783         u32 frame_val;
784         unsigned int loops;
785         int ret;
786
787         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
788             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
789                 return 0;
790
791         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
792                 tw32_f(MAC_MI_MODE,
793                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
794                 udelay(80);
795         }
796
797         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
798                       MI_COM_PHY_ADDR_MASK);
799         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
800                       MI_COM_REG_ADDR_MASK);
801         frame_val |= (val & MI_COM_DATA_MASK);
802         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
803
804         tw32_f(MAC_MI_COM, frame_val);
805
806         loops = PHY_BUSY_LOOPS;
807         while (loops != 0) {
808                 udelay(10);
809                 frame_val = tr32(MAC_MI_COM);
810                 if ((frame_val & MI_COM_BUSY) == 0) {
811                         udelay(5);
812                         frame_val = tr32(MAC_MI_COM);
813                         break;
814                 }
815                 loops -= 1;
816         }
817
818         ret = -EBUSY;
819         if (loops != 0)
820                 ret = 0;
821
822         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
823                 tw32_f(MAC_MI_MODE, tp->mi_mode);
824                 udelay(80);
825         }
826
827         return ret;
828 }
829
830 static int tg3_bmcr_reset(struct tg3 *tp)
831 {
832         u32 phy_control;
833         int limit, err;
834
835         /* OK, reset it, and poll the BMCR_RESET bit until it
836          * clears or we time out.
837          */
838         phy_control = BMCR_RESET;
839         err = tg3_writephy(tp, MII_BMCR, phy_control);
840         if (err != 0)
841                 return -EBUSY;
842
843         limit = 5000;
844         while (limit--) {
845                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
846                 if (err != 0)
847                         return -EBUSY;
848
849                 if ((phy_control & BMCR_RESET) == 0) {
850                         udelay(40);
851                         break;
852                 }
853                 udelay(10);
854         }
855         if (limit <= 0)
856                 return -EBUSY;
857
858         return 0;
859 }
860
861 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
862 {
863         struct tg3 *tp = (struct tg3 *)bp->priv;
864         u32 val;
865
866         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
867                 return -EAGAIN;
868
869         if (tg3_readphy(tp, reg, &val))
870                 return -EIO;
871
872         return val;
873 }
874
875 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
876 {
877         struct tg3 *tp = (struct tg3 *)bp->priv;
878
879         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
880                 return -EAGAIN;
881
882         if (tg3_writephy(tp, reg, val))
883                 return -EIO;
884
885         return 0;
886 }
887
888 static int tg3_mdio_reset(struct mii_bus *bp)
889 {
890         return 0;
891 }
892
893 static void tg3_mdio_config_5785(struct tg3 *tp)
894 {
895         u32 val;
896         struct phy_device *phydev;
897
898         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
899         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
900         case TG3_PHY_ID_BCM50610:
901                 val = MAC_PHYCFG2_50610_LED_MODES;
902                 break;
903         case TG3_PHY_ID_BCMAC131:
904                 val = MAC_PHYCFG2_AC131_LED_MODES;
905                 break;
906         case TG3_PHY_ID_RTL8211C:
907                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
908                 break;
909         case TG3_PHY_ID_RTL8201E:
910                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
911                 break;
912         default:
913                 return;
914         }
915
916         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
917                 tw32(MAC_PHYCFG2, val);
918
919                 val = tr32(MAC_PHYCFG1);
920                 val &= ~MAC_PHYCFG1_RGMII_INT;
921                 tw32(MAC_PHYCFG1, val);
922
923                 return;
924         }
925
926         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
927                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
928                        MAC_PHYCFG2_FMODE_MASK_MASK |
929                        MAC_PHYCFG2_GMODE_MASK_MASK |
930                        MAC_PHYCFG2_ACT_MASK_MASK   |
931                        MAC_PHYCFG2_QUAL_MASK_MASK |
932                        MAC_PHYCFG2_INBAND_ENABLE;
933
934         tw32(MAC_PHYCFG2, val);
935
936         val = tr32(MAC_PHYCFG1) & ~(MAC_PHYCFG1_RGMII_EXT_RX_DEC |
937                                     MAC_PHYCFG1_RGMII_SND_STAT_EN);
938         if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {
939                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
940                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
941                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
942                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
943         }
944         tw32(MAC_PHYCFG1, val | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV);
945
946         val = tr32(MAC_EXT_RGMII_MODE);
947         val &= ~(MAC_RGMII_MODE_RX_INT_B |
948                  MAC_RGMII_MODE_RX_QUALITY |
949                  MAC_RGMII_MODE_RX_ACTIVITY |
950                  MAC_RGMII_MODE_RX_ENG_DET |
951                  MAC_RGMII_MODE_TX_ENABLE |
952                  MAC_RGMII_MODE_TX_LOWPWR |
953                  MAC_RGMII_MODE_TX_RESET);
954         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
955                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
956                         val |= MAC_RGMII_MODE_RX_INT_B |
957                                MAC_RGMII_MODE_RX_QUALITY |
958                                MAC_RGMII_MODE_RX_ACTIVITY |
959                                MAC_RGMII_MODE_RX_ENG_DET;
960                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
961                         val |= MAC_RGMII_MODE_TX_ENABLE |
962                                MAC_RGMII_MODE_TX_LOWPWR |
963                                MAC_RGMII_MODE_TX_RESET;
964         }
965         tw32(MAC_EXT_RGMII_MODE, val);
966 }
967
968 static void tg3_mdio_start(struct tg3 *tp)
969 {
970         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
971                 mutex_lock(&tp->mdio_bus->mdio_lock);
972                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
973                 mutex_unlock(&tp->mdio_bus->mdio_lock);
974         }
975
976         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
977         tw32_f(MAC_MI_MODE, tp->mi_mode);
978         udelay(80);
979
980         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
981             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
982                 tg3_mdio_config_5785(tp);
983 }
984
985 static void tg3_mdio_stop(struct tg3 *tp)
986 {
987         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
988                 mutex_lock(&tp->mdio_bus->mdio_lock);
989                 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
990                 mutex_unlock(&tp->mdio_bus->mdio_lock);
991         }
992 }
993
994 static int tg3_mdio_init(struct tg3 *tp)
995 {
996         int i;
997         u32 reg;
998         struct phy_device *phydev;
999
1000         tg3_mdio_start(tp);
1001
1002         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1003             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1004                 return 0;
1005
1006         tp->mdio_bus = mdiobus_alloc();
1007         if (tp->mdio_bus == NULL)
1008                 return -ENOMEM;
1009
1010         tp->mdio_bus->name     = "tg3 mdio bus";
1011         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1012                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1013         tp->mdio_bus->priv     = tp;
1014         tp->mdio_bus->parent   = &tp->pdev->dev;
1015         tp->mdio_bus->read     = &tg3_mdio_read;
1016         tp->mdio_bus->write    = &tg3_mdio_write;
1017         tp->mdio_bus->reset    = &tg3_mdio_reset;
1018         tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
1019         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1020
1021         for (i = 0; i < PHY_MAX_ADDR; i++)
1022                 tp->mdio_bus->irq[i] = PHY_POLL;
1023
1024         /* The bus registration will look for all the PHYs on the mdio bus.
1025          * Unfortunately, it does not ensure the PHY is powered up before
1026          * accessing the PHY ID registers.  A chip reset is the
1027          * quickest way to bring the device back to an operational state..
1028          */
1029         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1030                 tg3_bmcr_reset(tp);
1031
1032         i = mdiobus_register(tp->mdio_bus);
1033         if (i) {
1034                 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1035                         tp->dev->name, i);
1036                 mdiobus_free(tp->mdio_bus);
1037                 return i;
1038         }
1039
1040         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1041
1042         if (!phydev || !phydev->drv) {
1043                 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1044                 mdiobus_unregister(tp->mdio_bus);
1045                 mdiobus_free(tp->mdio_bus);
1046                 return -ENODEV;
1047         }
1048
1049         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1050         case TG3_PHY_ID_BCM57780:
1051                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1052                 break;
1053         case TG3_PHY_ID_BCM50610:
1054                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1055                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1056                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1057                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1058                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1059                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1060                 /* fallthru */
1061         case TG3_PHY_ID_RTL8211C:
1062                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1063                 break;
1064         case TG3_PHY_ID_RTL8201E:
1065         case TG3_PHY_ID_BCMAC131:
1066                 phydev->interface = PHY_INTERFACE_MODE_MII;
1067                 break;
1068         }
1069
1070         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1071
1072         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1073                 tg3_mdio_config_5785(tp);
1074
1075         return 0;
1076 }
1077
1078 static void tg3_mdio_fini(struct tg3 *tp)
1079 {
1080         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1081                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1082                 mdiobus_unregister(tp->mdio_bus);
1083                 mdiobus_free(tp->mdio_bus);
1084                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1085         }
1086 }
1087
1088 /* tp->lock is held. */
1089 static inline void tg3_generate_fw_event(struct tg3 *tp)
1090 {
1091         u32 val;
1092
1093         val = tr32(GRC_RX_CPU_EVENT);
1094         val |= GRC_RX_CPU_DRIVER_EVENT;
1095         tw32_f(GRC_RX_CPU_EVENT, val);
1096
1097         tp->last_event_jiffies = jiffies;
1098 }
1099
1100 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1101
1102 /* tp->lock is held. */
1103 static void tg3_wait_for_event_ack(struct tg3 *tp)
1104 {
1105         int i;
1106         unsigned int delay_cnt;
1107         long time_remain;
1108
1109         /* If enough time has passed, no wait is necessary. */
1110         time_remain = (long)(tp->last_event_jiffies + 1 +
1111                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1112                       (long)jiffies;
1113         if (time_remain < 0)
1114                 return;
1115
1116         /* Check if we can shorten the wait time. */
1117         delay_cnt = jiffies_to_usecs(time_remain);
1118         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1119                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1120         delay_cnt = (delay_cnt >> 3) + 1;
1121
1122         for (i = 0; i < delay_cnt; i++) {
1123                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1124                         break;
1125                 udelay(8);
1126         }
1127 }
1128
1129 /* tp->lock is held. */
1130 static void tg3_ump_link_report(struct tg3 *tp)
1131 {
1132         u32 reg;
1133         u32 val;
1134
1135         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1136             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1137                 return;
1138
1139         tg3_wait_for_event_ack(tp);
1140
1141         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1142
1143         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1144
1145         val = 0;
1146         if (!tg3_readphy(tp, MII_BMCR, &reg))
1147                 val = reg << 16;
1148         if (!tg3_readphy(tp, MII_BMSR, &reg))
1149                 val |= (reg & 0xffff);
1150         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1151
1152         val = 0;
1153         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1154                 val = reg << 16;
1155         if (!tg3_readphy(tp, MII_LPA, &reg))
1156                 val |= (reg & 0xffff);
1157         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1158
1159         val = 0;
1160         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1161                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1162                         val = reg << 16;
1163                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1164                         val |= (reg & 0xffff);
1165         }
1166         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1167
1168         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1169                 val = reg << 16;
1170         else
1171                 val = 0;
1172         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1173
1174         tg3_generate_fw_event(tp);
1175 }
1176
1177 static void tg3_link_report(struct tg3 *tp)
1178 {
1179         if (!netif_carrier_ok(tp->dev)) {
1180                 if (netif_msg_link(tp))
1181                         printk(KERN_INFO PFX "%s: Link is down.\n",
1182                                tp->dev->name);
1183                 tg3_ump_link_report(tp);
1184         } else if (netif_msg_link(tp)) {
1185                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1186                        tp->dev->name,
1187                        (tp->link_config.active_speed == SPEED_1000 ?
1188                         1000 :
1189                         (tp->link_config.active_speed == SPEED_100 ?
1190                          100 : 10)),
1191                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1192                         "full" : "half"));
1193
1194                 printk(KERN_INFO PFX
1195                        "%s: Flow control is %s for TX and %s for RX.\n",
1196                        tp->dev->name,
1197                        (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1198                        "on" : "off",
1199                        (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1200                        "on" : "off");
1201                 tg3_ump_link_report(tp);
1202         }
1203 }
1204
1205 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1206 {
1207         u16 miireg;
1208
1209         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1210                 miireg = ADVERTISE_PAUSE_CAP;
1211         else if (flow_ctrl & FLOW_CTRL_TX)
1212                 miireg = ADVERTISE_PAUSE_ASYM;
1213         else if (flow_ctrl & FLOW_CTRL_RX)
1214                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1215         else
1216                 miireg = 0;
1217
1218         return miireg;
1219 }
1220
1221 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1222 {
1223         u16 miireg;
1224
1225         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1226                 miireg = ADVERTISE_1000XPAUSE;
1227         else if (flow_ctrl & FLOW_CTRL_TX)
1228                 miireg = ADVERTISE_1000XPSE_ASYM;
1229         else if (flow_ctrl & FLOW_CTRL_RX)
1230                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1231         else
1232                 miireg = 0;
1233
1234         return miireg;
1235 }
1236
1237 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1238 {
1239         u8 cap = 0;
1240
1241         if (lcladv & ADVERTISE_1000XPAUSE) {
1242                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1243                         if (rmtadv & LPA_1000XPAUSE)
1244                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1245                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1246                                 cap = FLOW_CTRL_RX;
1247                 } else {
1248                         if (rmtadv & LPA_1000XPAUSE)
1249                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1250                 }
1251         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1252                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1253                         cap = FLOW_CTRL_TX;
1254         }
1255
1256         return cap;
1257 }
1258
1259 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1260 {
1261         u8 autoneg;
1262         u8 flowctrl = 0;
1263         u32 old_rx_mode = tp->rx_mode;
1264         u32 old_tx_mode = tp->tx_mode;
1265
1266         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1267                 autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
1268         else
1269                 autoneg = tp->link_config.autoneg;
1270
1271         if (autoneg == AUTONEG_ENABLE &&
1272             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1273                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1274                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1275                 else
1276                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1277         } else
1278                 flowctrl = tp->link_config.flowctrl;
1279
1280         tp->link_config.active_flowctrl = flowctrl;
1281
1282         if (flowctrl & FLOW_CTRL_RX)
1283                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1284         else
1285                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1286
1287         if (old_rx_mode != tp->rx_mode)
1288                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1289
1290         if (flowctrl & FLOW_CTRL_TX)
1291                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1292         else
1293                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1294
1295         if (old_tx_mode != tp->tx_mode)
1296                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1297 }
1298
1299 static void tg3_adjust_link(struct net_device *dev)
1300 {
1301         u8 oldflowctrl, linkmesg = 0;
1302         u32 mac_mode, lcl_adv, rmt_adv;
1303         struct tg3 *tp = netdev_priv(dev);
1304         struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1305
1306         spin_lock(&tp->lock);
1307
1308         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1309                                     MAC_MODE_HALF_DUPLEX);
1310
1311         oldflowctrl = tp->link_config.active_flowctrl;
1312
1313         if (phydev->link) {
1314                 lcl_adv = 0;
1315                 rmt_adv = 0;
1316
1317                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1318                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1319                 else
1320                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1321
1322                 if (phydev->duplex == DUPLEX_HALF)
1323                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1324                 else {
1325                         lcl_adv = tg3_advert_flowctrl_1000T(
1326                                   tp->link_config.flowctrl);
1327
1328                         if (phydev->pause)
1329                                 rmt_adv = LPA_PAUSE_CAP;
1330                         if (phydev->asym_pause)
1331                                 rmt_adv |= LPA_PAUSE_ASYM;
1332                 }
1333
1334                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1335         } else
1336                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1337
1338         if (mac_mode != tp->mac_mode) {
1339                 tp->mac_mode = mac_mode;
1340                 tw32_f(MAC_MODE, tp->mac_mode);
1341                 udelay(40);
1342         }
1343
1344         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1345                 if (phydev->speed == SPEED_10)
1346                         tw32(MAC_MI_STAT,
1347                              MAC_MI_STAT_10MBPS_MODE |
1348                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1349                 else
1350                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1351         }
1352
1353         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1354                 tw32(MAC_TX_LENGTHS,
1355                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1356                       (6 << TX_LENGTHS_IPG_SHIFT) |
1357                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1358         else
1359                 tw32(MAC_TX_LENGTHS,
1360                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1361                       (6 << TX_LENGTHS_IPG_SHIFT) |
1362                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1363
1364         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1365             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1366             phydev->speed != tp->link_config.active_speed ||
1367             phydev->duplex != tp->link_config.active_duplex ||
1368             oldflowctrl != tp->link_config.active_flowctrl)
1369             linkmesg = 1;
1370
1371         tp->link_config.active_speed = phydev->speed;
1372         tp->link_config.active_duplex = phydev->duplex;
1373
1374         spin_unlock(&tp->lock);
1375
1376         if (linkmesg)
1377                 tg3_link_report(tp);
1378 }
1379
1380 static int tg3_phy_init(struct tg3 *tp)
1381 {
1382         struct phy_device *phydev;
1383
1384         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1385                 return 0;
1386
1387         /* Bring the PHY back to a known state. */
1388         tg3_bmcr_reset(tp);
1389
1390         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1391
1392         /* Attach the MAC to the PHY. */
1393         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1394                              phydev->dev_flags, phydev->interface);
1395         if (IS_ERR(phydev)) {
1396                 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1397                 return PTR_ERR(phydev);
1398         }
1399
1400         /* Mask with MAC supported features. */
1401         switch (phydev->interface) {
1402         case PHY_INTERFACE_MODE_GMII:
1403         case PHY_INTERFACE_MODE_RGMII:
1404                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1405                         phydev->supported &= (PHY_GBIT_FEATURES |
1406                                               SUPPORTED_Pause |
1407                                               SUPPORTED_Asym_Pause);
1408                         break;
1409                 }
1410                 /* fallthru */
1411         case PHY_INTERFACE_MODE_MII:
1412                 phydev->supported &= (PHY_BASIC_FEATURES |
1413                                       SUPPORTED_Pause |
1414                                       SUPPORTED_Asym_Pause);
1415                 break;
1416         default:
1417                 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1418                 return -EINVAL;
1419         }
1420
1421         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1422
1423         phydev->advertising = phydev->supported;
1424
1425         return 0;
1426 }
1427
1428 static void tg3_phy_start(struct tg3 *tp)
1429 {
1430         struct phy_device *phydev;
1431
1432         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1433                 return;
1434
1435         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1436
1437         if (tp->link_config.phy_is_low_power) {
1438                 tp->link_config.phy_is_low_power = 0;
1439                 phydev->speed = tp->link_config.orig_speed;
1440                 phydev->duplex = tp->link_config.orig_duplex;
1441                 phydev->autoneg = tp->link_config.orig_autoneg;
1442                 phydev->advertising = tp->link_config.orig_advertising;
1443         }
1444
1445         phy_start(phydev);
1446
1447         phy_start_aneg(phydev);
1448 }
1449
1450 static void tg3_phy_stop(struct tg3 *tp)
1451 {
1452         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1453                 return;
1454
1455         phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
1456 }
1457
1458 static void tg3_phy_fini(struct tg3 *tp)
1459 {
1460         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1461                 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1462                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1463         }
1464 }
1465
1466 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1467 {
1468         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1469         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1470 }
1471
1472 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1473 {
1474         u32 reg;
1475
1476         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1477                 return;
1478
1479         reg = MII_TG3_MISC_SHDW_WREN |
1480               MII_TG3_MISC_SHDW_SCR5_SEL |
1481               MII_TG3_MISC_SHDW_SCR5_LPED |
1482               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1483               MII_TG3_MISC_SHDW_SCR5_SDTL |
1484               MII_TG3_MISC_SHDW_SCR5_C125OE;
1485         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1486                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1487
1488         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1489
1490
1491         reg = MII_TG3_MISC_SHDW_WREN |
1492               MII_TG3_MISC_SHDW_APD_SEL |
1493               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1494         if (enable)
1495                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1496
1497         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1498 }
1499
1500 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1501 {
1502         u32 phy;
1503
1504         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1505             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1506                 return;
1507
1508         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1509                 u32 ephy;
1510
1511                 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
1512                         tg3_writephy(tp, MII_TG3_EPHY_TEST,
1513                                      ephy | MII_TG3_EPHY_SHADOW_EN);
1514                         if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
1515                                 if (enable)
1516                                         phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
1517                                 else
1518                                         phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
1519                                 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
1520                         }
1521                         tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
1522                 }
1523         } else {
1524                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1525                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1526                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1527                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1528                         if (enable)
1529                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1530                         else
1531                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1532                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1533                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1534                 }
1535         }
1536 }
1537
1538 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1539 {
1540         u32 val;
1541
1542         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1543                 return;
1544
1545         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1546             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1547                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1548                              (val | (1 << 15) | (1 << 4)));
1549 }
1550
1551 static void tg3_phy_apply_otp(struct tg3 *tp)
1552 {
1553         u32 otp, phy;
1554
1555         if (!tp->phy_otp)
1556                 return;
1557
1558         otp = tp->phy_otp;
1559
1560         /* Enable SM_DSP clock and tx 6dB coding. */
1561         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1562               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1563               MII_TG3_AUXCTL_ACTL_TX_6DB;
1564         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1565
1566         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1567         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1568         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1569
1570         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1571               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1572         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1573
1574         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1575         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1576         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1577
1578         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1579         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1580
1581         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1582         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1583
1584         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1585               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1586         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1587
1588         /* Turn off SM_DSP clock. */
1589         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1590               MII_TG3_AUXCTL_ACTL_TX_6DB;
1591         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1592 }
1593
1594 static int tg3_wait_macro_done(struct tg3 *tp)
1595 {
1596         int limit = 100;
1597
1598         while (limit--) {
1599                 u32 tmp32;
1600
1601                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1602                         if ((tmp32 & 0x1000) == 0)
1603                                 break;
1604                 }
1605         }
1606         if (limit <= 0)
1607                 return -EBUSY;
1608
1609         return 0;
1610 }
1611
1612 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1613 {
1614         static const u32 test_pat[4][6] = {
1615         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1616         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1617         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1618         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1619         };
1620         int chan;
1621
1622         for (chan = 0; chan < 4; chan++) {
1623                 int i;
1624
1625                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1626                              (chan * 0x2000) | 0x0200);
1627                 tg3_writephy(tp, 0x16, 0x0002);
1628
1629                 for (i = 0; i < 6; i++)
1630                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1631                                      test_pat[chan][i]);
1632
1633                 tg3_writephy(tp, 0x16, 0x0202);
1634                 if (tg3_wait_macro_done(tp)) {
1635                         *resetp = 1;
1636                         return -EBUSY;
1637                 }
1638
1639                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1640                              (chan * 0x2000) | 0x0200);
1641                 tg3_writephy(tp, 0x16, 0x0082);
1642                 if (tg3_wait_macro_done(tp)) {
1643                         *resetp = 1;
1644                         return -EBUSY;
1645                 }
1646
1647                 tg3_writephy(tp, 0x16, 0x0802);
1648                 if (tg3_wait_macro_done(tp)) {
1649                         *resetp = 1;
1650                         return -EBUSY;
1651                 }
1652
1653                 for (i = 0; i < 6; i += 2) {
1654                         u32 low, high;
1655
1656                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1657                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1658                             tg3_wait_macro_done(tp)) {
1659                                 *resetp = 1;
1660                                 return -EBUSY;
1661                         }
1662                         low &= 0x7fff;
1663                         high &= 0x000f;
1664                         if (low != test_pat[chan][i] ||
1665                             high != test_pat[chan][i+1]) {
1666                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1667                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1668                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1669
1670                                 return -EBUSY;
1671                         }
1672                 }
1673         }
1674
1675         return 0;
1676 }
1677
1678 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1679 {
1680         int chan;
1681
1682         for (chan = 0; chan < 4; chan++) {
1683                 int i;
1684
1685                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1686                              (chan * 0x2000) | 0x0200);
1687                 tg3_writephy(tp, 0x16, 0x0002);
1688                 for (i = 0; i < 6; i++)
1689                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1690                 tg3_writephy(tp, 0x16, 0x0202);
1691                 if (tg3_wait_macro_done(tp))
1692                         return -EBUSY;
1693         }
1694
1695         return 0;
1696 }
1697
1698 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1699 {
1700         u32 reg32, phy9_orig;
1701         int retries, do_phy_reset, err;
1702
1703         retries = 10;
1704         do_phy_reset = 1;
1705         do {
1706                 if (do_phy_reset) {
1707                         err = tg3_bmcr_reset(tp);
1708                         if (err)
1709                                 return err;
1710                         do_phy_reset = 0;
1711                 }
1712
1713                 /* Disable transmitter and interrupt.  */
1714                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1715                         continue;
1716
1717                 reg32 |= 0x3000;
1718                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1719
1720                 /* Set full-duplex, 1000 mbps.  */
1721                 tg3_writephy(tp, MII_BMCR,
1722                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1723
1724                 /* Set to master mode.  */
1725                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1726                         continue;
1727
1728                 tg3_writephy(tp, MII_TG3_CTRL,
1729                              (MII_TG3_CTRL_AS_MASTER |
1730                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1731
1732                 /* Enable SM_DSP_CLOCK and 6dB.  */
1733                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1734
1735                 /* Block the PHY control access.  */
1736                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1737                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1738
1739                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1740                 if (!err)
1741                         break;
1742         } while (--retries);
1743
1744         err = tg3_phy_reset_chanpat(tp);
1745         if (err)
1746                 return err;
1747
1748         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1749         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1750
1751         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1752         tg3_writephy(tp, 0x16, 0x0000);
1753
1754         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1755             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1756                 /* Set Extended packet length bit for jumbo frames */
1757                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1758         }
1759         else {
1760                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1761         }
1762
1763         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1764
1765         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1766                 reg32 &= ~0x3000;
1767                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1768         } else if (!err)
1769                 err = -EBUSY;
1770
1771         return err;
1772 }
1773
1774 /* This will reset the tigon3 PHY if there is no valid
1775  * link unless the FORCE argument is non-zero.
1776  */
1777 static int tg3_phy_reset(struct tg3 *tp)
1778 {
1779         u32 cpmuctrl;
1780         u32 phy_status;
1781         int err;
1782
1783         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1784                 u32 val;
1785
1786                 val = tr32(GRC_MISC_CFG);
1787                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1788                 udelay(40);
1789         }
1790         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1791         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1792         if (err != 0)
1793                 return -EBUSY;
1794
1795         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1796                 netif_carrier_off(tp->dev);
1797                 tg3_link_report(tp);
1798         }
1799
1800         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1801             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1802             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1803                 err = tg3_phy_reset_5703_4_5(tp);
1804                 if (err)
1805                         return err;
1806                 goto out;
1807         }
1808
1809         cpmuctrl = 0;
1810         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1811             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1812                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1813                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1814                         tw32(TG3_CPMU_CTRL,
1815                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1816         }
1817
1818         err = tg3_bmcr_reset(tp);
1819         if (err)
1820                 return err;
1821
1822         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1823                 u32 phy;
1824
1825                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1826                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1827
1828                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1829         }
1830
1831         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1832             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1833                 u32 val;
1834
1835                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1836                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1837                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1838                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1839                         udelay(40);
1840                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1841                 }
1842         }
1843
1844         tg3_phy_apply_otp(tp);
1845
1846         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1847                 tg3_phy_toggle_apd(tp, true);
1848         else
1849                 tg3_phy_toggle_apd(tp, false);
1850
1851 out:
1852         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1853                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1854                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1855                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1856                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1857                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1858                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1859         }
1860         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1861                 tg3_writephy(tp, 0x1c, 0x8d68);
1862                 tg3_writephy(tp, 0x1c, 0x8d68);
1863         }
1864         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1865                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1866                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1867                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1868                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1869                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1870                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1871                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1872                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1873         }
1874         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1875                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1876                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1877                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1878                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1879                         tg3_writephy(tp, MII_TG3_TEST1,
1880                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1881                 } else
1882                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1883                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1884         }
1885         /* Set Extended packet length bit (bit 14) on all chips that */
1886         /* support jumbo frames */
1887         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1888                 /* Cannot do read-modify-write on 5401 */
1889                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1890         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1891                 u32 phy_reg;
1892
1893                 /* Set bit 14 with read-modify-write to preserve other bits */
1894                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1895                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1896                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1897         }
1898
1899         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1900          * jumbo frames transmission.
1901          */
1902         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1903                 u32 phy_reg;
1904
1905                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1906                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1907                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1908         }
1909
1910         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1911                 /* adjust output voltage */
1912                 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1913         }
1914
1915         tg3_phy_toggle_automdix(tp, 1);
1916         tg3_phy_set_wirespeed(tp);
1917         return 0;
1918 }
1919
1920 static void tg3_frob_aux_power(struct tg3 *tp)
1921 {
1922         struct tg3 *tp_peer = tp;
1923
1924         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1925                 return;
1926
1927         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1928             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1929                 struct net_device *dev_peer;
1930
1931                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1932                 /* remove_one() may have been run on the peer. */
1933                 if (!dev_peer)
1934                         tp_peer = tp;
1935                 else
1936                         tp_peer = netdev_priv(dev_peer);
1937         }
1938
1939         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1940             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1941             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1942             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1943                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1944                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1945                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1946                                     (GRC_LCLCTRL_GPIO_OE0 |
1947                                      GRC_LCLCTRL_GPIO_OE1 |
1948                                      GRC_LCLCTRL_GPIO_OE2 |
1949                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1950                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1951                                     100);
1952                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) {
1953                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1954                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1955                                              GRC_LCLCTRL_GPIO_OE1 |
1956                                              GRC_LCLCTRL_GPIO_OE2 |
1957                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
1958                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
1959                                              tp->grc_local_ctrl;
1960                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1961
1962                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
1963                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1964
1965                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
1966                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1967                 } else {
1968                         u32 no_gpio2;
1969                         u32 grc_local_ctrl = 0;
1970
1971                         if (tp_peer != tp &&
1972                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1973                                 return;
1974
1975                         /* Workaround to prevent overdrawing Amps. */
1976                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1977                             ASIC_REV_5714) {
1978                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1979                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1980                                             grc_local_ctrl, 100);
1981                         }
1982
1983                         /* On 5753 and variants, GPIO2 cannot be used. */
1984                         no_gpio2 = tp->nic_sram_data_cfg &
1985                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1986
1987                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1988                                          GRC_LCLCTRL_GPIO_OE1 |
1989                                          GRC_LCLCTRL_GPIO_OE2 |
1990                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1991                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1992                         if (no_gpio2) {
1993                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1994                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
1995                         }
1996                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1997                                                     grc_local_ctrl, 100);
1998
1999                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2000
2001                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2002                                                     grc_local_ctrl, 100);
2003
2004                         if (!no_gpio2) {
2005                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2006                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2007                                             grc_local_ctrl, 100);
2008                         }
2009                 }
2010         } else {
2011                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2012                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2013                         if (tp_peer != tp &&
2014                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2015                                 return;
2016
2017                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2018                                     (GRC_LCLCTRL_GPIO_OE1 |
2019                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2020
2021                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2022                                     GRC_LCLCTRL_GPIO_OE1, 100);
2023
2024                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2025                                     (GRC_LCLCTRL_GPIO_OE1 |
2026                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2027                 }
2028         }
2029 }
2030
2031 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2032 {
2033         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2034                 return 1;
2035         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2036                 if (speed != SPEED_10)
2037                         return 1;
2038         } else if (speed == SPEED_10)
2039                 return 1;
2040
2041         return 0;
2042 }
2043
2044 static int tg3_setup_phy(struct tg3 *, int);
2045
2046 #define RESET_KIND_SHUTDOWN     0
2047 #define RESET_KIND_INIT         1
2048 #define RESET_KIND_SUSPEND      2
2049
2050 static void tg3_write_sig_post_reset(struct tg3 *, int);
2051 static int tg3_halt_cpu(struct tg3 *, u32);
2052 static int tg3_nvram_lock(struct tg3 *);
2053 static void tg3_nvram_unlock(struct tg3 *);
2054
2055 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2056 {
2057         u32 val;
2058
2059         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2060                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2061                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2062                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2063
2064                         sg_dig_ctrl |=
2065                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2066                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2067                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2068                 }
2069                 return;
2070         }
2071
2072         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2073                 tg3_bmcr_reset(tp);
2074                 val = tr32(GRC_MISC_CFG);
2075                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2076                 udelay(40);
2077                 return;
2078         } else if (do_low_power) {
2079                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2080                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2081
2082                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2083                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2084                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2085                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2086                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2087         }
2088
2089         /* The PHY should not be powered down on some chips because
2090          * of bugs.
2091          */
2092         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2093             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2094             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2095              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2096                 return;
2097
2098         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2099             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2100                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2101                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2102                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2103                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2104         }
2105
2106         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2107 }
2108
2109 /* tp->lock is held. */
2110 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2111 {
2112         u32 addr_high, addr_low;
2113         int i;
2114
2115         addr_high = ((tp->dev->dev_addr[0] << 8) |
2116                      tp->dev->dev_addr[1]);
2117         addr_low = ((tp->dev->dev_addr[2] << 24) |
2118                     (tp->dev->dev_addr[3] << 16) |
2119                     (tp->dev->dev_addr[4] <<  8) |
2120                     (tp->dev->dev_addr[5] <<  0));
2121         for (i = 0; i < 4; i++) {
2122                 if (i == 1 && skip_mac_1)
2123                         continue;
2124                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2125                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2126         }
2127
2128         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2129             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2130                 for (i = 0; i < 12; i++) {
2131                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2132                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2133                 }
2134         }
2135
2136         addr_high = (tp->dev->dev_addr[0] +
2137                      tp->dev->dev_addr[1] +
2138                      tp->dev->dev_addr[2] +
2139                      tp->dev->dev_addr[3] +
2140                      tp->dev->dev_addr[4] +
2141                      tp->dev->dev_addr[5]) &
2142                 TX_BACKOFF_SEED_MASK;
2143         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2144 }
2145
2146 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2147 {
2148         u32 misc_host_ctrl;
2149         bool device_should_wake, do_low_power;
2150
2151         /* Make sure register accesses (indirect or otherwise)
2152          * will function correctly.
2153          */
2154         pci_write_config_dword(tp->pdev,
2155                                TG3PCI_MISC_HOST_CTRL,
2156                                tp->misc_host_ctrl);
2157
2158         switch (state) {
2159         case PCI_D0:
2160                 pci_enable_wake(tp->pdev, state, false);
2161                 pci_set_power_state(tp->pdev, PCI_D0);
2162
2163                 /* Switch out of Vaux if it is a NIC */
2164                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2165                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2166
2167                 return 0;
2168
2169         case PCI_D1:
2170         case PCI_D2:
2171         case PCI_D3hot:
2172                 break;
2173
2174         default:
2175                 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2176                         tp->dev->name, state);
2177                 return -EINVAL;
2178         }
2179
2180         /* Restore the CLKREQ setting. */
2181         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2182                 u16 lnkctl;
2183
2184                 pci_read_config_word(tp->pdev,
2185                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2186                                      &lnkctl);
2187                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2188                 pci_write_config_word(tp->pdev,
2189                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2190                                       lnkctl);
2191         }
2192
2193         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2194         tw32(TG3PCI_MISC_HOST_CTRL,
2195              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2196
2197         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2198                              device_may_wakeup(&tp->pdev->dev) &&
2199                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2200
2201         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2202                 do_low_power = false;
2203                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2204                     !tp->link_config.phy_is_low_power) {
2205                         struct phy_device *phydev;
2206                         u32 phyid, advertising;
2207
2208                         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
2209
2210                         tp->link_config.phy_is_low_power = 1;
2211
2212                         tp->link_config.orig_speed = phydev->speed;
2213                         tp->link_config.orig_duplex = phydev->duplex;
2214                         tp->link_config.orig_autoneg = phydev->autoneg;
2215                         tp->link_config.orig_advertising = phydev->advertising;
2216
2217                         advertising = ADVERTISED_TP |
2218                                       ADVERTISED_Pause |
2219                                       ADVERTISED_Autoneg |
2220                                       ADVERTISED_10baseT_Half;
2221
2222                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2223                             device_should_wake) {
2224                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2225                                         advertising |=
2226                                                 ADVERTISED_100baseT_Half |
2227                                                 ADVERTISED_100baseT_Full |
2228                                                 ADVERTISED_10baseT_Full;
2229                                 else
2230                                         advertising |= ADVERTISED_10baseT_Full;
2231                         }
2232
2233                         phydev->advertising = advertising;
2234
2235                         phy_start_aneg(phydev);
2236
2237                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2238                         if (phyid != TG3_PHY_ID_BCMAC131) {
2239                                 phyid &= TG3_PHY_OUI_MASK;
2240                                 if (phyid == TG3_PHY_OUI_1 &&
2241                                     phyid == TG3_PHY_OUI_2 &&
2242                                     phyid == TG3_PHY_OUI_3)
2243                                         do_low_power = true;
2244                         }
2245                 }
2246         } else {
2247                 do_low_power = true;
2248
2249                 if (tp->link_config.phy_is_low_power == 0) {
2250                         tp->link_config.phy_is_low_power = 1;
2251                         tp->link_config.orig_speed = tp->link_config.speed;
2252                         tp->link_config.orig_duplex = tp->link_config.duplex;
2253                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2254                 }
2255
2256                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2257                         tp->link_config.speed = SPEED_10;
2258                         tp->link_config.duplex = DUPLEX_HALF;
2259                         tp->link_config.autoneg = AUTONEG_ENABLE;
2260                         tg3_setup_phy(tp, 0);
2261                 }
2262         }
2263
2264         __tg3_set_mac_addr(tp, 0);
2265
2266         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2267                 u32 val;
2268
2269                 val = tr32(GRC_VCPU_EXT_CTRL);
2270                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2271         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2272                 int i;
2273                 u32 val;
2274
2275                 for (i = 0; i < 200; i++) {
2276                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2277                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2278                                 break;
2279                         msleep(1);
2280                 }
2281         }
2282         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2283                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2284                                                      WOL_DRV_STATE_SHUTDOWN |
2285                                                      WOL_DRV_WOL |
2286                                                      WOL_SET_MAGIC_PKT);
2287
2288         if (device_should_wake) {
2289                 u32 mac_mode;
2290
2291                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2292                         if (do_low_power) {
2293                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2294                                 udelay(40);
2295                         }
2296
2297                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2298                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2299                         else
2300                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2301
2302                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2303                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2304                             ASIC_REV_5700) {
2305                                 u32 speed = (tp->tg3_flags &
2306                                              TG3_FLAG_WOL_SPEED_100MB) ?
2307                                              SPEED_100 : SPEED_10;
2308                                 if (tg3_5700_link_polarity(tp, speed))
2309                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2310                                 else
2311                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2312                         }
2313                 } else {
2314                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2315                 }
2316
2317                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2318                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2319
2320                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2321                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2322                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2323                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2324                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2325                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2326
2327                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2328                         mac_mode |= tp->mac_mode &
2329                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2330                         if (mac_mode & MAC_MODE_APE_TX_EN)
2331                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2332                 }
2333
2334                 tw32_f(MAC_MODE, mac_mode);
2335                 udelay(100);
2336
2337                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2338                 udelay(10);
2339         }
2340
2341         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2342             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2343              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2344                 u32 base_val;
2345
2346                 base_val = tp->pci_clock_ctrl;
2347                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2348                              CLOCK_CTRL_TXCLK_DISABLE);
2349
2350                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2351                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2352         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2353                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2354                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2355                 /* do nothing */
2356         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2357                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2358                 u32 newbits1, newbits2;
2359
2360                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2361                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2362                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2363                                     CLOCK_CTRL_TXCLK_DISABLE |
2364                                     CLOCK_CTRL_ALTCLK);
2365                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2366                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2367                         newbits1 = CLOCK_CTRL_625_CORE;
2368                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2369                 } else {
2370                         newbits1 = CLOCK_CTRL_ALTCLK;
2371                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2372                 }
2373
2374                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2375                             40);
2376
2377                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2378                             40);
2379
2380                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2381                         u32 newbits3;
2382
2383                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2384                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2385                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2386                                             CLOCK_CTRL_TXCLK_DISABLE |
2387                                             CLOCK_CTRL_44MHZ_CORE);
2388                         } else {
2389                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2390                         }
2391
2392                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2393                                     tp->pci_clock_ctrl | newbits3, 40);
2394                 }
2395         }
2396
2397         if (!(device_should_wake) &&
2398             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2399                 tg3_power_down_phy(tp, do_low_power);
2400
2401         tg3_frob_aux_power(tp);
2402
2403         /* Workaround for unstable PLL clock */
2404         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2405             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2406                 u32 val = tr32(0x7d00);
2407
2408                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2409                 tw32(0x7d00, val);
2410                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2411                         int err;
2412
2413                         err = tg3_nvram_lock(tp);
2414                         tg3_halt_cpu(tp, RX_CPU_BASE);
2415                         if (!err)
2416                                 tg3_nvram_unlock(tp);
2417                 }
2418         }
2419
2420         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2421
2422         if (device_should_wake)
2423                 pci_enable_wake(tp->pdev, state, true);
2424
2425         /* Finally, set the new power state. */
2426         pci_set_power_state(tp->pdev, state);
2427
2428         return 0;
2429 }
2430
2431 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2432 {
2433         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2434         case MII_TG3_AUX_STAT_10HALF:
2435                 *speed = SPEED_10;
2436                 *duplex = DUPLEX_HALF;
2437                 break;
2438
2439         case MII_TG3_AUX_STAT_10FULL:
2440                 *speed = SPEED_10;
2441                 *duplex = DUPLEX_FULL;
2442                 break;
2443
2444         case MII_TG3_AUX_STAT_100HALF:
2445                 *speed = SPEED_100;
2446                 *duplex = DUPLEX_HALF;
2447                 break;
2448
2449         case MII_TG3_AUX_STAT_100FULL:
2450                 *speed = SPEED_100;
2451                 *duplex = DUPLEX_FULL;
2452                 break;
2453
2454         case MII_TG3_AUX_STAT_1000HALF:
2455                 *speed = SPEED_1000;
2456                 *duplex = DUPLEX_HALF;
2457                 break;
2458
2459         case MII_TG3_AUX_STAT_1000FULL:
2460                 *speed = SPEED_1000;
2461                 *duplex = DUPLEX_FULL;
2462                 break;
2463
2464         default:
2465                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2466                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2467                                  SPEED_10;
2468                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2469                                   DUPLEX_HALF;
2470                         break;
2471                 }
2472                 *speed = SPEED_INVALID;
2473                 *duplex = DUPLEX_INVALID;
2474                 break;
2475         }
2476 }
2477
2478 static void tg3_phy_copper_begin(struct tg3 *tp)
2479 {
2480         u32 new_adv;
2481         int i;
2482
2483         if (tp->link_config.phy_is_low_power) {
2484                 /* Entering low power mode.  Disable gigabit and
2485                  * 100baseT advertisements.
2486                  */
2487                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2488
2489                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2490                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2491                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2492                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2493
2494                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2495         } else if (tp->link_config.speed == SPEED_INVALID) {
2496                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2497                         tp->link_config.advertising &=
2498                                 ~(ADVERTISED_1000baseT_Half |
2499                                   ADVERTISED_1000baseT_Full);
2500
2501                 new_adv = ADVERTISE_CSMA;
2502                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2503                         new_adv |= ADVERTISE_10HALF;
2504                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2505                         new_adv |= ADVERTISE_10FULL;
2506                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2507                         new_adv |= ADVERTISE_100HALF;
2508                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2509                         new_adv |= ADVERTISE_100FULL;
2510
2511                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2512
2513                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2514
2515                 if (tp->link_config.advertising &
2516                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2517                         new_adv = 0;
2518                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2519                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2520                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2521                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2522                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2523                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2524                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2525                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2526                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2527                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2528                 } else {
2529                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2530                 }
2531         } else {
2532                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2533                 new_adv |= ADVERTISE_CSMA;
2534
2535                 /* Asking for a specific link mode. */
2536                 if (tp->link_config.speed == SPEED_1000) {
2537                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2538
2539                         if (tp->link_config.duplex == DUPLEX_FULL)
2540                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2541                         else
2542                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2543                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2544                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2545                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2546                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2547                 } else {
2548                         if (tp->link_config.speed == SPEED_100) {
2549                                 if (tp->link_config.duplex == DUPLEX_FULL)
2550                                         new_adv |= ADVERTISE_100FULL;
2551                                 else
2552                                         new_adv |= ADVERTISE_100HALF;
2553                         } else {
2554                                 if (tp->link_config.duplex == DUPLEX_FULL)
2555                                         new_adv |= ADVERTISE_10FULL;
2556                                 else
2557                                         new_adv |= ADVERTISE_10HALF;
2558                         }
2559                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2560
2561                         new_adv = 0;
2562                 }
2563
2564                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2565         }
2566
2567         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2568             tp->link_config.speed != SPEED_INVALID) {
2569                 u32 bmcr, orig_bmcr;
2570
2571                 tp->link_config.active_speed = tp->link_config.speed;
2572                 tp->link_config.active_duplex = tp->link_config.duplex;
2573
2574                 bmcr = 0;
2575                 switch (tp->link_config.speed) {
2576                 default:
2577                 case SPEED_10:
2578                         break;
2579
2580                 case SPEED_100:
2581                         bmcr |= BMCR_SPEED100;
2582                         break;
2583
2584                 case SPEED_1000:
2585                         bmcr |= TG3_BMCR_SPEED1000;
2586                         break;
2587                 }
2588
2589                 if (tp->link_config.duplex == DUPLEX_FULL)
2590                         bmcr |= BMCR_FULLDPLX;
2591
2592                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2593                     (bmcr != orig_bmcr)) {
2594                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2595                         for (i = 0; i < 1500; i++) {
2596                                 u32 tmp;
2597
2598                                 udelay(10);
2599                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2600                                     tg3_readphy(tp, MII_BMSR, &tmp))
2601                                         continue;
2602                                 if (!(tmp & BMSR_LSTATUS)) {
2603                                         udelay(40);
2604                                         break;
2605                                 }
2606                         }
2607                         tg3_writephy(tp, MII_BMCR, bmcr);
2608                         udelay(40);
2609                 }
2610         } else {
2611                 tg3_writephy(tp, MII_BMCR,
2612                              BMCR_ANENABLE | BMCR_ANRESTART);
2613         }
2614 }
2615
2616 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2617 {
2618         int err;
2619
2620         /* Turn off tap power management. */
2621         /* Set Extended packet length bit */
2622         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2623
2624         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2625         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2626
2627         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2628         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2629
2630         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2631         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2632
2633         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2634         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2635
2636         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2637         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2638
2639         udelay(40);
2640
2641         return err;
2642 }
2643
2644 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2645 {
2646         u32 adv_reg, all_mask = 0;
2647
2648         if (mask & ADVERTISED_10baseT_Half)
2649                 all_mask |= ADVERTISE_10HALF;
2650         if (mask & ADVERTISED_10baseT_Full)
2651                 all_mask |= ADVERTISE_10FULL;
2652         if (mask & ADVERTISED_100baseT_Half)
2653                 all_mask |= ADVERTISE_100HALF;
2654         if (mask & ADVERTISED_100baseT_Full)
2655                 all_mask |= ADVERTISE_100FULL;
2656
2657         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2658                 return 0;
2659
2660         if ((adv_reg & all_mask) != all_mask)
2661                 return 0;
2662         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2663                 u32 tg3_ctrl;
2664
2665                 all_mask = 0;
2666                 if (mask & ADVERTISED_1000baseT_Half)
2667                         all_mask |= ADVERTISE_1000HALF;
2668                 if (mask & ADVERTISED_1000baseT_Full)
2669                         all_mask |= ADVERTISE_1000FULL;
2670
2671                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2672                         return 0;
2673
2674                 if ((tg3_ctrl & all_mask) != all_mask)
2675                         return 0;
2676         }
2677         return 1;
2678 }
2679
2680 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2681 {
2682         u32 curadv, reqadv;
2683
2684         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2685                 return 1;
2686
2687         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2688         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2689
2690         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2691                 if (curadv != reqadv)
2692                         return 0;
2693
2694                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2695                         tg3_readphy(tp, MII_LPA, rmtadv);
2696         } else {
2697                 /* Reprogram the advertisement register, even if it
2698                  * does not affect the current link.  If the link
2699                  * gets renegotiated in the future, we can save an
2700                  * additional renegotiation cycle by advertising
2701                  * it correctly in the first place.
2702                  */
2703                 if (curadv != reqadv) {
2704                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2705                                      ADVERTISE_PAUSE_ASYM);
2706                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2707                 }
2708         }
2709
2710         return 1;
2711 }
2712
2713 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2714 {
2715         int current_link_up;
2716         u32 bmsr, dummy;
2717         u32 lcl_adv, rmt_adv;
2718         u16 current_speed;
2719         u8 current_duplex;
2720         int i, err;
2721
2722         tw32(MAC_EVENT, 0);
2723
2724         tw32_f(MAC_STATUS,
2725              (MAC_STATUS_SYNC_CHANGED |
2726               MAC_STATUS_CFG_CHANGED |
2727               MAC_STATUS_MI_COMPLETION |
2728               MAC_STATUS_LNKSTATE_CHANGED));
2729         udelay(40);
2730
2731         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2732                 tw32_f(MAC_MI_MODE,
2733                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2734                 udelay(80);
2735         }
2736
2737         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2738
2739         /* Some third-party PHYs need to be reset on link going
2740          * down.
2741          */
2742         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2743              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2744              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2745             netif_carrier_ok(tp->dev)) {
2746                 tg3_readphy(tp, MII_BMSR, &bmsr);
2747                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2748                     !(bmsr & BMSR_LSTATUS))
2749                         force_reset = 1;
2750         }
2751         if (force_reset)
2752                 tg3_phy_reset(tp);
2753
2754         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2755                 tg3_readphy(tp, MII_BMSR, &bmsr);
2756                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2757                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2758                         bmsr = 0;
2759
2760                 if (!(bmsr & BMSR_LSTATUS)) {
2761                         err = tg3_init_5401phy_dsp(tp);
2762                         if (err)
2763                                 return err;
2764
2765                         tg3_readphy(tp, MII_BMSR, &bmsr);
2766                         for (i = 0; i < 1000; i++) {
2767                                 udelay(10);
2768                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2769                                     (bmsr & BMSR_LSTATUS)) {
2770                                         udelay(40);
2771                                         break;
2772                                 }
2773                         }
2774
2775                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
2776                             !(bmsr & BMSR_LSTATUS) &&
2777                             tp->link_config.active_speed == SPEED_1000) {
2778                                 err = tg3_phy_reset(tp);
2779                                 if (!err)
2780                                         err = tg3_init_5401phy_dsp(tp);
2781                                 if (err)
2782                                         return err;
2783                         }
2784                 }
2785         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2786                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2787                 /* 5701 {A0,B0} CRC bug workaround */
2788                 tg3_writephy(tp, 0x15, 0x0a75);
2789                 tg3_writephy(tp, 0x1c, 0x8c68);
2790                 tg3_writephy(tp, 0x1c, 0x8d68);
2791                 tg3_writephy(tp, 0x1c, 0x8c68);
2792         }
2793
2794         /* Clear pending interrupts... */
2795         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2796         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2797
2798         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
2799                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
2800         else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
2801                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
2802
2803         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2804             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2805                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
2806                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2807                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
2808                 else
2809                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
2810         }
2811
2812         current_link_up = 0;
2813         current_speed = SPEED_INVALID;
2814         current_duplex = DUPLEX_INVALID;
2815
2816         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
2817                 u32 val;
2818
2819                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
2820                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
2821                 if (!(val & (1 << 10))) {
2822                         val |= (1 << 10);
2823                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2824                         goto relink;
2825                 }
2826         }
2827
2828         bmsr = 0;
2829         for (i = 0; i < 100; i++) {
2830                 tg3_readphy(tp, MII_BMSR, &bmsr);
2831                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2832                     (bmsr & BMSR_LSTATUS))
2833                         break;
2834                 udelay(40);
2835         }
2836
2837         if (bmsr & BMSR_LSTATUS) {
2838                 u32 aux_stat, bmcr;
2839
2840                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
2841                 for (i = 0; i < 2000; i++) {
2842                         udelay(10);
2843                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
2844                             aux_stat)
2845                                 break;
2846                 }
2847
2848                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
2849                                              &current_speed,
2850                                              &current_duplex);
2851
2852                 bmcr = 0;
2853                 for (i = 0; i < 200; i++) {
2854                         tg3_readphy(tp, MII_BMCR, &bmcr);
2855                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
2856                                 continue;
2857                         if (bmcr && bmcr != 0x7fff)
2858                                 break;
2859                         udelay(10);
2860                 }
2861
2862                 lcl_adv = 0;
2863                 rmt_adv = 0;
2864
2865                 tp->link_config.active_speed = current_speed;
2866                 tp->link_config.active_duplex = current_duplex;
2867
2868                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2869                         if ((bmcr & BMCR_ANENABLE) &&
2870                             tg3_copper_is_advertising_all(tp,
2871                                                 tp->link_config.advertising)) {
2872                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
2873                                                                   &rmt_adv))
2874                                         current_link_up = 1;
2875                         }
2876                 } else {
2877                         if (!(bmcr & BMCR_ANENABLE) &&
2878                             tp->link_config.speed == current_speed &&
2879                             tp->link_config.duplex == current_duplex &&
2880                             tp->link_config.flowctrl ==
2881                             tp->link_config.active_flowctrl) {
2882                                 current_link_up = 1;
2883                         }
2884                 }
2885
2886                 if (current_link_up == 1 &&
2887                     tp->link_config.active_duplex == DUPLEX_FULL)
2888                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2889         }
2890
2891 relink:
2892         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
2893                 u32 tmp;
2894
2895                 tg3_phy_copper_begin(tp);
2896
2897                 tg3_readphy(tp, MII_BMSR, &tmp);
2898                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
2899                     (tmp & BMSR_LSTATUS))
2900                         current_link_up = 1;
2901         }
2902
2903         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
2904         if (current_link_up == 1) {
2905                 if (tp->link_config.active_speed == SPEED_100 ||
2906                     tp->link_config.active_speed == SPEED_10)
2907                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
2908                 else
2909                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2910         } else
2911                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2912
2913         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2914         if (tp->link_config.active_duplex == DUPLEX_HALF)
2915                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2916
2917         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
2918                 if (current_link_up == 1 &&
2919                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
2920                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2921                 else
2922                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2923         }
2924
2925         /* ??? Without this setting Netgear GA302T PHY does not
2926          * ??? send/receive packets...
2927          */
2928         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2929             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2930                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2931                 tw32_f(MAC_MI_MODE, tp->mi_mode);
2932                 udelay(80);
2933         }
2934
2935         tw32_f(MAC_MODE, tp->mac_mode);
2936         udelay(40);
2937
2938         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2939                 /* Polled via timer. */
2940                 tw32_f(MAC_EVENT, 0);
2941         } else {
2942                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2943         }
2944         udelay(40);
2945
2946         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2947             current_link_up == 1 &&
2948             tp->link_config.active_speed == SPEED_1000 &&
2949             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2950              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2951                 udelay(120);
2952                 tw32_f(MAC_STATUS,
2953                      (MAC_STATUS_SYNC_CHANGED |
2954                       MAC_STATUS_CFG_CHANGED));
2955                 udelay(40);
2956                 tg3_write_mem(tp,
2957                               NIC_SRAM_FIRMWARE_MBOX,
2958                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2959         }
2960
2961         /* Prevent send BD corruption. */
2962         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2963                 u16 oldlnkctl, newlnkctl;
2964
2965                 pci_read_config_word(tp->pdev,
2966                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2967                                      &oldlnkctl);
2968                 if (tp->link_config.active_speed == SPEED_100 ||
2969                     tp->link_config.active_speed == SPEED_10)
2970                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
2971                 else
2972                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
2973                 if (newlnkctl != oldlnkctl)
2974                         pci_write_config_word(tp->pdev,
2975                                               tp->pcie_cap + PCI_EXP_LNKCTL,
2976                                               newlnkctl);
2977         }
2978
2979         if (current_link_up != netif_carrier_ok(tp->dev)) {
2980                 if (current_link_up)
2981                         netif_carrier_on(tp->dev);
2982                 else
2983                         netif_carrier_off(tp->dev);
2984                 tg3_link_report(tp);
2985         }
2986
2987         return 0;
2988 }
2989
2990 struct tg3_fiber_aneginfo {
2991         int state;
2992 #define ANEG_STATE_UNKNOWN              0
2993 #define ANEG_STATE_AN_ENABLE            1
2994 #define ANEG_STATE_RESTART_INIT         2
2995 #define ANEG_STATE_RESTART              3
2996 #define ANEG_STATE_DISABLE_LINK_OK      4
2997 #define ANEG_STATE_ABILITY_DETECT_INIT  5
2998 #define ANEG_STATE_ABILITY_DETECT       6
2999 #define ANEG_STATE_ACK_DETECT_INIT      7
3000 #define ANEG_STATE_ACK_DETECT           8
3001 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3002 #define ANEG_STATE_COMPLETE_ACK         10
3003 #define ANEG_STATE_IDLE_DETECT_INIT     11
3004 #define ANEG_STATE_IDLE_DETECT          12
3005 #define ANEG_STATE_LINK_OK              13
3006 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3007 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3008
3009         u32 flags;
3010 #define MR_AN_ENABLE            0x00000001
3011 #define MR_RESTART_AN           0x00000002
3012 #define MR_AN_COMPLETE          0x00000004
3013 #define MR_PAGE_RX              0x00000008
3014 #define MR_NP_LOADED            0x00000010
3015 #define MR_TOGGLE_TX            0x00000020
3016 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3017 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3018 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3019 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3020 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3021 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3022 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3023 #define MR_TOGGLE_RX            0x00002000
3024 #define MR_NP_RX                0x00004000
3025
3026 #define MR_LINK_OK              0x80000000
3027
3028         unsigned long link_time, cur_time;
3029
3030         u32 ability_match_cfg;
3031         int ability_match_count;
3032
3033         char ability_match, idle_match, ack_match;
3034
3035         u32 txconfig, rxconfig;
3036 #define ANEG_CFG_NP             0x00000080
3037 #define ANEG_CFG_ACK            0x00000040
3038 #define ANEG_CFG_RF2            0x00000020
3039 #define ANEG_CFG_RF1            0x00000010
3040 #define ANEG_CFG_PS2            0x00000001
3041 #define ANEG_CFG_PS1            0x00008000
3042 #define ANEG_CFG_HD             0x00004000
3043 #define ANEG_CFG_FD             0x00002000
3044 #define ANEG_CFG_INVAL          0x00001f06
3045
3046 };
3047 #define ANEG_OK         0
3048 #define ANEG_DONE       1
3049 #define ANEG_TIMER_ENAB 2
3050 #define ANEG_FAILED     -1
3051
3052 #define ANEG_STATE_SETTLE_TIME  10000
3053
3054 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3055                                    struct tg3_fiber_aneginfo *ap)
3056 {
3057         u16 flowctrl;
3058         unsigned long delta;
3059         u32 rx_cfg_reg;
3060         int ret;
3061
3062         if (ap->state == ANEG_STATE_UNKNOWN) {
3063                 ap->rxconfig = 0;
3064                 ap->link_time = 0;
3065                 ap->cur_time = 0;
3066                 ap->ability_match_cfg = 0;
3067                 ap->ability_match_count = 0;
3068                 ap->ability_match = 0;
3069                 ap->idle_match = 0;
3070                 ap->ack_match = 0;
3071         }
3072         ap->cur_time++;
3073
3074         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3075                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3076
3077                 if (rx_cfg_reg != ap->ability_match_cfg) {
3078                         ap->ability_match_cfg = rx_cfg_reg;
3079                         ap->ability_match = 0;
3080                         ap->ability_match_count = 0;
3081                 } else {
3082                         if (++ap->ability_match_count > 1) {
3083                                 ap->ability_match = 1;
3084                                 ap->ability_match_cfg = rx_cfg_reg;
3085                         }
3086                 }
3087                 if (rx_cfg_reg & ANEG_CFG_ACK)
3088                         ap->ack_match = 1;
3089                 else
3090                         ap->ack_match = 0;
3091
3092                 ap->idle_match = 0;
3093         } else {
3094                 ap->idle_match = 1;
3095                 ap->ability_match_cfg = 0;
3096                 ap->ability_match_count = 0;
3097                 ap->ability_match = 0;
3098                 ap->ack_match = 0;
3099
3100                 rx_cfg_reg = 0;
3101         }
3102
3103         ap->rxconfig = rx_cfg_reg;
3104         ret = ANEG_OK;
3105
3106         switch(ap->state) {
3107         case ANEG_STATE_UNKNOWN:
3108                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3109                         ap->state = ANEG_STATE_AN_ENABLE;
3110
3111                 /* fallthru */
3112         case ANEG_STATE_AN_ENABLE:
3113                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3114                 if (ap->flags & MR_AN_ENABLE) {
3115                         ap->link_time = 0;
3116                         ap->cur_time = 0;
3117                         ap->ability_match_cfg = 0;
3118                         ap->ability_match_count = 0;
3119                         ap->ability_match = 0;
3120                         ap->idle_match = 0;
3121                         ap->ack_match = 0;
3122
3123                         ap->state = ANEG_STATE_RESTART_INIT;
3124                 } else {
3125                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3126                 }
3127                 break;
3128
3129         case ANEG_STATE_RESTART_INIT:
3130                 ap->link_time = ap->cur_time;
3131                 ap->flags &= ~(MR_NP_LOADED);
3132                 ap->txconfig = 0;
3133                 tw32(MAC_TX_AUTO_NEG, 0);
3134                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3135                 tw32_f(MAC_MODE, tp->mac_mode);
3136                 udelay(40);
3137
3138                 ret = ANEG_TIMER_ENAB;
3139                 ap->state = ANEG_STATE_RESTART;
3140
3141                 /* fallthru */
3142         case ANEG_STATE_RESTART:
3143                 delta = ap->cur_time - ap->link_time;
3144                 if (delta > ANEG_STATE_SETTLE_TIME) {
3145                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3146                 } else {
3147                         ret = ANEG_TIMER_ENAB;
3148                 }
3149                 break;
3150
3151         case ANEG_STATE_DISABLE_LINK_OK:
3152                 ret = ANEG_DONE;
3153                 break;
3154
3155         case ANEG_STATE_ABILITY_DETECT_INIT:
3156                 ap->flags &= ~(MR_TOGGLE_TX);
3157                 ap->txconfig = ANEG_CFG_FD;
3158                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3159                 if (flowctrl & ADVERTISE_1000XPAUSE)
3160                         ap->txconfig |= ANEG_CFG_PS1;
3161                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3162                         ap->txconfig |= ANEG_CFG_PS2;
3163                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3164                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3165                 tw32_f(MAC_MODE, tp->mac_mode);
3166                 udelay(40);
3167
3168                 ap->state = ANEG_STATE_ABILITY_DETECT;
3169                 break;
3170
3171         case ANEG_STATE_ABILITY_DETECT:
3172                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3173                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3174                 }
3175                 break;
3176
3177         case ANEG_STATE_ACK_DETECT_INIT:
3178                 ap->txconfig |= ANEG_CFG_ACK;
3179                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3180                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3181                 tw32_f(MAC_MODE, tp->mac_mode);
3182                 udelay(40);
3183
3184                 ap->state = ANEG_STATE_ACK_DETECT;
3185
3186                 /* fallthru */
3187         case ANEG_STATE_ACK_DETECT:
3188                 if (ap->ack_match != 0) {
3189                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3190                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3191                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3192                         } else {
3193                                 ap->state = ANEG_STATE_AN_ENABLE;
3194                         }
3195                 } else if (ap->ability_match != 0 &&
3196                            ap->rxconfig == 0) {
3197                         ap->state = ANEG_STATE_AN_ENABLE;
3198                 }
3199                 break;
3200
3201         case ANEG_STATE_COMPLETE_ACK_INIT:
3202                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3203                         ret = ANEG_FAILED;
3204                         break;
3205                 }
3206                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3207                                MR_LP_ADV_HALF_DUPLEX |
3208                                MR_LP_ADV_SYM_PAUSE |
3209                                MR_LP_ADV_ASYM_PAUSE |
3210                                MR_LP_ADV_REMOTE_FAULT1 |
3211                                MR_LP_ADV_REMOTE_FAULT2 |
3212                                MR_LP_ADV_NEXT_PAGE |
3213                                MR_TOGGLE_RX |
3214                                MR_NP_RX);
3215                 if (ap->rxconfig & ANEG_CFG_FD)
3216                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3217                 if (ap->rxconfig & ANEG_CFG_HD)
3218                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3219                 if (ap->rxconfig & ANEG_CFG_PS1)
3220                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3221                 if (ap->rxconfig & ANEG_CFG_PS2)
3222                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3223                 if (ap->rxconfig & ANEG_CFG_RF1)
3224                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3225                 if (ap->rxconfig & ANEG_CFG_RF2)
3226                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3227                 if (ap->rxconfig & ANEG_CFG_NP)
3228                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3229
3230                 ap->link_time = ap->cur_time;
3231
3232                 ap->flags ^= (MR_TOGGLE_TX);
3233                 if (ap->rxconfig & 0x0008)
3234                         ap->flags |= MR_TOGGLE_RX;
3235                 if (ap->rxconfig & ANEG_CFG_NP)
3236                         ap->flags |= MR_NP_RX;
3237                 ap->flags |= MR_PAGE_RX;
3238
3239                 ap->state = ANEG_STATE_COMPLETE_ACK;
3240                 ret = ANEG_TIMER_ENAB;
3241                 break;
3242
3243         case ANEG_STATE_COMPLETE_ACK:
3244                 if (ap->ability_match != 0 &&
3245                     ap->rxconfig == 0) {
3246                         ap->state = ANEG_STATE_AN_ENABLE;
3247                         break;
3248                 }
3249                 delta = ap->cur_time - ap->link_time;
3250                 if (delta > ANEG_STATE_SETTLE_TIME) {
3251                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3252                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3253                         } else {
3254                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3255                                     !(ap->flags & MR_NP_RX)) {
3256                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3257                                 } else {
3258                                         ret = ANEG_FAILED;
3259                                 }
3260                         }
3261                 }
3262                 break;
3263
3264         case ANEG_STATE_IDLE_DETECT_INIT:
3265                 ap->link_time = ap->cur_time;
3266                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3267                 tw32_f(MAC_MODE, tp->mac_mode);
3268                 udelay(40);
3269
3270                 ap->state = ANEG_STATE_IDLE_DETECT;
3271                 ret = ANEG_TIMER_ENAB;
3272                 break;
3273
3274         case ANEG_STATE_IDLE_DETECT:
3275                 if (ap->ability_match != 0 &&
3276                     ap->rxconfig == 0) {
3277                         ap->state = ANEG_STATE_AN_ENABLE;
3278                         break;
3279                 }
3280                 delta = ap->cur_time - ap->link_time;
3281                 if (delta > ANEG_STATE_SETTLE_TIME) {
3282                         /* XXX another gem from the Broadcom driver :( */
3283                         ap->state = ANEG_STATE_LINK_OK;
3284                 }
3285                 break;
3286
3287         case ANEG_STATE_LINK_OK:
3288                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3289                 ret = ANEG_DONE;
3290                 break;
3291
3292         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3293                 /* ??? unimplemented */
3294                 break;
3295
3296         case ANEG_STATE_NEXT_PAGE_WAIT:
3297                 /* ??? unimplemented */
3298                 break;
3299
3300         default:
3301                 ret = ANEG_FAILED;
3302                 break;
3303         }
3304
3305         return ret;
3306 }
3307
3308 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3309 {
3310         int res = 0;
3311         struct tg3_fiber_aneginfo aninfo;
3312         int status = ANEG_FAILED;
3313         unsigned int tick;
3314         u32 tmp;
3315
3316         tw32_f(MAC_TX_AUTO_NEG, 0);
3317
3318         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3319         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3320         udelay(40);
3321
3322         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3323         udelay(40);
3324
3325         memset(&aninfo, 0, sizeof(aninfo));
3326         aninfo.flags |= MR_AN_ENABLE;
3327         aninfo.state = ANEG_STATE_UNKNOWN;
3328         aninfo.cur_time = 0;
3329         tick = 0;
3330         while (++tick < 195000) {
3331                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3332                 if (status == ANEG_DONE || status == ANEG_FAILED)
3333                         break;
3334
3335                 udelay(1);
3336         }
3337
3338         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3339         tw32_f(MAC_MODE, tp->mac_mode);
3340         udelay(40);
3341
3342         *txflags = aninfo.txconfig;
3343         *rxflags = aninfo.flags;
3344
3345         if (status == ANEG_DONE &&
3346             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3347                              MR_LP_ADV_FULL_DUPLEX)))
3348                 res = 1;
3349
3350         return res;
3351 }
3352
3353 static void tg3_init_bcm8002(struct tg3 *tp)
3354 {
3355         u32 mac_status = tr32(MAC_STATUS);
3356         int i;
3357
3358         /* Reset when initting first time or we have a link. */
3359         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3360             !(mac_status & MAC_STATUS_PCS_SYNCED))
3361                 return;
3362
3363         /* Set PLL lock range. */
3364         tg3_writephy(tp, 0x16, 0x8007);
3365
3366         /* SW reset */
3367         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3368
3369         /* Wait for reset to complete. */
3370         /* XXX schedule_timeout() ... */
3371         for (i = 0; i < 500; i++)
3372                 udelay(10);
3373
3374         /* Config mode; select PMA/Ch 1 regs. */
3375         tg3_writephy(tp, 0x10, 0x8411);
3376
3377         /* Enable auto-lock and comdet, select txclk for tx. */
3378         tg3_writephy(tp, 0x11, 0x0a10);
3379
3380         tg3_writephy(tp, 0x18, 0x00a0);
3381         tg3_writephy(tp, 0x16, 0x41ff);
3382
3383         /* Assert and deassert POR. */
3384         tg3_writephy(tp, 0x13, 0x0400);
3385         udelay(40);
3386         tg3_writephy(tp, 0x13, 0x0000);
3387
3388         tg3_writephy(tp, 0x11, 0x0a50);
3389         udelay(40);
3390         tg3_writephy(tp, 0x11, 0x0a10);
3391
3392         /* Wait for signal to stabilize */
3393         /* XXX schedule_timeout() ... */
3394         for (i = 0; i < 15000; i++)
3395                 udelay(10);
3396
3397         /* Deselect the channel register so we can read the PHYID
3398          * later.
3399          */
3400         tg3_writephy(tp, 0x10, 0x8011);
3401 }
3402
3403 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3404 {
3405         u16 flowctrl;
3406         u32 sg_dig_ctrl, sg_dig_status;
3407         u32 serdes_cfg, expected_sg_dig_ctrl;
3408         int workaround, port_a;
3409         int current_link_up;
3410
3411         serdes_cfg = 0;
3412         expected_sg_dig_ctrl = 0;
3413         workaround = 0;
3414         port_a = 1;
3415         current_link_up = 0;
3416
3417         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3418             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3419                 workaround = 1;
3420                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3421                         port_a = 0;
3422
3423                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3424                 /* preserve bits 20-23 for voltage regulator */
3425                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3426         }
3427
3428         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3429
3430         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3431                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3432                         if (workaround) {
3433                                 u32 val = serdes_cfg;
3434
3435                                 if (port_a)
3436                                         val |= 0xc010000;
3437                                 else
3438                                         val |= 0x4010000;
3439                                 tw32_f(MAC_SERDES_CFG, val);
3440                         }
3441
3442                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3443                 }
3444                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3445                         tg3_setup_flow_control(tp, 0, 0);
3446                         current_link_up = 1;
3447                 }
3448                 goto out;
3449         }
3450
3451         /* Want auto-negotiation.  */
3452         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3453
3454         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3455         if (flowctrl & ADVERTISE_1000XPAUSE)
3456                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3457         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3458                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3459
3460         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3461                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3462                     tp->serdes_counter &&
3463                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3464                                     MAC_STATUS_RCVD_CFG)) ==
3465                      MAC_STATUS_PCS_SYNCED)) {
3466                         tp->serdes_counter--;
3467                         current_link_up = 1;
3468                         goto out;
3469                 }
3470 restart_autoneg:
3471                 if (workaround)
3472                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3473                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3474                 udelay(5);
3475                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3476
3477                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3478                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3479         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3480                                  MAC_STATUS_SIGNAL_DET)) {
3481                 sg_dig_status = tr32(SG_DIG_STATUS);
3482                 mac_status = tr32(MAC_STATUS);
3483
3484                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3485                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3486                         u32 local_adv = 0, remote_adv = 0;
3487
3488                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3489                                 local_adv |= ADVERTISE_1000XPAUSE;
3490                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3491                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3492
3493                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3494                                 remote_adv |= LPA_1000XPAUSE;
3495                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3496                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3497
3498                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3499                         current_link_up = 1;
3500                         tp->serdes_counter = 0;
3501                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3502                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3503                         if (tp->serdes_counter)
3504                                 tp->serdes_counter--;
3505                         else {
3506                                 if (workaround) {
3507                                         u32 val = serdes_cfg;
3508
3509                                         if (port_a)
3510                                                 val |= 0xc010000;
3511                                         else
3512                                                 val |= 0x4010000;
3513
3514                                         tw32_f(MAC_SERDES_CFG, val);
3515                                 }
3516
3517                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3518                                 udelay(40);
3519
3520                                 /* Link parallel detection - link is up */
3521                                 /* only if we have PCS_SYNC and not */
3522                                 /* receiving config code words */
3523                                 mac_status = tr32(MAC_STATUS);
3524                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3525                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3526                                         tg3_setup_flow_control(tp, 0, 0);
3527                                         current_link_up = 1;
3528                                         tp->tg3_flags2 |=
3529                                                 TG3_FLG2_PARALLEL_DETECT;
3530                                         tp->serdes_counter =
3531                                                 SERDES_PARALLEL_DET_TIMEOUT;
3532                                 } else
3533                                         goto restart_autoneg;
3534                         }
3535                 }
3536         } else {
3537                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3538                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3539         }
3540
3541 out:
3542         return current_link_up;
3543 }
3544
3545 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3546 {
3547         int current_link_up = 0;
3548
3549         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3550                 goto out;
3551
3552         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3553                 u32 txflags, rxflags;
3554                 int i;
3555
3556                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3557                         u32 local_adv = 0, remote_adv = 0;
3558
3559                         if (txflags & ANEG_CFG_PS1)
3560                                 local_adv |= ADVERTISE_1000XPAUSE;
3561                         if (txflags & ANEG_CFG_PS2)
3562                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3563
3564                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3565                                 remote_adv |= LPA_1000XPAUSE;
3566                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3567                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3568
3569                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3570
3571                         current_link_up = 1;
3572                 }
3573                 for (i = 0; i < 30; i++) {
3574                         udelay(20);
3575                         tw32_f(MAC_STATUS,
3576                                (MAC_STATUS_SYNC_CHANGED |
3577                                 MAC_STATUS_CFG_CHANGED));
3578                         udelay(40);
3579                         if ((tr32(MAC_STATUS) &
3580                              (MAC_STATUS_SYNC_CHANGED |
3581                               MAC_STATUS_CFG_CHANGED)) == 0)
3582                                 break;
3583                 }
3584
3585                 mac_status = tr32(MAC_STATUS);
3586                 if (current_link_up == 0 &&
3587                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3588                     !(mac_status & MAC_STATUS_RCVD_CFG))
3589                         current_link_up = 1;
3590         } else {
3591                 tg3_setup_flow_control(tp, 0, 0);
3592
3593                 /* Forcing 1000FD link up. */
3594                 current_link_up = 1;
3595
3596                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3597                 udelay(40);
3598
3599                 tw32_f(MAC_MODE, tp->mac_mode);
3600                 udelay(40);
3601         }
3602
3603 out:
3604         return current_link_up;
3605 }
3606
3607 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3608 {
3609         u32 orig_pause_cfg;
3610         u16 orig_active_speed;
3611         u8 orig_active_duplex;
3612         u32 mac_status;
3613         int current_link_up;
3614         int i;
3615
3616         orig_pause_cfg = tp->link_config.active_flowctrl;
3617         orig_active_speed = tp->link_config.active_speed;
3618         orig_active_duplex = tp->link_config.active_duplex;
3619
3620         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3621             netif_carrier_ok(tp->dev) &&
3622             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3623                 mac_status = tr32(MAC_STATUS);
3624                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3625                                MAC_STATUS_SIGNAL_DET |
3626                                MAC_STATUS_CFG_CHANGED |
3627                                MAC_STATUS_RCVD_CFG);
3628                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3629                                    MAC_STATUS_SIGNAL_DET)) {
3630                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3631                                             MAC_STATUS_CFG_CHANGED));
3632                         return 0;
3633                 }
3634         }
3635
3636         tw32_f(MAC_TX_AUTO_NEG, 0);
3637
3638         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3639         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3640         tw32_f(MAC_MODE, tp->mac_mode);
3641         udelay(40);
3642
3643         if (tp->phy_id == PHY_ID_BCM8002)
3644                 tg3_init_bcm8002(tp);
3645
3646         /* Enable link change event even when serdes polling.  */
3647         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3648         udelay(40);
3649
3650         current_link_up = 0;
3651         mac_status = tr32(MAC_STATUS);
3652
3653         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3654                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3655         else
3656                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3657
3658         tp->hw_status->status =
3659                 (SD_STATUS_UPDATED |
3660                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3661
3662         for (i = 0; i < 100; i++) {
3663                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3664                                     MAC_STATUS_CFG_CHANGED));
3665                 udelay(5);
3666                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3667                                          MAC_STATUS_CFG_CHANGED |
3668                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3669                         break;
3670         }
3671
3672         mac_status = tr32(MAC_STATUS);
3673         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3674                 current_link_up = 0;
3675                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3676                     tp->serdes_counter == 0) {
3677                         tw32_f(MAC_MODE, (tp->mac_mode |
3678                                           MAC_MODE_SEND_CONFIGS));
3679                         udelay(1);
3680                         tw32_f(MAC_MODE, tp->mac_mode);
3681                 }
3682         }
3683
3684         if (current_link_up == 1) {
3685                 tp->link_config.active_speed = SPEED_1000;
3686                 tp->link_config.active_duplex = DUPLEX_FULL;
3687                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3688                                     LED_CTRL_LNKLED_OVERRIDE |
3689                                     LED_CTRL_1000MBPS_ON));
3690         } else {
3691                 tp->link_config.active_speed = SPEED_INVALID;
3692                 tp->link_config.active_duplex = DUPLEX_INVALID;
3693                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3694                                     LED_CTRL_LNKLED_OVERRIDE |
3695                                     LED_CTRL_TRAFFIC_OVERRIDE));
3696         }
3697
3698         if (current_link_up != netif_carrier_ok(tp->dev)) {
3699                 if (current_link_up)
3700                         netif_carrier_on(tp->dev);
3701                 else
3702                         netif_carrier_off(tp->dev);
3703                 tg3_link_report(tp);
3704         } else {
3705                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
3706                 if (orig_pause_cfg != now_pause_cfg ||
3707                     orig_active_speed != tp->link_config.active_speed ||
3708                     orig_active_duplex != tp->link_config.active_duplex)
3709                         tg3_link_report(tp);
3710         }
3711
3712         return 0;
3713 }
3714
3715 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3716 {
3717         int current_link_up, err = 0;
3718         u32 bmsr, bmcr;
3719         u16 current_speed;
3720         u8 current_duplex;
3721         u32 local_adv, remote_adv;
3722
3723         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3724         tw32_f(MAC_MODE, tp->mac_mode);
3725         udelay(40);
3726
3727         tw32(MAC_EVENT, 0);
3728
3729         tw32_f(MAC_STATUS,
3730              (MAC_STATUS_SYNC_CHANGED |
3731               MAC_STATUS_CFG_CHANGED |
3732               MAC_STATUS_MI_COMPLETION |
3733               MAC_STATUS_LNKSTATE_CHANGED));
3734         udelay(40);
3735
3736         if (force_reset)
3737                 tg3_phy_reset(tp);
3738
3739         current_link_up = 0;
3740         current_speed = SPEED_INVALID;
3741         current_duplex = DUPLEX_INVALID;
3742
3743         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3744         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3745         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3746                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3747                         bmsr |= BMSR_LSTATUS;
3748                 else
3749                         bmsr &= ~BMSR_LSTATUS;
3750         }
3751
3752         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3753
3754         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
3755             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3756                 /* do nothing, just check for link up at the end */
3757         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3758                 u32 adv, new_adv;
3759
3760                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3761                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
3762                                   ADVERTISE_1000XPAUSE |
3763                                   ADVERTISE_1000XPSE_ASYM |
3764                                   ADVERTISE_SLCT);
3765
3766                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3767
3768                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
3769                         new_adv |= ADVERTISE_1000XHALF;
3770                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
3771                         new_adv |= ADVERTISE_1000XFULL;
3772
3773                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
3774                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
3775                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
3776                         tg3_writephy(tp, MII_BMCR, bmcr);
3777
3778                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3779                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
3780                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3781
3782                         return err;
3783                 }
3784         } else {
3785                 u32 new_bmcr;
3786
3787                 bmcr &= ~BMCR_SPEED1000;
3788                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
3789
3790                 if (tp->link_config.duplex == DUPLEX_FULL)
3791                         new_bmcr |= BMCR_FULLDPLX;
3792
3793                 if (new_bmcr != bmcr) {
3794                         /* BMCR_SPEED1000 is a reserved bit that needs
3795                          * to be set on write.
3796                          */
3797                         new_bmcr |= BMCR_SPEED1000;
3798
3799                         /* Force a linkdown */
3800                         if (netif_carrier_ok(tp->dev)) {
3801                                 u32 adv;
3802
3803                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3804                                 adv &= ~(ADVERTISE_1000XFULL |
3805                                          ADVERTISE_1000XHALF |
3806                                          ADVERTISE_SLCT);
3807                                 tg3_writephy(tp, MII_ADVERTISE, adv);
3808                                 tg3_writephy(tp, MII_BMCR, bmcr |
3809                                                            BMCR_ANRESTART |
3810                                                            BMCR_ANENABLE);
3811                                 udelay(10);
3812                                 netif_carrier_off(tp->dev);
3813                         }
3814                         tg3_writephy(tp, MII_BMCR, new_bmcr);
3815                         bmcr = new_bmcr;
3816                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3817                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3818                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
3819                             ASIC_REV_5714) {
3820                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3821                                         bmsr |= BMSR_LSTATUS;
3822                                 else
3823                                         bmsr &= ~BMSR_LSTATUS;
3824                         }
3825                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3826                 }
3827         }
3828
3829         if (bmsr & BMSR_LSTATUS) {
3830                 current_speed = SPEED_1000;
3831                 current_link_up = 1;
3832                 if (bmcr & BMCR_FULLDPLX)
3833                         current_duplex = DUPLEX_FULL;
3834                 else
3835                         current_duplex = DUPLEX_HALF;
3836
3837                 local_adv = 0;
3838                 remote_adv = 0;
3839
3840                 if (bmcr & BMCR_ANENABLE) {
3841                         u32 common;
3842
3843                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
3844                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
3845                         common = local_adv & remote_adv;
3846                         if (common & (ADVERTISE_1000XHALF |
3847                                       ADVERTISE_1000XFULL)) {
3848                                 if (common & ADVERTISE_1000XFULL)
3849                                         current_duplex = DUPLEX_FULL;
3850                                 else
3851                                         current_duplex = DUPLEX_HALF;
3852                         }
3853                         else
3854                                 current_link_up = 0;
3855                 }
3856         }
3857
3858         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
3859                 tg3_setup_flow_control(tp, local_adv, remote_adv);
3860
3861         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3862         if (tp->link_config.active_duplex == DUPLEX_HALF)
3863                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3864
3865         tw32_f(MAC_MODE, tp->mac_mode);
3866         udelay(40);
3867
3868         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3869
3870         tp->link_config.active_speed = current_speed;
3871         tp->link_config.active_duplex = current_duplex;
3872
3873         if (current_link_up != netif_carrier_ok(tp->dev)) {
3874                 if (current_link_up)
3875                         netif_carrier_on(tp->dev);
3876                 else {
3877                         netif_carrier_off(tp->dev);
3878                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3879                 }
3880                 tg3_link_report(tp);
3881         }
3882         return err;
3883 }
3884
3885 static void tg3_serdes_parallel_detect(struct tg3 *tp)
3886 {
3887         if (tp->serdes_counter) {
3888                 /* Give autoneg time to complete. */
3889                 tp->serdes_counter--;
3890                 return;
3891         }
3892         if (!netif_carrier_ok(tp->dev) &&
3893             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
3894                 u32 bmcr;
3895
3896                 tg3_readphy(tp, MII_BMCR, &bmcr);
3897                 if (bmcr & BMCR_ANENABLE) {
3898                         u32 phy1, phy2;
3899
3900                         /* Select shadow register 0x1f */
3901                         tg3_writephy(tp, 0x1c, 0x7c00);
3902                         tg3_readphy(tp, 0x1c, &phy1);
3903
3904                         /* Select expansion interrupt status register */
3905                         tg3_writephy(tp, 0x17, 0x0f01);
3906                         tg3_readphy(tp, 0x15, &phy2);
3907                         tg3_readphy(tp, 0x15, &phy2);
3908
3909                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
3910                                 /* We have signal detect and not receiving
3911                                  * config code words, link is up by parallel
3912                                  * detection.
3913                                  */
3914
3915                                 bmcr &= ~BMCR_ANENABLE;
3916                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
3917                                 tg3_writephy(tp, MII_BMCR, bmcr);
3918                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
3919                         }
3920                 }
3921         }
3922         else if (netif_carrier_ok(tp->dev) &&
3923                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
3924                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3925                 u32 phy2;
3926
3927                 /* Select expansion interrupt status register */
3928                 tg3_writephy(tp, 0x17, 0x0f01);
3929                 tg3_readphy(tp, 0x15, &phy2);
3930                 if (phy2 & 0x20) {
3931                         u32 bmcr;
3932
3933                         /* Config code words received, turn on autoneg. */
3934                         tg3_readphy(tp, MII_BMCR, &bmcr);
3935                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
3936
3937                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3938
3939                 }
3940         }
3941 }
3942
3943 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
3944 {
3945         int err;
3946
3947         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
3948                 err = tg3_setup_fiber_phy(tp, force_reset);
3949         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
3950                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
3951         } else {
3952                 err = tg3_setup_copper_phy(tp, force_reset);
3953         }
3954
3955         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
3956                 u32 val, scale;
3957
3958                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
3959                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
3960                         scale = 65;
3961                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
3962                         scale = 6;
3963                 else
3964                         scale = 12;
3965
3966                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
3967                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
3968                 tw32(GRC_MISC_CFG, val);
3969         }
3970
3971         if (tp->link_config.active_speed == SPEED_1000 &&
3972             tp->link_config.active_duplex == DUPLEX_HALF)
3973                 tw32(MAC_TX_LENGTHS,
3974                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3975                       (6 << TX_LENGTHS_IPG_SHIFT) |
3976                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3977         else
3978                 tw32(MAC_TX_LENGTHS,
3979                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3980                       (6 << TX_LENGTHS_IPG_SHIFT) |
3981                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3982
3983         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3984                 if (netif_carrier_ok(tp->dev)) {
3985                         tw32(HOSTCC_STAT_COAL_TICKS,
3986                              tp->coal.stats_block_coalesce_usecs);
3987                 } else {
3988                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
3989                 }
3990         }
3991
3992         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
3993                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
3994                 if (!netif_carrier_ok(tp->dev))
3995                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
3996                               tp->pwrmgmt_thresh;
3997                 else
3998                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
3999                 tw32(PCIE_PWR_MGMT_THRESH, val);
4000         }
4001
4002         return err;
4003 }
4004
4005 /* This is called whenever we suspect that the system chipset is re-
4006  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4007  * is bogus tx completions. We try to recover by setting the
4008  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4009  * in the workqueue.
4010  */
4011 static void tg3_tx_recover(struct tg3 *tp)
4012 {
4013         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4014                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4015
4016         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4017                "mapped I/O cycles to the network device, attempting to "
4018                "recover. Please report the problem to the driver maintainer "
4019                "and include system chipset information.\n", tp->dev->name);
4020
4021         spin_lock(&tp->lock);
4022         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4023         spin_unlock(&tp->lock);
4024 }
4025
4026 static inline u32 tg3_tx_avail(struct tg3 *tp)
4027 {
4028         smp_mb();
4029         return (tp->tx_pending -
4030                 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
4031 }
4032
4033 /* Tigon3 never reports partial packet sends.  So we do not
4034  * need special logic to handle SKBs that have not had all
4035  * of their frags sent yet, like SunGEM does.
4036  */
4037 static void tg3_tx(struct tg3 *tp)
4038 {
4039         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
4040         u32 sw_idx = tp->tx_cons;
4041
4042         while (sw_idx != hw_idx) {
4043                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
4044                 struct sk_buff *skb = ri->skb;
4045                 int i, tx_bug = 0;
4046
4047                 if (unlikely(skb == NULL)) {
4048                         tg3_tx_recover(tp);
4049                         return;
4050                 }
4051
4052                 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
4053
4054                 ri->skb = NULL;
4055
4056                 sw_idx = NEXT_TX(sw_idx);
4057
4058                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4059                         ri = &tp->tx_buffers[sw_idx];
4060                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4061                                 tx_bug = 1;
4062                         sw_idx = NEXT_TX(sw_idx);
4063                 }
4064
4065                 dev_kfree_skb(skb);
4066
4067                 if (unlikely(tx_bug)) {
4068                         tg3_tx_recover(tp);
4069                         return;
4070                 }
4071         }
4072
4073         tp->tx_cons = sw_idx;
4074
4075         /* Need to make the tx_cons update visible to tg3_start_xmit()
4076          * before checking for netif_queue_stopped().  Without the
4077          * memory barrier, there is a small possibility that tg3_start_xmit()
4078          * will miss it and cause the queue to be stopped forever.
4079          */
4080         smp_mb();
4081
4082         if (unlikely(netif_queue_stopped(tp->dev) &&
4083                      (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
4084                 netif_tx_lock(tp->dev);
4085                 if (netif_queue_stopped(tp->dev) &&
4086                     (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
4087                         netif_wake_queue(tp->dev);
4088                 netif_tx_unlock(tp->dev);
4089         }
4090 }
4091
4092 /* Returns size of skb allocated or < 0 on error.
4093  *
4094  * We only need to fill in the address because the other members
4095  * of the RX descriptor are invariant, see tg3_init_rings.
4096  *
4097  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4098  * posting buffers we only dirty the first cache line of the RX
4099  * descriptor (containing the address).  Whereas for the RX status
4100  * buffers the cpu only reads the last cacheline of the RX descriptor
4101  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4102  */
4103 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
4104                             int src_idx, u32 dest_idx_unmasked)
4105 {
4106         struct tg3_rx_buffer_desc *desc;
4107         struct ring_info *map, *src_map;
4108         struct sk_buff *skb;
4109         dma_addr_t mapping;
4110         int skb_size, dest_idx;
4111
4112         src_map = NULL;
4113         switch (opaque_key) {
4114         case RXD_OPAQUE_RING_STD:
4115                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4116                 desc = &tp->rx_std[dest_idx];
4117                 map = &tp->rx_std_buffers[dest_idx];
4118                 if (src_idx >= 0)
4119                         src_map = &tp->rx_std_buffers[src_idx];
4120                 skb_size = tp->rx_pkt_buf_sz;
4121                 break;
4122
4123         case RXD_OPAQUE_RING_JUMBO:
4124                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4125                 desc = &tp->rx_jumbo[dest_idx];
4126                 map = &tp->rx_jumbo_buffers[dest_idx];
4127                 if (src_idx >= 0)
4128                         src_map = &tp->rx_jumbo_buffers[src_idx];
4129                 skb_size = RX_JUMBO_PKT_BUF_SZ;
4130                 break;
4131
4132         default:
4133                 return -EINVAL;
4134         }
4135
4136         /* Do not overwrite any of the map or rp information
4137          * until we are sure we can commit to a new buffer.
4138          *
4139          * Callers depend upon this behavior and assume that
4140          * we leave everything unchanged if we fail.
4141          */
4142         skb = netdev_alloc_skb(tp->dev, skb_size);
4143         if (skb == NULL)
4144                 return -ENOMEM;
4145
4146         skb_reserve(skb, tp->rx_offset);
4147
4148         mapping = pci_map_single(tp->pdev, skb->data,
4149                                  skb_size - tp->rx_offset,
4150                                  PCI_DMA_FROMDEVICE);
4151
4152         map->skb = skb;
4153         pci_unmap_addr_set(map, mapping, mapping);
4154
4155         if (src_map != NULL)
4156                 src_map->skb = NULL;
4157
4158         desc->addr_hi = ((u64)mapping >> 32);
4159         desc->addr_lo = ((u64)mapping & 0xffffffff);
4160
4161         return skb_size;
4162 }
4163
4164 /* We only need to move over in the address because the other
4165  * members of the RX descriptor are invariant.  See notes above
4166  * tg3_alloc_rx_skb for full details.
4167  */
4168 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
4169                            int src_idx, u32 dest_idx_unmasked)
4170 {
4171         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4172         struct ring_info *src_map, *dest_map;
4173         int dest_idx;
4174
4175         switch (opaque_key) {
4176         case RXD_OPAQUE_RING_STD:
4177                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4178                 dest_desc = &tp->rx_std[dest_idx];
4179                 dest_map = &tp->rx_std_buffers[dest_idx];
4180                 src_desc = &tp->rx_std[src_idx];
4181                 src_map = &tp->rx_std_buffers[src_idx];
4182                 break;
4183
4184         case RXD_OPAQUE_RING_JUMBO:
4185                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4186                 dest_desc = &tp->rx_jumbo[dest_idx];
4187                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
4188                 src_desc = &tp->rx_jumbo[src_idx];
4189                 src_map = &tp->rx_jumbo_buffers[src_idx];
4190                 break;
4191
4192         default:
4193                 return;
4194         }
4195
4196         dest_map->skb = src_map->skb;
4197         pci_unmap_addr_set(dest_map, mapping,
4198                            pci_unmap_addr(src_map, mapping));
4199         dest_desc->addr_hi = src_desc->addr_hi;
4200         dest_desc->addr_lo = src_desc->addr_lo;
4201
4202         src_map->skb = NULL;
4203 }
4204
4205 #if TG3_VLAN_TAG_USED
4206 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
4207 {
4208         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
4209 }
4210 #endif
4211
4212 /* The RX ring scheme is composed of multiple rings which post fresh
4213  * buffers to the chip, and one special ring the chip uses to report
4214  * status back to the host.
4215  *
4216  * The special ring reports the status of received packets to the
4217  * host.  The chip does not write into the original descriptor the
4218  * RX buffer was obtained from.  The chip simply takes the original
4219  * descriptor as provided by the host, updates the status and length
4220  * field, then writes this into the next status ring entry.
4221  *
4222  * Each ring the host uses to post buffers to the chip is described
4223  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4224  * it is first placed into the on-chip ram.  When the packet's length
4225  * is known, it walks down the TG3_BDINFO entries to select the ring.
4226  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4227  * which is within the range of the new packet's length is chosen.
4228  *
4229  * The "separate ring for rx status" scheme may sound queer, but it makes
4230  * sense from a cache coherency perspective.  If only the host writes
4231  * to the buffer post rings, and only the chip writes to the rx status
4232  * rings, then cache lines never move beyond shared-modified state.
4233  * If both the host and chip were to write into the same ring, cache line
4234  * eviction could occur since both entities want it in an exclusive state.
4235  */
4236 static int tg3_rx(struct tg3 *tp, int budget)
4237 {
4238         u32 work_mask, rx_std_posted = 0;
4239         u32 sw_idx = tp->rx_rcb_ptr;
4240         u16 hw_idx;
4241         int received;
4242
4243         hw_idx = tp->hw_status->idx[0].rx_producer;
4244         /*
4245          * We need to order the read of hw_idx and the read of
4246          * the opaque cookie.
4247          */
4248         rmb();
4249         work_mask = 0;
4250         received = 0;
4251         while (sw_idx != hw_idx && budget > 0) {
4252                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
4253                 unsigned int len;
4254                 struct sk_buff *skb;
4255                 dma_addr_t dma_addr;
4256                 u32 opaque_key, desc_idx, *post_ptr;
4257
4258                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4259                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4260                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4261                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
4262                                                   mapping);
4263                         skb = tp->rx_std_buffers[desc_idx].skb;
4264                         post_ptr = &tp->rx_std_ptr;
4265                         rx_std_posted++;
4266                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4267                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
4268                                                   mapping);
4269                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
4270                         post_ptr = &tp->rx_jumbo_ptr;
4271                 }
4272                 else {
4273                         goto next_pkt_nopost;
4274                 }
4275
4276                 work_mask |= opaque_key;
4277
4278                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4279                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4280                 drop_it:
4281                         tg3_recycle_rx(tp, opaque_key,
4282                                        desc_idx, *post_ptr);
4283                 drop_it_no_recycle:
4284                         /* Other statistics kept track of by card. */
4285                         tp->net_stats.rx_dropped++;
4286                         goto next_pkt;
4287                 }
4288
4289                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4290                       ETH_FCS_LEN;
4291
4292                 if (len > RX_COPY_THRESHOLD
4293                         && tp->rx_offset == NET_IP_ALIGN
4294                         /* rx_offset will likely not equal NET_IP_ALIGN
4295                          * if this is a 5701 card running in PCI-X mode
4296                          * [see tg3_get_invariants()]
4297                          */
4298                 ) {
4299                         int skb_size;
4300
4301                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
4302                                                     desc_idx, *post_ptr);
4303                         if (skb_size < 0)
4304                                 goto drop_it;
4305
4306                         pci_unmap_single(tp->pdev, dma_addr,
4307                                          skb_size - tp->rx_offset,
4308                                          PCI_DMA_FROMDEVICE);
4309
4310                         skb_put(skb, len);
4311                 } else {
4312                         struct sk_buff *copy_skb;
4313
4314                         tg3_recycle_rx(tp, opaque_key,
4315                                        desc_idx, *post_ptr);
4316
4317                         copy_skb = netdev_alloc_skb(tp->dev,
4318                                                     len + TG3_RAW_IP_ALIGN);
4319                         if (copy_skb == NULL)
4320                                 goto drop_it_no_recycle;
4321
4322                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4323                         skb_put(copy_skb, len);
4324                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4325                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4326                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4327
4328                         /* We'll reuse the original ring buffer. */
4329                         skb = copy_skb;
4330                 }
4331
4332                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4333                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4334                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4335                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4336                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4337                 else
4338                         skb->ip_summed = CHECKSUM_NONE;
4339
4340                 skb->protocol = eth_type_trans(skb, tp->dev);
4341 #if TG3_VLAN_TAG_USED
4342                 if (tp->vlgrp != NULL &&
4343                     desc->type_flags & RXD_FLAG_VLAN) {
4344                         tg3_vlan_rx(tp, skb,
4345                                     desc->err_vlan & RXD_VLAN_MASK);
4346                 } else
4347 #endif
4348                         netif_receive_skb(skb);
4349
4350                 received++;
4351                 budget--;
4352
4353 next_pkt:
4354                 (*post_ptr)++;
4355
4356                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4357                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4358
4359                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4360                                      TG3_64BIT_REG_LOW, idx);
4361                         work_mask &= ~RXD_OPAQUE_RING_STD;
4362                         rx_std_posted = 0;
4363                 }
4364 next_pkt_nopost:
4365                 sw_idx++;
4366                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4367
4368                 /* Refresh hw_idx to see if there is new work */
4369                 if (sw_idx == hw_idx) {
4370                         hw_idx = tp->hw_status->idx[0].rx_producer;
4371                         rmb();
4372                 }
4373         }
4374
4375         /* ACK the status ring. */
4376         tp->rx_rcb_ptr = sw_idx;
4377         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
4378
4379         /* Refill RX ring(s). */
4380         if (work_mask & RXD_OPAQUE_RING_STD) {
4381                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
4382                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4383                              sw_idx);
4384         }
4385         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4386                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
4387                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4388                              sw_idx);
4389         }
4390         mmiowb();
4391
4392         return received;
4393 }
4394
4395 static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
4396 {
4397         struct tg3_hw_status *sblk = tp->hw_status;
4398
4399         /* handle link change and other phy events */
4400         if (!(tp->tg3_flags &
4401               (TG3_FLAG_USE_LINKCHG_REG |
4402                TG3_FLAG_POLL_SERDES))) {
4403                 if (sblk->status & SD_STATUS_LINK_CHG) {
4404                         sblk->status = SD_STATUS_UPDATED |
4405                                 (sblk->status & ~SD_STATUS_LINK_CHG);
4406                         spin_lock(&tp->lock);
4407                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4408                                 tw32_f(MAC_STATUS,
4409                                      (MAC_STATUS_SYNC_CHANGED |
4410                                       MAC_STATUS_CFG_CHANGED |
4411                                       MAC_STATUS_MI_COMPLETION |
4412                                       MAC_STATUS_LNKSTATE_CHANGED));
4413                                 udelay(40);
4414                         } else
4415                                 tg3_setup_phy(tp, 0);
4416                         spin_unlock(&tp->lock);
4417                 }
4418         }
4419
4420         /* run TX completion thread */
4421         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
4422                 tg3_tx(tp);
4423                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4424                         return work_done;
4425         }
4426
4427         /* run RX thread, within the bounds set by NAPI.
4428          * All RX "locking" is done by ensuring outside
4429          * code synchronizes with tg3->napi.poll()
4430          */
4431         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
4432                 work_done += tg3_rx(tp, budget - work_done);
4433
4434         return work_done;
4435 }
4436
4437 static int tg3_poll(struct napi_struct *napi, int budget)
4438 {
4439         struct tg3 *tp = container_of(napi, struct tg3, napi);
4440         int work_done = 0;
4441         struct tg3_hw_status *sblk = tp->hw_status;
4442
4443         while (1) {
4444                 work_done = tg3_poll_work(tp, work_done, budget);
4445
4446                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4447                         goto tx_recovery;
4448
4449                 if (unlikely(work_done >= budget))
4450                         break;
4451
4452                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4453                         /* tp->last_tag is used in tg3_restart_ints() below
4454                          * to tell the hw how much work has been processed,
4455                          * so we must read it before checking for more work.
4456                          */
4457                         tp->last_tag = sblk->status_tag;
4458                         rmb();
4459                 } else
4460                         sblk->status &= ~SD_STATUS_UPDATED;
4461
4462                 if (likely(!tg3_has_work(tp))) {
4463                         netif_rx_complete(napi);
4464                         tg3_restart_ints(tp);
4465                         break;
4466                 }
4467         }
4468
4469         return work_done;
4470
4471 tx_recovery:
4472         /* work_done is guaranteed to be less than budget. */
4473         netif_rx_complete(napi);
4474         schedule_work(&tp->reset_task);
4475         return work_done;
4476 }
4477
4478 static void tg3_irq_quiesce(struct tg3 *tp)
4479 {
4480         BUG_ON(tp->irq_sync);
4481
4482         tp->irq_sync = 1;
4483         smp_mb();
4484
4485         synchronize_irq(tp->pdev->irq);
4486 }
4487
4488 static inline int tg3_irq_sync(struct tg3 *tp)
4489 {
4490         return tp->irq_sync;
4491 }
4492
4493 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4494  * If irq_sync is non-zero, then the IRQ handler must be synchronized
4495  * with as well.  Most of the time, this is not necessary except when
4496  * shutting down the device.
4497  */
4498 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4499 {
4500         spin_lock_bh(&tp->lock);
4501         if (irq_sync)
4502                 tg3_irq_quiesce(tp);
4503 }
4504
4505 static inline void tg3_full_unlock(struct tg3 *tp)
4506 {
4507         spin_unlock_bh(&tp->lock);
4508 }
4509
4510 /* One-shot MSI handler - Chip automatically disables interrupt
4511  * after sending MSI so driver doesn't have to do it.
4512  */
4513 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4514 {
4515         struct net_device *dev = dev_id;
4516         struct tg3 *tp = netdev_priv(dev);
4517
4518         prefetch(tp->hw_status);
4519         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4520
4521         if (likely(!tg3_irq_sync(tp)))
4522                 netif_rx_schedule(&tp->napi);
4523
4524         return IRQ_HANDLED;
4525 }
4526
4527 /* MSI ISR - No need to check for interrupt sharing and no need to
4528  * flush status block and interrupt mailbox. PCI ordering rules
4529  * guarantee that MSI will arrive after the status block.
4530  */
4531 static irqreturn_t tg3_msi(int irq, void *dev_id)
4532 {
4533         struct net_device *dev = dev_id;
4534         struct tg3 *tp = netdev_priv(dev);
4535
4536         prefetch(tp->hw_status);
4537         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4538         /*
4539          * Writing any value to intr-mbox-0 clears PCI INTA# and
4540          * chip-internal interrupt pending events.
4541          * Writing non-zero to intr-mbox-0 additional tells the
4542          * NIC to stop sending us irqs, engaging "in-intr-handler"
4543          * event coalescing.
4544          */
4545         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4546         if (likely(!tg3_irq_sync(tp)))
4547                 netif_rx_schedule(&tp->napi);
4548
4549         return IRQ_RETVAL(1);
4550 }
4551
4552 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4553 {
4554         struct net_device *dev = dev_id;
4555         struct tg3 *tp = netdev_priv(dev);
4556         struct tg3_hw_status *sblk = tp->hw_status;
4557         unsigned int handled = 1;
4558
4559         /* In INTx mode, it is possible for the interrupt to arrive at
4560          * the CPU before the status block posted prior to the interrupt.
4561          * Reading the PCI State register will confirm whether the
4562          * interrupt is ours and will flush the status block.
4563          */
4564         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4565                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4566                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4567                         handled = 0;
4568                         goto out;
4569                 }
4570         }
4571
4572         /*
4573          * Writing any value to intr-mbox-0 clears PCI INTA# and
4574          * chip-internal interrupt pending events.
4575          * Writing non-zero to intr-mbox-0 additional tells the
4576          * NIC to stop sending us irqs, engaging "in-intr-handler"
4577          * event coalescing.
4578          *
4579          * Flush the mailbox to de-assert the IRQ immediately to prevent
4580          * spurious interrupts.  The flush impacts performance but
4581          * excessive spurious interrupts can be worse in some cases.
4582          */
4583         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4584         if (tg3_irq_sync(tp))
4585                 goto out;
4586         sblk->status &= ~SD_STATUS_UPDATED;
4587         if (likely(tg3_has_work(tp))) {
4588                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4589                 netif_rx_schedule(&tp->napi);
4590         } else {
4591                 /* No work, shared interrupt perhaps?  re-enable
4592                  * interrupts, and flush that PCI write
4593                  */
4594                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4595                                0x00000000);
4596         }
4597 out:
4598         return IRQ_RETVAL(handled);
4599 }
4600
4601 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4602 {
4603         struct net_device *dev = dev_id;
4604         struct tg3 *tp = netdev_priv(dev);
4605         struct tg3_hw_status *sblk = tp->hw_status;
4606         unsigned int handled = 1;
4607
4608         /* In INTx mode, it is possible for the interrupt to arrive at
4609          * the CPU before the status block posted prior to the interrupt.
4610          * Reading the PCI State register will confirm whether the
4611          * interrupt is ours and will flush the status block.
4612          */
4613         if (unlikely(sblk->status_tag == tp->last_tag)) {
4614                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4615                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4616                         handled = 0;
4617                         goto out;
4618                 }
4619         }
4620
4621         /*
4622          * writing any value to intr-mbox-0 clears PCI INTA# and
4623          * chip-internal interrupt pending events.
4624          * writing non-zero to intr-mbox-0 additional tells the
4625          * NIC to stop sending us irqs, engaging "in-intr-handler"
4626          * event coalescing.
4627          *
4628          * Flush the mailbox to de-assert the IRQ immediately to prevent
4629          * spurious interrupts.  The flush impacts performance but
4630          * excessive spurious interrupts can be worse in some cases.
4631          */
4632         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4633         if (tg3_irq_sync(tp))
4634                 goto out;
4635         if (netif_rx_schedule_prep(&tp->napi)) {
4636                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4637                 /* Update last_tag to mark that this status has been
4638                  * seen. Because interrupt may be shared, we may be
4639                  * racing with tg3_poll(), so only update last_tag
4640                  * if tg3_poll() is not scheduled.
4641                  */
4642                 tp->last_tag = sblk->status_tag;
4643                 __netif_rx_schedule(&tp->napi);
4644         }
4645 out:
4646         return IRQ_RETVAL(handled);
4647 }
4648
4649 /* ISR for interrupt test */
4650 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4651 {
4652         struct net_device *dev = dev_id;
4653         struct tg3 *tp = netdev_priv(dev);
4654         struct tg3_hw_status *sblk = tp->hw_status;
4655
4656         if ((sblk->status & SD_STATUS_UPDATED) ||
4657             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4658                 tg3_disable_ints(tp);
4659                 return IRQ_RETVAL(1);
4660         }
4661         return IRQ_RETVAL(0);
4662 }
4663
4664 static int tg3_init_hw(struct tg3 *, int);
4665 static int tg3_halt(struct tg3 *, int, int);
4666
4667 /* Restart hardware after configuration changes, self-test, etc.
4668  * Invoked with tp->lock held.
4669  */
4670 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4671         __releases(tp->lock)
4672         __acquires(tp->lock)
4673 {
4674         int err;
4675
4676         err = tg3_init_hw(tp, reset_phy);
4677         if (err) {
4678                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4679                        "aborting.\n", tp->dev->name);
4680                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4681                 tg3_full_unlock(tp);
4682                 del_timer_sync(&tp->timer);
4683                 tp->irq_sync = 0;
4684                 napi_enable(&tp->napi);
4685                 dev_close(tp->dev);
4686                 tg3_full_lock(tp, 0);
4687         }
4688         return err;
4689 }
4690
4691 #ifdef CONFIG_NET_POLL_CONTROLLER
4692 static void tg3_poll_controller(struct net_device *dev)
4693 {
4694         struct tg3 *tp = netdev_priv(dev);
4695
4696         tg3_interrupt(tp->pdev->irq, dev);
4697 }
4698 #endif
4699
4700 static void tg3_reset_task(struct work_struct *work)
4701 {
4702         struct tg3 *tp = container_of(work, struct tg3, reset_task);
4703         int err;
4704         unsigned int restart_timer;
4705
4706         tg3_full_lock(tp, 0);
4707
4708         if (!netif_running(tp->dev)) {
4709                 tg3_full_unlock(tp);
4710                 return;
4711         }
4712
4713         tg3_full_unlock(tp);
4714
4715         tg3_phy_stop(tp);
4716
4717         tg3_netif_stop(tp);
4718
4719         tg3_full_lock(tp, 1);
4720
4721         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4722         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4723
4724         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4725                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4726                 tp->write32_rx_mbox = tg3_write_flush_reg32;
4727                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4728                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4729         }
4730
4731         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
4732         err = tg3_init_hw(tp, 1);
4733         if (err)
4734                 goto out;
4735
4736         tg3_netif_start(tp);
4737
4738         if (restart_timer)
4739                 mod_timer(&tp->timer, jiffies + 1);
4740
4741 out:
4742         tg3_full_unlock(tp);
4743
4744         if (!err)
4745                 tg3_phy_start(tp);
4746 }
4747
4748 static void tg3_dump_short_state(struct tg3 *tp)
4749 {
4750         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
4751                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
4752         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
4753                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
4754 }
4755
4756 static void tg3_tx_timeout(struct net_device *dev)
4757 {
4758         struct tg3 *tp = netdev_priv(dev);
4759
4760         if (netif_msg_tx_err(tp)) {
4761                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
4762                        dev->name);
4763                 tg3_dump_short_state(tp);
4764         }
4765
4766         schedule_work(&tp->reset_task);
4767 }
4768
4769 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
4770 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
4771 {
4772         u32 base = (u32) mapping & 0xffffffff;
4773
4774         return ((base > 0xffffdcc0) &&
4775                 (base + len + 8 < base));
4776 }
4777
4778 /* Test for DMA addresses > 40-bit */
4779 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
4780                                           int len)
4781 {
4782 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
4783         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
4784                 return (((u64) mapping + len) > DMA_40BIT_MASK);
4785         return 0;
4786 #else
4787         return 0;
4788 #endif
4789 }
4790
4791 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
4792
4793 /* Workaround 4GB and 40-bit hardware DMA bugs. */
4794 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
4795                                        u32 last_plus_one, u32 *start,
4796                                        u32 base_flags, u32 mss)
4797 {
4798         struct sk_buff *new_skb;
4799         dma_addr_t new_addr = 0;
4800         u32 entry = *start;
4801         int i, ret = 0;
4802
4803         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
4804                 new_skb = skb_copy(skb, GFP_ATOMIC);
4805         else {
4806                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
4807
4808                 new_skb = skb_copy_expand(skb,
4809                                           skb_headroom(skb) + more_headroom,
4810                                           skb_tailroom(skb), GFP_ATOMIC);
4811         }
4812
4813         if (!new_skb) {
4814                 ret = -1;
4815         } else {
4816                 /* New SKB is guaranteed to be linear. */
4817                 entry = *start;
4818                 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
4819                 new_addr = skb_shinfo(new_skb)->dma_maps[0];
4820
4821                 /* Make sure new skb does not cross any 4G boundaries.
4822                  * Drop the packet if it does.
4823                  */
4824                 if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) {
4825                         if (!ret)
4826                                 skb_dma_unmap(&tp->pdev->dev, new_skb,
4827                                               DMA_TO_DEVICE);
4828                         ret = -1;
4829                         dev_kfree_skb(new_skb);
4830                         new_skb = NULL;
4831                 } else {
4832                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
4833                                     base_flags, 1 | (mss << 1));
4834                         *start = NEXT_TX(entry);
4835                 }
4836         }
4837
4838         /* Now clean up the sw ring entries. */
4839         i = 0;
4840         while (entry != last_plus_one) {
4841                 if (i == 0) {
4842                         tp->tx_buffers[entry].skb = new_skb;
4843                 } else {
4844                         tp->tx_buffers[entry].skb = NULL;
4845                 }
4846                 entry = NEXT_TX(entry);
4847                 i++;
4848         }
4849
4850         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
4851         dev_kfree_skb(skb);
4852
4853         return ret;
4854 }
4855
4856 static void tg3_set_txd(struct tg3 *tp, int entry,
4857                         dma_addr_t mapping, int len, u32 flags,
4858                         u32 mss_and_is_end)
4859 {
4860         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
4861         int is_end = (mss_and_is_end & 0x1);
4862         u32 mss = (mss_and_is_end >> 1);
4863         u32 vlan_tag = 0;
4864
4865         if (is_end)
4866                 flags |= TXD_FLAG_END;
4867         if (flags & TXD_FLAG_VLAN) {
4868                 vlan_tag = flags >> 16;
4869                 flags &= 0xffff;
4870         }
4871         vlan_tag |= (mss << TXD_MSS_SHIFT);
4872
4873         txd->addr_hi = ((u64) mapping >> 32);
4874         txd->addr_lo = ((u64) mapping & 0xffffffff);
4875         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
4876         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
4877 }
4878
4879 /* hard_start_xmit for devices that don't have any bugs and
4880  * support TG3_FLG2_HW_TSO_2 only.
4881  */
4882 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
4883 {
4884         struct tg3 *tp = netdev_priv(dev);
4885         u32 len, entry, base_flags, mss;
4886         struct skb_shared_info *sp;
4887         dma_addr_t mapping;
4888
4889         len = skb_headlen(skb);
4890
4891         /* We are running in BH disabled context with netif_tx_lock
4892          * and TX reclaim runs via tp->napi.poll inside of a software
4893          * interrupt.  Furthermore, IRQ processing runs lockless so we have
4894          * no IRQ context deadlocks to worry about either.  Rejoice!
4895          */
4896         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4897                 if (!netif_queue_stopped(dev)) {
4898                         netif_stop_queue(dev);
4899
4900                         /* This is a hard error, log it. */
4901                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4902                                "queue awake!\n", dev->name);
4903                 }
4904                 return NETDEV_TX_BUSY;
4905         }
4906
4907         entry = tp->tx_prod;
4908         base_flags = 0;
4909         mss = 0;
4910         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4911                 int tcp_opt_len, ip_tcp_len;
4912
4913                 if (skb_header_cloned(skb) &&
4914                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4915                         dev_kfree_skb(skb);
4916                         goto out_unlock;
4917                 }
4918
4919                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
4920                         mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
4921                 else {
4922                         struct iphdr *iph = ip_hdr(skb);
4923
4924                         tcp_opt_len = tcp_optlen(skb);
4925                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4926
4927                         iph->check = 0;
4928                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
4929                         mss |= (ip_tcp_len + tcp_opt_len) << 9;
4930                 }
4931
4932                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4933                                TXD_FLAG_CPU_POST_DMA);
4934
4935                 tcp_hdr(skb)->check = 0;
4936
4937         }
4938         else if (skb->ip_summed == CHECKSUM_PARTIAL)
4939                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4940 #if TG3_VLAN_TAG_USED
4941         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4942                 base_flags |= (TXD_FLAG_VLAN |
4943                                (vlan_tx_tag_get(skb) << 16));
4944 #endif
4945
4946         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
4947                 dev_kfree_skb(skb);
4948                 goto out_unlock;
4949         }
4950
4951         sp = skb_shinfo(skb);
4952
4953         mapping = sp->dma_maps[0];
4954
4955         tp->tx_buffers[entry].skb = skb;
4956
4957         tg3_set_txd(tp, entry, mapping, len, base_flags,
4958                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4959
4960         entry = NEXT_TX(entry);
4961
4962         /* Now loop through additional data fragments, and queue them. */
4963         if (skb_shinfo(skb)->nr_frags > 0) {
4964                 unsigned int i, last;
4965
4966                 last = skb_shinfo(skb)->nr_frags - 1;
4967                 for (i = 0; i <= last; i++) {
4968                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4969
4970                         len = frag->size;
4971                         mapping = sp->dma_maps[i + 1];
4972                         tp->tx_buffers[entry].skb = NULL;
4973
4974                         tg3_set_txd(tp, entry, mapping, len,
4975                                     base_flags, (i == last) | (mss << 1));
4976
4977                         entry = NEXT_TX(entry);
4978                 }
4979         }
4980
4981         /* Packets are ready, update Tx producer idx local and on card. */
4982         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4983
4984         tp->tx_prod = entry;
4985         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4986                 netif_stop_queue(dev);
4987                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4988                         netif_wake_queue(tp->dev);
4989         }
4990
4991 out_unlock:
4992         mmiowb();
4993
4994         dev->trans_start = jiffies;
4995
4996         return NETDEV_TX_OK;
4997 }
4998
4999 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
5000
5001 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5002  * TSO header is greater than 80 bytes.
5003  */
5004 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5005 {
5006         struct sk_buff *segs, *nskb;
5007
5008         /* Estimate the number of fragments in the worst case */
5009         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
5010                 netif_stop_queue(tp->dev);
5011                 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
5012                         return NETDEV_TX_BUSY;
5013
5014                 netif_wake_queue(tp->dev);
5015         }
5016
5017         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5018         if (IS_ERR(segs))
5019                 goto tg3_tso_bug_end;
5020
5021         do {
5022                 nskb = segs;
5023                 segs = segs->next;
5024                 nskb->next = NULL;
5025                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5026         } while (segs);
5027
5028 tg3_tso_bug_end:
5029         dev_kfree_skb(skb);
5030
5031         return NETDEV_TX_OK;
5032 }
5033
5034 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5035  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5036  */
5037 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
5038 {
5039         struct tg3 *tp = netdev_priv(dev);
5040         u32 len, entry, base_flags, mss;
5041         struct skb_shared_info *sp;
5042         int would_hit_hwbug;
5043         dma_addr_t mapping;
5044
5045         len = skb_headlen(skb);
5046
5047         /* We are running in BH disabled context with netif_tx_lock
5048          * and TX reclaim runs via tp->napi.poll inside of a software
5049          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5050          * no IRQ context deadlocks to worry about either.  Rejoice!
5051          */
5052         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5053                 if (!netif_queue_stopped(dev)) {
5054                         netif_stop_queue(dev);
5055
5056                         /* This is a hard error, log it. */
5057                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5058                                "queue awake!\n", dev->name);
5059                 }
5060                 return NETDEV_TX_BUSY;
5061         }
5062
5063         entry = tp->tx_prod;
5064         base_flags = 0;
5065         if (skb->ip_summed == CHECKSUM_PARTIAL)
5066                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5067         mss = 0;
5068         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5069                 struct iphdr *iph;
5070                 int tcp_opt_len, ip_tcp_len, hdr_len;
5071
5072                 if (skb_header_cloned(skb) &&
5073                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5074                         dev_kfree_skb(skb);
5075                         goto out_unlock;
5076                 }
5077
5078                 tcp_opt_len = tcp_optlen(skb);
5079                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5080
5081                 hdr_len = ip_tcp_len + tcp_opt_len;
5082                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5083                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5084                         return (tg3_tso_bug(tp, skb));
5085
5086                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5087                                TXD_FLAG_CPU_POST_DMA);
5088
5089                 iph = ip_hdr(skb);
5090                 iph->check = 0;
5091                 iph->tot_len = htons(mss + hdr_len);
5092                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5093                         tcp_hdr(skb)->check = 0;
5094                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5095                 } else
5096                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5097                                                                  iph->daddr, 0,
5098                                                                  IPPROTO_TCP,
5099                                                                  0);
5100
5101                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
5102                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
5103                         if (tcp_opt_len || iph->ihl > 5) {
5104                                 int tsflags;
5105
5106                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5107                                 mss |= (tsflags << 11);
5108                         }
5109                 } else {
5110                         if (tcp_opt_len || iph->ihl > 5) {
5111                                 int tsflags;
5112
5113                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5114                                 base_flags |= tsflags << 12;
5115                         }
5116                 }
5117         }
5118 #if TG3_VLAN_TAG_USED
5119         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5120                 base_flags |= (TXD_FLAG_VLAN |
5121                                (vlan_tx_tag_get(skb) << 16));
5122 #endif
5123
5124         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5125                 dev_kfree_skb(skb);
5126                 goto out_unlock;
5127         }
5128
5129         sp = skb_shinfo(skb);
5130
5131         mapping = sp->dma_maps[0];
5132
5133         tp->tx_buffers[entry].skb = skb;
5134
5135         would_hit_hwbug = 0;
5136
5137         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5138                 would_hit_hwbug = 1;
5139         else if (tg3_4g_overflow_test(mapping, len))
5140                 would_hit_hwbug = 1;
5141
5142         tg3_set_txd(tp, entry, mapping, len, base_flags,
5143                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5144
5145         entry = NEXT_TX(entry);
5146
5147         /* Now loop through additional data fragments, and queue them. */
5148         if (skb_shinfo(skb)->nr_frags > 0) {
5149                 unsigned int i, last;
5150
5151                 last = skb_shinfo(skb)->nr_frags - 1;
5152                 for (i = 0; i <= last; i++) {
5153                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5154
5155                         len = frag->size;
5156                         mapping = sp->dma_maps[i + 1];
5157
5158                         tp->tx_buffers[entry].skb = NULL;
5159
5160                         if (tg3_4g_overflow_test(mapping, len))
5161                                 would_hit_hwbug = 1;
5162
5163                         if (tg3_40bit_overflow_test(tp, mapping, len))
5164                                 would_hit_hwbug = 1;
5165
5166                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5167                                 tg3_set_txd(tp, entry, mapping, len,
5168                                             base_flags, (i == last)|(mss << 1));
5169                         else
5170                                 tg3_set_txd(tp, entry, mapping, len,
5171                                             base_flags, (i == last));
5172
5173                         entry = NEXT_TX(entry);
5174                 }
5175         }
5176
5177         if (would_hit_hwbug) {
5178                 u32 last_plus_one = entry;
5179                 u32 start;
5180
5181                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5182                 start &= (TG3_TX_RING_SIZE - 1);
5183
5184                 /* If the workaround fails due to memory/mapping
5185                  * failure, silently drop this packet.
5186                  */
5187                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
5188                                                 &start, base_flags, mss))
5189                         goto out_unlock;
5190
5191                 entry = start;
5192         }
5193
5194         /* Packets are ready, update Tx producer idx local and on card. */
5195         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5196
5197         tp->tx_prod = entry;
5198         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5199                 netif_stop_queue(dev);
5200                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5201                         netif_wake_queue(tp->dev);
5202         }
5203
5204 out_unlock:
5205         mmiowb();
5206
5207         dev->trans_start = jiffies;
5208
5209         return NETDEV_TX_OK;
5210 }
5211
5212 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5213                                int new_mtu)
5214 {
5215         dev->mtu = new_mtu;
5216
5217         if (new_mtu > ETH_DATA_LEN) {
5218                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5219                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5220                         ethtool_op_set_tso(dev, 0);
5221                 }
5222                 else
5223                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5224         } else {
5225                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5226                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5227                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5228         }
5229 }
5230
5231 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5232 {
5233         struct tg3 *tp = netdev_priv(dev);
5234         int err;
5235
5236         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5237                 return -EINVAL;
5238
5239         if (!netif_running(dev)) {
5240                 /* We'll just catch it later when the
5241                  * device is up'd.
5242                  */
5243                 tg3_set_mtu(dev, tp, new_mtu);
5244                 return 0;
5245         }
5246
5247         tg3_phy_stop(tp);
5248
5249         tg3_netif_stop(tp);
5250
5251         tg3_full_lock(tp, 1);
5252
5253         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5254
5255         tg3_set_mtu(dev, tp, new_mtu);
5256
5257         err = tg3_restart_hw(tp, 0);
5258
5259         if (!err)
5260                 tg3_netif_start(tp);
5261
5262         tg3_full_unlock(tp);
5263
5264         if (!err)
5265                 tg3_phy_start(tp);
5266
5267         return err;
5268 }
5269
5270 /* Free up pending packets in all rx/tx rings.
5271  *
5272  * The chip has been shut down and the driver detached from
5273  * the networking, so no interrupts or new tx packets will
5274  * end up in the driver.  tp->{tx,}lock is not held and we are not
5275  * in an interrupt context and thus may sleep.
5276  */
5277 static void tg3_free_rings(struct tg3 *tp)
5278 {
5279         struct ring_info *rxp;
5280         int i;
5281
5282         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5283                 rxp = &tp->rx_std_buffers[i];
5284
5285                 if (rxp->skb == NULL)
5286                         continue;
5287                 pci_unmap_single(tp->pdev,
5288                                  pci_unmap_addr(rxp, mapping),
5289                                  tp->rx_pkt_buf_sz - tp->rx_offset,
5290                                  PCI_DMA_FROMDEVICE);
5291                 dev_kfree_skb_any(rxp->skb);
5292                 rxp->skb = NULL;
5293         }
5294
5295         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5296                 rxp = &tp->rx_jumbo_buffers[i];
5297
5298                 if (rxp->skb == NULL)
5299                         continue;
5300                 pci_unmap_single(tp->pdev,
5301                                  pci_unmap_addr(rxp, mapping),
5302                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
5303                                  PCI_DMA_FROMDEVICE);
5304                 dev_kfree_skb_any(rxp->skb);
5305                 rxp->skb = NULL;
5306         }
5307
5308         for (i = 0; i < TG3_TX_RING_SIZE; ) {
5309                 struct tx_ring_info *txp;
5310                 struct sk_buff *skb;
5311
5312                 txp = &tp->tx_buffers[i];
5313                 skb = txp->skb;
5314
5315                 if (skb == NULL) {
5316                         i++;
5317                         continue;
5318                 }
5319
5320                 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5321
5322                 txp->skb = NULL;
5323
5324                 i += skb_shinfo(skb)->nr_frags + 1;
5325
5326                 dev_kfree_skb_any(skb);
5327         }
5328 }
5329
5330 /* Initialize tx/rx rings for packet processing.
5331  *
5332  * The chip has been shut down and the driver detached from
5333  * the networking, so no interrupts or new tx packets will
5334  * end up in the driver.  tp->{tx,}lock are held and thus
5335  * we may not sleep.
5336  */
5337 static int tg3_init_rings(struct tg3 *tp)
5338 {
5339         u32 i;
5340
5341         /* Free up all the SKBs. */
5342         tg3_free_rings(tp);
5343
5344         /* Zero out all descriptors. */
5345         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
5346         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
5347         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5348         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
5349
5350         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
5351         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5352             (tp->dev->mtu > ETH_DATA_LEN))
5353                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
5354
5355         /* Initialize invariants of the rings, we only set this
5356          * stuff once.  This works because the card does not
5357          * write into the rx buffer posting rings.
5358          */
5359         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5360                 struct tg3_rx_buffer_desc *rxd;
5361
5362                 rxd = &tp->rx_std[i];
5363                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
5364                         << RXD_LEN_SHIFT;
5365                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5366                 rxd->opaque = (RXD_OPAQUE_RING_STD |
5367                                (i << RXD_OPAQUE_INDEX_SHIFT));
5368         }
5369
5370         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5371                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5372                         struct tg3_rx_buffer_desc *rxd;
5373
5374                         rxd = &tp->rx_jumbo[i];
5375                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
5376                                 << RXD_LEN_SHIFT;
5377                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5378                                 RXD_FLAG_JUMBO;
5379                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5380                                (i << RXD_OPAQUE_INDEX_SHIFT));
5381                 }
5382         }
5383
5384         /* Now allocate fresh SKBs for each rx ring. */
5385         for (i = 0; i < tp->rx_pending; i++) {
5386                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5387                         printk(KERN_WARNING PFX
5388                                "%s: Using a smaller RX standard ring, "
5389                                "only %d out of %d buffers were allocated "
5390                                "successfully.\n",
5391                                tp->dev->name, i, tp->rx_pending);
5392                         if (i == 0)
5393                                 return -ENOMEM;
5394                         tp->rx_pending = i;
5395                         break;
5396                 }
5397         }
5398
5399         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5400                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5401                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
5402                                              -1, i) < 0) {
5403                                 printk(KERN_WARNING PFX
5404                                        "%s: Using a smaller RX jumbo ring, "
5405                                        "only %d out of %d buffers were "
5406                                        "allocated successfully.\n",
5407                                        tp->dev->name, i, tp->rx_jumbo_pending);
5408                                 if (i == 0) {
5409                                         tg3_free_rings(tp);
5410                                         return -ENOMEM;
5411                                 }
5412                                 tp->rx_jumbo_pending = i;
5413                                 break;
5414                         }
5415                 }
5416         }
5417         return 0;
5418 }
5419
5420 /*
5421  * Must not be invoked with interrupt sources disabled and
5422  * the hardware shutdown down.
5423  */
5424 static void tg3_free_consistent(struct tg3 *tp)
5425 {
5426         kfree(tp->rx_std_buffers);
5427         tp->rx_std_buffers = NULL;
5428         if (tp->rx_std) {
5429                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5430                                     tp->rx_std, tp->rx_std_mapping);
5431                 tp->rx_std = NULL;
5432         }
5433         if (tp->rx_jumbo) {
5434                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5435                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
5436                 tp->rx_jumbo = NULL;
5437         }
5438         if (tp->rx_rcb) {
5439                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5440                                     tp->rx_rcb, tp->rx_rcb_mapping);
5441                 tp->rx_rcb = NULL;
5442         }
5443         if (tp->tx_ring) {
5444                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5445                         tp->tx_ring, tp->tx_desc_mapping);
5446                 tp->tx_ring = NULL;
5447         }
5448         if (tp->hw_status) {
5449                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5450                                     tp->hw_status, tp->status_mapping);
5451                 tp->hw_status = NULL;
5452         }
5453         if (tp->hw_stats) {
5454                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5455                                     tp->hw_stats, tp->stats_mapping);
5456                 tp->hw_stats = NULL;
5457         }
5458 }
5459
5460 /*
5461  * Must not be invoked with interrupt sources disabled and
5462  * the hardware shutdown down.  Can sleep.
5463  */
5464 static int tg3_alloc_consistent(struct tg3 *tp)
5465 {
5466         tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
5467                                       (TG3_RX_RING_SIZE +
5468                                        TG3_RX_JUMBO_RING_SIZE)) +
5469                                      (sizeof(struct tx_ring_info) *
5470                                       TG3_TX_RING_SIZE),
5471                                      GFP_KERNEL);
5472         if (!tp->rx_std_buffers)
5473                 return -ENOMEM;
5474
5475         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
5476         tp->tx_buffers = (struct tx_ring_info *)
5477                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
5478
5479         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5480                                           &tp->rx_std_mapping);
5481         if (!tp->rx_std)
5482                 goto err_out;
5483
5484         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5485                                             &tp->rx_jumbo_mapping);
5486
5487         if (!tp->rx_jumbo)
5488                 goto err_out;
5489
5490         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5491                                           &tp->rx_rcb_mapping);
5492         if (!tp->rx_rcb)
5493                 goto err_out;
5494
5495         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5496                                            &tp->tx_desc_mapping);
5497         if (!tp->tx_ring)
5498                 goto err_out;
5499
5500         tp->hw_status = pci_alloc_consistent(tp->pdev,
5501                                              TG3_HW_STATUS_SIZE,
5502                                              &tp->status_mapping);
5503         if (!tp->hw_status)
5504                 goto err_out;
5505
5506         tp->hw_stats = pci_alloc_consistent(tp->pdev,
5507                                             sizeof(struct tg3_hw_stats),
5508                                             &tp->stats_mapping);
5509         if (!tp->hw_stats)
5510                 goto err_out;
5511
5512         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5513         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5514
5515         return 0;
5516
5517 err_out:
5518         tg3_free_consistent(tp);
5519         return -ENOMEM;
5520 }
5521
5522 #define MAX_WAIT_CNT 1000
5523
5524 /* To stop a block, clear the enable bit and poll till it
5525  * clears.  tp->lock is held.
5526  */
5527 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
5528 {
5529         unsigned int i;
5530         u32 val;
5531
5532         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5533                 switch (ofs) {
5534                 case RCVLSC_MODE:
5535                 case DMAC_MODE:
5536                 case MBFREE_MODE:
5537                 case BUFMGR_MODE:
5538                 case MEMARB_MODE:
5539                         /* We can't enable/disable these bits of the
5540                          * 5705/5750, just say success.
5541                          */
5542                         return 0;
5543
5544                 default:
5545                         break;
5546                 }
5547         }
5548
5549         val = tr32(ofs);
5550         val &= ~enable_bit;
5551         tw32_f(ofs, val);
5552
5553         for (i = 0; i < MAX_WAIT_CNT; i++) {
5554                 udelay(100);
5555                 val = tr32(ofs);
5556                 if ((val & enable_bit) == 0)
5557                         break;
5558         }
5559
5560         if (i == MAX_WAIT_CNT && !silent) {
5561                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5562                        "ofs=%lx enable_bit=%x\n",
5563                        ofs, enable_bit);
5564                 return -ENODEV;
5565         }
5566
5567         return 0;
5568 }
5569
5570 /* tp->lock is held. */
5571 static int tg3_abort_hw(struct tg3 *tp, int silent)
5572 {
5573         int i, err;
5574
5575         tg3_disable_ints(tp);
5576
5577         tp->rx_mode &= ~RX_MODE_ENABLE;
5578         tw32_f(MAC_RX_MODE, tp->rx_mode);
5579         udelay(10);
5580
5581         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5582         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5583         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5584         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5585         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5586         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5587
5588         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5589         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5590         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5591         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5592         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5593         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5594         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
5595
5596         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5597         tw32_f(MAC_MODE, tp->mac_mode);
5598         udelay(40);
5599
5600         tp->tx_mode &= ~TX_MODE_ENABLE;
5601         tw32_f(MAC_TX_MODE, tp->tx_mode);
5602
5603         for (i = 0; i < MAX_WAIT_CNT; i++) {
5604                 udelay(100);
5605                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5606                         break;
5607         }
5608         if (i >= MAX_WAIT_CNT) {
5609                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5610                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5611                        tp->dev->name, tr32(MAC_TX_MODE));
5612                 err |= -ENODEV;
5613         }
5614
5615         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
5616         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5617         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
5618
5619         tw32(FTQ_RESET, 0xffffffff);
5620         tw32(FTQ_RESET, 0x00000000);
5621
5622         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5623         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
5624
5625         if (tp->hw_status)
5626                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5627         if (tp->hw_stats)
5628                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5629
5630         return err;
5631 }
5632
5633 /* tp->lock is held. */
5634 static int tg3_nvram_lock(struct tg3 *tp)
5635 {
5636         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
5637                 int i;
5638
5639                 if (tp->nvram_lock_cnt == 0) {
5640                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
5641                         for (i = 0; i < 8000; i++) {
5642                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
5643                                         break;
5644                                 udelay(20);
5645                         }
5646                         if (i == 8000) {
5647                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
5648                                 return -ENODEV;
5649                         }
5650                 }
5651                 tp->nvram_lock_cnt++;
5652         }
5653         return 0;
5654 }
5655
5656 /* tp->lock is held. */
5657 static void tg3_nvram_unlock(struct tg3 *tp)
5658 {
5659         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
5660                 if (tp->nvram_lock_cnt > 0)
5661                         tp->nvram_lock_cnt--;
5662                 if (tp->nvram_lock_cnt == 0)
5663                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
5664         }
5665 }
5666
5667 /* tp->lock is held. */
5668 static void tg3_enable_nvram_access(struct tg3 *tp)
5669 {
5670         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5671             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5672                 u32 nvaccess = tr32(NVRAM_ACCESS);
5673
5674                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
5675         }
5676 }
5677
5678 /* tp->lock is held. */
5679 static void tg3_disable_nvram_access(struct tg3 *tp)
5680 {
5681         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5682             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5683                 u32 nvaccess = tr32(NVRAM_ACCESS);
5684
5685                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
5686         }
5687 }
5688
5689 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5690 {
5691         int i;
5692         u32 apedata;
5693
5694         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5695         if (apedata != APE_SEG_SIG_MAGIC)
5696                 return;
5697
5698         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
5699         if (!(apedata & APE_FW_STATUS_READY))
5700                 return;
5701
5702         /* Wait for up to 1 millisecond for APE to service previous event. */
5703         for (i = 0; i < 10; i++) {
5704                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5705                         return;
5706
5707                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5708
5709                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5710                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5711                                         event | APE_EVENT_STATUS_EVENT_PENDING);
5712
5713                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5714
5715                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5716                         break;
5717
5718                 udelay(100);
5719         }
5720
5721         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5722                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5723 }
5724
5725 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5726 {
5727         u32 event;
5728         u32 apedata;
5729
5730         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5731                 return;
5732
5733         switch (kind) {
5734                 case RESET_KIND_INIT:
5735                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5736                                         APE_HOST_SEG_SIG_MAGIC);
5737                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5738                                         APE_HOST_SEG_LEN_MAGIC);
5739                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5740                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5741                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
5742                                         APE_HOST_DRIVER_ID_MAGIC);
5743                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
5744                                         APE_HOST_BEHAV_NO_PHYLOCK);
5745
5746                         event = APE_EVENT_STATUS_STATE_START;
5747                         break;
5748                 case RESET_KIND_SHUTDOWN:
5749                         /* With the interface we are currently using,
5750                          * APE does not track driver state.  Wiping
5751                          * out the HOST SEGMENT SIGNATURE forces
5752                          * the APE to assume OS absent status.
5753                          */
5754                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
5755
5756                         event = APE_EVENT_STATUS_STATE_UNLOAD;
5757                         break;
5758                 case RESET_KIND_SUSPEND:
5759                         event = APE_EVENT_STATUS_STATE_SUSPEND;
5760                         break;
5761                 default:
5762                         return;
5763