tg3: Fix 5717 and 57765 memory selftests
[linux-2.6.git] / drivers / net / tg3.c
1 /*
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  * Copyright (C) 2005-2009 Broadcom Corporation.
8  *
9  * Firmware is:
10  *      Derived from proprietary unpublished source code,
11  *      Copyright (C) 2000-2003 Broadcom Corporation.
12  *
13  *      Permission is hereby granted for the distribution of this firmware
14  *      data in hexadecimal or equivalent format, provided this copyright
15  *      notice is accompanying it.
16  */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
26 #include <linux/in.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/phy.h>
36 #include <linux/brcmphy.h>
37 #include <linux/if_vlan.h>
38 #include <linux/ip.h>
39 #include <linux/tcp.h>
40 #include <linux/workqueue.h>
41 #include <linux/prefetch.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/firmware.h>
44
45 #include <net/checksum.h>
46 #include <net/ip.h>
47
48 #include <asm/system.h>
49 #include <asm/io.h>
50 #include <asm/byteorder.h>
51 #include <asm/uaccess.h>
52
53 #ifdef CONFIG_SPARC
54 #include <asm/idprom.h>
55 #include <asm/prom.h>
56 #endif
57
58 #define BAR_0   0
59 #define BAR_2   2
60
61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62 #define TG3_VLAN_TAG_USED 1
63 #else
64 #define TG3_VLAN_TAG_USED 0
65 #endif
66
67 #include "tg3.h"
68
69 #define DRV_MODULE_NAME         "tg3"
70 #define PFX DRV_MODULE_NAME     ": "
71 #define DRV_MODULE_VERSION      "3.105"
72 #define DRV_MODULE_RELDATE      "December 2, 2009"
73
74 #define TG3_DEF_MAC_MODE        0
75 #define TG3_DEF_RX_MODE         0
76 #define TG3_DEF_TX_MODE         0
77 #define TG3_DEF_MSG_ENABLE        \
78         (NETIF_MSG_DRV          | \
79          NETIF_MSG_PROBE        | \
80          NETIF_MSG_LINK         | \
81          NETIF_MSG_TIMER        | \
82          NETIF_MSG_IFDOWN       | \
83          NETIF_MSG_IFUP         | \
84          NETIF_MSG_RX_ERR       | \
85          NETIF_MSG_TX_ERR)
86
87 /* length of time before we decide the hardware is borked,
88  * and dev->tx_timeout() should be called to fix the problem
89  */
90 #define TG3_TX_TIMEOUT                  (5 * HZ)
91
92 /* hardware minimum and maximum for a single frame's data payload */
93 #define TG3_MIN_MTU                     60
94 #define TG3_MAX_MTU(tp) \
95         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
96
97 /* These numbers seem to be hard coded in the NIC firmware somehow.
98  * You can't change the ring sizes, but you can change where you place
99  * them in the NIC onboard memory.
100  */
101 #define TG3_RX_RING_SIZE                512
102 #define TG3_DEF_RX_RING_PENDING         200
103 #define TG3_RX_JUMBO_RING_SIZE          256
104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
105 #define TG3_RSS_INDIR_TBL_SIZE 128
106
107 /* Do not place this n-ring entries value into the tp struct itself,
108  * we really want to expose these constants to GCC so that modulo et
109  * al.  operations are done with shifts and masks instead of with
110  * hw multiply/modulo instructions.  Another solution would be to
111  * replace things like '% foo' with '& (foo - 1)'.
112  */
113 #define TG3_RX_RCB_RING_SIZE(tp)        \
114         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
115           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
116
117 #define TG3_TX_RING_SIZE                512
118 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
119
120 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
121                                  TG3_RX_RING_SIZE)
122 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
123                                  TG3_RX_JUMBO_RING_SIZE)
124 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
125                                  TG3_RX_RCB_RING_SIZE(tp))
126 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
127                                  TG3_TX_RING_SIZE)
128 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
129
130 #define TG3_DMA_BYTE_ENAB               64
131
132 #define TG3_RX_STD_DMA_SZ               1536
133 #define TG3_RX_JMB_DMA_SZ               9046
134
135 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
136
137 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
138 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
139
140 #define TG3_RX_STD_BUFF_RING_SIZE \
141         (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
142
143 #define TG3_RX_JMB_BUFF_RING_SIZE \
144         (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
145
146 /* minimum number of free TX descriptors required to wake up TX process */
147 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
148
149 #define TG3_RAW_IP_ALIGN 2
150
151 /* number of ETHTOOL_GSTATS u64's */
152 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
153
154 #define TG3_NUM_TEST            6
155
156 #define FIRMWARE_TG3            "tigon/tg3.bin"
157 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
158 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
159
160 static char version[] __devinitdata =
161         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
162
163 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
164 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
165 MODULE_LICENSE("GPL");
166 MODULE_VERSION(DRV_MODULE_VERSION);
167 MODULE_FIRMWARE(FIRMWARE_TG3);
168 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
169 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
170
171 #define TG3_RSS_MIN_NUM_MSIX_VECS       2
172
173 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
174 module_param(tg3_debug, int, 0);
175 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
176
177 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
247         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
248         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
249         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
250         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
251         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
252         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
253         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
254         {}
255 };
256
257 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
258
259 static const struct {
260         const char string[ETH_GSTRING_LEN];
261 } ethtool_stats_keys[TG3_NUM_STATS] = {
262         { "rx_octets" },
263         { "rx_fragments" },
264         { "rx_ucast_packets" },
265         { "rx_mcast_packets" },
266         { "rx_bcast_packets" },
267         { "rx_fcs_errors" },
268         { "rx_align_errors" },
269         { "rx_xon_pause_rcvd" },
270         { "rx_xoff_pause_rcvd" },
271         { "rx_mac_ctrl_rcvd" },
272         { "rx_xoff_entered" },
273         { "rx_frame_too_long_errors" },
274         { "rx_jabbers" },
275         { "rx_undersize_packets" },
276         { "rx_in_length_errors" },
277         { "rx_out_length_errors" },
278         { "rx_64_or_less_octet_packets" },
279         { "rx_65_to_127_octet_packets" },
280         { "rx_128_to_255_octet_packets" },
281         { "rx_256_to_511_octet_packets" },
282         { "rx_512_to_1023_octet_packets" },
283         { "rx_1024_to_1522_octet_packets" },
284         { "rx_1523_to_2047_octet_packets" },
285         { "rx_2048_to_4095_octet_packets" },
286         { "rx_4096_to_8191_octet_packets" },
287         { "rx_8192_to_9022_octet_packets" },
288
289         { "tx_octets" },
290         { "tx_collisions" },
291
292         { "tx_xon_sent" },
293         { "tx_xoff_sent" },
294         { "tx_flow_control" },
295         { "tx_mac_errors" },
296         { "tx_single_collisions" },
297         { "tx_mult_collisions" },
298         { "tx_deferred" },
299         { "tx_excessive_collisions" },
300         { "tx_late_collisions" },
301         { "tx_collide_2times" },
302         { "tx_collide_3times" },
303         { "tx_collide_4times" },
304         { "tx_collide_5times" },
305         { "tx_collide_6times" },
306         { "tx_collide_7times" },
307         { "tx_collide_8times" },
308         { "tx_collide_9times" },
309         { "tx_collide_10times" },
310         { "tx_collide_11times" },
311         { "tx_collide_12times" },
312         { "tx_collide_13times" },
313         { "tx_collide_14times" },
314         { "tx_collide_15times" },
315         { "tx_ucast_packets" },
316         { "tx_mcast_packets" },
317         { "tx_bcast_packets" },
318         { "tx_carrier_sense_errors" },
319         { "tx_discards" },
320         { "tx_errors" },
321
322         { "dma_writeq_full" },
323         { "dma_write_prioq_full" },
324         { "rxbds_empty" },
325         { "rx_discards" },
326         { "rx_errors" },
327         { "rx_threshold_hit" },
328
329         { "dma_readq_full" },
330         { "dma_read_prioq_full" },
331         { "tx_comp_queue_full" },
332
333         { "ring_set_send_prod_index" },
334         { "ring_status_update" },
335         { "nic_irqs" },
336         { "nic_avoided_irqs" },
337         { "nic_tx_threshold_hit" }
338 };
339
340 static const struct {
341         const char string[ETH_GSTRING_LEN];
342 } ethtool_test_keys[TG3_NUM_TEST] = {
343         { "nvram test     (online) " },
344         { "link test      (online) " },
345         { "register test  (offline)" },
346         { "memory test    (offline)" },
347         { "loopback test  (offline)" },
348         { "interrupt test (offline)" },
349 };
350
351 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
352 {
353         writel(val, tp->regs + off);
354 }
355
356 static u32 tg3_read32(struct tg3 *tp, u32 off)
357 {
358         return (readl(tp->regs + off));
359 }
360
361 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
362 {
363         writel(val, tp->aperegs + off);
364 }
365
366 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
367 {
368         return (readl(tp->aperegs + off));
369 }
370
371 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
372 {
373         unsigned long flags;
374
375         spin_lock_irqsave(&tp->indirect_lock, flags);
376         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
377         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
378         spin_unlock_irqrestore(&tp->indirect_lock, flags);
379 }
380
381 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
382 {
383         writel(val, tp->regs + off);
384         readl(tp->regs + off);
385 }
386
387 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
388 {
389         unsigned long flags;
390         u32 val;
391
392         spin_lock_irqsave(&tp->indirect_lock, flags);
393         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
394         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
395         spin_unlock_irqrestore(&tp->indirect_lock, flags);
396         return val;
397 }
398
399 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
400 {
401         unsigned long flags;
402
403         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
404                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
405                                        TG3_64BIT_REG_LOW, val);
406                 return;
407         }
408         if (off == TG3_RX_STD_PROD_IDX_REG) {
409                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
410                                        TG3_64BIT_REG_LOW, val);
411                 return;
412         }
413
414         spin_lock_irqsave(&tp->indirect_lock, flags);
415         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
416         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
417         spin_unlock_irqrestore(&tp->indirect_lock, flags);
418
419         /* In indirect mode when disabling interrupts, we also need
420          * to clear the interrupt bit in the GRC local ctrl register.
421          */
422         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
423             (val == 0x1)) {
424                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
425                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
426         }
427 }
428
429 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
430 {
431         unsigned long flags;
432         u32 val;
433
434         spin_lock_irqsave(&tp->indirect_lock, flags);
435         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
436         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
437         spin_unlock_irqrestore(&tp->indirect_lock, flags);
438         return val;
439 }
440
441 /* usec_wait specifies the wait time in usec when writing to certain registers
442  * where it is unsafe to read back the register without some delay.
443  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
444  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
445  */
446 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
447 {
448         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
449             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
450                 /* Non-posted methods */
451                 tp->write32(tp, off, val);
452         else {
453                 /* Posted method */
454                 tg3_write32(tp, off, val);
455                 if (usec_wait)
456                         udelay(usec_wait);
457                 tp->read32(tp, off);
458         }
459         /* Wait again after the read for the posted method to guarantee that
460          * the wait time is met.
461          */
462         if (usec_wait)
463                 udelay(usec_wait);
464 }
465
466 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
467 {
468         tp->write32_mbox(tp, off, val);
469         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
470             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
471                 tp->read32_mbox(tp, off);
472 }
473
474 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
475 {
476         void __iomem *mbox = tp->regs + off;
477         writel(val, mbox);
478         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
479                 writel(val, mbox);
480         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
481                 readl(mbox);
482 }
483
484 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
485 {
486         return (readl(tp->regs + off + GRCMBOX_BASE));
487 }
488
489 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
490 {
491         writel(val, tp->regs + off + GRCMBOX_BASE);
492 }
493
494 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
495 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
496 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
497 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
498 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
499
500 #define tw32(reg,val)           tp->write32(tp, reg, val)
501 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
502 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
503 #define tr32(reg)               tp->read32(tp, reg)
504
505 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
506 {
507         unsigned long flags;
508
509         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
510             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
511                 return;
512
513         spin_lock_irqsave(&tp->indirect_lock, flags);
514         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
515                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
516                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
517
518                 /* Always leave this as zero. */
519                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
520         } else {
521                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
522                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
523
524                 /* Always leave this as zero. */
525                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
526         }
527         spin_unlock_irqrestore(&tp->indirect_lock, flags);
528 }
529
530 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
531 {
532         unsigned long flags;
533
534         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
535             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
536                 *val = 0;
537                 return;
538         }
539
540         spin_lock_irqsave(&tp->indirect_lock, flags);
541         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
542                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
543                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
544
545                 /* Always leave this as zero. */
546                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
547         } else {
548                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
549                 *val = tr32(TG3PCI_MEM_WIN_DATA);
550
551                 /* Always leave this as zero. */
552                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
553         }
554         spin_unlock_irqrestore(&tp->indirect_lock, flags);
555 }
556
557 static void tg3_ape_lock_init(struct tg3 *tp)
558 {
559         int i;
560
561         /* Make sure the driver hasn't any stale locks. */
562         for (i = 0; i < 8; i++)
563                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
564                                 APE_LOCK_GRANT_DRIVER);
565 }
566
567 static int tg3_ape_lock(struct tg3 *tp, int locknum)
568 {
569         int i, off;
570         int ret = 0;
571         u32 status;
572
573         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
574                 return 0;
575
576         switch (locknum) {
577                 case TG3_APE_LOCK_GRC:
578                 case TG3_APE_LOCK_MEM:
579                         break;
580                 default:
581                         return -EINVAL;
582         }
583
584         off = 4 * locknum;
585
586         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
587
588         /* Wait for up to 1 millisecond to acquire lock. */
589         for (i = 0; i < 100; i++) {
590                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
591                 if (status == APE_LOCK_GRANT_DRIVER)
592                         break;
593                 udelay(10);
594         }
595
596         if (status != APE_LOCK_GRANT_DRIVER) {
597                 /* Revoke the lock request. */
598                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
599                                 APE_LOCK_GRANT_DRIVER);
600
601                 ret = -EBUSY;
602         }
603
604         return ret;
605 }
606
607 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
608 {
609         int off;
610
611         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
612                 return;
613
614         switch (locknum) {
615                 case TG3_APE_LOCK_GRC:
616                 case TG3_APE_LOCK_MEM:
617                         break;
618                 default:
619                         return;
620         }
621
622         off = 4 * locknum;
623         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
624 }
625
626 static void tg3_disable_ints(struct tg3 *tp)
627 {
628         int i;
629
630         tw32(TG3PCI_MISC_HOST_CTRL,
631              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
632         for (i = 0; i < tp->irq_max; i++)
633                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
634 }
635
636 static void tg3_enable_ints(struct tg3 *tp)
637 {
638         int i;
639         u32 coal_now = 0;
640
641         tp->irq_sync = 0;
642         wmb();
643
644         tw32(TG3PCI_MISC_HOST_CTRL,
645              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
646
647         for (i = 0; i < tp->irq_cnt; i++) {
648                 struct tg3_napi *tnapi = &tp->napi[i];
649                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
650                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
651                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
652
653                 coal_now |= tnapi->coal_now;
654         }
655
656         /* Force an initial interrupt */
657         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
658             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
659                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
660         else
661                 tw32(HOSTCC_MODE, tp->coalesce_mode |
662                      HOSTCC_MODE_ENABLE | coal_now);
663 }
664
665 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
666 {
667         struct tg3 *tp = tnapi->tp;
668         struct tg3_hw_status *sblk = tnapi->hw_status;
669         unsigned int work_exists = 0;
670
671         /* check for phy events */
672         if (!(tp->tg3_flags &
673               (TG3_FLAG_USE_LINKCHG_REG |
674                TG3_FLAG_POLL_SERDES))) {
675                 if (sblk->status & SD_STATUS_LINK_CHG)
676                         work_exists = 1;
677         }
678         /* check for RX/TX work to do */
679         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
680             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
681                 work_exists = 1;
682
683         return work_exists;
684 }
685
686 /* tg3_int_reenable
687  *  similar to tg3_enable_ints, but it accurately determines whether there
688  *  is new work pending and can return without flushing the PIO write
689  *  which reenables interrupts
690  */
691 static void tg3_int_reenable(struct tg3_napi *tnapi)
692 {
693         struct tg3 *tp = tnapi->tp;
694
695         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
696         mmiowb();
697
698         /* When doing tagged status, this work check is unnecessary.
699          * The last_tag we write above tells the chip which piece of
700          * work we've completed.
701          */
702         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
703             tg3_has_work(tnapi))
704                 tw32(HOSTCC_MODE, tp->coalesce_mode |
705                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
706 }
707
708 static void tg3_napi_disable(struct tg3 *tp)
709 {
710         int i;
711
712         for (i = tp->irq_cnt - 1; i >= 0; i--)
713                 napi_disable(&tp->napi[i].napi);
714 }
715
716 static void tg3_napi_enable(struct tg3 *tp)
717 {
718         int i;
719
720         for (i = 0; i < tp->irq_cnt; i++)
721                 napi_enable(&tp->napi[i].napi);
722 }
723
724 static inline void tg3_netif_stop(struct tg3 *tp)
725 {
726         tp->dev->trans_start = jiffies; /* prevent tx timeout */
727         tg3_napi_disable(tp);
728         netif_tx_disable(tp->dev);
729 }
730
731 static inline void tg3_netif_start(struct tg3 *tp)
732 {
733         /* NOTE: unconditional netif_tx_wake_all_queues is only
734          * appropriate so long as all callers are assured to
735          * have free tx slots (such as after tg3_init_hw)
736          */
737         netif_tx_wake_all_queues(tp->dev);
738
739         tg3_napi_enable(tp);
740         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
741         tg3_enable_ints(tp);
742 }
743
744 static void tg3_switch_clocks(struct tg3 *tp)
745 {
746         u32 clock_ctrl;
747         u32 orig_clock_ctrl;
748
749         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
750             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
751                 return;
752
753         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
754
755         orig_clock_ctrl = clock_ctrl;
756         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
757                        CLOCK_CTRL_CLKRUN_OENABLE |
758                        0x1f);
759         tp->pci_clock_ctrl = clock_ctrl;
760
761         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
762                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
763                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
764                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
765                 }
766         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
767                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
768                             clock_ctrl |
769                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
770                             40);
771                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
772                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
773                             40);
774         }
775         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
776 }
777
778 #define PHY_BUSY_LOOPS  5000
779
780 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
781 {
782         u32 frame_val;
783         unsigned int loops;
784         int ret;
785
786         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
787                 tw32_f(MAC_MI_MODE,
788                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
789                 udelay(80);
790         }
791
792         *val = 0x0;
793
794         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
795                       MI_COM_PHY_ADDR_MASK);
796         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
797                       MI_COM_REG_ADDR_MASK);
798         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
799
800         tw32_f(MAC_MI_COM, frame_val);
801
802         loops = PHY_BUSY_LOOPS;
803         while (loops != 0) {
804                 udelay(10);
805                 frame_val = tr32(MAC_MI_COM);
806
807                 if ((frame_val & MI_COM_BUSY) == 0) {
808                         udelay(5);
809                         frame_val = tr32(MAC_MI_COM);
810                         break;
811                 }
812                 loops -= 1;
813         }
814
815         ret = -EBUSY;
816         if (loops != 0) {
817                 *val = frame_val & MI_COM_DATA_MASK;
818                 ret = 0;
819         }
820
821         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
822                 tw32_f(MAC_MI_MODE, tp->mi_mode);
823                 udelay(80);
824         }
825
826         return ret;
827 }
828
829 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
830 {
831         u32 frame_val;
832         unsigned int loops;
833         int ret;
834
835         if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
836             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
837                 return 0;
838
839         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
840                 tw32_f(MAC_MI_MODE,
841                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
842                 udelay(80);
843         }
844
845         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
846                       MI_COM_PHY_ADDR_MASK);
847         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
848                       MI_COM_REG_ADDR_MASK);
849         frame_val |= (val & MI_COM_DATA_MASK);
850         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
851
852         tw32_f(MAC_MI_COM, frame_val);
853
854         loops = PHY_BUSY_LOOPS;
855         while (loops != 0) {
856                 udelay(10);
857                 frame_val = tr32(MAC_MI_COM);
858                 if ((frame_val & MI_COM_BUSY) == 0) {
859                         udelay(5);
860                         frame_val = tr32(MAC_MI_COM);
861                         break;
862                 }
863                 loops -= 1;
864         }
865
866         ret = -EBUSY;
867         if (loops != 0)
868                 ret = 0;
869
870         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
871                 tw32_f(MAC_MI_MODE, tp->mi_mode);
872                 udelay(80);
873         }
874
875         return ret;
876 }
877
878 static int tg3_bmcr_reset(struct tg3 *tp)
879 {
880         u32 phy_control;
881         int limit, err;
882
883         /* OK, reset it, and poll the BMCR_RESET bit until it
884          * clears or we time out.
885          */
886         phy_control = BMCR_RESET;
887         err = tg3_writephy(tp, MII_BMCR, phy_control);
888         if (err != 0)
889                 return -EBUSY;
890
891         limit = 5000;
892         while (limit--) {
893                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
894                 if (err != 0)
895                         return -EBUSY;
896
897                 if ((phy_control & BMCR_RESET) == 0) {
898                         udelay(40);
899                         break;
900                 }
901                 udelay(10);
902         }
903         if (limit < 0)
904                 return -EBUSY;
905
906         return 0;
907 }
908
909 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
910 {
911         struct tg3 *tp = bp->priv;
912         u32 val;
913
914         spin_lock_bh(&tp->lock);
915
916         if (tg3_readphy(tp, reg, &val))
917                 val = -EIO;
918
919         spin_unlock_bh(&tp->lock);
920
921         return val;
922 }
923
924 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
925 {
926         struct tg3 *tp = bp->priv;
927         u32 ret = 0;
928
929         spin_lock_bh(&tp->lock);
930
931         if (tg3_writephy(tp, reg, val))
932                 ret = -EIO;
933
934         spin_unlock_bh(&tp->lock);
935
936         return ret;
937 }
938
939 static int tg3_mdio_reset(struct mii_bus *bp)
940 {
941         return 0;
942 }
943
944 static void tg3_mdio_config_5785(struct tg3 *tp)
945 {
946         u32 val;
947         struct phy_device *phydev;
948
949         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
950         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
951         case TG3_PHY_ID_BCM50610:
952         case TG3_PHY_ID_BCM50610M:
953                 val = MAC_PHYCFG2_50610_LED_MODES;
954                 break;
955         case TG3_PHY_ID_BCMAC131:
956                 val = MAC_PHYCFG2_AC131_LED_MODES;
957                 break;
958         case TG3_PHY_ID_RTL8211C:
959                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
960                 break;
961         case TG3_PHY_ID_RTL8201E:
962                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
963                 break;
964         default:
965                 return;
966         }
967
968         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
969                 tw32(MAC_PHYCFG2, val);
970
971                 val = tr32(MAC_PHYCFG1);
972                 val &= ~(MAC_PHYCFG1_RGMII_INT |
973                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
974                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
975                 tw32(MAC_PHYCFG1, val);
976
977                 return;
978         }
979
980         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
981                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
982                        MAC_PHYCFG2_FMODE_MASK_MASK |
983                        MAC_PHYCFG2_GMODE_MASK_MASK |
984                        MAC_PHYCFG2_ACT_MASK_MASK   |
985                        MAC_PHYCFG2_QUAL_MASK_MASK |
986                        MAC_PHYCFG2_INBAND_ENABLE;
987
988         tw32(MAC_PHYCFG2, val);
989
990         val = tr32(MAC_PHYCFG1);
991         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
992                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
993         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
994                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
995                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
996                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
997                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
998         }
999         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1000                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1001         tw32(MAC_PHYCFG1, val);
1002
1003         val = tr32(MAC_EXT_RGMII_MODE);
1004         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1005                  MAC_RGMII_MODE_RX_QUALITY |
1006                  MAC_RGMII_MODE_RX_ACTIVITY |
1007                  MAC_RGMII_MODE_RX_ENG_DET |
1008                  MAC_RGMII_MODE_TX_ENABLE |
1009                  MAC_RGMII_MODE_TX_LOWPWR |
1010                  MAC_RGMII_MODE_TX_RESET);
1011         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
1012                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1013                         val |= MAC_RGMII_MODE_RX_INT_B |
1014                                MAC_RGMII_MODE_RX_QUALITY |
1015                                MAC_RGMII_MODE_RX_ACTIVITY |
1016                                MAC_RGMII_MODE_RX_ENG_DET;
1017                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1018                         val |= MAC_RGMII_MODE_TX_ENABLE |
1019                                MAC_RGMII_MODE_TX_LOWPWR |
1020                                MAC_RGMII_MODE_TX_RESET;
1021         }
1022         tw32(MAC_EXT_RGMII_MODE, val);
1023 }
1024
1025 static void tg3_mdio_start(struct tg3 *tp)
1026 {
1027         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1028         tw32_f(MAC_MI_MODE, tp->mi_mode);
1029         udelay(80);
1030
1031         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1032                 u32 funcnum, is_serdes;
1033
1034                 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1035                 if (funcnum)
1036                         tp->phy_addr = 2;
1037                 else
1038                         tp->phy_addr = 1;
1039
1040                 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1041                 if (is_serdes)
1042                         tp->phy_addr += 7;
1043         } else
1044                 tp->phy_addr = TG3_PHY_MII_ADDR;
1045
1046         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1047             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1048                 tg3_mdio_config_5785(tp);
1049 }
1050
1051 static int tg3_mdio_init(struct tg3 *tp)
1052 {
1053         int i;
1054         u32 reg;
1055         struct phy_device *phydev;
1056
1057         tg3_mdio_start(tp);
1058
1059         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1060             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1061                 return 0;
1062
1063         tp->mdio_bus = mdiobus_alloc();
1064         if (tp->mdio_bus == NULL)
1065                 return -ENOMEM;
1066
1067         tp->mdio_bus->name     = "tg3 mdio bus";
1068         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1069                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1070         tp->mdio_bus->priv     = tp;
1071         tp->mdio_bus->parent   = &tp->pdev->dev;
1072         tp->mdio_bus->read     = &tg3_mdio_read;
1073         tp->mdio_bus->write    = &tg3_mdio_write;
1074         tp->mdio_bus->reset    = &tg3_mdio_reset;
1075         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1076         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1077
1078         for (i = 0; i < PHY_MAX_ADDR; i++)
1079                 tp->mdio_bus->irq[i] = PHY_POLL;
1080
1081         /* The bus registration will look for all the PHYs on the mdio bus.
1082          * Unfortunately, it does not ensure the PHY is powered up before
1083          * accessing the PHY ID registers.  A chip reset is the
1084          * quickest way to bring the device back to an operational state..
1085          */
1086         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1087                 tg3_bmcr_reset(tp);
1088
1089         i = mdiobus_register(tp->mdio_bus);
1090         if (i) {
1091                 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1092                         tp->dev->name, i);
1093                 mdiobus_free(tp->mdio_bus);
1094                 return i;
1095         }
1096
1097         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1098
1099         if (!phydev || !phydev->drv) {
1100                 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1101                 mdiobus_unregister(tp->mdio_bus);
1102                 mdiobus_free(tp->mdio_bus);
1103                 return -ENODEV;
1104         }
1105
1106         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1107         case TG3_PHY_ID_BCM57780:
1108                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1109                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1110                 break;
1111         case TG3_PHY_ID_BCM50610:
1112         case TG3_PHY_ID_BCM50610M:
1113                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1114                                      PHY_BRCM_RX_REFCLK_UNUSED |
1115                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1116                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1117                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1118                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1119                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1120                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1121                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1122                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1123                 /* fallthru */
1124         case TG3_PHY_ID_RTL8211C:
1125                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1126                 break;
1127         case TG3_PHY_ID_RTL8201E:
1128         case TG3_PHY_ID_BCMAC131:
1129                 phydev->interface = PHY_INTERFACE_MODE_MII;
1130                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1131                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1132                 break;
1133         }
1134
1135         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1136
1137         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1138                 tg3_mdio_config_5785(tp);
1139
1140         return 0;
1141 }
1142
1143 static void tg3_mdio_fini(struct tg3 *tp)
1144 {
1145         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1146                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1147                 mdiobus_unregister(tp->mdio_bus);
1148                 mdiobus_free(tp->mdio_bus);
1149         }
1150 }
1151
1152 /* tp->lock is held. */
1153 static inline void tg3_generate_fw_event(struct tg3 *tp)
1154 {
1155         u32 val;
1156
1157         val = tr32(GRC_RX_CPU_EVENT);
1158         val |= GRC_RX_CPU_DRIVER_EVENT;
1159         tw32_f(GRC_RX_CPU_EVENT, val);
1160
1161         tp->last_event_jiffies = jiffies;
1162 }
1163
1164 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1165
1166 /* tp->lock is held. */
1167 static void tg3_wait_for_event_ack(struct tg3 *tp)
1168 {
1169         int i;
1170         unsigned int delay_cnt;
1171         long time_remain;
1172
1173         /* If enough time has passed, no wait is necessary. */
1174         time_remain = (long)(tp->last_event_jiffies + 1 +
1175                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1176                       (long)jiffies;
1177         if (time_remain < 0)
1178                 return;
1179
1180         /* Check if we can shorten the wait time. */
1181         delay_cnt = jiffies_to_usecs(time_remain);
1182         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1183                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1184         delay_cnt = (delay_cnt >> 3) + 1;
1185
1186         for (i = 0; i < delay_cnt; i++) {
1187                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1188                         break;
1189                 udelay(8);
1190         }
1191 }
1192
1193 /* tp->lock is held. */
1194 static void tg3_ump_link_report(struct tg3 *tp)
1195 {
1196         u32 reg;
1197         u32 val;
1198
1199         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1200             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1201                 return;
1202
1203         tg3_wait_for_event_ack(tp);
1204
1205         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1206
1207         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1208
1209         val = 0;
1210         if (!tg3_readphy(tp, MII_BMCR, &reg))
1211                 val = reg << 16;
1212         if (!tg3_readphy(tp, MII_BMSR, &reg))
1213                 val |= (reg & 0xffff);
1214         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1215
1216         val = 0;
1217         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1218                 val = reg << 16;
1219         if (!tg3_readphy(tp, MII_LPA, &reg))
1220                 val |= (reg & 0xffff);
1221         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1222
1223         val = 0;
1224         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1225                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1226                         val = reg << 16;
1227                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1228                         val |= (reg & 0xffff);
1229         }
1230         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1231
1232         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1233                 val = reg << 16;
1234         else
1235                 val = 0;
1236         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1237
1238         tg3_generate_fw_event(tp);
1239 }
1240
1241 static void tg3_link_report(struct tg3 *tp)
1242 {
1243         if (!netif_carrier_ok(tp->dev)) {
1244                 if (netif_msg_link(tp))
1245                         printk(KERN_INFO PFX "%s: Link is down.\n",
1246                                tp->dev->name);
1247                 tg3_ump_link_report(tp);
1248         } else if (netif_msg_link(tp)) {
1249                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1250                        tp->dev->name,
1251                        (tp->link_config.active_speed == SPEED_1000 ?
1252                         1000 :
1253                         (tp->link_config.active_speed == SPEED_100 ?
1254                          100 : 10)),
1255                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1256                         "full" : "half"));
1257
1258                 printk(KERN_INFO PFX
1259                        "%s: Flow control is %s for TX and %s for RX.\n",
1260                        tp->dev->name,
1261                        (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1262                        "on" : "off",
1263                        (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1264                        "on" : "off");
1265                 tg3_ump_link_report(tp);
1266         }
1267 }
1268
1269 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1270 {
1271         u16 miireg;
1272
1273         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1274                 miireg = ADVERTISE_PAUSE_CAP;
1275         else if (flow_ctrl & FLOW_CTRL_TX)
1276                 miireg = ADVERTISE_PAUSE_ASYM;
1277         else if (flow_ctrl & FLOW_CTRL_RX)
1278                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1279         else
1280                 miireg = 0;
1281
1282         return miireg;
1283 }
1284
1285 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1286 {
1287         u16 miireg;
1288
1289         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1290                 miireg = ADVERTISE_1000XPAUSE;
1291         else if (flow_ctrl & FLOW_CTRL_TX)
1292                 miireg = ADVERTISE_1000XPSE_ASYM;
1293         else if (flow_ctrl & FLOW_CTRL_RX)
1294                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1295         else
1296                 miireg = 0;
1297
1298         return miireg;
1299 }
1300
1301 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1302 {
1303         u8 cap = 0;
1304
1305         if (lcladv & ADVERTISE_1000XPAUSE) {
1306                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1307                         if (rmtadv & LPA_1000XPAUSE)
1308                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1309                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1310                                 cap = FLOW_CTRL_RX;
1311                 } else {
1312                         if (rmtadv & LPA_1000XPAUSE)
1313                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1314                 }
1315         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1316                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1317                         cap = FLOW_CTRL_TX;
1318         }
1319
1320         return cap;
1321 }
1322
1323 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1324 {
1325         u8 autoneg;
1326         u8 flowctrl = 0;
1327         u32 old_rx_mode = tp->rx_mode;
1328         u32 old_tx_mode = tp->tx_mode;
1329
1330         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1331                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1332         else
1333                 autoneg = tp->link_config.autoneg;
1334
1335         if (autoneg == AUTONEG_ENABLE &&
1336             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1337                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1338                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1339                 else
1340                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1341         } else
1342                 flowctrl = tp->link_config.flowctrl;
1343
1344         tp->link_config.active_flowctrl = flowctrl;
1345
1346         if (flowctrl & FLOW_CTRL_RX)
1347                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1348         else
1349                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1350
1351         if (old_rx_mode != tp->rx_mode)
1352                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1353
1354         if (flowctrl & FLOW_CTRL_TX)
1355                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1356         else
1357                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1358
1359         if (old_tx_mode != tp->tx_mode)
1360                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1361 }
1362
1363 static void tg3_adjust_link(struct net_device *dev)
1364 {
1365         u8 oldflowctrl, linkmesg = 0;
1366         u32 mac_mode, lcl_adv, rmt_adv;
1367         struct tg3 *tp = netdev_priv(dev);
1368         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1369
1370         spin_lock_bh(&tp->lock);
1371
1372         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1373                                     MAC_MODE_HALF_DUPLEX);
1374
1375         oldflowctrl = tp->link_config.active_flowctrl;
1376
1377         if (phydev->link) {
1378                 lcl_adv = 0;
1379                 rmt_adv = 0;
1380
1381                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1382                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1383                 else if (phydev->speed == SPEED_1000 ||
1384                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1385                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1386                 else
1387                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1388
1389                 if (phydev->duplex == DUPLEX_HALF)
1390                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1391                 else {
1392                         lcl_adv = tg3_advert_flowctrl_1000T(
1393                                   tp->link_config.flowctrl);
1394
1395                         if (phydev->pause)
1396                                 rmt_adv = LPA_PAUSE_CAP;
1397                         if (phydev->asym_pause)
1398                                 rmt_adv |= LPA_PAUSE_ASYM;
1399                 }
1400
1401                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1402         } else
1403                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1404
1405         if (mac_mode != tp->mac_mode) {
1406                 tp->mac_mode = mac_mode;
1407                 tw32_f(MAC_MODE, tp->mac_mode);
1408                 udelay(40);
1409         }
1410
1411         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1412                 if (phydev->speed == SPEED_10)
1413                         tw32(MAC_MI_STAT,
1414                              MAC_MI_STAT_10MBPS_MODE |
1415                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1416                 else
1417                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1418         }
1419
1420         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1421                 tw32(MAC_TX_LENGTHS,
1422                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1423                       (6 << TX_LENGTHS_IPG_SHIFT) |
1424                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1425         else
1426                 tw32(MAC_TX_LENGTHS,
1427                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1428                       (6 << TX_LENGTHS_IPG_SHIFT) |
1429                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1430
1431         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1432             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1433             phydev->speed != tp->link_config.active_speed ||
1434             phydev->duplex != tp->link_config.active_duplex ||
1435             oldflowctrl != tp->link_config.active_flowctrl)
1436             linkmesg = 1;
1437
1438         tp->link_config.active_speed = phydev->speed;
1439         tp->link_config.active_duplex = phydev->duplex;
1440
1441         spin_unlock_bh(&tp->lock);
1442
1443         if (linkmesg)
1444                 tg3_link_report(tp);
1445 }
1446
1447 static int tg3_phy_init(struct tg3 *tp)
1448 {
1449         struct phy_device *phydev;
1450
1451         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1452                 return 0;
1453
1454         /* Bring the PHY back to a known state. */
1455         tg3_bmcr_reset(tp);
1456
1457         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1458
1459         /* Attach the MAC to the PHY. */
1460         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1461                              phydev->dev_flags, phydev->interface);
1462         if (IS_ERR(phydev)) {
1463                 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1464                 return PTR_ERR(phydev);
1465         }
1466
1467         /* Mask with MAC supported features. */
1468         switch (phydev->interface) {
1469         case PHY_INTERFACE_MODE_GMII:
1470         case PHY_INTERFACE_MODE_RGMII:
1471                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1472                         phydev->supported &= (PHY_GBIT_FEATURES |
1473                                               SUPPORTED_Pause |
1474                                               SUPPORTED_Asym_Pause);
1475                         break;
1476                 }
1477                 /* fallthru */
1478         case PHY_INTERFACE_MODE_MII:
1479                 phydev->supported &= (PHY_BASIC_FEATURES |
1480                                       SUPPORTED_Pause |
1481                                       SUPPORTED_Asym_Pause);
1482                 break;
1483         default:
1484                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1485                 return -EINVAL;
1486         }
1487
1488         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1489
1490         phydev->advertising = phydev->supported;
1491
1492         return 0;
1493 }
1494
1495 static void tg3_phy_start(struct tg3 *tp)
1496 {
1497         struct phy_device *phydev;
1498
1499         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1500                 return;
1501
1502         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1503
1504         if (tp->link_config.phy_is_low_power) {
1505                 tp->link_config.phy_is_low_power = 0;
1506                 phydev->speed = tp->link_config.orig_speed;
1507                 phydev->duplex = tp->link_config.orig_duplex;
1508                 phydev->autoneg = tp->link_config.orig_autoneg;
1509                 phydev->advertising = tp->link_config.orig_advertising;
1510         }
1511
1512         phy_start(phydev);
1513
1514         phy_start_aneg(phydev);
1515 }
1516
1517 static void tg3_phy_stop(struct tg3 *tp)
1518 {
1519         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1520                 return;
1521
1522         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1523 }
1524
1525 static void tg3_phy_fini(struct tg3 *tp)
1526 {
1527         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1528                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1529                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1530         }
1531 }
1532
1533 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1534 {
1535         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1536         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1537 }
1538
1539 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1540 {
1541         u32 phytest;
1542
1543         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1544                 u32 phy;
1545
1546                 tg3_writephy(tp, MII_TG3_FET_TEST,
1547                              phytest | MII_TG3_FET_SHADOW_EN);
1548                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1549                         if (enable)
1550                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1551                         else
1552                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1553                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1554                 }
1555                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1556         }
1557 }
1558
1559 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1560 {
1561         u32 reg;
1562
1563         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1564                 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1565              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1566                 return;
1567
1568         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1569                 tg3_phy_fet_toggle_apd(tp, enable);
1570                 return;
1571         }
1572
1573         reg = MII_TG3_MISC_SHDW_WREN |
1574               MII_TG3_MISC_SHDW_SCR5_SEL |
1575               MII_TG3_MISC_SHDW_SCR5_LPED |
1576               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1577               MII_TG3_MISC_SHDW_SCR5_SDTL |
1578               MII_TG3_MISC_SHDW_SCR5_C125OE;
1579         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1580                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1581
1582         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1583
1584
1585         reg = MII_TG3_MISC_SHDW_WREN |
1586               MII_TG3_MISC_SHDW_APD_SEL |
1587               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1588         if (enable)
1589                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1590
1591         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1592 }
1593
1594 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1595 {
1596         u32 phy;
1597
1598         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1599             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1600                 return;
1601
1602         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1603                 u32 ephy;
1604
1605                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1606                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1607
1608                         tg3_writephy(tp, MII_TG3_FET_TEST,
1609                                      ephy | MII_TG3_FET_SHADOW_EN);
1610                         if (!tg3_readphy(tp, reg, &phy)) {
1611                                 if (enable)
1612                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1613                                 else
1614                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1615                                 tg3_writephy(tp, reg, phy);
1616                         }
1617                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1618                 }
1619         } else {
1620                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1621                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1622                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1623                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1624                         if (enable)
1625                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1626                         else
1627                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1628                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1629                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1630                 }
1631         }
1632 }
1633
1634 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1635 {
1636         u32 val;
1637
1638         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1639                 return;
1640
1641         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1642             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1643                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1644                              (val | (1 << 15) | (1 << 4)));
1645 }
1646
1647 static void tg3_phy_apply_otp(struct tg3 *tp)
1648 {
1649         u32 otp, phy;
1650
1651         if (!tp->phy_otp)
1652                 return;
1653
1654         otp = tp->phy_otp;
1655
1656         /* Enable SM_DSP clock and tx 6dB coding. */
1657         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1658               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1659               MII_TG3_AUXCTL_ACTL_TX_6DB;
1660         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1661
1662         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1663         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1664         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1665
1666         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1667               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1668         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1669
1670         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1671         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1672         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1673
1674         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1675         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1676
1677         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1678         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1679
1680         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1681               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1682         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1683
1684         /* Turn off SM_DSP clock. */
1685         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1686               MII_TG3_AUXCTL_ACTL_TX_6DB;
1687         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1688 }
1689
1690 static int tg3_wait_macro_done(struct tg3 *tp)
1691 {
1692         int limit = 100;
1693
1694         while (limit--) {
1695                 u32 tmp32;
1696
1697                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1698                         if ((tmp32 & 0x1000) == 0)
1699                                 break;
1700                 }
1701         }
1702         if (limit < 0)
1703                 return -EBUSY;
1704
1705         return 0;
1706 }
1707
1708 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1709 {
1710         static const u32 test_pat[4][6] = {
1711         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1712         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1713         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1714         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1715         };
1716         int chan;
1717
1718         for (chan = 0; chan < 4; chan++) {
1719                 int i;
1720
1721                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1722                              (chan * 0x2000) | 0x0200);
1723                 tg3_writephy(tp, 0x16, 0x0002);
1724
1725                 for (i = 0; i < 6; i++)
1726                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1727                                      test_pat[chan][i]);
1728
1729                 tg3_writephy(tp, 0x16, 0x0202);
1730                 if (tg3_wait_macro_done(tp)) {
1731                         *resetp = 1;
1732                         return -EBUSY;
1733                 }
1734
1735                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1736                              (chan * 0x2000) | 0x0200);
1737                 tg3_writephy(tp, 0x16, 0x0082);
1738                 if (tg3_wait_macro_done(tp)) {
1739                         *resetp = 1;
1740                         return -EBUSY;
1741                 }
1742
1743                 tg3_writephy(tp, 0x16, 0x0802);
1744                 if (tg3_wait_macro_done(tp)) {
1745                         *resetp = 1;
1746                         return -EBUSY;
1747                 }
1748
1749                 for (i = 0; i < 6; i += 2) {
1750                         u32 low, high;
1751
1752                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1753                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1754                             tg3_wait_macro_done(tp)) {
1755                                 *resetp = 1;
1756                                 return -EBUSY;
1757                         }
1758                         low &= 0x7fff;
1759                         high &= 0x000f;
1760                         if (low != test_pat[chan][i] ||
1761                             high != test_pat[chan][i+1]) {
1762                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1763                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1764                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1765
1766                                 return -EBUSY;
1767                         }
1768                 }
1769         }
1770
1771         return 0;
1772 }
1773
1774 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1775 {
1776         int chan;
1777
1778         for (chan = 0; chan < 4; chan++) {
1779                 int i;
1780
1781                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1782                              (chan * 0x2000) | 0x0200);
1783                 tg3_writephy(tp, 0x16, 0x0002);
1784                 for (i = 0; i < 6; i++)
1785                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1786                 tg3_writephy(tp, 0x16, 0x0202);
1787                 if (tg3_wait_macro_done(tp))
1788                         return -EBUSY;
1789         }
1790
1791         return 0;
1792 }
1793
1794 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1795 {
1796         u32 reg32, phy9_orig;
1797         int retries, do_phy_reset, err;
1798
1799         retries = 10;
1800         do_phy_reset = 1;
1801         do {
1802                 if (do_phy_reset) {
1803                         err = tg3_bmcr_reset(tp);
1804                         if (err)
1805                                 return err;
1806                         do_phy_reset = 0;
1807                 }
1808
1809                 /* Disable transmitter and interrupt.  */
1810                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1811                         continue;
1812
1813                 reg32 |= 0x3000;
1814                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1815
1816                 /* Set full-duplex, 1000 mbps.  */
1817                 tg3_writephy(tp, MII_BMCR,
1818                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1819
1820                 /* Set to master mode.  */
1821                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1822                         continue;
1823
1824                 tg3_writephy(tp, MII_TG3_CTRL,
1825                              (MII_TG3_CTRL_AS_MASTER |
1826                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1827
1828                 /* Enable SM_DSP_CLOCK and 6dB.  */
1829                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1830
1831                 /* Block the PHY control access.  */
1832                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1833                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1834
1835                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1836                 if (!err)
1837                         break;
1838         } while (--retries);
1839
1840         err = tg3_phy_reset_chanpat(tp);
1841         if (err)
1842                 return err;
1843
1844         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1845         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1846
1847         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1848         tg3_writephy(tp, 0x16, 0x0000);
1849
1850         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1851             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1852                 /* Set Extended packet length bit for jumbo frames */
1853                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1854         }
1855         else {
1856                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1857         }
1858
1859         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1860
1861         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1862                 reg32 &= ~0x3000;
1863                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1864         } else if (!err)
1865                 err = -EBUSY;
1866
1867         return err;
1868 }
1869
1870 /* This will reset the tigon3 PHY if there is no valid
1871  * link unless the FORCE argument is non-zero.
1872  */
1873 static int tg3_phy_reset(struct tg3 *tp)
1874 {
1875         u32 cpmuctrl;
1876         u32 phy_status;
1877         int err;
1878
1879         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1880                 u32 val;
1881
1882                 val = tr32(GRC_MISC_CFG);
1883                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1884                 udelay(40);
1885         }
1886         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1887         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1888         if (err != 0)
1889                 return -EBUSY;
1890
1891         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1892                 netif_carrier_off(tp->dev);
1893                 tg3_link_report(tp);
1894         }
1895
1896         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1897             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1898             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1899                 err = tg3_phy_reset_5703_4_5(tp);
1900                 if (err)
1901                         return err;
1902                 goto out;
1903         }
1904
1905         cpmuctrl = 0;
1906         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1907             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1908                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1909                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1910                         tw32(TG3_CPMU_CTRL,
1911                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1912         }
1913
1914         err = tg3_bmcr_reset(tp);
1915         if (err)
1916                 return err;
1917
1918         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1919                 u32 phy;
1920
1921                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1922                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1923
1924                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1925         }
1926
1927         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1928             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1929                 u32 val;
1930
1931                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1932                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1933                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1934                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1935                         udelay(40);
1936                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1937                 }
1938         }
1939
1940         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1941             (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))
1942                 return 0;
1943
1944         tg3_phy_apply_otp(tp);
1945
1946         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1947                 tg3_phy_toggle_apd(tp, true);
1948         else
1949                 tg3_phy_toggle_apd(tp, false);
1950
1951 out:
1952         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1953                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1954                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1955                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1956                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1957                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1958                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1959         }
1960         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1961                 tg3_writephy(tp, 0x1c, 0x8d68);
1962                 tg3_writephy(tp, 0x1c, 0x8d68);
1963         }
1964         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1965                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1966                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1967                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1968                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1969                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1970                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1971                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1972                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1973         }
1974         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1975                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1976                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1977                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1978                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1979                         tg3_writephy(tp, MII_TG3_TEST1,
1980                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1981                 } else
1982                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1983                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1984         }
1985         /* Set Extended packet length bit (bit 14) on all chips that */
1986         /* support jumbo frames */
1987         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1988                 /* Cannot do read-modify-write on 5401 */
1989                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1990         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1991                 u32 phy_reg;
1992
1993                 /* Set bit 14 with read-modify-write to preserve other bits */
1994                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1995                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1996                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1997         }
1998
1999         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2000          * jumbo frames transmission.
2001          */
2002         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2003                 u32 phy_reg;
2004
2005                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2006                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
2007                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2008         }
2009
2010         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2011                 /* adjust output voltage */
2012                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2013         }
2014
2015         tg3_phy_toggle_automdix(tp, 1);
2016         tg3_phy_set_wirespeed(tp);
2017         return 0;
2018 }
2019
2020 static void tg3_frob_aux_power(struct tg3 *tp)
2021 {
2022         struct tg3 *tp_peer = tp;
2023
2024         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
2025                 return;
2026
2027         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2028             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2029             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2030                 struct net_device *dev_peer;
2031
2032                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2033                 /* remove_one() may have been run on the peer. */
2034                 if (!dev_peer)
2035                         tp_peer = tp;
2036                 else
2037                         tp_peer = netdev_priv(dev_peer);
2038         }
2039
2040         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2041             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2042             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2043             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2044                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2045                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2046                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2047                                     (GRC_LCLCTRL_GPIO_OE0 |
2048                                      GRC_LCLCTRL_GPIO_OE1 |
2049                                      GRC_LCLCTRL_GPIO_OE2 |
2050                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2051                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2052                                     100);
2053                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2054                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2055                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2056                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2057                                              GRC_LCLCTRL_GPIO_OE1 |
2058                                              GRC_LCLCTRL_GPIO_OE2 |
2059                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2060                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2061                                              tp->grc_local_ctrl;
2062                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2063
2064                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2065                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2066
2067                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2068                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2069                 } else {
2070                         u32 no_gpio2;
2071                         u32 grc_local_ctrl = 0;
2072
2073                         if (tp_peer != tp &&
2074                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2075                                 return;
2076
2077                         /* Workaround to prevent overdrawing Amps. */
2078                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2079                             ASIC_REV_5714) {
2080                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2081                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2082                                             grc_local_ctrl, 100);
2083                         }
2084
2085                         /* On 5753 and variants, GPIO2 cannot be used. */
2086                         no_gpio2 = tp->nic_sram_data_cfg &
2087                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2088
2089                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2090                                          GRC_LCLCTRL_GPIO_OE1 |
2091                                          GRC_LCLCTRL_GPIO_OE2 |
2092                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2093                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2094                         if (no_gpio2) {
2095                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2096                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2097                         }
2098                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2099                                                     grc_local_ctrl, 100);
2100
2101                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2102
2103                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2104                                                     grc_local_ctrl, 100);
2105
2106                         if (!no_gpio2) {
2107                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2108                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2109                                             grc_local_ctrl, 100);
2110                         }
2111                 }
2112         } else {
2113                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2114                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2115                         if (tp_peer != tp &&
2116                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2117                                 return;
2118
2119                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2120                                     (GRC_LCLCTRL_GPIO_OE1 |
2121                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2122
2123                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2124                                     GRC_LCLCTRL_GPIO_OE1, 100);
2125
2126                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2127                                     (GRC_LCLCTRL_GPIO_OE1 |
2128                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2129                 }
2130         }
2131 }
2132
2133 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2134 {
2135         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2136                 return 1;
2137         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2138                 if (speed != SPEED_10)
2139                         return 1;
2140         } else if (speed == SPEED_10)
2141                 return 1;
2142
2143         return 0;
2144 }
2145
2146 static int tg3_setup_phy(struct tg3 *, int);
2147
2148 #define RESET_KIND_SHUTDOWN     0
2149 #define RESET_KIND_INIT         1
2150 #define RESET_KIND_SUSPEND      2
2151
2152 static void tg3_write_sig_post_reset(struct tg3 *, int);
2153 static int tg3_halt_cpu(struct tg3 *, u32);
2154
2155 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2156 {
2157         u32 val;
2158
2159         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2160                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2161                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2162                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2163
2164                         sg_dig_ctrl |=
2165                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2166                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2167                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2168                 }
2169                 return;
2170         }
2171
2172         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2173                 tg3_bmcr_reset(tp);
2174                 val = tr32(GRC_MISC_CFG);
2175                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2176                 udelay(40);
2177                 return;
2178         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2179                 u32 phytest;
2180                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2181                         u32 phy;
2182
2183                         tg3_writephy(tp, MII_ADVERTISE, 0);
2184                         tg3_writephy(tp, MII_BMCR,
2185                                      BMCR_ANENABLE | BMCR_ANRESTART);
2186
2187                         tg3_writephy(tp, MII_TG3_FET_TEST,
2188                                      phytest | MII_TG3_FET_SHADOW_EN);
2189                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2190                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2191                                 tg3_writephy(tp,
2192                                              MII_TG3_FET_SHDW_AUXMODE4,
2193                                              phy);
2194                         }
2195                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2196                 }
2197                 return;
2198         } else if (do_low_power) {
2199                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2200                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2201
2202                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2203                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2204                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2205                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2206                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2207         }
2208
2209         /* The PHY should not be powered down on some chips because
2210          * of bugs.
2211          */
2212         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2213             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2214             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2215              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2216                 return;
2217
2218         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2219             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2220                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2221                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2222                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2223                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2224         }
2225
2226         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2227 }
2228
2229 /* tp->lock is held. */
2230 static int tg3_nvram_lock(struct tg3 *tp)
2231 {
2232         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2233                 int i;
2234
2235                 if (tp->nvram_lock_cnt == 0) {
2236                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2237                         for (i = 0; i < 8000; i++) {
2238                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2239                                         break;
2240                                 udelay(20);
2241                         }
2242                         if (i == 8000) {
2243                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2244                                 return -ENODEV;
2245                         }
2246                 }
2247                 tp->nvram_lock_cnt++;
2248         }
2249         return 0;
2250 }
2251
2252 /* tp->lock is held. */
2253 static void tg3_nvram_unlock(struct tg3 *tp)
2254 {
2255         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2256                 if (tp->nvram_lock_cnt > 0)
2257                         tp->nvram_lock_cnt--;
2258                 if (tp->nvram_lock_cnt == 0)
2259                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2260         }
2261 }
2262
2263 /* tp->lock is held. */
2264 static void tg3_enable_nvram_access(struct tg3 *tp)
2265 {
2266         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2267             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2268                 u32 nvaccess = tr32(NVRAM_ACCESS);
2269
2270                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2271         }
2272 }
2273
2274 /* tp->lock is held. */
2275 static void tg3_disable_nvram_access(struct tg3 *tp)
2276 {
2277         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2278             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2279                 u32 nvaccess = tr32(NVRAM_ACCESS);
2280
2281                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2282         }
2283 }
2284
2285 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2286                                         u32 offset, u32 *val)
2287 {
2288         u32 tmp;
2289         int i;
2290
2291         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2292                 return -EINVAL;
2293
2294         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2295                                         EEPROM_ADDR_DEVID_MASK |
2296                                         EEPROM_ADDR_READ);
2297         tw32(GRC_EEPROM_ADDR,
2298              tmp |
2299              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2300              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2301               EEPROM_ADDR_ADDR_MASK) |
2302              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2303
2304         for (i = 0; i < 1000; i++) {
2305                 tmp = tr32(GRC_EEPROM_ADDR);
2306
2307                 if (tmp & EEPROM_ADDR_COMPLETE)
2308                         break;
2309                 msleep(1);
2310         }
2311         if (!(tmp & EEPROM_ADDR_COMPLETE))
2312                 return -EBUSY;
2313
2314         tmp = tr32(GRC_EEPROM_DATA);
2315
2316         /*
2317          * The data will always be opposite the native endian
2318          * format.  Perform a blind byteswap to compensate.
2319          */
2320         *val = swab32(tmp);
2321
2322         return 0;
2323 }
2324
2325 #define NVRAM_CMD_TIMEOUT 10000
2326
2327 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2328 {
2329         int i;
2330
2331         tw32(NVRAM_CMD, nvram_cmd);
2332         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2333                 udelay(10);
2334                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2335                         udelay(10);
2336                         break;
2337                 }
2338         }
2339
2340         if (i == NVRAM_CMD_TIMEOUT)
2341                 return -EBUSY;
2342
2343         return 0;
2344 }
2345
2346 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2347 {
2348         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2349             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2350             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2351            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2352             (tp->nvram_jedecnum == JEDEC_ATMEL))
2353
2354                 addr = ((addr / tp->nvram_pagesize) <<
2355                         ATMEL_AT45DB0X1B_PAGE_POS) +
2356                        (addr % tp->nvram_pagesize);
2357
2358         return addr;
2359 }
2360
2361 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2362 {
2363         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2364             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2365             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2366            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2367             (tp->nvram_jedecnum == JEDEC_ATMEL))
2368
2369                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2370                         tp->nvram_pagesize) +
2371                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2372
2373         return addr;
2374 }
2375
2376 /* NOTE: Data read in from NVRAM is byteswapped according to
2377  * the byteswapping settings for all other register accesses.
2378  * tg3 devices are BE devices, so on a BE machine, the data
2379  * returned will be exactly as it is seen in NVRAM.  On a LE
2380  * machine, the 32-bit value will be byteswapped.
2381  */
2382 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2383 {
2384         int ret;
2385
2386         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2387                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2388
2389         offset = tg3_nvram_phys_addr(tp, offset);
2390
2391         if (offset > NVRAM_ADDR_MSK)
2392                 return -EINVAL;
2393
2394         ret = tg3_nvram_lock(tp);
2395         if (ret)
2396                 return ret;
2397
2398         tg3_enable_nvram_access(tp);
2399
2400         tw32(NVRAM_ADDR, offset);
2401         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2402                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2403
2404         if (ret == 0)
2405                 *val = tr32(NVRAM_RDDATA);
2406
2407         tg3_disable_nvram_access(tp);
2408
2409         tg3_nvram_unlock(tp);
2410
2411         return ret;
2412 }
2413
2414 /* Ensures NVRAM data is in bytestream format. */
2415 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2416 {
2417         u32 v;
2418         int res = tg3_nvram_read(tp, offset, &v);
2419         if (!res)
2420                 *val = cpu_to_be32(v);
2421         return res;
2422 }
2423
2424 /* tp->lock is held. */
2425 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2426 {
2427         u32 addr_high, addr_low;
2428         int i;
2429
2430         addr_high = ((tp->dev->dev_addr[0] << 8) |
2431                      tp->dev->dev_addr[1]);
2432         addr_low = ((tp->dev->dev_addr[2] << 24) |
2433                     (tp->dev->dev_addr[3] << 16) |
2434                     (tp->dev->dev_addr[4] <<  8) |
2435                     (tp->dev->dev_addr[5] <<  0));
2436         for (i = 0; i < 4; i++) {
2437                 if (i == 1 && skip_mac_1)
2438                         continue;
2439                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2440                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2441         }
2442
2443         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2444             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2445                 for (i = 0; i < 12; i++) {
2446                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2447                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2448                 }
2449         }
2450
2451         addr_high = (tp->dev->dev_addr[0] +
2452                      tp->dev->dev_addr[1] +
2453                      tp->dev->dev_addr[2] +
2454                      tp->dev->dev_addr[3] +
2455                      tp->dev->dev_addr[4] +
2456                      tp->dev->dev_addr[5]) &
2457                 TX_BACKOFF_SEED_MASK;
2458         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2459 }
2460
2461 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2462 {
2463         u32 misc_host_ctrl;
2464         bool device_should_wake, do_low_power;
2465
2466         /* Make sure register accesses (indirect or otherwise)
2467          * will function correctly.
2468          */
2469         pci_write_config_dword(tp->pdev,
2470                                TG3PCI_MISC_HOST_CTRL,
2471                                tp->misc_host_ctrl);
2472
2473         switch (state) {
2474         case PCI_D0:
2475                 pci_enable_wake(tp->pdev, state, false);
2476                 pci_set_power_state(tp->pdev, PCI_D0);
2477
2478                 /* Switch out of Vaux if it is a NIC */
2479                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2480                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2481
2482                 return 0;
2483
2484         case PCI_D1:
2485         case PCI_D2:
2486         case PCI_D3hot:
2487                 break;
2488
2489         default:
2490                 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2491                         tp->dev->name, state);
2492                 return -EINVAL;
2493         }
2494
2495         /* Restore the CLKREQ setting. */
2496         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2497                 u16 lnkctl;
2498
2499                 pci_read_config_word(tp->pdev,
2500                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2501                                      &lnkctl);
2502                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2503                 pci_write_config_word(tp->pdev,
2504                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2505                                       lnkctl);
2506         }
2507
2508         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2509         tw32(TG3PCI_MISC_HOST_CTRL,
2510              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2511
2512         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2513                              device_may_wakeup(&tp->pdev->dev) &&
2514                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2515
2516         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2517                 do_low_power = false;
2518                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2519                     !tp->link_config.phy_is_low_power) {
2520                         struct phy_device *phydev;
2521                         u32 phyid, advertising;
2522
2523                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2524
2525                         tp->link_config.phy_is_low_power = 1;
2526
2527                         tp->link_config.orig_speed = phydev->speed;
2528                         tp->link_config.orig_duplex = phydev->duplex;
2529                         tp->link_config.orig_autoneg = phydev->autoneg;
2530                         tp->link_config.orig_advertising = phydev->advertising;
2531
2532                         advertising = ADVERTISED_TP |
2533                                       ADVERTISED_Pause |
2534                                       ADVERTISED_Autoneg |
2535                                       ADVERTISED_10baseT_Half;
2536
2537                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2538                             device_should_wake) {
2539                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2540                                         advertising |=
2541                                                 ADVERTISED_100baseT_Half |
2542                                                 ADVERTISED_100baseT_Full |
2543                                                 ADVERTISED_10baseT_Full;
2544                                 else
2545                                         advertising |= ADVERTISED_10baseT_Full;
2546                         }
2547
2548                         phydev->advertising = advertising;
2549
2550                         phy_start_aneg(phydev);
2551
2552                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2553                         if (phyid != TG3_PHY_ID_BCMAC131) {
2554                                 phyid &= TG3_PHY_OUI_MASK;
2555                                 if (phyid == TG3_PHY_OUI_1 ||
2556                                     phyid == TG3_PHY_OUI_2 ||
2557                                     phyid == TG3_PHY_OUI_3)
2558                                         do_low_power = true;
2559                         }
2560                 }
2561         } else {
2562                 do_low_power = true;
2563
2564                 if (tp->link_config.phy_is_low_power == 0) {
2565                         tp->link_config.phy_is_low_power = 1;
2566                         tp->link_config.orig_speed = tp->link_config.speed;
2567                         tp->link_config.orig_duplex = tp->link_config.duplex;
2568                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2569                 }
2570
2571                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2572                         tp->link_config.speed = SPEED_10;
2573                         tp->link_config.duplex = DUPLEX_HALF;
2574                         tp->link_config.autoneg = AUTONEG_ENABLE;
2575                         tg3_setup_phy(tp, 0);
2576                 }
2577         }
2578
2579         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2580                 u32 val;
2581
2582                 val = tr32(GRC_VCPU_EXT_CTRL);
2583                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2584         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2585                 int i;
2586                 u32 val;
2587
2588                 for (i = 0; i < 200; i++) {
2589                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2590                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2591                                 break;
2592                         msleep(1);
2593                 }
2594         }
2595         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2596                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2597                                                      WOL_DRV_STATE_SHUTDOWN |
2598                                                      WOL_DRV_WOL |
2599                                                      WOL_SET_MAGIC_PKT);
2600
2601         if (device_should_wake) {
2602                 u32 mac_mode;
2603
2604                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2605                         if (do_low_power) {
2606                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2607                                 udelay(40);
2608                         }
2609
2610                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2611                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2612                         else
2613                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2614
2615                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2616                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2617                             ASIC_REV_5700) {
2618                                 u32 speed = (tp->tg3_flags &
2619                                              TG3_FLAG_WOL_SPEED_100MB) ?
2620                                              SPEED_100 : SPEED_10;
2621                                 if (tg3_5700_link_polarity(tp, speed))
2622                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2623                                 else
2624                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2625                         }
2626                 } else {
2627                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2628                 }
2629
2630                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2631                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2632
2633                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2634                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2635                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2636                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2637                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2638                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2639
2640                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2641                         mac_mode |= tp->mac_mode &
2642                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2643                         if (mac_mode & MAC_MODE_APE_TX_EN)
2644                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2645                 }
2646
2647                 tw32_f(MAC_MODE, mac_mode);
2648                 udelay(100);
2649
2650                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2651                 udelay(10);
2652         }
2653
2654         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2655             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2656              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2657                 u32 base_val;
2658
2659                 base_val = tp->pci_clock_ctrl;
2660                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2661                              CLOCK_CTRL_TXCLK_DISABLE);
2662
2663                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2664                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2665         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2666                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2667                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2668                 /* do nothing */
2669         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2670                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2671                 u32 newbits1, newbits2;
2672
2673                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2674                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2675                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2676                                     CLOCK_CTRL_TXCLK_DISABLE |
2677                                     CLOCK_CTRL_ALTCLK);
2678                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2679                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2680                         newbits1 = CLOCK_CTRL_625_CORE;
2681                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2682                 } else {
2683                         newbits1 = CLOCK_CTRL_ALTCLK;
2684                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2685                 }
2686
2687                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2688                             40);
2689
2690                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2691                             40);
2692
2693                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2694                         u32 newbits3;
2695
2696                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2697                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2698                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2699                                             CLOCK_CTRL_TXCLK_DISABLE |
2700                                             CLOCK_CTRL_44MHZ_CORE);
2701                         } else {
2702                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2703                         }
2704
2705                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2706                                     tp->pci_clock_ctrl | newbits3, 40);
2707                 }
2708         }
2709
2710         if (!(device_should_wake) &&
2711             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2712                 tg3_power_down_phy(tp, do_low_power);
2713
2714         tg3_frob_aux_power(tp);
2715
2716         /* Workaround for unstable PLL clock */
2717         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2718             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2719                 u32 val = tr32(0x7d00);
2720
2721                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2722                 tw32(0x7d00, val);
2723                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2724                         int err;
2725
2726                         err = tg3_nvram_lock(tp);
2727                         tg3_halt_cpu(tp, RX_CPU_BASE);
2728                         if (!err)
2729                                 tg3_nvram_unlock(tp);
2730                 }
2731         }
2732
2733         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2734
2735         if (device_should_wake)
2736                 pci_enable_wake(tp->pdev, state, true);
2737
2738         /* Finally, set the new power state. */
2739         pci_set_power_state(tp->pdev, state);
2740
2741         return 0;
2742 }
2743
2744 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2745 {
2746         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2747         case MII_TG3_AUX_STAT_10HALF:
2748                 *speed = SPEED_10;
2749                 *duplex = DUPLEX_HALF;
2750                 break;
2751
2752         case MII_TG3_AUX_STAT_10FULL:
2753                 *speed = SPEED_10;
2754                 *duplex = DUPLEX_FULL;
2755                 break;
2756
2757         case MII_TG3_AUX_STAT_100HALF:
2758                 *speed = SPEED_100;
2759                 *duplex = DUPLEX_HALF;
2760                 break;
2761
2762         case MII_TG3_AUX_STAT_100FULL:
2763                 *speed = SPEED_100;
2764                 *duplex = DUPLEX_FULL;
2765                 break;
2766
2767         case MII_TG3_AUX_STAT_1000HALF:
2768                 *speed = SPEED_1000;
2769                 *duplex = DUPLEX_HALF;
2770                 break;
2771
2772         case MII_TG3_AUX_STAT_1000FULL:
2773                 *speed = SPEED_1000;
2774                 *duplex = DUPLEX_FULL;
2775                 break;
2776
2777         default:
2778                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2779                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2780                                  SPEED_10;
2781                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2782                                   DUPLEX_HALF;
2783                         break;
2784                 }
2785                 *speed = SPEED_INVALID;
2786                 *duplex = DUPLEX_INVALID;
2787                 break;
2788         }
2789 }
2790
2791 static void tg3_phy_copper_begin(struct tg3 *tp)
2792 {
2793         u32 new_adv;
2794         int i;
2795
2796         if (tp->link_config.phy_is_low_power) {
2797                 /* Entering low power mode.  Disable gigabit and
2798                  * 100baseT advertisements.
2799                  */
2800                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2801
2802                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2803                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2804                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2805                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2806
2807                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2808         } else if (tp->link_config.speed == SPEED_INVALID) {
2809                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2810                         tp->link_config.advertising &=
2811                                 ~(ADVERTISED_1000baseT_Half |
2812                                   ADVERTISED_1000baseT_Full);
2813
2814                 new_adv = ADVERTISE_CSMA;
2815                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2816                         new_adv |= ADVERTISE_10HALF;
2817                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2818                         new_adv |= ADVERTISE_10FULL;
2819                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2820                         new_adv |= ADVERTISE_100HALF;
2821                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2822                         new_adv |= ADVERTISE_100FULL;
2823
2824                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2825
2826                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2827
2828                 if (tp->link_config.advertising &
2829                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2830                         new_adv = 0;
2831                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2832                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2833                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2834                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2835                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2836                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2837                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2838                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2839                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2840                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2841                 } else {
2842                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2843                 }
2844         } else {
2845                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2846                 new_adv |= ADVERTISE_CSMA;
2847
2848                 /* Asking for a specific link mode. */
2849                 if (tp->link_config.speed == SPEED_1000) {
2850                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2851
2852                         if (tp->link_config.duplex == DUPLEX_FULL)
2853                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2854                         else
2855                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2856                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2857                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2858                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2859                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2860                 } else {
2861                         if (tp->link_config.speed == SPEED_100) {
2862                                 if (tp->link_config.duplex == DUPLEX_FULL)
2863                                         new_adv |= ADVERTISE_100FULL;
2864                                 else
2865                                         new_adv |= ADVERTISE_100HALF;
2866                         } else {
2867                                 if (tp->link_config.duplex == DUPLEX_FULL)
2868                                         new_adv |= ADVERTISE_10FULL;
2869                                 else
2870                                         new_adv |= ADVERTISE_10HALF;
2871                         }
2872                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2873
2874                         new_adv = 0;
2875                 }
2876
2877                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2878         }
2879
2880         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2881             tp->link_config.speed != SPEED_INVALID) {
2882                 u32 bmcr, orig_bmcr;
2883
2884                 tp->link_config.active_speed = tp->link_config.speed;
2885                 tp->link_config.active_duplex = tp->link_config.duplex;
2886
2887                 bmcr = 0;
2888                 switch (tp->link_config.speed) {
2889                 default:
2890                 case SPEED_10:
2891                         break;
2892
2893                 case SPEED_100:
2894                         bmcr |= BMCR_SPEED100;
2895                         break;
2896
2897                 case SPEED_1000:
2898                         bmcr |= TG3_BMCR_SPEED1000;
2899                         break;
2900                 }
2901
2902                 if (tp->link_config.duplex == DUPLEX_FULL)
2903                         bmcr |= BMCR_FULLDPLX;
2904
2905                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2906                     (bmcr != orig_bmcr)) {
2907                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2908                         for (i = 0; i < 1500; i++) {
2909                                 u32 tmp;
2910
2911                                 udelay(10);
2912                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2913                                     tg3_readphy(tp, MII_BMSR, &tmp))
2914                                         continue;
2915                                 if (!(tmp & BMSR_LSTATUS)) {
2916                                         udelay(40);
2917                                         break;
2918                                 }
2919                         }
2920                         tg3_writephy(tp, MII_BMCR, bmcr);
2921                         udelay(40);
2922                 }
2923         } else {
2924                 tg3_writephy(tp, MII_BMCR,
2925                              BMCR_ANENABLE | BMCR_ANRESTART);
2926         }
2927 }
2928
2929 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2930 {
2931         int err;
2932
2933         /* Turn off tap power management. */
2934         /* Set Extended packet length bit */
2935         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2936
2937         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2938         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2939
2940         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2941         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2942
2943         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2944         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2945
2946         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2947         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2948
2949         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2950         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2951
2952         udelay(40);
2953
2954         return err;
2955 }
2956
2957 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2958 {
2959         u32 adv_reg, all_mask = 0;
2960
2961         if (mask & ADVERTISED_10baseT_Half)
2962                 all_mask |= ADVERTISE_10HALF;
2963         if (mask & ADVERTISED_10baseT_Full)
2964                 all_mask |= ADVERTISE_10FULL;
2965         if (mask & ADVERTISED_100baseT_Half)
2966                 all_mask |= ADVERTISE_100HALF;
2967         if (mask & ADVERTISED_100baseT_Full)
2968                 all_mask |= ADVERTISE_100FULL;
2969
2970         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2971                 return 0;
2972
2973         if ((adv_reg & all_mask) != all_mask)
2974                 return 0;
2975         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2976                 u32 tg3_ctrl;
2977
2978                 all_mask = 0;
2979                 if (mask & ADVERTISED_1000baseT_Half)
2980                         all_mask |= ADVERTISE_1000HALF;
2981                 if (mask & ADVERTISED_1000baseT_Full)
2982                         all_mask |= ADVERTISE_1000FULL;
2983
2984                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2985                         return 0;
2986
2987                 if ((tg3_ctrl & all_mask) != all_mask)
2988                         return 0;
2989         }
2990         return 1;
2991 }
2992
2993 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2994 {
2995         u32 curadv, reqadv;
2996
2997         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2998                 return 1;
2999
3000         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3001         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3002
3003         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3004                 if (curadv != reqadv)
3005                         return 0;
3006
3007                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3008                         tg3_readphy(tp, MII_LPA, rmtadv);
3009         } else {
3010                 /* Reprogram the advertisement register, even if it
3011                  * does not affect the current link.  If the link
3012                  * gets renegotiated in the future, we can save an
3013                  * additional renegotiation cycle by advertising
3014                  * it correctly in the first place.
3015                  */
3016                 if (curadv != reqadv) {
3017                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3018                                      ADVERTISE_PAUSE_ASYM);
3019                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3020                 }
3021         }
3022
3023         return 1;
3024 }
3025
3026 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3027 {
3028         int current_link_up;
3029         u32 bmsr, dummy;
3030         u32 lcl_adv, rmt_adv;
3031         u16 current_speed;
3032         u8 current_duplex;
3033         int i, err;
3034
3035         tw32(MAC_EVENT, 0);
3036
3037         tw32_f(MAC_STATUS,
3038              (MAC_STATUS_SYNC_CHANGED |
3039               MAC_STATUS_CFG_CHANGED |
3040               MAC_STATUS_MI_COMPLETION |
3041               MAC_STATUS_LNKSTATE_CHANGED));
3042         udelay(40);
3043
3044         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3045                 tw32_f(MAC_MI_MODE,
3046                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3047                 udelay(80);
3048         }
3049
3050         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3051
3052         /* Some third-party PHYs need to be reset on link going
3053          * down.
3054          */
3055         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3056              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3057              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3058             netif_carrier_ok(tp->dev)) {
3059                 tg3_readphy(tp, MII_BMSR, &bmsr);
3060                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3061                     !(bmsr & BMSR_LSTATUS))
3062                         force_reset = 1;
3063         }
3064         if (force_reset)
3065                 tg3_phy_reset(tp);
3066
3067         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3068                 tg3_readphy(tp, MII_BMSR, &bmsr);
3069                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3070                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3071                         bmsr = 0;
3072
3073                 if (!(bmsr & BMSR_LSTATUS)) {
3074                         err = tg3_init_5401phy_dsp(tp);
3075                         if (err)
3076                                 return err;
3077
3078                         tg3_readphy(tp, MII_BMSR, &bmsr);
3079                         for (i = 0; i < 1000; i++) {
3080                                 udelay(10);
3081                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3082                                     (bmsr & BMSR_LSTATUS)) {
3083                                         udelay(40);
3084                                         break;
3085                                 }
3086                         }
3087
3088                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3089                             !(bmsr & BMSR_LSTATUS) &&
3090                             tp->link_config.active_speed == SPEED_1000) {
3091                                 err = tg3_phy_reset(tp);
3092                                 if (!err)
3093                                         err = tg3_init_5401phy_dsp(tp);
3094                                 if (err)
3095                                         return err;
3096                         }
3097                 }
3098         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3099                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3100                 /* 5701 {A0,B0} CRC bug workaround */
3101                 tg3_writephy(tp, 0x15, 0x0a75);
3102                 tg3_writephy(tp, 0x1c, 0x8c68);
3103                 tg3_writephy(tp, 0x1c, 0x8d68);
3104                 tg3_writephy(tp, 0x1c, 0x8c68);
3105         }
3106
3107         /* Clear pending interrupts... */
3108         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3109         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3110
3111         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3112                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3113         else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3114                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3115
3116         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3117             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3118                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3119                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3120                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3121                 else
3122                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3123         }
3124
3125         current_link_up = 0;
3126         current_speed = SPEED_INVALID;
3127         current_duplex = DUPLEX_INVALID;
3128
3129         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3130                 u32 val;
3131
3132                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3133                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3134                 if (!(val & (1 << 10))) {
3135                         val |= (1 << 10);
3136                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3137                         goto relink;
3138                 }
3139         }
3140
3141         bmsr = 0;
3142         for (i = 0; i < 100; i++) {
3143                 tg3_readphy(tp, MII_BMSR, &bmsr);
3144                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3145                     (bmsr & BMSR_LSTATUS))
3146                         break;
3147                 udelay(40);
3148         }
3149
3150         if (bmsr & BMSR_LSTATUS) {
3151                 u32 aux_stat, bmcr;
3152
3153                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3154                 for (i = 0; i < 2000; i++) {
3155                         udelay(10);
3156                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3157                             aux_stat)
3158                                 break;
3159                 }
3160
3161                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3162                                              &current_speed,
3163                                              &current_duplex);
3164
3165                 bmcr = 0;
3166                 for (i = 0; i < 200; i++) {
3167                         tg3_readphy(tp, MII_BMCR, &bmcr);
3168                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3169                                 continue;
3170                         if (bmcr && bmcr != 0x7fff)
3171                                 break;
3172                         udelay(10);
3173                 }
3174
3175                 lcl_adv = 0;
3176                 rmt_adv = 0;
3177
3178                 tp->link_config.active_speed = current_speed;
3179                 tp->link_config.active_duplex = current_duplex;
3180
3181                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3182                         if ((bmcr & BMCR_ANENABLE) &&
3183                             tg3_copper_is_advertising_all(tp,
3184                                                 tp->link_config.advertising)) {
3185                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3186                                                                   &rmt_adv))
3187                                         current_link_up = 1;
3188                         }
3189                 } else {
3190                         if (!(bmcr & BMCR_ANENABLE) &&
3191                             tp->link_config.speed == current_speed &&
3192                             tp->link_config.duplex == current_duplex &&
3193                             tp->link_config.flowctrl ==
3194                             tp->link_config.active_flowctrl) {
3195                                 current_link_up = 1;
3196                         }
3197                 }
3198
3199                 if (current_link_up == 1 &&
3200                     tp->link_config.active_duplex == DUPLEX_FULL)
3201                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3202         }
3203
3204 relink:
3205         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3206                 u32 tmp;
3207
3208                 tg3_phy_copper_begin(tp);
3209
3210                 tg3_readphy(tp, MII_BMSR, &tmp);
3211                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3212                     (tmp & BMSR_LSTATUS))
3213                         current_link_up = 1;
3214         }
3215
3216         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3217         if (current_link_up == 1) {
3218                 if (tp->link_config.active_speed == SPEED_100 ||
3219                     tp->link_config.active_speed == SPEED_10)
3220                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3221                 else
3222                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3223         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3224                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3225         else
3226                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3227
3228         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3229         if (tp->link_config.active_duplex == DUPLEX_HALF)
3230                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3231
3232         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3233                 if (current_link_up == 1 &&
3234                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3235                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3236                 else
3237                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3238         }
3239
3240         /* ??? Without this setting Netgear GA302T PHY does not
3241          * ??? send/receive packets...
3242          */
3243         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3244             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3245                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3246                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3247                 udelay(80);
3248         }
3249
3250         tw32_f(MAC_MODE, tp->mac_mode);
3251         udelay(40);
3252
3253         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3254                 /* Polled via timer. */
3255                 tw32_f(MAC_EVENT, 0);
3256         } else {
3257                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3258         }
3259         udelay(40);
3260
3261         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3262             current_link_up == 1 &&
3263             tp->link_config.active_speed == SPEED_1000 &&
3264             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3265              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3266                 udelay(120);
3267                 tw32_f(MAC_STATUS,
3268                      (MAC_STATUS_SYNC_CHANGED |
3269                       MAC_STATUS_CFG_CHANGED));
3270                 udelay(40);
3271                 tg3_write_mem(tp,
3272                               NIC_SRAM_FIRMWARE_MBOX,
3273                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3274         }
3275
3276         /* Prevent send BD corruption. */
3277         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3278                 u16 oldlnkctl, newlnkctl;
3279
3280                 pci_read_config_word(tp->pdev,
3281                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3282                                      &oldlnkctl);
3283                 if (tp->link_config.active_speed == SPEED_100 ||
3284                     tp->link_config.active_speed == SPEED_10)
3285                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3286                 else
3287                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3288                 if (newlnkctl != oldlnkctl)
3289                         pci_write_config_word(tp->pdev,
3290                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3291                                               newlnkctl);
3292         }
3293
3294         if (current_link_up != netif_carrier_ok(tp->dev)) {
3295                 if (current_link_up)
3296                         netif_carrier_on(tp->dev);
3297                 else
3298                         netif_carrier_off(tp->dev);
3299                 tg3_link_report(tp);
3300         }
3301
3302         return 0;
3303 }
3304
3305 struct tg3_fiber_aneginfo {
3306         int state;
3307 #define ANEG_STATE_UNKNOWN              0
3308 #define ANEG_STATE_AN_ENABLE            1
3309 #define ANEG_STATE_RESTART_INIT         2
3310 #define ANEG_STATE_RESTART              3
3311 #define ANEG_STATE_DISABLE_LINK_OK      4
3312 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3313 #define ANEG_STATE_ABILITY_DETECT       6
3314 #define ANEG_STATE_ACK_DETECT_INIT      7
3315 #define ANEG_STATE_ACK_DETECT           8
3316 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3317 #define ANEG_STATE_COMPLETE_ACK         10
3318 #define ANEG_STATE_IDLE_DETECT_INIT     11
3319 #define ANEG_STATE_IDLE_DETECT          12
3320 #define ANEG_STATE_LINK_OK              13
3321 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3322 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3323
3324         u32 flags;
3325 #define MR_AN_ENABLE            0x00000001
3326 #define MR_RESTART_AN           0x00000002
3327 #define MR_AN_COMPLETE          0x00000004
3328 #define MR_PAGE_RX              0x00000008
3329 #define MR_NP_LOADED            0x00000010
3330 #define MR_TOGGLE_TX            0x00000020
3331 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3332 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3333 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3334 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3335 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3336 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3337 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3338 #define MR_TOGGLE_RX            0x00002000
3339 #define MR_NP_RX                0x00004000
3340
3341 #define MR_LINK_OK              0x80000000
3342
3343         unsigned long link_time, cur_time;
3344
3345         u32 ability_match_cfg;
3346         int ability_match_count;
3347
3348         char ability_match, idle_match, ack_match;
3349
3350         u32 txconfig, rxconfig;
3351 #define ANEG_CFG_NP             0x00000080
3352 #define ANEG_CFG_ACK            0x00000040
3353 #define ANEG_CFG_RF2            0x00000020
3354 #define ANEG_CFG_RF1            0x00000010
3355 #define ANEG_CFG_PS2            0x00000001
3356 #define ANEG_CFG_PS1            0x00008000
3357 #define ANEG_CFG_HD             0x00004000
3358 #define ANEG_CFG_FD             0x00002000
3359 #define ANEG_CFG_INVAL          0x00001f06
3360
3361 };
3362 #define ANEG_OK         0
3363 #define ANEG_DONE       1
3364 #define ANEG_TIMER_ENAB 2
3365 #define ANEG_FAILED     -1
3366
3367 #define ANEG_STATE_SETTLE_TIME  10000
3368
3369 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3370                                    struct tg3_fiber_aneginfo *ap)
3371 {
3372         u16 flowctrl;
3373         unsigned long delta;
3374         u32 rx_cfg_reg;
3375         int ret;
3376
3377         if (ap->state == ANEG_STATE_UNKNOWN) {
3378                 ap->rxconfig = 0;
3379                 ap->link_time = 0;
3380                 ap->cur_time = 0;
3381                 ap->ability_match_cfg = 0;
3382                 ap->ability_match_count = 0;
3383                 ap->ability_match = 0;
3384                 ap->idle_match = 0;
3385                 ap->ack_match = 0;
3386         }
3387         ap->cur_time++;
3388
3389         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3390                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3391
3392                 if (rx_cfg_reg != ap->ability_match_cfg) {
3393                         ap->ability_match_cfg = rx_cfg_reg;
3394                         ap->ability_match = 0;
3395                         ap->ability_match_count = 0;
3396                 } else {
3397                         if (++ap->ability_match_count > 1) {
3398                                 ap->ability_match = 1;
3399                                 ap->ability_match_cfg = rx_cfg_reg;
3400                         }
3401                 }
3402                 if (rx_cfg_reg & ANEG_CFG_ACK)
3403                         ap->ack_match = 1;
3404                 else
3405                         ap->ack_match = 0;
3406
3407                 ap->idle_match = 0;
3408         } else {
3409                 ap->idle_match = 1;
3410                 ap->ability_match_cfg = 0;
3411                 ap->ability_match_count = 0;
3412                 ap->ability_match = 0;
3413                 ap->ack_match = 0;
3414
3415                 rx_cfg_reg = 0;
3416         }
3417
3418         ap->rxconfig = rx_cfg_reg;
3419         ret = ANEG_OK;
3420
3421         switch(ap->state) {
3422         case ANEG_STATE_UNKNOWN:
3423                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3424                         ap->state = ANEG_STATE_AN_ENABLE;
3425
3426                 /* fallthru */
3427         case ANEG_STATE_AN_ENABLE:
3428                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3429                 if (ap->flags & MR_AN_ENABLE) {
3430                         ap->link_time = 0;
3431                         ap->cur_time = 0;
3432                         ap->ability_match_cfg = 0;
3433                         ap->ability_match_count = 0;
3434                         ap->ability_match = 0;
3435                         ap->idle_match = 0;
3436                         ap->ack_match = 0;
3437
3438                         ap->state = ANEG_STATE_RESTART_INIT;
3439                 } else {
3440                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3441                 }
3442                 break;
3443
3444         case ANEG_STATE_RESTART_INIT:
3445                 ap->link_time = ap->cur_time;
3446                 ap->flags &= ~(MR_NP_LOADED);
3447                 ap->txconfig = 0;
3448                 tw32(MAC_TX_AUTO_NEG, 0);
3449                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3450                 tw32_f(MAC_MODE, tp->mac_mode);
3451                 udelay(40);
3452
3453                 ret = ANEG_TIMER_ENAB;
3454                 ap->state = ANEG_STATE_RESTART;
3455
3456                 /* fallthru */
3457         case ANEG_STATE_RESTART:
3458                 delta = ap->cur_time - ap->link_time;
3459                 if (delta > ANEG_STATE_SETTLE_TIME) {
3460                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3461                 } else {
3462                         ret = ANEG_TIMER_ENAB;
3463                 }
3464                 break;
3465
3466         case ANEG_STATE_DISABLE_LINK_OK:
3467                 ret = ANEG_DONE;
3468                 break;
3469
3470         case ANEG_STATE_ABILITY_DETECT_INIT:
3471                 ap->flags &= ~(MR_TOGGLE_TX);
3472                 ap->txconfig = ANEG_CFG_FD;
3473                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3474                 if (flowctrl & ADVERTISE_1000XPAUSE)
3475                         ap->txconfig |= ANEG_CFG_PS1;
3476                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3477                         ap->txconfig |= ANEG_CFG_PS2;
3478                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3479                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3480                 tw32_f(MAC_MODE, tp->mac_mode);
3481                 udelay(40);
3482
3483                 ap->state = ANEG_STATE_ABILITY_DETECT;
3484                 break;
3485
3486         case ANEG_STATE_ABILITY_DETECT:
3487                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3488                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3489                 }
3490                 break;
3491
3492         case ANEG_STATE_ACK_DETECT_INIT:
3493                 ap->txconfig |= ANEG_CFG_ACK;
3494                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3495                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3496                 tw32_f(MAC_MODE, tp->mac_mode);
3497                 udelay(40);
3498
3499                 ap->state = ANEG_STATE_ACK_DETECT;
3500
3501                 /* fallthru */
3502         case ANEG_STATE_ACK_DETECT:
3503                 if (ap->ack_match != 0) {
3504                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3505                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3506                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3507                         } else {
3508                                 ap->state = ANEG_STATE_AN_ENABLE;
3509                         }
3510                 } else if (ap->ability_match != 0 &&
3511                            ap->rxconfig == 0) {
3512                         ap->state = ANEG_STATE_AN_ENABLE;
3513                 }
3514                 break;
3515
3516         case ANEG_STATE_COMPLETE_ACK_INIT:
3517                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3518                         ret = ANEG_FAILED;
3519                         break;
3520                 }
3521                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3522                                MR_LP_ADV_HALF_DUPLEX |
3523                                MR_LP_ADV_SYM_PAUSE |
3524                                MR_LP_ADV_ASYM_PAUSE |
3525                                MR_LP_ADV_REMOTE_FAULT1 |
3526                                MR_LP_ADV_REMOTE_FAULT2 |
3527                                MR_LP_ADV_NEXT_PAGE |
3528                                MR_TOGGLE_RX |
3529                                MR_NP_RX);
3530                 if (ap->rxconfig & ANEG_CFG_FD)
3531                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3532                 if (ap->rxconfig & ANEG_CFG_HD)
3533                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3534                 if (ap->rxconfig & ANEG_CFG_PS1)
3535                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3536                 if (ap->rxconfig & ANEG_CFG_PS2)
3537                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3538                 if (ap->rxconfig & ANEG_CFG_RF1)
3539                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3540                 if (ap->rxconfig & ANEG_CFG_RF2)
3541                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3542                 if (ap->rxconfig & ANEG_CFG_NP)
3543                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3544
3545                 ap->link_time = ap->cur_time;
3546
3547                 ap->flags ^= (MR_TOGGLE_TX);
3548                 if (ap->rxconfig & 0x0008)
3549                         ap->flags |= MR_TOGGLE_RX;
3550                 if (ap->rxconfig & ANEG_CFG_NP)
3551                         ap->flags |= MR_NP_RX;
3552                 ap->flags |= MR_PAGE_RX;
3553
3554                 ap->state = ANEG_STATE_COMPLETE_ACK;
3555                 ret = ANEG_TIMER_ENAB;
3556                 break;
3557
3558         case ANEG_STATE_COMPLETE_ACK:
3559                 if (ap->ability_match != 0 &&
3560                     ap->rxconfig == 0) {
3561                         ap->state = ANEG_STATE_AN_ENABLE;
3562                         break;
3563                 }
3564                 delta = ap->cur_time - ap->link_time;
3565                 if (delta > ANEG_STATE_SETTLE_TIME) {
3566                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3567                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3568                         } else {
3569                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3570                                     !(ap->flags & MR_NP_RX)) {
3571                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3572                                 } else {
3573                                         ret = ANEG_FAILED;
3574                                 }
3575                         }
3576                 }
3577                 break;
3578
3579         case ANEG_STATE_IDLE_DETECT_INIT:
3580                 ap->link_time = ap->cur_time;
3581                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3582                 tw32_f(MAC_MODE, tp->mac_mode);
3583                 udelay(40);
3584
3585                 ap->state = ANEG_STATE_IDLE_DETECT;
3586                 ret = ANEG_TIMER_ENAB;
3587                 break;
3588
3589         case ANEG_STATE_IDLE_DETECT:
3590                 if (ap->ability_match != 0 &&
3591                     ap->rxconfig == 0) {
3592                         ap->state = ANEG_STATE_AN_ENABLE;
3593                         break;
3594                 }
3595                 delta = ap->cur_time - ap->link_time;
3596                 if (delta > ANEG_STATE_SETTLE_TIME) {
3597                         /* XXX another gem from the Broadcom driver :( */
3598                         ap->state = ANEG_STATE_LINK_OK;
3599                 }
3600                 break;
3601
3602         case ANEG_STATE_LINK_OK:
3603                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3604                 ret = ANEG_DONE;
3605                 break;
3606
3607         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3608                 /* ??? unimplemented */
3609                 break;
3610
3611         case ANEG_STATE_NEXT_PAGE_WAIT:
3612                 /* ??? unimplemented */
3613                 break;
3614
3615         default:
3616                 ret = ANEG_FAILED;
3617                 break;
3618         }
3619
3620         return ret;
3621 }
3622
3623 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3624 {
3625         int res = 0;
3626         struct tg3_fiber_aneginfo aninfo;
3627         int status = ANEG_FAILED;
3628         unsigned int tick;
3629         u32 tmp;
3630
3631         tw32_f(MAC_TX_AUTO_NEG, 0);
3632
3633         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3634         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3635         udelay(40);
3636
3637         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3638         udelay(40);
3639
3640         memset(&aninfo, 0, sizeof(aninfo));
3641         aninfo.flags |= MR_AN_ENABLE;
3642         aninfo.state = ANEG_STATE_UNKNOWN;
3643         aninfo.cur_time = 0;
3644         tick = 0;
3645         while (++tick < 195000) {
3646                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3647                 if (status == ANEG_DONE || status == ANEG_FAILED)
3648                         break;
3649
3650                 udelay(1);
3651         }
3652
3653         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3654         tw32_f(MAC_MODE, tp->mac_mode);
3655         udelay(40);
3656
3657         *txflags = aninfo.txconfig;
3658         *rxflags = aninfo.flags;
3659
3660         if (status == ANEG_DONE &&
3661             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3662                              MR_LP_ADV_FULL_DUPLEX)))
3663                 res = 1;
3664
3665         return res;
3666 }
3667
3668 static void tg3_init_bcm8002(struct tg3 *tp)
3669 {
3670         u32 mac_status = tr32(MAC_STATUS);
3671         int i;
3672
3673         /* Reset when initting first time or we have a link. */
3674         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3675             !(mac_status & MAC_STATUS_PCS_SYNCED))
3676                 return;
3677
3678         /* Set PLL lock range. */
3679         tg3_writephy(tp, 0x16, 0x8007);
3680
3681         /* SW reset */
3682         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3683
3684         /* Wait for reset to complete. */
3685         /* XXX schedule_timeout() ... */
3686         for (i = 0; i < 500; i++)
3687                 udelay(10);
3688
3689         /* Config mode; select PMA/Ch 1 regs. */
3690         tg3_writephy(tp, 0x10, 0x8411);
3691
3692         /* Enable auto-lock and comdet, select txclk for tx. */
3693         tg3_writephy(tp, 0x11, 0x0a10);
3694
3695         tg3_writephy(tp, 0x18, 0x00a0);
3696         tg3_writephy(tp, 0x16, 0x41ff);
3697
3698         /* Assert and deassert POR. */
3699         tg3_writephy(tp, 0x13, 0x0400);
3700         udelay(40);
3701         tg3_writephy(tp, 0x13, 0x0000);
3702
3703         tg3_writephy(tp, 0x11, 0x0a50);
3704         udelay(40);
3705         tg3_writephy(tp, 0x11, 0x0a10);
3706
3707         /* Wait for signal to stabilize */
3708         /* XXX schedule_timeout() ... */
3709         for (i = 0; i < 15000; i++)
3710                 udelay(10);
3711
3712         /* Deselect the channel register so we can read the PHYID
3713          * later.
3714          */
3715         tg3_writephy(tp, 0x10, 0x8011);
3716 }
3717
3718 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3719 {
3720         u16 flowctrl;
3721         u32 sg_dig_ctrl, sg_dig_status;
3722         u32 serdes_cfg, expected_sg_dig_ctrl;
3723         int workaround, port_a;
3724         int current_link_up;
3725
3726         serdes_cfg = 0;
3727         expected_sg_dig_ctrl = 0;
3728         workaround = 0;
3729         port_a = 1;
3730         current_link_up = 0;
3731
3732         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3733             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3734                 workaround = 1;
3735                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3736                         port_a = 0;
3737
3738                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3739                 /* preserve bits 20-23 for voltage regulator */
3740                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3741         }
3742
3743         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3744
3745         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3746                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3747                         if (workaround) {
3748                                 u32 val = serdes_cfg;
3749
3750                                 if (port_a)
3751                                         val |= 0xc010000;
3752                                 else
3753                                         val |= 0x4010000;
3754                                 tw32_f(MAC_SERDES_CFG, val);
3755                         }
3756
3757                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3758                 }
3759                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3760                         tg3_setup_flow_control(tp, 0, 0);
3761                         current_link_up = 1;
3762                 }
3763                 goto out;
3764         }
3765
3766         /* Want auto-negotiation.  */
3767         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3768
3769         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3770         if (flowctrl & ADVERTISE_1000XPAUSE)
3771                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3772         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3773                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3774
3775         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3776                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3777                     tp->serdes_counter &&
3778                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3779                                     MAC_STATUS_RCVD_CFG)) ==
3780                      MAC_STATUS_PCS_SYNCED)) {
3781                         tp->serdes_counter--;
3782                         current_link_up = 1;
3783                         goto out;
3784                 }
3785 restart_autoneg:
3786                 if (workaround)
3787                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3788                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3789                 udelay(5);
3790                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3791
3792                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3793                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3794         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3795                                  MAC_STATUS_SIGNAL_DET)) {
3796                 sg_dig_status = tr32(SG_DIG_STATUS);
3797                 mac_status = tr32(MAC_STATUS);
3798
3799                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3800                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3801                         u32 local_adv = 0, remote_adv = 0;
3802
3803                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3804                                 local_adv |= ADVERTISE_1000XPAUSE;
3805                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3806                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3807
3808                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3809                                 remote_adv |= LPA_1000XPAUSE;
3810                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3811                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3812
3813                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3814                         current_link_up = 1;
3815                         tp->serdes_counter = 0;
3816                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3817                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3818                         if (tp->serdes_counter)
3819                                 tp->serdes_counter--;
3820                         else {
3821                                 if (workaround) {
3822                                         u32 val = serdes_cfg;
3823
3824                                         if (port_a)
3825                                                 val |= 0xc010000;
3826                                         else
3827                                                 val |= 0x4010000;
3828
3829                                         tw32_f(MAC_SERDES_CFG, val);
3830                                 }
3831
3832                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3833                                 udelay(40);
3834
3835                                 /* Link parallel detection - link is up */
3836                                 /* only if we have PCS_SYNC and not */
3837                                 /* receiving config code words */
3838                                 mac_status = tr32(MAC_STATUS);
3839                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3840                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3841                                         tg3_setup_flow_control(tp, 0, 0);
3842                                         current_link_up = 1;
3843                                         tp->tg3_flags2 |=
3844                                                 TG3_FLG2_PARALLEL_DETECT;
3845                                         tp->serdes_counter =
3846                                                 SERDES_PARALLEL_DET_TIMEOUT;
3847                                 } else
3848                                         goto restart_autoneg;
3849                         }
3850                 }
3851         } else {
3852                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3853                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3854         }
3855
3856 out:
3857         return current_link_up;
3858 }
3859
3860 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3861 {
3862         int current_link_up = 0;
3863
3864         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3865                 goto out;
3866
3867         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3868                 u32 txflags, rxflags;
3869                 int i;
3870
3871                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3872                         u32 local_adv = 0, remote_adv = 0;
3873
3874                         if (txflags & ANEG_CFG_PS1)
3875                                 local_adv |= ADVERTISE_1000XPAUSE;
3876                         if (txflags & ANEG_CFG_PS2)
3877                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3878
3879                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3880                                 remote_adv |= LPA_1000XPAUSE;
3881                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3882                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3883
3884                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3885
3886                         current_link_up = 1;
3887                 }
3888                 for (i = 0; i < 30; i++) {
3889                         udelay(20);
3890                         tw32_f(MAC_STATUS,
3891                                (MAC_STATUS_SYNC_CHANGED |
3892                                 MAC_STATUS_CFG_CHANGED));
3893                         udelay(40);
3894                         if ((tr32(MAC_STATUS) &
3895                              (MAC_STATUS_SYNC_CHANGED |
3896                               MAC_STATUS_CFG_CHANGED)) == 0)
3897                                 break;
3898                 }
3899
3900                 mac_status = tr32(MAC_STATUS);
3901                 if (current_link_up == 0 &&
3902                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3903                     !(mac_status & MAC_STATUS_RCVD_CFG))
3904                         current_link_up = 1;
3905         } else {
3906                 tg3_setup_flow_control(tp, 0, 0);
3907
3908                 /* Forcing 1000FD link up. */
3909                 current_link_up = 1;
3910
3911                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3912                 udelay(40);
3913
3914                 tw32_f(MAC_MODE, tp->mac_mode);
3915                 udelay(40);
3916         }
3917
3918 out:
3919         return current_link_up;
3920 }
3921
3922 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3923 {
3924         u32 orig_pause_cfg;
3925         u16 orig_active_speed;
3926         u8 orig_active_duplex;
3927         u32 mac_status;
3928         int current_link_up;
3929         int i;
3930
3931         orig_pause_cfg = tp->link_config.active_flowctrl;
3932         orig_active_speed = tp->link_config.active_speed;
3933         orig_active_duplex = tp->link_config.active_duplex;
3934
3935         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3936             netif_carrier_ok(tp->dev) &&
3937             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3938                 mac_status = tr32(MAC_STATUS);
3939                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3940                                MAC_STATUS_SIGNAL_DET |
3941                                MAC_STATUS_CFG_CHANGED |
3942                                MAC_STATUS_RCVD_CFG);
3943                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3944                                    MAC_STATUS_SIGNAL_DET)) {
3945                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3946                                             MAC_STATUS_CFG_CHANGED));
3947                         return 0;
3948                 }
3949         }
3950
3951         tw32_f(MAC_TX_AUTO_NEG, 0);
3952
3953         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3954         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3955         tw32_f(MAC_MODE, tp->mac_mode);
3956         udelay(40);
3957
3958         if (tp->phy_id == PHY_ID_BCM8002)
3959                 tg3_init_bcm8002(tp);
3960
3961         /* Enable link change event even when serdes polling.  */
3962         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3963         udelay(40);
3964
3965         current_link_up = 0;
3966         mac_status = tr32(MAC_STATUS);
3967
3968         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3969                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3970         else
3971                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3972
3973         tp->napi[0].hw_status->status =
3974                 (SD_STATUS_UPDATED |
3975                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3976
3977         for (i = 0; i < 100; i++) {
3978                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3979                                     MAC_STATUS_CFG_CHANGED));
3980                 udelay(5);
3981                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3982                                          MAC_STATUS_CFG_CHANGED |
3983                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3984                         break;
3985         }
3986
3987         mac_status = tr32(MAC_STATUS);
3988         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3989                 current_link_up = 0;
3990                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3991                     tp->serdes_counter == 0) {
3992                         tw32_f(MAC_MODE, (tp->mac_mode |
3993                                           MAC_MODE_SEND_CONFIGS));
3994                         udelay(1);
3995                         tw32_f(MAC_MODE, tp->mac_mode);
3996                 }
3997         }
3998
3999         if (current_link_up == 1) {
4000                 tp->link_config.active_speed = SPEED_1000;
4001                 tp->link_config.active_duplex = DUPLEX_FULL;
4002                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4003                                     LED_CTRL_LNKLED_OVERRIDE |
4004                                     LED_CTRL_1000MBPS_ON));
4005         } else {
4006                 tp->link_config.active_speed = SPEED_INVALID;
4007                 tp->link_config.active_duplex = DUPLEX_INVALID;
4008                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4009                                     LED_CTRL_LNKLED_OVERRIDE |
4010                                     LED_CTRL_TRAFFIC_OVERRIDE));
4011         }
4012
4013         if (current_link_up != netif_carrier_ok(tp->dev)) {
4014                 if (current_link_up)
4015                         netif_carrier_on(tp->dev);
4016                 else
4017                         netif_carrier_off(tp->dev);
4018                 tg3_link_report(tp);
4019         } else {
4020                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4021                 if (orig_pause_cfg != now_pause_cfg ||
4022                     orig_active_speed != tp->link_config.active_speed ||
4023                     orig_active_duplex != tp->link_config.active_duplex)
4024                         tg3_link_report(tp);
4025         }
4026
4027         return 0;
4028 }
4029
4030 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4031 {
4032         int current_link_up, err = 0;
4033         u32 bmsr, bmcr;
4034         u16 current_speed;
4035         u8 current_duplex;
4036         u32 local_adv, remote_adv;
4037
4038         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4039         tw32_f(MAC_MODE, tp->mac_mode);
4040         udelay(40);
4041
4042         tw32(MAC_EVENT, 0);
4043
4044         tw32_f(MAC_STATUS,
4045              (MAC_STATUS_SYNC_CHANGED |
4046               MAC_STATUS_CFG_CHANGED |
4047               MAC_STATUS_MI_COMPLETION |
4048               MAC_STATUS_LNKSTATE_CHANGED));
4049         udelay(40);
4050
4051         if (force_reset)
4052                 tg3_phy_reset(tp);
4053
4054         current_link_up = 0;
4055         current_speed = SPEED_INVALID;
4056         current_duplex = DUPLEX_INVALID;
4057
4058         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4059         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4060         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4061                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4062                         bmsr |= BMSR_LSTATUS;
4063                 else
4064                         bmsr &= ~BMSR_LSTATUS;
4065         }
4066
4067         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4068
4069         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4070             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4071                 /* do nothing, just check for link up at the end */
4072         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4073                 u32 adv, new_adv;
4074
4075                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4076                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4077                                   ADVERTISE_1000XPAUSE |
4078                                   ADVERTISE_1000XPSE_ASYM |
4079                                   ADVERTISE_SLCT);
4080
4081                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4082
4083                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4084                         new_adv |= ADVERTISE_1000XHALF;
4085                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4086                         new_adv |= ADVERTISE_1000XFULL;
4087
4088                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4089                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4090                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4091                         tg3_writephy(tp, MII_BMCR, bmcr);
4092
4093                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4094                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4095                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4096
4097                         return err;
4098                 }
4099         } else {
4100                 u32 new_bmcr;
4101
4102                 bmcr &= ~BMCR_SPEED1000;
4103                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4104
4105                 if (tp->link_config.duplex == DUPLEX_FULL)
4106                         new_bmcr |= BMCR_FULLDPLX;
4107
4108                 if (new_bmcr != bmcr) {
4109                         /* BMCR_SPEED1000 is a reserved bit that needs
4110                          * to be set on write.
4111                          */
4112                         new_bmcr |= BMCR_SPEED1000;
4113
4114                         /* Force a linkdown */
4115                         if (netif_carrier_ok(tp->dev)) {
4116                                 u32 adv;
4117
4118                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4119                                 adv &= ~(ADVERTISE_1000XFULL |
4120                                          ADVERTISE_1000XHALF |
4121                                          ADVERTISE_SLCT);
4122                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4123                                 tg3_writephy(tp, MII_BMCR, bmcr |
4124                                                            BMCR_ANRESTART |
4125                                                            BMCR_ANENABLE);
4126                                 udelay(10);
4127                                 netif_carrier_off(tp->dev);
4128                         }
4129                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4130                         bmcr = new_bmcr;
4131                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4132                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4133                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4134                             ASIC_REV_5714) {
4135                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4136                                         bmsr |= BMSR_LSTATUS;
4137                                 else
4138                                         bmsr &= ~BMSR_LSTATUS;
4139                         }
4140                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4141                 }
4142         }
4143
4144         if (bmsr & BMSR_LSTATUS) {
4145                 current_speed = SPEED_1000;
4146                 current_link_up = 1;
4147                 if (bmcr & BMCR_FULLDPLX)
4148                         current_duplex = DUPLEX_FULL;
4149                 else
4150                         current_duplex = DUPLEX_HALF;
4151
4152                 local_adv = 0;
4153                 remote_adv = 0;
4154
4155                 if (bmcr & BMCR_ANENABLE) {
4156                         u32 common;
4157
4158                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4159                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4160                         common = local_adv & remote_adv;
4161                         if (common & (ADVERTISE_1000XHALF |
4162                                       ADVERTISE_1000XFULL)) {
4163                                 if (common & ADVERTISE_1000XFULL)
4164                                         current_duplex = DUPLEX_FULL;
4165                                 else
4166                                         current_duplex = DUPLEX_HALF;
4167                         }
4168                         else
4169                                 current_link_up = 0;
4170                 }
4171         }
4172
4173         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4174                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4175
4176         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4177         if (tp->link_config.active_duplex == DUPLEX_HALF)
4178                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4179
4180         tw32_f(MAC_MODE, tp->mac_mode);
4181         udelay(40);
4182
4183         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4184
4185         tp->link_config.active_speed = current_speed;
4186         tp->link_config.active_duplex = current_duplex;
4187
4188         if (current_link_up != netif_carrier_ok(tp->dev)) {
4189                 if (current_link_up)
4190                         netif_carrier_on(tp->dev);
4191                 else {
4192                         netif_carrier_off(tp->dev);
4193                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4194                 }
4195                 tg3_link_report(tp);
4196         }
4197         return err;
4198 }
4199
4200 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4201 {
4202         if (tp->serdes_counter) {
4203                 /* Give autoneg time to complete. */
4204                 tp->serdes_counter--;
4205                 return;
4206         }
4207         if (!netif_carrier_ok(tp->dev) &&
4208             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4209                 u32 bmcr;
4210
4211                 tg3_readphy(tp, MII_BMCR, &bmcr);
4212                 if (bmcr & BMCR_ANENABLE) {
4213                         u32 phy1, phy2;
4214
4215                         /* Select shadow register 0x1f */
4216                         tg3_writephy(tp, 0x1c, 0x7c00);
4217                         tg3_readphy(tp, 0x1c, &phy1);
4218
4219                         /* Select expansion interrupt status register */
4220                         tg3_writephy(tp, 0x17, 0x0f01);
4221                         tg3_readphy(tp, 0x15, &phy2);
4222                         tg3_readphy(tp, 0x15, &phy2);
4223
4224                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4225                                 /* We have signal detect and not receiving
4226                                  * config code words, link is up by parallel
4227                                  * detection.
4228                                  */
4229
4230                                 bmcr &= ~BMCR_ANENABLE;
4231                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4232                                 tg3_writephy(tp, MII_BMCR, bmcr);
4233                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4234                         }
4235                 }
4236         }
4237         else if (netif_carrier_ok(tp->dev) &&
4238                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4239                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4240                 u32 phy2;
4241
4242                 /* Select expansion interrupt status register */
4243                 tg3_writephy(tp, 0x17, 0x0f01);
4244                 tg3_readphy(tp, 0x15, &phy2);
4245                 if (phy2 & 0x20) {
4246                         u32 bmcr;
4247
4248                         /* Config code words received, turn on autoneg. */
4249                         tg3_readphy(tp, MII_BMCR, &bmcr);
4250                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4251
4252                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4253
4254                 }
4255         }
4256 }
4257
4258 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4259 {
4260         int err;
4261
4262         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4263                 err = tg3_setup_fiber_phy(tp, force_reset);
4264         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4265                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4266         } else {
4267                 err = tg3_setup_copper_phy(tp, force_reset);
4268         }
4269
4270         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4271                 u32 val, scale;
4272
4273                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4274                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4275                         scale = 65;
4276                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4277                         scale = 6;
4278                 else
4279                         scale = 12;
4280
4281                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4282                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4283                 tw32(GRC_MISC_CFG, val);
4284         }
4285
4286         if (tp->link_config.active_speed == SPEED_1000 &&
4287             tp->link_config.active_duplex == DUPLEX_HALF)
4288                 tw32(MAC_TX_LENGTHS,
4289                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4290                       (6 << TX_LENGTHS_IPG_SHIFT) |
4291                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4292         else
4293                 tw32(MAC_TX_LENGTHS,
4294                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4295                       (6 << TX_LENGTHS_IPG_SHIFT) |
4296                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4297
4298         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4299                 if (netif_carrier_ok(tp->dev)) {
4300                         tw32(HOSTCC_STAT_COAL_TICKS,
4301                              tp->coal.stats_block_coalesce_usecs);
4302                 } else {
4303                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4304                 }
4305         }
4306
4307         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4308                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4309                 if (!netif_carrier_ok(tp->dev))
4310                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4311                               tp->pwrmgmt_thresh;
4312                 else
4313                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4314                 tw32(PCIE_PWR_MGMT_THRESH, val);
4315         }
4316
4317         return err;
4318 }
4319
4320 /* This is called whenever we suspect that the system chipset is re-
4321  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4322  * is bogus tx completions. We try to recover by setting the
4323  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4324  * in the workqueue.
4325  */
4326 static void tg3_tx_recover(struct tg3 *tp)
4327 {
4328         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4329                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4330
4331         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4332                "mapped I/O cycles to the network device, attempting to "
4333                "recover. Please report the problem to the driver maintainer "
4334                "and include system chipset information.\n", tp->dev->name);
4335
4336         spin_lock(&tp->lock);
4337         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4338         spin_unlock(&tp->lock);
4339 }
4340
4341 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4342 {
4343         smp_mb();
4344         return tnapi->tx_pending -
4345                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4346 }
4347
4348 /* Tigon3 never reports partial packet sends.  So we do not
4349  * need special logic to handle SKBs that have not had all
4350  * of their frags sent yet, like SunGEM does.
4351  */
4352 static void tg3_tx(struct tg3_napi *tnapi)
4353 {
4354         struct tg3 *tp = tnapi->tp;
4355         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4356         u32 sw_idx = tnapi->tx_cons;
4357         struct netdev_queue *txq;
4358         int index = tnapi - tp->napi;
4359
4360         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4361                 index--;
4362
4363         txq = netdev_get_tx_queue(tp->dev, index);
4364
4365         while (sw_idx != hw_idx) {
4366                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4367                 struct sk_buff *skb = ri->skb;
4368                 int i, tx_bug = 0;
4369
4370                 if (unlikely(skb == NULL)) {
4371                         tg3_tx_recover(tp);
4372                         return;
4373                 }
4374
4375                 pci_unmap_single(tp->pdev,
4376                                  pci_unmap_addr(ri, mapping),
4377                                  skb_headlen(skb),
4378                                  PCI_DMA_TODEVICE);
4379
4380                 ri->skb = NULL;
4381
4382                 sw_idx = NEXT_TX(sw_idx);
4383
4384                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4385                         ri = &tnapi->tx_buffers[sw_idx];
4386                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4387                                 tx_bug = 1;
4388
4389                         pci_unmap_page(tp->pdev,
4390                                        pci_unmap_addr(ri, mapping),
4391                                        skb_shinfo(skb)->frags[i].size,
4392                                        PCI_DMA_TODEVICE);
4393                         sw_idx = NEXT_TX(sw_idx);
4394                 }
4395
4396                 dev_kfree_skb(skb);
4397
4398                 if (unlikely(tx_bug)) {
4399                         tg3_tx_recover(tp);
4400                         return;
4401                 }
4402         }
4403
4404         tnapi->tx_cons = sw_idx;
4405
4406         /* Need to make the tx_cons update visible to tg3_start_xmit()
4407          * before checking for netif_queue_stopped().  Without the
4408          * memory barrier, there is a small possibility that tg3_start_xmit()
4409          * will miss it and cause the queue to be stopped forever.
4410          */
4411         smp_mb();
4412
4413         if (unlikely(netif_tx_queue_stopped(txq) &&
4414                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4415                 __netif_tx_lock(txq, smp_processor_id());
4416                 if (netif_tx_queue_stopped(txq) &&
4417                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4418                         netif_tx_wake_queue(txq);
4419                 __netif_tx_unlock(txq);
4420         }
4421 }
4422
4423 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4424 {
4425         if (!ri->skb)
4426                 return;
4427
4428         pci_unmap_single(tp->pdev, pci_unmap_addr(ri, mapping),
4429                          map_sz, PCI_DMA_FROMDEVICE);
4430         dev_kfree_skb_any(ri->skb);
4431         ri->skb = NULL;
4432 }
4433
4434 /* Returns size of skb allocated or < 0 on error.
4435  *
4436  * We only need to fill in the address because the other members
4437  * of the RX descriptor are invariant, see tg3_init_rings.
4438  *
4439  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4440  * posting buffers we only dirty the first cache line of the RX
4441  * descriptor (containing the address).  Whereas for the RX status
4442  * buffers the cpu only reads the last cacheline of the RX descriptor
4443  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4444  */
4445 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4446                             u32 opaque_key, u32 dest_idx_unmasked)
4447 {
4448         struct tg3_rx_buffer_desc *desc;
4449         struct ring_info *map, *src_map;
4450         struct sk_buff *skb;
4451         dma_addr_t mapping;
4452         int skb_size, dest_idx;
4453
4454         src_map = NULL;
4455         switch (opaque_key) {
4456         case RXD_OPAQUE_RING_STD:
4457                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4458                 desc = &tpr->rx_std[dest_idx];
4459                 map = &tpr->rx_std_buffers[dest_idx];
4460                 skb_size = tp->rx_pkt_map_sz;
4461                 break;
4462
4463         case RXD_OPAQUE_RING_JUMBO:
4464                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4465                 desc = &tpr->rx_jmb[dest_idx].std;
4466                 map = &tpr->rx_jmb_buffers[dest_idx];
4467                 skb_size = TG3_RX_JMB_MAP_SZ;
4468                 break;
4469
4470         default:
4471                 return -EINVAL;
4472         }
4473
4474         /* Do not overwrite any of the map or rp information
4475          * until we are sure we can commit to a new buffer.
4476          *
4477          * Callers depend upon this behavior and assume that
4478          * we leave everything unchanged if we fail.
4479          */
4480         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4481         if (skb == NULL)
4482                 return -ENOMEM;
4483
4484         skb_reserve(skb, tp->rx_offset);
4485
4486         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4487                                  PCI_DMA_FROMDEVICE);
4488         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4489                 dev_kfree_skb(skb);
4490                 return -EIO;
4491         }
4492
4493         map->skb = skb;
4494         pci_unmap_addr_set(map, mapping, mapping);
4495
4496         desc->addr_hi = ((u64)mapping >> 32);
4497         desc->addr_lo = ((u64)mapping & 0xffffffff);
4498
4499         return skb_size;
4500 }
4501
4502 /* We only need to move over in the address because the other
4503  * members of the RX descriptor are invariant.  See notes above
4504  * tg3_alloc_rx_skb for full details.
4505  */
4506 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4507                            struct tg3_rx_prodring_set *dpr,
4508                            u32 opaque_key, int src_idx,
4509                            u32 dest_idx_unmasked)
4510 {
4511         struct tg3 *tp = tnapi->tp;
4512         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4513         struct ring_info *src_map, *dest_map;
4514         int dest_idx;
4515         struct tg3_rx_prodring_set *spr = &tp->prodring[0];
4516
4517         switch (opaque_key) {
4518         case RXD_OPAQUE_RING_STD:
4519                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4520                 dest_desc = &dpr->rx_std[dest_idx];
4521                 dest_map = &dpr->rx_std_buffers[dest_idx];
4522                 src_desc = &spr->rx_std[src_idx];
4523                 src_map = &spr->rx_std_buffers[src_idx];
4524                 break;
4525
4526         case RXD_OPAQUE_RING_JUMBO:
4527                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4528                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4529                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4530                 src_desc = &spr->rx_jmb[src_idx].std;
4531                 src_map = &spr->rx_jmb_buffers[src_idx];
4532                 break;
4533
4534         default:
4535                 return;
4536         }
4537
4538         dest_map->skb = src_map->skb;
4539         pci_unmap_addr_set(dest_map, mapping,
4540                            pci_unmap_addr(src_map, mapping));
4541         dest_desc->addr_hi = src_desc->addr_hi;
4542         dest_desc->addr_lo = src_desc->addr_lo;
4543         src_map->skb = NULL;
4544 }
4545
4546 /* The RX ring scheme is composed of multiple rings which post fresh
4547  * buffers to the chip, and one special ring the chip uses to report
4548  * status back to the host.
4549  *
4550  * The special ring reports the status of received packets to the
4551  * host.  The chip does not write into the original descriptor the
4552  * RX buffer was obtained from.  The chip simply takes the original
4553  * descriptor as provided by the host, updates the status and length
4554  * field, then writes this into the next status ring entry.
4555  *
4556  * Each ring the host uses to post buffers to the chip is described
4557  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4558  * it is first placed into the on-chip ram.  When the packet's length
4559  * is known, it walks down the TG3_BDINFO entries to select the ring.
4560  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4561  * which is within the range of the new packet's length is chosen.
4562  *
4563  * The "separate ring for rx status" scheme may sound queer, but it makes
4564  * sense from a cache coherency perspective.  If only the host writes
4565  * to the buffer post rings, and only the chip writes to the rx status
4566  * rings, then cache lines never move beyond shared-modified state.
4567  * If both the host and chip were to write into the same ring, cache line
4568  * eviction could occur since both entities want it in an exclusive state.
4569  */
4570 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4571 {
4572         struct tg3 *tp = tnapi->tp;
4573         u32 work_mask, rx_std_posted = 0;
4574         u32 std_prod_idx, jmb_prod_idx;
4575         u32 sw_idx = tnapi->rx_rcb_ptr;
4576         u16 hw_idx;
4577         int received;
4578         struct tg3_rx_prodring_set *tpr = tnapi->prodring;
4579
4580         hw_idx = *(tnapi->rx_rcb_prod_idx);
4581         /*
4582          * We need to order the read of hw_idx and the read of
4583          * the opaque cookie.
4584          */
4585         rmb();
4586         work_mask = 0;
4587         received = 0;
4588         std_prod_idx = tpr->rx_std_prod_idx;
4589         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4590         while (sw_idx != hw_idx && budget > 0) {
4591                 struct ring_info *ri;
4592                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4593                 unsigned int len;
4594                 struct sk_buff *skb;
4595                 dma_addr_t dma_addr;
4596                 u32 opaque_key, desc_idx, *post_ptr;
4597
4598                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4599                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4600                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4601                         ri = &tp->prodring[0].rx_std_buffers[desc_idx];
4602                         dma_addr = pci_unmap_addr(ri, mapping);
4603                         skb = ri->skb;
4604                         post_ptr = &std_prod_idx;
4605                         rx_std_posted++;
4606                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4607                         ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
4608                         dma_addr = pci_unmap_addr(ri, mapping);
4609                         skb = ri->skb;
4610                         post_ptr = &jmb_prod_idx;
4611                 } else
4612                         goto next_pkt_nopost;
4613
4614                 work_mask |= opaque_key;
4615
4616                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4617                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4618                 drop_it:
4619                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4620                                        desc_idx, *post_ptr);
4621                 drop_it_no_recycle:
4622                         /* Other statistics kept track of by card. */
4623                         tp->net_stats.rx_dropped++;
4624                         goto next_pkt;
4625                 }
4626
4627                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4628                       ETH_FCS_LEN;
4629
4630                 if (len > RX_COPY_THRESHOLD &&
4631                     tp->rx_offset == NET_IP_ALIGN) {
4632                     /* rx_offset will likely not equal NET_IP_ALIGN
4633                      * if this is a 5701 card running in PCI-X mode
4634                      * [see tg3_get_invariants()]
4635                      */
4636                         int skb_size;
4637
4638                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4639                                                     *post_ptr);
4640                         if (skb_size < 0)
4641                                 goto drop_it;
4642
4643                         ri->skb = NULL;
4644
4645                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4646                                          PCI_DMA_FROMDEVICE);
4647
4648                         skb_put(skb, len);
4649                 } else {
4650                         struct sk_buff *copy_skb;
4651
4652                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4653                                        desc_idx, *post_ptr);
4654
4655                         copy_skb = netdev_alloc_skb(tp->dev,
4656                                                     len + TG3_RAW_IP_ALIGN);
4657                         if (copy_skb == NULL)
4658                                 goto drop_it_no_recycle;
4659
4660                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4661                         skb_put(copy_skb, len);
4662                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4663                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4664                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4665
4666                         /* We'll reuse the original ring buffer. */
4667                         skb = copy_skb;
4668                 }
4669
4670                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4671                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4672                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4673                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4674                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4675                 else
4676                         skb->ip_summed = CHECKSUM_NONE;
4677
4678                 skb->protocol = eth_type_trans(skb, tp->dev);
4679
4680                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4681                     skb->protocol != htons(ETH_P_8021Q)) {
4682                         dev_kfree_skb(skb);
4683                         goto next_pkt;
4684                 }
4685
4686 #if TG3_VLAN_TAG_USED
4687                 if (tp->vlgrp != NULL &&
4688                     desc->type_flags & RXD_FLAG_VLAN) {
4689                         vlan_gro_receive(&tnapi->napi, tp->vlgrp,
4690                                          desc->err_vlan & RXD_VLAN_MASK, skb);
4691                 } else
4692 #endif
4693                         napi_gro_receive(&tnapi->napi, skb);
4694
4695                 received++;
4696                 budget--;
4697
4698 next_pkt:
4699                 (*post_ptr)++;
4700
4701                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4702                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4703                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, idx);
4704                         work_mask &= ~RXD_OPAQUE_RING_STD;
4705                         rx_std_posted = 0;
4706                 }
4707 next_pkt_nopost:
4708                 sw_idx++;
4709                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4710
4711                 /* Refresh hw_idx to see if there is new work */
4712                 if (sw_idx == hw_idx) {
4713                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4714                         rmb();
4715                 }
4716         }
4717
4718         /* ACK the status ring. */
4719         tnapi->rx_rcb_ptr = sw_idx;
4720         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4721
4722         /* Refill RX ring(s). */
4723         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) || tnapi == &tp->napi[1]) {
4724                 if (work_mask & RXD_OPAQUE_RING_STD) {
4725                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4726                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4727                                      tpr->rx_std_prod_idx);
4728                 }
4729                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4730                         tpr->rx_jmb_prod_idx = jmb_prod_idx %
4731                                                TG3_RX_JUMBO_RING_SIZE;
4732                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4733                                      tpr->rx_jmb_prod_idx);
4734                 }
4735                 mmiowb();
4736         } else if (work_mask) {
4737                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4738                  * updated before the producer indices can be updated.
4739                  */
4740                 smp_wmb();
4741
4742                 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4743                 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4744
4745                 napi_schedule(&tp->napi[1].napi);
4746         }
4747
4748         return received;
4749 }
4750
4751 static void tg3_poll_link(struct tg3 *tp)
4752 {
4753         /* handle link change and other phy events */
4754         if (!(tp->tg3_flags &
4755               (TG3_FLAG_USE_LINKCHG_REG |
4756                TG3_FLAG_POLL_SERDES))) {
4757                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4758
4759                 if (sblk->status & SD_STATUS_LINK_CHG) {
4760                         sblk->status = SD_STATUS_UPDATED |
4761                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4762                         spin_lock(&tp->lock);
4763                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4764                                 tw32_f(MAC_STATUS,
4765                                      (MAC_STATUS_SYNC_CHANGED |
4766                                       MAC_STATUS_CFG_CHANGED |
4767                                       MAC_STATUS_MI_COMPLETION |
4768                                       MAC_STATUS_LNKSTATE_CHANGED));
4769                                 udelay(40);
4770                         } else
4771                                 tg3_setup_phy(tp, 0);
4772                         spin_unlock(&tp->lock);
4773                 }
4774         }
4775 }
4776
4777 static void tg3_rx_prodring_xfer(struct tg3 *tp,
4778                                  struct tg3_rx_prodring_set *dpr,
4779                                  struct tg3_rx_prodring_set *spr)
4780 {
4781         u32 si, di, cpycnt, src_prod_idx;
4782         int i;
4783
4784         while (1) {
4785                 src_prod_idx = spr->rx_std_prod_idx;
4786
4787                 /* Make sure updates to the rx_std_buffers[] entries and the
4788                  * standard producer index are seen in the correct order.
4789                  */
4790                 smp_rmb();
4791
4792                 if (spr->rx_std_cons_idx == src_prod_idx)
4793                         break;
4794
4795                 if (spr->rx_std_cons_idx < src_prod_idx)
4796                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4797                 else
4798                         cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4799
4800                 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4801
4802                 si = spr->rx_std_cons_idx;
4803                 di = dpr->rx_std_prod_idx;
4804
4805                 memcpy(&dpr->rx_std_buffers[di],
4806                        &spr->rx_std_buffers[si],
4807                        cpycnt * sizeof(struct ring_info));
4808
4809                 for (i = 0; i < cpycnt; i++, di++, si++) {
4810                         struct tg3_rx_buffer_desc *sbd, *dbd;
4811                         sbd = &spr->rx_std[si];
4812                         dbd = &dpr->rx_std[di];
4813                         dbd->addr_hi = sbd->addr_hi;
4814                         dbd->addr_lo = sbd->addr_lo;
4815                 }
4816
4817                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4818                                        TG3_RX_RING_SIZE;
4819                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4820                                        TG3_RX_RING_SIZE;
4821         }
4822
4823         while (1) {
4824                 src_prod_idx = spr->rx_jmb_prod_idx;
4825
4826                 /* Make sure updates to the rx_jmb_buffers[] entries and
4827                  * the jumbo producer index are seen in the correct order.
4828                  */
4829                 smp_rmb();
4830
4831                 if (spr->rx_jmb_cons_idx == src_prod_idx)
4832                         break;
4833
4834                 if (spr->rx_jmb_cons_idx < src_prod_idx)
4835                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4836                 else
4837                         cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4838
4839                 cpycnt = min(cpycnt,
4840                              TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4841
4842                 si = spr->rx_jmb_cons_idx;
4843                 di = dpr->rx_jmb_prod_idx;
4844
4845                 memcpy(&dpr->rx_jmb_buffers[di],
4846                        &spr->rx_jmb_buffers[si],
4847                        cpycnt * sizeof(struct ring_info));
4848
4849                 for (i = 0; i < cpycnt; i++, di++, si++) {
4850                         struct tg3_rx_buffer_desc *sbd, *dbd;
4851                         sbd = &spr->rx_jmb[si].std;
4852                         dbd = &dpr->rx_jmb[di].std;
4853                         dbd->addr_hi = sbd->addr_hi;
4854                         dbd->addr_lo = sbd->addr_lo;
4855                 }
4856
4857                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4858                                        TG3_RX_JUMBO_RING_SIZE;
4859                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4860                                        TG3_RX_JUMBO_RING_SIZE;
4861         }
4862 }
4863
4864 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4865 {
4866         struct tg3 *tp = tnapi->tp;
4867
4868         /* run TX completion thread */
4869         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4870                 tg3_tx(tnapi);
4871                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4872                         return work_done;
4873         }
4874
4875         /* run RX thread, within the bounds set by NAPI.
4876          * All RX "locking" is done by ensuring outside
4877          * code synchronizes with tg3->napi.poll()
4878          */
4879         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4880                 work_done += tg3_rx(tnapi, budget - work_done);
4881
4882         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4883                 int i;
4884                 u32 std_prod_idx = tp->prodring[0].rx_std_prod_idx;
4885                 u32 jmb_prod_idx = tp->prodring[0].rx_jmb_prod_idx;
4886
4887                 for (i = 2; i < tp->irq_cnt; i++)
4888                         tg3_rx_prodring_xfer(tp, tnapi->prodring,
4889                                              tp->napi[i].prodring);
4890
4891                 wmb();
4892
4893                 if (std_prod_idx != tp->prodring[0].rx_std_prod_idx) {
4894                         u32 mbox = TG3_RX_STD_PROD_IDX_REG;
4895                         tw32_rx_mbox(mbox, tp->prodring[0].rx_std_prod_idx);
4896                 }
4897
4898                 if (jmb_prod_idx != tp->prodring[0].rx_jmb_prod_idx) {
4899                         u32 mbox = TG3_RX_JMB_PROD_IDX_REG;
4900                         tw32_rx_mbox(mbox, tp->prodring[0].rx_jmb_prod_idx);
4901                 }
4902
4903                 mmiowb();
4904         }
4905
4906         return work_done;
4907 }
4908
4909 static int tg3_poll_msix(struct napi_struct *napi, int budget)
4910 {
4911         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4912         struct tg3 *tp = tnapi->tp;
4913         int work_done = 0;
4914         struct tg3_hw_status *sblk = tnapi->hw_status;
4915
4916         while (1) {
4917                 work_done = tg3_poll_work(tnapi, work_done, budget);
4918
4919                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4920                         goto tx_recovery;
4921
4922                 if (unlikely(work_done >= budget))
4923                         break;
4924
4925                 /* tp->last_tag is used in tg3_restart_ints() below
4926                  * to tell the hw how much work has been processed,
4927                  * so we must read it before checking for more work.
4928                  */
4929                 tnapi->last_tag = sblk->status_tag;
4930                 tnapi->last_irq_tag = tnapi->last_tag;
4931                 rmb();
4932
4933                 /* check for RX/TX work to do */
4934                 if (sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4935                     *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr) {
4936                         napi_complete(napi);
4937                         /* Reenable interrupts. */
4938                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
4939                         mmiowb();
4940                         break;
4941                 }
4942         }
4943
4944         return work_done;
4945
4946 tx_recovery:
4947         /* work_done is guaranteed to be less than budget. */
4948         napi_complete(napi);
4949         schedule_work(&tp->reset_task);
4950         return work_done;
4951 }
4952
4953 static int tg3_poll(struct napi_struct *napi, int budget)
4954 {
4955         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4956         struct tg3 *tp = tnapi->tp;
4957         int work_done = 0;
4958         struct tg3_hw_status *sblk = tnapi->hw_status;
4959
4960         while (1) {
4961                 tg3_poll_link(tp);
4962
4963                 work_done = tg3_poll_work(tnapi, work_done, budget);
4964
4965                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4966                         goto tx_recovery;
4967
4968                 if (unlikely(work_done >= budget))
4969                         break;
4970
4971                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4972                         /* tp->last_tag is used in tg3_int_reenable() below
4973                          * to tell the hw how much work has been processed,
4974                          * so we must read it before checking for more work.
4975                          */
4976                         tnapi->last_tag = sblk->status_tag;
4977                         tnapi->last_irq_tag = tnapi->last_tag;
4978                         rmb();
4979                 } else
4980                         sblk->status &= ~SD_STATUS_UPDATED;
4981
4982                 if (likely(!tg3_has_work(tnapi))) {
4983                         napi_complete(napi);
4984                         tg3_int_reenable(tnapi);
4985                         break;
4986                 }
4987         }
4988
4989         return work_done;
4990
4991 tx_recovery:
4992         /* work_done is guaranteed to be less than budget. */
4993         napi_complete(napi);
4994         schedule_work(&tp->reset_task);
4995         return work_done;
4996 }
4997
4998 static void tg3_irq_quiesce(struct tg3 *tp)
4999 {
5000         int i;
5001
5002         BUG_ON(tp->irq_sync);
5003
5004         tp->irq_sync = 1;
5005         smp_mb();
5006
5007         for (i = 0; i < tp->irq_cnt; i++)
5008                 synchronize_irq(tp->napi[i].irq_vec);
5009 }
5010
5011 static inline int tg3_irq_sync(struct tg3 *tp)
5012 {
5013         return tp->irq_sync;
5014 }
5015
5016 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5017  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5018  * with as well.  Most of the time, this is not necessary except when
5019  * shutting down the device.
5020  */
5021 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5022 {
5023         spin_lock_bh(&tp->lock);
5024         if (irq_sync)
5025                 tg3_irq_quiesce(tp);
5026 }
5027
5028 static inline void tg3_full_unlock(struct tg3 *tp)
5029 {
5030         spin_unlock_bh(&tp->lock);
5031 }
5032
5033 /* One-shot MSI handler - Chip automatically disables interrupt
5034  * after sending MSI so driver doesn't have to do it.
5035  */
5036 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5037 {
5038         struct tg3_napi *tnapi = dev_id;
5039         struct tg3 *tp = tnapi->tp;
5040
5041         prefetch(tnapi->hw_status);
5042         if (tnapi->rx_rcb)
5043                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5044
5045         if (likely(!tg3_irq_sync(tp)))
5046                 napi_schedule(&tnapi->napi);
5047
5048         return IRQ_HANDLED;
5049 }
5050
5051 /* MSI ISR - No need to check for interrupt sharing and no need to
5052  * flush status block and interrupt mailbox. PCI ordering rules
5053  * guarantee that MSI will arrive after the status block.
5054  */
5055 static irqreturn_t tg3_msi(int irq, void *dev_id)
5056 {
5057         struct tg3_napi *tnapi = dev_id;
5058         struct tg3 *tp = tnapi->tp;
5059
5060         prefetch(tnapi->hw_status);
5061         if (tnapi->rx_rcb)
5062                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5063         /*
5064          * Writing any value to intr-mbox-0 clears PCI INTA# and
5065          * chip-internal interrupt pending events.
5066          * Writing non-zero to intr-mbox-0 additional tells the
5067          * NIC to stop sending us irqs, engaging "in-intr-handler"
5068          * event coalescing.
5069          */
5070         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5071         if (likely(!tg3_irq_sync(tp)))
5072                 napi_schedule(&tnapi->napi);
5073
5074         return IRQ_RETVAL(1);
5075 }
5076
5077 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5078 {
5079         struct tg3_napi *tnapi = dev_id;
5080         struct tg3 *tp = tnapi->tp;
5081         struct tg3_hw_status *sblk = tnapi->hw_status;
5082         unsigned int handled = 1;
5083
5084         /* In INTx mode, it is possible for the interrupt to arrive at
5085          * the CPU before the status block posted prior to the interrupt.
5086          * Reading the PCI State register will confirm whether the
5087          * interrupt is ours and will flush the status block.
5088          */
5089         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5090                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5091                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5092                         handled = 0;
5093                         goto out;
5094                 }
5095         }
5096
5097         /*
5098          * Writing any value to intr-mbox-0 clears PCI INTA# and
5099          * chip-internal interrupt pending events.
5100          * Writing non-zero to intr-mbox-0 additional tells the
5101          * NIC to stop sending us irqs, engaging "in-intr-handler"
5102          * event coalescing.
5103          *
5104          * Flush the mailbox to de-assert the IRQ immediately to prevent
5105          * spurious interrupts.  The flush impacts performance but
5106          * excessive spurious interrupts can be worse in some cases.
5107          */
5108         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5109         if (tg3_irq_sync(tp))
5110                 goto out;
5111         sblk->status &= ~SD_STATUS_UPDATED;
5112         if (likely(tg3_has_work(tnapi))) {
5113                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5114                 napi_schedule(&tnapi->napi);
5115         } else {
5116                 /* No work, shared interrupt perhaps?  re-enable
5117                  * interrupts, and flush that PCI write
5118                  */
5119                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5120                                0x00000000);
5121         }
5122 out:
5123         return IRQ_RETVAL(handled);
5124 }
5125
5126 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5127 {
5128         struct tg3_napi *tnapi = dev_id;
5129         struct tg3 *tp = tnapi->tp;
5130         struct tg3_hw_status *sblk = tnapi->hw_status;
5131         unsigned int handled = 1;
5132
5133         /* In INTx mode, it is possible for the interrupt to arrive at
5134          * the CPU before the status block posted prior to the interrupt.
5135          * Reading the PCI State register will confirm whether the
5136          * interrupt is ours and will flush the status block.
5137          */
5138         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5139                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5140                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5141                         handled = 0;
5142                         goto out;
5143                 }
5144         }
5145
5146         /*
5147          * writing any value to intr-mbox-0 clears PCI INTA# and
5148          * chip-internal interrupt pending events.
5149          * writing non-zero to intr-mbox-0 additional tells the
5150          * NIC to stop sending us irqs, engaging "in-intr-handler"
5151          * event coalescing.
5152          *
5153          * Flush the mailbox to de-assert the IRQ immediately to prevent
5154          * spurious interrupts.  The flush impacts performance but
5155          * excessive spurious interrupts can be worse in some cases.
5156          */
5157         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5158
5159         /*
5160          * In a shared interrupt configuration, sometimes other devices'
5161          * interrupts will scream.  We record the current status tag here
5162          * so that the above check can report that the screaming interrupts
5163          * are unhandled.  Eventually they will be silenced.
5164          */
5165         tnapi->last_irq_tag = sblk->status_tag;
5166
5167         if (tg3_irq_sync(tp))
5168                 goto out;
5169
5170         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5171
5172         napi_schedule(&tnapi->napi);
5173
5174 out:
5175         return IRQ_RETVAL(handled);
5176 }
5177
5178 /* ISR for interrupt test */
5179 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5180 {
5181         struct tg3_napi *tnapi = dev_id;
5182         struct tg3 *tp = tnapi->tp;
5183         struct tg3_hw_status *sblk = tnapi->hw_status;
5184
5185         if ((sblk->status & SD_STATUS_UPDATED) ||
5186             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5187                 tg3_disable_ints(tp);
5188                 return IRQ_RETVAL(1);
5189         }
5190         return IRQ_RETVAL(0);
5191 }
5192
5193 static int tg3_init_hw(struct tg3 *, int);
5194 static int tg3_halt(struct tg3 *, int, int);
5195
5196 /* Restart hardware after configuration changes, self-test, etc.
5197  * Invoked with tp->lock held.
5198  */
5199 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5200         __releases(tp->lock)
5201         __acquires(tp->lock)
5202 {
5203         int err;
5204
5205         err = tg3_init_hw(tp, reset_phy);
5206         if (err) {
5207                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
5208                        "aborting.\n", tp->dev->name);
5209                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5210                 tg3_full_unlock(tp);
5211                 del_timer_sync(&tp->timer);
5212                 tp->irq_sync = 0;
5213                 tg3_napi_enable(tp);
5214                 dev_close(tp->dev);
5215                 tg3_full_lock(tp, 0);
5216         }
5217         return err;
5218 }
5219
5220 #ifdef CONFIG_NET_POLL_CONTROLLER
5221 static void tg3_poll_controller(struct net_device *dev)
5222 {
5223         int i;
5224         struct tg3 *tp = netdev_priv(dev);
5225
5226         for (i = 0; i < tp->irq_cnt; i++)
5227                 tg3_interrupt(tp->napi[i].irq_vec, dev);
5228 }
5229 #endif
5230
5231 static void tg3_reset_task(struct work_struct *work)
5232 {
5233         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5234         int err;
5235         unsigned int restart_timer;
5236
5237         tg3_full_lock(tp, 0);
5238
5239         if (!netif_running(tp->dev)) {
5240                 tg3_full_unlock(tp);
5241                 return;
5242         }
5243
5244         tg3_full_unlock(tp);
5245
5246         tg3_phy_stop(tp);
5247
5248         tg3_netif_stop(tp);
5249
5250         tg3_full_lock(tp, 1);
5251
5252         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5253         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5254
5255         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5256                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5257                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5258                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5259                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5260         }
5261
5262         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5263         err = tg3_init_hw(tp, 1);
5264         if (err)
5265                 goto out;
5266
5267         tg3_netif_start(tp);
5268
5269         if (restart_timer)
5270                 mod_timer(&tp->timer, jiffies + 1);
5271
5272 out:
5273         tg3_full_unlock(tp);
5274
5275         if (!err)
5276                 tg3_phy_start(tp);
5277 }
5278
5279 static void tg3_dump_short_state(struct tg3 *tp)
5280 {
5281         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5282                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5283         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5284                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5285 }
5286
5287 static void tg3_tx_timeout(struct net_device *dev)
5288 {
5289         struct tg3 *tp = netdev_priv(dev);
5290
5291         if (netif_msg_tx_err(tp)) {
5292                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5293                        dev->name);
5294                 tg3_dump_short_state(tp);
5295         }
5296
5297         schedule_work(&tp->reset_task);
5298 }
5299
5300 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5301 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5302 {
5303         u32 base = (u32) mapping & 0xffffffff;
5304
5305         return ((base > 0xffffdcc0) &&
5306                 (base + len + 8 < base));
5307 }
5308
5309 /* Test for DMA addresses > 40-bit */
5310 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5311                                           int len)
5312 {
5313 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5314         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5315                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5316         return 0;
5317 #else
5318         return 0;
5319 #endif
5320 }
5321
5322 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5323
5324 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5325 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5326                                        struct sk_buff *skb, u32 last_plus_one,
5327                                        u32 *start, u32 base_flags, u32 mss)
5328 {
5329         struct tg3 *tp = tnapi->tp;
5330         struct sk_buff *new_skb;
5331         dma_addr_t new_addr = 0;
5332         u32 entry = *start;
5333         int i, ret = 0;
5334
5335         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5336                 new_skb = skb_copy(skb, GFP_ATOMIC);
5337         else {
5338                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5339
5340                 new_skb = skb_copy_expand(skb,
5341                                           skb_headroom(skb) + more_headroom,
5342                                           skb_tailroom(skb), GFP_ATOMIC);
5343         }
5344
5345         if (!new_skb) {
5346                 ret = -1;
5347         } else {
5348                 /* New SKB is guaranteed to be linear. */
5349                 entry = *start;
5350                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5351                                           PCI_DMA_TODEVICE);
5352                 /* Make sure the mapping succeeded */
5353                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5354                         ret = -1;
5355                         dev_kfree_skb(new_skb);
5356                         new_skb = NULL;
5357
5358                 /* Make sure new skb does not cross any 4G boundaries.
5359                  * Drop the packet if it does.
5360                  */
5361                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5362                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5363                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5364                                          PCI_DMA_TODEVICE);
5365                         ret = -1;
5366                         dev_kfree_skb(new_skb);
5367                         new_skb = NULL;
5368                 } else {
5369                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5370                                     base_flags, 1 | (mss << 1));
5371                         *start = NEXT_TX(entry);
5372                 }
5373         }
5374
5375         /* Now clean up the sw ring entries. */
5376         i = 0;
5377         while (entry != last_plus_one) {
5378                 int len;
5379
5380                 if (i == 0)
5381                         len = skb_headlen(skb);
5382                 else
5383                         len = skb_shinfo(skb)->frags[i-1].size;
5384
5385                 pci_unmap_single(tp->pdev,
5386                                  pci_unmap_addr(&tnapi->tx_buffers[entry],
5387                                                 mapping),
5388                                  len, PCI_DMA_TODEVICE);
5389                 if (i == 0) {
5390                         tnapi->tx_buffers[entry].skb = new_skb;
5391                         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5392                                            new_addr);
5393                 } else {
5394                         tnapi->tx_buffers[entry].skb = NULL;
5395                 }
5396                 entry = NEXT_TX(entry);
5397                 i++;
5398         }
5399
5400         dev_kfree_skb(skb);
5401
5402         return ret;
5403 }
5404
5405 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5406                         dma_addr_t mapping, int len, u32 flags,
5407                         u32 mss_and_is_end)
5408 {
5409         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5410         int is_end = (mss_and_is_end & 0x1);
5411         u32 mss = (mss_and_is_end >> 1);
5412         u32 vlan_tag = 0;
5413
5414         if (is_end)
5415                 flags |= TXD_FLAG_END;
5416         if (flags & TXD_FLAG_VLAN) {
5417                 vlan_tag = flags >> 16;
5418                 flags &= 0xffff;
5419         }
5420         vlan_tag |= (mss << TXD_MSS_SHIFT);
5421
5422         txd->addr_hi = ((u64) mapping >> 32);
5423         txd->addr_lo = ((u64) mapping & 0xffffffff);
5424         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5425         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5426 }
5427
5428 /* hard_start_xmit for devices that don't have any bugs and
5429  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5430  */
5431 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5432                                   struct net_device *dev)
5433 {
5434         struct tg3 *tp = netdev_priv(dev);
5435         u32 len, entry, base_flags, mss;
5436         dma_addr_t mapping;
5437         struct tg3_napi *tnapi;
5438         struct netdev_queue *txq;
5439         unsigned int i, last;
5440
5441
5442         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5443         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5444         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5445                 tnapi++;
5446
5447         /* We are running in BH disabled context with netif_tx_lock
5448          * and TX reclaim runs via tp->napi.poll inside of a software
5449          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5450          * no IRQ context deadlocks to worry about either.  Rejoice!
5451          */
5452         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5453                 if (!netif_tx_queue_stopped(txq)) {
5454                         netif_tx_stop_queue(txq);
5455
5456                         /* This is a hard error, log it. */
5457                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5458                                "queue awake!\n", dev->name);
5459                 }
5460                 return NETDEV_TX_BUSY;
5461         }
5462
5463         entry = tnapi->tx_prod;
5464         base_flags = 0;
5465         mss = 0;
5466         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5467                 int tcp_opt_len, ip_tcp_len;
5468                 u32 hdrlen;
5469
5470                 if (skb_header_cloned(skb) &&
5471                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5472                         dev_kfree_skb(skb);
5473                         goto out_unlock;
5474                 }
5475
5476                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5477                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5478                 else {
5479                         struct iphdr *iph = ip_hdr(skb);
5480
5481                         tcp_opt_len = tcp_optlen(skb);
5482                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5483
5484                         iph->check = 0;
5485                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5486                         hdrlen = ip_tcp_len + tcp_opt_len;
5487                 }
5488
5489                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5490                         mss |= (hdrlen & 0xc) << 12;
5491                         if (hdrlen & 0x10)
5492                                 base_flags |= 0x00000010;
5493                         base_flags |= (hdrlen & 0x3e0) << 5;
5494                 } else
5495                         mss |= hdrlen << 9;
5496
5497                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5498                                TXD_FLAG_CPU_POST_DMA);
5499
5500                 tcp_hdr(skb)->check = 0;
5501
5502         }
5503         else if (skb->ip_summed == CHECKSUM_PARTIAL)
5504                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5505 #if TG3_VLAN_TAG_USED
5506         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5507                 base_flags |= (TXD_FLAG_VLAN |
5508                                (vlan_tx_tag_get(skb) << 16));
5509 #endif
5510
5511         len = skb_headlen(skb);
5512
5513         /* Queue skb data, a.k.a. the main skb fragment. */
5514         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5515         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5516                 dev_kfree_skb(skb);
5517                 goto out_unlock;
5518         }
5519
5520         tnapi->tx_buffers[entry].skb = skb;
5521         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5522
5523         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5524             !mss && skb->len > ETH_DATA_LEN)
5525                 base_flags |= TXD_FLAG_JMB_PKT;
5526
5527         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5528                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5529
5530         entry = NEXT_TX(entry);
5531
5532         /* Now loop through additional data fragments, and queue them. */
5533         if (skb_shinfo(skb)->nr_frags > 0) {
5534                 last = skb_shinfo(skb)->nr_frags - 1;
5535                 for (i = 0; i <= last; i++) {
5536                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5537
5538                         len = frag->size;
5539                         mapping = pci_map_page(tp->pdev,
5540                                                frag->page,
5541                                                frag->page_offset,
5542                                                len, PCI_DMA_TODEVICE);
5543                         if (pci_dma_mapping_error(tp->pdev, mapping))
5544                                 goto dma_error;
5545
5546                         tnapi->tx_buffers[entry].skb = NULL;
5547                         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5548                                            mapping);
5549
5550                         tg3_set_txd(tnapi, entry, mapping, len,
5551                                     base_flags, (i == last) | (mss << 1));
5552
5553                         entry = NEXT_TX(entry);
5554                 }
5555         }
5556
5557         /* Packets are ready, update Tx producer idx local and on card. */
5558         tw32_tx_mbox(tnapi->prodmbox, entry);
5559
5560         tnapi->tx_prod = entry;
5561         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5562                 netif_tx_stop_queue(txq);
5563                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5564                         netif_tx_wake_queue(txq);
5565         }
5566
5567 out_unlock:
5568         mmiowb();
5569
5570         return NETDEV_TX_OK;
5571
5572 dma_error:
5573         last = i;
5574         entry = tnapi->tx_prod;
5575         tnapi->tx_buffers[entry].skb = NULL;
5576         pci_unmap_single(tp->pdev,
5577                          pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5578                          skb_headlen(skb),
5579                          PCI_DMA_TODEVICE);
5580         for (i = 0; i <= last; i++) {
5581                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5582                 entry = NEXT_TX(entry);
5583
5584                 pci_unmap_page(tp->pdev,
5585                                pci_unmap_addr(&tnapi->tx_buffers[entry],
5586                                               mapping),
5587                                frag->size, PCI_DMA_TODEVICE);
5588         }
5589
5590         dev_kfree_skb(skb);
5591         return NETDEV_TX_OK;
5592 }
5593
5594 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5595                                           struct net_device *);
5596
5597 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5598  * TSO header is greater than 80 bytes.
5599  */
5600 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5601 {
5602         struct sk_buff *segs, *nskb;
5603         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5604
5605         /* Estimate the number of fragments in the worst case */
5606         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5607                 netif_stop_queue(tp->dev);
5608                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5609                         return NETDEV_TX_BUSY;
5610
5611                 netif_wake_queue(tp->dev);
5612         }
5613
5614         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5615         if (IS_ERR(segs))
5616                 goto tg3_tso_bug_end;
5617
5618         do {
5619                 nskb = segs;
5620                 segs = segs->next;
5621                 nskb->next = NULL;
5622                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5623         } while (segs);
5624
5625 tg3_tso_bug_end:
5626         dev_kfree_skb(skb);
5627
5628         return NETDEV_TX_OK;
5629 }
5630
5631 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5632  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5633  */
5634 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5635                                           struct net_device *dev)
5636 {
5637         struct tg3 *tp = netdev_priv(dev);
5638         u32 len, entry, base_flags, mss;
5639         int would_hit_hwbug;
5640         dma_addr_t mapping;
5641         struct tg3_napi *tnapi;
5642         struct netdev_queue *txq;
5643         unsigned int i, last;
5644
5645
5646         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5647         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5648         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5649                 tnapi++;
5650
5651         /* We are running in BH disabled context with netif_tx_lock
5652          * and TX reclaim runs via tp->napi.poll inside of a software
5653          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5654          * no IRQ context deadlocks to worry about either.  Rejoice!
5655          */
5656         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5657                 if (!netif_tx_queue_stopped(txq)) {
5658                         netif_tx_stop_queue(txq);
5659
5660                         /* This is a hard error, log it. */
5661                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5662                                "queue awake!\n", dev->name);
5663                 }
5664                 return NETDEV_TX_BUSY;
5665         }
5666
5667         entry = tnapi->tx_prod;
5668         base_flags = 0;
5669         if (skb->ip_summed == CHECKSUM_PARTIAL)
5670                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5671
5672         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5673                 struct iphdr *iph;
5674                 u32 tcp_opt_len, ip_tcp_len, hdr_len;
5675
5676                 if (skb_header_cloned(skb) &&
5677                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5678                         dev_kfree_skb(skb);
5679                         goto out_unlock;
5680                 }
5681
5682                 tcp_opt_len = tcp_optlen(skb);
5683                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5684
5685                 hdr_len = ip_tcp_len + tcp_opt_len;
5686                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5687                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5688                         return (tg3_tso_bug(tp, skb));
5689
5690                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5691                                TXD_FLAG_CPU_POST_DMA);
5692
5693                 iph = ip_hdr(skb);
5694                 iph->check = 0;
5695                 iph->tot_len = htons(mss + hdr_len);
5696                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5697                         tcp_hdr(skb)->check = 0;
5698                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5699                 } else
5700                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5701                                                                  iph->daddr, 0,
5702                                                                  IPPROTO_TCP,
5703                                                                  0);
5704
5705                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5706                         mss |= (hdr_len & 0xc) << 12;
5707                         if (hdr_len & 0x10)
5708                                 base_flags |= 0x00000010;
5709                         base_flags |= (hdr_len & 0x3e0) << 5;
5710                 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5711                         mss |= hdr_len << 9;
5712                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5713                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5714                         if (tcp_opt_len || iph->ihl > 5) {
5715                                 int tsflags;
5716
5717                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5718                                 mss |= (tsflags << 11);
5719                         }
5720                 } else {
5721                         if (tcp_opt_len || iph->ihl > 5) {
5722                                 int tsflags;
5723
5724                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5725                                 base_flags |= tsflags << 12;
5726                         }
5727                 }
5728         }
5729 #if TG3_VLAN_TAG_USED
5730         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5731                 base_flags |= (TXD_FLAG_VLAN |
5732                                (vlan_tx_tag_get(skb) << 16));
5733 #endif
5734
5735         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5736             !mss && skb->len > ETH_DATA_LEN)
5737                 base_flags |= TXD_FLAG_JMB_PKT;
5738
5739         len = skb_headlen(skb);
5740
5741         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5742         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5743                 dev_kfree_skb(skb);
5744                 goto out_unlock;
5745         }
5746
5747         tnapi->tx_buffers[entry].skb = skb;
5748         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5749
5750         would_hit_hwbug = 0;
5751
5752      &nb