[SPARC]: module version cleanups
[linux-2.6.git] / drivers / net / sunbmac.c
1 /* $Id: sunbmac.c,v 1.30 2002/01/15 06:48:55 davem Exp $
2  * sunbmac.c: Driver for Sparc BigMAC 100baseT ethernet adapters.
3  *
4  * Copyright (C) 1997, 1998, 1999, 2003 David S. Miller (davem@redhat.com)
5  */
6
7 #include <linux/module.h>
8
9 #include <linux/kernel.h>
10 #include <linux/types.h>
11 #include <linux/fcntl.h>
12 #include <linux/interrupt.h>
13 #include <linux/ioport.h>
14 #include <linux/in.h>
15 #include <linux/slab.h>
16 #include <linux/string.h>
17 #include <linux/delay.h>
18 #include <linux/init.h>
19 #include <linux/crc32.h>
20 #include <linux/errno.h>
21 #include <linux/ethtool.h>
22 #include <linux/netdevice.h>
23 #include <linux/etherdevice.h>
24 #include <linux/skbuff.h>
25 #include <linux/bitops.h>
26
27 #include <asm/auxio.h>
28 #include <asm/byteorder.h>
29 #include <asm/dma.h>
30 #include <asm/idprom.h>
31 #include <asm/io.h>
32 #include <asm/openprom.h>
33 #include <asm/oplib.h>
34 #include <asm/pgtable.h>
35 #include <asm/sbus.h>
36 #include <asm/system.h>
37
38 #include "sunbmac.h"
39
40 #define DRV_NAME        "sunbmac"
41 #define DRV_VERSION     "2.0"
42 #define DRV_RELDATE     "11/24/03"
43 #define DRV_AUTHOR      "David S. Miller (davem@redhat.com)"
44
45 static char version[] __initdata =
46         DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
47
48 MODULE_VERSION(DRV_VERSION);
49 MODULE_AUTHOR(DRV_AUTHOR);
50 MODULE_DESCRIPTION("Sun BigMAC 100baseT ethernet driver");
51 MODULE_LICENSE("GPL");
52
53 #undef DEBUG_PROBE
54 #undef DEBUG_TX
55 #undef DEBUG_IRQ
56
57 #ifdef DEBUG_PROBE
58 #define DP(x)  printk x
59 #else
60 #define DP(x)
61 #endif
62
63 #ifdef DEBUG_TX
64 #define DTX(x)  printk x
65 #else
66 #define DTX(x)
67 #endif
68
69 #ifdef DEBUG_IRQ
70 #define DIRQ(x)  printk x
71 #else
72 #define DIRQ(x)
73 #endif
74
75 static struct bigmac *root_bigmac_dev;
76
77 #define DEFAULT_JAMSIZE    4 /* Toe jam */
78
79 #define QEC_RESET_TRIES 200
80
81 static int qec_global_reset(void __iomem *gregs)
82 {
83         int tries = QEC_RESET_TRIES;
84
85         sbus_writel(GLOB_CTRL_RESET, gregs + GLOB_CTRL);
86         while (--tries) {
87                 if (sbus_readl(gregs + GLOB_CTRL) & GLOB_CTRL_RESET) {
88                         udelay(20);
89                         continue;
90                 }
91                 break;
92         }
93         if (tries)
94                 return 0;
95         printk(KERN_ERR "BigMAC: Cannot reset the QEC.\n");
96         return -1;
97 }
98
99 static void qec_init(struct bigmac *bp)
100 {
101         void __iomem *gregs = bp->gregs;
102         struct sbus_dev *qec_sdev = bp->qec_sdev;
103         u8 bsizes = bp->bigmac_bursts;
104         u32 regval;
105
106         /* 64byte bursts do not work at the moment, do
107          * not even try to enable them.  -DaveM
108          */
109         if (bsizes & DMA_BURST32)
110                 regval = GLOB_CTRL_B32;
111         else
112                 regval = GLOB_CTRL_B16;
113         sbus_writel(regval | GLOB_CTRL_BMODE, gregs + GLOB_CTRL);
114         sbus_writel(GLOB_PSIZE_2048, gregs + GLOB_PSIZE);
115
116         /* All of memsize is given to bigmac. */
117         sbus_writel(qec_sdev->reg_addrs[1].reg_size,
118                     gregs + GLOB_MSIZE);
119
120         /* Half to the transmitter, half to the receiver. */
121         sbus_writel(qec_sdev->reg_addrs[1].reg_size >> 1,
122                     gregs + GLOB_TSIZE);
123         sbus_writel(qec_sdev->reg_addrs[1].reg_size >> 1,
124                     gregs + GLOB_RSIZE);
125 }
126
127 #define TX_RESET_TRIES     32
128 #define RX_RESET_TRIES     32
129
130 static void bigmac_tx_reset(void __iomem *bregs)
131 {
132         int tries = TX_RESET_TRIES;
133
134         sbus_writel(0, bregs + BMAC_TXCFG);
135
136         /* The fifo threshold bit is read-only and does
137          * not clear.  -DaveM
138          */
139         while ((sbus_readl(bregs + BMAC_TXCFG) & ~(BIGMAC_TXCFG_FIFO)) != 0 &&
140                --tries != 0)
141                 udelay(20);
142
143         if (!tries) {
144                 printk(KERN_ERR "BIGMAC: Transmitter will not reset.\n");
145                 printk(KERN_ERR "BIGMAC: tx_cfg is %08x\n",
146                        sbus_readl(bregs + BMAC_TXCFG));
147         }
148 }
149
150 static void bigmac_rx_reset(void __iomem *bregs)
151 {
152         int tries = RX_RESET_TRIES;
153
154         sbus_writel(0, bregs + BMAC_RXCFG);
155         while (sbus_readl(bregs + BMAC_RXCFG) && --tries)
156                 udelay(20);
157
158         if (!tries) {
159                 printk(KERN_ERR "BIGMAC: Receiver will not reset.\n");
160                 printk(KERN_ERR "BIGMAC: rx_cfg is %08x\n",
161                        sbus_readl(bregs + BMAC_RXCFG));
162         }
163 }
164
165 /* Reset the transmitter and receiver. */
166 static void bigmac_stop(struct bigmac *bp)
167 {
168         bigmac_tx_reset(bp->bregs);
169         bigmac_rx_reset(bp->bregs);
170 }
171
172 static void bigmac_get_counters(struct bigmac *bp, void __iomem *bregs)
173 {
174         struct net_device_stats *stats = &bp->enet_stats;
175
176         stats->rx_crc_errors += sbus_readl(bregs + BMAC_RCRCECTR);
177         sbus_writel(0, bregs + BMAC_RCRCECTR);
178
179         stats->rx_frame_errors += sbus_readl(bregs + BMAC_UNALECTR);
180         sbus_writel(0, bregs + BMAC_UNALECTR);
181
182         stats->rx_length_errors += sbus_readl(bregs + BMAC_GLECTR);
183         sbus_writel(0, bregs + BMAC_GLECTR);
184
185         stats->tx_aborted_errors += sbus_readl(bregs + BMAC_EXCTR);
186
187         stats->collisions +=
188                 (sbus_readl(bregs + BMAC_EXCTR) +
189                  sbus_readl(bregs + BMAC_LTCTR));
190         sbus_writel(0, bregs + BMAC_EXCTR);
191         sbus_writel(0, bregs + BMAC_LTCTR);
192 }
193
194 static void bigmac_clean_rings(struct bigmac *bp)
195 {
196         int i;
197
198         for (i = 0; i < RX_RING_SIZE; i++) {
199                 if (bp->rx_skbs[i] != NULL) {
200                         dev_kfree_skb_any(bp->rx_skbs[i]);
201                         bp->rx_skbs[i] = NULL;
202                 }
203         }
204
205         for (i = 0; i < TX_RING_SIZE; i++) {
206                 if (bp->tx_skbs[i] != NULL) {
207                         dev_kfree_skb_any(bp->tx_skbs[i]);
208                         bp->tx_skbs[i] = NULL;
209                 }
210         }
211 }
212
213 static void bigmac_init_rings(struct bigmac *bp, int from_irq)
214 {
215         struct bmac_init_block *bb = bp->bmac_block;
216         struct net_device *dev = bp->dev;
217         int i, gfp_flags = GFP_KERNEL;
218
219         if (from_irq || in_interrupt())
220                 gfp_flags = GFP_ATOMIC;
221
222         bp->rx_new = bp->rx_old = bp->tx_new = bp->tx_old = 0;
223
224         /* Free any skippy bufs left around in the rings. */
225         bigmac_clean_rings(bp);
226
227         /* Now get new skbufs for the receive ring. */
228         for (i = 0; i < RX_RING_SIZE; i++) {
229                 struct sk_buff *skb;
230
231                 skb = big_mac_alloc_skb(RX_BUF_ALLOC_SIZE, gfp_flags);
232                 if (!skb)
233                         continue;
234
235                 bp->rx_skbs[i] = skb;
236                 skb->dev = dev;
237
238                 /* Because we reserve afterwards. */
239                 skb_put(skb, ETH_FRAME_LEN);
240                 skb_reserve(skb, 34);
241
242                 bb->be_rxd[i].rx_addr =
243                         sbus_map_single(bp->bigmac_sdev, skb->data,
244                                         RX_BUF_ALLOC_SIZE - 34,
245                                         SBUS_DMA_FROMDEVICE);
246                 bb->be_rxd[i].rx_flags =
247                         (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH));
248         }
249
250         for (i = 0; i < TX_RING_SIZE; i++)
251                 bb->be_txd[i].tx_flags = bb->be_txd[i].tx_addr = 0;
252 }
253
254 #define MGMT_CLKON  (MGMT_PAL_INT_MDIO|MGMT_PAL_EXT_MDIO|MGMT_PAL_OENAB|MGMT_PAL_DCLOCK)
255 #define MGMT_CLKOFF (MGMT_PAL_INT_MDIO|MGMT_PAL_EXT_MDIO|MGMT_PAL_OENAB)
256
257 static void idle_transceiver(void __iomem *tregs)
258 {
259         int i = 20;
260
261         while (i--) {
262                 sbus_writel(MGMT_CLKOFF, tregs + TCVR_MPAL);
263                 sbus_readl(tregs + TCVR_MPAL);
264                 sbus_writel(MGMT_CLKON, tregs + TCVR_MPAL);
265                 sbus_readl(tregs + TCVR_MPAL);
266         }
267 }
268
269 static void write_tcvr_bit(struct bigmac *bp, void __iomem *tregs, int bit)
270 {
271         if (bp->tcvr_type == internal) {
272                 bit = (bit & 1) << 3;
273                 sbus_writel(bit | (MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO),
274                             tregs + TCVR_MPAL);
275                 sbus_readl(tregs + TCVR_MPAL);
276                 sbus_writel(bit | MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK,
277                             tregs + TCVR_MPAL);
278                 sbus_readl(tregs + TCVR_MPAL);
279         } else if (bp->tcvr_type == external) {
280                 bit = (bit & 1) << 2;
281                 sbus_writel(bit | MGMT_PAL_INT_MDIO | MGMT_PAL_OENAB,
282                             tregs + TCVR_MPAL);
283                 sbus_readl(tregs + TCVR_MPAL);
284                 sbus_writel(bit | MGMT_PAL_INT_MDIO | MGMT_PAL_OENAB | MGMT_PAL_DCLOCK,
285                             tregs + TCVR_MPAL);
286                 sbus_readl(tregs + TCVR_MPAL);
287         } else {
288                 printk(KERN_ERR "write_tcvr_bit: No transceiver type known!\n");
289         }
290 }
291
292 static int read_tcvr_bit(struct bigmac *bp, void __iomem *tregs)
293 {
294         int retval = 0;
295
296         if (bp->tcvr_type == internal) {
297                 sbus_writel(MGMT_PAL_EXT_MDIO, tregs + TCVR_MPAL);
298                 sbus_readl(tregs + TCVR_MPAL);
299                 sbus_writel(MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK,
300                             tregs + TCVR_MPAL);
301                 sbus_readl(tregs + TCVR_MPAL);
302                 retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_INT_MDIO) >> 3;
303         } else if (bp->tcvr_type == external) {
304                 sbus_writel(MGMT_PAL_INT_MDIO, tregs + TCVR_MPAL);
305                 sbus_readl(tregs + TCVR_MPAL);
306                 sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK, tregs + TCVR_MPAL);
307                 sbus_readl(tregs + TCVR_MPAL);
308                 retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_EXT_MDIO) >> 2;
309         } else {
310                 printk(KERN_ERR "read_tcvr_bit: No transceiver type known!\n");
311         }
312         return retval;
313 }
314
315 static int read_tcvr_bit2(struct bigmac *bp, void __iomem *tregs)
316 {
317         int retval = 0;
318
319         if (bp->tcvr_type == internal) {
320                 sbus_writel(MGMT_PAL_EXT_MDIO, tregs + TCVR_MPAL);
321                 sbus_readl(tregs + TCVR_MPAL);
322                 retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_INT_MDIO) >> 3;
323                 sbus_writel(MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK, tregs + TCVR_MPAL);
324                 sbus_readl(tregs + TCVR_MPAL);
325         } else if (bp->tcvr_type == external) {
326                 sbus_writel(MGMT_PAL_INT_MDIO, tregs + TCVR_MPAL);
327                 sbus_readl(tregs + TCVR_MPAL);
328                 retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_EXT_MDIO) >> 2;
329                 sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK, tregs + TCVR_MPAL);
330                 sbus_readl(tregs + TCVR_MPAL);
331         } else {
332                 printk(KERN_ERR "read_tcvr_bit2: No transceiver type known!\n");
333         }
334         return retval;
335 }
336
337 static void put_tcvr_byte(struct bigmac *bp,
338                           void __iomem *tregs,
339                           unsigned int byte)
340 {
341         int shift = 4;
342
343         do {
344                 write_tcvr_bit(bp, tregs, ((byte >> shift) & 1));
345                 shift -= 1;
346         } while (shift >= 0);
347 }
348
349 static void bigmac_tcvr_write(struct bigmac *bp, void __iomem *tregs,
350                               int reg, unsigned short val)
351 {
352         int shift;
353
354         reg &= 0xff;
355         val &= 0xffff;
356         switch(bp->tcvr_type) {
357         case internal:
358         case external:
359                 break;
360
361         default:
362                 printk(KERN_ERR "bigmac_tcvr_read: Whoops, no known transceiver type.\n");
363                 return;
364         };
365
366         idle_transceiver(tregs);
367         write_tcvr_bit(bp, tregs, 0);
368         write_tcvr_bit(bp, tregs, 1);
369         write_tcvr_bit(bp, tregs, 0);
370         write_tcvr_bit(bp, tregs, 1);
371
372         put_tcvr_byte(bp, tregs,
373                       ((bp->tcvr_type == internal) ?
374                        BIGMAC_PHY_INTERNAL : BIGMAC_PHY_EXTERNAL));
375
376         put_tcvr_byte(bp, tregs, reg);
377
378         write_tcvr_bit(bp, tregs, 1);
379         write_tcvr_bit(bp, tregs, 0);
380
381         shift = 15;
382         do {
383                 write_tcvr_bit(bp, tregs, (val >> shift) & 1);
384                 shift -= 1;
385         } while (shift >= 0);
386 }
387
388 static unsigned short bigmac_tcvr_read(struct bigmac *bp,
389                                        void __iomem *tregs,
390                                        int reg)
391 {
392         unsigned short retval = 0;
393
394         reg &= 0xff;
395         switch(bp->tcvr_type) {
396         case internal:
397         case external:
398                 break;
399
400         default:
401                 printk(KERN_ERR "bigmac_tcvr_read: Whoops, no known transceiver type.\n");
402                 return 0xffff;
403         };
404
405         idle_transceiver(tregs);
406         write_tcvr_bit(bp, tregs, 0);
407         write_tcvr_bit(bp, tregs, 1);
408         write_tcvr_bit(bp, tregs, 1);
409         write_tcvr_bit(bp, tregs, 0);
410
411         put_tcvr_byte(bp, tregs,
412                       ((bp->tcvr_type == internal) ?
413                        BIGMAC_PHY_INTERNAL : BIGMAC_PHY_EXTERNAL));
414
415         put_tcvr_byte(bp, tregs, reg);
416
417         if (bp->tcvr_type == external) {
418                 int shift = 15;
419
420                 (void) read_tcvr_bit2(bp, tregs);
421                 (void) read_tcvr_bit2(bp, tregs);
422
423                 do {
424                         int tmp;
425
426                         tmp = read_tcvr_bit2(bp, tregs);
427                         retval |= ((tmp & 1) << shift);
428                         shift -= 1;
429                 } while (shift >= 0);
430
431                 (void) read_tcvr_bit2(bp, tregs);
432                 (void) read_tcvr_bit2(bp, tregs);
433                 (void) read_tcvr_bit2(bp, tregs);
434         } else {
435                 int shift = 15;
436
437                 (void) read_tcvr_bit(bp, tregs);
438                 (void) read_tcvr_bit(bp, tregs);
439
440                 do {
441                         int tmp;
442
443                         tmp = read_tcvr_bit(bp, tregs);
444                         retval |= ((tmp & 1) << shift);
445                         shift -= 1;
446                 } while (shift >= 0);
447
448                 (void) read_tcvr_bit(bp, tregs);
449                 (void) read_tcvr_bit(bp, tregs);
450                 (void) read_tcvr_bit(bp, tregs);
451         }
452         return retval;
453 }
454
455 static void bigmac_tcvr_init(struct bigmac *bp)
456 {
457         void __iomem *tregs = bp->tregs;
458         u32 mpal;
459
460         idle_transceiver(tregs);
461         sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK,
462                     tregs + TCVR_MPAL);
463         sbus_readl(tregs + TCVR_MPAL);
464
465         /* Only the bit for the present transceiver (internal or
466          * external) will stick, set them both and see what stays.
467          */
468         sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO, tregs + TCVR_MPAL);
469         sbus_readl(tregs + TCVR_MPAL);
470         udelay(20);
471
472         mpal = sbus_readl(tregs + TCVR_MPAL);
473         if (mpal & MGMT_PAL_EXT_MDIO) {
474                 bp->tcvr_type = external;
475                 sbus_writel(~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE),
476                             tregs + TCVR_TPAL);
477                 sbus_readl(tregs + TCVR_TPAL);
478         } else if (mpal & MGMT_PAL_INT_MDIO) {
479                 bp->tcvr_type = internal;
480                 sbus_writel(~(TCVR_PAL_SERIAL | TCVR_PAL_EXTLBACK |
481                               TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE),
482                             tregs + TCVR_TPAL);
483                 sbus_readl(tregs + TCVR_TPAL);
484         } else {
485                 printk(KERN_ERR "BIGMAC: AIEEE, neither internal nor "
486                        "external MDIO available!\n");
487                 printk(KERN_ERR "BIGMAC: mgmt_pal[%08x] tcvr_pal[%08x]\n",
488                        sbus_readl(tregs + TCVR_MPAL),
489                        sbus_readl(tregs + TCVR_TPAL));
490         }
491 }
492
493 static int bigmac_init(struct bigmac *, int);
494
495 static int try_next_permutation(struct bigmac *bp, void __iomem *tregs)
496 {
497         if (bp->sw_bmcr & BMCR_SPEED100) {
498                 int timeout;
499
500                 /* Reset the PHY. */
501                 bp->sw_bmcr     = (BMCR_ISOLATE | BMCR_PDOWN | BMCR_LOOPBACK);
502                 bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
503                 bp->sw_bmcr     = (BMCR_RESET);
504                 bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
505
506                 timeout = 64;
507                 while (--timeout) {
508                         bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
509                         if ((bp->sw_bmcr & BMCR_RESET) == 0)
510                                 break;
511                         udelay(20);
512                 }
513                 if (timeout == 0)
514                         printk(KERN_ERR "%s: PHY reset failed.\n", bp->dev->name);
515
516                 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
517
518                 /* Now we try 10baseT. */
519                 bp->sw_bmcr &= ~(BMCR_SPEED100);
520                 bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
521                 return 0;
522         }
523
524         /* We've tried them all. */
525         return -1;
526 }
527
528 static void bigmac_timer(unsigned long data)
529 {
530         struct bigmac *bp = (struct bigmac *) data;
531         void __iomem *tregs = bp->tregs;
532         int restart_timer = 0;
533
534         bp->timer_ticks++;
535         if (bp->timer_state == ltrywait) {
536                 bp->sw_bmsr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMSR);
537                 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
538                 if (bp->sw_bmsr & BMSR_LSTATUS) {
539                         printk(KERN_INFO "%s: Link is now up at %s.\n",
540                                bp->dev->name,
541                                (bp->sw_bmcr & BMCR_SPEED100) ?
542                                "100baseT" : "10baseT");
543                         bp->timer_state = asleep;
544                         restart_timer = 0;
545                 } else {
546                         if (bp->timer_ticks >= 4) {
547                                 int ret;
548
549                                 ret = try_next_permutation(bp, tregs);
550                                 if (ret == -1) {
551                                         printk(KERN_ERR "%s: Link down, cable problem?\n",
552                                                bp->dev->name);
553                                         ret = bigmac_init(bp, 0);
554                                         if (ret) {
555                                                 printk(KERN_ERR "%s: Error, cannot re-init the "
556                                                        "BigMAC.\n", bp->dev->name);
557                                         }
558                                         return;
559                                 }
560                                 bp->timer_ticks = 0;
561                                 restart_timer = 1;
562                         } else {
563                                 restart_timer = 1;
564                         }
565                 }
566         } else {
567                 /* Can't happens.... */
568                 printk(KERN_ERR "%s: Aieee, link timer is asleep but we got one anyways!\n",
569                        bp->dev->name);
570                 restart_timer = 0;
571                 bp->timer_ticks = 0;
572                 bp->timer_state = asleep; /* foo on you */
573         }
574
575         if (restart_timer != 0) {
576                 bp->bigmac_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2 sec. */
577                 add_timer(&bp->bigmac_timer);
578         }
579 }
580
581 /* Well, really we just force the chip into 100baseT then
582  * 10baseT, each time checking for a link status.
583  */
584 static void bigmac_begin_auto_negotiation(struct bigmac *bp)
585 {
586         void __iomem *tregs = bp->tregs;
587         int timeout;
588
589         /* Grab new software copies of PHY registers. */
590         bp->sw_bmsr     = bigmac_tcvr_read(bp, tregs, BIGMAC_BMSR);
591         bp->sw_bmcr     = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
592
593         /* Reset the PHY. */
594         bp->sw_bmcr     = (BMCR_ISOLATE | BMCR_PDOWN | BMCR_LOOPBACK);
595         bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
596         bp->sw_bmcr     = (BMCR_RESET);
597         bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
598
599         timeout = 64;
600         while (--timeout) {
601                 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
602                 if ((bp->sw_bmcr & BMCR_RESET) == 0)
603                         break;
604                 udelay(20);
605         }
606         if (timeout == 0)
607                 printk(KERN_ERR "%s: PHY reset failed.\n", bp->dev->name);
608
609         bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
610
611         /* First we try 100baseT. */
612         bp->sw_bmcr |= BMCR_SPEED100;
613         bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
614
615         bp->timer_state = ltrywait;
616         bp->timer_ticks = 0;
617         bp->bigmac_timer.expires = jiffies + (12 * HZ) / 10;
618         bp->bigmac_timer.data = (unsigned long) bp;
619         bp->bigmac_timer.function = &bigmac_timer;
620         add_timer(&bp->bigmac_timer);
621 }
622
623 static int bigmac_init(struct bigmac *bp, int from_irq)
624 {
625         void __iomem *gregs        = bp->gregs;
626         void __iomem *cregs        = bp->creg;
627         void __iomem *bregs        = bp->bregs;
628         unsigned char *e = &bp->dev->dev_addr[0];
629
630         /* Latch current counters into statistics. */
631         bigmac_get_counters(bp, bregs);
632
633         /* Reset QEC. */
634         qec_global_reset(gregs);
635
636         /* Init QEC. */
637         qec_init(bp);
638
639         /* Alloc and reset the tx/rx descriptor chains. */
640         bigmac_init_rings(bp, from_irq);
641
642         /* Initialize the PHY. */
643         bigmac_tcvr_init(bp);
644
645         /* Stop transmitter and receiver. */
646         bigmac_stop(bp);
647
648         /* Set hardware ethernet address. */
649         sbus_writel(((e[4] << 8) | e[5]), bregs + BMAC_MACADDR2);
650         sbus_writel(((e[2] << 8) | e[3]), bregs + BMAC_MACADDR1);
651         sbus_writel(((e[0] << 8) | e[1]), bregs + BMAC_MACADDR0);
652
653         /* Clear the hash table until mc upload occurs. */
654         sbus_writel(0, bregs + BMAC_HTABLE3);
655         sbus_writel(0, bregs + BMAC_HTABLE2);
656         sbus_writel(0, bregs + BMAC_HTABLE1);
657         sbus_writel(0, bregs + BMAC_HTABLE0);
658
659         /* Enable Big Mac hash table filter. */
660         sbus_writel(BIGMAC_RXCFG_HENABLE | BIGMAC_RXCFG_FIFO,
661                     bregs + BMAC_RXCFG);
662         udelay(20);
663
664         /* Ok, configure the Big Mac transmitter. */
665         sbus_writel(BIGMAC_TXCFG_FIFO, bregs + BMAC_TXCFG);
666
667         /* The HME docs recommend to use the 10LSB of our MAC here. */
668         sbus_writel(((e[5] | e[4] << 8) & 0x3ff),
669                     bregs + BMAC_RSEED);
670
671         /* Enable the output drivers no matter what. */
672         sbus_writel(BIGMAC_XCFG_ODENABLE | BIGMAC_XCFG_RESV,
673                     bregs + BMAC_XIFCFG);
674
675         /* Tell the QEC where the ring descriptors are. */
676         sbus_writel(bp->bblock_dvma + bib_offset(be_rxd, 0),
677                     cregs + CREG_RXDS);
678         sbus_writel(bp->bblock_dvma + bib_offset(be_txd, 0),
679                     cregs + CREG_TXDS);
680
681         /* Setup the FIFO pointers into QEC local memory. */
682         sbus_writel(0, cregs + CREG_RXRBUFPTR);
683         sbus_writel(0, cregs + CREG_RXWBUFPTR);
684         sbus_writel(sbus_readl(gregs + GLOB_RSIZE),
685                     cregs + CREG_TXRBUFPTR);
686         sbus_writel(sbus_readl(gregs + GLOB_RSIZE),
687                     cregs + CREG_TXWBUFPTR);
688
689         /* Tell bigmac what interrupts we don't want to hear about. */
690         sbus_writel(BIGMAC_IMASK_GOTFRAME | BIGMAC_IMASK_SENTFRAME,
691                     bregs + BMAC_IMASK);
692
693         /* Enable the various other irq's. */
694         sbus_writel(0, cregs + CREG_RIMASK);
695         sbus_writel(0, cregs + CREG_TIMASK);
696         sbus_writel(0, cregs + CREG_QMASK);
697         sbus_writel(0, cregs + CREG_BMASK);
698
699         /* Set jam size to a reasonable default. */
700         sbus_writel(DEFAULT_JAMSIZE, bregs + BMAC_JSIZE);
701
702         /* Clear collision counter. */
703         sbus_writel(0, cregs + CREG_CCNT);
704
705         /* Enable transmitter and receiver. */
706         sbus_writel(sbus_readl(bregs + BMAC_TXCFG) | BIGMAC_TXCFG_ENABLE,
707                     bregs + BMAC_TXCFG);
708         sbus_writel(sbus_readl(bregs + BMAC_RXCFG) | BIGMAC_RXCFG_ENABLE,
709                     bregs + BMAC_RXCFG);
710
711         /* Ok, start detecting link speed/duplex. */
712         bigmac_begin_auto_negotiation(bp);
713
714         /* Success. */
715         return 0;
716 }
717
718 /* Error interrupts get sent here. */
719 static void bigmac_is_medium_rare(struct bigmac *bp, u32 qec_status, u32 bmac_status)
720 {
721         printk(KERN_ERR "bigmac_is_medium_rare: ");
722         if (qec_status & (GLOB_STAT_ER | GLOB_STAT_BM)) {
723                 if (qec_status & GLOB_STAT_ER)
724                         printk("QEC_ERROR, ");
725                 if (qec_status & GLOB_STAT_BM)
726                         printk("QEC_BMAC_ERROR, ");
727         }
728         if (bmac_status & CREG_STAT_ERRORS) {
729                 if (bmac_status & CREG_STAT_BERROR)
730                         printk("BMAC_ERROR, ");
731                 if (bmac_status & CREG_STAT_TXDERROR)
732                         printk("TXD_ERROR, ");
733                 if (bmac_status & CREG_STAT_TXLERR)
734                         printk("TX_LATE_ERROR, ");
735                 if (bmac_status & CREG_STAT_TXPERR)
736                         printk("TX_PARITY_ERROR, ");
737                 if (bmac_status & CREG_STAT_TXSERR)
738                         printk("TX_SBUS_ERROR, ");
739
740                 if (bmac_status & CREG_STAT_RXDROP)
741                         printk("RX_DROP_ERROR, ");
742
743                 if (bmac_status & CREG_STAT_RXSMALL)
744                         printk("RX_SMALL_ERROR, ");
745                 if (bmac_status & CREG_STAT_RXLERR)
746                         printk("RX_LATE_ERROR, ");
747                 if (bmac_status & CREG_STAT_RXPERR)
748                         printk("RX_PARITY_ERROR, ");
749                 if (bmac_status & CREG_STAT_RXSERR)
750                         printk("RX_SBUS_ERROR, ");
751         }
752
753         printk(" RESET\n");
754         bigmac_init(bp, 1);
755 }
756
757 /* BigMAC transmit complete service routines. */
758 static void bigmac_tx(struct bigmac *bp)
759 {
760         struct be_txd *txbase = &bp->bmac_block->be_txd[0];
761         struct net_device *dev = bp->dev;
762         int elem;
763
764         spin_lock(&bp->lock);
765
766         elem = bp->tx_old;
767         DTX(("bigmac_tx: tx_old[%d] ", elem));
768         while (elem != bp->tx_new) {
769                 struct sk_buff *skb;
770                 struct be_txd *this = &txbase[elem];
771
772                 DTX(("this(%p) [flags(%08x)addr(%08x)]",
773                      this, this->tx_flags, this->tx_addr));
774
775                 if (this->tx_flags & TXD_OWN)
776                         break;
777                 skb = bp->tx_skbs[elem];
778                 bp->enet_stats.tx_packets++;
779                 bp->enet_stats.tx_bytes += skb->len;
780                 sbus_unmap_single(bp->bigmac_sdev,
781                                   this->tx_addr, skb->len,
782                                   SBUS_DMA_TODEVICE);
783
784                 DTX(("skb(%p) ", skb));
785                 bp->tx_skbs[elem] = NULL;
786                 dev_kfree_skb_irq(skb);
787
788                 elem = NEXT_TX(elem);
789         }
790         DTX((" DONE, tx_old=%d\n", elem));
791         bp->tx_old = elem;
792
793         if (netif_queue_stopped(dev) &&
794             TX_BUFFS_AVAIL(bp) > 0)
795                 netif_wake_queue(bp->dev);
796
797         spin_unlock(&bp->lock);
798 }
799
800 /* BigMAC receive complete service routines. */
801 static void bigmac_rx(struct bigmac *bp)
802 {
803         struct be_rxd *rxbase = &bp->bmac_block->be_rxd[0];
804         struct be_rxd *this;
805         int elem = bp->rx_new, drops = 0;
806         u32 flags;
807
808         this = &rxbase[elem];
809         while (!((flags = this->rx_flags) & RXD_OWN)) {
810                 struct sk_buff *skb;
811                 int len = (flags & RXD_LENGTH); /* FCS not included */
812
813                 /* Check for errors. */
814                 if (len < ETH_ZLEN) {
815                         bp->enet_stats.rx_errors++;
816                         bp->enet_stats.rx_length_errors++;
817
818         drop_it:
819                         /* Return it to the BigMAC. */
820                         bp->enet_stats.rx_dropped++;
821                         this->rx_flags =
822                                 (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH));
823                         goto next;
824                 }
825                 skb = bp->rx_skbs[elem];
826                 if (len > RX_COPY_THRESHOLD) {
827                         struct sk_buff *new_skb;
828
829                         /* Now refill the entry, if we can. */
830                         new_skb = big_mac_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
831                         if (new_skb == NULL) {
832                                 drops++;
833                                 goto drop_it;
834                         }
835                         sbus_unmap_single(bp->bigmac_sdev,
836                                           this->rx_addr,
837                                           RX_BUF_ALLOC_SIZE - 34,
838                                           SBUS_DMA_FROMDEVICE);
839                         bp->rx_skbs[elem] = new_skb;
840                         new_skb->dev = bp->dev;
841                         skb_put(new_skb, ETH_FRAME_LEN);
842                         skb_reserve(new_skb, 34);
843                         this->rx_addr = sbus_map_single(bp->bigmac_sdev,
844                                                         new_skb->data,
845                                                         RX_BUF_ALLOC_SIZE - 34,
846                                                         SBUS_DMA_FROMDEVICE);
847                         this->rx_flags =
848                                 (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH));
849
850                         /* Trim the original skb for the netif. */
851                         skb_trim(skb, len);
852                 } else {
853                         struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
854
855                         if (copy_skb == NULL) {
856                                 drops++;
857                                 goto drop_it;
858                         }
859                         copy_skb->dev = bp->dev;
860                         skb_reserve(copy_skb, 2);
861                         skb_put(copy_skb, len);
862                         sbus_dma_sync_single_for_cpu(bp->bigmac_sdev,
863                                                      this->rx_addr, len,
864                                                      SBUS_DMA_FROMDEVICE);
865                         eth_copy_and_sum(copy_skb, (unsigned char *)skb->data, len, 0);
866                         sbus_dma_sync_single_for_device(bp->bigmac_sdev,
867                                                         this->rx_addr, len,
868                                                         SBUS_DMA_FROMDEVICE);
869
870                         /* Reuse original ring buffer. */
871                         this->rx_flags =
872                                 (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH));
873
874                         skb = copy_skb;
875                 }
876
877                 /* No checksums done by the BigMAC ;-( */
878                 skb->protocol = eth_type_trans(skb, bp->dev);
879                 netif_rx(skb);
880                 bp->dev->last_rx = jiffies;
881                 bp->enet_stats.rx_packets++;
882                 bp->enet_stats.rx_bytes += len;
883         next:
884                 elem = NEXT_RX(elem);
885                 this = &rxbase[elem];
886         }
887         bp->rx_new = elem;
888         if (drops)
889                 printk(KERN_NOTICE "%s: Memory squeeze, deferring packet.\n", bp->dev->name);
890 }
891
892 static irqreturn_t bigmac_interrupt(int irq, void *dev_id, struct pt_regs *regs)
893 {
894         struct bigmac *bp = (struct bigmac *) dev_id;
895         u32 qec_status, bmac_status;
896
897         DIRQ(("bigmac_interrupt: "));
898
899         /* Latch status registers now. */
900         bmac_status = sbus_readl(bp->creg + CREG_STAT);
901         qec_status = sbus_readl(bp->gregs + GLOB_STAT);
902
903         DIRQ(("qec_status=%08x bmac_status=%08x\n", qec_status, bmac_status));
904         if ((qec_status & (GLOB_STAT_ER | GLOB_STAT_BM)) ||
905            (bmac_status & CREG_STAT_ERRORS))
906                 bigmac_is_medium_rare(bp, qec_status, bmac_status);
907
908         if (bmac_status & CREG_STAT_TXIRQ)
909                 bigmac_tx(bp);
910
911         if (bmac_status & CREG_STAT_RXIRQ)
912                 bigmac_rx(bp);
913
914         return IRQ_HANDLED;
915 }
916
917 static int bigmac_open(struct net_device *dev)
918 {
919         struct bigmac *bp = (struct bigmac *) dev->priv;
920         int ret;
921
922         ret = request_irq(dev->irq, &bigmac_interrupt, SA_SHIRQ, dev->name, bp);
923         if (ret) {
924                 printk(KERN_ERR "BIGMAC: Can't order irq %d to go.\n", dev->irq);
925                 return ret;
926         }
927         init_timer(&bp->bigmac_timer);
928         ret = bigmac_init(bp, 0);
929         if (ret)
930                 free_irq(dev->irq, bp);
931         return ret;
932 }
933
934 static int bigmac_close(struct net_device *dev)
935 {
936         struct bigmac *bp = (struct bigmac *) dev->priv;
937
938         del_timer(&bp->bigmac_timer);
939         bp->timer_state = asleep;
940         bp->timer_ticks = 0;
941
942         bigmac_stop(bp);
943         bigmac_clean_rings(bp);
944         free_irq(dev->irq, bp);
945         return 0;
946 }
947
948 static void bigmac_tx_timeout(struct net_device *dev)
949 {
950         struct bigmac *bp = (struct bigmac *) dev->priv;
951
952         bigmac_init(bp, 0);
953         netif_wake_queue(dev);
954 }
955
956 /* Put a packet on the wire. */
957 static int bigmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
958 {
959         struct bigmac *bp = (struct bigmac *) dev->priv;
960         int len, entry;
961         u32 mapping;
962
963         len = skb->len;
964         mapping = sbus_map_single(bp->bigmac_sdev, skb->data, len, SBUS_DMA_TODEVICE);
965
966         /* Avoid a race... */
967         spin_lock_irq(&bp->lock);
968         entry = bp->tx_new;
969         DTX(("bigmac_start_xmit: len(%d) entry(%d)\n", len, entry));
970         bp->bmac_block->be_txd[entry].tx_flags = TXD_UPDATE;
971         bp->tx_skbs[entry] = skb;
972         bp->bmac_block->be_txd[entry].tx_addr = mapping;
973         bp->bmac_block->be_txd[entry].tx_flags =
974                 (TXD_OWN | TXD_SOP | TXD_EOP | (len & TXD_LENGTH));
975         bp->tx_new = NEXT_TX(entry);
976         if (TX_BUFFS_AVAIL(bp) <= 0)
977                 netif_stop_queue(dev);
978         spin_unlock_irq(&bp->lock);
979
980         /* Get it going. */
981         sbus_writel(CREG_CTRL_TWAKEUP, bp->creg + CREG_CTRL);
982
983
984         dev->trans_start = jiffies;
985
986         return 0;
987 }
988
989 static struct net_device_stats *bigmac_get_stats(struct net_device *dev)
990 {
991         struct bigmac *bp = (struct bigmac *) dev->priv;
992
993         bigmac_get_counters(bp, bp->bregs);
994         return &bp->enet_stats;
995 }
996
997 static void bigmac_set_multicast(struct net_device *dev)
998 {
999         struct bigmac *bp = (struct bigmac *) dev->priv;
1000         void __iomem *bregs = bp->bregs;
1001         struct dev_mc_list *dmi = dev->mc_list;
1002         char *addrs;
1003         int i;
1004         u32 tmp, crc;
1005
1006         /* Disable the receiver.  The bit self-clears when
1007          * the operation is complete.
1008          */
1009         tmp = sbus_readl(bregs + BMAC_RXCFG);
1010         tmp &= ~(BIGMAC_RXCFG_ENABLE);
1011         sbus_writel(tmp, bregs + BMAC_RXCFG);
1012         while ((sbus_readl(bregs + BMAC_RXCFG) & BIGMAC_RXCFG_ENABLE) != 0)
1013                 udelay(20);
1014
1015         if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
1016                 sbus_writel(0xffff, bregs + BMAC_HTABLE0);
1017                 sbus_writel(0xffff, bregs + BMAC_HTABLE1);
1018                 sbus_writel(0xffff, bregs + BMAC_HTABLE2);
1019                 sbus_writel(0xffff, bregs + BMAC_HTABLE3);
1020         } else if (dev->flags & IFF_PROMISC) {
1021                 tmp = sbus_readl(bregs + BMAC_RXCFG);
1022                 tmp |= BIGMAC_RXCFG_PMISC;
1023                 sbus_writel(tmp, bregs + BMAC_RXCFG);
1024         } else {
1025                 u16 hash_table[4];
1026
1027                 for (i = 0; i < 4; i++)
1028                         hash_table[i] = 0;
1029
1030                 for (i = 0; i < dev->mc_count; i++) {
1031                         addrs = dmi->dmi_addr;
1032                         dmi = dmi->next;
1033
1034                         if (!(*addrs & 1))
1035                                 continue;
1036
1037                         crc = ether_crc_le(6, addrs);
1038                         crc >>= 26;
1039                         hash_table[crc >> 4] |= 1 << (crc & 0xf);
1040                 }
1041                 sbus_writel(hash_table[0], bregs + BMAC_HTABLE0);
1042                 sbus_writel(hash_table[1], bregs + BMAC_HTABLE1);
1043                 sbus_writel(hash_table[2], bregs + BMAC_HTABLE2);
1044                 sbus_writel(hash_table[3], bregs + BMAC_HTABLE3);
1045         }
1046
1047         /* Re-enable the receiver. */
1048         tmp = sbus_readl(bregs + BMAC_RXCFG);
1049         tmp |= BIGMAC_RXCFG_ENABLE;
1050         sbus_writel(tmp, bregs + BMAC_RXCFG);
1051 }
1052
1053 /* Ethtool support... */
1054 static void bigmac_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1055 {
1056         struct bigmac *bp = dev->priv;
1057
1058         strcpy(info->driver, "sunbmac");
1059         strcpy(info->version, "2.0");
1060         sprintf(info->bus_info, "SBUS:%d",
1061                 bp->qec_sdev->slot);
1062 }
1063
1064 static u32 bigmac_get_link(struct net_device *dev)
1065 {
1066         struct bigmac *bp = dev->priv;
1067
1068         spin_lock_irq(&bp->lock);
1069         bp->sw_bmsr = bigmac_tcvr_read(bp, bp->tregs, BIGMAC_BMSR);
1070         spin_unlock_irq(&bp->lock);
1071
1072         return (bp->sw_bmsr & BMSR_LSTATUS);
1073 }
1074
1075 static struct ethtool_ops bigmac_ethtool_ops = {
1076         .get_drvinfo            = bigmac_get_drvinfo,
1077         .get_link               = bigmac_get_link,
1078 };
1079
1080 static int __init bigmac_ether_init(struct sbus_dev *qec_sdev)
1081 {
1082         struct net_device *dev;
1083         static int version_printed;
1084         struct bigmac *bp;
1085         u8 bsizes, bsizes_more;
1086         int i;
1087
1088         /* Get a new device struct for this interface. */
1089         dev = alloc_etherdev(sizeof(struct bigmac));
1090         if (!dev)
1091                 return -ENOMEM;
1092         SET_MODULE_OWNER(dev);
1093
1094         if (version_printed++ == 0)
1095                 printk(KERN_INFO "%s", version);
1096
1097         dev->base_addr = (long) qec_sdev;
1098         for (i = 0; i < 6; i++)
1099                 dev->dev_addr[i] = idprom->id_ethaddr[i];
1100
1101         /* Setup softc, with backpointers to QEC and BigMAC SBUS device structs. */
1102         bp = dev->priv;
1103         bp->qec_sdev = qec_sdev;
1104         bp->bigmac_sdev = qec_sdev->child;
1105
1106         spin_lock_init(&bp->lock);
1107
1108         /* Verify the registers we expect, are actually there. */
1109         if ((bp->bigmac_sdev->num_registers != 3) ||
1110            (bp->qec_sdev->num_registers != 2)) {
1111                 printk(KERN_ERR "BIGMAC: Device does not have 2 and 3 regs, it has %d and %d.\n",
1112                        bp->qec_sdev->num_registers,
1113                        bp->bigmac_sdev->num_registers);
1114                 printk(KERN_ERR "BIGMAC: Would you like that for here or to go?\n");
1115                 goto fail_and_cleanup;
1116         }
1117
1118         /* Map in QEC global control registers. */
1119         bp->gregs = sbus_ioremap(&bp->qec_sdev->resource[0], 0,
1120                                  GLOB_REG_SIZE, "BigMAC QEC GLobal Regs");
1121         if (!bp->gregs) {
1122                 printk(KERN_ERR "BIGMAC: Cannot map QEC global registers.\n");
1123                 goto fail_and_cleanup;
1124         }
1125
1126         /* Make sure QEC is in BigMAC mode. */
1127         if ((sbus_readl(bp->gregs + GLOB_CTRL) & 0xf0000000) != GLOB_CTRL_BMODE) {
1128                 printk(KERN_ERR "BigMAC: AIEEE, QEC is not in BigMAC mode!\n");
1129                 goto fail_and_cleanup;
1130         }
1131
1132         /* Reset the QEC. */
1133         if (qec_global_reset(bp->gregs))
1134                 goto fail_and_cleanup;
1135
1136         /* Get supported SBUS burst sizes. */
1137         bsizes = prom_getintdefault(bp->qec_sdev->prom_node,
1138                                     "burst-sizes",
1139                                     0xff);
1140
1141         bsizes_more = prom_getintdefault(bp->qec_sdev->bus->prom_node,
1142                                          "burst-sizes",
1143                                          0xff);
1144
1145         bsizes &= 0xff;
1146         if (bsizes_more != 0xff)
1147                 bsizes &= bsizes_more;
1148         if (bsizes == 0xff || (bsizes & DMA_BURST16) == 0 ||
1149             (bsizes & DMA_BURST32) == 0)
1150                 bsizes = (DMA_BURST32 - 1);
1151         bp->bigmac_bursts = bsizes;
1152
1153         /* Perform QEC initialization. */
1154         qec_init(bp);
1155
1156         /* Map in the BigMAC channel registers. */
1157         bp->creg = sbus_ioremap(&bp->bigmac_sdev->resource[0], 0,
1158                                 CREG_REG_SIZE, "BigMAC QEC Channel Regs");
1159         if (!bp->creg) {
1160                 printk(KERN_ERR "BIGMAC: Cannot map QEC channel registers.\n");
1161                 goto fail_and_cleanup;
1162         }
1163
1164         /* Map in the BigMAC control registers. */
1165         bp->bregs = sbus_ioremap(&bp->bigmac_sdev->resource[1], 0,
1166                                  BMAC_REG_SIZE, "BigMAC Primary Regs");
1167         if (!bp->bregs) {
1168                 printk(KERN_ERR "BIGMAC: Cannot map BigMAC primary registers.\n");
1169                 goto fail_and_cleanup;
1170         }
1171
1172         /* Map in the BigMAC transceiver registers, this is how you poke at
1173          * the BigMAC's PHY.
1174          */
1175         bp->tregs = sbus_ioremap(&bp->bigmac_sdev->resource[2], 0,
1176                                  TCVR_REG_SIZE, "BigMAC Transceiver Regs");
1177         if (!bp->tregs) {
1178                 printk(KERN_ERR "BIGMAC: Cannot map BigMAC transceiver registers.\n");
1179                 goto fail_and_cleanup;
1180         }
1181
1182         /* Stop the BigMAC. */
1183         bigmac_stop(bp);
1184
1185         /* Allocate transmit/receive descriptor DVMA block. */
1186         bp->bmac_block = sbus_alloc_consistent(bp->bigmac_sdev,
1187                                                PAGE_SIZE,
1188                                                &bp->bblock_dvma);
1189         if (bp->bmac_block == NULL || bp->bblock_dvma == 0) {
1190                 printk(KERN_ERR "BIGMAC: Cannot allocate consistent DMA.\n");
1191                 goto fail_and_cleanup;
1192         }
1193
1194         /* Get the board revision of this BigMAC. */
1195         bp->board_rev = prom_getintdefault(bp->bigmac_sdev->prom_node,
1196                                            "board-version", 1);
1197
1198         /* Init auto-negotiation timer state. */
1199         init_timer(&bp->bigmac_timer);
1200         bp->timer_state = asleep;
1201         bp->timer_ticks = 0;
1202
1203         /* Backlink to generic net device struct. */
1204         bp->dev = dev;
1205
1206         /* Set links to our BigMAC open and close routines. */
1207         dev->open = &bigmac_open;
1208         dev->stop = &bigmac_close;
1209         dev->hard_start_xmit = &bigmac_start_xmit;
1210         dev->ethtool_ops = &bigmac_ethtool_ops;
1211
1212         /* Set links to BigMAC statistic and multi-cast loading code. */
1213         dev->get_stats = &bigmac_get_stats;
1214         dev->set_multicast_list = &bigmac_set_multicast;
1215
1216         dev->tx_timeout = &bigmac_tx_timeout;
1217         dev->watchdog_timeo = 5*HZ;
1218
1219         /* Finish net device registration. */
1220         dev->irq = bp->bigmac_sdev->irqs[0];
1221         dev->dma = 0;
1222
1223         if (register_netdev(dev)) {
1224                 printk(KERN_ERR "BIGMAC: Cannot register device.\n");
1225                 goto fail_and_cleanup;
1226         }
1227
1228         /* Put us into the list of instances attached for later driver
1229          * exit.
1230          */
1231         bp->next_module = root_bigmac_dev;
1232         root_bigmac_dev = bp;
1233
1234         printk(KERN_INFO "%s: BigMAC 100baseT Ethernet ", dev->name);
1235         for (i = 0; i < 6; i++)
1236                 printk("%2.2x%c", dev->dev_addr[i],
1237                        i == 5 ? ' ' : ':');
1238         printk("\n");
1239
1240         return 0;
1241
1242 fail_and_cleanup:
1243         /* Something went wrong, undo whatever we did so far. */
1244         /* Free register mappings if any. */
1245         if (bp->gregs)
1246                 sbus_iounmap(bp->gregs, GLOB_REG_SIZE);
1247         if (bp->creg)
1248                 sbus_iounmap(bp->creg, CREG_REG_SIZE);
1249         if (bp->bregs)
1250                 sbus_iounmap(bp->bregs, BMAC_REG_SIZE);
1251         if (bp->tregs)
1252                 sbus_iounmap(bp->tregs, TCVR_REG_SIZE);
1253
1254         if (bp->bmac_block)
1255                 sbus_free_consistent(bp->bigmac_sdev,
1256                                      PAGE_SIZE,
1257                                      bp->bmac_block,
1258                                      bp->bblock_dvma);
1259
1260         /* This also frees the co-located 'dev->priv' */
1261         free_netdev(dev);
1262         return -ENODEV;
1263 }
1264
1265 /* QEC can be the parent of either QuadEthernet or
1266  * a BigMAC.  We want the latter.
1267  */
1268 static int __init bigmac_match(struct sbus_dev *sdev)
1269 {
1270         struct sbus_dev *child = sdev->child;
1271
1272         if (strcmp(sdev->prom_name, "qec") != 0)
1273                 return 0;
1274
1275         if (child == NULL)
1276                 return 0;
1277
1278         if (strcmp(child->prom_name, "be") != 0)
1279                 return 0;
1280
1281         return 1;
1282 }
1283
1284 static int __init bigmac_probe(void)
1285 {
1286         struct sbus_bus *sbus;
1287         struct sbus_dev *sdev = NULL;
1288         static int called;
1289         int cards = 0, v;
1290
1291         root_bigmac_dev = NULL;
1292
1293         if (called)
1294                 return -ENODEV;
1295         called++;
1296
1297         for_each_sbus(sbus) {
1298                 for_each_sbusdev(sdev, sbus) {
1299                         if (bigmac_match(sdev)) {
1300                                 cards++;
1301                                 if ((v = bigmac_ether_init(sdev)))
1302                                         return v;
1303                         }
1304                 }
1305         }
1306         if (!cards)
1307                 return -ENODEV;
1308         return 0;
1309 }
1310
1311 static void __exit bigmac_cleanup(void)
1312 {
1313         while (root_bigmac_dev) {
1314                 struct bigmac *bp = root_bigmac_dev;
1315                 struct bigmac *bp_nxt = root_bigmac_dev->next_module;
1316
1317                 sbus_iounmap(bp->gregs, GLOB_REG_SIZE);
1318                 sbus_iounmap(bp->creg, CREG_REG_SIZE);
1319                 sbus_iounmap(bp->bregs, BMAC_REG_SIZE);
1320                 sbus_iounmap(bp->tregs, TCVR_REG_SIZE);
1321                 sbus_free_consistent(bp->bigmac_sdev,
1322                                      PAGE_SIZE,
1323                                      bp->bmac_block,
1324                                      bp->bblock_dvma);
1325
1326                 unregister_netdev(bp->dev);
1327                 free_netdev(bp->dev);
1328                 root_bigmac_dev = bp_nxt;
1329         }
1330 }
1331
1332 module_init(bigmac_probe);
1333 module_exit(bigmac_cleanup);