clocksource: improve sh_cmt clocksource overflow handling
[linux-2.6.git] / drivers / net / smsc911x.h
1 /***************************************************************************
2  *
3  * Copyright (C) 2004-2008 SMSC
4  * Copyright (C) 2005-2008 ARM
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License
8  * as published by the Free Software Foundation; either version 2
9  * of the License, or (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
19  *
20  ***************************************************************************/
21 #ifndef __SMSC911X_H__
22 #define __SMSC911X_H__
23
24 #define TX_FIFO_LOW_THRESHOLD   ((u32)1600)
25 #define SMSC911X_EEPROM_SIZE    ((u32)7)
26 #define USE_DEBUG               0
27
28 /* This is the maximum number of packets to be received every
29  * NAPI poll */
30 #define SMSC_NAPI_WEIGHT        16
31
32 /* implements a PHY loopback test at initialisation time, to ensure a packet
33  * can be succesfully looped back */
34 #define USE_PHY_WORK_AROUND
35
36 #define DPRINTK(nlevel, klevel, fmt, args...) \
37         ((void)((NETIF_MSG_##nlevel & pdata->msg_enable) && \
38         printk(KERN_##klevel "%s: %s: " fmt "\n", \
39         pdata->dev->name, __func__, ## args)))
40
41 #if USE_DEBUG >= 1
42 #define SMSC_WARNING(nlevel, fmt, args...) \
43         DPRINTK(nlevel, WARNING, fmt, ## args)
44 #else
45 #define SMSC_WARNING(nlevel, fmt, args...) \
46         ({ do {} while (0); 0; })
47 #endif
48
49 #if USE_DEBUG >= 2
50 #define SMSC_TRACE(nlevel, fmt, args...) \
51         DPRINTK(nlevel, INFO, fmt, ## args)
52 #else
53 #define SMSC_TRACE(nlevel, fmt, args...) \
54         ({ do {} while (0); 0; })
55 #endif
56
57 #ifdef CONFIG_DEBUG_SPINLOCK
58 #define SMSC_ASSERT_MAC_LOCK(pdata) \
59                 WARN_ON(!spin_is_locked(&pdata->mac_lock))
60 #else
61 #define SMSC_ASSERT_MAC_LOCK(pdata) do {} while (0)
62 #endif                          /* CONFIG_DEBUG_SPINLOCK */
63
64 /* SMSC911x registers and bitfields */
65 #define RX_DATA_FIFO                    0x00
66
67 #define TX_DATA_FIFO                    0x20
68 #define TX_CMD_A_ON_COMP_               0x80000000
69 #define TX_CMD_A_BUF_END_ALGN_          0x03000000
70 #define TX_CMD_A_4_BYTE_ALGN_           0x00000000
71 #define TX_CMD_A_16_BYTE_ALGN_          0x01000000
72 #define TX_CMD_A_32_BYTE_ALGN_          0x02000000
73 #define TX_CMD_A_DATA_OFFSET_           0x001F0000
74 #define TX_CMD_A_FIRST_SEG_             0x00002000
75 #define TX_CMD_A_LAST_SEG_              0x00001000
76 #define TX_CMD_A_BUF_SIZE_              0x000007FF
77 #define TX_CMD_B_PKT_TAG_               0xFFFF0000
78 #define TX_CMD_B_ADD_CRC_DISABLE_       0x00002000
79 #define TX_CMD_B_DISABLE_PADDING_       0x00001000
80 #define TX_CMD_B_PKT_BYTE_LENGTH_       0x000007FF
81
82 #define RX_STATUS_FIFO                  0x40
83 #define RX_STS_ES_                      0x00008000
84 #define RX_STS_LENGTH_ERR_              0x00001000
85 #define RX_STS_MCAST_                   0x00000400
86 #define RX_STS_FRAME_TYPE_              0x00000020
87 #define RX_STS_CRC_ERR_                 0x00000002
88
89 #define RX_STATUS_FIFO_PEEK             0x44
90
91 #define TX_STATUS_FIFO                  0x48
92 #define TX_STS_ES_                      0x00008000
93 #define TX_STS_LOST_CARRIER_            0x00000800
94 #define TX_STS_NO_CARRIER_              0x00000400
95 #define TX_STS_LATE_COL_                0x00000200
96 #define TX_STS_EXCESS_COL_              0x00000100
97
98 #define TX_STATUS_FIFO_PEEK             0x4C
99
100 #define ID_REV                          0x50
101 #define ID_REV_CHIP_ID_                 0xFFFF0000
102 #define ID_REV_REV_ID_                  0x0000FFFF
103
104 #define INT_CFG                         0x54
105 #define INT_CFG_INT_DEAS_               0xFF000000
106 #define INT_CFG_INT_DEAS_CLR_           0x00004000
107 #define INT_CFG_INT_DEAS_STS_           0x00002000
108 #define INT_CFG_IRQ_INT_                0x00001000
109 #define INT_CFG_IRQ_EN_                 0x00000100
110 #define INT_CFG_IRQ_POL_                0x00000010
111 #define INT_CFG_IRQ_TYPE_               0x00000001
112
113 #define INT_STS                         0x58
114 #define INT_STS_SW_INT_                 0x80000000
115 #define INT_STS_TXSTOP_INT_             0x02000000
116 #define INT_STS_RXSTOP_INT_             0x01000000
117 #define INT_STS_RXDFH_INT_              0x00800000
118 #define INT_STS_RXDF_INT_               0x00400000
119 #define INT_STS_TX_IOC_                 0x00200000
120 #define INT_STS_RXD_INT_                0x00100000
121 #define INT_STS_GPT_INT_                0x00080000
122 #define INT_STS_PHY_INT_                0x00040000
123 #define INT_STS_PME_INT_                0x00020000
124 #define INT_STS_TXSO_                   0x00010000
125 #define INT_STS_RWT_                    0x00008000
126 #define INT_STS_RXE_                    0x00004000
127 #define INT_STS_TXE_                    0x00002000
128 #define INT_STS_TDFU_                   0x00000800
129 #define INT_STS_TDFO_                   0x00000400
130 #define INT_STS_TDFA_                   0x00000200
131 #define INT_STS_TSFF_                   0x00000100
132 #define INT_STS_TSFL_                   0x00000080
133 #define INT_STS_RXDF_                   0x00000040
134 #define INT_STS_RDFL_                   0x00000020
135 #define INT_STS_RSFF_                   0x00000010
136 #define INT_STS_RSFL_                   0x00000008
137 #define INT_STS_GPIO2_INT_              0x00000004
138 #define INT_STS_GPIO1_INT_              0x00000002
139 #define INT_STS_GPIO0_INT_              0x00000001
140
141 #define INT_EN                          0x5C
142 #define INT_EN_SW_INT_EN_               0x80000000
143 #define INT_EN_TXSTOP_INT_EN_           0x02000000
144 #define INT_EN_RXSTOP_INT_EN_           0x01000000
145 #define INT_EN_RXDFH_INT_EN_            0x00800000
146 #define INT_EN_TIOC_INT_EN_             0x00200000
147 #define INT_EN_RXD_INT_EN_              0x00100000
148 #define INT_EN_GPT_INT_EN_              0x00080000
149 #define INT_EN_PHY_INT_EN_              0x00040000
150 #define INT_EN_PME_INT_EN_              0x00020000
151 #define INT_EN_TXSO_EN_                 0x00010000
152 #define INT_EN_RWT_EN_                  0x00008000
153 #define INT_EN_RXE_EN_                  0x00004000
154 #define INT_EN_TXE_EN_                  0x00002000
155 #define INT_EN_TDFU_EN_                 0x00000800
156 #define INT_EN_TDFO_EN_                 0x00000400
157 #define INT_EN_TDFA_EN_                 0x00000200
158 #define INT_EN_TSFF_EN_                 0x00000100
159 #define INT_EN_TSFL_EN_                 0x00000080
160 #define INT_EN_RXDF_EN_                 0x00000040
161 #define INT_EN_RDFL_EN_                 0x00000020
162 #define INT_EN_RSFF_EN_                 0x00000010
163 #define INT_EN_RSFL_EN_                 0x00000008
164 #define INT_EN_GPIO2_INT_               0x00000004
165 #define INT_EN_GPIO1_INT_               0x00000002
166 #define INT_EN_GPIO0_INT_               0x00000001
167
168 #define BYTE_TEST                       0x64
169
170 #define FIFO_INT                        0x68
171 #define FIFO_INT_TX_AVAIL_LEVEL_        0xFF000000
172 #define FIFO_INT_TX_STS_LEVEL_          0x00FF0000
173 #define FIFO_INT_RX_AVAIL_LEVEL_        0x0000FF00
174 #define FIFO_INT_RX_STS_LEVEL_          0x000000FF
175
176 #define RX_CFG                          0x6C
177 #define RX_CFG_RX_END_ALGN_             0xC0000000
178 #define RX_CFG_RX_END_ALGN4_            0x00000000
179 #define RX_CFG_RX_END_ALGN16_           0x40000000
180 #define RX_CFG_RX_END_ALGN32_           0x80000000
181 #define RX_CFG_RX_DMA_CNT_              0x0FFF0000
182 #define RX_CFG_RX_DUMP_                 0x00008000
183 #define RX_CFG_RXDOFF_                  0x00001F00
184
185 #define TX_CFG                          0x70
186 #define TX_CFG_TXS_DUMP_                0x00008000
187 #define TX_CFG_TXD_DUMP_                0x00004000
188 #define TX_CFG_TXSAO_                   0x00000004
189 #define TX_CFG_TX_ON_                   0x00000002
190 #define TX_CFG_STOP_TX_                 0x00000001
191
192 #define HW_CFG                          0x74
193 #define HW_CFG_TTM_                     0x00200000
194 #define HW_CFG_SF_                      0x00100000
195 #define HW_CFG_TX_FIF_SZ_               0x000F0000
196 #define HW_CFG_TR_                      0x00003000
197 #define HW_CFG_SRST_                    0x00000001
198
199 /* only available on 115/117 */
200 #define HW_CFG_PHY_CLK_SEL_             0x00000060
201 #define HW_CFG_PHY_CLK_SEL_INT_PHY_     0x00000000
202 #define HW_CFG_PHY_CLK_SEL_EXT_PHY_     0x00000020
203 #define HW_CFG_PHY_CLK_SEL_CLK_DIS_     0x00000040
204 #define HW_CFG_SMI_SEL_                 0x00000010
205 #define HW_CFG_EXT_PHY_DET_             0x00000008
206 #define HW_CFG_EXT_PHY_EN_              0x00000004
207 #define HW_CFG_SRST_TO_                 0x00000002
208
209 /* only available  on 116/118 */
210 #define HW_CFG_32_16_BIT_MODE_          0x00000004
211
212 #define RX_DP_CTRL                      0x78
213 #define RX_DP_CTRL_RX_FFWD_             0x80000000
214
215 #define RX_FIFO_INF                     0x7C
216 #define RX_FIFO_INF_RXSUSED_            0x00FF0000
217 #define RX_FIFO_INF_RXDUSED_            0x0000FFFF
218
219 #define TX_FIFO_INF                     0x80
220 #define TX_FIFO_INF_TSUSED_             0x00FF0000
221 #define TX_FIFO_INF_TDFREE_             0x0000FFFF
222
223 #define PMT_CTRL                        0x84
224 #define PMT_CTRL_PM_MODE_               0x00003000
225 #define PMT_CTRL_PM_MODE_D0_            0x00000000
226 #define PMT_CTRL_PM_MODE_D1_            0x00001000
227 #define PMT_CTRL_PM_MODE_D2_            0x00002000
228 #define PMT_CTRL_PM_MODE_D3_            0x00003000
229 #define PMT_CTRL_PHY_RST_               0x00000400
230 #define PMT_CTRL_WOL_EN_                0x00000200
231 #define PMT_CTRL_ED_EN_                 0x00000100
232 #define PMT_CTRL_PME_TYPE_              0x00000040
233 #define PMT_CTRL_WUPS_                  0x00000030
234 #define PMT_CTRL_WUPS_NOWAKE_           0x00000000
235 #define PMT_CTRL_WUPS_ED_               0x00000010
236 #define PMT_CTRL_WUPS_WOL_              0x00000020
237 #define PMT_CTRL_WUPS_MULTI_            0x00000030
238 #define PMT_CTRL_PME_IND_               0x00000008
239 #define PMT_CTRL_PME_POL_               0x00000004
240 #define PMT_CTRL_PME_EN_                0x00000002
241 #define PMT_CTRL_READY_                 0x00000001
242
243 #define GPIO_CFG                        0x88
244 #define GPIO_CFG_LED3_EN_               0x40000000
245 #define GPIO_CFG_LED2_EN_               0x20000000
246 #define GPIO_CFG_LED1_EN_               0x10000000
247 #define GPIO_CFG_GPIO2_INT_POL_         0x04000000
248 #define GPIO_CFG_GPIO1_INT_POL_         0x02000000
249 #define GPIO_CFG_GPIO0_INT_POL_         0x01000000
250 #define GPIO_CFG_EEPR_EN_               0x00700000
251 #define GPIO_CFG_GPIOBUF2_              0x00040000
252 #define GPIO_CFG_GPIOBUF1_              0x00020000
253 #define GPIO_CFG_GPIOBUF0_              0x00010000
254 #define GPIO_CFG_GPIODIR2_              0x00000400
255 #define GPIO_CFG_GPIODIR1_              0x00000200
256 #define GPIO_CFG_GPIODIR0_              0x00000100
257 #define GPIO_CFG_GPIOD4_                0x00000020
258 #define GPIO_CFG_GPIOD3_                0x00000010
259 #define GPIO_CFG_GPIOD2_                0x00000004
260 #define GPIO_CFG_GPIOD1_                0x00000002
261 #define GPIO_CFG_GPIOD0_                0x00000001
262
263 #define GPT_CFG                         0x8C
264 #define GPT_CFG_TIMER_EN_               0x20000000
265 #define GPT_CFG_GPT_LOAD_               0x0000FFFF
266
267 #define GPT_CNT                         0x90
268 #define GPT_CNT_GPT_CNT_                0x0000FFFF
269
270 #define WORD_SWAP                       0x98
271
272 #define FREE_RUN                        0x9C
273
274 #define RX_DROP                         0xA0
275
276 #define MAC_CSR_CMD                     0xA4
277 #define MAC_CSR_CMD_CSR_BUSY_           0x80000000
278 #define MAC_CSR_CMD_R_NOT_W_            0x40000000
279 #define MAC_CSR_CMD_CSR_ADDR_           0x000000FF
280
281 #define MAC_CSR_DATA                    0xA8
282
283 #define AFC_CFG                         0xAC
284 #define AFC_CFG_AFC_HI_                 0x00FF0000
285 #define AFC_CFG_AFC_LO_                 0x0000FF00
286 #define AFC_CFG_BACK_DUR_               0x000000F0
287 #define AFC_CFG_FCMULT_                 0x00000008
288 #define AFC_CFG_FCBRD_                  0x00000004
289 #define AFC_CFG_FCADD_                  0x00000002
290 #define AFC_CFG_FCANY_                  0x00000001
291
292 #define E2P_CMD                         0xB0
293 #define E2P_CMD_EPC_BUSY_               0x80000000
294 #define E2P_CMD_EPC_CMD_                0x70000000
295 #define E2P_CMD_EPC_CMD_READ_           0x00000000
296 #define E2P_CMD_EPC_CMD_EWDS_           0x10000000
297 #define E2P_CMD_EPC_CMD_EWEN_           0x20000000
298 #define E2P_CMD_EPC_CMD_WRITE_          0x30000000
299 #define E2P_CMD_EPC_CMD_WRAL_           0x40000000
300 #define E2P_CMD_EPC_CMD_ERASE_          0x50000000
301 #define E2P_CMD_EPC_CMD_ERAL_           0x60000000
302 #define E2P_CMD_EPC_CMD_RELOAD_         0x70000000
303 #define E2P_CMD_EPC_TIMEOUT_            0x00000200
304 #define E2P_CMD_MAC_ADDR_LOADED_        0x00000100
305 #define E2P_CMD_EPC_ADDR_               0x000000FF
306
307 #define E2P_DATA                        0xB4
308 #define E2P_DATA_EEPROM_DATA_           0x000000FF
309 #define LAN_REGISTER_EXTENT             0x00000100
310
311 /*
312  * MAC Control and Status Register (Indirect Address)
313  * Offset (through the MAC_CSR CMD and DATA port)
314  */
315 #define MAC_CR                          0x01
316 #define MAC_CR_RXALL_                   0x80000000
317 #define MAC_CR_HBDIS_                   0x10000000
318 #define MAC_CR_RCVOWN_                  0x00800000
319 #define MAC_CR_LOOPBK_                  0x00200000
320 #define MAC_CR_FDPX_                    0x00100000
321 #define MAC_CR_MCPAS_                   0x00080000
322 #define MAC_CR_PRMS_                    0x00040000
323 #define MAC_CR_INVFILT_                 0x00020000
324 #define MAC_CR_PASSBAD_                 0x00010000
325 #define MAC_CR_HFILT_                   0x00008000
326 #define MAC_CR_HPFILT_                  0x00002000
327 #define MAC_CR_LCOLL_                   0x00001000
328 #define MAC_CR_BCAST_                   0x00000800
329 #define MAC_CR_DISRTY_                  0x00000400
330 #define MAC_CR_PADSTR_                  0x00000100
331 #define MAC_CR_BOLMT_MASK_              0x000000C0
332 #define MAC_CR_DFCHK_                   0x00000020
333 #define MAC_CR_TXEN_                    0x00000008
334 #define MAC_CR_RXEN_                    0x00000004
335
336 #define ADDRH                           0x02
337
338 #define ADDRL                           0x03
339
340 #define HASHH                           0x04
341
342 #define HASHL                           0x05
343
344 #define MII_ACC                         0x06
345 #define MII_ACC_PHY_ADDR_               0x0000F800
346 #define MII_ACC_MIIRINDA_               0x000007C0
347 #define MII_ACC_MII_WRITE_              0x00000002
348 #define MII_ACC_MII_BUSY_               0x00000001
349
350 #define MII_DATA                        0x07
351
352 #define FLOW                            0x08
353 #define FLOW_FCPT_                      0xFFFF0000
354 #define FLOW_FCPASS_                    0x00000004
355 #define FLOW_FCEN_                      0x00000002
356 #define FLOW_FCBSY_                     0x00000001
357
358 #define VLAN1                           0x09
359
360 #define VLAN2                           0x0A
361
362 #define WUFF                            0x0B
363
364 #define WUCSR                           0x0C
365 #define WUCSR_GUE_                      0x00000200
366 #define WUCSR_WUFR_                     0x00000040
367 #define WUCSR_MPR_                      0x00000020
368 #define WUCSR_WAKE_EN_                  0x00000004
369 #define WUCSR_MPEN_                     0x00000002
370
371 /*
372  * Phy definitions (vendor-specific)
373  */
374 #define LAN9118_PHY_ID                  0x00C0001C
375
376 #define MII_INTSTS                      0x1D
377
378 #define MII_INTMSK                      0x1E
379 #define PHY_INTMSK_AN_RCV_              (1 << 1)
380 #define PHY_INTMSK_PDFAULT_             (1 << 2)
381 #define PHY_INTMSK_AN_ACK_              (1 << 3)
382 #define PHY_INTMSK_LNKDOWN_             (1 << 4)
383 #define PHY_INTMSK_RFAULT_              (1 << 5)
384 #define PHY_INTMSK_AN_COMP_             (1 << 6)
385 #define PHY_INTMSK_ENERGYON_            (1 << 7)
386 #define PHY_INTMSK_DEFAULT_             (PHY_INTMSK_ENERGYON_ | \
387                                          PHY_INTMSK_AN_COMP_ | \
388                                          PHY_INTMSK_RFAULT_ | \
389                                          PHY_INTMSK_LNKDOWN_)
390
391 #define ADVERTISE_PAUSE_ALL             (ADVERTISE_PAUSE_CAP | \
392                                          ADVERTISE_PAUSE_ASYM)
393
394 #define LPA_PAUSE_ALL                   (LPA_PAUSE_CAP | \
395                                          LPA_PAUSE_ASYM)
396
397 #endif                          /* __SMSC911X_H__ */