rndis_wlan: cleanup: rename and remove local pointers
[linux-2.6.git] / drivers / net / smc911x.h
1 /*------------------------------------------------------------------------
2  . smc911x.h - macros for SMSC's LAN911{5,6,7,8} single-chip Ethernet device.
3  .
4  . Copyright (C) 2005 Sensoria Corp.
5  . Derived from the unified SMC91x driver by Nicolas Pitre
6  .
7  . This program is free software; you can redistribute it and/or modify
8  . it under the terms of the GNU General Public License as published by
9  . the Free Software Foundation; either version 2 of the License, or
10  . (at your option) any later version.
11  .
12  . This program is distributed in the hope that it will be useful,
13  . but WITHOUT ANY WARRANTY; without even the implied warranty of
14  . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  . GNU General Public License for more details.
16  .
17  . You should have received a copy of the GNU General Public License
18  . along with this program; if not, write to the Free Software
19  . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
20  .
21  . Information contained in this file was obtained from the LAN9118
22  . manual from SMC.  To get a copy, if you really want one, you can find
23  . information under www.smsc.com.
24  .
25  . Authors
26  .       Dustin McIntire                 <dustin@sensoria.com>
27  .
28  ---------------------------------------------------------------------------*/
29 #ifndef _SMC911X_H_
30 #define _SMC911X_H_
31
32 #include <linux/smc911x.h>
33 /*
34  * Use the DMA feature on PXA chips
35  */
36 #ifdef CONFIG_ARCH_PXA
37   #define SMC_USE_PXA_DMA       1
38   #define SMC_USE_16BIT         0
39   #define SMC_USE_32BIT         1
40   #define SMC_IRQ_SENSE         IRQF_TRIGGER_FALLING
41 #elif defined(CONFIG_SH_MAGIC_PANEL_R2)
42   #define SMC_USE_16BIT         0
43   #define SMC_USE_32BIT         1
44   #define SMC_IRQ_SENSE         IRQF_TRIGGER_LOW
45 #else
46 /*
47  * Default configuration
48  */
49
50 #define SMC_DYNAMIC_BUS_CONFIG
51 #endif
52
53 /* store this information for the driver.. */
54 struct smc911x_local {
55         /*
56          * If I have to wait until the DMA is finished and ready to reload a
57          * packet, I will store the skbuff here. Then, the DMA will send it
58          * out and free it.
59          */
60         struct sk_buff *pending_tx_skb;
61
62         /* version/revision of the SMC911x chip */
63         u16 version;
64         u16 revision;
65
66         /* FIFO sizes */
67         int tx_fifo_kb;
68         int tx_fifo_size;
69         int rx_fifo_size;
70         int afc_cfg;
71
72         /* Contains the current active receive/phy mode */
73         int ctl_rfduplx;
74         int ctl_rspeed;
75
76         u32 msg_enable;
77         u32 phy_type;
78         struct mii_if_info mii;
79
80         /* work queue */
81         struct work_struct phy_configure;
82         int work_pending;
83
84         int tx_throttle;
85         spinlock_t lock;
86
87         struct net_device *netdev;
88
89 #ifdef SMC_USE_DMA
90         /* DMA needs the physical address of the chip */
91         u_long physaddr;
92         int rxdma;
93         int txdma;
94         int rxdma_active;
95         int txdma_active;
96         struct sk_buff *current_rx_skb;
97         struct sk_buff *current_tx_skb;
98         struct device *dev;
99 #endif
100         void __iomem *base;
101 #ifdef SMC_DYNAMIC_BUS_CONFIG
102         struct smc911x_platdata cfg;
103 #endif
104 };
105
106 /*
107  * Define the bus width specific IO macros
108  */
109
110 #ifdef SMC_DYNAMIC_BUS_CONFIG
111 static inline unsigned int SMC_inl(struct smc911x_local *lp, int reg)
112 {
113         void __iomem *ioaddr = lp->base + reg;
114
115         if (lp->cfg.flags & SMC911X_USE_32BIT)
116                 return readl(ioaddr);
117
118         if (lp->cfg.flags & SMC911X_USE_16BIT)
119                 return readw(ioaddr) | (readw(ioaddr + 2) << 16);
120
121         BUG();
122 }
123
124 static inline void SMC_outl(unsigned int value, struct smc911x_local *lp,
125                             int reg)
126 {
127         void __iomem *ioaddr = lp->base + reg;
128
129         if (lp->cfg.flags & SMC911X_USE_32BIT) {
130                 writel(value, ioaddr);
131                 return;
132         }
133
134         if (lp->cfg.flags & SMC911X_USE_16BIT) {
135                 writew(value & 0xffff, ioaddr);
136                 writew(value >> 16, ioaddr + 2);
137                 return;
138         }
139
140         BUG();
141 }
142
143 static inline void SMC_insl(struct smc911x_local *lp, int reg,
144                               void *addr, unsigned int count)
145 {
146         void __iomem *ioaddr = lp->base + reg;
147
148         if (lp->cfg.flags & SMC911X_USE_32BIT) {
149                 readsl(ioaddr, addr, count);
150                 return;
151         }
152
153         if (lp->cfg.flags & SMC911X_USE_16BIT) {
154                 readsw(ioaddr, addr, count * 2);
155                 return;
156         }
157
158         BUG();
159 }
160
161 static inline void SMC_outsl(struct smc911x_local *lp, int reg,
162                              void *addr, unsigned int count)
163 {
164         void __iomem *ioaddr = lp->base + reg;
165
166         if (lp->cfg.flags & SMC911X_USE_32BIT) {
167                 writesl(ioaddr, addr, count);
168                 return;
169         }
170
171         if (lp->cfg.flags & SMC911X_USE_16BIT) {
172                 writesw(ioaddr, addr, count * 2);
173                 return;
174         }
175
176         BUG();
177 }
178 #else
179 #if     SMC_USE_16BIT
180 #define SMC_inl(lp, r)           ((readw((lp)->base + (r)) & 0xFFFF) + (readw((lp)->base + (r) + 2) << 16))
181 #define SMC_outl(v, lp, r)                       \
182         do{                                      \
183                  writew(v & 0xFFFF, (lp)->base + (r));   \
184                  writew(v >> 16, (lp)->base + (r) + 2); \
185          } while (0)
186 #define SMC_insl(lp, r, p, l)    readsw((short*)((lp)->base + (r)), p, l*2)
187 #define SMC_outsl(lp, r, p, l)   writesw((short*)((lp)->base + (r)), p, l*2)
188
189 #elif   SMC_USE_32BIT
190 #define SMC_inl(lp, r)           readl((lp)->base + (r))
191 #define SMC_outl(v, lp, r)       writel(v, (lp)->base + (r))
192 #define SMC_insl(lp, r, p, l)    readsl((int*)((lp)->base + (r)), p, l)
193 #define SMC_outsl(lp, r, p, l)   writesl((int*)((lp)->base + (r)), p, l)
194
195 #endif /* SMC_USE_16BIT */
196 #endif /* SMC_DYNAMIC_BUS_CONFIG */
197
198
199 #ifdef SMC_USE_PXA_DMA
200 #define SMC_USE_DMA
201
202 /*
203  * Define the request and free functions
204  * These are unfortunately architecture specific as no generic allocation
205  * mechanism exits
206  */
207 #define SMC_DMA_REQUEST(dev, handler) \
208          pxa_request_dma(dev->name, DMA_PRIO_LOW, handler, dev)
209
210 #define SMC_DMA_FREE(dev, dma) \
211          pxa_free_dma(dma)
212
213 #define SMC_DMA_ACK_IRQ(dev, dma)                                       \
214 {                                                                       \
215         if (DCSR(dma) & DCSR_BUSERR) {                                  \
216                 printk("%s: DMA %d bus error!\n", dev->name, dma);      \
217         }                                                               \
218         DCSR(dma) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR;            \
219 }
220
221 /*
222  * Use a DMA for RX and TX packets.
223  */
224 #include <linux/dma-mapping.h>
225 #include <asm/dma.h>
226 #include <asm/arch/pxa-regs.h>
227
228 static dma_addr_t rx_dmabuf, tx_dmabuf;
229 static int rx_dmalen, tx_dmalen;
230
231 #ifdef SMC_insl
232 #undef SMC_insl
233 #define SMC_insl(lp, r, p, l) \
234         smc_pxa_dma_insl(lp, lp->physaddr, r, lp->rxdma, p, l)
235
236 static inline void
237 smc_pxa_dma_insl(struct smc911x_local *lp, u_long physaddr,
238                 int reg, int dma, u_char *buf, int len)
239 {
240         /* 64 bit alignment is required for memory to memory DMA */
241         if ((long)buf & 4) {
242                 *((u32 *)buf) = SMC_inl(lp, reg);
243                 buf += 4;
244                 len--;
245         }
246
247         len *= 4;
248         rx_dmabuf = dma_map_single(lp->dev, buf, len, DMA_FROM_DEVICE);
249         rx_dmalen = len;
250         DCSR(dma) = DCSR_NODESC;
251         DTADR(dma) = rx_dmabuf;
252         DSADR(dma) = physaddr + reg;
253         DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
254                 DCMD_WIDTH4 | DCMD_ENDIRQEN | (DCMD_LENGTH & rx_dmalen));
255         DCSR(dma) = DCSR_NODESC | DCSR_RUN;
256 }
257 #endif
258
259 #ifdef SMC_outsl
260 #undef SMC_outsl
261 #define SMC_outsl(lp, r, p, l) \
262          smc_pxa_dma_outsl(lp, lp->physaddr, r, lp->txdma, p, l)
263
264 static inline void
265 smc_pxa_dma_outsl(struct smc911x_local *lp, u_long physaddr,
266                 int reg, int dma, u_char *buf, int len)
267 {
268         /* 64 bit alignment is required for memory to memory DMA */
269         if ((long)buf & 4) {
270                 SMC_outl(*((u32 *)buf), lp, reg);
271                 buf += 4;
272                 len--;
273         }
274
275         len *= 4;
276         tx_dmabuf = dma_map_single(lp->dev, buf, len, DMA_TO_DEVICE);
277         tx_dmalen = len;
278         DCSR(dma) = DCSR_NODESC;
279         DSADR(dma) = tx_dmabuf;
280         DTADR(dma) = physaddr + reg;
281         DCMD(dma) = (DCMD_INCSRCADDR | DCMD_BURST32 |
282                 DCMD_WIDTH4 | DCMD_ENDIRQEN | (DCMD_LENGTH & tx_dmalen));
283         DCSR(dma) = DCSR_NODESC | DCSR_RUN;
284 }
285 #endif
286 #endif   /* SMC_USE_PXA_DMA */
287
288
289 /* Chip Parameters and Register Definitions */
290
291 #define SMC911X_TX_FIFO_LOW_THRESHOLD   (1536*2)
292
293 #define SMC911X_IO_EXTENT        0x100
294
295 #define SMC911X_EEPROM_LEN       7
296
297 /* Below are the register offsets and bit definitions
298  * of the Lan911x memory space
299  */
300 #define RX_DATA_FIFO             (0x00)
301
302 #define TX_DATA_FIFO             (0x20)
303 #define TX_CMD_A_INT_ON_COMP_           (0x80000000)
304 #define TX_CMD_A_INT_BUF_END_ALGN_      (0x03000000)
305 #define TX_CMD_A_INT_4_BYTE_ALGN_       (0x00000000)
306 #define TX_CMD_A_INT_16_BYTE_ALGN_      (0x01000000)
307 #define TX_CMD_A_INT_32_BYTE_ALGN_      (0x02000000)
308 #define TX_CMD_A_INT_DATA_OFFSET_       (0x001F0000)
309 #define TX_CMD_A_INT_FIRST_SEG_         (0x00002000)
310 #define TX_CMD_A_INT_LAST_SEG_          (0x00001000)
311 #define TX_CMD_A_BUF_SIZE_              (0x000007FF)
312 #define TX_CMD_B_PKT_TAG_               (0xFFFF0000)
313 #define TX_CMD_B_ADD_CRC_DISABLE_       (0x00002000)
314 #define TX_CMD_B_DISABLE_PADDING_       (0x00001000)
315 #define TX_CMD_B_PKT_BYTE_LENGTH_       (0x000007FF)
316
317 #define RX_STATUS_FIFO          (0x40)
318 #define RX_STS_PKT_LEN_                 (0x3FFF0000)
319 #define RX_STS_ES_                      (0x00008000)
320 #define RX_STS_BCST_                    (0x00002000)
321 #define RX_STS_LEN_ERR_                 (0x00001000)
322 #define RX_STS_RUNT_ERR_                (0x00000800)
323 #define RX_STS_MCAST_                   (0x00000400)
324 #define RX_STS_TOO_LONG_                (0x00000080)
325 #define RX_STS_COLL_                    (0x00000040)
326 #define RX_STS_ETH_TYPE_                (0x00000020)
327 #define RX_STS_WDOG_TMT_                (0x00000010)
328 #define RX_STS_MII_ERR_                 (0x00000008)
329 #define RX_STS_DRIBBLING_               (0x00000004)
330 #define RX_STS_CRC_ERR_                 (0x00000002)
331 #define RX_STATUS_FIFO_PEEK     (0x44)
332 #define TX_STATUS_FIFO          (0x48)
333 #define TX_STS_TAG_                     (0xFFFF0000)
334 #define TX_STS_ES_                      (0x00008000)
335 #define TX_STS_LOC_                     (0x00000800)
336 #define TX_STS_NO_CARR_                 (0x00000400)
337 #define TX_STS_LATE_COLL_               (0x00000200)
338 #define TX_STS_MANY_COLL_               (0x00000100)
339 #define TX_STS_COLL_CNT_                (0x00000078)
340 #define TX_STS_MANY_DEFER_              (0x00000004)
341 #define TX_STS_UNDERRUN_                (0x00000002)
342 #define TX_STS_DEFERRED_                (0x00000001)
343 #define TX_STATUS_FIFO_PEEK     (0x4C)
344 #define ID_REV                  (0x50)
345 #define ID_REV_CHIP_ID_                 (0xFFFF0000)  /* RO */
346 #define ID_REV_REV_ID_                  (0x0000FFFF)  /* RO */
347
348 #define INT_CFG                 (0x54)
349 #define INT_CFG_INT_DEAS_               (0xFF000000)  /* R/W */
350 #define INT_CFG_INT_DEAS_CLR_           (0x00004000)
351 #define INT_CFG_INT_DEAS_STS_           (0x00002000)
352 #define INT_CFG_IRQ_INT_                (0x00001000)  /* RO */
353 #define INT_CFG_IRQ_EN_                 (0x00000100)  /* R/W */
354 #define INT_CFG_IRQ_POL_                (0x00000010)  /* R/W Not Affected by SW Reset */
355 #define INT_CFG_IRQ_TYPE_               (0x00000001)  /* R/W Not Affected by SW Reset */
356
357 #define INT_STS                 (0x58)
358 #define INT_STS_SW_INT_                 (0x80000000)  /* R/WC */
359 #define INT_STS_TXSTOP_INT_             (0x02000000)  /* R/WC */
360 #define INT_STS_RXSTOP_INT_             (0x01000000)  /* R/WC */
361 #define INT_STS_RXDFH_INT_              (0x00800000)  /* R/WC */
362 #define INT_STS_RXDF_INT_               (0x00400000)  /* R/WC */
363 #define INT_STS_TX_IOC_                 (0x00200000)  /* R/WC */
364 #define INT_STS_RXD_INT_                (0x00100000)  /* R/WC */
365 #define INT_STS_GPT_INT_                (0x00080000)  /* R/WC */
366 #define INT_STS_PHY_INT_                (0x00040000)  /* RO */
367 #define INT_STS_PME_INT_                (0x00020000)  /* R/WC */
368 #define INT_STS_TXSO_                   (0x00010000)  /* R/WC */
369 #define INT_STS_RWT_                    (0x00008000)  /* R/WC */
370 #define INT_STS_RXE_                    (0x00004000)  /* R/WC */
371 #define INT_STS_TXE_                    (0x00002000)  /* R/WC */
372 //#define       INT_STS_ERX_            (0x00001000)  /* R/WC */
373 #define INT_STS_TDFU_                   (0x00000800)  /* R/WC */
374 #define INT_STS_TDFO_                   (0x00000400)  /* R/WC */
375 #define INT_STS_TDFA_                   (0x00000200)  /* R/WC */
376 #define INT_STS_TSFF_                   (0x00000100)  /* R/WC */
377 #define INT_STS_TSFL_                   (0x00000080)  /* R/WC */
378 //#define       INT_STS_RXDF_           (0x00000040)  /* R/WC */
379 #define INT_STS_RDFO_                   (0x00000040)  /* R/WC */
380 #define INT_STS_RDFL_                   (0x00000020)  /* R/WC */
381 #define INT_STS_RSFF_                   (0x00000010)  /* R/WC */
382 #define INT_STS_RSFL_                   (0x00000008)  /* R/WC */
383 #define INT_STS_GPIO2_INT_              (0x00000004)  /* R/WC */
384 #define INT_STS_GPIO1_INT_              (0x00000002)  /* R/WC */
385 #define INT_STS_GPIO0_INT_              (0x00000001)  /* R/WC */
386
387 #define INT_EN                  (0x5C)
388 #define INT_EN_SW_INT_EN_               (0x80000000)  /* R/W */
389 #define INT_EN_TXSTOP_INT_EN_           (0x02000000)  /* R/W */
390 #define INT_EN_RXSTOP_INT_EN_           (0x01000000)  /* R/W */
391 #define INT_EN_RXDFH_INT_EN_            (0x00800000)  /* R/W */
392 //#define       INT_EN_RXDF_INT_EN_             (0x00400000)  /* R/W */
393 #define INT_EN_TIOC_INT_EN_             (0x00200000)  /* R/W */
394 #define INT_EN_RXD_INT_EN_              (0x00100000)  /* R/W */
395 #define INT_EN_GPT_INT_EN_              (0x00080000)  /* R/W */
396 #define INT_EN_PHY_INT_EN_              (0x00040000)  /* R/W */
397 #define INT_EN_PME_INT_EN_              (0x00020000)  /* R/W */
398 #define INT_EN_TXSO_EN_                 (0x00010000)  /* R/W */
399 #define INT_EN_RWT_EN_                  (0x00008000)  /* R/W */
400 #define INT_EN_RXE_EN_                  (0x00004000)  /* R/W */
401 #define INT_EN_TXE_EN_                  (0x00002000)  /* R/W */
402 //#define       INT_EN_ERX_EN_                  (0x00001000)  /* R/W */
403 #define INT_EN_TDFU_EN_                 (0x00000800)  /* R/W */
404 #define INT_EN_TDFO_EN_                 (0x00000400)  /* R/W */
405 #define INT_EN_TDFA_EN_                 (0x00000200)  /* R/W */
406 #define INT_EN_TSFF_EN_                 (0x00000100)  /* R/W */
407 #define INT_EN_TSFL_EN_                 (0x00000080)  /* R/W */
408 //#define       INT_EN_RXDF_EN_                 (0x00000040)  /* R/W */
409 #define INT_EN_RDFO_EN_                 (0x00000040)  /* R/W */
410 #define INT_EN_RDFL_EN_                 (0x00000020)  /* R/W */
411 #define INT_EN_RSFF_EN_                 (0x00000010)  /* R/W */
412 #define INT_EN_RSFL_EN_                 (0x00000008)  /* R/W */
413 #define INT_EN_GPIO2_INT_               (0x00000004)  /* R/W */
414 #define INT_EN_GPIO1_INT_               (0x00000002)  /* R/W */
415 #define INT_EN_GPIO0_INT_               (0x00000001)  /* R/W */
416
417 #define BYTE_TEST               (0x64)
418 #define FIFO_INT                (0x68)
419 #define FIFO_INT_TX_AVAIL_LEVEL_        (0xFF000000)  /* R/W */
420 #define FIFO_INT_TX_STS_LEVEL_          (0x00FF0000)  /* R/W */
421 #define FIFO_INT_RX_AVAIL_LEVEL_        (0x0000FF00)  /* R/W */
422 #define FIFO_INT_RX_STS_LEVEL_          (0x000000FF)  /* R/W */
423
424 #define RX_CFG                  (0x6C)
425 #define RX_CFG_RX_END_ALGN_             (0xC0000000)  /* R/W */
426 #define         RX_CFG_RX_END_ALGN4_            (0x00000000)  /* R/W */
427 #define         RX_CFG_RX_END_ALGN16_           (0x40000000)  /* R/W */
428 #define         RX_CFG_RX_END_ALGN32_           (0x80000000)  /* R/W */
429 #define RX_CFG_RX_DMA_CNT_              (0x0FFF0000)  /* R/W */
430 #define RX_CFG_RX_DUMP_                 (0x00008000)  /* R/W */
431 #define RX_CFG_RXDOFF_                  (0x00001F00)  /* R/W */
432 //#define       RX_CFG_RXBAD_                   (0x00000001)  /* R/W */
433
434 #define TX_CFG                  (0x70)
435 //#define       TX_CFG_TX_DMA_LVL_              (0xE0000000)     /* R/W */
436 //#define       TX_CFG_TX_DMA_CNT_              (0x0FFF0000)     /* R/W Self Clearing */
437 #define TX_CFG_TXS_DUMP_                (0x00008000)  /* Self Clearing */
438 #define TX_CFG_TXD_DUMP_                (0x00004000)  /* Self Clearing */
439 #define TX_CFG_TXSAO_                   (0x00000004)  /* R/W */
440 #define TX_CFG_TX_ON_                   (0x00000002)  /* R/W */
441 #define TX_CFG_STOP_TX_                 (0x00000001)  /* Self Clearing */
442
443 #define HW_CFG                  (0x74)
444 #define HW_CFG_TTM_                     (0x00200000)  /* R/W */
445 #define HW_CFG_SF_                      (0x00100000)  /* R/W */
446 #define HW_CFG_TX_FIF_SZ_               (0x000F0000)  /* R/W */
447 #define HW_CFG_TR_                      (0x00003000)  /* R/W */
448 #define HW_CFG_PHY_CLK_SEL_             (0x00000060)  /* R/W */
449 #define          HW_CFG_PHY_CLK_SEL_INT_PHY_    (0x00000000) /* R/W */
450 #define          HW_CFG_PHY_CLK_SEL_EXT_PHY_    (0x00000020) /* R/W */
451 #define          HW_CFG_PHY_CLK_SEL_CLK_DIS_    (0x00000040) /* R/W */
452 #define HW_CFG_SMI_SEL_                 (0x00000010)  /* R/W */
453 #define HW_CFG_EXT_PHY_DET_             (0x00000008)  /* RO */
454 #define HW_CFG_EXT_PHY_EN_              (0x00000004)  /* R/W */
455 #define HW_CFG_32_16_BIT_MODE_          (0x00000004)  /* RO */
456 #define HW_CFG_SRST_TO_                 (0x00000002)  /* RO */
457 #define HW_CFG_SRST_                    (0x00000001)  /* Self Clearing */
458
459 #define RX_DP_CTRL              (0x78)
460 #define RX_DP_CTRL_RX_FFWD_             (0x80000000)  /* R/W */
461 #define RX_DP_CTRL_FFWD_BUSY_           (0x80000000)  /* RO */
462
463 #define RX_FIFO_INF             (0x7C)
464 #define  RX_FIFO_INF_RXSUSED_           (0x00FF0000)  /* RO */
465 #define  RX_FIFO_INF_RXDUSED_           (0x0000FFFF)  /* RO */
466
467 #define TX_FIFO_INF             (0x80)
468 #define TX_FIFO_INF_TSUSED_             (0x00FF0000)  /* RO */
469 #define TX_FIFO_INF_TDFREE_             (0x0000FFFF)  /* RO */
470
471 #define PMT_CTRL                (0x84)
472 #define PMT_CTRL_PM_MODE_               (0x00003000)  /* Self Clearing */
473 #define PMT_CTRL_PHY_RST_               (0x00000400)  /* Self Clearing */
474 #define PMT_CTRL_WOL_EN_                (0x00000200)  /* R/W */
475 #define PMT_CTRL_ED_EN_                 (0x00000100)  /* R/W */
476 #define PMT_CTRL_PME_TYPE_              (0x00000040)  /* R/W Not Affected by SW Reset */
477 #define PMT_CTRL_WUPS_                  (0x00000030)  /* R/WC */
478 #define         PMT_CTRL_WUPS_NOWAKE_           (0x00000000)  /* R/WC */
479 #define         PMT_CTRL_WUPS_ED_               (0x00000010)  /* R/WC */
480 #define         PMT_CTRL_WUPS_WOL_              (0x00000020)  /* R/WC */
481 #define         PMT_CTRL_WUPS_MULTI_            (0x00000030)  /* R/WC */
482 #define PMT_CTRL_PME_IND_               (0x00000008)  /* R/W */
483 #define PMT_CTRL_PME_POL_               (0x00000004)  /* R/W */
484 #define PMT_CTRL_PME_EN_                (0x00000002)  /* R/W Not Affected by SW Reset */
485 #define PMT_CTRL_READY_                 (0x00000001)  /* RO */
486
487 #define GPIO_CFG                (0x88)
488 #define GPIO_CFG_LED3_EN_               (0x40000000)  /* R/W */
489 #define GPIO_CFG_LED2_EN_               (0x20000000)  /* R/W */
490 #define GPIO_CFG_LED1_EN_               (0x10000000)  /* R/W */
491 #define GPIO_CFG_GPIO2_INT_POL_         (0x04000000)  /* R/W */
492 #define GPIO_CFG_GPIO1_INT_POL_         (0x02000000)  /* R/W */
493 #define GPIO_CFG_GPIO0_INT_POL_         (0x01000000)  /* R/W */
494 #define GPIO_CFG_EEPR_EN_               (0x00700000)  /* R/W */
495 #define GPIO_CFG_GPIOBUF2_              (0x00040000)  /* R/W */
496 #define GPIO_CFG_GPIOBUF1_              (0x00020000)  /* R/W */
497 #define GPIO_CFG_GPIOBUF0_              (0x00010000)  /* R/W */
498 #define GPIO_CFG_GPIODIR2_              (0x00000400)  /* R/W */
499 #define GPIO_CFG_GPIODIR1_              (0x00000200)  /* R/W */
500 #define GPIO_CFG_GPIODIR0_              (0x00000100)  /* R/W */
501 #define GPIO_CFG_GPIOD4_                (0x00000010)  /* R/W */
502 #define GPIO_CFG_GPIOD3_                (0x00000008)  /* R/W */
503 #define GPIO_CFG_GPIOD2_                (0x00000004)  /* R/W */
504 #define GPIO_CFG_GPIOD1_                (0x00000002)  /* R/W */
505 #define GPIO_CFG_GPIOD0_                (0x00000001)  /* R/W */
506
507 #define GPT_CFG                 (0x8C)
508 #define GPT_CFG_TIMER_EN_               (0x20000000)  /* R/W */
509 #define GPT_CFG_GPT_LOAD_               (0x0000FFFF)  /* R/W */
510
511 #define GPT_CNT                 (0x90)
512 #define GPT_CNT_GPT_CNT_                (0x0000FFFF)  /* RO */
513
514 #define ENDIAN                  (0x98)
515 #define FREE_RUN                (0x9C)
516 #define RX_DROP                 (0xA0)
517 #define MAC_CSR_CMD             (0xA4)
518 #define  MAC_CSR_CMD_CSR_BUSY_          (0x80000000)  /* Self Clearing */
519 #define  MAC_CSR_CMD_R_NOT_W_           (0x40000000)  /* R/W */
520 #define  MAC_CSR_CMD_CSR_ADDR_          (0x000000FF)  /* R/W */
521
522 #define MAC_CSR_DATA            (0xA8)
523 #define AFC_CFG                 (0xAC)
524 #define         AFC_CFG_AFC_HI_                 (0x00FF0000)  /* R/W */
525 #define         AFC_CFG_AFC_LO_                 (0x0000FF00)  /* R/W */
526 #define         AFC_CFG_BACK_DUR_               (0x000000F0)  /* R/W */
527 #define         AFC_CFG_FCMULT_                 (0x00000008)  /* R/W */
528 #define         AFC_CFG_FCBRD_                  (0x00000004)  /* R/W */
529 #define         AFC_CFG_FCADD_                  (0x00000002)  /* R/W */
530 #define         AFC_CFG_FCANY_                  (0x00000001)  /* R/W */
531
532 #define E2P_CMD                 (0xB0)
533 #define E2P_CMD_EPC_BUSY_               (0x80000000)  /* Self Clearing */
534 #define E2P_CMD_EPC_CMD_                        (0x70000000)  /* R/W */
535 #define         E2P_CMD_EPC_CMD_READ_           (0x00000000)  /* R/W */
536 #define         E2P_CMD_EPC_CMD_EWDS_           (0x10000000)  /* R/W */
537 #define         E2P_CMD_EPC_CMD_EWEN_           (0x20000000)  /* R/W */
538 #define         E2P_CMD_EPC_CMD_WRITE_          (0x30000000)  /* R/W */
539 #define         E2P_CMD_EPC_CMD_WRAL_           (0x40000000)  /* R/W */
540 #define         E2P_CMD_EPC_CMD_ERASE_          (0x50000000)  /* R/W */
541 #define         E2P_CMD_EPC_CMD_ERAL_           (0x60000000)  /* R/W */
542 #define         E2P_CMD_EPC_CMD_RELOAD_         (0x70000000)  /* R/W */
543 #define E2P_CMD_EPC_TIMEOUT_            (0x00000200)  /* RO */
544 #define E2P_CMD_MAC_ADDR_LOADED_        (0x00000100)  /* RO */
545 #define E2P_CMD_EPC_ADDR_               (0x000000FF)  /* R/W */
546
547 #define E2P_DATA                (0xB4)
548 #define E2P_DATA_EEPROM_DATA_           (0x000000FF)  /* R/W */
549 /* end of LAN register offsets and bit definitions */
550
551 /*
552  ****************************************************************************
553  ****************************************************************************
554  * MAC Control and Status Register (Indirect Address)
555  * Offset (through the MAC_CSR CMD and DATA port)
556  ****************************************************************************
557  ****************************************************************************
558  *
559  */
560 #define MAC_CR                  (0x01)  /* R/W */
561
562 /* MAC_CR - MAC Control Register */
563 #define MAC_CR_RXALL_                   (0x80000000)
564 // TODO: delete this bit? It is not described in the data sheet.
565 #define MAC_CR_HBDIS_                   (0x10000000)
566 #define MAC_CR_RCVOWN_                  (0x00800000)
567 #define MAC_CR_LOOPBK_                  (0x00200000)
568 #define MAC_CR_FDPX_                    (0x00100000)
569 #define MAC_CR_MCPAS_                   (0x00080000)
570 #define MAC_CR_PRMS_                    (0x00040000)
571 #define MAC_CR_INVFILT_                 (0x00020000)
572 #define MAC_CR_PASSBAD_                 (0x00010000)
573 #define MAC_CR_HFILT_                   (0x00008000)
574 #define MAC_CR_HPFILT_                  (0x00002000)
575 #define MAC_CR_LCOLL_                   (0x00001000)
576 #define MAC_CR_BCAST_                   (0x00000800)
577 #define MAC_CR_DISRTY_                  (0x00000400)
578 #define MAC_CR_PADSTR_                  (0x00000100)
579 #define MAC_CR_BOLMT_MASK_              (0x000000C0)
580 #define MAC_CR_DFCHK_                   (0x00000020)
581 #define MAC_CR_TXEN_                    (0x00000008)
582 #define MAC_CR_RXEN_                    (0x00000004)
583
584 #define ADDRH                   (0x02)    /* R/W mask 0x0000FFFFUL */
585 #define ADDRL                   (0x03)    /* R/W mask 0xFFFFFFFFUL */
586 #define HASHH                   (0x04)    /* R/W */
587 #define HASHL                   (0x05)    /* R/W */
588
589 #define MII_ACC                 (0x06)    /* R/W */
590 #define MII_ACC_PHY_ADDR_               (0x0000F800)
591 #define MII_ACC_MIIRINDA_               (0x000007C0)
592 #define MII_ACC_MII_WRITE_              (0x00000002)
593 #define MII_ACC_MII_BUSY_               (0x00000001)
594
595 #define MII_DATA                (0x07)    /* R/W mask 0x0000FFFFUL */
596
597 #define FLOW                    (0x08)    /* R/W */
598 #define FLOW_FCPT_                      (0xFFFF0000)
599 #define FLOW_FCPASS_                    (0x00000004)
600 #define FLOW_FCEN_                      (0x00000002)
601 #define FLOW_FCBSY_                     (0x00000001)
602
603 #define VLAN1                   (0x09)    /* R/W mask 0x0000FFFFUL */
604 #define VLAN1_VTI1_                     (0x0000ffff)
605
606 #define VLAN2                   (0x0A)    /* R/W mask 0x0000FFFFUL */
607 #define VLAN2_VTI2_                     (0x0000ffff)
608
609 #define WUFF                    (0x0B)    /* WO */
610
611 #define WUCSR                   (0x0C)    /* R/W */
612 #define WUCSR_GUE_                      (0x00000200)
613 #define WUCSR_WUFR_                     (0x00000040)
614 #define WUCSR_MPR_                      (0x00000020)
615 #define WUCSR_WAKE_EN_                  (0x00000004)
616 #define WUCSR_MPEN_                     (0x00000002)
617
618 /*
619  ****************************************************************************
620  * Chip Specific MII Defines
621  ****************************************************************************
622  *
623  * Phy register offsets and bit definitions
624  *
625  */
626
627 #define PHY_MODE_CTRL_STS       ((u32)17)       /* Mode Control/Status Register */
628 //#define MODE_CTRL_STS_FASTRIP_          ((u16)0x4000)
629 #define MODE_CTRL_STS_EDPWRDOWN_         ((u16)0x2000)
630 //#define MODE_CTRL_STS_LOWSQEN_           ((u16)0x0800)
631 //#define MODE_CTRL_STS_MDPREBP_           ((u16)0x0400)
632 //#define MODE_CTRL_STS_FARLOOPBACK_  ((u16)0x0200)
633 //#define MODE_CTRL_STS_FASTEST_           ((u16)0x0100)
634 //#define MODE_CTRL_STS_REFCLKEN_          ((u16)0x0010)
635 //#define MODE_CTRL_STS_PHYADBP_           ((u16)0x0008)
636 //#define MODE_CTRL_STS_FORCE_G_LINK_ ((u16)0x0004)
637 #define MODE_CTRL_STS_ENERGYON_         ((u16)0x0002)
638
639 #define PHY_INT_SRC                     ((u32)29)
640 #define PHY_INT_SRC_ENERGY_ON_                  ((u16)0x0080)
641 #define PHY_INT_SRC_ANEG_COMP_                  ((u16)0x0040)
642 #define PHY_INT_SRC_REMOTE_FAULT_               ((u16)0x0020)
643 #define PHY_INT_SRC_LINK_DOWN_                  ((u16)0x0010)
644 #define PHY_INT_SRC_ANEG_LP_ACK_                ((u16)0x0008)
645 #define PHY_INT_SRC_PAR_DET_FAULT_              ((u16)0x0004)
646 #define PHY_INT_SRC_ANEG_PGRX_                  ((u16)0x0002)
647
648 #define PHY_INT_MASK                    ((u32)30)
649 #define PHY_INT_MASK_ENERGY_ON_                 ((u16)0x0080)
650 #define PHY_INT_MASK_ANEG_COMP_                 ((u16)0x0040)
651 #define PHY_INT_MASK_REMOTE_FAULT_              ((u16)0x0020)
652 #define PHY_INT_MASK_LINK_DOWN_                 ((u16)0x0010)
653 #define PHY_INT_MASK_ANEG_LP_ACK_               ((u16)0x0008)
654 #define PHY_INT_MASK_PAR_DET_FAULT_             ((u16)0x0004)
655 #define PHY_INT_MASK_ANEG_PGRX_                 ((u16)0x0002)
656
657 #define PHY_SPECIAL                     ((u32)31)
658 #define PHY_SPECIAL_ANEG_DONE_                  ((u16)0x1000)
659 #define PHY_SPECIAL_RES_                        ((u16)0x0040)
660 #define PHY_SPECIAL_RES_MASK_                   ((u16)0x0FE1)
661 #define PHY_SPECIAL_SPD_                        ((u16)0x001C)
662 #define PHY_SPECIAL_SPD_10HALF_                 ((u16)0x0004)
663 #define PHY_SPECIAL_SPD_10FULL_                 ((u16)0x0014)
664 #define PHY_SPECIAL_SPD_100HALF_                ((u16)0x0008)
665 #define PHY_SPECIAL_SPD_100FULL_                ((u16)0x0018)
666
667 #define LAN911X_INTERNAL_PHY_ID         (0x0007C000)
668
669 /* Chip ID values */
670 #define CHIP_9115       0x115
671 #define CHIP_9116       0x116
672 #define CHIP_9117       0x117
673 #define CHIP_9118       0x118
674
675 struct chip_id {
676         u16 id;
677         char *name;
678 };
679
680 static const struct chip_id chip_ids[] =  {
681         { CHIP_9115, "LAN9115" },
682         { CHIP_9116, "LAN9116" },
683         { CHIP_9117, "LAN9117" },
684         { CHIP_9118, "LAN9118" },
685         { 0, NULL },
686 };
687
688 #define IS_REV_A(x)     ((x & 0xFFFF)==0)
689
690 /*
691  * Macros to abstract register access according to the data bus
692  * capabilities.  Please use those and not the in/out primitives.
693  */
694 /* FIFO read/write macros */
695 #define SMC_PUSH_DATA(lp, p, l) SMC_outsl( lp, TX_DATA_FIFO, p, (l) >> 2 )
696 #define SMC_PULL_DATA(lp, p, l) SMC_insl ( lp, RX_DATA_FIFO, p, (l) >> 2 )
697 #define SMC_SET_TX_FIFO(lp, x)  SMC_outl( x, lp, TX_DATA_FIFO )
698 #define SMC_GET_RX_FIFO(lp)     SMC_inl( lp, RX_DATA_FIFO )
699
700
701 /* I/O mapped register read/write macros */
702 #define SMC_GET_TX_STS_FIFO(lp)         SMC_inl( lp, TX_STATUS_FIFO )
703 #define SMC_GET_RX_STS_FIFO(lp)         SMC_inl( lp, RX_STATUS_FIFO )
704 #define SMC_GET_RX_STS_FIFO_PEEK(lp)    SMC_inl( lp, RX_STATUS_FIFO_PEEK )
705 #define SMC_GET_PN(lp)                  (SMC_inl( lp, ID_REV ) >> 16)
706 #define SMC_GET_REV(lp)                 (SMC_inl( lp, ID_REV ) & 0xFFFF)
707 #define SMC_GET_IRQ_CFG(lp)             SMC_inl( lp, INT_CFG )
708 #define SMC_SET_IRQ_CFG(lp, x)          SMC_outl( x, lp, INT_CFG )
709 #define SMC_GET_INT(lp)                 SMC_inl( lp, INT_STS )
710 #define SMC_ACK_INT(lp, x)                      SMC_outl( x, lp, INT_STS )
711 #define SMC_GET_INT_EN(lp)              SMC_inl( lp, INT_EN )
712 #define SMC_SET_INT_EN(lp, x)           SMC_outl( x, lp, INT_EN )
713 #define SMC_GET_BYTE_TEST(lp)           SMC_inl( lp, BYTE_TEST )
714 #define SMC_SET_BYTE_TEST(lp, x)                SMC_outl( x, lp, BYTE_TEST )
715 #define SMC_GET_FIFO_INT(lp)            SMC_inl( lp, FIFO_INT )
716 #define SMC_SET_FIFO_INT(lp, x)         SMC_outl( x, lp, FIFO_INT )
717 #define SMC_SET_FIFO_TDA(lp, x)                                 \
718         do {                                                    \
719                 unsigned long __flags;                          \
720                 int __mask;                                     \
721                 local_irq_save(__flags);                        \
722                 __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<24);  \
723                 SMC_SET_FIFO_INT( (lp), __mask | (x)<<24 );     \
724                 local_irq_restore(__flags);                     \
725         } while (0)
726 #define SMC_SET_FIFO_TSL(lp, x)                                 \
727         do {                                                    \
728                 unsigned long __flags;                          \
729                 int __mask;                                     \
730                 local_irq_save(__flags);                        \
731                 __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<16);  \
732                 SMC_SET_FIFO_INT( (lp), __mask | (((x) & 0xFF)<<16));   \
733                 local_irq_restore(__flags);                     \
734         } while (0)
735 #define SMC_SET_FIFO_RSA(lp, x)                                 \
736         do {                                                    \
737                 unsigned long __flags;                          \
738                 int __mask;                                     \
739                 local_irq_save(__flags);                        \
740                 __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<8);   \
741                 SMC_SET_FIFO_INT( (lp), __mask | (((x) & 0xFF)<<8));    \
742                 local_irq_restore(__flags);                     \
743         } while (0)
744 #define SMC_SET_FIFO_RSL(lp, x)                                 \
745         do {                                                    \
746                 unsigned long __flags;                          \
747                 int __mask;                                     \
748                 local_irq_save(__flags);                        \
749                 __mask = SMC_GET_FIFO_INT((lp)) & ~0xFF;        \
750                 SMC_SET_FIFO_INT( (lp),__mask | ((x) & 0xFF));  \
751                 local_irq_restore(__flags);                     \
752         } while (0)
753 #define SMC_GET_RX_CFG(lp)              SMC_inl( lp, RX_CFG )
754 #define SMC_SET_RX_CFG(lp, x)           SMC_outl( x, lp, RX_CFG )
755 #define SMC_GET_TX_CFG(lp)              SMC_inl( lp, TX_CFG )
756 #define SMC_SET_TX_CFG(lp, x)           SMC_outl( x, lp, TX_CFG )
757 #define SMC_GET_HW_CFG(lp)              SMC_inl( lp, HW_CFG )
758 #define SMC_SET_HW_CFG(lp, x)           SMC_outl( x, lp, HW_CFG )
759 #define SMC_GET_RX_DP_CTRL(lp)          SMC_inl( lp, RX_DP_CTRL )
760 #define SMC_SET_RX_DP_CTRL(lp, x)               SMC_outl( x, lp, RX_DP_CTRL )
761 #define SMC_GET_PMT_CTRL(lp)            SMC_inl( lp, PMT_CTRL )
762 #define SMC_SET_PMT_CTRL(lp, x)         SMC_outl( x, lp, PMT_CTRL )
763 #define SMC_GET_GPIO_CFG(lp)            SMC_inl( lp, GPIO_CFG )
764 #define SMC_SET_GPIO_CFG(lp, x)         SMC_outl( x, lp, GPIO_CFG )
765 #define SMC_GET_RX_FIFO_INF(lp)         SMC_inl( lp, RX_FIFO_INF )
766 #define SMC_SET_RX_FIFO_INF(lp, x)              SMC_outl( x, lp, RX_FIFO_INF )
767 #define SMC_GET_TX_FIFO_INF(lp)         SMC_inl( lp, TX_FIFO_INF )
768 #define SMC_SET_TX_FIFO_INF(lp, x)              SMC_outl( x, lp, TX_FIFO_INF )
769 #define SMC_GET_GPT_CFG(lp)             SMC_inl( lp, GPT_CFG )
770 #define SMC_SET_GPT_CFG(lp, x)          SMC_outl( x, lp, GPT_CFG )
771 #define SMC_GET_RX_DROP(lp)             SMC_inl( lp, RX_DROP )
772 #define SMC_SET_RX_DROP(lp, x)          SMC_outl( x, lp, RX_DROP )
773 #define SMC_GET_MAC_CMD(lp)             SMC_inl( lp, MAC_CSR_CMD )
774 #define SMC_SET_MAC_CMD(lp, x)          SMC_outl( x, lp, MAC_CSR_CMD )
775 #define SMC_GET_MAC_DATA(lp)            SMC_inl( lp, MAC_CSR_DATA )
776 #define SMC_SET_MAC_DATA(lp, x)         SMC_outl( x, lp, MAC_CSR_DATA )
777 #define SMC_GET_AFC_CFG(lp)             SMC_inl( lp, AFC_CFG )
778 #define SMC_SET_AFC_CFG(lp, x)          SMC_outl( x, lp, AFC_CFG )
779 #define SMC_GET_E2P_CMD(lp)             SMC_inl( lp, E2P_CMD )
780 #define SMC_SET_E2P_CMD(lp, x)          SMC_outl( x, lp, E2P_CMD )
781 #define SMC_GET_E2P_DATA(lp)            SMC_inl( lp, E2P_DATA )
782 #define SMC_SET_E2P_DATA(lp, x)         SMC_outl( x, lp, E2P_DATA )
783
784 /* MAC register read/write macros */
785 #define SMC_GET_MAC_CSR(lp,a,v)                                         \
786         do {                                                            \
787                 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_);  \
788                 SMC_SET_MAC_CMD((lp),MAC_CSR_CMD_CSR_BUSY_ |            \
789                         MAC_CSR_CMD_R_NOT_W_ | (a) );                   \
790                 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_);  \
791                 v = SMC_GET_MAC_DATA((lp));                             \
792         } while (0)
793 #define SMC_SET_MAC_CSR(lp,a,v)                                         \
794         do {                                                            \
795                 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_);  \
796                 SMC_SET_MAC_DATA((lp), v);                              \
797                 SMC_SET_MAC_CMD((lp), MAC_CSR_CMD_CSR_BUSY_ | (a) );    \
798                 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_);  \
799         } while (0)
800 #define SMC_GET_MAC_CR(lp, x)   SMC_GET_MAC_CSR( (lp), MAC_CR, x )
801 #define SMC_SET_MAC_CR(lp, x)   SMC_SET_MAC_CSR( (lp), MAC_CR, x )
802 #define SMC_GET_ADDRH(lp, x)    SMC_GET_MAC_CSR( (lp), ADDRH, x )
803 #define SMC_SET_ADDRH(lp, x)    SMC_SET_MAC_CSR( (lp), ADDRH, x )
804 #define SMC_GET_ADDRL(lp, x)    SMC_GET_MAC_CSR( (lp), ADDRL, x )
805 #define SMC_SET_ADDRL(lp, x)    SMC_SET_MAC_CSR( (lp), ADDRL, x )
806 #define SMC_GET_HASHH(lp, x)    SMC_GET_MAC_CSR( (lp), HASHH, x )
807 #define SMC_SET_HASHH(lp, x)    SMC_SET_MAC_CSR( (lp), HASHH, x )
808 #define SMC_GET_HASHL(lp, x)    SMC_GET_MAC_CSR( (lp), HASHL, x )
809 #define SMC_SET_HASHL(lp, x)    SMC_SET_MAC_CSR( (lp), HASHL, x )
810 #define SMC_GET_MII_ACC(lp, x)  SMC_GET_MAC_CSR( (lp), MII_ACC, x )
811 #define SMC_SET_MII_ACC(lp, x)  SMC_SET_MAC_CSR( (lp), MII_ACC, x )
812 #define SMC_GET_MII_DATA(lp, x) SMC_GET_MAC_CSR( (lp), MII_DATA, x )
813 #define SMC_SET_MII_DATA(lp, x) SMC_SET_MAC_CSR( (lp), MII_DATA, x )
814 #define SMC_GET_FLOW(lp, x)             SMC_GET_MAC_CSR( (lp), FLOW, x )
815 #define SMC_SET_FLOW(lp, x)             SMC_SET_MAC_CSR( (lp), FLOW, x )
816 #define SMC_GET_VLAN1(lp, x)    SMC_GET_MAC_CSR( (lp), VLAN1, x )
817 #define SMC_SET_VLAN1(lp, x)    SMC_SET_MAC_CSR( (lp), VLAN1, x )
818 #define SMC_GET_VLAN2(lp, x)    SMC_GET_MAC_CSR( (lp), VLAN2, x )
819 #define SMC_SET_VLAN2(lp, x)    SMC_SET_MAC_CSR( (lp), VLAN2, x )
820 #define SMC_SET_WUFF(lp, x)             SMC_SET_MAC_CSR( (lp), WUFF, x )
821 #define SMC_GET_WUCSR(lp, x)    SMC_GET_MAC_CSR( (lp), WUCSR, x )
822 #define SMC_SET_WUCSR(lp, x)    SMC_SET_MAC_CSR( (lp), WUCSR, x )
823
824 /* PHY register read/write macros */
825 #define SMC_GET_MII(lp,a,phy,v)                                 \
826         do {                                                    \
827                 u32 __v;                                        \
828                 do {                                            \
829                         SMC_GET_MII_ACC((lp), __v);                     \
830                 } while ( __v & MII_ACC_MII_BUSY_ );            \
831                 SMC_SET_MII_ACC( (lp), ((phy)<<11) | ((a)<<6) | \
832                         MII_ACC_MII_BUSY_);                     \
833                 do {                                            \
834                         SMC_GET_MII_ACC( (lp), __v);                    \
835                 } while ( __v & MII_ACC_MII_BUSY_ );            \
836                 SMC_GET_MII_DATA((lp), v);                              \
837         } while (0)
838 #define SMC_SET_MII(lp,a,phy,v)                                 \
839         do {                                                    \
840                 u32 __v;                                        \
841                 do {                                            \
842                         SMC_GET_MII_ACC((lp), __v);                     \
843                 } while ( __v & MII_ACC_MII_BUSY_ );            \
844                 SMC_SET_MII_DATA((lp), v);                              \
845                 SMC_SET_MII_ACC( (lp), ((phy)<<11) | ((a)<<6) | \
846                         MII_ACC_MII_BUSY_        |              \
847                         MII_ACC_MII_WRITE_  );                  \
848                 do {                                            \
849                         SMC_GET_MII_ACC((lp), __v);                     \
850                 } while ( __v & MII_ACC_MII_BUSY_ );            \
851         } while (0)
852 #define SMC_GET_PHY_BMCR(lp,phy,x)              SMC_GET_MII( (lp), MII_BMCR, phy, x )
853 #define SMC_SET_PHY_BMCR(lp,phy,x)              SMC_SET_MII( (lp), MII_BMCR, phy, x )
854 #define SMC_GET_PHY_BMSR(lp,phy,x)              SMC_GET_MII( (lp), MII_BMSR, phy, x )
855 #define SMC_GET_PHY_ID1(lp,phy,x)               SMC_GET_MII( (lp), MII_PHYSID1, phy, x )
856 #define SMC_GET_PHY_ID2(lp,phy,x)               SMC_GET_MII( (lp), MII_PHYSID2, phy, x )
857 #define SMC_GET_PHY_MII_ADV(lp,phy,x)   SMC_GET_MII( (lp), MII_ADVERTISE, phy, x )
858 #define SMC_SET_PHY_MII_ADV(lp,phy,x)   SMC_SET_MII( (lp), MII_ADVERTISE, phy, x )
859 #define SMC_GET_PHY_MII_LPA(lp,phy,x)   SMC_GET_MII( (lp), MII_LPA, phy, x )
860 #define SMC_SET_PHY_MII_LPA(lp,phy,x)   SMC_SET_MII( (lp), MII_LPA, phy, x )
861 #define SMC_GET_PHY_CTRL_STS(lp,phy,x)  SMC_GET_MII( (lp), PHY_MODE_CTRL_STS, phy, x )
862 #define SMC_SET_PHY_CTRL_STS(lp,phy,x)  SMC_SET_MII( (lp), PHY_MODE_CTRL_STS, phy, x )
863 #define SMC_GET_PHY_INT_SRC(lp,phy,x)   SMC_GET_MII( (lp), PHY_INT_SRC, phy, x )
864 #define SMC_SET_PHY_INT_SRC(lp,phy,x)   SMC_SET_MII( (lp), PHY_INT_SRC, phy, x )
865 #define SMC_GET_PHY_INT_MASK(lp,phy,x)  SMC_GET_MII( (lp), PHY_INT_MASK, phy, x )
866 #define SMC_SET_PHY_INT_MASK(lp,phy,x)  SMC_SET_MII( (lp), PHY_INT_MASK, phy, x )
867 #define SMC_GET_PHY_SPECIAL(lp,phy,x)   SMC_GET_MII( (lp), PHY_SPECIAL, phy, x )
868
869
870
871 /* Misc read/write macros */
872
873 #ifndef SMC_GET_MAC_ADDR
874 #define SMC_GET_MAC_ADDR(lp, addr)                              \
875         do {                                                    \
876                 unsigned int __v;                               \
877                                                                 \
878                 SMC_GET_MAC_CSR((lp), ADDRL, __v);                      \
879                 addr[0] = __v; addr[1] = __v >> 8;              \
880                 addr[2] = __v >> 16; addr[3] = __v >> 24;       \
881                 SMC_GET_MAC_CSR((lp), ADDRH, __v);                      \
882                 addr[4] = __v; addr[5] = __v >> 8;              \
883         } while (0)
884 #endif
885
886 #define SMC_SET_MAC_ADDR(lp, addr)                              \
887         do {                                                    \
888                  SMC_SET_MAC_CSR((lp), ADDRL,                           \
889                                  addr[0] |                      \
890                                 (addr[1] << 8) |                \
891                                 (addr[2] << 16) |               \
892                                 (addr[3] << 24));               \
893                  SMC_SET_MAC_CSR((lp), ADDRH, addr[4]|(addr[5] << 8));\
894         } while (0)
895
896
897 #define SMC_WRITE_EEPROM_CMD(lp, cmd, addr)                             \
898         do {                                                            \
899                 while (SMC_GET_E2P_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_);  \
900                 SMC_SET_MAC_CMD((lp), MAC_CSR_CMD_R_NOT_W_ | a );               \
901                 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_);  \
902         } while (0)
903
904 #endif   /* _SMC911X_H_ */