2 sis190.c: Silicon Integrated Systems SiS190 ethernet driver
4 Copyright (c) 2003 K.M. Liu <kmliu@sis.com>
5 Copyright (c) 2003, 2004 Jeff Garzik <jgarzik@pobox.com>
6 Copyright (c) 2003, 2004, 2005 Francois Romieu <romieu@fr.zoreil.com>
8 Based on r8169.c, tg3.c, 8139cp.c, skge.c, epic100.c and SiS 190/191
11 This software may be used and distributed according to the terms of
12 the GNU General Public License (GPL), incorporated herein by reference.
13 Drivers based on or derived from this code fall under the GPL and must
14 retain the authorship, copyright and license notice. This file is not
15 a complete program and may only be used when the entire operating
16 system is licensed under the GPL.
18 See the file COPYING in this distribution for more information.
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/netdevice.h>
25 #include <linux/rtnetlink.h>
26 #include <linux/etherdevice.h>
27 #include <linux/ethtool.h>
28 #include <linux/pci.h>
29 #include <linux/mii.h>
30 #include <linux/delay.h>
31 #include <linux/crc32.h>
32 #include <linux/dma-mapping.h>
35 #define net_drv(p, arg...) if (netif_msg_drv(p)) \
37 #define net_probe(p, arg...) if (netif_msg_probe(p)) \
39 #define net_link(p, arg...) if (netif_msg_link(p)) \
41 #define net_intr(p, arg...) if (netif_msg_intr(p)) \
43 #define net_tx_err(p, arg...) if (netif_msg_tx_err(p)) \
46 #define PHY_MAX_ADDR 32
47 #define PHY_ID_ANY 0x1f
48 #define MII_REG_ANY 0x1f
50 #ifdef CONFIG_SIS190_NAPI
51 #define NAPI_SUFFIX "-NAPI"
53 #define NAPI_SUFFIX ""
56 #define DRV_VERSION "1.2" NAPI_SUFFIX
57 #define DRV_NAME "sis190"
58 #define SIS190_DRIVER_NAME DRV_NAME " Gigabit Ethernet driver " DRV_VERSION
59 #define PFX DRV_NAME ": "
61 #ifdef CONFIG_SIS190_NAPI
62 #define sis190_rx_skb netif_receive_skb
63 #define sis190_rx_quota(count, quota) min(count, quota)
65 #define sis190_rx_skb netif_rx
66 #define sis190_rx_quota(count, quota) count
69 #define MAC_ADDR_LEN 6
71 #define NUM_TX_DESC 64 /* [8..1024] */
72 #define NUM_RX_DESC 64 /* [8..8192] */
73 #define TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
74 #define RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
75 #define RX_BUF_SIZE 1536
76 #define RX_BUF_MASK 0xfff8
78 #define SIS190_REGS_SIZE 0x80
79 #define SIS190_TX_TIMEOUT (6*HZ)
80 #define SIS190_PHY_TIMEOUT (10*HZ)
81 #define SIS190_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
82 NETIF_MSG_LINK | NETIF_MSG_IFUP | \
85 /* Enhanced PHY access register bit definitions */
86 #define EhnMIIread 0x0000
87 #define EhnMIIwrite 0x0020
88 #define EhnMIIdataShift 16
89 #define EhnMIIpmdShift 6 /* 7016 only */
90 #define EhnMIIregShift 11
91 #define EhnMIIreq 0x0010
92 #define EhnMIInotDone 0x0010
94 /* Write/read MMIO register */
95 #define SIS_W8(reg, val) writeb ((val), ioaddr + (reg))
96 #define SIS_W16(reg, val) writew ((val), ioaddr + (reg))
97 #define SIS_W32(reg, val) writel ((val), ioaddr + (reg))
98 #define SIS_R8(reg) readb (ioaddr + (reg))
99 #define SIS_R16(reg) readw (ioaddr + (reg))
100 #define SIS_R32(reg) readl (ioaddr + (reg))
102 #define SIS_PCI_COMMIT() SIS_R32(IntrControl)
104 enum sis190_registers {
106 TxDescStartAddr = 0x04,
107 rsv0 = 0x08, // reserved
108 TxSts = 0x0c, // unused (Control/Status)
110 RxDescStartAddr = 0x14,
111 rsv1 = 0x18, // reserved
112 RxSts = 0x1c, // unused
116 IntrTimer = 0x2c, // unused (Interupt Timer)
117 PMControl = 0x30, // unused (Power Mgmt Control/Status)
118 rsv2 = 0x34, // reserved
121 StationControl = 0x40,
123 GIoCR = 0x48, // unused (GMAC IO Compensation)
124 GIoCtrl = 0x4c, // unused (GMAC IO Control)
126 TxLimit = 0x54, // unused (Tx MAC Timer/TryLimit)
127 RGDelay = 0x58, // unused (RGMII Tx Internal Delay)
128 rsv3 = 0x5c, // reserved
132 // Undocumented = 0x6c,
134 RxWolData = 0x74, // unused (Rx WOL Data Access)
135 RxMPSControl = 0x78, // unused (Rx MPS Control)
136 rsv4 = 0x7c, // reserved
139 enum sis190_register_content {
141 SoftInt = 0x40000000, // unused
142 Timeup = 0x20000000, // unused
143 PauseFrame = 0x00080000, // unused
144 MagicPacket = 0x00040000, // unused
145 WakeupFrame = 0x00020000, // unused
146 LinkChange = 0x00010000,
147 RxQEmpty = 0x00000080,
149 TxQ1Empty = 0x00000020, // unused
150 TxQ1Int = 0x00000010,
151 TxQ0Empty = 0x00000008, // unused
152 TxQ0Int = 0x00000004,
158 CmdRxEnb = 0x08, // unused
160 RxBufEmpty = 0x01, // unused
163 Cfg9346_Lock = 0x00, // unused
164 Cfg9346_Unlock = 0xc0, // unused
167 AcceptErr = 0x20, // unused
168 AcceptRunt = 0x10, // unused
169 AcceptBroadcast = 0x0800,
170 AcceptMulticast = 0x0400,
171 AcceptMyPhys = 0x0200,
172 AcceptAllPhys = 0x0100,
176 RxCfgDMAShift = 8, // 0x1a in RxControl ?
179 TxInterFrameGapShift = 24,
180 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
190 LinkStatus = 0x02, // unused
191 FullDup = 0x01, // unused
194 TBILinkOK = 0x02000000, // unused
211 enum _DescStatusBit {
213 OWNbit = 0x80000000, // RXOWN/TXOWN
214 INTbit = 0x40000000, // RXINT/TXINT
215 CRCbit = 0x00020000, // CRCOFF/CRCEN
216 PADbit = 0x00010000, // PREADD/PADEN
218 RingEnd = 0x80000000,
220 LSEN = 0x08000000, // TSO ? -- FR
247 RxDescCountMask = 0x7f000000, // multi-desc pkt when > 1 ? -- FR
256 RxSizeMask = 0x0000ffff
258 * The asic could apparently do vlan, TSO, jumbo (sis191 only) and
259 * provide two (unused with Linux) Tx queues. No publically
260 * available documentation alas.
264 enum sis190_eeprom_access_register_bits {
265 EECS = 0x00000001, // unused
266 EECLK = 0x00000002, // unused
267 EEDO = 0x00000008, // unused
268 EEDI = 0x00000004, // unused
271 EEWOP = 0x00000100 // unused
274 /* EEPROM Addresses */
275 enum sis190_eeprom_address {
276 EEPROMSignature = 0x00,
277 EEPROMCLK = 0x01, // unused
282 struct sis190_private {
283 void __iomem *mmio_addr;
284 struct pci_dev *pci_dev;
285 struct net_device_stats stats;
294 struct RxDesc *RxDescRing;
295 struct TxDesc *TxDescRing;
296 struct sk_buff *Rx_skbuff[NUM_RX_DESC];
297 struct sk_buff *Tx_skbuff[NUM_TX_DESC];
298 struct work_struct phy_task;
299 struct timer_list timer;
301 struct mii_if_info mii_if;
302 struct list_head first_phy;
306 struct list_head list;
313 enum sis190_phy_type {
320 static struct mii_chip_info {
324 } mii_chip_table[] = {
325 { "Broadcom PHY BCM5461", { 0x0020, 0x60c0 }, LAN },
326 { "Agere PHY ET1101B", { 0x0282, 0xf010 }, LAN },
327 { "Marvell PHY 88E1111", { 0x0141, 0x0cc0 }, LAN },
328 { "Realtek PHY RTL8201", { 0x0000, 0x8200 }, LAN },
332 const static struct {
334 u8 version; /* depend on docs */
335 u32 RxConfigMask; /* clear the bits supported by this chip */
336 } sis_chip_info[] = {
337 { DRV_NAME, 0x00, 0xff7e1880, },
340 static struct pci_device_id sis190_pci_tbl[] __devinitdata = {
341 { PCI_DEVICE(PCI_VENDOR_ID_SI, 0x0190), 0, 0, 0 },
345 MODULE_DEVICE_TABLE(pci, sis190_pci_tbl);
347 static int rx_copybreak = 200;
353 MODULE_DESCRIPTION("SiS sis190 Gigabit Ethernet driver");
354 module_param(rx_copybreak, int, 0);
355 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
356 module_param_named(debug, debug.msg_enable, int, 0);
357 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
358 MODULE_AUTHOR("K.M. Liu <kmliu@sis.com>, Ueimor <romieu@fr.zoreil.com>");
359 MODULE_VERSION(DRV_VERSION);
360 MODULE_LICENSE("GPL");
362 static const u32 sis190_intr_mask =
363 RxQEmpty | RxQInt | TxQ1Int | TxQ0Int | RxHalt | TxHalt;
366 * Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
367 * The chips use a 64 element hash table based on the Ethernet CRC.
369 static int multicast_filter_limit = 32;
371 static void __mdio_cmd(void __iomem *ioaddr, u32 ctl)
375 SIS_W32(GMIIControl, ctl);
379 for (i = 0; i < 100; i++) {
380 if (!(SIS_R32(GMIIControl) & EhnMIInotDone))
386 printk(KERN_ERR PFX "PHY command failed !\n");
389 static void mdio_write(void __iomem *ioaddr, int phy_id, int reg, int val)
391 __mdio_cmd(ioaddr, EhnMIIreq | EhnMIIwrite |
392 (((u32) reg) << EhnMIIregShift) | (phy_id << EhnMIIpmdShift) |
393 (((u32) val) << EhnMIIdataShift));
396 static int mdio_read(void __iomem *ioaddr, int phy_id, int reg)
398 __mdio_cmd(ioaddr, EhnMIIreq | EhnMIIread |
399 (((u32) reg) << EhnMIIregShift) | (phy_id << EhnMIIpmdShift));
401 return (u16) (SIS_R32(GMIIControl) >> EhnMIIdataShift);
404 static void __mdio_write(struct net_device *dev, int phy_id, int reg, int val)
406 struct sis190_private *tp = netdev_priv(dev);
408 mdio_write(tp->mmio_addr, phy_id, reg, val);
411 static int __mdio_read(struct net_device *dev, int phy_id, int reg)
413 struct sis190_private *tp = netdev_priv(dev);
415 return mdio_read(tp->mmio_addr, phy_id, reg);
418 static u16 mdio_read_latched(void __iomem *ioaddr, int phy_id, int reg)
420 mdio_read(ioaddr, phy_id, reg);
421 return mdio_read(ioaddr, phy_id, reg);
424 static u16 __devinit sis190_read_eeprom(void __iomem *ioaddr, u32 reg)
429 if (!(SIS_R32(ROMControl) & 0x0002))
432 SIS_W32(ROMInterface, EEREQ | EEROP | (reg << 10));
434 for (i = 0; i < 200; i++) {
435 if (!(SIS_R32(ROMInterface) & EEREQ)) {
436 data = (SIS_R32(ROMInterface) & 0xffff0000) >> 16;
445 static void sis190_irq_mask_and_ack(void __iomem *ioaddr)
447 SIS_W32(IntrMask, 0x00);
448 SIS_W32(IntrStatus, 0xffffffff);
452 static void sis190_asic_down(void __iomem *ioaddr)
454 /* Stop the chip's Tx and Rx DMA processes. */
456 SIS_W32(TxControl, 0x1a00);
457 SIS_W32(RxControl, 0x1a00);
459 sis190_irq_mask_and_ack(ioaddr);
462 static void sis190_mark_as_last_descriptor(struct RxDesc *desc)
464 desc->size |= cpu_to_le32(RingEnd);
467 static inline void sis190_give_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
469 u32 eor = le32_to_cpu(desc->size) & RingEnd;
472 desc->size = cpu_to_le32((rx_buf_sz & RX_BUF_MASK) | eor);
474 desc->status = cpu_to_le32(OWNbit | INTbit);
477 static inline void sis190_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
480 desc->addr = cpu_to_le32(mapping);
481 sis190_give_to_asic(desc, rx_buf_sz);
484 static inline void sis190_make_unusable_by_asic(struct RxDesc *desc)
487 desc->addr = 0xdeadbeef;
488 desc->size &= cpu_to_le32(RingEnd);
493 static int sis190_alloc_rx_skb(struct pci_dev *pdev, struct sk_buff **sk_buff,
494 struct RxDesc *desc, u32 rx_buf_sz)
500 skb = dev_alloc_skb(rx_buf_sz);
506 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
509 sis190_map_to_asic(desc, mapping, rx_buf_sz);
515 sis190_make_unusable_by_asic(desc);
519 static u32 sis190_rx_fill(struct sis190_private *tp, struct net_device *dev,
524 for (cur = start; cur < end; cur++) {
525 int ret, i = cur % NUM_RX_DESC;
527 if (tp->Rx_skbuff[i])
530 ret = sis190_alloc_rx_skb(tp->pci_dev, tp->Rx_skbuff + i,
531 tp->RxDescRing + i, tp->rx_buf_sz);
538 static inline int sis190_try_rx_copy(struct sk_buff **sk_buff, int pkt_size,
539 struct RxDesc *desc, int rx_buf_sz)
543 if (pkt_size < rx_copybreak) {
546 skb = dev_alloc_skb(pkt_size + NET_IP_ALIGN);
548 skb_reserve(skb, NET_IP_ALIGN);
549 eth_copy_and_sum(skb, sk_buff[0]->data, pkt_size, 0);
551 sis190_give_to_asic(desc, rx_buf_sz);
558 static inline int sis190_rx_pkt_err(u32 status, struct net_device_stats *stats)
560 #define ErrMask (OVRUN | SHORT | LIMIT | MIIER | NIBON | COLON | ABORT)
562 if ((status & CRCOK) && !(status & ErrMask))
565 if (!(status & CRCOK))
566 stats->rx_crc_errors++;
567 else if (status & OVRUN)
568 stats->rx_over_errors++;
569 else if (status & (SHORT | LIMIT))
570 stats->rx_length_errors++;
571 else if (status & (MIIER | NIBON | COLON))
572 stats->rx_frame_errors++;
578 static int sis190_rx_interrupt(struct net_device *dev,
579 struct sis190_private *tp, void __iomem *ioaddr)
581 struct net_device_stats *stats = &tp->stats;
582 u32 rx_left, cur_rx = tp->cur_rx;
585 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
586 rx_left = sis190_rx_quota(rx_left, (u32) dev->quota);
588 for (; rx_left > 0; rx_left--, cur_rx++) {
589 unsigned int entry = cur_rx % NUM_RX_DESC;
590 struct RxDesc *desc = tp->RxDescRing + entry;
593 if (desc->status & OWNbit)
596 status = le32_to_cpu(desc->PSize);
598 // net_intr(tp, KERN_INFO "%s: Rx PSize = %08x.\n", dev->name,
601 if (sis190_rx_pkt_err(status, stats) < 0)
602 sis190_give_to_asic(desc, tp->rx_buf_sz);
604 struct sk_buff *skb = tp->Rx_skbuff[entry];
605 int pkt_size = (status & RxSizeMask) - 4;
606 void (*pci_action)(struct pci_dev *, dma_addr_t,
607 size_t, int) = pci_dma_sync_single_for_device;
609 if (unlikely(pkt_size > tp->rx_buf_sz)) {
610 net_intr(tp, KERN_INFO
611 "%s: (frag) status = %08x.\n",
614 stats->rx_length_errors++;
615 sis190_give_to_asic(desc, tp->rx_buf_sz);
619 pci_dma_sync_single_for_cpu(tp->pci_dev,
620 le32_to_cpu(desc->addr), tp->rx_buf_sz,
623 if (sis190_try_rx_copy(&skb, pkt_size, desc,
625 pci_action = pci_unmap_single;
626 tp->Rx_skbuff[entry] = NULL;
627 sis190_make_unusable_by_asic(desc);
630 pci_action(tp->pci_dev, le32_to_cpu(desc->addr),
631 tp->rx_buf_sz, PCI_DMA_FROMDEVICE);
634 skb_put(skb, pkt_size);
635 skb->protocol = eth_type_trans(skb, dev);
639 dev->last_rx = jiffies;
641 stats->rx_bytes += pkt_size;
642 if ((status & BCAST) == MCAST)
646 count = cur_rx - tp->cur_rx;
649 delta = sis190_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
650 if (!delta && count && netif_msg_intr(tp))
651 printk(KERN_INFO "%s: no Rx buffer allocated.\n", dev->name);
652 tp->dirty_rx += delta;
654 if (((tp->dirty_rx + NUM_RX_DESC) == tp->cur_rx) && netif_msg_intr(tp))
655 printk(KERN_EMERG "%s: Rx buffers exhausted.\n", dev->name);
660 static void sis190_unmap_tx_skb(struct pci_dev *pdev, struct sk_buff *skb,
665 len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
667 pci_unmap_single(pdev, le32_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
669 memset(desc, 0x00, sizeof(*desc));
672 static void sis190_tx_interrupt(struct net_device *dev,
673 struct sis190_private *tp, void __iomem *ioaddr)
675 u32 pending, dirty_tx = tp->dirty_tx;
677 * It would not be needed if queueing was allowed to be enabled
678 * again too early (hint: think preempt and unclocked smp systems).
680 unsigned int queue_stopped;
683 pending = tp->cur_tx - dirty_tx;
684 queue_stopped = (pending == NUM_TX_DESC);
686 for (; pending; pending--, dirty_tx++) {
687 unsigned int entry = dirty_tx % NUM_TX_DESC;
688 struct TxDesc *txd = tp->TxDescRing + entry;
691 if (le32_to_cpu(txd->status) & OWNbit)
694 skb = tp->Tx_skbuff[entry];
696 tp->stats.tx_packets++;
697 tp->stats.tx_bytes += skb->len;
699 sis190_unmap_tx_skb(tp->pci_dev, skb, txd);
700 tp->Tx_skbuff[entry] = NULL;
701 dev_kfree_skb_irq(skb);
704 if (tp->dirty_tx != dirty_tx) {
705 tp->dirty_tx = dirty_tx;
708 netif_wake_queue(dev);
713 * The interrupt handler does all of the Rx thread work and cleans up after
716 static irqreturn_t sis190_interrupt(int irq, void *__dev, struct pt_regs *regs)
718 struct net_device *dev = __dev;
719 struct sis190_private *tp = netdev_priv(dev);
720 void __iomem *ioaddr = tp->mmio_addr;
721 unsigned int handled = 0;
724 status = SIS_R32(IntrStatus);
726 if ((status == 0xffffffff) || !status)
731 if (unlikely(!netif_running(dev))) {
732 sis190_asic_down(ioaddr);
736 SIS_W32(IntrStatus, status);
738 // net_intr(tp, KERN_INFO "%s: status = %08x.\n", dev->name, status);
740 if (status & LinkChange) {
741 net_intr(tp, KERN_INFO "%s: link change.\n", dev->name);
742 schedule_work(&tp->phy_task);
746 sis190_rx_interrupt(dev, tp, ioaddr);
748 if (status & TxQ0Int)
749 sis190_tx_interrupt(dev, tp, ioaddr);
751 return IRQ_RETVAL(handled);
754 #ifdef CONFIG_NET_POLL_CONTROLLER
755 static void sis190_netpoll(struct net_device *dev)
757 struct sis190_private *tp = netdev_priv(dev);
758 struct pci_dev *pdev = tp->pci_dev;
760 disable_irq(pdev->irq);
761 sis190_interrupt(pdev->irq, dev, NULL);
762 enable_irq(pdev->irq);
766 static void sis190_free_rx_skb(struct sis190_private *tp,
767 struct sk_buff **sk_buff, struct RxDesc *desc)
769 struct pci_dev *pdev = tp->pci_dev;
771 pci_unmap_single(pdev, le32_to_cpu(desc->addr), tp->rx_buf_sz,
773 dev_kfree_skb(*sk_buff);
775 sis190_make_unusable_by_asic(desc);
778 static void sis190_rx_clear(struct sis190_private *tp)
782 for (i = 0; i < NUM_RX_DESC; i++) {
783 if (!tp->Rx_skbuff[i])
785 sis190_free_rx_skb(tp, tp->Rx_skbuff + i, tp->RxDescRing + i);
789 static void sis190_init_ring_indexes(struct sis190_private *tp)
791 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
794 static int sis190_init_ring(struct net_device *dev)
796 struct sis190_private *tp = netdev_priv(dev);
798 sis190_init_ring_indexes(tp);
800 memset(tp->Tx_skbuff, 0x0, NUM_TX_DESC * sizeof(struct sk_buff *));
801 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
803 if (sis190_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
806 sis190_mark_as_last_descriptor(tp->RxDescRing + NUM_RX_DESC - 1);
815 static void sis190_set_rx_mode(struct net_device *dev)
817 struct sis190_private *tp = netdev_priv(dev);
818 void __iomem *ioaddr = tp->mmio_addr;
820 u32 mc_filter[2]; /* Multicast hash filter */
823 if (dev->flags & IFF_PROMISC) {
824 /* Unconditionally log net taps. */
825 net_drv(tp, KERN_NOTICE "%s: Promiscuous mode enabled.\n",
828 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
830 mc_filter[1] = mc_filter[0] = 0xffffffff;
831 } else if ((dev->mc_count > multicast_filter_limit) ||
832 (dev->flags & IFF_ALLMULTI)) {
833 /* Too many to filter perfectly -- accept all multicasts. */
834 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
835 mc_filter[1] = mc_filter[0] = 0xffffffff;
837 struct dev_mc_list *mclist;
840 rx_mode = AcceptBroadcast | AcceptMyPhys;
841 mc_filter[1] = mc_filter[0] = 0;
842 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
843 i++, mclist = mclist->next) {
845 ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
846 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
847 rx_mode |= AcceptMulticast;
851 spin_lock_irqsave(&tp->lock, flags);
853 SIS_W16(RxMacControl, rx_mode | 0x2);
854 SIS_W32(RxHashTable, mc_filter[0]);
855 SIS_W32(RxHashTable + 4, mc_filter[1]);
857 spin_unlock_irqrestore(&tp->lock, flags);
860 static void sis190_soft_reset(void __iomem *ioaddr)
862 SIS_W32(IntrControl, 0x8000);
865 SIS_W32(IntrControl, 0x0);
866 sis190_asic_down(ioaddr);
870 static void sis190_hw_start(struct net_device *dev)
872 struct sis190_private *tp = netdev_priv(dev);
873 void __iomem *ioaddr = tp->mmio_addr;
875 sis190_soft_reset(ioaddr);
877 SIS_W32(TxDescStartAddr, tp->tx_dma);
878 SIS_W32(RxDescStartAddr, tp->rx_dma);
880 SIS_W32(IntrStatus, 0xffffffff);
881 SIS_W32(IntrMask, 0x0);
883 * Default is 100Mbps.
884 * A bit strange: 100Mbps is 0x1801 elsewhere -- FR 2005/06/09
886 SIS_W16(StationControl, 0x1901);
887 SIS_W32(GMIIControl, 0x0);
888 SIS_W32(TxMacControl, 0x60);
889 SIS_W16(RxMacControl, 0x02);
890 SIS_W32(RxHashTable, 0x0);
892 SIS_W32(RxWolCtrl, 0x0);
893 SIS_W32(RxWolData, 0x0);
897 sis190_set_rx_mode(dev);
899 /* Enable all known interrupts by setting the interrupt mask. */
900 SIS_W32(IntrMask, sis190_intr_mask);
902 SIS_W32(TxControl, 0x1a00 | CmdTxEnb);
903 SIS_W32(RxControl, 0x1a1d);
905 netif_start_queue(dev);
908 static void sis190_phy_task(void * data)
910 struct net_device *dev = data;
911 struct sis190_private *tp = netdev_priv(dev);
912 void __iomem *ioaddr = tp->mmio_addr;
913 int phy_id = tp->mii_if.phy_id;
918 val = mdio_read(ioaddr, phy_id, MII_BMCR);
919 if (val & BMCR_RESET) {
920 // FIXME: needlessly high ? -- FR 02/07/2005
921 mod_timer(&tp->timer, jiffies + HZ/10);
922 } else if (!(mdio_read_latched(ioaddr, phy_id, MII_BMSR) &
923 BMSR_ANEGCOMPLETE)) {
924 net_link(tp, KERN_WARNING "%s: PHY reset until link up.\n",
926 mdio_write(ioaddr, phy_id, MII_BMCR, val | BMCR_RESET);
927 mod_timer(&tp->timer, jiffies + SIS190_PHY_TIMEOUT);
935 { LPA_1000XFULL | LPA_SLCT,
936 "1000 Mbps Full Duplex",
938 { LPA_1000XHALF | LPA_SLCT,
939 "1000 Mbps Half Duplex",
942 "100 Mbps Full Duplex",
945 "100 Mbps Half Duplex",
948 "10 Mbps Full Duplex",
951 "10 Mbps Half Duplex",
953 { 0, "unknown", 0x0000 }
956 val = mdio_read(ioaddr, phy_id, 0x1f);
957 net_link(tp, KERN_INFO "%s: mii ext = %04x.\n", dev->name, val);
959 val = mdio_read(ioaddr, phy_id, MII_LPA);
960 net_link(tp, KERN_INFO "%s: mii lpa = %04x.\n", dev->name, val);
962 for (p = reg31; p->ctl; p++) {
963 if ((val & p->val) == p->val)
967 SIS_W16(StationControl, p->ctl);
968 net_link(tp, KERN_INFO "%s: link on %s mode.\n", dev->name,
970 netif_carrier_on(dev);
976 static void sis190_phy_timer(unsigned long __opaque)
978 struct net_device *dev = (struct net_device *)__opaque;
979 struct sis190_private *tp = netdev_priv(dev);
981 if (likely(netif_running(dev)))
982 schedule_work(&tp->phy_task);
985 static inline void sis190_delete_timer(struct net_device *dev)
987 struct sis190_private *tp = netdev_priv(dev);
989 del_timer_sync(&tp->timer);
992 static inline void sis190_request_timer(struct net_device *dev)
994 struct sis190_private *tp = netdev_priv(dev);
995 struct timer_list *timer = &tp->timer;
998 timer->expires = jiffies + SIS190_PHY_TIMEOUT;
999 timer->data = (unsigned long)dev;
1000 timer->function = sis190_phy_timer;
1004 static void sis190_set_rxbufsize(struct sis190_private *tp,
1005 struct net_device *dev)
1007 unsigned int mtu = dev->mtu;
1009 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1010 /* RxDesc->size has a licence to kill the lower bits */
1011 if (tp->rx_buf_sz & 0x07) {
1013 tp->rx_buf_sz &= RX_BUF_MASK;
1017 static int sis190_open(struct net_device *dev)
1019 struct sis190_private *tp = netdev_priv(dev);
1020 struct pci_dev *pdev = tp->pci_dev;
1023 sis190_set_rxbufsize(tp, dev);
1026 * Rx and Tx descriptors need 256 bytes alignment.
1027 * pci_alloc_consistent() guarantees a stronger alignment.
1029 tp->TxDescRing = pci_alloc_consistent(pdev, TX_RING_BYTES, &tp->tx_dma);
1030 if (!tp->TxDescRing)
1033 tp->RxDescRing = pci_alloc_consistent(pdev, RX_RING_BYTES, &tp->rx_dma);
1034 if (!tp->RxDescRing)
1037 rc = sis190_init_ring(dev);
1041 INIT_WORK(&tp->phy_task, sis190_phy_task, dev);
1043 sis190_request_timer(dev);
1045 rc = request_irq(dev->irq, sis190_interrupt, SA_SHIRQ, dev->name, dev);
1047 goto err_release_timer_2;
1049 sis190_hw_start(dev);
1053 err_release_timer_2:
1054 sis190_delete_timer(dev);
1055 sis190_rx_clear(tp);
1057 pci_free_consistent(tp->pci_dev, RX_RING_BYTES, tp->RxDescRing,
1060 pci_free_consistent(tp->pci_dev, TX_RING_BYTES, tp->TxDescRing,
1065 static void sis190_tx_clear(struct sis190_private *tp)
1069 for (i = 0; i < NUM_TX_DESC; i++) {
1070 struct sk_buff *skb = tp->Tx_skbuff[i];
1075 sis190_unmap_tx_skb(tp->pci_dev, skb, tp->TxDescRing + i);
1076 tp->Tx_skbuff[i] = NULL;
1079 tp->stats.tx_dropped++;
1081 tp->cur_tx = tp->dirty_tx = 0;
1084 static void sis190_down(struct net_device *dev)
1086 struct sis190_private *tp = netdev_priv(dev);
1087 void __iomem *ioaddr = tp->mmio_addr;
1088 unsigned int poll_locked = 0;
1090 sis190_delete_timer(dev);
1092 netif_stop_queue(dev);
1094 flush_scheduled_work();
1097 spin_lock_irq(&tp->lock);
1099 sis190_asic_down(ioaddr);
1101 spin_unlock_irq(&tp->lock);
1103 synchronize_irq(dev->irq);
1106 netif_poll_disable(dev);
1110 synchronize_sched();
1112 } while (SIS_R32(IntrMask));
1114 sis190_tx_clear(tp);
1115 sis190_rx_clear(tp);
1118 static int sis190_close(struct net_device *dev)
1120 struct sis190_private *tp = netdev_priv(dev);
1121 struct pci_dev *pdev = tp->pci_dev;
1125 free_irq(dev->irq, dev);
1127 netif_poll_enable(dev);
1129 pci_free_consistent(pdev, TX_RING_BYTES, tp->TxDescRing, tp->tx_dma);
1130 pci_free_consistent(pdev, RX_RING_BYTES, tp->RxDescRing, tp->rx_dma);
1132 tp->TxDescRing = NULL;
1133 tp->RxDescRing = NULL;
1138 static int sis190_start_xmit(struct sk_buff *skb, struct net_device *dev)
1140 struct sis190_private *tp = netdev_priv(dev);
1141 void __iomem *ioaddr = tp->mmio_addr;
1142 u32 len, entry, dirty_tx;
1143 struct TxDesc *desc;
1146 if (unlikely(skb->len < ETH_ZLEN)) {
1147 skb = skb_padto(skb, ETH_ZLEN);
1149 tp->stats.tx_dropped++;
1157 entry = tp->cur_tx % NUM_TX_DESC;
1158 desc = tp->TxDescRing + entry;
1160 if (unlikely(le32_to_cpu(desc->status) & OWNbit)) {
1161 netif_stop_queue(dev);
1162 net_tx_err(tp, KERN_ERR PFX
1163 "%s: BUG! Tx Ring full when queue awake!\n",
1165 return NETDEV_TX_BUSY;
1168 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
1170 tp->Tx_skbuff[entry] = skb;
1172 desc->PSize = cpu_to_le32(len);
1173 desc->addr = cpu_to_le32(mapping);
1175 desc->size = cpu_to_le32(len);
1176 if (entry == (NUM_TX_DESC - 1))
1177 desc->size |= cpu_to_le32(RingEnd);
1181 desc->status = cpu_to_le32(OWNbit | INTbit | DEFbit | CRCbit | PADbit);
1187 SIS_W32(TxControl, 0x1a00 | CmdReset | CmdTxEnb);
1189 dev->trans_start = jiffies;
1191 dirty_tx = tp->dirty_tx;
1192 if ((tp->cur_tx - NUM_TX_DESC) == dirty_tx) {
1193 netif_stop_queue(dev);
1195 if (dirty_tx != tp->dirty_tx)
1196 netif_wake_queue(dev);
1199 return NETDEV_TX_OK;
1202 static struct net_device_stats *sis190_get_stats(struct net_device *dev)
1204 struct sis190_private *tp = netdev_priv(dev);
1209 static void sis190_free_phy(struct list_head *first_phy)
1211 struct sis190_phy *cur, *next;
1213 list_for_each_entry_safe(cur, next, first_phy, list) {
1219 * sis190_default_phy - Select default PHY for sis190 mac.
1220 * @dev: the net device to probe for
1222 * Select first detected PHY with link as default.
1223 * If no one is link on, select PHY whose types is HOME as default.
1224 * If HOME doesn't exist, select LAN.
1226 static u16 sis190_default_phy(struct net_device *dev)
1228 struct sis190_phy *phy, *phy_home, *phy_default, *phy_lan;
1229 struct sis190_private *tp = netdev_priv(dev);
1230 struct mii_if_info *mii_if = &tp->mii_if;
1231 void __iomem *ioaddr = tp->mmio_addr;
1234 phy_home = phy_default = phy_lan = NULL;
1236 list_for_each_entry(phy, &tp->first_phy, list) {
1237 status = mdio_read_latched(ioaddr, phy->phy_id, MII_BMSR);
1239 // Link ON & Not select default PHY & not ghost PHY.
1240 if ((status & BMSR_LSTATUS) &&
1242 (phy->type != UNKNOWN)) {
1245 status = mdio_read(ioaddr, phy->phy_id, MII_BMCR);
1246 mdio_write(ioaddr, phy->phy_id, MII_BMCR,
1247 status | BMCR_ANENABLE | BMCR_ISOLATE);
1248 if (phy->type == HOME)
1250 else if (phy->type == LAN)
1257 phy_default = phy_home;
1259 phy_default = phy_lan;
1261 phy_default = list_entry(&tp->first_phy,
1262 struct sis190_phy, list);
1265 if (mii_if->phy_id != phy_default->phy_id) {
1266 mii_if->phy_id = phy_default->phy_id;
1267 net_probe(tp, KERN_INFO
1268 "%s: Using transceiver at address %d as default.\n",
1269 dev->name, mii_if->phy_id);
1272 status = mdio_read(ioaddr, mii_if->phy_id, MII_BMCR);
1273 status &= (~BMCR_ISOLATE);
1275 mdio_write(ioaddr, mii_if->phy_id, MII_BMCR, status);
1276 status = mdio_read_latched(ioaddr, mii_if->phy_id, MII_BMSR);
1281 static void sis190_init_phy(struct net_device *dev, struct sis190_private *tp,
1282 struct sis190_phy *phy, unsigned int phy_id,
1285 void __iomem *ioaddr = tp->mmio_addr;
1286 struct mii_chip_info *p;
1288 INIT_LIST_HEAD(&phy->list);
1289 phy->status = mii_status;
1290 phy->phy_id = phy_id;
1292 phy->id[0] = mdio_read(ioaddr, phy_id, MII_PHYSID1);
1293 phy->id[1] = mdio_read(ioaddr, phy_id, MII_PHYSID2);
1295 for (p = mii_chip_table; p->type; p++) {
1296 if ((p->id[0] == phy->id[0]) &&
1297 (p->id[1] == (phy->id[1] & 0xfff0))) {
1303 phy->type = (p->type == MIX) ?
1304 ((mii_status & (BMSR_100FULL | BMSR_100HALF)) ?
1305 LAN : HOME) : p->type;
1307 phy->type = UNKNOWN;
1309 net_probe(tp, KERN_INFO "%s: %s transceiver at address %d.\n",
1310 dev->name, (phy->type == UNKNOWN) ? "Unknown PHY" : p->name,
1315 * sis190_mii_probe - Probe MII PHY for sis190
1316 * @dev: the net device to probe for
1318 * Search for total of 32 possible mii phy addresses.
1319 * Identify and set current phy if found one,
1320 * return error if it failed to found.
1322 static int __devinit sis190_mii_probe(struct net_device *dev)
1324 struct sis190_private *tp = netdev_priv(dev);
1325 struct mii_if_info *mii_if = &tp->mii_if;
1326 void __iomem *ioaddr = tp->mmio_addr;
1330 INIT_LIST_HEAD(&tp->first_phy);
1332 for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
1333 struct sis190_phy *phy;
1336 status = mdio_read_latched(ioaddr, phy_id, MII_BMSR);
1338 // Try next mii if the current one is not accessible.
1339 if (status == 0xffff || status == 0x0000)
1342 phy = kmalloc(sizeof(*phy), GFP_KERNEL);
1344 sis190_free_phy(&tp->first_phy);
1349 sis190_init_phy(dev, tp, phy, phy_id, status);
1351 list_add(&tp->first_phy, &phy->list);
1354 if (list_empty(&tp->first_phy)) {
1355 net_probe(tp, KERN_INFO "%s: No MII transceivers found!\n",
1361 /* Select default PHY for mac */
1362 sis190_default_phy(dev);
1365 mii_if->mdio_read = __mdio_read;
1366 mii_if->mdio_write = __mdio_write;
1367 mii_if->phy_id_mask = PHY_ID_ANY;
1368 mii_if->reg_num_mask = MII_REG_ANY;
1373 static void __devexit sis190_mii_remove(struct net_device *dev)
1375 struct sis190_private *tp = netdev_priv(dev);
1377 sis190_free_phy(&tp->first_phy);
1380 static void sis190_release_board(struct pci_dev *pdev)
1382 struct net_device *dev = pci_get_drvdata(pdev);
1383 struct sis190_private *tp = netdev_priv(dev);
1385 iounmap(tp->mmio_addr);
1386 pci_release_regions(pdev);
1387 pci_disable_device(pdev);
1391 static struct net_device * __devinit sis190_init_board(struct pci_dev *pdev)
1393 struct sis190_private *tp;
1394 struct net_device *dev;
1395 void __iomem *ioaddr;
1398 dev = alloc_etherdev(sizeof(*tp));
1400 net_drv(&debug, KERN_ERR PFX "unable to alloc new ethernet\n");
1405 SET_MODULE_OWNER(dev);
1406 SET_NETDEV_DEV(dev, &pdev->dev);
1408 tp = netdev_priv(dev);
1409 tp->msg_enable = netif_msg_init(debug.msg_enable, SIS190_MSG_DEFAULT);
1411 rc = pci_enable_device(pdev);
1413 net_probe(tp, KERN_ERR "%s: enable failure\n", pci_name(pdev));
1414 goto err_free_dev_1;
1419 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1420 net_probe(tp, KERN_ERR "%s: region #0 is no MMIO resource.\n",
1422 goto err_pci_disable_2;
1424 if (pci_resource_len(pdev, 0) < SIS190_REGS_SIZE) {
1425 net_probe(tp, KERN_ERR "%s: invalid PCI region size(s).\n",
1427 goto err_pci_disable_2;
1430 rc = pci_request_regions(pdev, DRV_NAME);
1432 net_probe(tp, KERN_ERR PFX "%s: could not request regions.\n",
1434 goto err_pci_disable_2;
1437 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1439 net_probe(tp, KERN_ERR "%s: DMA configuration failed.\n",
1441 goto err_free_res_3;
1444 pci_set_master(pdev);
1446 ioaddr = ioremap(pci_resource_start(pdev, 0), SIS190_REGS_SIZE);
1448 net_probe(tp, KERN_ERR "%s: cannot remap MMIO, aborting\n",
1451 goto err_free_res_3;
1455 tp->mmio_addr = ioaddr;
1457 sis190_irq_mask_and_ack(ioaddr);
1459 sis190_soft_reset(ioaddr);
1464 pci_release_regions(pdev);
1466 pci_disable_device(pdev);
1474 static void sis190_tx_timeout(struct net_device *dev)
1476 struct sis190_private *tp = netdev_priv(dev);
1477 void __iomem *ioaddr = tp->mmio_addr;
1480 /* Disable Tx, if not already */
1481 tmp8 = SIS_R8(TxControl);
1482 if (tmp8 & CmdTxEnb)
1483 SIS_W8(TxControl, tmp8 & ~CmdTxEnb);
1486 net_tx_err(tp, KERN_INFO "%s: Transmit timeout, status %08x %08x.\n",
1487 dev->name, SIS_R32(TxControl), SIS_R32(TxSts));
1489 /* Disable interrupts by clearing the interrupt mask. */
1490 SIS_W32(IntrMask, 0x0000);
1492 /* Stop a shared interrupt from scavenging while we are. */
1493 spin_lock_irq(&tp->lock);
1494 sis190_tx_clear(tp);
1495 spin_unlock_irq(&tp->lock);
1497 /* ...and finally, reset everything. */
1498 sis190_hw_start(dev);
1500 netif_wake_queue(dev);
1503 static int __devinit sis190_get_mac_addr_from_eeprom(struct pci_dev *pdev,
1504 struct net_device *dev)
1506 struct sis190_private *tp = netdev_priv(dev);
1507 void __iomem *ioaddr = tp->mmio_addr;
1511 net_probe(tp, KERN_INFO "%s: Read MAC address from EEPROM\n",
1514 /* Check to see if there is a sane EEPROM */
1515 sig = (u16) sis190_read_eeprom(ioaddr, EEPROMSignature);
1517 if ((sig == 0xffff) || (sig == 0x0000)) {
1518 net_probe(tp, KERN_INFO "%s: Error EEPROM read %x.\n",
1519 pci_name(pdev), sig);
1523 /* Get MAC address from EEPROM */
1524 for (i = 0; i < MAC_ADDR_LEN / 2; i++) {
1525 __le16 w = sis190_read_eeprom(ioaddr, EEPROMMACAddr + i);
1527 ((u16 *)dev->dev_addr)[0] = le16_to_cpu(w);
1534 * sis190_get_mac_addr_from_apc - Get MAC address for SiS965 model
1536 * @dev: network device to get address for
1538 * SiS965 model, use APC CMOS RAM to store MAC address.
1539 * APC CMOS RAM is accessed through ISA bridge.
1540 * MAC address is read into @net_dev->dev_addr.
1542 static int __devinit sis190_get_mac_addr_from_apc(struct pci_dev *pdev,
1543 struct net_device *dev)
1545 struct sis190_private *tp = netdev_priv(dev);
1546 struct pci_dev *isa_bridge;
1550 net_probe(tp, KERN_INFO "%s: Read MAC address from APC.\n",
1553 isa_bridge = pci_get_device(PCI_VENDOR_ID_SI, 0x0965, NULL);
1555 net_probe(tp, KERN_INFO "%s: Can not find ISA bridge.\n",
1560 /* Enable port 78h & 79h to access APC Registers. */
1561 pci_read_config_byte(isa_bridge, 0x48, &tmp8);
1562 reg = (tmp8 & ~0x02);
1563 pci_write_config_byte(isa_bridge, 0x48, reg);
1565 pci_read_config_byte(isa_bridge, 0x48, ®);
1567 for (i = 0; i < MAC_ADDR_LEN; i++) {
1568 outb(0x9 + i, 0x78);
1569 dev->dev_addr[i] = inb(0x79);
1575 /* Restore the value to ISA Bridge */
1576 pci_write_config_byte(isa_bridge, 0x48, tmp8);
1577 pci_dev_put(isa_bridge);
1583 * sis190_init_rxfilter - Initialize the Rx filter
1584 * @dev: network device to initialize
1586 * Set receive filter address to our MAC address
1587 * and enable packet filtering.
1589 static inline void sis190_init_rxfilter(struct net_device *dev)
1591 struct sis190_private *tp = netdev_priv(dev);
1592 void __iomem *ioaddr = tp->mmio_addr;
1596 ctl = SIS_R16(RxMacControl);
1598 * Disable packet filtering before setting filter.
1599 * Note: SiS's driver writes 32 bits but RxMacControl is 16 bits
1600 * only and followed by RxMacAddr (6 bytes). Strange. -- FR
1602 SIS_W16(RxMacControl, ctl & ~0x0f00);
1604 for (i = 0; i < MAC_ADDR_LEN; i++)
1605 SIS_W8(RxMacAddr + i, dev->dev_addr[i]);
1607 SIS_W16(RxMacControl, ctl);
1611 static int sis190_get_mac_addr(struct pci_dev *pdev, struct net_device *dev)
1615 pci_read_config_byte(pdev, 0x73, &from);
1617 return (from & 0x00000001) ?
1618 sis190_get_mac_addr_from_apc(pdev, dev) :
1619 sis190_get_mac_addr_from_eeprom(pdev, dev);
1622 static void sis190_set_speed_auto(struct net_device *dev)
1624 struct sis190_private *tp = netdev_priv(dev);
1625 void __iomem *ioaddr = tp->mmio_addr;
1626 int phy_id = tp->mii_if.phy_id;
1629 net_link(tp, KERN_INFO "%s: Enabling Auto-negotiation.\n", dev->name);
1631 val = mdio_read(ioaddr, phy_id, MII_ADVERTISE);
1633 // Enable 10/100 Full/Half Mode, leave MII_ADVERTISE bit4:0
1635 mdio_write(ioaddr, phy_id, MII_ADVERTISE, (val & ADVERTISE_SLCT) |
1636 ADVERTISE_100FULL | ADVERTISE_10FULL |
1637 ADVERTISE_100HALF | ADVERTISE_10HALF);
1639 // Enable 1000 Full Mode.
1640 mdio_write(ioaddr, phy_id, MII_CTRL1000, ADVERTISE_1000FULL);
1642 // Enable auto-negotiation and restart auto-negotiation.
1643 mdio_write(ioaddr, phy_id, MII_BMCR,
1644 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET);
1647 static int sis190_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1649 struct sis190_private *tp = netdev_priv(dev);
1651 return mii_ethtool_gset(&tp->mii_if, cmd);
1654 static int sis190_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1656 struct sis190_private *tp = netdev_priv(dev);
1658 return mii_ethtool_sset(&tp->mii_if, cmd);
1661 static void sis190_get_drvinfo(struct net_device *dev,
1662 struct ethtool_drvinfo *info)
1664 struct sis190_private *tp = netdev_priv(dev);
1666 strcpy(info->driver, DRV_NAME);
1667 strcpy(info->version, DRV_VERSION);
1668 strcpy(info->bus_info, pci_name(tp->pci_dev));
1671 static int sis190_get_regs_len(struct net_device *dev)
1673 return SIS190_REGS_SIZE;
1676 static void sis190_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1679 struct sis190_private *tp = netdev_priv(dev);
1680 unsigned long flags;
1682 if (regs->len > SIS190_REGS_SIZE)
1683 regs->len = SIS190_REGS_SIZE;
1685 spin_lock_irqsave(&tp->lock, flags);
1686 memcpy_fromio(p, tp->mmio_addr, regs->len);
1687 spin_unlock_irqrestore(&tp->lock, flags);
1690 static int sis190_nway_reset(struct net_device *dev)
1692 struct sis190_private *tp = netdev_priv(dev);
1694 return mii_nway_restart(&tp->mii_if);
1697 static u32 sis190_get_msglevel(struct net_device *dev)
1699 struct sis190_private *tp = netdev_priv(dev);
1701 return tp->msg_enable;
1704 static void sis190_set_msglevel(struct net_device *dev, u32 value)
1706 struct sis190_private *tp = netdev_priv(dev);
1708 tp->msg_enable = value;
1711 static struct ethtool_ops sis190_ethtool_ops = {
1712 .get_settings = sis190_get_settings,
1713 .set_settings = sis190_set_settings,
1714 .get_drvinfo = sis190_get_drvinfo,
1715 .get_regs_len = sis190_get_regs_len,
1716 .get_regs = sis190_get_regs,
1717 .get_link = ethtool_op_get_link,
1718 .get_msglevel = sis190_get_msglevel,
1719 .set_msglevel = sis190_set_msglevel,
1720 .nway_reset = sis190_nway_reset,
1723 static int sis190_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1725 struct sis190_private *tp = netdev_priv(dev);
1727 return !netif_running(dev) ? -EINVAL :
1728 generic_mii_ioctl(&tp->mii_if, if_mii(ifr), cmd, NULL);
1731 static int __devinit sis190_init_one(struct pci_dev *pdev,
1732 const struct pci_device_id *ent)
1734 static int printed_version = 0;
1735 struct sis190_private *tp;
1736 struct net_device *dev;
1737 void __iomem *ioaddr;
1740 if (!printed_version) {
1741 net_drv(&debug, KERN_INFO SIS190_DRIVER_NAME " loaded.\n");
1742 printed_version = 1;
1745 dev = sis190_init_board(pdev);
1751 tp = netdev_priv(dev);
1752 ioaddr = tp->mmio_addr;
1754 rc = sis190_get_mac_addr(pdev, dev);
1756 goto err_release_board;
1758 sis190_init_rxfilter(dev);
1760 INIT_WORK(&tp->phy_task, sis190_phy_task, dev);
1762 dev->open = sis190_open;
1763 dev->stop = sis190_close;
1764 dev->do_ioctl = sis190_ioctl;
1765 dev->get_stats = sis190_get_stats;
1766 dev->tx_timeout = sis190_tx_timeout;
1767 dev->watchdog_timeo = SIS190_TX_TIMEOUT;
1768 dev->hard_start_xmit = sis190_start_xmit;
1769 #ifdef CONFIG_NET_POLL_CONTROLLER
1770 dev->poll_controller = sis190_netpoll;
1772 dev->set_multicast_list = sis190_set_rx_mode;
1773 SET_ETHTOOL_OPS(dev, &sis190_ethtool_ops);
1774 dev->irq = pdev->irq;
1775 dev->base_addr = (unsigned long) 0xdead;
1777 spin_lock_init(&tp->lock);
1778 rc = register_netdev(dev);
1780 goto err_release_board;
1782 pci_set_drvdata(pdev, dev);
1784 rc = sis190_mii_probe(dev);
1786 goto err_unregister_dev;
1788 net_probe(tp, KERN_INFO "%s: %s at %p (IRQ: %d), "
1789 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
1790 pci_name(pdev), sis_chip_info[ent->driver_data].name,
1792 dev->dev_addr[0], dev->dev_addr[1],
1793 dev->dev_addr[2], dev->dev_addr[3],
1794 dev->dev_addr[4], dev->dev_addr[5]);
1796 netif_carrier_off(dev);
1798 sis190_set_speed_auto(dev);
1803 unregister_netdev(dev);
1805 sis190_release_board(pdev);
1809 static void __devexit sis190_remove_one(struct pci_dev *pdev)
1811 struct net_device *dev = pci_get_drvdata(pdev);
1813 sis190_mii_remove(dev);
1814 unregister_netdev(dev);
1815 sis190_release_board(pdev);
1816 pci_set_drvdata(pdev, NULL);
1819 static struct pci_driver sis190_pci_driver = {
1821 .id_table = sis190_pci_tbl,
1822 .probe = sis190_init_one,
1823 .remove = __devexit_p(sis190_remove_one),
1826 static int __init sis190_init_module(void)
1828 return pci_module_init(&sis190_pci_driver);
1831 static void __exit sis190_cleanup_module(void)
1833 pci_unregister_driver(&sis190_pci_driver);
1836 module_init(sis190_init_module);
1837 module_exit(sis190_cleanup_module);