Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas...
[linux-2.6.git] / drivers / net / sfc / nic.c
1 /****************************************************************************
2  * Driver for Solarflare Solarstorm network controllers and boards
3  * Copyright 2005-2006 Fen Systems Ltd.
4  * Copyright 2006-2011 Solarflare Communications Inc.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms of the GNU General Public License version 2 as published
8  * by the Free Software Foundation, incorporated herein by reference.
9  */
10
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/seq_file.h>
16 #include "net_driver.h"
17 #include "bitfield.h"
18 #include "efx.h"
19 #include "nic.h"
20 #include "regs.h"
21 #include "io.h"
22 #include "workarounds.h"
23
24 /**************************************************************************
25  *
26  * Configurable values
27  *
28  **************************************************************************
29  */
30
31 /* This is set to 16 for a good reason.  In summary, if larger than
32  * 16, the descriptor cache holds more than a default socket
33  * buffer's worth of packets (for UDP we can only have at most one
34  * socket buffer's worth outstanding).  This combined with the fact
35  * that we only get 1 TX event per descriptor cache means the NIC
36  * goes idle.
37  */
38 #define TX_DC_ENTRIES 16
39 #define TX_DC_ENTRIES_ORDER 1
40
41 #define RX_DC_ENTRIES 64
42 #define RX_DC_ENTRIES_ORDER 3
43
44 /* If EFX_MAX_INT_ERRORS internal errors occur within
45  * EFX_INT_ERROR_EXPIRE seconds, we consider the NIC broken and
46  * disable it.
47  */
48 #define EFX_INT_ERROR_EXPIRE 3600
49 #define EFX_MAX_INT_ERRORS 5
50
51 /* We poll for events every FLUSH_INTERVAL ms, and check FLUSH_POLL_COUNT times
52  */
53 #define EFX_FLUSH_INTERVAL 10
54 #define EFX_FLUSH_POLL_COUNT 100
55
56 /* Size and alignment of special buffers (4KB) */
57 #define EFX_BUF_SIZE 4096
58
59 /* Depth of RX flush request fifo */
60 #define EFX_RX_FLUSH_COUNT 4
61
62 /* Generated event code for efx_generate_test_event() */
63 #define EFX_CHANNEL_MAGIC_TEST(_channel)        \
64         (0x00010100 + (_channel)->channel)
65
66 /* Generated event code for efx_generate_fill_event() */
67 #define EFX_CHANNEL_MAGIC_FILL(_channel)        \
68         (0x00010200 + (_channel)->channel)
69
70 /**************************************************************************
71  *
72  * Solarstorm hardware access
73  *
74  **************************************************************************/
75
76 static inline void efx_write_buf_tbl(struct efx_nic *efx, efx_qword_t *value,
77                                      unsigned int index)
78 {
79         efx_sram_writeq(efx, efx->membase + efx->type->buf_tbl_base,
80                         value, index);
81 }
82
83 /* Read the current event from the event queue */
84 static inline efx_qword_t *efx_event(struct efx_channel *channel,
85                                      unsigned int index)
86 {
87         return ((efx_qword_t *) (channel->eventq.addr)) +
88                 (index & channel->eventq_mask);
89 }
90
91 /* See if an event is present
92  *
93  * We check both the high and low dword of the event for all ones.  We
94  * wrote all ones when we cleared the event, and no valid event can
95  * have all ones in either its high or low dwords.  This approach is
96  * robust against reordering.
97  *
98  * Note that using a single 64-bit comparison is incorrect; even
99  * though the CPU read will be atomic, the DMA write may not be.
100  */
101 static inline int efx_event_present(efx_qword_t *event)
102 {
103         return !(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
104                   EFX_DWORD_IS_ALL_ONES(event->dword[1]));
105 }
106
107 static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b,
108                                      const efx_oword_t *mask)
109 {
110         return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) ||
111                 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
112 }
113
114 int efx_nic_test_registers(struct efx_nic *efx,
115                            const struct efx_nic_register_test *regs,
116                            size_t n_regs)
117 {
118         unsigned address = 0, i, j;
119         efx_oword_t mask, imask, original, reg, buf;
120
121         /* Falcon should be in loopback to isolate the XMAC from the PHY */
122         WARN_ON(!LOOPBACK_INTERNAL(efx));
123
124         for (i = 0; i < n_regs; ++i) {
125                 address = regs[i].address;
126                 mask = imask = regs[i].mask;
127                 EFX_INVERT_OWORD(imask);
128
129                 efx_reado(efx, &original, address);
130
131                 /* bit sweep on and off */
132                 for (j = 0; j < 128; j++) {
133                         if (!EFX_EXTRACT_OWORD32(mask, j, j))
134                                 continue;
135
136                         /* Test this testable bit can be set in isolation */
137                         EFX_AND_OWORD(reg, original, mask);
138                         EFX_SET_OWORD32(reg, j, j, 1);
139
140                         efx_writeo(efx, &reg, address);
141                         efx_reado(efx, &buf, address);
142
143                         if (efx_masked_compare_oword(&reg, &buf, &mask))
144                                 goto fail;
145
146                         /* Test this testable bit can be cleared in isolation */
147                         EFX_OR_OWORD(reg, original, mask);
148                         EFX_SET_OWORD32(reg, j, j, 0);
149
150                         efx_writeo(efx, &reg, address);
151                         efx_reado(efx, &buf, address);
152
153                         if (efx_masked_compare_oword(&reg, &buf, &mask))
154                                 goto fail;
155                 }
156
157                 efx_writeo(efx, &original, address);
158         }
159
160         return 0;
161
162 fail:
163         netif_err(efx, hw, efx->net_dev,
164                   "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT
165                   " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg),
166                   EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask));
167         return -EIO;
168 }
169
170 /**************************************************************************
171  *
172  * Special buffer handling
173  * Special buffers are used for event queues and the TX and RX
174  * descriptor rings.
175  *
176  *************************************************************************/
177
178 /*
179  * Initialise a special buffer
180  *
181  * This will define a buffer (previously allocated via
182  * efx_alloc_special_buffer()) in the buffer table, allowing
183  * it to be used for event queues, descriptor rings etc.
184  */
185 static void
186 efx_init_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
187 {
188         efx_qword_t buf_desc;
189         int index;
190         dma_addr_t dma_addr;
191         int i;
192
193         EFX_BUG_ON_PARANOID(!buffer->addr);
194
195         /* Write buffer descriptors to NIC */
196         for (i = 0; i < buffer->entries; i++) {
197                 index = buffer->index + i;
198                 dma_addr = buffer->dma_addr + (i * 4096);
199                 netif_dbg(efx, probe, efx->net_dev,
200                           "mapping special buffer %d at %llx\n",
201                           index, (unsigned long long)dma_addr);
202                 EFX_POPULATE_QWORD_3(buf_desc,
203                                      FRF_AZ_BUF_ADR_REGION, 0,
204                                      FRF_AZ_BUF_ADR_FBUF, dma_addr >> 12,
205                                      FRF_AZ_BUF_OWNER_ID_FBUF, 0);
206                 efx_write_buf_tbl(efx, &buf_desc, index);
207         }
208 }
209
210 /* Unmaps a buffer and clears the buffer table entries */
211 static void
212 efx_fini_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
213 {
214         efx_oword_t buf_tbl_upd;
215         unsigned int start = buffer->index;
216         unsigned int end = (buffer->index + buffer->entries - 1);
217
218         if (!buffer->entries)
219                 return;
220
221         netif_dbg(efx, hw, efx->net_dev, "unmapping special buffers %d-%d\n",
222                   buffer->index, buffer->index + buffer->entries - 1);
223
224         EFX_POPULATE_OWORD_4(buf_tbl_upd,
225                              FRF_AZ_BUF_UPD_CMD, 0,
226                              FRF_AZ_BUF_CLR_CMD, 1,
227                              FRF_AZ_BUF_CLR_END_ID, end,
228                              FRF_AZ_BUF_CLR_START_ID, start);
229         efx_writeo(efx, &buf_tbl_upd, FR_AZ_BUF_TBL_UPD);
230 }
231
232 /*
233  * Allocate a new special buffer
234  *
235  * This allocates memory for a new buffer, clears it and allocates a
236  * new buffer ID range.  It does not write into the buffer table.
237  *
238  * This call will allocate 4KB buffers, since 8KB buffers can't be
239  * used for event queues and descriptor rings.
240  */
241 static int efx_alloc_special_buffer(struct efx_nic *efx,
242                                     struct efx_special_buffer *buffer,
243                                     unsigned int len)
244 {
245         len = ALIGN(len, EFX_BUF_SIZE);
246
247         buffer->addr = dma_alloc_coherent(&efx->pci_dev->dev, len,
248                                           &buffer->dma_addr, GFP_KERNEL);
249         if (!buffer->addr)
250                 return -ENOMEM;
251         buffer->len = len;
252         buffer->entries = len / EFX_BUF_SIZE;
253         BUG_ON(buffer->dma_addr & (EFX_BUF_SIZE - 1));
254
255         /* All zeros is a potentially valid event so memset to 0xff */
256         memset(buffer->addr, 0xff, len);
257
258         /* Select new buffer ID */
259         buffer->index = efx->next_buffer_table;
260         efx->next_buffer_table += buffer->entries;
261
262         netif_dbg(efx, probe, efx->net_dev,
263                   "allocating special buffers %d-%d at %llx+%x "
264                   "(virt %p phys %llx)\n", buffer->index,
265                   buffer->index + buffer->entries - 1,
266                   (u64)buffer->dma_addr, len,
267                   buffer->addr, (u64)virt_to_phys(buffer->addr));
268
269         return 0;
270 }
271
272 static void
273 efx_free_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
274 {
275         if (!buffer->addr)
276                 return;
277
278         netif_dbg(efx, hw, efx->net_dev,
279                   "deallocating special buffers %d-%d at %llx+%x "
280                   "(virt %p phys %llx)\n", buffer->index,
281                   buffer->index + buffer->entries - 1,
282                   (u64)buffer->dma_addr, buffer->len,
283                   buffer->addr, (u64)virt_to_phys(buffer->addr));
284
285         dma_free_coherent(&efx->pci_dev->dev, buffer->len, buffer->addr,
286                           buffer->dma_addr);
287         buffer->addr = NULL;
288         buffer->entries = 0;
289 }
290
291 /**************************************************************************
292  *
293  * Generic buffer handling
294  * These buffers are used for interrupt status and MAC stats
295  *
296  **************************************************************************/
297
298 int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer,
299                          unsigned int len)
300 {
301         buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
302                                             &buffer->dma_addr);
303         if (!buffer->addr)
304                 return -ENOMEM;
305         buffer->len = len;
306         memset(buffer->addr, 0, len);
307         return 0;
308 }
309
310 void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
311 {
312         if (buffer->addr) {
313                 pci_free_consistent(efx->pci_dev, buffer->len,
314                                     buffer->addr, buffer->dma_addr);
315                 buffer->addr = NULL;
316         }
317 }
318
319 /**************************************************************************
320  *
321  * TX path
322  *
323  **************************************************************************/
324
325 /* Returns a pointer to the specified transmit descriptor in the TX
326  * descriptor queue belonging to the specified channel.
327  */
328 static inline efx_qword_t *
329 efx_tx_desc(struct efx_tx_queue *tx_queue, unsigned int index)
330 {
331         return ((efx_qword_t *) (tx_queue->txd.addr)) + index;
332 }
333
334 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
335 static inline void efx_notify_tx_desc(struct efx_tx_queue *tx_queue)
336 {
337         unsigned write_ptr;
338         efx_dword_t reg;
339
340         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
341         EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr);
342         efx_writed_page(tx_queue->efx, &reg,
343                         FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue);
344 }
345
346 /* Write pointer and first descriptor for TX descriptor ring */
347 static inline void efx_push_tx_desc(struct efx_tx_queue *tx_queue,
348                                     const efx_qword_t *txd)
349 {
350         unsigned write_ptr;
351         efx_oword_t reg;
352
353         BUILD_BUG_ON(FRF_AZ_TX_DESC_LBN != 0);
354         BUILD_BUG_ON(FR_AA_TX_DESC_UPD_KER != FR_BZ_TX_DESC_UPD_P0);
355
356         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
357         EFX_POPULATE_OWORD_2(reg, FRF_AZ_TX_DESC_PUSH_CMD, true,
358                              FRF_AZ_TX_DESC_WPTR, write_ptr);
359         reg.qword[0] = *txd;
360         efx_writeo_page(tx_queue->efx, &reg,
361                         FR_BZ_TX_DESC_UPD_P0, tx_queue->queue);
362 }
363
364 static inline bool
365 efx_may_push_tx_desc(struct efx_tx_queue *tx_queue, unsigned int write_count)
366 {
367         unsigned empty_read_count = ACCESS_ONCE(tx_queue->empty_read_count);
368
369         if (empty_read_count == 0)
370                 return false;
371
372         tx_queue->empty_read_count = 0;
373         return ((empty_read_count ^ write_count) & ~EFX_EMPTY_COUNT_VALID) == 0;
374 }
375
376 /* For each entry inserted into the software descriptor ring, create a
377  * descriptor in the hardware TX descriptor ring (in host memory), and
378  * write a doorbell.
379  */
380 void efx_nic_push_buffers(struct efx_tx_queue *tx_queue)
381 {
382
383         struct efx_tx_buffer *buffer;
384         efx_qword_t *txd;
385         unsigned write_ptr;
386         unsigned old_write_count = tx_queue->write_count;
387
388         BUG_ON(tx_queue->write_count == tx_queue->insert_count);
389
390         do {
391                 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
392                 buffer = &tx_queue->buffer[write_ptr];
393                 txd = efx_tx_desc(tx_queue, write_ptr);
394                 ++tx_queue->write_count;
395
396                 /* Create TX descriptor ring entry */
397                 EFX_POPULATE_QWORD_4(*txd,
398                                      FSF_AZ_TX_KER_CONT, buffer->continuation,
399                                      FSF_AZ_TX_KER_BYTE_COUNT, buffer->len,
400                                      FSF_AZ_TX_KER_BUF_REGION, 0,
401                                      FSF_AZ_TX_KER_BUF_ADDR, buffer->dma_addr);
402         } while (tx_queue->write_count != tx_queue->insert_count);
403
404         wmb(); /* Ensure descriptors are written before they are fetched */
405
406         if (efx_may_push_tx_desc(tx_queue, old_write_count)) {
407                 txd = efx_tx_desc(tx_queue,
408                                   old_write_count & tx_queue->ptr_mask);
409                 efx_push_tx_desc(tx_queue, txd);
410                 ++tx_queue->pushes;
411         } else {
412                 efx_notify_tx_desc(tx_queue);
413         }
414 }
415
416 /* Allocate hardware resources for a TX queue */
417 int efx_nic_probe_tx(struct efx_tx_queue *tx_queue)
418 {
419         struct efx_nic *efx = tx_queue->efx;
420         unsigned entries;
421
422         entries = tx_queue->ptr_mask + 1;
423         return efx_alloc_special_buffer(efx, &tx_queue->txd,
424                                         entries * sizeof(efx_qword_t));
425 }
426
427 void efx_nic_init_tx(struct efx_tx_queue *tx_queue)
428 {
429         struct efx_nic *efx = tx_queue->efx;
430         efx_oword_t reg;
431
432         tx_queue->flushed = FLUSH_NONE;
433
434         /* Pin TX descriptor ring */
435         efx_init_special_buffer(efx, &tx_queue->txd);
436
437         /* Push TX descriptor ring to card */
438         EFX_POPULATE_OWORD_10(reg,
439                               FRF_AZ_TX_DESCQ_EN, 1,
440                               FRF_AZ_TX_ISCSI_DDIG_EN, 0,
441                               FRF_AZ_TX_ISCSI_HDIG_EN, 0,
442                               FRF_AZ_TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
443                               FRF_AZ_TX_DESCQ_EVQ_ID,
444                               tx_queue->channel->channel,
445                               FRF_AZ_TX_DESCQ_OWNER_ID, 0,
446                               FRF_AZ_TX_DESCQ_LABEL, tx_queue->queue,
447                               FRF_AZ_TX_DESCQ_SIZE,
448                               __ffs(tx_queue->txd.entries),
449                               FRF_AZ_TX_DESCQ_TYPE, 0,
450                               FRF_BZ_TX_NON_IP_DROP_DIS, 1);
451
452         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
453                 int csum = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
454                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_TX_IP_CHKSM_DIS, !csum);
455                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_TX_TCP_CHKSM_DIS,
456                                     !csum);
457         }
458
459         efx_writeo_table(efx, &reg, efx->type->txd_ptr_tbl_base,
460                          tx_queue->queue);
461
462         if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) {
463                 /* Only 128 bits in this register */
464                 BUILD_BUG_ON(EFX_MAX_TX_QUEUES > 128);
465
466                 efx_reado(efx, &reg, FR_AA_TX_CHKSM_CFG);
467                 if (tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD)
468                         clear_bit_le(tx_queue->queue, (void *)&reg);
469                 else
470                         set_bit_le(tx_queue->queue, (void *)&reg);
471                 efx_writeo(efx, &reg, FR_AA_TX_CHKSM_CFG);
472         }
473
474         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
475                 EFX_POPULATE_OWORD_1(reg,
476                                      FRF_BZ_TX_PACE,
477                                      (tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI) ?
478                                      FFE_BZ_TX_PACE_OFF :
479                                      FFE_BZ_TX_PACE_RESERVED);
480                 efx_writeo_table(efx, &reg, FR_BZ_TX_PACE_TBL,
481                                  tx_queue->queue);
482         }
483 }
484
485 static void efx_flush_tx_queue(struct efx_tx_queue *tx_queue)
486 {
487         struct efx_nic *efx = tx_queue->efx;
488         efx_oword_t tx_flush_descq;
489
490         tx_queue->flushed = FLUSH_PENDING;
491
492         /* Post a flush command */
493         EFX_POPULATE_OWORD_2(tx_flush_descq,
494                              FRF_AZ_TX_FLUSH_DESCQ_CMD, 1,
495                              FRF_AZ_TX_FLUSH_DESCQ, tx_queue->queue);
496         efx_writeo(efx, &tx_flush_descq, FR_AZ_TX_FLUSH_DESCQ);
497 }
498
499 void efx_nic_fini_tx(struct efx_tx_queue *tx_queue)
500 {
501         struct efx_nic *efx = tx_queue->efx;
502         efx_oword_t tx_desc_ptr;
503
504         /* The queue should have been flushed */
505         WARN_ON(tx_queue->flushed != FLUSH_DONE);
506
507         /* Remove TX descriptor ring from card */
508         EFX_ZERO_OWORD(tx_desc_ptr);
509         efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
510                          tx_queue->queue);
511
512         /* Unpin TX descriptor ring */
513         efx_fini_special_buffer(efx, &tx_queue->txd);
514 }
515
516 /* Free buffers backing TX queue */
517 void efx_nic_remove_tx(struct efx_tx_queue *tx_queue)
518 {
519         efx_free_special_buffer(tx_queue->efx, &tx_queue->txd);
520 }
521
522 /**************************************************************************
523  *
524  * RX path
525  *
526  **************************************************************************/
527
528 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
529 static inline efx_qword_t *
530 efx_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
531 {
532         return ((efx_qword_t *) (rx_queue->rxd.addr)) + index;
533 }
534
535 /* This creates an entry in the RX descriptor queue */
536 static inline void
537 efx_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned index)
538 {
539         struct efx_rx_buffer *rx_buf;
540         efx_qword_t *rxd;
541
542         rxd = efx_rx_desc(rx_queue, index);
543         rx_buf = efx_rx_buffer(rx_queue, index);
544         EFX_POPULATE_QWORD_3(*rxd,
545                              FSF_AZ_RX_KER_BUF_SIZE,
546                              rx_buf->len -
547                              rx_queue->efx->type->rx_buffer_padding,
548                              FSF_AZ_RX_KER_BUF_REGION, 0,
549                              FSF_AZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
550 }
551
552 /* This writes to the RX_DESC_WPTR register for the specified receive
553  * descriptor ring.
554  */
555 void efx_nic_notify_rx_desc(struct efx_rx_queue *rx_queue)
556 {
557         struct efx_nic *efx = rx_queue->efx;
558         efx_dword_t reg;
559         unsigned write_ptr;
560
561         while (rx_queue->notified_count != rx_queue->added_count) {
562                 efx_build_rx_desc(
563                         rx_queue,
564                         rx_queue->notified_count & rx_queue->ptr_mask);
565                 ++rx_queue->notified_count;
566         }
567
568         wmb();
569         write_ptr = rx_queue->added_count & rx_queue->ptr_mask;
570         EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr);
571         efx_writed_page(efx, &reg, FR_AZ_RX_DESC_UPD_DWORD_P0,
572                         efx_rx_queue_index(rx_queue));
573 }
574
575 int efx_nic_probe_rx(struct efx_rx_queue *rx_queue)
576 {
577         struct efx_nic *efx = rx_queue->efx;
578         unsigned entries;
579
580         entries = rx_queue->ptr_mask + 1;
581         return efx_alloc_special_buffer(efx, &rx_queue->rxd,
582                                         entries * sizeof(efx_qword_t));
583 }
584
585 void efx_nic_init_rx(struct efx_rx_queue *rx_queue)
586 {
587         efx_oword_t rx_desc_ptr;
588         struct efx_nic *efx = rx_queue->efx;
589         bool is_b0 = efx_nic_rev(efx) >= EFX_REV_FALCON_B0;
590         bool iscsi_digest_en = is_b0;
591
592         netif_dbg(efx, hw, efx->net_dev,
593                   "RX queue %d ring in special buffers %d-%d\n",
594                   efx_rx_queue_index(rx_queue), rx_queue->rxd.index,
595                   rx_queue->rxd.index + rx_queue->rxd.entries - 1);
596
597         rx_queue->flushed = FLUSH_NONE;
598
599         /* Pin RX descriptor ring */
600         efx_init_special_buffer(efx, &rx_queue->rxd);
601
602         /* Push RX descriptor ring to card */
603         EFX_POPULATE_OWORD_10(rx_desc_ptr,
604                               FRF_AZ_RX_ISCSI_DDIG_EN, iscsi_digest_en,
605                               FRF_AZ_RX_ISCSI_HDIG_EN, iscsi_digest_en,
606                               FRF_AZ_RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
607                               FRF_AZ_RX_DESCQ_EVQ_ID,
608                               efx_rx_queue_channel(rx_queue)->channel,
609                               FRF_AZ_RX_DESCQ_OWNER_ID, 0,
610                               FRF_AZ_RX_DESCQ_LABEL,
611                               efx_rx_queue_index(rx_queue),
612                               FRF_AZ_RX_DESCQ_SIZE,
613                               __ffs(rx_queue->rxd.entries),
614                               FRF_AZ_RX_DESCQ_TYPE, 0 /* kernel queue */ ,
615                               /* For >=B0 this is scatter so disable */
616                               FRF_AZ_RX_DESCQ_JUMBO, !is_b0,
617                               FRF_AZ_RX_DESCQ_EN, 1);
618         efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
619                          efx_rx_queue_index(rx_queue));
620 }
621
622 static void efx_flush_rx_queue(struct efx_rx_queue *rx_queue)
623 {
624         struct efx_nic *efx = rx_queue->efx;
625         efx_oword_t rx_flush_descq;
626
627         rx_queue->flushed = FLUSH_PENDING;
628
629         /* Post a flush command */
630         EFX_POPULATE_OWORD_2(rx_flush_descq,
631                              FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
632                              FRF_AZ_RX_FLUSH_DESCQ,
633                              efx_rx_queue_index(rx_queue));
634         efx_writeo(efx, &rx_flush_descq, FR_AZ_RX_FLUSH_DESCQ);
635 }
636
637 void efx_nic_fini_rx(struct efx_rx_queue *rx_queue)
638 {
639         efx_oword_t rx_desc_ptr;
640         struct efx_nic *efx = rx_queue->efx;
641
642         /* The queue should already have been flushed */
643         WARN_ON(rx_queue->flushed != FLUSH_DONE);
644
645         /* Remove RX descriptor ring from card */
646         EFX_ZERO_OWORD(rx_desc_ptr);
647         efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
648                          efx_rx_queue_index(rx_queue));
649
650         /* Unpin RX descriptor ring */
651         efx_fini_special_buffer(efx, &rx_queue->rxd);
652 }
653
654 /* Free buffers backing RX queue */
655 void efx_nic_remove_rx(struct efx_rx_queue *rx_queue)
656 {
657         efx_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
658 }
659
660 /**************************************************************************
661  *
662  * Event queue processing
663  * Event queues are processed by per-channel tasklets.
664  *
665  **************************************************************************/
666
667 /* Update a channel's event queue's read pointer (RPTR) register
668  *
669  * This writes the EVQ_RPTR_REG register for the specified channel's
670  * event queue.
671  */
672 void efx_nic_eventq_read_ack(struct efx_channel *channel)
673 {
674         efx_dword_t reg;
675         struct efx_nic *efx = channel->efx;
676
677         EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR,
678                              channel->eventq_read_ptr & channel->eventq_mask);
679         efx_writed_table(efx, &reg, efx->type->evq_rptr_tbl_base,
680                          channel->channel);
681 }
682
683 /* Use HW to insert a SW defined event */
684 static void efx_generate_event(struct efx_channel *channel, efx_qword_t *event)
685 {
686         efx_oword_t drv_ev_reg;
687
688         BUILD_BUG_ON(FRF_AZ_DRV_EV_DATA_LBN != 0 ||
689                      FRF_AZ_DRV_EV_DATA_WIDTH != 64);
690         drv_ev_reg.u32[0] = event->u32[0];
691         drv_ev_reg.u32[1] = event->u32[1];
692         drv_ev_reg.u32[2] = 0;
693         drv_ev_reg.u32[3] = 0;
694         EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, channel->channel);
695         efx_writeo(channel->efx, &drv_ev_reg, FR_AZ_DRV_EV);
696 }
697
698 /* Handle a transmit completion event
699  *
700  * The NIC batches TX completion events; the message we receive is of
701  * the form "complete all TX events up to this index".
702  */
703 static int
704 efx_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
705 {
706         unsigned int tx_ev_desc_ptr;
707         unsigned int tx_ev_q_label;
708         struct efx_tx_queue *tx_queue;
709         struct efx_nic *efx = channel->efx;
710         int tx_packets = 0;
711
712         if (likely(EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_COMP))) {
713                 /* Transmit completion */
714                 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_DESC_PTR);
715                 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
716                 tx_queue = efx_channel_get_tx_queue(
717                         channel, tx_ev_q_label % EFX_TXQ_TYPES);
718                 tx_packets = ((tx_ev_desc_ptr - tx_queue->read_count) &
719                               tx_queue->ptr_mask);
720                 channel->irq_mod_score += tx_packets;
721                 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
722         } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_WQ_FF_FULL)) {
723                 /* Rewrite the FIFO write pointer */
724                 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
725                 tx_queue = efx_channel_get_tx_queue(
726                         channel, tx_ev_q_label % EFX_TXQ_TYPES);
727
728                 if (efx_dev_registered(efx))
729                         netif_tx_lock(efx->net_dev);
730                 efx_notify_tx_desc(tx_queue);
731                 if (efx_dev_registered(efx))
732                         netif_tx_unlock(efx->net_dev);
733         } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_PKT_ERR) &&
734                    EFX_WORKAROUND_10727(efx)) {
735                 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
736         } else {
737                 netif_err(efx, tx_err, efx->net_dev,
738                           "channel %d unexpected TX event "
739                           EFX_QWORD_FMT"\n", channel->channel,
740                           EFX_QWORD_VAL(*event));
741         }
742
743         return tx_packets;
744 }
745
746 /* Detect errors included in the rx_evt_pkt_ok bit. */
747 static void efx_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
748                                  const efx_qword_t *event,
749                                  bool *rx_ev_pkt_ok,
750                                  bool *discard)
751 {
752         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
753         struct efx_nic *efx = rx_queue->efx;
754         bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
755         bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
756         bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
757         bool rx_ev_other_err, rx_ev_pause_frm;
758         bool rx_ev_hdr_type, rx_ev_mcast_pkt;
759         unsigned rx_ev_pkt_type;
760
761         rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
762         rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
763         rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_TOBE_DISC);
764         rx_ev_pkt_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_TYPE);
765         rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
766                                                  FSF_AZ_RX_EV_BUF_OWNER_ID_ERR);
767         rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
768                                                   FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR);
769         rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
770                                                    FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR);
771         rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_ETH_CRC_ERR);
772         rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_FRM_TRUNC);
773         rx_ev_drib_nib = ((efx_nic_rev(efx) >= EFX_REV_FALCON_B0) ?
774                           0 : EFX_QWORD_FIELD(*event, FSF_AA_RX_EV_DRIB_NIB));
775         rx_ev_pause_frm = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PAUSE_FRM_ERR);
776
777         /* Every error apart from tobe_disc and pause_frm */
778         rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
779                            rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
780                            rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
781
782         /* Count errors that are not in MAC stats.  Ignore expected
783          * checksum errors during self-test. */
784         if (rx_ev_frm_trunc)
785                 ++channel->n_rx_frm_trunc;
786         else if (rx_ev_tobe_disc)
787                 ++channel->n_rx_tobe_disc;
788         else if (!efx->loopback_selftest) {
789                 if (rx_ev_ip_hdr_chksum_err)
790                         ++channel->n_rx_ip_hdr_chksum_err;
791                 else if (rx_ev_tcp_udp_chksum_err)
792                         ++channel->n_rx_tcp_udp_chksum_err;
793         }
794
795         /* The frame must be discarded if any of these are true. */
796         *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
797                     rx_ev_tobe_disc | rx_ev_pause_frm);
798
799         /* TOBE_DISC is expected on unicast mismatches; don't print out an
800          * error message.  FRM_TRUNC indicates RXDP dropped the packet due
801          * to a FIFO overflow.
802          */
803 #ifdef EFX_ENABLE_DEBUG
804         if (rx_ev_other_err && net_ratelimit()) {
805                 netif_dbg(efx, rx_err, efx->net_dev,
806                           " RX queue %d unexpected RX event "
807                           EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n",
808                           efx_rx_queue_index(rx_queue), EFX_QWORD_VAL(*event),
809                           rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
810                           rx_ev_ip_hdr_chksum_err ?
811                           " [IP_HDR_CHKSUM_ERR]" : "",
812                           rx_ev_tcp_udp_chksum_err ?
813                           " [TCP_UDP_CHKSUM_ERR]" : "",
814                           rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
815                           rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
816                           rx_ev_drib_nib ? " [DRIB_NIB]" : "",
817                           rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
818                           rx_ev_pause_frm ? " [PAUSE]" : "");
819         }
820 #endif
821 }
822
823 /* Handle receive events that are not in-order. */
824 static void
825 efx_handle_rx_bad_index(struct efx_rx_queue *rx_queue, unsigned index)
826 {
827         struct efx_nic *efx = rx_queue->efx;
828         unsigned expected, dropped;
829
830         expected = rx_queue->removed_count & rx_queue->ptr_mask;
831         dropped = (index - expected) & rx_queue->ptr_mask;
832         netif_info(efx, rx_err, efx->net_dev,
833                    "dropped %d events (index=%d expected=%d)\n",
834                    dropped, index, expected);
835
836         efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
837                            RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
838 }
839
840 /* Handle a packet received event
841  *
842  * The NIC gives a "discard" flag if it's a unicast packet with the
843  * wrong destination address
844  * Also "is multicast" and "matches multicast filter" flags can be used to
845  * discard non-matching multicast packets.
846  */
847 static void
848 efx_handle_rx_event(struct efx_channel *channel, const efx_qword_t *event)
849 {
850         unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt;
851         unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
852         unsigned expected_ptr;
853         bool rx_ev_pkt_ok, discard = false, checksummed;
854         struct efx_rx_queue *rx_queue;
855         struct efx_nic *efx = channel->efx;
856
857         /* Basic packet information */
858         rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_BYTE_CNT);
859         rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_OK);
860         rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
861         WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_JUMBO_CONT));
862         WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_SOP) != 1);
863         WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_Q_LABEL) !=
864                 channel->channel);
865
866         rx_queue = efx_channel_get_rx_queue(channel);
867
868         rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_DESC_PTR);
869         expected_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
870         if (unlikely(rx_ev_desc_ptr != expected_ptr))
871                 efx_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
872
873         if (likely(rx_ev_pkt_ok)) {
874                 /* If packet is marked as OK and packet type is TCP/IP or
875                  * UDP/IP, then we can rely on the hardware checksum.
876                  */
877                 checksummed =
878                         likely(efx->rx_checksum_enabled) &&
879                         (rx_ev_hdr_type == FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_TCP ||
880                          rx_ev_hdr_type == FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_UDP);
881         } else {
882                 efx_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok, &discard);
883                 checksummed = false;
884         }
885
886         /* Detect multicast packets that didn't match the filter */
887         rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
888         if (rx_ev_mcast_pkt) {
889                 unsigned int rx_ev_mcast_hash_match =
890                         EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_HASH_MATCH);
891
892                 if (unlikely(!rx_ev_mcast_hash_match)) {
893                         ++channel->n_rx_mcast_mismatch;
894                         discard = true;
895                 }
896         }
897
898         channel->irq_mod_score += 2;
899
900         /* Handle received packet */
901         efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt,
902                       checksummed, discard);
903 }
904
905 static void
906 efx_handle_generated_event(struct efx_channel *channel, efx_qword_t *event)
907 {
908         struct efx_nic *efx = channel->efx;
909         unsigned code;
910
911         code = EFX_QWORD_FIELD(*event, FSF_AZ_DRV_GEN_EV_MAGIC);
912         if (code == EFX_CHANNEL_MAGIC_TEST(channel))
913                 ; /* ignore */
914         else if (code == EFX_CHANNEL_MAGIC_FILL(channel))
915                 /* The queue must be empty, so we won't receive any rx
916                  * events, so efx_process_channel() won't refill the
917                  * queue. Refill it here */
918                 efx_fast_push_rx_descriptors(efx_channel_get_rx_queue(channel));
919         else
920                 netif_dbg(efx, hw, efx->net_dev, "channel %d received "
921                           "generated event "EFX_QWORD_FMT"\n",
922                           channel->channel, EFX_QWORD_VAL(*event));
923 }
924
925 static void
926 efx_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
927 {
928         struct efx_nic *efx = channel->efx;
929         unsigned int ev_sub_code;
930         unsigned int ev_sub_data;
931
932         ev_sub_code = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBCODE);
933         ev_sub_data = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
934
935         switch (ev_sub_code) {
936         case FSE_AZ_TX_DESCQ_FLS_DONE_EV:
937                 netif_vdbg(efx, hw, efx->net_dev, "channel %d TXQ %d flushed\n",
938                            channel->channel, ev_sub_data);
939                 break;
940         case FSE_AZ_RX_DESCQ_FLS_DONE_EV:
941                 netif_vdbg(efx, hw, efx->net_dev, "channel %d RXQ %d flushed\n",
942                            channel->channel, ev_sub_data);
943                 break;
944         case FSE_AZ_EVQ_INIT_DONE_EV:
945                 netif_dbg(efx, hw, efx->net_dev,
946                           "channel %d EVQ %d initialised\n",
947                           channel->channel, ev_sub_data);
948                 break;
949         case FSE_AZ_SRM_UPD_DONE_EV:
950                 netif_vdbg(efx, hw, efx->net_dev,
951                            "channel %d SRAM update done\n", channel->channel);
952                 break;
953         case FSE_AZ_WAKE_UP_EV:
954                 netif_vdbg(efx, hw, efx->net_dev,
955                            "channel %d RXQ %d wakeup event\n",
956                            channel->channel, ev_sub_data);
957                 break;
958         case FSE_AZ_TIMER_EV:
959                 netif_vdbg(efx, hw, efx->net_dev,
960                            "channel %d RX queue %d timer expired\n",
961                            channel->channel, ev_sub_data);
962                 break;
963         case FSE_AA_RX_RECOVER_EV:
964                 netif_err(efx, rx_err, efx->net_dev,
965                           "channel %d seen DRIVER RX_RESET event. "
966                         "Resetting.\n", channel->channel);
967                 atomic_inc(&efx->rx_reset);
968                 efx_schedule_reset(efx,
969                                    EFX_WORKAROUND_6555(efx) ?
970                                    RESET_TYPE_RX_RECOVERY :
971                                    RESET_TYPE_DISABLE);
972                 break;
973         case FSE_BZ_RX_DSC_ERROR_EV:
974                 netif_err(efx, rx_err, efx->net_dev,
975                           "RX DMA Q %d reports descriptor fetch error."
976                           " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
977                 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
978                 break;
979         case FSE_BZ_TX_DSC_ERROR_EV:
980                 netif_err(efx, tx_err, efx->net_dev,
981                           "TX DMA Q %d reports descriptor fetch error."
982                           " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
983                 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
984                 break;
985         default:
986                 netif_vdbg(efx, hw, efx->net_dev,
987                            "channel %d unknown driver event code %d "
988                            "data %04x\n", channel->channel, ev_sub_code,
989                            ev_sub_data);
990                 break;
991         }
992 }
993
994 int efx_nic_process_eventq(struct efx_channel *channel, int budget)
995 {
996         struct efx_nic *efx = channel->efx;
997         unsigned int read_ptr;
998         efx_qword_t event, *p_event;
999         int ev_code;
1000         int tx_packets = 0;
1001         int spent = 0;
1002
1003         read_ptr = channel->eventq_read_ptr;
1004
1005         for (;;) {
1006                 p_event = efx_event(channel, read_ptr);
1007                 event = *p_event;
1008
1009                 if (!efx_event_present(&event))
1010                         /* End of events */
1011                         break;
1012
1013                 netif_vdbg(channel->efx, intr, channel->efx->net_dev,
1014                            "channel %d event is "EFX_QWORD_FMT"\n",
1015                            channel->channel, EFX_QWORD_VAL(event));
1016
1017                 /* Clear this event by marking it all ones */
1018                 EFX_SET_QWORD(*p_event);
1019
1020                 ++read_ptr;
1021
1022                 ev_code = EFX_QWORD_FIELD(event, FSF_AZ_EV_CODE);
1023
1024                 switch (ev_code) {
1025                 case FSE_AZ_EV_CODE_RX_EV:
1026                         efx_handle_rx_event(channel, &event);
1027                         if (++spent == budget)
1028                                 goto out;
1029                         break;
1030                 case FSE_AZ_EV_CODE_TX_EV:
1031                         tx_packets += efx_handle_tx_event(channel, &event);
1032                         if (tx_packets > efx->txq_entries) {
1033                                 spent = budget;
1034                                 goto out;
1035                         }
1036                         break;
1037                 case FSE_AZ_EV_CODE_DRV_GEN_EV:
1038                         efx_handle_generated_event(channel, &event);
1039                         break;
1040                 case FSE_AZ_EV_CODE_DRIVER_EV:
1041                         efx_handle_driver_event(channel, &event);
1042                         break;
1043                 case FSE_CZ_EV_CODE_MCDI_EV:
1044                         efx_mcdi_process_event(channel, &event);
1045                         break;
1046                 case FSE_AZ_EV_CODE_GLOBAL_EV:
1047                         if (efx->type->handle_global_event &&
1048                             efx->type->handle_global_event(channel, &event))
1049                                 break;
1050                         /* else fall through */
1051                 default:
1052                         netif_err(channel->efx, hw, channel->efx->net_dev,
1053                                   "channel %d unknown event type %d (data "
1054                                   EFX_QWORD_FMT ")\n", channel->channel,
1055                                   ev_code, EFX_QWORD_VAL(event));
1056                 }
1057         }
1058
1059 out:
1060         channel->eventq_read_ptr = read_ptr;
1061         return spent;
1062 }
1063
1064 /* Check whether an event is present in the eventq at the current
1065  * read pointer.  Only useful for self-test.
1066  */
1067 bool efx_nic_event_present(struct efx_channel *channel)
1068 {
1069         return efx_event_present(efx_event(channel, channel->eventq_read_ptr));
1070 }
1071
1072 /* Allocate buffer table entries for event queue */
1073 int efx_nic_probe_eventq(struct efx_channel *channel)
1074 {
1075         struct efx_nic *efx = channel->efx;
1076         unsigned entries;
1077
1078         entries = channel->eventq_mask + 1;
1079         return efx_alloc_special_buffer(efx, &channel->eventq,
1080                                         entries * sizeof(efx_qword_t));
1081 }
1082
1083 void efx_nic_init_eventq(struct efx_channel *channel)
1084 {
1085         efx_oword_t reg;
1086         struct efx_nic *efx = channel->efx;
1087
1088         netif_dbg(efx, hw, efx->net_dev,
1089                   "channel %d event queue in special buffers %d-%d\n",
1090                   channel->channel, channel->eventq.index,
1091                   channel->eventq.index + channel->eventq.entries - 1);
1092
1093         if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) {
1094                 EFX_POPULATE_OWORD_3(reg,
1095                                      FRF_CZ_TIMER_Q_EN, 1,
1096                                      FRF_CZ_HOST_NOTIFY_MODE, 0,
1097                                      FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
1098                 efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL, channel->channel);
1099         }
1100
1101         /* Pin event queue buffer */
1102         efx_init_special_buffer(efx, &channel->eventq);
1103
1104         /* Fill event queue with all ones (i.e. empty events) */
1105         memset(channel->eventq.addr, 0xff, channel->eventq.len);
1106
1107         /* Push event queue to card */
1108         EFX_POPULATE_OWORD_3(reg,
1109                              FRF_AZ_EVQ_EN, 1,
1110                              FRF_AZ_EVQ_SIZE, __ffs(channel->eventq.entries),
1111                              FRF_AZ_EVQ_BUF_BASE_ID, channel->eventq.index);
1112         efx_writeo_table(efx, &reg, efx->type->evq_ptr_tbl_base,
1113                          channel->channel);
1114
1115         efx->type->push_irq_moderation(channel);
1116 }
1117
1118 void efx_nic_fini_eventq(struct efx_channel *channel)
1119 {
1120         efx_oword_t reg;
1121         struct efx_nic *efx = channel->efx;
1122
1123         /* Remove event queue from card */
1124         EFX_ZERO_OWORD(reg);
1125         efx_writeo_table(efx, &reg, efx->type->evq_ptr_tbl_base,
1126                          channel->channel);
1127         if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0)
1128                 efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL, channel->channel);
1129
1130         /* Unpin event queue */
1131         efx_fini_special_buffer(efx, &channel->eventq);
1132 }
1133
1134 /* Free buffers backing event queue */
1135 void efx_nic_remove_eventq(struct efx_channel *channel)
1136 {
1137         efx_free_special_buffer(channel->efx, &channel->eventq);
1138 }
1139
1140
1141 void efx_nic_generate_test_event(struct efx_channel *channel)
1142 {
1143         unsigned int magic = EFX_CHANNEL_MAGIC_TEST(channel);
1144         efx_qword_t test_event;
1145
1146         EFX_POPULATE_QWORD_2(test_event, FSF_AZ_EV_CODE,
1147                              FSE_AZ_EV_CODE_DRV_GEN_EV,
1148                              FSF_AZ_DRV_GEN_EV_MAGIC, magic);
1149         efx_generate_event(channel, &test_event);
1150 }
1151
1152 void efx_nic_generate_fill_event(struct efx_channel *channel)
1153 {
1154         unsigned int magic = EFX_CHANNEL_MAGIC_FILL(channel);
1155         efx_qword_t test_event;
1156
1157         EFX_POPULATE_QWORD_2(test_event, FSF_AZ_EV_CODE,
1158                              FSE_AZ_EV_CODE_DRV_GEN_EV,
1159                              FSF_AZ_DRV_GEN_EV_MAGIC, magic);
1160         efx_generate_event(channel, &test_event);
1161 }
1162
1163 /**************************************************************************
1164  *
1165  * Flush handling
1166  *
1167  **************************************************************************/
1168
1169
1170 static void efx_poll_flush_events(struct efx_nic *efx)
1171 {
1172         struct efx_channel *channel = efx_get_channel(efx, 0);
1173         struct efx_tx_queue *tx_queue;
1174         struct efx_rx_queue *rx_queue;
1175         unsigned int read_ptr = channel->eventq_read_ptr;
1176         unsigned int end_ptr = read_ptr + channel->eventq_mask - 1;
1177
1178         do {
1179                 efx_qword_t *event = efx_event(channel, read_ptr);
1180                 int ev_code, ev_sub_code, ev_queue;
1181                 bool ev_failed;
1182
1183                 if (!efx_event_present(event))
1184                         break;
1185
1186                 ev_code = EFX_QWORD_FIELD(*event, FSF_AZ_EV_CODE);
1187                 ev_sub_code = EFX_QWORD_FIELD(*event,
1188                                               FSF_AZ_DRIVER_EV_SUBCODE);
1189                 if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV &&
1190                     ev_sub_code == FSE_AZ_TX_DESCQ_FLS_DONE_EV) {
1191                         ev_queue = EFX_QWORD_FIELD(*event,
1192                                                    FSF_AZ_DRIVER_EV_SUBDATA);
1193                         if (ev_queue < EFX_TXQ_TYPES * efx->n_tx_channels) {
1194                                 tx_queue = efx_get_tx_queue(
1195                                         efx, ev_queue / EFX_TXQ_TYPES,
1196                                         ev_queue % EFX_TXQ_TYPES);
1197                                 tx_queue->flushed = FLUSH_DONE;
1198                         }
1199                 } else if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV &&
1200                            ev_sub_code == FSE_AZ_RX_DESCQ_FLS_DONE_EV) {
1201                         ev_queue = EFX_QWORD_FIELD(
1202                                 *event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
1203                         ev_failed = EFX_QWORD_FIELD(
1204                                 *event, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
1205                         if (ev_queue < efx->n_rx_channels) {
1206                                 rx_queue = efx_get_rx_queue(efx, ev_queue);
1207                                 rx_queue->flushed =
1208                                         ev_failed ? FLUSH_FAILED : FLUSH_DONE;
1209                         }
1210                 }
1211
1212                 /* We're about to destroy the queue anyway, so
1213                  * it's ok to throw away every non-flush event */
1214                 EFX_SET_QWORD(*event);
1215
1216                 ++read_ptr;
1217         } while (read_ptr != end_ptr);
1218
1219         channel->eventq_read_ptr = read_ptr;
1220 }
1221
1222 /* Handle tx and rx flushes at the same time, since they run in
1223  * parallel in the hardware and there's no reason for us to
1224  * serialise them */
1225 int efx_nic_flush_queues(struct efx_nic *efx)
1226 {
1227         struct efx_channel *channel;
1228         struct efx_rx_queue *rx_queue;
1229         struct efx_tx_queue *tx_queue;
1230         int i, tx_pending, rx_pending;
1231
1232         /* If necessary prepare the hardware for flushing */
1233         efx->type->prepare_flush(efx);
1234
1235         /* Flush all tx queues in parallel */
1236         efx_for_each_channel(channel, efx) {
1237                 efx_for_each_possible_channel_tx_queue(tx_queue, channel) {
1238                         if (tx_queue->initialised)
1239                                 efx_flush_tx_queue(tx_queue);
1240                 }
1241         }
1242
1243         /* The hardware supports four concurrent rx flushes, each of which may
1244          * need to be retried if there is an outstanding descriptor fetch */
1245         for (i = 0; i < EFX_FLUSH_POLL_COUNT; ++i) {
1246                 rx_pending = tx_pending = 0;
1247                 efx_for_each_channel(channel, efx) {
1248                         efx_for_each_channel_rx_queue(rx_queue, channel) {
1249                                 if (rx_queue->flushed == FLUSH_PENDING)
1250                                         ++rx_pending;
1251                         }
1252                 }
1253                 efx_for_each_channel(channel, efx) {
1254                         efx_for_each_channel_rx_queue(rx_queue, channel) {
1255                                 if (rx_pending == EFX_RX_FLUSH_COUNT)
1256                                         break;
1257                                 if (rx_queue->flushed == FLUSH_FAILED ||
1258                                     rx_queue->flushed == FLUSH_NONE) {
1259                                         efx_flush_rx_queue(rx_queue);
1260                                         ++rx_pending;
1261                                 }
1262                         }
1263                         efx_for_each_possible_channel_tx_queue(tx_queue, channel) {
1264                                 if (tx_queue->initialised &&
1265                                     tx_queue->flushed != FLUSH_DONE)
1266                                         ++tx_pending;
1267                         }
1268                 }
1269
1270                 if (rx_pending == 0 && tx_pending == 0)
1271                         return 0;
1272
1273                 msleep(EFX_FLUSH_INTERVAL);
1274                 efx_poll_flush_events(efx);
1275         }
1276
1277         /* Mark the queues as all flushed. We're going to return failure
1278          * leading to a reset, or fake up success anyway */
1279         efx_for_each_channel(channel, efx) {
1280                 efx_for_each_possible_channel_tx_queue(tx_queue, channel) {
1281                         if (tx_queue->initialised &&
1282                             tx_queue->flushed != FLUSH_DONE)
1283                                 netif_err(efx, hw, efx->net_dev,
1284                                           "tx queue %d flush command timed out\n",
1285                                           tx_queue->queue);
1286                         tx_queue->flushed = FLUSH_DONE;
1287                 }
1288                 efx_for_each_channel_rx_queue(rx_queue, channel) {
1289                         if (rx_queue->flushed != FLUSH_DONE)
1290                                 netif_err(efx, hw, efx->net_dev,
1291                                           "rx queue %d flush command timed out\n",
1292                                           efx_rx_queue_index(rx_queue));
1293                         rx_queue->flushed = FLUSH_DONE;
1294                 }
1295         }
1296
1297         return -ETIMEDOUT;
1298 }
1299
1300 /**************************************************************************
1301  *
1302  * Hardware interrupts
1303  * The hardware interrupt handler does very little work; all the event
1304  * queue processing is carried out by per-channel tasklets.
1305  *
1306  **************************************************************************/
1307
1308 /* Enable/disable/generate interrupts */
1309 static inline void efx_nic_interrupts(struct efx_nic *efx,
1310                                       bool enabled, bool force)
1311 {
1312         efx_oword_t int_en_reg_ker;
1313
1314         EFX_POPULATE_OWORD_3(int_en_reg_ker,
1315                              FRF_AZ_KER_INT_LEVE_SEL, efx->fatal_irq_level,
1316                              FRF_AZ_KER_INT_KER, force,
1317                              FRF_AZ_DRV_INT_EN_KER, enabled);
1318         efx_writeo(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER);
1319 }
1320
1321 void efx_nic_enable_interrupts(struct efx_nic *efx)
1322 {
1323         struct efx_channel *channel;
1324
1325         EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1326         wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1327
1328         /* Enable interrupts */
1329         efx_nic_interrupts(efx, true, false);
1330
1331         /* Force processing of all the channels to get the EVQ RPTRs up to
1332            date */
1333         efx_for_each_channel(channel, efx)
1334                 efx_schedule_channel(channel);
1335 }
1336
1337 void efx_nic_disable_interrupts(struct efx_nic *efx)
1338 {
1339         /* Disable interrupts */
1340         efx_nic_interrupts(efx, false, false);
1341 }
1342
1343 /* Generate a test interrupt
1344  * Interrupt must already have been enabled, otherwise nasty things
1345  * may happen.
1346  */
1347 void efx_nic_generate_interrupt(struct efx_nic *efx)
1348 {
1349         efx_nic_interrupts(efx, true, true);
1350 }
1351
1352 /* Process a fatal interrupt
1353  * Disable bus mastering ASAP and schedule a reset
1354  */
1355 irqreturn_t efx_nic_fatal_interrupt(struct efx_nic *efx)
1356 {
1357         struct falcon_nic_data *nic_data = efx->nic_data;
1358         efx_oword_t *int_ker = efx->irq_status.addr;
1359         efx_oword_t fatal_intr;
1360         int error, mem_perr;
1361
1362         efx_reado(efx, &fatal_intr, FR_AZ_FATAL_INTR_KER);
1363         error = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_FATAL_INTR);
1364
1365         netif_err(efx, hw, efx->net_dev, "SYSTEM ERROR "EFX_OWORD_FMT" status "
1366                   EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1367                   EFX_OWORD_VAL(fatal_intr),
1368                   error ? "disabling bus mastering" : "no recognised error");
1369
1370         /* If this is a memory parity error dump which blocks are offending */
1371         mem_perr = (EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER) ||
1372                     EFX_OWORD_FIELD(fatal_intr, FRF_AZ_SRM_PERR_INT_KER));
1373         if (mem_perr) {
1374                 efx_oword_t reg;
1375                 efx_reado(efx, &reg, FR_AZ_MEM_STAT);
1376                 netif_err(efx, hw, efx->net_dev,
1377                           "SYSTEM ERROR: memory parity error "EFX_OWORD_FMT"\n",
1378                           EFX_OWORD_VAL(reg));
1379         }
1380
1381         /* Disable both devices */
1382         pci_clear_master(efx->pci_dev);
1383         if (efx_nic_is_dual_func(efx))
1384                 pci_clear_master(nic_data->pci_dev2);
1385         efx_nic_disable_interrupts(efx);
1386
1387         /* Count errors and reset or disable the NIC accordingly */
1388         if (efx->int_error_count == 0 ||
1389             time_after(jiffies, efx->int_error_expire)) {
1390                 efx->int_error_count = 0;
1391                 efx->int_error_expire =
1392                         jiffies + EFX_INT_ERROR_EXPIRE * HZ;
1393         }
1394         if (++efx->int_error_count < EFX_MAX_INT_ERRORS) {
1395                 netif_err(efx, hw, efx->net_dev,
1396                           "SYSTEM ERROR - reset scheduled\n");
1397                 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1398         } else {
1399                 netif_err(efx, hw, efx->net_dev,
1400                           "SYSTEM ERROR - max number of errors seen."
1401                           "NIC will be disabled\n");
1402                 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1403         }
1404
1405         return IRQ_HANDLED;
1406 }
1407
1408 /* Handle a legacy interrupt
1409  * Acknowledges the interrupt and schedule event queue processing.
1410  */
1411 static irqreturn_t efx_legacy_interrupt(int irq, void *dev_id)
1412 {
1413         struct efx_nic *efx = dev_id;
1414         efx_oword_t *int_ker = efx->irq_status.addr;
1415         irqreturn_t result = IRQ_NONE;
1416         struct efx_channel *channel;
1417         efx_dword_t reg;
1418         u32 queues;
1419         int syserr;
1420
1421         /* Could this be ours?  If interrupts are disabled then the
1422          * channel state may not be valid.
1423          */
1424         if (!efx->legacy_irq_enabled)
1425                 return result;
1426
1427         /* Read the ISR which also ACKs the interrupts */
1428         efx_readd(efx, &reg, FR_BZ_INT_ISR0);
1429         queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1430
1431         /* Check to see if we have a serious error condition */
1432         if (queues & (1U << efx->fatal_irq_level)) {
1433                 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1434                 if (unlikely(syserr))
1435                         return efx_nic_fatal_interrupt(efx);
1436         }
1437
1438         if (queues != 0) {
1439                 if (EFX_WORKAROUND_15783(efx))
1440                         efx->irq_zero_count = 0;
1441
1442                 /* Schedule processing of any interrupting queues */
1443                 efx_for_each_channel(channel, efx) {
1444                         if (queues & 1)
1445                                 efx_schedule_channel(channel);
1446                         queues >>= 1;
1447                 }
1448                 result = IRQ_HANDLED;
1449
1450         } else if (EFX_WORKAROUND_15783(efx)) {
1451                 efx_qword_t *event;
1452
1453                 /* We can't return IRQ_HANDLED more than once on seeing ISR=0
1454                  * because this might be a shared interrupt. */
1455                 if (efx->irq_zero_count++ == 0)
1456                         result = IRQ_HANDLED;
1457
1458                 /* Ensure we schedule or rearm all event queues */
1459                 efx_for_each_channel(channel, efx) {
1460                         event = efx_event(channel, channel->eventq_read_ptr);
1461                         if (efx_event_present(event))
1462                                 efx_schedule_channel(channel);
1463                         else
1464                                 efx_nic_eventq_read_ack(channel);
1465                 }
1466         }
1467
1468         if (result == IRQ_HANDLED) {
1469                 efx->last_irq_cpu = raw_smp_processor_id();
1470                 netif_vdbg(efx, intr, efx->net_dev,
1471                            "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1472                            irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1473         }
1474
1475         return result;
1476 }
1477
1478 /* Handle an MSI interrupt
1479  *
1480  * Handle an MSI hardware interrupt.  This routine schedules event
1481  * queue processing.  No interrupt acknowledgement cycle is necessary.
1482  * Also, we never need to check that the interrupt is for us, since
1483  * MSI interrupts cannot be shared.
1484  */
1485 static irqreturn_t efx_msi_interrupt(int irq, void *dev_id)
1486 {
1487         struct efx_channel *channel = *(struct efx_channel **)dev_id;
1488         struct efx_nic *efx = channel->efx;
1489         efx_oword_t *int_ker = efx->irq_status.addr;
1490         int syserr;
1491
1492         efx->last_irq_cpu = raw_smp_processor_id();
1493         netif_vdbg(efx, intr, efx->net_dev,
1494                    "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1495                    irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1496
1497         /* Check to see if we have a serious error condition */
1498         if (channel->channel == efx->fatal_irq_level) {
1499                 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1500                 if (unlikely(syserr))
1501                         return efx_nic_fatal_interrupt(efx);
1502         }
1503
1504         /* Schedule processing of the channel */
1505         efx_schedule_channel(channel);
1506
1507         return IRQ_HANDLED;
1508 }
1509
1510
1511 /* Setup RSS indirection table.
1512  * This maps from the hash value of the packet to RXQ
1513  */
1514 void efx_nic_push_rx_indir_table(struct efx_nic *efx)
1515 {
1516         size_t i = 0;
1517         efx_dword_t dword;
1518
1519         if (efx_nic_rev(efx) < EFX_REV_FALCON_B0)
1520                 return;
1521
1522         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
1523                      FR_BZ_RX_INDIRECTION_TBL_ROWS);
1524
1525         for (i = 0; i < FR_BZ_RX_INDIRECTION_TBL_ROWS; i++) {
1526                 EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE,
1527                                      efx->rx_indir_table[i]);
1528                 efx_writed_table(efx, &dword, FR_BZ_RX_INDIRECTION_TBL, i);
1529         }
1530 }
1531
1532 /* Hook interrupt handler(s)
1533  * Try MSI and then legacy interrupts.
1534  */
1535 int efx_nic_init_interrupt(struct efx_nic *efx)
1536 {
1537         struct efx_channel *channel;
1538         int rc;
1539
1540         if (!EFX_INT_MODE_USE_MSI(efx)) {
1541                 irq_handler_t handler;
1542                 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1543                         handler = efx_legacy_interrupt;
1544                 else
1545                         handler = falcon_legacy_interrupt_a1;
1546
1547                 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
1548                                  efx->name, efx);
1549                 if (rc) {
1550                         netif_err(efx, drv, efx->net_dev,
1551                                   "failed to hook legacy IRQ %d\n",
1552                                   efx->pci_dev->irq);
1553                         goto fail1;
1554                 }
1555                 return 0;
1556         }
1557
1558         /* Hook MSI or MSI-X interrupt */
1559         efx_for_each_channel(channel, efx) {
1560                 rc = request_irq(channel->irq, efx_msi_interrupt,
1561                                  IRQF_PROBE_SHARED, /* Not shared */
1562                                  efx->channel_name[channel->channel],
1563                                  &efx->channel[channel->channel]);
1564                 if (rc) {
1565                         netif_err(efx, drv, efx->net_dev,
1566                                   "failed to hook IRQ %d\n", channel->irq);
1567                         goto fail2;
1568                 }
1569         }
1570
1571         return 0;
1572
1573  fail2:
1574         efx_for_each_channel(channel, efx)
1575                 free_irq(channel->irq, &efx->channel[channel->channel]);
1576  fail1:
1577         return rc;
1578 }
1579
1580 void efx_nic_fini_interrupt(struct efx_nic *efx)
1581 {
1582         struct efx_channel *channel;
1583         efx_oword_t reg;
1584
1585         /* Disable MSI/MSI-X interrupts */
1586         efx_for_each_channel(channel, efx) {
1587                 if (channel->irq)
1588                         free_irq(channel->irq, &efx->channel[channel->channel]);
1589         }
1590
1591         /* ACK legacy interrupt */
1592         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1593                 efx_reado(efx, &reg, FR_BZ_INT_ISR0);
1594         else
1595                 falcon_irq_ack_a1(efx);
1596
1597         /* Disable legacy interrupt */
1598         if (efx->legacy_irq)
1599                 free_irq(efx->legacy_irq, efx);
1600 }
1601
1602 u32 efx_nic_fpga_ver(struct efx_nic *efx)
1603 {
1604         efx_oword_t altera_build;
1605         efx_reado(efx, &altera_build, FR_AZ_ALTERA_BUILD);
1606         return EFX_OWORD_FIELD(altera_build, FRF_AZ_ALTERA_BUILD_VER);
1607 }
1608
1609 void efx_nic_init_common(struct efx_nic *efx)
1610 {
1611         efx_oword_t temp;
1612
1613         /* Set positions of descriptor caches in SRAM. */
1614         EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR,
1615                              efx->type->tx_dc_base / 8);
1616         efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG);
1617         EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR,
1618                              efx->type->rx_dc_base / 8);
1619         efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG);
1620
1621         /* Set TX descriptor cache size. */
1622         BUILD_BUG_ON(TX_DC_ENTRIES != (8 << TX_DC_ENTRIES_ORDER));
1623         EFX_POPULATE_OWORD_1(temp, FRF_AZ_TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
1624         efx_writeo(efx, &temp, FR_AZ_TX_DC_CFG);
1625
1626         /* Set RX descriptor cache size.  Set low watermark to size-8, as
1627          * this allows most efficient prefetching.
1628          */
1629         BUILD_BUG_ON(RX_DC_ENTRIES != (8 << RX_DC_ENTRIES_ORDER));
1630         EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
1631         efx_writeo(efx, &temp, FR_AZ_RX_DC_CFG);
1632         EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
1633         efx_writeo(efx, &temp, FR_AZ_RX_DC_PF_WM);
1634
1635         /* Program INT_KER address */
1636         EFX_POPULATE_OWORD_2(temp,
1637                              FRF_AZ_NORM_INT_VEC_DIS_KER,
1638                              EFX_INT_MODE_USE_MSI(efx),
1639                              FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr);
1640         efx_writeo(efx, &temp, FR_AZ_INT_ADR_KER);
1641
1642         if (EFX_WORKAROUND_17213(efx) && !EFX_INT_MODE_USE_MSI(efx))
1643                 /* Use an interrupt level unused by event queues */
1644                 efx->fatal_irq_level = 0x1f;
1645         else
1646                 /* Use a valid MSI-X vector */
1647                 efx->fatal_irq_level = 0;
1648
1649         /* Enable all the genuinely fatal interrupts.  (They are still
1650          * masked by the overall interrupt mask, controlled by
1651          * falcon_interrupts()).
1652          *
1653          * Note: All other fatal interrupts are enabled
1654          */
1655         EFX_POPULATE_OWORD_3(temp,
1656                              FRF_AZ_ILL_ADR_INT_KER_EN, 1,
1657                              FRF_AZ_RBUF_OWN_INT_KER_EN, 1,
1658                              FRF_AZ_TBUF_OWN_INT_KER_EN, 1);
1659         if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0)
1660                 EFX_SET_OWORD_FIELD(temp, FRF_CZ_SRAM_PERR_INT_P_KER_EN, 1);
1661         EFX_INVERT_OWORD(temp);
1662         efx_writeo(efx, &temp, FR_AZ_FATAL_INTR_KER);
1663
1664         efx_nic_push_rx_indir_table(efx);
1665
1666         /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
1667          * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
1668          */
1669         efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
1670         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe);
1671         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1);
1672         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1);
1673         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 1);
1674         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_DIS_NON_IP_EV, 1);
1675         /* Enable SW_EV to inherit in char driver - assume harmless here */
1676         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_SOFT_EVT_EN, 1);
1677         /* Prefetch threshold 2 => fetch when descriptor cache half empty */
1678         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_THRESHOLD, 2);
1679         /* Disable hardware watchdog which can misfire */
1680         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_WD_TMR, 0x3fffff);
1681         /* Squash TX of packets of 16 bytes or less */
1682         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1683                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
1684         efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
1685
1686         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
1687                 EFX_POPULATE_OWORD_4(temp,
1688                                      /* Default values */
1689                                      FRF_BZ_TX_PACE_SB_NOT_AF, 0x15,
1690                                      FRF_BZ_TX_PACE_SB_AF, 0xb,
1691                                      FRF_BZ_TX_PACE_FB_BASE, 0,
1692                                      /* Allow large pace values in the
1693                                       * fast bin. */
1694                                      FRF_BZ_TX_PACE_BIN_TH,
1695                                      FFE_BZ_TX_PACE_RESERVED);
1696                 efx_writeo(efx, &temp, FR_BZ_TX_PACE);
1697         }
1698 }
1699
1700 /* Register dump */
1701
1702 #define REGISTER_REVISION_A     1
1703 #define REGISTER_REVISION_B     2
1704 #define REGISTER_REVISION_C     3
1705 #define REGISTER_REVISION_Z     3       /* latest revision */
1706
1707 struct efx_nic_reg {
1708         u32 offset:24;
1709         u32 min_revision:2, max_revision:2;
1710 };
1711
1712 #define REGISTER(name, min_rev, max_rev) {                              \
1713         FR_ ## min_rev ## max_rev ## _ ## name,                         \
1714         REGISTER_REVISION_ ## min_rev, REGISTER_REVISION_ ## max_rev    \
1715 }
1716 #define REGISTER_AA(name) REGISTER(name, A, A)
1717 #define REGISTER_AB(name) REGISTER(name, A, B)
1718 #define REGISTER_AZ(name) REGISTER(name, A, Z)
1719 #define REGISTER_BB(name) REGISTER(name, B, B)
1720 #define REGISTER_BZ(name) REGISTER(name, B, Z)
1721 #define REGISTER_CZ(name) REGISTER(name, C, Z)
1722
1723 static const struct efx_nic_reg efx_nic_regs[] = {
1724         REGISTER_AZ(ADR_REGION),
1725         REGISTER_AZ(INT_EN_KER),
1726         REGISTER_BZ(INT_EN_CHAR),
1727         REGISTER_AZ(INT_ADR_KER),
1728         REGISTER_BZ(INT_ADR_CHAR),
1729         /* INT_ACK_KER is WO */
1730         /* INT_ISR0 is RC */
1731         REGISTER_AZ(HW_INIT),
1732         REGISTER_CZ(USR_EV_CFG),
1733         REGISTER_AB(EE_SPI_HCMD),
1734         REGISTER_AB(EE_SPI_HADR),
1735         REGISTER_AB(EE_SPI_HDATA),
1736         REGISTER_AB(EE_BASE_PAGE),
1737         REGISTER_AB(EE_VPD_CFG0),
1738         /* EE_VPD_SW_CNTL and EE_VPD_SW_DATA are not used */
1739         /* PMBX_DBG_IADDR and PBMX_DBG_IDATA are indirect */
1740         /* PCIE_CORE_INDIRECT is indirect */
1741         REGISTER_AB(NIC_STAT),
1742         REGISTER_AB(GPIO_CTL),
1743         REGISTER_AB(GLB_CTL),
1744         /* FATAL_INTR_KER and FATAL_INTR_CHAR are partly RC */
1745         REGISTER_BZ(DP_CTRL),
1746         REGISTER_AZ(MEM_STAT),
1747         REGISTER_AZ(CS_DEBUG),
1748         REGISTER_AZ(ALTERA_BUILD),
1749         REGISTER_AZ(CSR_SPARE),
1750         REGISTER_AB(PCIE_SD_CTL0123),
1751         REGISTER_AB(PCIE_SD_CTL45),
1752         REGISTER_AB(PCIE_PCS_CTL_STAT),
1753         /* DEBUG_DATA_OUT is not used */
1754         /* DRV_EV is WO */
1755         REGISTER_AZ(EVQ_CTL),
1756         REGISTER_AZ(EVQ_CNT1),
1757         REGISTER_AZ(EVQ_CNT2),
1758         REGISTER_AZ(BUF_TBL_CFG),
1759         REGISTER_AZ(SRM_RX_DC_CFG),
1760         REGISTER_AZ(SRM_TX_DC_CFG),
1761         REGISTER_AZ(SRM_CFG),
1762         /* BUF_TBL_UPD is WO */
1763         REGISTER_AZ(SRM_UPD_EVQ),
1764         REGISTER_AZ(SRAM_PARITY),
1765         REGISTER_AZ(RX_CFG),
1766         REGISTER_BZ(RX_FILTER_CTL),
1767         /* RX_FLUSH_DESCQ is WO */
1768         REGISTER_AZ(RX_DC_CFG),
1769         REGISTER_AZ(RX_DC_PF_WM),
1770         REGISTER_BZ(RX_RSS_TKEY),
1771         /* RX_NODESC_DROP is RC */
1772         REGISTER_AA(RX_SELF_RST),
1773         /* RX_DEBUG, RX_PUSH_DROP are not used */
1774         REGISTER_CZ(RX_RSS_IPV6_REG1),
1775         REGISTER_CZ(RX_RSS_IPV6_REG2),
1776         REGISTER_CZ(RX_RSS_IPV6_REG3),
1777         /* TX_FLUSH_DESCQ is WO */
1778         REGISTER_AZ(TX_DC_CFG),
1779         REGISTER_AA(TX_CHKSM_CFG),
1780         REGISTER_AZ(TX_CFG),
1781         /* TX_PUSH_DROP is not used */
1782         REGISTER_AZ(TX_RESERVED),
1783         REGISTER_BZ(TX_PACE),
1784         /* TX_PACE_DROP_QID is RC */
1785         REGISTER_BB(TX_VLAN),
1786         REGISTER_BZ(TX_IPFIL_PORTEN),
1787         REGISTER_AB(MD_TXD),
1788         REGISTER_AB(MD_RXD),
1789         REGISTER_AB(MD_CS),
1790         REGISTER_AB(MD_PHY_ADR),
1791         REGISTER_AB(MD_ID),
1792         /* MD_STAT is RC */
1793         REGISTER_AB(MAC_STAT_DMA),
1794         REGISTER_AB(MAC_CTRL),
1795         REGISTER_BB(GEN_MODE),
1796         REGISTER_AB(MAC_MC_HASH_REG0),
1797         REGISTER_AB(MAC_MC_HASH_REG1),
1798         REGISTER_AB(GM_CFG1),
1799         REGISTER_AB(GM_CFG2),
1800         /* GM_IPG and GM_HD are not used */
1801         REGISTER_AB(GM_MAX_FLEN),
1802         /* GM_TEST is not used */
1803         REGISTER_AB(GM_ADR1),
1804         REGISTER_AB(GM_ADR2),
1805         REGISTER_AB(GMF_CFG0),
1806         REGISTER_AB(GMF_CFG1),
1807         REGISTER_AB(GMF_CFG2),
1808         REGISTER_AB(GMF_CFG3),
1809         REGISTER_AB(GMF_CFG4),
1810         REGISTER_AB(GMF_CFG5),
1811         REGISTER_BB(TX_SRC_MAC_CTL),
1812         REGISTER_AB(XM_ADR_LO),
1813         REGISTER_AB(XM_ADR_HI),
1814         REGISTER_AB(XM_GLB_CFG),
1815         REGISTER_AB(XM_TX_CFG),
1816         REGISTER_AB(XM_RX_CFG),
1817         REGISTER_AB(XM_MGT_INT_MASK),
1818         REGISTER_AB(XM_FC),
1819         REGISTER_AB(XM_PAUSE_TIME),
1820         REGISTER_AB(XM_TX_PARAM),
1821         REGISTER_AB(XM_RX_PARAM),
1822         /* XM_MGT_INT_MSK (note no 'A') is RC */
1823         REGISTER_AB(XX_PWR_RST),
1824         REGISTER_AB(XX_SD_CTL),
1825         REGISTER_AB(XX_TXDRV_CTL),
1826         /* XX_PRBS_CTL, XX_PRBS_CHK and XX_PRBS_ERR are not used */
1827         /* XX_CORE_STAT is partly RC */
1828 };
1829
1830 struct efx_nic_reg_table {
1831         u32 offset:24;
1832         u32 min_revision:2, max_revision:2;
1833         u32 step:6, rows:21;
1834 };
1835
1836 #define REGISTER_TABLE_DIMENSIONS(_, offset, min_rev, max_rev, step, rows) { \
1837         offset,                                                         \
1838         REGISTER_REVISION_ ## min_rev, REGISTER_REVISION_ ## max_rev,   \
1839         step, rows                                                      \
1840 }
1841 #define REGISTER_TABLE(name, min_rev, max_rev)                          \
1842         REGISTER_TABLE_DIMENSIONS(                                      \
1843                 name, FR_ ## min_rev ## max_rev ## _ ## name,           \
1844                 min_rev, max_rev,                                       \
1845                 FR_ ## min_rev ## max_rev ## _ ## name ## _STEP,        \
1846                 FR_ ## min_rev ## max_rev ## _ ## name ## _ROWS)
1847 #define REGISTER_TABLE_AA(name) REGISTER_TABLE(name, A, A)
1848 #define REGISTER_TABLE_AZ(name) REGISTER_TABLE(name, A, Z)
1849 #define REGISTER_TABLE_BB(name) REGISTER_TABLE(name, B, B)
1850 #define REGISTER_TABLE_BZ(name) REGISTER_TABLE(name, B, Z)
1851 #define REGISTER_TABLE_BB_CZ(name)                                      \
1852         REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, B, B,           \
1853                                   FR_BZ_ ## name ## _STEP,              \
1854                                   FR_BB_ ## name ## _ROWS),             \
1855         REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, C, Z,           \
1856                                   FR_BZ_ ## name ## _STEP,              \
1857                                   FR_CZ_ ## name ## _ROWS)
1858 #define REGISTER_TABLE_CZ(name) REGISTER_TABLE(name, C, Z)
1859
1860 static const struct efx_nic_reg_table efx_nic_reg_tables[] = {
1861         /* DRIVER is not used */
1862         /* EVQ_RPTR, TIMER_COMMAND, USR_EV and {RX,TX}_DESC_UPD are WO */
1863         REGISTER_TABLE_BB(TX_IPFIL_TBL),
1864         REGISTER_TABLE_BB(TX_SRC_MAC_TBL),
1865         REGISTER_TABLE_AA(RX_DESC_PTR_TBL_KER),
1866         REGISTER_TABLE_BB_CZ(RX_DESC_PTR_TBL),
1867         REGISTER_TABLE_AA(TX_DESC_PTR_TBL_KER),
1868         REGISTER_TABLE_BB_CZ(TX_DESC_PTR_TBL),
1869         REGISTER_TABLE_AA(EVQ_PTR_TBL_KER),
1870         REGISTER_TABLE_BB_CZ(EVQ_PTR_TBL),
1871         /* We can't reasonably read all of the buffer table (up to 8MB!).
1872          * However this driver will only use a few entries.  Reading
1873          * 1K entries allows for some expansion of queue count and
1874          * size before we need to change the version. */
1875         REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL_KER, FR_AA_BUF_FULL_TBL_KER,
1876                                   A, A, 8, 1024),
1877         REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL, FR_BZ_BUF_FULL_TBL,
1878                                   B, Z, 8, 1024),
1879         REGISTER_TABLE_CZ(RX_MAC_FILTER_TBL0),
1880         REGISTER_TABLE_BB_CZ(TIMER_TBL),
1881         REGISTER_TABLE_BB_CZ(TX_PACE_TBL),
1882         REGISTER_TABLE_BZ(RX_INDIRECTION_TBL),
1883         /* TX_FILTER_TBL0 is huge and not used by this driver */
1884         REGISTER_TABLE_CZ(TX_MAC_FILTER_TBL0),
1885         REGISTER_TABLE_CZ(MC_TREG_SMEM),
1886         /* MSIX_PBA_TABLE is not mapped */
1887         /* SRM_DBG is not mapped (and is redundant with BUF_FLL_TBL) */
1888         REGISTER_TABLE_BZ(RX_FILTER_TBL0),
1889 };
1890
1891 size_t efx_nic_get_regs_len(struct efx_nic *efx)
1892 {
1893         const struct efx_nic_reg *reg;
1894         const struct efx_nic_reg_table *table;
1895         size_t len = 0;
1896
1897         for (reg = efx_nic_regs;
1898              reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs);
1899              reg++)
1900                 if (efx->type->revision >= reg->min_revision &&
1901                     efx->type->revision <= reg->max_revision)
1902                         len += sizeof(efx_oword_t);
1903
1904         for (table = efx_nic_reg_tables;
1905              table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables);
1906              table++)
1907                 if (efx->type->revision >= table->min_revision &&
1908                     efx->type->revision <= table->max_revision)
1909                         len += table->rows * min_t(size_t, table->step, 16);
1910
1911         return len;
1912 }
1913
1914 void efx_nic_get_regs(struct efx_nic *efx, void *buf)
1915 {
1916         const struct efx_nic_reg *reg;
1917         const struct efx_nic_reg_table *table;
1918
1919         for (reg = efx_nic_regs;
1920              reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs);
1921              reg++) {
1922                 if (efx->type->revision >= reg->min_revision &&
1923                     efx->type->revision <= reg->max_revision) {
1924                         efx_reado(efx, (efx_oword_t *)buf, reg->offset);
1925                         buf += sizeof(efx_oword_t);
1926                 }
1927         }
1928
1929         for (table = efx_nic_reg_tables;
1930              table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables);
1931              table++) {
1932                 size_t size, i;
1933
1934                 if (!(efx->type->revision >= table->min_revision &&
1935                       efx->type->revision <= table->max_revision))
1936                         continue;
1937
1938                 size = min_t(size_t, table->step, 16);
1939
1940                 if (table->offset >= efx->type->mem_map_size) {
1941                         /* No longer mapped; return dummy data */
1942                         memcpy(buf, "\xde\xc0\xad\xde", 4);
1943                         buf += table->rows * size;
1944                         continue;
1945                 }
1946
1947                 for (i = 0; i < table->rows; i++) {
1948                         switch (table->step) {
1949                         case 4: /* 32-bit register or SRAM */
1950                                 efx_readd_table(efx, buf, table->offset, i);
1951                                 break;
1952                         case 8: /* 64-bit SRAM */
1953                                 efx_sram_readq(efx,
1954                                                efx->membase + table->offset,
1955                                                buf, i);
1956                                 break;
1957                         case 16: /* 128-bit register */
1958                                 efx_reado_table(efx, buf, table->offset, i);
1959                                 break;
1960                         case 32: /* 128-bit register, interleaved */
1961                                 efx_reado_table(efx, buf, table->offset, 2 * i);
1962                                 break;
1963                         default:
1964                                 WARN_ON(1);
1965                                 return;
1966                         }
1967                         buf += size;
1968                 }
1969         }
1970 }