a4c7830ec9b085fc91e214d34fb171377e43fce8
[linux-2.6.git] / drivers / net / sfc / falcon.c
1 /****************************************************************************
2  * Driver for Solarflare Solarstorm network controllers and boards
3  * Copyright 2005-2006 Fen Systems Ltd.
4  * Copyright 2006-2010 Solarflare Communications Inc.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms of the GNU General Public License version 2 as published
8  * by the Free Software Foundation, incorporated herein by reference.
9  */
10
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/seq_file.h>
16 #include <linux/i2c.h>
17 #include <linux/mii.h>
18 #include <linux/slab.h>
19 #include "net_driver.h"
20 #include "bitfield.h"
21 #include "efx.h"
22 #include "mac.h"
23 #include "spi.h"
24 #include "nic.h"
25 #include "regs.h"
26 #include "io.h"
27 #include "phy.h"
28 #include "workarounds.h"
29
30 /* Hardware control for SFC4000 (aka Falcon). */
31
32 static const unsigned int
33 /* "Large" EEPROM device: Atmel AT25640 or similar
34  * 8 KB, 16-bit address, 32 B write block */
35 large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN)
36                      | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
37                      | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)),
38 /* Default flash device: Atmel AT25F1024
39  * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */
40 default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN)
41                       | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
42                       | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
43                       | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
44                       | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN));
45
46 /**************************************************************************
47  *
48  * I2C bus - this is a bit-bashing interface using GPIO pins
49  * Note that it uses the output enables to tristate the outputs
50  * SDA is the data pin and SCL is the clock
51  *
52  **************************************************************************
53  */
54 static void falcon_setsda(void *data, int state)
55 {
56         struct efx_nic *efx = (struct efx_nic *)data;
57         efx_oword_t reg;
58
59         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
60         EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state);
61         efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
62 }
63
64 static void falcon_setscl(void *data, int state)
65 {
66         struct efx_nic *efx = (struct efx_nic *)data;
67         efx_oword_t reg;
68
69         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
70         EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state);
71         efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
72 }
73
74 static int falcon_getsda(void *data)
75 {
76         struct efx_nic *efx = (struct efx_nic *)data;
77         efx_oword_t reg;
78
79         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
80         return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN);
81 }
82
83 static int falcon_getscl(void *data)
84 {
85         struct efx_nic *efx = (struct efx_nic *)data;
86         efx_oword_t reg;
87
88         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
89         return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN);
90 }
91
92 static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
93         .setsda         = falcon_setsda,
94         .setscl         = falcon_setscl,
95         .getsda         = falcon_getsda,
96         .getscl         = falcon_getscl,
97         .udelay         = 5,
98         /* Wait up to 50 ms for slave to let us pull SCL high */
99         .timeout        = DIV_ROUND_UP(HZ, 20),
100 };
101
102 static void falcon_push_irq_moderation(struct efx_channel *channel)
103 {
104         efx_dword_t timer_cmd;
105         struct efx_nic *efx = channel->efx;
106
107         /* Set timer register */
108         if (channel->irq_moderation) {
109                 EFX_POPULATE_DWORD_2(timer_cmd,
110                                      FRF_AB_TC_TIMER_MODE,
111                                      FFE_BB_TIMER_MODE_INT_HLDOFF,
112                                      FRF_AB_TC_TIMER_VAL,
113                                      channel->irq_moderation - 1);
114         } else {
115                 EFX_POPULATE_DWORD_2(timer_cmd,
116                                      FRF_AB_TC_TIMER_MODE,
117                                      FFE_BB_TIMER_MODE_DIS,
118                                      FRF_AB_TC_TIMER_VAL, 0);
119         }
120         BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0);
121         efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
122                                channel->channel);
123 }
124
125 static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx);
126
127 static void falcon_prepare_flush(struct efx_nic *efx)
128 {
129         falcon_deconfigure_mac_wrapper(efx);
130
131         /* Wait for the tx and rx fifo's to get to the next packet boundary
132          * (~1ms without back-pressure), then to drain the remainder of the
133          * fifo's at data path speeds (negligible), with a healthy margin. */
134         msleep(10);
135 }
136
137 /* Acknowledge a legacy interrupt from Falcon
138  *
139  * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
140  *
141  * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
142  * BIU. Interrupt acknowledge is read sensitive so must write instead
143  * (then read to ensure the BIU collector is flushed)
144  *
145  * NB most hardware supports MSI interrupts
146  */
147 inline void falcon_irq_ack_a1(struct efx_nic *efx)
148 {
149         efx_dword_t reg;
150
151         EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e);
152         efx_writed(efx, &reg, FR_AA_INT_ACK_KER);
153         efx_readd(efx, &reg, FR_AA_WORK_AROUND_BROKEN_PCI_READS);
154 }
155
156
157 irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
158 {
159         struct efx_nic *efx = dev_id;
160         efx_oword_t *int_ker = efx->irq_status.addr;
161         int syserr;
162         int queues;
163
164         /* Check to see if this is our interrupt.  If it isn't, we
165          * exit without having touched the hardware.
166          */
167         if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
168                 netif_vdbg(efx, intr, efx->net_dev,
169                            "IRQ %d on CPU %d not for me\n", irq,
170                            raw_smp_processor_id());
171                 return IRQ_NONE;
172         }
173         efx->last_irq_cpu = raw_smp_processor_id();
174         netif_vdbg(efx, intr, efx->net_dev,
175                    "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
176                    irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
177
178         /* Determine interrupting queues, clear interrupt status
179          * register and acknowledge the device interrupt.
180          */
181         BUILD_BUG_ON(FSF_AZ_NET_IVEC_INT_Q_WIDTH > EFX_MAX_CHANNELS);
182         queues = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_INT_Q);
183
184         /* Check to see if we have a serious error condition */
185         if (queues & (1U << efx->fatal_irq_level)) {
186                 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
187                 if (unlikely(syserr))
188                         return efx_nic_fatal_interrupt(efx);
189         }
190
191         EFX_ZERO_OWORD(*int_ker);
192         wmb(); /* Ensure the vector is cleared before interrupt ack */
193         falcon_irq_ack_a1(efx);
194
195         if (queues & 1)
196                 efx_schedule_channel(efx_get_channel(efx, 0));
197         if (queues & 2)
198                 efx_schedule_channel(efx_get_channel(efx, 1));
199         return IRQ_HANDLED;
200 }
201 /**************************************************************************
202  *
203  * EEPROM/flash
204  *
205  **************************************************************************
206  */
207
208 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
209
210 static int falcon_spi_poll(struct efx_nic *efx)
211 {
212         efx_oword_t reg;
213         efx_reado(efx, &reg, FR_AB_EE_SPI_HCMD);
214         return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0;
215 }
216
217 /* Wait for SPI command completion */
218 static int falcon_spi_wait(struct efx_nic *efx)
219 {
220         /* Most commands will finish quickly, so we start polling at
221          * very short intervals.  Sometimes the command may have to
222          * wait for VPD or expansion ROM access outside of our
223          * control, so we allow up to 100 ms. */
224         unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10);
225         int i;
226
227         for (i = 0; i < 10; i++) {
228                 if (!falcon_spi_poll(efx))
229                         return 0;
230                 udelay(10);
231         }
232
233         for (;;) {
234                 if (!falcon_spi_poll(efx))
235                         return 0;
236                 if (time_after_eq(jiffies, timeout)) {
237                         netif_err(efx, hw, efx->net_dev,
238                                   "timed out waiting for SPI\n");
239                         return -ETIMEDOUT;
240                 }
241                 schedule_timeout_uninterruptible(1);
242         }
243 }
244
245 int falcon_spi_cmd(struct efx_nic *efx, const struct efx_spi_device *spi,
246                    unsigned int command, int address,
247                    const void *in, void *out, size_t len)
248 {
249         bool addressed = (address >= 0);
250         bool reading = (out != NULL);
251         efx_oword_t reg;
252         int rc;
253
254         /* Input validation */
255         if (len > FALCON_SPI_MAX_LEN)
256                 return -EINVAL;
257
258         /* Check that previous command is not still running */
259         rc = falcon_spi_poll(efx);
260         if (rc)
261                 return rc;
262
263         /* Program address register, if we have an address */
264         if (addressed) {
265                 EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address);
266                 efx_writeo(efx, &reg, FR_AB_EE_SPI_HADR);
267         }
268
269         /* Program data register, if we have data */
270         if (in != NULL) {
271                 memcpy(&reg, in, len);
272                 efx_writeo(efx, &reg, FR_AB_EE_SPI_HDATA);
273         }
274
275         /* Issue read/write command */
276         EFX_POPULATE_OWORD_7(reg,
277                              FRF_AB_EE_SPI_HCMD_CMD_EN, 1,
278                              FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id,
279                              FRF_AB_EE_SPI_HCMD_DABCNT, len,
280                              FRF_AB_EE_SPI_HCMD_READ, reading,
281                              FRF_AB_EE_SPI_HCMD_DUBCNT, 0,
282                              FRF_AB_EE_SPI_HCMD_ADBCNT,
283                              (addressed ? spi->addr_len : 0),
284                              FRF_AB_EE_SPI_HCMD_ENC, command);
285         efx_writeo(efx, &reg, FR_AB_EE_SPI_HCMD);
286
287         /* Wait for read/write to complete */
288         rc = falcon_spi_wait(efx);
289         if (rc)
290                 return rc;
291
292         /* Read data */
293         if (out != NULL) {
294                 efx_reado(efx, &reg, FR_AB_EE_SPI_HDATA);
295                 memcpy(out, &reg, len);
296         }
297
298         return 0;
299 }
300
301 static size_t
302 falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start)
303 {
304         return min(FALCON_SPI_MAX_LEN,
305                    (spi->block_size - (start & (spi->block_size - 1))));
306 }
307
308 static inline u8
309 efx_spi_munge_command(const struct efx_spi_device *spi,
310                       const u8 command, const unsigned int address)
311 {
312         return command | (((address >> 8) & spi->munge_address) << 3);
313 }
314
315 /* Wait up to 10 ms for buffered write completion */
316 int
317 falcon_spi_wait_write(struct efx_nic *efx, const struct efx_spi_device *spi)
318 {
319         unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100);
320         u8 status;
321         int rc;
322
323         for (;;) {
324                 rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
325                                     &status, sizeof(status));
326                 if (rc)
327                         return rc;
328                 if (!(status & SPI_STATUS_NRDY))
329                         return 0;
330                 if (time_after_eq(jiffies, timeout)) {
331                         netif_err(efx, hw, efx->net_dev,
332                                   "SPI write timeout on device %d"
333                                   " last status=0x%02x\n",
334                                   spi->device_id, status);
335                         return -ETIMEDOUT;
336                 }
337                 schedule_timeout_uninterruptible(1);
338         }
339 }
340
341 int falcon_spi_read(struct efx_nic *efx, const struct efx_spi_device *spi,
342                     loff_t start, size_t len, size_t *retlen, u8 *buffer)
343 {
344         size_t block_len, pos = 0;
345         unsigned int command;
346         int rc = 0;
347
348         while (pos < len) {
349                 block_len = min(len - pos, FALCON_SPI_MAX_LEN);
350
351                 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
352                 rc = falcon_spi_cmd(efx, spi, command, start + pos, NULL,
353                                     buffer + pos, block_len);
354                 if (rc)
355                         break;
356                 pos += block_len;
357
358                 /* Avoid locking up the system */
359                 cond_resched();
360                 if (signal_pending(current)) {
361                         rc = -EINTR;
362                         break;
363                 }
364         }
365
366         if (retlen)
367                 *retlen = pos;
368         return rc;
369 }
370
371 int
372 falcon_spi_write(struct efx_nic *efx, const struct efx_spi_device *spi,
373                  loff_t start, size_t len, size_t *retlen, const u8 *buffer)
374 {
375         u8 verify_buffer[FALCON_SPI_MAX_LEN];
376         size_t block_len, pos = 0;
377         unsigned int command;
378         int rc = 0;
379
380         while (pos < len) {
381                 rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
382                 if (rc)
383                         break;
384
385                 block_len = min(len - pos,
386                                 falcon_spi_write_limit(spi, start + pos));
387                 command = efx_spi_munge_command(spi, SPI_WRITE, start + pos);
388                 rc = falcon_spi_cmd(efx, spi, command, start + pos,
389                                     buffer + pos, NULL, block_len);
390                 if (rc)
391                         break;
392
393                 rc = falcon_spi_wait_write(efx, spi);
394                 if (rc)
395                         break;
396
397                 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
398                 rc = falcon_spi_cmd(efx, spi, command, start + pos,
399                                     NULL, verify_buffer, block_len);
400                 if (memcmp(verify_buffer, buffer + pos, block_len)) {
401                         rc = -EIO;
402                         break;
403                 }
404
405                 pos += block_len;
406
407                 /* Avoid locking up the system */
408                 cond_resched();
409                 if (signal_pending(current)) {
410                         rc = -EINTR;
411                         break;
412                 }
413         }
414
415         if (retlen)
416                 *retlen = pos;
417         return rc;
418 }
419
420 /**************************************************************************
421  *
422  * MAC wrapper
423  *
424  **************************************************************************
425  */
426
427 static void falcon_push_multicast_hash(struct efx_nic *efx)
428 {
429         union efx_multicast_hash *mc_hash = &efx->multicast_hash;
430
431         WARN_ON(!mutex_is_locked(&efx->mac_lock));
432
433         efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0);
434         efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1);
435 }
436
437 static void falcon_reset_macs(struct efx_nic *efx)
438 {
439         struct falcon_nic_data *nic_data = efx->nic_data;
440         efx_oword_t reg, mac_ctrl;
441         int count;
442
443         if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) {
444                 /* It's not safe to use GLB_CTL_REG to reset the
445                  * macs, so instead use the internal MAC resets
446                  */
447                 EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1);
448                 efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);
449
450                 for (count = 0; count < 10000; count++) {
451                         efx_reado(efx, &reg, FR_AB_XM_GLB_CFG);
452                         if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) ==
453                             0)
454                                 return;
455                         udelay(10);
456                 }
457
458                 netif_err(efx, hw, efx->net_dev,
459                           "timed out waiting for XMAC core reset\n");
460         }
461
462         /* Mac stats will fail whist the TX fifo is draining */
463         WARN_ON(nic_data->stats_disable_count == 0);
464
465         efx_reado(efx, &mac_ctrl, FR_AB_MAC_CTRL);
466         EFX_SET_OWORD_FIELD(mac_ctrl, FRF_BB_TXFIFO_DRAIN_EN, 1);
467         efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
468
469         efx_reado(efx, &reg, FR_AB_GLB_CTL);
470         EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1);
471         EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1);
472         EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1);
473         efx_writeo(efx, &reg, FR_AB_GLB_CTL);
474
475         count = 0;
476         while (1) {
477                 efx_reado(efx, &reg, FR_AB_GLB_CTL);
478                 if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) &&
479                     !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) &&
480                     !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) {
481                         netif_dbg(efx, hw, efx->net_dev,
482                                   "Completed MAC reset after %d loops\n",
483                                   count);
484                         break;
485                 }
486                 if (count > 20) {
487                         netif_err(efx, hw, efx->net_dev, "MAC reset failed\n");
488                         break;
489                 }
490                 count++;
491                 udelay(10);
492         }
493
494         /* Ensure the correct MAC is selected before statistics
495          * are re-enabled by the caller */
496         efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
497
498         falcon_setup_xaui(efx);
499 }
500
501 void falcon_drain_tx_fifo(struct efx_nic *efx)
502 {
503         efx_oword_t reg;
504
505         if ((efx_nic_rev(efx) < EFX_REV_FALCON_B0) ||
506             (efx->loopback_mode != LOOPBACK_NONE))
507                 return;
508
509         efx_reado(efx, &reg, FR_AB_MAC_CTRL);
510         /* There is no point in draining more than once */
511         if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN))
512                 return;
513
514         falcon_reset_macs(efx);
515 }
516
517 static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
518 {
519         efx_oword_t reg;
520
521         if (efx_nic_rev(efx) < EFX_REV_FALCON_B0)
522                 return;
523
524         /* Isolate the MAC -> RX */
525         efx_reado(efx, &reg, FR_AZ_RX_CFG);
526         EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0);
527         efx_writeo(efx, &reg, FR_AZ_RX_CFG);
528
529         /* Isolate TX -> MAC */
530         falcon_drain_tx_fifo(efx);
531 }
532
533 void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
534 {
535         struct efx_link_state *link_state = &efx->link_state;
536         efx_oword_t reg;
537         int link_speed, isolate;
538
539         isolate = !!ACCESS_ONCE(efx->reset_pending);
540
541         switch (link_state->speed) {
542         case 10000: link_speed = 3; break;
543         case 1000:  link_speed = 2; break;
544         case 100:   link_speed = 1; break;
545         default:    link_speed = 0; break;
546         }
547         /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
548          * as advertised.  Disable to ensure packets are not
549          * indefinitely held and TX queue can be flushed at any point
550          * while the link is down. */
551         EFX_POPULATE_OWORD_5(reg,
552                              FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */,
553                              FRF_AB_MAC_BCAD_ACPT, 1,
554                              FRF_AB_MAC_UC_PROM, efx->promiscuous,
555                              FRF_AB_MAC_LINK_STATUS, 1, /* always set */
556                              FRF_AB_MAC_SPEED, link_speed);
557         /* On B0, MAC backpressure can be disabled and packets get
558          * discarded. */
559         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
560                 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN,
561                                     !link_state->up || isolate);
562         }
563
564         efx_writeo(efx, &reg, FR_AB_MAC_CTRL);
565
566         /* Restore the multicast hash registers. */
567         falcon_push_multicast_hash(efx);
568
569         efx_reado(efx, &reg, FR_AZ_RX_CFG);
570         /* Enable XOFF signal from RX FIFO (we enabled it during NIC
571          * initialisation but it may read back as 0) */
572         EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
573         /* Unisolate the MAC -> RX */
574         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
575                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, !isolate);
576         efx_writeo(efx, &reg, FR_AZ_RX_CFG);
577 }
578
579 static void falcon_stats_request(struct efx_nic *efx)
580 {
581         struct falcon_nic_data *nic_data = efx->nic_data;
582         efx_oword_t reg;
583
584         WARN_ON(nic_data->stats_pending);
585         WARN_ON(nic_data->stats_disable_count);
586
587         if (nic_data->stats_dma_done == NULL)
588                 return; /* no mac selected */
589
590         *nic_data->stats_dma_done = FALCON_STATS_NOT_DONE;
591         nic_data->stats_pending = true;
592         wmb(); /* ensure done flag is clear */
593
594         /* Initiate DMA transfer of stats */
595         EFX_POPULATE_OWORD_2(reg,
596                              FRF_AB_MAC_STAT_DMA_CMD, 1,
597                              FRF_AB_MAC_STAT_DMA_ADR,
598                              efx->stats_buffer.dma_addr);
599         efx_writeo(efx, &reg, FR_AB_MAC_STAT_DMA);
600
601         mod_timer(&nic_data->stats_timer, round_jiffies_up(jiffies + HZ / 2));
602 }
603
604 static void falcon_stats_complete(struct efx_nic *efx)
605 {
606         struct falcon_nic_data *nic_data = efx->nic_data;
607
608         if (!nic_data->stats_pending)
609                 return;
610
611         nic_data->stats_pending = 0;
612         if (*nic_data->stats_dma_done == FALCON_STATS_DONE) {
613                 rmb(); /* read the done flag before the stats */
614                 efx->mac_op->update_stats(efx);
615         } else {
616                 netif_err(efx, hw, efx->net_dev,
617                           "timed out waiting for statistics\n");
618         }
619 }
620
621 static void falcon_stats_timer_func(unsigned long context)
622 {
623         struct efx_nic *efx = (struct efx_nic *)context;
624         struct falcon_nic_data *nic_data = efx->nic_data;
625
626         spin_lock(&efx->stats_lock);
627
628         falcon_stats_complete(efx);
629         if (nic_data->stats_disable_count == 0)
630                 falcon_stats_request(efx);
631
632         spin_unlock(&efx->stats_lock);
633 }
634
635 static bool falcon_loopback_link_poll(struct efx_nic *efx)
636 {
637         struct efx_link_state old_state = efx->link_state;
638
639         WARN_ON(!mutex_is_locked(&efx->mac_lock));
640         WARN_ON(!LOOPBACK_INTERNAL(efx));
641
642         efx->link_state.fd = true;
643         efx->link_state.fc = efx->wanted_fc;
644         efx->link_state.up = true;
645         efx->link_state.speed = 10000;
646
647         return !efx_link_state_equal(&efx->link_state, &old_state);
648 }
649
650 static int falcon_reconfigure_port(struct efx_nic *efx)
651 {
652         int rc;
653
654         WARN_ON(efx_nic_rev(efx) > EFX_REV_FALCON_B0);
655
656         /* Poll the PHY link state *before* reconfiguring it. This means we
657          * will pick up the correct speed (in loopback) to select the correct
658          * MAC.
659          */
660         if (LOOPBACK_INTERNAL(efx))
661                 falcon_loopback_link_poll(efx);
662         else
663                 efx->phy_op->poll(efx);
664
665         falcon_stop_nic_stats(efx);
666         falcon_deconfigure_mac_wrapper(efx);
667
668         falcon_reset_macs(efx);
669
670         efx->phy_op->reconfigure(efx);
671         rc = efx->mac_op->reconfigure(efx);
672         BUG_ON(rc);
673
674         falcon_start_nic_stats(efx);
675
676         /* Synchronise efx->link_state with the kernel */
677         efx_link_status_changed(efx);
678
679         return 0;
680 }
681
682 /**************************************************************************
683  *
684  * PHY access via GMII
685  *
686  **************************************************************************
687  */
688
689 /* Wait for GMII access to complete */
690 static int falcon_gmii_wait(struct efx_nic *efx)
691 {
692         efx_oword_t md_stat;
693         int count;
694
695         /* wait up to 50ms - taken max from datasheet */
696         for (count = 0; count < 5000; count++) {
697                 efx_reado(efx, &md_stat, FR_AB_MD_STAT);
698                 if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) {
699                         if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 ||
700                             EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) {
701                                 netif_err(efx, hw, efx->net_dev,
702                                           "error from GMII access "
703                                           EFX_OWORD_FMT"\n",
704                                           EFX_OWORD_VAL(md_stat));
705                                 return -EIO;
706                         }
707                         return 0;
708                 }
709                 udelay(10);
710         }
711         netif_err(efx, hw, efx->net_dev, "timed out waiting for GMII\n");
712         return -ETIMEDOUT;
713 }
714
715 /* Write an MDIO register of a PHY connected to Falcon. */
716 static int falcon_mdio_write(struct net_device *net_dev,
717                              int prtad, int devad, u16 addr, u16 value)
718 {
719         struct efx_nic *efx = netdev_priv(net_dev);
720         struct falcon_nic_data *nic_data = efx->nic_data;
721         efx_oword_t reg;
722         int rc;
723
724         netif_vdbg(efx, hw, efx->net_dev,
725                    "writing MDIO %d register %d.%d with 0x%04x\n",
726                     prtad, devad, addr, value);
727
728         mutex_lock(&nic_data->mdio_lock);
729
730         /* Check MDIO not currently being accessed */
731         rc = falcon_gmii_wait(efx);
732         if (rc)
733                 goto out;
734
735         /* Write the address/ID register */
736         EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
737         efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
738
739         EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
740                              FRF_AB_MD_DEV_ADR, devad);
741         efx_writeo(efx, &reg, FR_AB_MD_ID);
742
743         /* Write data */
744         EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value);
745         efx_writeo(efx, &reg, FR_AB_MD_TXD);
746
747         EFX_POPULATE_OWORD_2(reg,
748                              FRF_AB_MD_WRC, 1,
749                              FRF_AB_MD_GC, 0);
750         efx_writeo(efx, &reg, FR_AB_MD_CS);
751
752         /* Wait for data to be written */
753         rc = falcon_gmii_wait(efx);
754         if (rc) {
755                 /* Abort the write operation */
756                 EFX_POPULATE_OWORD_2(reg,
757                                      FRF_AB_MD_WRC, 0,
758                                      FRF_AB_MD_GC, 1);
759                 efx_writeo(efx, &reg, FR_AB_MD_CS);
760                 udelay(10);
761         }
762
763 out:
764         mutex_unlock(&nic_data->mdio_lock);
765         return rc;
766 }
767
768 /* Read an MDIO register of a PHY connected to Falcon. */
769 static int falcon_mdio_read(struct net_device *net_dev,
770                             int prtad, int devad, u16 addr)
771 {
772         struct efx_nic *efx = netdev_priv(net_dev);
773         struct falcon_nic_data *nic_data = efx->nic_data;
774         efx_oword_t reg;
775         int rc;
776
777         mutex_lock(&nic_data->mdio_lock);
778
779         /* Check MDIO not currently being accessed */
780         rc = falcon_gmii_wait(efx);
781         if (rc)
782                 goto out;
783
784         EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
785         efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
786
787         EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
788                              FRF_AB_MD_DEV_ADR, devad);
789         efx_writeo(efx, &reg, FR_AB_MD_ID);
790
791         /* Request data to be read */
792         EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0);
793         efx_writeo(efx, &reg, FR_AB_MD_CS);
794
795         /* Wait for data to become available */
796         rc = falcon_gmii_wait(efx);
797         if (rc == 0) {
798                 efx_reado(efx, &reg, FR_AB_MD_RXD);
799                 rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD);
800                 netif_vdbg(efx, hw, efx->net_dev,
801                            "read from MDIO %d register %d.%d, got %04x\n",
802                            prtad, devad, addr, rc);
803         } else {
804                 /* Abort the read operation */
805                 EFX_POPULATE_OWORD_2(reg,
806                                      FRF_AB_MD_RIC, 0,
807                                      FRF_AB_MD_GC, 1);
808                 efx_writeo(efx, &reg, FR_AB_MD_CS);
809
810                 netif_dbg(efx, hw, efx->net_dev,
811                           "read from MDIO %d register %d.%d, got error %d\n",
812                           prtad, devad, addr, rc);
813         }
814
815 out:
816         mutex_unlock(&nic_data->mdio_lock);
817         return rc;
818 }
819
820 /* This call is responsible for hooking in the MAC and PHY operations */
821 static int falcon_probe_port(struct efx_nic *efx)
822 {
823         struct falcon_nic_data *nic_data = efx->nic_data;
824         int rc;
825
826         switch (efx->phy_type) {
827         case PHY_TYPE_SFX7101:
828                 efx->phy_op = &falcon_sfx7101_phy_ops;
829                 break;
830         case PHY_TYPE_QT2022C2:
831         case PHY_TYPE_QT2025C:
832                 efx->phy_op = &falcon_qt202x_phy_ops;
833                 break;
834         case PHY_TYPE_TXC43128:
835                 efx->phy_op = &falcon_txc_phy_ops;
836                 break;
837         default:
838                 netif_err(efx, probe, efx->net_dev, "Unknown PHY type %d\n",
839                           efx->phy_type);
840                 return -ENODEV;
841         }
842
843         /* Fill out MDIO structure and loopback modes */
844         mutex_init(&nic_data->mdio_lock);
845         efx->mdio.mdio_read = falcon_mdio_read;
846         efx->mdio.mdio_write = falcon_mdio_write;
847         rc = efx->phy_op->probe(efx);
848         if (rc != 0)
849                 return rc;
850
851         /* Initial assumption */
852         efx->link_state.speed = 10000;
853         efx->link_state.fd = true;
854
855         /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
856         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
857                 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
858         else
859                 efx->wanted_fc = EFX_FC_RX;
860         if (efx->mdio.mmds & MDIO_DEVS_AN)
861                 efx->wanted_fc |= EFX_FC_AUTO;
862
863         /* Allocate buffer for stats */
864         rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer,
865                                   FALCON_MAC_STATS_SIZE);
866         if (rc)
867                 return rc;
868         netif_dbg(efx, probe, efx->net_dev,
869                   "stats buffer at %llx (virt %p phys %llx)\n",
870                   (u64)efx->stats_buffer.dma_addr,
871                   efx->stats_buffer.addr,
872                   (u64)virt_to_phys(efx->stats_buffer.addr));
873         nic_data->stats_dma_done = efx->stats_buffer.addr + XgDmaDone_offset;
874
875         return 0;
876 }
877
878 static void falcon_remove_port(struct efx_nic *efx)
879 {
880         efx->phy_op->remove(efx);
881         efx_nic_free_buffer(efx, &efx->stats_buffer);
882 }
883
884 /* Global events are basically PHY events */
885 static bool
886 falcon_handle_global_event(struct efx_channel *channel, efx_qword_t *event)
887 {
888         struct efx_nic *efx = channel->efx;
889         struct falcon_nic_data *nic_data = efx->nic_data;
890
891         if (EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_G_PHY0_INTR) ||
892             EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XG_PHY0_INTR) ||
893             EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XFP_PHY0_INTR))
894                 /* Ignored */
895                 return true;
896
897         if ((efx_nic_rev(efx) == EFX_REV_FALCON_B0) &&
898             EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_XG_MGT_INTR)) {
899                 nic_data->xmac_poll_required = true;
900                 return true;
901         }
902
903         if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1 ?
904             EFX_QWORD_FIELD(*event, FSF_AA_GLB_EV_RX_RECOVERY) :
905             EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_RX_RECOVERY)) {
906                 netif_err(efx, rx_err, efx->net_dev,
907                           "channel %d seen global RX_RESET event. Resetting.\n",
908                           channel->channel);
909
910                 atomic_inc(&efx->rx_reset);
911                 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
912                                    RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
913                 return true;
914         }
915
916         return false;
917 }
918
919 /**************************************************************************
920  *
921  * Falcon test code
922  *
923  **************************************************************************/
924
925 static int
926 falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
927 {
928         struct falcon_nic_data *nic_data = efx->nic_data;
929         struct falcon_nvconfig *nvconfig;
930         struct efx_spi_device *spi;
931         void *region;
932         int rc, magic_num, struct_ver;
933         __le16 *word, *limit;
934         u32 csum;
935
936         if (efx_spi_present(&nic_data->spi_flash))
937                 spi = &nic_data->spi_flash;
938         else if (efx_spi_present(&nic_data->spi_eeprom))
939                 spi = &nic_data->spi_eeprom;
940         else
941                 return -EINVAL;
942
943         region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
944         if (!region)
945                 return -ENOMEM;
946         nvconfig = region + FALCON_NVCONFIG_OFFSET;
947
948         mutex_lock(&nic_data->spi_lock);
949         rc = falcon_spi_read(efx, spi, 0, FALCON_NVCONFIG_END, NULL, region);
950         mutex_unlock(&nic_data->spi_lock);
951         if (rc) {
952                 netif_err(efx, hw, efx->net_dev, "Failed to read %s\n",
953                           efx_spi_present(&nic_data->spi_flash) ?
954                           "flash" : "EEPROM");
955                 rc = -EIO;
956                 goto out;
957         }
958
959         magic_num = le16_to_cpu(nvconfig->board_magic_num);
960         struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
961
962         rc = -EINVAL;
963         if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) {
964                 netif_err(efx, hw, efx->net_dev,
965                           "NVRAM bad magic 0x%x\n", magic_num);
966                 goto out;
967         }
968         if (struct_ver < 2) {
969                 netif_err(efx, hw, efx->net_dev,
970                           "NVRAM has ancient version 0x%x\n", struct_ver);
971                 goto out;
972         } else if (struct_ver < 4) {
973                 word = &nvconfig->board_magic_num;
974                 limit = (__le16 *) (nvconfig + 1);
975         } else {
976                 word = region;
977                 limit = region + FALCON_NVCONFIG_END;
978         }
979         for (csum = 0; word < limit; ++word)
980                 csum += le16_to_cpu(*word);
981
982         if (~csum & 0xffff) {
983                 netif_err(efx, hw, efx->net_dev,
984                           "NVRAM has incorrect checksum\n");
985                 goto out;
986         }
987
988         rc = 0;
989         if (nvconfig_out)
990                 memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
991
992  out:
993         kfree(region);
994         return rc;
995 }
996
997 static int falcon_test_nvram(struct efx_nic *efx)
998 {
999         return falcon_read_nvram(efx, NULL);
1000 }
1001
1002 static const struct efx_nic_register_test falcon_b0_register_tests[] = {
1003         { FR_AZ_ADR_REGION,
1004           EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
1005         { FR_AZ_RX_CFG,
1006           EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
1007         { FR_AZ_TX_CFG,
1008           EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
1009         { FR_AZ_TX_RESERVED,
1010           EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
1011         { FR_AB_MAC_CTRL,
1012           EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
1013         { FR_AZ_SRM_TX_DC_CFG,
1014           EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
1015         { FR_AZ_RX_DC_CFG,
1016           EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
1017         { FR_AZ_RX_DC_PF_WM,
1018           EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
1019         { FR_BZ_DP_CTRL,
1020           EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
1021         { FR_AB_GM_CFG2,
1022           EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
1023         { FR_AB_GMF_CFG0,
1024           EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
1025         { FR_AB_XM_GLB_CFG,
1026           EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
1027         { FR_AB_XM_TX_CFG,
1028           EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
1029         { FR_AB_XM_RX_CFG,
1030           EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
1031         { FR_AB_XM_RX_PARAM,
1032           EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
1033         { FR_AB_XM_FC,
1034           EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
1035         { FR_AB_XM_ADR_LO,
1036           EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
1037         { FR_AB_XX_SD_CTL,
1038           EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
1039 };
1040
1041 static int falcon_b0_test_registers(struct efx_nic *efx)
1042 {
1043         return efx_nic_test_registers(efx, falcon_b0_register_tests,
1044                                       ARRAY_SIZE(falcon_b0_register_tests));
1045 }
1046
1047 /**************************************************************************
1048  *
1049  * Device reset
1050  *
1051  **************************************************************************
1052  */
1053
1054 /* Resets NIC to known state.  This routine must be called in process
1055  * context and is allowed to sleep. */
1056 static int __falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
1057 {
1058         struct falcon_nic_data *nic_data = efx->nic_data;
1059         efx_oword_t glb_ctl_reg_ker;
1060         int rc;
1061
1062         netif_dbg(efx, hw, efx->net_dev, "performing %s hardware reset\n",
1063                   RESET_TYPE(method));
1064
1065         /* Initiate device reset */
1066         if (method == RESET_TYPE_WORLD) {
1067                 rc = pci_save_state(efx->pci_dev);
1068                 if (rc) {
1069                         netif_err(efx, drv, efx->net_dev,
1070                                   "failed to backup PCI state of primary "
1071                                   "function prior to hardware reset\n");
1072                         goto fail1;
1073                 }
1074                 if (efx_nic_is_dual_func(efx)) {
1075                         rc = pci_save_state(nic_data->pci_dev2);
1076                         if (rc) {
1077                                 netif_err(efx, drv, efx->net_dev,
1078                                           "failed to backup PCI state of "
1079                                           "secondary function prior to "
1080                                           "hardware reset\n");
1081                                 goto fail2;
1082                         }
1083                 }
1084
1085                 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
1086                                      FRF_AB_EXT_PHY_RST_DUR,
1087                                      FFE_AB_EXT_PHY_RST_DUR_10240US,
1088                                      FRF_AB_SWRST, 1);
1089         } else {
1090                 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
1091                                      /* exclude PHY from "invisible" reset */
1092                                      FRF_AB_EXT_PHY_RST_CTL,
1093                                      method == RESET_TYPE_INVISIBLE,
1094                                      /* exclude EEPROM/flash and PCIe */
1095                                      FRF_AB_PCIE_CORE_RST_CTL, 1,
1096                                      FRF_AB_PCIE_NSTKY_RST_CTL, 1,
1097                                      FRF_AB_PCIE_SD_RST_CTL, 1,
1098                                      FRF_AB_EE_RST_CTL, 1,
1099                                      FRF_AB_EXT_PHY_RST_DUR,
1100                                      FFE_AB_EXT_PHY_RST_DUR_10240US,
1101                                      FRF_AB_SWRST, 1);
1102         }
1103         efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
1104
1105         netif_dbg(efx, hw, efx->net_dev, "waiting for hardware reset\n");
1106         schedule_timeout_uninterruptible(HZ / 20);
1107
1108         /* Restore PCI configuration if needed */
1109         if (method == RESET_TYPE_WORLD) {
1110                 if (efx_nic_is_dual_func(efx))
1111                         pci_restore_state(nic_data->pci_dev2);
1112                 pci_restore_state(efx->pci_dev);
1113                 netif_dbg(efx, drv, efx->net_dev,
1114                           "successfully restored PCI config\n");
1115         }
1116
1117         /* Assert that reset complete */
1118         efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
1119         if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) {
1120                 rc = -ETIMEDOUT;
1121                 netif_err(efx, hw, efx->net_dev,
1122                           "timed out waiting for hardware reset\n");
1123                 goto fail3;
1124         }
1125         netif_dbg(efx, hw, efx->net_dev, "hardware reset complete\n");
1126
1127         return 0;
1128
1129         /* pci_save_state() and pci_restore_state() MUST be called in pairs */
1130 fail2:
1131         pci_restore_state(efx->pci_dev);
1132 fail1:
1133 fail3:
1134         return rc;
1135 }
1136
1137 static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
1138 {
1139         struct falcon_nic_data *nic_data = efx->nic_data;
1140         int rc;
1141
1142         mutex_lock(&nic_data->spi_lock);
1143         rc = __falcon_reset_hw(efx, method);
1144         mutex_unlock(&nic_data->spi_lock);
1145
1146         return rc;
1147 }
1148
1149 static void falcon_monitor(struct efx_nic *efx)
1150 {
1151         bool link_changed;
1152         int rc;
1153
1154         BUG_ON(!mutex_is_locked(&efx->mac_lock));
1155
1156         rc = falcon_board(efx)->type->monitor(efx);
1157         if (rc) {
1158                 netif_err(efx, hw, efx->net_dev,
1159                           "Board sensor %s; shutting down PHY\n",
1160                           (rc == -ERANGE) ? "reported fault" : "failed");
1161                 efx->phy_mode |= PHY_MODE_LOW_POWER;
1162                 rc = __efx_reconfigure_port(efx);
1163                 WARN_ON(rc);
1164         }
1165
1166         if (LOOPBACK_INTERNAL(efx))
1167                 link_changed = falcon_loopback_link_poll(efx);
1168         else
1169                 link_changed = efx->phy_op->poll(efx);
1170
1171         if (link_changed) {
1172                 falcon_stop_nic_stats(efx);
1173                 falcon_deconfigure_mac_wrapper(efx);
1174
1175                 falcon_reset_macs(efx);
1176                 rc = efx->mac_op->reconfigure(efx);
1177                 BUG_ON(rc);
1178
1179                 falcon_start_nic_stats(efx);
1180
1181                 efx_link_status_changed(efx);
1182         }
1183
1184         falcon_poll_xmac(efx);
1185 }
1186
1187 /* Zeroes out the SRAM contents.  This routine must be called in
1188  * process context and is allowed to sleep.
1189  */
1190 static int falcon_reset_sram(struct efx_nic *efx)
1191 {
1192         efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
1193         int count;
1194
1195         /* Set the SRAM wake/sleep GPIO appropriately. */
1196         efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
1197         EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1);
1198         EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1);
1199         efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
1200
1201         /* Initiate SRAM reset */
1202         EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
1203                              FRF_AZ_SRM_INIT_EN, 1,
1204                              FRF_AZ_SRM_NB_SZ, 0);
1205         efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
1206
1207         /* Wait for SRAM reset to complete */
1208         count = 0;
1209         do {
1210                 netif_dbg(efx, hw, efx->net_dev,
1211                           "waiting for SRAM reset (attempt %d)...\n", count);
1212
1213                 /* SRAM reset is slow; expect around 16ms */
1214                 schedule_timeout_uninterruptible(HZ / 50);
1215
1216                 /* Check for reset complete */
1217                 efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
1218                 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) {
1219                         netif_dbg(efx, hw, efx->net_dev,
1220                                   "SRAM reset complete\n");
1221
1222                         return 0;
1223                 }
1224         } while (++count < 20); /* wait up to 0.4 sec */
1225
1226         netif_err(efx, hw, efx->net_dev, "timed out waiting for SRAM reset\n");
1227         return -ETIMEDOUT;
1228 }
1229
1230 static void falcon_spi_device_init(struct efx_nic *efx,
1231                                   struct efx_spi_device *spi_device,
1232                                   unsigned int device_id, u32 device_type)
1233 {
1234         if (device_type != 0) {
1235                 spi_device->device_id = device_id;
1236                 spi_device->size =
1237                         1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
1238                 spi_device->addr_len =
1239                         SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
1240                 spi_device->munge_address = (spi_device->size == 1 << 9 &&
1241                                              spi_device->addr_len == 1);
1242                 spi_device->erase_command =
1243                         SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD);
1244                 spi_device->erase_size =
1245                         1 << SPI_DEV_TYPE_FIELD(device_type,
1246                                                 SPI_DEV_TYPE_ERASE_SIZE);
1247                 spi_device->block_size =
1248                         1 << SPI_DEV_TYPE_FIELD(device_type,
1249                                                 SPI_DEV_TYPE_BLOCK_SIZE);
1250         } else {
1251                 spi_device->size = 0;
1252         }
1253 }
1254
1255 /* Extract non-volatile configuration */
1256 static int falcon_probe_nvconfig(struct efx_nic *efx)
1257 {
1258         struct falcon_nic_data *nic_data = efx->nic_data;
1259         struct falcon_nvconfig *nvconfig;
1260         int rc;
1261
1262         nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
1263         if (!nvconfig)
1264                 return -ENOMEM;
1265
1266         rc = falcon_read_nvram(efx, nvconfig);
1267         if (rc)
1268                 goto out;
1269
1270         efx->phy_type = nvconfig->board_v2.port0_phy_type;
1271         efx->mdio.prtad = nvconfig->board_v2.port0_phy_addr;
1272
1273         if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
1274                 falcon_spi_device_init(
1275                         efx, &nic_data->spi_flash, FFE_AB_SPI_DEVICE_FLASH,
1276                         le32_to_cpu(nvconfig->board_v3
1277                                     .spi_device_type[FFE_AB_SPI_DEVICE_FLASH]));
1278                 falcon_spi_device_init(
1279                         efx, &nic_data->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM,
1280                         le32_to_cpu(nvconfig->board_v3
1281                                     .spi_device_type[FFE_AB_SPI_DEVICE_EEPROM]));
1282         }
1283
1284         /* Read the MAC addresses */
1285         memcpy(efx->net_dev->perm_addr, nvconfig->mac_address[0], ETH_ALEN);
1286
1287         netif_dbg(efx, probe, efx->net_dev, "PHY is %d phy_id %d\n",
1288                   efx->phy_type, efx->mdio.prtad);
1289
1290         rc = falcon_probe_board(efx,
1291                                 le16_to_cpu(nvconfig->board_v2.board_revision));
1292 out:
1293         kfree(nvconfig);
1294         return rc;
1295 }
1296
1297 /* Probe all SPI devices on the NIC */
1298 static void falcon_probe_spi_devices(struct efx_nic *efx)
1299 {
1300         struct falcon_nic_data *nic_data = efx->nic_data;
1301         efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
1302         int boot_dev;
1303
1304         efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL);
1305         efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
1306         efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
1307
1308         if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) {
1309                 boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ?
1310                             FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM);
1311                 netif_dbg(efx, probe, efx->net_dev, "Booted from %s\n",
1312                           boot_dev == FFE_AB_SPI_DEVICE_FLASH ?
1313                           "flash" : "EEPROM");
1314         } else {
1315                 /* Disable VPD and set clock dividers to safe
1316                  * values for initial programming. */
1317                 boot_dev = -1;
1318                 netif_dbg(efx, probe, efx->net_dev,
1319                           "Booted from internal ASIC settings;"
1320                           " setting SPI config\n");
1321                 EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0,
1322                                      /* 125 MHz / 7 ~= 20 MHz */
1323                                      FRF_AB_EE_SF_CLOCK_DIV, 7,
1324                                      /* 125 MHz / 63 ~= 2 MHz */
1325                                      FRF_AB_EE_EE_CLOCK_DIV, 63);
1326                 efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
1327         }
1328
1329         mutex_init(&nic_data->spi_lock);
1330
1331         if (boot_dev == FFE_AB_SPI_DEVICE_FLASH)
1332                 falcon_spi_device_init(efx, &nic_data->spi_flash,
1333                                        FFE_AB_SPI_DEVICE_FLASH,
1334                                        default_flash_type);
1335         if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM)
1336                 falcon_spi_device_init(efx, &nic_data->spi_eeprom,
1337                                        FFE_AB_SPI_DEVICE_EEPROM,
1338                                        large_eeprom_type);
1339 }
1340
1341 static int falcon_probe_nic(struct efx_nic *efx)
1342 {
1343         struct falcon_nic_data *nic_data;
1344         struct falcon_board *board;
1345         int rc;
1346
1347         /* Allocate storage for hardware specific data */
1348         nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
1349         if (!nic_data)
1350                 return -ENOMEM;
1351         efx->nic_data = nic_data;
1352
1353         rc = -ENODEV;
1354
1355         if (efx_nic_fpga_ver(efx) != 0) {
1356                 netif_err(efx, probe, efx->net_dev,
1357                           "Falcon FPGA not supported\n");
1358                 goto fail1;
1359         }
1360
1361         if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
1362                 efx_oword_t nic_stat;
1363                 struct pci_dev *dev;
1364                 u8 pci_rev = efx->pci_dev->revision;
1365
1366                 if ((pci_rev == 0xff) || (pci_rev == 0)) {
1367                         netif_err(efx, probe, efx->net_dev,
1368                                   "Falcon rev A0 not supported\n");
1369                         goto fail1;
1370                 }
1371                 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
1372                 if (EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) == 0) {
1373                         netif_err(efx, probe, efx->net_dev,
1374                                   "Falcon rev A1 1G not supported\n");
1375                         goto fail1;
1376                 }
1377                 if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) {
1378                         netif_err(efx, probe, efx->net_dev,
1379                                   "Falcon rev A1 PCI-X not supported\n");
1380                         goto fail1;
1381                 }
1382
1383                 dev = pci_dev_get(efx->pci_dev);
1384                 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
1385                                              dev))) {
1386                         if (dev->bus == efx->pci_dev->bus &&
1387                             dev->devfn == efx->pci_dev->devfn + 1) {
1388                                 nic_data->pci_dev2 = dev;
1389                                 break;
1390                         }
1391                 }
1392                 if (!nic_data->pci_dev2) {
1393                         netif_err(efx, probe, efx->net_dev,
1394                                   "failed to find secondary function\n");
1395                         rc = -ENODEV;
1396                         goto fail2;
1397                 }
1398         }
1399
1400         /* Now we can reset the NIC */
1401         rc = __falcon_reset_hw(efx, RESET_TYPE_ALL);
1402         if (rc) {
1403                 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
1404                 goto fail3;
1405         }
1406
1407         /* Allocate memory for INT_KER */
1408         rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
1409         if (rc)
1410                 goto fail4;
1411         BUG_ON(efx->irq_status.dma_addr & 0x0f);
1412
1413         netif_dbg(efx, probe, efx->net_dev,
1414                   "INT_KER at %llx (virt %p phys %llx)\n",
1415                   (u64)efx->irq_status.dma_addr,
1416                   efx->irq_status.addr,
1417                   (u64)virt_to_phys(efx->irq_status.addr));
1418
1419         falcon_probe_spi_devices(efx);
1420
1421         /* Read in the non-volatile configuration */
1422         rc = falcon_probe_nvconfig(efx);
1423         if (rc) {
1424                 if (rc == -EINVAL)
1425                         netif_err(efx, probe, efx->net_dev, "NVRAM is invalid\n");
1426                 goto fail5;
1427         }
1428
1429         /* Initialise I2C adapter */
1430         board = falcon_board(efx);
1431         board->i2c_adap.owner = THIS_MODULE;
1432         board->i2c_data = falcon_i2c_bit_operations;
1433         board->i2c_data.data = efx;
1434         board->i2c_adap.algo_data = &board->i2c_data;
1435         board->i2c_adap.dev.parent = &efx->pci_dev->dev;
1436         strlcpy(board->i2c_adap.name, "SFC4000 GPIO",
1437                 sizeof(board->i2c_adap.name));
1438         rc = i2c_bit_add_bus(&board->i2c_adap);
1439         if (rc)
1440                 goto fail5;
1441
1442         rc = falcon_board(efx)->type->init(efx);
1443         if (rc) {
1444                 netif_err(efx, probe, efx->net_dev,
1445                           "failed to initialise board\n");
1446                 goto fail6;
1447         }
1448
1449         nic_data->stats_disable_count = 1;
1450         setup_timer(&nic_data->stats_timer, &falcon_stats_timer_func,
1451                     (unsigned long)efx);
1452
1453         return 0;
1454
1455  fail6:
1456         BUG_ON(i2c_del_adapter(&board->i2c_adap));
1457         memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
1458  fail5:
1459         efx_nic_free_buffer(efx, &efx->irq_status);
1460  fail4:
1461  fail3:
1462         if (nic_data->pci_dev2) {
1463                 pci_dev_put(nic_data->pci_dev2);
1464                 nic_data->pci_dev2 = NULL;
1465         }
1466  fail2:
1467  fail1:
1468         kfree(efx->nic_data);
1469         return rc;
1470 }
1471
1472 static void falcon_init_rx_cfg(struct efx_nic *efx)
1473 {
1474         /* Prior to Siena the RX DMA engine will split each frame at
1475          * intervals of RX_USR_BUF_SIZE (32-byte units). We set it to
1476          * be so large that that never happens. */
1477         const unsigned huge_buf_size = (3 * 4096) >> 5;
1478         /* RX control FIFO thresholds (32 entries) */
1479         const unsigned ctrl_xon_thr = 20;
1480         const unsigned ctrl_xoff_thr = 25;
1481         efx_oword_t reg;
1482
1483         efx_reado(efx, &reg, FR_AZ_RX_CFG);
1484         if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
1485                 /* Data FIFO size is 5.5K */
1486                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0);
1487                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE,
1488                                     huge_buf_size);
1489                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, 512 >> 8);
1490                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, 2048 >> 8);
1491                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr);
1492                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr);
1493         } else {
1494                 /* Data FIFO size is 80K; register fields moved */
1495                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0);
1496                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE,
1497                                     huge_buf_size);
1498                 /* Send XON and XOFF at ~3 * max MTU away from empty/full */
1499                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, 27648 >> 8);
1500                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, 54272 >> 8);
1501                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr);
1502                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr);
1503                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
1504
1505                 /* Enable hash insertion. This is broken for the
1506                  * 'Falcon' hash so also select Toeplitz TCP/IPv4 and
1507                  * IPv4 hashes. */
1508                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_INSRT_HDR, 1);
1509                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_ALG, 1);
1510                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_IP_HASH, 1);
1511         }
1512         /* Always enable XOFF signal from RX FIFO.  We enable
1513          * or disable transmission of pause frames at the MAC. */
1514         EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
1515         efx_writeo(efx, &reg, FR_AZ_RX_CFG);
1516 }
1517
1518 /* This call performs hardware-specific global initialisation, such as
1519  * defining the descriptor cache sizes and number of RSS channels.
1520  * It does not set up any buffers, descriptor rings or event queues.
1521  */
1522 static int falcon_init_nic(struct efx_nic *efx)
1523 {
1524         efx_oword_t temp;
1525         int rc;
1526
1527         /* Use on-chip SRAM */
1528         efx_reado(efx, &temp, FR_AB_NIC_STAT);
1529         EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1);
1530         efx_writeo(efx, &temp, FR_AB_NIC_STAT);
1531
1532         rc = falcon_reset_sram(efx);
1533         if (rc)
1534                 return rc;
1535
1536         /* Clear the parity enables on the TX data fifos as
1537          * they produce false parity errors because of timing issues
1538          */
1539         if (EFX_WORKAROUND_5129(efx)) {
1540                 efx_reado(efx, &temp, FR_AZ_CSR_SPARE);
1541                 EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0);
1542                 efx_writeo(efx, &temp, FR_AZ_CSR_SPARE);
1543         }
1544
1545         if (EFX_WORKAROUND_7244(efx)) {
1546                 efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL);
1547                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8);
1548                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8);
1549                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8);
1550                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8);
1551                 efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL);
1552         }
1553
1554         /* XXX This is documented only for Falcon A0/A1 */
1555         /* Setup RX.  Wait for descriptor is broken and must
1556          * be disabled.  RXDP recovery shouldn't be needed, but is.
1557          */
1558         efx_reado(efx, &temp, FR_AA_RX_SELF_RST);
1559         EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1);
1560         EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1);
1561         if (EFX_WORKAROUND_5583(efx))
1562                 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1);
1563         efx_writeo(efx, &temp, FR_AA_RX_SELF_RST);
1564
1565         /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
1566          * descriptors (which is bad).
1567          */
1568         efx_reado(efx, &temp, FR_AZ_TX_CFG);
1569         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
1570         efx_writeo(efx, &temp, FR_AZ_TX_CFG);
1571
1572         falcon_init_rx_cfg(efx);
1573
1574         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
1575                 /* Set hash key for IPv4 */
1576                 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
1577                 efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
1578
1579                 /* Set destination of both TX and RX Flush events */
1580                 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
1581                 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
1582         }
1583
1584         efx_nic_init_common(efx);
1585
1586         return 0;
1587 }
1588
1589 static void falcon_remove_nic(struct efx_nic *efx)
1590 {
1591         struct falcon_nic_data *nic_data = efx->nic_data;
1592         struct falcon_board *board = falcon_board(efx);
1593         int rc;
1594
1595         board->type->fini(efx);
1596
1597         /* Remove I2C adapter and clear it in preparation for a retry */
1598         rc = i2c_del_adapter(&board->i2c_adap);
1599         BUG_ON(rc);
1600         memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
1601
1602         efx_nic_free_buffer(efx, &efx->irq_status);
1603
1604         __falcon_reset_hw(efx, RESET_TYPE_ALL);
1605
1606         /* Release the second function after the reset */
1607         if (nic_data->pci_dev2) {
1608                 pci_dev_put(nic_data->pci_dev2);
1609                 nic_data->pci_dev2 = NULL;
1610         }
1611
1612         /* Tear down the private nic state */
1613         kfree(efx->nic_data);
1614         efx->nic_data = NULL;
1615 }
1616
1617 static void falcon_update_nic_stats(struct efx_nic *efx)
1618 {
1619         struct falcon_nic_data *nic_data = efx->nic_data;
1620         efx_oword_t cnt;
1621
1622         if (nic_data->stats_disable_count)
1623                 return;
1624
1625         efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP);
1626         efx->n_rx_nodesc_drop_cnt +=
1627                 EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT);
1628
1629         if (nic_data->stats_pending &&
1630             *nic_data->stats_dma_done == FALCON_STATS_DONE) {
1631                 nic_data->stats_pending = false;
1632                 rmb(); /* read the done flag before the stats */
1633                 efx->mac_op->update_stats(efx);
1634         }
1635 }
1636
1637 void falcon_start_nic_stats(struct efx_nic *efx)
1638 {
1639         struct falcon_nic_data *nic_data = efx->nic_data;
1640
1641         spin_lock_bh(&efx->stats_lock);
1642         if (--nic_data->stats_disable_count == 0)
1643                 falcon_stats_request(efx);
1644         spin_unlock_bh(&efx->stats_lock);
1645 }
1646
1647 void falcon_stop_nic_stats(struct efx_nic *efx)
1648 {
1649         struct falcon_nic_data *nic_data = efx->nic_data;
1650         int i;
1651
1652         might_sleep();
1653
1654         spin_lock_bh(&efx->stats_lock);
1655         ++nic_data->stats_disable_count;
1656         spin_unlock_bh(&efx->stats_lock);
1657
1658         del_timer_sync(&nic_data->stats_timer);
1659
1660         /* Wait enough time for the most recent transfer to
1661          * complete. */
1662         for (i = 0; i < 4 && nic_data->stats_pending; i++) {
1663                 if (*nic_data->stats_dma_done == FALCON_STATS_DONE)
1664                         break;
1665                 msleep(1);
1666         }
1667
1668         spin_lock_bh(&efx->stats_lock);
1669         falcon_stats_complete(efx);
1670         spin_unlock_bh(&efx->stats_lock);
1671 }
1672
1673 static void falcon_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
1674 {
1675         falcon_board(efx)->type->set_id_led(efx, mode);
1676 }
1677
1678 /**************************************************************************
1679  *
1680  * Wake on LAN
1681  *
1682  **************************************************************************
1683  */
1684
1685 static void falcon_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1686 {
1687         wol->supported = 0;
1688         wol->wolopts = 0;
1689         memset(&wol->sopass, 0, sizeof(wol->sopass));
1690 }
1691
1692 static int falcon_set_wol(struct efx_nic *efx, u32 type)
1693 {
1694         if (type != 0)
1695                 return -EINVAL;
1696         return 0;
1697 }
1698
1699 /**************************************************************************
1700  *
1701  * Revision-dependent attributes used by efx.c and nic.c
1702  *
1703  **************************************************************************
1704  */
1705
1706 const struct efx_nic_type falcon_a1_nic_type = {
1707         .probe = falcon_probe_nic,
1708         .remove = falcon_remove_nic,
1709         .init = falcon_init_nic,
1710         .fini = efx_port_dummy_op_void,
1711         .monitor = falcon_monitor,
1712         .reset = falcon_reset_hw,
1713         .probe_port = falcon_probe_port,
1714         .remove_port = falcon_remove_port,
1715         .handle_global_event = falcon_handle_global_event,
1716         .prepare_flush = falcon_prepare_flush,
1717         .update_stats = falcon_update_nic_stats,
1718         .start_stats = falcon_start_nic_stats,
1719         .stop_stats = falcon_stop_nic_stats,
1720         .set_id_led = falcon_set_id_led,
1721         .push_irq_moderation = falcon_push_irq_moderation,
1722         .push_multicast_hash = falcon_push_multicast_hash,
1723         .reconfigure_port = falcon_reconfigure_port,
1724         .get_wol = falcon_get_wol,
1725         .set_wol = falcon_set_wol,
1726         .resume_wol = efx_port_dummy_op_void,
1727         .test_nvram = falcon_test_nvram,
1728         .default_mac_ops = &falcon_xmac_operations,
1729
1730         .revision = EFX_REV_FALCON_A1,
1731         .mem_map_size = 0x20000,
1732         .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER,
1733         .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER,
1734         .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER,
1735         .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER,
1736         .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER,
1737         .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
1738         .rx_buffer_padding = 0x24,
1739         .max_interrupt_mode = EFX_INT_MODE_MSI,
1740         .phys_addr_channels = 4,
1741         .tx_dc_base = 0x130000,
1742         .rx_dc_base = 0x100000,
1743         .offload_features = NETIF_F_IP_CSUM,
1744         .reset_world_flags = ETH_RESET_IRQ,
1745 };
1746
1747 const struct efx_nic_type falcon_b0_nic_type = {
1748         .probe = falcon_probe_nic,
1749         .remove = falcon_remove_nic,
1750         .init = falcon_init_nic,
1751         .fini = efx_port_dummy_op_void,
1752         .monitor = falcon_monitor,
1753         .reset = falcon_reset_hw,
1754         .probe_port = falcon_probe_port,
1755         .remove_port = falcon_remove_port,
1756         .handle_global_event = falcon_handle_global_event,
1757         .prepare_flush = falcon_prepare_flush,
1758         .update_stats = falcon_update_nic_stats,
1759         .start_stats = falcon_start_nic_stats,
1760         .stop_stats = falcon_stop_nic_stats,
1761         .set_id_led = falcon_set_id_led,
1762         .push_irq_moderation = falcon_push_irq_moderation,
1763         .push_multicast_hash = falcon_push_multicast_hash,
1764         .reconfigure_port = falcon_reconfigure_port,
1765         .get_wol = falcon_get_wol,
1766         .set_wol = falcon_set_wol,
1767         .resume_wol = efx_port_dummy_op_void,
1768         .test_registers = falcon_b0_test_registers,
1769         .test_nvram = falcon_test_nvram,
1770         .default_mac_ops = &falcon_xmac_operations,
1771
1772         .revision = EFX_REV_FALCON_B0,
1773         /* Map everything up to and including the RSS indirection
1774          * table.  Don't map MSI-X table, MSI-X PBA since Linux
1775          * requires that they not be mapped.  */
1776         .mem_map_size = (FR_BZ_RX_INDIRECTION_TBL +
1777                          FR_BZ_RX_INDIRECTION_TBL_STEP *
1778                          FR_BZ_RX_INDIRECTION_TBL_ROWS),
1779         .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
1780         .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
1781         .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
1782         .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
1783         .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
1784         .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
1785         .rx_buffer_hash_size = 0x10,
1786         .rx_buffer_padding = 0,
1787         .max_interrupt_mode = EFX_INT_MODE_MSIX,
1788         .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
1789                                    * interrupt handler only supports 32
1790                                    * channels */
1791         .tx_dc_base = 0x130000,
1792         .rx_dc_base = 0x100000,
1793         .offload_features = NETIF_F_IP_CSUM | NETIF_F_RXHASH | NETIF_F_NTUPLE,
1794         .reset_world_flags = ETH_RESET_IRQ,
1795 };
1796